From 002387972493424341efdff24cf7eb5d77b20433 Mon Sep 17 00:00:00 2001 From: "Ycarus (Yannick Chabanois)" Date: Sat, 27 Aug 2022 07:50:12 +0200 Subject: [PATCH 01/19] Fix SIP ALG --- .../root/etc/init.d/openmptcprouter | 20 +++++++++++++++++++ .../files/etc/uci-defaults/1980-omr-firewall | 7 ++++++- 2 files changed, 26 insertions(+), 1 deletion(-) diff --git a/luci-app-openmptcprouter/root/etc/init.d/openmptcprouter b/luci-app-openmptcprouter/root/etc/init.d/openmptcprouter index 9954d850a..8c75d0366 100755 --- a/luci-app-openmptcprouter/root/etc/init.d/openmptcprouter +++ b/luci-app-openmptcprouter/root/etc/init.d/openmptcprouter @@ -181,6 +181,26 @@ start_service() { rmmod fast_classifier 2>&1 >/dev/null fi + if [ "$(uci -q get openmptcprouter.settings.sipalg)" = "0" ]; then + uci -q batch <<-EOF >/dev/null + set firewall.zone_lan.auto_helper='0' + set firewall.zone_wan.auto_helper='0' + set firewall.zone_vpn.auto_helper='0' + commit firewall + EOF + rmmod nf_nat_sip 2>&1 >/dev/null + rmmod nf_conntrack_sip 2>&1 >/dev/null + else + uci -q batch <<-EOF >/dev/null + set firewall.zone_lan.auto_helper='1' + set firewall.zone_wan.auto_helper='1' + set firewall.zone_vpn.auto_helper='1' + commit firewall + EOF + modprobe nf_conntrack_sip 2>&1 >/dev/null + modprobe nf_nat_sip 2>&1 >/dev/null + fi + if [ "$(uci -q get rpcd.@rpcd[0].socket)" != "/var/run/ubus/ubus.sock" ]; then uci -q batch <<-EOF >/dev/null set rpcd.@rpcd[0].socket='/var/run/ubus/ubus.sock' diff --git a/openmptcprouter/files/etc/uci-defaults/1980-omr-firewall b/openmptcprouter/files/etc/uci-defaults/1980-omr-firewall index b4493bb18..c736e2b87 100755 --- a/openmptcprouter/files/etc/uci-defaults/1980-omr-firewall +++ b/openmptcprouter/files/etc/uci-defaults/1980-omr-firewall @@ -242,7 +242,12 @@ uci -q batch <<-EOF >/dev/null set firewall.@include[0].reload='1' commit firewall EOF -if [ "$(uci -q get openmptcprouter.settings.sipalg)" != "1" ]; then +if [ "$(uci -q get openmptcprouter.settings.sipalg)" = "" ]; then + uci -q batch <<-EOF >/dev/null + set openmptcprouter.settings.sipalg='1' + EOF +fi +if [ "$(uci -q get openmptcprouter.settings.sipalg)" = "0" ]; then uci -q batch <<-EOF >/dev/null set firewall.zone_lan.auto_helper='0' set firewall.zone_wan.auto_helper='0' From 58c4f6cb28fa96232af8026b028c853645eef284 Mon Sep 17 00:00:00 2001 From: "Ycarus (Yannick Chabanois)" Date: Mon, 29 Aug 2022 20:08:59 +0200 Subject: [PATCH 02/19] Small SIP ALG fixes --- .../luasrc/controller/openmptcprouter.lua | 10 ---------- .../root/etc/init.d/openmptcprouter | 4 ++-- .../files/etc/uci-defaults/1980-omr-firewall | 1 + 3 files changed, 3 insertions(+), 12 deletions(-) diff --git a/luci-app-openmptcprouter/luasrc/controller/openmptcprouter.lua b/luci-app-openmptcprouter/luasrc/controller/openmptcprouter.lua index ce5edb130..00c421517 100644 --- a/luci-app-openmptcprouter/luasrc/controller/openmptcprouter.lua +++ b/luci-app-openmptcprouter/luasrc/controller/openmptcprouter.lua @@ -1233,16 +1233,6 @@ function settings_add() -- Enable/disable SIP ALG local sipalg = luci.http.formvalue("sipalg") or "0" ucic:set("openmptcprouter","settings","sipalg",sipalg) - ucic:foreach("firewall", "zone", function (section) - ucic:set("firewall",section[".name"],"auto_helper",sipalg) - end) - if sipalg == "1" then - luci.sys.call("modprobe -q nf_conntrack_sip >/dev/null 2>/dev/null") - luci.sys.call("modprobe -q nf_nat_sip >/dev/null 2>/dev/null") - else - luci.sys.call("rmmod nf_nat_sip >/dev/null 2>/dev/null") - luci.sys.call("rmmod nf_conntrack_sip >/dev/null 2>/dev/null") - end ucic:save("openmptcprouter") ucic:commit("openmptcprouter") diff --git a/luci-app-openmptcprouter/root/etc/init.d/openmptcprouter b/luci-app-openmptcprouter/root/etc/init.d/openmptcprouter index 8c75d0366..6a667e263 100755 --- a/luci-app-openmptcprouter/root/etc/init.d/openmptcprouter +++ b/luci-app-openmptcprouter/root/etc/init.d/openmptcprouter @@ -197,8 +197,8 @@ start_service() { set firewall.zone_vpn.auto_helper='1' commit firewall EOF - modprobe nf_conntrack_sip 2>&1 >/dev/null - modprobe nf_nat_sip 2>&1 >/dev/null + modprobe -q nf_conntrack_sip 2>&1 >/dev/null + modprobe -q nf_nat_sip 2>&1 >/dev/null fi if [ "$(uci -q get rpcd.@rpcd[0].socket)" != "/var/run/ubus/ubus.sock" ]; then diff --git a/openmptcprouter/files/etc/uci-defaults/1980-omr-firewall b/openmptcprouter/files/etc/uci-defaults/1980-omr-firewall index c736e2b87..afde68d82 100755 --- a/openmptcprouter/files/etc/uci-defaults/1980-omr-firewall +++ b/openmptcprouter/files/etc/uci-defaults/1980-omr-firewall @@ -245,6 +245,7 @@ EOF if [ "$(uci -q get openmptcprouter.settings.sipalg)" = "" ]; then uci -q batch <<-EOF >/dev/null set openmptcprouter.settings.sipalg='1' + commit openmptcprouter EOF fi if [ "$(uci -q get openmptcprouter.settings.sipalg)" = "0" ]; then From d7c59fffae17441f32cb6e9724972b1df9ef6cbb Mon Sep 17 00:00:00 2001 From: "Ycarus (Yannick Chabanois)" Date: Tue, 30 Aug 2022 21:01:54 +0200 Subject: [PATCH 03/19] Fix release on upgrade, header and status page --- .../root/www/luci-static/resources/sysupgrade.js | 2 +- mptcp/files/usr/share/omr/post-tracking.d/post-tracking | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/luci-app-sysupgrade/root/www/luci-static/resources/sysupgrade.js b/luci-app-sysupgrade/root/www/luci-static/resources/sysupgrade.js index 5750ad0b5..64c751dda 100644 --- a/luci-app-sysupgrade/root/www/luci-static/resources/sysupgrade.js +++ b/luci-app-sysupgrade/root/www/luci-static/resources/sysupgrade.js @@ -159,7 +159,7 @@ function set_status(type, message, loading, show_log) { function upgrade_check() { var current_version = data.release.version.toLowerCase(); - var current_branch = current_version.split('.').slice(0, 2).join('.') + var current_branch = current_version.split('-')[0].split('.').slice(0, 2).join('.') var candidates = [] hide("#status_box"); hide("#server_div"); diff --git a/mptcp/files/usr/share/omr/post-tracking.d/post-tracking b/mptcp/files/usr/share/omr/post-tracking.d/post-tracking index 5b723e4fd..7500e76c1 100755 --- a/mptcp/files/usr/share/omr/post-tracking.d/post-tracking +++ b/mptcp/files/usr/share/omr/post-tracking.d/post-tracking @@ -1322,7 +1322,7 @@ if [ -n "$OMR_TRACKER_INTERFACE" ] && ([ "$(uci -q get openmptcprouter.$OMR_TRAC local latestversions="$(curl -4 -s -m 3 https://www.openmptcprouter.com/version/version.json)" [ -n "$latestversions" ] && { uci -q set openmptcprouter.latest_versions=latest_versions - uci -q set openmptcprouter.latest_versions.omr=$(echo $latestversions | jsonfilter -q -e '@.omr') + uci -q set openmptcprouter.latest_versions.omr=$(echo $latestversions | jsonfilter -q -e '@.omr')-$(ubus call system board | jsonfilter -e '@.kernel' | cut -d'.' -f1,2) uci -q set openmptcprouter.latest_versions.vps=$(echo $latestversions | jsonfilter -q -e '@.vps') uci -q set openmptcprouter.latest_versions.lc=$(date +"%s") } From 70571e546bfd47f04e0b75b7d603a67cdf1a9244 Mon Sep 17 00:00:00 2001 From: "Ycarus (Yannick Chabanois)" Date: Tue, 30 Aug 2022 21:02:19 +0200 Subject: [PATCH 04/19] add a sleep between rmmod for sip alg --- luci-app-openmptcprouter/root/etc/init.d/openmptcprouter | 2 ++ 1 file changed, 2 insertions(+) diff --git a/luci-app-openmptcprouter/root/etc/init.d/openmptcprouter b/luci-app-openmptcprouter/root/etc/init.d/openmptcprouter index 6a667e263..189f2669b 100755 --- a/luci-app-openmptcprouter/root/etc/init.d/openmptcprouter +++ b/luci-app-openmptcprouter/root/etc/init.d/openmptcprouter @@ -189,6 +189,7 @@ start_service() { commit firewall EOF rmmod nf_nat_sip 2>&1 >/dev/null + sleep 2 rmmod nf_conntrack_sip 2>&1 >/dev/null else uci -q batch <<-EOF >/dev/null @@ -198,6 +199,7 @@ start_service() { commit firewall EOF modprobe -q nf_conntrack_sip 2>&1 >/dev/null + sleep 2 modprobe -q nf_nat_sip 2>&1 >/dev/null fi From 8cf19a4638912486177fb590e9c26fba771d6a36 Mon Sep 17 00:00:00 2001 From: suyuan <175338101@qq.com> Date: Mon, 29 Aug 2022 01:11:42 +0800 Subject: [PATCH 05/19] fix --- qaa/firmware/nss-firmware/Makefile | 70 + qaa/nss/nss-ifb/Makefile | 49 + qaa/nss/nss-ifb/README.md | 45 + qaa/nss/nss-ifb/src/Makefile | 3 + qaa/nss/nss-ifb/src/nss_ifb.c | 304 ++++ qaa/nss/qca-nss-cfi/Makefile | 99 ++ .../patches/0001-compile-only-cryptoapi.patch | 30 + .../patches/0002-wip-support-5.4.patch | 78 + .../0003-Convert-ablkcipher-to-skcipher.patch | 707 +++++++++ qaa/nss/qca-nss-clients-64/Makefile | 97 ++ .../qca-nss-clients-64/files/qca-nss-ipsec | 214 +++ .../files/qca-nss-mirred.init | 28 + .../files/qca-nss-ovpn.init | 69 + qaa/nss/qca-nss-clients/Makefile | 469 ++++++ qaa/nss/qca-nss-clients/files/qca-nss-ipsec | 92 ++ .../qca-nss-clients/files/qca-nss-mirred.init | 28 + .../qca-nss-clients/files/qca-nss-ovpn.init | 69 + .../100-kernel-5.4-support-qdisc.patch | 1145 +++++++++++++++ .../patches/101-kernel-5.4-support-gre.patch | 106 ++ .../102-kernel-5.4-support-ipsec.patch | 29 + .../patches/103-kernel-5.4-support-dtls.patch | 11 + .../patches/104-kernel-5.4-support-l2tp.patch | 64 + .../patches/200-qdisc-fix-compile-error.patch | 14 + .../202-vlanmgr-fix-compile-error.patch | 48 + qaa/nss/qca-nss-crypto/Makefile | 74 + .../patches/100-kernel-5.4-support.patch | 42 + .../200-fix-NULL-pointer-exception.patch | 57 + qaa/nss/qca-nss-dp/Makefile | 62 + ...port-newer-kernels-time-stamping-API.patch | 44 + ...-phy-mode-code-compatible-with-newer.patch | 48 + ...03-Drop-_nocache-variants-of-ioremap.patch | 48 + .../0004-EDMA-Fix-NAPI-packet-counting.patch | 31 + ...-Use-NAPI_POLL_WEIGHT-as-NAPI-weight.patch | 41 + .../0006-NSS-DP-fix-of_get_mac_address.patch | 50 + qaa/nss/qca-nss-drv-64/Makefile | 121 ++ qaa/nss/qca-nss-drv-64/files/qca-nss-drv.conf | 6 + .../qca-nss-drv-64/files/qca-nss-drv.debug | 26 + .../qca-nss-drv-64/files/qca-nss-drv.hotplug | 70 + qaa/nss/qca-nss-drv-64/files/qca-nss-drv.init | 50 + .../qca-nss-drv-64/files/qca-nss-drv.sysctl | 4 + ...ore-add-5.10-kernel-to-version-check.patch | 25 + ...replace-ioremap_nocache-with-ioremap.patch | 164 +++ ...0003-DMA-Fix-NULL-pointer-exceptions.patch | 49 + ...hack-support-for-mismatched-firmware.patch | 344 +++++ qaa/nss/qca-nss-drv/Makefile | 125 ++ .../files/nss-firmware/LICENSE.TXT | 45 + .../qca-nss-drv/files/nss-firmware/NOTICE.TXT | 217 +++ .../qca-nss-drv/files/nss-firmware/README.md | 10 + .../files/nss-firmware/qca-nss0-retail.bin | Bin 0 -> 536324 bytes .../files/nss-firmware/qca-nss1-retail.bin | Bin 0 -> 218224 bytes qaa/nss/qca-nss-drv/files/qca-nss-drv.conf | 6 + qaa/nss/qca-nss-drv/files/qca-nss-drv.debug | 26 + qaa/nss/qca-nss-drv/files/qca-nss-drv.hotplug | 70 + qaa/nss/qca-nss-drv/files/qca-nss-drv.init | 50 + qaa/nss/qca-nss-drv/files/qca-nss-drv.sysctl | 4 + .../patches/100-kernel-5.4-support.patch | 107 ++ ...ol-fab-scaling-from-package-Makefile.patch | 38 + .../200-fix-NULL-pointer-exception.patch | 11 + ...1-Fix-Kernel-Panic-dma-with-NULL-dev.patch | 82 ++ .../400-Exported-set-nexthop-function.patch | 47 + qaa/nss/qca-nss-ecm-64/Makefile | 96 ++ qaa/nss/qca-nss-ecm-64/files/ecm_dump.sh | 95 ++ qaa/nss/qca-nss-ecm-64/files/on-demand-down | 6 + .../qca-nss-ecm-64/files/qca-nss-ecm.defaults | 28 + .../qca-nss-ecm-64/files/qca-nss-ecm.firewall | 18 + qaa/nss/qca-nss-ecm-64/files/qca-nss-ecm.init | 137 ++ .../qca-nss-ecm-64/files/qca-nss-ecm.sysctl | 2 + qaa/nss/qca-nss-ecm-64/files/qca-nss-ecm.uci | 2 + ...de-componentize-the-module-even-more.patch | 335 +++++ .../patches/100-kernel-5.10-support.patch | 831 +++++++++++ .../203-rework-nfct-notification.patch | 25 + .../patches/204-More-compile-fixes.patch | 58 + .../patches/205-resolve-high-load.patch | 61 + qaa/nss/qca-nss-ecm/Makefile | 278 ++++ qaa/nss/qca-nss-ecm/files/ecm_dump.sh | 95 ++ qaa/nss/qca-nss-ecm/files/on-demand-down | 6 + .../qca-nss-ecm/files/qca-nss-ecm.defaults | 28 + .../qca-nss-ecm/files/qca-nss-ecm.firewall | 18 + qaa/nss/qca-nss-ecm/files/qca-nss-ecm.init | 133 ++ qaa/nss/qca-nss-ecm/files/qca-nss-ecm.sysctl | 2 + qaa/nss/qca-nss-ecm/files/qca-nss-ecm.uci | 2 + .../patches/001-Drop_SFE_from_ecm.patch | 12 + .../patches/100-kernel-5.4-support.patch | 1276 +++++++++++++++++ .../101-Fix_Kern_Panic_on_UDP_CONNTRACK.patch | 60 + .../patches/200-resolve-high-load.patch | 44 + .../203-rework-nfct-notification.patch | 20 + ...heck-TCP_UDP-conntrack-state-earlier.patch | 236 +++ ...ix-NSS-stats-request-roll-over-issue.patch | 52 + ...01-Fix-for-ref-leak-during-multicast.patch | 112 ++ ...neighbour-solicitation-send-function.patch | 33 + ...e-leak-during-multicast_PPPoE-bridge.patch | 260 ++++ ...-global-accelerated-count-under-lock.patch | 59 + ...x-IPv6-neighbor-solicitation-request.patch | 83 ++ ...tation-fix-with-zero-gateway-address.patch | 63 + ...-port-when-bridge-hairpin-is-enabled.patch | 126 ++ qaa/nss/qca-nss-gmac/Makefile | 47 + .../patches/100-kernel-5.4-support.patch | 279 ++++ .../patches/101-nss-gmac-test-ptr.patch | 25 + ...-work-around-interface-close-warning.patch | 15 + qaa/qca-mcs/Makefile | 54 + qaa/qca-rfs/Makefile | 51 + qaa/qca-rfs/files/qrfs.init | 27 + .../patches/100-add-kernel-5.4-support.patch | 57 + .../200-rework-nfct-notification.patch | 20 + qaa/qca-ssdk-shell/Makefile | 48 + qaa/qca-ssdk/Makefile | 125 ++ qaa/qca-ssdk/files/qca-ssdk | 206 +++ .../0001-SSDK-config-add-kernel-5.10.patch | 56 + ...replace-ioremap_nocache-with-ioremap.patch | 102 ++ ...use-of_mdio_find_bus-to-get-MDIO-bus.patch | 40 + .../patches/0005-add-kernel-5.4-support.patch | 108 ++ .../0006-fix-mdio-probe-on-ipq806x.patch | 11 + ...0007-SSDK-dts-fix-of_get_mac_address.patch | 42 + .../0008-add-aquantia-phy-id-113CB0.patch | 37 + 114 files changed, 12104 insertions(+) create mode 100644 qaa/firmware/nss-firmware/Makefile create mode 100644 qaa/nss/nss-ifb/Makefile create mode 100644 qaa/nss/nss-ifb/README.md create mode 100644 qaa/nss/nss-ifb/src/Makefile create mode 100644 qaa/nss/nss-ifb/src/nss_ifb.c create mode 100644 qaa/nss/qca-nss-cfi/Makefile create mode 100644 qaa/nss/qca-nss-cfi/patches/0001-compile-only-cryptoapi.patch create mode 100644 qaa/nss/qca-nss-cfi/patches/0002-wip-support-5.4.patch create mode 100644 qaa/nss/qca-nss-cfi/patches/0003-Convert-ablkcipher-to-skcipher.patch create mode 100644 qaa/nss/qca-nss-clients-64/Makefile create mode 100644 qaa/nss/qca-nss-clients-64/files/qca-nss-ipsec create mode 100644 qaa/nss/qca-nss-clients-64/files/qca-nss-mirred.init create mode 100644 qaa/nss/qca-nss-clients-64/files/qca-nss-ovpn.init create mode 100644 qaa/nss/qca-nss-clients/Makefile create mode 100644 qaa/nss/qca-nss-clients/files/qca-nss-ipsec create mode 100644 qaa/nss/qca-nss-clients/files/qca-nss-mirred.init create mode 100644 qaa/nss/qca-nss-clients/files/qca-nss-ovpn.init create mode 100644 qaa/nss/qca-nss-clients/patches/100-kernel-5.4-support-qdisc.patch create mode 100644 qaa/nss/qca-nss-clients/patches/101-kernel-5.4-support-gre.patch create mode 100644 qaa/nss/qca-nss-clients/patches/102-kernel-5.4-support-ipsec.patch create mode 100644 qaa/nss/qca-nss-clients/patches/103-kernel-5.4-support-dtls.patch create mode 100644 qaa/nss/qca-nss-clients/patches/104-kernel-5.4-support-l2tp.patch create mode 100644 qaa/nss/qca-nss-clients/patches/200-qdisc-fix-compile-error.patch create mode 100644 qaa/nss/qca-nss-clients/patches/202-vlanmgr-fix-compile-error.patch create mode 100644 qaa/nss/qca-nss-crypto/Makefile create mode 100644 qaa/nss/qca-nss-crypto/patches/100-kernel-5.4-support.patch create mode 100644 qaa/nss/qca-nss-crypto/patches/200-fix-NULL-pointer-exception.patch create mode 100644 qaa/nss/qca-nss-dp/Makefile create mode 100644 qaa/nss/qca-nss-dp/patches/0001-edma_tx_rx-support-newer-kernels-time-stamping-API.patch create mode 100644 qaa/nss/qca-nss-dp/patches/0002-nss_dp_main-make-phy-mode-code-compatible-with-newer.patch create mode 100644 qaa/nss/qca-nss-dp/patches/0003-Drop-_nocache-variants-of-ioremap.patch create mode 100644 qaa/nss/qca-nss-dp/patches/0004-EDMA-Fix-NAPI-packet-counting.patch create mode 100644 qaa/nss/qca-nss-dp/patches/0005-EDMA-Use-NAPI_POLL_WEIGHT-as-NAPI-weight.patch create mode 100644 qaa/nss/qca-nss-dp/patches/0006-NSS-DP-fix-of_get_mac_address.patch create mode 100644 qaa/nss/qca-nss-drv-64/Makefile create mode 100644 qaa/nss/qca-nss-drv-64/files/qca-nss-drv.conf create mode 100644 qaa/nss/qca-nss-drv-64/files/qca-nss-drv.debug create mode 100644 qaa/nss/qca-nss-drv-64/files/qca-nss-drv.hotplug create mode 100644 qaa/nss/qca-nss-drv-64/files/qca-nss-drv.init create mode 100644 qaa/nss/qca-nss-drv-64/files/qca-nss-drv.sysctl create mode 100644 qaa/nss/qca-nss-drv-64/patches/0001-core-add-5.10-kernel-to-version-check.patch create mode 100644 qaa/nss/qca-nss-drv-64/patches/0002-nss-drv-replace-ioremap_nocache-with-ioremap.patch create mode 100644 qaa/nss/qca-nss-drv-64/patches/0003-DMA-Fix-NULL-pointer-exceptions.patch create mode 100644 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create mode 100644 qaa/nss/qca-nss-drv/patches/200-fix-NULL-pointer-exception.patch create mode 100644 qaa/nss/qca-nss-drv/patches/201-Fix-Kernel-Panic-dma-with-NULL-dev.patch create mode 100644 qaa/nss/qca-nss-drv/patches/400-Exported-set-nexthop-function.patch create mode 100644 qaa/nss/qca-nss-ecm-64/Makefile create mode 100644 qaa/nss/qca-nss-ecm-64/files/ecm_dump.sh create mode 100644 qaa/nss/qca-nss-ecm-64/files/on-demand-down create mode 100644 qaa/nss/qca-nss-ecm-64/files/qca-nss-ecm.defaults create mode 100644 qaa/nss/qca-nss-ecm-64/files/qca-nss-ecm.firewall create mode 100644 qaa/nss/qca-nss-ecm-64/files/qca-nss-ecm.init create mode 100644 qaa/nss/qca-nss-ecm-64/files/qca-nss-ecm.sysctl create mode 100644 qaa/nss/qca-nss-ecm-64/files/qca-nss-ecm.uci create mode 100644 qaa/nss/qca-nss-ecm-64/patches/001-treewide-componentize-the-module-even-more.patch create mode 100644 qaa/nss/qca-nss-ecm-64/patches/100-kernel-5.10-support.patch create mode 100644 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qaa/qca-ssdk/patches/0004-platform-use-of_mdio_find_bus-to-get-MDIO-bus.patch create mode 100644 qaa/qca-ssdk/patches/0005-add-kernel-5.4-support.patch create mode 100644 qaa/qca-ssdk/patches/0006-fix-mdio-probe-on-ipq806x.patch create mode 100644 qaa/qca-ssdk/patches/0007-SSDK-dts-fix-of_get_mac_address.patch create mode 100644 qaa/qca-ssdk/patches/0008-add-aquantia-phy-id-113CB0.patch diff --git a/qaa/firmware/nss-firmware/Makefile b/qaa/firmware/nss-firmware/Makefile new file mode 100644 index 000000000..6ea4a57c0 --- /dev/null +++ b/qaa/firmware/nss-firmware/Makefile @@ -0,0 +1,70 @@ +# +# Copyright (C) 2021 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +include $(TOPDIR)/rules.mk + +PKG_NAME:=nss-firmware +PKG_SOURCE_DATE:=2021-03-12 +PKG_SOURCE_VERSION:=73f378d6be21a9c20a69b77000dbb54a537006a9 +PKG_MIRROR_HASH:=0c21afe29002754edf2983bc9e8543dddd722e75bd12e961e300e99a310d1f62 +PKG_RELEASE:=$(AUTORELEASE) + +PKG_SOURCE_PROTO:=git +PKG_SOURCE_URL:=https://github.com/quic/qca-sdk-nss-fw.git + +PKG_LICENSE_FILES:=LICENSE.md + +PKG_MAINTAINER:=Robert Marko + +include $(INCLUDE_DIR)/package.mk + +VERSION_PATH=$(PKG_BUILD_DIR)/QCA_Networking_2020.SPF_11.3/CS + +define Package/nss-firmware-default + SECTION:=firmware + CATEGORY:=Firmware + URL:=$(PKG_SOURCE_URL) + DEPENDS:=@(TARGET_ipq807x||TARGET_ipq60xx) +endef + +define Package/nss-firmware-ipq6018 +$(Package/nss-firmware-default) + TITLE:=NSS firmware for IPQ6018 devices + NSS_ARCHIVE:=$(VERSION_PATH)/IPQ6018.ATH.11.3/BIN-NSS.CP.11.3-9-R.tar.bz2 +endef + +define Package/nss-firmware-ipq8074 +$(Package/nss-firmware-default) + TITLE:=NSS firmware for IPQ8074 devices + NSS_ARCHIVE:=$(VERSION_PATH)/IPQ8074.ATH.11.3/BIN-NSS.HK.11.3-9-R.tar.bz2 +endef + +define Build/Compile + +endef + +define Package/nss-firmware-ipq6018/install + $(TAR) -C $(PKG_BUILD_DIR) -xf $(NSS_ARCHIVE) + $(INSTALL_DIR) $(1)/lib/firmware/ + $(INSTALL_DATA) \ + $(PKG_BUILD_DIR)/BIN-NSS.CP.11.3-9-R/retail_router0.bin \ + $(1)/lib/firmware/qca-nss0-retail.bin +endef + +define Package/nss-firmware-ipq8074/install + $(TAR) -C $(PKG_BUILD_DIR) -xf $(NSS_ARCHIVE) + $(INSTALL_DIR) $(1)/lib/firmware/ + $(INSTALL_DATA) \ + $(PKG_BUILD_DIR)/BIN-NSS.HK.11.3-9-R/retail_router0.bin \ + $(1)/lib/firmware/qca-nss0-retail.bin + $(INSTALL_DATA) \ + $(PKG_BUILD_DIR)/BIN-NSS.HK.11.3-9-R/retail_router1.bin \ + $(1)/lib/firmware/qca-nss1-retail.bin +endef + +$(eval $(call BuildPackage,nss-firmware-ipq6018)) +$(eval $(call BuildPackage,nss-firmware-ipq8074)) diff --git a/qaa/nss/nss-ifb/Makefile b/qaa/nss/nss-ifb/Makefile new file mode 100644 index 000000000..6b7f0b480 --- /dev/null +++ b/qaa/nss/nss-ifb/Makefile @@ -0,0 +1,49 @@ +# +# Copyright (C) 2008-2012 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/kernel.mk + +PKG_NAME:=nss-ifb +PKG_RELEASE:=1 + +include $(INCLUDE_DIR)/package.mk + +define KernelPackage/nss-ifb + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=NSS IFB Interface + DEPENDS:=+kmod-qca-nss-drv @LINUX_5_4 + FILES:=$(PKG_BUILD_DIR)/nss-ifb.ko + KCONFIG:= +endef + +define KernelPackage/nss-ifb/description + Kernel module to register a NSS aware IFB interface. +endef + +EXTRA_KCONFIG:= \ + CONFIG_NET_CLS=y + +EXTRA_CFLAGS:= \ + -I$(STAGING_DIR)/usr/include/qca-nss-drv + +MAKE_OPTS:= \ + $(KERNEL_MAKE_FLAGS) \ + M="$(PKG_BUILD_DIR)" \ + EXTRA_CFLAGS="$(EXTRA_CFLAGS)" \ + $(EXTRA_KCONFIG) + +define Build/Compile + $(MAKE) -C "$(LINUX_DIR)" \ + $(MAKE_OPTS) \ + modules +endef + +$(eval $(call KernelPackage,nss-ifb)) + diff --git a/qaa/nss/nss-ifb/README.md b/qaa/nss/nss-ifb/README.md new file mode 100644 index 000000000..a0af7a5eb --- /dev/null +++ b/qaa/nss/nss-ifb/README.md @@ -0,0 +1,45 @@ +NSS Physical Interface Ingress Driver +===================================== + +This driver redirect NSS physical interface (namely GMACs) ingress traffic to itself +and sends it back to the Linux network stack (as the source GMACs packets) as it's +egress traffic. + +This allows the NSS QDISC drivers to manage the egress traffic of this driver's +NSS virtual interface. + +This driver will create a single network interface named 'nssifb'. The default +source interface is defined as 'eth0'. It can be changed using the following module +parameter path: + +/sys/module/nss-ifb/parameter/nss_src_dev + +To change the source NSS physical interface to 'eth1', use the following command: + +printf eth1 > /sys/module/nss-ifb/parameter/nss_src_dev + +You need to change the source interface first before bringing up the 'nssifb' +interface. Changing it after the interface is up will have no effect. You need +to bring down the interface and bring it back up to have the changes take effect. + +CPU load imposed on the Krait CPUs appears negligible with this driver intercepting +the physical interface's ingress traffic. Full line speed of the GMAC interface +could still be achieved. + +The commands below shows an example to shape ingress traffic to 500 Mbps and egress +to 200 Mbps for the 'eth0' interface. + +# Load the module if it's not loaded +modprobe nss-ifb + +# Bring up the nssifb interface to active ingress redirect +ip link set up nssifb + +# Shape ingress traffic to 500 Mbit with chained NSSFQ_CODEL +tc qdisc add dev nssifb root handle 1: nsstbl rate 500Mbit burst 1Mb +tc qdisc add dev nssifb parent 1: handle 10: nssfq_codel limit 10240 flows 1024 quantum 1514 target 5ms interval 100ms set_default + +# Shape egress traffic to 200 Mbit with chained NSSFQ_CODEL +tc qdisc add dev eth0 root handle 1: nsstbl rate 200Mbit burst 1Mb +tc qdisc add dev eth0 parent 1: handle 10: nssfq_codel limit 10240 flows 1024 quantum 1514 target 5ms interval 100ms set_default + diff --git a/qaa/nss/nss-ifb/src/Makefile b/qaa/nss/nss-ifb/src/Makefile new file mode 100644 index 000000000..332b9b4ed --- /dev/null +++ b/qaa/nss/nss-ifb/src/Makefile @@ -0,0 +1,3 @@ +obj-m += nss-ifb.o + +nss-ifb-objs := nss_ifb.o diff --git a/qaa/nss/nss-ifb/src/nss_ifb.c b/qaa/nss/nss-ifb/src/nss_ifb.c new file mode 100644 index 000000000..18c017fe0 --- /dev/null +++ b/qaa/nss/nss-ifb/src/nss_ifb.c @@ -0,0 +1,304 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +/* + * This driver is adapted from the Linux /drivers/net/ifb.c file. + * + * Redirect QCA NSS physical interface ingress traffic to this driver's + * virtual interface. This will allow ingress traffic shaping using the + * QCA NSS shaper. + */ + +#include + +#define TX_Q_LIMIT 32 + +struct nss_ifb_dev_private { + struct nss_virt_if_handle *nssctx; + struct net_device *nss_src_dev; + uint32_t nss_src_if_num; + char nss_src_dev_name[32]; +}; + +char nss_dev_name_array[32] = "eth0"; +char *nss_dev_name = nss_dev_name_array; +module_param(nss_dev_name, charp, 0644); +MODULE_PARM_DESC(nss_dev_name, "NSS physical interface source device name"); + +/* + * Virtual interface egress packet callback. + * + * We send it back to the Linux network stack. + */ +static void nss_ifb_data_cb(struct net_device *netdev, struct sk_buff *skb, struct napi_struct *napi) +{ + struct nss_ifb_dev_private *dp = netdev_priv(netdev); + + skb->protocol = eth_type_trans(skb, dp->nss_src_dev); + skb->ip_summed = CHECKSUM_UNNECESSARY; + + napi_gro_receive(napi, skb); +} + +/* + * Virtual interface ingress packet callback. + * + * We just send it back to the NSS firmware to let the shaper work on it. + */ +static void nss_ifb_xmit_cb(struct net_device *netdev, struct sk_buff *skb) +{ + struct nss_ifb_dev_private *dp = netdev_priv(netdev); + int ret; + + ret = nss_virt_if_tx_buf(dp->nssctx, skb); + if (unlikely(ret)) { + pr_warn("Failed [%d] to send skb [len: %d, protocol: 0x%X] to NSS!\n", + ret, skb->len, ntohs(skb->protocol)); + } +} + +static void nss_ifb_stats64(struct net_device *dev, + struct rtnl_link_stats64 *stats) +{ + +} + +static int nss_ifb_dev_init(struct net_device *dev) +{ + struct nss_ifb_dev_private *dp = netdev_priv(dev); + + dp->nssctx = nss_virt_if_create_sync_nexthop(dev, NSS_ETH_RX_INTERFACE, NSS_ETH_RX_INTERFACE); + if (!dp->nssctx) { + dp->nssctx = NULL; + pr_warn("Could not create a NSS virtual interface for dev [%s]\n", + dev->name); + + return -ENODEV; + } + pr_info("Created a NSS virtual interface for dev [%s]\n", dev->name); + + nss_virt_if_register(dp->nssctx, nss_ifb_data_cb, dev); + pr_info("NSS IFB data callback registered\n"); + + nss_virt_if_xmit_callback_register(dp->nssctx, nss_ifb_xmit_cb); + pr_info("NSS IFB transmit callback registered\n"); + + return 0; +} + +static void nss_ifb_dev_uninit(struct net_device *dev) +{ + struct nss_ifb_dev_private *dp = netdev_priv(dev); + int ret; + + nss_virt_if_xmit_callback_unregister(dp->nssctx); + pr_info("NSS IFB transmit callback unregistered\n"); + + ret = nss_virt_if_destroy_sync(dp->nssctx); + if (ret == NSS_TX_SUCCESS) { + pr_info("NSS virtual interface destroyed for dev [%s]\n", dev->name); + } + else { + pr_warn("Unable to destroy NSS virtual interface for dev [%s], error[%d]\n", + dev->name, ret); + } + dp->nssctx = NULL; +} + +static netdev_tx_t nss_ifb_xmit(struct sk_buff *skb, struct net_device *dev) +{ + return NETDEV_TX_OK; +} + +static int nss_ifb_close(struct net_device *dev) +{ + struct nss_ifb_dev_private *dp = netdev_priv(dev); + struct nss_ctx_instance *nss_ctx; + struct net_device *src_dev; + uint32_t src_if_num; + int ret; + + nss_ctx = dp->nssctx->nss_ctx; + src_dev = dp->nss_src_dev; + src_if_num = dp->nss_src_if_num; + + ret = nss_phys_if_set_nexthop(nss_ctx, src_if_num, NSS_ETH_RX_INTERFACE); + if (ret != NSS_TX_SUCCESS) { + pr_warn("%p: Failed to reset next hop for net device [%s].\n", + nss_ctx, src_dev->name); + } + else { + pr_info("%p: Reset nexthop successful for net device [%s].\n", + nss_ctx, src_dev->name); + } + + dev_put(src_dev); + dp->nss_src_dev = NULL; + dp->nss_src_if_num = -1; + + return 0; +} + +static int nss_ifb_open(struct net_device *dev) +{ + struct nss_ifb_dev_private *dp = netdev_priv(dev); + struct net_device *src_dev; + uint32_t src_if_num; + uint32_t nh_if_num; + nss_tx_status_t nss_tx_status; + struct nss_ctx_instance *nss_ctx; + + nss_ctx = dp->nssctx->nss_ctx; + nh_if_num = dp->nssctx->if_num_n2h; + + strcpy(dp->nss_src_dev_name, nss_dev_name); + + src_dev = dev_get_by_name(&init_net, dp->nss_src_dev_name); + if (!src_dev) { + pr_warn("%p: Cannot find the net device [%s]\n", + nss_ctx, dp->nss_src_dev_name); + + return -ENODEV; + } + pr_info("%p: Found net device [%s]\n", nss_ctx, dp->nss_src_dev_name); + + src_if_num = nss_cmn_get_interface_number_by_dev(src_dev); + if (src_if_num < 0) { + pr_warn("%p: Invalid interface number:%d\n", nss_ctx, src_if_num); + dev_put(src_dev); + + return -ENODEV; + } + pr_info("%p: Net device [%s] has NSS intf_num [%d]\n", + nss_ctx, dp->nss_src_dev_name, src_if_num); + + nss_tx_status = nss_phys_if_set_nexthop(nss_ctx, src_if_num, nh_if_num); + if (nss_tx_status != NSS_TX_SUCCESS) { + pr_warn("%p: Sending message failed, cannot change nexthop for [%s]\n", + nss_ctx, dp->nss_src_dev_name); + } + else { + pr_info("Nexthop successfully set for [%s] to [%s]\n", + dp->nss_src_dev_name, dev->name); + } + + dp->nss_src_dev = src_dev; + dp->nss_src_if_num = src_if_num; + + return 0; +} + +static const struct net_device_ops nss_ifb_netdev_ops = { + .ndo_open = nss_ifb_open, + .ndo_stop = nss_ifb_close, + .ndo_get_stats64 = nss_ifb_stats64, + .ndo_start_xmit = nss_ifb_xmit, + .ndo_validate_addr = eth_validate_addr, + .ndo_init = nss_ifb_dev_init, + .ndo_uninit = nss_ifb_dev_uninit, +}; + +#define IFB_FEATURES (NETIF_F_HW_CSUM | NETIF_F_SG | NETIF_F_FRAGLIST | \ + NETIF_F_TSO_ECN | NETIF_F_TSO | NETIF_F_TSO6 | \ + NETIF_F_GSO_ENCAP_ALL | \ + NETIF_F_HIGHDMA | NETIF_F_HW_VLAN_CTAG_TX | \ + NETIF_F_HW_VLAN_STAG_TX) + +static void nss_ifb_dev_free(struct net_device *dev) +{ + +} + +static void nss_ifb_setup(struct net_device *dev) +{ + /* Initialize the device structure. */ + dev->netdev_ops = &nss_ifb_netdev_ops; + + /* Fill in device structure with ethernet-generic values. */ + ether_setup(dev); + dev->tx_queue_len = TX_Q_LIMIT; + + dev->features |= IFB_FEATURES; + dev->hw_features |= dev->features; + dev->hw_enc_features |= dev->features; + dev->vlan_features |= IFB_FEATURES & ~(NETIF_F_HW_VLAN_CTAG_TX | + NETIF_F_HW_VLAN_STAG_TX); + + dev->flags |= IFF_NOARP; + dev->flags &= ~IFF_MULTICAST; + dev->priv_flags &= ~IFF_TX_SKB_SHARING; + netif_keep_dst(dev); + eth_hw_addr_random(dev); + dev->needs_free_netdev = true; + dev->priv_destructor = nss_ifb_dev_free; + + dev->min_mtu = 0; + dev->max_mtu = 0; +} + +static int nss_ifb_validate(struct nlattr *tb[], struct nlattr *data[], + struct netlink_ext_ack *extack) +{ + if (tb[IFLA_ADDRESS]) { + if (nla_len(tb[IFLA_ADDRESS]) != ETH_ALEN) + return -EINVAL; + if (!is_valid_ether_addr(nla_data(tb[IFLA_ADDRESS]))) + return -EADDRNOTAVAIL; + } + return 0; +} + +static struct rtnl_link_ops nss_ifb_link_ops __read_mostly = { + .kind = "nss_ifb", + .priv_size = sizeof(struct nss_ifb_dev_private), + .setup = nss_ifb_setup, + .validate = nss_ifb_validate, +}; + +static int __init nss_ifb_init_module(void) +{ + struct net_device *dev; + int err; + + down_write(&pernet_ops_rwsem); + rtnl_lock(); + err = __rtnl_link_register(&nss_ifb_link_ops); + if (err < 0) + goto out; + + dev = alloc_netdev(sizeof(struct nss_ifb_dev_private), "nssifb", + NET_NAME_UNKNOWN, nss_ifb_setup); + + if (dev) { + dev->rtnl_link_ops = &nss_ifb_link_ops; + err = register_netdevice(dev); + } + else { + err = -ENOMEM; + } + + if (err) + __rtnl_link_unregister(&nss_ifb_link_ops); + +out: + rtnl_unlock(); + up_write(&pernet_ops_rwsem); + + if (!err) + pr_info("NSS IFB module loaded.\n"); + else + pr_warn("Failed to load NSS IFB module.\n"); + + return err; +} + +static void __exit nss_ifb_cleanup_module(void) +{ + rtnl_link_unregister(&nss_ifb_link_ops); + + pr_info("NSS IFB module unloaded.\n"); +} + +module_init(nss_ifb_init_module); +module_exit(nss_ifb_cleanup_module); +MODULE_LICENSE("GPL"); +MODULE_ALIAS_RTNL_LINK("nss_ifb"); diff --git a/qaa/nss/qca-nss-cfi/Makefile b/qaa/nss/qca-nss-cfi/Makefile new file mode 100644 index 000000000..570b45cf2 --- /dev/null +++ b/qaa/nss/qca-nss-cfi/Makefile @@ -0,0 +1,99 @@ +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/kernel.mk + +PKG_NAME:=qca-nss-cfi +PKG_RELEASE:=2 + +PKG_SOURCE_URL:=https://source.codeaurora.org/quic/qsdk/oss/lklm/nss-cfi +PKG_SOURCE_PROTO:=git +PKG_SOURCE_VERSION:=8035a8ddefdcc8a2f06c96b2a82618ca6ce6406d +PKG_MIRROR_HASH:=23316395d1346994d069eb41ef73a5505853687f8beab14f83545b3a05e52429 + +include $(INCLUDE_DIR)/package.mk + +ifeq ($(CONFIG_TARGET_ipq),y) +subtarget:=$(SUBTARGET) +else +subtarget:=$(CONFIG_TARGET_BOARD) +endif + +# v1.0 is for Akronite +# v2.0 is for Hawkeye/Cypress/Maple +ifneq (, $(findstring $(subtarget), "ipq807x" "ipq807x_64" "ipq60xx" "ipq60xx_64")) + CFI_OCF_DIR:=ocf/v2.0 + CFI_CRYPTOAPI_DIR:=cryptoapi/v2.0 +else + CFI_CRYPTOAPI_DIR:=cryptoapi/v1.1 + CFI_OCF_DIR:=ocf/v1.0 + CFI_IPSEC_DIR:=ipsec/v1.0 +endif + +define KernelPackage/qca-nss-cfi-cryptoapi + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + DEPENDS:=@TARGET_ipq806x||TARGET_ipq_ipq806x||TARGET_ipq_ipq807x||TARGET_ipq_ipq807x_64||TARGET_ipq807x||TARGET_ipq807x_64||TARGET_ipq_ipq60xx||TARGET_ipq_ipq60xx_64 \ + +kmod-qca-nss-crypto +kmod-crypto-authenc @LINUX_5_4 + TITLE:=Kernel driver for NSS cfi + FILES:=$(PKG_BUILD_DIR)/$(CFI_CRYPTOAPI_DIR)/qca-nss-cfi-cryptoapi.ko + AUTOLOAD:=$(call AutoLoad,59,qca-nss-cfi-cryptoapi) +endef + +# OCF should be dropped +# define KernelPackage/qca-nss-cfi-ocf +# SECTION:=kernel +# CATEGORY:=Kernel modules +# SUBMENU:=Network Devices +# DEPENDS:=@TARGET_ipq806x||TARGET_ipq_ipq806x||TARGET_ipq_ipq807x||TARGET_ipq_ipq807x_64||TARGET_ipq807x||TARGET_ipq807x_64||TARGET_ipq_ipq60xx||TARGET_ipq_ipq60xx_64 \ +# +kmod-qca-nss-crypto +PACKAGE_kmod-crypto-ocf:kmod-crypto-ocf @!LINUX_3_18 +# TITLE:=Kernel driver for NSS cfi +# FILES:=$(PKG_BUILD_DIR)/$(CFI_OCF_DIR)/qca-nss-cfi-ocf.ko + +# ifdef CFI_IPSEC_DIR +# FILES+=$(PKG_BUILD_DIR)/$(CFI_IPSEC_DIR)/qca-nss-ipsec.ko +# AUTOLOAD:=$(call AutoLoad,61,qca-nss-cfi-ocf qca-nss-ipsec) +# else +# AUTOLOAD:=$(call AutoLoad,61,qca-nss-cfi-ocf) +# endif +# endef + +define Build/InstallDev/qca-nss-cfi + $(INSTALL_DIR) $(1)/usr/include/qca-nss-cfi + $(CP) $(PKG_BUILD_DIR)/$(CFI_CRYPTOAPI_DIR)/../exports/* $(1)/usr/include/qca-nss-cfi + $(CP) $(PKG_BUILD_DIR)/include/* $(1)/usr/include/qca-nss-cfi +endef + +define Build/InstallDev + $(call Build/InstallDev/qca-nss-cfi,$(1)) +endef + +define KernelPackage/qca-nss-cfi/Description +This package contains a NSS cfi driver for QCA chipset +endef + +EXTRA_CFLAGS+= \ + -DCONFIG_NSS_DEBUG_LEVEL=4 \ + -I$(LINUX_DIR)/crypto/ocf \ + -I$(STAGING_DIR)/usr/include/qca-nss-crypto \ + -I$(STAGING_DIR)/usr/include/crypto \ + -I$(STAGING_DIR)/usr/include/qca-nss-drv + +ifneq (, $(findstring $(subtarget), "ipq807x" "ipq807x_64" "ipq60xx" "ipq60xx_64")) +EXTRA_CFLAGS+= -I$(STAGING_DIR)/usr/include/qca-nss-clients +endif + +define Build/Compile + $(MAKE) $(PKG_JOBS) -C "$(LINUX_DIR)" \ + $(KERNEL_MAKE_FLAGS) \ + $(PKG_MAKE_FLAGS) \ + M="$(PKG_BUILD_DIR)" \ + EXTRA_CFLAGS="$(EXTRA_CFLAGS)" \ + CFI_CRYPTOAPI_DIR=$(CFI_CRYPTOAPI_DIR) \ + CFI_OCF_DIR=$(CFI_OCF_DIR) \ + CFI_IPSEC_DIR=$(CFI_IPSEC_DIR) \ + SoC=$(subtarget) \ + modules +endef + +$(eval $(call KernelPackage,qca-nss-cfi-cryptoapi)) +#$(eval $(call KernelPackage,qca-nss-cfi-ocf)) diff --git a/qaa/nss/qca-nss-cfi/patches/0001-compile-only-cryptoapi.patch b/qaa/nss/qca-nss-cfi/patches/0001-compile-only-cryptoapi.patch new file mode 100644 index 000000000..00968f5fe --- /dev/null +++ b/qaa/nss/qca-nss-cfi/patches/0001-compile-only-cryptoapi.patch @@ -0,0 +1,30 @@ +From a8a573c5ce83bdddca9a60c62161638a5fd906d4 Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Sat, 13 Jun 2020 12:57:14 +0200 +Subject: [PATCH 1/3] compile only cryptoapi + +--- + Makefile | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +diff --git a/Makefile b/Makefile +index c42adca..36a9d3f 100644 +--- a/Makefile ++++ b/Makefile +@@ -4,9 +4,9 @@ + + export BUILD_ID = \"Build Id: $(shell date +'%m/%d/%y, %H:%M:%S')\" + +-obj-m += $(CFI_OCF_DIR)/ ++# obj-m += $(CFI_OCF_DIR)/ + obj-m += $(CFI_CRYPTOAPI_DIR)/ + +-ifeq ($(SoC),$(filter $(SoC),ipq806x)) +-obj-m += $(CFI_IPSEC_DIR)/ +-endif ++# ifeq ($(SoC),$(filter $(SoC),ipq806x)) ++# obj-m += $(CFI_IPSEC_DIR)/ ++# endif +-- +2.27.0.rc0 + diff --git a/qaa/nss/qca-nss-cfi/patches/0002-wip-support-5.4.patch b/qaa/nss/qca-nss-cfi/patches/0002-wip-support-5.4.patch new file mode 100644 index 000000000..d68fc939b --- /dev/null +++ b/qaa/nss/qca-nss-cfi/patches/0002-wip-support-5.4.patch @@ -0,0 +1,78 @@ +From 202f57bae49947a04301ac8ac9bdc00f28f09355 Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Sat, 13 Jun 2020 12:58:26 +0200 +Subject: [PATCH 2/3] wip: support 5.4 + +--- + cryptoapi/v1.1/nss_cryptoapi.c | 1 - + cryptoapi/v1.1/nss_cryptoapi_ablk.c | 12 ++++++------ + cryptoapi/v1.1/nss_cryptoapi_aead.c | 2 +- + 3 files changed, 7 insertions(+), 8 deletions(-) + +diff --git a/cryptoapi/v1.1/nss_cryptoapi.c b/cryptoapi/v1.1/nss_cryptoapi.c +index d1a7313..a10590e 100644 +--- a/cryptoapi/v1.1/nss_cryptoapi.c ++++ b/cryptoapi/v1.1/nss_cryptoapi.c +@@ -231,7 +231,6 @@ static struct crypto_alg cryptoapi_ablkcipher_algs[] = { + .cra_u = { + .ablkcipher = { + .ivsize = CTR_RFC3686_IV_SIZE, +- .geniv = "seqiv", + .min_keysize = AES_MIN_KEY_SIZE + CTR_RFC3686_NONCE_SIZE, + .max_keysize = AES_MAX_KEY_SIZE + CTR_RFC3686_NONCE_SIZE, + .setkey = nss_cryptoapi_ablk_aes_setkey, +diff --git a/cryptoapi/v1.1/nss_cryptoapi_ablk.c b/cryptoapi/v1.1/nss_cryptoapi_ablk.c +index 223591c..9b6c65e 100644 +--- a/cryptoapi/v1.1/nss_cryptoapi_ablk.c ++++ b/cryptoapi/v1.1/nss_cryptoapi_ablk.c +@@ -108,7 +108,7 @@ EXPORT_SYMBOL(nss_cryptoapi_skcipher_ctx2session); + int nss_cryptoapi_ablkcipher_init(struct crypto_tfm *tfm) + { + struct nss_cryptoapi_ctx *ctx = crypto_tfm_ctx(tfm); +- struct crypto_ablkcipher *sw_tfm; ++ struct crypto_cipher *sw_tfm; + + nss_cfi_assert(ctx); + +@@ -122,20 +122,20 @@ int nss_cryptoapi_ablkcipher_init(struct crypto_tfm *tfm) + + nss_cryptoapi_set_magic(ctx); + +- if (!(crypto_tfm_alg_flags(tfm) & CRYPTO_ALG_NEED_FALLBACK)) ++ if (!(crypto_tfm_alg_type(tfm) & CRYPTO_ALG_NEED_FALLBACK)) + return 0; + + /* Alloc fallback transform for future use */ +- sw_tfm = crypto_alloc_ablkcipher(crypto_tfm_alg_name(tfm), 0, CRYPTO_ALG_ASYNC | +- CRYPTO_ALG_NEED_FALLBACK); ++ sw_tfm = crypto_alloc_cipher(crypto_tfm_alg_name(tfm), 0, CRYPTO_ALG_ASYNC | ++ CRYPTO_ALG_NEED_FALLBACK); + if (IS_ERR(sw_tfm)) { + nss_cfi_err("unable to alloc software crypto for %s\n", crypto_tfm_alg_name(tfm)); + return -EINVAL; + } + + /* set this tfm reqsize same to fallback tfm */ +- tfm->crt_ablkcipher.reqsize = crypto_ablkcipher_reqsize(sw_tfm); +- ctx->sw_tfm = crypto_ablkcipher_tfm(sw_tfm); ++ tfm->crt_ablkcipher.reqsize = sizeof(struct nss_cryptoapi_ctx); ++ ctx->sw_tfm = crypto_cipher_tfm(sw_tfm); + + return 0; + } +diff --git a/cryptoapi/v1.1/nss_cryptoapi_aead.c b/cryptoapi/v1.1/nss_cryptoapi_aead.c +index 527936b..53e4bed 100644 +--- a/cryptoapi/v1.1/nss_cryptoapi_aead.c ++++ b/cryptoapi/v1.1/nss_cryptoapi_aead.c +@@ -103,7 +103,7 @@ int nss_cryptoapi_aead_init(struct crypto_aead *aead) + + nss_cryptoapi_set_magic(ctx); + +- if (!(crypto_tfm_alg_flags(tfm) & CRYPTO_ALG_NEED_FALLBACK)) ++ if (!(crypto_tfm_alg_type(tfm) & CRYPTO_ALG_NEED_FALLBACK)) + return 0; + + /* Alloc fallback transform for future use */ +-- +2.27.0.rc0 + diff --git a/qaa/nss/qca-nss-cfi/patches/0003-Convert-ablkcipher-to-skcipher.patch b/qaa/nss/qca-nss-cfi/patches/0003-Convert-ablkcipher-to-skcipher.patch new file mode 100644 index 000000000..b4520a3d6 --- /dev/null +++ b/qaa/nss/qca-nss-cfi/patches/0003-Convert-ablkcipher-to-skcipher.patch @@ -0,0 +1,707 @@ +From e3a53a6d11b2c1770545a2820a58c117799bcb70 Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Tue, 16 Jun 2020 18:12:34 +0200 +Subject: [PATCH 3/3] Convert ablkcipher to skcipher + +--- + cryptoapi/v1.1/nss_cryptoapi.c | 149 +++++++++++-------------- + cryptoapi/v1.1/nss_cryptoapi_ablk.c | 136 +++++++++++----------- + cryptoapi/v1.1/nss_cryptoapi_debugfs.c | 1 + + cryptoapi/v1.1/nss_cryptoapi_private.h | 16 +-- + 4 files changed, 145 insertions(+), 157 deletions(-) + +diff --git a/cryptoapi/v1.1/nss_cryptoapi.c b/cryptoapi/v1.1/nss_cryptoapi.c +index a10590e..3a835dc 100644 +--- a/cryptoapi/v1.1/nss_cryptoapi.c ++++ b/cryptoapi/v1.1/nss_cryptoapi.c +@@ -66,7 +66,7 @@ struct aead_alg cryptoapi_aead_algs[] = { + .cra_name = "echainiv(authenc(hmac(sha1),cbc(aes)))", + .cra_driver_name = "nss-hmac-sha1-cbc-aes", + .cra_priority = 10000, +- .cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NOSUPP_SG | CRYPTO_ALG_NEED_FALLBACK, ++ .cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NOSUPP_SG | CRYPTO_ALG_NEED_FALLBACK | CRYPTO_ALG_KERN_DRIVER_ONLY, + .cra_blocksize = AES_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct nss_cryptoapi_ctx), + .cra_alignmask = 0, +@@ -87,7 +87,7 @@ struct aead_alg cryptoapi_aead_algs[] = { + .cra_name = "seqiv(authenc(hmac(sha1),rfc3686(ctr(aes))))", + .cra_driver_name = "nss-hmac-sha1-rfc3686-ctr-aes", + .cra_priority = 10000, +- .cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NOSUPP_SG | CRYPTO_ALG_NEED_FALLBACK, ++ .cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NOSUPP_SG | CRYPTO_ALG_NEED_FALLBACK | CRYPTO_ALG_KERN_DRIVER_ONLY, + .cra_blocksize = AES_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct nss_cryptoapi_ctx), + .cra_alignmask = 0, +@@ -108,7 +108,7 @@ struct aead_alg cryptoapi_aead_algs[] = { + .cra_name = "echainiv(authenc(hmac(sha1),cbc(des3_ede)))", + .cra_driver_name = "nss-hmac-sha1-cbc-3des", + .cra_priority = 300, +- .cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NOSUPP_SG, ++ .cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NOSUPP_SG | CRYPTO_ALG_KERN_DRIVER_ONLY, + .cra_blocksize = DES3_EDE_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct nss_cryptoapi_ctx), + .cra_alignmask = 0, +@@ -129,7 +129,7 @@ struct aead_alg cryptoapi_aead_algs[] = { + .cra_name = "echainiv(authenc(hmac(sha256),cbc(aes)))", + .cra_driver_name = "nss-hmac-sha256-cbc-aes", + .cra_priority = 10000, +- .cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NOSUPP_SG | CRYPTO_ALG_NEED_FALLBACK, ++ .cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NOSUPP_SG | CRYPTO_ALG_NEED_FALLBACK | CRYPTO_ALG_KERN_DRIVER_ONLY, + .cra_blocksize = AES_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct nss_cryptoapi_ctx), + .cra_alignmask = 0, +@@ -150,7 +150,7 @@ struct aead_alg cryptoapi_aead_algs[] = { + .cra_name = "seqiv(authenc(hmac(sha256),rfc3686(ctr(aes))))", + .cra_driver_name = "nss-hmac-sha256-rfc3686-ctr-aes", + .cra_priority = 10000, +- .cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NOSUPP_SG | CRYPTO_ALG_NEED_FALLBACK, ++ .cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NOSUPP_SG | CRYPTO_ALG_NEED_FALLBACK | CRYPTO_ALG_KERN_DRIVER_ONLY, + .cra_blocksize = AES_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct nss_cryptoapi_ctx), + .cra_alignmask = 0, +@@ -171,7 +171,7 @@ struct aead_alg cryptoapi_aead_algs[] = { + .cra_name = "echainiv(authenc(hmac(sha256),cbc(des3_ede)))", + .cra_driver_name = "nss-hmac-sha256-cbc-3des", + .cra_priority = 300, +- .cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NOSUPP_SG, ++ .cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NOSUPP_SG | CRYPTO_ALG_KERN_DRIVER_ONLY, + .cra_blocksize = DES3_EDE_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct nss_cryptoapi_ctx), + .cra_alignmask = 0, +@@ -192,75 +192,66 @@ struct aead_alg cryptoapi_aead_algs[] = { + /* + * ABLK cipher algorithms + */ +-static struct crypto_alg cryptoapi_ablkcipher_algs[] = { ++static struct skcipher_alg cryptoapi_skcipher_algs[] = { + { +- .cra_name = "cbc(aes)", +- .cra_driver_name = "nss-cbc-aes", +- .cra_priority = 10000, +- .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_NOSUPP_SG | CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK, +- .cra_blocksize = AES_BLOCK_SIZE, +- .cra_ctxsize = sizeof(struct nss_cryptoapi_ctx), +- .cra_alignmask = 0, +- .cra_type = &crypto_ablkcipher_type, +- .cra_module = THIS_MODULE, +- .cra_init = nss_cryptoapi_ablkcipher_init, +- .cra_exit = nss_cryptoapi_ablkcipher_exit, +- .cra_u = { +- .ablkcipher = { +- .ivsize = AES_BLOCK_SIZE, +- .min_keysize = AES_MIN_KEY_SIZE, +- .max_keysize = AES_MAX_KEY_SIZE, +- .setkey = nss_cryptoapi_ablk_aes_setkey, +- .encrypt = nss_cryptoapi_ablk_aes_encrypt, +- .decrypt = nss_cryptoapi_ablk_aes_decrypt, +- }, ++ .base = { ++ .cra_name = "cbc(aes)", ++ .cra_driver_name = "nss-cbc-aes", ++ .cra_priority = 10000, ++ .cra_flags = CRYPTO_ALG_TYPE_SKCIPHER | CRYPTO_ALG_NOSUPP_SG | CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK | CRYPTO_ALG_KERN_DRIVER_ONLY, ++ .cra_blocksize = AES_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct nss_cryptoapi_ctx), ++ .cra_alignmask = 0, ++ .cra_module = THIS_MODULE, + }, ++ .init = nss_cryptoapi_skcipher_init, ++ .exit = nss_cryptoapi_skcipher_exit, ++ .ivsize = AES_BLOCK_SIZE, ++ .min_keysize = AES_MIN_KEY_SIZE, ++ .max_keysize = AES_MAX_KEY_SIZE, ++ .setkey = nss_cryptoapi_ablk_aes_setkey, ++ .encrypt = nss_cryptoapi_ablk_aes_encrypt, ++ .decrypt = nss_cryptoapi_ablk_aes_decrypt, + }, + { +- .cra_name = "rfc3686(ctr(aes))", +- .cra_driver_name = "nss-rfc3686-ctr-aes", +- .cra_priority = 30000, +- .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_NOSUPP_SG | CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK, +- .cra_blocksize = AES_BLOCK_SIZE, +- .cra_ctxsize = sizeof(struct nss_cryptoapi_ctx), +- .cra_alignmask = 0, +- .cra_type = &crypto_ablkcipher_type, +- .cra_module = THIS_MODULE, +- .cra_init = nss_cryptoapi_ablkcipher_init, +- .cra_exit = nss_cryptoapi_ablkcipher_exit, +- .cra_u = { +- .ablkcipher = { +- .ivsize = CTR_RFC3686_IV_SIZE, +- .min_keysize = AES_MIN_KEY_SIZE + CTR_RFC3686_NONCE_SIZE, +- .max_keysize = AES_MAX_KEY_SIZE + CTR_RFC3686_NONCE_SIZE, +- .setkey = nss_cryptoapi_ablk_aes_setkey, +- .encrypt = nss_cryptoapi_ablk_aes_encrypt, +- .decrypt = nss_cryptoapi_ablk_aes_decrypt, +- }, ++ .base = { ++ .cra_name = "rfc3686(ctr(aes))", ++ .cra_driver_name = "nss-rfc3686-ctr-aes", ++ .cra_priority = 30000, ++ .cra_flags = CRYPTO_ALG_TYPE_SKCIPHER | CRYPTO_ALG_NOSUPP_SG | CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK | CRYPTO_ALG_KERN_DRIVER_ONLY, ++ .cra_blocksize = AES_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct nss_cryptoapi_ctx), ++ .cra_alignmask = 0, ++ .cra_module = THIS_MODULE, + }, ++ .init = nss_cryptoapi_skcipher_init, ++ .exit = nss_cryptoapi_skcipher_exit, ++ .ivsize = CTR_RFC3686_IV_SIZE, ++ .min_keysize = AES_MIN_KEY_SIZE + CTR_RFC3686_NONCE_SIZE, ++ .max_keysize = AES_MAX_KEY_SIZE + CTR_RFC3686_NONCE_SIZE, ++ .setkey = nss_cryptoapi_ablk_aes_setkey, ++ .encrypt = nss_cryptoapi_ablk_aes_encrypt, ++ .decrypt = nss_cryptoapi_ablk_aes_decrypt, + }, + { +- .cra_name = "cbc(des3_ede)", +- .cra_driver_name = "nss-cbc-3des", +- .cra_priority = 1000, +- .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_NOSUPP_SG | CRYPTO_ALG_ASYNC, +- .cra_blocksize = DES3_EDE_BLOCK_SIZE, +- .cra_ctxsize = sizeof(struct nss_cryptoapi_ctx), +- .cra_alignmask = 0, +- .cra_type = &crypto_ablkcipher_type, +- .cra_module = THIS_MODULE, +- .cra_init = nss_cryptoapi_ablkcipher_init, +- .cra_exit = nss_cryptoapi_ablkcipher_exit, +- .cra_u = { +- .ablkcipher = { +- .ivsize = DES3_EDE_BLOCK_SIZE, +- .min_keysize = DES3_EDE_KEY_SIZE, +- .max_keysize = DES3_EDE_KEY_SIZE, +- .setkey = nss_cryptoapi_3des_cbc_setkey, +- .encrypt = nss_cryptoapi_3des_cbc_encrypt, +- .decrypt = nss_cryptoapi_3des_cbc_decrypt, +- }, ++ .base = { ++ .cra_name = "cbc(des3_ede)", ++ .cra_driver_name = "nss-cbc-3des", ++ .cra_priority = 1000, ++ .cra_flags = CRYPTO_ALG_TYPE_SKCIPHER | CRYPTO_ALG_NOSUPP_SG | CRYPTO_ALG_ASYNC | CRYPTO_ALG_KERN_DRIVER_ONLY, ++ .cra_blocksize = DES3_EDE_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct nss_cryptoapi_ctx), ++ .cra_alignmask = 0, ++ .cra_module = THIS_MODULE, + }, ++ .init = nss_cryptoapi_skcipher_init, ++ .exit = nss_cryptoapi_skcipher_exit, ++ .ivsize = DES3_EDE_BLOCK_SIZE, ++ .min_keysize = DES3_EDE_KEY_SIZE, ++ .max_keysize = DES3_EDE_KEY_SIZE, ++ .setkey = nss_cryptoapi_3des_cbc_setkey, ++ .encrypt = nss_cryptoapi_3des_cbc_encrypt, ++ .decrypt = nss_cryptoapi_3des_cbc_decrypt, + }, + }; + +@@ -277,14 +268,14 @@ static nss_crypto_user_ctx_t nss_cryptoapi_register(nss_crypto_handle_t crypto) + + sc->crypto = crypto; + +- for (i = 0; i < ARRAY_SIZE(cryptoapi_ablkcipher_algs); i++) { +- rc = crypto_register_alg(&cryptoapi_ablkcipher_algs[i]); ++ for (i = 0; i < ARRAY_SIZE(cryptoapi_skcipher_algs); i++) { ++ rc = crypto_register_skcipher(&cryptoapi_skcipher_algs[i]); + if (rc) { +- nss_cfi_trace("Ablk registration failed, algo: %s\n", cryptoapi_ablkcipher_algs[i].cra_name); +- cryptoapi_ablkcipher_algs[i].cra_flags = 0; ++ nss_cfi_trace("Ablk registration failed, algo: %s\n", cryptoapi_skcipher_algs[i].base.cra_name); ++ cryptoapi_skcipher_algs[i].base.cra_flags = 0; + continue; + } +- nss_cfi_info("Ablk registration succeeded, algo: %s\n", cryptoapi_ablkcipher_algs[i].cra_name); ++ nss_cfi_info("Ablk registration succeeded, algo: %s\n", cryptoapi_skcipher_algs[i].base.cra_name); + } + + for (i = 0; i < ARRAY_SIZE(cryptoapi_aead_algs); i++) { +@@ -317,7 +308,7 @@ static nss_crypto_user_ctx_t nss_cryptoapi_register(nss_crypto_handle_t crypto) + static void nss_cryptoapi_unregister(nss_crypto_user_ctx_t cfi) + { + struct nss_cryptoapi *sc = &gbl_ctx; +- int i, ret = 0; ++ int i; + + nss_cfi_info("unregister nss_cryptoapi\n"); + +@@ -326,16 +317,12 @@ static void nss_cryptoapi_unregister(nss_crypto_user_ctx_t cfi) + */ + atomic_set(&gbl_ctx.registered, 0); + +- for (i = 0; i < ARRAY_SIZE(cryptoapi_ablkcipher_algs); i++) { +- if (!cryptoapi_ablkcipher_algs[i].cra_flags) { +- continue; +- } +- ret = crypto_unregister_alg(&cryptoapi_ablkcipher_algs[i]); +- if (ret) { +- nss_cfi_err("Ablk unregister failed, algo: %s\n", cryptoapi_ablkcipher_algs[i].cra_name); ++ for (i = 0; i < ARRAY_SIZE(cryptoapi_skcipher_algs); i++) { ++ if (!cryptoapi_skcipher_algs[i].base.cra_flags) { + continue; + } +- nss_cfi_info("Ablk unregister succeeded, algo: %s\n", cryptoapi_ablkcipher_algs[i].cra_name); ++ crypto_unregister_skcipher(&cryptoapi_skcipher_algs[i]); ++ nss_cfi_info("Ablk unregister succeeded, algo: %s\n", cryptoapi_skcipher_algs[i].base.cra_name); + } + + for (i = 0; i < ARRAY_SIZE(cryptoapi_aead_algs); i++) { +diff --git a/cryptoapi/v1.1/nss_cryptoapi_ablk.c b/cryptoapi/v1.1/nss_cryptoapi_ablk.c +index 9b6c65e..913e9cc 100644 +--- a/cryptoapi/v1.1/nss_cryptoapi_ablk.c ++++ b/cryptoapi/v1.1/nss_cryptoapi_ablk.c +@@ -102,12 +102,12 @@ int nss_cryptoapi_skcipher_ctx2session(struct crypto_skcipher *sk, uint32_t *sid + EXPORT_SYMBOL(nss_cryptoapi_skcipher_ctx2session); + + /* +- * nss_cryptoapi_ablkcipher_init() +- * Cryptoapi ablkcipher init function. ++ * nss_cryptoapi_skcipher_init() ++ * Cryptoapi skcipher init function. + */ +-int nss_cryptoapi_ablkcipher_init(struct crypto_tfm *tfm) ++int nss_cryptoapi_skcipher_init(struct crypto_skcipher *tfm) + { +- struct nss_cryptoapi_ctx *ctx = crypto_tfm_ctx(tfm); ++ struct nss_cryptoapi_ctx *ctx = crypto_skcipher_ctx(tfm); + struct crypto_cipher *sw_tfm; + + nss_cfi_assert(ctx); +@@ -122,31 +122,31 @@ int nss_cryptoapi_ablkcipher_init(struct crypto_tfm *tfm) + + nss_cryptoapi_set_magic(ctx); + +- if (!(crypto_tfm_alg_type(tfm) & CRYPTO_ALG_NEED_FALLBACK)) ++ if (!(crypto_tfm_alg_type(&tfm->base) & CRYPTO_ALG_NEED_FALLBACK)) + return 0; + + /* Alloc fallback transform for future use */ +- sw_tfm = crypto_alloc_cipher(crypto_tfm_alg_name(tfm), 0, CRYPTO_ALG_ASYNC | ++ sw_tfm = crypto_alloc_cipher(crypto_tfm_alg_name(&tfm->base), 0, CRYPTO_ALG_ASYNC | + CRYPTO_ALG_NEED_FALLBACK); + if (IS_ERR(sw_tfm)) { +- nss_cfi_err("unable to alloc software crypto for %s\n", crypto_tfm_alg_name(tfm)); ++ nss_cfi_err("unable to alloc software crypto for %s\n", crypto_tfm_alg_name(&tfm->base)); + return -EINVAL; + } + + /* set this tfm reqsize same to fallback tfm */ +- tfm->crt_ablkcipher.reqsize = sizeof(struct nss_cryptoapi_ctx); ++ crypto_skcipher_set_reqsize(tfm, sizeof(struct nss_cryptoapi_ctx)); + ctx->sw_tfm = crypto_cipher_tfm(sw_tfm); + + return 0; + } + + /* +- * nss_cryptoapi_ablkcipher_exit() +- * Cryptoapi ablkcipher exit function. ++ * nss_cryptoapi_skcipher_exit() ++ * Cryptoapi skcipher exit function. + */ +-void nss_cryptoapi_ablkcipher_exit(struct crypto_tfm *tfm) ++void nss_cryptoapi_skcipher_exit(struct crypto_skcipher *tfm) + { +- struct nss_cryptoapi_ctx *ctx = crypto_tfm_ctx(tfm); ++ struct nss_cryptoapi_ctx *ctx = crypto_skcipher_ctx(tfm); + struct nss_cryptoapi *sc = &gbl_ctx; + nss_crypto_status_t status; + +@@ -158,7 +158,7 @@ void nss_cryptoapi_ablkcipher_exit(struct crypto_tfm *tfm) + } + + if (ctx->sw_tfm) { +- crypto_free_ablkcipher(__crypto_ablkcipher_cast(ctx->sw_tfm)); ++ crypto_free_skcipher(__crypto_skcipher_cast(ctx->sw_tfm)); + ctx->sw_tfm = NULL; + } + +@@ -183,9 +183,9 @@ void nss_cryptoapi_ablkcipher_exit(struct crypto_tfm *tfm) + * nss_cryptoapi_ablk_aes_setkey() + * Cryptoapi setkey routine for aes. + */ +-int nss_cryptoapi_ablk_aes_setkey(struct crypto_ablkcipher *cipher, const u8 *key, unsigned int keylen) ++int nss_cryptoapi_ablk_aes_setkey(struct crypto_skcipher *cipher, const u8 *key, unsigned int keylen) + { +- struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher); ++ struct crypto_tfm *tfm = crypto_skcipher_tfm(cipher); + struct nss_cryptoapi_ctx *ctx = crypto_tfm_ctx(tfm); + struct nss_cryptoapi *sc = &gbl_ctx; + struct nss_crypto_key cip; +@@ -255,10 +255,10 @@ int nss_cryptoapi_ablk_aes_setkey(struct crypto_ablkcipher *cipher, const u8 *ke + + /* set flag to fallback tfm */ + crypto_tfm_clear_flags(ctx->sw_tfm, CRYPTO_TFM_REQ_MASK); +- crypto_tfm_set_flags(ctx->sw_tfm, crypto_ablkcipher_get_flags(cipher) & CRYPTO_TFM_REQ_MASK); ++ crypto_tfm_set_flags(ctx->sw_tfm, crypto_skcipher_get_flags(cipher) & CRYPTO_TFM_REQ_MASK); + + /* Set key to the fallback tfm */ +- ret = crypto_ablkcipher_setkey(__crypto_ablkcipher_cast(ctx->sw_tfm), key, keylen); ++ ret = crypto_skcipher_setkey(__crypto_skcipher_cast(ctx->sw_tfm), key, keylen); + if (ret) { + nss_cfi_err("Failed to set key to the sw crypto"); + +@@ -266,7 +266,7 @@ int nss_cryptoapi_ablk_aes_setkey(struct crypto_ablkcipher *cipher, const u8 *ke + * Set back the fallback tfm flag to the original flag one after + * doing setkey + */ +- crypto_ablkcipher_set_flags(cipher, crypto_tfm_get_flags(ctx->sw_tfm)); ++ crypto_skcipher_set_flags(cipher, crypto_tfm_get_flags(ctx->sw_tfm)); + } + return ret; + default: +@@ -289,23 +289,23 @@ int nss_cryptoapi_ablk_aes_setkey(struct crypto_ablkcipher *cipher, const u8 *ke + return 0; + + fail: +- crypto_ablkcipher_set_flags(cipher, flag); ++ crypto_skcipher_set_flags(cipher, flag); + return -EINVAL; + } + + /* +- * nss_cryptoapi_ablkcipher_done() ++ * nss_cryptoapi_skcipher_done() + * Cipher operation completion callback function + */ +-void nss_cryptoapi_ablkcipher_done(struct nss_crypto_buf *buf) ++void nss_cryptoapi_skcipher_done(struct nss_crypto_buf *buf) + { + struct nss_cryptoapi_ctx *ctx; +- struct ablkcipher_request *req; ++ struct skcipher_request *req; + int err = 0; + + nss_cfi_assert(buf); + +- req = (struct ablkcipher_request *)nss_crypto_get_cb_ctx(buf); ++ req = (struct skcipher_request *)nss_crypto_get_cb_ctx(buf); + + /* + * check cryptoapi context magic number. +@@ -319,7 +319,7 @@ void nss_cryptoapi_ablkcipher_done(struct nss_crypto_buf *buf) + nss_crypto_buf_free(gbl_ctx.crypto, buf); + + nss_cfi_dbg("after transformation\n"); +- nss_cfi_dbg_data(sg_virt(req->dst), req->nbytes, ' '); ++ nss_cfi_dbg_data(sg_virt(req->dst), req->cryptlen, ' '); + + /* + * Passing always pass in case of encrypt. +@@ -337,7 +337,7 @@ void nss_cryptoapi_ablkcipher_done(struct nss_crypto_buf *buf) + * Cryptoapi: obtain sg to virtual address mapping. + * Check for multiple sg in src and dst + */ +-int nss_cryptoapi_ablk_checkaddr(struct ablkcipher_request *req) ++int nss_cryptoapi_ablk_checkaddr(struct skcipher_request *req) + { + /* + * Currently only single sg is supported +@@ -356,7 +356,7 @@ int nss_cryptoapi_ablk_checkaddr(struct ablkcipher_request *req) + /* + * If the size of data is more than 65K reject transformation + */ +- if (req->nbytes > NSS_CRYPTOAPI_MAX_DATA_LEN) { ++ if (req->cryptlen > NSS_CRYPTOAPI_MAX_DATA_LEN) { + nss_cfi_err("Buffer length exceeded limit\n"); + return -EINVAL; + } +@@ -368,10 +368,10 @@ int nss_cryptoapi_ablk_checkaddr(struct ablkcipher_request *req) + * nss_cryptoapi_ablk_transform() + * Crytoapi common routine for encryption and decryption operations. + */ +-struct nss_crypto_buf *nss_cryptoapi_ablk_transform(struct ablkcipher_request *req, struct nss_cryptoapi_ablk_info *info) ++struct nss_crypto_buf *nss_cryptoapi_ablk_transform(struct skcipher_request *req, struct nss_cryptoapi_ablk_info *info) + { +- struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(req); +- struct nss_cryptoapi_ctx *ctx = crypto_ablkcipher_ctx(cipher); ++ struct crypto_skcipher *cipher = crypto_skcipher_reqtfm(req); ++ struct nss_cryptoapi_ctx *ctx = crypto_skcipher_ctx(cipher); + struct nss_crypto_buf *buf; + struct nss_cryptoapi *sc = &gbl_ctx; + nss_crypto_status_t status; +@@ -382,7 +382,7 @@ struct nss_crypto_buf *nss_cryptoapi_ablk_transform(struct ablkcipher_request *r + nss_cfi_assert(ctx); + + nss_cfi_dbg("src_vaddr: 0x%p, dst_vaddr: 0x%p, iv: 0x%p\n", +- sg_virt(req->src), sg_virt(req->dst), req->info); ++ sg_virt(req->src), sg_virt(req->dst), req->iv); + + info->params->cipher_skip = 0; + info->params->auth_skip = 0; +@@ -419,19 +419,19 @@ struct nss_crypto_buf *nss_cryptoapi_ablk_transform(struct ablkcipher_request *r + /* + * Get IV location and memcpy the IV + */ +- iv_size = crypto_ablkcipher_ivsize(cipher); ++ iv_size = crypto_skcipher_ivsize(cipher); + iv_addr = nss_crypto_get_ivaddr(buf); + + switch (ctx->cip_alg) { + case NSS_CRYPTO_CIPHER_AES_CBC: + case NSS_CRYPTO_CIPHER_DES: +- memcpy(iv_addr, req->info, iv_size); ++ memcpy(iv_addr, req->iv, iv_size); + break; + + case NSS_CRYPTO_CIPHER_AES_CTR: + ((uint32_t *)iv_addr)[0] = ctx->ctx_iv[0]; +- ((uint32_t *)iv_addr)[1] = ((uint32_t *)req->info)[0]; +- ((uint32_t *)iv_addr)[2] = ((uint32_t *)req->info)[1]; ++ ((uint32_t *)iv_addr)[1] = ((uint32_t *)req->iv)[0]; ++ ((uint32_t *)iv_addr)[2] = ((uint32_t *)req->iv)[1]; + ((uint32_t *)iv_addr)[3] = ctx->ctx_iv[3]; + break; + +@@ -446,7 +446,7 @@ struct nss_crypto_buf *nss_cryptoapi_ablk_transform(struct ablkcipher_request *r + /* + * Fill Cipher and Auth len + */ +- cipher_len = req->nbytes; ++ cipher_len = req->cryptlen; + auth_len = 0; + + nss_crypto_set_data(buf, sg_virt(req->src), sg_virt(req->dst), cipher_len); +@@ -463,12 +463,12 @@ struct nss_crypto_buf *nss_cryptoapi_ablk_transform(struct ablkcipher_request *r + } + + /* +- * nss_cryptoapi_ablkcipher_fallback() +- * Cryptoapi fallback for ablkcipher algorithm. ++ * nss_cryptoapi_skcipher_fallback() ++ * Cryptoapi fallback for skcipher algorithm. + */ +-int nss_cryptoapi_ablkcipher_fallback(struct nss_cryptoapi_ctx *ctx, struct ablkcipher_request *req, int type) ++int nss_cryptoapi_skcipher_fallback(struct nss_cryptoapi_ctx *ctx, struct skcipher_request *req, int type) + { +- struct crypto_ablkcipher *orig_tfm = crypto_ablkcipher_reqtfm(req); ++ struct crypto_skcipher *orig_tfm = crypto_skcipher_reqtfm(req); + int err; + + if (!ctx->sw_tfm) { +@@ -476,16 +476,16 @@ int nss_cryptoapi_ablkcipher_fallback(struct nss_cryptoapi_ctx *ctx, struct ablk + } + + /* Set new fallback tfm to the request */ +- ablkcipher_request_set_tfm(req, __crypto_ablkcipher_cast(ctx->sw_tfm)); ++ skcipher_request_set_tfm(req, __crypto_skcipher_cast(ctx->sw_tfm)); + + ctx->queued++; + + switch (type) { + case NSS_CRYPTOAPI_ENCRYPT: +- err = crypto_ablkcipher_encrypt(req); ++ err = crypto_skcipher_encrypt(req); + break; + case NSS_CRYPTOAPI_DECRYPT: +- err = crypto_ablkcipher_decrypt(req); ++ err = crypto_skcipher_decrypt(req); + break; + default: + err = -EINVAL; +@@ -495,7 +495,7 @@ int nss_cryptoapi_ablkcipher_fallback(struct nss_cryptoapi_ctx *ctx, struct ablk + ctx->completed++; + + /* Set original tfm to the request */ +- ablkcipher_request_set_tfm(req, orig_tfm); ++ skcipher_request_set_tfm(req, orig_tfm); + + return err; + } +@@ -504,13 +504,13 @@ int nss_cryptoapi_ablkcipher_fallback(struct nss_cryptoapi_ctx *ctx, struct ablk + * nss_cryptoapi_ablk_aes_encrypt() + * Crytoapi encrypt for aes(aes-cbc/rfc3686-aes-ctr) algorithms. + */ +-int nss_cryptoapi_ablk_aes_encrypt(struct ablkcipher_request *req) ++int nss_cryptoapi_ablk_aes_encrypt(struct skcipher_request *req) + { + struct nss_crypto_params params = { .req_type = NSS_CRYPTO_REQ_TYPE_ENCRYPT }; +- struct nss_cryptoapi_ablk_info info = {.cb_fn = nss_cryptoapi_ablkcipher_done, ++ struct nss_cryptoapi_ablk_info info = {.cb_fn = nss_cryptoapi_skcipher_done, + .params = ¶ms}; +- struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(req); +- struct nss_cryptoapi_ctx *ctx = crypto_ablkcipher_ctx(cipher); ++ struct crypto_skcipher *cipher = crypto_skcipher_reqtfm(req); ++ struct nss_cryptoapi_ctx *ctx = crypto_skcipher_ctx(cipher); + struct nss_cryptoapi *sc = &gbl_ctx; + struct nss_crypto_buf *buf; + +@@ -520,7 +520,7 @@ int nss_cryptoapi_ablk_aes_encrypt(struct ablkcipher_request *req) + nss_cryptoapi_verify_magic(ctx); + + if (ctx->fallback_req) +- return nss_cryptoapi_ablkcipher_fallback(ctx, req, NSS_CRYPTOAPI_ENCRYPT); ++ return nss_cryptoapi_skcipher_fallback(ctx, req, NSS_CRYPTOAPI_ENCRYPT); + + /* + * Check if previous call to setkey couldn't allocate session with core crypto. +@@ -539,9 +539,9 @@ int nss_cryptoapi_ablk_aes_encrypt(struct ablkcipher_request *req) + * According to RFC3686, AES-CTR algo need not be padded if the + * plaintext or ciphertext is unaligned to block size boundary. + */ +- if (nss_cryptoapi_check_unalign(req->nbytes, AES_BLOCK_SIZE) && (ctx->cip_alg != NSS_CRYPTO_CIPHER_AES_CTR)) { ++ if (nss_cryptoapi_check_unalign(req->cryptlen, AES_BLOCK_SIZE) && (ctx->cip_alg != NSS_CRYPTO_CIPHER_AES_CTR)) { + nss_cfi_err("Invalid cipher len - Not aligned to algo blocksize\n"); +- crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_BLOCK_LEN); ++ crypto_skcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_BLOCK_LEN); + return -EINVAL; + } + +@@ -571,13 +571,13 @@ int nss_cryptoapi_ablk_aes_encrypt(struct ablkcipher_request *req) + * nss_cryptoapi_ablk_aes_decrypt() + * Crytoapi decrypt for aes(aes-cbc/rfc3686-aes-ctr) algorithms. + */ +-int nss_cryptoapi_ablk_aes_decrypt(struct ablkcipher_request *req) ++int nss_cryptoapi_ablk_aes_decrypt(struct skcipher_request *req) + { + struct nss_crypto_params params = { .req_type = NSS_CRYPTO_REQ_TYPE_DECRYPT }; +- struct nss_cryptoapi_ablk_info info = {.cb_fn = nss_cryptoapi_ablkcipher_done, ++ struct nss_cryptoapi_ablk_info info = {.cb_fn = nss_cryptoapi_skcipher_done, + .params = ¶ms}; +- struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(req); +- struct nss_cryptoapi_ctx *ctx = crypto_ablkcipher_ctx(cipher); ++ struct crypto_skcipher *cipher = crypto_skcipher_reqtfm(req); ++ struct nss_cryptoapi_ctx *ctx = crypto_skcipher_ctx(cipher); + struct nss_cryptoapi *sc = &gbl_ctx; + struct nss_crypto_buf *buf; + +@@ -587,7 +587,7 @@ int nss_cryptoapi_ablk_aes_decrypt(struct ablkcipher_request *req) + nss_cryptoapi_verify_magic(ctx); + + if (ctx->fallback_req) +- return nss_cryptoapi_ablkcipher_fallback(ctx, req, NSS_CRYPTOAPI_DECRYPT); ++ return nss_cryptoapi_skcipher_fallback(ctx, req, NSS_CRYPTOAPI_DECRYPT); + + /* + * Check if previous call to setkey couldn't allocate session with core crypto. +@@ -606,9 +606,9 @@ int nss_cryptoapi_ablk_aes_decrypt(struct ablkcipher_request *req) + * According to RFC3686, AES-CTR algo need not be padded if the + * plaintext or ciphertext is unaligned to block size boundary. + */ +- if (nss_cryptoapi_check_unalign(req->nbytes, AES_BLOCK_SIZE) && (ctx->cip_alg != NSS_CRYPTO_CIPHER_AES_CTR)) { ++ if (nss_cryptoapi_check_unalign(req->cryptlen, AES_BLOCK_SIZE) && (ctx->cip_alg != NSS_CRYPTO_CIPHER_AES_CTR)) { + nss_cfi_err("Invalid cipher len - Not aligned to algo blocksize\n"); +- crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_BLOCK_LEN); ++ crypto_skcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_BLOCK_LEN); + return -EINVAL; + } + +@@ -638,9 +638,9 @@ int nss_cryptoapi_ablk_aes_decrypt(struct ablkcipher_request *req) + * nss_cryptoapi_3des_cbc_setkey() + * Cryptoapi DES3 CBC setkey function. + */ +-int nss_cryptoapi_3des_cbc_setkey(struct crypto_ablkcipher *cipher, const u8 *key, unsigned int keylen) ++int nss_cryptoapi_3des_cbc_setkey(struct crypto_skcipher *cipher, const u8 *key, unsigned int keylen) + { +- struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher); ++ struct crypto_tfm *tfm = crypto_skcipher_tfm(cipher); + struct nss_cryptoapi_ctx *ctx = crypto_tfm_ctx(tfm); + struct nss_cryptoapi *sc = &gbl_ctx; + struct nss_crypto_key cip = { .algo = NSS_CRYPTO_CIPHER_DES }; +@@ -693,7 +693,7 @@ int nss_cryptoapi_3des_cbc_setkey(struct crypto_ablkcipher *cipher, const u8 *ke + return 0; + + fail: +- crypto_ablkcipher_set_flags(cipher, flag); ++ crypto_skcipher_set_flags(cipher, flag); + return -EINVAL; + } + +@@ -701,7 +701,7 @@ fail: + * nss_cryptoapi_3des_cbc_encrypt() + * Cryptoapi DES3 CBC encrypt function. + */ +-int nss_cryptoapi_3des_cbc_encrypt(struct ablkcipher_request *req) ++int nss_cryptoapi_3des_cbc_encrypt(struct skcipher_request *req) + { + struct nss_cryptoapi *sc = &gbl_ctx; + struct nss_cryptoapi_ctx *ctx = crypto_tfm_ctx(req->base.tfm); +@@ -727,14 +727,14 @@ int nss_cryptoapi_3des_cbc_encrypt(struct ablkcipher_request *req) + return -EINVAL; + } + +- if (nss_cryptoapi_check_unalign(req->nbytes, DES3_EDE_BLOCK_SIZE)) { ++ if (nss_cryptoapi_check_unalign(req->cryptlen, DES3_EDE_BLOCK_SIZE)) { + nss_cfi_err("Invalid cipher len - Not aligned to algo blocksize\n"); +- crypto_ablkcipher_set_flags(crypto_ablkcipher_reqtfm(req), CRYPTO_TFM_RES_BAD_BLOCK_LEN); ++ crypto_skcipher_set_flags(crypto_skcipher_reqtfm(req), CRYPTO_TFM_RES_BAD_BLOCK_LEN); + return -EINVAL; + } + + info.params = ¶ms; +- info.cb_fn = nss_cryptoapi_ablkcipher_done; ++ info.cb_fn = nss_cryptoapi_skcipher_done; + + buf = nss_cryptoapi_ablk_transform(req, &info); + if (!buf) { +@@ -762,7 +762,7 @@ int nss_cryptoapi_3des_cbc_encrypt(struct ablkcipher_request *req) + * nss_cryptoapi_3des_cbc_decrypt() + * Cryptoapi DES3 CBC decrypt function. + */ +-int nss_cryptoapi_3des_cbc_decrypt(struct ablkcipher_request *req) ++int nss_cryptoapi_3des_cbc_decrypt(struct skcipher_request *req) + { + struct nss_cryptoapi *sc = &gbl_ctx; + struct nss_cryptoapi_ctx *ctx = crypto_tfm_ctx(req->base.tfm); +@@ -788,14 +788,14 @@ int nss_cryptoapi_3des_cbc_decrypt(struct ablkcipher_request *req) + return -EINVAL; + } + +- if (nss_cryptoapi_check_unalign(req->nbytes, DES3_EDE_BLOCK_SIZE)) { ++ if (nss_cryptoapi_check_unalign(req->cryptlen, DES3_EDE_BLOCK_SIZE)) { + nss_cfi_err("Invalid cipher len - Not aligned to algo blocksize\n"); +- crypto_ablkcipher_set_flags(crypto_ablkcipher_reqtfm(req), CRYPTO_TFM_RES_BAD_BLOCK_LEN); ++ crypto_skcipher_set_flags(crypto_skcipher_reqtfm(req), CRYPTO_TFM_RES_BAD_BLOCK_LEN); + return -EINVAL; + } + + info.params = ¶ms; +- info.cb_fn = nss_cryptoapi_ablkcipher_done; ++ info.cb_fn = nss_cryptoapi_skcipher_done; + + buf = nss_cryptoapi_ablk_transform(req, &info); + if (!buf) { +diff --git a/cryptoapi/v1.1/nss_cryptoapi_debugfs.c b/cryptoapi/v1.1/nss_cryptoapi_debugfs.c +index dff774c..cf4bc70 100644 +--- a/cryptoapi/v1.1/nss_cryptoapi_debugfs.c ++++ b/cryptoapi/v1.1/nss_cryptoapi_debugfs.c +@@ -55,6 +55,7 @@ + */ + void nss_cryptoapi_debugfs_add_stats(struct dentry *parent, struct nss_cryptoapi_ctx *session_ctx) + { ++ pr_info("add stats"); + debugfs_create_u64("queued", S_IRUGO, parent, &session_ctx->queued); + debugfs_create_u64("completed", S_IRUGO, parent, &session_ctx->completed); + debugfs_create_u64("queue_failed", S_IRUGO, parent, &session_ctx->queue_failed); +diff --git a/cryptoapi/v1.1/nss_cryptoapi_private.h b/cryptoapi/v1.1/nss_cryptoapi_private.h +index 5feb9e3..70c6714 100644 +--- a/cryptoapi/v1.1/nss_cryptoapi_private.h ++++ b/cryptoapi/v1.1/nss_cryptoapi_private.h +@@ -141,16 +141,16 @@ int nss_cryptoapi_sha256_3des_encrypt(struct aead_request *req); + int nss_cryptoapi_sha256_3des_decrypt(struct aead_request *req); + + /* ABLKCIPHER */ +-int nss_cryptoapi_ablkcipher_init(struct crypto_tfm *tfm); +-void nss_cryptoapi_ablkcipher_exit(struct crypto_tfm *tfm); +-int nss_cryptoapi_ablk_aes_setkey(struct crypto_ablkcipher *cipher, const u8 *key, unsigned int len); +-int nss_cryptoapi_3des_cbc_setkey(struct crypto_ablkcipher *cipher, const u8 *key, unsigned int len); ++int nss_cryptoapi_skcipher_init(struct crypto_skcipher *tfm); ++void nss_cryptoapi_skcipher_exit(struct crypto_skcipher *tfm); ++int nss_cryptoapi_ablk_aes_setkey(struct crypto_skcipher *cipher, const u8 *key, unsigned int len); ++int nss_cryptoapi_3des_cbc_setkey(struct crypto_skcipher *cipher, const u8 *key, unsigned int len); + +-int nss_cryptoapi_ablk_aes_encrypt(struct ablkcipher_request *req); +-int nss_cryptoapi_ablk_aes_decrypt(struct ablkcipher_request *req); ++int nss_cryptoapi_ablk_aes_encrypt(struct skcipher_request *req); ++int nss_cryptoapi_ablk_aes_decrypt(struct skcipher_request *req); + +-int nss_cryptoapi_3des_cbc_encrypt(struct ablkcipher_request *req); +-int nss_cryptoapi_3des_cbc_decrypt(struct ablkcipher_request *req); ++int nss_cryptoapi_3des_cbc_encrypt(struct skcipher_request *req); ++int nss_cryptoapi_3des_cbc_decrypt(struct skcipher_request *req); + + #endif /* __NSS_CRYPTOAPI_PRIVATE_H */ + +-- +2.27.0.rc0 + diff --git a/qaa/nss/qca-nss-clients-64/Makefile b/qaa/nss/qca-nss-clients-64/Makefile new file mode 100644 index 000000000..741646ba8 --- /dev/null +++ b/qaa/nss/qca-nss-clients-64/Makefile @@ -0,0 +1,97 @@ +include $(TOPDIR)/rules.mk + +PKG_NAME:=qca-nss-clients-64 +PKG_RELEASE:=$(AUTORELEASE) + +PKG_SOURCE_URL:=https://source.codeaurora.org/quic/cc-qrdk/oss/lklm/nss-clients +PKG_SOURCE_PROTO:=git +PKG_SOURCE_DATE:=2021-04-29 +PKG_SOURCE_VERSION:=b93c72c1b72c591c2ddc2f0b24f0e2b457720118 +PKG_MIRROR_HASH:=fbfba64a364b095ea7c9a24cd7af96b63ab0bc29c179e1628c675aa223c0d063 + +include $(INCLUDE_DIR)/kernel.mk +include $(INCLUDE_DIR)/package.mk + +define KernelPackage/qca-nss-drv-pppoe-64 + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=Kernel driver for NSS (connection manager) - PPPoE + DEPENDS:=@TARGET_ipq807x +kmod-qca-nss-drv-64 +kmod-ppp +kmod-pppoe + FILES:=$(PKG_BUILD_DIR)/pppoe/qca-nss-pppoe.ko + AUTOLOAD:=$(call AutoLoad,51,qca-nss-pppoe) +endef + +define KernelPackage/qca-nss-drv-pppoe-64/Description +Kernel modules for NSS connection manager - Support for PPPoE +endef + +define KernelPackage/qca-nss-drv-bridge-mgr-64 + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=Kernel driver for NSS bridge manager + DEPENDS:=@LINUX_5_10 @TARGET_ipq807x +kmod-qca-nss-drv-64 +kmod-qca-nss-drv-vlan-mgr-64 + FILES:=$(PKG_BUILD_DIR)/bridge/qca-nss-bridge-mgr.ko + AUTOLOAD:=$(call AutoLoad,51,qca-nss-bridge-mgr) +endef + +define KernelPackage/qca-nss-drv-bridge-mgr-64/Description +Kernel modules for NSS bridge manager +endef + +define KernelPackage/qca-nss-drv-vlan-mgr-64 + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=Kernel driver for NSS vlan manager + DEPENDS:=@LINUX_5_10 @TARGET_ipq807x +kmod-qca-nss-drv-64 + FILES:=$(PKG_BUILD_DIR)/vlan/qca-nss-vlan.ko + AUTOLOAD:=$(call AutoLoad,51,qca-nss-vlan) +endef + +define KernelPackage/qca-nss-drv-vlan-mgr-64/Description +Kernel modules for NSS vlan manager +endef + +EXTRA_CFLAGS+= \ + -I$(STAGING_DIR)/usr/include/qca-nss-drv \ + -I$(STAGING_DIR)/usr/include/qca-nss-crypto \ + -I$(STAGING_DIR)/usr/include/qca-nss-cfi \ + -I$(STAGING_DIR)/usr/include/qca-nss-gmac \ + -I$(STAGING_DIR)/usr/include/qca-ssdk \ + -I$(STAGING_DIR)/usr/include/qca-ssdk/fal \ + -I$(STAGING_DIR)/usr/include/nat46 + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-pppoe-64),) +NSS_CLIENTS_MAKE_OPTS+=pppoe=y +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-bridge-mgr-64),) +NSS_CLIENTS_MAKE_OPTS+=bridge-mgr=y +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-vlan-mgr-64),) +NSS_CLIENTS_MAKE_OPTS+=vlan-mgr=y +endif + +ifeq ($(CONFIG_TARGET_BOARD), "ipq807x") + SOC="ipq807x_64" +else ifeq ($(CONFIG_TARGET_BOARD), "ipq60xx") + SOC="ipq60xx_64" +endif + +define Build/Compile + $(MAKE) -C "$(LINUX_DIR)" $(strip $(NSS_CLIENTS_MAKE_OPTS)) \ + CROSS_COMPILE="$(TARGET_CROSS)" \ + ARCH="$(LINUX_KARCH)" \ + M="$(PKG_BUILD_DIR)" \ + EXTRA_CFLAGS="$(EXTRA_CFLAGS)" \ + SoC=$(SOC) \ + $(KERNEL_MAKE_FLAGS) \ + modules +endef + +$(eval $(call KernelPackage,qca-nss-drv-pppoe-64)) +$(eval $(call KernelPackage,qca-nss-drv-bridge-mgr-64)) +$(eval $(call KernelPackage,qca-nss-drv-vlan-mgr-64)) diff --git a/qaa/nss/qca-nss-clients-64/files/qca-nss-ipsec b/qaa/nss/qca-nss-clients-64/files/qca-nss-ipsec new file mode 100644 index 000000000..5f682c8e9 --- /dev/null +++ b/qaa/nss/qca-nss-clients-64/files/qca-nss-ipsec @@ -0,0 +1,214 @@ +#!/bin/sh /etc/rc.common +# +# Copyright (c) 2018-2019, 2021 The Linux Foundation. All rights reserved. +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +NSS_IPSEC_LOG_FILE=/tmp/.nss_ipsec_log +NSS_IPSEC_LOG_STR_ECM="ECM_Loaded" +NSS_IPSEC_OL_FILE=/tmp/qca_nss_ipsec_ol + +ecm_load () { + if [ ! -d /sys/module/ecm ]; then + /etc/init.d/qca-nss-ecm start + if [ -d /sys/module/ecm ]; then + echo ${NSS_IPSEC_LOG_STR_ECM} >> ${NSS_IPSEC_LOG_FILE} + fi + fi +} + +ecm_unload () { + if [ -f /tmp/.nss_ipsec_log ]; then + str=`grep ${NSS_IPSEC_LOG_STR_ECM} ${NSS_IPSEC_LOG_FILE}` + if [[ $str == ${NSS_IPSEC_LOG_STR_ECM} ]]; then + /etc/init.d/qca-nss-ecm stop + `sed 's/${NSS_IPSEC_LOG_STR_ECM}/ /g' $NSS_IPSEC_LOG_FILE > $NSS_IPSEC_LOG_FILE` + fi + fi +} + +ecm_disable() { + + if [ ! -d /sys/module/ecm ]; then + return; + fi + + echo 1 > /sys/kernel/debug/ecm/front_end_ipv4_stop + echo 1 > /sys/kernel/debug/ecm/front_end_ipv6_stop + echo 1 > /sys/kernel/debug/ecm/ecm_db/defunct_all + sleep 2 +} + +ecm_enable() { + if [ ! -d /sys/module/ecm ]; then + return; + fi + + echo 0 > /sys/kernel/debug/ecm/ecm_db/defunct_all + echo 0 > /sys/kernel/debug/ecm/front_end_ipv4_stop + echo 0 > /sys/kernel/debug/ecm/front_end_ipv6_stop +} + +kernel_version_check_5_4() { + major_ver=$(uname -r | awk -F '.' '{print $1}') + minor_ver=$(uname -r | awk -F '.' '{print $2}') + if [ $major_ver -lt 5 ] || ([ $major_ver -eq 5 ] && [ $minor_ver -lt 4 ] ) ; then + return 1 + else + return 0 + fi +} + +start_klips() { + if kernel_version_check_5_4 + then + echo "Kernel 5.4 doesn't support klips stack." + return $? + fi + + touch $NSS_IPSEC_OL_FILE + ecm_load + + local kernel_version=$(uname -r) + + insmod /lib/modules/${kernel_version}/qca-nss-ipsec-klips.ko + if [ "$?" -gt 0 ]; then + echo "Failed to load plugin. Please start ecm if not done already" + ecm_enable + rm $NSS_IPSEC_OL_FILE + return + fi + + /etc/init.d/ipsec start + sleep 2 + ipsec eroute + + ecm_enable +} + +stop_klips() { + if kernel_version_check_5_4 + then + echo "Kernel 5.4 doesn't support klips stack." + return $? + fi + + ecm_disable + + /etc/init.d/ipsec stop + rmmod qca-nss-ipsec-klips + rm $NSS_IPSEC_OL_FILE + + ecm_unload +} + +start_xfrm() { + touch $NSS_IPSEC_OL_FILE + ecm_load + + local kernel_version=$(uname -r) + + # load all NETKEY modules first. + for mod in xfrm_ipcomp ipcomp xfrm6_tunnel ipcomp6 xfrm6_mode_tunnel xfrm6_mode_beet xfrm6_mode_ro \ + xfrm6_mode_transport xfrm4_mode_transport xfrm4_mode_tunnel \ + xfrm4_tunnel xfrm4_mode_beet esp4 esp6 ah4 ah6 af_key + do + insmod $mod 2> /dev/null + done + + # Now load the xfrm plugin + insmod /lib/modules/${kernel_version}/qca-nss-ipsec-xfrm.ko + if [ "$?" -gt 0 ]; then + echo "Failed to load plugin. Please start ecm if not done already" + ecm_enable + rm $NSS_IPSEC_OL_FILE + return + fi + + /etc/init.d/ipsec start + sleep 2 + + ecm_enable +} + +stop_xfrm() { + ecm_disable + + #Shutdown Pluto first. Then only plugin can be removed. + plutopid=/var/run/pluto/pluto.pid + if [ -f $plutopid ]; then + pid=`cat $plutopid` + if [ ! -z "$pid" ]; then + ipsec whack --shutdown | grep -v "002"; + if [ -s $plutopid ]; then + echo "Attempt to shut Pluto down failed! Trying kill:" + kill $pid; + sleep 5; + fi + fi + rm -rf $plutopid + fi + ip xfrm state flush; + ip xfrm policy flush; + sleep 2 + + #Now we can remove the plugin + retries=5 + while [ -d /sys/module/qca_nss_ipsec_xfrm ] + do + rmmod qca-nss-ipsec-xfrm + if [ "$?" -eq 0 ]; then + rm $NSS_IPSEC_OL_FILE + break + fi + + if [ ${retries} -eq 0 ]; then + echo "Failed to unload qca-nss-ipsec-xfrm plugin!" + exit + fi + + echo "XFRM plugin unload failed; retrying ${retries} times" + sleep 1 + retries=`expr ${retries} - 1` + done + + /etc/init.d/ipsec stop + ecm_unload +} + +start() { + local protostack=`uci -q get ipsec.setup.protostack` + if [ "$protostack" = "klips" ]; then + start_klips + return $? + fi + + start_xfrm + return $? +} + +stop() { + local protostack=`uci -q get ipsec.setup.protostack` + if [ "$protostack" = "klips" ]; then + stop_klips + return $? + fi + + stop_xfrm + return $? +} + +restart() { + stop + start +} diff --git a/qaa/nss/qca-nss-clients-64/files/qca-nss-mirred.init b/qaa/nss/qca-nss-clients-64/files/qca-nss-mirred.init new file mode 100644 index 000000000..1f931f090 --- /dev/null +++ b/qaa/nss/qca-nss-clients-64/files/qca-nss-mirred.init @@ -0,0 +1,28 @@ +#!/bin/sh /etc/rc.common + +########################################################################### +# Copyright (c) 2019, The Linux Foundation. All rights reserved. +# Permission to use, copy, modify, and/or distribute this software for +# any purpose with or without fee is hereby granted, provided that the +# above copyright notice and this permission notice appear in all copies. +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT +# OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +########################################################################### + +restart() { + rmmod act_nssmirred.ko + insmod act_nssmirred.ko +} + +start() { + insmod act_nssmirred.ko +} + +stop() { + rmmod act_nssmirred.ko +} diff --git a/qaa/nss/qca-nss-clients-64/files/qca-nss-ovpn.init b/qaa/nss/qca-nss-clients-64/files/qca-nss-ovpn.init new file mode 100644 index 000000000..622e295ee --- /dev/null +++ b/qaa/nss/qca-nss-clients-64/files/qca-nss-ovpn.init @@ -0,0 +1,69 @@ +#!/bin/sh /etc/rc.common + +########################################################################### +# Copyright (c) 2019, The Linux Foundation. All rights reserved. +# Permission to use, copy, modify, and/or distribute this software for +# any purpose with or without fee is hereby granted, provided that the +# above copyright notice and this permission notice appear in all copies. +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT +# OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +########################################################################### + +ecm_disable() { + if [ ! -d /sys/module/ecm ]; then + return + fi + + echo 1 > /sys/kernel/debug/ecm/front_end_ipv4_stop + echo 1 > /sys/kernel/debug/ecm/front_end_ipv6_stop + echo 1 > /sys/kernel/debug/ecm/ecm_db/defunct_all + sleep 2 +} + +ecm_enable() { + if [ ! -d /sys/module/ecm ]; then + return + fi + + echo 0 > /sys/kernel/debug/ecm/ecm_db/defunct_all + echo 0 > /sys/kernel/debug/ecm/front_end_ipv4_stop + echo 0 > /sys/kernel/debug/ecm/front_end_ipv6_stop +} + +restart() { + ecm_disable + + /etc/init.d/openvpn stop + rmmod qca-nss-ovpn-link + rmmod qca-nss-ovpn-mgr + + insmod qca-nss-ovpn-mgr + insmod qca-nss-ovpn-link + + if [ "$?" -gt 0 ]; then + echo "Failed to load plugin. Please start ecm if not done already" + ecm_enable + return + fi + + ecm_enable +} + +start() { + restart +} + +stop() { + ecm_disable + + /etc/init.d/openvpn stop + rmmod qca-nss-ovpn-link + rmmod qca-nss-ovpn-mgr + + ecm_enable +} diff --git a/qaa/nss/qca-nss-clients/Makefile b/qaa/nss/qca-nss-clients/Makefile new file mode 100644 index 000000000..e782cf81d --- /dev/null +++ b/qaa/nss/qca-nss-clients/Makefile @@ -0,0 +1,469 @@ +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/kernel.mk + +PKG_NAME:=qca-nss-clients +PKG_RELEASE:=2 + +PKG_SOURCE_URL:=https://source.codeaurora.org/quic/qsdk/oss/lklm/nss-clients +PKG_SOURCE_PROTO:=git +PKG_SOURCE_VERSION:=740d0102c518cd49f30c5580982b218b480006b1 +PKG_MIRROR_HASH:=2f427d01dba69b1b89d3a081daf08b36fb345d55b9c9462eb358e5b071e2a171 + +include $(INCLUDE_DIR)/package.mk + +# Keep default as ipq806x for branches that does not have subtarget framework +ifeq ($(CONFIG_TARGET_ipq),y) +subtarget:=$(SUBTARGET) +else +subtarget:=$(CONFIG_TARGET_BOARD) +endif + +ifneq (, $(findstring $(subtarget), "ipq807x" "ipq807x_64" "ipq60xx" "ipq60xx_64")) +# DTLS Manager v2.0 for Hawkeye/Cypress + DTLSMGR_DIR:=v2.0 +# IPsec Manager v2.0 for Hawkeye/Cypress + IPSECMGR_DIR:=v2.0 +# KLIPS plugin + IPSECMGR_KLIPS:= $(PKG_BUILD_DIR)/ipsecmgr/$(IPSECMGR_DIR)/plugins/klips/qca-nss-ipsec-klips.ko +else +# DTLS Manager v1.0 for Akronite. + DTLSMGR_DIR:=v1.0 +# IPsec Manager v1.0 for Akronite. + IPSECMGR_DIR:=v1.0 +# KLIPS plugin not needed + IPSECMGR_KLIPS:= +endif + +define KernelPackage/qca-nss-drv-tun6rd + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=Kernel driver for NSS (connection manager) - tun6rd + DEPENDS:=+kmod-qca-nss-drv +kmod-sit +6rd @!LINUX_3_18 + FILES:=$(PKG_BUILD_DIR)/qca-nss-tun6rd.ko + AUTOLOAD:=$(call AutoLoad,60,qca-nss-tun6rd) +endef + +define KernelPackage/qca-nss-drv-tun6rd/Description +Kernel modules for NSS connection manager - Support for 6rd tunnel +endef + +define KernelPackage/qca-nss-drv-dtlsmgr + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=Kernel driver for NSS (connection manager) - dtlsmgr + DEPENDS:=+kmod-qca-nss-drv +kmod-qca-nss-cfi-cryptoapi @!LINUX_3_18 + FILES:=$(PKG_BUILD_DIR)/dtls/$(DTLSMGR_DIR)/qca-nss-dtlsmgr.ko +endef + +define KernelPackage/qca-nss-drv-dtls/Description +Kernel modules for NSS connection manager - Support for DTLS sessions +endef + +define KernelPackage/qca-nss-drv-l2tpv2 + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=Kernel driver for NSS (connection manager) - l2tp + DEPENDS:=+kmod-qca-nss-drv +kmod-ppp +kmod-l2tp @!LINUX_3_18 + FILES:=$(PKG_BUILD_DIR)/l2tp/l2tpv2/qca-nss-l2tpv2.ko + KCONFIG:=CONFIG_L2TP=y + AUTOLOAD:=$(call AutoLoad,51,qca-nss-l2tpv2) +endef + +define KernelPackage/qca-nss-drv-l2tpv2/Description +Kernel modules for NSS connection manager - Support for l2tp tunnel +endef + +define KernelPackage/qca-nss-drv-pptp + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=Kernel driver for NSS (connection manager) - PPTP + DEPENDS:=+kmod-qca-nss-drv +kmod-pptp @!LINUX_3_18 + FILES:=$(PKG_BUILD_DIR)/pptp/qca-nss-pptp.ko + AUTOLOAD:=$(call AutoLoad,51,qca-nss-pptp) +endef + +define KernelPackage/qca-nss-drv-pptp/Description +Kernel modules for NSS connection manager - Support for PPTP tunnel +endef + +define KernelPackage/qca-nss-drv-pppoe + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=Kernel driver for NSS (connection manager) - PPPoE + DEPENDS:=+kmod-qca-nss-drv +kmod-pppoe @!LINUX_3_18 \ + +!(TARGET_ipq_ipq807x_QSDK_256||TARGET_ipq_ipq60xx_QSDK_256):kmod-bonding + FILES:=$(PKG_BUILD_DIR)/pppoe/qca-nss-pppoe.ko + AUTOLOAD:=$(call AutoLoad,51,qca-nss-pppoe) +endef + +define KernelPackage/qca-nss-drv-pppoe/Description +Kernel modules for NSS connection manager - Support for PPPoE +endef + +define KernelPackage/qca-nss-drv-map-t + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=Kernel driver for NSS (connection manager) - MAP-T + DEPENDS:=+kmod-qca-nss-drv +kmod-nat46 @!LINUX_3_18 + FILES:=$(PKG_BUILD_DIR)/map/map-t/qca-nss-map-t.ko + AUTOLOAD:=$(call AutoLoad,51,qca-nss-map-t) +endef + +define KernelPackage/qca-nss-drv-map-t/Description +Kernel modules for NSS connection manager - Support for MAP-T +endef + +define KernelPackage/qca-nss-drv-gre + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=Kernel driver for NSS (connection manager) - GRE + DEPENDS:=@TARGET_ipq_ipq806x||TARGET_ipq806x||TARGET_ipq_ipq807x||TARGET_ipq_ipq807x_64||TARGET_ipq807x||TARGET_ipq807x_64||TARGET_ipq_ipq60xx||TARGET_ipq_ipq60xx_64||TARGET_ipq_ipq50xx||TARGET_ipq_ipq50xx_64 \ + +kmod-qca-nss-drv @!LINUX_3_18 +kmod-gre6 + FILES:=$(PKG_BUILD_DIR)/gre/qca-nss-gre.ko $(PKG_BUILD_DIR)/gre/test/qca-nss-gre-test.ko + AUTOLOAD:=$(call AutoLoad,51,qca-nss-gre) +endef + +define KernelPackage/qca-nss-drv-gre/Description +Kernel modules for NSS connection manager - Support for GRE +endef + +define KernelPackage/qca-nss-drv-tunipip6 + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=Kernel driver for NSS (connection manager) - DS-lite and ipip6 Tunnel + DEPENDS:=+kmod-qca-nss-drv +kmod-iptunnel6 +kmod-ip6-tunnel @!LINUX_3_18 + FILES:=$(PKG_BUILD_DIR)/qca-nss-tunipip6.ko + AUTOLOAD:=$(call AutoLoad,60,qca-nss-tunipip6) +endef + +define KernelPackage/qca-nss-drv-tunipip6/Description +Kernel modules for NSS connection manager +Add support for DS-lite and ipip6 tunnel +endef + +define KernelPackage/qca-nss-drv-profile + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + DEPENDS:=+kmod-qca-nss-drv @!LINUX_3_18 + TITLE:=Profiler for QCA NSS driver (IPQ806x) + FILES:=$(PKG_BUILD_DIR)/profiler/qca-nss-profile-drv.ko +endef + +define KernelPackage/qca-nss-drv-profile/Description +This package contains a NSS driver profiler for QCA chipset +endef + +define KernelPackage/qca-nss-drv-ipsecmgr + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=Kernel driver for NSS (ipsec manager) - ipsecmgr + DEPENDS:=@TARGET_ipq806x||TARGET_ipq_ipq806x||TARGET_ipq_ipq807x||TARGET_ipq_ipq807x_64||TARGET_ipq807x||TARGET_ipq807x_64||TARGET_ipq_ipq60xx||TARGET_ipq_ipq60xx_64 \ + +kmod-qca-nss-drv +kmod-qca-nss-ecm-standard +kmod-qca-nss-cfi-cryptoapi @!LINUX_3_18 +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-l2tpv2),) + DEPENDS+=+kmod-qca-nss-drv-l2tpv2 +endif + FILES:=$(PKG_BUILD_DIR)/ipsecmgr/$(IPSECMGR_DIR)/qca-nss-ipsecmgr.ko $(IPSECMGR_KLIPS) + AUTOLOAD:=$(call AutoLoad,60,qca-nss-ipsecmgr) +endef + +define KernelPackage/qca-nss-drv-ipsecmgr/Description +Kernel module for NSS IPsec offload manager +endef + +define KernelPackage/qca-nss-drv-capwapmgr + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + DEPENDS:=+kmod-qca-nss-drv +kmod-qca-nss-drv-dtlsmgr @!LINUX_3_18 + TITLE:=NSS CAPWAP Manager for QCA NSS driver (IPQ806x) + FILES:=$(PKG_BUILD_DIR)/capwapmgr/qca-nss-capwapmgr.ko +endef + +define KernelPackage/qca-nss-drv-capwapmgr/Description +This package contains a NSS CAPWAP Manager +endef + +define KernelPackage/qca-nss-drv-bridge-mgr + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=Kernel driver for NSS bridge manager + DEPENDS:=@TARGET_ipq_ipq807x||TARGET_ipq_ipq807x_64||TARGET_ipq807x||TARGET_ipq807x_64||TARGET_ipq_ipq60xx||TARGET_ipq_ipq60xx_64 \ + +TARGET_ipq_ipq807x:kmod-qca-nss-drv-vlan-mgr \ + +TARGET_ipq_ipq807x_64:kmod-qca-nss-drv-vlan-mgr \ + +TARGET_ipq807x:kmod-qca-nss-drv-vlan-mgr \ + +TARGET_ipq807x_64:kmod-qca-nss-drv-vlan-mgr \ + +TARGET_ipq_ipq60xx:kmod-qca-nss-drv-vlan-mgr \ + +TARGET_ipq_ipq60xx_64:kmod-qca-nss-drv-vlan-mgr @!LINUX_3_18 \ + +!(TARGET_ipq_ipq807x_QSDK_256||TARGET_ipq_ipq60xx_QSDK_256):kmod-bonding + FILES:=$(PKG_BUILD_DIR)/bridge/qca-nss-bridge-mgr.ko + AUTOLOAD:=$(call AutoLoad,51,qca-nss-bridge-mgr) +endef + +define KernelPackage/qca-nss-drv-bridge-mgr/Description +Kernel modules for NSS bridge manager +endef + +define KernelPackage/qca-nss-drv-vlan-mgr + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=Kernel driver for NSS vlan manager + DEPENDS:=@TARGET_ipq806x||TARGET_ipq807x +kmod-qca-nss-drv @!LINUX_3_18 \ + +!(TARGET_ipq_ipq807x_QSDK_256||TARGET_ipq_ipq60xx_QSDK_256):kmod-bonding + FILES:=$(PKG_BUILD_DIR)/vlan/qca-nss-vlan.ko + AUTOLOAD:=$(call AutoLoad,51,qca-nss-vlan) +endef + +define KernelPackage/qca-nss-drv-vlan-mgr/Description +Kernel modules for NSS vlan manager +endef + +define KernelPackage/qca-nss-drv-qdisc + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Support + TITLE:=Qdisc for configuring shapers in NSS + DEPENDS:=+kmod-qca-nss-drv @!LINUX_3_18 + FILES:=$(PKG_BUILD_DIR)/nss_qdisc/qca-nss-qdisc.ko + KCONFIG:=CONFIG_NET_CLS_ACT=y + AUTOLOAD:=$(call AutoLoad,58,qca-nss-qdisc) +endef + +define KernelPackage/qca-nss-drv-qdisc/Description +Linux qdisc that aids in configuring shapers in the NSS +endef + +define KernelPackage/qca-nss-drv-lag-mgr + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=Kernel driver for NSS LAG manager + DEPENDS:=+kmod-qca-nss-drv @!LINUX_3_18 \ + +TARGET_ipq_ipq807x:kmod-qca-nss-drv-vlan-mgr \ + +TARGET_ipq_ipq807x_64:kmod-qca-nss-drv-vlan-mgr @!LINUX_3_18 \ + +TARGET_ipq807x:kmod-qca-nss-drv-vlan-mgr \ + +TARGET_ipq807x_64:kmod-qca-nss-drv-vlan-mgr @!LINUX_3_18 \ + +TARGET_ipq_ipq60xx:kmod-qca-nss-drv-vlan-mgr @!LINUX_3_18 \ + +TARGET_ipq_ipq60xx_64:kmod-qca-nss-drv-vlan-mgr @!LINUX_3_18 \ + +kmod-bonding + FILES:=$(PKG_BUILD_DIR)/lag/qca-nss-lag-mgr.ko + AUTOLOAD:=$(call AutoLoad,51,qca-nss-lag-mgr) +endef + +define KernelPackage/qca-nss-drv-lag-mgr/Description +Kernel modules for NSS LAG manager +endef + +define KernelPackage/qca-nss-drv-netlink + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + DEPENDS:=@TARGET_ipq807x||TARGET_ipq_ipq807x||TARGET_ipq807x_64||TARGET_ipq_ipq807x_64||TARGET_ipq_ipq60xx||TARGET_ipq_ipq60xx_64||TARGET_ipq_ipq50xx||TARGET_ipq_ipq50xx_64 \ + +kmod-qca-nss-drv @!LINUX_3_18 \ + +PACKAGE_kmod-qca-nss-drv-ipsecmgr:kmod-qca-nss-drv-ipsecmgr \ + +PACKAGE_kmod-qca-nss-drv-dtlsmgr:kmod-qca-nss-drv-dtlsmgr \ + +PACKAGE_kmod-qca-nss-drv-capwapmgr:kmod-qca-nss-drv-capwapmgr @!LINUX_3_18 + TITLE:=NSS NETLINK Manager for QCA NSS driver + FILES:=$(PKG_BUILD_DIR)/netlink/qca-nss-netlink.ko +endef + +define KernelPackage/qca-nss-drv-netlink/Description +Kernel module for NSS netlink manager +endef + +define KernelPackage/qca-nss-drv-ovpn-mgr + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=Kernel driver for NSS OpenVPN manager + DEPENDS:=+kmod-qca-nss-drv +kmod-qca-nss-cfi-cryptoapi +kmod-tun +kmod-ipt-conntrack @!LINUX_3_18 \ + @TARGET_ipq_ipq807x||TARGET_ipq_ipq807x_64||TARGET_ipq_ipq60xx||TARGET_ipq_ipq60xx_64 + FILES:=$(PKG_BUILD_DIR)/openvpn/src/qca-nss-ovpn-mgr.ko +endef + +define KernelPackage/qca-nss-drv-ovpn-mgr/Description +Kernel module for NSS OpenVPN manager +endef + +define KernelPackage/qca-nss-drv-ovpn-link + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=Kernel driver for interfacing NSS OpenVPN manager with ECM + DEPENDS:=+kmod-qca-nss-drv-ovpn-mgr +@PACKAGE_kmod-qca-nss-ecm-premium @!LINUX_3_18 \ + @TARGET_ipq_ipq807x||TARGET_ipq_ipq807x_64||TARGET_ipq_ipq60xx||TARGET_ipq_ipq60xx_64 + FILES:=$(PKG_BUILD_DIR)/openvpn/plugins/qca-nss-ovpn-link.ko +endef + +define KernelPackage/qca-nss-drv-ovpn-link/Description +This module registers with ECM and communicates with NSS OpenVPN manager for supporting OpenVPN offload. +endef + +define KernelPackage/qca-nss-drv-pvxlanmgr + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + DEPENDS:=+kmod-qca-nss-drv @!LINUX_3_18 + TITLE:=NSS PVXLAN Manager for QCA NSS driver + FILES:=$(PKG_BUILD_DIR)/pvxlanmgr/qca-nss-pvxlanmgr.ko +endef + +define KernelPackage/qca-nss-drv-pvxlanmgr/Description +Kernel module for managing NSS PVxLAN +endef + +define Build/InstallDev/qca-nss-clients + $(INSTALL_DIR) $(1)/usr/include/qca-nss-clients + $(CP) $(PKG_BUILD_DIR)/netlink/include/* $(1)/usr/include/qca-nss-clients/ + $(CP) $(PKG_BUILD_DIR)/exports/* $(1)/usr/include/qca-nss-clients/ +endef + +define Build/InstallDev + $(call Build/InstallDev/qca-nss-clients,$(1)) +endef + +define KernelPackage/qca-nss-drv-ovpn-mgr/install + $(INSTALL_DIR) $(1)/etc/init.d + $(INSTALL_BIN) ./files/qca-nss-ovpn.init $(1)/etc/init.d/qca-nss-ovpn +endef + +define KernelPackage/qca-nss-drv-ipsecmgr/install + $(INSTALL_DIR) $(1)/etc/init.d + $(INSTALL_BIN) ./files/qca-nss-ipsec $(1)/etc/init.d/qca-nss-ipsec +endef + + +EXTRA_CFLAGS+= \ + -I$(STAGING_DIR)/usr/include/qca-nss-drv \ + -I$(STAGING_DIR)/usr/include/qca-nss-crypto \ + -I$(STAGING_DIR)/usr/include/qca-nss-cfi \ + -I$(STAGING_DIR)/usr/include/qca-nss-gmac \ + -I$(STAGING_DIR)/usr/include/qca-nss-ecm \ + -I$(STAGING_DIR)/usr/include/qca-ssdk \ + -I$(STAGING_DIR)/usr/include/qca-ssdk/fal \ + -I$(STAGING_DIR)/usr/include/nat46 + +# Build individual packages if selected +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-profile),) +MAKE_OPTS+=profile=y +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-capwapmgr),) +MAKE_OPTS+=capwapmgr=y +EXTRA_CFLAGS += -DNSS_CAPWAPMGR_ONE_NETDEV +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-tun6rd),) +MAKE_OPTS+=tun6rd=m +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-dtlsmgr),) +MAKE_OPTS+=dtlsmgr=y +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-l2tpv2),) +MAKE_OPTS+=l2tpv2=y +EXTRA_CFLAGS += -DNSS_L2TPV2_ENABLED +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-pptp),) +MAKE_OPTS+=pptp=y +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-map-t),) +MAKE_OPTS+=map-t=y +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-tunipip6),) +MAKE_OPTS+=tunipip6=m +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-qdisc),) +MAKE_OPTS+=qdisc=y +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-ipsecmgr),) +EXTRA_CFLAGS+= -I$(PKG_BUILD_DIR)/exports \ + -I$(STAGING_DIR)/usr/include/qca-nss-ecm +MAKE_OPTS+=ipsecmgr=y +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-bridge-mgr),) +MAKE_OPTS+=bridge-mgr=y +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-vlan-mgr),) +MAKE_OPTS+=vlan-mgr=y +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-lag-mgr),) +MAKE_OPTS+=lag-mgr=y +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-gre),) +EXTRA_CFLAGS+= -I$(PKG_BUILD_DIR)/exports +MAKE_OPTS+=gre=y +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-pppoe),) +MAKE_OPTS+=pppoe=y +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-netlink),) +MAKE_OPTS+=netlink=y +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-ovpn-mgr),) +MAKE_OPTS+=ovpn-mgr=y +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-ovpn-link),) +MAKE_OPTS+=ovpn-link=y +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-pvxlanmgr),) +MAKE_OPTS+=pvxlanmgr=y +endif + +define Build/Compile + $(MAKE) $(PKG_JOBS) -C "$(LINUX_DIR)" $(strip $(MAKE_OPTS)) \ + $(KERNEL_MAKE_FLAGS) \ + $(PKG_MAKE_FLAGS) \ + M="$(PKG_BUILD_DIR)" \ + EXTRA_CFLAGS="$(EXTRA_CFLAGS)" \ + SoC="$(subtarget)" \ + DTLSMGR_DIR="$(DTLSMGR_DIR)" \ + IPSECMGR_DIR="$(IPSECMGR_DIR)" \ + modules +endef + +$(eval $(call KernelPackage,qca-nss-drv-profile)) +$(eval $(call KernelPackage,qca-nss-drv-capwapmgr)) +$(eval $(call KernelPackage,qca-nss-drv-tun6rd)) +$(eval $(call KernelPackage,qca-nss-drv-dtlsmgr)) +$(eval $(call KernelPackage,qca-nss-drv-l2tpv2)) +$(eval $(call KernelPackage,qca-nss-drv-pptp)) +$(eval $(call KernelPackage,qca-nss-drv-pppoe)) +$(eval $(call KernelPackage,qca-nss-drv-map-t)) +$(eval $(call KernelPackage,qca-nss-drv-tunipip6)) +$(eval $(call KernelPackage,qca-nss-drv-qdisc)) +$(eval $(call KernelPackage,qca-nss-drv-netlink)) +$(eval $(call KernelPackage,qca-nss-drv-ipsecmgr)) +$(eval $(call KernelPackage,qca-nss-drv-bridge-mgr)) +$(eval $(call KernelPackage,qca-nss-drv-vlan-mgr)) +$(eval $(call KernelPackage,qca-nss-drv-lag-mgr)) +$(eval $(call KernelPackage,qca-nss-drv-gre)) +$(eval $(call KernelPackage,qca-nss-drv-ovpn-mgr)) +$(eval $(call KernelPackage,qca-nss-drv-ovpn-link)) +$(eval $(call KernelPackage,qca-nss-drv-pvxlanmgr)) diff --git a/qaa/nss/qca-nss-clients/files/qca-nss-ipsec b/qaa/nss/qca-nss-clients/files/qca-nss-ipsec new file mode 100644 index 000000000..bb202e8e7 --- /dev/null +++ b/qaa/nss/qca-nss-clients/files/qca-nss-ipsec @@ -0,0 +1,92 @@ +#!/bin/sh /etc/rc.common +# +# Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +NSS_IPSEC_LOG_FILE=/tmp/.nss_ipsec_log +NSS_IPSEC_LOG_STR_ECM="ECM_Loaded" + +ecm_load () { + if [ ! -d /sys/module/ecm ]; then + /etc/init.d/qca-nss-ecm start + if [ -d /sys/module/ecm ]; then + echo ${NSS_IPSEC_LOG_STR_ECM} >> ${NSS_IPSEC_LOG_FILE} + fi + fi +} + +ecm_unload () { + if [ -f /tmp/.nss_ipsec_log ]; then + str=`grep ${NSS_IPSEC_LOG_STR_ECM} ${NSS_IPSEC_LOG_FILE}` + if [[ $str == ${NSS_IPSEC_LOG_STR_ECM} ]]; then + /etc/init.d/qca-nss-ecm stop + `sed 's/${NSS_IPSEC_LOG_STR_ECM}/ /g' $NSS_IPSEC_LOG_FILE > $NSS_IPSEC_LOG_FILE` + fi + fi +} + +ecm_disable() { + + if [ ! -d /sys/module/ecm ]; then + return; + fi + + echo 1 > /sys/kernel/debug/ecm/front_end_ipv4_stop + echo 1 > /sys/kernel/debug/ecm/front_end_ipv6_stop + echo 1 > /sys/kernel/debug/ecm/ecm_db/defunct_all + sleep 2 +} + +ecm_enable() { + if [ ! -d /sys/module/ecm ]; then + return; + fi + + echo 0 > /sys/kernel/debug/ecm/ecm_db/defunct_all + echo 0 > /sys/kernel/debug/ecm/front_end_ipv4_stop + echo 0 > /sys/kernel/debug/ecm/front_end_ipv6_stop +} + +start() { + ecm_load + + local kernel_version=$(uname -r) + + insmod /lib/modules/${kernel_version}/qca-nss-ipsec-klips.ko + if [ "$?" -gt 0 ]; then + echo "Failed to load plugin. Please start ecm if not done already" + ecm_enable + return + fi + + /etc/init.d/ipsec start + sleep 2 + ipsec eroute + + ecm_enable +} + +stop() { + ecm_disable + + /etc/init.d/ipsec stop + rmmod qca-nss-ipsec-klips + + ecm_unload +} + +restart() { + stop + start +} diff --git a/qaa/nss/qca-nss-clients/files/qca-nss-mirred.init b/qaa/nss/qca-nss-clients/files/qca-nss-mirred.init new file mode 100644 index 000000000..1f931f090 --- /dev/null +++ b/qaa/nss/qca-nss-clients/files/qca-nss-mirred.init @@ -0,0 +1,28 @@ +#!/bin/sh /etc/rc.common + +########################################################################### +# Copyright (c) 2019, The Linux Foundation. All rights reserved. +# Permission to use, copy, modify, and/or distribute this software for +# any purpose with or without fee is hereby granted, provided that the +# above copyright notice and this permission notice appear in all copies. +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT +# OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +########################################################################### + +restart() { + rmmod act_nssmirred.ko + insmod act_nssmirred.ko +} + +start() { + insmod act_nssmirred.ko +} + +stop() { + rmmod act_nssmirred.ko +} diff --git a/qaa/nss/qca-nss-clients/files/qca-nss-ovpn.init b/qaa/nss/qca-nss-clients/files/qca-nss-ovpn.init new file mode 100644 index 000000000..622e295ee --- /dev/null +++ b/qaa/nss/qca-nss-clients/files/qca-nss-ovpn.init @@ -0,0 +1,69 @@ +#!/bin/sh /etc/rc.common + +########################################################################### +# Copyright (c) 2019, The Linux Foundation. All rights reserved. +# Permission to use, copy, modify, and/or distribute this software for +# any purpose with or without fee is hereby granted, provided that the +# above copyright notice and this permission notice appear in all copies. +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT +# OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +########################################################################### + +ecm_disable() { + if [ ! -d /sys/module/ecm ]; then + return + fi + + echo 1 > /sys/kernel/debug/ecm/front_end_ipv4_stop + echo 1 > /sys/kernel/debug/ecm/front_end_ipv6_stop + echo 1 > /sys/kernel/debug/ecm/ecm_db/defunct_all + sleep 2 +} + +ecm_enable() { + if [ ! -d /sys/module/ecm ]; then + return + fi + + echo 0 > /sys/kernel/debug/ecm/ecm_db/defunct_all + echo 0 > /sys/kernel/debug/ecm/front_end_ipv4_stop + echo 0 > /sys/kernel/debug/ecm/front_end_ipv6_stop +} + +restart() { + ecm_disable + + /etc/init.d/openvpn stop + rmmod qca-nss-ovpn-link + rmmod qca-nss-ovpn-mgr + + insmod qca-nss-ovpn-mgr + insmod qca-nss-ovpn-link + + if [ "$?" -gt 0 ]; then + echo "Failed to load plugin. Please start ecm if not done already" + ecm_enable + return + fi + + ecm_enable +} + +start() { + restart +} + +stop() { + ecm_disable + + /etc/init.d/openvpn stop + rmmod qca-nss-ovpn-link + rmmod qca-nss-ovpn-mgr + + ecm_enable +} diff --git a/qaa/nss/qca-nss-clients/patches/100-kernel-5.4-support-qdisc.patch b/qaa/nss/qca-nss-clients/patches/100-kernel-5.4-support-qdisc.patch new file mode 100644 index 000000000..0ec8d766e --- /dev/null +++ b/qaa/nss/qca-nss-clients/patches/100-kernel-5.4-support-qdisc.patch @@ -0,0 +1,1145 @@ +--- a/nss_qdisc/nss_qdisc.h ++++ b/nss_qdisc/nss_qdisc.h +@@ -338,7 +340,7 @@ extern void nss_qdisc_destroy(struct nss + * Initializes a shaper in NSS, based on the position of this qdisc (child or root) + * and if its a normal interface or a bridge interface. + */ +-extern int nss_qdisc_init(struct Qdisc *sch, struct nss_qdisc *nq, nss_shaper_node_type_t type, uint32_t classid, uint32_t accel_mode); ++extern int nss_qdisc_init(struct Qdisc *sch, struct netlink_ext_ack *extack, struct nss_qdisc *nq, nss_shaper_node_type_t type, uint32_t classid, uint32_t accel_mode); + + /* + * nss_qdisc_start_basic_stats_polling() +--- a/nss_qdisc/nss_bf.c ++++ b/nss_qdisc/nss_bf.c +@@ -69,7 +69,7 @@ static inline struct nss_bf_class_data * + * Configures a new class. + */ + static int nss_bf_change_class(struct Qdisc *sch, u32 classid, u32 parentid, +- struct nlattr **tca, unsigned long *arg) ++ struct nlattr **tca, unsigned long *arg, struct netlink_ext_ack *extack) + { + struct nss_bf_sched_data *q = qdisc_priv(sch); + struct nss_bf_class_data *cl = (struct nss_bf_class_data *)*arg; +@@ -121,7 +121,7 @@ static int nss_bf_change_class(struct Qd + * that is registered to Linux. Therefore we initialize the NSSBF_GROUP shaper + * here. + */ +- if (nss_qdisc_init(sch, &cl->nq, NSS_SHAPER_NODE_TYPE_BF_GROUP, classid, accel_mode) < 0) { ++ if (nss_qdisc_init(sch, extack, &cl->nq, NSS_SHAPER_NODE_TYPE_BF_GROUP, classid, accel_mode) < 0) { + nss_qdisc_error("Nss init for class %u failed\n", classid); + kfree(cl); + return -EINVAL; +@@ -260,7 +260,7 @@ static void nss_bf_destroy_class(struct + /* + * And now we destroy the child. + */ +- qdisc_destroy(cl->qdisc); ++ qdisc_put(cl->qdisc); + + /* + * Stop the stats polling timer and free class +@@ -325,7 +325,7 @@ static int nss_bf_delete_class(struct Qd + * Replaces the qdisc attached to the provided class. + */ + static int nss_bf_graft_class(struct Qdisc *sch, unsigned long arg, struct Qdisc *new, +- struct Qdisc **old) ++ struct Qdisc **old, struct netlink_ext_ack *extack) + { + struct nss_bf_sched_data *q = qdisc_priv(sch); + struct nss_bf_class_data *cl = (struct nss_bf_class_data *)arg; +@@ -432,24 +432,6 @@ static unsigned long nss_bf_get_class(st + } + + /* +- * nss_bf_put_class() +- * Reduces reference count for this class. +- */ +-static void nss_bf_put_class(struct Qdisc *sch, unsigned long arg) +-{ +- struct nss_bf_class_data *cl = (struct nss_bf_class_data *)arg; +- nss_qdisc_info("bf put class for %p\n", cl); +- +- /* +- * We are safe to destroy the qdisc if the reference count +- * goes down to 0. +- */ +- if (atomic_sub_return(1, &cl->nq.refcnt) == 0) { +- nss_bf_destroy_class(sch, cl); +- } +-} +- +-/* + * nss_bf_dump_class() + * Dumps all configurable parameters pertaining to this class. + */ +@@ -538,7 +520,7 @@ static void nss_bf_walk(struct Qdisc *sc + * nss_bf_change_qdisc() + * Can be used to configure a nssbf qdisc. + */ +-static int nss_bf_change_qdisc(struct Qdisc *sch, struct nlattr *opt) ++static int nss_bf_change_qdisc(struct Qdisc *sch, struct nlattr *opt, struct netlink_ext_ack *extack) + { + struct nss_bf_sched_data *q = qdisc_priv(sch); + struct tc_nssbf_qopt *qopt; +@@ -684,7 +666,7 @@ static void nss_bf_destroy_qdisc(struct + * nss_bf_init_qdisc() + * Initializes the nssbf qdisc. + */ +-static int nss_bf_init_qdisc(struct Qdisc *sch, struct nlattr *opt) ++static int nss_bf_init_qdisc(struct Qdisc *sch, struct nlattr *opt, struct netlink_ext_ack *extack) + { + struct nss_bf_sched_data *q = qdisc_priv(sch); + struct tc_nssbf_qopt *qopt; +@@ -720,7 +702,7 @@ static int nss_bf_init_qdisc(struct Qdis + /* + * Initialize the NSSBF shaper in NSS + */ +- if (nss_qdisc_init(sch, &q->nq, NSS_SHAPER_NODE_TYPE_BF, 0, accel_mode) < 0) { ++ if (nss_qdisc_init(sch, extack, &q->nq, NSS_SHAPER_NODE_TYPE_BF, 0, accel_mode) < 0) { + return -EINVAL; + } + +@@ -729,7 +711,7 @@ static int nss_bf_init_qdisc(struct Qdis + /* + * Tune nss_bf parameters. + */ +- if (nss_bf_change_qdisc(sch, opt) < 0) { ++ if (nss_bf_change_qdisc(sch, opt, NULL) < 0) { + nss_qdisc_destroy(&q->nq); + return -EINVAL; + } +@@ -772,7 +754,7 @@ nla_put_failure: + * nss_bf_enqueue() + * Enqueues a skb to nssbf qdisc. + */ +-static int nss_bf_enqueue(struct sk_buff *skb, struct Qdisc *sch) ++static int nss_bf_enqueue(struct sk_buff *skb, struct Qdisc *sch, struct sk_buff **to_free) + { + return nss_qdisc_enqueue(skb, sch); + } +@@ -787,18 +769,6 @@ static struct sk_buff *nss_bf_dequeue(st + } + + /* +- * nss_bf_drop() +- * Drops a single skb from linux queue, if not empty. +- * +- * Does not drop packets that are queued in the NSS. +- */ +-static unsigned int nss_bf_drop(struct Qdisc *sch) +-{ +- printk("In bf drop\n"); +- return nss_qdisc_drop(sch); +-} +- +-/* + * Registration structure for nssbf class + */ + const struct Qdisc_class_ops nss_bf_class_ops = { +@@ -807,9 +777,8 @@ const struct Qdisc_class_ops nss_bf_clas + .graft = nss_bf_graft_class, + .leaf = nss_bf_leaf_class, + .qlen_notify = nss_bf_qlen_notify, +- .get = nss_bf_get_class, +- .put = nss_bf_put_class, ++ .find = nss_bf_get_class, + .dump = nss_bf_dump_class, + .dump_stats = nss_bf_dump_class_stats, + .walk = nss_bf_walk + }; +@@ -830,7 +798,6 @@ struct Qdisc_ops nss_bf_qdisc_ops __read + .enqueue = nss_bf_enqueue, + .dequeue = nss_bf_dequeue, + .peek = qdisc_peek_dequeued, +- .drop = nss_bf_drop, + .cl_ops = &nss_bf_class_ops, + .priv_size = sizeof(struct nss_bf_sched_data), + .owner = THIS_MODULE +--- a/nss_qdisc/nss_blackhole.c ++++ b/nss_qdisc/nss_blackhole.c +@@ -35,7 +35,7 @@ static struct nla_policy nss_blackhole_p + * nss_blackhole_enqueue() + * Enqueue API for nss blackhole qdisc. + */ +-static int nss_blackhole_enqueue(struct sk_buff *skb, struct Qdisc *sch) ++static int nss_blackhole_enqueue(struct sk_buff *skb, struct Qdisc *sch, struct sk_buff **to_free) + { + return nss_qdisc_enqueue(skb, sch); + } +@@ -50,18 +50,6 @@ static struct sk_buff *nss_blackhole_deq + } + + /* +- * nss_blackhole_drop() +- * The following function drops a packet from HLOS queue. +- * +- * Note, this does not drop packets from queues in the NSS. We do not support that. +- */ +-static unsigned int nss_blackhole_drop(struct Qdisc *sch) +-{ +- nss_qdisc_info("qdisc %x dropping\n", sch->handle); +- return nss_qdisc_drop(sch); +-} +- +-/* + * nss_blackhole_reset() + * Resets the nss blackhole qdisc. + */ +@@ -92,7 +80,7 @@ static void nss_blackhole_destroy(struct + * nss_blackhole_change() + * Function call used to configure the parameters of the nss blackhole qdisc. + */ +-static int nss_blackhole_change(struct Qdisc *sch, struct nlattr *opt) ++static int nss_blackhole_change(struct Qdisc *sch, struct nlattr *opt, struct netlink_ext_ack *extack) + { + struct nss_blackhole_sched_data *q; + struct tc_nssblackhole_qopt *qopt; +@@ -154,7 +142,7 @@ static int nss_blackhole_change(struct Q + * nss_blackhole_init() + * Initializes a nss blackhole qdisc. + */ +-static int nss_blackhole_init(struct Qdisc *sch, struct nlattr *opt) ++static int nss_blackhole_init(struct Qdisc *sch, struct nlattr *opt, struct netlink_ext_ack *extack) + { + struct nss_qdisc *nq = qdisc_priv(sch); + struct tc_nssblackhole_qopt *qopt; +@@ -176,12 +164,12 @@ static int nss_blackhole_init(struct Qdi + nss_qdisc_info("qdisc %x initializing\n", sch->handle); + nss_blackhole_reset(sch); + +- if (nss_qdisc_init(sch, nq, NSS_SHAPER_NODE_TYPE_FIFO, 0, accel_mode) < 0) { ++ if (nss_qdisc_init(sch, extack, nq, NSS_SHAPER_NODE_TYPE_FIFO, 0, accel_mode) < 0) { + return -EINVAL; + } + + nss_qdisc_info("qdisc %x initialized with parent %x\n", sch->handle, sch->parent); +- if (nss_blackhole_change(sch, opt) < 0) { ++ if (nss_blackhole_change(sch, opt, NULL) < 0) { + nss_qdisc_destroy(nq); + return -EINVAL; + } +@@ -251,7 +239,6 @@ struct Qdisc_ops nss_blackhole_qdisc_ops + .enqueue = nss_blackhole_enqueue, + .dequeue = nss_blackhole_dequeue, + .peek = nss_blackhole_peek, +- .drop = nss_blackhole_drop, + .init = nss_blackhole_init, + .reset = nss_blackhole_reset, + .destroy = nss_blackhole_destroy, +--- a/nss_qdisc/nss_codel.c ++++ b/nss_qdisc/nss_codel.c +@@ -76,7 +76,7 @@ static struct nla_policy nss_codel_polic + * nss_codel_enqueue() + * Enqueue a packet into nss_codel queue in NSS firmware (bounce). + */ +-static int nss_codel_enqueue(struct sk_buff *skb, struct Qdisc *sch) ++static int nss_codel_enqueue(struct sk_buff *skb, struct Qdisc *sch, struct sk_buff **to_free) + { + return nss_qdisc_enqueue(skb, sch); + } +@@ -91,17 +91,6 @@ static struct sk_buff *nss_codel_dequeue + } + + /* +- * nss_codel_drop() +- * Drops a packet from the bounce complete queue. +- * +- * Note: this does not drop packets from the NSS queues. +- */ +-static unsigned int nss_codel_drop(struct Qdisc *sch) +-{ +- return nss_qdisc_drop(sch); +-} +- +-/* + * nss_codel_reset() + * Resets nss_codel qdisc. + */ +@@ -234,7 +223,7 @@ static int nss_codel_mem_sz_get(struct Q + * nss_codel_change() + * Used to configure the nss_codel queue in NSS firmware. + */ +-static int nss_codel_change(struct Qdisc *sch, struct nlattr *opt) ++static int nss_codel_change(struct Qdisc *sch, struct nlattr *opt, struct netlink_ext_ack *extack) + { + struct nss_codel_sched_data *q = qdisc_priv(sch); + struct tc_nsscodel_qopt *qopt; +@@ -381,7 +370,7 @@ fail: + * nss_codel_init() + * Initializes the nss_codel qdisc. + */ +-static int nss_codel_init(struct Qdisc *sch, struct nlattr *opt) ++static int nss_codel_init(struct Qdisc *sch, struct nlattr *opt, struct netlink_ext_ack *extack) + { + struct nss_qdisc *nq = qdisc_priv(sch); + struct tc_nsscodel_qopt *qopt; +@@ -404,7 +393,7 @@ static int nss_codel_init(struct Qdisc * + nss_qdisc_register_configure_callback(nq, nss_codel_configure_callback); + nss_qdisc_register_stats_callback(nq, nss_codel_stats_callback); + +- if (nss_qdisc_init(sch, nq, NSS_SHAPER_NODE_TYPE_CODEL, 0, qopt->accel_mode) < 0) { ++ if (nss_qdisc_init(sch, extack, nq, NSS_SHAPER_NODE_TYPE_CODEL, 0, qopt->accel_mode) < 0) { + return -EINVAL; + } + +@@ -412,7 +401,7 @@ static int nss_codel_init(struct Qdisc * + return -EINVAL; + } + +- if (nss_codel_change(sch, opt) < 0) { ++ if (nss_codel_change(sch, opt, NULL) < 0) { + nss_qdisc_destroy(nq); + return -EINVAL; + } +@@ -511,7 +500,6 @@ struct Qdisc_ops nss_codel_qdisc_ops __r + .enqueue = nss_codel_enqueue, + .dequeue = nss_codel_dequeue, + .peek = nss_codel_peek, +- .drop = nss_codel_drop, + .init = nss_codel_init, + .reset = nss_codel_reset, + .destroy = nss_codel_destroy, +@@ -530,7 +518,6 @@ struct Qdisc_ops nss_fq_codel_qdisc_ops + .enqueue = nss_codel_enqueue, + .dequeue = nss_codel_dequeue, + .peek = nss_codel_peek, +- .drop = nss_codel_drop, + .init = nss_codel_init, + .reset = nss_codel_reset, + .destroy = nss_codel_destroy, +--- a/nss_qdisc/nss_fifo.c ++++ b/nss_qdisc/nss_fifo.c +@@ -29,7 +29,7 @@ static struct nla_policy nss_fifo_policy + [TCA_NSSFIFO_PARMS] = { .len = sizeof(struct tc_nssfifo_qopt) }, + }; + +-static int nss_fifo_enqueue(struct sk_buff *skb, struct Qdisc *sch) ++static int nss_fifo_enqueue(struct sk_buff *skb, struct Qdisc *sch, struct sk_buff **to_free) + { + return nss_qdisc_enqueue(skb, sch); + } +@@ -39,12 +39,6 @@ static struct sk_buff *nss_fifo_dequeue( + return nss_qdisc_dequeue(sch); + } + +-static unsigned int nss_fifo_drop(struct Qdisc *sch) +-{ +- nss_qdisc_info("nss_fifo dropping"); +- return nss_qdisc_drop(sch); +-} +- + static void nss_fifo_reset(struct Qdisc *sch) + { + nss_qdisc_info("nss_fifo resetting!"); +@@ -158,7 +152,7 @@ fail: + } + #endif + +-static int nss_fifo_change(struct Qdisc *sch, struct nlattr *opt) ++static int nss_fifo_change(struct Qdisc *sch, struct nlattr *opt, struct netlink_ext_ack *extack) + { + struct nss_fifo_sched_data *q = qdisc_priv(sch); + struct nss_qdisc *nq = &q->nq; +@@ -208,7 +202,7 @@ static int nss_fifo_change(struct Qdisc + return 0; + } + +-static int nss_fifo_init(struct Qdisc *sch, struct nlattr *opt) ++static int nss_fifo_init(struct Qdisc *sch, struct nlattr *opt, struct netlink_ext_ack *extack) + { + struct nss_qdisc *nq = qdisc_priv(sch); + struct tc_nssfifo_qopt *qopt; +@@ -226,13 +220,13 @@ static int nss_fifo_init(struct Qdisc *s + return -EINVAL; + } + +- if (nss_qdisc_init(sch, nq, NSS_SHAPER_NODE_TYPE_FIFO, 0, qopt->accel_mode) < 0) { ++ if (nss_qdisc_init(sch, extack, nq, NSS_SHAPER_NODE_TYPE_FIFO, 0, qopt->accel_mode) < 0) { + nss_qdisc_warning("Fifo %x init failed", sch->handle); + return -EINVAL; + } + + nss_qdisc_info("NSS fifo initialized - handle %x parent %x\n", sch->handle, sch->parent); +- if (nss_fifo_change(sch, opt) < 0) { ++ if (nss_fifo_change(sch, opt, NULL) < 0) { + nss_qdisc_destroy(nq); + return -EINVAL; + } +@@ -290,7 +284,6 @@ struct Qdisc_ops nss_pfifo_qdisc_ops __r + .enqueue = nss_fifo_enqueue, + .dequeue = nss_fifo_dequeue, + .peek = nss_fifo_peek, +- .drop = nss_fifo_drop, + .init = nss_fifo_init, + .reset = nss_fifo_reset, + .destroy = nss_fifo_destroy, +@@ -305,7 +298,6 @@ struct Qdisc_ops nss_bfifo_qdisc_ops __r + .enqueue = nss_fifo_enqueue, + .dequeue = nss_fifo_dequeue, + .peek = nss_fifo_peek, +- .drop = nss_fifo_drop, + .init = nss_fifo_init, + .reset = nss_fifo_reset, + .destroy = nss_fifo_destroy, +--- a/nss_qdisc/nss_htb.c ++++ b/nss_qdisc/nss_htb.c +@@ -267,7 +267,7 @@ static int nss_htb_ppe_change_class(stru + * Configures a new class. + */ + static int nss_htb_change_class(struct Qdisc *sch, u32 classid, u32 parentid, +- struct nlattr **tca, unsigned long *arg) ++ struct nlattr **tca, unsigned long *arg, struct netlink_ext_ack *extack) + { + struct nss_htb_sched_data *q = qdisc_priv(sch); + struct nss_htb_class_data *cl = (struct nss_htb_class_data *)*arg; +@@ -332,7 +332,7 @@ static int nss_htb_change_class(struct Q + * here. + */ + cl->nq.parent = nq_parent; +- if (nss_qdisc_init(sch, &cl->nq, NSS_SHAPER_NODE_TYPE_HTB_GROUP, classid, accel_mode) < 0) { ++ if (nss_qdisc_init(sch, extack, &cl->nq, NSS_SHAPER_NODE_TYPE_HTB_GROUP, classid, accel_mode) < 0) { + nss_qdisc_error("nss_init for htb class %x failed\n", classid); + goto failure; + } +@@ -478,7 +478,7 @@ static void nss_htb_destroy_class(struct + /* + * And now we destroy the child. + */ +- qdisc_destroy(cl->qdisc); ++ qdisc_put(cl->qdisc); + + /* + * Stop the stats polling timer and free class +@@ -577,7 +577,8 @@ static int nss_htb_delete_class(struct Q + * nss_htb_graft_class() + * Replaces the qdisc attached to the provided class. + */ +-static int nss_htb_graft_class(struct Qdisc *sch, unsigned long arg, struct Qdisc *new, struct Qdisc **old) ++static int nss_htb_graft_class(struct Qdisc *sch, unsigned long arg, struct Qdisc *new, struct Qdisc **old, ++ struct netlink_ext_ack *extack) + { + struct nss_htb_class_data *cl = (struct nss_htb_class_data *)arg; + struct nss_if_msg nim_detach; +@@ -682,25 +683,6 @@ static unsigned long nss_htb_get_class(s + } + + /* +- * nss_htb_put_class() +- * Reduces reference count for this class. +- */ +-static void nss_htb_put_class(struct Qdisc *sch, unsigned long arg) +-{ +- struct nss_htb_class_data *cl = (struct nss_htb_class_data *)arg; +- nss_qdisc_trace("executing put on htb class %x in qdisc %x\n", +- cl->nq.qos_tag, sch->handle); +- +- /* +- * We are safe to destroy the qdisc if the reference count +- * goes down to 0. +- */ +- if (atomic_sub_return(1, &cl->nq.refcnt) == 0) { +- nss_htb_destroy_class(sch, cl); +- } +-} +- +-/* + * nss_htb_dump_class() + * Dumps all configurable parameters pertaining to this class. + */ +@@ -795,7 +777,7 @@ static void nss_htb_walk(struct Qdisc *s + * nss_htb_change_qdisc() + * Can be used to configure a htb qdisc. + */ +-static int nss_htb_change_qdisc(struct Qdisc *sch, struct nlattr *opt) ++static int nss_htb_change_qdisc(struct Qdisc *sch, struct nlattr *opt, struct netlink_ext_ack *extack) + { + struct nss_htb_sched_data *q = qdisc_priv(sch); + struct tc_nsshtb_qopt *qopt; +@@ -945,7 +927,7 @@ static void nss_htb_destroy_qdisc(struct + * nss_htb_init_qdisc() + * Initializes the htb qdisc. + */ +-static int nss_htb_init_qdisc(struct Qdisc *sch, struct nlattr *opt) ++static int nss_htb_init_qdisc(struct Qdisc *sch, struct nlattr *opt,struct netlink_ext_ack *extack) + { + struct nss_htb_sched_data *q = qdisc_priv(sch); + struct tc_nsshtb_qopt *qopt; +@@ -977,7 +959,7 @@ static int nss_htb_init_qdisc(struct Qdi + /* + * Initialize the NSSHTB shaper in NSS + */ +- if (nss_qdisc_init(sch, &q->nq, NSS_SHAPER_NODE_TYPE_HTB, 0, accel_mode) < 0) { ++ if (nss_qdisc_init(sch, extack, &q->nq, NSS_SHAPER_NODE_TYPE_HTB, 0, accel_mode) < 0) { + nss_qdisc_error("failed to initialize htb qdisc %x in nss", sch->handle); + return -EINVAL; + } +@@ -987,7 +969,7 @@ static int nss_htb_init_qdisc(struct Qdi + /* + * Tune HTB parameters + */ +- if (nss_htb_change_qdisc(sch, opt) < 0) { ++ if (nss_htb_change_qdisc(sch, opt, NULL) < 0) { + nss_qdisc_destroy(&q->nq); + return -EINVAL; + } +@@ -1032,7 +1014,7 @@ static int nss_htb_dump_qdisc(struct Qdi + * nss_htb_enqueue() + * Enqueues a skb to htb qdisc. + */ +-static int nss_htb_enqueue(struct sk_buff *skb, struct Qdisc *sch) ++static int nss_htb_enqueue(struct sk_buff *skb, struct Qdisc *sch, struct sk_buff **to_free) + { + return nss_qdisc_enqueue(skb, sch); + } +@@ -1047,18 +1029,6 @@ static struct sk_buff *nss_htb_dequeue(s + } + + /* +- * nss_htb_drop() +- * Drops a single skb from linux queue, if not empty. +- * +- * Does not drop packets that are queued in the NSS. +- */ +-static unsigned int nss_htb_drop(struct Qdisc *sch) +-{ +- nss_qdisc_trace("drop called on htb qdisc %x\n", sch->handle); +- return nss_qdisc_drop(sch); +-} +- +-/* + * Registration structure for htb class + */ + const struct Qdisc_class_ops nss_htb_class_ops = { +@@ -1067,9 +1037,8 @@ const struct Qdisc_class_ops nss_htb_cla + .graft = nss_htb_graft_class, + .leaf = nss_htb_leaf_class, + .qlen_notify = nss_htb_qlen_notify, +- .get = nss_htb_get_class, +- .put = nss_htb_put_class, ++ .find = nss_htb_get_class, + .dump = nss_htb_dump_class, + .dump_stats = nss_htb_dump_class_stats, + .walk = nss_htb_walk + }; +@@ -1090,7 +1058,6 @@ struct Qdisc_ops nss_htb_qdisc_ops __rea + .enqueue = nss_htb_enqueue, + .dequeue = nss_htb_dequeue, + .peek = qdisc_peek_dequeued, +- .drop = nss_htb_drop, + .cl_ops = &nss_htb_class_ops, + .priv_size = sizeof(struct nss_htb_sched_data), + .owner = THIS_MODULE +--- a/nss_qdisc/nss_prio.c ++++ b/nss_qdisc/nss_prio.c +@@ -37,7 +37,7 @@ static struct nla_policy nss_prio_policy + * nss_prio_enqueue() + * Enqueues a skb to nssprio qdisc. + */ +-static int nss_prio_enqueue(struct sk_buff *skb, struct Qdisc *sch) ++static int nss_prio_enqueue(struct sk_buff *skb, struct Qdisc *sch, struct sk_buff **to_free) + { + return nss_qdisc_enqueue(skb, sch); + } +@@ -52,17 +52,6 @@ static struct sk_buff *nss_prio_dequeue( + } + + /* +- * nss_prio_drop() +- * Drops a single skb from linux queue, if not empty. +- * +- * Does not drop packets that are queued in the NSS. +- */ +-static unsigned int nss_prio_drop(struct Qdisc *sch) +-{ +- return nss_qdisc_drop(sch); +-} +- +-/* + * nss_prio_peek() + * Peeks the first packet in queue for this qdisc. + */ +@@ -117,7 +106,7 @@ static void nss_prio_destroy(struct Qdis + /* + * We can now destroy it + */ +- qdisc_destroy(q->queues[i]); ++ qdisc_put(q->queues[i]); + } + + /* +@@ -157,7 +146,7 @@ static int nss_prio_get_max_bands(struct + * nss_prio_change() + * Function call to configure the nssprio parameters + */ +-static int nss_prio_change(struct Qdisc *sch, struct nlattr *opt) ++static int nss_prio_change(struct Qdisc *sch, struct nlattr *opt, struct netlink_ext_ack *extack) + { + struct nss_prio_sched_data *q; + struct tc_nssprio_qopt *qopt; +@@ -209,7 +198,7 @@ static int nss_prio_change(struct Qdisc + * nss_prio_init() + * Initializes the nssprio qdisc + */ +-static int nss_prio_init(struct Qdisc *sch, struct nlattr *opt) ++static int nss_prio_init(struct Qdisc *sch, struct nlattr *opt, struct netlink_ext_ack *extack) + { + struct nss_prio_sched_data *q = qdisc_priv(sch); + struct tc_nssprio_qopt *qopt; +@@ -230,14 +219,14 @@ static int nss_prio_init(struct Qdisc *s + accel_mode = qopt->accel_mode; + } + +- if (nss_qdisc_init(sch, &q->nq, NSS_SHAPER_NODE_TYPE_PRIO, 0, accel_mode) < 0) { ++ if (nss_qdisc_init(sch, extack, &q->nq, NSS_SHAPER_NODE_TYPE_PRIO, 0, accel_mode) < 0) { + return -EINVAL; + } + + nss_qdisc_info("Nssprio initialized - handle %x parent %x\n", + sch->handle, sch->parent); + +- if (nss_prio_change(sch, opt) < 0) { ++ if (nss_prio_change(sch, opt, NULL) < 0) { + nss_qdisc_destroy(&q->nq); + return -EINVAL; + } +@@ -280,7 +269,7 @@ nla_put_failure: + * Replaces existing child qdisc with the new qdisc that is passed. + */ + static int nss_prio_graft(struct Qdisc *sch, unsigned long arg, +- struct Qdisc *new, struct Qdisc **old) ++ struct Qdisc *new, struct Qdisc **old, struct netlink_ext_ack *extack) + { + struct nss_prio_sched_data *q = qdisc_priv(sch); + struct nss_qdisc *nq_new = qdisc_priv(new); +@@ -383,15 +372,6 @@ static unsigned long nss_prio_get(struct + } + + /* +- * nss_prio_put() +- * Unused API. +- */ +-static void nss_prio_put(struct Qdisc *sch, unsigned long arg) +-{ +- nss_qdisc_info("Inside prio put\n"); +-} +- +-/* + * nss_prio_walk() + * Walks the priority band. + */ +@@ -460,9 +440,8 @@ static int nss_prio_dump_class_stats(str + const struct Qdisc_class_ops nss_prio_class_ops = { + .graft = nss_prio_graft, + .leaf = nss_prio_leaf, +- .get = nss_prio_get, +- .put = nss_prio_put, ++ .find = nss_prio_get, + .walk = nss_prio_walk, + .dump = nss_prio_dump_class, + .dump_stats = nss_prio_dump_class_stats, + }; +@@ -481,7 +459,6 @@ struct Qdisc_ops nss_prio_qdisc_ops __re + .enqueue = nss_prio_enqueue, + .dequeue = nss_prio_dequeue, + .peek = nss_prio_peek, +- .drop = nss_prio_drop, + .init = nss_prio_init, + .reset = nss_prio_reset, + .destroy = nss_prio_destroy, +--- a/nss_qdisc/nss_qdisc.c ++++ b/nss_qdisc/nss_qdisc.c +@@ -929,7 +929,7 @@ static inline void nss_qdisc_add_to_tail + * We do not use the qdisc_enqueue_tail() API here in order + * to prevent stats from getting updated by the API. + */ +- __skb_queue_tail(&sch->q, skb); ++ __qdisc_enqueue_tail(skb, &sch->q); + + spin_unlock_bh(&nq->bounce_protection_lock); + }; +@@ -944,7 +944,7 @@ static inline void nss_qdisc_add_to_tail + * We do not use the qdisc_enqueue_tail() API here in order + * to prevent stats from getting updated by the API. + */ +- __skb_queue_tail(&sch->q, skb); ++ __qdisc_enqueue_tail(skb, &sch->q); + }; + + /* +@@ -966,7 +966,7 @@ static inline struct sk_buff *nss_qdisc_ + * We use __skb_dequeue() to ensure that + * stats don't get updated twice. + */ +- skb = __skb_dequeue(&sch->q); ++ skb = __qdisc_dequeue_head(&sch->q); + + spin_unlock_bh(&nq->bounce_protection_lock); + +@@ -983,7 +983,7 @@ static inline struct sk_buff *nss_qdisc_ + * We use __skb_dequeue() to ensure that + * stats don't get updated twice. + */ +- return __skb_dequeue(&sch->q); ++ return __qdisc_dequeue_head(&sch->q); + }; + + /* +@@ -1064,14 +1064,19 @@ struct Qdisc *nss_qdisc_replace(struct Q + void *nss_qdisc_qopt_get(struct nlattr *opt, struct nla_policy *policy, + uint32_t tca_max, uint32_t tca_params) + { +- struct nlattr *na[tca_max + 1]; ++ struct nlattr *na[8]; + int err; + ++ if (tca_max > 8) { ++ pr_warn("nss_qdisc_qopt_get(): Too many options!\n"); ++ return NULL; ++ } ++ + if (!opt) { + return NULL; + } + +- err = nla_parse_nested(na, tca_max, opt, policy); ++ err = nla_parse_nested_deprecated(na, tca_max, opt, policy, NULL); + if (err < 0) + return NULL; + +@@ -1104,10 +1109,10 @@ struct sk_buff *nss_qdisc_peek(struct Qd + struct sk_buff *skb; + + if (!nq->is_virtual) { +- skb = skb_peek(&sch->q); ++ skb = qdisc_peek_head(sch); + } else { + spin_lock_bh(&nq->bounce_protection_lock); +- skb = skb_peek(&sch->q); ++ skb = qdisc_peek_head(sch); + spin_unlock_bh(&nq->bounce_protection_lock); + } + +@@ -1122,15 +1127,16 @@ unsigned int nss_qdisc_drop(struct Qdisc + { + struct nss_qdisc *nq = qdisc_priv(sch); + unsigned int ret; ++ struct sk_buff *to_free = qdisc_peek_head(sch); + + if (!nq->is_virtual) { +- ret = __qdisc_queue_drop_head(sch, &sch->q); ++ ret = __qdisc_queue_drop_head(sch, &sch->q, &to_free); + } else { + spin_lock_bh(&nq->bounce_protection_lock); + /* + * This function is safe to call within locks + */ +- ret = __qdisc_queue_drop_head(sch, &sch->q); ++ ret = __qdisc_queue_drop_head(sch, &sch->q, &to_free); + spin_unlock_bh(&nq->bounce_protection_lock); + } + +@@ -1958,7 +1964,7 @@ void nss_qdisc_destroy(struct nss_qdisc + * Initializes a shaper in NSS, based on the position of this qdisc (child or root) + * and if its a normal interface or a bridge interface. + */ +-int nss_qdisc_init(struct Qdisc *sch, struct nss_qdisc *nq, nss_shaper_node_type_t type, uint32_t classid, uint32_t accel_mode) ++int nss_qdisc_init(struct Qdisc *sch, struct netlink_ext_ack *extack, struct nss_qdisc *nq, nss_shaper_node_type_t type, uint32_t classid, uint32_t accel_mode) + { + struct Qdisc *root; + u32 parent; +@@ -2471,6 +2481,8 @@ static void nss_qdisc_basic_stats_callba + struct gnet_stats_queue *qstats; + struct nss_shaper_node_stats_response *response; + atomic_t *refcnt; ++ refcount_t *refcnt_new; ++ bool is_refcnt_zero = false; + + if (nim->cm.response != NSS_CMN_RESPONSE_ACK) { + nss_qdisc_warning("Qdisc %p (type %d): Receive stats FAILED - " +@@ -2494,7 +2506,7 @@ static void nss_qdisc_basic_stats_callba + } else { + bstats = &qdisc->bstats; + qstats = &qdisc->qstats; +- refcnt = &qdisc->refcnt; ++ refcnt_new = &qdisc->refcnt; + qdisc->q.qlen = response->sn_stats.qlen_packets; + } + +@@ -2533,11 +2545,20 @@ static void nss_qdisc_basic_stats_callba + * All access to nq fields below do not need lock protection. They + * do not get manipulated on different thread contexts. + */ +- if (atomic_read(refcnt) == 0) { ++ if (nq->is_class) { ++ if (atomic_read(refcnt) == 0) ++ is_refcnt_zero = true; ++ } ++ else { ++ if (refcount_read(refcnt_new) == 0) ++ is_refcnt_zero = true; ++ } ++ if (is_refcnt_zero) { + atomic_sub(1, &nq->pending_stat_requests); + wake_up(&nq->wait_queue); + return; + } ++ + + /* + * Requests for stats again, after 1 sec. +@@ -2555,9 +2576,9 @@ static void nss_qdisc_basic_stats_callba + * nss_qdisc_get_stats_timer_callback() + * Invoked periodically to get updated stats + */ +-static void nss_qdisc_get_stats_timer_callback(unsigned long int data) ++static void nss_qdisc_get_stats_timer_callback(struct timer_list *arg) + { +- struct nss_qdisc *nq = (struct nss_qdisc *)data; ++ struct nss_qdisc *nq = (struct nss_qdisc *)arg->cust_data; + nss_tx_status_t rc; + struct nss_if_msg nim; + int msg_type; +@@ -2604,9 +2625,8 @@ void nss_qdisc_start_basic_stats_polling + return; + } + +- init_timer(&nq->stats_get_timer); +- nq->stats_get_timer.function = nss_qdisc_get_stats_timer_callback; +- nq->stats_get_timer.data = (unsigned long)nq; ++ timer_setup(&nq->stats_get_timer, nss_qdisc_get_stats_timer_callback, 0); ++ nq->stats_get_timer.cust_data = (unsigned long)nq; + nq->stats_get_timer.expires = jiffies + HZ; + atomic_set(&nq->pending_stat_requests, 1); + add_timer(&nq->stats_get_timer); +@@ -2650,7 +2670,7 @@ int nss_qdisc_gnet_stats_copy_basic(stru + #if (LINUX_VERSION_CODE <= KERNEL_VERSION(3, 18, 0)) + return gnet_stats_copy_basic(d, b); + #else +- return gnet_stats_copy_basic(d, NULL, b); ++ return gnet_stats_copy_basic(NULL, d, NULL, b); + #endif + } + +--- a/nss_qdisc/nss_tbl.c ++++ b/nss_qdisc/nss_tbl.c +@@ -29,7 +29,7 @@ static struct nla_policy nss_tbl_policy[ + [TCA_NSSTBL_PARMS] = { .len = sizeof(struct tc_nsstbl_qopt) }, + }; + +-static int nss_tbl_enqueue(struct sk_buff *skb, struct Qdisc *sch) ++static int nss_tbl_enqueue(struct sk_buff *skb, struct Qdisc *sch, struct sk_buff **to_free) + { + return nss_qdisc_enqueue(skb, sch); + } +@@ -39,11 +39,6 @@ static struct sk_buff *nss_tbl_dequeue(s + return nss_qdisc_dequeue(sch); + } + +-static unsigned int nss_tbl_drop(struct Qdisc *sch) +-{ +- return nss_qdisc_drop(sch); +-} +- + static struct sk_buff *nss_tbl_peek(struct Qdisc *sch) + { + return nss_qdisc_peek(sch); +@@ -77,7 +72,7 @@ static void nss_tbl_destroy(struct Qdisc + /* + * Now we can destroy our child qdisc + */ +- qdisc_destroy(q->qdisc); ++ qdisc_put(q->qdisc); + + /* + * Stop the polling of basic stats and destroy qdisc. +@@ -132,7 +127,7 @@ fail: + } + #endif + +-static int nss_tbl_change(struct Qdisc *sch, struct nlattr *opt) ++static int nss_tbl_change(struct Qdisc *sch, struct nlattr *opt, struct netlink_ext_ack *extack) + { + struct nss_tbl_sched_data *q = qdisc_priv(sch); + struct tc_nsstbl_qopt *qopt; +@@ -216,7 +211,7 @@ static int nss_tbl_change(struct Qdisc * + return 0; + } + +-static int nss_tbl_init(struct Qdisc *sch, struct nlattr *opt) ++static int nss_tbl_init(struct Qdisc *sch, struct nlattr *opt, struct netlink_ext_ack *extack) + { + struct nss_tbl_sched_data *q = qdisc_priv(sch); + struct tc_nsstbl_qopt *qopt; +@@ -232,10 +227,10 @@ static int nss_tbl_init(struct Qdisc *sc + return -EINVAL; + } + +- if (nss_qdisc_init(sch, &q->nq, NSS_SHAPER_NODE_TYPE_TBL, 0, qopt->accel_mode) < 0) ++ if (nss_qdisc_init(sch, extack, &q->nq, NSS_SHAPER_NODE_TYPE_TBL, 0, qopt->accel_mode) < 0) + return -EINVAL; + +- if (nss_tbl_change(sch, opt) < 0) { ++ if (nss_tbl_change(sch, opt, NULL) < 0) { + nss_qdisc_info("Failed to configure tbl\n"); + nss_qdisc_destroy(&q->nq); + return -EINVAL; +@@ -287,7 +282,7 @@ static int nss_tbl_dump_class(struct Qdi + } + + static int nss_tbl_graft(struct Qdisc *sch, unsigned long arg, struct Qdisc *new, +- struct Qdisc **old) ++ struct Qdisc **old, struct netlink_ext_ack *extack) + { + struct nss_tbl_sched_data *q = qdisc_priv(sch); + struct nss_qdisc *nq_new = (struct nss_qdisc *)qdisc_priv(new); +@@ -344,10 +339,6 @@ static unsigned long nss_tbl_get(struct + return 1; + } + +-static void nss_tbl_put(struct Qdisc *sch, unsigned long arg) +-{ +-} +- + static void nss_tbl_walk(struct Qdisc *sch, struct qdisc_walker *walker) + { + nss_qdisc_info("Nsstbl walk called"); +@@ -364,9 +355,8 @@ static void nss_tbl_walk(struct Qdisc *s + const struct Qdisc_class_ops nss_tbl_class_ops = { + .graft = nss_tbl_graft, + .leaf = nss_tbl_leaf, +- .get = nss_tbl_get, +- .put = nss_tbl_put, ++ .find = nss_tbl_get, + .walk = nss_tbl_walk, + .dump = nss_tbl_dump_class, + }; + +@@ -381,7 +370,6 @@ struct Qdisc_ops nss_tbl_qdisc_ops __rea + .enqueue = nss_tbl_enqueue, + .dequeue = nss_tbl_dequeue, + .peek = nss_tbl_peek, +- .drop = nss_tbl_drop, + .init = nss_tbl_init, + .reset = nss_tbl_reset, + .destroy = nss_tbl_destroy, +--- a/nss_qdisc/nss_wred.c ++++ b/nss_qdisc/nss_wred.c +@@ -55,7 +55,7 @@ static struct nla_policy nss_wred_policy + * nss_wred_enqueue() + * Enqueue API for nsswred qdisc + */ +-static int nss_wred_enqueue(struct sk_buff *skb, struct Qdisc *sch) ++static int nss_wred_enqueue(struct sk_buff *skb, struct Qdisc *sch, struct sk_buff **to_free) + { + return nss_qdisc_enqueue(skb, sch); + } +@@ -70,16 +70,6 @@ static struct sk_buff *nss_wred_dequeue( + } + + /* +- * nss_wred_drop() +- * Drops a packet from HLOS queue. +- */ +-static unsigned int nss_wred_drop(struct Qdisc *sch) +-{ +- nss_qdisc_info("nsswred dropping"); +- return nss_qdisc_drop(sch); +-} +- +-/* + * nss_wred_reset() + * Reset the nsswred qdisc + */ +@@ -171,7 +161,7 @@ fail: + * nss_wred_change() + * Function call to configure the nsswred parameters + */ +-static int nss_wred_change(struct Qdisc *sch, struct nlattr *opt) ++static int nss_wred_change(struct Qdisc *sch, struct nlattr *opt, struct netlink_ext_ack *extack) + { + struct nss_wred_sched_data *q = qdisc_priv(sch); + struct tc_nsswred_qopt *qopt; +@@ -298,7 +288,7 @@ static int nss_wred_change(struct Qdisc + * nss_wred_init() + * Init the nsswred qdisc + */ +-static int nss_wred_init(struct Qdisc *sch, struct nlattr *opt) ++static int nss_wred_init(struct Qdisc *sch, struct nlattr *opt, struct netlink_ext_ack *extack) + { + struct nss_qdisc *nq = qdisc_priv(sch); + struct tc_nsswred_qopt *qopt; +@@ -315,11 +305,11 @@ static int nss_wred_init(struct Qdisc *s + nss_qdisc_info("Initializing Wred - type %d\n", NSS_SHAPER_NODE_TYPE_WRED); + nss_wred_reset(sch); + +- if (nss_qdisc_init(sch, nq, NSS_SHAPER_NODE_TYPE_WRED, 0, qopt->accel_mode) < 0) ++ if (nss_qdisc_init(sch, extack, nq, NSS_SHAPER_NODE_TYPE_WRED, 0, qopt->accel_mode) < 0) + return -EINVAL; + + nss_qdisc_info("NSS wred initialized - handle %x parent %x\n", sch->handle, sch->parent); +- if (nss_wred_change(sch, opt) < 0) { ++ if (nss_wred_change(sch, opt, NULL) < 0) { + nss_qdisc_destroy(nq); + return -EINVAL; + } +@@ -405,7 +395,6 @@ struct Qdisc_ops nss_red_qdisc_ops __rea + .enqueue = nss_wred_enqueue, + .dequeue = nss_wred_dequeue, + .peek = nss_wred_peek, +- .drop = nss_wred_drop, + .init = nss_wred_init, + .reset = nss_wred_reset, + .destroy = nss_wred_destroy, +@@ -423,7 +412,6 @@ struct Qdisc_ops nss_wred_qdisc_ops __re + .enqueue = nss_wred_enqueue, + .dequeue = nss_wred_dequeue, + .peek = nss_wred_peek, +- .drop = nss_wred_drop, + .init = nss_wred_init, + .reset = nss_wred_reset, + .destroy = nss_wred_destroy, +--- a/nss_qdisc/nss_wrr.c ++++ b/nss_qdisc/nss_wrr.c +@@ -84,7 +84,7 @@ static void nss_wrr_destroy_class(struct + /* + * And now we destroy the child. + */ +- qdisc_destroy(cl->qdisc); ++ qdisc_put(cl->qdisc); + + /* + * Stop the stats polling timer and free class +@@ -219,7 +219,7 @@ static int nss_wrr_ppe_change_class(stru + #endif + + static int nss_wrr_change_class(struct Qdisc *sch, u32 classid, u32 parentid, +- struct nlattr **tca, unsigned long *arg) ++ struct nlattr **tca, unsigned long *arg, struct netlink_ext_ack *extack) + { + struct nss_wrr_sched_data *q = qdisc_priv(sch); + struct nss_wrr_class_data *cl = (struct nss_wrr_class_data *)*arg; +@@ -286,7 +286,7 @@ static int nss_wrr_change_class(struct Q + * here. + */ + cl->nq.parent = &q->nq; +- if (nss_qdisc_init(sch, &cl->nq, NSS_SHAPER_NODE_TYPE_WRR_GROUP, classid, accel_mode) < 0) { ++ if (nss_qdisc_init(sch, extack, &cl->nq, NSS_SHAPER_NODE_TYPE_WRR_GROUP, classid, accel_mode) < 0) { + nss_qdisc_error("Nss init for class %u failed\n", classid); + return -EINVAL; + } +@@ -422,7 +422,7 @@ static int nss_wrr_delete_class(struct Q + } + + static int nss_wrr_graft_class(struct Qdisc *sch, unsigned long arg, struct Qdisc *new, +- struct Qdisc **old) ++ struct Qdisc **old, struct netlink_ext_ack *extack) + { + struct nss_wrr_sched_data *q = qdisc_priv(sch); + struct nss_wrr_class_data *cl = (struct nss_wrr_class_data *)arg; +@@ -517,20 +517,6 @@ static unsigned long nss_wrr_get_class(s + return (unsigned long)cl; + } + +-static void nss_wrr_put_class(struct Qdisc *sch, unsigned long arg) +-{ +- struct nss_wrr_class_data *cl = (struct nss_wrr_class_data *)arg; +- nss_qdisc_info("nss_wrr put class for %p\n", cl); +- +- /* +- * We are safe to destroy the qdisc if the reference count +- * goes down to 0. +- */ +- if (atomic_sub_return(1, &cl->nq.refcnt) == 0) { +- nss_wrr_destroy_class(sch, cl); +- } +-} +- + static int nss_wrr_dump_class(struct Qdisc *sch, unsigned long arg, struct sk_buff *skb, + struct tcmsg *tcm) + { +@@ -600,7 +586,7 @@ static void nss_wrr_walk(struct Qdisc *s + } + } + +-static int nss_wrr_init_qdisc(struct Qdisc *sch, struct nlattr *opt) ++static int nss_wrr_init_qdisc(struct Qdisc *sch, struct nlattr *opt, struct netlink_ext_ack *extack) + { + struct nss_wrr_sched_data *q = qdisc_priv(sch); + int err; +@@ -629,7 +615,7 @@ static int nss_wrr_init_qdisc(struct Qdi + /* + * Initialize the NSSWRR shaper in NSS + */ +- if (nss_qdisc_init(sch, &q->nq, NSS_SHAPER_NODE_TYPE_WRR, 0, qopt->accel_mode) < 0) { ++ if (nss_qdisc_init(sch, extack, &q->nq, NSS_SHAPER_NODE_TYPE_WRR, 0, qopt->accel_mode) < 0) { + nss_qdisc_warning("Failed init nss_wrr qdisc"); + return -EINVAL; + } +@@ -669,7 +655,7 @@ static int nss_wrr_init_qdisc(struct Qdi + return 0; + } + +-static int nss_wrr_change_qdisc(struct Qdisc *sch, struct nlattr *opt) ++static int nss_wrr_change_qdisc(struct Qdisc *sch, struct nlattr *opt, struct netlink_ext_ack *extack) + { + struct nss_wrr_sched_data *q; + struct tc_nsswrr_qopt *qopt; +@@ -809,7 +795,7 @@ nla_put_failure: + return -EMSGSIZE; + } + +-static int nss_wrr_enqueue(struct sk_buff *skb, struct Qdisc *sch) ++static int nss_wrr_enqueue(struct sk_buff *skb, struct Qdisc *sch, struct sk_buff **to_free) + { + return nss_qdisc_enqueue(skb, sch); + } +@@ -819,21 +805,14 @@ static struct sk_buff *nss_wrr_dequeue(s + return nss_qdisc_dequeue(sch); + } + +-static unsigned int nss_wrr_drop(struct Qdisc *sch) +-{ +- nss_qdisc_info("Nsswrr drop\n"); +- return nss_qdisc_drop(sch); +-} +- + const struct Qdisc_class_ops nss_wrr_class_ops = { + .change = nss_wrr_change_class, + .delete = nss_wrr_delete_class, + .graft = nss_wrr_graft_class, + .leaf = nss_wrr_leaf_class, + .qlen_notify = nss_wrr_qlen_notify, +- .get = nss_wrr_get_class, +- .put = nss_wrr_put_class, ++ .find = nss_wrr_get_class, + .dump = nss_wrr_dump_class, + .dump_stats = nss_wrr_dump_class_stats, + .walk = nss_bf_walk + }; +@@ -851,7 +829,6 @@ struct Qdisc_ops nss_wrr_qdisc_ops __rea + .enqueue = nss_wrr_enqueue, + .dequeue = nss_wrr_dequeue, + .peek = qdisc_peek_dequeued, +- .drop = nss_wrr_drop, + .cl_ops = &nss_wrr_class_ops, + .priv_size = sizeof(struct nss_wrr_sched_data), + .owner = THIS_MODULE +@@ -863,9 +840,8 @@ const struct Qdisc_class_ops nss_wfq_cla + .graft = nss_wrr_graft_class, + .leaf = nss_wrr_leaf_class, + .qlen_notify = nss_wrr_qlen_notify, +- .get = nss_wrr_get_class, +- .put = nss_wrr_put_class, ++ .find = nss_wrr_get_class, + .dump = nss_wrr_dump_class, + .dump_stats = nss_wrr_dump_class_stats, + .walk = nss_wrr_walk + }; +@@ -883,7 +858,6 @@ struct Qdisc_ops nss_wfq_qdisc_ops __rea + .enqueue = nss_wrr_enqueue, + .dequeue = nss_wrr_dequeue, + .peek = qdisc_peek_dequeued, +- .drop = nss_wrr_drop, + .cl_ops = &nss_wrr_class_ops, + .priv_size = sizeof(struct nss_wrr_sched_data), + .owner = THIS_MODULE diff --git a/qaa/nss/qca-nss-clients/patches/101-kernel-5.4-support-gre.patch b/qaa/nss/qca-nss-clients/patches/101-kernel-5.4-support-gre.patch new file mode 100644 index 000000000..705ceabe6 --- /dev/null +++ b/qaa/nss/qca-nss-clients/patches/101-kernel-5.4-support-gre.patch @@ -0,0 +1,106 @@ +From 7c89187ab2d165ccffed627742e7cb72cce375ef Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Sun, 12 Jul 2020 22:49:30 +0200 +Subject: [PATCH] kernel-5.4-support-gre + +--- + gre/nss_connmgr_gre.c | 16 +++++++--------- + gre/nss_connmgr_gre_v6.c | 4 ++-- + 2 files changed, 9 insertions(+), 11 deletions(-) + +diff --git a/gre/nss_connmgr_gre.c b/gre/nss_connmgr_gre.c +index 52203b1..6de8f6e 100644 +--- a/gre/nss_connmgr_gre.c ++++ b/gre/nss_connmgr_gre.c +@@ -88,7 +88,7 @@ static int nss_connmgr_gre_dev_init(struct net_device *dev) + u64_stats_init(&stats->syncp); + } + +- if ((dev->priv_flags & IFF_GRE_V4_TAP) || (dev->type == ARPHRD_IPGRE)) { ++ if ((dev->priv_flags_qca_ecm & IFF_QCA_ECM_GRE_V4_TAP) || (dev->type == ARPHRD_IPGRE)) { + dev->needed_headroom = sizeof(struct iphdr) + sizeof(struct ethhdr) + MAX_WIFI_HEADROOM + append; + dev->mtu = ETH_DATA_LEN - sizeof(struct iphdr) - append; + dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_SG | NETIF_F_FRAGLIST | NETIF_F_HIGHDMA; +@@ -169,7 +169,7 @@ fail: + * nss_connmgr_gre_dev_stats64() + * Netdev ops function to retrieve stats. + */ +-struct rtnl_link_stats64 *nss_connmgr_gre_dev_stats64(struct net_device *dev, ++void nss_connmgr_gre_dev_stats64(struct net_device *dev, + struct rtnl_link_stats64 *tot) + { + uint64_t rx_packets, rx_bytes, tx_packets, tx_bytes; +@@ -202,8 +202,6 @@ struct rtnl_link_stats64 *nss_connmgr_gre_dev_stats64(struct net_device *dev, + tot->rx_dropped = dev->stats.rx_dropped; + tot->tx_dropped = dev->stats.tx_dropped; + } +- +- return tot; + } + + /* +@@ -390,7 +388,7 @@ static int32_t nss_connmgr_gre_prepare_config_cmd(struct net_device *dev, + { + struct nss_gre_config_msg *cmsg = &req->msg.cmsg; + +- if ((dev->type == ARPHRD_ETHER) && (dev->priv_flags & IFF_GRE_V4_TAP)) { ++ if ((dev->type == ARPHRD_ETHER) && (dev->priv_flags_qca_ecm & IFF_QCA_ECM_GRE_V4_TAP)) { + cmsg->mode = NSS_GRE_MODE_TAP; + cmsg->ip_type = NSS_GRE_IP_IPV4; + if (enable_unalign) { +@@ -399,7 +397,7 @@ static int32_t nss_connmgr_gre_prepare_config_cmd(struct net_device *dev, + return nss_connmgr_gre_v4_get_config(dev, req, next_dev, hold); + } + +- if ((dev->type == ARPHRD_ETHER) && (dev->priv_flags & IFF_GRE_V6_TAP)) { ++ if ((dev->type == ARPHRD_ETHER) && (dev->priv_flags_qca_ecm & IFF_QCA_ECM_GRE_V6_TAP)) { + cmsg->mode = NSS_GRE_MODE_TAP; + cmsg->ip_type = NSS_GRE_IP_IPV6; + if (enable_unalign) { +@@ -605,7 +603,7 @@ static bool nss_connmgr_gre_is_gre(struct net_device *dev) + { + if ((dev->type == ARPHRD_IPGRE) || + (dev->type == ARPHRD_IP6GRE) || ((dev->type == ARPHRD_ETHER) && +- (dev->priv_flags & (IFF_GRE_V4_TAP | IFF_GRE_V6_TAP)))) { ++ (dev->priv_flags_qca_ecm & (IFF_QCA_ECM_GRE_V4_TAP | IFF_QCA_ECM_GRE_V6_TAP)))) { + return true; + } + +@@ -692,10 +690,10 @@ static struct net_device *__nss_connmgr_gre_create_interface(struct nss_connmgr_ + nss_connmgr_gre_tap_setup(dev); + + if (cfg->is_ipv6) { +- dev->priv_flags |= IFF_GRE_V6_TAP; ++ dev->priv_flags_qca_ecm |= IFF_QCA_ECM_GRE_V6_TAP; + ret = nss_connmgr_gre_v6_set_config(dev, cfg); + } else { +- dev->priv_flags |= IFF_GRE_V4_TAP; ++ dev->priv_flags_qca_ecm |= IFF_QCA_ECM_GRE_V4_TAP; + ret = nss_connmgr_gre_v4_set_config(dev, cfg); + } + break; +diff --git a/gre/nss_connmgr_gre_v6.c b/gre/nss_connmgr_gre_v6.c +index f9a8e58..e93c7e4 100644 +--- a/gre/nss_connmgr_gre_v6.c ++++ b/gre/nss_connmgr_gre_v6.c +@@ -46,7 +46,7 @@ static struct net_device *nss_connmgr_gre_v6_get_tx_dev(uint8_t *dest_ip) + struct net_device *dev; + + memcpy(ipv6_addr.s6_addr, dest_ip, 16); +- rt = rt6_lookup(&init_net, &ipv6_addr, NULL, 0, 0); ++ rt = rt6_lookup(&init_net, &ipv6_addr, NULL, 0, NULL, 0); + if (!rt) { + return NULL; + } +@@ -92,7 +92,7 @@ static int nss_connmgr_gre_v6_get_mac_address(uint8_t *src_ip, uint8_t *dest_ip, + * Find dest MAC address + */ + memcpy(ipv6_addr.s6_addr, dest_ip, 16); +- rt = rt6_lookup(&init_net, &ipv6_addr, NULL, 0, 0); ++ rt = rt6_lookup(&init_net, &ipv6_addr, NULL, 0, NULL, 0); + if (!rt) { + return GRE_ERR_NEIGH_LOOKUP; + } +-- +2.27.0 + diff --git a/qaa/nss/qca-nss-clients/patches/102-kernel-5.4-support-ipsec.patch b/qaa/nss/qca-nss-clients/patches/102-kernel-5.4-support-ipsec.patch new file mode 100644 index 000000000..de43b4d01 --- /dev/null +++ b/qaa/nss/qca-nss-clients/patches/102-kernel-5.4-support-ipsec.patch @@ -0,0 +1,29 @@ +--- a/ipsecmgr/v1.0/nss_ipsecmgr.c ++++ b/ipsecmgr/v1.0/nss_ipsecmgr.c +@@ -377,7 +377,7 @@ free: + * nss_ipsecmgr_tunnel_stats() + * get tunnel statistics + */ +-static struct rtnl_link_stats64 *nss_ipsecmgr_tunnel_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) ++void nss_ipsecmgr_tunnel_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) + { + struct nss_ipsecmgr_priv *priv = netdev_priv(dev); + +@@ -389,8 +389,6 @@ static struct rtnl_link_stats64 *nss_ips + read_lock_bh(&ipsecmgr_ctx->lock); + memcpy(stats, &priv->stats, sizeof(struct rtnl_link_stats64)); + read_unlock_bh(&ipsecmgr_ctx->lock); +- +- return stats; + } + + /* +@@ -442,7 +440,7 @@ static void nss_ipsecmgr_tunnel_setup(st + dev->header_ops = NULL; + dev->netdev_ops = &nss_ipsecmgr_tunnel_ops; + +- dev->destructor = nss_ipsecmgr_tunnel_free; ++ dev->priv_destructor = nss_ipsecmgr_tunnel_free; + + /* + * get the MAC address from the ethernet device diff --git a/qaa/nss/qca-nss-clients/patches/103-kernel-5.4-support-dtls.patch b/qaa/nss/qca-nss-clients/patches/103-kernel-5.4-support-dtls.patch new file mode 100644 index 000000000..ae9c91470 --- /dev/null +++ b/qaa/nss/qca-nss-clients/patches/103-kernel-5.4-support-dtls.patch @@ -0,0 +1,11 @@ +--- a/dtls/v1.0/nss_connmgr_dtls_netdev.c ++++ b/dtls/v1.0/nss_connmgr_dtls_netdev.c +@@ -160,7 +160,7 @@ static void nss_dtlsmgr_dev_setup(struct + dev->ethtool_ops = NULL; + dev->header_ops = NULL; + dev->netdev_ops = &nss_dtlsmgr_session_ops; +- dev->destructor = NULL; ++ dev->priv_destructor = NULL; + + memcpy(dev->dev_addr, "\xaa\xbb\xcc\xdd\xee\xff", dev->addr_len); + memset(dev->broadcast, 0xff, dev->addr_len); diff --git a/qaa/nss/qca-nss-clients/patches/104-kernel-5.4-support-l2tp.patch b/qaa/nss/qca-nss-clients/patches/104-kernel-5.4-support-l2tp.patch new file mode 100644 index 000000000..c637235cc --- /dev/null +++ b/qaa/nss/qca-nss-clients/patches/104-kernel-5.4-support-l2tp.patch @@ -0,0 +1,64 @@ +--- a/l2tp/l2tpv2/nss_connmgr_l2tpv2.h ++++ b/l2tp/l2tpv2/nss_connmgr_l2tpv2.h +@@ -30,10 +30,10 @@ + + #define L2TP_V_2 2 + +-#define tunnel_hold(tunnel) atomic_inc(&tunnel->ref_count) +-#define tunnel_put(tunnel) atomic_dec(&tunnel->ref_count) +-#define session_hold(session) atomic_inc(&session->ref_count) +-#define session_put(session) atomic_dec(&session->ref_count) ++#define tunnel_hold(tunnel) refcount_inc(&tunnel->ref_count) ++#define tunnel_put(tunnel) refcount_dec(&tunnel->ref_count) ++#define session_hold(session) refcount_inc(&session->ref_count) ++#define session_put(session) refcount_dec(&session->ref_count) + + /* + * ---------------------------------------------------------------------------------- +--- a/l2tp/l2tpv2/nss_connmgr_l2tpv2.c ++++ b/l2tp/l2tpv2/nss_connmgr_l2tpv2.c +@@ -244,7 +244,7 @@ static struct nss_connmgr_l2tpv2_session + */ + data->l2tpv2.session.session_id = session->session_id; + data->l2tpv2.session.peer_session_id = session->peer_session_id; +- data->l2tpv2.session.offset = session->offset; ++ data->l2tpv2.session.offset = 0; + data->l2tpv2.session.hdr_len = session->hdr_len; + data->l2tpv2.session.reorder_timeout = session->reorder_timeout; + data->l2tpv2.session.recv_seq = session->recv_seq; +@@ -253,7 +253,7 @@ static struct nss_connmgr_l2tpv2_session + nss_connmgr_l2tpv2_info("sess %u, peer=%u nr=%u ns=%u off=%u hdr_len=%u timeout=%x" + " recv_seq=%x send_seq=%x\n", + session->session_id, session->peer_session_id, session->nr, +- session->ns, session->offset, session->hdr_len, ++ session->ns, 0, session->hdr_len, + session->reorder_timeout, session->recv_seq, + session->send_seq); + +--- a/l2tp/l2tpv2/nss_l2tpv2_stats.c ++++ b/l2tp/l2tpv2/nss_l2tpv2_stats.c +@@ -21,6 +21,7 @@ + */ + + #include ++#include + #include + #include + #include +@@ -103,14 +104,14 @@ void nss_l2tpv2_update_dev_stats(struct + /* + * Update tunnel & session stats + */ +- tunnel = l2tp_tunnel_find(dev_net(dev), data.l2tpv2.tunnel.tunnel_id); ++ tunnel = l2tp_tunnel_get(dev_net(dev), data.l2tpv2.tunnel.tunnel_id); + if (!tunnel) { + dev_put(dev); + return; + } + tunnel_hold(tunnel); + +- session = l2tp_session_find(dev_net(dev), tunnel, data.l2tpv2.session.session_id); ++ session = l2tp_session_get(dev_net(dev), data.l2tpv2.session.session_id); + if (!session) { + tunnel_put(tunnel); + dev_put(dev); diff --git a/qaa/nss/qca-nss-clients/patches/200-qdisc-fix-compile-error.patch b/qaa/nss/qca-nss-clients/patches/200-qdisc-fix-compile-error.patch new file mode 100644 index 000000000..4e147489b --- /dev/null +++ b/qaa/nss/qca-nss-clients/patches/200-qdisc-fix-compile-error.patch @@ -0,0 +1,14 @@ +--- a/nss_qdisc/nss_qdisc.c ++++ b/nss_qdisc/nss_qdisc.c +@@ -2708,9 +2708,11 @@ static int nss_qdisc_if_event_cb(struct + case NETDEV_BR_JOIN: + nss_qdisc_info("Reveived NETDEV_BR_JOIN on interface %s\n", + dev->name); ++ goto fall_through; + case NETDEV_BR_LEAVE: + nss_qdisc_info("Reveived NETDEV_BR_LEAVE on interface %s\n", + dev->name); ++fall_through: + br = nss_qdisc_get_dev_master(dev); + if_num = nss_cmn_get_interface_number(nss_qdisc_ctx, dev); + diff --git a/qaa/nss/qca-nss-clients/patches/202-vlanmgr-fix-compile-error.patch b/qaa/nss/qca-nss-clients/patches/202-vlanmgr-fix-compile-error.patch new file mode 100644 index 000000000..53af31924 --- /dev/null +++ b/qaa/nss/qca-nss-clients/patches/202-vlanmgr-fix-compile-error.patch @@ -0,0 +1,48 @@ +--- a/vlan/nss_vlan_mgr.c ++++ b/vlan/nss_vlan_mgr.c +@@ -820,8 +820,10 @@ static struct nss_vlan_pvt *nss_vlan_mgr + */ + static void nss_vlan_mgr_instance_free(struct nss_vlan_pvt *v) + { ++#ifdef NSS_VLAN_MGR_PPE_SUPPORT + int32_t i; + int ret = 0; ++#endif + + spin_lock(&vlan_mgr_ctx.lock); + BUG_ON(--v->refs); +@@ -979,8 +981,11 @@ static int nss_vlan_mgr_register_event(s + int ret; + #endif + uint32_t vlan_tag; ++#ifdef NSS_VLAN_MGR_PPE_SUPPORT + struct net_device *slave; +- int32_t port, port_if; ++ int32_t port; ++#endif ++ int32_t port_if; + struct vlan_dev_priv *vlan; + struct net_device *real_dev; + bool is_bond_master = false; +@@ -1354,8 +1359,10 @@ return_with_error: + int nss_vlan_mgr_join_bridge(struct net_device *dev, uint32_t bridge_vsi) + { + struct nss_vlan_pvt *v = nss_vlan_mgr_instance_find_and_ref(dev); ++#ifdef NSS_VLAN_MGR_PPE_SUPPORT + struct net_device *real_dev; + int ret; ++#endif + + if (!v) + return 0; +@@ -1415,8 +1422,10 @@ EXPORT_SYMBOL(nss_vlan_mgr_join_bridge); + int nss_vlan_mgr_leave_bridge(struct net_device *dev, uint32_t bridge_vsi) + { + struct nss_vlan_pvt *v = nss_vlan_mgr_instance_find_and_ref(dev); ++#ifdef NSS_VLAN_MGR_PPE_SUPPORT + struct net_device *real_dev; + int ret; ++#endif + + if (!v) + return 0; diff --git a/qaa/nss/qca-nss-crypto/Makefile b/qaa/nss/qca-nss-crypto/Makefile new file mode 100644 index 000000000..213e24471 --- /dev/null +++ b/qaa/nss/qca-nss-crypto/Makefile @@ -0,0 +1,74 @@ +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/kernel.mk + +PKG_NAME:=qca-nss-crypto +PKG_RELEASE:=1 + +PKG_SOURCE_URL:=https://source.codeaurora.org/quic/qsdk/oss/lklm/nss-crypto +PKG_SOURCE_PROTO:=git +PKG_SOURCE_VERSION:=e7651c2986d30b5e8ca5ad6b9a72c47febdf3cca +PKG_MIRROR_HASH:=381ba448ccd9e0ff69fa52b3e10687b72260b7d0bf865cac10be7f159573b6c8 + +include $(INCLUDE_DIR)/package.mk + +ifeq ($(CONFIG_TARGET_ipq),y) +subtarget:=$(SUBTARGET) +else +subtarget:=$(CONFIG_TARGET_BOARD) +endif + +# v1.0 is for Akronite +# v2.0 is for Hawkeye/Cypress/Maple +ifneq (, $(findstring $(subtarget), "ipq807x" "ipq807x_64" "ipq60xx" "ipq60xx_64" "ipq50xx" "ipq50xx_64")) +NSS_CRYPTO_DIR:=v2.0 +else +NSS_CRYPTO_DIR:=v1.0 +endif + +define KernelPackage/qca-nss-crypto/Default + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + DEPENDS:=@(TARGET_ipq806x||TARGET_ipq807x||TARGET_ipq50xx||TARGET_ipq60xx) +kmod-qca-nss-drv +endef + +define KernelPackage/qca-nss-crypto + $(call KernelPackage/qca-nss-crypto/Default) + TITLE:=Kernel driver for NSS crypto driver + FILES:=$(PKG_BUILD_DIR)/$(NSS_CRYPTO_DIR)/src/qca-nss-crypto.ko \ + $(PKG_BUILD_DIR)/$(NSS_CRYPTO_DIR)/tool/qca-nss-crypto-tool.ko + AUTOLOAD:=$(call AutoLoad,52,qca-nss-crypto) +endef + +define KernelPackage/qca-nss-crypto/Description +This package contains a NSS crypto driver for QCA chipset +endef + +define Build/InstallDev/qca-nss-crypto + $(INSTALL_DIR) $(1)/usr/include/qca-nss-crypto + $(CP) $(PKG_BUILD_DIR)/$(NSS_CRYPTO_DIR)/include/* $(1)/usr/include/qca-nss-crypto +endef + +define Build/InstallDev + $(call Build/InstallDev/qca-nss-crypto,$(1)) +endef + +EXTRA_CFLAGS+= \ + -DCONFIG_NSS_DEBUG_LEVEL=4 \ + -I$(STAGING_DIR)/usr/include/qca-nss-crypto \ + -I$(STAGING_DIR)/usr/include/qca-nss-drv \ + -I$(PKG_BUILD_DIR)/$(NSS_CRYPTO_DIR)/include \ + -I$(PKG_BUILD_DIR)/$(NSS_CRYPTO_DIR)/src + +define Build/Compile + $(MAKE) $(PKG_JOBS) -C "$(LINUX_DIR)" \ + $(KERNEL_MAKE_FLAGS) \ + $(PKG_MAKE_FLAGS) \ + M="$(PKG_BUILD_DIR)" \ + EXTRA_CFLAGS="$(EXTRA_CFLAGS)" \ + NSS_CRYPTO_DIR=$(NSS_CRYPTO_DIR) \ + SoC="$(subtarget)" \ + modules +endef + +$(eval $(call KernelPackage,qca-nss-crypto)) diff --git a/qaa/nss/qca-nss-crypto/patches/100-kernel-5.4-support.patch b/qaa/nss/qca-nss-crypto/patches/100-kernel-5.4-support.patch new file mode 100644 index 000000000..b9ef6191e --- /dev/null +++ b/qaa/nss/qca-nss-crypto/patches/100-kernel-5.4-support.patch @@ -0,0 +1,42 @@ +--- a/v1.0/tool/nss_crypto_bench.c ++++ b/v1.0/tool/nss_crypto_bench.c +@@ -75,8 +75,8 @@ static DECLARE_WAIT_QUEUE_HEAD(tx_comp); + static DECLARE_WAIT_QUEUE_HEAD(tx_start); + static struct task_struct *tx_thread = NULL; + +-static struct timeval init_time; +-static struct timeval comp_time; ++static struct timespec64 init_time; ++static struct timespec64 comp_time; + static spinlock_t op_lock; + static nss_crypto_handle_t crypto_hdl; + +@@ -782,7 +782,7 @@ static int crypto_bench_tx(void *arg) + crypto_bench_debug("#"); + + /* get start time */ +- do_gettimeofday(&init_time); ++ ktime_get_real_ts64(&init_time); + + /** + * Request submission +@@ -812,8 +812,8 @@ static int crypto_bench_tx(void *arg) + * Calculate time and output the Mbps + */ + +- init_usecs = (init_time.tv_sec * 1000 * 1000) + init_time.tv_usec; +- comp_usecs = (comp_time.tv_sec * 1000 * 1000) + comp_time.tv_usec; ++ init_usecs = (init_time.tv_sec * 1000 * 1000) + (init_time.tv_nsec / NSEC_PER_USEC); ++ comp_usecs = (comp_time.tv_sec * 1000 * 1000) + (comp_time.tv_nsec / NSEC_PER_USEC); + delta_usecs = comp_usecs - init_usecs; + + reqs_completed = param.num_reqs - atomic_read(&tx_reqs); +@@ -870,7 +870,7 @@ static void crypto_bench_done(struct nss + nss_crypto_buf_free(crypto_hdl, buf); + + if (atomic_dec_and_test(&tx_reqs)) { +- do_gettimeofday(&comp_time); ++ ktime_get_real_ts64(&comp_time); + + wake_up_interruptible(&tx_comp); + param.num_loops--; diff --git a/qaa/nss/qca-nss-crypto/patches/200-fix-NULL-pointer-exception.patch b/qaa/nss/qca-nss-crypto/patches/200-fix-NULL-pointer-exception.patch new file mode 100644 index 000000000..6bd95109a --- /dev/null +++ b/qaa/nss/qca-nss-crypto/patches/200-fix-NULL-pointer-exception.patch @@ -0,0 +1,57 @@ +--- a/v1.0/src/nss_crypto_if.c ++++ b/v1.0/src/nss_crypto_if.c +@@ -370,15 +370,16 @@ void nss_crypto_transform_done(struct ne + struct nss_crypto_buf *buf = (struct nss_crypto_buf *)skb->data; + struct nss_crypto_buf_node *entry; + void *addr; ++ struct device *cdev = gbl_crypto_ctrl.eng[0].dev; + + if (likely(buf->data_in == buf->data_out)) { +- dma_unmap_single(NULL, buf->data_in, buf->data_len, DMA_BIDIRECTIONAL); ++ dma_unmap_single(cdev, buf->data_in, buf->data_len, DMA_BIDIRECTIONAL); + } else { +- dma_unmap_single(NULL, buf->data_in, buf->data_len, DMA_TO_DEVICE); +- dma_unmap_single(NULL, buf->data_out, buf->data_len, DMA_FROM_DEVICE); ++ dma_unmap_single(cdev, buf->data_in, buf->data_len, DMA_TO_DEVICE); ++ dma_unmap_single(cdev, buf->data_out, buf->data_len, DMA_FROM_DEVICE); + } + +- dma_unmap_single(NULL, buf->iv_addr, L1_CACHE_BYTES, DMA_BIDIRECTIONAL); ++ dma_unmap_single(cdev, buf->iv_addr, L1_CACHE_BYTES, DMA_BIDIRECTIONAL); + + addr = phys_to_virt(buf->iv_addr); + entry = container_of(addr, struct nss_crypto_buf_node, results); +@@ -531,6 +532,7 @@ nss_crypto_status_t nss_crypto_transform + uint32_t paddr; + void *vaddr; + size_t len; ++ struct device *cdev = gbl_crypto_ctrl.eng[0].dev; + + if (!buf->cb_fn) { + nss_crypto_warn("%p:no buffer(%p) callback present\n", crypto, buf); +@@ -544,7 +546,7 @@ nss_crypto_status_t nss_crypto_transform + */ + vaddr = (void *)buf->data_in; + len = buf->data_len; +- paddr = dma_map_single(NULL, vaddr, len, DMA_TO_DEVICE); ++ paddr = dma_map_single(cdev, vaddr, len, DMA_TO_DEVICE); + buf->data_in = paddr; + + if (vaddr == (void *)buf->data_out) { +@@ -555,14 +557,14 @@ nss_crypto_status_t nss_crypto_transform + */ + vaddr = (void *)buf->data_out; + len = buf->data_len; +- paddr = dma_map_single(NULL, vaddr, len, DMA_FROM_DEVICE); ++ paddr = dma_map_single(cdev, vaddr, len, DMA_FROM_DEVICE); + buf->data_out = paddr; + } + + /* + * We need to map the results into IV + */ +- paddr = dma_map_single(NULL, entry->results, L1_CACHE_BYTES, DMA_BIDIRECTIONAL); ++ paddr = dma_map_single(cdev, entry->results, L1_CACHE_BYTES, DMA_BIDIRECTIONAL); + buf->hash_addr = paddr; + buf->iv_addr = paddr; + diff --git a/qaa/nss/qca-nss-dp/Makefile b/qaa/nss/qca-nss-dp/Makefile new file mode 100644 index 000000000..8da7d314a --- /dev/null +++ b/qaa/nss/qca-nss-dp/Makefile @@ -0,0 +1,62 @@ +include $(TOPDIR)/rules.mk + +PKG_NAME:=qca-nss-dp +PKG_RELEASE:=$(AUTORELEASE) + +PKG_SOURCE_URL:=https://source.codeaurora.org/quic/cc-qrdk/oss/lklm/nss-dp +PKG_SOURCE_PROTO:=git +PKG_SOURCE_DATE:=2021-03-26 +PKG_SOURCE_VERSION:=e0c89348d5ad99559ce2fbe15d37b3b5bc66aa03 +PKG_MIRROR_HASH:=f369f0c3b33b5f4ad6d0a6ad6ac5495f63c9ecaf94e4e7fa345169f3e44fcf45 + +PKG_BUILD_PARALLEL:=1 + +include $(INCLUDE_DIR)/kernel.mk +include $(INCLUDE_DIR)/package.mk + +define KernelPackage/qca-nss-dp + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + DEPENDS:=@(TARGET_ipq807x||TARGET_ipq60xx) +kmod-qca-ssdk-nohnat + TITLE:=Kernel driver for NSS data plane + FILES:=$(PKG_BUILD_DIR)/qca-nss-dp.ko + AUTOLOAD:=$(call AutoLoad,31,qca-nss-dp) +endef + +define KernelPackage/qca-nss-dp/Description +This package contains a NSS data plane driver for QCA chipset +endef + +define Build/InstallDev + mkdir -p $(1)/usr/include/qca-nss-dp + $(CP) $(PKG_BUILD_DIR)/exports/* $(1)/usr/include/qca-nss-dp/ +endef + +EXTRA_CFLAGS+= \ + -I$(STAGING_DIR)/usr/include/qca-ssdk + +NSS_DP_HAL_DIR:=$(PKG_BUILD_DIR)/hal +define Build/Configure + $(LN) $(NSS_DP_HAL_DIR)/arch/$(CONFIG_TARGET_BOARD)/nss_$(CONFIG_TARGET_BOARD).h \ + $(PKG_BUILD_DIR)/exports/nss_dp_arch.h +endef + +ifeq ($(CONFIG_TARGET_BOARD), "ipq807x") + SOC="ipq807x_64" +else ifeq ($(CONFIG_TARGET_BOARD), "ipq60xx") + SOC="ipq60xx_64" +endif + +define Build/Compile + +$(MAKE) -C "$(LINUX_DIR)" \ + CROSS_COMPILE="$(TARGET_CROSS)" \ + ARCH="$(LINUX_KARCH)" \ + M="$(PKG_BUILD_DIR)" \ + EXTRA_CFLAGS="$(EXTRA_CFLAGS)" SoC="$(SOC)" \ + $(KERNEL_MAKE_FLAGS) \ + $(PKG_JOBS) \ + modules +endef + +$(eval $(call KernelPackage,qca-nss-dp)) diff --git a/qaa/nss/qca-nss-dp/patches/0001-edma_tx_rx-support-newer-kernels-time-stamping-API.patch b/qaa/nss/qca-nss-dp/patches/0001-edma_tx_rx-support-newer-kernels-time-stamping-API.patch new file mode 100644 index 000000000..15f6caa46 --- /dev/null +++ b/qaa/nss/qca-nss-dp/patches/0001-edma_tx_rx-support-newer-kernels-time-stamping-API.patch @@ -0,0 +1,44 @@ +From 40979666b4371012405715ffa61ab5760fcdc6b3 Mon Sep 17 00:00:00 2001 +Message-Id: <40979666b4371012405715ffa61ab5760fcdc6b3.1620066716.git.baruch@tkos.co.il> +From: Baruch Siach +Date: Mon, 3 May 2021 20:07:36 +0300 +Subject: [PATCH 1/3] edma_tx_rx: support newer kernels time stamping API + +--- + hal/edma/edma_tx_rx.c | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +--- a/hal/edma/edma_tx_rx.c ++++ b/hal/edma/edma_tx_rx.c +@@ -226,10 +226,16 @@ void nss_phy_tstamp_rx_buf(__attribute__ + * set to the correct PTP class value by calling ptp_classify_raw + * in drv->rxtstamp function. + */ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 6, 0)) + if (ndev && ndev->phydev && ndev->phydev->drv && + ndev->phydev->drv->rxtstamp) + if(ndev->phydev->drv->rxtstamp(ndev->phydev, skb, 0)) + return; ++#else ++ if (ndev && phy_has_rxtstamp(ndev->phydev)) ++ if (phy_rxtstamp(ndev->phydev, skb, 0)) ++ return; ++#endif + + netif_receive_skb(skb); + } +@@ -247,9 +253,14 @@ void nss_phy_tstamp_tx_buf(struct net_de + * set to the correct PTP class value by calling ptp_classify_raw + * in the drv->txtstamp function. + */ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 6, 0)) + if (ndev && ndev->phydev && ndev->phydev->drv && + ndev->phydev->drv->txtstamp) + ndev->phydev->drv->txtstamp(ndev->phydev, skb, 0); ++#else ++ if (ndev && phy_has_txtstamp(ndev->phydev)) ++ phy_rxtstamp(ndev->phydev, skb, 0); ++#endif + } + EXPORT_SYMBOL(nss_phy_tstamp_tx_buf); + diff --git a/qaa/nss/qca-nss-dp/patches/0002-nss_dp_main-make-phy-mode-code-compatible-with-newer.patch b/qaa/nss/qca-nss-dp/patches/0002-nss_dp_main-make-phy-mode-code-compatible-with-newer.patch new file mode 100644 index 000000000..a3305dd32 --- /dev/null +++ b/qaa/nss/qca-nss-dp/patches/0002-nss_dp_main-make-phy-mode-code-compatible-with-newer.patch @@ -0,0 +1,48 @@ +From cef7873a2d77df13ee702d902ed4e06b2248904b Mon Sep 17 00:00:00 2001 +Message-Id: +In-Reply-To: <40979666b4371012405715ffa61ab5760fcdc6b3.1620066716.git.baruch@tkos.co.il> +References: <40979666b4371012405715ffa61ab5760fcdc6b3.1620066716.git.baruch@tkos.co.il> +From: Baruch Siach +Date: Mon, 3 May 2021 20:17:22 +0300 +Subject: [PATCH 2/3] nss_dp_main: make phy mode code compatible with newer + kernels + +--- + include/nss_dp_dev.h | 4 ++-- + nss_dp_main.c | 4 ++++ + 2 files changed, 6 insertions(+), 2 deletions(-) + +--- a/include/nss_dp_dev.h ++++ b/include/nss_dp_dev.h +@@ -25,7 +25,7 @@ + #include + #include + #include +-#include ++#include + + #include "nss_dp_api_if.h" + #include "nss_dp_hal_if.h" +@@ -46,7 +46,7 @@ struct nss_dp_dev { + /* Phy related stuff */ + struct phy_device *phydev; /* Phy device */ + struct mii_bus *miibus; /* MII bus */ +- uint32_t phy_mii_type; /* RGMII/SGMII/QSGMII */ ++ phy_interface_t phy_mii_type; /* RGMII/SGMII/QSGMII */ + uint32_t phy_mdio_addr; /* Mdio address */ + bool link_poll; /* Link polling enable? */ + uint32_t forced_speed; /* Forced speed? */ +--- a/nss_dp_main.c ++++ b/nss_dp_main.c +@@ -463,7 +463,11 @@ static int32_t nss_dp_of_get_pdata(struc + hal_pdata->netdev = netdev; + hal_pdata->macid = dp_priv->macid; + ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 5, 0)) + dp_priv->phy_mii_type = of_get_phy_mode(np); ++#else ++ of_get_phy_mode(np, &dp_priv->phy_mii_type); ++#endif + dp_priv->link_poll = of_property_read_bool(np, "qcom,link-poll"); + if (of_property_read_u32(np, "qcom,phy-mdio-addr", + &dp_priv->phy_mdio_addr) && dp_priv->link_poll) { diff --git a/qaa/nss/qca-nss-dp/patches/0003-Drop-_nocache-variants-of-ioremap.patch b/qaa/nss/qca-nss-dp/patches/0003-Drop-_nocache-variants-of-ioremap.patch new file mode 100644 index 000000000..3139d349b --- /dev/null +++ b/qaa/nss/qca-nss-dp/patches/0003-Drop-_nocache-variants-of-ioremap.patch @@ -0,0 +1,48 @@ +From c8c52512ff48bee578901c381a42f027e79eadf9 Mon Sep 17 00:00:00 2001 +Message-Id: +In-Reply-To: <40979666b4371012405715ffa61ab5760fcdc6b3.1620066716.git.baruch@tkos.co.il> +References: <40979666b4371012405715ffa61ab5760fcdc6b3.1620066716.git.baruch@tkos.co.il> +From: Baruch Siach +Date: Mon, 3 May 2021 20:20:29 +0300 +Subject: [PATCH 3/3] Drop _nocache variants of ioremap() + +Recent kernels removed them. +--- + hal/edma/edma_data_plane.c | 2 +- + hal/gmac_hal_ops/qcom/qcom_if.c | 2 +- + hal/gmac_hal_ops/syn/xgmac/syn_if.c | 2 +- + 3 files changed, 3 insertions(+), 3 deletions(-) + +--- a/hal/edma/edma_data_plane.c ++++ b/hal/edma/edma_data_plane.c +@@ -797,7 +797,7 @@ int edma_init(void) + /* + * Remap register resource + */ +- edma_hw.reg_base = ioremap_nocache((edma_hw.reg_resource)->start, ++ edma_hw.reg_base = ioremap((edma_hw.reg_resource)->start, + resource_size(edma_hw.reg_resource)); + if (!edma_hw.reg_base) { + pr_warn("Unable to remap EDMA register memory.\n"); +--- a/hal/gmac_hal_ops/qcom/qcom_if.c ++++ b/hal/gmac_hal_ops/qcom/qcom_if.c +@@ -400,7 +400,7 @@ static void *qcom_init(struct gmac_hal_p + qhd->nghd.mac_id = gmacpdata->macid; + + /* Populate the mac base addresses */ +- qhd->nghd.mac_base = devm_ioremap_nocache(&dp_priv->pdev->dev, ++ qhd->nghd.mac_base = devm_ioremap(&dp_priv->pdev->dev, + res->start, resource_size(res)); + if (!qhd->nghd.mac_base) { + netdev_dbg(ndev, "ioremap fail.\n"); +--- a/hal/gmac_hal_ops/syn/xgmac/syn_if.c ++++ b/hal/gmac_hal_ops/syn/xgmac/syn_if.c +@@ -422,7 +422,7 @@ static void *syn_init(struct gmac_hal_pl + + /* Populate the mac base addresses */ + shd->nghd.mac_base = +- devm_ioremap_nocache(&dp_priv->pdev->dev, res->start, ++ devm_ioremap(&dp_priv->pdev->dev, res->start, + resource_size(res)); + if (!shd->nghd.mac_base) { + netdev_dbg(ndev, "ioremap fail.\n"); diff --git a/qaa/nss/qca-nss-dp/patches/0004-EDMA-Fix-NAPI-packet-counting.patch b/qaa/nss/qca-nss-dp/patches/0004-EDMA-Fix-NAPI-packet-counting.patch new file mode 100644 index 000000000..eb57fe90a --- /dev/null +++ b/qaa/nss/qca-nss-dp/patches/0004-EDMA-Fix-NAPI-packet-counting.patch @@ -0,0 +1,31 @@ +From d74920e2a7c413ef40eed72f9cf287cf6fbd5fb8 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Thu, 20 May 2021 14:56:46 +0200 +Subject: [PATCH 1/2] EDMA: Fix NAPI packet counting + +There is a bug in the NAPI packet counting that will +cause NAPI over budget warnings. + +Signed-off-by: Baruch Siach +Signed-off-by: Robert Marko +--- + hal/edma/edma_tx_rx.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/hal/edma/edma_tx_rx.c ++++ b/hal/edma/edma_tx_rx.c +@@ -458,12 +458,12 @@ int edma_napi(struct napi_struct *napi, + + for (i = 0; i < ehw->txcmpl_rings; i++) { + txcmpl_ring = &ehw->txcmpl_ring[i]; +- work_done += edma_clean_tx(ehw, txcmpl_ring); ++ edma_clean_tx(ehw, txcmpl_ring); + } + + for (i = 0; i < ehw->rxfill_rings; i++) { + rxfill_ring = &ehw->rxfill_ring[i]; +- work_done += edma_alloc_rx_buffer(ehw, rxfill_ring); ++ edma_alloc_rx_buffer(ehw, rxfill_ring); + } + + /* diff --git a/qaa/nss/qca-nss-dp/patches/0005-EDMA-Use-NAPI_POLL_WEIGHT-as-NAPI-weight.patch b/qaa/nss/qca-nss-dp/patches/0005-EDMA-Use-NAPI_POLL_WEIGHT-as-NAPI-weight.patch new file mode 100644 index 000000000..f231c514a --- /dev/null +++ b/qaa/nss/qca-nss-dp/patches/0005-EDMA-Use-NAPI_POLL_WEIGHT-as-NAPI-weight.patch @@ -0,0 +1,41 @@ +From 44a30d94abcbb10aacc21db29be212518a6b1bf7 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Thu, 20 May 2021 14:57:46 +0200 +Subject: [PATCH] EDMA: Use NAPI_POLL_WEIGHT as NAPI weight + +Currently a weight of 100 is used by the EDMA, according +to upstream max of 64 should be used and that is used for +almost any driver. + +They also introduced NAPI_POLL_WEIGHT define which equals +to 64. + +So use NAPI_POLL_WEIGHT as the weight. + +Signed-off-by: Robert Marko +--- + hal/edma/edma_data_plane.c | 2 +- + hal/edma/edma_data_plane.h | 1 - + 2 files changed, 1 insertion(+), 2 deletions(-) + +--- a/hal/edma/edma_data_plane.c ++++ b/hal/edma/edma_data_plane.c +@@ -582,7 +582,7 @@ static int edma_register_netdevice(struc + */ + if (!edma_hw.napi_added) { + netif_napi_add(netdev, &edma_hw.napi, edma_napi, +- EDMA_NAPI_WORK); ++ NAPI_POLL_WEIGHT); + /* + * Register the interrupt handlers and enable interrupts + */ +--- a/hal/edma/edma_data_plane.h ++++ b/hal/edma/edma_data_plane.h +@@ -27,7 +27,6 @@ + #define EDMA_RX_PREHDR_SIZE (sizeof(struct edma_rx_preheader)) + #define EDMA_TX_PREHDR_SIZE (sizeof(struct edma_tx_preheader)) + #define EDMA_RING_SIZE 128 +-#define EDMA_NAPI_WORK 100 + #define EDMA_START_GMACS NSS_DP_START_IFNUM + #define EDMA_MAX_GMACS NSS_DP_HAL_MAX_PORTS + #define EDMA_TX_PKT_MIN_SIZE 33 /* IPQ807x EDMA needs a minimum packet size of 33 bytes */ diff --git a/qaa/nss/qca-nss-dp/patches/0006-NSS-DP-fix-of_get_mac_address.patch b/qaa/nss/qca-nss-dp/patches/0006-NSS-DP-fix-of_get_mac_address.patch new file mode 100644 index 000000000..d4965716d --- /dev/null +++ b/qaa/nss/qca-nss-dp/patches/0006-NSS-DP-fix-of_get_mac_address.patch @@ -0,0 +1,50 @@ +From cadeb62a42296563141d6954eec58e34ef86778d Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Fri, 13 Aug 2021 20:12:08 +0200 +Subject: [PATCH] NSS-DP: fix of_get_mac_address() + +Recently OpenWrt backported the updated of_get_mac_address() +function which returns and error code instead. + +So, patch the SSDK to use it and fix the compilation error. + +Signed-off-by: Robert Marko +--- + nss_dp_main.c | 13 ++++--------- + 1 file changed, 4 insertions(+), 9 deletions(-) + +diff --git a/nss_dp_main.c b/nss_dp_main.c +index 5580b13..28df280 100644 +--- a/nss_dp_main.c ++++ b/nss_dp_main.c +@@ -434,9 +434,10 @@ static int32_t nss_dp_of_get_pdata(struct device_node *np, + struct net_device *netdev, + struct gmac_hal_platform_data *hal_pdata) + { +- uint8_t *maddr; ++ u8 maddr[ETH_ALEN]; + struct nss_dp_dev *dp_priv; + struct resource memres_devtree = {0}; ++ int ret; + + dp_priv = netdev_priv(netdev); + +@@ -475,14 +476,8 @@ static int32_t nss_dp_of_get_pdata(struct device_node *np, + of_property_read_u32(np, "qcom,forced-speed", &dp_priv->forced_speed); + of_property_read_u32(np, "qcom,forced-duplex", &dp_priv->forced_duplex); + +- maddr = (uint8_t *)of_get_mac_address(np); +-#if (LINUX_VERSION_CODE > KERNEL_VERSION(5, 4, 0)) +- if (IS_ERR((void *)maddr)) { +- maddr = NULL; +- } +-#endif +- +- if (maddr && is_valid_ether_addr(maddr)) { ++ ret = of_get_mac_address(np, maddr); ++ if (!ret && is_valid_ether_addr(maddr)) { + ether_addr_copy(netdev->dev_addr, maddr); + } else { + random_ether_addr(netdev->dev_addr); +-- +2.31.1 diff --git a/qaa/nss/qca-nss-drv-64/Makefile b/qaa/nss/qca-nss-drv-64/Makefile new file mode 100644 index 000000000..ac73475f7 --- /dev/null +++ b/qaa/nss/qca-nss-drv-64/Makefile @@ -0,0 +1,121 @@ +include $(TOPDIR)/rules.mk + +PKG_NAME:=qca-nss-drv-64 +PKG_RELEASE:=$(AUTORELEASE) + +PKG_SOURCE_URL:=https://source.codeaurora.org/quic/qsdk/oss/lklm/nss-drv +PKG_SOURCE_PROTO:=git +PKG_SOURCE_DATE:=2021-04-26 +PKG_SOURCE_VERSION:=1cf4bf81fd395f61648efeae78cdf1df60e954ff +PKG_MIRROR_HASH:=3dd84a548a530188021fd4dab54ca4e1eb9056ca77381b24f587365fc7c16f21 + +PKG_BUILD_PARALLEL:=1 + +include $(INCLUDE_DIR)/kernel.mk +include $(INCLUDE_DIR)/package.mk + +NSS_CLIENTS_DIR:=$(TOPDIR)/qca/src/qca-nss-clients + +define KernelPackage/qca-nss-drv-64 + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + DEPENDS:=@(TARGET_ipq807x||TARGET_ipq60xx) +kmod-qca-nss-dp + TITLE:=Kernel driver for NSS (core driver) + FILES:=$(PKG_BUILD_DIR)/qca-nss-drv.ko + AUTOLOAD:=$(call AutoLoad,32,qca-nss-drv) +endef + +define KernelPackage/qca-nss-drv-64/install + $(INSTALL_DIR) $(1)/lib/debug + $(INSTALL_DIR) $(1)/etc/init.d + $(INSTALL_DIR) $(1)/etc/sysctl.d + $(INSTALL_DIR) $(1)/etc/hotplug.d/firmware + $(INSTALL_DIR) $(1)/etc/config + + $(INSTALL_BIN) ./files/qca-nss-drv.debug $(1)/lib/debug/qca-nss-drv + $(INSTALL_BIN) ./files/qca-nss-drv.init $(1)/etc/init.d/qca-nss-drv + $(INSTALL_BIN) ./files/qca-nss-drv.sysctl $(1)/etc/sysctl.d/qca-nss-drv.conf + $(INSTALL_BIN) ./files/qca-nss-drv.hotplug $(1)/etc/hotplug.d/firmware/10-qca-nss-fw + $(INSTALL_BIN) ./files/qca-nss-drv.conf $(1)/etc/config/nss + +endef + +define KernelPackage/qca-nss-drv-64/Description +This package contains a NSS driver for QCA chipset +endef + +define Build/InstallDev + mkdir -p $(1)/usr/include/qca-nss-drv + $(CP) $(PKG_BUILD_DIR)/exports/* $(1)/usr/include/qca-nss-drv/ +endef + +EXTRA_CFLAGS+= -I$(STAGING_DIR)/usr/include/qca-nss-gmac -I$(STAGING_DIR)/usr/include/qca-nss-dp -I$(STAGING_DIR)/usr/include/qca-ssdk + +ifneq (, $(findstring $(CONFIG_TARGET_BOARD), "ipq807x" "ipq60xx")) +EXTRA_CFLAGS+= -DNSS_MEM_PROFILE_MEDIUM +LOW_MEM_PROFILE_MAKE_OPTS=y +endif + +ifeq ($(CONFIG_KERNEL_SKB_FIXED_SIZE_2K),y) +EXTRA_CFLAGS+= -DNSS_SKB_FIXED_SIZE_2K +endif + +DRV_MAKE_OPTS:= +ifeq ($(LOW_MEM_PROFILE_MAKE_OPTS),y) +DRV_MAKE_OPTS+=NSS_DRV_C2C_ENABLE=n \ + NSS_DRV_CAPWAP_ENABLE=n \ + NSS_DRV_CLMAP_ENABLE=n \ + NSS_DRV_CRYPTO_ENABLE=n \ + NSS_DRV_DTLS_ENABLE=n \ + NSS_DRV_GRE_ENABLE=n \ + NSS_DRV_GRE_REDIR_ENABLE=n \ + NSS_DRV_GRE_TUNNEL_ENABLE=n \ + NSS_DRV_IGS_ENABLE=n \ + NSS_DRV_IPSEC_ENABLE=n \ + NSS_DRV_LAG_ENABLE=n \ + NSS_DRV_L2TP_ENABLE=n \ + NSS_DRV_MAPT_ENABLE=n \ + NSS_DRV_OAM_ENABLE=n \ + NSS_DRV_PPTP_ENABLE=n \ + NSS_DRV_PORTID_ENABLE=n \ + NSS_DRV_PVXLAN_ENABLE=n \ + NSS_DRV_QRFS_ENABLE=n \ + NSS_DRV_QVPN_ENABLE=n \ + NSS_DRV_RMNET_ENABLE=n \ + NSS_DRV_SHAPER_ENABLE=n \ + NSS_DRV_SJACK_ENABLE=n \ + NSS_DRV_TLS_ENABLE=n \ + NSS_DRV_TRUSTSEC_ENABLE=n \ + NSS_DRV_TSTAMP_ENABLE=n \ + NSS_DRV_TUN6RD_ENABLE=n \ + NSS_DRV_TUNIPIP6_ENABLE=n \ + NSS_DRV_VXLAN_ENABLE=n \ + NSS_DRV_MATCH_ENABLE=n \ + NSS_DRV_MIRROR_ENABLE=n +endif + +ifeq ($(CONFIG_TARGET_BOARD), "ipq807x") + SOC="ipq807x_64" +else ifeq ($(CONFIG_TARGET_BOARD), "ipq60xx") + SOC="ipq60xx_64" +endif + +define Build/Configure + $(LN) arch/nss_$(SOC).h $(PKG_BUILD_DIR)/exports/nss_arch.h + sed -i "s/define NSS_FW_VERSION_MAJOR.*/define NSS_FW_VERSION_MAJOR 11/" $(PKG_BUILD_DIR)/exports/nss_fw_version.h + sed -i "s/define NSS_FW_VERSION_MINOR.*/define NSS_FW_VERSION_MINOR 3/" $(PKG_BUILD_DIR)/exports/nss_fw_version.h +endef + +define Build/Compile + +$(MAKE) -C "$(LINUX_DIR)" $(strip $(DRV_MAKE_OPTS)) \ + CROSS_COMPILE="$(TARGET_CROSS)" \ + ARCH="$(LINUX_KARCH)" \ + M="$(PKG_BUILD_DIR)" \ + EXTRA_CFLAGS="$(EXTRA_CFLAGS)" SoC=$(SOC) \ + $(KERNEL_MAKE_FLAGS) \ + $(PKG_JOBS) \ + modules +endef + +$(eval $(call KernelPackage,qca-nss-drv-64)) diff --git a/qaa/nss/qca-nss-drv-64/files/qca-nss-drv.conf b/qaa/nss/qca-nss-drv-64/files/qca-nss-drv.conf new file mode 100644 index 000000000..a8a1fbf40 --- /dev/null +++ b/qaa/nss/qca-nss-drv-64/files/qca-nss-drv.conf @@ -0,0 +1,6 @@ +config nss_firmware 'qca_nss_0' + +config nss_firmware 'qca_nss_1' + +config general + option enable_rps '1' diff --git a/qaa/nss/qca-nss-drv-64/files/qca-nss-drv.debug b/qaa/nss/qca-nss-drv-64/files/qca-nss-drv.debug new file mode 100644 index 000000000..5d435c3a7 --- /dev/null +++ b/qaa/nss/qca-nss-drv-64/files/qca-nss-drv.debug @@ -0,0 +1,26 @@ +#!/bin/sh /sbin/sysdebug +# +# Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +# + +log cat /sys/kernel/debug/qca-nss-drv/stats/pppoe +log cat /sys/kernel/debug/qca-nss-drv/stats/n2h +log cat /sys/kernel/debug/qca-nss-drv/stats/ipv6 +log cat /sys/kernel/debug/qca-nss-drv/stats/ipv4 +log cat /sys/kernel/debug/qca-nss-drv/stats/gmac +log cat /sys/kernel/debug/qca-nss-drv/stats/drv +log cat /sys/kernel/debug/qca-nss-drv/stats/wifi +log cat /sys/kernel/debug/qca-nss-drv/stats/wifi_if +log cat /sys/kernel/debug/qca-nss-drv/stats/eth_rx diff --git a/qaa/nss/qca-nss-drv-64/files/qca-nss-drv.hotplug b/qaa/nss/qca-nss-drv-64/files/qca-nss-drv.hotplug new file mode 100644 index 000000000..1e4813838 --- /dev/null +++ b/qaa/nss/qca-nss-drv-64/files/qca-nss-drv.hotplug @@ -0,0 +1,70 @@ +#!/bin/sh +# +# Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +# + +KERNEL=`uname -r` +case "${KERNEL}" in + 3.4*) + select_or_load=load_nss_fw + ;; + *) + select_or_load=select_nss_fw + ;; +esac + +load_nss_fw () { + ls -l $1 | awk ' { print $9,$5 } '> /dev/console + echo 1 > /sys/class/firmware/$DEVICENAME/loading + cat $1 > /sys/class/firmware/$DEVICENAME/data + echo 0 > /sys/class/firmware/$DEVICENAME/loading +} + +select_nss_fw () { + rm -f /lib/firmware/$DEVICENAME + ln -s $1 /lib/firmware/$DEVICENAME + ls -l /lib/firmware/$DEVICENAME | awk ' { print $9,$5 } '> /dev/console +} + +[ "$ACTION" != "add" ] && exit + +# dev name for UCI, since it doesn't let you use . or - +SDEVNAME=$(echo ${DEVICENAME} | sed s/[.-]/_/g) + +SELECTED_FW=$(uci get nss.${SDEVNAME}.firmware 2>/dev/null) +[ -e "${SELECTED_FW}" ] && { + $select_or_load ${SELECTED_FW} + exit +} + +case $DEVICENAME in + qca-nss0* | qca-nss.0*) + if [ -e /lib/firmware/qca-nss0-enterprise.bin ] ; then + $select_or_load /lib/firmware/qca-nss0-enterprise.bin + else + $select_or_load /lib/firmware/qca-nss0-retail.bin + fi + exit + ;; + qca-nss1* | qca-nss.1*) + if [ -e /lib/firmware/qca-nss1-enterprise.bin ] ; then + $select_or_load /lib/firmware/qca-nss1-enterprise.bin + else + $select_or_load /lib/firmware/qca-nss1-retail.bin + fi + exit + ;; +esac + diff --git a/qaa/nss/qca-nss-drv-64/files/qca-nss-drv.init b/qaa/nss/qca-nss-drv-64/files/qca-nss-drv.init new file mode 100644 index 000000000..de12cb6d1 --- /dev/null +++ b/qaa/nss/qca-nss-drv-64/files/qca-nss-drv.init @@ -0,0 +1,50 @@ +#!/bin/sh /etc/rc.common +# +# Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +# + +START=70 + +enable_rps() { + irq_nss_rps=`grep nss_queue1 /proc/interrupts | cut -d ':' -f 1 | tr -d ' '` + for entry in $irq_nss_rps + do + echo 2 > /proc/irq/$entry/smp_affinity + done + + irq_nss_rps=`grep nss_queue2 /proc/interrupts | cut -d ':' -f 1 | tr -d ' '` + for entry in $irq_nss_rps + do + echo 4 > /proc/irq/$entry/smp_affinity + done + + irq_nss_rps=`grep nss_queue3 /proc/interrupts | cut -d ':' -f 1 | tr -d ' '` + for entry in $irq_nss_rps + do + echo 8 > /proc/irq/$entry/smp_affinity + done + + # Enable NSS RPS + sysctl -w dev.nss.rps.enable=1 >/dev/null 2>/dev/null + +} + + +start() { + local rps_enabled="$(uci_get nss @general[0] enable_rps)" + if [ "$rps_enabled" -eq 1 ]; then + enable_rps + fi +} diff --git a/qaa/nss/qca-nss-drv-64/files/qca-nss-drv.sysctl b/qaa/nss/qca-nss-drv-64/files/qca-nss-drv.sysctl new file mode 100644 index 000000000..fc36c33eb --- /dev/null +++ b/qaa/nss/qca-nss-drv-64/files/qca-nss-drv.sysctl @@ -0,0 +1,4 @@ +# Default Number of connection configuration +dev.nss.ipv4cfg.ipv4_conn=4096 +dev.nss.ipv6cfg.ipv6_conn=4096 + diff --git a/qaa/nss/qca-nss-drv-64/patches/0001-core-add-5.10-kernel-to-version-check.patch b/qaa/nss/qca-nss-drv-64/patches/0001-core-add-5.10-kernel-to-version-check.patch new file mode 100644 index 000000000..3fea9b5ce --- /dev/null +++ b/qaa/nss/qca-nss-drv-64/patches/0001-core-add-5.10-kernel-to-version-check.patch @@ -0,0 +1,25 @@ +From 3885c752e12f74cad6c97888b797e5903ad1930d Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Thu, 13 May 2021 23:22:38 +0200 +Subject: [PATCH] core: add 5.10 kernel to version check + +NSS DRV has a kernel version check, so simply add +5.10 as supported. + +Signed-off-by: Robert Marko +--- + nss_core.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/nss_core.c ++++ b/nss_core.c +@@ -52,7 +52,8 @@ + (((LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0)))) || \ + (((LINUX_VERSION_CODE >= KERNEL_VERSION(3, 18, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 19, 0)))) || \ + (((LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(4, 5, 0)))) || \ +-(((LINUX_VERSION_CODE >= KERNEL_VERSION(5, 4, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 5, 0)))))) ++(((LINUX_VERSION_CODE >= KERNEL_VERSION(5, 4, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 5, 0)))) || \ ++(((LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 11, 0)))))) + #error "Check skb recycle code in this file to match Linux version" + #endif + diff --git a/qaa/nss/qca-nss-drv-64/patches/0002-nss-drv-replace-ioremap_nocache-with-ioremap.patch b/qaa/nss/qca-nss-drv-64/patches/0002-nss-drv-replace-ioremap_nocache-with-ioremap.patch new file mode 100644 index 000000000..77155750c --- /dev/null +++ b/qaa/nss/qca-nss-drv-64/patches/0002-nss-drv-replace-ioremap_nocache-with-ioremap.patch @@ -0,0 +1,164 @@ +From b5e2a7167ca3df9fce34f0d7c05468d4f5597275 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Thu, 13 May 2021 23:33:18 +0200 +Subject: [PATCH] nss-drv: replace ioremap_nocache() with ioremap() + +ioremap_nocache() does not exist anymore. + +Signed-off-by: Robert Marko +--- + nss_hal/ipq50xx/nss_hal_pvt.c | 6 +++--- + nss_hal/ipq60xx/nss_hal_pvt.c | 8 ++++---- + nss_hal/ipq806x/nss_hal_pvt.c | 4 ++-- + nss_hal/ipq807x/nss_hal_pvt.c | 6 +++--- + nss_hal/nss_hal.c | 4 ++-- + nss_meminfo.c | 2 +- + nss_ppe.c | 2 +- + 7 files changed, 16 insertions(+), 16 deletions(-) + +--- a/nss_hal/ipq50xx/nss_hal_pvt.c ++++ b/nss_hal/ipq50xx/nss_hal_pvt.c +@@ -184,13 +184,13 @@ static struct nss_platform_data *__nss_h + npd->nphys = res_nphys.start; + npd->qgic_phys = res_qgic_phys.start; + +- npd->nmap = ioremap_nocache(npd->nphys, resource_size(&res_nphys)); ++ npd->nmap = ioremap(npd->nphys, resource_size(&res_nphys)); + if (!npd->nmap) { + nss_info_always("%px: nss%d: ioremap() fail for nphys\n", nss_ctx, nss_ctx->id); + goto out; + } + +- npd->qgic_map = ioremap_nocache(npd->qgic_phys, resource_size(&res_qgic_phys)); ++ npd->qgic_map = ioremap(npd->qgic_phys, resource_size(&res_qgic_phys)); + if (!npd->qgic_map) { + nss_info_always("%px: nss%d: ioremap() fail for qgic map\n", nss_ctx, nss_ctx->id); + goto out; +@@ -348,7 +348,7 @@ static int __nss_hal_common_reset(struct + + of_node_put(cmn); + +- nss_misc_reset = ioremap_nocache(res_nss_misc_reset.start, resource_size(&res_nss_misc_reset)); ++ nss_misc_reset = ioremap(res_nss_misc_reset.start, resource_size(&res_nss_misc_reset)); + if (!nss_misc_reset) { + pr_err("%px: ioremap fail for nss_misc_reset\n", nss_dev); + return -EFAULT; +--- a/nss_hal/ipq60xx/nss_hal_pvt.c ++++ b/nss_hal/ipq60xx/nss_hal_pvt.c +@@ -207,13 +207,13 @@ static struct nss_platform_data *__nss_h + npd->nphys = res_nphys.start; + npd->qgic_phys = res_qgic_phys.start; + +- npd->nmap = ioremap_nocache(npd->nphys, resource_size(&res_nphys)); ++ npd->nmap = ioremap(npd->nphys, resource_size(&res_nphys)); + if (!npd->nmap) { + nss_info_always("%px: nss%d: ioremap() fail for nphys\n", nss_ctx, nss_ctx->id); + goto out; + } + +- npd->qgic_map = ioremap_nocache(npd->qgic_phys, resource_size(&res_qgic_phys)); ++ npd->qgic_map = ioremap(npd->qgic_phys, resource_size(&res_qgic_phys)); + if (!npd->qgic_map) { + nss_info_always("%px: nss%d: ioremap() fail for qgic map\n", nss_ctx, nss_ctx->id); + goto out; +@@ -433,13 +433,13 @@ static int __nss_hal_common_reset(struct + + of_node_put(cmn); + +- nss_misc_reset = ioremap_nocache(res_nss_misc_reset.start, resource_size(&res_nss_misc_reset)); ++ nss_misc_reset = ioremap(res_nss_misc_reset.start, resource_size(&res_nss_misc_reset)); + if (!nss_misc_reset) { + pr_err("%px: ioremap fail for nss_misc_reset\n", nss_dev); + return -EFAULT; + } + +- nss_misc_reset_flag = ioremap_nocache(res_nss_misc_reset_flag.start, resource_size(&res_nss_misc_reset_flag)); ++ nss_misc_reset_flag = ioremap(res_nss_misc_reset_flag.start, resource_size(&res_nss_misc_reset_flag)); + if (!nss_misc_reset_flag) { + pr_err("%px: ioremap fail for nss_misc_reset_flag\n", nss_dev); + return -EFAULT; +--- a/nss_hal/ipq806x/nss_hal_pvt.c ++++ b/nss_hal/ipq806x/nss_hal_pvt.c +@@ -458,7 +458,7 @@ static struct nss_platform_data *__nss_h + npd->nphys = res_nphys.start; + npd->vphys = res_vphys.start; + +- npd->nmap = ioremap_nocache(npd->nphys, resource_size(&res_nphys)); ++ npd->nmap = ioremap(npd->nphys, resource_size(&res_nphys)); + if (!npd->nmap) { + nss_info_always("%px: nss%d: ioremap() fail for nphys\n", nss_ctx, nss_ctx->id); + goto out; +@@ -711,7 +711,7 @@ static int __nss_hal_common_reset(struct + } + of_node_put(cmn); + +- fpb_base = ioremap_nocache(res_nss_fpb_base.start, resource_size(&res_nss_fpb_base)); ++ fpb_base = ioremap(res_nss_fpb_base.start, resource_size(&res_nss_fpb_base)); + if (!fpb_base) { + pr_err("%px: ioremap fail for nss_fpb_base\n", nss_dev); + return -EFAULT; +--- a/nss_hal/ipq807x/nss_hal_pvt.c ++++ b/nss_hal/ipq807x/nss_hal_pvt.c +@@ -234,7 +234,7 @@ static struct nss_platform_data *__nss_h + npd->vphys = res_vphys.start; + npd->qgic_phys = res_qgic_phys.start; + +- npd->nmap = ioremap_nocache(npd->nphys, resource_size(&res_nphys)); ++ npd->nmap = ioremap(npd->nphys, resource_size(&res_nphys)); + if (!npd->nmap) { + nss_info_always("%px: nss%d: ioremap() fail for nphys\n", nss_ctx, nss_ctx->id); + goto out; +@@ -247,7 +247,7 @@ static struct nss_platform_data *__nss_h + goto out; + } + +- npd->qgic_map = ioremap_nocache(npd->qgic_phys, resource_size(&res_qgic_phys)); ++ npd->qgic_map = ioremap(npd->qgic_phys, resource_size(&res_qgic_phys)); + if (!npd->qgic_map) { + nss_info_always("%px: nss%d: ioremap() fail for qgic map\n", nss_ctx, nss_ctx->id); + goto out; +@@ -467,7 +467,7 @@ static int __nss_hal_common_reset(struct + } + of_node_put(cmn); + +- nss_misc_reset = ioremap_nocache(res_nss_misc_reset.start, resource_size(&res_nss_misc_reset)); ++ nss_misc_reset = ioremap(res_nss_misc_reset.start, resource_size(&res_nss_misc_reset)); + if (!nss_misc_reset) { + pr_err("%px: ioremap fail for nss_misc_reset\n", nss_dev); + return -EFAULT; +--- a/nss_hal/nss_hal.c ++++ b/nss_hal/nss_hal.c +@@ -78,9 +78,9 @@ int nss_hal_firmware_load(struct nss_ctx + return rc; + } + +- load_mem = ioremap_nocache(npd->load_addr, nss_fw->size); ++ load_mem = ioremap(npd->load_addr, nss_fw->size); + if (!load_mem) { +- nss_info_always("%px: ioremap_nocache failed: %x", nss_ctx, npd->load_addr); ++ nss_info_always("%px: ioremap failed: %x", nss_ctx, npd->load_addr); + release_firmware(nss_fw); + return rc; + } +--- a/nss_meminfo.c ++++ b/nss_meminfo.c +@@ -728,7 +728,7 @@ bool nss_meminfo_init(struct nss_ctx_ins + /* + * meminfo_start is the label where the start address of meminfo map is stored. + */ +- meminfo_start = (uint32_t *)ioremap_nocache(nss_ctx->load + NSS_MEMINFO_MAP_START_OFFSET, ++ meminfo_start = (uint32_t *)ioremap(nss_ctx->load + NSS_MEMINFO_MAP_START_OFFSET, + NSS_MEMINFO_RESERVE_AREA_SIZE); + if (!meminfo_start) { + nss_info_always("%px: cannot remap meminfo start\n", nss_ctx); +--- a/nss_ppe.c ++++ b/nss_ppe.c +@@ -357,7 +357,7 @@ void nss_ppe_init(void) + /* + * Get the PPE base address + */ +- ppe_pvt.ppe_base = ioremap_nocache(PPE_BASE_ADDR, PPE_REG_SIZE); ++ ppe_pvt.ppe_base = ioremap(PPE_BASE_ADDR, PPE_REG_SIZE); + if (!ppe_pvt.ppe_base) { + nss_warning("DRV can't get PPE base address\n"); + return; diff --git a/qaa/nss/qca-nss-drv-64/patches/0003-DMA-Fix-NULL-pointer-exceptions.patch b/qaa/nss/qca-nss-drv-64/patches/0003-DMA-Fix-NULL-pointer-exceptions.patch new file mode 100644 index 000000000..0c13a7887 --- /dev/null +++ b/qaa/nss/qca-nss-drv-64/patches/0003-DMA-Fix-NULL-pointer-exceptions.patch @@ -0,0 +1,49 @@ +From 62e457f262aaa0db7113ad3ccbcb7ae49d4d7ea8 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Tue, 8 Jun 2021 23:24:43 +0200 +Subject: [PATCH] DMA: Fix NULL pointer exceptions + +There are multiple instances that pass NULL instead +of device to DMA functions. +That is incorrect and will cause kernel NULL pointer +exceptions. + +So, simply pass the device structure pointers. + +Signed-off-by: Robert Marko +--- + nss_core.c | 2 +- + nss_coredump.c | 4 ++-- + 2 files changed, 3 insertions(+), 3 deletions(-) + +--- a/nss_core.c ++++ b/nss_core.c +@@ -1617,7 +1617,7 @@ static int32_t nss_core_handle_cause_que + * + */ + if (unlikely((buffer_type == N2H_BUFFER_CRYPTO_RESP))) { +- dma_unmap_single(NULL, (desc->buffer + desc->payload_offs), desc->payload_len, DMA_FROM_DEVICE); ++ dma_unmap_single(nss_ctx->dev, (desc->buffer + desc->payload_offs), desc->payload_len, DMA_FROM_DEVICE); + goto consume; + } + +--- a/nss_coredump.c ++++ b/nss_coredump.c +@@ -154,7 +154,7 @@ void nss_fw_coredump_notify(struct nss_c + dma_addr = nss_own->meminfo_ctx.logbuffer_dma; + } + +- dma_sync_single_for_cpu(NULL, dma_addr, sizeof(struct nss_log_descriptor), DMA_FROM_DEVICE); ++ dma_sync_single_for_cpu(nss_own->dev, dma_addr, sizeof(struct nss_log_descriptor), DMA_FROM_DEVICE); + + /* + * If the current entry is smaller than or equal to the number of NSS_LOG_COREDUMP_LINE_NUM, +@@ -181,7 +181,7 @@ void nss_fw_coredump_notify(struct nss_c + + offset = (index * sizeof(struct nss_log_entry)) + + offsetof(struct nss_log_descriptor, log_ring_buffer); +- dma_sync_single_for_cpu(NULL, dma_addr + offset, ++ dma_sync_single_for_cpu(nss_own->dev, dma_addr + offset, + sizeof(struct nss_log_entry), DMA_FROM_DEVICE); + nss_info_always("%px: %s\n", nss_own, nle_print->message); + nle_print++; diff --git a/qaa/nss/qca-nss-drv-64/patches/999-treewide-hack-support-for-mismatched-firmware.patch b/qaa/nss/qca-nss-drv-64/patches/999-treewide-hack-support-for-mismatched-firmware.patch new file mode 100644 index 000000000..46025b823 --- /dev/null +++ b/qaa/nss/qca-nss-drv-64/patches/999-treewide-hack-support-for-mismatched-firmware.patch @@ -0,0 +1,344 @@ +From d0bffc800a50305315a0d7cf37140291ef5b1b61 Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Thu, 27 May 2021 03:52:47 +0200 +Subject: [PATCH] treewide: hack support for mismatched firmware + +Make new qsdk feature configurable to support old half compatible +firmware. + +Signed-off-by: Ansuel Smith +--- + exports/nss_fw_version.h | 11 +++++++++++ + exports/nss_ipv4.h | 8 ++++++++ + exports/nss_ipv6.h | 7 +++++++ + exports/nss_wifi_vdev.h | 14 ++++++++++++++ + exports/nss_wifili_if.h | 8 ++++++++ + nss_ipv4_stats.c | 2 ++ + nss_ipv4_strings.c | 2 ++ + nss_ipv6_stats.c | 2 ++ + nss_ipv6_strings.c | 2 ++ + 9 files changed, 56 insertions(+) + create mode 100644 exports/nss_fw_version.h + +diff --git a/exports/nss_fw_version.h b/exports/nss_fw_version.h +new file mode 100644 +index 0000000..895d523 +--- /dev/null ++++ b/exports/nss_fw_version.h +@@ -0,0 +1,11 @@ ++#ifndef __NSS_FW_VERSION_H ++#define __NSS_FW_VERSION_H ++ ++#define NSS_FW_VERSION_MAJOR 11 ++#define NSS_FW_VERSION_MINOR 4 ++ ++#define NSS_FW_VERSION(a,b) (((a) << 8) + (b)) ++ ++#define NSS_FW_VERSION_CODE NSS_FW_VERSION(NSS_FW_VERSION_MAJOR, NSS_FW_VERSION_MINOR) ++ ++#endif /* __NSS_FW_VERSION_H */ +\ No newline at end of file +diff --git a/exports/nss_ipv4.h b/exports/nss_ipv4.h +index ee3a552..25c4d82 100644 +--- a/exports/nss_ipv4.h ++++ b/exports/nss_ipv4.h +@@ -26,6 +26,8 @@ + #include "nss_stats_public.h" + #endif + ++#include "nss_fw_version.h" ++ + /** + * @addtogroup nss_ipv4_subsystem + * @{ +@@ -216,12 +218,14 @@ enum nss_ipv4_stats_types { + /**< Number of IPv4 multicast connection destroy requests that missed the cache. */ + NSS_IPV4_STATS_MC_CONNECTION_FLUSHES, + /**< Number of IPv4 multicast connection flushes. */ ++#if (NSS_FW_VERSION_CODE > NSS_FW_VERSION(11,3)) + NSS_IPV4_STATS_CONNECTION_CREATE_INVALID_MIRROR_IFNUM, + /**< Number of IPv4 mirror connection requests with an invalid interface number. */ + NSS_IPV4_STATS_CONNECTION_CREATE_INVALID_MIRROR_IFTYPE, + /**< Number of IPv4 mirror connection requests with an invalid interface type. */ + NSS_IPV4_STATS_MIRROR_FAILURES, + /**< Number of IPv4 mirror failures. */ ++#endif + NSS_IPV4_STATS_MAX, + /**< Maximum message type. */ + }; +@@ -609,8 +613,10 @@ struct nss_ipv4_rule_create_msg { + /**< Ingress shaping related accleration parameters. */ + struct nss_ipv4_identifier_rule identifier; + /**< Rule for adding identifier. */ ++#if (NSS_FW_VERSION_CODE > NSS_FW_VERSION(11,3)) + struct nss_ipv4_mirror_rule mirror_rule; + /**< Mirror rule parameter. */ ++#endif + }; + + /** +@@ -955,6 +961,7 @@ struct nss_ipv4_node_sync { + uint32_t ipv4_mc_connection_flushes; + /**< Number of multicast connection flushes. */ + ++#if (NSS_FW_VERSION_CODE > NSS_FW_VERSION(11,3)) + uint32_t ipv4_connection_create_invalid_mirror_ifnum; + /**< Number of create request failed with an invalid mirror interface number. */ + +@@ -963,6 +970,7 @@ struct nss_ipv4_node_sync { + + uint32_t ipv4_mirror_failures; + /**< Mirror packet failed. */ ++#endif + + uint32_t exception_events[NSS_IPV4_EXCEPTION_EVENT_MAX]; + /**< Number of exception events. */ +diff --git a/exports/nss_ipv6.h b/exports/nss_ipv6.h +index 930e74c..a21f939 100644 +--- a/exports/nss_ipv6.h ++++ b/exports/nss_ipv6.h +@@ -195,6 +195,8 @@ enum nss_ipv6_stats_types { + /**< Number of IPv6 multicast connection destroy requests that missed the cache. */ + NSS_IPV6_STATS_MC_CONNECTION_FLUSHES, + /**< Number of IPv6 multicast connection flushes. */ ++ ++#if (NSS_FW_VERSION_CODE > NSS_FW_VERSION(11,3)) + NSS_IPV6_STATS_CONNECTION_CREATE_INVALID_MIRROR_IFNUM, + /**< Number of IPv6 mirror connection requests with an invalid interface number. */ + NSS_IPV6_STATS_CONNECTION_CREATE_INVALID_MIRROR_IFTYPE, +@@ -202,6 +204,7 @@ enum nss_ipv6_stats_types { + + NSS_IPV6_STATS_MIRROR_FAILURES, + /**< Number of IPv6 mirror failures. */ ++#endif + + NSS_IPV6_STATS_MAX, + /**< Maximum message type. */ +@@ -702,8 +705,10 @@ struct nss_ipv6_rule_create_msg { + /**< Ingress shaping related accleration parameters. */ + struct nss_ipv6_identifier_rule identifier; + /**< Rule for adding identifier. */ ++#if (NSS_FW_VERSION_CODE > NSS_FW_VERSION(11,3)) + struct nss_ipv6_mirror_rule mirror_rule; + /**< Mirror rule parameter. */ ++#endif + }; + + /** +@@ -950,6 +955,7 @@ struct nss_ipv6_node_sync { + uint32_t ipv6_mc_connection_flushes; + /**< Number of multicast connection flushes. */ + ++#if (NSS_FW_VERSION_CODE > NSS_FW_VERSION(11,3)) + uint32_t ipv6_connection_create_invalid_mirror_ifnum; + /**< Number of create request failed with an invalid mirror interface number. */ + +@@ -958,6 +964,7 @@ struct nss_ipv6_node_sync { + + uint32_t ipv6_mirror_failures; + /**< Mirror packet failed. */ ++#endif + + uint32_t exception_events[NSS_IPV6_EXCEPTION_EVENT_MAX]; + /**< Number of exception events. */ +diff --git a/exports/nss_wifi_vdev.h b/exports/nss_wifi_vdev.h +index 1b52f66..da91b56 100644 +--- a/exports/nss_wifi_vdev.h ++++ b/exports/nss_wifi_vdev.h +@@ -74,8 +74,10 @@ enum nss_wifi_vdev_msg_types { + NSS_WIFI_VDEV_INTERFACE_RECOVERY_RESET_MSG, + NSS_WIFI_VDEV_INTERFACE_RECOVERY_RECONF_MSG, + NSS_WIFI_VDEV_SET_GROUP_KEY, ++#if (NSS_FW_VERSION_CODE > NSS_FW_VERSION(11,3)) + NSS_WIFI_VDEV_HMMC_MEMBER_ADD_MSG, + NSS_WIFI_VDEV_HMMC_MEMBER_DEL_MSG, ++#endif + NSS_WIFI_VDEV_MAX_MSG + }; + +@@ -130,6 +132,7 @@ enum nss_wifi_vdev_err_types { + NSS_WIFI_VDEV_VLAN_MODE_CONFIG_FAIL, + NSS_WIFI_VDEV_RECOVERY_RESET_FAIL, + NSS_WIFI_VDEV_RECOVERY_RECONF_FAIL, ++#if (NSS_FW_VERSION_CODE > NSS_FW_VERSION(11,3)) + NSS_WIFI_VDEV_CONFIG_GROUP_KEY_FAIL, + NSS_WIFI_VDEV_MULTIPASS_NOT_ENABLED, + NSS_WIFI_VDEV_ALLOC_VLAN_MAP_FAILED, +@@ -139,6 +142,7 @@ enum nss_wifi_vdev_err_types { + NSS_WIFI_VDEV_PPE_PORT_DESTROY_FAIL, + NSS_WIFI_VDEV_PPE_VSI_ASSIGN_FAIL, + NSS_WIFI_VDEV_PPE_VSI_UNASSIGN_FAIL, ++#endif + NSS_WIFI_VDEV_EINV_MAX_CFG + }; + +@@ -161,11 +165,13 @@ enum nss_wifi_vdev_ext_data_pkt_type { + NSS_WIFI_VDEV_EXT_TX_COMPL_PKT_TYPE = 11, /**< Tx completion. */ + NSS_WIFI_VDEV_EXT_DATA_PKT_TYPE_WDS_LEARN = 12, /**< WDS source port learning command. */ + NSS_WIFI_VDEV_EXT_DATA_PPDU_INFO = 13, /**< PPDU metadata information. */ ++#if (NSS_FW_VERSION_CODE > NSS_FW_VERSION(11,3)) + NSS_WIFI_VDEV_EXT_DATA_PKT_TYPE_MCBC_RX = 14, /**< Multicast/broadcast packet received. */ + NSS_WIFI_VDEV_MESH_EXT_DATA_PKT_TYPE_RX_SPL_PACKET = 15, + /**< Mesh link VAP special packet. */ + NSS_WIFI_VDEV_MESH_EXT_DATA_PKT_TYPE_RX_MCAST_EXC = 16, + /**< Mesh link VAP multicast packet. */ ++#endif + NSS_WIFI_VDEV_EXT_DATA_PKT_TYPE_MAX + }; + +@@ -201,9 +207,11 @@ enum nss_wifi_vdev_cmd { + NSS_WIFI_VDEV_ENABLE_IGMP_ME_CMD, /**< Configuration to set IGMP multicast enhancement on VAP. */ + NSS_WIFI_VDEV_CFG_WDS_BACKHAUL_CMD, + /**< Configuration to set WDS backhaul extension on VAP. */ ++#if (NSS_FW_VERSION_CODE > NSS_FW_VERSION(11,3)) + NSS_WIFI_VDEV_CFG_MCBC_EXC_TO_HOST_CMD, /**< Configuration to set multicast/broadcast exception to host on VAP. */ + NSS_WIFI_VDEV_CFG_PEER_AUTHORIZE_CMD, + /**< Configuration to enable peer authorization on VAP. */ ++#endif + NSS_WIFI_VDEV_MAX_CMD + }; + +@@ -271,7 +279,9 @@ struct nss_wifi_vdev_config_msg { + uint8_t is_nss_qwrap_en; /**< VAP is configured for NSS firmware QWRAP logic. */ + uint8_t tx_per_pkt_vdev_id_check; /**< Transmit per-packet virtual device ID check. */ + uint8_t align_pad; /**< Reserved field. */ ++#if (NSS_FW_VERSION_CODE > NSS_FW_VERSION(11,3)) + uint32_t vap_ext_mode; /**< Different VAP extended modes. */ ++#endif + }; + + /** +@@ -1037,8 +1047,10 @@ struct nss_wifi_vdev_stats_sync_msg { + uint32_t rx_mcast_bytes; /**< Receive multicast bytes count. */ + uint32_t rx_decrypt_err; /**< Receive decryption error */ + uint32_t rx_mic_err; /**< Receive MIC error */ ++#if (NSS_FW_VERSION_CODE > NSS_FW_VERSION(11,3)) + uint32_t mcbc_exc_host_fail_cnt; + /**< Number of multicast/broadcast packets failed to send to host through exception path. */ ++#endif + }; + + /** +@@ -1070,6 +1082,7 @@ struct nss_wifi_vdev_msg { + /**< Updates a snooplist group member. */ + struct nss_wifi_vdev_me_snptbl_deny_grp_add_msg vdev_deny_member_add; + /**< Add a snooplist member to the deny list. */ ++#if (NSS_FW_VERSION_CODE > NSS_FW_VERSION(11,3)) + struct nss_wifi_vdev_me_hmmc_add_msg vdev_hmmc_member_add; + /**< Adds a new member into the HMMC list. */ + struct nss_wifi_vdev_me_hmmc_del_msg vdev_hmmc_member_del; +@@ -1078,6 +1091,7 @@ struct nss_wifi_vdev_msg { + /**< Adds a new member into the deny list. */ + struct nss_wifi_vdev_me_deny_ip_del_msg vdev_deny_list_member_del; + /**< Delete a member from the deny list. */ ++#endif + struct nss_wifi_vdev_txmsg vdev_txmsgext; + /**< Transmits special data. */ + struct nss_wifi_vdev_vow_dbg_cfg_msg vdev_vow_dbg_cfg; +diff --git a/exports/nss_wifili_if.h b/exports/nss_wifili_if.h +index fce20fd..1f26d67 100644 +--- a/exports/nss_wifili_if.h ++++ b/exports/nss_wifili_if.h +@@ -62,8 +62,12 @@ + /**< Maximum number of bandwidth supported. */ + #define NSS_WIFILI_REPT_MU_MIMO 1 + #define NSS_WIFILI_REPT_MU_OFDMA_MIMO 3 ++#if (NSS_FW_VERSION_CODE > NSS_FW_VERSION(11,3)) ++#define NSS_WIFILI_MAX_RESERVED_TYPE 3 ++#else + #define NSS_WIFILI_MAX_RESERVED_TYPE 2 + /**< Maximum reserved type. */ ++#endif + #define NSS_WIFILI_SOC_PER_PACKET_METADATA_SIZE 60 + /**< Metadata area total size. */ + #define NSS_WIFILI_MEC_PEER_ID 0xDEAD +@@ -1333,7 +1337,9 @@ struct nss_wifili_rx_err { + struct nss_wifili_rx_ctrl_stats { + struct nss_wifili_rx_err err; /**< Rx peer errors. */ + uint32_t multipass_rx_pkt_drop; /**< Total number of multipass packets without a VLAN header. */ ++#if (NSS_FW_VERSION_CODE > NSS_FW_VERSION(11,3)) + uint32_t peer_unauth_rx_pkt_drop; /**< Number of receive packets dropped due to an authorized peer. */ ++#endif + uint32_t reserved_type[NSS_WIFILI_MAX_RESERVED_TYPE]; /**< Reserved type for future use. */ + uint32_t non_amsdu_cnt; /**< Number of MSDUs with no MSDU level aggregation. */ + uint32_t amsdu_cnt; /**< Number of MSDUs part of AMSDU. */ +@@ -1810,10 +1816,12 @@ struct nss_wifili_msg { + /**< Peer four-address event message. */ + struct nss_wifili_dbdc_repeater_loop_detection_msg wdrldm; + /**< Wifili DBDC repeater loop detection message. */ ++#if (NSS_FW_VERSION_CODE > NSS_FW_VERSION(11,3)) + struct nss_wifili_peer_update_auth_flag peer_auth; + /**< Peer authentication flag message. */ + struct nss_wifili_mesh_capability_info cap_info; + /**< Mesh capability flag. */ ++#endif + } msg; /**< Message payload. */ + }; + +diff --git a/nss_ipv4_stats.c b/nss_ipv4_stats.c +index 39b162c..c875a63 100644 +--- a/nss_ipv4_stats.c ++++ b/nss_ipv4_stats.c +@@ -177,9 +177,11 @@ void nss_ipv4_stats_node_sync(struct nss_ctx_instance *nss_ctx, struct nss_ipv4_ + nss_ipv4_stats[NSS_IPV4_STATS_MC_CONNECTION_DESTROY_REQUESTS] += nins->ipv4_mc_connection_destroy_requests; + nss_ipv4_stats[NSS_IPV4_STATS_MC_CONNECTION_DESTROY_MISSES] += nins->ipv4_mc_connection_destroy_misses; + nss_ipv4_stats[NSS_IPV4_STATS_MC_CONNECTION_FLUSHES] += nins->ipv4_mc_connection_flushes; ++#if (NSS_FW_VERSION_CODE > NSS_FW_VERSION(11,3)) + nss_ipv4_stats[NSS_IPV4_STATS_CONNECTION_CREATE_INVALID_MIRROR_IFNUM] += nins->ipv4_connection_create_invalid_mirror_ifnum; + nss_ipv4_stats[NSS_IPV4_STATS_CONNECTION_CREATE_INVALID_MIRROR_IFTYPE] += nins->ipv4_connection_create_invalid_mirror_iftype; + nss_ipv4_stats[NSS_IPV4_STATS_MIRROR_FAILURES] += nins->ipv4_mirror_failures; ++#endif + + for (i = 0; i < NSS_IPV4_EXCEPTION_EVENT_MAX; i++) { + nss_ipv4_exception_stats[i] += nins->exception_events[i]; +diff --git a/nss_ipv4_strings.c b/nss_ipv4_strings.c +index 77ff352..ce4c249 100644 +--- a/nss_ipv4_strings.c ++++ b/nss_ipv4_strings.c +@@ -137,9 +137,11 @@ struct nss_stats_info nss_ipv4_strings_stats[NSS_IPV4_STATS_MAX] = { + {"mc_destroy_requests" , NSS_STATS_TYPE_SPECIAL}, + {"mc_destroy_misses" , NSS_STATS_TYPE_SPECIAL}, + {"mc_flushes" , NSS_STATS_TYPE_SPECIAL}, ++#if (NSS_FW_VERSION_CODE > NSS_FW_VERSION(11,3)) + {"mirror_invalid_ifnum_conn_create_req" , NSS_STATS_TYPE_SPECIAL}, + {"mirror_invalid_iftype_conn_create_req" , NSS_STATS_TYPE_SPECIAL}, + {"mirror_failures" , NSS_STATS_TYPE_SPECIAL}, ++#endif + }; + + /* +diff --git a/nss_ipv6_stats.c b/nss_ipv6_stats.c +index 617f55b..a492a6c 100644 +--- a/nss_ipv6_stats.c ++++ b/nss_ipv6_stats.c +@@ -180,9 +180,11 @@ void nss_ipv6_stats_node_sync(struct nss_ctx_instance *nss_ctx, struct nss_ipv6_ + nss_ipv6_stats[NSS_IPV6_STATS_MC_CONNECTION_DESTROY_REQUESTS] += nins->ipv6_mc_connection_destroy_requests; + nss_ipv6_stats[NSS_IPV6_STATS_MC_CONNECTION_DESTROY_MISSES] += nins->ipv6_mc_connection_destroy_misses; + nss_ipv6_stats[NSS_IPV6_STATS_MC_CONNECTION_FLUSHES] += nins->ipv6_mc_connection_flushes; ++#if (NSS_FW_VERSION_CODE > NSS_FW_VERSION(11,3)) + nss_ipv6_stats[NSS_IPV6_STATS_CONNECTION_CREATE_INVALID_MIRROR_IFNUM] += nins->ipv6_connection_create_invalid_mirror_ifnum; + nss_ipv6_stats[NSS_IPV6_STATS_CONNECTION_CREATE_INVALID_MIRROR_IFTYPE] += nins->ipv6_connection_create_invalid_mirror_iftype; + nss_ipv6_stats[NSS_IPV6_STATS_MIRROR_FAILURES] += nins->ipv6_mirror_failures; ++#endif + + for (i = 0; i < NSS_IPV6_EXCEPTION_EVENT_MAX; i++) { + nss_ipv6_exception_stats[i] += nins->exception_events[i]; +diff --git a/nss_ipv6_strings.c b/nss_ipv6_strings.c +index 57b100f..29df9c9 100644 +--- a/nss_ipv6_strings.c ++++ b/nss_ipv6_strings.c +@@ -115,9 +115,11 @@ struct nss_stats_info nss_ipv6_strings_stats[NSS_IPV6_STATS_MAX] = { + {"mc_destroy_requests" ,NSS_STATS_TYPE_SPECIAL}, + {"mc_destroy_misses" ,NSS_STATS_TYPE_SPECIAL}, + {"mc_flushes" ,NSS_STATS_TYPE_SPECIAL}, ++#if (NSS_FW_VERSION_CODE > NSS_FW_VERSION(11,3)) + {"mirror_invalid_ifnum_conn_create_req" ,NSS_STATS_TYPE_SPECIAL}, + {"mirror_invalid_iftype_conn_create_req" ,NSS_STATS_TYPE_SPECIAL}, + {"mirror_failures" ,NSS_STATS_TYPE_SPECIAL}, ++#endif + }; + + /* +-- +2.31.1 + diff --git a/qaa/nss/qca-nss-drv/Makefile b/qaa/nss/qca-nss-drv/Makefile new file mode 100644 index 000000000..7e695ca38 --- /dev/null +++ b/qaa/nss/qca-nss-drv/Makefile @@ -0,0 +1,125 @@ +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/kernel.mk + +PKG_NAME:=qca-nss-drv +PKG_RELEASE:=2 + +PKG_SOURCE_URL:=https://source.codeaurora.org/quic/qsdk/oss/lklm/nss-drv +PKG_SOURCE_PROTO:=git +PKG_SOURCE_VERSION:=809a00deffe9f3d4ecd15965790a152757073437 +PKG_MIRROR_HASH:=9c4340561fe9d6ccaa094bbfc5c7f98c27867d2d9a3f1a3f9a7483bca9bbedf8 + +NSS_CLIENTS_DIR:=$(TOPDIR)/qca/src/qca-nss-clients + +include $(INCLUDE_DIR)/package.mk + +define KernelPackage/qca-nss-drv + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + DEPENDS:=@TARGET_ipq806x||TARGET_ipq_ipq806x||TARGET_ipq_ipq807x||TARGET_ipq_ipq807x_64||TARGET_ipq807x||TARGET_ipq807x_64||TARGET_ipq_ipq60xx||TARGET_ipq_ipq60xx_64||TARGET_ipq_ipq50xx||TARGET_ipq_ipq50xx_64 \ + +PACKAGE_kmod-qca-nss-gmac:kmod-qca-nss-gmac @LINUX_5_4 + TITLE:=Kernel driver for NSS (core driver) + FILES:=$(PKG_BUILD_DIR)/qca-nss-drv.ko + AUTOLOAD:=$(call AutoLoad,32,qca-nss-drv) +endef + +define KernelPackage/qca-nss-drv/install + $(INSTALL_DIR) $(1)/lib/debug + $(INSTALL_DIR) $(1)/etc/init.d + $(INSTALL_DIR) $(1)/etc/sysctl.d + $(INSTALL_DIR) $(1)/etc/hotplug.d/firmware + $(INSTALL_DIR) $(1)/etc/config + $(INSTALL_DIR) $(1)/lib/firmware + + $(INSTALL_BIN) ./files/qca-nss-drv.debug $(1)/lib/debug/qca-nss-drv + $(INSTALL_BIN) ./files/qca-nss-drv.init $(1)/etc/init.d/qca-nss-drv + $(INSTALL_BIN) ./files/qca-nss-drv.sysctl $(1)/etc/sysctl.d/qca-nss-drv.conf + $(INSTALL_BIN) ./files/qca-nss-drv.hotplug $(1)/etc/hotplug.d/firmware/10-qca-nss-fw + $(INSTALL_BIN) ./files/qca-nss-drv.conf $(1)/etc/config/nss + $(INSTALL_BIN) ./files/nss-firmware/qca-nss0-retail.bin $(1)/lib/firmware/qca-nss0.bin + $(INSTALL_BIN) ./files/nss-firmware/qca-nss1-retail.bin $(1)/lib/firmware/qca-nss1.bin + +endef + +define KernelPackage/qca-nss-drv/Description +This package contains a NSS driver for QCA chipset +endef + +define Build/InstallDev + mkdir -p $(1)/usr/include/qca-nss-drv + $(CP) $(PKG_BUILD_DIR)/exports/* $(1)/usr/include/qca-nss-drv/ +ifneq (, $(findstring $(subtarget), "ipq807x" "ipq807x_64" "ipq60xx" "ipq60xx_64" "ipq50xx" "ipq50xx_64")) + $(RM) $(1)/usr/include/qca-nss-drv/nss_ipsecmgr.h + $(INSTALL_DIR) $(1)/usr/include/qca-nss-clients + $(CP) $(NSS_CLIENTS_DIR)/exports/nss_ipsecmgr.h $(1)/usr/include/qca-nss-clients/. +endif +endef + +EXTRA_CFLAGS+= -I$(STAGING_DIR)/usr/include/qca-nss-gmac + +# Keeping default as ipq806x for branches that does not have subtarget framework +ifeq ($(CONFIG_TARGET_ipq),y) +subtarget:=$(SUBTARGET) +else +subtarget:=$(CONFIG_TARGET_BOARD) +endif + +ifeq ($(CONFIG_KERNEL_IPQ_MEM_PROFILE),256) +EXTRA_CFLAGS+= -DNSS_MEM_PROFILE_LOW +endif + +ifeq ($(CONFIG_KERNEL_IPQ_MEM_PROFILE),512) +EXTRA_CFLAGS+= -DNSS_MEM_PROFILE_MEDIUM +endif + +ifeq ($(CONFIG_KERNEL_SKB_FIXED_SIZE_2K),y) +EXTRA_CFLAGS+= -DNSS_SKB_FIXED_SIZE_2K +endif + +DRV_MAKE_OPTS:= +ifeq ($(CONFIG_KERNEL_IPQ_MEM_PROFILE),256) +DRV_MAKE_OPTS+=NSS_DRV_C2C_ENABLE=n \ + NSS_DRV_CAPWAP_ENABLE=n \ + NSS_DRV_CLMAP_ENABLE=n \ + NSS_DRV_CRYPTO_ENABLE=n \ + NSS_DRV_DTLS_ENABLE=n \ + NSS_DRV_GRE_ENABLE=n \ + NSS_DRV_GRE_REDIR_ENABLE=n \ + NSS_DRV_GRE_TUNNEL_ENABLE=n \ + NSS_DRV_IGS_ENABLE=n \ + NSS_DRV_IPSEC_ENABLE=n \ + NSS_DRV_LAG_ENABLE=n \ + NSS_DRV_L2TP_ENABLE=n \ + NSS_DRV_MAPT_ENABLE=n \ + NSS_DRV_OAM_ENABLE=n \ + NSS_DRV_PPTP_ENABLE=n \ + NSS_DRV_PORTID_ENABLE=n \ + NSS_DRV_PVXLAN_ENABLE=n \ + NSS_DRV_QRFS_ENABLE=n \ + NSS_DRV_QVPN_ENABLE=n \ + NSS_DRV_RMNET_ENABLE=n \ + NSS_DRV_SHAPER_ENABLE=n \ + NSS_DRV_SJACK_ENABLE=n \ + NSS_DRV_TLS_ENABLE=n \ + NSS_DRV_TRUSTSEC_ENABLE=n \ + NSS_DRV_TSTAMP_ENABLE=n \ + NSS_DRV_TUN6RD_ENABLE=n \ + NSS_DRV_TUNIPIP6_ENABLE=n \ + NSS_DRV_VXLAN_ENABLE=n +endif + +define Build/Configure + $(LN) arch/nss_$(subtarget).h $(PKG_BUILD_DIR)/exports/nss_arch.h +endef + +define Build/Compile + $(MAKE) $(PKG_JOBS) -C "$(LINUX_DIR)" $(strip $(DRV_MAKE_OPTS)) \ + $(KERNEL_MAKE_FLAGS) \ + $(PKG_MAKE_FLAGS) \ + M="$(PKG_BUILD_DIR)" \ + EXTRA_CFLAGS="$(EXTRA_CFLAGS)" SoC="$(subtarget)" \ + modules +endef + +$(eval $(call KernelPackage,qca-nss-drv)) diff --git a/qaa/nss/qca-nss-drv/files/nss-firmware/LICENSE.TXT b/qaa/nss/qca-nss-drv/files/nss-firmware/LICENSE.TXT new file mode 100644 index 000000000..41631989a --- /dev/null +++ b/qaa/nss/qca-nss-drv/files/nss-firmware/LICENSE.TXT @@ -0,0 +1,45 @@ +Copyright (c) 2014 Qualcomm Atheros, Inc. + +All rights reserved. + +Redistribution and use in binary forms, without +modification, are permitted (subject to the limitations in the +disclaimer below) provided that the following conditions are met: + +*Redistributions must reproduce the above copyright + notice, this list of conditions, and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +*Neither the name of Qualcomm Atheros, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + +*No Reverse engineering, decompiling, decrypting, or disassembling of this + software is permitted. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +A PARTICULAR PURPOSE ARE DISCLAIMED. NO LICENSES OR OTHER RIGHTS, +WHETHER EXPRESS, IMPLIED, BASED ON ESTOPPEL OR OTHERWISE, ARE GRANTED +TO ANY PARTY'S PATENTS, PATENT APPLICATIONS, OR PATENTABLE INVENTIONS +BY VIRTUE OF THIS LICENSE OR THE DELIVERY OR PROVISION BY QUALCOMM +ATHEROS, INC. OF THE SOFTWARE. + +IN NO EVENT SHALL THE COPYRIGHT OWNER OR ANY CONTRIBUTOR BE LIABLE FOR +ANY INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND REGARDLESS OF ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +OTHERWISE) ARISING IN ANY WAY OUT OF OR RESULTING FROM THE USE OF THE +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. IN ANY +EVENT, THE TOTAL AGGREGATE LIABILITY THAT MAY BE IMPOSED ON QUALCOMM +ATHEROS, INC. FOR ANY DIRECT DAMAGES ARISING UNDER OR RESULTING FROM +THIS AGREEMENT OR IN CONNECTION WITH ANY USE OF THE SOFTWARE SHALL NOT +EXCEED A TOTAL AMOUNT OF US$5.00. + +IF ANY OF THE ABOVE PROVISIONS ARE HELD TO BE VOID, INVALID, +UNENFORCEABLE, OR ILLEGAL, THE OTHER PROVISIONS SHALL CONTINUE IN FULL +FORCE AND EFFECT. + diff --git a/qaa/nss/qca-nss-drv/files/nss-firmware/NOTICE.TXT b/qaa/nss/qca-nss-drv/files/nss-firmware/NOTICE.TXT new file mode 100644 index 000000000..ab54aa019 --- /dev/null +++ b/qaa/nss/qca-nss-drv/files/nss-firmware/NOTICE.TXT @@ -0,0 +1,217 @@ +============================================================================= + +This Notice.txt file contains certain notices of software components included +with the software that Qualcomm Atheros, Inc. ("Qualcomm Atheros") is required +to provide you. Except where prohibited by the open source license, the content +of this notices file is only provided to satisfy Qualcomm Atheros's attribution +and notice requirement; your use of these software components together with the +Qualcomm Atheros software (Qualcomm Atheros software hereinafter referred to as +"Software") is subject to the terms of your license from Qualcomm Atheros. +Compliance with all copyright laws and software license agreements included in +the notice section of this file are the responsibility of the user. Except as +may be granted by separate express written agreement, this file provides no +license to any Qualcomm Atheros patents, trademarks, copyrights, or other +intellectual property. + +Copyright (c) 2014 Qualcomm Atheros, Inc. All rights reserved. + +Qualcomm is a trademark of Qualcomm Incorporated, registered in the United +States and other countries. All Qualcomm Incorporated trademarks are used with +permission. Atheros is a trademark of Qualcomm Atheros, Inc., registered in the +United States and other countries. Other products and brand names may be +trademarks or registered trademarks of their respective owners. + +NOTICES: + +============================================================================= + +/* + * doprint.c + * Formatted string print support. + * + * Copyright 2001-2012 Qualcomm Atheros, Inc. All Rights Reserved. + * + * Qualcomm Atheros Confidential and Proprietary. + * + * This code originates with BSD Unix however it has been extensively + * modified. The original copyright is reproduced below: + * + * Copyright (c) 1988 Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted provided + * that: (1) source distributions retain this entire copyright notice and + * comment, and (2) distributions including binaries display the following + * acknowledgement: ``This product includes software developed by the + * University of California, Berkeley and its contributors'' in the + * documentation or other materials provided with the distribution and in + * all advertising materials mentioning features or use of this software. + * Neither the name of the University nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + + +/* + * math.c + * Support for the standard C library. + * + * Copyright 2006-2012 Qualcomm Atheros, Inc. All Rights Reserved. + * + * Qualcomm Atheros Confidential and Proprietary. + * + * Software contained within this file was originally released with the + * following + * copyright and license statement: + * + * ==================================================== + * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved. + * + * Developed at SunPro, a Sun Microsystems, Inc. business. + * Permission to use, copy, modify, and distribute this + * software is freely granted, provided that this notice + * is preserved. + * ==================================================== + */ + + +/* + * stdlib.c + * Routines from stdlib.h. + * + * Copyright 2004-2012 Qualcomm Atheros, Inc. All Rights Reserved. + * + * Qualcomm Atheros Confidential and Proprietary. + * + * The code for strtol() and strtoul() are also subject to the following: + * + * Copyright (c) 1990, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +drr_alg_utils.h: +/****************************************************************************/ +/*- + * Copyright (c) 1992, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + + +shaper_list_utils.h: +/****************************************************************************/ +/*- + * Copyright (c) 1992, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + + +codel_alg_inv_sqrt.h +/****************************************************************************/ +/*- + * Copyright (c) 1992, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ diff --git a/qaa/nss/qca-nss-drv/files/nss-firmware/README.md b/qaa/nss/qca-nss-drv/files/nss-firmware/README.md new file mode 100644 index 000000000..2d0b47508 --- /dev/null +++ b/qaa/nss/qca-nss-drv/files/nss-firmware/README.md @@ -0,0 +1,10 @@ +NSS FIRMWARE +============ + +This repo contains firmware files to enable the NSS MAC on QCA IPQ806x SoC. + +This product includes software developed by the University of California, +Berkeley and its contributors. + +NSS firmware extracted from Synology RT2600ac SRM 1.2 - Version: 1.2-7742-4 + diff --git a/qaa/nss/qca-nss-drv/files/nss-firmware/qca-nss0-retail.bin b/qaa/nss/qca-nss-drv/files/nss-firmware/qca-nss0-retail.bin new file mode 100644 index 0000000000000000000000000000000000000000..08f6efe6c8d8c476a7b68c8b44e125db75276cef GIT binary patch literal 536324 zcmeFa33QyrneScIUENaKvMqItmk9y2HY_lS9SjbcOpw`Z0ZAZ`#W$YNuiY{h5sQNX zHMH#(VKG~f5|Ti|1ewXqgd~$YNoMYZxyjJ--bMxt7#s(%!SYUwvjV}k?(hG0zj8~K zf!uq}ckcP_NT<)cS3ULAv)5Bq#+Y?cv+enYZy0k~b$Qbijst&Q)LO61e(R3qoBPLH zmtVAeQDTwh7vop8DDlCnPsLAcAJc5x$Bgsd@)G_1k8c{|U23iAe%?}Ma6H(b%^R~U z-{0SvKiK~O=iQutpYsmR@8rCT^9MO!&iSL9-@^G_oPUk;Z*%?#=Re^5E1ciW`PVuB z4(ET*`42gNi1Y7p{v*!+j`M%u{Ga*#3%{T6`zgPl@%uTy$N2pRzyHba7yN#iH_1=f z1w9KA{mEwApS*zIh5Rn!_c?2lpXWE5Uy`54Z?3H{6SmuS6E~i57q?eBcf6}pTb;{Q zf`g6Qj7h)Mzjc$|srEun?@bxzJ!{OIq2C_l+duH_2-R`zyVnsm$-cJ3qrrJ{bM3;> zT`SxP+rxdv{?vVZdv#yJhUf>AOoS5FbRO>S-}K);WBT6D^J^=s`)Y@I-f2$QZg_4? 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All rights reserved. +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +# + +log cat /sys/kernel/debug/qca-nss-drv/stats/pppoe +log cat /sys/kernel/debug/qca-nss-drv/stats/n2h +log cat /sys/kernel/debug/qca-nss-drv/stats/ipv6 +log cat /sys/kernel/debug/qca-nss-drv/stats/ipv4 +log cat /sys/kernel/debug/qca-nss-drv/stats/gmac +log cat /sys/kernel/debug/qca-nss-drv/stats/drv +log cat /sys/kernel/debug/qca-nss-drv/stats/wifi +log cat /sys/kernel/debug/qca-nss-drv/stats/wifi_if +log cat /sys/kernel/debug/qca-nss-drv/stats/eth_rx diff --git a/qaa/nss/qca-nss-drv/files/qca-nss-drv.hotplug b/qaa/nss/qca-nss-drv/files/qca-nss-drv.hotplug new file mode 100644 index 000000000..1e4813838 --- /dev/null +++ b/qaa/nss/qca-nss-drv/files/qca-nss-drv.hotplug @@ -0,0 +1,70 @@ +#!/bin/sh +# +# Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +# + +KERNEL=`uname -r` +case "${KERNEL}" in + 3.4*) + select_or_load=load_nss_fw + ;; + *) + select_or_load=select_nss_fw + ;; +esac + +load_nss_fw () { + ls -l $1 | awk ' { print $9,$5 } '> /dev/console + echo 1 > /sys/class/firmware/$DEVICENAME/loading + cat $1 > /sys/class/firmware/$DEVICENAME/data + echo 0 > /sys/class/firmware/$DEVICENAME/loading +} + +select_nss_fw () { + rm -f /lib/firmware/$DEVICENAME + ln -s $1 /lib/firmware/$DEVICENAME + ls -l /lib/firmware/$DEVICENAME | awk ' { print $9,$5 } '> /dev/console +} + +[ "$ACTION" != "add" ] && exit + +# dev name for UCI, since it doesn't let you use . or - +SDEVNAME=$(echo ${DEVICENAME} | sed s/[.-]/_/g) + +SELECTED_FW=$(uci get nss.${SDEVNAME}.firmware 2>/dev/null) +[ -e "${SELECTED_FW}" ] && { + $select_or_load ${SELECTED_FW} + exit +} + +case $DEVICENAME in + qca-nss0* | qca-nss.0*) + if [ -e /lib/firmware/qca-nss0-enterprise.bin ] ; then + $select_or_load /lib/firmware/qca-nss0-enterprise.bin + else + $select_or_load /lib/firmware/qca-nss0-retail.bin + fi + exit + ;; + qca-nss1* | qca-nss.1*) + if [ -e /lib/firmware/qca-nss1-enterprise.bin ] ; then + $select_or_load /lib/firmware/qca-nss1-enterprise.bin + else + $select_or_load /lib/firmware/qca-nss1-retail.bin + fi + exit + ;; +esac + diff --git a/qaa/nss/qca-nss-drv/files/qca-nss-drv.init b/qaa/nss/qca-nss-drv/files/qca-nss-drv.init new file mode 100644 index 000000000..de12cb6d1 --- /dev/null +++ b/qaa/nss/qca-nss-drv/files/qca-nss-drv.init @@ -0,0 +1,50 @@ +#!/bin/sh /etc/rc.common +# +# Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +# + +START=70 + +enable_rps() { + irq_nss_rps=`grep nss_queue1 /proc/interrupts | cut -d ':' -f 1 | tr -d ' '` + for entry in $irq_nss_rps + do + echo 2 > /proc/irq/$entry/smp_affinity + done + + irq_nss_rps=`grep nss_queue2 /proc/interrupts | cut -d ':' -f 1 | tr -d ' '` + for entry in $irq_nss_rps + do + echo 4 > /proc/irq/$entry/smp_affinity + done + + irq_nss_rps=`grep nss_queue3 /proc/interrupts | cut -d ':' -f 1 | tr -d ' '` + for entry in $irq_nss_rps + do + echo 8 > /proc/irq/$entry/smp_affinity + done + + # Enable NSS RPS + sysctl -w dev.nss.rps.enable=1 >/dev/null 2>/dev/null + +} + + +start() { + local rps_enabled="$(uci_get nss @general[0] enable_rps)" + if [ "$rps_enabled" -eq 1 ]; then + enable_rps + fi +} diff --git a/qaa/nss/qca-nss-drv/files/qca-nss-drv.sysctl b/qaa/nss/qca-nss-drv/files/qca-nss-drv.sysctl new file mode 100644 index 000000000..fc36c33eb --- /dev/null +++ b/qaa/nss/qca-nss-drv/files/qca-nss-drv.sysctl @@ -0,0 +1,4 @@ +# Default Number of connection configuration +dev.nss.ipv4cfg.ipv4_conn=4096 +dev.nss.ipv6cfg.ipv6_conn=4096 + diff --git a/qaa/nss/qca-nss-drv/patches/100-kernel-5.4-support.patch b/qaa/nss/qca-nss-drv/patches/100-kernel-5.4-support.patch new file mode 100644 index 000000000..4268225c3 --- /dev/null +++ b/qaa/nss/qca-nss-drv/patches/100-kernel-5.4-support.patch @@ -0,0 +1,107 @@ +diff --git a/Makefile b/Makefile +index d998548..b1a4a83 100644 +--- a/Makefile ++++ b/Makefile +@@ -161,7 +161,7 @@ endif + ccflags-y += -I$(obj)/nss_hal/include -I$(obj)/nss_data_plane/include -I$(obj)/exports -DNSS_DEBUG_LEVEL=0 -DNSS_PKT_STATS_ENABLED=1 + + ccflags-y += -DNSS_PM_DEBUG_LEVEL=0 -DNSS_SKB_REUSE_SUPPORT=1 +-ccflags-y += -Werror ++# ccflags-y += -Werror + + ifneq ($(findstring 3.4, $(KERNELVERSION)),) + NSS_CCFLAGS = -DNSS_DT_SUPPORT=0 -DNSS_FW_DBG_SUPPORT=1 -DNSS_PM_SUPPORT=1 -DNSS_EMPTY_BUFFER_SIZE=1984 +diff --git a/nss_core.c b/nss_core.c +index 6c9716a..8956eb5 100644 +--- a/nss_core.c ++++ b/nss_core.c +@@ -26,6 +26,7 @@ + #include + #include + #include ++#include + #include "nss_tx_rx_common.h" + #include "nss_data_plane.h" + +@@ -45,7 +46,8 @@ + (((LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 15, 0)))) || \ + (((LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0)))) || \ + (((LINUX_VERSION_CODE >= KERNEL_VERSION(3, 18, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 19, 0)))) || \ +-(((LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(4, 5, 0)))))) ++(((LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(4, 5, 0)))) || \ ++(((LINUX_VERSION_CODE >= KERNEL_VERSION(5, 4, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 5, 0)))))) + #error "Check skb recycle code in this file to match Linux version" + #endif + +@@ -395,7 +397,11 @@ static void nss_get_ddr_info(struct nss_mmu_ddr_info *mmu, char *name) + struct device_node *node; + + si_meminfo(&vals); ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)) ++ cached = global_zone_page_state(NR_FILE_PAGES); ++#else + cached = global_page_state(NR_FILE_PAGES); ++#endif /*KERNEL_VERSION(4, 14, 0)*/ + avail_ddr = (vals.totalram + cached + vals.sharedram) * vals.mem_unit; + + /* +@@ -679,7 +685,11 @@ static inline void nss_core_handle_virt_if_pkt(struct nss_ctx_instance *nss_ctx, + * Mimic Linux behavior to allow multi-queue netdev choose which queue to use + */ + if (ndev->netdev_ops->ndo_select_queue) { ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0)) ++ queue_offset = ndev->netdev_ops->ndo_select_queue(ndev, nbuf, NULL); ++#else + queue_offset = ndev->netdev_ops->ndo_select_queue(ndev, nbuf, NULL, NULL); ++#endif /*KERNEL_VERSION(5, 3, 0)*/ + } + + skb_set_queue_mapping(nbuf, queue_offset); +@@ -2269,7 +2279,11 @@ static inline bool nss_skb_can_reuse(struct nss_ctx_instance *nss_ctx, + * This check is added to avoid deadlock from nf_conntrack + * when ecm is trying to flush a rule. + */ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 11, 0)) ++ if (unlikely(skb_nfct(nbuf))) { ++#else + if (unlikely(nbuf->nfct)) { ++#endif /*KERNEL_VERSION(4, 11, 0)*/ + return false; + } + #endif +@@ -2279,7 +2285,11 @@ static inline bool nss_skb_can_reuse(struct nss_ctx_instance *nss_ctx, + * This check is added to avoid deadlock from nf_bridge + * when ecm is trying to flush a rule. + */ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 11, 0)) ++ if (unlikely(skb_ext_exist(nbuf, SKB_EXT_BRIDGE_NF))) { ++#else + if (unlikely(nbuf->nf_bridge)) { ++#endif /*KERNEL_VERSION(4, 11, 0)*/ + return false; + } + #endif +diff --git a/nss_n2h.c b/nss_n2h.c +index 781ce2b..695ac13 100644 +--- a/nss_n2h.c ++++ b/nss_n2h.c +@@ -19,6 +19,7 @@ + * NSS N2H node APIs + */ + ++#include + #include "nss_tx_rx_common.h" + #include "nss_n2h_stats.h" + + +--- a/nss_data_plane/nss_data_plane_gmac.c ++++ b/nss_data_plane/nss_data_plane_gmac.c +@@ -20,7 +20,7 @@ + #include "nss_tx_rx_common.h" + #include + +-#define NSS_DP_GMAC_SUPPORTED_FEATURES (NETIF_F_HIGHDMA | NETIF_F_HW_CSUM | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_FRAGLIST | (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_UFO)) ++#define NSS_DP_GMAC_SUPPORTED_FEATURES (NETIF_F_HIGHDMA | NETIF_F_HW_CSUM | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_FRAGLIST | (NETIF_F_TSO | NETIF_F_TSO6)) + #define NSS_DATA_PLANE_GMAC_MAX_INTERFACES 4 + + static DEFINE_SPINLOCK(nss_data_plane_gmac_stats_lock); diff --git a/qaa/nss/qca-nss-drv/patches/101-nss-drv-Control-fab-scaling-from-package-Makefile.patch b/qaa/nss/qca-nss-drv/patches/101-nss-drv-Control-fab-scaling-from-package-Makefile.patch new file mode 100644 index 000000000..b0facc856 --- /dev/null +++ b/qaa/nss/qca-nss-drv/patches/101-nss-drv-Control-fab-scaling-from-package-Makefile.patch @@ -0,0 +1,38 @@ +From 40d4b080f17883ac6b39c74a5feb1af384ab6a51 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Thu, 11 Jun 2020 16:57:39 +0200 +Subject: [PATCH] nss-drv: Control fab scaling from package Makefile + +Lets control the fab scaling from the package Makefile +instead of using kernel checks that dont work. +Fab scaling in OpenWrt is done in a external way. + +Signed-off-by: Robert Marko +--- + Makefile | 9 --------- + 1 file changed, 9 deletions(-) + +diff --git a/Makefile b/Makefile +index 20729ab..2567dd4 100644 +--- a/Makefile ++++ b/Makefile +@@ -405,15 +405,8 @@ NSS_CCFLAGS = -DNSS_DT_SUPPORT=1 -DNSS_FW_DBG_SUPPORT=0 -DNSS_PM_SUPPORT=0 + ccflags-y += -I$(obj) + endif + +-# Fabric scaling is supported in 3.14 and 4.4 only +-ifneq ($(findstring 3.14, $(KERNELVERSION)),) +-NSS_CCFLAGS += -DNSS_FABRIC_SCALING_SUPPORT=1 +-else ifneq ($(findstring 4.4, $(KERNELVERSION)),) +-NSS_CCFLAGS += -DNSS_FABRIC_SCALING_SUPPORT=1 +-else +-NSS_CCFLAGS += -DNSS_FABRIC_SCALING_SUPPORT=0 +-endif ++NSS_CCFLAGS += -DNSS_FABRIC_SCALING_SUPPORT=0 + + # Disable Frequency scaling + ifeq "$(NSS_FREQ_SCALE_DISABLE)" "y" + ccflags-y += -DNSS_FREQ_SCALE_SUPPORT=0 +-- +2.26.2 + diff --git a/qaa/nss/qca-nss-drv/patches/200-fix-NULL-pointer-exception.patch b/qaa/nss/qca-nss-drv/patches/200-fix-NULL-pointer-exception.patch new file mode 100644 index 000000000..3d8bba950 --- /dev/null +++ b/qaa/nss/qca-nss-drv/patches/200-fix-NULL-pointer-exception.patch @@ -0,0 +1,11 @@ +--- a/nss_core.c ++++ b/nss_core.c +@@ -1599,7 +1599,7 @@ static int32_t nss_core_handle_cause_que + * + */ + if (unlikely((buffer_type == N2H_BUFFER_CRYPTO_RESP))) { +- dma_unmap_single(NULL, (desc->buffer + desc->payload_offs), desc->payload_len, DMA_FROM_DEVICE); ++ dma_unmap_single(nss_ctx->dev, (desc->buffer + desc->payload_offs), desc->payload_len, DMA_FROM_DEVICE); + goto consume; + } + diff --git a/qaa/nss/qca-nss-drv/patches/201-Fix-Kernel-Panic-dma-with-NULL-dev.patch b/qaa/nss/qca-nss-drv/patches/201-Fix-Kernel-Panic-dma-with-NULL-dev.patch new file mode 100644 index 000000000..addfef1bb --- /dev/null +++ b/qaa/nss/qca-nss-drv/patches/201-Fix-Kernel-Panic-dma-with-NULL-dev.patch @@ -0,0 +1,82 @@ +From 89949decfd9a0f86427b502aae4fbc3a3ef399f0 Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Tue, 23 Jun 2020 19:50:28 +0200 +Subject: [PATCH] Fix Kernel Panic dma with NULL dev + +--- + nss_coredump.c | 4 ++-- + nss_log.c | 8 +++++--- + 2 files changed, 8 insertions(+), 6 deletions(-) + +diff --git a/nss_coredump.c b/nss_coredump.c +index aa4ba82..957eca0 100644 +--- a/nss_coredump.c ++++ b/nss_coredump.c +@@ -154,7 +154,7 @@ void nss_fw_coredump_notify(struct nss_ctx_instance *nss_own, + dma_addr = nss_own->meminfo_ctx.logbuffer_dma; + } + +- dma_sync_single_for_cpu(NULL, dma_addr, sizeof(struct nss_log_descriptor), DMA_FROM_DEVICE); ++ dma_sync_single_for_cpu(nss_own->dev, dma_addr, sizeof(struct nss_log_descriptor), DMA_FROM_DEVICE); + + /* + * If the current entry is smaller than or equal to the number of NSS_LOG_COREDUMP_LINE_NUM, +@@ -181,7 +181,7 @@ void nss_fw_coredump_notify(struct nss_ctx_instance *nss_own, + + offset = (index * sizeof(struct nss_log_entry)) + + offsetof(struct nss_log_descriptor, log_ring_buffer); +- dma_sync_single_for_cpu(NULL, dma_addr + offset, ++ dma_sync_single_for_cpu(nss_own->dev, dma_addr + offset, + sizeof(struct nss_log_entry), DMA_FROM_DEVICE); + nss_info_always("%p: %s\n", nss_own, nle_print->message); + nle_print++; +diff --git a/nss_log.c b/nss_log.c +index 06ebba4..f9bd6c8 100644 +--- a/nss_log.c ++++ b/nss_log.c +@@ -44,6 +44,7 @@ struct nss_log_data { + uint32_t last_entry; /* Last known sampled entry (or index) */ + uint32_t nentries; /* Caches the total number of entries of log buffer */ + int nss_id; /* NSS Core id being used */ ++ struct device *nss_dev; + }; + + struct nss_log_ring_buffer_addr nss_rbe[NSS_MAX_CORES]; +@@ -125,6 +126,7 @@ static int nss_log_open(struct inode *inode, struct file *filp) + data->last_entry = 0; + data->nentries = nss_rbe[nss_id].nentries; + data->dma_addr = nss_rbe[nss_id].dma_addr; ++ data->nss_dev = nss_ctx->dev; + + /* + * Increment the reference count so that we don't free +@@ -207,7 +209,7 @@ static ssize_t nss_log_read(struct file *filp, char __user *buf, size_t size, lo + /* + * Get the current index + */ +- dma_sync_single_for_cpu(NULL, data->dma_addr, sizeof(struct nss_log_descriptor), DMA_FROM_DEVICE); ++ dma_sync_single_for_cpu(data->nss_dev, data->dma_addr, sizeof(struct nss_log_descriptor), DMA_FROM_DEVICE); + entry = nss_log_current_entry(desc); + + /* +@@ -251,7 +253,7 @@ static ssize_t nss_log_read(struct file *filp, char __user *buf, size_t size, lo + offset = (offset * sizeof(struct nss_log_entry)) + + offsetof(struct nss_log_descriptor, log_ring_buffer); + +- dma_sync_single_for_cpu(NULL, data->dma_addr + offset, ++ dma_sync_single_for_cpu(data->nss_dev, data->dma_addr + offset, + sizeof(struct nss_log_entry), DMA_FROM_DEVICE); + rb = &desc->log_ring_buffer[index]; + +@@ -510,7 +512,7 @@ bool nss_debug_log_buffer_alloc(uint8_t nss_id, uint32_t nentry) + return true; + + fail: +- dma_unmap_single(NULL, dma_addr, size, DMA_FROM_DEVICE); ++ dma_unmap_single(nss_ctx->dev, dma_addr, size, DMA_FROM_DEVICE); + kfree(addr); + wake_up(&nss_log_wq); + return false; +-- +2.27.0 + diff --git a/qaa/nss/qca-nss-drv/patches/400-Exported-set-nexthop-function.patch b/qaa/nss/qca-nss-drv/patches/400-Exported-set-nexthop-function.patch new file mode 100644 index 000000000..8c0ffe774 --- /dev/null +++ b/qaa/nss/qca-nss-drv/patches/400-Exported-set-nexthop-function.patch @@ -0,0 +1,47 @@ +From f8cf061454a3707c0c84d0fca685e84455f91362 Mon Sep 17 00:00:00 2001 +From: Suruchi Suman +Date: Tue, 3 Dec 2019 12:57:38 +0530 +Subject: [qca-nss-drv] Exported set nexhop function from drv. + +Change-Id: I3df6658bef72fe574ac9acfb7aac61785769766f +Signed-off-by: Suruchi Suman +--- + nss_phys_if.c | 9 ++++++++- + 1 file changed, 8 insertions(+), 1 deletion(-) + +diff --git a/nss_phys_if.c b/nss_phys_if.c +index 4f9b20f..0c58d95 100644 +--- a/nss_phys_if.c ++++ b/nss_phys_if.c +@@ -1,6 +1,6 @@ + /* + ************************************************************************** +- * Copyright (c) 2014-2019, The Linux Foundation. All rights reserved. ++ * Copyright (c) 2014-2020, The Linux Foundation. All rights reserved. + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. +@@ -583,6 +583,12 @@ nss_tx_status_t nss_phys_if_set_nexthop(struct nss_ctx_instance *nss_ctx, uint32 + struct nss_phys_if_msg nim; + + NSS_VERIFY_CTX_MAGIC(nss_ctx); ++ ++ if (nexthop >= NSS_MAX_NET_INTERFACES) { ++ nss_warning("%p: Invalid nexthop interface number: %d", nss_ctx, nexthop); ++ return NSS_TX_FAILURE_BAD_PARAM; ++ } ++ + nss_info("%p: Phys If nexthop will be set to %d, id:%d\n", nss_ctx, nexthop, if_num); + + nss_cmn_msg_init(&nim.cm, if_num, NSS_PHYS_IF_SET_NEXTHOP, +@@ -591,6 +597,7 @@ nss_tx_status_t nss_phys_if_set_nexthop(struct nss_ctx_instance *nss_ctx, uint32 + + return nss_phys_if_msg_sync(nss_ctx, &nim); + } ++EXPORT_SYMBOL(nss_phys_if_set_nexthop); + + /* + * nss_get_state() +-- +cgit v1.1 + diff --git a/qaa/nss/qca-nss-ecm-64/Makefile b/qaa/nss/qca-nss-ecm-64/Makefile new file mode 100644 index 000000000..77afbb204 --- /dev/null +++ b/qaa/nss/qca-nss-ecm-64/Makefile @@ -0,0 +1,96 @@ +include $(TOPDIR)/rules.mk + +PKG_NAME:=qca-nss-ecm-64 +PKG_RELEASE:=$(AUTORELEASE) + +PKG_SOURCE_URL:=https://source.codeaurora.org/quic/cc-qrdk/oss/lklm/qca-nss-ecm +PKG_SOURCE_PROTO:=git +PKG_SOURCE_DATE:=2021-04-29 +PKG_SOURCE_VERSION:=c115aec34867b582e2e5ea79fc5315971e0e953c +PKG_MIRROR_HASH:=962385b45daa2e552a15018bf2930c2df1f6f575d885375bf935a142b4255da5 + +PKG_BUILD_PARALLEL:=1 + +include $(INCLUDE_DIR)/kernel.mk +include $(INCLUDE_DIR)/package.mk + +define KernelPackage/qca-nss-ecm-64 + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Support + DEPENDS:=@(TARGET_ipq807x||TARGET_ipq60xx) \ + +kmod-qca-nss-drv-64 \ + +iptables-mod-extra \ + +kmod-ipt-conntrack \ + +kmod-ipt-physdev \ + +iptables-mod-physdev \ + +kmod-ppp \ + +kmod-pppoe + TITLE:=QCA NSS Enhanced Connection Manager (ECM) + FILES:=$(PKG_BUILD_DIR)/*.ko + KCONFIG:=CONFIG_BRIDGE_NETFILTER=y \ + CONFIG_NF_CONNTRACK_EVENTS=y \ + CONFIG_NF_CONNTRACK_CHAIN_EVENTS=y \ + CONFIG_NF_CONNTRACK_DSCPREMARK_EXT=n +endef + +define KernelPackage/qca-nss-ecm-64/Description +This package contains the QCA NSS Enhanced Connection Manager +endef + +define KernelPackage/qca-nss-ecm-64/install + $(INSTALL_DIR) $(1)/etc/firewall.d $(1)/etc/init.d $(1)/usr/bin $(1)/lib/netifd/offload $(1)/etc/config $(1)/etc/uci-defaults $(1)/etc/sysctl.d + $(INSTALL_DATA) ./files/qca-nss-ecm.firewall $(1)/etc/firewall.d/qca-nss-ecm + $(INSTALL_BIN) ./files/qca-nss-ecm.init $(1)/etc/init.d/qca-nss-ecm + $(INSTALL_BIN) ./files/ecm_dump.sh $(1)/usr/bin/ + $(INSTALL_BIN) ./files/on-demand-down $(1)/lib/netifd/offload/on-demand-down + $(INSTALL_DATA) ./files/qca-nss-ecm.uci $(1)/etc/config/ecm + $(INSTALL_DATA) ./files/qca-nss-ecm.defaults $(1)/etc/uci-defaults/99-qca-nss-ecm + $(INSTALL_BIN) ./files/qca-nss-ecm.sysctl $(1)/etc/sysctl.d/qca-nss-ecm.conf +endef + +EXTRA_CFLAGS+=-I$(STAGING_DIR)/usr/include/qca-nss-drv + +ifneq (, $(findstring $(CONFIG_TARGET_BOARD), "ipq807x" "ipq60xx")) +ECM_MAKE_OPTS+= ECM_FRONT_END_NSS_ENABLE=y \ + ECM_CLASSIFIER_HYFI_ENABLE=n \ + ECM_MULTICAST_ENABLE=n \ + ECM_INTERFACE_IPSEC_ENABLE=n \ + ECM_INTERFACE_PPTP_ENABLE=n \ + ECM_INTERFACE_L2TPV2_ENABLE=n \ + ECM_INTERFACE_GRE_TAP_ENABLE=n \ + ECM_INTERFACE_GRE_TUN_ENABLE=n \ + ECM_INTERFACE_SIT_ENABLE=n \ + ECM_INTERFACE_TUNIPIP6_ENABLE=n \ + ECM_INTERFACE_RAWIP_ENABLE=n \ + ECM_INTERFACE_VLAN_ENABLE=n \ + ECM_CLASSIFIER_MARK_ENABLE=n \ + ECM_CLASSIFIER_DSCP_ENABLE=n \ + ECM_CLASSIFIER_PCC_ENABLE=n \ + ECM_BAND_STEERING_ENABLE=n \ + ECM_INTERFACE_PPPOE_ENABLE=y +endif + +ifeq ($(CONFIG_TARGET_BOARD), "ipq807x") + SOC="ipq807x_64" +else ifeq ($(CONFIG_TARGET_BOARD), "ipq60xx") + SOC="ipq60xx_64" +endif + +define Build/InstallDev + mkdir -p $(1)/usr/include/qca-nss-ecm + $(CP) $(PKG_BUILD_DIR)/exports/* $(1)/usr/include/qca-nss-ecm +endef + +define Build/Compile + +$(MAKE) -C "$(LINUX_DIR)" $(strip $(ECM_MAKE_OPTS)) \ + CROSS_COMPILE="$(TARGET_CROSS)" \ + ARCH="$(LINUX_KARCH)" \ + M="$(PKG_BUILD_DIR)" \ + EXTRA_CFLAGS="$(EXTRA_CFLAGS)" SoC=$(SOC) \ + $(KERNEL_MAKE_FLAGS) \ + $(PKG_JOBS) \ + modules +endef + +$(eval $(call KernelPackage,qca-nss-ecm-64)) diff --git a/qaa/nss/qca-nss-ecm-64/files/ecm_dump.sh b/qaa/nss/qca-nss-ecm-64/files/ecm_dump.sh new file mode 100644 index 000000000..dbf7de753 --- /dev/null +++ b/qaa/nss/qca-nss-ecm-64/files/ecm_dump.sh @@ -0,0 +1,95 @@ +#!/bin/sh +# +# Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +# + +ECM_MODULE=${1:-ecm_state} +MOUNT_ROOT=/dev/ecm + +# +# usage: ecm_dump.sh [module=ecm_db] +# +# with no parameters, ecm_dump.sh will attempt to mount the +# ecm_db state file and cat its contents. +# +# example with a parameter: ecm_dump.sh ecm_classifier_default +# +# this will cause ecm_dump to attempt to find and mount the state +# file for the ecm_classifier_default module, and if successful +# cat the contents. +# + +# this is one of the state files, which happens to be the +# last module started in ecm +ECM_STATE=/sys/kernel/debug/ecm/ecm_state/state_dev_major + +# tests to see if ECM is up and ready to receive commands. +# returns 0 if ECM is fully up and ready, else 1 +ecm_is_ready() { + if [ ! -e "${ECM_STATE}" ] + then + return 1 + fi + return 0 +} + +# +# module_state_mount(module_name) +# Mounts the state file of the module, if supported +# +module_state_mount() { + local module_name=$1 + local mount_dir=$2 + local state_file="/sys/kernel/debug/ecm/${module_name}/state_dev_major" + + if [ -e "${mount_dir}/${module_name}" ] + then + # already mounted + return 0 + fi + + #echo "Mount state file for $module_name ..." + if [ ! -e "$state_file" ] + then + #echo "... $module_name does not support state" + return 1 + fi + + local major="`cat $state_file`" + #echo "... Mounting state $state_file with major: $major" + mknod "${mount_dir}/${module_name}" c $major 0 +} + +# +# main +# +ecm_is_ready || { + #echo "ECM is not running" + exit 1 +} + +# all state files are mounted under MOUNT_ROOT, so make sure it exists +mkdir -p ${MOUNT_ROOT} + +# +# attempt to mount state files for the requested module and cat it +# if the mount succeeded +# +module_state_mount ${ECM_MODULE} ${MOUNT_ROOT} && { + cat ${MOUNT_ROOT}/${ECM_MODULE} + exit 0 +} + +exit 2 diff --git a/qaa/nss/qca-nss-ecm-64/files/on-demand-down b/qaa/nss/qca-nss-ecm-64/files/on-demand-down new file mode 100644 index 000000000..02d708e03 --- /dev/null +++ b/qaa/nss/qca-nss-ecm-64/files/on-demand-down @@ -0,0 +1,6 @@ +#!/bin/sh +# Copyright (c) 2016 The Linux Foundation. All rights reserved. + +[ -e "/sys/kernel/debug/ecm/ecm_db/defunct_all" ] && { + echo 1 > /sys/kernel/debug/ecm/ecm_db/defunct_all +} diff --git a/qaa/nss/qca-nss-ecm-64/files/qca-nss-ecm.defaults b/qaa/nss/qca-nss-ecm-64/files/qca-nss-ecm.defaults new file mode 100644 index 000000000..308e265c9 --- /dev/null +++ b/qaa/nss/qca-nss-ecm-64/files/qca-nss-ecm.defaults @@ -0,0 +1,28 @@ +#!/bin/sh +# +# Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +# + +uci -q batch << EOF + delete firewall.qcanssecm + set firewall.qcanssecm=include + set firewall.qcanssecm.type=script + set firewall.qcanssecm.path=/etc/firewall.d/qca-nss-ecm + set firewall.qcanssecm.family=any + set firewall.qcanssecm.reload=1 + commit firewall +EOF + +exit 0 diff --git a/qaa/nss/qca-nss-ecm-64/files/qca-nss-ecm.firewall b/qaa/nss/qca-nss-ecm-64/files/qca-nss-ecm.firewall new file mode 100644 index 000000000..24c64def2 --- /dev/null +++ b/qaa/nss/qca-nss-ecm-64/files/qca-nss-ecm.firewall @@ -0,0 +1,18 @@ +#!/bin/sh +# +# Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +# + +iptables -A FORWARD -m physdev --physdev-is-bridged -j ACCEPT diff --git a/qaa/nss/qca-nss-ecm-64/files/qca-nss-ecm.init b/qaa/nss/qca-nss-ecm-64/files/qca-nss-ecm.init new file mode 100644 index 000000000..78cf16dc0 --- /dev/null +++ b/qaa/nss/qca-nss-ecm-64/files/qca-nss-ecm.init @@ -0,0 +1,137 @@ +#!/bin/sh /etc/rc.common +# +# Copyright (c) 2014, 2019-2020 The Linux Foundation. All rights reserved. +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +# The shebang above has an extra space intentially to avoid having +# openwrt build scripts automatically enable this package starting +# at boot. + +START=19 + +get_front_end_mode() { + config_load "ecm" + config_get front_end global acceleration_engine "auto" + + case $front_end in + auto) + echo '0' + ;; + nss) + echo '1' + ;; + sfe) + echo '2' + ;; + *) + echo 'uci_option_acceleration_engine is invalid' + esac +} + +support_bridge() { + #NSS support bridge acceleration + [ -d /sys/kernel/debug/ecm/ecm_nss_ipv4 ] && return 0 + #SFE doesn't support bridge acceleration + [ -d /sys/kernel/debug/ecm/ecm_sfe_ipv4 ] && return 1 +} + +load_sfe() { + local kernel_version=$(uname -r) + + [ -e "/lib/modules/$kernel_version/shortcut-fe.ko" ] && { + [ -d /sys/module/shortcut_fe ] || insmod shortcut-fe + } + + [ -e "/lib/modules/$kernel_version/shortcut-fe-ipv6.ko" ] && { + [ -d /sys/module/shortcut_fe_ipv6 ] || insmod shortcut-fe-ipv6 + } + + [ -e "/lib/modules/$kernel_version/shortcut-fe-cm.ko" ] && { + [ -d /sys/module/shortcut_fe_cm ] || insmod shortcut-fe-cm + } + + [ -e "/lib/modules/$kernel_version/shortcut-fe-drv.ko" ] && { + [ -d /sys/module/shortcut_fe_drv ] || insmod shortcut-fe-drv + } +} + +load_ecm() { + [ -d /sys/module/ecm ] || { + [ ! -e /proc/device-tree/MP_256 ] && load_sfe + insmod ecm front_end_selection=$(get_front_end_mode) + } + + support_bridge && { + sysctl -w net.bridge.bridge-nf-call-ip6tables=1 + sysctl -w net.bridge.bridge-nf-call-iptables=1 + } +} + +unload_ecm() { + sysctl -w net.bridge.bridge-nf-call-ip6tables=0 + sysctl -w net.bridge.bridge-nf-call-iptables=0 + + if [ -d /sys/module/ecm ]; then + # + # Stop ECM frontends + # + echo 1 > /sys/kernel/debug/ecm/front_end_ipv4_stop + echo 1 > /sys/kernel/debug/ecm/front_end_ipv6_stop + + # + # Defunct the connections + # + echo 1 > /sys/kernel/debug/ecm/ecm_db/defunct_all + sleep 5; + + rmmod ecm + sleep 1 + fi +} + +start() { + load_ecm + + # If the acceleration engine is NSS, enable wifi redirect. + [ -d /sys/kernel/debug/ecm/ecm_nss_ipv4 ] && sysctl -w dev.nss.general.redirect=1 + + support_bridge && { + echo 'net.bridge.bridge-nf-call-ip6tables=1' >> /etc/sysctl.d/qca-nss-ecm.conf + echo 'net.bridge.bridge-nf-call-iptables=1' >> /etc/sysctl.d/qca-nss-ecm.conf + } + + if [ -d /sys/module/qca_ovsmgr ]; then + insmod ecm_ovs + fi + +} + +stop() { + # If ECM is already not loaded, just return. + if [ ! -d /sys/module/ecm ]; then + return + fi + + # If the acceleration engine is NSS, disable wifi redirect. + [ -d /sys/kernel/debug/ecm/ecm_nss_ipv4 ] && sysctl -w dev.nss.general.redirect=0 + + sed '/net.bridge.bridge-nf-call-ip6tables=1/d' -i /etc/sysctl.d/qca-nss-ecm.conf + sed '/net.bridge.bridge-nf-call-iptables=1/d' -i /etc/sysctl.d/qca-nss-ecm.conf + + if [ -d /sys/module/ecm_ovs ]; then + rmmod ecm_ovs + fi + + unload_ecm +} diff --git a/qaa/nss/qca-nss-ecm-64/files/qca-nss-ecm.sysctl b/qaa/nss/qca-nss-ecm-64/files/qca-nss-ecm.sysctl new file mode 100644 index 000000000..1a3d76b18 --- /dev/null +++ b/qaa/nss/qca-nss-ecm-64/files/qca-nss-ecm.sysctl @@ -0,0 +1,2 @@ +# nf_conntrack_tcp_no_window_check is 0 by default, set it to 1 +net.netfilter.nf_conntrack_tcp_no_window_check=1 diff --git a/qaa/nss/qca-nss-ecm-64/files/qca-nss-ecm.uci b/qaa/nss/qca-nss-ecm-64/files/qca-nss-ecm.uci new file mode 100644 index 000000000..4f2de6877 --- /dev/null +++ b/qaa/nss/qca-nss-ecm-64/files/qca-nss-ecm.uci @@ -0,0 +1,2 @@ +config ecm 'global' + option acceleration_engine 'auto' diff --git a/qaa/nss/qca-nss-ecm-64/patches/001-treewide-componentize-the-module-even-more.patch b/qaa/nss/qca-nss-ecm-64/patches/001-treewide-componentize-the-module-even-more.patch new file mode 100644 index 000000000..4e7932c9d --- /dev/null +++ b/qaa/nss/qca-nss-ecm-64/patches/001-treewide-componentize-the-module-even-more.patch @@ -0,0 +1,335 @@ +From 73345c87b28a473b35b57e673f8de963c3d73da1 Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Wed, 19 May 2021 02:38:53 +0200 +Subject: [PATCH] treewide: componentize the module even more + +Signed-off-by: Ansuel Smith +--- + Makefile | 56 +++++++++++++++++++++++++------- + ecm_db/ecm_db_connection.c | 8 +++++ + ecm_db/ecm_db_node.c | 4 +++ + ecm_interface.c | 8 +++++ + frontends/ecm_front_end_common.c | 7 ++++ + 5 files changed, 72 insertions(+), 11 deletions(-) + +--- a/Makefile ++++ b/Makefile +@@ -82,10 +82,18 @@ ccflags-$(ECM_INTERFACE_BOND_ENABLE) += + # Define ECM_INTERFACE_PPPOE_ENABLE=y in order + # to enable support for PPPoE acceleration. + # ############################################################################# +-ECM_INTERFACE_PPPOE_ENABLE=y ++ifndef $(ECM_INTERFACE_PPPOE_ENABLE) ++ ECM_INTERFACE_PPPOE_ENABLE=y ++endif + ccflags-$(ECM_INTERFACE_PPPOE_ENABLE) += -DECM_INTERFACE_PPPOE_ENABLE + + # ############################################################################# ++# Define ECM_INTERFACE_L2TPV2_PPTP_ENABLE=y in order ++# to enable support for l2tpv2 or PPTP detection. ++# ############################################################################# ++ccflags-$(ECM_INTERFACE_L2TPV2_PPTP_ENABLE) += -DECM_INTERFACE_L2TPV2_PPTP_ENABLE ++ ++# ############################################################################# + # Define ECM_INTERFACE_L2TPV2_ENABLE=y in order + # to enable support for l2tpv2 acceleration. + # ############################################################################# +@@ -118,6 +126,12 @@ ccflags-$(ECM_INTERFACE_PPP_ENABLE) += - + ccflags-$(ECM_INTERFACE_MAP_T_ENABLE) += -DECM_INTERFACE_MAP_T_ENABLE + + # ############################################################################# ++# Define ECM_INTERFACE_GRE_ENABLE=y in order ++# to enable support for GRE detection. ++# ############################################################################# ++ccflags-$(ECM_INTERFACE_GRE_ENABLE) += -DECM_INTERFACE_GRE_ENABLE ++ ++# ############################################################################# + # Define ECM_INTERFACE_GRE_TAP_ENABLE=y in order + # to enable support for GRE TAP interface. + # ############################################################################# +@@ -186,7 +200,9 @@ ccflags-$(ECM_INTERFACE_OVS_BRIDGE_ENABL + # ############################################################################# + # Define ECM_INTERFACE_VLAN_ENABLE=y in order to enable support for VLAN + # ############################################################################# +-ECM_INTERFACE_VLAN_ENABLE=y ++ifndef $(ECM_INTERFACE_VLAN_ENABLE) ++ ECM_INTERFACE_VLAN_ENABLE=y ++endif + ccflags-$(ECM_INTERFACE_VLAN_ENABLE) += -DECM_INTERFACE_VLAN_ENABLE + + # ############################################################################# +@@ -228,7 +244,9 @@ ccflags-$(ECM_CLASSIFIER_OVS_ENABLE) += + # ############################################################################# + # Define ECM_CLASSIFIER_MARK_ENABLE=y in order to enable mark classifier. + # ############################################################################# +-ECM_CLASSIFIER_MARK_ENABLE=y ++ifndef $(ECM_CLASSIFIER_MARK_ENABLE) ++ ECM_CLASSIFIER_MARK_ENABLE=y ++endif + ecm-$(ECM_CLASSIFIER_MARK_ENABLE) += ecm_classifier_mark.o + ccflags-$(ECM_CLASSIFIER_MARK_ENABLE) += -DECM_CLASSIFIER_MARK_ENABLE + +@@ -247,7 +265,9 @@ ccflags-$(ECM_CLASSIFIER_NL_ENABLE) += - + # ############################################################################# + # Define ECM_CLASSIFIER_DSCP_ENABLE=y in order to enable DSCP classifier. + # ############################################################################# +-ECM_CLASSIFIER_DSCP_ENABLE=y ++ifndef $(ECM_CLASSIFIER_DSCP_ENABLE) ++ ECM_CLASSIFIER_DSCP_ENABLE=y ++endif + ecm-$(ECM_CLASSIFIER_DSCP_ENABLE) += ecm_classifier_dscp.o + ccflags-$(ECM_CLASSIFIER_DSCP_ENABLE) += -DECM_CLASSIFIER_DSCP_ENABLE + ccflags-$(ECM_CLASSIFIER_DSCP_IGS) += -DECM_CLASSIFIER_DSCP_IGS +@@ -274,7 +294,9 @@ endif + # the Parental Controls subsystem classifier in ECM. Currently disabled until + # customers require it / if they need to integrate their Parental Controls with it. + # ############################################################################# +-ECM_CLASSIFIER_PCC_ENABLE=y ++ifndef $(ECM_CLASSIFIER_PCC_ENABLE) ++ ECM_CLASSIFIER_PCC_ENABLE=y ++endif + ecm-$(ECM_CLASSIFIER_PCC_ENABLE) += ecm_classifier_pcc.o + ccflags-$(ECM_CLASSIFIER_PCC_ENABLE) += -DECM_CLASSIFIER_PCC_ENABLE + +@@ -301,28 +323,36 @@ ccflags-$(ECM_NON_PORTED_SUPPORT_ENABLE) + # ############################################################################# + # Define ECM_STATE_OUTPUT_ENABLE=y to support XML state output + # ############################################################################# +-ECM_STATE_OUTPUT_ENABLE=y ++ifndef $(ECM_STATE_OUTPUT_ENABLE) ++ ECM_STATE_OUTPUT_ENABLE=y ++endif + ecm-$(ECM_STATE_OUTPUT_ENABLE) += ecm_state.o + ccflags-$(ECM_STATE_OUTPUT_ENABLE) += -DECM_STATE_OUTPUT_ENABLE + + # ############################################################################# + # Define ECM_DB_ADVANCED_STATS_ENABLE to support XML state output + # ############################################################################# +-ECM_DB_ADVANCED_STATS_ENABLE=y ++ifndef $(ECM_DB_ADVANCED_STATS_ENABLE) ++ ECM_DB_ADVANCED_STATS_ENABLE=y ++endif + ccflags-$(ECM_DB_ADVANCED_STATS_ENABLE) += -DECM_DB_ADVANCED_STATS_ENABLE + + # ############################################################################# + # Define ECM_DB_CONNECTION_CROSS_REFERENCING_ENABLE=y in order to enable + # the database to track relationships between objects. + # ############################################################################# +-ECM_DB_CONNECTION_CROSS_REFERENCING_ENABLE=y ++ifndef $(ECM_DB_CONNECTION_CROSS_REFERENCING_ENABLE) ++ ECM_DB_CONNECTION_CROSS_REFERENCING_ENABLE=y ++endif + ccflags-$(ECM_DB_CONNECTION_CROSS_REFERENCING_ENABLE) += -DECM_DB_XREF_ENABLE + + # ############################################################################# + # Define ECM_TRACKER_DPI_SUPPORT_ENABLE=y in order to enable support for + # deep packet inspection and tracking of data with the trackers. + # ############################################################################# +-ECM_TRACKER_DPI_SUPPORT_ENABLE=y ++ifndef $(ECM_TRACKER_DPI_SUPPORT_ENABLE) ++ ECM_TRACKER_DPI_SUPPORT_ENABLE=y ++endif + ccflags-$(ECM_TRACKER_DPI_SUPPORT_ENABLE) += -DECM_TRACKER_DPI_SUPPORT_ENABLE + + # ############################################################################# +@@ -330,14 +360,18 @@ ccflags-$(ECM_TRACKER_DPI_SUPPORT_ENABLE + # support for the database keeping lists of connections that are assigned + # on a per TYPE of classifier basis. + # ############################################################################# +-ECM_DB_CLASSIFIER_TYPE_ASSIGNMENTS_TRACK_ENABLE=y ++ifndef $(ECM_DB_CLASSIFIER_TYPE_ASSIGNMENTS_TRACK_ENABLE) ++ ECM_DB_CLASSIFIER_TYPE_ASSIGNMENTS_TRACK_ENABLE=y ++endif + ccflags-$(ECM_DB_CLASSIFIER_TYPE_ASSIGNMENTS_TRACK_ENABLE) += -DECM_DB_CTA_TRACK_ENABLE + + # ############################################################################# + # Define ECM_BAND_STEERING_ENABLE=y in order to enable + # band steering feature. + # ############################################################################# +-ECM_BAND_STEERING_ENABLE=y ++ifndef $(ECM_BAND_STEERING_ENABLE) ++ ECM_BAND_STEERING_ENABLE=y ++endif + ccflags-$(ECM_BAND_STEERING_ENABLE) += -DECM_BAND_STEERING_ENABLE + + # ############################################################################# +--- a/ecm_db/ecm_db_connection.c ++++ b/ecm_db/ecm_db_connection.c +@@ -430,7 +430,9 @@ EXPORT_SYMBOL(ecm_db_connection_make_def + */ + void ecm_db_connection_data_totals_update(struct ecm_db_connection_instance *ci, bool is_from, uint64_t size, uint64_t packets) + { ++#ifdef ECM_DB_ADVANCED_STATS_ENABLE + int32_t i; ++#endif + + DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed\n", ci); + +@@ -529,7 +531,9 @@ EXPORT_SYMBOL(ecm_db_connection_data_tot + */ + void ecm_db_connection_data_totals_update_dropped(struct ecm_db_connection_instance *ci, bool is_from, uint64_t size, uint64_t packets) + { ++#ifdef ECM_DB_ADVANCED_STATS_ENABLE + int32_t i; ++#endif + + DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed\n", ci); + +@@ -1508,6 +1512,7 @@ void ecm_db_connection_defunct_all(void) + } + EXPORT_SYMBOL(ecm_db_connection_defunct_all); + ++#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE + /* + * ecm_db_connection_defunct_by_classifier() + * Make defunct based on masked fields +@@ -1667,6 +1672,7 @@ next_ci: + ECM_IP_ADDR_TO_OCTAL(dest_addr_mask), dest_port_mask, proto_mask, cnt); + } + } ++#endif + + /* + * ecm_db_connection_defunct_by_port() +@@ -1956,6 +1962,7 @@ struct ecm_db_node_instance *ecm_db_conn + } + EXPORT_SYMBOL(ecm_db_connection_node_get_and_ref); + ++#ifdef ECM_DB_XREF_ENABLE + /* + * ecm_db_connection_mapping_get_and_ref_next() + * Return reference to next connection in the mapping chain in the specified direction. +@@ -1997,6 +2004,7 @@ struct ecm_db_connection_instance *ecm_d + return nci; + } + EXPORT_SYMBOL(ecm_db_connection_iface_get_and_ref_next); ++#endif + + /* + * ecm_db_connection_mapping_get_and_ref() +--- a/ecm_db/ecm_db_node.c ++++ b/ecm_db/ecm_db_node.c +@@ -224,9 +224,11 @@ EXPORT_SYMBOL(ecm_db_node_get_and_ref_ne + */ + int ecm_db_node_deref(struct ecm_db_node_instance *ni) + { ++#ifdef ECM_DB_XREF_ENABLE + #if (DEBUG_LEVEL >= 1) + int dir; + #endif ++#endif + DEBUG_CHECK_MAGIC(ni, ECM_DB_NODE_INSTANCE_MAGIC, "%px: magic failed\n", ni); + + spin_lock_bh(&ecm_db_lock); +@@ -486,9 +488,11 @@ EXPORT_SYMBOL(ecm_db_node_iface_get_and_ + void ecm_db_node_add(struct ecm_db_node_instance *ni, struct ecm_db_iface_instance *ii, uint8_t *address, + ecm_db_node_final_callback_t final, void *arg) + { ++#ifdef ECM_DB_XREF_ENABLE + #if (DEBUG_LEVEL >= 1) + int dir; + #endif ++#endif + ecm_db_node_hash_t hash_index; + struct ecm_db_listener_instance *li; + +--- a/ecm_interface.c ++++ b/ecm_interface.c +@@ -1343,6 +1343,7 @@ struct neighbour *ecm_interface_ipv6_nei + */ + bool ecm_interface_is_pptp(struct sk_buff *skb, const struct net_device *out) + { ++#ifdef ECM_INTERFACE_PPTP_ENABLE + struct net_device *in; + + /* +@@ -1367,6 +1368,7 @@ bool ecm_interface_is_pptp(struct sk_buf + } + + dev_put(in); ++#endif + return false; + } + +@@ -1379,6 +1381,7 @@ bool ecm_interface_is_pptp(struct sk_buf + */ + bool ecm_interface_is_l2tp_packet_by_version(struct sk_buff *skb, const struct net_device *out, int ver) + { ++#ifdef ECM_INTERFACE_L2TPV2_PPTP_ENABLE + uint32_t flag = 0; + struct net_device *in; + +@@ -1411,6 +1414,7 @@ bool ecm_interface_is_l2tp_packet_by_ver + } + + dev_put(in); ++#endif + return false; + } + +@@ -1423,6 +1427,7 @@ bool ecm_interface_is_l2tp_packet_by_ver + */ + bool ecm_interface_is_l2tp_pptp(struct sk_buff *skb, const struct net_device *out) + { ++#ifdef ECM_INTERFACE_L2TPV2_PPTP_ENABLE + struct net_device *in; + + /* +@@ -1445,6 +1450,7 @@ bool ecm_interface_is_l2tp_pptp(struct s + } + + dev_put(in); ++#endif + return false; + } + +@@ -6630,6 +6636,7 @@ static void ecm_interface_regenerate_con + return; + } + ++#ifdef ECM_DB_XREF_ENABLE + for (dir = 0; dir < ECM_DB_OBJ_DIR_MAX; dir++) { + /* + * Re-generate all connections associated with this interface +@@ -6645,6 +6652,7 @@ static void ecm_interface_regenerate_con + ci[dir] = cin; + } + } ++#endif + + #ifdef ECM_MULTICAST_ENABLE + /* +--- a/frontends/ecm_front_end_common.c ++++ b/frontends/ecm_front_end_common.c +@@ -106,6 +106,7 @@ bool ecm_front_end_gre_proto_is_accel_al + struct nf_conntrack_tuple *tuple, + int ip_version) + { ++#ifdef ECM_INTERFACE_GRE_ENABLE + struct net_device *dev; + struct gre_base_hdr *greh; + +@@ -117,10 +118,12 @@ bool ecm_front_end_gre_proto_is_accel_al + /* + * Case 1: PPTP locally terminated + */ ++#ifdef ECM_INTERFACE_PPTP_ENABLE + if (ecm_interface_is_pptp(skb, outdev)) { + DEBUG_TRACE("%px: PPTP GRE locally terminated - allow acceleration\n", skb); + return true; + } ++#endif + + /* + * Case 2: PPTP pass through +@@ -223,6 +226,10 @@ bool ecm_front_end_gre_proto_is_accel_al + */ + DEBUG_TRACE("%px: GRE IPv%d pass through - allow acceleration\n", skb, ip_version); + return true; ++#else ++ DEBUG_TRACE("%px: GRE%d feature is disabled - do not allow acceleration\n", skb, ip_version); ++ return false; ++#endif + } + + #ifdef ECM_CLASSIFIER_DSCP_ENABLE diff --git a/qaa/nss/qca-nss-ecm-64/patches/100-kernel-5.10-support.patch b/qaa/nss/qca-nss-ecm-64/patches/100-kernel-5.10-support.patch new file mode 100644 index 000000000..107b9571b --- /dev/null +++ b/qaa/nss/qca-nss-ecm-64/patches/100-kernel-5.10-support.patch @@ -0,0 +1,831 @@ +From e8b642c23af9146c973e828a7f4e0fb56cfc8d0b Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Sat, 15 May 2021 03:51:14 +0200 +Subject: [PATCH] add support for kernel 5.10 + +Signed-off-by: Ansuel Smith +--- + ecm_classifier_default.c | 24 +++--------- + ecm_classifier_dscp.c | 8 +--- + ecm_classifier_emesh.c | 16 ++------ + ecm_classifier_hyfi.c | 7 +--- + ecm_classifier_mark.c | 8 +--- + ecm_classifier_ovs.c | 8 +--- + ecm_classifier_pcc.c | 8 +--- + ecm_conntrack_notifier.c | 8 +--- + ecm_db/ecm_db_connection.c | 7 +--- + ecm_db/ecm_db_host.c | 7 +--- + ecm_db/ecm_db_iface.c | 7 +--- + ecm_db/ecm_db_mapping.c | 7 +--- + ecm_db/ecm_db_node.c | 7 +--- + ecm_interface.c | 4 +- + ecm_state.c | 14 ++----- + frontends/ecm_front_end_common.c | 4 +- + frontends/ecm_front_end_ipv4.c | 7 +--- + frontends/ecm_front_end_ipv6.c | 7 +--- + frontends/nss/ecm_nss_bond_notifier.c | 8 +--- + frontends/nss/ecm_nss_ipv4.c | 49 +++++++------------------ + frontends/nss/ecm_nss_ipv6.c | 49 +++++++------------------ + frontends/nss/ecm_nss_multicast_ipv4.c | 7 +--- + frontends/nss/ecm_nss_multicast_ipv6.c | 7 +--- + frontends/nss/ecm_nss_non_ported_ipv4.c | 7 +--- + frontends/nss/ecm_nss_non_ported_ipv6.c | 7 +--- + frontends/nss/ecm_nss_ported_ipv4.c | 8 +--- + frontends/nss/ecm_nss_ported_ipv6.c | 8 +--- + frontends/sfe/ecm_sfe_ipv4.c | 49 +++++++------------------ + frontends/sfe/ecm_sfe_ipv6.c | 49 +++++++------------------ + frontends/sfe/ecm_sfe_non_ported_ipv4.c | 7 +--- + frontends/sfe/ecm_sfe_non_ported_ipv6.c | 7 +--- + frontends/sfe/ecm_sfe_ported_ipv4.c | 8 +--- + frontends/sfe/ecm_sfe_ported_ipv6.c | 8 +--- + 33 files changed, 122 insertions(+), 314 deletions(-) + +--- a/ecm_classifier_default.c ++++ b/ecm_classifier_default.c +@@ -776,26 +776,14 @@ int ecm_classifier_default_init(struct d + return -1; + } + +- if (!debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_default_dentry, +- (u32 *)&ecm_classifier_default_enabled)) { +- DEBUG_ERROR("Failed to create ecm deafult classifier enabled file in debugfs\n"); +- debugfs_remove_recursive(ecm_classifier_default_dentry); +- return -1; +- } ++ debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_default_dentry, ++ (u32 *)&ecm_classifier_default_enabled); + +- if (!debugfs_create_u32("accel_mode", S_IRUGO | S_IWUSR, ecm_classifier_default_dentry, +- (u32 *)&ecm_classifier_default_accel_mode)) { +- DEBUG_ERROR("Failed to create ecm deafult classifier accel_mode file in debugfs\n"); +- debugfs_remove_recursive(ecm_classifier_default_dentry); +- return -1; +- } ++ debugfs_create_u32("accel_mode", S_IRUGO | S_IWUSR, ecm_classifier_default_dentry, ++ (u32 *)&ecm_classifier_default_accel_mode); + +- if (!debugfs_create_u32("accel_delay_pkts", S_IRUGO | S_IWUSR, ecm_classifier_default_dentry, +- (u32 *)&ecm_classifier_accel_delay_pkts)) { +- DEBUG_ERROR("Failed to create accel delay packet counts in debugfs\n"); +- debugfs_remove_recursive(ecm_classifier_default_dentry); +- return -1; +- } ++ debugfs_create_u32("accel_delay_pkts", S_IRUGO | S_IWUSR, ecm_classifier_default_dentry, ++ (u32 *)&ecm_classifier_accel_delay_pkts); + + return 0; + } +--- a/ecm_classifier_dscp.c ++++ b/ecm_classifier_dscp.c +@@ -747,12 +747,8 @@ int ecm_classifier_dscp_init(struct dent + return -1; + } + +- if (!debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_dscp_dentry, +- (u32 *)&ecm_classifier_dscp_enabled)) { +- DEBUG_ERROR("Failed to create dscp enabled file in debugfs\n"); +- debugfs_remove_recursive(ecm_classifier_dscp_dentry); +- return -1; +- } ++ debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_dscp_dentry, ++ (u32 *)&ecm_classifier_dscp_enabled); + + return 0; + } +--- a/ecm_classifier_emesh.c ++++ b/ecm_classifier_emesh.c +@@ -977,19 +977,11 @@ int ecm_classifier_emesh_init(struct den + return -1; + } + +- if (!debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_emesh_dentry, +- (u32 *)&ecm_classifier_emesh_enabled)) { +- DEBUG_ERROR("Failed to create ecm emesh classifier enabled file in debugfs\n"); +- debugfs_remove_recursive(ecm_classifier_emesh_dentry); +- return -1; +- } ++ debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_emesh_dentry, ++ (u32 *)&ecm_classifier_emesh_enabled); + +- if (!debugfs_create_u32("latency_config_enabled", S_IRUGO | S_IWUSR, ecm_classifier_emesh_dentry, +- (u32 *)&ecm_classifier_emesh_latency_config_enabled)) { +- DEBUG_ERROR("Failed to create ecm emesh classifier latency config enabled file in debugfs\n"); +- debugfs_remove_recursive(ecm_classifier_emesh_dentry); +- return -1; +- } ++ debugfs_create_u32("latency_config_enabled", S_IRUGO | S_IWUSR, ecm_classifier_emesh_dentry, ++ (u32 *)&ecm_classifier_emesh_latency_config_enabled); + + /* + * Register for service prioritization notification update. +--- a/ecm_classifier_hyfi.c ++++ b/ecm_classifier_hyfi.c +@@ -1099,11 +1099,8 @@ int ecm_classifier_hyfi_rules_init(struc + goto classifier_task_cleanup; + } + +- if (!debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_hyfi_dentry, +- (u32 *)&ecm_classifier_hyfi_enabled)) { +- DEBUG_ERROR("Failed to create ecm hyfi classifier enabled file in debugfs\n"); +- goto classifier_task_cleanup; +- } ++ debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_hyfi_dentry, ++ (u32 *)&ecm_classifier_hyfi_enabled); + + if (!debugfs_create_file("cmd", S_IWUSR, ecm_classifier_hyfi_dentry, + NULL, &ecm_classifier_hyfi_cmd_fops)) { +--- a/ecm_classifier_mark.c ++++ b/ecm_classifier_mark.c +@@ -753,12 +753,8 @@ int ecm_classifier_mark_init(struct dent + return -1; + } + +- if (!debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_mark_dentry, +- (u32 *)&ecm_classifier_mark_enabled)) { +- DEBUG_ERROR("Failed to create mark enabled file in debugfs\n"); +- debugfs_remove_recursive(ecm_classifier_mark_dentry); +- return -1; +- } ++ debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_mark_dentry, ++ (u32 *)&ecm_classifier_mark_enabled); + + return 0; + } +--- a/ecm_classifier_ovs.c ++++ b/ecm_classifier_ovs.c +@@ -2200,12 +2200,8 @@ int ecm_classifier_ovs_init(struct dentr + return -1; + } + +- if (!debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_ovs_dentry, +- (u32 *)&ecm_classifier_ovs_enabled)) { +- DEBUG_ERROR("Failed to create ovs enabled file in debugfs\n"); +- debugfs_remove_recursive(ecm_classifier_ovs_dentry); +- return -1; +- } ++ debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_ovs_dentry, ++ (u32 *)&ecm_classifier_ovs_enabled); + + return 0; + } +--- a/ecm_classifier_pcc.c ++++ b/ecm_classifier_pcc.c +@@ -1308,12 +1308,8 @@ int ecm_classifier_pcc_init(struct dentr + return -1; + } + +- if (!debugfs_create_u32("enabled", S_IRUGO, ecm_classifier_pcc_dentry, +- (u32 *)&ecm_classifier_pcc_enabled)) { +- DEBUG_ERROR("Failed to create pcc enabled file in debugfs\n"); +- debugfs_remove_recursive(ecm_classifier_pcc_dentry); +- return -1; +- } ++ debugfs_create_u32("enabled", S_IRUGO, ecm_classifier_pcc_dentry, ++ (u32 *)&ecm_classifier_pcc_enabled); + + return 0; + } +--- a/ecm_conntrack_notifier.c ++++ b/ecm_conntrack_notifier.c +@@ -414,12 +414,8 @@ int ecm_conntrack_notifier_init(struct d + return -1; + } + +- if (!debugfs_create_u32("stop", S_IRUGO | S_IWUSR, ecm_conntrack_notifier_dentry, +- (u32 *)&ecm_conntrack_notifier_stopped)) { +- DEBUG_ERROR("Failed to create ecm conntrack notifier stopped file in debugfs\n"); +- debugfs_remove_recursive(ecm_conntrack_notifier_dentry); +- return -1; +- } ++ debugfs_create_u32("stop", S_IRUGO | S_IWUSR, ecm_conntrack_notifier_dentry, ++ (u32 *)&ecm_conntrack_notifier_stopped); + + #ifdef CONFIG_NF_CONNTRACK_EVENTS + /* +--- a/ecm_db/ecm_db_connection.c ++++ b/ecm_db/ecm_db_connection.c +@@ -3642,11 +3642,8 @@ static struct file_operations ecm_db_con + */ + bool ecm_db_connection_init(struct dentry *dentry) + { +- if (!debugfs_create_u32("connection_count", S_IRUGO, dentry, +- (u32 *)&ecm_db_connection_count)) { +- DEBUG_ERROR("Failed to create ecm db connection count file in debugfs\n"); +- return false; +- } ++ debugfs_create_u32("connection_count", S_IRUGO, dentry, ++ (u32 *)&ecm_db_connection_count); + + if (!debugfs_create_file("connection_count_simple", S_IRUGO, dentry, + NULL, &ecm_db_connection_count_simple_fops)) { +--- a/ecm_db/ecm_db_host.c ++++ b/ecm_db/ecm_db_host.c +@@ -770,11 +770,8 @@ EXPORT_SYMBOL(ecm_db_host_alloc); + bool ecm_db_host_init(struct dentry *dentry) + { + +- if (!debugfs_create_u32("host_count", S_IRUGO, dentry, +- (u32 *)&ecm_db_host_count)) { +- DEBUG_ERROR("Failed to create ecm db host count file in debugfs\n"); +- return false;; +- } ++ debugfs_create_u32("host_count", S_IRUGO, dentry, ++ (u32 *)&ecm_db_host_count); + + ecm_db_host_table = vzalloc(sizeof(struct ecm_db_host_instance *) * ECM_DB_HOST_HASH_SLOTS); + if (!ecm_db_host_table) { +--- a/ecm_db/ecm_db_iface.c ++++ b/ecm_db/ecm_db_iface.c +@@ -3670,11 +3670,8 @@ EXPORT_SYMBOL(ecm_db_iface_alloc); + */ + bool ecm_db_iface_init(struct dentry *dentry) + { +- if (!debugfs_create_u32("iface_count", S_IRUGO, dentry, +- (u32 *)&ecm_db_iface_count)) { +- DEBUG_ERROR("Failed to create ecm db iface count file in debugfs\n"); +- return false; +- } ++ debugfs_create_u32("iface_count", S_IRUGO, dentry, ++ (u32 *)&ecm_db_iface_count); + + return true; + } +--- a/ecm_db/ecm_db_mapping.c ++++ b/ecm_db/ecm_db_mapping.c +@@ -806,11 +806,8 @@ EXPORT_SYMBOL(ecm_db_mapping_alloc); + */ + bool ecm_db_mapping_init(struct dentry *dentry) + { +- if (!debugfs_create_u32("mapping_count", S_IRUGO, dentry, +- (u32 *)&ecm_db_mapping_count)) { +- DEBUG_ERROR("Failed to create ecm db mapping count file in debugfs\n"); +- return false; +- } ++ debugfs_create_u32("mapping_count", S_IRUGO, dentry, ++ (u32 *)&ecm_db_mapping_count); + + ecm_db_mapping_table = vzalloc(sizeof(struct ecm_db_mapping_instance *) * ECM_DB_MAPPING_HASH_SLOTS); + if (!ecm_db_mapping_table) { +--- a/ecm_db/ecm_db_node.c ++++ b/ecm_db/ecm_db_node.c +@@ -1187,11 +1187,8 @@ keep_sni_conn: + */ + bool ecm_db_node_init(struct dentry *dentry) + { +- if (!debugfs_create_u32("node_count", S_IRUGO, dentry, +- (u32 *)&ecm_db_node_count)) { +- DEBUG_ERROR("Failed to create ecm db node count file in debugfs\n"); +- return false; +- } ++ debugfs_create_u32("node_count", S_IRUGO, dentry, ++ (u32 *)&ecm_db_node_count); + + ecm_db_node_table = vzalloc(sizeof(struct ecm_db_node_instance *) * ECM_DB_NODE_HASH_SLOTS); + if (!ecm_db_node_table) { +--- a/ecm_interface.c ++++ b/ecm_interface.c +@@ -332,7 +332,7 @@ static struct net_device *ecm_interface_ + struct net_device *dev; + + ECM_IP_ADDR_TO_NIN6_ADDR(addr6, addr); +- dev = (struct net_device *)ipv6_dev_find(&init_net, &addr6, 1); ++ dev = (struct net_device *)ipv6_dev_find_and_hold(&init_net, &addr6, 1); + return dev; + } + #endif +@@ -734,7 +734,7 @@ static bool ecm_interface_mac_addr_get_i + * Get the MAC address that corresponds to IP address given. + */ + ECM_IP_ADDR_TO_NIN6_ADDR(daddr, addr); +- local_dev = ipv6_dev_find(&init_net, &daddr, 1); ++ local_dev = ipv6_dev_find_and_hold(&init_net, &daddr, 1); + if (local_dev) { + DEBUG_TRACE("%pi6 is a local address\n", &daddr); + memcpy(mac_addr, dev->dev_addr, ETH_ALEN); +--- a/ecm_state.c ++++ b/ecm_state.c +@@ -899,17 +899,11 @@ int ecm_state_init(struct dentry *dentry + return -1; + } + +- if (!debugfs_create_u32("state_dev_major", S_IRUGO, ecm_state_dentry, +- (u32 *)&ecm_state_dev_major_id)) { +- DEBUG_ERROR("Failed to create ecm state dev major file in debugfs\n"); +- goto init_cleanup; +- } ++ debugfs_create_u32("state_dev_major", S_IRUGO, ecm_state_dentry, ++ (u32 *)&ecm_state_dev_major_id); + +- if (!debugfs_create_u32("state_file_output_mask", S_IRUGO | S_IWUSR, ecm_state_dentry, +- (u32 *)&ecm_state_file_output_mask)) { +- DEBUG_ERROR("Failed to create ecm state output mask file in debugfs\n"); +- goto init_cleanup; +- } ++ debugfs_create_u32("state_file_output_mask", S_IRUGO | S_IWUSR, ecm_state_dentry, ++ (u32 *)&ecm_state_file_output_mask); + + /* + * Register a char device that we will use to provide a dump of our state +--- a/frontends/ecm_front_end_common.c ++++ b/frontends/ecm_front_end_common.c +@@ -192,7 +192,7 @@ bool ecm_front_end_gre_proto_is_accel_al + return false; + } + } else { +- dev = ipv6_dev_find(&init_net, &(tuple->src.u3.in6), 1); ++ dev = ipv6_dev_find_and_hold(&init_net, &(tuple->src.u3.in6), 1); + if (dev) { + /* + * Source IP address is local +@@ -202,7 +202,7 @@ bool ecm_front_end_gre_proto_is_accel_al + return false; + } + +- dev = ipv6_dev_find(&init_net, &(tuple->dst.u3.in6), 1); ++ dev = ipv6_dev_find_and_hold(&init_net, &(tuple->dst.u3.in6), 1); + if (dev) { + /* + * Destination IP address is local +--- a/frontends/ecm_front_end_ipv4.c ++++ b/frontends/ecm_front_end_ipv4.c +@@ -376,11 +376,8 @@ void ecm_front_end_ipv4_stop(int num) + */ + int ecm_front_end_ipv4_init(struct dentry *dentry) + { +- if (!debugfs_create_u32("front_end_ipv4_stop", S_IRUGO | S_IWUSR, dentry, +- (u32 *)&ecm_front_end_ipv4_stopped)) { +- DEBUG_ERROR("Failed to create ecm front end ipv4 stop file in debugfs\n"); +- return -1; +- } ++ debugfs_create_u32("front_end_ipv4_stop", S_IRUGO | S_IWUSR, dentry, ++ (u32 *)&ecm_front_end_ipv4_stopped); + + switch (ecm_front_end_type_get()) { + case ECM_FRONT_END_TYPE_NSS: +--- a/frontends/ecm_front_end_ipv6.c ++++ b/frontends/ecm_front_end_ipv6.c +@@ -255,11 +255,8 @@ void ecm_front_end_ipv6_stop(int num) + */ + int ecm_front_end_ipv6_init(struct dentry *dentry) + { +- if (!debugfs_create_u32("front_end_ipv6_stop", S_IRUGO | S_IWUSR, dentry, +- (u32 *)&ecm_front_end_ipv6_stopped)) { +- DEBUG_ERROR("Failed to create ecm front end ipv6 stop file in debugfs\n"); +- return -1; +- } ++ debugfs_create_u32("front_end_ipv6_stop", S_IRUGO | S_IWUSR, dentry, ++ (u32 *)&ecm_front_end_ipv6_stopped); + + switch (ecm_front_end_type_get()) { + case ECM_FRONT_END_TYPE_NSS: +--- a/frontends/nss/ecm_nss_bond_notifier.c ++++ b/frontends/nss/ecm_nss_bond_notifier.c +@@ -240,12 +240,8 @@ int ecm_nss_bond_notifier_init(struct de + return -1; + } + +- if (!debugfs_create_u32("stop", S_IRUGO | S_IWUSR, ecm_nss_bond_notifier_dentry, +- (u32 *)&ecm_nss_bond_notifier_stopped)) { +- DEBUG_ERROR("Failed to create ecm bond notifier stopped file in debugfs\n"); +- debugfs_remove_recursive(ecm_nss_bond_notifier_dentry); +- return -1; +- } ++ debugfs_create_u32("stop", S_IRUGO | S_IWUSR, ecm_nss_bond_notifier_dentry, ++ (u32 *)&ecm_nss_bond_notifier_stopped); + + /* + * Register Link Aggregation callbacks with the bonding driver +--- a/frontends/nss/ecm_nss_ipv4.c ++++ b/frontends/nss/ecm_nss_ipv4.c +@@ -2802,41 +2802,23 @@ int ecm_nss_ipv4_init(struct dentry *den + return result; + } + +- if (!debugfs_create_u32("no_action_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, +- (u32 *)&ecm_nss_ipv4_no_action_limit_default)) { +- DEBUG_ERROR("Failed to create ecm nss ipv4 no_action_limit_default file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("no_action_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, ++ (u32 *)&ecm_nss_ipv4_no_action_limit_default); + +- if (!debugfs_create_u32("driver_fail_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, +- (u32 *)&ecm_nss_ipv4_driver_fail_limit_default)) { +- DEBUG_ERROR("Failed to create ecm nss ipv4 driver_fail_limit_default file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("driver_fail_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, ++ (u32 *)&ecm_nss_ipv4_driver_fail_limit_default); + +- if (!debugfs_create_u32("nack_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, +- (u32 *)&ecm_nss_ipv4_nack_limit_default)) { +- DEBUG_ERROR("Failed to create ecm nss ipv4 nack_limit_default file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("nack_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, ++ (u32 *)&ecm_nss_ipv4_nack_limit_default); + +- if (!debugfs_create_u32("accelerated_count", S_IRUGO, ecm_nss_ipv4_dentry, +- (u32 *)&ecm_nss_ipv4_accelerated_count)) { +- DEBUG_ERROR("Failed to create ecm nss ipv4 accelerated_count file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("accelerated_count", S_IRUGO, ecm_nss_ipv4_dentry, ++ (u32 *)&ecm_nss_ipv4_accelerated_count); + +- if (!debugfs_create_u32("pending_accel_count", S_IRUGO, ecm_nss_ipv4_dentry, +- (u32 *)&ecm_nss_ipv4_pending_accel_count)) { +- DEBUG_ERROR("Failed to create ecm nss ipv4 pending_accel_count file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("pending_accel_count", S_IRUGO, ecm_nss_ipv4_dentry, ++ (u32 *)&ecm_nss_ipv4_pending_accel_count); + +- if (!debugfs_create_u32("pending_decel_count", S_IRUGO, ecm_nss_ipv4_dentry, +- (u32 *)&ecm_nss_ipv4_pending_decel_count)) { +- DEBUG_ERROR("Failed to create ecm nss ipv4 pending_decel_count file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("pending_decel_count", S_IRUGO, ecm_nss_ipv4_dentry, ++ (u32 *)&ecm_nss_ipv4_pending_decel_count); + + if (!debugfs_create_file("accel_limit_mode", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, + NULL, &ecm_nss_ipv4_accel_limit_mode_fops)) { +@@ -2867,11 +2849,8 @@ int ecm_nss_ipv4_init(struct dentry *den + goto task_cleanup; + } + +- if (!debugfs_create_u32("vlan_passthrough_set", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, +- (u32 *)&ecm_nss_ipv4_vlan_passthrough_enable)) { +- DEBUG_ERROR("Failed to create ecm nss ipv4 vlan passthrough file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("vlan_passthrough_set", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, ++ (u32 *)&ecm_nss_ipv4_vlan_passthrough_enable); + + #ifdef ECM_NON_PORTED_SUPPORT_ENABLE + if (!ecm_nss_non_ported_ipv4_debugfs_init(ecm_nss_ipv4_dentry)) { +--- a/frontends/nss/ecm_nss_ipv6.c ++++ b/frontends/nss/ecm_nss_ipv6.c +@@ -2542,41 +2542,23 @@ int ecm_nss_ipv6_init(struct dentry *den + return result; + } + +- if (!debugfs_create_u32("no_action_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, +- (u32 *)&ecm_nss_ipv6_no_action_limit_default)) { +- DEBUG_ERROR("Failed to create ecm nss ipv6 no_action_limit_default file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("no_action_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, ++ (u32 *)&ecm_nss_ipv6_no_action_limit_default); + +- if (!debugfs_create_u32("driver_fail_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, +- (u32 *)&ecm_nss_ipv6_driver_fail_limit_default)) { +- DEBUG_ERROR("Failed to create ecm nss ipv6 driver_fail_limit_default file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("driver_fail_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, ++ (u32 *)&ecm_nss_ipv6_driver_fail_limit_default); + +- if (!debugfs_create_u32("nack_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, +- (u32 *)&ecm_nss_ipv6_nack_limit_default)) { +- DEBUG_ERROR("Failed to create ecm nss ipv6 nack_limit_default file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("nack_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, ++ (u32 *)&ecm_nss_ipv6_nack_limit_default); + +- if (!debugfs_create_u32("accelerated_count", S_IRUGO, ecm_nss_ipv6_dentry, +- (u32 *)&ecm_nss_ipv6_accelerated_count)) { +- DEBUG_ERROR("Failed to create ecm nss ipv6 accelerated_count file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("accelerated_count", S_IRUGO, ecm_nss_ipv6_dentry, ++ (u32 *)&ecm_nss_ipv6_accelerated_count); + +- if (!debugfs_create_u32("pending_accel_count", S_IRUGO, ecm_nss_ipv6_dentry, +- (u32 *)&ecm_nss_ipv6_pending_accel_count)) { +- DEBUG_ERROR("Failed to create ecm nss ipv6 pending_accel_count file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("pending_accel_count", S_IRUGO, ecm_nss_ipv6_dentry, ++ (u32 *)&ecm_nss_ipv6_pending_accel_count); + +- if (!debugfs_create_u32("pending_decel_count", S_IRUGO, ecm_nss_ipv6_dentry, +- (u32 *)&ecm_nss_ipv6_pending_decel_count)) { +- DEBUG_ERROR("Failed to create ecm nss ipv6 pending_decel_count file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("pending_decel_count", S_IRUGO, ecm_nss_ipv6_dentry, ++ (u32 *)&ecm_nss_ipv6_pending_decel_count); + + if (!debugfs_create_file("accel_limit_mode", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, + NULL, &ecm_nss_ipv6_accel_limit_mode_fops)) { +@@ -2607,11 +2589,8 @@ int ecm_nss_ipv6_init(struct dentry *den + goto task_cleanup; + } + +- if (!debugfs_create_u32("vlan_passthrough_set", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, +- (u32 *)&ecm_nss_ipv6_vlan_passthrough_enable)) { +- DEBUG_ERROR("Failed to create ecm nss ipv6 vlan passthrough file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("vlan_passthrough_set", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, ++ (u32 *)&ecm_nss_ipv6_vlan_passthrough_enable); + + #ifdef ECM_NON_PORTED_SUPPORT_ENABLE + if (!ecm_nss_non_ported_ipv6_debugfs_init(ecm_nss_ipv6_dentry)) { +--- a/frontends/nss/ecm_nss_multicast_ipv4.c ++++ b/frontends/nss/ecm_nss_multicast_ipv4.c +@@ -4139,11 +4139,8 @@ void ecm_nss_multicast_ipv4_stop(int num + */ + int ecm_nss_multicast_ipv4_init(struct dentry *dentry) + { +- if (!debugfs_create_u32("ecm_nss_multicast_ipv4_stop", S_IRUGO | S_IWUSR, dentry, +- (u32 *)&ecm_front_end_ipv4_mc_stopped)) { +- DEBUG_ERROR("Failed to create ecm front end ipv4 mc stop file in debugfs\n"); +- return -1; +- } ++ debugfs_create_u32("ecm_nss_multicast_ipv4_stop", S_IRUGO | S_IWUSR, dentry, ++ (u32 *)&ecm_front_end_ipv4_mc_stopped); + + /* + * Register multicast update callback to MCS snooper +--- a/frontends/nss/ecm_nss_multicast_ipv6.c ++++ b/frontends/nss/ecm_nss_multicast_ipv6.c +@@ -3939,11 +3939,8 @@ void ecm_nss_multicast_ipv6_stop(int num + */ + int ecm_nss_multicast_ipv6_init(struct dentry *dentry) + { +- if (!debugfs_create_u32("ecm_nss_multicast_ipv6_stop", S_IRUGO | S_IWUSR, dentry, +- (u32 *)&ecm_front_end_ipv6_mc_stopped)) { +- DEBUG_ERROR("Failed to create ecm front end ipv6 mc stop file in debugfs\n"); +- return -1; +- } ++ debugfs_create_u32("ecm_nss_multicast_ipv6_stop", S_IRUGO | S_IWUSR, dentry, ++ (u32 *)&ecm_front_end_ipv6_mc_stopped); + + /* + * Register multicast update callback to MCS snooper +--- a/frontends/nss/ecm_nss_non_ported_ipv4.c ++++ b/frontends/nss/ecm_nss_non_ported_ipv4.c +@@ -2615,11 +2615,8 @@ done: + */ + bool ecm_nss_non_ported_ipv4_debugfs_init(struct dentry *dentry) + { +- if (!debugfs_create_u32("non_ported_accelerated_count", S_IRUGO, dentry, +- (u32 *)&ecm_nss_non_ported_ipv4_accelerated_count)) { +- DEBUG_ERROR("Failed to create ecm nss ipv4 non_ported_accelerated_count file in debugfs\n"); +- return false; +- } ++ debugfs_create_u32("non_ported_accelerated_count", S_IRUGO, dentry, ++ (u32 *)&ecm_nss_non_ported_ipv4_accelerated_count); + + return true; + } +--- a/frontends/nss/ecm_nss_non_ported_ipv6.c ++++ b/frontends/nss/ecm_nss_non_ported_ipv6.c +@@ -2329,11 +2329,8 @@ done: + */ + bool ecm_nss_non_ported_ipv6_debugfs_init(struct dentry *dentry) + { +- if (!debugfs_create_u32("non_ported_accelerated_count", S_IRUGO, dentry, +- (u32 *)&ecm_nss_non_ported_ipv6_accelerated_count)) { +- DEBUG_ERROR("Failed to create ecm nss ipv6 non_ported_accelerated_count file in debugfs\n"); +- return false; +- } ++ debugfs_create_u32("non_ported_accelerated_count", S_IRUGO, dentry, ++ (u32 *)&ecm_nss_non_ported_ipv6_accelerated_count); + + return true; + } +--- a/frontends/nss/ecm_nss_ported_ipv4.c ++++ b/frontends/nss/ecm_nss_ported_ipv4.c +@@ -2944,12 +2944,8 @@ bool ecm_nss_ported_ipv4_debugfs_init(st + return false; + } + +- if (!debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, +- &ecm_nss_ported_ipv4_accelerated_count[ECM_NSS_PORTED_IPV4_PROTO_TCP])) { +- DEBUG_ERROR("Failed to create ecm nss ipv4 tcp_accelerated_count file in debugfs\n"); +- debugfs_remove(udp_dentry); +- return false; +- } ++ debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, ++ &ecm_nss_ported_ipv4_accelerated_count[ECM_NSS_PORTED_IPV4_PROTO_TCP]); + + return true; + } +--- a/frontends/nss/ecm_nss_ported_ipv6.c ++++ b/frontends/nss/ecm_nss_ported_ipv6.c +@@ -2732,12 +2732,8 @@ bool ecm_nss_ported_ipv6_debugfs_init(st + return false; + } + +- if (!debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, +- &ecm_nss_ported_ipv6_accelerated_count[ECM_NSS_PORTED_IPV6_PROTO_TCP])) { +- DEBUG_ERROR("Failed to create ecm nss ipv6 tcp_accelerated_count file in debugfs\n"); +- debugfs_remove(udp_dentry); +- return false; +- } ++ debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, ++ &ecm_nss_ported_ipv6_accelerated_count[ECM_NSS_PORTED_IPV6_PROTO_TCP]); + + return true; + } +--- a/frontends/sfe/ecm_sfe_ipv4.c ++++ b/frontends/sfe/ecm_sfe_ipv4.c +@@ -1808,48 +1808,27 @@ int ecm_sfe_ipv4_init(struct dentry *den + } + + #ifdef CONFIG_XFRM +- if (!debugfs_create_u32("reject_acceleration_for_ipsec", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, +- (u32 *)&ecm_sfe_ipv4_reject_acceleration_for_ipsec)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv4 reject_acceleration_for_ipsec file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("reject_acceleration_for_ipsec", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, ++ (u32 *)&ecm_sfe_ipv4_reject_acceleration_for_ipsec); + #endif + +- if (!debugfs_create_u32("no_action_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, +- (u32 *)&ecm_sfe_ipv4_no_action_limit_default)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv4 no_action_limit_default file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("no_action_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, ++ (u32 *)&ecm_sfe_ipv4_no_action_limit_default); + +- if (!debugfs_create_u32("driver_fail_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, +- (u32 *)&ecm_sfe_ipv4_driver_fail_limit_default)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv4 driver_fail_limit_default file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("driver_fail_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, ++ (u32 *)&ecm_sfe_ipv4_driver_fail_limit_default); + +- if (!debugfs_create_u32("nack_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, +- (u32 *)&ecm_sfe_ipv4_nack_limit_default)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv4 nack_limit_default file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("nack_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, ++ (u32 *)&ecm_sfe_ipv4_nack_limit_default); + +- if (!debugfs_create_u32("accelerated_count", S_IRUGO, ecm_sfe_ipv4_dentry, +- (u32 *)&ecm_sfe_ipv4_accelerated_count)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv4 accelerated_count file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("accelerated_count", S_IRUGO, ecm_sfe_ipv4_dentry, ++ (u32 *)&ecm_sfe_ipv4_accelerated_count); + +- if (!debugfs_create_u32("pending_accel_count", S_IRUGO, ecm_sfe_ipv4_dentry, +- (u32 *)&ecm_sfe_ipv4_pending_accel_count)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv4 pending_accel_count file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("pending_accel_count", S_IRUGO, ecm_sfe_ipv4_dentry, ++ (u32 *)&ecm_sfe_ipv4_pending_accel_count); + +- if (!debugfs_create_u32("pending_decel_count", S_IRUGO, ecm_sfe_ipv4_dentry, +- (u32 *)&ecm_sfe_ipv4_pending_decel_count)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv4 pending_decel_count file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("pending_decel_count", S_IRUGO, ecm_sfe_ipv4_dentry, ++ (u32 *)&ecm_sfe_ipv4_pending_decel_count); + + if (!debugfs_create_file("accel_limit_mode", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, + NULL, &ecm_sfe_ipv4_accel_limit_mode_fops)) { +--- a/frontends/sfe/ecm_sfe_ipv6.c ++++ b/frontends/sfe/ecm_sfe_ipv6.c +@@ -1532,48 +1532,27 @@ int ecm_sfe_ipv6_init(struct dentry *den + } + + #ifdef CONFIG_XFRM +- if (!debugfs_create_u32("reject_acceleration_for_ipsec", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, +- (u32 *)&ecm_sfe_ipv6_reject_acceleration_for_ipsec)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv6 reject_acceleration_for_ipsec file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("reject_acceleration_for_ipsec", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, ++ (u32 *)&ecm_sfe_ipv6_reject_acceleration_for_ipsec); + #endif + +- if (!debugfs_create_u32("no_action_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, +- (u32 *)&ecm_sfe_ipv6_no_action_limit_default)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv6 no_action_limit_default file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("no_action_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, ++ (u32 *)&ecm_sfe_ipv6_no_action_limit_default); + +- if (!debugfs_create_u32("driver_fail_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, +- (u32 *)&ecm_sfe_ipv6_driver_fail_limit_default)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv6 driver_fail_limit_default file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("driver_fail_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, ++ (u32 *)&ecm_sfe_ipv6_driver_fail_limit_default); + +- if (!debugfs_create_u32("nack_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, +- (u32 *)&ecm_sfe_ipv6_nack_limit_default)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv6 nack_limit_default file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("nack_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, ++ (u32 *)&ecm_sfe_ipv6_nack_limit_default); + +- if (!debugfs_create_u32("accelerated_count", S_IRUGO, ecm_sfe_ipv6_dentry, +- (u32 *)&ecm_sfe_ipv6_accelerated_count)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv6 accelerated_count file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("accelerated_count", S_IRUGO, ecm_sfe_ipv6_dentry, ++ (u32 *)&ecm_sfe_ipv6_accelerated_count); + +- if (!debugfs_create_u32("pending_accel_count", S_IRUGO, ecm_sfe_ipv6_dentry, +- (u32 *)&ecm_sfe_ipv6_pending_accel_count)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv6 pending_accel_count file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("pending_accel_count", S_IRUGO, ecm_sfe_ipv6_dentry, ++ (u32 *)&ecm_sfe_ipv6_pending_accel_count); + +- if (!debugfs_create_u32("pending_decel_count", S_IRUGO, ecm_sfe_ipv6_dentry, +- (u32 *)&ecm_sfe_ipv6_pending_decel_count)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv6 pending_decel_count file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("pending_decel_count", S_IRUGO, ecm_sfe_ipv6_dentry, ++ (u32 *)&ecm_sfe_ipv6_pending_decel_count); + + if (!debugfs_create_file("accel_limit_mode", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, + NULL, &ecm_sfe_ipv6_accel_limit_mode_fops)) { +--- a/frontends/sfe/ecm_sfe_non_ported_ipv4.c ++++ b/frontends/sfe/ecm_sfe_non_ported_ipv4.c +@@ -2284,11 +2284,8 @@ done: + */ + bool ecm_sfe_non_ported_ipv4_debugfs_init(struct dentry *dentry) + { +- if (!debugfs_create_u32("non_ported_accelerated_count", S_IRUGO, dentry, +- (u32 *)&ecm_sfe_non_ported_ipv4_accelerated_count)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv4 non_ported_accelerated_count file in debugfs\n"); +- return false; +- } ++ debugfs_create_u32("non_ported_accelerated_count", S_IRUGO, dentry, ++ (u32 *)&ecm_sfe_non_ported_ipv4_accelerated_count); + + return true; + } +--- a/frontends/sfe/ecm_sfe_non_ported_ipv6.c ++++ b/frontends/sfe/ecm_sfe_non_ported_ipv6.c +@@ -2083,11 +2083,8 @@ done: + */ + bool ecm_sfe_non_ported_ipv6_debugfs_init(struct dentry *dentry) + { +- if (!debugfs_create_u32("non_ported_accelerated_count", S_IRUGO, dentry, +- (u32 *)&ecm_sfe_non_ported_ipv6_accelerated_count)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv6 non_ported_accelerated_count file in debugfs\n"); +- return false; +- } ++ debugfs_create_u32("non_ported_accelerated_count", S_IRUGO, dentry, ++ (u32 *)&ecm_sfe_non_ported_ipv6_accelerated_count); + + return true; + } +--- a/frontends/sfe/ecm_sfe_ported_ipv4.c ++++ b/frontends/sfe/ecm_sfe_ported_ipv4.c +@@ -2528,12 +2528,8 @@ bool ecm_sfe_ported_ipv4_debugfs_init(st + return false; + } + +- if (!debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, +- &ecm_sfe_ported_ipv4_accelerated_count[ECM_SFE_PORTED_IPV4_PROTO_TCP])) { +- DEBUG_ERROR("Failed to create ecm sfe ipv4 tcp_accelerated_count file in debugfs\n"); +- debugfs_remove(udp_dentry); +- return false; +- } ++ debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, ++ &ecm_sfe_ported_ipv4_accelerated_count[ECM_SFE_PORTED_IPV4_PROTO_TCP]); + + return true; + } +--- a/frontends/sfe/ecm_sfe_ported_ipv6.c ++++ b/frontends/sfe/ecm_sfe_ported_ipv6.c +@@ -2374,12 +2374,8 @@ bool ecm_sfe_ported_ipv6_debugfs_init(st + return false; + } + +- if (!debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, +- &ecm_sfe_ported_ipv6_accelerated_count[ECM_SFE_PORTED_IPV6_PROTO_TCP])) { +- DEBUG_ERROR("Failed to create ecm sfe ipv6 tcp_accelerated_count file in debugfs\n"); +- debugfs_remove(udp_dentry); +- return false; +- } ++ debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, ++ &ecm_sfe_ported_ipv6_accelerated_count[ECM_SFE_PORTED_IPV6_PROTO_TCP]); + + return true; + } diff --git a/qaa/nss/qca-nss-ecm-64/patches/203-rework-nfct-notification.patch b/qaa/nss/qca-nss-ecm-64/patches/203-rework-nfct-notification.patch new file mode 100644 index 000000000..72005cd70 --- /dev/null +++ b/qaa/nss/qca-nss-ecm-64/patches/203-rework-nfct-notification.patch @@ -0,0 +1,25 @@ +--- a/ecm_conntrack_notifier.c ++++ b/ecm_conntrack_notifier.c +@@ -421,7 +421,11 @@ int ecm_conntrack_notifier_init(struct d + /* + * Eventing subsystem is available so we register a notifier hook to get fast notifications of expired connections + */ ++#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS ++ result = nf_conntrack_register_chain_notifier(&init_net, &ecm_conntrack_notifier); ++#else + result = nf_conntrack_register_notifier(&init_net, &ecm_conntrack_notifier); ++#endif + if (result < 0) { + DEBUG_ERROR("Can't register nf notifier hook.\n"); + debugfs_remove_recursive(ecm_conntrack_notifier_dentry); +@@ -439,7 +443,9 @@ EXPORT_SYMBOL(ecm_conntrack_notifier_ini + void ecm_conntrack_notifier_exit(void) + { + DEBUG_INFO("ECM Conntrack Notifier exit\n"); +-#ifdef CONFIG_NF_CONNTRACK_EVENTS ++#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS ++ nf_conntrack_unregister_chain_notifier(&init_net, &ecm_conntrack_notifier); ++#else + nf_conntrack_unregister_notifier(&init_net, &ecm_conntrack_notifier); + #endif + /* diff --git a/qaa/nss/qca-nss-ecm-64/patches/204-More-compile-fixes.patch b/qaa/nss/qca-nss-ecm-64/patches/204-More-compile-fixes.patch new file mode 100644 index 000000000..a998d8295 --- /dev/null +++ b/qaa/nss/qca-nss-ecm-64/patches/204-More-compile-fixes.patch @@ -0,0 +1,58 @@ +From e6d701c0d454d841366c556b2ef07a5203ffb35d Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Fri, 21 May 2021 21:41:31 +0200 +Subject: [PATCH] More compile fixes + +More runtime compile fixes. + +Signed-off-by: Robert Marko +--- + frontends/nss/ecm_nss_ported_ipv4.c | 12 +++--------- + frontends/nss/ecm_nss_ported_ipv6.c | 12 +++--------- + 2 files changed, 6 insertions(+), 18 deletions(-) + +diff --git a/frontends/nss/ecm_nss_ported_ipv4.c b/frontends/nss/ecm_nss_ported_ipv4.c +index 3522f0f..7f5fcd1 100644 +--- a/frontends/nss/ecm_nss_ported_ipv4.c ++++ b/frontends/nss/ecm_nss_ported_ipv4.c +@@ -2935,14 +2935,8 @@ done: + */ + bool ecm_nss_ported_ipv4_debugfs_init(struct dentry *dentry) + { +- struct dentry *udp_dentry; +- +- udp_dentry = debugfs_create_u32("udp_accelerated_count", S_IRUGO, dentry, ++ debugfs_create_u32("udp_accelerated_count", S_IRUGO, dentry, + &ecm_nss_ported_ipv4_accelerated_count[ECM_NSS_PORTED_IPV4_PROTO_UDP]); +- if (!udp_dentry) { +- DEBUG_ERROR("Failed to create ecm nss ipv4 udp_accelerated_count file in debugfs\n"); +- return false; +- } + + debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, + &ecm_nss_ported_ipv4_accelerated_count[ECM_NSS_PORTED_IPV4_PROTO_TCP]); +diff --git a/frontends/nss/ecm_nss_ported_ipv6.c b/frontends/nss/ecm_nss_ported_ipv6.c +index f43ac95..e0f779c 100644 +--- a/frontends/nss/ecm_nss_ported_ipv6.c ++++ b/frontends/nss/ecm_nss_ported_ipv6.c + /* + * ecm_nss_ported_ipv6_connection_callback() +@@ -2723,14 +2723,8 @@ done: + */ + bool ecm_nss_ported_ipv6_debugfs_init(struct dentry *dentry) + { +- struct dentry *udp_dentry; +- +- udp_dentry = debugfs_create_u32("udp_accelerated_count", S_IRUGO, dentry, ++ debugfs_create_u32("udp_accelerated_count", S_IRUGO, dentry, + &ecm_nss_ported_ipv6_accelerated_count[ECM_NSS_PORTED_IPV6_PROTO_UDP]); +- if (!udp_dentry) { +- DEBUG_ERROR("Failed to create ecm nss ipv6 udp_accelerated_count file in debugfs\n"); +- return false; +- } + + debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, + &ecm_nss_ported_ipv6_accelerated_count[ECM_NSS_PORTED_IPV6_PROTO_TCP]); +-- +2.31.1 + diff --git a/qaa/nss/qca-nss-ecm-64/patches/205-resolve-high-load.patch b/qaa/nss/qca-nss-ecm-64/patches/205-resolve-high-load.patch new file mode 100644 index 000000000..f4106a355 --- /dev/null +++ b/qaa/nss/qca-nss-ecm-64/patches/205-resolve-high-load.patch @@ -0,0 +1,61 @@ +From 6924b71ed809b37fffd74d6428a8ca83e5919746 Mon Sep 17 00:00:00 2001 +From: Dirk Buchwalder +Date: Sun, 27 Jun 2021 16:52:39 +0200 +Subject: [PATCH] qca-nss-ecm: resolve the cpu high load regarding ecm + +If using ECM, cpu load goes up (around 1.0) and stucks there. +This is due to using uninterruptible sleep function, +the patch changes this to interruptible sleep function. + +Signed-off-by: Dirk Buchwalder buchwalder@posteo.de +--- + frontends/nss/ecm_nss_ipv4.c | 4 ++-- + frontends/nss/ecm_nss_ipv6.c | 4 ++-- + 2 files changed, 4 insertions(+), 4 deletions(-) + +diff --git a/frontends/nss/ecm_nss_ipv4.c b/frontends/nss/ecm_nss_ipv4.c +index e00553c..94b39cd 100644 +--- a/frontends/nss/ecm_nss_ipv4.c ++++ b/frontends/nss/ecm_nss_ipv4.c +@@ -2471,7 +2471,7 @@ static void ecm_nss_ipv4_stats_sync_req_work(struct work_struct *work) + } + spin_unlock_bh(&ecm_nss_ipv4_lock); + +- usleep_range(ECM_NSS_IPV4_STATS_SYNC_UDELAY - 100, ECM_NSS_IPV4_STATS_SYNC_UDELAY); ++ msleep_interruptible(ECM_NSS_IPV4_STATS_SYNC_UDELAY / 1000); + + /* + * If index is 0, we are starting a new round, but if we still have time remain +@@ -2485,7 +2485,7 @@ static void ecm_nss_ipv4_stats_sync_req_work(struct work_struct *work) + } + + if (time_after(ecm_nss_ipv4_next_req_time, current_jiffies)) { +- msleep(jiffies_to_msecs(ecm_nss_ipv4_next_req_time - current_jiffies)); ++ msleep_interruptible(jiffies_to_msecs(ecm_nss_ipv4_next_req_time - current_jiffies)); + } + ecm_nss_ipv4_roll_check_jiffies = jiffies; + ecm_nss_ipv4_next_req_time = ecm_nss_ipv4_roll_check_jiffies + ECM_NSS_IPV4_STATS_SYNC_PERIOD; +diff --git a/frontends/nss/ecm_nss_ipv6.c b/frontends/nss/ecm_nss_ipv6.c +index 82e739f..30af050 100644 +--- a/frontends/nss/ecm_nss_ipv6.c ++++ b/frontends/nss/ecm_nss_ipv6.c +@@ -2210,7 +2210,7 @@ static void ecm_nss_ipv6_stats_sync_req_work(struct work_struct *work) + } + spin_unlock_bh(&ecm_nss_ipv6_lock); + +- usleep_range(ECM_NSS_IPV6_STATS_SYNC_UDELAY - 100, ECM_NSS_IPV6_STATS_SYNC_UDELAY); ++ msleep_interruptible(ECM_NSS_IPV6_STATS_SYNC_UDELAY / 1000); + + /* + * If index is 0, we are starting a new round, but if we still have time remain +@@ -2224,7 +2224,7 @@ static void ecm_nss_ipv6_stats_sync_req_work(struct work_struct *work) + } + + if (time_after(ecm_nss_ipv6_next_req_time, current_jiffies)) { +- msleep(jiffies_to_msecs(ecm_nss_ipv6_next_req_time - current_jiffies)); ++ msleep_interruptible(jiffies_to_msecs(ecm_nss_ipv6_next_req_time - current_jiffies)); + } + ecm_nss_ipv6_roll_check_jiffies = jiffies; + ecm_nss_ipv6_next_req_time = ecm_nss_ipv6_roll_check_jiffies + ECM_NSS_IPV6_STATS_SYNC_PERIOD; +-- +2.31.1 diff --git a/qaa/nss/qca-nss-ecm/Makefile b/qaa/nss/qca-nss-ecm/Makefile new file mode 100644 index 000000000..0053ff12e --- /dev/null +++ b/qaa/nss/qca-nss-ecm/Makefile @@ -0,0 +1,278 @@ +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/kernel.mk + +PKG_NAME:=qca-nss-ecm +PKG_RELEASE:=1 + +PKG_SOURCE_URL:=https://source.codeaurora.org/quic/qsdk/oss/lklm/qca-nss-ecm +PKG_SOURCE_PROTO:=git +PKG_SOURCE_VERSION:=9228212b4238c0d8c296f795948ede8f2ca0242e +PKG_MIRROR_HASH:=02fe4c86c8c88fb15704b1b253ab756a2658f24ce5db64a7909cb60bf9c1cdff + +LOCAL_VARIANT=$(patsubst qca-nss-ecm-%,%,$(patsubst qca-nss-ecm-%,%,$(BUILD_VARIANT))) +include $(INCLUDE_DIR)/package.mk + +ifeq ($(CONFIG_QCA_NSS_ECM_EXAMPLES_PCC),y) + FILES_EXAMPLES=$(PKG_BUILD_DIR)/examples/ecm_pcc_test.ko +endif + +ifeq ($(CONFIG_QCA_NSS_ECM_EXAMPLES_MARK),y) + FILES_EXAMPLES+=$(PKG_BUILD_DIR)/examples/ecm_mark_test.ko +endif + +#Explicitly enable OVS external module, if ovsmgr is enabled. +ifneq ($(CONFIG_PACKAGE_kmod-qca-ovsmgr),) +CONFIG_QCA_NSS_ECM_OVS=y +endif + +ifeq ($(CONFIG_QCA_NSS_ECM_OVS),y) + FILES_EXAMPLES+=$(PKG_BUILD_DIR)/examples/ecm_ovs.ko +endif + +define KernelPackage/qca-nss-ecm/Default + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Support + DEPENDS:=+TARGET_ipq806x:kmod-qca-nss-drv \ + +TARGET_ipq_ipq806x:kmod-qca-nss-drv \ + +TARGET_ipq_ipq807x:kmod-qca-nss-drv \ + +TARGET_ipq_ipq807x_64:kmod-qca-nss-drv \ + +TARGET_ipq807x:kmod-qca-nss-drv \ + +TARGET_ipq807x_64:kmod-qca-nss-drv \ + +TARGET_ipq_ipq60xx:kmod-qca-nss-drv \ + +TARGET_ipq_ipq60xx_64:kmod-qca-nss-drv \ + +TARGET_ipq_ipq50xx:kmod-qca-nss-drv \ + +TARGET_ipq_ipq50xx_64:kmod-qca-nss-drv \ + +iptables-mod-extra +kmod-ipt-conntrack \ + +kmod-pppoe @LINUX_5_4 \ + +kmod-ipsec + TITLE:=QCA NSS Enhanced Connection Manager (ECM) + FILES:=$(PKG_BUILD_DIR)/*.ko $(FILES_EXAMPLES) + KCONFIG:=CONFIG_BRIDGE_NETFILTER=y \ + CONFIG_NF_CONNTRACK_EVENTS=y \ + CONFIG_NF_CONNTRACK_CHAIN_EVENTS=y \ + CONFIG_NF_CONNTRACK_DSCPREMARK_EXT=y + MENU:=1 + PROVIDES:=kmod-qca-nss-ecm +endef + +define KernelPackage/qca-nss-ecm/Description/Default +This package contains the QCA NSS Enhanced Connection Manager +endef + +define KernelPackage/qca-nss-ecm/Default/install + $(INSTALL_DIR) $(1)/etc/firewall.d $(1)/etc/init.d $(1)/usr/bin $(1)/lib/netifd/offload $(1)/etc/config $(1)/etc/uci-defaults $(1)/etc/sysctl.d + $(INSTALL_DATA) ./files/qca-nss-ecm.firewall $(1)/etc/firewall.d/qca-nss-ecm + $(INSTALL_BIN) ./files/qca-nss-ecm.init $(1)/etc/init.d/qca-nss-ecm + $(INSTALL_BIN) ./files/ecm_dump.sh $(1)/usr/bin/ + $(INSTALL_BIN) ./files/on-demand-down $(1)/lib/netifd/offload/on-demand-down + $(INSTALL_DATA) ./files/qca-nss-ecm.uci $(1)/etc/config/ecm + $(INSTALL_DATA) ./files/qca-nss-ecm.defaults $(1)/etc/uci-defaults/99-qca-nss-ecm + $(INSTALL_BIN) ./files/qca-nss-ecm.sysctl $(1)/etc/sysctl.d/qca-nss-ecm.conf +ifeq ($(CONFIG_KERNEL_IPQ_MEM_PROFILE),256) + echo 'net.netfilter.nf_conntrack_max=2048' >> $(1)/etc/sysctl.d/qca-nss-ecm.conf +endif +ifeq ($(CONFIG_KERNEL_IPQ_MEM_PROFILE),512) + echo 'net.netfilter.nf_conntrack_max=8192' >> $(1)/etc/sysctl.d/qca-nss-ecm.conf +endif +endef + +define KernelPackage/qca-nss-ecm-standard + $(call KernelPackage/qca-nss-ecm/Default) + VARIANT:=standard + DEPENDS+=+PACKAGE_kmod-qca-mcs:kmod-qca-mcs +endef + +define KernelPackage/qca-nss-ecm-standard/Description + $(call KernelPackage/qca-nss-ecm/Description/Default) +endef + +define KernelPackage/qca-nss-ecm-standard/install +$(call KernelPackage/qca-nss-ecm/Default/install, $(1)) +endef + +# Variant with additional features enabled for premium profile +define KernelPackage/qca-nss-ecm-premium/Default +$(call KernelPackage/qca-nss-ecm/Default) + TITLE+= (with premium features) + VARIANT:=premium + DEPENDS+=+kmod-nat46 \ + +kmod-l2tp +kmod-pppol2tp +kmod-pptp \ + +kmod-bonding +endef + +define KernelPackage/qca-nss-ecm-premium/Description/Default +$(call KernelPackage/qca-nss-ecm/Description/Default) +with the premium features enabled +endef + +define KernelPackage/qca-nss-ecm-premium/Default/install +$(call KernelPackage/qca-nss-ecm/install) +endef + +define KernelPackage/qca-nss-ecm-premium +$(call KernelPackage/qca-nss-ecm-premium/Default) +endef + +define KernelPackage/qca-nss-ecm-premium/Description +$(call KernelPackage/qca-nss-ecm-premium/Description/Default) +endef + +define KernelPackage/qca-nss-ecm-premium/install +$(call KernelPackage/qca-nss-ecm-standard/install, $(1)) +endef + +# Variant with additional features enabled for noload profile +define KernelPackage/qca-nss-ecm-noload + $(call KernelPackage/qca-nss-ecm/Default) + TITLE+= (with noload features) + PROVIDES:=kmod-qca-nss-ecm + VARIANT:=noload + DEPENDS+=+kmod-l2tp +kmod-pppol2tp +kmod-pptp \ + +kmod-bonding +endef + +define KernelPackage/qca-nss-ecm-noload/Description + $(call KernelPackage/qca-nss-ecm/Description/Default) + When selected, this package installs the driver but does not load it at init. +endef + +define KernelPackage/qca-nss-ecm-noload/install +$(call KernelPackage/qca-nss-ecm/Default/install, $(1)) + # + # Remove the START line from the init script, so that the symlink + # in the /etc/rc.d directory is not created. + # + sed -i '/START=/d' $(1)/etc/init.d/qca-nss-ecm +endef + +define KernelPackage/qca-nss-ecm-premium-noload + $(call KernelPackage/qca-nss-ecm-premium/Default) + PROVIDES:=kmod-qca-nss-ecm-premium +endef + +define KernelPackage/qca-nss-ecm-premium-noload/Description + $(call KernelPackage/qca-nss-ecm-premium/Description/Default) + When selected, this package installs the driver but does not load it at init. +endef + +define KernelPackage/qca-nss-ecm-premium-noload/install +$(call KernelPackage/qca-nss-ecm-premium/Default/install, $(1)) +endef + +define Build/InstallDev/qca-nss-ecm + $(INSTALL_DIR) $(1)/usr/include/qca-nss-ecm + $(CP) $(PKG_BUILD_DIR)/exports/* $(1)/usr/include/qca-nss-ecm/ +endef + +define Build/InstallDev + $(call Build/InstallDev/qca-nss-ecm,$(1)) +endef + +EXTRA_CFLAGS+= \ + -I$(STAGING_DIR)/usr/include/hyfibr \ + -I$(STAGING_DIR)/usr/include/qca-mcs \ + -I$(STAGING_DIR)/usr/include/qca-nss-drv \ + -I$(STAGING_DIR)/usr/include/shortcut-fe \ + -I$(STAGING_DIR)/usr/include/nat46 + +ECM_MAKE_OPTS:=ECM_CLASSIFIER_HYFI_ENABLE=y +ifneq ($(LOCAL_VARIANT),standard) +ECM_MAKE_OPTS+=ECM_MULTICAST_ENABLE=y \ + ECM_INTERFACE_IPSEC_ENABLE=y \ + # ECM_INTERFACE_PPTP_ENABLE=y \ + ECM_INTERFACE_L2TPV2_ENABLE=y \ + ECM_INTERFACE_GRE_TAP_ENABLE=y \ + ECM_INTERFACE_GRE_TUN_ENABLE=y \ + ECM_INTERFACE_SIT_ENABLE=y \ + ECM_INTERFACE_TUNIPIP6_ENABLE=y \ + ECM_INTERFACE_RAWIP_ENABLE=y + +ifeq ($(CONFIG_TARGET_ipq_ipq40xx)$(CONFIG_TARGET_ipq40xx),) +ECM_MAKE_OPTS+=ECM_INTERFACE_BOND_ENABLE=y +endif +endif + +ifeq ($(filter $(CONFIG_KERNEL_IPQ_MEM_PROFILE), 256),) +ECM_MAKE_OPTS+=ECM_XFRM_ENABLE=y +endif + +# ifneq ($(CONFIG_PACKAGE_kmod-nat46),) +# ECM_MAKE_OPTS+=ECM_INTERFACE_MAP_T_ENABLE=y +# endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-mcs),) +ECM_MAKE_OPTS+=ECM_MULTICAST_ENABLE=y +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-ovpn-link),) +ECM_MAKE_OPTS+=ECM_INTERFACE_OVPN_ENABLE=y +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-vxlanmgr),) +ECM_MAKE_OPTS+=ECM_INTERFACE_VXLAN_ENABLE=y +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-ovsmgr),) +ECM_MAKE_OPTS+=ECM_INTERFACE_OVS_BRIDGE_ENABLE=y \ + ECM_CLASSIFIER_OVS_ENABLE=y +EXTRA_CFLAGS+= -I$(STAGING_DIR)/usr/include/qca-ovsmgr +endif + +# Keeping default as ipq806x for branches that does not have subtarget framework +ifeq ($(CONFIG_TARGET_ipq),y) +subtarget:=$(SUBTARGET) +else +subtarget:=$(CONFIG_TARGET_BOARD) +endif + +define Build/InstallDev + $(INSTALL_DIR) $(1)/usr/include/qca-nss-ecm + $(CP) $(PKG_BUILD_DIR)/exports/* $(1)/usr/include/qca-nss-ecm +endef + +define Build/Compile + $(MAKE) $(PKG_JOBS) -C "$(LINUX_DIR)" $(strip $(ECM_MAKE_OPTS)) \ + $(KERNEL_MAKE_FLAGS) \ + $(PKG_MAKE_FLAGS) \ + M="$(PKG_BUILD_DIR)" \ + EXTRA_CFLAGS="$(EXTRA_CFLAGS)" SoC="$(subtarget)" \ + EXAMPLES_BUILD_PCC="$(CONFIG_QCA_NSS_ECM_EXAMPLES_PCC)" \ + EXAMPLES_BUILD_MARK="$(CONFIG_QCA_NSS_ECM_EXAMPLES_MARK)" \ + EXAMPLES_BUILD_OVS="$(CONFIG_QCA_NSS_ECM_OVS)" \ + ECM_FRONT_END_SFE_ENABLE="$(CONFIG_QCA_ECM_SFE_SUPPORT)" \ + modules +endef + +define KernelPackage/qca-nss-ecm-premium/config +menu "ECM Configuration" + depends on PACKAGE_kmod_qca-nss-ecm-premium + + config QCA_NSS_ECM_EXAMPLES_PCC + bool "Build PCC usage example" + help + Selecting this will build the PCC classifier usage example module. + default n + + config QCA_NSS_ECM_EXAMPLES_MARK + bool "Build Mark classifier usage example" + help + Selecting this will build the Mark classifier usage example module. + default n + + config QCA_NSS_ECM_OVS + bool "Build OVS classifier external module" + help + Selecting this will build the OVS classifier external module. + default n + + config QCA_ECM_SFE_SUPPORT + bool "Add SFE support to ECM driver" + default n +endmenu +endef + +$(eval $(call KernelPackage,qca-nss-ecm-noload)) +$(eval $(call KernelPackage,qca-nss-ecm-standard)) +$(eval $(call KernelPackage,qca-nss-ecm-premium-noload)) +$(eval $(call KernelPackage,qca-nss-ecm-premium)) diff --git a/qaa/nss/qca-nss-ecm/files/ecm_dump.sh b/qaa/nss/qca-nss-ecm/files/ecm_dump.sh new file mode 100644 index 000000000..dbf7de753 --- /dev/null +++ b/qaa/nss/qca-nss-ecm/files/ecm_dump.sh @@ -0,0 +1,95 @@ +#!/bin/sh +# +# Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +# + +ECM_MODULE=${1:-ecm_state} +MOUNT_ROOT=/dev/ecm + +# +# usage: ecm_dump.sh [module=ecm_db] +# +# with no parameters, ecm_dump.sh will attempt to mount the +# ecm_db state file and cat its contents. +# +# example with a parameter: ecm_dump.sh ecm_classifier_default +# +# this will cause ecm_dump to attempt to find and mount the state +# file for the ecm_classifier_default module, and if successful +# cat the contents. +# + +# this is one of the state files, which happens to be the +# last module started in ecm +ECM_STATE=/sys/kernel/debug/ecm/ecm_state/state_dev_major + +# tests to see if ECM is up and ready to receive commands. +# returns 0 if ECM is fully up and ready, else 1 +ecm_is_ready() { + if [ ! -e "${ECM_STATE}" ] + then + return 1 + fi + return 0 +} + +# +# module_state_mount(module_name) +# Mounts the state file of the module, if supported +# +module_state_mount() { + local module_name=$1 + local mount_dir=$2 + local state_file="/sys/kernel/debug/ecm/${module_name}/state_dev_major" + + if [ -e "${mount_dir}/${module_name}" ] + then + # already mounted + return 0 + fi + + #echo "Mount state file for $module_name ..." + if [ ! -e "$state_file" ] + then + #echo "... $module_name does not support state" + return 1 + fi + + local major="`cat $state_file`" + #echo "... Mounting state $state_file with major: $major" + mknod "${mount_dir}/${module_name}" c $major 0 +} + +# +# main +# +ecm_is_ready || { + #echo "ECM is not running" + exit 1 +} + +# all state files are mounted under MOUNT_ROOT, so make sure it exists +mkdir -p ${MOUNT_ROOT} + +# +# attempt to mount state files for the requested module and cat it +# if the mount succeeded +# +module_state_mount ${ECM_MODULE} ${MOUNT_ROOT} && { + cat ${MOUNT_ROOT}/${ECM_MODULE} + exit 0 +} + +exit 2 diff --git a/qaa/nss/qca-nss-ecm/files/on-demand-down b/qaa/nss/qca-nss-ecm/files/on-demand-down new file mode 100644 index 000000000..02d708e03 --- /dev/null +++ b/qaa/nss/qca-nss-ecm/files/on-demand-down @@ -0,0 +1,6 @@ +#!/bin/sh +# Copyright (c) 2016 The Linux Foundation. All rights reserved. + +[ -e "/sys/kernel/debug/ecm/ecm_db/defunct_all" ] && { + echo 1 > /sys/kernel/debug/ecm/ecm_db/defunct_all +} diff --git a/qaa/nss/qca-nss-ecm/files/qca-nss-ecm.defaults b/qaa/nss/qca-nss-ecm/files/qca-nss-ecm.defaults new file mode 100644 index 000000000..308e265c9 --- /dev/null +++ b/qaa/nss/qca-nss-ecm/files/qca-nss-ecm.defaults @@ -0,0 +1,28 @@ +#!/bin/sh +# +# Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +# + +uci -q batch << EOF + delete firewall.qcanssecm + set firewall.qcanssecm=include + set firewall.qcanssecm.type=script + set firewall.qcanssecm.path=/etc/firewall.d/qca-nss-ecm + set firewall.qcanssecm.family=any + set firewall.qcanssecm.reload=1 + commit firewall +EOF + +exit 0 diff --git a/qaa/nss/qca-nss-ecm/files/qca-nss-ecm.firewall b/qaa/nss/qca-nss-ecm/files/qca-nss-ecm.firewall new file mode 100644 index 000000000..24c64def2 --- /dev/null +++ b/qaa/nss/qca-nss-ecm/files/qca-nss-ecm.firewall @@ -0,0 +1,18 @@ +#!/bin/sh +# +# Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +# + +iptables -A FORWARD -m physdev --physdev-is-bridged -j ACCEPT diff --git a/qaa/nss/qca-nss-ecm/files/qca-nss-ecm.init b/qaa/nss/qca-nss-ecm/files/qca-nss-ecm.init new file mode 100644 index 000000000..0d58c3599 --- /dev/null +++ b/qaa/nss/qca-nss-ecm/files/qca-nss-ecm.init @@ -0,0 +1,133 @@ +#!/bin/sh /etc/rc.common +# +# Copyright (c) 2014, 2019 The Linux Foundation. All rights reserved. +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +# The shebang above has an extra space intentially to avoid having +# openwrt build scripts automatically enable this package starting +# at boot. + +START=19 + +get_front_end_mode() { + config_load "ecm" + config_get front_end global acceleration_engine "auto" + + case $front_end in + auto) + echo '0' + ;; + nss) + echo '1' + ;; + sfe) + echo '2' + ;; + *) + echo 'uci_option_acceleration_engine is invalid' + esac +} + +support_bridge() { + #NSS support bridge acceleration + [ -d /sys/kernel/debug/ecm/ecm_nss_ipv4 ] && return 0 + #SFE doesn't support bridge acceleration + [ -d /sys/kernel/debug/ecm/ecm_sfe_ipv4 ] && return 1 +} + +load_sfe() { + local kernel_version=$(uname -r) + + [ -e "/lib/modules/$kernel_version/shortcut-fe.ko" ] && { + [ -d /sys/module/shortcut_fe ] || insmod shortcut-fe + } + + [ -e "/lib/modules/$kernel_version/shortcut-fe-ipv6.ko" ] && { + [ -d /sys/module/shortcut_fe_ipv6 ] || insmod shortcut-fe-ipv6 + } + + [ -e "/lib/modules/$kernel_version/shortcut-fe-cm.ko" ] && { + [ -d /sys/module/shortcut_fe_cm ] || insmod shortcut-fe-cm + } + + [ -e "/lib/modules/$kernel_version/shortcut-fe-drv.ko" ] && { + [ -d /sys/module/shortcut_fe_drv ] || insmod shortcut-fe-drv + } + +} + +load_ecm() { + [ -d /sys/module/ecm ] || { + [ ! -e /proc/device-tree/MP_256 ] && load_sfe + insmod ecm front_end_selection=$(get_front_end_mode) + } + + support_bridge && { + sysctl -w net.bridge.bridge-nf-call-ip6tables=1 + sysctl -w net.bridge.bridge-nf-call-iptables=1 + } +} + +unload_ecm() { + sysctl -w net.bridge.bridge-nf-call-ip6tables=0 + sysctl -w net.bridge.bridge-nf-call-iptables=0 + + if [ -d /sys/module/ecm ]; then + # + # Stop ECM frontends + # + echo 1 > /sys/kernel/debug/ecm/front_end_ipv4_stop + echo 1 > /sys/kernel/debug/ecm/front_end_ipv6_stop + + # + # Defunct the connections + # + echo 1 > /sys/kernel/debug/ecm/ecm_db/defunct_all + sleep 5; + + rmmod ecm + sleep 1 + fi +} + +start() { + load_ecm + + # If the acceleration engine is NSS, enable wifi redirect. + [ -d /sys/kernel/debug/ecm/ecm_nss_ipv4 ] && sysctl -w dev.nss.general.redirect=1 + + support_bridge && { + echo 'net.bridge.bridge-nf-call-ip6tables=1' >> /etc/sysctl.d/qca-nss-ecm.conf + echo 'net.bridge.bridge-nf-call-iptables=1' >> /etc/sysctl.d/qca-nss-ecm.conf + } + + if [ -d /sys/module/qca_ovsmgr ]; then + insmod ecm_ovs + fi + +} + +stop() { + # If the acceleration engine is NSS, disable wifi redirect. + [ -d /sys/kernel/debug/ecm/ecm_nss_ipv4 ] && sysctl -w dev.nss.general.redirect=0 + + sed '/net.bridge.bridge-nf-call-ip6tables=1/d' -i /etc/sysctl.d/qca-nss-ecm.conf + sed '/net.bridge.bridge-nf-call-iptables=1/d' -i /etc/sysctl.d/qca-nss-ecm.conf + + if [ -d /sys/module/ecm_ovs ]; then + rmmod ecm_ovs + fi + + unload_ecm +} diff --git a/qaa/nss/qca-nss-ecm/files/qca-nss-ecm.sysctl b/qaa/nss/qca-nss-ecm/files/qca-nss-ecm.sysctl new file mode 100644 index 000000000..1a3d76b18 --- /dev/null +++ b/qaa/nss/qca-nss-ecm/files/qca-nss-ecm.sysctl @@ -0,0 +1,2 @@ +# nf_conntrack_tcp_no_window_check is 0 by default, set it to 1 +net.netfilter.nf_conntrack_tcp_no_window_check=1 diff --git a/qaa/nss/qca-nss-ecm/files/qca-nss-ecm.uci b/qaa/nss/qca-nss-ecm/files/qca-nss-ecm.uci new file mode 100644 index 000000000..4f2de6877 --- /dev/null +++ b/qaa/nss/qca-nss-ecm/files/qca-nss-ecm.uci @@ -0,0 +1,2 @@ +config ecm 'global' + option acceleration_engine 'auto' diff --git a/qaa/nss/qca-nss-ecm/patches/001-Drop_SFE_from_ecm.patch b/qaa/nss/qca-nss-ecm/patches/001-Drop_SFE_from_ecm.patch new file mode 100644 index 000000000..b1cd2b7b1 --- /dev/null +++ b/qaa/nss/qca-nss-ecm/patches/001-Drop_SFE_from_ecm.patch @@ -0,0 +1,12 @@ +--- a/Makefile ++++ b/Makefile +@@ -66,8 +66,7 @@ endif + # Define ECM_FRONT_END_SFE_ENABLE=y in order to select + # sfe as ECM's front end. + # ############################################################################# +-ifeq ($(SoC),$(filter $(SoC),ipq806x ipq40xx)) +-ECM_FRONT_END_SFE_ENABLE=y ++ifeq ($(ECM_FRONT_END_SFE_ENABLE), y) + ecm-$(ECM_FRONT_END_SFE_ENABLE) += frontends/sfe/ecm_sfe_ipv4.o + ecm-$(ECM_FRONT_END_SFE_ENABLE) += frontends/sfe/ecm_sfe_ported_ipv4.o + ccflags-$(ECM_FRONT_END_SFE_ENABLE) += -DECM_FRONT_END_SFE_ENABLE diff --git a/qaa/nss/qca-nss-ecm/patches/100-kernel-5.4-support.patch b/qaa/nss/qca-nss-ecm/patches/100-kernel-5.4-support.patch new file mode 100644 index 000000000..b863ad7e0 --- /dev/null +++ b/qaa/nss/qca-nss-ecm/patches/100-kernel-5.4-support.patch @@ -0,0 +1,1276 @@ +--- a/ecm_classifier_default.c ++++ b/ecm_classifier_default.c +@@ -42,7 +42,6 @@ + #include + #include + #include +-#include + #include + #include + #include +--- a/ecm_classifier_dscp.c ++++ b/ecm_classifier_dscp.c +@@ -41,7 +41,6 @@ + #include + #include + #include +-#include + #include + #include + #include +--- a/ecm_classifier_hyfi.c ++++ b/ecm_classifier_hyfi.c +@@ -41,7 +41,6 @@ + #include + #include + #include +-#include + #include + #include + #include +--- a/ecm_classifier_nl.c ++++ b/ecm_classifier_nl.c +@@ -41,7 +41,6 @@ + #include + #include + #include +-#include + #if (LINUX_VERSION_CODE <= KERNEL_VERSION(4, 2, 0)) + #include + #else +@@ -146,12 +145,42 @@ static struct genl_multicast_group ecm_c + }, + }; + ++static int ecm_classifier_nl_genl_msg_ACCEL(struct sk_buff *skb, struct genl_info *info); ++static int ecm_classifier_nl_genl_msg_DUMP(struct sk_buff *skb, struct netlink_callback *cb); ++ ++/* ++ * Generic Netlink message-to-handler mapping ++ */ ++static struct genl_ops ecm_cl_nl_genl_ops[] = { ++ { ++ .cmd = ECM_CL_NL_GENL_CMD_ACCEL, ++ .flags = 0, ++ .doit = ecm_classifier_nl_genl_msg_ACCEL, ++ .dumpit = NULL, ++ }, ++ { ++ .cmd = ECM_CL_NL_GENL_CMD_ACCEL_OK, ++ .flags = 0, ++ .doit = NULL, ++ .dumpit = ecm_classifier_nl_genl_msg_DUMP, ++ }, ++ { ++ .cmd = ECM_CL_NL_GENL_CMD_CONNECTION_CLOSED, ++ .flags = 0, ++ .doit = NULL, ++ .dumpit = ecm_classifier_nl_genl_msg_DUMP, ++ }, ++}; ++ + static struct genl_family ecm_cl_nl_genl_family = { +- .id = GENL_ID_GENERATE, + .hdrsize = 0, + .name = ECM_CL_NL_GENL_NAME, + .version = ECM_CL_NL_GENL_VERSION, + .maxattr = ECM_CL_NL_GENL_ATTR_MAX, ++ .ops = ecm_cl_nl_genl_ops, ++ .n_ops = ARRAY_SIZE(ecm_cl_nl_genl_ops), ++ .mcgrps = ecm_cl_nl_genl_mcgrp, ++ .n_mcgrps = ARRAY_SIZE(ecm_cl_nl_genl_mcgrp), + }; + + /* +@@ -215,12 +244,7 @@ ecm_classifier_nl_send_genl_msg(enum ECM + return ret; + } + +- ret = genlmsg_end(skb, msg_head); +- if (ret < 0) { +- DEBUG_WARN("failed to finalize genl msg: %d\n", ret); +- nlmsg_free(skb); +- return ret; +- } ++ genlmsg_end(skb, msg_head); + + /* genlmsg_multicast frees the skb in both success and error cases */ + #if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 13, 0) +@@ -1377,85 +1401,14 @@ static struct file_operations ecm_classi + .write = ecm_classifier_nl_set_command, + }; + +-/* +- * Generic Netlink attr checking policies +- */ +-static struct nla_policy +-ecm_cl_nl_genl_policy[ECM_CL_NL_GENL_ATTR_COUNT] = { +- [ECM_CL_NL_GENL_ATTR_TUPLE] = { +- .type = NLA_UNSPEC, +- .len = sizeof(struct ecm_cl_nl_genl_attr_tuple), }, +-}; +- +-/* +- * Generic Netlink message-to-handler mapping +- */ +-static struct genl_ops ecm_cl_nl_genl_ops[] = { +- { +- .cmd = ECM_CL_NL_GENL_CMD_ACCEL, +- .flags = 0, +- .policy = ecm_cl_nl_genl_policy, +- .doit = ecm_classifier_nl_genl_msg_ACCEL, +- .dumpit = NULL, +- }, +- { +- .cmd = ECM_CL_NL_GENL_CMD_ACCEL_OK, +- .flags = 0, +- .policy = ecm_cl_nl_genl_policy, +- .doit = NULL, +- .dumpit = ecm_classifier_nl_genl_msg_DUMP, +- }, +- { +- .cmd = ECM_CL_NL_GENL_CMD_CONNECTION_CLOSED, +- .flags = 0, +- .policy = ecm_cl_nl_genl_policy, +- .doit = NULL, +- .dumpit = ecm_classifier_nl_genl_msg_DUMP, +- }, +-}; +- + static int ecm_classifier_nl_register_genl(void) + { + int result; + +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 13, 0) +- result = genl_register_family_with_ops_groups(&ecm_cl_nl_genl_family, +- ecm_cl_nl_genl_ops, +- ecm_cl_nl_genl_mcgrp); +- if (result != 0) { +- DEBUG_ERROR("failed to register genl ops: %d\n", result); +- return result; +- } +-#else + result = genl_register_family(&ecm_cl_nl_genl_family); +- if (result != 0) { ++ if (result != 0) + DEBUG_ERROR("failed to register genl family: %d\n", result); +- goto err1; +- } +- +- result = genl_register_ops(&ecm_cl_nl_genl_family, +- ecm_cl_nl_genl_ops); +- if (result != 0) { +- DEBUG_ERROR("failed to register genl ops: %d\n", result); +- goto err2; +- } +- +- result = genl_register_mc_group(&ecm_cl_nl_genl_family, +- ecm_cl_nl_genl_mcgrp); +- if (result != 0) { +- DEBUG_ERROR("failed to register genl multicast group: %d\n", +- result); +- goto err3; +- } +- +- return 0; + +-err3: +- genl_unregister_ops(&ecm_cl_nl_genl_family, ecm_cl_nl_genl_ops); +-err2: +- genl_unregister_family(&ecm_cl_nl_genl_family); +-err1: +-#endif + return result; + } + +--- a/ecm_classifier_pcc.c ++++ b/ecm_classifier_pcc.c +@@ -49,7 +49,6 @@ + #include + #include + #include +-#include + #include + #include + #include +--- a/ecm_conntrack_notifier.c ++++ b/ecm_conntrack_notifier.c +@@ -51,7 +51,6 @@ + #include + #include + #include +-#include + #include + #include + #include +@@ -345,14 +344,6 @@ static int ecm_conntrack_event(unsigned + return NOTIFY_DONE; + } + +- /* +- * Special untracked connection is not monitored +- */ +- if (ct == &nf_conntrack_untracked) { +- DEBUG_TRACE("Fake connection event - ignoring\n"); +- return NOTIFY_DONE; +- } +- + /* + * Only interested if this is IPv4 or IPv6. + */ +--- a/ecm_db/ecm_db.c ++++ b/ecm_db/ecm_db.c +@@ -42,7 +42,6 @@ + #include + #include + #include +-#include + #include + #include + #include +--- a/ecm_db/ecm_db_connection.c ++++ b/ecm_db/ecm_db_connection.c +@@ -41,7 +41,6 @@ + #include + #include + #include +-#include + #include + #include + #include +--- a/ecm_db/ecm_db_host.c ++++ b/ecm_db/ecm_db_host.c +@@ -41,7 +41,6 @@ + #include + #include + #include +-#include + #include + #include + #include +--- a/ecm_db/ecm_db_iface.c ++++ b/ecm_db/ecm_db_iface.c +@@ -41,7 +41,6 @@ + #include + #include + #include +-#include + #include + #include + #include +--- a/ecm_db/ecm_db_listener.c ++++ b/ecm_db/ecm_db_listener.c +@@ -41,7 +41,6 @@ + #include + #include + #include +-#include + #include + #include + #include +--- a/ecm_db/ecm_db_mapping.c ++++ b/ecm_db/ecm_db_mapping.c +@@ -41,7 +41,6 @@ + #include + #include + #include +-#include + #include + #include + #include +--- a/ecm_db/ecm_db_multicast.c ++++ b/ecm_db/ecm_db_multicast.c +@@ -42,7 +42,6 @@ + #include + #include + #include +-#include + #include + #include + #include +--- a/ecm_db/ecm_db_node.c ++++ b/ecm_db/ecm_db_node.c +@@ -41,7 +41,6 @@ + #include + #include + #include +-#include + #include + #include + #include +--- a/ecm_db/ecm_db_timer.c ++++ b/ecm_db/ecm_db_timer.c +@@ -42,7 +42,6 @@ + #include + #include + #include +-#include + #include + #include + #include +@@ -387,7 +386,7 @@ EXPORT_SYMBOL(ecm_db_time_get); + * Manage expiration of connections + * NOTE: This is softirq context + */ +-static void ecm_db_timer_callback(unsigned long data) ++static void ecm_db_timer_callback(struct timer_list *arg) + { + uint32_t timer; + +@@ -425,9 +424,7 @@ void ecm_db_timer_init(void) + /* + * Set a timer to manage cleanup of expired connections + */ +- init_timer(&ecm_db_timer); +- ecm_db_timer.function = ecm_db_timer_callback; +- ecm_db_timer.data = 0; ++ timer_setup(&ecm_db_timer, ecm_db_timer_callback, 0); + ecm_db_timer.expires = jiffies + HZ; + add_timer(&ecm_db_timer); + +--- a/ecm_interface.c ++++ b/ecm_interface.c +@@ -66,7 +66,6 @@ + #include + #include + #include +-#include + #include + #include + #include +@@ -537,7 +536,7 @@ static bool ecm_interface_find_gateway_ipv4(ip_addr_t addr, ip_addr_t gw_addr) + return false; + } + +- ECM_NIN4_ADDR_TO_IP_ADDR(gw_addr, rt->rt_gateway) ++ ECM_NIN4_ADDR_TO_IP_ADDR(gw_addr, rt->rt_gw4) + ecm_interface_route_release(&ecm_rt); + return true; + } +@@ -596,7 +595,7 @@ static bool ecm_interface_mac_addr_get_ipv4(ip_addr_t addr, uint8_t *mac_addr, b + if (rt->rt_uses_gateway || (rt->rt_flags & RTF_GATEWAY)) { + #endif + *on_link = false; +- ECM_NIN4_ADDR_TO_IP_ADDR(gw_addr, rt->rt_gateway) ++ ECM_NIN4_ADDR_TO_IP_ADDR(gw_addr, rt->rt_gw4) + } else { + *on_link = true; + } +@@ -1003,7 +1002,7 @@ static bool ecm_interface_find_route_by_addr_ipv6(ip_addr_t addr, struct ecm_int + * Get a route to the given IP address, this will allow us to also find the interface + * it is using to communicate with that IP address. + */ +- ecm_rt->rt.rtv6 = rt6_lookup(&init_net, &naddr, NULL, 0, 0); ++ ecm_rt->rt.rtv6 = rt6_lookup(&init_net, &naddr, NULL, 0, NULL, 0); + if (!ecm_rt->rt.rtv6) { + DEBUG_TRACE("No output route to: " ECM_IP_ADDR_OCTAL_FMT "\n", ECM_IP_ADDR_TO_OCTAL(addr)); + return NULL; +@@ -1077,7 +1076,7 @@ void ecm_interface_send_neighbour_solicitation(struct net_device *dev, ip_addr_t + /* + * Find the route entry + */ +- rt6i = rt6_lookup(netf, &dst_addr, NULL, 0, 0); ++ rt6i = rt6_lookup(netf, &dst_addr, NULL, 0, NULL, 0); + if (!rt6i) { + DEBUG_TRACE("IPv6 Route lookup failure for destination IPv6 address " ECM_IP_ADDR_OCTAL_FMT "\n", ECM_IP_ADDR_TO_OCTAL(addr)); + return; +@@ -1104,7 +1103,7 @@ void ecm_interface_send_neighbour_solicitation(struct net_device *dev, ip_addr_t + #if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0)) + ndisc_send_ns(dev, neigh, &dst_addr, &mc_dst_addr, &src_addr); + #else +- ndisc_send_ns(dev, &dst_addr, &mc_dst_addr, &src_addr); ++ ndisc_send_ns(dev, &dst_addr, &mc_dst_addr, &src_addr, 0); + #endif + neigh_release(neigh); + dst_release(&rt6i->dst); +@@ -1194,7 +1193,7 @@ struct neighbour *ecm_interface_ipv6_neigh_get(ip_addr_t addr) + struct in6_addr ipv6_addr; + + ECM_IP_ADDR_TO_NIN6_ADDR(ipv6_addr, addr); +- rt = rt6_lookup(&init_net, &ipv6_addr, NULL, 0, 0); ++ rt = rt6_lookup(&init_net, &ipv6_addr, NULL, 0, NULL, 0); + if (!rt) { + return NULL; + } +@@ -1220,7 +1219,7 @@ bool ecm_interface_is_pptp(struct sk_buff *skb, const struct net_device *out) + * skip first pass of l2tp/pptp tunnel encapsulated traffic + */ + if (out->type == ARPHRD_PPP) { +- if (out->priv_flags & IFF_PPP_PPTP) { ++ if (out->priv_flags_qca_ecm & IFF_QCA_ECM_PPP_PPTP) { + return true; + } + } +@@ -1231,7 +1230,7 @@ bool ecm_interface_is_pptp(struct sk_buff *skb, const struct net_device *out) + } + + if (in->type == ARPHRD_PPP) { +- if (in->priv_flags & IFF_PPP_PPTP) { ++ if (in->priv_flags_qca_ecm & IFF_QCA_ECM_PPP_PPTP) { + dev_put(in); + return true; + } +@@ -1256,10 +1255,10 @@ bool ecm_interface_is_l2tp_packet_by_version(struct sk_buff *skb, const struct n + + switch (ver) { + case 2: +- flag = IFF_PPP_L2TPV2; ++ flag = IFF_QCA_ECM_PPP_L2TPV2; + break; + case 3: +- flag = IFF_PPP_L2TPV3; ++ flag = IFF_QCA_ECM_PPP_L2TPV3; + break; + default: + break; +@@ -1268,10 +1267,8 @@ bool ecm_interface_is_l2tp_packet_by_version(struct sk_buff *skb, const struct n + /* + * skip first pass of l2tp/pptp tunnel encapsulated traffic + */ +- if (out->type == ARPHRD_PPP) { +- if (out->priv_flags & flag) { +- return true; +- } ++ if (out->priv_flags_qca_ecm & flag) { ++ return true; + } + + in = dev_get_by_index(&init_net, skb->skb_iif); +@@ -1279,11 +1276,9 @@ bool ecm_interface_is_l2tp_packet_by_version(struct sk_buff *skb, const struct n + return true; + } + +- if (in->type == ARPHRD_PPP) { +- if (in->priv_flags & flag) { +- dev_put(in); +- return true; +- } ++ if (out->priv_flags_qca_ecm & flag) { ++ dev_put(in); ++ return true; + } + + dev_put(in); +@@ -1304,11 +1299,9 @@ bool ecm_interface_is_l2tp_pptp(struct sk_buff *skb, const struct net_device *ou + /* + * skip first pass of l2tp/pptp tunnel encapsulated traffic + */ +- if (out->type == ARPHRD_PPP) { +- if (out->priv_flags & (IFF_PPP_L2TPV2 | IFF_PPP_L2TPV3 | +- IFF_PPP_PPTP)) { +- return true; +- } ++ if (out->priv_flags_qca_ecm & (IFF_QCA_ECM_PPP_L2TPV2 | IFF_QCA_ECM_PPP_L2TPV3 | ++ IFF_QCA_ECM_PPP_PPTP)) { ++ return true; + } + + in = dev_get_by_index(&init_net, skb->skb_iif); +@@ -1316,12 +1309,10 @@ bool ecm_interface_is_l2tp_pptp(struct sk_buff *skb, const struct net_device *ou + return true; + } + +- if (in->type == ARPHRD_PPP) { +- if (in->priv_flags & (IFF_PPP_L2TPV2 | IFF_PPP_L2TPV3 | +- IFF_PPP_PPTP)) { +- dev_put(in); +- return true; +- } ++ if (out->priv_flags_qca_ecm & (IFF_QCA_ECM_PPP_L2TPV2 | IFF_QCA_ECM_PPP_L2TPV3 | ++ IFF_QCA_ECM_PPP_PPTP)) { ++ dev_put(in); ++ return true; + } + + dev_put(in); +@@ -2416,7 +2407,7 @@ struct ecm_db_iface_instance *ecm_interface_establish_and_ref(struct ecm_front_e + /* + * GRE TAP? + */ +- if (dev->priv_flags & (IFF_GRE_V4_TAP | IFF_GRE_V6_TAP)) { ++ if (dev->priv_flags_qca_ecm & (IFF_QCA_ECM_GRE_V4_TAP | IFF_QCA_ECM_GRE_V6_TAP)) { + interface_type = feci->ae_interface_type_get(feci, dev); + ae_interface_num = feci->ae_interface_number_by_dev_type_get(dev, interface_type); + +@@ -2680,7 +2671,7 @@ identifier_update: + /* + * OVPN Tunnel? + */ +- if ((dev_type == ARPHRD_NONE) && (dev->priv_flags & IFF_TUN_TAP)) { ++ if ((dev_type == ARPHRD_NONE) && (dev->priv_flags_qca_ecm & IFF_QCA_ECM_TUN_TAP)) { + struct net_device *tun_dev = NULL; + ip_addr_t saddr, daddr; + +@@ -2746,7 +2737,7 @@ identifier_update: + * ppp_is_multilink() and ppp_hold_channels() which acquire same lock + */ + +- if ((dev->priv_flags & IFF_PPP_L2TPV2) && ppp_is_xmit_locked(dev)) { ++ if ((dev->priv_flags_qca_ecm & IFF_QCA_ECM_PPP_L2TPV2) && ppp_is_xmit_locked(dev)) { + if (skb && (skb->skb_iif == dev->ifindex)) { + struct pppol2tp_common_addr info; + +@@ -2804,7 +2795,7 @@ identifier_update: + #endif + + #ifdef ECM_INTERFACE_PPTP_ENABLE +- if ((protocol == IPPROTO_GRE) && skb && v4_hdr && (dev->priv_flags & IFF_PPP_PPTP)) { ++ if ((protocol == IPPROTO_GRE) && skb && v4_hdr && (dev->priv_flags_qca_ecm & IFF_QCA_ECM_PPP_PPTP)) { + struct gre_hdr_pptp *gre_hdr; + uint16_t proto; + int ret; +@@ -3972,7 +3963,7 @@ int32_t ecm_interface_heirarchy_construct(struct ecm_front_end_connection_instan + if (((ip_version == 4) && (protocol == IPPROTO_IPV6)) || + ((ip_version == 6) && (protocol == IPPROTO_IPIP)) || + (protocol == IPPROTO_GRE) || +- ((given_dest_dev->type == ARPHRD_NONE) && (given_dest_dev->priv_flags & IFF_TUN_TAP))) { ++ ((given_dest_dev->type == ARPHRD_NONE) && (given_dest_dev->priv_flags_qca_ecm & IFF_QCA_ECM_TUN_TAP))) { + dev_put(dest_dev); + dest_dev = given_dest_dev; + if (dest_dev) { +@@ -3991,7 +3982,7 @@ int32_t ecm_interface_heirarchy_construct(struct ecm_front_end_connection_instan + /* + * if the address is a local address and indev=l2tp. + */ +- if ((given_src_dev->type == ARPHRD_PPP) && (given_src_dev->priv_flags & IFF_PPP_L2TPV2) && ppp_is_xmit_locked(given_src_dev)) { ++ if ((given_src_dev->type == ARPHRD_PPP) && (given_src_dev->priv_flags_qca_ecm & IFF_QCA_ECM_PPP_L2TPV2) && ppp_is_xmit_locked(given_src_dev)) { + dev_put(dest_dev); + dest_dev = given_dest_dev; + if (dest_dev) { +@@ -4005,7 +3996,7 @@ int32_t ecm_interface_heirarchy_construct(struct ecm_front_end_connection_instan + /* + * if the address is a local address and indev=PPTP. + */ +- if (protocol == IPPROTO_GRE && given_dest_dev && (given_dest_dev->priv_flags & IFF_PPP_PPTP)){ ++ if (protocol == IPPROTO_GRE && given_dest_dev && (given_dest_dev->priv_flags_qca_ecm & IFF_QCA_ECM_PPP_PPTP)){ + dev_put(dest_dev); + dest_dev = given_dest_dev; + if (dest_dev) { +@@ -4054,7 +4045,7 @@ int32_t ecm_interface_heirarchy_construct(struct ecm_front_end_connection_instan + if (((ip_version == 4) && (protocol == IPPROTO_IPV6)) || + ((ip_version == 6) && (protocol == IPPROTO_IPIP)) || + (protocol == IPPROTO_GRE) || +- ((given_src_dev->type == ARPHRD_NONE) && (given_src_dev->priv_flags & IFF_TUN_TAP))) { ++ ((given_src_dev->type == ARPHRD_NONE) && (given_src_dev->priv_flags_qca_ecm & IFF_QCA_ECM_TUN_TAP))) { + dev_put(src_dev); + src_dev = given_src_dev; + if (src_dev) { +@@ -4504,7 +4495,7 @@ lag_success: + /* + * OVPN ? + */ +- if ((dest_dev_type == ARPHRD_NONE) && (dest_dev->priv_flags & IFF_TUN_TAP)) { ++ if ((dest_dev_type == ARPHRD_NONE) && (dest_dev->priv_flags_qca_ecm & IFF_QCA_ECM_TUN_TAP)) { + DEBUG_TRACE("Net device: %p is OVPN, device name: %s\n", dest_dev, dest_dev->name); + break; + } +@@ -4523,7 +4514,7 @@ lag_success: + DEBUG_TRACE("%p: Net device: %p is PPP\n", feci, dest_dev); + + #ifdef ECM_INTERFACE_L2TPV2_ENABLE +- if ((given_src_dev->priv_flags & IFF_PPP_L2TPV2) && ppp_is_xmit_locked(given_src_dev)) { ++ if ((given_src_dev->priv_flags_qca_ecm & IFF_QCA_ECM_PPP_L2TPV2) && ppp_is_xmit_locked(given_src_dev)) { + if (skb->skb_iif == dest_dev->ifindex) { + DEBUG_TRACE("%p: Net device: %p PPP channel is PPPoL2TPV2\n", feci, dest_dev); + break; +@@ -4532,7 +4523,7 @@ lag_success: + #endif + + #ifdef ECM_INTERFACE_PPTP_ENABLE +- if (protocol == IPPROTO_GRE && dest_dev && (dest_dev->priv_flags & IFF_PPP_PPTP)) { ++ if (protocol == IPPROTO_GRE && dest_dev && (dest_dev->priv_flags_qca_ecm & IFF_QCA_ECM_PPP_PPTP)) { + DEBUG_TRACE("%p: Net device: %p PPP channel is PPTP\n", feci, dest_dev); + break; + } +@@ -4798,7 +4789,7 @@ int32_t ecm_interface_multicast_from_heirarchy_construct(struct ecm_front_end_co + /* + * if the address is a local address and indev=l2tp. + */ +- if ((given_src_dev->type == ARPHRD_PPP) && (given_src_dev->priv_flags & IFF_PPP_L2TPV2) && ppp_is_xmit_locked(given_src_dev)) { ++ if ((given_src_dev->type == ARPHRD_PPP) && (given_src_dev->priv_flags_qca_ecm & IFF_QCA_ECM_PPP_L2TPV2) && ppp_is_xmit_locked(given_src_dev)) { + dev_put(dest_dev); + dest_dev = given_dest_dev; + if (dest_dev) { +@@ -5265,7 +5256,7 @@ int32_t ecm_interface_multicast_from_heirarchy_construct(struct ecm_front_end_co + DEBUG_TRACE("Net device: %p is PPP\n", dest_dev); + + #ifdef ECM_INTERFACE_L2TPV2_ENABLE +- if ((given_src_dev->priv_flags & IFF_PPP_L2TPV2) && ppp_is_xmit_locked(given_src_dev)) { ++ if ((given_src_dev->priv_flags_qca_ecm & IFF_QCA_ECM_PPP_L2TPV2) && ppp_is_xmit_locked(given_src_dev)) { + if (skb->skb_iif == dest_dev->ifindex) { + DEBUG_TRACE("Net device: %p PPP channel is PPPoL2TPV2\n", dest_dev); + break; +@@ -6520,7 +6511,7 @@ static int ecm_interface_wifi_event_rx(struct socket *sock, struct sockaddr_nl * + #endif + oldfs = get_fs(); + set_fs(KERNEL_DS); +- size = sock_recvmsg(sock, &msg, len, msg.msg_flags); ++ size = sock_recvmsg(sock, &msg, msg.msg_flags); + set_fs(oldfs); + + return size; +@@ -6609,7 +6600,7 @@ int ecm_interface_wifi_event_stop(void) + } + + DEBUG_INFO("kill ecm_interface_wifi_event thread\n"); +- force_sig(SIGKILL, __ewn.thread); ++ send_sig(SIGKILL, __ewn.thread, 1); + err = kthread_stop(__ewn.thread); + __ewn.thread = NULL; + +--- a/ecm_tracker.c ++++ b/ecm_tracker.c +@@ -43,7 +43,6 @@ + #include + #include + #include +-#include + #include + #include + #include +--- a/ecm_tracker_datagram.c ++++ b/ecm_tracker_datagram.c +@@ -43,7 +43,6 @@ + #include + #include + #include +-#include + #include + #include + #include +--- a/ecm_tracker_tcp.c ++++ b/ecm_tracker_tcp.c +@@ -43,7 +43,6 @@ + #include + #include + #include +-#include + #include + #include + #include +@@ -1143,7 +1142,7 @@ static bool ecm_tracker_tcp_extract_mss( + const u8 *hash_location; + tcp_parse_options(skb, &opt_rx, &hash_location, 0); + #elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)) +- tcp_parse_options(skb, &opt_rx, 0, NULL); ++ tcp_parse_options(&init_net, skb, &opt_rx, 0, NULL); + #else + #error "Unsupported kernel version for tcp_parse_options()" + #endif +--- a/ecm_tracker_udp.c ++++ b/ecm_tracker_udp.c +@@ -43,7 +43,6 @@ + #include + #include + #include +-#include + #include + #include + #include +--- a/frontends/ecm_front_end_ipv4.c ++++ b/frontends/ecm_front_end_ipv4.c +@@ -215,7 +215,7 @@ bool ecm_front_end_ipv4_interface_constr + * behind a gateway. + */ + DEBUG_TRACE("Gateway address will be looked up overwrite the rt_dst_addr\n"); +- ECM_NIN4_ADDR_TO_IP_ADDR(rt_dst_addr, rt->rt_gateway) ++ ECM_NIN4_ADDR_TO_IP_ADDR(rt_dst_addr, rt->rt_gw4) + gateway = true; + } + +--- a/frontends/include/ecm_front_end_common.h ++++ b/frontends/include/ecm_front_end_common.h +@@ -98,13 +98,6 @@ static inline bool ecm_front_end_acceler + return false; + } + +- if (unlikely(nf_ct_is_untracked(ct))) { +- /* +- * Untracked traffic certainly can't be accelerated. +- */ +- return true; +- } +- + #if (LINUX_VERSION_CODE <= KERNEL_VERSION(3, 6, 0)) + acct = nf_conn_acct_find(ct); + #else +--- a/frontends/nss/ecm_nss_bond_notifier.c ++++ b/frontends/nss/ecm_nss_bond_notifier.c +@@ -52,7 +52,6 @@ + #include + #include + #include +-#include + #include + #include + #include +--- a/frontends/nss/ecm_nss_common.h ++++ b/frontends/nss/ecm_nss_common.h +@@ -144,7 +144,7 @@ static inline int32_t ecm_nss_common_get_interface_type(struct ecm_front_end_con + /* + * If device is not GRETAP then return NONE. + */ +- if (!(dev->priv_flags & (IFF_GRE_V4_TAP | IFF_GRE_V6_TAP))) { ++ if (!(dev->priv_flags_qca_ecm & (IFF_QCA_ECM_GRE_V4_TAP | IFF_QCA_ECM_GRE_V6_TAP))) { + break; + } + #endif +--- a/frontends/nss/ecm_nss_ipv4.c ++++ b/frontends/nss/ecm_nss_ipv4.c +@@ -48,7 +48,6 @@ + #include + #include + #include +-#include + #if (LINUX_VERSION_CODE <= KERNEL_VERSION(4, 2, 0)) + #include + #else +@@ -1053,7 +1052,7 @@ static unsigned int ecm_nss_ipv4_ip_process(struct net_device *out_dev, struct n + * If any of the input or output interface is a GRE V4 TAP/TUN interface + * we can continue to accelerate it. + */ +- if ((in_dev->priv_flags & IFF_GRE_V4_TAP) || (out_dev->priv_flags & IFF_GRE_V4_TAP)) { ++ if ((in_dev->priv_flags_qca_ecm & IFF_QCA_ECM_GRE_V4_TAP) || (out_dev->priv_flags_qca_ecm & IFF_QCA_ECM_GRE_V4_TAP)) { + #ifndef ECM_INTERFACE_GRE_TAP_ENABLE + DEBUG_TRACE("GRE TAP acceleration is disabled\n"); + return NF_ACCEPT; +@@ -1082,7 +1081,7 @@ static unsigned int ecm_nss_ipv4_ip_process(struct net_device *out_dev, struct n + reply_tuple.dst.u3.ip = orig_tuple.src.u3.ip; + sender = ECM_TRACKER_SENDER_TYPE_SRC; + } else { +- if (unlikely(ct == &nf_conntrack_untracked)) { ++ if (unlikely(ctinfo == IP_CT_UNTRACKED)) { + DEBUG_TRACE("%p: ct: untracked\n", skb); + return NF_ACCEPT; + } +@@ -2097,7 +2096,6 @@ sync_conntrack: + } + + ct = nf_ct_tuplehash_to_ctrack(h); +- NF_CT_ASSERT(ct->timeout.data == (unsigned long)ct); + DEBUG_TRACE("%p: NSS Sync: conntrack connection\n", ct); + + ecm_front_end_flow_and_return_directions_get(ct, flow_ip, 4, &flow_dir, &return_dir); +@@ -2108,7 +2106,7 @@ sync_conntrack: + */ + if (!test_bit(IPS_FIXED_TIMEOUT_BIT, &ct->status)) { + spin_lock_bh(&ct->lock); +- ct->timeout.expires += delta_jiffies; ++ ct->timeout += delta_jiffies; + spin_unlock_bh(&ct->lock); + } + +@@ -2166,17 +2164,15 @@ sync_conntrack: + u_int64_t reply_pkts = atomic64_read(&acct[IP_CT_DIR_REPLY].packets); + + if (reply_pkts != 0) { +- struct nf_conntrack_l4proto *l4proto; + unsigned int *timeouts; + + set_bit(IPS_SEEN_REPLY_BIT, &ct->status); + set_bit(IPS_ASSURED_BIT, &ct->status); + +- l4proto = __nf_ct_l4proto_find(AF_INET, IPPROTO_UDP); +- timeouts = nf_ct_timeout_lookup(&init_net, ct, l4proto); ++ timeouts = nf_ct_timeout_lookup(ct); + + spin_lock_bh(&ct->lock); +- ct->timeout.expires = jiffies + timeouts[UDP_CT_REPLIED]; ++ ct->timeout = jiffies + timeouts[UDP_CT_REPLIED]; + spin_unlock_bh(&ct->lock); + } + } +@@ -2690,7 +2686,8 @@ int ecm_nss_ipv4_init(struct dentry *dentry) + /* + * Register netfilter hooks + */ +- result = nf_register_hooks(ecm_nss_ipv4_netfilter_hooks, ARRAY_SIZE(ecm_nss_ipv4_netfilter_hooks)); ++ result = nf_register_net_hooks(&init_net, ecm_nss_ipv4_netfilter_hooks, \ ++ ARRAY_SIZE(ecm_nss_ipv4_netfilter_hooks)); + if (result < 0) { + DEBUG_ERROR("Can't register netfilter hooks.\n"); + nss_ipv4_notify_unregister(); +@@ -2702,8 +2699,8 @@ int ecm_nss_ipv4_init(struct dentry *dentry) + if (result < 0) { + DEBUG_ERROR("Failed to init ecm ipv4 multicast frontend\n"); + nss_ipv4_notify_unregister(); +- nf_unregister_hooks(ecm_nss_ipv4_netfilter_hooks, +- ARRAY_SIZE(ecm_nss_ipv4_netfilter_hooks)); ++ nf_unregister_net_hooks(&init_net, ecm_nss_ipv4_netfilter_hooks, ++ ARRAY_SIZE(ecm_nss_ipv4_netfilter_hooks)); + goto task_cleanup; + } + #endif +@@ -2714,8 +2711,8 @@ int ecm_nss_ipv4_init(struct dentry *dentry) + #ifdef ECM_MULTICAST_ENABLE + ecm_nss_multicast_ipv4_exit(); + #endif +- nf_unregister_hooks(ecm_nss_ipv4_netfilter_hooks, +- ARRAY_SIZE(ecm_nss_ipv4_netfilter_hooks)); ++ nf_unregister_net_hooks(&init_net, ecm_nss_ipv4_netfilter_hooks, ++ ARRAY_SIZE(ecm_nss_ipv4_netfilter_hooks)); + goto task_cleanup; + } + +@@ -2742,8 +2739,8 @@ void ecm_nss_ipv4_exit(void) + /* + * Stop the network stack hooks + */ +- nf_unregister_hooks(ecm_nss_ipv4_netfilter_hooks, +- ARRAY_SIZE(ecm_nss_ipv4_netfilter_hooks)); ++ nf_unregister_net_hooks(&init_net, ecm_nss_ipv4_netfilter_hooks, ++ ARRAY_SIZE(ecm_nss_ipv4_netfilter_hooks)); + + /* + * Unregister from the Linux NSS Network driver +--- a/frontends/nss/ecm_nss_ipv6.c ++++ b/frontends/nss/ecm_nss_ipv6.c +@@ -51,7 +51,6 @@ + #include + #include + #include +-#include + #if (LINUX_VERSION_CODE <= KERNEL_VERSION(4, 2, 0)) + #include + #else +@@ -1035,7 +1034,7 @@ static unsigned int ecm_nss_ipv6_ip_process(struct net_device *out_dev, struct n + * If any of the input or output interface is a GRE V4 TAP/TUN interface + * we can continue to accelerate it. + */ +- if ((in_dev->priv_flags & IFF_GRE_V4_TAP) || (out_dev->priv_flags & IFF_GRE_V4_TAP)) { ++ if ((in_dev->priv_flags_qca_ecm & IFF_QCA_ECM_GRE_V4_TAP) || (out_dev->priv_flags_qca_ecm & IFF_QCA_ECM_GRE_V4_TAP)) { + #ifndef ECM_INTERFACE_GRE_TAP_ENABLE + DEBUG_TRACE("GRE TAP acceleration is disabled\n"); + return NF_ACCEPT; +@@ -1064,7 +1063,7 @@ static unsigned int ecm_nss_ipv6_ip_process(struct net_device *out_dev, struct n + ECM_IP_ADDR_TO_NIN6_ADDR(reply_tuple.dst.u3.in6, ip_hdr.src_addr); + sender = ECM_TRACKER_SENDER_TYPE_SRC; + } else { +- if (unlikely(ct == &nf_conntrack_untracked)) { ++ if (unlikely(ctinfo == IP_CT_UNTRACKED)) { + DEBUG_TRACE("%p: ct: untracked\n", skb); + return NF_ACCEPT; + } +@@ -1809,7 +1808,6 @@ sync_conntrack: + } + + ct = nf_ct_tuplehash_to_ctrack(h); +- NF_CT_ASSERT(ct->timeout.data == (unsigned long)ct); + DEBUG_TRACE("%p: NSS Sync: conntrack connection\n", ct); + + ecm_front_end_flow_and_return_directions_get(ct, flow_ip, 6, &flow_dir, &return_dir); +@@ -1820,7 +1818,7 @@ sync_conntrack: + */ + if (!test_bit(IPS_FIXED_TIMEOUT_BIT, &ct->status)) { + spin_lock_bh(&ct->lock); +- ct->timeout.expires += delta_jiffies; ++ ct->timeout += delta_jiffies; + spin_unlock_bh(&ct->lock); + } + +@@ -1878,17 +1876,15 @@ sync_conntrack: + u_int64_t reply_pkts = atomic64_read(&acct[IP_CT_DIR_REPLY].packets); + + if (reply_pkts != 0) { +- struct nf_conntrack_l4proto *l4proto; + unsigned int *timeouts; + + set_bit(IPS_SEEN_REPLY_BIT, &ct->status); + set_bit(IPS_ASSURED_BIT, &ct->status); + +- l4proto = __nf_ct_l4proto_find(AF_INET6, IPPROTO_UDP); +- timeouts = nf_ct_timeout_lookup(&init_net, ct, l4proto); ++ timeouts = nf_ct_timeout_lookup(ct); + + spin_lock_bh(&ct->lock); +- ct->timeout.expires = jiffies + timeouts[UDP_CT_REPLIED]; ++ ct->timeout = jiffies + timeouts[UDP_CT_REPLIED]; + spin_unlock_bh(&ct->lock); + } + } +@@ -2402,7 +2398,7 @@ int ecm_nss_ipv6_init(struct dentry *dentry) + /* + * Register netfilter hooks + */ +- result = nf_register_hooks(ecm_nss_ipv6_netfilter_hooks, ARRAY_SIZE(ecm_nss_ipv6_netfilter_hooks)); ++ result = nf_register_net_hooks(&init_net, ecm_nss_ipv6_netfilter_hooks, ARRAY_SIZE(ecm_nss_ipv6_netfilter_hooks)); + if (result < 0) { + DEBUG_ERROR("Can't register netfilter hooks.\n"); + nss_ipv6_notify_unregister(); +@@ -2414,8 +2410,8 @@ int ecm_nss_ipv6_init(struct dentry *dentry) + if (result < 0) { + DEBUG_ERROR("Failed to init ecm ipv6 multicast frontend\n"); + nss_ipv6_notify_unregister(); +- nf_unregister_hooks(ecm_nss_ipv6_netfilter_hooks, +- ARRAY_SIZE(ecm_nss_ipv6_netfilter_hooks)); ++ nf_unregister_net_hooks(&init_net, ecm_nss_ipv6_netfilter_hooks, ++ ARRAY_SIZE(ecm_nss_ipv6_netfilter_hooks)); + goto task_cleanup; + } + #endif +@@ -2426,8 +2422,8 @@ int ecm_nss_ipv6_init(struct dentry *dentry) + #ifdef ECM_MULTICAST_ENABLE + ecm_nss_multicast_ipv6_exit(); + #endif +- nf_unregister_hooks(ecm_nss_ipv6_netfilter_hooks, +- ARRAY_SIZE(ecm_nss_ipv6_netfilter_hooks)); ++ nf_unregister_net_hooks(&init_net, ecm_nss_ipv6_netfilter_hooks, ++ ARRAY_SIZE(ecm_nss_ipv6_netfilter_hooks)); + goto task_cleanup; + } + +@@ -2453,8 +2449,8 @@ void ecm_nss_ipv6_exit(void) + /* + * Stop the network stack hooks + */ +- nf_unregister_hooks(ecm_nss_ipv6_netfilter_hooks, +- ARRAY_SIZE(ecm_nss_ipv6_netfilter_hooks)); ++ nf_unregister_net_hooks(&init_net, ecm_nss_ipv6_netfilter_hooks, ++ ARRAY_SIZE(ecm_nss_ipv6_netfilter_hooks)); + + /* + * Unregister from the Linux NSS Network driver +--- a/frontends/nss/ecm_nss_multicast_ipv4.c ++++ b/frontends/nss/ecm_nss_multicast_ipv4.c +@@ -50,7 +50,6 @@ + #include + #include + #include +-#include + #include + #include + #include +--- a/frontends/nss/ecm_nss_multicast_ipv6.c ++++ b/frontends/nss/ecm_nss_multicast_ipv6.c +@@ -51,7 +51,6 @@ + #include + #include + #include +-#include + #include + #include + #include +--- a/frontends/nss/ecm_nss_non_ported_ipv4.c ++++ b/frontends/nss/ecm_nss_non_ported_ipv4.c +@@ -47,7 +47,6 @@ + #include + #include + #include +-#include + #include + #include + #include +@@ -640,7 +639,7 @@ static void ecm_nss_non_ported_ipv4_connection_accelerate(struct ecm_front_end_c + #ifdef ECM_INTERFACE_GRE_TAP_ENABLE + dev = dev_get_by_index(&init_net, ecm_db_iface_interface_identifier_get(ii)); + if (dev) { +- if (dev->priv_flags & IFF_GRE_V4_TAP) { ++ if (dev->priv_flags_qca_ecm & IFF_QCA_ECM_GRE_V4_TAP) { + /* + * Clear QOS_VALID to prevent outer rule from overwriting + * inner flow's QoS classification. +--- a/frontends/nss/ecm_nss_non_ported_ipv6.c ++++ b/frontends/nss/ecm_nss_non_ported_ipv6.c +@@ -47,7 +47,6 @@ + #include + #include + #include +-#include + #include + #include + #include +@@ -548,7 +547,7 @@ static void ecm_nss_non_ported_ipv6_connection_accelerate(struct ecm_front_end_c + #ifdef ECM_INTERFACE_GRE_TAP_ENABLE + dev = dev_get_by_index(&init_net, ecm_db_iface_interface_identifier_get(ii)); + if (dev) { +- if (dev->priv_flags & IFF_GRE_V6_TAP) { ++ if (dev->priv_flags_qca_ecm & IFF_QCA_ECM_GRE_V6_TAP) { + /* + * Clear QOS_VALID to prevent outer rule from overwriting + * inner flow's QoS classification. +--- a/frontends/nss/ecm_nss_ported_ipv4.c ++++ b/frontends/nss/ecm_nss_ported_ipv4.c +@@ -47,7 +47,6 @@ + #include + #include + #include +-#include + #include + #include + #include +--- a/frontends/nss/ecm_nss_ported_ipv6.c ++++ b/frontends/nss/ecm_nss_ported_ipv6.c +@@ -47,7 +47,6 @@ + #include + #include + #include +-#include + #include + #include + #include +@@ -1996,7 +1995,7 @@ unsigned int ecm_nss_ported_ipv6_process + /* + * Deny acceleration for L2TP-over-UDP tunnel + */ +- if ((in_dev->priv_flags & IFF_PPP_L2TPV2) && ppp_is_xmit_locked(in_dev)) { ++ if ((in_dev->priv_flags_qca_ecm & IFF_QCA_ECM_PPP_L2TPV2) && ppp_is_xmit_locked(in_dev)) { + DEBUG_TRACE("Skip packets for L2TP tunnel in skb %p\n", skb); + can_accel = false; + } +--- a/frontends/sfe/ecm_sfe_ipv4.c ++++ b/frontends/sfe/ecm_sfe_ipv4.c +@@ -47,7 +47,6 @@ + #include + #include + #include +-#include + #if (LINUX_VERSION_CODE <= KERNEL_VERSION(4, 2, 0)) + #include + #else +@@ -746,7 +745,8 @@ static unsigned int ecm_sfe_ipv4_ip_proc + * If skb_dst(skb)->xfrm is not null, packet is to be encrypted by ipsec, we can't accelerate it. + * If skb->sp is not null, packet is decrypted by ipsec. We only accelerate it when configuration didn't reject ipsec. + */ +- if (unlikely((skb_dst(skb) && skb_dst(skb)->xfrm) || (ecm_sfe_ipv4_reject_acceleration_for_ipsec && skb->sp))) { ++ if (unlikely((skb_dst(skb) && skb_dst(skb)->xfrm) || \ ++ (ecm_sfe_ipv4_reject_acceleration_for_ipsec && skb_ext_exist(skb, SKB_EXT_SEC_PATH)))) { + DEBUG_TRACE("skip local ipsec flows\n"); + return NF_ACCEPT; + } +@@ -762,7 +762,7 @@ static unsigned int ecm_sfe_ipv4_ip_process(struct net_device *out_dev, struct n + reply_tuple.dst.u3.ip = orig_tuple.src.u3.ip; + sender = ECM_TRACKER_SENDER_TYPE_SRC; + } else { +- if (unlikely(ct == &nf_conntrack_untracked)) { ++ if (unlikely(ctinfo == IP_CT_UNTRACKED)) { + DEBUG_TRACE("%p: ct: untracked\n", skb); + return NF_ACCEPT; + } +@@ -1531,7 +1526,6 @@ sync_conntrack: + } + + ct = nf_ct_tuplehash_to_ctrack(h); +- NF_CT_ASSERT(ct->timeout.data == (unsigned long)ct); + DEBUG_TRACE("%p: SFE Sync: conntrack connection\n", ct); + + ecm_front_end_flow_and_return_directions_get(ct, flow_ip, 4, &flow_dir, &return_dir); +@@ -1551,7 +1545,7 @@ sync_conntrack: + delta_jiffies = ((sync->inc_ticks * HZ) + (MSEC_PER_SEC / 2)) / MSEC_PER_SEC; + + spin_lock_bh(&ct->lock); +- ct->timeout.expires += delta_jiffies; ++ ct->timeout += delta_jiffies; + spin_unlock_bh(&ct->lock); + } + +@@ -1609,17 +1603,15 @@ sync_conntrack: + u_int64_t reply_pkts = atomic64_read(&acct[IP_CT_DIR_REPLY].packets); + + if (reply_pkts != 0) { +- struct nf_conntrack_l4proto *l4proto; + unsigned int *timeouts; + + set_bit(IPS_SEEN_REPLY_BIT, &ct->status); + set_bit(IPS_ASSURED_BIT, &ct->status); + +- l4proto = __nf_ct_l4proto_find(AF_INET, IPPROTO_UDP); +- timeouts = nf_ct_timeout_lookup(&init_net, ct, l4proto); ++ timeouts = nf_ct_timeout_lookup(ct); + + spin_lock_bh(&ct->lock); +- ct->timeout.expires = jiffies + timeouts[UDP_CT_REPLIED]; ++ ct->timeout = jiffies + timeouts[UDP_CT_REPLIED]; + spin_unlock_bh(&ct->lock); + } + } +@@ -1901,7 +1893,7 @@ int ecm_sfe_ipv4_init(struct dentry *den + /* + * Register netfilter hooks + */ +- result = nf_register_hooks(ecm_sfe_ipv4_netfilter_hooks, ARRAY_SIZE(ecm_sfe_ipv4_netfilter_hooks)); ++ result = nf_register_net_hooks(&init_net, ecm_sfe_ipv4_netfilter_hooks, ARRAY_SIZE(ecm_sfe_ipv4_netfilter_hooks)); + if (result < 0) { + DEBUG_ERROR("Can't register netfilter hooks.\n"); + sfe_drv_ipv4_notify_unregister(); +@@ -1934,8 +1926,8 @@ void ecm_sfe_ipv4_exit(void) + /* + * Stop the network stack hooks + */ +- nf_unregister_hooks(ecm_sfe_ipv4_netfilter_hooks, +- ARRAY_SIZE(ecm_sfe_ipv4_netfilter_hooks)); ++ nf_unregister_net_hooks(&init_net, ecm_sfe_ipv4_netfilter_hooks, ++ ARRAY_SIZE(ecm_sfe_ipv4_netfilter_hooks)); + + /* + * Unregister from the simulated sfe driver +--- a/frontends/sfe/ecm_sfe_ipv6.c ++++ b/frontends/sfe/ecm_sfe_ipv6.c +@@ -51,7 +51,6 @@ + #include + #include + #include +-#include + #if (LINUX_VERSION_CODE <= KERNEL_VERSION(4, 2, 0)) + #include + #else +@@ -714,7 +713,8 @@ static unsigned int ecm_sfe_ipv6_ip_proc + * If skb_dst(skb)->xfrm is not null, packet is to be encrypted by ipsec, we can't accelerate it. + * If skb->sp is not null, packet is decrypted by ipsec. We only accelerate it when configuration didn't reject ipsec. + */ +- if (unlikely((skb_dst(skb) && skb_dst(skb)->xfrm) || (ecm_sfe_ipv6_reject_acceleration_for_ipsec && skb->sp))) { ++ if (unlikely((skb_dst(skb) && skb_dst(skb)->xfrm) || \ ++ (ecm_sfe_ipv6_reject_acceleration_for_ipsec && skb_ext_exist(skb, SKB_EXT_SEC_PATH)))) { + DEBUG_TRACE("skip local ipsec flows\n"); + return NF_ACCEPT; + } +@@ -733,7 +733,7 @@ static unsigned int ecm_sfe_ipv6_ip_proc + ECM_IP_ADDR_TO_NIN6_ADDR(reply_tuple.dst.u3.in6, ip_hdr.src_addr); + sender = ECM_TRACKER_SENDER_TYPE_SRC; + } else { +- if (unlikely(ct == &nf_conntrack_untracked)) { ++ if (unlikely(ctinfo == IP_CT_UNTRACKED)) { + DEBUG_TRACE("%p: ct: untracked\n", skb); + return NF_ACCEPT; + } +@@ -1255,7 +1255,6 @@ sync_conntrack: + } + + ct = nf_ct_tuplehash_to_ctrack(h); +- NF_CT_ASSERT(ct->timeout.data == (unsigned long)ct); + DEBUG_TRACE("%p: SFE Sync: conntrack connection\n", ct); + + ecm_front_end_flow_and_return_directions_get(ct, flow_ip, 6, &flow_dir, &return_dir); +@@ -1275,7 +1274,7 @@ sync_conntrack: + delta_jiffies = ((sync->inc_ticks * HZ) + (MSEC_PER_SEC / 2)) / MSEC_PER_SEC; + + spin_lock_bh(&ct->lock); +- ct->timeout.expires += delta_jiffies; ++ ct->timeout += delta_jiffies; + spin_unlock_bh(&ct->lock); + } + #if (LINUX_VERSION_CODE <= KERNEL_VERSION(3,6,0)) +@@ -1332,17 +1331,15 @@ sync_conntrack: + u_int64_t reply_pkts = atomic64_read(&acct[IP_CT_DIR_REPLY].packets); + + if (reply_pkts != 0) { +- struct nf_conntrack_l4proto *l4proto; + unsigned int *timeouts; + + set_bit(IPS_SEEN_REPLY_BIT, &ct->status); + set_bit(IPS_ASSURED_BIT, &ct->status); + +- l4proto = __nf_ct_l4proto_find(AF_INET6, IPPROTO_UDP); +- timeouts = nf_ct_timeout_lookup(&init_net, ct, l4proto); ++ timeouts = nf_ct_timeout_lookup(ct); + + spin_lock_bh(&ct->lock); +- ct->timeout.expires = jiffies + timeouts[UDP_CT_REPLIED]; ++ ct->timeout = jiffies + timeouts[UDP_CT_REPLIED]; + spin_unlock_bh(&ct->lock); + } + } +@@ -1624,7 +1621,7 @@ int ecm_sfe_ipv6_init(struct dentry *den + /* + * Register netfilter hooks + */ +- result = nf_register_hooks(ecm_sfe_ipv6_netfilter_hooks, ARRAY_SIZE(ecm_sfe_ipv6_netfilter_hooks)); ++ result = nf_register_net_hooks(&init_net, ecm_sfe_ipv6_netfilter_hooks, ARRAY_SIZE(ecm_sfe_ipv6_netfilter_hooks)); + if (result < 0) { + DEBUG_ERROR("Can't register netfilter hooks.\n"); + sfe_drv_ipv6_notify_unregister(); +@@ -1656,8 +1653,8 @@ void ecm_sfe_ipv6_exit(void) + /* + * Stop the network stack hooks + */ +- nf_unregister_hooks(ecm_sfe_ipv6_netfilter_hooks, +- ARRAY_SIZE(ecm_sfe_ipv6_netfilter_hooks)); ++ nf_unregister_net_hooks(&init_net, ecm_sfe_ipv6_netfilter_hooks, ++ ARRAY_SIZE(ecm_sfe_ipv6_netfilter_hooks)); + + /* + * Unregister from the Linux SFE Network driver +--- a/frontends/sfe/ecm_sfe_non_ported_ipv4.c ++++ b/frontends/sfe/ecm_sfe_non_ported_ipv4.c +@@ -46,7 +46,6 @@ + #include + #include + #include +-#include + #include + #include + #include +@@ -1829,7 +1828,7 @@ unsigned int ecm_sfe_non_ported_ipv4_pro + /* + * Packet has been decrypted by ipsec, mark it in connection. + */ +- if (unlikely(skb->sp)) { ++ if (unlikely(skb_ext_exist(skb, SKB_EXT_SEC_PATH))) { + ((struct ecm_sfe_non_ported_ipv4_connection_instance *)feci)->flow_ipsec_state = ECM_SFE_IPSEC_STATE_WAS_DECRYPTED; + ((struct ecm_sfe_non_ported_ipv4_connection_instance *)feci)->return_ipsec_state = ECM_SFE_IPSEC_STATE_TO_ENCRYPT; + } +--- a/frontends/sfe/ecm_sfe_non_ported_ipv6.c ++++ b/frontends/sfe/ecm_sfe_non_ported_ipv6.c +@@ -47,7 +47,6 @@ + #include + #include + #include +-#include + #include + #include + #include +@@ -1710,7 +1709,7 @@ unsigned int ecm_sfe_non_ported_ipv6_pro + /* + * Packet has been decrypted by ipsec, mark it in connection. + */ +- if (unlikely(skb->sp)) { ++ if (unlikely(skb_ext_exist(skb, SKB_EXT_SEC_PATH))) { + ((struct ecm_sfe_non_ported_ipv6_connection_instance *)feci)->flow_ipsec_state = ECM_SFE_IPSEC_STATE_WAS_DECRYPTED; + ((struct ecm_sfe_non_ported_ipv6_connection_instance *)feci)->return_ipsec_state = ECM_SFE_IPSEC_STATE_TO_ENCRYPT; + } +--- a/frontends/sfe/ecm_sfe_ported_ipv4.c ++++ b/frontends/sfe/ecm_sfe_ported_ipv4.c +@@ -46,7 +46,6 @@ + #include + #include + #include +-#include + #include + #include + #include +@@ -2053,7 +2052,7 @@ unsigned int ecm_sfe_ported_ipv4_process + /* + * Packet has been decrypted by ipsec, mark it in connection. + */ +- if (unlikely(skb->sp)) { ++ if (unlikely(skb_ext_exist(skb, SKB_EXT_SEC_PATH))) { + ((struct ecm_sfe_ported_ipv4_connection_instance *)feci)->flow_ipsec_state = ECM_SFE_IPSEC_STATE_WAS_DECRYPTED; + ((struct ecm_sfe_ported_ipv4_connection_instance *)feci)->return_ipsec_state = ECM_SFE_IPSEC_STATE_TO_ENCRYPT; + } +--- a/frontends/sfe/ecm_sfe_ported_ipv6.c ++++ b/frontends/sfe/ecm_sfe_ported_ipv6.c +@@ -47,7 +47,6 @@ + #include + #include + #include +-#include + #include + #include + #include +@@ -1826,7 +1825,7 @@ unsigned int ecm_sfe_ported_ipv6_process + /* + * Deny acceleration for L2TP-over-UDP tunnel + */ +- if ((in_dev->priv_flags & IFF_PPP_L2TPV2) && ppp_is_xmit_locked(in_dev)) { ++ if ((in_dev->priv_flags_qca_ecm & IFF_QCA_ECM_PPP_L2TPV2) && ppp_is_xmit_locked(in_dev)) { + DEBUG_TRACE("Skip packets for L2TP tunnel in skb %p\n", skb); + can_accel = false; + } +@@ -1958,7 +1957,7 @@ unsigned int ecm_sfe_ported_ipv6_process + /* + * Packet has been decrypted by ipsec, mark it in connection. + */ +- if (unlikely(skb->sp)) { ++ if (unlikely(skb_ext_exist(skb, SKB_EXT_SEC_PATH))) { + ((struct ecm_sfe_ported_ipv6_connection_instance *)feci)->flow_ipsec_state = ECM_SFE_IPSEC_STATE_WAS_DECRYPTED; + ((struct ecm_sfe_ported_ipv6_connection_instance *)feci)->return_ipsec_state = ECM_SFE_IPSEC_STATE_TO_ENCRYPT; + } diff --git a/qaa/nss/qca-nss-ecm/patches/101-Fix_Kern_Panic_on_UDP_CONNTRACK.patch b/qaa/nss/qca-nss-ecm/patches/101-Fix_Kern_Panic_on_UDP_CONNTRACK.patch new file mode 100644 index 000000000..6633f72b4 --- /dev/null +++ b/qaa/nss/qca-nss-ecm/patches/101-Fix_Kern_Panic_on_UDP_CONNTRACK.patch @@ -0,0 +1,60 @@ +diff --git a/frontends/nss/ecm_nss_ipv4.c b/frontends/nss/ecm_nss_ipv4.c +index 1ce4b61..29e70ba 100644 +--- a/frontends/nss/ecm_nss_ipv4.c ++++ b/frontends/nss/ecm_nss_ipv4.c +@@ -2171,6 +2171,10 @@ sync_conntrack: + + timeouts = nf_ct_timeout_lookup(ct); + ++ /* Copy of udp_get_timeouts in kernel */ ++ if (!timeouts) ++ timeouts = nf_udp_pernet(nf_ct_net(ct))->timeouts; ++ + spin_lock_bh(&ct->lock); + ct->timeout = jiffies + timeouts[UDP_CT_REPLIED]; + spin_unlock_bh(&ct->lock); +diff --git a/frontends/nss/ecm_nss_ipv6.c b/frontends/nss/ecm_nss_ipv6.c +index 2adc5ec..08253b6 100644 +--- a/frontends/nss/ecm_nss_ipv6.c ++++ b/frontends/nss/ecm_nss_ipv6.c +@@ -1883,6 +1883,10 @@ sync_conntrack: + + timeouts = nf_ct_timeout_lookup(ct); + ++ /* Copy of udp_get_timeouts in kernel */ ++ if (!timeouts) ++ timeouts = nf_udp_pernet(nf_ct_net(ct))->timeouts; ++ + spin_lock_bh(&ct->lock); + ct->timeout = jiffies + timeouts[UDP_CT_REPLIED]; + spin_unlock_bh(&ct->lock); +diff --git a/frontends/sfe/ecm_sfe_ipv4.c b/frontends/sfe/ecm_sfe_ipv4.c +index 7cfe4fc..8f525ee 100644 +--- a/frontends/sfe/ecm_sfe_ipv4.c ++++ b/frontends/sfe/ecm_sfe_ipv4.c +@@ -1608,6 +1608,10 @@ sync_conntrack: + + timeouts = nf_ct_timeout_lookup(ct); + ++ /* Copy of udp_get_timeouts in kernel */ ++ if (!timeouts) ++ timeouts = nf_udp_pernet(nf_ct_net(ct))->timeouts; ++ + spin_lock_bh(&ct->lock); + ct->timeout = jiffies + timeouts[UDP_CT_REPLIED]; + spin_unlock_bh(&ct->lock); +diff --git a/frontends/sfe/ecm_sfe_ipv6.c b/frontends/sfe/ecm_sfe_ipv6.c +index dfde309..47c531a 100644 +--- a/frontends/sfe/ecm_sfe_ipv6.c ++++ b/frontends/sfe/ecm_sfe_ipv6.c +@@ -1321,6 +1321,10 @@ sync_conntrack: + + timeouts = nf_ct_timeout_lookup(ct); + ++ /* Copy of udp_get_timeouts in kernel */ ++ if (!timeouts) ++ timeouts = nf_udp_pernet(nf_ct_net(ct))->timeouts; ++ + spin_lock_bh(&ct->lock); + ct->timeout = jiffies + timeouts[UDP_CT_REPLIED]; + spin_unlock_bh(&ct->lock); diff --git a/qaa/nss/qca-nss-ecm/patches/200-resolve-high-load.patch b/qaa/nss/qca-nss-ecm/patches/200-resolve-high-load.patch new file mode 100644 index 000000000..2f39d2770 --- /dev/null +++ b/qaa/nss/qca-nss-ecm/patches/200-resolve-high-load.patch @@ -0,0 +1,44 @@ +The sync update work queue tasks is calling uninterruptible sleep function, which is +causing high CPU load. Changed to interruptible sleep function. The stats update +task should be interruptible. + +--- a/frontends/nss/ecm_nss_ipv4.c ++++ b.frontends/nss/ecm_nss_ipv4.c +@@ -2411,7 +2411,7 @@ static void ecm_nss_ipv4_stats_sync_req_ + } + spin_unlock_bh(&ecm_nss_ipv4_lock); + +- usleep_range(ECM_NSS_IPV4_STATS_SYNC_UDELAY - 100, ECM_NSS_IPV4_STATS_SYNC_UDELAY); ++ msleep_interruptible(ECM_NSS_IPV4_STATS_SYNC_UDELAY / 1000); + + /* + * If index is 0, we are starting a new round, but if we still have time remain +@@ -2425,7 +2425,7 @@ static void ecm_nss_ipv4_stats_sync_req_ + } + + if (ecm_nss_ipv4_next_req_time > current_jiffies) { +- msleep(jiffies_to_msecs(ecm_nss_ipv4_next_req_time - current_jiffies)); ++ msleep_interruptible(jiffies_to_msecs(ecm_nss_ipv4_next_req_time - current_jiffies)); + } + ecm_nss_ipv4_roll_check_jiffies = jiffies; + ecm_nss_ipv4_next_req_time = ecm_nss_ipv4_roll_check_jiffies + ECM_NSS_IPV4_STATS_SYNC_PERIOD; +--- a/frontends/nss/ecm_nss_ipv6.c ++++ b.frontends/nss/ecm_nss_ipv6.c +@@ -2128,7 +2128,7 @@ static void ecm_nss_ipv6_stats_sync_req_ + } + spin_unlock_bh(&ecm_nss_ipv6_lock); + +- usleep_range(ECM_NSS_IPV6_STATS_SYNC_UDELAY - 100, ECM_NSS_IPV6_STATS_SYNC_UDELAY); ++ msleep_interruptible(ECM_NSS_IPV6_STATS_SYNC_UDELAY / 1000); + + /* + * If index is 0, we are starting a new round, but if we still have time remain +@@ -2142,7 +2142,7 @@ static void ecm_nss_ipv6_stats_sync_req_ + } + + if (ecm_nss_ipv6_next_req_time > current_jiffies) { +- msleep(jiffies_to_msecs(ecm_nss_ipv6_next_req_time - current_jiffies)); ++ msleep_interruptible(jiffies_to_msecs(ecm_nss_ipv6_next_req_time - current_jiffies)); + } + ecm_nss_ipv6_roll_check_jiffies = jiffies; + ecm_nss_ipv6_next_req_time = ecm_nss_ipv6_roll_check_jiffies + ECM_NSS_IPV6_STATS_SYNC_PERIOD; diff --git a/qaa/nss/qca-nss-ecm/patches/203-rework-nfct-notification.patch b/qaa/nss/qca-nss-ecm/patches/203-rework-nfct-notification.patch new file mode 100644 index 000000000..a0e09c1fa --- /dev/null +++ b/qaa/nss/qca-nss-ecm/patches/203-rework-nfct-notification.patch @@ -0,0 +1,20 @@ +--- a/ecm_conntrack_notifier.c ++++ b/ecm_conntrack_notifier.c +@@ -411,7 +411,7 @@ int ecm_conntrack_notifier_init(struct d + /* + * Eventing subsystem is available so we register a notifier hook to get fast notifications of expired connections + */ +- result = nf_conntrack_register_notifier(&init_net, &ecm_conntrack_notifier); ++ result = nf_conntrack_register_chain_notifier(&init_net, &ecm_conntrack_notifier); + if (result < 0) { + DEBUG_ERROR("Can't register nf notifier hook.\n"); + debugfs_remove_recursive(ecm_conntrack_notifier_dentry); +@@ -430,7 +430,7 @@ void ecm_conntrack_notifier_exit(void) + { + DEBUG_INFO("ECM Conntrack Notifier exit\n"); + #ifdef CONFIG_NF_CONNTRACK_EVENTS +- nf_conntrack_unregister_notifier(&init_net, &ecm_conntrack_notifier); ++ nf_conntrack_unregister_chain_notifier(&init_net, &ecm_conntrack_notifier); + #endif + /* + * Remove the debugfs files recursively. diff --git a/qaa/nss/qca-nss-ecm/patches/400-Check-TCP_UDP-conntrack-state-earlier.patch b/qaa/nss/qca-nss-ecm/patches/400-Check-TCP_UDP-conntrack-state-earlier.patch new file mode 100644 index 000000000..b7882c1b3 --- /dev/null +++ b/qaa/nss/qca-nss-ecm/patches/400-Check-TCP_UDP-conntrack-state-earlier.patch @@ -0,0 +1,236 @@ +From 90cace88a342e77ee8ca1e961cf7b7a7930d4c89 Mon Sep 17 00:00:00 2001 +From: Murat Sezgin +Date: Mon, 9 Mar 2020 12:51:03 -0700 +Subject: [qca-nss-ecm] Check TCP/UDP conntrack state earlier + +Check the conntrack state before processing the flow +and adding it to the database. The unconfirmed +connections can be changed after the confirmation. + +Changed the TCP tracker connection state matrix to set the +state of the connection as ESTABLISHED when any of the src or +dest side is set as ESTABLISHED. With this change ECM will not +handle the SYN and SYN-ACK packets of the TCP handshake. Only the +ACK and FIN flaged packets will be used during the creation and +closing the connection respectively. + +Signed-off-by: Murat Sezgin +Change-Id: I3e0a58d604df4c6a85478ca9c05f24d50cd8c894 +--- + ecm_classifier_default.c | 36 ++++++++---------------------------- + ecm_tracker_tcp.c | 4 ++-- + frontends/nss/ecm_nss_ported_ipv4.c | 17 +++++++++++++++++ + frontends/nss/ecm_nss_ported_ipv6.c | 17 +++++++++++++++++ + frontends/sfe/ecm_sfe_ported_ipv4.c | 17 +++++++++++++++++ + frontends/sfe/ecm_sfe_ported_ipv6.c | 17 +++++++++++++++++ + 6 files changed, 78 insertions(+), 30 deletions(-) + +diff --git a/ecm_classifier_default.c b/ecm_classifier_default.c +index 22c4bec..d04cdfa 100644 +--- a/ecm_classifier_default.c ++++ b/ecm_classifier_default.c +@@ -1,6 +1,6 @@ + /* + ************************************************************************** +- * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. ++ * Copyright (c) 2014-2016, 2020, The Linux Foundation. All rights reserved. + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. +@@ -285,12 +285,12 @@ static void ecm_classifier_default_process(struct ecm_classifier_instance *aci, + } + + /* +- * Check the TCP connection state. ++ * Check the TCP connection state, when the ct is NULL. ++ * ct valid case was already checked in the ecm_nss{sfe}_ported_ipv4{6}_process functions. + * If we are not established then we deny acceleration. +- * Take lead from conntrack if exists. + */ + ct = nf_ct_get(skb, &ctinfo); +- if (ct == NULL) { ++ if (!ct) { + DEBUG_TRACE("%p: No Conntrack found for packet, using ECM tracker state\n", cdii); + if (unlikely(prevailing_state != ECM_TRACKER_CONNECTION_STATE_ESTABLISHED)) { + cdii->process_response.accel_mode = ECM_CLASSIFIER_ACCELERATION_MODE_NO; +@@ -298,29 +298,10 @@ static void ecm_classifier_default_process(struct ecm_classifier_instance *aci, + } + } else { + /* +- * Unconfirmed connection may be dropped by Linux at the final step, +- * So we don't allow acceleration for the unconfirmed connections. +- */ +- if (!nf_ct_is_confirmed(ct)) { +- DEBUG_TRACE("%p: Unconfirmed connection\n", ct); +- cdii->process_response.accel_mode = ECM_CLASSIFIER_ACCELERATION_MODE_NO; +- goto return_response; +- } +- +- /* +- * Don't try to manage a non-established connection. +- */ +- if (!test_bit(IPS_ASSURED_BIT, &ct->status)) { +- DEBUG_TRACE("%p: Non-established connection\n", ct); +- cdii->process_response.accel_mode = ECM_CLASSIFIER_ACCELERATION_MODE_NO; +- goto return_response; +- } +- +- /* +- * If the connection is shutting down do not manage it. +- * state can not be SYN_SENT, SYN_RECV because connection is assured +- * Not managed states: FIN_WAIT, CLOSE_WAIT, LAST_ACK, TIME_WAIT, CLOSE. +- */ ++ * If the connection is shutting down do not manage it. ++ * state can not be SYN_SENT, SYN_RECV because connection is assured ++ * Not managed states: FIN_WAIT, CLOSE_WAIT, LAST_ACK, TIME_WAIT, CLOSE. ++ */ + spin_lock_bh(&ct->lock); + if (ct->proto.tcp.state != TCP_CONNTRACK_ESTABLISHED) { + spin_unlock_bh(&ct->lock); +@@ -333,7 +314,6 @@ static void ecm_classifier_default_process(struct ecm_classifier_instance *aci, + + return_response: + ; +- + /* + * Return the process response + */ +diff --git a/ecm_tracker_tcp.c b/ecm_tracker_tcp.c +index f073c36..e5b327a 100644 +--- a/ecm_tracker_tcp.c ++++ b/ecm_tracker_tcp.c +@@ -257,9 +257,9 @@ static DEFINE_SPINLOCK(ecm_tracker_tcp_lock); /* Global lock for the tracker gl + */ + static ecm_tracker_connection_state_t ecm_tracker_tcp_connection_state_matrix[ECM_TRACKER_SENDER_STATE_MAX][ECM_TRACKER_SENDER_STATE_MAX] = + { /* Unknown Establishing Established Closing Closed Fault */ +- /* Unknown */ {ECM_TRACKER_CONNECTION_STATE_ESTABLISHING, ECM_TRACKER_CONNECTION_STATE_ESTABLISHING, ECM_TRACKER_CONNECTION_STATE_ESTABLISHING, ECM_TRACKER_CONNECTION_STATE_FAULT, ECM_TRACKER_CONNECTION_STATE_FAULT, ECM_TRACKER_CONNECTION_STATE_FAULT}, ++ /* Unknown */ {ECM_TRACKER_CONNECTION_STATE_ESTABLISHING, ECM_TRACKER_CONNECTION_STATE_ESTABLISHING, ECM_TRACKER_CONNECTION_STATE_ESTABLISHED, ECM_TRACKER_CONNECTION_STATE_FAULT, ECM_TRACKER_CONNECTION_STATE_FAULT, ECM_TRACKER_CONNECTION_STATE_FAULT}, + /* Establishing */ {ECM_TRACKER_CONNECTION_STATE_ESTABLISHING, ECM_TRACKER_CONNECTION_STATE_ESTABLISHING, ECM_TRACKER_CONNECTION_STATE_ESTABLISHING, ECM_TRACKER_CONNECTION_STATE_FAULT, ECM_TRACKER_CONNECTION_STATE_FAULT, ECM_TRACKER_CONNECTION_STATE_FAULT}, +- /* Established */ {ECM_TRACKER_CONNECTION_STATE_ESTABLISHING, ECM_TRACKER_CONNECTION_STATE_ESTABLISHING, ECM_TRACKER_CONNECTION_STATE_ESTABLISHED, ECM_TRACKER_CONNECTION_STATE_CLOSING, ECM_TRACKER_CONNECTION_STATE_CLOSING, ECM_TRACKER_CONNECTION_STATE_FAULT}, ++ /* Established */ {ECM_TRACKER_CONNECTION_STATE_ESTABLISHED, ECM_TRACKER_CONNECTION_STATE_ESTABLISHING, ECM_TRACKER_CONNECTION_STATE_ESTABLISHED, ECM_TRACKER_CONNECTION_STATE_CLOSING, ECM_TRACKER_CONNECTION_STATE_CLOSING, ECM_TRACKER_CONNECTION_STATE_FAULT}, + /* Closing */ {ECM_TRACKER_CONNECTION_STATE_FAULT, ECM_TRACKER_CONNECTION_STATE_FAULT, ECM_TRACKER_CONNECTION_STATE_CLOSING, ECM_TRACKER_CONNECTION_STATE_CLOSING, ECM_TRACKER_CONNECTION_STATE_CLOSING, ECM_TRACKER_CONNECTION_STATE_FAULT}, + /* Closed */ {ECM_TRACKER_CONNECTION_STATE_FAULT, ECM_TRACKER_CONNECTION_STATE_FAULT, ECM_TRACKER_CONNECTION_STATE_CLOSING, ECM_TRACKER_CONNECTION_STATE_CLOSING, ECM_TRACKER_CONNECTION_STATE_CLOSED, ECM_TRACKER_CONNECTION_STATE_FAULT}, + /* Fault */ {ECM_TRACKER_CONNECTION_STATE_FAULT, ECM_TRACKER_CONNECTION_STATE_FAULT, ECM_TRACKER_CONNECTION_STATE_FAULT, ECM_TRACKER_CONNECTION_STATE_FAULT, ECM_TRACKER_CONNECTION_STATE_FAULT, ECM_TRACKER_CONNECTION_STATE_FAULT}, +diff --git a/frontends/nss/ecm_nss_ported_ipv4.c b/frontends/nss/ecm_nss_ported_ipv4.c +index 1435ec0..34c056f 100644 +--- a/frontends/nss/ecm_nss_ported_ipv4.c ++++ b/frontends/nss/ecm_nss_ported_ipv4.c +@@ -2002,8 +2002,25 @@ unsigned int ecm_nss_ported_ipv4_process(struct net_device *out_dev, struct net_ + int protocol = (int)orig_tuple->dst.protonum; + __be16 *layer4hdr = NULL; + ++ /* ++ * Unconfirmed connection may be dropped by Linux at the final step, ++ * So we don't allow acceleration for the unconfirmed connections. ++ */ ++ if (likely(ct) && !nf_ct_is_confirmed(ct)) { ++ DEBUG_WARN("%p: Unconfirmed connection\n", ct); ++ return NF_ACCEPT; ++ } ++ + if (protocol == IPPROTO_TCP) { + /* ++ * Don't try to manage a non-established connection. ++ */ ++ if (likely(ct) && !test_bit(IPS_ASSURED_BIT, &ct->status)) { ++ DEBUG_WARN("%p: Non-established TCP connection\n", ct); ++ return NF_ACCEPT; ++ } ++ ++ /* + * Extract TCP header to obtain port information + */ + tcp_hdr = ecm_tracker_tcp_check_header_and_read(skb, iph, &tcp_hdr_buff); +diff --git a/frontends/nss/ecm_nss_ported_ipv6.c b/frontends/nss/ecm_nss_ported_ipv6.c +index 4c154a6..bd6349b 100644 +--- a/frontends/nss/ecm_nss_ported_ipv6.c ++++ b/frontends/nss/ecm_nss_ported_ipv6.c +@@ -1914,8 +1914,25 @@ unsigned int ecm_nss_ported_ipv6_process(struct net_device *out_dev, + int protocol = (int)orig_tuple->dst.protonum; + __be16 *layer4hdr = NULL; + ++ /* ++ * Unconfirmed connection may be dropped by Linux at the final step, ++ * So we don't allow acceleration for the unconfirmed connections. ++ */ ++ if (likely(ct) && !nf_ct_is_confirmed(ct)) { ++ DEBUG_WARN("%p: Unconfirmed connection\n", ct); ++ return NF_ACCEPT; ++ } ++ + if (protocol == IPPROTO_TCP) { + /* ++ * Don't try to manage a non-established connection. ++ */ ++ if (likely(ct) && !test_bit(IPS_ASSURED_BIT, &ct->status)) { ++ DEBUG_WARN("%p: Non-established TCP connection\n", ct); ++ return NF_ACCEPT; ++ } ++ ++ /* + * Extract TCP header to obtain port information + */ + tcp_hdr = ecm_tracker_tcp_check_header_and_read(skb, iph, &tcp_hdr_buff); +diff --git a/frontends/sfe/ecm_sfe_ported_ipv4.c b/frontends/sfe/ecm_sfe_ported_ipv4.c +index e034cde..df1ce57 100644 +--- a/frontends/sfe/ecm_sfe_ported_ipv4.c ++++ b/frontends/sfe/ecm_sfe_ported_ipv4.c +@@ -1805,8 +1805,25 @@ unsigned int ecm_sfe_ported_ipv4_process(struct net_device *out_dev, struct net_ + int protocol = (int)orig_tuple->dst.protonum; + __be16 *layer4hdr = NULL; + ++ /* ++ * Unconfirmed connection may be dropped by Linux at the final step, ++ * So we don't allow acceleration for the unconfirmed connections. ++ */ ++ if (likely(ct) && !nf_ct_is_confirmed(ct)) { ++ DEBUG_WARN("%p: Unconfirmed connection\n", ct); ++ return NF_ACCEPT; ++ } ++ + if (protocol == IPPROTO_TCP) { + /* ++ * Don't try to manage a non-established connection. ++ */ ++ if (likely(ct) && !test_bit(IPS_ASSURED_BIT, &ct->status)) { ++ DEBUG_WARN("%p: Non-established TCP connection\n", ct); ++ return NF_ACCEPT; ++ } ++ ++ /* + * Extract TCP header to obtain port information + */ + tcp_hdr = ecm_tracker_tcp_check_header_and_read(skb, iph, &tcp_hdr_buff); +diff --git a/frontends/sfe/ecm_sfe_ported_ipv6.c b/frontends/sfe/ecm_sfe_ported_ipv6.c +index 6ac05ad..657a1c7 100644 +--- a/frontends/sfe/ecm_sfe_ported_ipv6.c ++++ b/frontends/sfe/ecm_sfe_ported_ipv6.c +@@ -1746,8 +1746,25 @@ unsigned int ecm_sfe_ported_ipv6_process(struct net_device *out_dev, + int protocol = (int)orig_tuple->dst.protonum; + __be16 *layer4hdr = NULL; + ++ /* ++ * Unconfirmed connection may be dropped by Linux at the final step, ++ * So we don't allow acceleration for the unconfirmed connections. ++ */ ++ if (likely(ct) && !nf_ct_is_confirmed(ct)) { ++ DEBUG_WARN("%p: Unconfirmed connection\n", ct); ++ return NF_ACCEPT; ++ } ++ + if (protocol == IPPROTO_TCP) { + /* ++ * Don't try to manage a non-established connection. ++ */ ++ if (likely(ct) && !test_bit(IPS_ASSURED_BIT, &ct->status)) { ++ DEBUG_WARN("%p: Non-established TCP connection\n", ct); ++ return NF_ACCEPT; ++ } ++ ++ /* + * Extract TCP header to obtain port information + */ + tcp_hdr = ecm_tracker_tcp_check_header_and_read(skb, iph, &tcp_hdr_buff); +-- +cgit v1.1 + diff --git a/qaa/nss/qca-nss-ecm/patches/401-Fix-NSS-stats-request-roll-over-issue.patch b/qaa/nss/qca-nss-ecm/patches/401-Fix-NSS-stats-request-roll-over-issue.patch new file mode 100644 index 000000000..217054bb7 --- /dev/null +++ b/qaa/nss/qca-nss-ecm/patches/401-Fix-NSS-stats-request-roll-over-issue.patch @@ -0,0 +1,52 @@ +From 9ad19ffdcfdf77baf3abd4fcc933fd3dc8e791a5 Mon Sep 17 00:00:00 2001 +From: Murat Sezgin +Date: Sat, 20 Jun 2020 09:41:01 -0700 +Subject: [qca-nss-ecm] Fix NSS stats request roll over issue + +Use the correct timer API to check the next request time +when jiffies wrap happens. + +Signed-off-by: Murat Sezgin +Change-Id: I18646d28df7e17daeff2986dfe4bd73866d47668 +--- + frontends/nss/ecm_nss_ipv4.c | 4 ++-- + frontends/nss/ecm_nss_ipv6.c | 4 ++-- + 2 files changed, 4 insertions(+), 4 deletions(-) + +diff --git a/frontends/nss/ecm_nss_ipv4.c b/frontends/nss/ecm_nss_ipv4.c +index 3eaf5d8..80e1aee 100644 +--- a/frontends/nss/ecm_nss_ipv4.c ++++ b/frontends/nss/ecm_nss_ipv4.c +@@ -2421,10 +2421,10 @@ static void ecm_nss_ipv4_stats_sync_req_work(struct work_struct *work) + current_jiffies = jiffies; + + if (time_is_after_jiffies(ecm_nss_ipv4_roll_check_jiffies)) { +- ecm_nss_ipv4_next_req_time = 0; ++ ecm_nss_ipv4_next_req_time = jiffies + ECM_NSS_IPV4_STATS_SYNC_PERIOD; + } + +- if (ecm_nss_ipv4_next_req_time > current_jiffies) { ++ if (time_after(ecm_nss_ipv4_next_req_time, current_jiffies)) { + msleep_interruptible(jiffies_to_msecs(ecm_nss_ipv4_next_req_time - current_jiffies)); + } + ecm_nss_ipv4_roll_check_jiffies = jiffies; +diff --git a/frontends/nss/ecm_nss_ipv6.c b/frontends/nss/ecm_nss_ipv6.c +index 288dc55..483421e 100644 +--- a/frontends/nss/ecm_nss_ipv6.c ++++ b/frontends/nss/ecm_nss_ipv6.c +@@ -2135,10 +2135,10 @@ static void ecm_nss_ipv6_stats_sync_req_work(struct work_struct *work) + current_jiffies = jiffies; + + if (time_is_after_jiffies(ecm_nss_ipv6_roll_check_jiffies)) { +- ecm_nss_ipv6_next_req_time = 0; ++ ecm_nss_ipv6_next_req_time = jiffies + ECM_NSS_IPV6_STATS_SYNC_PERIOD; + } + +- if (ecm_nss_ipv6_next_req_time > current_jiffies) { ++ if (time_after(ecm_nss_ipv6_next_req_time, current_jiffies)) { + msleep_interruptible(jiffies_to_msecs(ecm_nss_ipv6_next_req_time - current_jiffies)); + } + ecm_nss_ipv6_roll_check_jiffies = jiffies; +-- +cgit v1.1 + diff --git a/qaa/nss/qca-nss-ecm/patches/401-Fix-for-ref-leak-during-multicast.patch b/qaa/nss/qca-nss-ecm/patches/401-Fix-for-ref-leak-during-multicast.patch new file mode 100644 index 000000000..e1df653b7 --- /dev/null +++ b/qaa/nss/qca-nss-ecm/patches/401-Fix-for-ref-leak-during-multicast.patch @@ -0,0 +1,112 @@ +From 4b41703a181b7187d9ff8cb744eb96d09997387c Mon Sep 17 00:00:00 2001 +From: Suman Ghosh +Date: Wed, 19 Feb 2020 15:09:19 +0530 +Subject: [qca-nss-ecm] Fix for ref leak during multicast 'to' hierarchy + creation + +Change-Id: I89df9dbe5ea054cf3b87d55ce68a751cb1d6c24f +Signed-off-by: Suman Ghosh +--- + ecm_interface.c | 34 ++++++++++++++++++++++++++++++---- + 1 file changed, 30 insertions(+), 4 deletions(-) + +diff --git a/ecm_interface.c b/ecm_interface.c +index 4f7a886..2a0ca5b 100644 +--- a/ecm_interface.c ++++ b/ecm_interface.c +@@ -3885,13 +3885,13 @@ int32_t ecm_interface_multicast_heirarchy_construct_routed(struct ecm_front_end_ + dest_dev = dev_get_by_index(&init_net, *dst_if_index); + if (!dest_dev) { + if (!src_dev_is_bridge) { +- int i; +- + /* + * If already constructed any interface heirarchies before hitting + * this error condition then Deref all interface heirarchies. + */ + if (valid_if > 0) { ++ int i; ++ + for (i = 0; i < valid_if; i++) { + ifaces = ecm_db_multicast_if_heirarchy_get(interfaces, i); + ecm_db_multicast_copy_if_heirarchy(to_list_single, ifaces); +@@ -3902,11 +3902,14 @@ int32_t ecm_interface_multicast_heirarchy_construct_routed(struct ecm_front_end_ + /* + * If valid netdev not found, Return 0 + */ ++ if (br_dev_src) { ++ dev_put(br_dev_src); ++ } ++ + return 0; + } + + dest_dev = br_dev_src; +- + } + + dest_dev_type = dest_dev->type; +@@ -3945,6 +3948,10 @@ int32_t ecm_interface_multicast_heirarchy_construct_routed(struct ecm_front_end_ + } + } + ++ if (br_dev_src && (dest_dev != br_dev_src)) { ++ dev_put(br_dev_src); ++ } ++ + dev_put(dest_dev); + return 0; + } +@@ -3972,6 +3979,10 @@ int32_t ecm_interface_multicast_heirarchy_construct_routed(struct ecm_front_end_ + ecm_db_connection_interfaces_deref(to_list_single, interface_first_base[i]); + } + ++ if (br_dev_src && (dest_dev != br_dev_src)) { ++ dev_put(br_dev_src); ++ } ++ + dev_put(dest_dev); + dev_put(mc_br_slave_dev); + return 0; +@@ -3997,6 +4008,10 @@ int32_t ecm_interface_multicast_heirarchy_construct_routed(struct ecm_front_end_ + } + } + ++ if (br_dev_src && (dest_dev != br_dev_src)) { ++ dev_put(br_dev_src); ++ } ++ + dev_put(dest_dev); + dev_put(mc_br_slave_dev); + return 0; +@@ -4032,6 +4047,10 @@ int32_t ecm_interface_multicast_heirarchy_construct_routed(struct ecm_front_end_ + } + } + ++ if (br_dev_src && (dest_dev != br_dev_src)) { ++ dev_put(br_dev_src); ++ } ++ + dev_put(dest_dev); + return 0; + } +@@ -4042,8 +4061,15 @@ int32_t ecm_interface_multicast_heirarchy_construct_routed(struct ecm_front_end_ + valid_if++; + } + +- dev_put(dest_dev); ++ if (dest_dev != br_dev_src) { ++ dev_put(dest_dev); ++ } + } ++ ++ if (br_dev_src) { ++ dev_put(br_dev_src); ++ } ++ + return total_ii_count; + } + EXPORT_SYMBOL(ecm_interface_multicast_heirarchy_construct_routed); +-- +cgit v1.1 + diff --git a/qaa/nss/qca-nss-ecm/patches/401-Fix-neighbour-solicitation-send-function.patch b/qaa/nss/qca-nss-ecm/patches/401-Fix-neighbour-solicitation-send-function.patch new file mode 100644 index 000000000..7d32d6fd5 --- /dev/null +++ b/qaa/nss/qca-nss-ecm/patches/401-Fix-neighbour-solicitation-send-function.patch @@ -0,0 +1,33 @@ +From 72e3ae508906553e7bc982bf3c0d99bb1cbe9008 Mon Sep 17 00:00:00 2001 +From: Murat Sezgin +Date: Wed, 20 Nov 2019 16:23:06 -0800 +Subject: [qca-nss-ecm] Fix neighbour solicitation send function. + +dst_ops->neigh_lookup function pointer is set to the +ip6_neigh_lookup function. This function returns an +error pointer with the ERR_PTR() macro. So, we should +check the return value of this function pointer with +the IS_ERR() macro. + +Change-Id: I188a6e53278faaa68f1854524f612efc1f7451fe +Signed-off-by: Murat Sezgin +--- + ecm_interface.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/ecm_interface.c b/ecm_interface.c +index 3f8554b..36509f0 100644 +--- a/ecm_interface.c ++++ b/ecm_interface.c +@@ -1100,7 +1100,7 @@ void ecm_interface_send_neighbour_solicitation(struct net_device *dev, ip_addr_t + #else + neigh = rt6i->dst.ops->neigh_lookup(&rt6i->dst, NULL, &dst_addr); + #endif +- if (neigh == NULL) { ++ if (IS_ERR(neigh)) { + DEBUG_TRACE("Neighbour lookup failure for destination IPv6 address " ECM_IP_ADDR_OCTAL_FMT "\n", ECM_IP_ADDR_TO_OCTAL(addr)); + dst_release(&rt6i->dst); + return; +-- +cgit v1.1 + diff --git a/qaa/nss/qca-nss-ecm/patches/402-Reference-leak-during-multicast_PPPoE-bridge.patch b/qaa/nss/qca-nss-ecm/patches/402-Reference-leak-during-multicast_PPPoE-bridge.patch new file mode 100644 index 000000000..97ce7a7e8 --- /dev/null +++ b/qaa/nss/qca-nss-ecm/patches/402-Reference-leak-during-multicast_PPPoE-bridge.patch @@ -0,0 +1,260 @@ +From 7c0610828b835b2aab96dd50ec841a3a28689112 Mon Sep 17 00:00:00 2001 +From: Suman Ghosh +Date: Mon, 16 Mar 2020 15:22:18 +0530 +Subject: [qca-nss-ecm] Reference leak during multicast + PPPoE bridge + +Signed-off-by: Suman Ghosh +Change-Id: I4472035f1bbb087e637169762ae2648c0fda792a +--- + ecm_interface.c | 136 +++++++++++++++++++++++++------------------------------- + 1 file changed, 60 insertions(+), 76 deletions(-) + +diff --git a/ecm_interface.c b/ecm_interface.c +index 1614336..c0d2357 100644 +--- a/ecm_interface.c ++++ b/ecm_interface.c +@@ -3796,6 +3796,25 @@ fail: + } + + /* ++ * ecm_interface_hierarchy_delete() ++ * Delete hierarchy of the requested interfaces. ++ */ ++static inline void ecm_interface_hierarchy_delete(struct ecm_db_iface_instance *interfaces, ++ uint32_t *interface_first_base, ++ int valid_if) ++{ ++ struct ecm_db_iface_instance *to_list_single[ECM_DB_IFACE_HEIRARCHY_MAX]; ++ struct ecm_db_iface_instance *ifaces; ++ int i; ++ ++ for (i = 0; i < valid_if; i++) { ++ ifaces = ecm_db_multicast_if_heirarchy_get(interfaces, i); ++ ecm_db_multicast_copy_if_heirarchy(to_list_single, ifaces); ++ ecm_db_connection_interfaces_deref(to_list_single, interface_first_base[i]); ++ } ++} ++ ++/* + * ecm_interface_multicast_heirarchy_construct_routed() + * Create destination interface heirarchy for a routed multicast connectiona + * +@@ -3816,7 +3835,6 @@ int32_t ecm_interface_multicast_heirarchy_construct_routed(struct ecm_front_end_ + uint32_t *interface_first_base, bool mfc_update, + __be16 *layer4hdr, struct sk_buff *skb) + { +- struct ecm_db_iface_instance *to_list_single[ECM_DB_IFACE_HEIRARCHY_MAX]; + struct ecm_db_iface_instance *ifaces; + struct net_device *dest_dev = NULL; + struct net_device *br_dev_src = NULL; +@@ -3829,7 +3847,7 @@ int32_t ecm_interface_multicast_heirarchy_construct_routed(struct ecm_front_end_ + int if_index; + int ii_cnt; + int total_ii_count = 0; +- bool src_dev_is_bridge = false; ++ bool src_dev_is_bridge = false, dest_dev_is_br_dev_src = false; + + DEBUG_TRACE("Construct interface heirarchy for dest_addr: " ECM_IP_ADDR_DOT_FMT " src_addr: " ECM_IP_ADDR_DOT_FMT "total destination ifs %d\n", + ECM_IP_ADDR_TO_DOT(packet_dest_addr), ECM_IP_ADDR_TO_DOT(packet_src_addr), max_if); +@@ -3876,6 +3894,7 @@ int32_t ecm_interface_multicast_heirarchy_construct_routed(struct ecm_front_end_ + continue; + } + ++ dest_dev_is_br_dev_src = false; + dest_dev = dev_get_by_index(&init_net, *dst_if_index); + if (!dest_dev) { + if (!src_dev_is_bridge) { +@@ -3884,26 +3903,23 @@ int32_t ecm_interface_multicast_heirarchy_construct_routed(struct ecm_front_end_ + * this error condition then Deref all interface heirarchies. + */ + if (valid_if > 0) { +- int i; +- +- for (i = 0; i < valid_if; i++) { +- ifaces = ecm_db_multicast_if_heirarchy_get(interfaces, i); +- ecm_db_multicast_copy_if_heirarchy(to_list_single, ifaces); +- ecm_db_connection_interfaces_deref(to_list_single, interface_first_base[i]); +- } ++ ecm_interface_hierarchy_delete(interfaces, interface_first_base, valid_if); + } + +- /* +- * If valid netdev not found, Return 0 +- */ +- if (br_dev_src) { +- dev_put(br_dev_src); +- } +- +- return 0; ++ goto fail1; + } + + dest_dev = br_dev_src; ++ ++ /* ++ * In some cases when WAN interface is added to bridge and traffic is downstream, ++ * the bridge device is part of the destination list from MFC, and at the same time ++ * 'src_dev_is_bridge' will be true as well. In such cases we will need to release ++ * the hold on the bridge device separately for dest_dev and br_dev_src. ++ * Setting this flag to true indicates that this is not the case, ++ * and that releasing the hold once is enough ++ */ ++ dest_dev_is_br_dev_src = true; + } + + dest_dev_type = dest_dev->type; +@@ -3927,7 +3943,6 @@ int32_t ecm_interface_multicast_heirarchy_construct_routed(struct ecm_front_end_ + } + + if ((if_num < 0) || (if_num > ECM_DB_MULTICAST_IF_MAX)) { +- int i; + DEBUG_WARN("MCS is not ready\n"); + + /* +@@ -3935,19 +3950,10 @@ int32_t ecm_interface_multicast_heirarchy_construct_routed(struct ecm_front_end_ + * this error condition then Deref all interface heirarchies. + */ + if (valid_if > 0) { +- for (i = 0; i < valid_if; i++) { +- ifaces = ecm_db_multicast_if_heirarchy_get(interfaces, i); +- ecm_db_multicast_copy_if_heirarchy(to_list_single, ifaces); +- ecm_db_connection_interfaces_deref(to_list_single, interface_first_base[i]); +- } ++ ecm_interface_hierarchy_delete(interfaces, interface_first_base, valid_if); + } + +- if (br_dev_src && (dest_dev != br_dev_src)) { +- dev_put(br_dev_src); +- } +- +- dev_put(dest_dev); +- return 0; ++ goto fail2; + } + + if (in_dev && !mfc_update) { +@@ -3955,34 +3961,20 @@ int32_t ecm_interface_multicast_heirarchy_construct_routed(struct ecm_front_end_ + } + + for (br_if = 0; br_if < if_num; br_if++) { ++ int total_if = valid_if + br_if; ++ + mc_br_slave_dev = dev_get_by_index(&init_net, mc_dst_if_index[br_if]); + if (!mc_br_slave_dev) { + continue; + } + +- if ((valid_if + br_if) > ECM_DB_MULTICAST_IF_MAX) { +- int i; +- +- /* +- * If already constructed any interface heirarchies before hitting +- * this error condition then Deref all interface heirarchies. +- */ +- for (i = 0; i < (valid_if + br_if); i++) { +- ifaces = ecm_db_multicast_if_heirarchy_get(interfaces, i); +- ecm_db_multicast_copy_if_heirarchy(to_list_single, ifaces); +- ecm_db_connection_interfaces_deref(to_list_single, interface_first_base[i]); +- } +- +- if (br_dev_src && (dest_dev != br_dev_src)) { +- dev_put(br_dev_src); +- } +- +- dev_put(dest_dev); ++ if (total_if > ECM_DB_MULTICAST_IF_MAX) { ++ ecm_interface_hierarchy_delete(interfaces, interface_first_base, total_if); + dev_put(mc_br_slave_dev); +- return 0; ++ goto fail2; + } + +- ifaces = ecm_db_multicast_if_heirarchy_get(interfaces, valid_if + br_if); ++ ifaces = ecm_db_multicast_if_heirarchy_get(interfaces, total_if); + /* + * Construct a single interface heirarchy of a multicast dev. + */ +@@ -3993,25 +3985,15 @@ int32_t ecm_interface_multicast_heirarchy_construct_routed(struct ecm_front_end_ + * If already constructed any interface heirarchies before hitting + * this error condition then Deref all interface heirarchies. + */ +- if ((valid_if + br_if) > 0) { +- int i; +- for (i = 0; i < (valid_if + br_if); i++) { +- ifaces = ecm_db_multicast_if_heirarchy_get(interfaces, i); +- ecm_db_multicast_copy_if_heirarchy(to_list_single, ifaces); +- ecm_db_connection_interfaces_deref(to_list_single, interface_first_base[i]); +- } +- } +- +- if (br_dev_src && (dest_dev != br_dev_src)) { +- dev_put(br_dev_src); ++ if (total_if > 0) { ++ ecm_interface_hierarchy_delete(interfaces, interface_first_base, total_if); + } + +- dev_put(dest_dev); + dev_put(mc_br_slave_dev); +- return 0; ++ goto fail2; + } + +- interface_first = ecm_db_multicast_if_first_get_at_index(interface_first_base, (valid_if + br_if)); ++ interface_first = ecm_db_multicast_if_first_get_at_index(interface_first_base, total_if); + *interface_first = ii_cnt; + total_ii_count += ii_cnt; + dev_put(mc_br_slave_dev); +@@ -4033,20 +4015,10 @@ int32_t ecm_interface_multicast_heirarchy_construct_routed(struct ecm_front_end_ + * this error condition then Deref all interface heirarchies. + */ + if (valid_if > 0) { +- int i; +- for (i = 0; i < valid_if; i++) { +- ifaces = ecm_db_multicast_if_heirarchy_get(interfaces, i); +- ecm_db_multicast_copy_if_heirarchy(to_list_single, ifaces); +- ecm_db_connection_interfaces_deref(to_list_single, interface_first_base[i]); +- } +- } +- +- if (br_dev_src && (dest_dev != br_dev_src)) { +- dev_put(br_dev_src); ++ ecm_interface_hierarchy_delete(interfaces, interface_first_base, valid_if); + } + +- dev_put(dest_dev); +- return 0; ++ goto fail2; + } + + interface_first = ecm_db_multicast_if_first_get_at_index(interface_first_base, valid_if); +@@ -4055,7 +4027,7 @@ int32_t ecm_interface_multicast_heirarchy_construct_routed(struct ecm_front_end_ + valid_if++; + } + +- if (dest_dev != br_dev_src) { ++ if (!dest_dev_is_br_dev_src) { + dev_put(dest_dev); + } + } +@@ -4065,6 +4037,18 @@ int32_t ecm_interface_multicast_heirarchy_construct_routed(struct ecm_front_end_ + } + + return total_ii_count; ++ ++fail2: ++ if (!dest_dev_is_br_dev_src) { ++ dev_put(dest_dev); ++ } ++ ++fail1: ++ if (br_dev_src) { ++ dev_put(br_dev_src); ++ } ++ ++ return 0; + } + EXPORT_SYMBOL(ecm_interface_multicast_heirarchy_construct_routed); + +-- +cgit v1.1 + diff --git a/qaa/nss/qca-nss-ecm/patches/403-Access-global-accelerated-count-under-lock.patch b/qaa/nss/qca-nss-ecm/patches/403-Access-global-accelerated-count-under-lock.patch new file mode 100644 index 000000000..d458e1134 --- /dev/null +++ b/qaa/nss/qca-nss-ecm/patches/403-Access-global-accelerated-count-under-lock.patch @@ -0,0 +1,59 @@ +From 65a49ebd1bd12b9952dfa214de0a2da43ba2abed Mon Sep 17 00:00:00 2001 +From: Bhaskar Valaboju +Date: Tue, 13 Aug 2019 14:21:03 +0530 +Subject: [qca-nss-ecm]: Access global ipv4/ipv6 accelerated count under lock + +Flow accelerated count maintained as global variables are accessed +in multiple kernel contexts. These counters are updated under lock, +but read without lock. Read is in kernel thread context (workqueue) +and sometimes it is taking stale entry (0) and doesn't change. +Lock is added to read correct value. + +Change-Id: I74cf27fe5097c6ae7dfcc06319762a8a322d79a3 +Signed-off-by: Bhaskar Valaboju +--- + frontends/nss/ecm_nss_ipv4.c | 3 +++ + frontends/nss/ecm_nss_ipv6.c | 3 +++ + 2 files changed, 6 insertions(+) + +(limited to 'frontends') + +diff --git a/frontends/nss/ecm_nss_ipv4.c b/frontends/nss/ecm_nss_ipv4.c +index afd660e..4e66cdf 100644 +--- a/frontends/nss/ecm_nss_ipv4.c ++++ b/frontends/nss/ecm_nss_ipv4.c +@@ -2288,10 +2288,13 @@ static void ecm_nss_ipv4_stats_sync_req_work(struct work_struct *work) + int retry = 3; + unsigned long int current_jiffies; + ++ spin_lock_bh(&ecm_nss_ipv4_lock); + if (ecm_nss_ipv4_accelerated_count == 0) { ++ spin_unlock_bh(&ecm_nss_ipv4_lock); + DEBUG_TRACE("There is no accelerated IPv4 connection\n"); + goto reschedule; + } ++ spin_unlock_bh(&ecm_nss_ipv4_lock); + + usleep_range(ECM_NSS_IPV4_STATS_SYNC_UDELAY - 100, ECM_NSS_IPV4_STATS_SYNC_UDELAY); + +diff --git a/frontends/nss/ecm_nss_ipv6.c b/frontends/nss/ecm_nss_ipv6.c +index 1f7f51e..55849e7 100644 +--- a/frontends/nss/ecm_nss_ipv6.c ++++ b/frontends/nss/ecm_nss_ipv6.c +@@ -1998,10 +1998,13 @@ static void ecm_nss_ipv6_stats_sync_req_work(struct work_struct *work) + int retry = 3; + unsigned long int current_jiffies; + ++ spin_lock_bh(&ecm_nss_ipv6_lock); + if (ecm_nss_ipv6_accelerated_count == 0) { ++ spin_unlock_bh(&ecm_nss_ipv6_lock); + DEBUG_TRACE("There is no accelerated IPv6 connection\n"); + goto reschedule; + } ++ spin_unlock_bh(&ecm_nss_ipv6_lock); + + usleep_range(ECM_NSS_IPV6_STATS_SYNC_UDELAY - 100, ECM_NSS_IPV6_STATS_SYNC_UDELAY); + +-- +cgit v1.1 + diff --git a/qaa/nss/qca-nss-ecm/patches/403-Fix-IPv6-neighbor-solicitation-request.patch b/qaa/nss/qca-nss-ecm/patches/403-Fix-IPv6-neighbor-solicitation-request.patch new file mode 100644 index 000000000..7639b88a0 --- /dev/null +++ b/qaa/nss/qca-nss-ecm/patches/403-Fix-IPv6-neighbor-solicitation-request.patch @@ -0,0 +1,83 @@ +From b96002061178f399c1e58a9ad821e5096a64f788 Mon Sep 17 00:00:00 2001 +From: Murat Sezgin +Date: Mon, 23 Mar 2020 10:59:39 -0700 +Subject: [qca-nss-ecm] Fix IPv6 neighbor solicitation request + +Send the solicitation request to the GW address, when +a GW address is found, while establishing the node instance. + +Signed-off-by: Murat Sezgin +Change-Id: I2187569bcfd05b0d091cf8c79171ee3c41c39cb9 +--- + frontends/nss/ecm_nss_ipv6.c | 7 ++++--- + frontends/nss/ecm_nss_multicast_ipv6.c | 9 +++++++++ + frontends/sfe/ecm_sfe_ipv6.c | 7 ++++--- + 3 files changed, 17 insertions(+), 6 deletions(-) + +diff --git a/frontends/nss/ecm_nss_ipv6.c b/frontends/nss/ecm_nss_ipv6.c +index c7dd37f..9011e18 100644 +--- a/frontends/nss/ecm_nss_ipv6.c ++++ b/frontends/nss/ecm_nss_ipv6.c +@@ -527,13 +527,14 @@ struct ecm_db_node_instance *ecm_nss_ipv6_node_establish_and_ref(struct ecm_fron + struct net_device *master; + master = ecm_interface_get_and_hold_dev_master(dev); + DEBUG_ASSERT(master, "Expected a master\n"); +- ecm_interface_send_neighbour_solicitation(master, addr); ++ ecm_interface_send_neighbour_solicitation(master, gw_addr); + dev_put(master); + } else { +- ecm_interface_send_neighbour_solicitation(dev, addr); ++ ecm_interface_send_neighbour_solicitation(dev, gw_addr); + } + +- DEBUG_TRACE("Failed to obtain mac for host " ECM_IP_ADDR_OCTAL_FMT "\n", ECM_IP_ADDR_TO_OCTAL(addr)); ++ DEBUG_TRACE("Failed to obtain mac for host " ECM_IP_ADDR_OCTAL_FMT " gw: " ECM_IP_ADDR_OCTAL_FMT "\n", ++ ECM_IP_ADDR_TO_OCTAL(addr), ECM_IP_ADDR_TO_OCTAL(gw_addr)); + return NULL; + } + done: +diff --git a/frontends/nss/ecm_nss_multicast_ipv6.c b/frontends/nss/ecm_nss_multicast_ipv6.c +index a361eec..38fde95 100644 +--- a/frontends/nss/ecm_nss_multicast_ipv6.c ++++ b/frontends/nss/ecm_nss_multicast_ipv6.c +@@ -2558,6 +2558,15 @@ static struct ecm_db_node_instance *ecm_nss_multicast_ipv6_node_establish_and_re + #endif + if (!ecm_interface_mac_addr_get(addr, node_addr, &on_link, gw_addr)) { + DEBUG_TRACE("Failed to obtain mac for host " ECM_IP_ADDR_OCTAL_FMT "\n", ECM_IP_ADDR_TO_OCTAL(addr)); ++ ++ /* ++ * If there is a gw_addr found during the lookup, use that address ++ * for neighbour solicitation request. ++ */ ++ if (!ECM_IP_ADDR_IS_NULL(gw_addr)) { ++ ECM_IP_ADDR_COPY(addr, gw_addr); ++ } ++ + if (ecm_front_end_is_bridge_port(dev)) { + struct net_device *master; + master = ecm_interface_get_and_hold_dev_master(dev); +diff --git a/frontends/sfe/ecm_sfe_ipv6.c b/frontends/sfe/ecm_sfe_ipv6.c +index 3fd5d46..51a9ccb 100644 +--- a/frontends/sfe/ecm_sfe_ipv6.c ++++ b/frontends/sfe/ecm_sfe_ipv6.c +@@ -256,13 +256,14 @@ struct ecm_db_node_instance *ecm_sfe_ipv6_node_establish_and_ref(struct ecm_fron + struct net_device *master; + master = ecm_interface_get_and_hold_dev_master(dev); + DEBUG_ASSERT(master, "Expected a master\n"); +- ecm_interface_send_neighbour_solicitation(master, addr); ++ ecm_interface_send_neighbour_solicitation(master, gw_addr); + dev_put(master); + } else { +- ecm_interface_send_neighbour_solicitation(dev, addr); ++ ecm_interface_send_neighbour_solicitation(dev, gw_addr); + } + +- DEBUG_TRACE("Failed to obtain mac for host " ECM_IP_ADDR_OCTAL_FMT "\n", ECM_IP_ADDR_TO_OCTAL(addr)); ++ DEBUG_TRACE("Failed to obtain mac for host " ECM_IP_ADDR_OCTAL_FMT " gw: " ECM_IP_ADDR_OCTAL_FMT "\n", ++ ECM_IP_ADDR_TO_OCTAL(addr), ECM_IP_ADDR_TO_OCTAL(gw_addr)); + return NULL; + } + done: +-- +cgit v1.1 + diff --git a/qaa/nss/qca-nss-ecm/patches/404-IPv6-solicitation-fix-with-zero-gateway-address.patch b/qaa/nss/qca-nss-ecm/patches/404-IPv6-solicitation-fix-with-zero-gateway-address.patch new file mode 100644 index 000000000..bdedff442 --- /dev/null +++ b/qaa/nss/qca-nss-ecm/patches/404-IPv6-solicitation-fix-with-zero-gateway-address.patch @@ -0,0 +1,63 @@ +From 5b51ae2f1eca61c6f68e40a05333da5a362ff327 Mon Sep 17 00:00:00 2001 +From: Murat Sezgin +Date: Mon, 13 Apr 2020 09:01:48 -0700 +Subject: [qca-nss-ecm] IPv6 solicitation fix with zero gateway address + +The ECM function can find a zero gateway address for +a host IP address. In this case, we need to use the +host IP address while sending the solicitation request. + +Signed-off-by: Murat Sezgin +Change-Id: I1979834088ddfe1843566f51f64348f79e2df0fc +--- + frontends/nss/ecm_nss_ipv6.c | 11 ++++++++++- + frontends/sfe/ecm_sfe_ipv6.c | 11 ++++++++++- + 2 files changed, 20 insertions(+), 2 deletions(-) + +diff --git a/frontends/nss/ecm_nss_ipv6.c b/frontends/nss/ecm_nss_ipv6.c +index a05781b..9eb591c 100644 +--- a/frontends/nss/ecm_nss_ipv6.c ++++ b/frontends/nss/ecm_nss_ipv6.c +@@ -516,7 +516,16 @@ struct ecm_db_node_instance *ecm_nss_ipv6_node_establish_and_ref(struct ecm_fron + return NULL; + } + +- DEBUG_TRACE("Have a gw address " ECM_IP_ADDR_OCTAL_FMT "\n", ECM_IP_ADDR_TO_OCTAL(gw_addr)); ++ /* ++ * The found gateway address can be all zeros, ++ * so in this case use the host address. ++ */ ++ if (ECM_IP_ADDR_IS_NULL(gw_addr)) { ++ DEBUG_TRACE("GW address is found as zeros, so use host IP\n"); ++ ECM_IP_ADDR_COPY(gw_addr, addr); ++ } else { ++ DEBUG_TRACE("Have a gw address " ECM_IP_ADDR_OCTAL_FMT "\n", ECM_IP_ADDR_TO_OCTAL(gw_addr)); ++ } + + if (ecm_interface_mac_addr_get_no_route(dev, gw_addr, node_addr)) { + DEBUG_TRACE("Found the mac address for gateway\n"); +diff --git a/frontends/sfe/ecm_sfe_ipv6.c b/frontends/sfe/ecm_sfe_ipv6.c +index 51a9ccb..e609df7 100644 +--- a/frontends/sfe/ecm_sfe_ipv6.c ++++ b/frontends/sfe/ecm_sfe_ipv6.c +@@ -245,7 +245,16 @@ struct ecm_db_node_instance *ecm_sfe_ipv6_node_establish_and_ref(struct ecm_fron + return NULL; + } + +- DEBUG_TRACE("Have a gw address " ECM_IP_ADDR_OCTAL_FMT "\n", ECM_IP_ADDR_TO_OCTAL(gw_addr)); ++ /* ++ * The found gateway address can be all zeros, ++ * so in this case use the host address. ++ */ ++ if (ECM_IP_ADDR_IS_NULL(gw_addr)) { ++ DEBUG_TRACE("GW address is found as zeros, so use host IP\n"); ++ ECM_IP_ADDR_COPY(gw_addr, addr); ++ } else { ++ DEBUG_TRACE("Have a gw address " ECM_IP_ADDR_OCTAL_FMT "\n", ECM_IP_ADDR_TO_OCTAL(gw_addr)); ++ } + + if (ecm_interface_mac_addr_get_no_route(dev, gw_addr, node_addr)) { + DEBUG_TRACE("Found the mac address for gateway\n"); +-- +cgit v1.1 + diff --git a/qaa/nss/qca-nss-ecm/patches/405-Allow-egress-on-same-port-when-bridge-hairpin-is-enabled.patch b/qaa/nss/qca-nss-ecm/patches/405-Allow-egress-on-same-port-when-bridge-hairpin-is-enabled.patch new file mode 100644 index 000000000..a236fb757 --- /dev/null +++ b/qaa/nss/qca-nss-ecm/patches/405-Allow-egress-on-same-port-when-bridge-hairpin-is-enabled.patch @@ -0,0 +1,126 @@ +From e23eabd570eabde1d1fc803127a97fd101642467 Mon Sep 17 00:00:00 2001 +From: Varsha Mishra +Date: Fri, 12 Jun 2020 01:06:58 +0530 +Subject: [qca-nss-ecm] Allow egress on same port when bridge hairpin is + enabled. + +When bridge hairpin is enabled, allow egress on same port. Wi-Fi intrabss +frames are getting exceptioned to stack. Bridge gets to make the decision +whether these frames need to be forwarded or dropped. + +Signed-off-by: Varsha Mishra +Change-Id: Ibdd72264d8887330ba0297ed12cbcfc390065bff +--- + frontends/nss/ecm_nss_ipv4.c | 28 ++++++++++++++++++++++------ + frontends/nss/ecm_nss_ipv6.c | 28 ++++++++++++++++++++++------ + 2 files changed, 44 insertions(+), 12 deletions(-) + +diff --git a/frontends/nss/ecm_nss_ipv4.c b/frontends/nss/ecm_nss_ipv4.c +index 60f799b..51c9ebf 100644 +--- a/frontends/nss/ecm_nss_ipv4.c ++++ b/frontends/nss/ecm_nss_ipv4.c +@@ -1756,7 +1756,9 @@ static unsigned int ecm_nss_ipv4_bridge_post_routing_hook(void *priv, + * Case 2: + * For routed packets the skb will have the src mac matching the bridge mac. + * Case 3: +- * If the packet was not local (case 1) or routed (case 2) then we process. ++ * If the packet was not local (case 1) or routed (case 2) then ++ * we process. There is an exception to case 2: when hairpin mode ++ * is enabled, we process. + */ + + /* +@@ -1768,14 +1770,28 @@ static unsigned int ecm_nss_ipv4_bridge_post_routing_hook(void *priv, + dev_put(bridge); + return NF_ACCEPT; + } ++ ++ /* ++ * This flag needs to be checked in slave port(eth0/ath0) ++ * and not on master interface(br-lan). Hairpin flag can be ++ * enabled/disabled for ports individually. ++ */ + if (in == out) { +- DEBUG_TRACE("skb: %p, bridge: %p (%s), port bounce on %p (%s)\n", skb, bridge, bridge->name, out, out->name); +- dev_put(in); +- dev_put(bridge); +- return NF_ACCEPT; ++ if (!br_is_hairpin_enabled(in)) { ++ DEBUG_TRACE("skb: %p, bridge: %p (%s), ignoring" ++ "the packet, hairpin not enabled" ++ "on port %p (%s)\n", skb, bridge, ++ bridge->name, out, out->name); ++ dev_put(in); ++ dev_put(bridge); ++ return NF_ACCEPT; ++ } ++ DEBUG_TRACE("skb: %p, bridge: %p (%s), hairpin enabled on port" ++ "%p (%s)\n", skb, bridge, bridge->name, out, out->name); + } ++ ++ /* ++ * Case 2: Routed trafffic would be handled by the INET post routing. ++ */ + if (!ecm_mac_addr_equal(skb_eth_hdr->h_source, bridge->dev_addr)) { +- /* +- * Case 2: Routed trafffic would be handled by the INET post routing. +- */ + DEBUG_TRACE("skb: %p, Ignoring routed packet to bridge: %p (%s)\n", skb, bridge, bridge->name); + goto skip_ipv4_bridge_flow; + } +diff --git a/frontends/nss/ecm_nss_ipv6.c b/frontends/nss/ecm_nss_ipv6.c +index 6ad425e..160c94c 100644 +--- a/frontends/nss/ecm_nss_ipv6.c ++++ b/frontends/nss/ecm_nss_ipv6.c +@@ -1498,7 +1498,9 @@ static unsigned int ecm_nss_ipv6_bridge_post_routing_hook(void *priv, + * Case 2: + * For routed packets the skb will have the src mac matching the bridge mac. + * Case 3: +- * If the packet was not local (case 1) or routed (case 2) then we process. ++ * If the packet was not local (case 1) or routed (case 2) then ++ * we process. There is an exception to case 2: when hairpin mode ++ * is enabled, we process. + */ + + /* +@@ -1510,14 +1512,28 @@ static unsigned int ecm_nss_ipv6_bridge_post_routing_hook(void *priv, + dev_put(bridge); + return NF_ACCEPT; + } ++ ++ /* ++ * This flag needs to be checked in slave port(eth0/ath0) ++ * and not on master interface(br-lan). Hairpin flag can be ++ * enabled/disabled for ports individually. ++ */ + if (in == out) { +- DEBUG_TRACE("skb: %p, bridge: %p (%s), port bounce on %p (%s)\n", skb, bridge, bridge->name, out, out->name); +- dev_put(in); +- dev_put(bridge); +- return NF_ACCEPT; ++ if (!br_is_hairpin_enabled(in)) { ++ DEBUG_TRACE("skb: %p, bridge: %p (%s), ignoring" ++ "the packet, hairpin not enabled" ++ "on port %p (%s)\n", skb, bridge, ++ bridge->name, out, out->name); ++ dev_put(in); ++ dev_put(bridge); ++ return NF_ACCEPT; ++ } ++ DEBUG_TRACE("skb: %p, bridge: %p (%s), hairpin enabled on port" ++ "%p (%s)\n", skb, bridge, bridge->name, out, out->name); + } ++ ++ /* ++ * Case 2: Routed trafffic would be handled by the INET post routing. ++ */ + if (!ecm_mac_addr_equal(skb_eth_hdr->h_source, bridge->dev_addr)) { +- /* +- * Case 2: Routed trafffic would be handled by the INET post routing. +- */ + DEBUG_TRACE("skb: %p, Ignoring routed packet to bridge: %p (%s)\n", skb, bridge, bridge->name); + goto skip_ipv6_bridge_flow; + } +-- +cgit v1.1 + diff --git a/qaa/nss/qca-nss-gmac/Makefile b/qaa/nss/qca-nss-gmac/Makefile new file mode 100644 index 000000000..8b39f0437 --- /dev/null +++ b/qaa/nss/qca-nss-gmac/Makefile @@ -0,0 +1,47 @@ +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/kernel.mk + +PKG_NAME:=qca-nss-gmac +PKG_RELEASE:=1 + +PKG_SOURCE_PROTO:=git +PKG_SOURCE_URL:=https://source.codeaurora.org/quic/qsdk/oss/lklm/nss-gmac +PKG_SOURCE_VERSION:=9b74deef2816d91e58926e6fab7a6ff931eb3b22 +PKG_MIRROR_HASH:=a1939caa638414323e60f7d29f797ea831c6036e424b8e7bd6cf2d3d874de064 + +include $(INCLUDE_DIR)/package.mk + +define KernelPackage/qca-nss-gmac + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + DEPENDS:=@TARGET_ipq806x @LINUX_5_4 + TITLE:=Kernel driver for NSS gmac + FILES:=$(PKG_BUILD_DIR)/ipq806x/qca-nss-gmac.ko + AUTOLOAD:=$(call AutoLoad,31,qca-nss-gmac) +endef + +define KernelPackage/qca-nss-gmac/Description +This package contains a NSS driver for QCA chipset +endef + +define Build/InstallDev + mkdir -p $(1)/usr/include/qca-nss-gmac + $(CP) $(PKG_BUILD_DIR)/ipq806x/exports/* $(1)/usr/include/qca-nss-gmac/ +endef + +EXTRA_CFLAGS+= \ + -DCONFIG_NSS_DEBUG_LEVEL=4 \ + -I$(PKG_BUILD_DIR)/nss_hal/include \ + -I$(PKG_BUILD_DIR)/nss_hal/$(BOARD) + +define Build/Compile + $(MAKE) $(PKG_JOBS) -C "$(LINUX_DIR)" \ + $(KERNEL_MAKE_FLAGS) \ + $(PKG_MAKE_FLAGS) \ + M="$(PKG_BUILD_DIR)" \ + EXTRA_CFLAGS="$(EXTRA_CFLAGS)" \ + modules +endef + +$(eval $(call KernelPackage,qca-nss-gmac)) diff --git a/qaa/nss/qca-nss-gmac/patches/100-kernel-5.4-support.patch b/qaa/nss/qca-nss-gmac/patches/100-kernel-5.4-support.patch new file mode 100644 index 000000000..f3b91abc2 --- /dev/null +++ b/qaa/nss/qca-nss-gmac/patches/100-kernel-5.4-support.patch @@ -0,0 +1,279 @@ +--- a/ipq806x/nss_gmac_ctrl.c ++++ b/ipq806x/nss_gmac_ctrl.c +@@ -322,16 +322,15 @@ void nss_gmac_tx_rx_desc_init(struct nss + * (for example "ifconfig eth0"). + * @param[in] pointer to net_device structure. + * @param[in] pointer to net_device_stats64 structure. +- * @return Returns pointer to net_device_stats64 structure. + */ +-struct rtnl_link_stats64 *nss_gmac_get_stats64(struct net_device *netdev, ++void nss_gmac_get_stats64(struct net_device *netdev, + struct rtnl_link_stats64 *stats) + { + struct nss_gmac_dev *gmacdev = (struct nss_gmac_dev *)netdev_priv(netdev); + BUG_ON(gmacdev == NULL); + + if (!gmacdev->data_plane_ops) +- return stats; ++ return; + + spin_lock_bh(&gmacdev->stats_lock); + gmacdev->data_plane_ops->get_stats(gmacdev->data_plane_ctx, &gmacdev->nss_stats); +@@ -354,8 +353,6 @@ struct rtnl_link_stats64 *nss_gmac_get_s + stats->tx_fifo_errors = gmacdev->nss_stats.tx_underflow_errors; + stats->tx_window_errors = gmacdev->nss_stats.tx_late_collision_errors; + spin_unlock_bh(&gmacdev->stats_lock); +- +- return stats; + } + + +@@ -439,7 +436,7 @@ static int nss_gmac_mtnp_show(struct dev + static int nss_gmac_tstamp_show(struct device *dev, struct device_attribute *attr, char *buf) + { + struct nss_gmac_dev *gmacdev = (struct nss_gmac_dev *)netdev_priv(to_net_dev(dev)); +- struct timeval tv; ++ struct timespec64 ts64; + uint32_t ret, timeout; + uint32_t ts_hi, ts_lo; + +@@ -459,11 +456,12 @@ static int nss_gmac_tstamp_show(struct d + return -1; + } + +- do_gettimeofday(&tv); ++ ktime_get_real_ts64(&ts64); + + ret = snprintf( + buf, PAGE_SIZE, +- "sec:%u nsec:%u time-of-day: %12d.%06d \n", ts_hi, ts_lo, (int)tv.tv_sec, (int)tv.tv_usec); ++ "sec:%u nsec:%u time-of-day: %12d.%06d \n", \ ++ ts_hi, ts_lo, (int)ts64.tv_sec, (int)(ts64.tv_nsec / NSEC_PER_USEC)); + + return ret; + } +@@ -951,7 +949,7 @@ static const struct net_device_ops nss_g + * @param[in] pointer to advertised features + * @return void + */ +-static void nss_gmac_update_features(uint32_t *supp, uint32_t *adv) ++static void nss_gmac_update_features(long unsigned int *supp, long unsigned int *adv) + { + *supp |= NSS_GMAC_SUPPORTED_FEATURES; + *adv |= NSS_GMAC_ADVERTISED_FEATURES; +@@ -1409,8 +1407,8 @@ static int32_t nss_gmac_probe(struct pla + goto nss_gmac_phy_attach_fail; + } + +- nss_gmac_update_features(&(gmacdev->phydev->supported), +- &(gmacdev->phydev->advertising)); ++ nss_gmac_update_features(gmacdev->phydev->supported, ++ gmacdev->phydev->advertising); + gmacdev->phydev->irq = PHY_POLL; + netdev_dbg(netdev, "PHY %s attach OK\n", phy_id); + +@@ -1440,6 +1438,8 @@ static int32_t nss_gmac_probe(struct pla + netdev_dbg(netdev, "%s MII_PHYSID2 - 0x%04x\n", netdev->name, + nss_gmac_mii_rd_reg(gmacdev, gmacdev->phy_base, MII_PHYSID2)); + } else if (gmacdev->phy_base != NSS_GMAC_NO_MDIO_PHY) { ++ SET_NETDEV_DEV(netdev, gmacdev->miibus->parent); ++ + /* + * Issue a phy_attach for the interface connected to a switch + */ +--- a/ipq806x/nss_gmac_ethtool.c ++++ b/ipq806x/nss_gmac_ethtool.c +@@ -143,9 +143,9 @@ static const struct nss_gmac_ethtool_sta + /** + * @brief Array of strings describing private flag names + */ +-static const char *gmac_strings_priv_flags[] = { +- "linkpoll", +- "tstamp", ++static const char *gmac_strings_priv_flags[][ETH_GSTRING_LEN] = { ++ {"linkpoll"}, ++ {"tstamp"}, + }; + + #define NSS_GMAC_STATS_LEN ARRAY_SIZE(gmac_gstrings_stats) +@@ -292,6 +292,7 @@ static int nss_gmac_set_pauseparam(struc + { + struct nss_gmac_dev *gmacdev = (struct nss_gmac_dev *)netdev_priv(netdev); + struct phy_device *phydev; ++ long unsigned int *advertising; + + BUG_ON(gmacdev == NULL); + BUG_ON(gmacdev->netdev != netdev); +@@ -327,14 +328,15 @@ static int nss_gmac_set_pauseparam(struc + phydev = gmacdev->phydev; + + /* Update flow control advertisment */ +- phydev->advertising &= ~(ADVERTISED_Pause | ADVERTISED_Asym_Pause); ++ advertising = phydev->advertising; ++ *advertising &= ~(ADVERTISED_Pause | ADVERTISED_Asym_Pause); + + if (gmacdev->pause & FLOW_CTRL_RX) +- phydev->advertising |= ++ *advertising |= + (ADVERTISED_Pause | ADVERTISED_Asym_Pause); + + if (gmacdev->pause & FLOW_CTRL_TX) +- phydev->advertising |= ADVERTISED_Asym_Pause; ++ *advertising |= ADVERTISED_Asym_Pause; + + genphy_config_aneg(gmacdev->phydev); + +@@ -396,12 +398,13 @@ static uint32_t nss_gmac_get_msglevel(st + * @param[in] pointer to struct net_device. + * @param[in] pointer to struct ethtool_cmd. + */ +-static int32_t nss_gmac_get_settings(struct net_device *netdev, +- struct ethtool_cmd *ecmd) ++static int nss_gmac_get_settings(struct net_device *netdev, ++ struct ethtool_link_ksettings *elk) + { + struct nss_gmac_dev *gmacdev = (struct nss_gmac_dev *)netdev_priv(netdev); + struct phy_device *phydev = NULL; + uint16_t phyreg; ++ u32 lp_advertising = 0; + + BUG_ON(gmacdev == NULL); + +@@ -413,10 +416,10 @@ static int32_t nss_gmac_get_settings(str + */ + if (!test_bit(__NSS_GMAC_LINKPOLL, &gmacdev->flags)) { + if (gmacdev->forced_speed != SPEED_UNKNOWN) { +- ethtool_cmd_speed_set(ecmd, gmacdev->forced_speed); +- ecmd->duplex = gmacdev->forced_duplex; +- ecmd->mdio_support = 0; +- ecmd->lp_advertising = 0; ++ elk->base.speed = gmacdev->forced_speed; ++ elk->base.duplex = gmacdev->forced_duplex; ++ elk->base.mdio_support = 0; ++ ethtool_convert_legacy_u32_to_link_mode(elk->link_modes.lp_advertising, 0); + return 0; + } else { + /* Non-link polled interfaced must have a forced +@@ -429,63 +429,59 @@ static int32_t nss_gmac_get_settings(struct net_device *netdev, + + /* update PHY status */ + if (phydev->is_c45 == true) { +- ecmd->mdio_support = ETH_MDIO_SUPPORTS_C45; ++ elk->base.mdio_support = ETH_MDIO_SUPPORTS_C45; + } else { + if (genphy_read_status(phydev) != 0) { + return -EIO; + } +- ecmd->mdio_support = ETH_MDIO_SUPPORTS_C22; ++ elk->base.mdio_support = ETH_MDIO_SUPPORTS_C22; + } + + /* Populate capabilities advertised by self */ +- ecmd->advertising = phydev->advertising; ++ bitmap_copy(elk->link_modes.advertising, phydev->advertising, __ETHTOOL_LINK_MODE_MASK_NBITS); + +- ecmd->autoneg = phydev->autoneg; +- +- if (gmacdev->link_state == LINKDOWN) { +- ethtool_cmd_speed_set(ecmd, SPEED_UNKNOWN); +- ecmd->duplex = DUPLEX_UNKNOWN; +- } else { +- ethtool_cmd_speed_set(ecmd, phydev->speed); +- ecmd->duplex = phydev->duplex; +- } +- +- ecmd->port = PORT_TP; +- ecmd->phy_address = gmacdev->phy_base; +- ecmd->transceiver = XCVR_EXTERNAL; ++ elk->base.autoneg = phydev->autoneg; ++ elk->base.speed = phydev->speed; ++ elk->base.duplex = phydev->duplex; ++ elk->base.port = PORT_TP; ++ elk->base.phy_address = gmacdev->phy_base; ++ elk->base.transceiver = XCVR_EXTERNAL; + + /* Populate supported capabilities */ +- ecmd->supported = phydev->supported; ++ bitmap_copy(elk->link_modes.supported, phydev->supported, __ETHTOOL_LINK_MODE_MASK_NBITS); + + if (phydev->is_c45 == true) + return 0; + + /* Populate capabilities advertised by link partner */ ++ ethtool_convert_link_mode_to_legacy_u32(&lp_advertising, elk->link_modes.lp_advertising); + phyreg = nss_gmac_mii_rd_reg(gmacdev, gmacdev->phy_base, MII_LPA); + if (phyreg & LPA_10HALF) +- ecmd->lp_advertising |= ADVERTISED_10baseT_Half; ++ lp_advertising |= ADVERTISED_10baseT_Half; + + if (phyreg & LPA_10FULL) +- ecmd->lp_advertising |= ADVERTISED_10baseT_Full; ++ lp_advertising |= ADVERTISED_10baseT_Full; + + if (phyreg & LPA_100HALF) +- ecmd->lp_advertising |= ADVERTISED_100baseT_Half; ++ lp_advertising |= ADVERTISED_100baseT_Half; + + if (phyreg & LPA_100FULL) +- ecmd->lp_advertising |= ADVERTISED_100baseT_Full; ++ lp_advertising |= ADVERTISED_100baseT_Full; + + if (phyreg & LPA_PAUSE_CAP) +- ecmd->lp_advertising |= ADVERTISED_Pause; ++ lp_advertising |= ADVERTISED_Pause; + + if (phyreg & LPA_PAUSE_ASYM) +- ecmd->lp_advertising |= ADVERTISED_Asym_Pause; ++ lp_advertising |= ADVERTISED_Asym_Pause; + + phyreg = nss_gmac_mii_rd_reg(gmacdev, gmacdev->phy_base, MII_STAT1000); + if (phyreg & LPA_1000HALF) +- ecmd->lp_advertising |= ADVERTISED_1000baseT_Half; ++ lp_advertising |= ADVERTISED_1000baseT_Half; + + if (phyreg & LPA_1000FULL) +- ecmd->lp_advertising |= ADVERTISED_1000baseT_Full; ++ lp_advertising |= ADVERTISED_1000baseT_Full; ++ ++ ethtool_convert_legacy_u32_to_link_mode(elk->link_modes.lp_advertising, lp_advertising); + + return 0; + } +@@ -489,8 +495,8 @@ static int32_t nss_gmac_get_settings(str + * @param[in] pointer to struct net_device. + * @param[in] pointer to struct ethtool_cmd. + */ +-static int32_t nss_gmac_set_settings(struct net_device *netdev, +- struct ethtool_cmd *ecmd) ++static int nss_gmac_set_settings(struct net_device *netdev, ++ const struct ethtool_link_ksettings *elk) + { + struct nss_gmac_dev *gmacdev = (struct nss_gmac_dev *)netdev_priv(netdev); + struct phy_device *phydev = NULL; +@@ -512,13 +518,13 @@ static int32_t nss_gmac_set_settings(str + return -EPERM; + } + +- if (ecmd->autoneg == AUTONEG_ENABLE) { ++ if (elk->base.autoneg == AUTONEG_ENABLE) { + set_bit(__NSS_GMAC_AUTONEG, &gmacdev->flags); + } else { + clear_bit(__NSS_GMAC_AUTONEG, &gmacdev->flags); + } + +- return phy_ethtool_sset(phydev, ecmd); ++ return phy_ethtool_ksettings_set(phydev, elk); + } + + /** +@@ -580,8 +586,8 @@ struct ethtool_ops nss_gmac_ethtool_ops + .set_pauseparam = &nss_gmac_set_pauseparam, + .nway_reset = &nss_gmac_nway_reset, + .get_wol = &nss_gmac_get_wol, +- .get_settings = &nss_gmac_get_settings, +- .set_settings = &nss_gmac_set_settings, ++ .get_link_ksettings = &nss_gmac_get_settings, ++ .set_link_ksettings = &nss_gmac_set_settings, + .get_strings = &nss_gmac_get_strings, + .get_sset_count = &nss_gmac_get_strset_count, + .get_ethtool_stats = &nss_gmac_get_ethtool_stats, diff --git a/qaa/nss/qca-nss-gmac/patches/101-nss-gmac-test-ptr.patch b/qaa/nss/qca-nss-gmac/patches/101-nss-gmac-test-ptr.patch new file mode 100644 index 000000000..a5bff16bd --- /dev/null +++ b/qaa/nss/qca-nss-gmac/patches/101-nss-gmac-test-ptr.patch @@ -0,0 +1,25 @@ +--- a/ipq806x/nss_gmac_ctrl.c ++++ b/ipq806x/nss_gmac_ctrl.c +@@ -957,7 +957,8 @@ static int32_t nss_gmac_of_get_pdata(struct device_node *np, + struct net_device *netdev, + struct msm_nss_gmac_platform_data *gmaccfg) + { +- uint8_t *maddr = NULL; ++ int ret; ++ u8 maddr[ETH_ALEN]; + struct nss_gmac_dev *gmacdev = (struct nss_gmac_dev *)netdev_priv(netdev); + struct resource memres_devtree = {0}; + +@@ -991,9 +992,9 @@ static int32_t nss_gmac_of_get_pdata(struct device_node *np, + pr_err("%s: Can't map interrupt\n", np->name); + return -EFAULT; + } +- maddr = (uint8_t *)of_get_mac_address(np); +- if (maddr) +- memcpy(gmaccfg->mac_addr, maddr, ETH_ALEN); ++ ret = of_get_mac_address(np, maddr); ++ if (!ret && is_valid_ether_addr(maddr)) ++ ether_addr_copy(gmaccfg->mac_addr, maddr); + + if (of_address_to_resource(np, 0, &memres_devtree) != 0) + return -EFAULT; diff --git a/qaa/nss/qca-nss-gmac/patches/200-work-around-interface-close-warning.patch b/qaa/nss/qca-nss-gmac/patches/200-work-around-interface-close-warning.patch new file mode 100644 index 000000000..7cb6d6fac --- /dev/null +++ b/qaa/nss/qca-nss-gmac/patches/200-work-around-interface-close-warning.patch @@ -0,0 +1,15 @@ +--- a/ipq806x/nss_gmac_tx_rx_offload.c ++++ b/ipq806x/nss_gmac_tx_rx_offload.c +@@ -1027,8 +1027,10 @@ int nss_gmac_close(struct net_device *ne + nss_gmac_disable_interrupt_all(gmacdev); + gmacdev->data_plane_ops->link_state(gmacdev->data_plane_ctx, 0); + +- if (!IS_ERR(gmacdev->phydev)) +- phy_stop(gmacdev->phydev); ++ if (!IS_ERR(gmacdev->phydev)) { ++ if (test_bit(__NSS_GMAC_LINKPOLL, &gmacdev->flags)) ++ phy_stop(gmacdev->phydev); ++ } + + clear_bit(__NSS_GMAC_UP, &gmacdev->flags); + clear_bit(__NSS_GMAC_CLOSING, &gmacdev->flags); diff --git a/qaa/qca-mcs/Makefile b/qaa/qca-mcs/Makefile new file mode 100644 index 000000000..af9372d89 --- /dev/null +++ b/qaa/qca-mcs/Makefile @@ -0,0 +1,54 @@ +include $(TOPDIR)/rules.mk + +PKG_NAME:=qca-mcs +PKG_RELEASE:=1 + +PKG_SOURCE_PROTO:=git +PKG_SOURCE_DATE:=2021-10-28 +PKG_SOURCE_URL:=https://source.codeaurora.org/quic/qsdk/oss/lklm/qca-mcs +PKG_SOURCE_VERSION:=31f5cd4b83da5a7c0fdca240b4e72677e4523b6e +PKG_MIRROR_HASH:=3e2e25025dc2e771aafe7d8b12f26ac831d123b34bdd7b7e84bd39c1e933491d + +include $(INCLUDE_DIR)/kernel.mk +include $(INCLUDE_DIR)/package.mk + +define KernelPackage/qca-mcs + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Support + TITLE:=QCA Multicast Snooping Support + DEPENDS:=@(TARGET_ipq806x||TARGET_ipq807x) + KCONFIG:= \ + CONFIG_NETFILTER=y \ + CONFIG_BRIDGE_NETFILTER=y + FILES:=$(PKG_BUILD_DIR)/qca-mcs.ko + AUTOLOAD:=$(call AutoLoad,52,qca-mcs) +endef + +define KernelPackage/qca-mcs/description + This package installs the IGMP/MLD Snooping Module +endef + +QCA_MC_SNOOPING_HEADERS= \ + $(PKG_BUILD_DIR)/mc_api.h \ + $(PKG_BUILD_DIR)/mc_ecm.h \ + +define Build/InstallDev + $(INSTALL_DIR) $(1)/usr/include/qca-mcs + $(foreach header_file,$(QCA_MC_SNOOPING_HEADERS), $(CP) $(header_file) $(1)/usr/include/qca-mcs;) + $(foreach header_file,$(QCA_MC_SNOOPING_HEADERS), $(CP) $(header_file) $(1)/usr/include/;) +endef + +QCA_MC_SNOOPING_MAKE_OPTS:= \ + $(KERNEL_MAKE_FLAGS) \ + CONFIG_SUPPORT_MLD=y \ + MDIR=$(PKG_BUILD_DIR) \ + KBUILDPATH=$(LINUX_DIR) \ + KERNELPATH=$(LINUX_SRC_DIR) \ + KERNELRELEASE=$(LINUX_RELEASE) + +define Build/Compile + $(MAKE) -C $(LINUX_DIR) M=$(PKG_BUILD_DIR) $(strip $(QCA_MC_SNOOPING_MAKE_OPTS)) +endef + +$(eval $(call KernelPackage,qca-mcs)) diff --git a/qaa/qca-rfs/Makefile b/qaa/qca-rfs/Makefile new file mode 100644 index 000000000..7831e4d36 --- /dev/null +++ b/qaa/qca-rfs/Makefile @@ -0,0 +1,51 @@ +include $(TOPDIR)/rules.mk + +PKG_NAME:=qca-rfs +PKG_RELEASE:=1 + +PKG_SOURCE_PROTO:=git +PKG_SOURCE_URL:=https://source.codeaurora.org/quic/qsdk/oss/lklm/qca-rfs +PKG_SOURCE_DATE:=2021-03-17 +PKG_SOURCE_VERSION:=75197c386f477c7b3a6f02489d9903a9409fd5cc +PKG_MIRROR_HASH:=90f1c3ec2e984cf8efa79c85d715ebd8a21e347ab57adbd9695de23e64eea1ec + +include $(INCLUDE_DIR)/kernel.mk +include $(INCLUDE_DIR)/package.mk + +define KernelPackage/qca-rfs + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Support + DEPENDS:=@TARGET_ipq40xx +kmod-ipt-conntrack + TITLE:=Kernel module for QCA Receiving Flow Steering + FILES:=$(PKG_BUILD_DIR)/qrfs.ko + KCONFIG:=\ + CONFIG_NF_CONNTRACK_EVENTS=y \ + CONFIG_NF_CONNTRACK_CHAIN_EVENTS=y + AUTOLOAD:=$(call AutoLoad,29,qrfs) +endef + +define KernelPackage/qca-rfs/Description +QCA-RFS is a kernel module for ESS Receive Flow Steering. +endef + +define Build/Compile + $(MAKE) $(PKG_JOBS) -C "$(LINUX_DIR)" \ + $(KERNEL_MAKE_FLAGS) \ + $(PKG_MAKE_FLAGS) \ + M="$(PKG_BUILD_DIR)" \ + EXTRA_CFLAGS="$(EXTRA_CFLAGS)" \ + modules +endef + +define Build/InstallDev + $(INSTALL_DIR) $(1)/usr/include/qca-rfs + $(CP) -rf $(PKG_BUILD_DIR)/rfs_dev.h $(1)/usr/include/qca-rfs +endef + +define KernelPackage/qca-rfs/install + $(INSTALL_DIR) $(1)/etc/init.d + $(INSTALL_BIN) ./files/qrfs.init $(1)/etc/init.d/qrfs +endef + +$(eval $(call KernelPackage,qca-rfs)) diff --git a/qaa/qca-rfs/files/qrfs.init b/qaa/qca-rfs/files/qrfs.init new file mode 100644 index 000000000..f3f8a38c8 --- /dev/null +++ b/qaa/qca-rfs/files/qrfs.init @@ -0,0 +1,27 @@ +#!/bin/sh /etc/rc.common +# +# Copyright (c) 2015 The Linux Foundation. All rights reserved. +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + + +START=70 + +start() { + echo "1" > /proc/qrfs/enable + ip neigh flush all +} + +stop() { + echo "0" > /proc/qrfs/enable +} diff --git a/qaa/qca-rfs/patches/100-add-kernel-5.4-support.patch b/qaa/qca-rfs/patches/100-add-kernel-5.4-support.patch new file mode 100644 index 000000000..b7b2db559 --- /dev/null +++ b/qaa/qca-rfs/patches/100-add-kernel-5.4-support.patch @@ -0,0 +1,57 @@ +--- a/rfs_cm.c ++++ b/rfs_cm.c +@@ -462,14 +462,6 @@ static int rfs_cm_conntrack_event(unsign + } + + /* +- * If this is an untracked connection then we can't have any state either. +- */ +- if (unlikely(ct == &nf_conntrack_untracked)) { +- RFS_TRACE("ignoring untracked conn\n"); +- return NOTIFY_DONE; +- } +- +- /* + * Ignore anything other than IPv4 connections. + */ + if (unlikely(nf_ct_l3num(ct) != AF_INET)) { +--- a/rfs_rule.c ++++ b/rfs_rule.c +@@ -702,7 +702,7 @@ int rfs_rule_init(void) + + RFS_DEBUG("RFS Rule init\n"); + spin_lock_init(&rr->hash_lock); +- memset(&rr->hash, 0, RFS_RULE_HASH_SIZE); ++ memset(&rr->hash, 0, sizeof(rr->hash)); + + rr->proc_rule = proc_create("rule", S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH, + rfs_proc_entry, &rule_proc_fops); +@@ -717,7 +717,7 @@ void rfs_rule_exit(void) + struct rfs_rule *rr = &__rr; + + RFS_DEBUG("RFS Rule exit\n"); +- if (rr->proc_rule); ++ if (rr->proc_rule) + remove_proc_entry("rule", rfs_proc_entry); + rfs_rule_destroy_all(); + } +--- a/rfs_wxt.c ++++ b/rfs_wxt.c +@@ -422,7 +422,7 @@ static int rfs_wxt_rx(struct socket *soc + #else + iov_iter_init(&msg.msg_iter, READ, &iov, 1, len); + #endif +- size = sock_recvmsg(sock, &msg, len, msg.msg_flags); ++ size = sock_recvmsg(sock, &msg, msg.msg_flags); + set_fs(oldfs); + + return size; +@@ -510,7 +510,7 @@ int rfs_wxt_stop(void) + } + + RFS_DEBUG("kill rfs_wxt thread"); +- force_sig(SIGKILL, __rwn.thread); ++ send_sig(SIGKILL, __rwn.thread, 1); + if (__rwn.thread) + err = kthread_stop(__rwn.thread); + __rwn.thread = NULL; diff --git a/qaa/qca-rfs/patches/200-rework-nfct-notification.patch b/qaa/qca-rfs/patches/200-rework-nfct-notification.patch new file mode 100644 index 000000000..81e608c02 --- /dev/null +++ b/qaa/qca-rfs/patches/200-rework-nfct-notification.patch @@ -0,0 +1,20 @@ +--- a/rfs_cm.c ++++ b/rfs_cm.c +@@ -709,7 +709,7 @@ int rfs_cm_start(void) + + RFS_DEBUG("RFS cm start\n"); + #ifdef CONFIG_NF_CONNTRACK_EVENTS +- ret = nf_conntrack_register_notifier(&init_net, &rfs_cm_conntrack_notifier); ++ ret = nf_conntrack_register_chain_notifier(&init_net, &rfs_cm_conntrack_notifier); + if (ret < 0) { + RFS_ERROR("can't register nf notifier hook: %d\n", ret); + return -1; +@@ -740,7 +740,7 @@ int rfs_cm_stop(void) + #endif + + #ifdef CONFIG_NF_CONNTRACK_EVENTS +- nf_conntrack_unregister_notifier(&init_net, &rfs_cm_conntrack_notifier); ++ nf_conntrack_unregister_chain_notifier(&init_net, &rfs_cm_conntrack_notifier); + #endif + + rfs_cm_connection_destroy_all(); diff --git a/qaa/qca-ssdk-shell/Makefile b/qaa/qca-ssdk-shell/Makefile new file mode 100644 index 000000000..90e2c2e64 --- /dev/null +++ b/qaa/qca-ssdk-shell/Makefile @@ -0,0 +1,48 @@ +include $(TOPDIR)/rules.mk + +PKG_NAME:=qca-ssdk-shell +PKG_RELEASE:=1 + +PKG_SOURCE_PROTO:=git +PKG_SOURCE_URL:=https://source.codeaurora.org/quic/qsdk/oss/ssdk-shell +PKG_SOURCE_DATE:=2021-01-27 +PKG_SOURCE_VERSION:=5661366d471a78314bc7010f985ad8cc15be832a +PKG_MIRROR_HASH:=73111e09e896f0abbe3ee1c358aea7ec14fe5e668ce8753b8968e03c78f9599b + +include $(INCLUDE_DIR)/kernel.mk +include $(INCLUDE_DIR)/package.mk + +define Package/qca-ssdk-shell + SECTION:=utils + CATEGORY:=Utilities + TITLE:=Shell application for QCA SSDK + DEPENDS:=@(TARGET_ipq40xx||TARGET_ipq806x||TARGET_ipq807x) +endef + +define Package/qca-ssdk-shell/Description + This package contains a qca-ssdk shell application for QCA chipset +endef + +ifndef CONFIG_TOOLCHAIN_BIN_PATH +CONFIG_TOOLCHAIN_BIN_PATH=$(TOOLCHAIN_DIR)/bin +endif + +QCASSDK_CONFIG_OPTS+= \ + TOOL_PATH=$(CONFIG_TOOLCHAIN_BIN_PATH) \ + SYS_PATH=$(LINUX_DIR) \ + TOOLPREFIX=$(TARGET_CROSS) \ + KVER=$(LINUX_VERSION) \ + CFLAGS="$(TARGET_CFLAGS)" \ + LDFLAGS="$(TARGET_LDFLAGS)" \ + ARCH=$(LINUX_KARCH) + +define Build/Compile + $(MAKE) -C $(PKG_BUILD_DIR) $(strip $(QCASSDK_CONFIG_OPTS)) +endef + +define Package/qca-ssdk-shell/install + $(INSTALL_DIR) $(1)/usr/sbin + $(INSTALL_BIN) $(PKG_BUILD_DIR)/build/bin/ssdk_sh $(1)/usr/sbin/ +endef + +$(eval $(call BuildPackage,qca-ssdk-shell)) diff --git a/qaa/qca-ssdk/Makefile b/qaa/qca-ssdk/Makefile new file mode 100644 index 000000000..3a68a50a2 --- /dev/null +++ b/qaa/qca-ssdk/Makefile @@ -0,0 +1,125 @@ +include $(TOPDIR)/rules.mk + +PKG_NAME:=qca-ssdk +PKG_RELEASE:=1 + +PKG_SOURCE_PROTO:=git +PKG_SOURCE_URL:=https://source.codeaurora.org/quic/qsdk/oss/lklm/qca-ssdk +PKG_SOURCE_DATE:=2021-04-28 +PKG_SOURCE_VERSION:=c9bc3bc34eaaac78083573524097356e2dcc1b66 +PKG_MIRROR_HASH:=29db78529be32427b8b96fcbfec22a016a243676781ec96d9d65b810944fa405 + +LOCAL_VARIANT=$(patsubst qca-ssdk-%,%,$(patsubst qca-ssdk-%,%,$(BUILD_VARIANT))) + +include $(INCLUDE_DIR)/kernel.mk +include $(INCLUDE_DIR)/package.mk + +define KernelPackage/qca-ssdk/default-nohnat + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=Kernel driver for QCA SSDK + FILES:=$(PKG_BUILD_DIR)/build/bin/qca-ssdk.ko + AUTOLOAD:=$(call AutoLoad,30,qca-ssdk) + PROVIDES:=qca-ssdk +endef + +define KernelPackage/qca-ssdk-nohnat +$(call KernelPackage/qca-ssdk/default-nohnat) + DEPENDS:=@(TARGET_ipq806x||TARGET_ipq807x) + VARIANT:=nohnat +endef + +define KernelPackage/qca-ssdk-nohnat/Description +This package contains a qca-ssdk driver for QCA chipset +endef + +define KernelPackage/qca-ssdk-hnat +$(call KernelPackage/qca-ssdk/default-nohnat) + DEPENDS:=@TARGET_ipq40xx +kmod-ipt-extra +kmod-ipt-filter \ + +kmod-ppp +TARGET_ipq40xx:kmod-qca-rfs + TITLE+= (hnat) + VARIANT:=hnat +endef + +define KernelPackage/qca-ssdk-hnat/Description +This package contains a qca-ssdk-hnat driver for QCA chipset +endef + +ifdef CONFIG_TOOLCHAIN_BIN_PATH +TOOLCHAIN_BIN_PATH=$(CONFIG_TOOLCHAIN_BIN_PATH) +else +TOOLCHAIN_BIN_PATH=$(TOOLCHAIN_DIR)/bin +endif + +QCASSDK_CONFIG_OPTS+= \ + $(KERNEL_MAKE_FLAGS) \ + KVER=$(LINUX_VERSION) \ + SYS_PATH=$(LINUX_DIR) \ + GCC_VERSION=$(GCC_VERSION) \ + TOOLPREFIX=$(TARGET_CROSS) \ + TOOL_PATH=$(TOOLCHAIN_BIN_PATH) \ + TARGET_SUFFIX=$(CONFIG_TARGET_SUFFIX) \ + EXTRA_CFLAGS=-fno-stack-protector -I$(STAGING_DIR)/usr/include + +ifeq ($(LOCAL_VARIANT),hnat) + QCASSDK_CONFIG_OPTS+= HNAT_FEATURE=enable +ifeq ($(BOARD),ipq40xx) + QCASSDK_CONFIG_OPTS+= RFS_FEATURE=enable +endif +endif + +ifeq ($(BOARD),ipq60xx) + QCASSDK_CONFIG_OPTS+= CHIP_TYPE=CPPE +else ifeq ($(BOARD),ipq807x) + QCASSDK_CONFIG_OPTS+= CHIP_TYPE=HPPE +else + QCASSDK_CONFIG_OPTS+= HK_CHIP=enable +endif + +ifneq (, $(findstring $(BOARD), ipq60xx ipq807x)) + QCASSDK_CONFIG_OPTS+= PTP_FEATURE=disable SWCONFIG_FEATURE=disable +endif + +define Build/Compile + $(MAKE) -C $(PKG_BUILD_DIR) $(strip $(QCASSDK_CONFIG_OPTS)) +endef + +define Build/InstallDev + $(INSTALL_DIR) $(1)/usr/include/qca-ssdk + $(INSTALL_DIR) $(1)/usr/include/qca-ssdk/api + $(INSTALL_DIR) $(1)/usr/include/qca-ssdk/ref + $(INSTALL_DIR) $(1)/usr/include/qca-ssdk/fal + $(INSTALL_DIR) $(1)/usr/include/qca-ssdk/sal + $(INSTALL_DIR) $(1)/usr/include/qca-ssdk/init + $(CP) -rf $(PKG_BUILD_DIR)/include/api/sw_ioctl.h $(1)/usr/include/qca-ssdk/api + if [ -f $(PKG_BUILD_DIR)/include/ref/ref_vsi.h ]; then \ + $(CP) -rf $(PKG_BUILD_DIR)/include/ref/ref_vsi.h $(1)/usr/include/qca-ssdk/ref/; \ + fi + if [ -f $(PKG_BUILD_DIR)/include/ref/ref_fdb.h ]; then \ + $(CP) -rf $(PKG_BUILD_DIR)/include/ref/ref_fdb.h $(1)/usr/include/qca-ssdk/ref/; \ + fi + if [ -f $(PKG_BUILD_DIR)/include/ref/ref_port_ctrl.h ]; then \ + $(CP) -rf $(PKG_BUILD_DIR)/include/ref/ref_port_ctrl.h $(1)/usr/include/qca-ssdk/ref/; \ + fi + if [ -f $(PKG_BUILD_DIR)/include/init/ssdk_init.h ]; then \ + $(CP) -rf $(PKG_BUILD_DIR)/include/init/ssdk_init.h $(1)/usr/include/qca-ssdk/init/; \ + fi + $(CP) -rf $(PKG_BUILD_DIR)/include/fal $(1)/usr/include/qca-ssdk + $(CP) -rf $(PKG_BUILD_DIR)/include/common/*.h $(1)/usr/include/qca-ssdk + $(CP) -rf $(PKG_BUILD_DIR)/include/sal/os/linux/*.h $(1)/usr/include/qca-ssdk + $(CP) -rf $(PKG_BUILD_DIR)/include/sal/os/*.h $(1)/usr/include/qca-ssdk +endef + +define KernelPackage/qca-ssdk-nohnat/install + $(INSTALL_DIR) $(1)/etc/init.d + $(INSTALL_BIN) ./files/qca-ssdk $(1)/etc/init.d/qca-ssdk +endef + +define KernelPackage/qca-ssdk-hnat/install + $(INSTALL_DIR) $(1)/etc/init.d + $(INSTALL_BIN) ./files/qca-ssdk $(1)/etc/init.d/qca-ssdk +endef + +$(eval $(call KernelPackage,qca-ssdk-nohnat)) +$(eval $(call KernelPackage,qca-ssdk-hnat)) diff --git a/qaa/qca-ssdk/files/qca-ssdk b/qaa/qca-ssdk/files/qca-ssdk new file mode 100644 index 000000000..389279c0c --- /dev/null +++ b/qaa/qca-ssdk/files/qca-ssdk @@ -0,0 +1,206 @@ +#!/bin/sh /etc/rc.common +# Copyright (c) 2018, The Linux Foundation. All rights reserved. +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +# + +START=16 + +#!/bin/sh +ruletype="ip4 ip6" +side="wan lan" +qwan="1 3 2 0 5 7 6 4" +qlan="0 1 2 3 4 5 6 7" + +function create_war_acl_rules(){ + for lw in $side + do + #echo $lw + if [ "$lw" == "wan" ];then + listid=254 + queue=$qwan + portmap=0x20 + else + listid=255 + queue=$qlan + portmap=0x1e + fi + #echo $queue + #echo "creating list $listid" + ssdk_sh acl list create $listid 255 + ruleid=0 + for rt in $ruletype + do + for qid in $queue + do + cmd="ssdk_sh acl rule add $listid $ruleid 1 n 0 0" + #echo $cmd + if [ "$rt" == "ip4" ];then + cmd="$cmd ip4 n n n n n n n n n n n n n n n n n n n n n n n n n n n n n" + #echo $cmd + else + cmd="$cmd ip6 n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n" + #echo $cmd + fi + if [ $ruleid -le 3 ];then + #non-zero dscp + cmd="$cmd y 0x0 0xff" + elif [ $ruleid -le 7 ];then + #zero dscp + cmd="$cmd n" + elif [ $ruleid -le 11 ];then + #non-zero dscp + cmd="$cmd y 0x0 0xff" + else + #zero dscp + cmd="$cmd n" + fi + p=$((ruleid/2)) + cmd="$cmd y mask $((ruleid%2)) 0x1 y mask $((p%2)) 0x1 n n n n n n n n n n n n n n n y n n n n n n n y $qid n n 0 0 n n n n n n n n n n n n n n n n n n n n 0" + #echo $cmd + $cmd + ruleid=`expr $ruleid + 1` + done + done + ssdk_sh acl list bind $listid 0 1 $portmap + done +} + +function create_war_cosmap(){ + ssdk_sh cosmap pri2q set 0 0 + ssdk_sh cosmap pri2q set 1 0 + ssdk_sh cosmap pri2q set 2 0 + ssdk_sh cosmap pri2q set 3 0 + ssdk_sh cosmap pri2q set 4 1 + ssdk_sh cosmap pri2q set 5 1 + ssdk_sh cosmap pri2q set 6 1 + ssdk_sh cosmap pri2q set 7 1 + ssdk_sh cosmap pri2ehq set 0 0 + ssdk_sh cosmap pri2ehq set 1 0 + ssdk_sh cosmap pri2ehq set 2 0 + ssdk_sh cosmap pri2ehq set 3 0 + ssdk_sh cosmap pri2ehq set 4 1 + ssdk_sh cosmap pri2ehq set 5 1 + ssdk_sh cosmap pri2ehq set 6 1 + ssdk_sh cosmap pri2ehq set 7 1 +} + +function create_acl_byp_egstp_rules(){ + ssdk_sh debug module_func set servcode 0xf 0x0 0x0 + ssdk_sh servcode config set 1 n 0 0xfffefc7f 0xffbdff 0 0 0 0 0 0 + ssdk_sh debug module_func set servcode 0x0 0x0 0x0 + ssdk_sh acl list create 56 48 + ssdk_sh acl rule add 56 0 1 n 0 0 mac n n n n n y 01-80-c2-00-00-00 ff-ff-ff-ff-ff-ff n n n n n n n n n n n n n n n n n n n n n n n y n n n n n n n n n n 0 0 n n n n n n n n n n n n n y n n n n n n n n n n n n y n n n n n n n n n n n n 0 + ssdk_sh acl rule add 56 1 1 n 0 0 mac n n n n n n n yes 0x8809 0xffff n n n n n n n n n n n n n n n n n n n n n y n n n n n n n n n n 0 0 n n n n n n n n n n n n n y n n n n n n n n n n n n y n n n n n n n n n n n n 0 + ssdk_sh acl rule add 56 2 1 n 0 0 mac n n n n n n n yes 0x888e 0xffff n n n n n n n n n n n n n n n n n n n n n y n n n n n n n n n n 0 0 n n n n n n n n n n n n n y n n n n n n n n n n n n y n n n n n n n n n n n n 0 + ssdk_sh acl list bind 56 0 2 1 +} + +function delete_war_acl_rules(){ + for lw in $side + do + #echo $lw + if [ "$lw" == "wan" ];then + listid=254 + queue=$qwan + portmap=0x20 + else + listid=255 + queue=$qlan + portmap=0x1e + fi + ssdk_sh acl list unbind $listid 0 1 $portmap + for rt in $ruletype + do + for qid in $queue + do + cmd="ssdk_sh acl rule del $listid 0 1" + echo $cmd + $cmd + done + done + #echo "deleting list $listid" + ssdk_sh acl list destroy $listid + done +} + +function delete_war_cosmap(){ + ssdk_sh cosmap pri2q set 0 0 + ssdk_sh cosmap pri2q set 1 0 + ssdk_sh cosmap pri2q set 2 1 + ssdk_sh cosmap pri2q set 3 1 + ssdk_sh cosmap pri2q set 4 2 + ssdk_sh cosmap pri2q set 5 2 + ssdk_sh cosmap pri2q set 6 3 + ssdk_sh cosmap pri2q set 7 3 + ssdk_sh cosmap pri2ehq set 0 1 + ssdk_sh cosmap pri2ehq set 1 0 + ssdk_sh cosmap pri2ehq set 2 2 + ssdk_sh cosmap pri2ehq set 3 2 + ssdk_sh cosmap pri2ehq set 4 3 + ssdk_sh cosmap pri2ehq set 5 3 + ssdk_sh cosmap pri2ehq set 6 4 + ssdk_sh cosmap pri2ehq set 7 5 +} + +function delete_acl_byp_egstp_rules(){ + ssdk_sh debug module_func set servcode 0xf 0x0 0x0 + ssdk_sh servcode config set 1 n 0 0xfffefcff 0xffbfff 0 0 0 0 0 0 + ssdk_sh debug module_func set servcode 0x0 0x0 0x0 + ssdk_sh acl list unbind 56 0 2 1 + ssdk_sh acl rule del 56 0 1 + ssdk_sh acl rule del 56 1 1 + ssdk_sh acl rule del 56 2 1 + ssdk_sh acl list destroy 56 +} + +function edma_war_config_add(){ + create_war_cosmap + ssdk_sh acl status set enable + create_war_acl_rules +} + +function edma_war_config_del(){ + delete_war_acl_rules + delete_war_cosmap +} + +start() { + chip_ver=`ssdk_sh debug reg get 0 4 | grep Data | tr -d 'SSDK Init OK![Data]:'` + #The following commands should be uncommented to enable EDMA WAR + if [ "$chip_ver" = "0x1401" ]; then + #edma_war_config_add + echo '' + fi + #The following commands should be uncommented to add acl egress stp bypass rules + if [ "$chip_ver" = "0x1500" ] || [ "$chip_ver" = "0x1501" ]; then + #create_acl_byp_egstp_rules + echo '' + fi + echo starting +} + +stop() { + chip_ver=`ssdk_sh debug reg get 0 4 | grep Data | tr -d 'SSDK Init OK![Data]:'` + #The following commands should be uncommented to disable EDMA WAR + if [ "$chip_ver" = "0x1401" ]; then + #edma_war_config_del + echo '' + fi + #The following commands should be uncommented to delete acl egress stp bypass rules + if [ "$chip_ver" = "0x1500" ] || [ "$chip_ver" = "0x1501" ]; then + #delete_acl_byp_egstp_rules + echo '' + fi + echo stoping +} diff --git a/qaa/qca-ssdk/patches/0001-SSDK-config-add-kernel-5.10.patch b/qaa/qca-ssdk/patches/0001-SSDK-config-add-kernel-5.10.patch new file mode 100644 index 000000000..1ee44fa96 --- /dev/null +++ b/qaa/qca-ssdk/patches/0001-SSDK-config-add-kernel-5.10.patch @@ -0,0 +1,56 @@ +From 472c0c8132784608312c80c4b02c03ea7c132235 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Wed, 12 May 2021 13:41:12 +0200 +Subject: [PATCH] SSDK: config: add kernel 5.10 + +This is purely to identify it and be able to set +flags correctly. + +Signed-off-by: Robert Marko +--- + config | 6 +++++- + make/linux_opt.mk | 4 ++-- + 2 files changed, 7 insertions(+), 3 deletions(-) + +--- a/config ++++ b/config +@@ -22,6 +22,10 @@ ifeq ($(KVER),$(filter 5.4%,$(KVER))) + OS_VER=5_4 + endif + ++ifeq ($(KVER),$(filter 5.10%,$(KVER))) ++OS_VER=5_10 ++endif ++ + ifeq ($(KVER), 3.4.0) + OS_VER=3_4 + endif +@@ -123,7 +127,7 @@ endif + endif + + ifeq ($(ARCH), arm64) +-ifeq ($(KVER),$(filter 4.1% 4.4% 4.9% 5.4%,$(KVER))) ++ifeq ($(KVER),$(filter 4.1% 4.4% 4.9% 5.4% 5.10%,$(KVER))) + CPU_CFLAG= -DMODULE -Os -pipe -march=armv8-a -mcpu=cortex-a53+crypto -fno-caller-saves -fno-strict-aliasing -Werror -fno-common -Wno-format-security -Wno-pointer-sign -Wno-unused-but-set-variable -Wno-error=unused-result -mcmodel=large + endif + endif +--- a/make/linux_opt.mk ++++ b/make/linux_opt.mk +@@ -388,7 +388,7 @@ ifeq (KSLIB, $(MODULE_TYPE)) + KASAN_SHADOW_SCALE_SHIFT := 3 + endif + +- ifeq (5_4, $(OS_VER)) ++ ifeq ($(OS_VER),$(filter 5_4 5_10, $(OS_VER))) + ifeq ($(ARCH), arm64) + KASAN_OPTION += -DKASAN_SHADOW_SCALE_SHIFT=$(KASAN_SHADOW_SCALE_SHIFT) + endif +@@ -419,7 +419,7 @@ ifeq (KSLIB, $(MODULE_TYPE)) + + endif + +- ifeq ($(OS_VER),$(filter 4_4 5_4, $(OS_VER))) ++ ifeq ($(OS_VER),$(filter 4_4 5_4 5_10, $(OS_VER))) + MODULE_CFLAG += -DKVER34 + MODULE_CFLAG += -DKVER32 + MODULE_CFLAG += -DLNX26_22 diff --git a/qaa/qca-ssdk/patches/0002-SSDK-replace-ioremap_nocache-with-ioremap.patch b/qaa/qca-ssdk/patches/0002-SSDK-replace-ioremap_nocache-with-ioremap.patch new file mode 100644 index 000000000..b293ad295 --- /dev/null +++ b/qaa/qca-ssdk/patches/0002-SSDK-replace-ioremap_nocache-with-ioremap.patch @@ -0,0 +1,102 @@ +From 784f2cfdfaf3bdf44917924e157049230a0ef5f8 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Wed, 12 May 2021 13:45:45 +0200 +Subject: [PATCH] SSDK: replace ioremap_nocache with ioremap + +ioremap_nocache was dropped upstream, simply use the +generic variety. + +Signed-off-by: Robert Marko +--- + src/init/ssdk_clk.c | 10 +++++----- + src/init/ssdk_init.c | 2 +- + src/init/ssdk_plat.c | 6 +++--- + 3 files changed, 9 insertions(+), 9 deletions(-) + +--- a/src/init/ssdk_clk.c ++++ b/src/init/ssdk_clk.c +@@ -623,7 +623,7 @@ ssdk_mp_tcsr_get(a_uint32_t tcsr_offset, + { + void __iomem *tcsr_base = NULL; + +- tcsr_base = ioremap_nocache(TCSR_ETH_ADDR, TCSR_ETH_SIZE); ++ tcsr_base = ioremap(TCSR_ETH_ADDR, TCSR_ETH_SIZE); + if (!tcsr_base) + { + SSDK_ERROR("Failed to map tcsr eth address!\n"); +@@ -640,7 +640,7 @@ ssdk_mp_tcsr_set(a_uint32_t tcsr_offset, + { + void __iomem *tcsr_base = NULL; + +- tcsr_base = ioremap_nocache(TCSR_ETH_ADDR, TCSR_ETH_SIZE); ++ tcsr_base = ioremap(TCSR_ETH_ADDR, TCSR_ETH_SIZE); + if (!tcsr_base) + { + SSDK_ERROR("Failed to map tcsr eth address!\n"); +@@ -688,7 +688,7 @@ ssdk_mp_cmnblk_stable_check(void) + a_uint32_t reg_val; + int i, loops = 20; + +- pll_lock = ioremap_nocache(CMN_PLL_LOCKED_ADDR, CMN_PLL_LOCKED_SIZE); ++ pll_lock = ioremap(CMN_PLL_LOCKED_ADDR, CMN_PLL_LOCKED_SIZE); + if (!pll_lock) { + SSDK_ERROR("Failed to map CMN PLL LOCK register!\n"); + return A_FALSE; +@@ -745,7 +745,7 @@ static void ssdk_cmnblk_pll_src_set(enum + void __iomem *cmn_pll_src_base = NULL; + a_uint32_t reg_val; + +- cmn_pll_src_base = ioremap_nocache(CMN_BLK_PLL_SRC_ADDR, CMN_BLK_SIZE); ++ cmn_pll_src_base = ioremap(CMN_BLK_PLL_SRC_ADDR, CMN_BLK_SIZE); + if (!cmn_pll_src_base) { + SSDK_ERROR("Failed to map cmn pll source address!\n"); + return; +@@ -766,7 +766,7 @@ static void ssdk_cmnblk_init(enum cmnblk + void __iomem *gcc_pll_base = NULL; + a_uint32_t reg_val; + +- gcc_pll_base = ioremap_nocache(CMN_BLK_ADDR, CMN_BLK_SIZE); ++ gcc_pll_base = ioremap(CMN_BLK_ADDR, CMN_BLK_SIZE); + if (!gcc_pll_base) { + SSDK_ERROR("Failed to map gcc pll address!\n"); + return; +--- a/src/init/ssdk_init.c ++++ b/src/init/ssdk_init.c +@@ -2770,7 +2770,7 @@ static int ssdk_dess_mac_mode_init(a_uin + (a_uint8_t *)®_value, 4); + mdelay(10); + /*softreset psgmii, fixme*/ +- gcc_addr = ioremap_nocache(0x1812000, 0x200); ++ gcc_addr = ioremap(0x1812000, 0x200); + if (!gcc_addr) { + SSDK_ERROR("gcc map fail!\n"); + return 0; +--- a/src/init/ssdk_plat.c ++++ b/src/init/ssdk_plat.c +@@ -1312,7 +1312,7 @@ ssdk_plat_init(ssdk_init_cfg *cfg, a_uin + reg_mode = ssdk_uniphy_reg_access_mode_get(dev_id); + if(reg_mode == HSL_REG_LOCAL_BUS) { + ssdk_uniphy_reg_map_info_get(dev_id, &map); +- qca_phy_priv_global[dev_id]->uniphy_hw_addr = ioremap_nocache(map.base_addr, ++ qca_phy_priv_global[dev_id]->uniphy_hw_addr = ioremap(map.base_addr, + map.size); + if (!qca_phy_priv_global[dev_id]->uniphy_hw_addr) { + SSDK_ERROR("%s ioremap fail.", __func__); +@@ -1327,7 +1327,7 @@ ssdk_plat_init(ssdk_init_cfg *cfg, a_uin + reg_mode = ssdk_switch_reg_access_mode_get(dev_id); + if(reg_mode == HSL_REG_LOCAL_BUS) { + ssdk_switch_reg_map_info_get(dev_id, &map); +- qca_phy_priv_global[dev_id]->hw_addr = ioremap_nocache(map.base_addr, ++ qca_phy_priv_global[dev_id]->hw_addr = ioremap(map.base_addr, + map.size); + if (!qca_phy_priv_global[dev_id]->hw_addr) { + SSDK_ERROR("%s ioremap fail.", __func__); +@@ -1358,7 +1358,7 @@ ssdk_plat_init(ssdk_init_cfg *cfg, a_uin + return -1; + } + +- qca_phy_priv_global[dev_id]->psgmii_hw_addr = ioremap_nocache(map.base_addr, ++ qca_phy_priv_global[dev_id]->psgmii_hw_addr = ioremap(map.base_addr, + map.size); + if (!qca_phy_priv_global[dev_id]->psgmii_hw_addr) { + SSDK_ERROR("%s ioremap fail.", __func__); diff --git a/qaa/qca-ssdk/patches/0004-platform-use-of_mdio_find_bus-to-get-MDIO-bus.patch b/qaa/qca-ssdk/patches/0004-platform-use-of_mdio_find_bus-to-get-MDIO-bus.patch new file mode 100644 index 000000000..3bcbcccf6 --- /dev/null +++ b/qaa/qca-ssdk/patches/0004-platform-use-of_mdio_find_bus-to-get-MDIO-bus.patch @@ -0,0 +1,40 @@ +From b6190ca46287d01a895c7cc14de30410c09ff1b8 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Wed, 12 May 2021 17:15:46 +0200 +Subject: [PATCH] SSDK: platform: use of_mdio_find_bus() to get MDIO bus + +Kernel has a generic of_mdio_find_bus() which can get the appropriate +MDIO bus based on the DT node. +So, drop the getting MDIO from platform data, which no longer works +in 5.4 and later and use of_mdio_find_bus(). + +Signed-off-by: Baruch Siach +Signed-off-by: Robert Marko +--- + src/init/ssdk_plat.c | 8 +------- + 1 file changed, 1 insertion(+), 7 deletions(-) + +--- a/src/init/ssdk_plat.c ++++ b/src/init/ssdk_plat.c +@@ -551,7 +551,6 @@ static int miibus_get(a_uint32_t dev_id) + struct device_node *mdio_node = NULL; + struct device_node *switch_node = NULL; + struct platform_device *mdio_plat = NULL; +- struct ipq40xx_mdio_data *mdio_data = NULL; + struct qca_phy_priv *priv; + hsl_reg_mode reg_mode = HSL_REG_LOCAL_BUS; + priv = qca_phy_priv_global[dev_id]; +@@ -584,12 +583,7 @@ static int miibus_get(a_uint32_t dev_id) + + if(reg_mode == HSL_REG_LOCAL_BUS) + { +- mdio_data = dev_get_drvdata(&mdio_plat->dev); +- if (!mdio_data) { +- SSDK_ERROR("cannot get mdio_data reference from device data\n"); +- return 1; +- } +- priv->miibus = mdio_data->mii_bus; ++ priv->miibus = of_mdio_find_bus(mdio_node); + } + else + priv->miibus = dev_get_drvdata(&mdio_plat->dev); diff --git a/qaa/qca-ssdk/patches/0005-add-kernel-5.4-support.patch b/qaa/qca-ssdk/patches/0005-add-kernel-5.4-support.patch new file mode 100644 index 000000000..6b08b05ae --- /dev/null +++ b/qaa/qca-ssdk/patches/0005-add-kernel-5.4-support.patch @@ -0,0 +1,108 @@ +--- a/app/nathelper/linux/lib/nat_helper_dt.c ++++ b/app/nathelper/linux/lib/nat_helper_dt.c +@@ -721,7 +721,7 @@ napt_ct_counter_sync(a_uint32_t hw_index) + } + + if (!test_bit(IPS_FIXED_TIMEOUT_BIT, &ct->status)) { +- ct->timeout.expires += delta_jiffies; ++ ct->timeout += delta_jiffies; + } + + if((cct != NULL) && (napt_hw_get_by_index(&napt, hw_index) == 0)) +@@ -770,7 +770,7 @@ napt_ct_timer_update(a_uint32_t hw_index) + } + + if (!test_bit(IPS_FIXED_TIMEOUT_BIT, &ct->status)) { +- ct->timeout.expires += delta_jiffies; ++ ct->timeout += delta_jiffies; + } + + return 0; +--- a/app/nathelper/linux/napt_helper.c ++++ b/app/nathelper/linux/napt_helper.c +@@ -64,11 +64,6 @@ napt_ct_aging_disable(uint32_t ct_addr) + } + + ct = (struct nf_conn *)ct_addr; +- +- if (timer_pending(&ct->timeout)) +- { +- del_timer(&ct->timeout); +- } + } + + int +@@ -85,7 +80,7 @@ napt_ct_aging_is_enable(uint32_t ct_addr) + + ct = (struct nf_conn *)ct_addr; + +- return timer_pending(&(((struct nf_conn *)ct)->timeout)); ++ return (nf_ct_is_expired(ct)); + } + + void +@@ -111,18 +106,17 @@ napt_ct_aging_enable(uint32_t ct_addr) + l3num = ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple.src.l3num; + protonum = ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple.dst.protonum; + +- ct->timeout.expires = jiffies+10*HZ; ++ ct->timeout = jiffies+10*HZ; + + if ((l3num == AF_INET) && (protonum == IPPROTO_TCP)) + { + if (ct->proto.tcp.state == TCP_CONNTRACK_ESTABLISHED) + { +- ct->timeout.expires = jiffies+(5*24*60*60*HZ); ++ ct->timeout = jiffies+(5*24*60*60*HZ); + } + } + + HNAT_PRINTK(" ct:[%x] add timeout again\n", ct_addr); +- add_timer(&ct->timeout); + } + + void +@@ -339,7 +333,6 @@ napt_ct_list_unlock(void) + uint32_t + napt_ct_list_iterate(uint32_t *hash, uint32_t *iterate) + { +- struct net *net = &init_net; + struct nf_conntrack_tuple_hash *h = NULL; + struct nf_conn *ct = NULL; + struct hlist_nulls_node *pos = (struct hlist_nulls_node *) (*iterate); +@@ -349,7 +342,7 @@ napt_ct_list_iterate(uint32_t *hash, uint32_t *iterate) + if(pos == 0) + { + /*get head for list*/ +- pos = rcu_dereference((&net->ct.hash[*hash])->first); ++ pos = rcu_dereference(hlist_nulls_first_rcu(&nf_conntrack_hash[*hash])); + } + + hlist_nulls_for_each_entry_from(h, pos, hnnode) +--- a/app/nathelper/linux/nat_ipt_helper.c ++++ b/app/nathelper/linux/nat_ipt_helper.c +@@ -534,10 +534,10 @@ nat_ipt_data_init(void) + memset(&old_replace, 0, sizeof (old_replace)); + + /*record ipt rule(SNAT) sequence for hw nat*/ +- memset(hw_nat_ipt_seq, 0, NAT_HW_NUM); ++ memset(hw_nat_ipt_seq, 0, sizeof(hw_nat_ipt_seq)); + + /*record ipt rule(SNAT) pubip index for hw nat*/ +- memset(hw_nat_pip_idx, 0, NAT_HW_NUM); ++ memset(hw_nat_pip_idx, 0, sizeof(hw_nat_pip_idx)); + } + + static void +--- a/make/linux_opt.mk ++++ b/make/linux_opt.mk +@@ -449,9 +449,6 @@ ifeq (KSLIB, $(MODULE_TYPE)) + else ifeq ($(ARCH), arm) + MODULE_INC += -I$(SYS_PATH) \ + -I$(TOOL_PATH)/../lib/gcc/$(TARGET_NAME)/$(GCC_VERSION)/include/ \ +- -I$(TOOL_PATH)/../lib/gcc/$(TARGET_NAME)/7.5.0/include/ \ +- -I$(TOOL_PATH)/../../lib/armv7a-vfp-neon-rdk-linux-gnueabi/gcc/arm-rdk-linux-gnueabi/4.8.4/include/ \ +- -I$(TOOL_PATH)/../../lib/arm-rdk-linux-musleabi/gcc/arm-rdk-linux-musleabi/6.4.0/include/ \ + -I$(SYS_PATH)/include \ + -I$(SYS_PATH)/source \ + -I$(SYS_PATH)/source/include \ diff --git a/qaa/qca-ssdk/patches/0006-fix-mdio-probe-on-ipq806x.patch b/qaa/qca-ssdk/patches/0006-fix-mdio-probe-on-ipq806x.patch new file mode 100644 index 000000000..8e802fe2a --- /dev/null +++ b/qaa/qca-ssdk/patches/0006-fix-mdio-probe-on-ipq806x.patch @@ -0,0 +1,11 @@ +--- a/src/init/ssdk_plat.c ++++ b/src/init/ssdk_plat.c +@@ -568,7 +568,7 @@ static int miibus_get(a_uint32_t dev_id) + if(reg_mode == HSL_REG_LOCAL_BUS) + mdio_node = of_find_compatible_node(NULL, NULL, "qcom,ipq40xx-mdio"); + else +- mdio_node = of_find_compatible_node(NULL, NULL, "virtual,mdio-gpio"); ++ mdio_node = of_find_compatible_node(NULL, NULL, "qcom,ipq8064-mdio"); + + if (!mdio_node) { + SSDK_ERROR("No MDIO node found in DTS!\n"); diff --git a/qaa/qca-ssdk/patches/0007-SSDK-dts-fix-of_get_mac_address.patch b/qaa/qca-ssdk/patches/0007-SSDK-dts-fix-of_get_mac_address.patch new file mode 100644 index 000000000..29be93128 --- /dev/null +++ b/qaa/qca-ssdk/patches/0007-SSDK-dts-fix-of_get_mac_address.patch @@ -0,0 +1,42 @@ +From f3a7b93137c1a6a1b8010b86296242178eed5d9e Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Fri, 13 Aug 2021 20:03:21 +0200 +Subject: [PATCH] SSDK: dts: fix of_get_mac_address() + +Recently OpenWrt backported the updated of_get_mac_address() +function which returns and error code instead. + +So, patch the SSDK to use it and fix the compilation error. + +Signed-off-by: Robert Marko +--- + src/init/ssdk_dts.c | 7 ++++--- + 1 file changed, 4 insertions(+), 3 deletions(-) + +--- a/src/init/ssdk_dts.c ++++ b/src/init/ssdk_dts.c +@@ -779,8 +779,9 @@ static void ssdk_dt_parse_intf_mac(void) + { + struct device_node *dp_node = NULL; + a_uint32_t dp = 0; +- a_uint8_t *maddr = NULL; ++ u8 maddr[ETH_ALEN]; + char dp_name[8] = {0}; ++ int ret; + + for (dp = 1; dp <= SSDK_MAX_NR_ETH; dp++) { + snprintf(dp_name, sizeof(dp_name), "dp%d", dp); +@@ -788,11 +789,11 @@ static void ssdk_dt_parse_intf_mac(void) + if (!dp_node) { + continue; + } +- maddr = (a_uint8_t *)of_get_mac_address(dp_node); ++ ret = of_get_mac_address(dp_node, maddr); + #if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0)) + if (maddr && is_valid_ether_addr(maddr)) { + #else +- if (!IS_ERR(maddr) && is_valid_ether_addr(maddr)) { ++ if (!ret && is_valid_ether_addr(maddr)) { + #endif + ssdk_dt_global.num_intf_mac++; + ether_addr_copy(ssdk_dt_global.intf_mac[dp-1].uc, maddr); diff --git a/qaa/qca-ssdk/patches/0008-add-aquantia-phy-id-113CB0.patch b/qaa/qca-ssdk/patches/0008-add-aquantia-phy-id-113CB0.patch new file mode 100644 index 000000000..69b08a819 --- /dev/null +++ b/qaa/qca-ssdk/patches/0008-add-aquantia-phy-id-113CB0.patch @@ -0,0 +1,37 @@ +From 440ab349813e5aa9dbeddab4d82ab64ff5347c5f Mon Sep 17 00:00:00 2001 +From: Dirk Buchwalder +Date: Sat, 30 Oct 2021 19:51:06 +0200 +Subject: [PATCH] add aquantia phy id 113CB0 / 0x31c31C12 + +This adds support for the AQR113C with the id +"113CB0 / 0x31c31C12" to the ssdk. + +This is used in the QNAP 301w + +Signed-off-by: Dirk Buchwalder + +--- + include/hsl/phy/hsl_phy.h | 1 + + src/hsl/phy/hsl_phy.c | 1 + + 2 files changed, 2 insertions(+) + +--- a/include/hsl/phy/hsl_phy.h ++++ b/include/hsl/phy/hsl_phy.h +@@ -579,6 +579,7 @@ typedef struct { + #define AQUANTIA_PHY_112 0x03a1b660 + #define AQUANTIA_PHY_113C_A0 0x31c31C10 + #define AQUANTIA_PHY_113C_A1 0x31c31C11 ++#define AQUANTIA_PHY_113CB0 0x31c31C12 + #define AQUANTIA_PHY_112C 0x03a1b792 + + #define PHY_805XV2 0x004DD082 +--- a/src/hsl/phy/hsl_phy.c ++++ b/src/hsl/phy/hsl_phy.c +@@ -235,6 +235,7 @@ phy_type_t hsl_phytype_get_by_phyid(a_ui + case AQUANTIA_PHY_112: + case AQUANTIA_PHY_113C_A0: + case AQUANTIA_PHY_113C_A1: ++ case AQUANTIA_PHY_113CB0: + case AQUANTIA_PHY_112C: + phytype = AQUANTIA_PHY_CHIP; + break; From 678c91253d0299a9e2ae9191fa6b230a20ac45f7 Mon Sep 17 00:00:00 2001 From: suyuan <175338101@qq.com> Date: Mon, 29 Aug 2022 01:08:33 +0800 Subject: [PATCH 06/19] update --- r8125/Makefile | 26 +- r8125/patches/010-config.patch | 22 + r8125/patches/020-5.19-support.patch | 18 + .../030-add-LED-configuration-from-OF.patch | 43 + r8152/Makefile | 10 +- r8152/patches/010-5.19-support.patch | 19 + r8168/Makefile | 25 +- ...-r8168-add-LED-configuration-from-OF.patch | 84 +- r8168/patches/020-5.18-support.patch | 47 + r8168/patches/030-5.19-support.patch | 18 + shortcut-fe/fast-classifier/Makefile | 109 + shortcut-fe/fast-classifier/src/Makefile | 10 + .../fast-classifier/src/fast-classifier.c | 2002 +++++++++ .../fast-classifier/src/fast-classifier.h | 57 + .../fast-classifier/src/nl_classifier_test.c | 281 ++ .../fast-classifier/src/userspace_example.c | 232 ++ shortcut-fe/shortcut-fe/Makefile | 88 + .../shortcut-fe/files/etc/init.d/shortcut-fe | 51 + .../shortcut-fe/files/usr/bin/sfe_dump | 35 + shortcut-fe/shortcut-fe/src/Kconfig | 14 + shortcut-fe/shortcut-fe/src/Makefile | 24 + shortcut-fe/shortcut-fe/src/sfe.h | 114 + shortcut-fe/shortcut-fe/src/sfe_backport.h | 195 + shortcut-fe/shortcut-fe/src/sfe_cm.c | 1210 ++++++ shortcut-fe/shortcut-fe/src/sfe_cm.h | 260 ++ shortcut-fe/shortcut-fe/src/sfe_ipv4.c | 3618 ++++++++++++++++ shortcut-fe/shortcut-fe/src/sfe_ipv6.c | 3625 +++++++++++++++++ shortcut-fe/simulated-driver/Makefile | 60 + .../patches/200-nss-qdisc-support.patch | 11 + upx/Makefile | 66 + 30 files changed, 12291 insertions(+), 83 deletions(-) create mode 100644 r8125/patches/010-config.patch create mode 100644 r8125/patches/020-5.19-support.patch create mode 100644 r8125/patches/030-add-LED-configuration-from-OF.patch create mode 100644 r8152/patches/010-5.19-support.patch create mode 100644 r8168/patches/020-5.18-support.patch create mode 100644 r8168/patches/030-5.19-support.patch create mode 100644 shortcut-fe/fast-classifier/Makefile create mode 100644 shortcut-fe/fast-classifier/src/Makefile create mode 100644 shortcut-fe/fast-classifier/src/fast-classifier.c create mode 100644 shortcut-fe/fast-classifier/src/fast-classifier.h create mode 100644 shortcut-fe/fast-classifier/src/nl_classifier_test.c create mode 100644 shortcut-fe/fast-classifier/src/userspace_example.c create mode 100644 shortcut-fe/shortcut-fe/Makefile create mode 100644 shortcut-fe/shortcut-fe/files/etc/init.d/shortcut-fe create mode 100644 shortcut-fe/shortcut-fe/files/usr/bin/sfe_dump create mode 100644 shortcut-fe/shortcut-fe/src/Kconfig create mode 100644 shortcut-fe/shortcut-fe/src/Makefile create mode 100644 shortcut-fe/shortcut-fe/src/sfe.h create mode 100644 shortcut-fe/shortcut-fe/src/sfe_backport.h create mode 100644 shortcut-fe/shortcut-fe/src/sfe_cm.c create mode 100644 shortcut-fe/shortcut-fe/src/sfe_cm.h create mode 100644 shortcut-fe/shortcut-fe/src/sfe_ipv4.c create mode 100644 shortcut-fe/shortcut-fe/src/sfe_ipv6.c create mode 100644 shortcut-fe/simulated-driver/Makefile create mode 100644 shortcut-fe/simulated-driver/patches/200-nss-qdisc-support.patch create mode 100644 upx/Makefile diff --git a/r8125/Makefile b/r8125/Makefile index e9b213c6e..f74b38e7c 100755 --- a/r8125/Makefile +++ b/r8125/Makefile @@ -7,10 +7,16 @@ include $(TOPDIR)/rules.mk include $(INCLUDE_DIR)/kernel.mk PKG_NAME:=r8125 -PKG_VERSION:=9.006.04 +PKG_VERSION:=9.009.02-1 PKG_RELEASE:=$(AUTORELEASE) -PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/$(PKG_NAME)-$(PKG_VERSION) +PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz +PKG_SOURCE_URL:=https://codeload.github.com/awesometic/realtek-r8125-dkms/tar.gz/$(PKG_VERSION)? +PKG_HASH:=e3f0a0a02a4ba847cb962ea7e12c89e3f4ab732944f04ebeb76d4d9711fa8ca6 +PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/realtek-$(PKG_NAME)-dkms-$(PKG_VERSION) + +PKG_LICENSE:=GPL-2.0-only +PKG_LICENSE_FILE:=LICENSE include $(INCLUDE_DIR)/package.mk @@ -18,7 +24,7 @@ define KernelPackage/r8125 TITLE:=Driver for Realtek r8125 chipsets SUBMENU:=Network Devices VERSION:=$(LINUX_VERSION)+$(PKG_VERSION)-$(BOARD)-$(PKG_RELEASE) - FILES:= $(PKG_BUILD_DIR)/r8125.ko + FILES:= $(PKG_BUILD_DIR)/src/r8125.ko AUTOLOAD:=$(call AutoProbe,r8125) endef @@ -26,20 +32,8 @@ define Package/r8125/description This package contains a driver for Realtek r8125 chipsets. endef -R8125_MAKEOPTS= -C $(PKG_BUILD_DIR) \ - PATH="$(TARGET_PATH)" \ - ARCH="$(LINUX_KARCH)" \ - CROSS_COMPILE="$(TARGET_CROSS)" \ - TARGET="$(HAL_TARGET)" \ - TOOLPREFIX="$(KERNEL_CROSS)" \ - TOOLPATH="$(KERNEL_CROSS)" \ - KERNELPATH="$(LINUX_DIR)" \ - KERNELDIR="$(LINUX_DIR)" \ - LDOPTS=" " \ - DOMULTI=1 - define Build/Compile - $(MAKE) $(R8125_MAKEOPTS) modules + +$(KERNEL_MAKE) M=$(PKG_BUILD_DIR)/src modules endef $(eval $(call KernelPackage,r8125)) diff --git a/r8125/patches/010-config.patch b/r8125/patches/010-config.patch new file mode 100644 index 000000000..e7934c01c --- /dev/null +++ b/r8125/patches/010-config.patch @@ -0,0 +1,22 @@ +--- a/src/Makefile ++++ b/src/Makefile +@@ -35,16 +35,16 @@ ENABLE_REALWOW_SUPPORT = n + ENABLE_DASH_SUPPORT = n + ENABLE_DASH_PRINTER_SUPPORT = n + CONFIG_DOWN_SPEED_100 = n +-CONFIG_ASPM = y ++CONFIG_ASPM = n + ENABLE_S5WOL = y + ENABLE_S5_KEEP_CURR_MAC = n + ENABLE_EEE = y + ENABLE_S0_MAGIC_PACKET = n + ENABLE_TX_NO_CLOSE = y +-ENABLE_MULTIPLE_TX_QUEUE = n ++ENABLE_MULTIPLE_TX_QUEUE = y + ENABLE_PTP_SUPPORT = n + ENABLE_PTP_MASTER_MODE = n +-ENABLE_RSS_SUPPORT = n ++ENABLE_RSS_SUPPORT = y + ENABLE_LIB_SUPPORT = n + ENABLE_USE_FIRMWARE_FILE = n + DISABLE_PM_SUPPORT = n diff --git a/r8125/patches/020-5.19-support.patch b/r8125/patches/020-5.19-support.patch new file mode 100644 index 000000000..481c7739e --- /dev/null +++ b/r8125/patches/020-5.19-support.patch @@ -0,0 +1,18 @@ +--- a/src/r8125_n.c ++++ b/src/r8125_n.c +@@ -116,6 +116,15 @@ + #define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw" + #define FIRMWARE_8168FP_4 "rtl_nic/rtl8168fp-4.fw" + ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0) ++static inline void netif_set_gso_max_size(struct net_device *dev, ++ unsigned int size) ++{ ++ /* dev->gso_max_size is read locklessly from sk_setup_caps() */ ++ WRITE_ONCE(dev->gso_max_size, size); ++} ++#endif ++ + /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). + The RTL chips use a 64 element hash table based on the Ethernet CRC. */ + static const int multicast_filter_limit = 32; diff --git a/r8125/patches/030-add-LED-configuration-from-OF.patch b/r8125/patches/030-add-LED-configuration-from-OF.patch new file mode 100644 index 000000000..5f6f1d29b --- /dev/null +++ b/r8125/patches/030-add-LED-configuration-from-OF.patch @@ -0,0 +1,43 @@ +--- a/src/r8125_n.c ++++ b/src/r8125_n.c +@@ -43,6 +43,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -10407,6 +10408,23 @@ rtl8125_setup_mqs_reg(struct rtl8125_private *tp) + } + } + ++static int ++rtl8125_led_configuration(struct rtl8125_private *tp) ++{ ++ u32 led_data; ++ int ret; ++ ++ ret = of_property_read_u32(tp->pci_dev->dev.of_node, ++ "realtek,led-data", &led_data); ++ ++ if (ret) ++ return ret; ++ ++ RTL_W16(tp, CustomLED, led_data); ++ ++ return 0; ++} ++ + static void + rtl8125_init_software_variable(struct net_device *dev) + { +@@ -10838,6 +10856,8 @@ rtl8125_init_software_variable(struct net_device *dev) + if (tp->InitRxDescType == RX_DESC_RING_TYPE_3) + tp->rtl8125_rx_config |= EnableRxDescV3; + ++ rtl8125_led_configuration(tp); ++ + tp->NicCustLedValue = RTL_R16(tp, CustomLED); + + tp->wol_opts = rtl8125_get_hw_wol(tp); diff --git a/r8152/Makefile b/r8152/Makefile index 9e199e273..2573b6624 100755 --- a/r8152/Makefile +++ b/r8152/Makefile @@ -7,12 +7,12 @@ include $(TOPDIR)/rules.mk include $(INCLUDE_DIR)/kernel.mk PKG_NAME:=r8152 -PKG_VERSION:=2.15.20211119 +PKG_VERSION:=2.16.1 PKG_RELEASE:=1 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz PKG_SOURCE_URL:=https://codeload.github.com/wget/realtek-r8152-linux/tar.gz/v$(PKG_VERSION)? -PKG_HASH:=b7926db3b4ca71d453ac1cf875d7a8ab409ece108edc6913e8bc1c0c3b99179d +PKG_HASH:=2be6a02f6e29485efd107bb7e777ad3c482d9db0ff7e5e6c5ef034a1557a395b PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/realtek-$(PKG_NAME)-linux-$(PKG_VERSION) @@ -23,13 +23,13 @@ PKG_MAINTAINER:=Tianling Shen include $(INCLUDE_DIR)/package.mk define KernelPackage/usb-net-rtl8152-vendor + VERSION:=$(LINUX_VERSION)+$(PKG_VERSION)-$(BOARD)-$(PKG_RELEASE) TITLE:=Kernel module for USB-to-Ethernet Realtek convertors SUBMENU:=USB Support - VERSION:=$(LINUX_VERSION)+$(PKG_VERSION)-$(BOARD)-$(PKG_RELEASE) DEPENDS:=+kmod-usb-net - CONFLICTS:=kmod-usb-net-rtl8152 - FILES:= $(PKG_BUILD_DIR)/r8152.ko + FILES:=$(PKG_BUILD_DIR)/r8152.ko AUTOLOAD:=$(call AutoProbe,r8152) + CONFLICTS:=kmod-usb-net-rtl8152 endef define KernelPackage/usb-net-rtl8152-vendor/description diff --git a/r8152/patches/010-5.19-support.patch b/r8152/patches/010-5.19-support.patch new file mode 100644 index 000000000..944e5bfcc --- /dev/null +++ b/r8152/patches/010-5.19-support.patch @@ -0,0 +1,19 @@ +--- a/r8152.c ++++ b/r8152.c +@@ -1026,6 +1026,16 @@ + #define RTL_ADVERTISED_1000_FULL BIT(5) + #define RTL_ADVERTISED_2500_FULL BIT(6) + ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0) ++static inline void netif_set_gso_max_size(struct net_device *dev, ++ unsigned int size) ++{ ++ /* dev->gso_max_size is read locklessly from sk_setup_caps() */ ++ WRITE_ONCE(dev->gso_max_size, size); ++} ++#endif ++ ++ + /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). + * The RTL chips use a 64 element hash table based on the Ethernet CRC. + */ diff --git a/r8168/Makefile b/r8168/Makefile index fd5977a5b..1258fc904 100755 --- a/r8168/Makefile +++ b/r8168/Makefile @@ -7,19 +7,16 @@ include $(TOPDIR)/rules.mk include $(INCLUDE_DIR)/kernel.mk PKG_NAME:=r8168 -PKG_VERSION:=8.049.02 -PKG_RELEASE:=$(AUTORELEAE) +PKG_VERSION:=8.050.03 +PKG_RELEASE:=$(AUTORELEASE) PKG_SOURCE_PROTO:=git PKG_SOURCE_URL:=https://github.com/BROBIRD/openwrt-r8168.git -PKG_SOURCE_DATE:=2021-10-08 -PKG_SOURCE_VERSION:=2b969c15afe403a685fc7ee069620782241e3ad6 -PKG_MIRROR_HASH:=e4632c10d460f005eff76da8a183d7ff0c8819b0d099872589b7b06a9b8d9952 +PKG_SOURCE_VERSION:=ddfaceacd1b7ed2857fb995642a8ffb1fc37e989 +PKG_MIRROR_HASH:=5428f60dc33e9503c6cfdf690c00077149dce24cbb0591129d905b9f1aad9202 PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/$(PKG_NAME)-$(PKG_VERSION) -MAKE_PATH:=src - include $(INCLUDE_DIR)/package.mk define KernelPackage/r8168 @@ -35,20 +32,8 @@ define Package/r8168/description This package contains a driver for Realtek r8168 chipsets. endef -R8168_MAKEOPTS= -C $(PKG_BUILD_DIR)/src \ - PATH="$(TARGET_PATH)" \ - ARCH="$(LINUX_KARCH)" \ - CROSS_COMPILE="$(TARGET_CROSS)" \ - TARGET="$(HAL_TARGET)" \ - TOOLPREFIX="$(KERNEL_CROSS)" \ - TOOLPATH="$(KERNEL_CROSS)" \ - KERNELPATH="$(LINUX_DIR)" \ - KERNELDIR="$(LINUX_DIR)" \ - LDOPTS=" " \ - DOMULTI=1 - define Build/Compile - $(MAKE) $(R8168_MAKEOPTS) modules + +$(KERNEL_MAKE) M=$(PKG_BUILD_DIR)/src modules endef $(eval $(call KernelPackage,r8168)) diff --git a/r8168/patches/001-r8168-add-LED-configuration-from-OF.patch b/r8168/patches/001-r8168-add-LED-configuration-from-OF.patch index 62a352dd8..f49842442 100755 --- a/r8168/patches/001-r8168-add-LED-configuration-from-OF.patch +++ b/r8168/patches/001-r8168-add-LED-configuration-from-OF.patch @@ -1,42 +1,42 @@ ---- a/src/r8168_n.c -+++ b/src/r8168_n.c -@@ -47,6 +47,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -23482,6 +23483,22 @@ rtl8168_set_bios_setting(struct net_devi - } - } - -+static int rtl8168_led_configuration(struct rtl8168_private *tp) -+{ -+ u32 led_data; -+ int ret; -+ -+ ret = of_property_read_u32(tp->pci_dev->dev.of_node, -+ "realtek,led-data", &led_data); -+ -+ if (ret) -+ return ret; -+ -+ RTL_W16(tp, CustomLED, led_data); -+ -+ return 0; -+} -+ - static void - rtl8168_init_software_variable(struct net_device *dev) - { -@@ -24000,6 +24017,8 @@ rtl8168_init_software_variable(struct ne - tp->NotWrMcuPatchCode = TRUE; - } - -+ rtl8168_led_configuration(tp); -+ - tp->NicCustLedValue = RTL_R16(tp, CustomLED); - - rtl8168_get_hw_wol(dev); +--- a/src/r8168_n.c ++++ b/src/r8168_n.c +@@ -47,6 +47,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -24643,6 +24644,22 @@ rtl8168_set_bios_setting(struct net_devi + } + } + ++static int rtl8168_led_configuration(struct rtl8168_private *tp) ++{ ++ u32 led_data; ++ int ret; ++ ++ ret = of_property_read_u32(tp->pci_dev->dev.of_node, ++ "realtek,led-data", &led_data); ++ ++ if (ret) ++ return ret; ++ ++ RTL_W16(tp, CustomLED, led_data); ++ ++ return 0; ++} ++ + static void + rtl8168_init_software_variable(struct net_device *dev) + { +@@ -25206,6 +25223,8 @@ rtl8168_init_software_variable(struct ne + tp->NotWrMcuPatchCode = TRUE; + } + ++ rtl8168_led_configuration(tp); ++ + tp->NicCustLedValue = RTL_R16(tp, CustomLED); + + rtl8168_get_hw_wol(dev); diff --git a/r8168/patches/020-5.18-support.patch b/r8168/patches/020-5.18-support.patch new file mode 100644 index 000000000..499389274 --- /dev/null +++ b/r8168/patches/020-5.18-support.patch @@ -0,0 +1,47 @@ +--- a/src/r8168_n.c ++++ b/src/r8168_n.c +@@ -3715,7 +3715,11 @@ + txd->opts2 = 0; + while (1) { + memset(tmpAddr, pattern++, len - 14); ++#if LINUX_VERSION_CODE < KERNEL_VERSION(5,18,0) + pci_dma_sync_single_for_device(tp->pci_dev, ++#else ++ dma_sync_single_for_device(tp_to_dev(tp), ++#endif + le64_to_cpu(mapping), + len, DMA_TO_DEVICE); + txd->opts1 = cpu_to_le32(DescOwn | FirstFrag | LastFrag | len); +@@ -3743,7 +3747,11 @@ + if (rx_len == len) { + dma_sync_single_for_cpu(tp_to_dev(tp), le64_to_cpu(rxd->addr), tp->rx_buf_sz, DMA_FROM_DEVICE); + i = memcmp(skb->data, rx_skb->data, rx_len); ++#if LINUX_VERSION_CODE < KERNEL_VERSION(5,18,0) + pci_dma_sync_single_for_device(tp->pci_dev, le64_to_cpu(rxd->addr), tp->rx_buf_sz, DMA_FROM_DEVICE); ++#else ++ dma_sync_single_for_device(tp_to_dev(tp), le64_to_cpu(rxd->addr), tp->rx_buf_sz, DMA_FROM_DEVICE); ++#endif + if (i == 0) { + // dev_printk(KERN_INFO, tp_to_dev(tp), "loopback test finished\n",rx_len,len); + break; +@@ -26464,11 +26472,20 @@ + + if ((sizeof(dma_addr_t) > 4) && + use_dac && ++#if LINUX_VERSION_CODE < KERNEL_VERSION(5,18,0) + !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && + !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) { ++#else ++ !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) && ++ !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) { ++#endif + dev->features |= NETIF_F_HIGHDMA; + } else { ++#if LINUX_VERSION_CODE < KERNEL_VERSION(5,18,0) + rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); ++#else ++ rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); ++#endif + if (rc < 0) { + #if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) + if (netif_msg_probe(tp)) diff --git a/r8168/patches/030-5.19-support.patch b/r8168/patches/030-5.19-support.patch new file mode 100644 index 000000000..d4dca3125 --- /dev/null +++ b/r8168/patches/030-5.19-support.patch @@ -0,0 +1,18 @@ +--- a/src/r8168_n.c ++++ b/src/r8168_n.c +@@ -116,6 +116,15 @@ + #define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw" + #define FIRMWARE_8168FP_4 "rtl_nic/rtl8168fp-4.fw" + ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0) ++static inline void netif_set_gso_max_size(struct net_device *dev, ++ unsigned int size) ++{ ++ /* dev->gso_max_size is read locklessly from sk_setup_caps() */ ++ WRITE_ONCE(dev->gso_max_size, size); ++} ++#endif ++ + /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). + The RTL chips use a 64 element hash table based on the Ethernet CRC. */ + static const int multicast_filter_limit = 32; diff --git a/shortcut-fe/fast-classifier/Makefile b/shortcut-fe/fast-classifier/Makefile new file mode 100644 index 000000000..09c1174dd --- /dev/null +++ b/shortcut-fe/fast-classifier/Makefile @@ -0,0 +1,109 @@ +# +# Copyright (c) 2013-2018 The Linux Foundation. All rights reserved. +# Permission to use, copy, modify, and/or distribute this software for +# any purpose with or without fee is hereby granted, provided that the +# above copyright notice and this permission notice appear in all copies. +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT +# OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +# + +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/kernel.mk + +PKG_NAME:=fast-classifier +PKG_RELEASE:=6 + +include $(INCLUDE_DIR)/package.mk + +define KernelPackage/fast-classifier/Default + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Support + DEPENDS:=+kmod-ipt-conntrack +kmod-shortcut-fe + TITLE:=Kernel driver for FAST Classifier + FILES:=$(PKG_BUILD_DIR)/fast-classifier.ko + KCONFIG:= \ + CONFIG_NF_CONNTRACK_EVENTS=y \ + CONFIG_NF_CONNTRACK_CHAIN_EVENTS=y \ + CONFIG_NF_CONNTRACK_MARK=y \ + CONFIG_XFRM=y + CONFLICTS:=kmod-shortcut-fe-drv kmod-shortcut-fe-cm +endef + +define KernelPackage/fast-classifier + $(call KernelPackage/fast-classifier/Default) +endef + +define KernelPackage/fast-classifier-noload + $(call KernelPackage/fast-classifier/Default) +endef + +define KernelPackage/fast-classifier/Default/description +FAST Classifier talks to SFE to make decisions about offloading connections +endef + +define KernelPackage/fast-classifier/description +$(call KernelPackage/fast-classifier/Default/description) +endef + +define KernelPackage/fast-classifier-noload/description +$(call KernelPackage/fast-classifier/Default/description) + +This package does not load fast-classifier at boot by default +endef + +define Package/fast-classifier-example + TITLE:=Example user space program for fast-classifier + DEPENDS:=+libnl +kmod-fast-classifier +endef + +define Package/fast-classifier-example/description +Example user space program that communicates with fast +classifier kernel module +endef + +HAVE_ECM:=$(CONFIG_PACKAGE_kmod-qca-nss-ecm-premium)$(CONFIG_PACKAGE_kmod-qca-nss-ecm-noload)$(CONFIG_PACKAGE_kmod-qca-nss-ecm-premium-noload)$(CONFIG_PACKAGE_kmod-qca-nss-ecm-standard) + +define Build/Compile/kmod + +$(MAKE) $(PKG_JOBS) -C "$(LINUX_DIR)" \ + $(KERNEL_MAKE_FLAGS) \ + $(PKG_MAKE_FLAGS) \ + M="$(PKG_BUILD_DIR)" \ + CONFIG_FAST_CLASSIFIER=m \ + EXTRA_CFLAGS+="-DSFE_SUPPORT_IPV6" \ + $(if $(HAVE_ECM),EXTRA_CFLAGS+="-DCONFIG_SFE_ECM" CONFIG_SFE_ECM=y,) \ + modules +endef + +define Build/Compile/example + $(TARGET_CC) -o $(PKG_BUILD_DIR)/userspace_fast_classifier \ + -I $(PKG_BUILD_DIR) \ + -I$(STAGING_DIR)/usr/include/libnl \ + -I$(STAGING_DIR)/usr/include/libnl3 \ + -lnl-genl-3 -lnl-3 \ + $(PKG_BUILD_DIR)/nl_classifier_test.c +endef + +define Build/Compile + $(Build/Compile/kmod) + $(if $(CONFIG_PACKAGE_fast-classifier-example),$(Build/Compile/example)) +endef + +define Build/InstallDev + $(INSTALL_DIR) $(1)/usr/include + $(CP) $(PKG_BUILD_DIR)/fast-classifier.h $(1)/usr/include/ +endef + +define Package/fast-classifier-example/install + $(INSTALL_DIR) $(1)/sbin + $(CP) $(PKG_BUILD_DIR)/userspace_fast_classifier $(1)/sbin/ +endef + +$(eval $(call KernelPackage,fast-classifier)) +#$(eval $(call KernelPackage,fast-classifier-noload)) +#$(eval $(call BuildPackage,fast-classifier-example)) diff --git a/shortcut-fe/fast-classifier/src/Makefile b/shortcut-fe/fast-classifier/src/Makefile new file mode 100644 index 000000000..58dd06e01 --- /dev/null +++ b/shortcut-fe/fast-classifier/src/Makefile @@ -0,0 +1,10 @@ +obj-$(CONFIG_FAST_CLASSIFIER) += fast-classifier.o + +ifeq ($(SFE_SUPPORT_IPV6),) +SFE_SUPPORT_IPV6=y +endif +ccflags-$(SFE_SUPPORT_IPV6) += -DSFE_SUPPORT_IPV6 + +ccflags-y += -I$(obj)/../shortcut-fe + +obj ?= . diff --git a/shortcut-fe/fast-classifier/src/fast-classifier.c b/shortcut-fe/fast-classifier/src/fast-classifier.c new file mode 100644 index 000000000..944dfae38 --- /dev/null +++ b/shortcut-fe/fast-classifier/src/fast-classifier.c @@ -0,0 +1,2002 @@ +/* + * fast-classifier.c + * Shortcut forwarding engine connection manager. + * fast-classifier + * + * Copyright (c) 2013-2018 The Linux Foundation. All rights reserved. + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT + * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include "fast-classifier.h" + +typedef enum fast_classifier_exception { + FAST_CL_EXCEPTION_PACKET_BROADCAST, + FAST_CL_EXCEPTION_PACKET_MULTICAST, + FAST_CL_EXCEPTION_NO_IIF, + FAST_CL_EXCEPTION_NO_CT, + FAST_CL_EXCEPTION_CT_NO_TRACK, + FAST_CL_EXCEPTION_CT_NO_CONFIRM, + FAST_CL_EXCEPTION_CT_IS_ALG, + FAST_CL_EXCEPTION_IS_IPV4_MCAST, + FAST_CL_EXCEPTION_IS_IPV6_MCAST, + FAST_CL_EXCEPTION_TCP_NOT_ASSURED, + FAST_CL_EXCEPTION_TCP_NOT_ESTABLISHED, + FAST_CL_EXCEPTION_UNKNOW_PROTOCOL, + FAST_CL_EXCEPTION_NO_SRC_DEV, + FAST_CL_EXCEPTION_NO_SRC_XLATE_DEV, + FAST_CL_EXCEPTION_NO_DEST_DEV, + FAST_CL_EXCEPTION_NO_DEST_XLATE_DEV, + FAST_CL_EXCEPTION_NO_BRIDGE, + FAST_CL_EXCEPTION_LOCAL_OUT, + FAST_CL_EXCEPTION_WAIT_FOR_ACCELERATION, + FAST_CL_EXCEPTION_UPDATE_PROTOCOL_FAIL, + FAST_CL_EXCEPTION_CT_DESTROY_MISS, + FAST_CL_EXCEPTION_MAX +} fast_classifier_exception_t; + +static char *fast_classifier_exception_events_string[FAST_CL_EXCEPTION_MAX] = { + "PACKET_BROADCAST", + "PACKET_MULTICAST", + "NO_IIF", + "NO_CT", + "CT_NO_TRACK", + "CT_NO_CONFIRM", + "CT_IS_ALG", + "IS_IPV4_MCAST", + "IS_IPV6_MCAST", + "TCP_NOT_ASSURED", + "TCP_NOT_ESTABLISHED", + "UNKNOW_PROTOCOL", + "NO_SRC_DEV", + "NO_SRC_XLATE_DEV", + "NO_DEST_DEV", + "NO_DEST_XLATE_DEV", + "NO_BRIDGE", + "LOCAL_OUT", + "WAIT_FOR_ACCELERATION", + "UPDATE_PROTOCOL_FAIL", + "CT_DESTROY_MISS", +}; + +/* + * Per-module structure. + */ +struct fast_classifier { + spinlock_t lock; /* Lock for SMP correctness */ + + /* + * Control state. + */ + struct kobject *sys_fast_classifier; /* sysfs linkage */ + + /* + * Callback notifiers. + */ + struct notifier_block dev_notifier; /* Device notifier */ + struct notifier_block inet_notifier; /* IPv4 notifier */ + struct notifier_block inet6_notifier; /* IPv6 notifier */ + u32 exceptions[FAST_CL_EXCEPTION_MAX]; +}; + +static struct fast_classifier __sc; + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 2, 0)) +static struct nla_policy fast_classifier_genl_policy[FAST_CLASSIFIER_A_MAX + 1] = { + [FAST_CLASSIFIER_A_TUPLE] = { + .type = NLA_UNSPEC, + .len = sizeof(struct fast_classifier_tuple) + }, +}; +#endif /*KERNEL_VERSION(5, 2, 0)*/ + +static struct genl_multicast_group fast_classifier_genl_mcgrp[] = { + { + .name = FAST_CLASSIFIER_GENL_MCGRP, + }, +}; + +static int fast_classifier_offload_genl_msg(struct sk_buff *skb, struct genl_info *info); +static int fast_classifier_nl_genl_msg_DUMP(struct sk_buff *skb, struct netlink_callback *cb); + +static struct genl_ops fast_classifier_gnl_ops[] = { + { + .cmd = FAST_CLASSIFIER_C_OFFLOAD, + .flags = 0, +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 2, 0)) + .policy = fast_classifier_genl_policy, +#endif /*KERNEL_VERSION(5, 2, 0)*/ + .doit = fast_classifier_offload_genl_msg, + .dumpit = NULL, + }, + { + .cmd = FAST_CLASSIFIER_C_OFFLOADED, + .flags = 0, +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 2, 0)) + .policy = fast_classifier_genl_policy, +#endif /*KERNEL_VERSION(5, 2, 0)*/ + .doit = NULL, + .dumpit = fast_classifier_nl_genl_msg_DUMP, + }, + { + .cmd = FAST_CLASSIFIER_C_DONE, + .flags = 0, +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 2, 0)) + .policy = fast_classifier_genl_policy, +#endif /*KERNEL_VERSION(5, 2, 0)*/ + .doit = NULL, + .dumpit = fast_classifier_nl_genl_msg_DUMP, + }, +}; + +static struct genl_family fast_classifier_gnl_family = { +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 10, 0)) + .id = GENL_ID_GENERATE, +#endif /*KERNEL_VERSION(4, 10, 0)*/ + .hdrsize = FAST_CLASSIFIER_GENL_HDRSIZE, + .name = FAST_CLASSIFIER_GENL_NAME, + .version = FAST_CLASSIFIER_GENL_VERSION, + .maxattr = FAST_CLASSIFIER_A_MAX, +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 10, 0)) + .ops = fast_classifier_gnl_ops, + .n_ops = ARRAY_SIZE(fast_classifier_gnl_ops), + .mcgrps = fast_classifier_genl_mcgrp, + .n_mcgrps = ARRAY_SIZE(fast_classifier_genl_mcgrp), +#endif /*KERNEL_VERSION(4, 10, 0)*/ +}; + +static atomic_t offload_msgs = ATOMIC_INIT(0); +static atomic_t offload_no_match_msgs = ATOMIC_INIT(0); +static atomic_t offloaded_msgs = ATOMIC_INIT(0); +static atomic_t done_msgs = ATOMIC_INIT(0); + +static atomic_t offloaded_fail_msgs = ATOMIC_INIT(0); +static atomic_t done_fail_msgs = ATOMIC_INIT(0); + +/* + * Accelerate incoming packets destined for bridge device + * If a incoming packet is ultimatly destined for + * a bridge device we will first see the packet coming + * from the phyiscal device, we can skip straight to + * processing the packet like it came from the bridge + * for some more performance gains + * + * This only works when the hook is above the bridge. We + * only implement ingress for now, because for egress we + * want to have the bridge devices qdiscs be used. + */ +static bool skip_to_bridge_ingress; + +/* + * fast_classifier_incr_exceptions() + * increase an exception counter. + */ +static inline void fast_classifier_incr_exceptions(fast_classifier_exception_t except) +{ + struct fast_classifier *sc = &__sc; + + spin_lock_bh(&sc->lock); + sc->exceptions[except]++; + spin_unlock_bh(&sc->lock); +} + +/* + * fast_classifier_recv() + * Handle packet receives. + * + * Returns 1 if the packet is forwarded or 0 if it isn't. + */ +int fast_classifier_recv(struct sk_buff *skb) +{ + struct net_device *dev; + struct net_device *master_dev = NULL; + int ret = 0; + + /* + * We know that for the vast majority of packets we need the transport + * layer header so we may as well start to fetch it now! + */ + prefetch(skb->data + 32); + barrier(); + + dev = skb->dev; + + /* + * Process packet like it arrived on the bridge device + */ + if (skip_to_bridge_ingress && + (dev->priv_flags & IFF_BRIDGE_PORT)) { + master_dev = sfe_dev_get_master(dev); + if (!master_dev) { + DEBUG_WARN("master dev is NULL %s\n", dev->name); + goto rx_exit; + } + dev = master_dev; + } + + /* + * We're only interested in IPv4 and IPv6 packets. + */ + if (likely(htons(ETH_P_IP) == skb->protocol)) { + struct in_device *in_dev; + + /* + * Does our input device support IP processing? + */ + in_dev = (struct in_device *)dev->ip_ptr; + if (unlikely(!in_dev)) { + DEBUG_TRACE("no IP processing for device: %s\n", dev->name); + goto rx_exit; + } + + /* + * Does it have an IP address? If it doesn't then we can't do anything + * interesting here! + */ + if (unlikely(!in_dev->ifa_list)) { + DEBUG_TRACE("no IP address for device: %s\n", dev->name); + goto rx_exit; + } + + ret = sfe_ipv4_recv(dev, skb); + + } else if (likely(htons(ETH_P_IPV6) == skb->protocol)) { + struct inet6_dev *in_dev; + + /* + * Does our input device support IPv6 processing? + */ + in_dev = (struct inet6_dev *)dev->ip6_ptr; + if (unlikely(!in_dev)) { + DEBUG_TRACE("no IPv6 processing for device: %s\n", dev->name); + goto rx_exit; + } + + /* + * Does it have an IPv6 address? If it doesn't then we can't do anything + * interesting here! + */ + if (unlikely(list_empty(&in_dev->addr_list))) { + DEBUG_TRACE("no IPv6 address for device: %s\n", dev->name); + goto rx_exit; + } + + ret = sfe_ipv6_recv(dev, skb); + + } else { + DEBUG_TRACE("not IP packet\n"); + } + +rx_exit: + if (master_dev) { + dev_put(master_dev); + } + + return ret; +} + +/* + * fast_classifier_find_dev_and_mac_addr() + * Find the device and MAC address for a given IPv4 address. + * + * Returns true if we find the device and MAC address, otherwise false. + * + * We look up the rtable entry for the address and, from its neighbour + * structure, obtain the hardware address. This means this function also + * works if the neighbours are routers too. + */ +static bool fast_classifier_find_dev_and_mac_addr(struct sk_buff *skb, sfe_ip_addr_t *addr, struct net_device **dev, u8 *mac_addr, bool is_v4) +{ + struct neighbour *neigh; + struct rtable *rt; + struct rt6_info *rt6; + struct dst_entry *dst; + struct net_device *mac_dev; + + /* + * If we have skb provided, use it as the original code is unable + * to lookup routes that are policy routed. + */ + if (unlikely(skb)) { + dst = skb_dst(skb); + goto skip_dst_lookup; + } + + /* + * Look up the rtable entry for the IP address then get the hardware + * address from its neighbour structure. This means this works when the + * neighbours are routers too. + */ + if (likely(is_v4)) { + rt = ip_route_output(&init_net, addr->ip, 0, 0, 0); + if (unlikely(IS_ERR(rt))) { + goto ret_fail; + } + + dst = (struct dst_entry *)rt; + } +#ifdef SFE_SUPPORT_IPV6 + else { +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 17, 0)) + rt6 = rt6_lookup(&init_net, (struct in6_addr *)addr->ip6, 0, 0, NULL, 0); +#else + rt6 = rt6_lookup(&init_net, (struct in6_addr *)addr->ip6, 0, 0, 0); +#endif /*KERNEL_VERSION(4, 17, 0)*/ + if (!rt6) { + goto ret_fail; + } + + dst = (struct dst_entry *)rt6; + } +#endif + +skip_dst_lookup: + rcu_read_lock(); + neigh = sfe_dst_get_neighbour(dst, addr); + if (unlikely(!neigh)) { + rcu_read_unlock(); + if (likely(!skb)) + dst_release(dst); + + goto ret_fail; + } + + if (unlikely(!(neigh->nud_state & NUD_VALID))) { + rcu_read_unlock(); + neigh_release(neigh); + if (likely(!skb)) + dst_release(dst); + + goto ret_fail; + } + + mac_dev = neigh->dev; + if (!mac_dev) { + rcu_read_unlock(); + neigh_release(neigh); + if (likely(!skb)) + dst_release(dst); + + goto ret_fail; + } + + memcpy(mac_addr, neigh->ha, (size_t)mac_dev->addr_len); + + dev_hold(mac_dev); + *dev = mac_dev; + rcu_read_unlock(); + neigh_release(neigh); + if (likely(!skb)) + dst_release(dst); + + return true; + +ret_fail: + if (is_v4) { + DEBUG_TRACE("failed to find MAC address for IP: %pI4\n", addr); + + } else { + DEBUG_TRACE("failed to find MAC address for IP: %pI6\n", addr); + } + + return false; +} + +static DEFINE_SPINLOCK(sfe_connections_lock); + +struct sfe_connection { + struct hlist_node hl; + struct sfe_connection_create *sic; + struct nf_conn *ct; + int hits; + int offload_permit; + int offloaded; + bool is_v4; + unsigned char smac[ETH_ALEN]; + unsigned char dmac[ETH_ALEN]; +}; + +static int sfe_connections_size; + +#define FC_CONN_HASH_ORDER 13 +static DEFINE_HASHTABLE(fc_conn_ht, FC_CONN_HASH_ORDER); + +static u32 fc_conn_hash(sfe_ip_addr_t *saddr, sfe_ip_addr_t *daddr, + unsigned short sport, unsigned short dport, bool is_v4) +{ + u32 idx, cnt = ((is_v4 ? sizeof(saddr->ip) : sizeof(saddr->ip6))/sizeof(u32)); + u32 hash = 0; + + for (idx = 0; idx < cnt; idx++) { + hash ^= ((u32 *)saddr)[idx] ^ ((u32 *)daddr)[idx]; + } + + return hash ^ (sport | (dport << 16)); +} + +/* + * fast_classifier_update_protocol() + * Update sfe_ipv4_create struct with new protocol information before we offload + */ +static int fast_classifier_update_protocol(struct sfe_connection_create *p_sic, struct nf_conn *ct) +{ + #if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0) + struct net *net=NULL ; + struct nf_tcp_net *tn=NULL; + #endif + switch (p_sic->protocol) { + case IPPROTO_TCP: + p_sic->src_td_window_scale = ct->proto.tcp.seen[0].td_scale; + p_sic->src_td_max_window = ct->proto.tcp.seen[0].td_maxwin; + p_sic->src_td_end = ct->proto.tcp.seen[0].td_end; + p_sic->src_td_max_end = ct->proto.tcp.seen[0].td_maxend; + p_sic->dest_td_window_scale = ct->proto.tcp.seen[1].td_scale; + p_sic->dest_td_max_window = ct->proto.tcp.seen[1].td_maxwin; + p_sic->dest_td_end = ct->proto.tcp.seen[1].td_end; + p_sic->dest_td_max_end = ct->proto.tcp.seen[1].td_maxend; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0) + net = nf_ct_net(ct); + tn = nf_tcp_pernet(net); + if ((tn&&tn->tcp_no_window_check) +#else + if (nf_ct_tcp_no_window_check +#endif + + || (ct->proto.tcp.seen[0].flags & IP_CT_TCP_FLAG_BE_LIBERAL) + || (ct->proto.tcp.seen[1].flags & IP_CT_TCP_FLAG_BE_LIBERAL)) { + p_sic->flags |= SFE_CREATE_FLAG_NO_SEQ_CHECK; + } + + /* + * If the connection is shutting down do not manage it. + * state can not be SYN_SENT, SYN_RECV because connection is assured + * Not managed states: FIN_WAIT, CLOSE_WAIT, LAST_ACK, TIME_WAIT, CLOSE. + */ + spin_lock(&ct->lock); + if (ct->proto.tcp.state != TCP_CONNTRACK_ESTABLISHED) { + spin_unlock(&ct->lock); + fast_classifier_incr_exceptions(FAST_CL_EXCEPTION_TCP_NOT_ESTABLISHED); + DEBUG_TRACE("connection in termination state: %#x, s: %pI4:%u, d: %pI4:%u\n", + ct->proto.tcp.state, &p_sic->src_ip, ntohs(p_sic->src_port), + &p_sic->dest_ip, ntohs(p_sic->dest_port)); + return 0; + } + spin_unlock(&ct->lock); + break; + + case IPPROTO_UDP: + break; + + default: + fast_classifier_incr_exceptions(FAST_CL_EXCEPTION_UNKNOW_PROTOCOL); + DEBUG_TRACE("unhandled protocol %d\n", p_sic->protocol); + return 0; + } + + return 1; +} + +/* fast_classifier_send_genl_msg() + * Function to send a generic netlink message + */ +static void fast_classifier_send_genl_msg(int msg, struct fast_classifier_tuple *fc_msg) +{ + struct sk_buff *skb; + int rc; + int buf_len; + int total_len; + void *msg_head; + + /* + * Calculate our packet payload size. + * Start with our family header. + */ + buf_len = fast_classifier_gnl_family.hdrsize; + + /* + * Add the nla_total_size of each attribute we're going to nla_put(). + */ + buf_len += nla_total_size(sizeof(*fc_msg)); + + /* + * Lastly we need to add space for the NL message header since + * genlmsg_new only accounts for the GENL header and not the + * outer NL header. To do this, we use a NL helper function which + * calculates the total size of a netlink message given a payload size. + * Note this value does not include the GENL header, but that's + * added automatically by genlmsg_new. + */ + total_len = nlmsg_total_size(buf_len); + skb = genlmsg_new(total_len, GFP_ATOMIC); + if (!skb) + return; + + msg_head = genlmsg_put(skb, 0, 0, &fast_classifier_gnl_family, 0, msg); + if (!msg_head) { + nlmsg_free(skb); + return; + } + + rc = nla_put(skb, FAST_CLASSIFIER_A_TUPLE, sizeof(struct fast_classifier_tuple), fc_msg); + if (rc != 0) { + genlmsg_cancel(skb, msg_head); + nlmsg_free(skb); + return; + } + +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(3, 19 , 0)) + rc = genlmsg_end(skb, msg_head); + if (rc < 0) { + genlmsg_cancel(skb, msg_head); + nlmsg_free(skb); + return; + } +#else + genlmsg_end(skb, msg_head); + +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 13, 0)) + rc = genlmsg_multicast(&fast_classifier_gnl_family, skb, 0, 0, GFP_ATOMIC); +#else + rc = genlmsg_multicast(skb, 0, fast_classifier_genl_mcgrp[0].id, GFP_ATOMIC); +#endif + switch (msg) { + case FAST_CLASSIFIER_C_OFFLOADED: + if (rc == 0) { + atomic_inc(&offloaded_msgs); + } else { + atomic_inc(&offloaded_fail_msgs); + } + break; + case FAST_CLASSIFIER_C_DONE: + if (rc == 0) { + atomic_inc(&done_msgs); + } else { + atomic_inc(&done_fail_msgs); + } + break; + default: + DEBUG_ERROR("fast-classifer: Unknown message type sent!\n"); + break; + } + + DEBUG_TRACE("Notify NL message %d ", msg); + if (fc_msg->ethertype == AF_INET) { + DEBUG_TRACE("sip=%pI4 dip=%pI4 ", &fc_msg->src_saddr, &fc_msg->dst_saddr); + } else { + DEBUG_TRACE("sip=%pI6 dip=%pI6 ", &fc_msg->src_saddr, &fc_msg->dst_saddr); + } + DEBUG_TRACE("protocol=%d sport=%d dport=%d smac=%pM dmac=%pM\n", + fc_msg->proto, fc_msg->sport, fc_msg->dport, fc_msg->smac, fc_msg->dmac); +} + +/* + * fast_classifier_find_conn() + * find a connection object in the hash table + * @pre the sfe_connection_lock must be held before calling this function + */ +static struct sfe_connection * +fast_classifier_find_conn(sfe_ip_addr_t *saddr, sfe_ip_addr_t *daddr, + unsigned short sport, unsigned short dport, + unsigned char proto, bool is_v4) +{ + struct sfe_connection_create *p_sic; + struct sfe_connection *conn; + u32 key; +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 9, 0)) + struct hlist_node *node; +#endif + + key = fc_conn_hash(saddr, daddr, sport, dport, is_v4); + + sfe_hash_for_each_possible(fc_conn_ht, conn, node, hl, key) { + if (conn->is_v4 != is_v4) { + continue; + } + + p_sic = conn->sic; + + if (p_sic->protocol == proto && + p_sic->src_port == sport && + p_sic->dest_port == dport && + sfe_addr_equal(&p_sic->src_ip, saddr, is_v4) && + sfe_addr_equal(&p_sic->dest_ip, daddr, is_v4)) { + return conn; + } + } + + DEBUG_TRACE("connection not found\n"); + return NULL; +} + +/* + * fast_classifier_sb_find_conn() + * find a connection object in the hash table according to information of packet + * if not found, reverse the tuple and try again. + * @pre the sfe_connection_lock must be held before calling this function + */ +static struct sfe_connection * +fast_classifier_sb_find_conn(sfe_ip_addr_t *saddr, sfe_ip_addr_t *daddr, + unsigned short sport, unsigned short dport, + unsigned char proto, bool is_v4) +{ + struct sfe_connection_create *p_sic; + struct sfe_connection *conn; + u32 key; +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 9, 0)) + struct hlist_node *node; +#endif + + key = fc_conn_hash(saddr, daddr, sport, dport, is_v4); + + sfe_hash_for_each_possible(fc_conn_ht, conn, node, hl, key) { + if (conn->is_v4 != is_v4) { + continue; + } + + p_sic = conn->sic; + + if (p_sic->protocol == proto && + p_sic->src_port == sport && + p_sic->dest_port_xlate == dport && + sfe_addr_equal(&p_sic->src_ip, saddr, is_v4) && + sfe_addr_equal(&p_sic->dest_ip_xlate, daddr, is_v4)) { + return conn; + } + } + + /* + * Reverse the tuple and try again + */ + key = fc_conn_hash(daddr, saddr, dport, sport, is_v4); + + sfe_hash_for_each_possible(fc_conn_ht, conn, node, hl, key) { + if (conn->is_v4 != is_v4) { + continue; + } + + p_sic = conn->sic; + + if (p_sic->protocol == proto && + p_sic->src_port == dport && + p_sic->dest_port_xlate == sport && + sfe_addr_equal(&p_sic->src_ip, daddr, is_v4) && + sfe_addr_equal(&p_sic->dest_ip_xlate, saddr, is_v4)) { + return conn; + } + } + + DEBUG_TRACE("connection not found\n"); + return NULL; +} + +/* + * fast_classifier_add_conn() + * add a connection object in the hash table if no duplicate + * @conn connection to add + * @return conn if successful, NULL if duplicate + */ +static struct sfe_connection * +fast_classifier_add_conn(struct sfe_connection *conn) +{ + struct sfe_connection_create *sic = conn->sic; + u32 key; + + spin_lock_bh(&sfe_connections_lock); + if (fast_classifier_find_conn(&sic->src_ip, &sic->dest_ip, sic->src_port, + sic->dest_port, sic->protocol, conn->is_v4)) { + spin_unlock_bh(&sfe_connections_lock); + return NULL; + } + + key = fc_conn_hash(&sic->src_ip, &sic->dest_ip, + sic->src_port, sic->dest_port, conn->is_v4); + + hash_add(fc_conn_ht, &conn->hl, key); + sfe_connections_size++; + spin_unlock_bh(&sfe_connections_lock); + + DEBUG_TRACE(" -> adding item to sfe_connections, new size: %d\n", sfe_connections_size); + + if (conn->is_v4) { + DEBUG_TRACE("new offloadable: key: %u proto: %d src_ip: %pI4 dst_ip: %pI4, src_port: %d, dst_port: %d\n", + key, sic->protocol, &(sic->src_ip), &(sic->dest_ip), sic->src_port, sic->dest_port); + } else { + DEBUG_TRACE("new offloadable: key: %u proto: %d src_ip: %pI6 dst_ip: %pI6, src_port: %d, dst_port: %d\n", + key, sic->protocol, &(sic->src_ip), &(sic->dest_ip), sic->src_port, sic->dest_port); + } + + return conn; +} + +/* + * fast_classifier_offload_genl_msg() + * Called from user space to offload a connection + */ +static int +fast_classifier_offload_genl_msg(struct sk_buff *skb, struct genl_info *info) +{ + struct nlattr *na; + struct fast_classifier_tuple *fc_msg; + struct sfe_connection *conn; + + na = info->attrs[FAST_CLASSIFIER_A_TUPLE]; + fc_msg = nla_data(na); + + if (fc_msg->ethertype == AF_INET) { + DEBUG_TRACE("want to offload: %d-%d, %pI4, %pI4, %d, %d SMAC=%pM DMAC=%pM\n", + fc_msg->ethertype, + fc_msg->proto, + &fc_msg->src_saddr, + &fc_msg->dst_saddr, + fc_msg->sport, + fc_msg->dport, + fc_msg->smac, + fc_msg->dmac); + } else { + DEBUG_TRACE("want to offload: %d-%d, %pI6, %pI6, %d, %d SMAC=%pM DMAC=%pM\n", + fc_msg->ethertype, + fc_msg->proto, + &fc_msg->src_saddr, + &fc_msg->dst_saddr, + fc_msg->sport, + fc_msg->dport, + fc_msg->smac, + fc_msg->dmac); + } + + spin_lock_bh(&sfe_connections_lock); + conn = fast_classifier_sb_find_conn((sfe_ip_addr_t *)&fc_msg->src_saddr, + (sfe_ip_addr_t *)&fc_msg->dst_saddr, + fc_msg->sport, + fc_msg->dport, + fc_msg->proto, + (fc_msg->ethertype == AF_INET)); + if (!conn) { + spin_unlock_bh(&sfe_connections_lock); + DEBUG_TRACE("REQUEST OFFLOAD NO MATCH\n"); + atomic_inc(&offload_no_match_msgs); + return 0; + } + + conn->offload_permit = 1; + spin_unlock_bh(&sfe_connections_lock); + atomic_inc(&offload_msgs); + + DEBUG_TRACE("INFO: calling sfe rule creation!\n"); + return 0; +} + +/* + * fast_classifier_nl_genl_msg_DUMP() + * ignore fast_classifier_messages OFFLOADED and DONE + */ +static int fast_classifier_nl_genl_msg_DUMP(struct sk_buff *skb, + struct netlink_callback *cb) +{ + return 0; +} + +/* auto offload connection once we have this many packets*/ +static int offload_at_pkts = 128; + +/* + * fast_classifier_post_routing() + * Called for packets about to leave the box - either locally generated or forwarded from another interface + */ +static unsigned int fast_classifier_post_routing(struct sk_buff *skb, bool is_v4) +{ + int ret; + struct sfe_connection_create sic; + struct sfe_connection_create *p_sic; + struct net_device *in; + struct nf_conn *ct; + enum ip_conntrack_info ctinfo; + struct net_device *dev; + struct net_device *src_dev; + struct net_device *dest_dev; + struct net_device *src_dev_tmp; + struct net_device *dest_dev_tmp; + struct net_device *src_br_dev = NULL; + struct net_device *dest_br_dev = NULL; + struct nf_conntrack_tuple orig_tuple; + struct nf_conntrack_tuple reply_tuple; + struct sfe_connection *conn; + struct sk_buff *tmp_skb = NULL; + + /* + * Don't process broadcast or multicast packets. + */ + if (unlikely(skb->pkt_type == PACKET_BROADCAST)) { + fast_classifier_incr_exceptions(FAST_CL_EXCEPTION_PACKET_BROADCAST); + DEBUG_TRACE("broadcast, ignoring\n"); + return NF_ACCEPT; + } + if (unlikely(skb->pkt_type == PACKET_MULTICAST)) { + fast_classifier_incr_exceptions(FAST_CL_EXCEPTION_PACKET_MULTICAST); + DEBUG_TRACE("multicast, ignoring\n"); + return NF_ACCEPT; + } + + /* + * Don't process packets that are not being forwarded. + */ + in = dev_get_by_index(&init_net, skb->skb_iif); + if (!in) { + fast_classifier_incr_exceptions(FAST_CL_EXCEPTION_NO_IIF); + DEBUG_TRACE("packet not forwarding\n"); + return NF_ACCEPT; + } + + dev_put(in); + + /* + * Don't process packets that aren't being tracked by conntrack. + */ + ct = nf_ct_get(skb, &ctinfo); + if (unlikely(!ct)) { + fast_classifier_incr_exceptions(FAST_CL_EXCEPTION_NO_CT); + DEBUG_TRACE("no conntrack connection, ignoring\n"); + return NF_ACCEPT; + } + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 12, 0)) + /* + * Don't process untracked connections. + */ + if (unlikely(nf_ct_is_untracked(ct))) { + fast_classifier_incr_exceptions(FAST_CL_EXCEPTION_CT_NO_TRACK); + DEBUG_TRACE("untracked connection\n"); + return NF_ACCEPT; + } +#endif /*KERNEL_VERSION(4, 12, 0)*/ + + /* + * Unconfirmed connection may be dropped by Linux at the final step, + * So we don't process unconfirmed connections. + */ + if (!nf_ct_is_confirmed(ct)) { + fast_classifier_incr_exceptions(FAST_CL_EXCEPTION_CT_NO_CONFIRM); + DEBUG_TRACE("unconfirmed connection\n"); + return NF_ACCEPT; + } + + /* + * Don't process connections that require support from a 'helper' (typically a NAT ALG). + */ + if (unlikely(nfct_help(ct))) { + fast_classifier_incr_exceptions(FAST_CL_EXCEPTION_CT_IS_ALG); + DEBUG_TRACE("connection has helper\n"); + return NF_ACCEPT; + } + + memset(&sic, 0, sizeof(sic)); + + /* + * Look up the details of our connection in conntrack. + * + * Note that the data we get from conntrack is for the "ORIGINAL" direction + * but our packet may actually be in the "REPLY" direction. + */ + orig_tuple = ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple; + reply_tuple = ct->tuplehash[IP_CT_DIR_REPLY].tuple; + sic.protocol = (s32)orig_tuple.dst.protonum; + + sic.flags = 0; + + /* + * Get addressing information, non-NAT first + */ + if (likely(is_v4)) { + u32 dscp; + + sic.src_ip.ip = (__be32)orig_tuple.src.u3.ip; + sic.dest_ip.ip = (__be32)orig_tuple.dst.u3.ip; + + if (ipv4_is_multicast(sic.src_ip.ip) || ipv4_is_multicast(sic.dest_ip.ip)) { + fast_classifier_incr_exceptions(FAST_CL_EXCEPTION_IS_IPV4_MCAST); + DEBUG_TRACE("multicast address\n"); + return NF_ACCEPT; + } + + /* + * NAT'ed addresses - note these are as seen from the 'reply' direction + * When NAT does not apply to this connection these will be identical to the above. + */ + sic.src_ip_xlate.ip = (__be32)reply_tuple.dst.u3.ip; + sic.dest_ip_xlate.ip = (__be32)reply_tuple.src.u3.ip; + + dscp = ipv4_get_dsfield(ip_hdr(skb)) >> XT_DSCP_SHIFT; + if (dscp) { + sic.dest_dscp = dscp; + sic.src_dscp = sic.dest_dscp; + sic.flags |= SFE_CREATE_FLAG_REMARK_DSCP; + } + } else { + u32 dscp; + + sic.src_ip.ip6[0] = *((struct sfe_ipv6_addr *)&orig_tuple.src.u3.in6); + sic.dest_ip.ip6[0] = *((struct sfe_ipv6_addr *)&orig_tuple.dst.u3.in6); + + if (ipv6_addr_is_multicast((struct in6_addr *)sic.src_ip.ip6) || + ipv6_addr_is_multicast((struct in6_addr *)sic.dest_ip.ip6)) { + fast_classifier_incr_exceptions(FAST_CL_EXCEPTION_IS_IPV6_MCAST); + DEBUG_TRACE("multicast address\n"); + return NF_ACCEPT; + } + + /* + * NAT'ed addresses - note these are as seen from the 'reply' direction + * When NAT does not apply to this connection these will be identical to the above. + */ + sic.src_ip_xlate.ip6[0] = *((struct sfe_ipv6_addr *)&reply_tuple.dst.u3.in6); + sic.dest_ip_xlate.ip6[0] = *((struct sfe_ipv6_addr *)&reply_tuple.src.u3.in6); + + dscp = ipv6_get_dsfield(ipv6_hdr(skb)) >> XT_DSCP_SHIFT; + if (dscp) { + sic.dest_dscp = dscp; + sic.src_dscp = sic.dest_dscp; + sic.flags |= SFE_CREATE_FLAG_REMARK_DSCP; + } + } + + switch (sic.protocol) { + case IPPROTO_TCP: + sic.src_port = orig_tuple.src.u.tcp.port; + sic.dest_port = orig_tuple.dst.u.tcp.port; + sic.src_port_xlate = reply_tuple.dst.u.tcp.port; + sic.dest_port_xlate = reply_tuple.src.u.tcp.port; + + /* + * Don't try to manage a non-established connection. + */ + if (!test_bit(IPS_ASSURED_BIT, &ct->status)) { + fast_classifier_incr_exceptions(FAST_CL_EXCEPTION_TCP_NOT_ASSURED); + DEBUG_TRACE("non-established connection\n"); + return NF_ACCEPT; + } + + break; + + case IPPROTO_UDP: + sic.src_port = orig_tuple.src.u.udp.port; + sic.dest_port = orig_tuple.dst.u.udp.port; + sic.src_port_xlate = reply_tuple.dst.u.udp.port; + sic.dest_port_xlate = reply_tuple.src.u.udp.port; + + /* + * Somehow, SFE is not playing nice with IPSec traffic. + * Do not accelerate for now. + */ + if (ntohs(sic.dest_port) == 4500 || ntohs(sic.dest_port) == 500) { + if (likely(is_v4)) + DEBUG_TRACE("quarkysg:: IPsec bypass: %pI4:%d(%pI4:%d) to %pI4:%d(%pI4:%d)\n", + &sic.src_ip.ip, ntohs(sic.src_port), &sic.src_ip_xlate.ip, ntohs(sic.src_port_xlate), + &sic.dest_ip.ip, ntohs(sic.dest_port), &sic.dest_ip_xlate.ip, ntohs(sic.dest_port_xlate)); + else + DEBUG_TRACE("quarkysg:: IPsec bypass: %pI6:%d to %pI6:%d\n", + &sic.src_ip.ip6, ntohs(sic.src_port), &sic.dest_ip.ip6, ntohs(sic.dest_port)); + return NF_ACCEPT; + } + break; + + default: + fast_classifier_incr_exceptions(FAST_CL_EXCEPTION_UNKNOW_PROTOCOL); + DEBUG_TRACE("unhandled protocol %d\n", sic.protocol); + return NF_ACCEPT; + } + +#ifdef CONFIG_XFRM + sic.original_accel = 1; + sic.reply_accel = 1; +#endif + + /* + * Get QoS information + */ + if (skb->priority) { + sic.dest_priority = skb->priority; + sic.src_priority = sic.dest_priority; + sic.flags |= SFE_CREATE_FLAG_REMARK_PRIORITY; + } + + if (is_v4) { + DEBUG_TRACE("POST_ROUTE: checking new connection: %d src_ip: %pI4 dst_ip: %pI4, src_port: %d, dst_port: %d\n", + sic.protocol, &sic.src_ip, &sic.dest_ip, sic.src_port, sic.dest_port); + } else { + DEBUG_TRACE("POST_ROUTE: checking new connection: %d src_ip: %pI6 dst_ip: %pI6, src_port: %d, dst_port: %d\n", + sic.protocol, &sic.src_ip, &sic.dest_ip, sic.src_port, sic.dest_port); + } + + /* + * If we already have this connection in our list, skip it + * XXX: this may need to be optimized + */ + spin_lock_bh(&sfe_connections_lock); + + conn = fast_classifier_find_conn(&sic.src_ip, &sic.dest_ip, sic.src_port, sic.dest_port, sic.protocol, is_v4); + if (conn) { + conn->hits++; + + if (!conn->offloaded) { + if (conn->offload_permit || conn->hits >= offload_at_pkts) { + DEBUG_TRACE("OFFLOADING CONNECTION, TOO MANY HITS\n"); + + if (fast_classifier_update_protocol(conn->sic, conn->ct) == 0) { + spin_unlock_bh(&sfe_connections_lock); + fast_classifier_incr_exceptions(FAST_CL_EXCEPTION_UPDATE_PROTOCOL_FAIL); + DEBUG_TRACE("UNKNOWN PROTOCOL OR CONNECTION CLOSING, SKIPPING\n"); + return NF_ACCEPT; + } + + DEBUG_TRACE("INFO: calling sfe rule creation!\n"); + spin_unlock_bh(&sfe_connections_lock); + + ret = is_v4 ? sfe_ipv4_create_rule(conn->sic) : sfe_ipv6_create_rule(conn->sic); + if ((ret == 0) || (ret == -EADDRINUSE)) { + struct fast_classifier_tuple fc_msg; + + if (is_v4) { + fc_msg.ethertype = AF_INET; + fc_msg.src_saddr.in = *((struct in_addr *)&sic.src_ip); + fc_msg.dst_saddr.in = *((struct in_addr *)&sic.dest_ip_xlate); + } else { + fc_msg.ethertype = AF_INET6; + fc_msg.src_saddr.in6 = *((struct in6_addr *)&sic.src_ip); + fc_msg.dst_saddr.in6 = *((struct in6_addr *)&sic.dest_ip_xlate); + } + + fc_msg.proto = sic.protocol; + fc_msg.sport = sic.src_port; + fc_msg.dport = sic.dest_port_xlate; + memcpy(fc_msg.smac, conn->smac, ETH_ALEN); + memcpy(fc_msg.dmac, conn->dmac, ETH_ALEN); + fast_classifier_send_genl_msg(FAST_CLASSIFIER_C_OFFLOADED, &fc_msg); + conn->offloaded = 1; + } + + return NF_ACCEPT; + } + } + + spin_unlock_bh(&sfe_connections_lock); + if (conn->offloaded) { + is_v4 ? sfe_ipv4_update_rule(conn->sic) : sfe_ipv6_update_rule(conn->sic); + } + + DEBUG_TRACE("FOUND, SKIPPING\n"); + fast_classifier_incr_exceptions(FAST_CL_EXCEPTION_WAIT_FOR_ACCELERATION); + return NF_ACCEPT; + } + + spin_unlock_bh(&sfe_connections_lock); + + /* + * Get the net device and MAC addresses that correspond to the various source and + * destination host addresses. + */ + if (!fast_classifier_find_dev_and_mac_addr(NULL, &sic.src_ip, &src_dev_tmp, sic.src_mac, is_v4)) { + fast_classifier_incr_exceptions(FAST_CL_EXCEPTION_NO_SRC_DEV); + return NF_ACCEPT; + } + src_dev = src_dev_tmp; + + if (!fast_classifier_find_dev_and_mac_addr(NULL, &sic.src_ip_xlate, &dev, sic.src_mac_xlate, is_v4)) { + fast_classifier_incr_exceptions(FAST_CL_EXCEPTION_NO_SRC_XLATE_DEV); + goto done1; + } + dev_put(dev); + + if (unlikely(!is_v4)) + tmp_skb = skb; + + if (!fast_classifier_find_dev_and_mac_addr(tmp_skb, &sic.dest_ip, &dev, sic.dest_mac, is_v4)) { + fast_classifier_incr_exceptions(FAST_CL_EXCEPTION_NO_DEST_DEV); + goto done1; + } + dev_put(dev); + + if (!fast_classifier_find_dev_and_mac_addr(skb, &sic.dest_ip_xlate, &dest_dev_tmp, sic.dest_mac_xlate, is_v4)) { + fast_classifier_incr_exceptions(FAST_CL_EXCEPTION_NO_DEST_XLATE_DEV); + goto done1; + } + dest_dev = dest_dev_tmp; + + /* + * Our devices may actually be part of a bridge interface. If that's + * the case then find the bridge interface instead. + */ + if (src_dev->priv_flags & IFF_BRIDGE_PORT) { + src_br_dev = sfe_dev_get_master(src_dev); + if (!src_br_dev) { + fast_classifier_incr_exceptions(FAST_CL_EXCEPTION_NO_BRIDGE); + DEBUG_TRACE("no bridge found for: %s\n", src_dev->name); + goto done2; + } + src_dev = src_br_dev; + } + + if (dest_dev->priv_flags & IFF_BRIDGE_PORT) { + dest_br_dev = sfe_dev_get_master(dest_dev); + if (!dest_br_dev) { + fast_classifier_incr_exceptions(FAST_CL_EXCEPTION_NO_BRIDGE); + DEBUG_TRACE("no bridge found for: %s\n", dest_dev->name); + goto done3; + } + dest_dev = dest_br_dev; + } + + sic.src_dev = src_dev; + sic.dest_dev = dest_dev; + + sic.src_mtu = src_dev->mtu; + sic.dest_mtu = dest_dev->mtu; + + if (skb->mark) { + DEBUG_TRACE("SKB MARK NON ZERO %x\n", skb->mark); + } + sic.mark = skb->mark; + + conn = kmalloc(sizeof(*conn), GFP_ATOMIC); + if (!conn) { + printk(KERN_CRIT "ERROR: no memory for sfe\n"); + goto done4; + } + conn->hits = 0; + conn->offload_permit = 0; + conn->offloaded = 0; + conn->is_v4 = is_v4; + DEBUG_TRACE("Source MAC=%pM\n", sic.src_mac); + memcpy(conn->smac, sic.src_mac, ETH_ALEN); + memcpy(conn->dmac, sic.dest_mac_xlate, ETH_ALEN); + + p_sic = kmalloc(sizeof(*p_sic), GFP_ATOMIC); + if (!p_sic) { + printk(KERN_CRIT "ERROR: no memory for sfe\n"); + kfree(conn); + goto done4; + } + + memcpy(p_sic, &sic, sizeof(sic)); + conn->sic = p_sic; + conn->ct = ct; + + if (!fast_classifier_add_conn(conn)) { + kfree(conn->sic); + kfree(conn); + } + + /* + * If we had bridge ports then release them too. + */ +done4: + if (dest_br_dev) { + dev_put(dest_br_dev); + } +done3: + if (src_br_dev) { + dev_put(src_br_dev); + } +done2: + dev_put(dest_dev_tmp); +done1: + dev_put(src_dev_tmp); + + return NF_ACCEPT; +} + +/* + * fast_classifier_ipv4_post_routing_hook() + * Called for packets about to leave the box - either locally generated or forwarded from another interface + */ +fast_classifier_ipv4_post_routing_hook(hooknum, ops, skb, in_unused, out, okfn) +{ + return fast_classifier_post_routing(skb, true); +} + +/* + * fast_classifier_ipv6_post_routing_hook() + * Called for packets about to leave the box - either locally generated or forwarded from another interface + */ +fast_classifier_ipv6_post_routing_hook(hooknum, ops, skb, in_unused, out, okfn) +{ + return fast_classifier_post_routing(skb, false); +} + +/* + * fast_classifier_update_mark() + * updates the mark for a fast-classifier connection + */ +static void fast_classifier_update_mark(struct sfe_connection_mark *mark, bool is_v4) +{ + struct sfe_connection *conn; + + spin_lock_bh(&sfe_connections_lock); + + conn = fast_classifier_find_conn(&mark->src_ip, &mark->dest_ip, + mark->src_port, mark->dest_port, + mark->protocol, is_v4); + if (conn) { + conn->sic->mark = mark->mark; + } + + spin_unlock_bh(&sfe_connections_lock); +} + +#ifdef CONFIG_NF_CONNTRACK_EVENTS +/* + * fast_classifier_conntrack_event() + * Callback event invoked when a conntrack connection's state changes. + */ +#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS +static int fast_classifier_conntrack_event(struct notifier_block *this, + unsigned long events, void *ptr) +#else +static int fast_classifier_conntrack_event(unsigned int events, struct nf_ct_event *item) +#endif +{ +#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS + struct nf_ct_event *item = ptr; +#endif + struct sfe_connection_destroy sid; + struct nf_conn *ct = item->ct; + struct nf_conntrack_tuple orig_tuple; + struct sfe_connection *conn; + struct fast_classifier_tuple fc_msg; + int offloaded = 0; + bool is_v4; + + /* + * If we don't have a conntrack entry then we're done. + */ + if (unlikely(!ct)) { + DEBUG_WARN("no ct in conntrack event callback\n"); + return NOTIFY_DONE; + } + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 12, 0)) + /* + * If this is an untracked connection then we can't have any state either. + */ + if (unlikely(nf_ct_is_untracked(ct))) { + DEBUG_TRACE("ignoring untracked conn\n"); + return NOTIFY_DONE; + } +#endif /*KERNEL_VERSION(4, 12, 0)*/ + + orig_tuple = ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple; + sid.protocol = (s32)orig_tuple.dst.protonum; + + /* + * Extract information from the conntrack connection. We're only interested + * in nominal connection information (i.e. we're ignoring any NAT information). + */ + if (likely(nf_ct_l3num(ct) == AF_INET)) { + sid.src_ip.ip = (__be32)orig_tuple.src.u3.ip; + sid.dest_ip.ip = (__be32)orig_tuple.dst.u3.ip; + is_v4 = true; + } else if (likely(nf_ct_l3num(ct) == AF_INET6)) { + sid.src_ip.ip6[0] = *((struct sfe_ipv6_addr *)&orig_tuple.src.u3.in6); + sid.dest_ip.ip6[0] = *((struct sfe_ipv6_addr *)&orig_tuple.dst.u3.in6); + is_v4 = false; + } else { + DEBUG_TRACE("ignoring non-IPv4 and non-IPv6 connection\n"); + return NOTIFY_DONE; + } + + switch (sid.protocol) { + case IPPROTO_TCP: + sid.src_port = orig_tuple.src.u.tcp.port; + sid.dest_port = orig_tuple.dst.u.tcp.port; + break; + + case IPPROTO_UDP: + sid.src_port = orig_tuple.src.u.udp.port; + sid.dest_port = orig_tuple.dst.u.udp.port; + break; + + default: + DEBUG_TRACE("unhandled protocol: %d\n", sid.protocol); + return NOTIFY_DONE; + } + + /* + * Check for an updated mark + */ + if ((events & (1 << IPCT_MARK)) && (ct->mark != 0)) { + struct sfe_connection_mark mark; + + mark.protocol = sid.protocol; + mark.src_ip = sid.src_ip; + mark.dest_ip = sid.dest_ip; + mark.src_port = sid.src_port; + mark.dest_port = sid.dest_port; + mark.mark = ct->mark; + + is_v4 ? sfe_ipv4_mark_rule(&mark) : sfe_ipv6_mark_rule(&mark); + fast_classifier_update_mark(&mark, is_v4); + } + + /* + * We're only interested in destroy events at this point + */ + if (unlikely(!(events & (1 << IPCT_DESTROY)))) { + DEBUG_TRACE("ignoring non-destroy event\n"); + return NOTIFY_DONE; + } + + if (is_v4) { + DEBUG_TRACE("Try to clean up: proto: %d src_ip: %pI4 dst_ip: %pI4, src_port: %d, dst_port: %d\n", + sid.protocol, &sid.src_ip, &sid.dest_ip, ntohs(sid.src_port), ntohs(sid.dest_port)); + } else { + DEBUG_TRACE("Try to clean up: proto: %d src_ip: %pI6 dst_ip: %pI6, src_port: %d, dst_port: %d\n", + sid.protocol, &sid.src_ip, &sid.dest_ip, ntohs(sid.src_port), ntohs(sid.dest_port)); + } + + spin_lock_bh(&sfe_connections_lock); + + conn = fast_classifier_find_conn(&sid.src_ip, &sid.dest_ip, sid.src_port, sid.dest_port, sid.protocol, is_v4); + if (conn && conn->offloaded) { + if (is_v4) { + fc_msg.ethertype = AF_INET; + fc_msg.src_saddr.in = *((struct in_addr *)&conn->sic->src_ip); + fc_msg.dst_saddr.in = *((struct in_addr *)&conn->sic->dest_ip_xlate); + } else { + fc_msg.ethertype = AF_INET6; + fc_msg.src_saddr.in6 = *((struct in6_addr *)&conn->sic->src_ip); + fc_msg.dst_saddr.in6 = *((struct in6_addr *)&conn->sic->dest_ip_xlate); + } + + fc_msg.proto = conn->sic->protocol; + fc_msg.sport = conn->sic->src_port; + fc_msg.dport = conn->sic->dest_port_xlate; + memcpy(fc_msg.smac, conn->smac, ETH_ALEN); + memcpy(fc_msg.dmac, conn->dmac, ETH_ALEN); + offloaded = 1; + } + + if (conn) { + DEBUG_TRACE("Free connection\n"); + + hash_del(&conn->hl); + sfe_connections_size--; + kfree(conn->sic); + kfree(conn); + } else { + fast_classifier_incr_exceptions(FAST_CL_EXCEPTION_CT_DESTROY_MISS); + } + + spin_unlock_bh(&sfe_connections_lock); + + is_v4 ? sfe_ipv4_destroy_rule(&sid) : sfe_ipv6_destroy_rule(&sid); + + if (offloaded) { + fast_classifier_send_genl_msg(FAST_CLASSIFIER_C_DONE, &fc_msg); + } + + return NOTIFY_DONE; +} + +/* + * Netfilter conntrack event system to monitor connection tracking changes + */ +#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS +static struct notifier_block fast_classifier_conntrack_notifier = { + .notifier_call = fast_classifier_conntrack_event, +}; +#else +static struct nf_ct_event_notifier fast_classifier_conntrack_notifier = { + .fcn = fast_classifier_conntrack_event, +}; +#endif +#endif + +/* + * Structure to establish a hook into the post routing netfilter point - this + * will pick up local outbound and packets going from one interface to another. + * + * Note: see include/linux/netfilter_ipv4.h for info related to priority levels. + * We want to examine packets after NAT translation and any ALG processing. + */ +static struct nf_hook_ops fast_classifier_ops_post_routing[] __read_mostly = { + SFE_IPV4_NF_POST_ROUTING_HOOK(__fast_classifier_ipv4_post_routing_hook), + SFE_IPV6_NF_POST_ROUTING_HOOK(__fast_classifier_ipv6_post_routing_hook), +}; + +/* + * fast_classifier_sync_rule() + * Synchronize a connection's state. + */ +static void fast_classifier_sync_rule(struct sfe_connection_sync *sis) +{ + struct nf_conntrack_tuple_hash *h; + struct nf_conntrack_tuple tuple; + struct nf_conn *ct; + SFE_NF_CONN_ACCT(acct); + + /* + * Create a tuple so as to be able to look up a connection + */ + memset(&tuple, 0, sizeof(tuple)); + tuple.src.u.all = (__be16)sis->src_port; + tuple.dst.dir = IP_CT_DIR_ORIGINAL; + tuple.dst.protonum = (u8)sis->protocol; + tuple.dst.u.all = (__be16)sis->dest_port; + + if (sis->is_v6) { + tuple.src.u3.in6 = *((struct in6_addr *)sis->src_ip.ip6); + tuple.dst.u3.in6 = *((struct in6_addr *)sis->dest_ip.ip6); + tuple.src.l3num = AF_INET6; + + DEBUG_TRACE("update connection - p: %d, s: %pI6:%u, d: %pI6:%u\n", + (int)tuple.dst.protonum, + &tuple.src.u3.in6, (unsigned int)ntohs(tuple.src.u.all), + &tuple.dst.u3.in6, (unsigned int)ntohs(tuple.dst.u.all)); + } else { + tuple.src.u3.ip = sis->src_ip.ip; + tuple.dst.u3.ip = sis->dest_ip.ip; + tuple.src.l3num = AF_INET; + + DEBUG_TRACE("update connection - p: %d, s: %pI4:%u, d: %pI4:%u\n", + (int)tuple.dst.protonum, + &tuple.src.u3.ip, (unsigned int)ntohs(tuple.src.u.all), + &tuple.dst.u3.ip, (unsigned int)ntohs(tuple.dst.u.all)); + } + + /* + * Update packet count for ingress on bridge device + */ + if (skip_to_bridge_ingress) { + struct rtnl_link_stats64 nlstats; + nlstats.tx_packets = 0; + nlstats.tx_bytes = 0; + + if (sis->src_dev && IFF_EBRIDGE && + (sis->src_new_packet_count || sis->src_new_byte_count)) { + nlstats.rx_packets = sis->src_new_packet_count; + nlstats.rx_bytes = sis->src_new_byte_count; + spin_lock_bh(&sfe_connections_lock); + br_dev_update_stats(sis->src_dev, &nlstats); + spin_unlock_bh(&sfe_connections_lock); + } + if (sis->dest_dev && IFF_EBRIDGE && + (sis->dest_new_packet_count || sis->dest_new_byte_count)) { + nlstats.rx_packets = sis->dest_new_packet_count; + nlstats.rx_bytes = sis->dest_new_byte_count; + spin_lock_bh(&sfe_connections_lock); + br_dev_update_stats(sis->dest_dev, &nlstats); + spin_unlock_bh(&sfe_connections_lock); + } + } + + /* + * Look up conntrack connection + */ + h = nf_conntrack_find_get(&init_net, SFE_NF_CT_DEFAULT_ZONE, &tuple); + if (unlikely(!h)) { + DEBUG_TRACE("no connection found\n"); + return; + } + + ct = nf_ct_tuplehash_to_ctrack(h); +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 9, 0)) + NF_CT_ASSERT(ct->timeout.data == (unsigned long)ct); +#endif /*KERNEL_VERSION(4, 9, 0)*/ + + /* + * Only update if this is not a fixed timeout + */ + if (!test_bit(IPS_FIXED_TIMEOUT_BIT, &ct->status)) { + spin_lock_bh(&ct->lock); +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 9, 0)) + ct->timeout += sis->delta_jiffies; +#else + ct->timeout.expires += sis->delta_jiffies; +#endif /*KERNEL_VERSION(4, 9, 0)*/ + spin_unlock_bh(&ct->lock); + } + + acct = nf_conn_acct_find(ct); + if (acct) { + spin_lock_bh(&ct->lock); + atomic64_add(sis->src_new_packet_count, &SFE_ACCT_COUNTER(acct)[IP_CT_DIR_ORIGINAL].packets); + atomic64_add(sis->src_new_byte_count, &SFE_ACCT_COUNTER(acct)[IP_CT_DIR_ORIGINAL].bytes); + atomic64_add(sis->dest_new_packet_count, &SFE_ACCT_COUNTER(acct)[IP_CT_DIR_REPLY].packets); + atomic64_add(sis->dest_new_byte_count, &SFE_ACCT_COUNTER(acct)[IP_CT_DIR_REPLY].bytes); + spin_unlock_bh(&ct->lock); + } + + switch (sis->protocol) { + case IPPROTO_TCP: + spin_lock_bh(&ct->lock); + if (ct->proto.tcp.seen[0].td_maxwin < sis->src_td_max_window) { + ct->proto.tcp.seen[0].td_maxwin = sis->src_td_max_window; + } + if ((s32)(ct->proto.tcp.seen[0].td_end - sis->src_td_end) < 0) { + ct->proto.tcp.seen[0].td_end = sis->src_td_end; + } + if ((s32)(ct->proto.tcp.seen[0].td_maxend - sis->src_td_max_end) < 0) { + ct->proto.tcp.seen[0].td_maxend = sis->src_td_max_end; + } + if (ct->proto.tcp.seen[1].td_maxwin < sis->dest_td_max_window) { + ct->proto.tcp.seen[1].td_maxwin = sis->dest_td_max_window; + } + if ((s32)(ct->proto.tcp.seen[1].td_end - sis->dest_td_end) < 0) { + ct->proto.tcp.seen[1].td_end = sis->dest_td_end; + } + if ((s32)(ct->proto.tcp.seen[1].td_maxend - sis->dest_td_max_end) < 0) { + ct->proto.tcp.seen[1].td_maxend = sis->dest_td_max_end; + } + spin_unlock_bh(&ct->lock); + break; + } + + /* + * Release connection + */ + nf_ct_put(ct); +} + +/* + * fast_classifier_device_event() + */ +static int fast_classifier_device_event(struct notifier_block *this, unsigned long event, void *ptr) +{ + struct net_device *dev = SFE_DEV_EVENT_PTR(ptr); + + if (dev && (event == NETDEV_DOWN)) { + sfe_ipv4_destroy_all_rules_for_dev(dev); + sfe_ipv6_destroy_all_rules_for_dev(dev); + } + + return NOTIFY_DONE; +} + +/* + * fast_classifier_inet_event() + */ +static int fast_classifier_inet_event(struct notifier_block *this, unsigned long event, void *ptr) +{ + struct net_device *dev = ((struct in_ifaddr *)ptr)->ifa_dev->dev; + + if (dev && (event == NETDEV_DOWN)) { + sfe_ipv4_destroy_all_rules_for_dev(dev); + } + + return NOTIFY_DONE; +} + +/* + * fast_classifier_inet6_event() + */ +static int fast_classifier_inet6_event(struct notifier_block *this, unsigned long event, void *ptr) +{ + struct net_device *dev = ((struct inet6_ifaddr *)ptr)->idev->dev; + + if (dev && (event == NETDEV_DOWN)) { + sfe_ipv6_destroy_all_rules_for_dev(dev); + } + + return NOTIFY_DONE; +} + +/* + * fast_classifier_get_offload_at_pkts() + */ +static ssize_t fast_classifier_get_offload_at_pkts(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return snprintf(buf, (ssize_t)PAGE_SIZE, "%d\n", offload_at_pkts); +} + +/* + * fast_classifier_set_offload_at_pkts() + */ +static ssize_t fast_classifier_set_offload_at_pkts(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + long new; + int ret; + + ret = kstrtol(buf, 0, &new); + if (ret == -EINVAL || ((int)new != new)) + return -EINVAL; + + offload_at_pkts = new; + + return size; +} + +/* + * fast_classifier_get_debug_info() + */ +static ssize_t fast_classifier_get_debug_info(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + size_t len = 0; + struct sfe_connection *conn; + u32 i; +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 9, 0)) + struct hlist_node *node; +#endif + + spin_lock_bh(&sfe_connections_lock); + len += scnprintf(buf, PAGE_SIZE - len, "size=%d offload=%d offload_no_match=%d" + " offloaded=%d done=%d offloaded_fail=%d done_fail=%d\n", + sfe_connections_size, + atomic_read(&offload_msgs), + atomic_read(&offload_no_match_msgs), + atomic_read(&offloaded_msgs), + atomic_read(&done_msgs), + atomic_read(&offloaded_fail_msgs), + atomic_read(&done_fail_msgs)); + sfe_hash_for_each(fc_conn_ht, i, node, conn, hl) { + len += scnprintf(buf + len, PAGE_SIZE - len, + (conn->is_v4 ? "o=%d, p=%d [%pM]:%pI4:%u %pI4:%u:[%pM] m=%08x h=%d\n" : "o=%d, p=%d [%pM]:%pI6:%u %pI6:%u:[%pM] m=%08x h=%d\n"), + conn->offloaded, + conn->sic->protocol, + conn->sic->src_mac, + &conn->sic->src_ip, + ntohs(conn->sic->src_port), + &conn->sic->dest_ip, + ntohs(conn->sic->dest_port), + conn->sic->dest_mac_xlate, + conn->sic->mark, + conn->hits); + } + spin_unlock_bh(&sfe_connections_lock); + + return len; +} + +/* + * fast_classifier_get_skip_bridge_ingress() + */ +static ssize_t fast_classifier_get_skip_bridge_ingress(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return snprintf(buf, (ssize_t)PAGE_SIZE, "%d\n", skip_to_bridge_ingress); +} + +/* + * fast_classifier_set_skip_bridge_ingress() + */ +static ssize_t fast_classifier_set_skip_bridge_ingress(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + long new; + int ret; + + ret = kstrtol(buf, 0, &new); + if (ret == -EINVAL || ((int)new != new)) + return -EINVAL; + + skip_to_bridge_ingress = new ? 1 : 0; + + return size; +} + +/* + * fast_classifier_get_exceptions + * dump exception counters + */ +static ssize_t fast_classifier_get_exceptions(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + int idx, len; + struct fast_classifier *sc = &__sc; + + spin_lock_bh(&sc->lock); + for (len = 0, idx = 0; idx < FAST_CL_EXCEPTION_MAX; idx++) { + if (sc->exceptions[idx]) { + len += snprintf(buf + len, (ssize_t)(PAGE_SIZE - len), "%s = %d\n", fast_classifier_exception_events_string[idx], sc->exceptions[idx]); + } + } + spin_unlock_bh(&sc->lock); + + return len; +} + +/* + * sysfs attributes. + */ +static const struct device_attribute fast_classifier_offload_at_pkts_attr = + __ATTR(offload_at_pkts, S_IWUSR | S_IRUGO, fast_classifier_get_offload_at_pkts, fast_classifier_set_offload_at_pkts); +static const struct device_attribute fast_classifier_debug_info_attr = + __ATTR(debug_info, S_IRUGO, fast_classifier_get_debug_info, NULL); +static const struct device_attribute fast_classifier_skip_bridge_ingress = + __ATTR(skip_to_bridge_ingress, S_IWUSR | S_IRUGO, fast_classifier_get_skip_bridge_ingress, fast_classifier_set_skip_bridge_ingress); +static const struct device_attribute fast_classifier_exceptions_attr = + __ATTR(exceptions, S_IRUGO, fast_classifier_get_exceptions, NULL); + +/* + * fast_classifier_init() + */ +static int __init fast_classifier_init(void) +{ + struct fast_classifier *sc = &__sc; + int result = -1; +#ifdef CONFIG_SFE_ECM + int (*fast_recv)(struct sk_buff *skb); +#endif + + printk(KERN_ALERT "fast-classifier: starting up\n"); + DEBUG_INFO("SFE CM init\n"); + + hash_init(fc_conn_ht); + + /* + * Create sys/fast_classifier + */ + sc->sys_fast_classifier = kobject_create_and_add("fast_classifier", NULL); + if (!sc->sys_fast_classifier) { + DEBUG_ERROR("failed to register fast_classifier\n"); + goto exit1; + } + + result = sysfs_create_file(sc->sys_fast_classifier, &fast_classifier_offload_at_pkts_attr.attr); + if (result) { + DEBUG_ERROR("failed to register offload at pkgs: %d\n", result); + goto exit2; + } + + result = sysfs_create_file(sc->sys_fast_classifier, &fast_classifier_debug_info_attr.attr); + if (result) { + DEBUG_ERROR("failed to register debug dev: %d\n", result); + sysfs_remove_file(sc->sys_fast_classifier, &fast_classifier_offload_at_pkts_attr.attr); + goto exit2; + } + + result = sysfs_create_file(sc->sys_fast_classifier, &fast_classifier_skip_bridge_ingress.attr); + if (result) { + DEBUG_ERROR("failed to register skip bridge on ingress: %d\n", result); + sysfs_remove_file(sc->sys_fast_classifier, &fast_classifier_offload_at_pkts_attr.attr); + sysfs_remove_file(sc->sys_fast_classifier, &fast_classifier_debug_info_attr.attr); + goto exit2; + } + + result = sysfs_create_file(sc->sys_fast_classifier, &fast_classifier_exceptions_attr.attr); + if (result) { + DEBUG_ERROR("failed to register exceptions file: %d\n", result); + sysfs_remove_file(sc->sys_fast_classifier, &fast_classifier_offload_at_pkts_attr.attr); + sysfs_remove_file(sc->sys_fast_classifier, &fast_classifier_debug_info_attr.attr); + sysfs_remove_file(sc->sys_fast_classifier, &fast_classifier_skip_bridge_ingress.attr); + goto exit2; + } + + sc->dev_notifier.notifier_call = fast_classifier_device_event; + sc->dev_notifier.priority = 1; + register_netdevice_notifier(&sc->dev_notifier); + + sc->inet_notifier.notifier_call = fast_classifier_inet_event; + sc->inet_notifier.priority = 1; + register_inetaddr_notifier(&sc->inet_notifier); + + sc->inet6_notifier.notifier_call = fast_classifier_inet6_event; + sc->inet6_notifier.priority = 1; + register_inet6addr_notifier(&sc->inet6_notifier); + + /* + * Register our netfilter hooks. + */ + result = nf_register_net_hooks(&init_net, fast_classifier_ops_post_routing, ARRAY_SIZE(fast_classifier_ops_post_routing)); + if (result < 0) { + DEBUG_ERROR("can't register nf post routing hook: %d\n", result); + goto exit3; + } + +#ifdef CONFIG_NF_CONNTRACK_EVENTS + /* + * Register a notifier hook to get fast notifications of expired connections. + */ +#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS + result = nf_conntrack_register_chain_notifier(&init_net, &fast_classifier_conntrack_notifier); +#else + result = nf_conntrack_register_notifier(&init_net, &fast_classifier_conntrack_notifier); +#endif + if (result < 0) { + DEBUG_ERROR("can't register nf notifier hook: %d\n", result); + goto exit4; + } +#endif + + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 10, 0)) + result = genl_register_family(&fast_classifier_gnl_family); + if (result) { + DEBUG_ERROR("failed to register genl family: %d\n", result); + goto exit5; + } +#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 13, 0)) + result = genl_register_family_with_ops_groups(&fast_classifier_gnl_family, + fast_classifier_gnl_ops, + fast_classifier_genl_mcgrp); + if (result) { + DEBUG_ERROR("failed to register genl ops: %d\n", result); + goto exit5; + } +#else + result = genl_register_family(&fast_classifier_gnl_family); + if (result) { + printk(KERN_CRIT "unable to register genl family\n"); + goto exit5; + } + + result = genl_register_ops(&fast_classifier_gnl_family, fast_classifier_gnl_ops); + if (result) { + printk(KERN_CRIT "unable to register ops\n"); + goto exit6; + } + + result = genl_register_mc_group(&fast_classifier_gnl_family, + fast_classifier_genl_mcgrp); + if (result) { + printk(KERN_CRIT "unable to register multicast group\n"); + goto exit6; + } +#endif + + printk(KERN_ALERT "fast-classifier: registered\n"); + + spin_lock_init(&sc->lock); + + /* + * Hook the receive path in the network stack. + */ +#ifdef CONFIG_SFE_ECM + rcu_read_lock(); + fast_recv = rcu_dereference(athrs_fast_nat_recv); + rcu_read_unlock(); + if (!fast_recv) { + BUG_ON(athrs_fast_nat_recv); + } +#else + BUG_ON(athrs_fast_nat_recv); +#endif + RCU_INIT_POINTER(athrs_fast_nat_recv, fast_classifier_recv); + + /* + * Hook the shortcut sync callback. + */ + sfe_ipv4_register_sync_rule_callback(fast_classifier_sync_rule); + sfe_ipv6_register_sync_rule_callback(fast_classifier_sync_rule); + return 0; + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 13, 0)) +exit6: + genl_unregister_family(&fast_classifier_gnl_family); +#endif + +exit5: +#ifdef CONFIG_NF_CONNTRACK_EVENTS +#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS + nf_conntrack_unregister_chain_notifier(&init_net, &fast_classifier_conntrack_notifier); +#else + nf_conntrack_unregister_notifier(&init_net, &fast_classifier_conntrack_notifier); +#endif + +exit4: +#endif + nf_unregister_net_hooks(&init_net, fast_classifier_ops_post_routing, ARRAY_SIZE(fast_classifier_ops_post_routing)); + +exit3: + unregister_inetaddr_notifier(&sc->inet_notifier); + unregister_inet6addr_notifier(&sc->inet6_notifier); + unregister_netdevice_notifier(&sc->dev_notifier); + sysfs_remove_file(sc->sys_fast_classifier, &fast_classifier_offload_at_pkts_attr.attr); + sysfs_remove_file(sc->sys_fast_classifier, &fast_classifier_debug_info_attr.attr); + sysfs_remove_file(sc->sys_fast_classifier, &fast_classifier_skip_bridge_ingress.attr); + sysfs_remove_file(sc->sys_fast_classifier, &fast_classifier_exceptions_attr.attr); + +exit2: + kobject_put(sc->sys_fast_classifier); + +exit1: + return result; +} + +/* + * fast_classifier_exit() + */ +static void __exit fast_classifier_exit(void) +{ + struct fast_classifier *sc = &__sc; + int result = -1; + + DEBUG_INFO("SFE CM exit\n"); + printk(KERN_ALERT "fast-classifier: shutting down\n"); + + /* + * Unregister our sync callback. + */ + sfe_ipv4_register_sync_rule_callback(NULL); + sfe_ipv6_register_sync_rule_callback(NULL); + + /* + * Unregister our receive callback. + */ + RCU_INIT_POINTER(athrs_fast_nat_recv, NULL); + + /* + * Wait for all callbacks to complete. + */ + rcu_barrier(); + + /* + * Destroy all connections. + */ + sfe_ipv4_destroy_all_rules_for_dev(NULL); + sfe_ipv6_destroy_all_rules_for_dev(NULL); + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 13, 0)) + result = genl_unregister_ops(&fast_classifier_gnl_family, fast_classifier_gnl_ops); + if (result != 0) { + printk(KERN_CRIT "Unable to unreigster genl_ops\n"); + } +#endif + + result = genl_unregister_family(&fast_classifier_gnl_family); + if (result != 0) { + printk(KERN_CRIT "Unable to unregister genl_family\n"); + } + +#ifdef CONFIG_NF_CONNTRACK_EVENTS +#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS + nf_conntrack_unregister_chain_notifier(&init_net, &fast_classifier_conntrack_notifier); +#else + nf_conntrack_unregister_notifier(&init_net, &fast_classifier_conntrack_notifier); +#endif +#endif + nf_unregister_net_hooks(&init_net, fast_classifier_ops_post_routing, ARRAY_SIZE(fast_classifier_ops_post_routing)); + + unregister_inet6addr_notifier(&sc->inet6_notifier); + unregister_inetaddr_notifier(&sc->inet_notifier); + unregister_netdevice_notifier(&sc->dev_notifier); + + kobject_put(sc->sys_fast_classifier); +} + +module_init(fast_classifier_init) +module_exit(fast_classifier_exit) + +MODULE_DESCRIPTION("Shortcut Forwarding Engine - Connection Manager"); +MODULE_LICENSE("Dual BSD/GPL"); + diff --git a/shortcut-fe/fast-classifier/src/fast-classifier.h b/shortcut-fe/fast-classifier/src/fast-classifier.h new file mode 100644 index 000000000..6b7a18cf6 --- /dev/null +++ b/shortcut-fe/fast-classifier/src/fast-classifier.h @@ -0,0 +1,57 @@ +/* + * User space header to send message to the fast classifier + * + * Copyright (c) 2013,2016 The Linux Foundation. All rights reserved. + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT + * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include + +#define FAST_CLASSIFIER_GENL_VERSION (1) +#define FAST_CLASSIFIER_GENL_NAME "FC" +#define FAST_CLASSIFIER_GENL_MCGRP "FC_MCGRP" +#define FAST_CLASSIFIER_GENL_HDRSIZE (0) + +enum { + FAST_CLASSIFIER_A_UNSPEC, + FAST_CLASSIFIER_A_TUPLE, + __FAST_CLASSIFIER_A_MAX, +}; + +#define FAST_CLASSIFIER_A_MAX (__FAST_CLASSIFIER_A_MAX - 1) + +enum { + FAST_CLASSIFIER_C_UNSPEC, + FAST_CLASSIFIER_C_OFFLOAD, + FAST_CLASSIFIER_C_OFFLOADED, + FAST_CLASSIFIER_C_DONE, + __FAST_CLASSIFIER_C_MAX, +}; + +#define FAST_CLASSIFIER_C_MAX (__FAST_CLASSIFIER_C_MAX - 1) + +struct fast_classifier_tuple { + unsigned short ethertype; + unsigned char proto; + union { + struct in_addr in; + struct in6_addr in6; + } src_saddr; + union { + struct in_addr in; + struct in6_addr in6; + } dst_saddr; + unsigned short sport; + unsigned short dport; + unsigned char smac[ETH_ALEN]; + unsigned char dmac[ETH_ALEN]; +}; diff --git a/shortcut-fe/fast-classifier/src/nl_classifier_test.c b/shortcut-fe/fast-classifier/src/nl_classifier_test.c new file mode 100644 index 000000000..639417964 --- /dev/null +++ b/shortcut-fe/fast-classifier/src/nl_classifier_test.c @@ -0,0 +1,281 @@ +/* + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT + * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include +#include +#include +#include +#include +#include + +#define NL_CLASSIFIER_GENL_VERSION 1 +#define NL_CLASSIFIER_GENL_FAMILY "FC" +#define NL_CLASSIFIER_GENL_GROUP "FC_MCGRP" +#define NL_CLASSIFIER_GENL_HDRSIZE 0 + +enum NL_CLASSIFIER_CMD { + NL_CLASSIFIER_CMD_UNSPEC, + NL_CLASSIFIER_CMD_ACCEL, + NL_CLASSIFIER_CMD_ACCEL_OK, + NL_CLASSIFIER_CMD_CONNECTION_CLOSED, + NL_CLASSIFIER_CMD_MAX, +}; + +enum NL_CLASSIFIER_ATTR { + NL_CLASSIFIER_ATTR_UNSPEC, + NL_CLASSIFIER_ATTR_TUPLE, + NL_CLASSIFIER_ATTR_MAX, +}; + +union nl_classifier_tuple_ip { + struct in_addr in; + struct in6_addr in6; +}; + +struct nl_classifier_tuple { + unsigned short af; + unsigned char proto; + union nl_classifier_tuple_ip src_ip; + union nl_classifier_tuple_ip dst_ip; + unsigned short sport; + unsigned short dport; + unsigned char smac[6]; + unsigned char dmac[6]; +}; + +struct nl_classifier_instance { + struct nl_sock *sock; + int family_id; + int group_id; + int stop; +}; + +struct nl_classifier_instance nl_cls_inst; + +static struct nla_policy nl_classifier_genl_policy[(NL_CLASSIFIER_ATTR_MAX+1)] = { + [NL_CLASSIFIER_ATTR_TUPLE] = { .type = NLA_UNSPEC }, +}; + +void nl_classifier_dump_nl_tuple(struct nl_classifier_tuple *tuple) +{ + char ip_str[64]; + + printf("protocol = %s\n", (tuple->proto == IPPROTO_UDP) ? "udp" : ((tuple->proto == IPPROTO_TCP) ? "tcp" : "unknown")); + printf("source ip = %s\n", inet_ntop(tuple->af, &tuple->src_ip, ip_str, sizeof(ip_str))); + printf("destination ip = %s\n", inet_ntop(tuple->af, &tuple->dst_ip, ip_str, sizeof(ip_str))); + printf("source port = %d\n", ntohs(tuple->sport)); + printf("destination port = %d\n", ntohs(tuple->dport)); +} + +int nl_classifier_msg_recv(struct nl_msg *msg, void *arg) +{ + struct nlmsghdr *nlh = nlmsg_hdr(msg); + struct genlmsghdr *gnlh = nlmsg_data(nlh); + struct nlattr *attrs[(NL_CLASSIFIER_ATTR_MAX+1)]; + + genlmsg_parse(nlh, NL_CLASSIFIER_GENL_HDRSIZE, attrs, NL_CLASSIFIER_ATTR_MAX, nl_classifier_genl_policy); + + switch (gnlh->cmd) { + case NL_CLASSIFIER_CMD_ACCEL_OK: + printf("Acceleration successful:\n"); + nl_classifier_dump_nl_tuple(nla_data(attrs[NL_CLASSIFIER_ATTR_TUPLE])); + return NL_OK; + case NL_CLASSIFIER_CMD_CONNECTION_CLOSED: + printf("Connection is closed:\n"); + nl_classifier_dump_nl_tuple(nla_data(attrs[NL_CLASSIFIER_ATTR_TUPLE])); + return NL_OK; + default: + printf("nl classifier received unknow message %d\n", gnlh->cmd); + } + + return NL_SKIP; +} + +void nl_classifier_offload(struct nl_classifier_instance *inst, + unsigned char proto, unsigned long *src_saddr, + unsigned long *dst_saddr, unsigned short sport, + unsigned short dport, int af) +{ + struct nl_msg *msg; + int ret; + struct nl_classifier_tuple classifier_msg; + + memset(&classifier_msg, 0, sizeof(classifier_msg)); + classifier_msg.af = af; + classifier_msg.proto = proto; + memcpy(&classifier_msg.src_ip, src_saddr, (af == AF_INET ? 4 : 16)); + memcpy(&classifier_msg.dst_ip, dst_saddr, (af == AF_INET ? 4 : 16)); + classifier_msg.sport = sport; + classifier_msg.dport = dport; + + msg = nlmsg_alloc(); + if (!msg) { + printf("Unable to allocate message\n"); + return; + } + + genlmsg_put(msg, NL_AUTO_PID, NL_AUTO_SEQ, inst->family_id, + NL_CLASSIFIER_GENL_HDRSIZE, NLM_F_REQUEST, + NL_CLASSIFIER_CMD_ACCEL, NL_CLASSIFIER_GENL_VERSION); + nla_put(msg, NL_CLASSIFIER_ATTR_TUPLE, sizeof(classifier_msg), &classifier_msg); + + ret = nl_send_auto(inst->sock, msg); + if (ret < 0) { + printf("send netlink message failed.\n"); + nlmsg_free(msg); + return; + } + + nlmsg_free(msg); + printf("nl classifier offload connection successful\n"); +} + +int nl_classifier_init(struct nl_classifier_instance *inst) +{ + int ret; + + inst->sock = nl_socket_alloc(); + if (!inst->sock) { + printf("Unable to allocation socket.\n"); + return -1; + } + genl_connect(inst->sock); + + inst->family_id = genl_ctrl_resolve(inst->sock, NL_CLASSIFIER_GENL_FAMILY); + if (inst->family_id < 0) { + printf("Unable to resolve family %s\n", NL_CLASSIFIER_GENL_FAMILY); + goto init_failed; + } + + inst->group_id = genl_ctrl_resolve_grp(inst->sock, NL_CLASSIFIER_GENL_FAMILY, NL_CLASSIFIER_GENL_GROUP); + if (inst->group_id < 0) { + printf("Unable to resolve mcast group %s\n", NL_CLASSIFIER_GENL_GROUP); + goto init_failed; + } + + ret = nl_socket_add_membership(inst->sock, inst->group_id); + if (ret < 0) { + printf("Unable to add membership\n"); + goto init_failed; + } + + nl_socket_disable_seq_check(inst->sock); + nl_socket_modify_cb(inst->sock, NL_CB_VALID, NL_CB_CUSTOM, nl_classifier_msg_recv, NULL); + + printf("nl classifier init successful\n"); + return 0; + +init_failed: + if (inst->sock) { + nl_close(inst->sock); + nl_socket_free(inst->sock); + inst->sock = NULL; + } + return -1; +} + +void nl_classifier_exit(struct nl_classifier_instance *inst) +{ + if (inst->sock) { + nl_close(inst->sock); + nl_socket_free(inst->sock); + inst->sock = NULL; + } + printf("nl classifier exit successful\n"); +} + +int nl_classifier_parse_arg(int argc, char *argv[], unsigned char *proto, unsigned long *src_saddr, + unsigned long *dst_saddr, unsigned short *sport, unsigned short *dport, int *af) +{ + int ret; + unsigned short port; + + if (argc < 7) { + printf("help: nl_classifier \n"); + return -1; + } + + if (0 == strncmp(argv[1], "v4", 2)) { + *af = AF_INET; + } else if (0 == strncmp(argv[1], "v6", 2)) { + *af = AF_INET6; + } else { + printf("Address family is not supported"); + return -1; + } + + if (0 == strncmp(argv[2], "udp", 3)) { + *proto = IPPROTO_UDP; + } else if (0 == strncmp(argv[2], "tcp", 3)) { + *proto = IPPROTO_TCP; + } else { + printf("Protocol is not supported"); + return -1; + } + + ret = inet_pton(*af, argv[3], src_saddr); + if (ret <= 0) { + printf("source ip has wrong format\n"); + return -1; + } + + ret = inet_pton(*af, argv[4], dst_saddr); + if (ret <= 0) { + printf("destination ip has wrong format\n"); + return -1; + } + + port = strtol(argv[5], NULL, 0); + *sport = htons(port); + port = strtol(argv[6], NULL, 0); + *dport = htons(port); + + printf("nl classifier parse arguments successful\n"); + return 0; +} + +int main(int argc, char *argv[]) +{ + struct nl_classifier_instance *inst = &nl_cls_inst; + unsigned char proto; + unsigned long src_addr[4]; + unsigned long dst_addr[4]; + unsigned short sport; + unsigned short dport; + int af; + int ret; + + ret = nl_classifier_parse_arg(argc, argv, &proto, src_addr, dst_addr, &sport, &dport, &af); + if (ret < 0) { + printf("Failed to parse arguments\n"); + return ret; + } + + ret = nl_classifier_init(inst); + if (ret < 0) { + printf("Unable to init generic netlink\n"); + return ret; + } + + nl_classifier_offload(inst, proto, src_addr, dst_addr, sport, dport, af); + + /* main loop to listen on message */ + while (!inst->stop) { + nl_recvmsgs_default(inst->sock); + } + + nl_classifier_exit(inst); + + return 0; +} diff --git a/shortcut-fe/fast-classifier/src/userspace_example.c b/shortcut-fe/fast-classifier/src/userspace_example.c new file mode 100644 index 000000000..4f4113d99 --- /dev/null +++ b/shortcut-fe/fast-classifier/src/userspace_example.c @@ -0,0 +1,232 @@ +/* + * Copyright (c) 2013,2016 The Linux Foundation. All rights reserved. + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT + * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include +#include +#include +#include +#include + +#include + +static struct nl_sock *sock; +static struct nl_sock *sock_event; +static int family; +static int grp_id; + +static struct nla_policy fast_classifier_genl_policy[FAST_CLASSIFIER_A_MAX + 1] = { + [FAST_CLASSIFIER_A_TUPLE] = { .type = NLA_UNSPEC }, +}; + +void dump_fc_tuple(struct fast_classifier_tuple *fc_msg) +{ + char src_str[INET_ADDRSTRLEN]; + char dst_str[INET_ADDRSTRLEN]; + + printf("TUPLE: %d, %s, %s, %d, %d" + " SMAC=%02x:%02x:%02x:%02x:%02x:%02x", + " DMAC=%02x:%02x:%02x:%02x:%02x:%02x\n", + fc_msg->proto, + inet_ntop(AF_INET, + &fc_msg->src_saddr.in.s_addr, + src_str, + INET_ADDRSTRLEN), + inet_ntop(AF_INET, + &fc_msg->dst_saddr.in.s_addr, + dst_str, + INET_ADDRSTRLEN), + fc_msg->sport, fc_msg->dport, + fc_msg->smac[0], fc_msg->smac[1], fc_msg->smac[2], + fc_msg->smac[3], fc_msg->smac[4], fc_msg->smac[5], + fc_msg->dmac[0], fc_msg->dmac[1], fc_msg->dmac[2], + fc_msg->dmac[3], fc_msg->dmac[4], fc_msg->dmac[5]); +} + +static int parse_cb(struct nl_msg *msg, void *arg) +{ + struct nlmsghdr *nlh = nlmsg_hdr(msg); + struct genlmsghdr *gnlh = nlmsg_data(nlh); + struct nlattr *attrs[FAST_CLASSIFIER_A_MAX]; + + genlmsg_parse(nlh, 0, attrs, FAST_CLASSIFIER_A_MAX, fast_classifier_genl_policy); + + switch (gnlh->cmd) { + case FAST_CLASSIFIER_C_OFFLOADED: + printf("Got a offloaded message\n"); + dump_fc_tuple(nla_data(attrs[FAST_CLASSIFIER_A_TUPLE])); + return NL_OK; + case FAST_CLASSIFIER_C_DONE: + printf("Got a done message\n"); + dump_fc_tuple(nla_data(attrs[FAST_CLASSIFIER_A_TUPLE])); + return NL_OK; + } + + return NL_SKIP; +} + +int fast_classifier_init(void) +{ + int err; + + sock = nl_socket_alloc(); + if (!sock) { + printf("Unable to allocation socket.\n"); + return -1; + } + genl_connect(sock); + + sock_event = nl_socket_alloc(); + if (!sock_event) { + nl_close(sock); + nl_socket_free(sock); + printf("Unable to allocation socket.\n"); + return -1; + } + genl_connect(sock_event); + + family = genl_ctrl_resolve(sock, FAST_CLASSIFIER_GENL_NAME); + if (family < 0) { + nl_close(sock_event); + nl_close(sock); + nl_socket_free(sock); + nl_socket_free(sock_event); + printf("Unable to resolve family\n"); + return -1; + } + + grp_id = genl_ctrl_resolve_grp(sock, FAST_CLASSIFIER_GENL_NAME, + FAST_CLASSIFIER_GENL_MCGRP); + if (grp_id < 0) { + printf("Unable to resolve mcast group\n"); + return -1; + } + + err = nl_socket_add_membership(sock_event, grp_id); + if (err < 0) { + printf("Unable to add membership\n"); + return -1; + } + + nl_socket_disable_seq_check(sock_event); + nl_socket_modify_cb(sock_event, NL_CB_VALID, NL_CB_CUSTOM, parse_cb, NULL); + + return 0; +} + +void fast_classifier_close(void) +{ + nl_close(sock_event); + nl_close(sock); + nl_socket_free(sock_event); + nl_socket_free(sock); +} + +void fast_classifier_ipv4_offload(unsigned char proto, unsigned long src_saddr, + unsigned long dst_saddr, unsigned short sport, + unsigned short dport) +{ + struct nl_msg *msg; + int ret; +#ifdef DEBUG + char src_str[INET_ADDRSTRLEN]; + char dst_str[INET_ADDRSTRLEN]; +#endif + struct fast_classifier_tuple fc_msg; + +#ifdef DEBUG + printf("DEBUG: would offload: %d, %s, %s, %d, %d\n", proto, + inet_ntop(AF_INET, &src_saddr, src_str, INET_ADDRSTRLEN), + inet_ntop(AF_INET, &dst_saddr, dst_str, INET_ADDRSTRLEN), + sport, dport); +#endif + + fc_msg.proto = proto; + fc_msg.src_saddr.in.s_addr = src_saddr; + fc_msg.dst_saddr.in.s_addr = dst_saddr; + fc_msg.sport = sport; + fc_msg.dport = dport; + fc_msg.smac[0] = 'a'; + fc_msg.smac[1] = 'b'; + fc_msg.smac[2] = 'c'; + fc_msg.smac[3] = 'd'; + fc_msg.smac[4] = 'e'; + fc_msg.smac[5] = 'f'; + fc_msg.dmac[0] = 'f'; + fc_msg.dmac[1] = 'e'; + fc_msg.dmac[2] = 'd'; + fc_msg.dmac[3] = 'c'; + fc_msg.dmac[4] = 'b'; + fc_msg.dmac[5] = 'a'; + + if (fast_classifier_init() < 0) { + printf("Unable to init generic netlink\n"); + exit(1); + } + + msg = nlmsg_alloc(); + if (!msg) { + nl_socket_free(sock); + printf("Unable to allocate message\n"); + return; + } + + genlmsg_put(msg, NL_AUTO_PID, NL_AUTO_SEQ, family, + FAST_CLASSIFIER_GENL_HDRSIZE, NLM_F_REQUEST, + FAST_CLASSIFIER_C_OFFLOAD, FAST_CLASSIFIER_GENL_VERSION); + nla_put(msg, 1, sizeof(fc_msg), &fc_msg); + + ret = nl_send_auto_complete(sock, msg); + + nlmsg_free(msg); + if (ret < 0) { + printf("nlmsg_free failed"); + nl_close(sock); + nl_socket_free(sock); + return; + } + + ret = nl_wait_for_ack(sock); + if (ret < 0) { + printf("wait for ack failed"); + nl_close(sock); + nl_socket_free(sock); + return; + } +} + +void fast_classifier_listen_for_messages(void) +{ + printf("waiting for netlink events\n"); + + while (1) { + nl_recvmsgs_default(sock_event); + } +} + +int main(int argc, char *argv[]) +{ + if (fast_classifier_init() < 0) { + printf("Unable to init generic netlink\n"); + exit(1); + } + + fast_classifier_ipv4_offload('a', 0, 0, 0, 0); + + /* this never returns */ + fast_classifier_listen_for_messages(); + + fast_classifier_close(); + + return 0; +} diff --git a/shortcut-fe/shortcut-fe/Makefile b/shortcut-fe/shortcut-fe/Makefile new file mode 100644 index 000000000..dd53042e5 --- /dev/null +++ b/shortcut-fe/shortcut-fe/Makefile @@ -0,0 +1,88 @@ +# +# Copyright (c) 2013-2018, 2020 The Linux Foundation. All rights reserved. +# Permission to use, copy, modify, and/or distribute this software for +# any purpose with or without fee is hereby granted, provided that the +# above copyright notice and this permission notice appear in all copies. +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT +# OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +# + +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/kernel.mk + +PKG_NAME:=shortcut-fe +PKG_RELEASE:=8 + +include $(INCLUDE_DIR)/package.mk + +define KernelPackage/shortcut-fe + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Support + DEPENDS:=@IPV6 +kmod-nf-conntrack + TITLE:=Kernel driver for SFE + FILES:= \ + $(PKG_BUILD_DIR)/shortcut-fe.ko \ + $(PKG_BUILD_DIR)/shortcut-fe-ipv6.ko + KCONFIG:= \ + CONFIG_NF_CONNTRACK_EVENTS=y \ + CONFIG_NF_CONNTRACK_TIMEOUT=y \ + CONFIG_SHORTCUT_FE=y \ + CONFIG_XFRM=y + PROVIDES:=$(PKG_NAME) + AUTOLOAD:=$(call AutoLoad,09,shortcut-fe shortcut-fe-ipv6) +endef + +define KernelPackage/shortcut-fe/Description +Shortcut is an in-Linux-kernel IP packet forwarding engine. +endef + +define KernelPackage/shortcut-fe/install + $(INSTALL_DIR) $(1)/usr/bin + $(INSTALL_BIN) ./files/usr/bin/sfe_dump $(1)/usr/bin +endef + +HAVE_ECM:=$(CONFIG_PACKAGE_kmod-qca-nss-ecm-premium)$(CONFIG_PACKAGE_kmod-qca-nss-ecm-noload)$(CONFIG_PACKAGE_kmod-qca-nss-ecm-premium-noload)$(CONFIG_PACKAGE_kmod-qca-nss-ecm-standard) + +define KernelPackage/shortcut-fe-cm + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Support + DEPENDS:=+kmod-ipt-conntrack +kmod-shortcut-fe + TITLE:=Kernel driver for SFE + FILES:=$(PKG_BUILD_DIR)/shortcut-fe-cm.ko + KCONFIG:= \ + CONFIG_NF_CONNTRACK_CHAIN_EVENTS=y \ + CONFIG_NF_CONNTRACK_EVENTS=y \ + CONFIG_XFRM=y + CONFLICTS:=kmod-shortcut-fe-drv +endef + +define KernelPackage/shortcut-fe-cm/Description +Simple connection manager for the Shortcut forwarding engine. +endef + +define Build/Compile + $(MAKE) $(PKG_JOBS) -C "$(LINUX_DIR)" \ + $(KERNEL_MAKE_FLAGS) \ + $(PKG_MAKE_FLAGS) \ + M="$(PKG_BUILD_DIR)" \ + EXTRA_CFLAGS+="-DSFE_SUPPORT_IPV6" SFE_SUPPORT_IPV6=y \ + $(if $(HAVE_ECM),EXTRA_CFLAGS+="-DCONFIG_SFE_ECM" CONFIG_SFE_ECM=y,) \ + modules +endef + +ifneq ($(CONFIG_PACKAGE_kmod-shortcut-fe)$(CONFIG_PACKAGE_kmod-shortcut-fe-cm),) +define Build/InstallDev + $(INSTALL_DIR) $(1)/usr/include/shortcut-fe + $(CP) -rf $(PKG_BUILD_DIR)/sfe.h $(1)/usr/include/shortcut-fe +endef +endif + +$(eval $(call KernelPackage,shortcut-fe)) +$(eval $(call KernelPackage,shortcut-fe-cm)) diff --git a/shortcut-fe/shortcut-fe/files/etc/init.d/shortcut-fe b/shortcut-fe/shortcut-fe/files/etc/init.d/shortcut-fe new file mode 100644 index 000000000..838512a36 --- /dev/null +++ b/shortcut-fe/shortcut-fe/files/etc/init.d/shortcut-fe @@ -0,0 +1,51 @@ +#!/bin/sh /etc/rc.common +# +# Copyright (c) 2014-2015 The Linux Foundation. All rights reserved. +# Permission to use, copy, modify, and/or distribute this software for +# any purpose with or without fee is hereby granted, provided that the +# above copyright notice and this permission notice appear in all copies. +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT +# OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +# + +#SFE connection manager has a lower priority, it should be started after other connection manager +#to detect the existence of connection manager with higher priority +START=70 + +have_cm() { + [ -d "/sys/kernel/debug/ecm" ] && echo 1 && return + + echo 0 +} + +#load shortcut-fe and connection manager +load_sfe() { + local kernel_version=$(uname -r) + + [ -d "/sys/module/shortcut_fe" ] || insmod /lib/modules/$kernel_version/shortcut-fe.ko + [ -d "/sys/module/shortcut_fe_ipv6" ] || insmod /lib/modules/$kernel_version/shortcut-fe-ipv6.ko + + [ -e "/lib/modules/$kernel_version/shortcut-fe-cm.ko" ] && { + [ -d /sys/module/shortcut_fe_cm ] || insmod /lib/modules/$kernel_version/shortcut-fe-cm.ko + } + [ -e "/lib/modules/$kernel_version/fast-classifier.ko" ] && { + [ -d /sys/module/fast_classifier ] || insmod /lib/modules/$kernel_version/fast-classifier.ko + } +} + +start() { + [ "$(have_cm)" = "0" ] && load_sfe +} + +stop() { + [ -d "/sys/module/shortcut_fe_cm" ] && rmmod shortcut_fe_cm + [ -d "/sys/module/shortcut_fe_ipv6" ] && rmmod shortcut_fe_ipv6 + [ -d "/sys/module/shortcut_fe" ] && rmmod shortcut_fe + [ -d "/sys/module/shortcut_fe_drv" ] && rmmod shortcut_fe_drv + [ -d "/sys/module/fast_classifier" ] && rmmod fast_classifier +} diff --git a/shortcut-fe/shortcut-fe/files/usr/bin/sfe_dump b/shortcut-fe/shortcut-fe/files/usr/bin/sfe_dump new file mode 100644 index 000000000..2a224e0ca --- /dev/null +++ b/shortcut-fe/shortcut-fe/files/usr/bin/sfe_dump @@ -0,0 +1,35 @@ +#!/bin/sh +# +# Copyright (c) 2015 The Linux Foundation. All rights reserved. +# Permission to use, copy, modify, and/or distribute this software for +# any purpose with or without fee is hereby granted, provided that the +# above copyright notice and this permission notice appear in all copies. +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT +# OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +# + +#@sfe_dump +#@example : sfe_dump (ipv4|ipv6) +sfe_dump(){ + [ -e "/dev/sfe_ipv4" ] || { + dev_num=$(cat /sys/sfe_ipv4/debug_dev) + mknod /dev/sfe_ipv4 c $dev_num 0 + } + [ -e "/dev/sfe_ipv6" ] || { + dev_num=$(cat /sys/sfe_ipv6/debug_dev) + mknod /dev/sfe_ipv6 c $dev_num 0 + } + cat /dev/sfe_$1 +} + +if [ -z "$1" ]; then + sfe_dump ipv4 + sfe_dump ipv6 +else + sfe_dump $1 +fi diff --git a/shortcut-fe/shortcut-fe/src/Kconfig b/shortcut-fe/shortcut-fe/src/Kconfig new file mode 100644 index 000000000..487f1e065 --- /dev/null +++ b/shortcut-fe/shortcut-fe/src/Kconfig @@ -0,0 +1,14 @@ +# +# Shortcut forwarding engine +# + +config SHORTCUT_FE + tristate "Shortcut Forwarding Engine" + depends on NF_CONNTRACK + ---help--- + Shortcut is a fast in-kernel packet forwarding engine. + + To compile this code as a module, choose M here: the module will be + called shortcut-fe. + + If unsure, say N. diff --git a/shortcut-fe/shortcut-fe/src/Makefile b/shortcut-fe/shortcut-fe/src/Makefile new file mode 100644 index 000000000..991a20ec6 --- /dev/null +++ b/shortcut-fe/shortcut-fe/src/Makefile @@ -0,0 +1,24 @@ +# +# Makefile for Shortcut FE. +# + +obj-m += shortcut-fe.o + +ifdef SFE_SUPPORT_IPV6 +obj-m += shortcut-fe-ipv6.o +endif + +obj-m += shortcut-fe-cm.o + +shortcut-fe-objs := \ + sfe_ipv4.o + +ifdef SFE_SUPPORT_IPV6 +shortcut-fe-ipv6-objs := \ + sfe_ipv6.o +endif + +shortcut-fe-cm-objs := \ + sfe_cm.o + +ccflags-y += -Werror -Wall diff --git a/shortcut-fe/shortcut-fe/src/sfe.h b/shortcut-fe/shortcut-fe/src/sfe.h new file mode 100644 index 000000000..279e7b3dc --- /dev/null +++ b/shortcut-fe/shortcut-fe/src/sfe.h @@ -0,0 +1,114 @@ +/* + * sfe.h + * Shortcut forwarding engine. + * + * Copyright (c) 2013-2017 The Linux Foundation. All rights reserved. + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT + * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +/* + * The following are debug macros used throughout the SFE. + * + * The DEBUG_LEVEL enables the followings based on its value, + * when dynamic debug option is disabled. + * + * 0 = OFF + * 1 = ASSERTS / ERRORS + * 2 = 1 + WARN + * 3 = 2 + INFO + * 4 = 3 + TRACE + */ +#define DEBUG_LEVEL 2 + +#if (DEBUG_LEVEL < 1) +#define DEBUG_ASSERT(s, ...) +#define DEBUG_ERROR(s, ...) +#else +#define DEBUG_ASSERT(c, s, ...) if (!(c)) { pr_emerg("ASSERT: %s:%d:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__); BUG(); } +#define DEBUG_ERROR(s, ...) pr_err("%s:%d:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__) +#endif + +#if defined(CONFIG_DYNAMIC_DEBUG) +/* + * Compile messages for dynamic enable/disable + */ +#define DEBUG_WARN(s, ...) pr_debug("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__) +#define DEBUG_INFO(s, ...) pr_debug("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__) +#define DEBUG_TRACE(s, ...) pr_debug("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__) +#else + +/* + * Statically compile messages at different levels + */ +#if (DEBUG_LEVEL < 2) +#define DEBUG_WARN(s, ...) +#else +#define DEBUG_WARN(s, ...) pr_warn("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__) +#endif + +#if (DEBUG_LEVEL < 3) +#define DEBUG_INFO(s, ...) +#else +#define DEBUG_INFO(s, ...) pr_notice("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__) +#endif + +#if (DEBUG_LEVEL < 4) +#define DEBUG_TRACE(s, ...) +#else +#define DEBUG_TRACE(s, ...) pr_info("%s[%d]:" s, __FUNCTION__, __LINE__, ##__VA_ARGS__) +#endif +#endif + +#ifdef CONFIG_NF_FLOW_COOKIE +typedef int (*flow_cookie_set_func_t)(u32 protocol, __be32 src_ip, __be16 src_port, + __be32 dst_ip, __be16 dst_port, u16 flow_cookie); +/* + * sfe_register_flow_cookie_cb + * register a function in SFE to let SFE use this function to configure flow cookie for a flow + * + * Hardware driver which support flow cookie should register a callback function in SFE. Then SFE + * can use this function to configure flow cookie for a flow. + * return: 0, success; !=0, fail + */ +int sfe_register_flow_cookie_cb(flow_cookie_set_func_t cb); + +/* + * sfe_unregister_flow_cookie_cb + * unregister function which is used to configure flow cookie for a flow + * + * return: 0, success; !=0, fail + */ +int sfe_unregister_flow_cookie_cb(flow_cookie_set_func_t cb); + +typedef int (*sfe_ipv6_flow_cookie_set_func_t)(u32 protocol, __be32 src_ip[4], __be16 src_port, + __be32 dst_ip[4], __be16 dst_port, u16 flow_cookie); + +/* + * sfe_ipv6_register_flow_cookie_cb + * register a function in SFE to let SFE use this function to configure flow cookie for a flow + * + * Hardware driver which support flow cookie should register a callback function in SFE. Then SFE + * can use this function to configure flow cookie for a flow. + * return: 0, success; !=0, fail + */ +int sfe_ipv6_register_flow_cookie_cb(sfe_ipv6_flow_cookie_set_func_t cb); + +/* + * sfe_ipv6_unregister_flow_cookie_cb + * unregister function which is used to configure flow cookie for a flow + * + * return: 0, success; !=0, fail + */ +int sfe_ipv6_unregister_flow_cookie_cb(sfe_ipv6_flow_cookie_set_func_t cb); + +#endif /*CONFIG_NF_FLOW_COOKIE*/ diff --git a/shortcut-fe/shortcut-fe/src/sfe_backport.h b/shortcut-fe/shortcut-fe/src/sfe_backport.h new file mode 100644 index 000000000..d2d60c73c --- /dev/null +++ b/shortcut-fe/shortcut-fe/src/sfe_backport.h @@ -0,0 +1,195 @@ +/* + * sfe_backport.h + * Shortcut forwarding engine compatible header file. + * + * Copyright (c) 2014-2016 The Linux Foundation. All rights reserved. + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT + * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0)) +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 7, 0)) +#include +#else +enum udp_conntrack { + UDP_CT_UNREPLIED, + UDP_CT_REPLIED, + UDP_CT_MAX +}; + +static inline unsigned int * +nf_ct_timeout_lookup(struct net *net, struct nf_conn *ct, + struct nf_conntrack_l4proto *l4proto) +{ +#ifdef CONFIG_NF_CONNTRACK_TIMEOUT + struct nf_conn_timeout *timeout_ext; + unsigned int *timeouts; + + timeout_ext = nf_ct_timeout_find(ct); + if (timeout_ext) + timeouts = NF_CT_TIMEOUT_EXT_DATA(timeout_ext); + else + timeouts = l4proto->get_timeouts(net); + + return timeouts; +#else + return l4proto->get_timeouts(net); +#endif /*CONFIG_NF_CONNTRACK_TIMEOUT*/ +} +#endif /*KERNEL_VERSION(3, 7, 0)*/ +#endif /*KERNEL_VERSION(3, 4, 0)*/ + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)) +#define sfe_define_post_routing_hook(FN_NAME, HOOKNUM, OPS, SKB, UNUSED, OUT, OKFN) \ +static unsigned int FN_NAME(void *priv, \ + struct sk_buff *SKB, \ + const struct nf_hook_state *state) +#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 13, 0)) +#define sfe_define_post_routing_hook(FN_NAME, HOOKNUM, OPS, SKB, UNUSED, OUT, OKFN) \ +static unsigned int FN_NAME(const struct nf_hook_ops *OPS, \ + struct sk_buff *SKB, \ + const struct net_device *UNUSED, \ + const struct net_device *OUT, \ + int (*OKFN)(struct sk_buff *)) +#else +#define sfe_define_post_routing_hook(FN_NAME, HOOKNUM, OPS, SKB, UNUSED, OUT, OKFN) \ +static unsigned int FN_NAME(unsigned int HOOKNUM, \ + struct sk_buff *SKB, \ + const struct net_device *UNUSED, \ + const struct net_device *OUT, \ + int (*OKFN)(struct sk_buff *)) +#endif + +#define sfe_cm_ipv4_post_routing_hook(HOOKNUM, OPS, SKB, UNUSED, OUT, OKFN) \ + sfe_define_post_routing_hook(__sfe_cm_ipv4_post_routing_hook, HOOKNUM, OPS, SKB, UNUSED, OUT, OKFN) +#define sfe_cm_ipv6_post_routing_hook(HOOKNUM, OPS, SKB, UNUSED, OUT, OKFN) \ + sfe_define_post_routing_hook(__sfe_cm_ipv6_post_routing_hook, HOOKNUM, OPS, SKB, UNUSED, OUT, OKFN) +#define fast_classifier_ipv4_post_routing_hook(HOOKNUM, OPS, SKB, UNUSED, OUT, OKFN) \ + sfe_define_post_routing_hook(__fast_classifier_ipv4_post_routing_hook, HOOKNUM, OPS, SKB, UNUSED, OUT, OKFN) +#define fast_classifier_ipv6_post_routing_hook(HOOKNUM, OPS, SKB, UNUSED, OUT, OKFN) \ + sfe_define_post_routing_hook(__fast_classifier_ipv6_post_routing_hook, HOOKNUM, OPS, SKB, UNUSED, OUT, OKFN) + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)) +#define SFE_IPV4_NF_POST_ROUTING_HOOK(fn) \ + { \ + .hook = fn, \ + .pf = NFPROTO_IPV4, \ + .hooknum = NF_INET_POST_ROUTING, \ + .priority = NF_IP_PRI_NAT_SRC + 1, \ + } +#else +#define SFE_IPV4_NF_POST_ROUTING_HOOK(fn) \ + { \ + .hook = fn, \ + .owner = THIS_MODULE, \ + .pf = NFPROTO_IPV4, \ + .hooknum = NF_INET_POST_ROUTING, \ + .priority = NF_IP_PRI_NAT_SRC + 1, \ + } +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)) +#define SFE_IPV6_NF_POST_ROUTING_HOOK(fn) \ + { \ + .hook = fn, \ + .pf = NFPROTO_IPV6, \ + .hooknum = NF_INET_POST_ROUTING, \ + .priority = NF_IP_PRI_NAT_SRC + 1, \ + } +#else +#define SFE_IPV6_NF_POST_ROUTING_HOOK(fn) \ + { \ + .hook = fn, \ + .owner = THIS_MODULE, \ + .pf = NFPROTO_IPV6, \ + .hooknum = NF_INET_POST_ROUTING, \ + .priority = NF_IP6_PRI_NAT_SRC + 1, \ + } +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 3, 0)) +#define SFE_NF_CT_DEFAULT_ZONE (&nf_ct_zone_dflt) +#else +#define SFE_NF_CT_DEFAULT_ZONE NF_CT_DEFAULT_ZONE +#endif + +/* + * sfe_dev_get_master + * get master of bridge port, and hold it + */ +static inline struct net_device *sfe_dev_get_master(struct net_device *dev) +{ + struct net_device *master; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)) + rcu_read_lock(); + master = netdev_master_upper_dev_get_rcu(dev); + if (master) + dev_hold(master); + + rcu_read_unlock(); +#else + master = dev->master; + if (master) + dev_hold(master); +#endif + return master; +} + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) +#define SFE_DEV_EVENT_PTR(PTR) netdev_notifier_info_to_dev(PTR) +#else +#define SFE_DEV_EVENT_PTR(PTR) (struct net_device *)(PTR) +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 13, 0)) +#define SFE_NF_CONN_ACCT(NM) struct nf_conn_acct *NM +#else +#define SFE_NF_CONN_ACCT(NM) struct nf_conn_counter *NM +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 13, 0)) +#define SFE_ACCT_COUNTER(NM) ((NM)->counter) +#else +#define SFE_ACCT_COUNTER(NM) (NM) +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)) +#define sfe_hash_for_each_possible(name, obj, node, member, key) \ + hash_for_each_possible(name, obj, member, key) +#else +#define sfe_hash_for_each_possible(name, obj, node, member, key) \ + hash_for_each_possible(name, obj, node, member, key) +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)) +#define sfe_hash_for_each(name, bkt, node, obj, member) \ + hash_for_each(name, bkt, obj, member) +#else +#define sfe_hash_for_each(name, bkt, node, obj, member) \ + hash_for_each(name, bkt, node, obj, member) +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0)) +#define sfe_dst_get_neighbour(dst, daddr) dst_neigh_lookup(dst, addr) +#else +static inline struct neighbour * +sfe_dst_get_neighbour(struct dst_entry *dst, void *daddr) +{ + struct neighbour *neigh = dst_get_neighbour_noref(dst); + + if (neigh) + neigh_hold(neigh); + + return neigh; +} +#endif diff --git a/shortcut-fe/shortcut-fe/src/sfe_cm.c b/shortcut-fe/shortcut-fe/src/sfe_cm.c new file mode 100644 index 000000000..2d3f79a04 --- /dev/null +++ b/shortcut-fe/shortcut-fe/src/sfe_cm.c @@ -0,0 +1,1210 @@ +/* + * sfe-cm.c + * Shortcut forwarding engine connection manager. + * + * Copyright (c) 2013-2018, 2020 The Linux Foundation. All rights reserved. + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT + * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "sfe.h" +#include "sfe_cm.h" +#include "sfe_backport.h" + +typedef enum sfe_cm_exception { + SFE_CM_EXCEPTION_PACKET_BROADCAST, + SFE_CM_EXCEPTION_PACKET_MULTICAST, + SFE_CM_EXCEPTION_NO_IIF, + SFE_CM_EXCEPTION_NO_CT, + SFE_CM_EXCEPTION_CT_NO_TRACK, + SFE_CM_EXCEPTION_CT_NO_CONFIRM, + SFE_CM_EXCEPTION_CT_IS_ALG, + SFE_CM_EXCEPTION_IS_IPV4_MCAST, + SFE_CM_EXCEPTION_IS_IPV6_MCAST, + SFE_CM_EXCEPTION_TCP_NOT_ASSURED, + SFE_CM_EXCEPTION_TCP_NOT_ESTABLISHED, + SFE_CM_EXCEPTION_UNKNOW_PROTOCOL, + SFE_CM_EXCEPTION_NO_SRC_DEV, + SFE_CM_EXCEPTION_NO_SRC_XLATE_DEV, + SFE_CM_EXCEPTION_NO_DEST_DEV, + SFE_CM_EXCEPTION_NO_DEST_XLATE_DEV, + SFE_CM_EXCEPTION_NO_BRIDGE, + SFE_CM_EXCEPTION_LOCAL_OUT, + SFE_CM_EXCEPTION_MAX +} sfe_cm_exception_t; + +static char *sfe_cm_exception_events_string[SFE_CM_EXCEPTION_MAX] = { + "PACKET_BROADCAST", + "PACKET_MULTICAST", + "NO_IIF", + "NO_CT", + "CT_NO_TRACK", + "CT_NO_CONFIRM", + "CT_IS_ALG", + "IS_IPV4_MCAST", + "IS_IPV6_MCAST", + "TCP_NOT_ASSURED", + "TCP_NOT_ESTABLISHED", + "UNKNOW_PROTOCOL", + "NO_SRC_DEV", + "NO_SRC_XLATE_DEV", + "NO_DEST_DEV", + "NO_DEST_XLATE_DEV", + "NO_BRIDGE", + "LOCAL_OUT" +}; + +/* + * Per-module structure. + */ +struct sfe_cm { + spinlock_t lock; /* Lock for SMP correctness */ + + /* + * Control state. + */ + struct kobject *sys_sfe_cm; /* sysfs linkage */ + + /* + * Callback notifiers. + */ + struct notifier_block dev_notifier; /* Device notifier */ + struct notifier_block inet_notifier; /* IPv4 notifier */ + struct notifier_block inet6_notifier; /* IPv6 notifier */ + u32 exceptions[SFE_CM_EXCEPTION_MAX]; +}; + +static struct sfe_cm __sc; + +/* + * sfe_cm_incr_exceptions() + * increase an exception counter. + */ +static inline void sfe_cm_incr_exceptions(sfe_cm_exception_t except) +{ + struct sfe_cm *sc = &__sc; + + spin_lock_bh(&sc->lock); + sc->exceptions[except]++; + spin_unlock_bh(&sc->lock); +} + +/* + * sfe_cm_recv() + * Handle packet receives. + * + * Returns 1 if the packet is forwarded or 0 if it isn't. + */ +int sfe_cm_recv(struct sk_buff *skb) +{ + struct net_device *dev; + + /* + * We know that for the vast majority of packets we need the transport + * layer header so we may as well start to fetch it now! + */ + prefetch(skb->data + 32); + barrier(); + + dev = skb->dev; + + /* + * We're only interested in IPv4 and IPv6 packets. + */ + if (likely(htons(ETH_P_IP) == skb->protocol)) { + struct in_device *in_dev; + + /* + * Does our input device support IP processing? + */ + in_dev = (struct in_device *)dev->ip_ptr; + if (unlikely(!in_dev)) { + DEBUG_TRACE("no IP processing for device: %s\n", dev->name); + return 0; + } + + /* + * Does it have an IP address? If it doesn't then we can't do anything + * interesting here! + */ + if (unlikely(!in_dev->ifa_list)) { + DEBUG_TRACE("no IP address for device: %s\n", dev->name); + return 0; + } + + return sfe_ipv4_recv(dev, skb); + } + + if (likely(htons(ETH_P_IPV6) == skb->protocol)) { + struct inet6_dev *in_dev; + + /* + * Does our input device support IPv6 processing? + */ + in_dev = (struct inet6_dev *)dev->ip6_ptr; + if (unlikely(!in_dev)) { + DEBUG_TRACE("no IPv6 processing for device: %s\n", dev->name); + return 0; + } + + /* + * Does it have an IPv6 address? If it doesn't then we can't do anything + * interesting here! + */ + if (unlikely(list_empty(&in_dev->addr_list))) { + DEBUG_TRACE("no IPv6 address for device: %s\n", dev->name); + return 0; + } + + return sfe_ipv6_recv(dev, skb); + } + + DEBUG_TRACE("not IP packet\n"); + return 0; +} + +/* + * sfe_cm_find_dev_and_mac_addr() + * Find the device and MAC address for a given IPv4/IPv6 address. + * + * Returns true if we find the device and MAC address, otherwise false. + * + * We look up the rtable entry for the address and, from its neighbour + * structure, obtain the hardware address. This means this function also + * works if the neighbours are routers too. + */ +static bool sfe_cm_find_dev_and_mac_addr(struct sk_buff *skb, sfe_ip_addr_t *addr, struct net_device **dev, u8 *mac_addr, int is_v4) +{ + struct neighbour *neigh; + struct rtable *rt; + struct rt6_info *rt6; + struct dst_entry *dst; + struct net_device *mac_dev; + + /* + * If we have skb provided, use it as the original code is unable + * to lookup routes that are policy routed. + */ + if (unlikely(skb)) { + dst = skb_dst(skb); + goto skip_dst_lookup; + } + + /* + * Look up the rtable entry for the IP address then get the hardware + * address from its neighbour structure. This means this work when the + * neighbours are routers too. + */ + if (likely(is_v4)) { + rt = ip_route_output(&init_net, addr->ip, 0, 0, 0); + if (unlikely(IS_ERR(rt))) { + goto ret_fail; + } + + dst = (struct dst_entry *)rt; + } else { +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 17, 0)) + rt6 = rt6_lookup(&init_net, (struct in6_addr *)addr->ip6, 0, 0, 0); +#else + rt6 = rt6_lookup(&init_net, (struct in6_addr *)addr->ip6, 0, 0, NULL, 0); +#endif + if (!rt6) { + goto ret_fail; + } + + dst = (struct dst_entry *)rt6; + } + +skip_dst_lookup: + rcu_read_lock(); + neigh = sfe_dst_get_neighbour(dst, addr); + if (unlikely(!neigh)) { + rcu_read_unlock(); + if (likely(!skb)) + dst_release(dst); + goto ret_fail; + } + + if (unlikely(!(neigh->nud_state & NUD_VALID))) { + rcu_read_unlock(); + neigh_release(neigh); + if (likely(!skb)) + dst_release(dst); + goto ret_fail; + } + + mac_dev = neigh->dev; + if (!mac_dev) { + rcu_read_unlock(); + neigh_release(neigh); + if (likely(!skb)) + dst_release(dst); + goto ret_fail; + } + + memcpy(mac_addr, neigh->ha, (size_t)mac_dev->addr_len); + + dev_hold(mac_dev); + *dev = mac_dev; + rcu_read_unlock(); + neigh_release(neigh); + if (likely(!skb)) + dst_release(dst); + + return true; + +ret_fail: + if (is_v4) { + DEBUG_TRACE("failed to find MAC address for IP: %pI4\n", &addr->ip); + + } else { + DEBUG_TRACE("failed to find MAC address for IP: %pI6\n", addr->ip6); + } + + return false; +} + +/* + * sfe_cm_post_routing() + * Called for packets about to leave the box - either locally generated or forwarded from another interface + */ +static unsigned int sfe_cm_post_routing(struct sk_buff *skb, int is_v4) +{ + struct sfe_connection_create sic; + struct net_device *in; + struct nf_conn *ct; + enum ip_conntrack_info ctinfo; + struct net_device *dev; + struct net_device *src_dev; + struct net_device *dest_dev; + struct net_device *src_dev_tmp; + struct net_device *dest_dev_tmp; + struct net_device *src_br_dev = NULL; + struct net_device *dest_br_dev = NULL; + struct nf_conntrack_tuple orig_tuple; + struct nf_conntrack_tuple reply_tuple; + struct sk_buff *tmp_skb = NULL; + SFE_NF_CONN_ACCT(acct); + + #if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0) + struct net *net=NULL; + struct nf_tcp_net *tn=NULL; + #endif + + /* + * Don't process broadcast or multicast packets. + */ + if (unlikely(skb->pkt_type == PACKET_BROADCAST)) { + sfe_cm_incr_exceptions(SFE_CM_EXCEPTION_PACKET_BROADCAST); + DEBUG_TRACE("broadcast, ignoring\n"); + return NF_ACCEPT; + } + if (unlikely(skb->pkt_type == PACKET_MULTICAST)) { + sfe_cm_incr_exceptions(SFE_CM_EXCEPTION_PACKET_MULTICAST); + DEBUG_TRACE("multicast, ignoring\n"); + return NF_ACCEPT; + } + +#ifdef CONFIG_XFRM + /* + * Packet to xfrm for encapsulation, we can't process it + */ + if (unlikely(skb_dst(skb)->xfrm)) { + DEBUG_TRACE("packet to xfrm, ignoring\n"); + return NF_ACCEPT; + } +#endif + + /* + * Don't process locally generated packets. + */ + if (skb->sk) { + sfe_cm_incr_exceptions(SFE_CM_EXCEPTION_LOCAL_OUT); + DEBUG_TRACE("skip local out packet\n"); + return NF_ACCEPT; + } + + /* + * Don't process packets that are not being forwarded. + */ + in = dev_get_by_index(&init_net, skb->skb_iif); + if (!in) { + sfe_cm_incr_exceptions(SFE_CM_EXCEPTION_NO_IIF); + DEBUG_TRACE("packet not forwarding\n"); + return NF_ACCEPT; + } + + dev_put(in); + + /* + * Don't process packets that aren't being tracked by conntrack. + */ + ct = nf_ct_get(skb, &ctinfo); + if (unlikely(!ct)) { + sfe_cm_incr_exceptions(SFE_CM_EXCEPTION_NO_CT); + DEBUG_TRACE("no conntrack connection, ignoring\n"); + return NF_ACCEPT; + } + + /* + * Don't process untracked connections. + */ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 12, 0)) + if (unlikely(nf_ct_is_untracked(ct))) { +#else + if (unlikely(ctinfo == IP_CT_UNTRACKED)) { +#endif + sfe_cm_incr_exceptions(SFE_CM_EXCEPTION_CT_NO_TRACK); + DEBUG_TRACE("untracked connection\n"); + return NF_ACCEPT; + } + + /* + * Unconfirmed connection may be dropped by Linux at the final step, + * So we don't process unconfirmed connections. + */ + if (!nf_ct_is_confirmed(ct)) { + sfe_cm_incr_exceptions(SFE_CM_EXCEPTION_CT_NO_CONFIRM); + DEBUG_TRACE("unconfirmed connection\n"); + return NF_ACCEPT; + } + + /* + * Don't process connections that require support from a 'helper' (typically a NAT ALG). + */ + if (unlikely(nfct_help(ct))) { + sfe_cm_incr_exceptions(SFE_CM_EXCEPTION_CT_IS_ALG); + DEBUG_TRACE("connection has helper\n"); + return NF_ACCEPT; + } + + /* + * Check if the acceleration of a flow could be rejected quickly. + */ + acct = nf_conn_acct_find(ct); + if (acct) { + long long packets = atomic64_read(&SFE_ACCT_COUNTER(acct)[CTINFO2DIR(ctinfo)].packets); + if ((packets > 0xff) && (packets & 0xff)) { + /* + * Connection hits slow path at least 256 times, so it must be not able to accelerate. + * But we also give it a chance to walk through ECM every 256 packets + */ + return NF_ACCEPT; + } + } + + /* + * Look up the details of our connection in conntrack. + * + * Note that the data we get from conntrack is for the "ORIGINAL" direction + * but our packet may actually be in the "REPLY" direction. + */ + orig_tuple = ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple; + reply_tuple = ct->tuplehash[IP_CT_DIR_REPLY].tuple; + sic.protocol = (s32)orig_tuple.dst.protonum; + + sic.flags = 0; + + /* + * Get addressing information, non-NAT first + */ + if (likely(is_v4)) { + u32 dscp; + + sic.src_ip.ip = (__be32)orig_tuple.src.u3.ip; + sic.dest_ip.ip = (__be32)orig_tuple.dst.u3.ip; + + if (ipv4_is_multicast(sic.src_ip.ip) || ipv4_is_multicast(sic.dest_ip.ip)) { + sfe_cm_incr_exceptions(SFE_CM_EXCEPTION_IS_IPV4_MCAST); + DEBUG_TRACE("multicast address\n"); + return NF_ACCEPT; + } + + /* + * NAT'ed addresses - note these are as seen from the 'reply' direction + * When NAT does not apply to this connection these will be identical to the above. + */ + sic.src_ip_xlate.ip = (__be32)reply_tuple.dst.u3.ip; + sic.dest_ip_xlate.ip = (__be32)reply_tuple.src.u3.ip; + + dscp = ipv4_get_dsfield(ip_hdr(skb)) >> XT_DSCP_SHIFT; + if (dscp) { + sic.dest_dscp = dscp; + sic.src_dscp = sic.dest_dscp; + sic.flags |= SFE_CREATE_FLAG_REMARK_DSCP; + } + } else { + u32 dscp; + + sic.src_ip.ip6[0] = *((struct sfe_ipv6_addr *)&orig_tuple.src.u3.in6); + sic.dest_ip.ip6[0] = *((struct sfe_ipv6_addr *)&orig_tuple.dst.u3.in6); + + if (ipv6_addr_is_multicast((struct in6_addr *)sic.src_ip.ip6) || + ipv6_addr_is_multicast((struct in6_addr *)sic.dest_ip.ip6)) { + sfe_cm_incr_exceptions(SFE_CM_EXCEPTION_IS_IPV6_MCAST); + DEBUG_TRACE("multicast address\n"); + return NF_ACCEPT; + } + + /* + * NAT'ed addresses - note these are as seen from the 'reply' direction + * When NAT does not apply to this connection these will be identical to the above. + */ + sic.src_ip_xlate.ip6[0] = *((struct sfe_ipv6_addr *)&reply_tuple.dst.u3.in6); + sic.dest_ip_xlate.ip6[0] = *((struct sfe_ipv6_addr *)&reply_tuple.src.u3.in6); + + dscp = ipv6_get_dsfield(ipv6_hdr(skb)) >> XT_DSCP_SHIFT; + if (dscp) { + sic.dest_dscp = dscp; + sic.src_dscp = sic.dest_dscp; + sic.flags |= SFE_CREATE_FLAG_REMARK_DSCP; + } + } + + switch (sic.protocol) { + case IPPROTO_TCP: + sic.src_port = orig_tuple.src.u.tcp.port; + sic.dest_port = orig_tuple.dst.u.tcp.port; + sic.src_port_xlate = reply_tuple.dst.u.tcp.port; + sic.dest_port_xlate = reply_tuple.src.u.tcp.port; + sic.src_td_window_scale = ct->proto.tcp.seen[0].td_scale; + sic.src_td_max_window = ct->proto.tcp.seen[0].td_maxwin; + sic.src_td_end = ct->proto.tcp.seen[0].td_end; + sic.src_td_max_end = ct->proto.tcp.seen[0].td_maxend; + sic.dest_td_window_scale = ct->proto.tcp.seen[1].td_scale; + sic.dest_td_max_window = ct->proto.tcp.seen[1].td_maxwin; + sic.dest_td_end = ct->proto.tcp.seen[1].td_end; + sic.dest_td_max_end = ct->proto.tcp.seen[1].td_maxend; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0) + net = nf_ct_net(ct); + tn = nf_tcp_pernet(net); + if ((tn&&tn->tcp_no_window_check) +#else + if (nf_ct_tcp_no_window_check +#endif + || (ct->proto.tcp.seen[0].flags & IP_CT_TCP_FLAG_BE_LIBERAL) + || (ct->proto.tcp.seen[1].flags & IP_CT_TCP_FLAG_BE_LIBERAL)) { + sic.flags |= SFE_CREATE_FLAG_NO_SEQ_CHECK; + } + + /* + * Don't try to manage a non-established connection. + */ + if (!test_bit(IPS_ASSURED_BIT, &ct->status)) { + sfe_cm_incr_exceptions(SFE_CM_EXCEPTION_TCP_NOT_ASSURED); + DEBUG_TRACE("non-established connection\n"); + return NF_ACCEPT; + } + + /* + * If the connection is shutting down do not manage it. + * state can not be SYN_SENT, SYN_RECV because connection is assured + * Not managed states: FIN_WAIT, CLOSE_WAIT, LAST_ACK, TIME_WAIT, CLOSE. + */ + spin_lock_bh(&ct->lock); + if (ct->proto.tcp.state != TCP_CONNTRACK_ESTABLISHED) { + spin_unlock_bh(&ct->lock); + sfe_cm_incr_exceptions(SFE_CM_EXCEPTION_TCP_NOT_ESTABLISHED); + DEBUG_TRACE("connection in termination state: %#x, s: %pI4:%u, d: %pI4:%u\n", + ct->proto.tcp.state, &sic.src_ip, ntohs(sic.src_port), + &sic.dest_ip, ntohs(sic.dest_port)); + return NF_ACCEPT; + } + spin_unlock_bh(&ct->lock); + + /* + * Somehow, SFE is not playing nice with IPSec traffic. + * Do not accelerate for now. + */ + if (ntohs(sic.dest_port) == 4500 || ntohs(sic.dest_port) == 500) { + if (likely(is_v4)) + DEBUG_TRACE("IPsec bypass: %pI4:%d(%pI4:%d) to %pI4:%d(%pI4:%d)\n", + &sic.src_ip.ip, ntohs(sic.src_port), &sic.src_ip_xlate.ip, ntohs(sic.src_port_xlate), + &sic.dest_ip.ip, ntohs(sic.dest_port), &sic.dest_ip_xlate.ip, ntohs(sic.dest_port_xlate)); + else + DEBUG_TRACE("IPsec bypass: %pI6:%d to %pI6:%d\n", + &sic.src_ip.ip6, ntohs(sic.src_port), &sic.dest_ip.ip6, ntohs(sic.dest_port)); + return NF_ACCEPT; + } + break; + + case IPPROTO_UDP: + sic.src_port = orig_tuple.src.u.udp.port; + sic.dest_port = orig_tuple.dst.u.udp.port; + sic.src_port_xlate = reply_tuple.dst.u.udp.port; + sic.dest_port_xlate = reply_tuple.src.u.udp.port; + break; + + default: + sfe_cm_incr_exceptions(SFE_CM_EXCEPTION_UNKNOW_PROTOCOL); + DEBUG_TRACE("unhandled protocol %d\n", sic.protocol); + return NF_ACCEPT; + } + +#ifdef CONFIG_XFRM + sic.original_accel = 1; + sic.reply_accel = 1; + + /* + * For packets de-capsulated from xfrm, we still can accelerate it + * on the direction we just received the packet. + */ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0)) + if (unlikely(skb->sp)) { +#else + if (unlikely(secpath_exists(skb))) { +#endif + if (sic.protocol == IPPROTO_TCP && + !(sic.flags & SFE_CREATE_FLAG_NO_SEQ_CHECK)) { + return NF_ACCEPT; + } + + if (CTINFO2DIR(ctinfo) == IP_CT_DIR_ORIGINAL) { + sic.reply_accel = 0; + } else { + sic.original_accel = 0; + } + } +#endif + + /* + * Get QoS information + */ + if (skb->priority) { + sic.dest_priority = skb->priority; + sic.src_priority = sic.dest_priority; + sic.flags |= SFE_CREATE_FLAG_REMARK_PRIORITY; + } + + /* + * Get the net device and MAC addresses that correspond to the various source and + * destination host addresses. + */ + if (!sfe_cm_find_dev_and_mac_addr(NULL, &sic.src_ip, &src_dev_tmp, sic.src_mac, is_v4)) { + sfe_cm_incr_exceptions(SFE_CM_EXCEPTION_NO_SRC_DEV); + return NF_ACCEPT; + } + src_dev = src_dev_tmp; + + if (!sfe_cm_find_dev_and_mac_addr(NULL, &sic.src_ip_xlate, &dev, sic.src_mac_xlate, is_v4)) { + sfe_cm_incr_exceptions(SFE_CM_EXCEPTION_NO_SRC_XLATE_DEV); + goto done1; + } + dev_put(dev); + /* Somehow, for IPv6, we need this workaround as well */ + if (unlikely(!is_v4)) + tmp_skb = skb; + if (!sfe_cm_find_dev_and_mac_addr(tmp_skb, &sic.dest_ip, &dev, sic.dest_mac, is_v4)) { + sfe_cm_incr_exceptions(SFE_CM_EXCEPTION_NO_DEST_DEV); + goto done1; + } + dev_put(dev); + + if (!sfe_cm_find_dev_and_mac_addr(skb, &sic.dest_ip_xlate, &dest_dev_tmp, sic.dest_mac_xlate, is_v4)) { + sfe_cm_incr_exceptions(SFE_CM_EXCEPTION_NO_DEST_XLATE_DEV); + goto done1; + } + dest_dev = dest_dev_tmp; + + /* + * Our devices may actually be part of a bridge interface. If that's + * the case then find the bridge interface instead. + */ + if (src_dev->priv_flags & IFF_BRIDGE_PORT) { + src_br_dev = sfe_dev_get_master(src_dev); + if (!src_br_dev) { + sfe_cm_incr_exceptions(SFE_CM_EXCEPTION_NO_BRIDGE); + DEBUG_TRACE("no bridge found for: %s\n", src_dev->name); + goto done2; + } + src_dev = src_br_dev; + } + + if (dest_dev->priv_flags & IFF_BRIDGE_PORT) { + dest_br_dev = sfe_dev_get_master(dest_dev); + if (!dest_br_dev) { + sfe_cm_incr_exceptions(SFE_CM_EXCEPTION_NO_BRIDGE); + DEBUG_TRACE("no bridge found for: %s\n", dest_dev->name); + goto done3; + } + dest_dev = dest_br_dev; + } + + sic.src_dev = src_dev; + sic.dest_dev = dest_dev; + + sic.src_mtu = src_dev->mtu; + sic.dest_mtu = dest_dev->mtu; + + if (likely(is_v4)) { + sfe_ipv4_create_rule(&sic); + } else { + sfe_ipv6_create_rule(&sic); + } + + /* + * If we had bridge ports then release them too. + */ + if (dest_br_dev) { + dev_put(dest_br_dev); + } +done3: + if (src_br_dev) { + dev_put(src_br_dev); + } +done2: + dev_put(dest_dev_tmp); +done1: + dev_put(src_dev_tmp); + + return NF_ACCEPT; +} + +/* + * sfe_cm_ipv4_post_routing_hook() + * Called for packets about to leave the box - either locally generated or forwarded from another interface + */ +sfe_cm_ipv4_post_routing_hook(hooknum, ops, skb, in_unused, out, okfn) +{ + return sfe_cm_post_routing(skb, true); +} + +/* + * sfe_cm_ipv6_post_routing_hook() + * Called for packets about to leave the box - either locally generated or forwarded from another interface + */ +sfe_cm_ipv6_post_routing_hook(hooknum, ops, skb, in_unused, out, okfn) +{ + return sfe_cm_post_routing(skb, false); +} + +#ifdef CONFIG_NF_CONNTRACK_EVENTS +/* + * sfe_cm_conntrack_event() + * Callback event invoked when a conntrack connection's state changes. + */ +#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS +static int sfe_cm_conntrack_event(struct notifier_block *this, + unsigned long events, void *ptr) +#else +static int sfe_cm_conntrack_event(unsigned int events, struct nf_ct_event *item) +#endif +{ +#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS + struct nf_ct_event *item = ptr; +#endif + struct sfe_connection_destroy sid; + struct nf_conn *ct = item->ct; + struct nf_conntrack_tuple orig_tuple; + + /* + * If we don't have a conntrack entry then we're done. + */ + if (unlikely(!ct)) { + DEBUG_WARN("no ct in conntrack event callback\n"); + return NOTIFY_DONE; + } + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 12, 0)) + if (unlikely(nf_ct_is_untracked(ct))) { + DEBUG_TRACE("ignoring untracked conn\n"); + return NOTIFY_DONE; + } +#endif + + /* + * We're only interested in destroy events. + */ + if (unlikely(!(events & (1 << IPCT_DESTROY)))) { + DEBUG_TRACE("ignoring non-destroy event\n"); + return NOTIFY_DONE; + } + + orig_tuple = ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple; + sid.protocol = (s32)orig_tuple.dst.protonum; + + /* + * Extract information from the conntrack connection. We're only interested + * in nominal connection information (i.e. we're ignoring any NAT information). + */ + switch (sid.protocol) { + case IPPROTO_TCP: + sid.src_port = orig_tuple.src.u.tcp.port; + sid.dest_port = orig_tuple.dst.u.tcp.port; + break; + + case IPPROTO_UDP: + sid.src_port = orig_tuple.src.u.udp.port; + sid.dest_port = orig_tuple.dst.u.udp.port; + break; + + default: + DEBUG_TRACE("unhandled protocol: %d\n", sid.protocol); + return NOTIFY_DONE; + } + + if (likely(nf_ct_l3num(ct) == AF_INET)) { + sid.src_ip.ip = (__be32)orig_tuple.src.u3.ip; + sid.dest_ip.ip = (__be32)orig_tuple.dst.u3.ip; + + sfe_ipv4_destroy_rule(&sid); + } else if (likely(nf_ct_l3num(ct) == AF_INET6)) { + sid.src_ip.ip6[0] = *((struct sfe_ipv6_addr *)&orig_tuple.src.u3.in6); + sid.dest_ip.ip6[0] = *((struct sfe_ipv6_addr *)&orig_tuple.dst.u3.in6); + + sfe_ipv6_destroy_rule(&sid); + } else { + DEBUG_TRACE("ignoring non-IPv4 and non-IPv6 connection\n"); + } + + return NOTIFY_DONE; +} + +/* + * Netfilter conntrack event system to monitor connection tracking changes + */ +#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS +static struct notifier_block sfe_cm_conntrack_notifier = { + .notifier_call = sfe_cm_conntrack_event, +}; +#else +static struct nf_ct_event_notifier sfe_cm_conntrack_notifier = { + .fcn = sfe_cm_conntrack_event, +}; +#endif +#endif + +/* + * Structure to establish a hook into the post routing netfilter point - this + * will pick up local outbound and packets going from one interface to another. + * + * Note: see include/linux/netfilter_ipv4.h for info related to priority levels. + * We want to examine packets after NAT translation and any ALG processing. + */ +static struct nf_hook_ops sfe_cm_ops_post_routing[] __read_mostly = { + SFE_IPV4_NF_POST_ROUTING_HOOK(__sfe_cm_ipv4_post_routing_hook), +#ifdef SFE_SUPPORT_IPV6 + SFE_IPV6_NF_POST_ROUTING_HOOK(__sfe_cm_ipv6_post_routing_hook), +#endif +}; + +/* + * sfe_cm_sync_rule() + * Synchronize a connection's state. + */ +static void sfe_cm_sync_rule(struct sfe_connection_sync *sis) +{ + struct nf_conntrack_tuple_hash *h; + struct nf_conntrack_tuple tuple; + struct nf_conn *ct; + SFE_NF_CONN_ACCT(acct); + + /* + * Create a tuple so as to be able to look up a connection + */ + memset(&tuple, 0, sizeof(tuple)); + tuple.src.u.all = (__be16)sis->src_port; + tuple.dst.dir = IP_CT_DIR_ORIGINAL; + tuple.dst.protonum = (u8)sis->protocol; + tuple.dst.u.all = (__be16)sis->dest_port; + + if (sis->is_v6) { + tuple.src.u3.in6 = *((struct in6_addr *)sis->src_ip.ip6); + tuple.dst.u3.in6 = *((struct in6_addr *)sis->dest_ip.ip6); + tuple.src.l3num = AF_INET6; + + DEBUG_TRACE("update connection - p: %d, s: %pI6:%u, d: %pI6:%u\n", + (int)tuple.dst.protonum, + &tuple.src.u3.in6, (unsigned int)ntohs(tuple.src.u.all), + &tuple.dst.u3.in6, (unsigned int)ntohs(tuple.dst.u.all)); + } else { + tuple.src.u3.ip = sis->src_ip.ip; + tuple.dst.u3.ip = sis->dest_ip.ip; + tuple.src.l3num = AF_INET; + + DEBUG_TRACE("update connection - p: %d, s: %pI4:%u, d: %pI4:%u\n", + (int)tuple.dst.protonum, + &tuple.src.u3.ip, (unsigned int)ntohs(tuple.src.u.all), + &tuple.dst.u3.ip, (unsigned int)ntohs(tuple.dst.u.all)); + } + + /* + * Look up conntrack connection + */ + h = nf_conntrack_find_get(&init_net, SFE_NF_CT_DEFAULT_ZONE, &tuple); + if (unlikely(!h)) { + DEBUG_TRACE("no connection found\n"); + return; + } + + ct = nf_ct_tuplehash_to_ctrack(h); +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 9, 0)) + NF_CT_ASSERT(ct->timeout.data == (unsigned long)ct); +#endif + /* + * Only update if this is not a fixed timeout + */ + if (!test_bit(IPS_FIXED_TIMEOUT_BIT, &ct->status)) { + spin_lock_bh(&ct->lock); +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 9, 0)) + ct->timeout.expires += sis->delta_jiffies; +#else + ct->timeout += sis->delta_jiffies; +#endif + spin_unlock_bh(&ct->lock); + } + + acct = nf_conn_acct_find(ct); + if (acct) { + spin_lock_bh(&ct->lock); + atomic64_add(sis->src_new_packet_count, &SFE_ACCT_COUNTER(acct)[IP_CT_DIR_ORIGINAL].packets); + atomic64_add(sis->src_new_byte_count, &SFE_ACCT_COUNTER(acct)[IP_CT_DIR_ORIGINAL].bytes); + atomic64_add(sis->dest_new_packet_count, &SFE_ACCT_COUNTER(acct)[IP_CT_DIR_REPLY].packets); + atomic64_add(sis->dest_new_byte_count, &SFE_ACCT_COUNTER(acct)[IP_CT_DIR_REPLY].bytes); + spin_unlock_bh(&ct->lock); + } + + switch (sis->protocol) { + case IPPROTO_TCP: + spin_lock_bh(&ct->lock); + if (ct->proto.tcp.seen[0].td_maxwin < sis->src_td_max_window) { + ct->proto.tcp.seen[0].td_maxwin = sis->src_td_max_window; + } + if ((s32)(ct->proto.tcp.seen[0].td_end - sis->src_td_end) < 0) { + ct->proto.tcp.seen[0].td_end = sis->src_td_end; + } + if ((s32)(ct->proto.tcp.seen[0].td_maxend - sis->src_td_max_end) < 0) { + ct->proto.tcp.seen[0].td_maxend = sis->src_td_max_end; + } + if (ct->proto.tcp.seen[1].td_maxwin < sis->dest_td_max_window) { + ct->proto.tcp.seen[1].td_maxwin = sis->dest_td_max_window; + } + if ((s32)(ct->proto.tcp.seen[1].td_end - sis->dest_td_end) < 0) { + ct->proto.tcp.seen[1].td_end = sis->dest_td_end; + } + if ((s32)(ct->proto.tcp.seen[1].td_maxend - sis->dest_td_max_end) < 0) { + ct->proto.tcp.seen[1].td_maxend = sis->dest_td_max_end; + } + spin_unlock_bh(&ct->lock); + break; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0)) + case IPPROTO_UDP: + /* + * In Linux connection track, UDP flow has two timeout values: + * /proc/sys/net/netfilter/nf_conntrack_udp_timeout: + * this is for uni-direction UDP flow, normally its value is 60 seconds + * /proc/sys/net/netfilter/nf_conntrack_udp_timeout_stream: + * this is for bi-direction UDP flow, normally its value is 180 seconds + * + * Linux will update timer of UDP flow to stream timeout once it seen packets + * in reply direction. But if flow is accelerated by NSS or SFE, Linux won't + * see any packets. So we have to do the same thing in our stats sync message. + */ + if (!test_bit(IPS_ASSURED_BIT, &ct->status) && acct) { + u_int64_t reply_pkts = atomic64_read(&SFE_ACCT_COUNTER(acct)[IP_CT_DIR_REPLY].packets); + + if (reply_pkts != 0) { + unsigned int *timeouts; + struct nf_conntrack_l4proto *l4proto __maybe_unused; + set_bit(IPS_SEEN_REPLY_BIT, &ct->status); + set_bit(IPS_ASSURED_BIT, &ct->status); + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 19, 0)) + l4proto = __nf_ct_l4proto_find((sis->is_v6 ? AF_INET6 : AF_INET), IPPROTO_UDP); + timeouts = nf_ct_timeout_lookup(&init_net, ct, l4proto); + spin_lock_bh(&ct->lock); + ct->timeout.expires = jiffies + timeouts[UDP_CT_REPLIED]; + spin_unlock_bh(&ct->lock); +#else + timeouts = nf_ct_timeout_lookup(ct); + if (!timeouts) { + timeouts = nf_udp_pernet(nf_ct_net(ct))->timeouts; + } + + spin_lock_bh(&ct->lock); + ct->timeout = jiffies + timeouts[UDP_CT_REPLIED]; + spin_unlock_bh(&ct->lock); +#endif + } + } + break; +#endif /*KERNEL_VERSION(3, 4, 0)*/ + } + + /* + * Release connection + */ + nf_ct_put(ct); +} + +/* + * sfe_cm_device_event() + */ +int sfe_cm_device_event(struct notifier_block *this, unsigned long event, void *ptr) +{ + struct net_device *dev = SFE_DEV_EVENT_PTR(ptr); + + if (dev && (event == NETDEV_DOWN)) { + sfe_ipv4_destroy_all_rules_for_dev(dev); + sfe_ipv6_destroy_all_rules_for_dev(dev); + } + + return NOTIFY_DONE; +} + +/* + * sfe_cm_inet_event() + */ +static int sfe_cm_inet_event(struct notifier_block *this, unsigned long event, void *ptr) +{ + struct net_device *dev = ((struct in_ifaddr *)ptr)->ifa_dev->dev; + + if (dev && (event == NETDEV_DOWN)) { + sfe_ipv4_destroy_all_rules_for_dev(dev); + } + + return NOTIFY_DONE; +} + +/* + * sfe_cm_inet6_event() + */ +static int sfe_cm_inet6_event(struct notifier_block *this, unsigned long event, void *ptr) +{ + struct net_device *dev = ((struct inet6_ifaddr *)ptr)->idev->dev; + + if (dev && (event == NETDEV_DOWN)) { + sfe_ipv6_destroy_all_rules_for_dev(dev); + } + + return NOTIFY_DONE; +} + +/* + * sfe_cm_get_exceptions + * dump exception counters + */ +static ssize_t sfe_cm_get_exceptions(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + int idx, len; + struct sfe_cm *sc = &__sc; + + spin_lock_bh(&sc->lock); + for (len = 0, idx = 0; idx < SFE_CM_EXCEPTION_MAX; idx++) { + if (sc->exceptions[idx]) { + len += snprintf(buf + len, (ssize_t)(PAGE_SIZE - len), "%s = %d\n", sfe_cm_exception_events_string[idx], sc->exceptions[idx]); + } + } + spin_unlock_bh(&sc->lock); + + return len; +} + +/* + * sysfs attributes. + */ +static const struct device_attribute sfe_cm_exceptions_attr = + __ATTR(exceptions, S_IRUGO, sfe_cm_get_exceptions, NULL); + +/* + * sfe_cm_init() + */ +static int __init sfe_cm_init(void) +{ + struct sfe_cm *sc = &__sc; + int result = -1; +#ifdef CONFIG_SFE_ECM + int (*fast_recv)(struct sk_buff *skb); +#endif + + DEBUG_INFO("SFE CM init\n"); + + /* + * Create sys/sfe_cm + */ + sc->sys_sfe_cm = kobject_create_and_add("sfe_cm", NULL); + if (!sc->sys_sfe_cm) { + DEBUG_ERROR("failed to register sfe_cm\n"); + goto exit1; + } + + /* + * Create sys/sfe_cm/exceptions + */ + result = sysfs_create_file(sc->sys_sfe_cm, &sfe_cm_exceptions_attr.attr); + if (result) { + DEBUG_ERROR("failed to register exceptions file: %d\n", result); + goto exit2; + } + + sc->dev_notifier.notifier_call = sfe_cm_device_event; + sc->dev_notifier.priority = 1; + register_netdevice_notifier(&sc->dev_notifier); + + sc->inet_notifier.notifier_call = sfe_cm_inet_event; + sc->inet_notifier.priority = 1; + register_inetaddr_notifier(&sc->inet_notifier); + + sc->inet6_notifier.notifier_call = sfe_cm_inet6_event; + sc->inet6_notifier.priority = 1; + register_inet6addr_notifier(&sc->inet6_notifier); + /* + * Register our netfilter hooks. + */ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 13, 0)) + result = nf_register_hooks(sfe_cm_ops_post_routing, ARRAY_SIZE(sfe_cm_ops_post_routing)); +#else + result = nf_register_net_hooks(&init_net, sfe_cm_ops_post_routing, ARRAY_SIZE(sfe_cm_ops_post_routing)); +#endif + if (result < 0) { + DEBUG_ERROR("can't register nf post routing hook: %d\n", result); + goto exit3; + } + + /* + * Register a notifier hook to get fast notifications of expired connections. + * Note: In CONFIG_NF_CONNTRACK_CHAIN_EVENTS enabled case, nf_conntrack_register_notifier() + * function always returns 0. + */ +#ifdef CONFIG_NF_CONNTRACK_EVENTS +#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS + result = nf_conntrack_register_chain_notifier(&init_net, &sfe_cm_conntrack_notifier); +#else + result = nf_conntrack_register_notifier(&init_net, &sfe_cm_conntrack_notifier); +#endif + if (result < 0) { + DEBUG_ERROR("can't register nf notifier hook: %d\n", result); + goto exit4; + } +#endif + spin_lock_init(&sc->lock); + + /* + * Hook the receive path in the network stack. + */ +#ifdef CONFIG_SFE_ECM + rcu_read_lock(); + fast_recv = rcu_dereference(athrs_fast_nat_recv); + rcu_read_unlock(); + if (!fast_recv) { + BUG_ON(athrs_fast_nat_recv); + } +#else + BUG_ON(athrs_fast_nat_recv); +#endif + RCU_INIT_POINTER(athrs_fast_nat_recv, sfe_cm_recv); + + /* + * Hook the shortcut sync callback. + */ + sfe_ipv4_register_sync_rule_callback(sfe_cm_sync_rule); + sfe_ipv6_register_sync_rule_callback(sfe_cm_sync_rule); + return 0; + +#ifdef CONFIG_NF_CONNTRACK_EVENTS +exit4: +#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 13, 0)) + nf_unregister_hooks(sfe_cm_ops_post_routing, ARRAY_SIZE(sfe_cm_ops_post_routing)); +#else + nf_unregister_net_hooks(&init_net, sfe_cm_ops_post_routing, ARRAY_SIZE(sfe_cm_ops_post_routing)); +#endif + +#endif +#endif +exit3: + unregister_inet6addr_notifier(&sc->inet6_notifier); + unregister_inetaddr_notifier(&sc->inet_notifier); + unregister_netdevice_notifier(&sc->dev_notifier); +exit2: + kobject_put(sc->sys_sfe_cm); + +exit1: + return result; +} + +/* + * sfe_cm_exit() + */ +static void __exit sfe_cm_exit(void) +{ + struct sfe_cm *sc = &__sc; + + DEBUG_INFO("SFE CM exit\n"); + + /* + * Unregister our sync callback. + */ + sfe_ipv4_register_sync_rule_callback(NULL); + sfe_ipv6_register_sync_rule_callback(NULL); + + /* + * Unregister our receive callback. + */ + RCU_INIT_POINTER(athrs_fast_nat_recv, NULL); + + /* + * Wait for all callbacks to complete. + */ + rcu_barrier(); + + /* + * Destroy all connections. + */ + sfe_ipv4_destroy_all_rules_for_dev(NULL); + sfe_ipv6_destroy_all_rules_for_dev(NULL); + +#ifdef CONFIG_NF_CONNTRACK_EVENTS +#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS + nf_conntrack_unregister_chain_notifier(&init_net, &sfe_cm_conntrack_notifier); +#else + nf_conntrack_unregister_notifier(&init_net, &sfe_cm_conntrack_notifier); +#endif +#endif + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 13, 0)) + nf_unregister_hooks(sfe_cm_ops_post_routing, ARRAY_SIZE(sfe_cm_ops_post_routing)); +#else + nf_unregister_net_hooks(&init_net, sfe_cm_ops_post_routing, ARRAY_SIZE(sfe_cm_ops_post_routing)); +#endif + unregister_inet6addr_notifier(&sc->inet6_notifier); + unregister_inetaddr_notifier(&sc->inet_notifier); + unregister_netdevice_notifier(&sc->dev_notifier); + + kobject_put(sc->sys_sfe_cm); +} + +module_init(sfe_cm_init) +module_exit(sfe_cm_exit) + +MODULE_DESCRIPTION("Shortcut Forwarding Engine - Connection Manager"); +MODULE_LICENSE("Dual BSD/GPL"); + diff --git a/shortcut-fe/shortcut-fe/src/sfe_cm.h b/shortcut-fe/shortcut-fe/src/sfe_cm.h new file mode 100644 index 000000000..124c86f47 --- /dev/null +++ b/shortcut-fe/shortcut-fe/src/sfe_cm.h @@ -0,0 +1,260 @@ +/* + * sfe_cm.h + * Shortcut forwarding engine. + * + * Copyright (c) 2013-2016 The Linux Foundation. All rights reserved. + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT + * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +/* + * connection flags. + */ +#define SFE_CREATE_FLAG_NO_SEQ_CHECK BIT(0) + /* Indicates that we should not check sequence numbers */ +#define SFE_CREATE_FLAG_REMARK_PRIORITY BIT(1) + /* Indicates that we should remark priority of skb */ +#define SFE_CREATE_FLAG_REMARK_DSCP BIT(2) + /* Indicates that we should remark DSCP of packet */ + +/* + * IPv6 address structure + */ +struct sfe_ipv6_addr { + __be32 addr[4]; +}; + +typedef union { + __be32 ip; + struct sfe_ipv6_addr ip6[1]; +} sfe_ip_addr_t; + +/* + * connection creation structure. + */ +struct sfe_connection_create { + int protocol; + struct net_device *src_dev; + struct net_device *dest_dev; + u32 flags; + u32 src_mtu; + u32 dest_mtu; + sfe_ip_addr_t src_ip; + sfe_ip_addr_t src_ip_xlate; + sfe_ip_addr_t dest_ip; + sfe_ip_addr_t dest_ip_xlate; + __be16 src_port; + __be16 src_port_xlate; + __be16 dest_port; + __be16 dest_port_xlate; + u8 src_mac[ETH_ALEN]; + u8 src_mac_xlate[ETH_ALEN]; + u8 dest_mac[ETH_ALEN]; + u8 dest_mac_xlate[ETH_ALEN]; + u8 src_td_window_scale; + u32 src_td_max_window; + u32 src_td_end; + u32 src_td_max_end; + u8 dest_td_window_scale; + u32 dest_td_max_window; + u32 dest_td_end; + u32 dest_td_max_end; + u32 mark; +#ifdef CONFIG_XFRM + u32 original_accel; + u32 reply_accel; +#endif + u32 src_priority; + u32 dest_priority; + u32 src_dscp; + u32 dest_dscp; +}; + +/* + * connection destruction structure. + */ +struct sfe_connection_destroy { + int protocol; + sfe_ip_addr_t src_ip; + sfe_ip_addr_t dest_ip; + __be16 src_port; + __be16 dest_port; +}; + +typedef enum sfe_sync_reason { + SFE_SYNC_REASON_STATS, /* Sync is to synchronize stats */ + SFE_SYNC_REASON_FLUSH, /* Sync is to flush a entry */ + SFE_SYNC_REASON_DESTROY /* Sync is to destroy a entry(requested by connection manager) */ +} sfe_sync_reason_t; + +/* + * Structure used to sync connection stats/state back within the system. + * + * NOTE: The addresses here are NON-NAT addresses, i.e. the true endpoint addressing. + * 'src' is the creator of the connection. + */ +struct sfe_connection_sync { + struct net_device *src_dev; + struct net_device *dest_dev; + int is_v6; /* Is it for ipv6? */ + int protocol; /* IP protocol number (IPPROTO_...) */ + sfe_ip_addr_t src_ip; /* Non-NAT source address, i.e. the creator of the connection */ + sfe_ip_addr_t src_ip_xlate; /* NATed source address */ + __be16 src_port; /* Non-NAT source port */ + __be16 src_port_xlate; /* NATed source port */ + sfe_ip_addr_t dest_ip; /* Non-NAT destination address, i.e. to whom the connection was created */ + sfe_ip_addr_t dest_ip_xlate; /* NATed destination address */ + __be16 dest_port; /* Non-NAT destination port */ + __be16 dest_port_xlate; /* NATed destination port */ + u32 src_td_max_window; + u32 src_td_end; + u32 src_td_max_end; + u64 src_packet_count; + u64 src_byte_count; + u32 src_new_packet_count; + u32 src_new_byte_count; + u32 dest_td_max_window; + u32 dest_td_end; + u32 dest_td_max_end; + u64 dest_packet_count; + u64 dest_byte_count; + u32 dest_new_packet_count; + u32 dest_new_byte_count; + u32 reason; /* reason for stats sync message, i.e. destroy, flush, period sync */ + u64 delta_jiffies; /* Time to be added to the current timeout to keep the connection alive */ +}; + +/* + * connection mark structure + */ +struct sfe_connection_mark { + int protocol; + sfe_ip_addr_t src_ip; + sfe_ip_addr_t dest_ip; + __be16 src_port; + __be16 dest_port; + u32 mark; +}; + +/* + * Expose the hook for the receive processing. + */ +extern int (*athrs_fast_nat_recv)(struct sk_buff *skb); + +/* + * Expose what should be a static flag in the TCP connection tracker. + */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 15, 0) +extern int nf_ct_tcp_no_window_check; +#endif +/* + * This callback will be called in a timer + * at 100 times per second to sync stats back to + * Linux connection track. + * + * A RCU lock is taken to prevent this callback + * from unregistering. + */ +typedef void (*sfe_sync_rule_callback_t)(struct sfe_connection_sync *); + +/* + * IPv4 APIs used by connection manager + */ +int sfe_ipv4_recv(struct net_device *dev, struct sk_buff *skb); +int sfe_ipv4_create_rule(struct sfe_connection_create *sic); +void sfe_ipv4_destroy_rule(struct sfe_connection_destroy *sid); +void sfe_ipv4_destroy_all_rules_for_dev(struct net_device *dev); +void sfe_ipv4_register_sync_rule_callback(sfe_sync_rule_callback_t callback); +void sfe_ipv4_update_rule(struct sfe_connection_create *sic); +void sfe_ipv4_mark_rule(struct sfe_connection_mark *mark); + +#ifdef SFE_SUPPORT_IPV6 +/* + * IPv6 APIs used by connection manager + */ +int sfe_ipv6_recv(struct net_device *dev, struct sk_buff *skb); +int sfe_ipv6_create_rule(struct sfe_connection_create *sic); +void sfe_ipv6_destroy_rule(struct sfe_connection_destroy *sid); +void sfe_ipv6_destroy_all_rules_for_dev(struct net_device *dev); +void sfe_ipv6_register_sync_rule_callback(sfe_sync_rule_callback_t callback); +void sfe_ipv6_update_rule(struct sfe_connection_create *sic); +void sfe_ipv6_mark_rule(struct sfe_connection_mark *mark); +#else +static inline int sfe_ipv6_recv(struct net_device *dev, struct sk_buff *skb) +{ + return 0; +} + +static inline int sfe_ipv6_create_rule(struct sfe_connection_create *sic) +{ + return 0; +} + +static inline void sfe_ipv6_destroy_rule(struct sfe_connection_destroy *sid) +{ + return; +} + +static inline void sfe_ipv6_destroy_all_rules_for_dev(struct net_device *dev) +{ + return; +} + +static inline void sfe_ipv6_register_sync_rule_callback(sfe_sync_rule_callback_t callback) +{ + return; +} + +static inline void sfe_ipv6_update_rule(struct sfe_connection_create *sic) +{ + return; +} + +static inline void sfe_ipv6_mark_rule(struct sfe_connection_mark *mark) +{ + return; +} +#endif + +/* + * sfe_ipv6_addr_equal() + * compare ipv6 address + * + * return: 1, equal; 0, no equal + */ +static inline int sfe_ipv6_addr_equal(struct sfe_ipv6_addr *a, + struct sfe_ipv6_addr *b) +{ + return a->addr[0] == b->addr[0] && + a->addr[1] == b->addr[1] && + a->addr[2] == b->addr[2] && + a->addr[3] == b->addr[3]; +} + +/* + * sfe_ipv4_addr_equal() + * compare ipv4 address + * + * return: 1, equal; 0, no equal + */ +#define sfe_ipv4_addr_equal(a, b) ((u32)(a) == (u32)(b)) + +/* + * sfe_addr_equal() + * compare ipv4 or ipv6 address + * + * return: 1, equal; 0, no equal + */ +static inline int sfe_addr_equal(sfe_ip_addr_t *a, + sfe_ip_addr_t *b, int is_v4) +{ + return is_v4 ? sfe_ipv4_addr_equal(a->ip, b->ip) : sfe_ipv6_addr_equal(a->ip6, b->ip6); +} diff --git a/shortcut-fe/shortcut-fe/src/sfe_ipv4.c b/shortcut-fe/shortcut-fe/src/sfe_ipv4.c new file mode 100644 index 000000000..cdcdd66dd --- /dev/null +++ b/shortcut-fe/shortcut-fe/src/sfe_ipv4.c @@ -0,0 +1,3618 @@ +/* + * sfe_ipv4.c + * Shortcut forwarding engine - IPv4 edition. + * + * Copyright (c) 2013-2016, 2019-2020 The Linux Foundation. All rights reserved. + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT + * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "sfe.h" +#include "sfe_cm.h" + +/* + * By default Linux IP header and transport layer header structures are + * unpacked, assuming that such headers should be 32-bit aligned. + * Unfortunately some wireless adaptors can't cope with this requirement and + * some CPUs can't handle misaligned accesses. For those platforms we + * define SFE_IPV4_UNALIGNED_IP_HEADER and mark the structures as packed. + * When we do this the compiler will generate slightly worse code than for the + * aligned case (on most platforms) but will be much quicker than fixing + * things up in an unaligned trap handler. + */ +#define SFE_IPV4_UNALIGNED_IP_HEADER 1 +#if SFE_IPV4_UNALIGNED_IP_HEADER +#define SFE_IPV4_UNALIGNED_STRUCT __attribute__((packed)) +#else +#define SFE_IPV4_UNALIGNED_STRUCT +#endif + +/* + * An Ethernet header, but with an optional "packed" attribute to + * help with performance on some platforms (see the definition of + * SFE_IPV4_UNALIGNED_STRUCT) + */ +struct sfe_ipv4_eth_hdr { + __be16 h_dest[ETH_ALEN / 2]; + __be16 h_source[ETH_ALEN / 2]; + __be16 h_proto; +} SFE_IPV4_UNALIGNED_STRUCT; + +#define SFE_IPV4_DSCP_MASK 0x3 +#define SFE_IPV4_DSCP_SHIFT 2 + +/* + * An IPv4 header, but with an optional "packed" attribute to + * help with performance on some platforms (see the definition of + * SFE_IPV4_UNALIGNED_STRUCT) + */ +struct sfe_ipv4_ip_hdr { +#if defined(__LITTLE_ENDIAN_BITFIELD) + __u8 ihl:4, + version:4; +#elif defined (__BIG_ENDIAN_BITFIELD) + __u8 version:4, + ihl:4; +#else +#error "Please fix " +#endif + __u8 tos; + __be16 tot_len; + __be16 id; + __be16 frag_off; + __u8 ttl; + __u8 protocol; + __sum16 check; + __be32 saddr; + __be32 daddr; + + /* + * The options start here. + */ +} SFE_IPV4_UNALIGNED_STRUCT; + +/* + * A UDP header, but with an optional "packed" attribute to + * help with performance on some platforms (see the definition of + * SFE_IPV4_UNALIGNED_STRUCT) + */ +struct sfe_ipv4_udp_hdr { + __be16 source; + __be16 dest; + __be16 len; + __sum16 check; +} SFE_IPV4_UNALIGNED_STRUCT; + +/* + * A TCP header, but with an optional "packed" attribute to + * help with performance on some platforms (see the definition of + * SFE_IPV4_UNALIGNED_STRUCT) + */ +struct sfe_ipv4_tcp_hdr { + __be16 source; + __be16 dest; + __be32 seq; + __be32 ack_seq; +#if defined(__LITTLE_ENDIAN_BITFIELD) + __u16 res1:4, + doff:4, + fin:1, + syn:1, + rst:1, + psh:1, + ack:1, + urg:1, + ece:1, + cwr:1; +#elif defined(__BIG_ENDIAN_BITFIELD) + __u16 doff:4, + res1:4, + cwr:1, + ece:1, + urg:1, + ack:1, + psh:1, + rst:1, + syn:1, + fin:1; +#else +#error "Adjust your defines" +#endif + __be16 window; + __sum16 check; + __be16 urg_ptr; +} SFE_IPV4_UNALIGNED_STRUCT; + +/* + * Specifies the lower bound on ACK numbers carried in the TCP header + */ +#define SFE_IPV4_TCP_MAX_ACK_WINDOW 65520 + +/* + * IPv4 TCP connection match additional data. + */ +struct sfe_ipv4_tcp_connection_match { + u8 win_scale; /* Window scale */ + u32 max_win; /* Maximum window size seen */ + u32 end; /* Sequence number of the next byte to send (seq + segment length) */ + u32 max_end; /* Sequence number of the last byte to ack */ +}; + +/* + * Bit flags for IPv4 connection matching entry. + */ +#define SFE_IPV4_CONNECTION_MATCH_FLAG_XLATE_SRC (1<<0) + /* Perform source translation */ +#define SFE_IPV4_CONNECTION_MATCH_FLAG_XLATE_DEST (1<<1) + /* Perform destination translation */ +#define SFE_IPV4_CONNECTION_MATCH_FLAG_NO_SEQ_CHECK (1<<2) + /* Ignore TCP sequence numbers */ +#define SFE_IPV4_CONNECTION_MATCH_FLAG_WRITE_FAST_ETH_HDR (1<<3) + /* Fast Ethernet header write */ +#define SFE_IPV4_CONNECTION_MATCH_FLAG_WRITE_L2_HDR (1<<4) + /* Fast Ethernet header write */ +#define SFE_IPV4_CONNECTION_MATCH_FLAG_PRIORITY_REMARK (1<<5) + /* remark priority of SKB */ +#define SFE_IPV4_CONNECTION_MATCH_FLAG_DSCP_REMARK (1<<6) + /* remark DSCP of packet */ + +/* + * IPv4 connection matching structure. + */ +struct sfe_ipv4_connection_match { + /* + * References to other objects. + */ + struct sfe_ipv4_connection_match *next; + struct sfe_ipv4_connection_match *prev; + struct sfe_ipv4_connection *connection; + struct sfe_ipv4_connection_match *counter_match; + /* Matches the flow in the opposite direction as the one in *connection */ + struct sfe_ipv4_connection_match *active_next; + struct sfe_ipv4_connection_match *active_prev; + bool active; /* Flag to indicate if we're on the active list */ + + /* + * Characteristics that identify flows that match this rule. + */ + struct net_device *match_dev; /* Network device */ + u8 match_protocol; /* Protocol */ + __be32 match_src_ip; /* Source IP address */ + __be32 match_dest_ip; /* Destination IP address */ + __be16 match_src_port; /* Source port/connection ident */ + __be16 match_dest_port; /* Destination port/connection ident */ + + /* + * Control the operations of the match. + */ + u32 flags; /* Bit flags */ +#ifdef CONFIG_NF_FLOW_COOKIE + u32 flow_cookie; /* used flow cookie, for debug */ +#endif +#ifdef CONFIG_XFRM + u32 flow_accel; /* The flow accelerated or not */ +#endif + + /* + * Connection state that we track once we match. + */ + union { /* Protocol-specific state */ + struct sfe_ipv4_tcp_connection_match tcp; + } protocol_state; + /* + * Stats recorded in a sync period. These stats will be added to + * rx_packet_count64/rx_byte_count64 after a sync period. + */ + u32 rx_packet_count; + u32 rx_byte_count; + + /* + * Packet translation information. + */ + __be32 xlate_src_ip; /* Address after source translation */ + __be16 xlate_src_port; /* Port/connection ident after source translation */ + u16 xlate_src_csum_adjustment; + /* Transport layer checksum adjustment after source translation */ + u16 xlate_src_partial_csum_adjustment; + /* Transport layer pseudo header checksum adjustment after source translation */ + + __be32 xlate_dest_ip; /* Address after destination translation */ + __be16 xlate_dest_port; /* Port/connection ident after destination translation */ + u16 xlate_dest_csum_adjustment; + /* Transport layer checksum adjustment after destination translation */ + u16 xlate_dest_partial_csum_adjustment; + /* Transport layer pseudo header checksum adjustment after destination translation */ + + /* + * QoS information + */ + u32 priority; + u32 dscp; + + /* + * Packet transmit information. + */ + struct net_device *xmit_dev; /* Network device on which to transmit */ + unsigned short int xmit_dev_mtu; + /* Interface MTU */ + u16 xmit_dest_mac[ETH_ALEN / 2]; + /* Destination MAC address to use when forwarding */ + u16 xmit_src_mac[ETH_ALEN / 2]; + /* Source MAC address to use when forwarding */ + + /* + * Summary stats. + */ + u64 rx_packet_count64; + u64 rx_byte_count64; +}; + +/* + * Per-connection data structure. + */ +struct sfe_ipv4_connection { + struct sfe_ipv4_connection *next; + /* Pointer to the next entry in a hash chain */ + struct sfe_ipv4_connection *prev; + /* Pointer to the previous entry in a hash chain */ + int protocol; /* IP protocol number */ + __be32 src_ip; /* Src IP addr pre-translation */ + __be32 src_ip_xlate; /* Src IP addr post-translation */ + __be32 dest_ip; /* Dest IP addr pre-translation */ + __be32 dest_ip_xlate; /* Dest IP addr post-translation */ + __be16 src_port; /* Src port pre-translation */ + __be16 src_port_xlate; /* Src port post-translation */ + __be16 dest_port; /* Dest port pre-translation */ + __be16 dest_port_xlate; /* Dest port post-translation */ + struct sfe_ipv4_connection_match *original_match; + /* Original direction matching structure */ + struct net_device *original_dev; + /* Original direction source device */ + struct sfe_ipv4_connection_match *reply_match; + /* Reply direction matching structure */ + struct net_device *reply_dev; /* Reply direction source device */ + u64 last_sync_jiffies; /* Jiffies count for the last sync */ + struct sfe_ipv4_connection *all_connections_next; + /* Pointer to the next entry in the list of all connections */ + struct sfe_ipv4_connection *all_connections_prev; + /* Pointer to the previous entry in the list of all connections */ + u32 mark; /* mark for outgoing packet */ + u32 debug_read_seq; /* sequence number for debug dump */ +}; + +/* + * IPv4 connections and hash table size information. + */ +#define SFE_IPV4_CONNECTION_HASH_SHIFT 12 +#define SFE_IPV4_CONNECTION_HASH_SIZE (1 << SFE_IPV4_CONNECTION_HASH_SHIFT) +#define SFE_IPV4_CONNECTION_HASH_MASK (SFE_IPV4_CONNECTION_HASH_SIZE - 1) + +#ifdef CONFIG_NF_FLOW_COOKIE +#define SFE_FLOW_COOKIE_SIZE 2048 +#define SFE_FLOW_COOKIE_MASK 0x7ff + +struct sfe_flow_cookie_entry { + struct sfe_ipv4_connection_match *match; + unsigned long last_clean_time; +}; +#endif + +enum sfe_ipv4_exception_events { + SFE_IPV4_EXCEPTION_EVENT_UDP_HEADER_INCOMPLETE, + SFE_IPV4_EXCEPTION_EVENT_UDP_NO_CONNECTION, + SFE_IPV4_EXCEPTION_EVENT_UDP_IP_OPTIONS_OR_INITIAL_FRAGMENT, + SFE_IPV4_EXCEPTION_EVENT_UDP_SMALL_TTL, + SFE_IPV4_EXCEPTION_EVENT_UDP_NEEDS_FRAGMENTATION, + SFE_IPV4_EXCEPTION_EVENT_TCP_HEADER_INCOMPLETE, + SFE_IPV4_EXCEPTION_EVENT_TCP_NO_CONNECTION_SLOW_FLAGS, + SFE_IPV4_EXCEPTION_EVENT_TCP_NO_CONNECTION_FAST_FLAGS, + SFE_IPV4_EXCEPTION_EVENT_TCP_IP_OPTIONS_OR_INITIAL_FRAGMENT, + SFE_IPV4_EXCEPTION_EVENT_TCP_SMALL_TTL, + SFE_IPV4_EXCEPTION_EVENT_TCP_NEEDS_FRAGMENTATION, + SFE_IPV4_EXCEPTION_EVENT_TCP_FLAGS, + SFE_IPV4_EXCEPTION_EVENT_TCP_SEQ_EXCEEDS_RIGHT_EDGE, + SFE_IPV4_EXCEPTION_EVENT_TCP_SMALL_DATA_OFFS, + SFE_IPV4_EXCEPTION_EVENT_TCP_BAD_SACK, + SFE_IPV4_EXCEPTION_EVENT_TCP_BIG_DATA_OFFS, + SFE_IPV4_EXCEPTION_EVENT_TCP_SEQ_BEFORE_LEFT_EDGE, + SFE_IPV4_EXCEPTION_EVENT_TCP_ACK_EXCEEDS_RIGHT_EDGE, + SFE_IPV4_EXCEPTION_EVENT_TCP_ACK_BEFORE_LEFT_EDGE, + SFE_IPV4_EXCEPTION_EVENT_ICMP_HEADER_INCOMPLETE, + SFE_IPV4_EXCEPTION_EVENT_ICMP_UNHANDLED_TYPE, + SFE_IPV4_EXCEPTION_EVENT_ICMP_IPV4_HEADER_INCOMPLETE, + SFE_IPV4_EXCEPTION_EVENT_ICMP_IPV4_NON_V4, + SFE_IPV4_EXCEPTION_EVENT_ICMP_IPV4_IP_OPTIONS_INCOMPLETE, + SFE_IPV4_EXCEPTION_EVENT_ICMP_IPV4_UDP_HEADER_INCOMPLETE, + SFE_IPV4_EXCEPTION_EVENT_ICMP_IPV4_TCP_HEADER_INCOMPLETE, + SFE_IPV4_EXCEPTION_EVENT_ICMP_IPV4_UNHANDLED_PROTOCOL, + SFE_IPV4_EXCEPTION_EVENT_ICMP_NO_CONNECTION, + SFE_IPV4_EXCEPTION_EVENT_ICMP_FLUSHED_CONNECTION, + SFE_IPV4_EXCEPTION_EVENT_HEADER_INCOMPLETE, + SFE_IPV4_EXCEPTION_EVENT_BAD_TOTAL_LENGTH, + SFE_IPV4_EXCEPTION_EVENT_NON_V4, + SFE_IPV4_EXCEPTION_EVENT_NON_INITIAL_FRAGMENT, + SFE_IPV4_EXCEPTION_EVENT_DATAGRAM_INCOMPLETE, + SFE_IPV4_EXCEPTION_EVENT_IP_OPTIONS_INCOMPLETE, + SFE_IPV4_EXCEPTION_EVENT_UNHANDLED_PROTOCOL, + SFE_IPV4_EXCEPTION_EVENT_CLONED_SKB_UNSHARE_ERROR, + SFE_IPV4_EXCEPTION_EVENT_LAST +}; + +static char *sfe_ipv4_exception_events_string[SFE_IPV4_EXCEPTION_EVENT_LAST] = { + "UDP_HEADER_INCOMPLETE", + "UDP_NO_CONNECTION", + "UDP_IP_OPTIONS_OR_INITIAL_FRAGMENT", + "UDP_SMALL_TTL", + "UDP_NEEDS_FRAGMENTATION", + "TCP_HEADER_INCOMPLETE", + "TCP_NO_CONNECTION_SLOW_FLAGS", + "TCP_NO_CONNECTION_FAST_FLAGS", + "TCP_IP_OPTIONS_OR_INITIAL_FRAGMENT", + "TCP_SMALL_TTL", + "TCP_NEEDS_FRAGMENTATION", + "TCP_FLAGS", + "TCP_SEQ_EXCEEDS_RIGHT_EDGE", + "TCP_SMALL_DATA_OFFS", + "TCP_BAD_SACK", + "TCP_BIG_DATA_OFFS", + "TCP_SEQ_BEFORE_LEFT_EDGE", + "TCP_ACK_EXCEEDS_RIGHT_EDGE", + "TCP_ACK_BEFORE_LEFT_EDGE", + "ICMP_HEADER_INCOMPLETE", + "ICMP_UNHANDLED_TYPE", + "ICMP_IPV4_HEADER_INCOMPLETE", + "ICMP_IPV4_NON_V4", + "ICMP_IPV4_IP_OPTIONS_INCOMPLETE", + "ICMP_IPV4_UDP_HEADER_INCOMPLETE", + "ICMP_IPV4_TCP_HEADER_INCOMPLETE", + "ICMP_IPV4_UNHANDLED_PROTOCOL", + "ICMP_NO_CONNECTION", + "ICMP_FLUSHED_CONNECTION", + "HEADER_INCOMPLETE", + "BAD_TOTAL_LENGTH", + "NON_V4", + "NON_INITIAL_FRAGMENT", + "DATAGRAM_INCOMPLETE", + "IP_OPTIONS_INCOMPLETE", + "UNHANDLED_PROTOCOL", + "CLONED_SKB_UNSHARE_ERROR" +}; + +/* + * Per-module structure. + */ +struct sfe_ipv4 { + spinlock_t lock; /* Lock for SMP correctness */ + struct sfe_ipv4_connection_match *active_head; + /* Head of the list of recently active connections */ + struct sfe_ipv4_connection_match *active_tail; + /* Tail of the list of recently active connections */ + struct sfe_ipv4_connection *all_connections_head; + /* Head of the list of all connections */ + struct sfe_ipv4_connection *all_connections_tail; + /* Tail of the list of all connections */ + unsigned int num_connections; /* Number of connections */ + struct timer_list timer; /* Timer used for periodic sync ops */ + sfe_sync_rule_callback_t __rcu sync_rule_callback; + /* Callback function registered by a connection manager for stats syncing */ + struct sfe_ipv4_connection *conn_hash[SFE_IPV4_CONNECTION_HASH_SIZE]; + /* Connection hash table */ + struct sfe_ipv4_connection_match *conn_match_hash[SFE_IPV4_CONNECTION_HASH_SIZE]; + /* Connection match hash table */ +#ifdef CONFIG_NF_FLOW_COOKIE + struct sfe_flow_cookie_entry sfe_flow_cookie_table[SFE_FLOW_COOKIE_SIZE]; + /* flow cookie table*/ + flow_cookie_set_func_t flow_cookie_set_func; + /* function used to configure flow cookie in hardware*/ + int flow_cookie_enable; + /* Enable/disable flow cookie at runtime */ +#endif + + /* + * Stats recorded in a sync period. These stats will be added to + * connection_xxx64 after a sync period. + */ + u32 connection_create_requests; + /* Number of IPv4 connection create requests */ + u32 connection_create_collisions; + /* Number of IPv4 connection create requests that collided with existing hash table entries */ + u32 connection_destroy_requests; + /* Number of IPv4 connection destroy requests */ + u32 connection_destroy_misses; + /* Number of IPv4 connection destroy requests that missed our hash table */ + u32 connection_match_hash_hits; + /* Number of IPv4 connection match hash hits */ + u32 connection_match_hash_reorders; + /* Number of IPv4 connection match hash reorders */ + u32 connection_flushes; /* Number of IPv4 connection flushes */ + u32 packets_forwarded; /* Number of IPv4 packets forwarded */ + u32 packets_not_forwarded; /* Number of IPv4 packets not forwarded */ + u32 exception_events[SFE_IPV4_EXCEPTION_EVENT_LAST]; + + /* + * Summary statistics. + */ + u64 connection_create_requests64; + /* Number of IPv4 connection create requests */ + u64 connection_create_collisions64; + /* Number of IPv4 connection create requests that collided with existing hash table entries */ + u64 connection_destroy_requests64; + /* Number of IPv4 connection destroy requests */ + u64 connection_destroy_misses64; + /* Number of IPv4 connection destroy requests that missed our hash table */ + u64 connection_match_hash_hits64; + /* Number of IPv4 connection match hash hits */ + u64 connection_match_hash_reorders64; + /* Number of IPv4 connection match hash reorders */ + u64 connection_flushes64; /* Number of IPv4 connection flushes */ + u64 packets_forwarded64; /* Number of IPv4 packets forwarded */ + u64 packets_not_forwarded64; + /* Number of IPv4 packets not forwarded */ + u64 exception_events64[SFE_IPV4_EXCEPTION_EVENT_LAST]; + + /* + * Control state. + */ + struct kobject *sys_sfe_ipv4; /* sysfs linkage */ + int debug_dev; /* Major number of the debug char device */ + u32 debug_read_seq; /* sequence number for debug dump */ +}; + +/* + * Enumeration of the XML output. + */ +enum sfe_ipv4_debug_xml_states { + SFE_IPV4_DEBUG_XML_STATE_START, + SFE_IPV4_DEBUG_XML_STATE_CONNECTIONS_START, + SFE_IPV4_DEBUG_XML_STATE_CONNECTIONS_CONNECTION, + SFE_IPV4_DEBUG_XML_STATE_CONNECTIONS_END, + SFE_IPV4_DEBUG_XML_STATE_EXCEPTIONS_START, + SFE_IPV4_DEBUG_XML_STATE_EXCEPTIONS_EXCEPTION, + SFE_IPV4_DEBUG_XML_STATE_EXCEPTIONS_END, + SFE_IPV4_DEBUG_XML_STATE_STATS, + SFE_IPV4_DEBUG_XML_STATE_END, + SFE_IPV4_DEBUG_XML_STATE_DONE +}; + +/* + * XML write state. + */ +struct sfe_ipv4_debug_xml_write_state { + enum sfe_ipv4_debug_xml_states state; + /* XML output file state machine state */ + int iter_exception; /* Next exception iterator */ +}; + +typedef bool (*sfe_ipv4_debug_xml_write_method_t)(struct sfe_ipv4 *si, char *buffer, char *msg, size_t *length, + int *total_read, struct sfe_ipv4_debug_xml_write_state *ws); + +static struct sfe_ipv4 __si; + +/* + * sfe_ipv4_gen_ip_csum() + * Generate the IP checksum for an IPv4 header. + * + * Note that this function assumes that we have only 20 bytes of IP header. + */ +static inline u16 sfe_ipv4_gen_ip_csum(struct sfe_ipv4_ip_hdr *iph) +{ + u32 sum; + u16 *i = (u16 *)iph; + + iph->check = 0; + + /* + * Generate the sum. + */ + sum = i[0] + i[1] + i[2] + i[3] + i[4] + i[5] + i[6] + i[7] + i[8] + i[9]; + + /* + * Fold it to ones-complement form. + */ + sum = (sum & 0xffff) + (sum >> 16); + sum = (sum & 0xffff) + (sum >> 16); + + return (u16)sum ^ 0xffff; +} + +/* + * sfe_ipv4_get_connection_match_hash() + * Generate the hash used in connection match lookups. + */ +static inline unsigned int sfe_ipv4_get_connection_match_hash(struct net_device *dev, u8 protocol, + __be32 src_ip, __be16 src_port, + __be32 dest_ip, __be16 dest_port) +{ + size_t dev_addr = (size_t)dev; + u32 hash = ((u32)dev_addr) ^ ntohl(src_ip ^ dest_ip) ^ protocol ^ ntohs(src_port ^ dest_port); + return ((hash >> SFE_IPV4_CONNECTION_HASH_SHIFT) ^ hash) & SFE_IPV4_CONNECTION_HASH_MASK; +} + +/* + * sfe_ipv4_find_sfe_ipv4_connection_match() + * Get the IPv4 flow match info that corresponds to a particular 5-tuple. + * + * On entry we must be holding the lock that protects the hash table. + */ +static struct sfe_ipv4_connection_match * +sfe_ipv4_find_sfe_ipv4_connection_match(struct sfe_ipv4 *si, struct net_device *dev, u8 protocol, + __be32 src_ip, __be16 src_port, + __be32 dest_ip, __be16 dest_port) +{ + struct sfe_ipv4_connection_match *cm; + struct sfe_ipv4_connection_match *head; + unsigned int conn_match_idx; + + conn_match_idx = sfe_ipv4_get_connection_match_hash(dev, protocol, src_ip, src_port, dest_ip, dest_port); + cm = si->conn_match_hash[conn_match_idx]; + + /* + * If we don't have anything in this chain then bail. + */ + if (unlikely(!cm)) { + return NULL; + } + + /* + * Hopefully the first entry is the one we want. + */ + if ((cm->match_src_port == src_port) + && (cm->match_dest_port == dest_port) + && (cm->match_src_ip == src_ip) + && (cm->match_dest_ip == dest_ip) + && (cm->match_protocol == protocol) + && (cm->match_dev == dev)) { + si->connection_match_hash_hits++; + return cm; + } + + /* + * Unfortunately we didn't find it at head, so we search it in chain and + * move matching entry to the top of the hash chain. We presume that this + * will be reused again very quickly. + */ + head = cm; + do { + cm = cm->next; + } while (cm && (cm->match_src_port != src_port + || cm->match_dest_port != dest_port + || cm->match_src_ip != src_ip + || cm->match_dest_ip != dest_ip + || cm->match_protocol != protocol + || cm->match_dev != dev)); + + /* + * Not found then we're done. + */ + if (unlikely(!cm)) { + return NULL; + } + + /* + * We found a match so move it. + */ + if (cm->next) { + cm->next->prev = cm->prev; + } + cm->prev->next = cm->next; + cm->prev = NULL; + cm->next = head; + head->prev = cm; + si->conn_match_hash[conn_match_idx] = cm; + si->connection_match_hash_reorders++; + + return cm; +} + +/* + * sfe_ipv4_connection_match_update_summary_stats() + * Update the summary stats for a connection match entry. + */ +static inline void sfe_ipv4_connection_match_update_summary_stats(struct sfe_ipv4_connection_match *cm) +{ + cm->rx_packet_count64 += cm->rx_packet_count; + cm->rx_packet_count = 0; + cm->rx_byte_count64 += cm->rx_byte_count; + cm->rx_byte_count = 0; +} + +/* + * sfe_ipv4_connection_match_compute_translations() + * Compute port and address translations for a connection match entry. + */ +static void sfe_ipv4_connection_match_compute_translations(struct sfe_ipv4_connection_match *cm) +{ + /* + * Before we insert the entry look to see if this is tagged as doing address + * translations. If it is then work out the adjustment that we need to apply + * to the transport checksum. + */ + if (cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_XLATE_SRC) { + /* + * Precompute an incremental checksum adjustment so we can + * edit packets in this stream very quickly. The algorithm is from RFC1624. + */ + u16 src_ip_hi = cm->match_src_ip >> 16; + u16 src_ip_lo = cm->match_src_ip & 0xffff; + u32 xlate_src_ip = ~cm->xlate_src_ip; + u16 xlate_src_ip_hi = xlate_src_ip >> 16; + u16 xlate_src_ip_lo = xlate_src_ip & 0xffff; + u16 xlate_src_port = ~cm->xlate_src_port; + u32 adj; + + /* + * When we compute this fold it down to a 16-bit offset + * as that way we can avoid having to do a double + * folding of the twos-complement result because the + * addition of 2 16-bit values cannot cause a double + * wrap-around! + */ + adj = src_ip_hi + src_ip_lo + cm->match_src_port + + xlate_src_ip_hi + xlate_src_ip_lo + xlate_src_port; + adj = (adj & 0xffff) + (adj >> 16); + adj = (adj & 0xffff) + (adj >> 16); + cm->xlate_src_csum_adjustment = (u16)adj; + + } + + if (cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_XLATE_DEST) { + /* + * Precompute an incremental checksum adjustment so we can + * edit packets in this stream very quickly. The algorithm is from RFC1624. + */ + u16 dest_ip_hi = cm->match_dest_ip >> 16; + u16 dest_ip_lo = cm->match_dest_ip & 0xffff; + u32 xlate_dest_ip = ~cm->xlate_dest_ip; + u16 xlate_dest_ip_hi = xlate_dest_ip >> 16; + u16 xlate_dest_ip_lo = xlate_dest_ip & 0xffff; + u16 xlate_dest_port = ~cm->xlate_dest_port; + u32 adj; + + /* + * When we compute this fold it down to a 16-bit offset + * as that way we can avoid having to do a double + * folding of the twos-complement result because the + * addition of 2 16-bit values cannot cause a double + * wrap-around! + */ + adj = dest_ip_hi + dest_ip_lo + cm->match_dest_port + + xlate_dest_ip_hi + xlate_dest_ip_lo + xlate_dest_port; + adj = (adj & 0xffff) + (adj >> 16); + adj = (adj & 0xffff) + (adj >> 16); + cm->xlate_dest_csum_adjustment = (u16)adj; + } + + if (cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_XLATE_SRC) { + u32 adj = ~cm->match_src_ip + cm->xlate_src_ip; + if (adj < cm->xlate_src_ip) { + adj++; + } + + adj = (adj & 0xffff) + (adj >> 16); + adj = (adj & 0xffff) + (adj >> 16); + cm->xlate_src_partial_csum_adjustment = (u16)adj; + } + + if (cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_XLATE_DEST) { + u32 adj = ~cm->match_dest_ip + cm->xlate_dest_ip; + if (adj < cm->xlate_dest_ip) { + adj++; + } + + adj = (adj & 0xffff) + (adj >> 16); + adj = (adj & 0xffff) + (adj >> 16); + cm->xlate_dest_partial_csum_adjustment = (u16)adj; + } + +} + +/* + * sfe_ipv4_update_summary_stats() + * Update the summary stats. + */ +static void sfe_ipv4_update_summary_stats(struct sfe_ipv4 *si) +{ + int i; + + si->connection_create_requests64 += si->connection_create_requests; + si->connection_create_requests = 0; + si->connection_create_collisions64 += si->connection_create_collisions; + si->connection_create_collisions = 0; + si->connection_destroy_requests64 += si->connection_destroy_requests; + si->connection_destroy_requests = 0; + si->connection_destroy_misses64 += si->connection_destroy_misses; + si->connection_destroy_misses = 0; + si->connection_match_hash_hits64 += si->connection_match_hash_hits; + si->connection_match_hash_hits = 0; + si->connection_match_hash_reorders64 += si->connection_match_hash_reorders; + si->connection_match_hash_reorders = 0; + si->connection_flushes64 += si->connection_flushes; + si->connection_flushes = 0; + si->packets_forwarded64 += si->packets_forwarded; + si->packets_forwarded = 0; + si->packets_not_forwarded64 += si->packets_not_forwarded; + si->packets_not_forwarded = 0; + + for (i = 0; i < SFE_IPV4_EXCEPTION_EVENT_LAST; i++) { + si->exception_events64[i] += si->exception_events[i]; + si->exception_events[i] = 0; + } +} + +/* + * sfe_ipv4_insert_sfe_ipv4_connection_match() + * Insert a connection match into the hash. + * + * On entry we must be holding the lock that protects the hash table. + */ +static inline void sfe_ipv4_insert_sfe_ipv4_connection_match(struct sfe_ipv4 *si, + struct sfe_ipv4_connection_match *cm) +{ + struct sfe_ipv4_connection_match **hash_head; + struct sfe_ipv4_connection_match *prev_head; + unsigned int conn_match_idx + = sfe_ipv4_get_connection_match_hash(cm->match_dev, cm->match_protocol, + cm->match_src_ip, cm->match_src_port, + cm->match_dest_ip, cm->match_dest_port); + + hash_head = &si->conn_match_hash[conn_match_idx]; + prev_head = *hash_head; + cm->prev = NULL; + if (prev_head) { + prev_head->prev = cm; + } + + cm->next = prev_head; + *hash_head = cm; + +#ifdef CONFIG_NF_FLOW_COOKIE + if (!si->flow_cookie_enable) + return; + + /* + * Configure hardware to put a flow cookie in packet of this flow, + * then we can accelerate the lookup process when we received this packet. + */ + for (conn_match_idx = 1; conn_match_idx < SFE_FLOW_COOKIE_SIZE; conn_match_idx++) { + struct sfe_flow_cookie_entry *entry = &si->sfe_flow_cookie_table[conn_match_idx]; + + if ((NULL == entry->match) && time_is_before_jiffies(entry->last_clean_time + HZ)) { + flow_cookie_set_func_t func; + + rcu_read_lock(); + func = rcu_dereference(si->flow_cookie_set_func); + if (func) { + if (!func(cm->match_protocol, cm->match_src_ip, cm->match_src_port, + cm->match_dest_ip, cm->match_dest_port, conn_match_idx)) { + entry->match = cm; + cm->flow_cookie = conn_match_idx; + } + } + rcu_read_unlock(); + + break; + } + } +#endif +} + +/* + * sfe_ipv4_remove_sfe_ipv4_connection_match() + * Remove a connection match object from the hash. + * + * On entry we must be holding the lock that protects the hash table. + */ +static inline void sfe_ipv4_remove_sfe_ipv4_connection_match(struct sfe_ipv4 *si, struct sfe_ipv4_connection_match *cm) +{ +#ifdef CONFIG_NF_FLOW_COOKIE + if (si->flow_cookie_enable) { + /* + * Tell hardware that we no longer need a flow cookie in packet of this flow + */ + unsigned int conn_match_idx; + + for (conn_match_idx = 1; conn_match_idx < SFE_FLOW_COOKIE_SIZE; conn_match_idx++) { + struct sfe_flow_cookie_entry *entry = &si->sfe_flow_cookie_table[conn_match_idx]; + + if (cm == entry->match) { + flow_cookie_set_func_t func; + + rcu_read_lock(); + func = rcu_dereference(si->flow_cookie_set_func); + if (func) { + func(cm->match_protocol, cm->match_src_ip, cm->match_src_port, + cm->match_dest_ip, cm->match_dest_port, 0); + } + rcu_read_unlock(); + + cm->flow_cookie = 0; + entry->match = NULL; + entry->last_clean_time = jiffies; + break; + } + } + } +#endif + + /* + * Unlink the connection match entry from the hash. + */ + if (cm->prev) { + cm->prev->next = cm->next; + } else { + unsigned int conn_match_idx + = sfe_ipv4_get_connection_match_hash(cm->match_dev, cm->match_protocol, + cm->match_src_ip, cm->match_src_port, + cm->match_dest_ip, cm->match_dest_port); + si->conn_match_hash[conn_match_idx] = cm->next; + } + + if (cm->next) { + cm->next->prev = cm->prev; + } + + /* + * If the connection match entry is in the active list remove it. + */ + if (cm->active) { + if (likely(cm->active_prev)) { + cm->active_prev->active_next = cm->active_next; + } else { + si->active_head = cm->active_next; + } + + if (likely(cm->active_next)) { + cm->active_next->active_prev = cm->active_prev; + } else { + si->active_tail = cm->active_prev; + } + } +} + +/* + * sfe_ipv4_get_connection_hash() + * Generate the hash used in connection lookups. + */ +static inline unsigned int sfe_ipv4_get_connection_hash(u8 protocol, __be32 src_ip, __be16 src_port, + __be32 dest_ip, __be16 dest_port) +{ + u32 hash = ntohl(src_ip ^ dest_ip) ^ protocol ^ ntohs(src_port ^ dest_port); + return ((hash >> SFE_IPV4_CONNECTION_HASH_SHIFT) ^ hash) & SFE_IPV4_CONNECTION_HASH_MASK; +} + +/* + * sfe_ipv4_find_sfe_ipv4_connection() + * Get the IPv4 connection info that corresponds to a particular 5-tuple. + * + * On entry we must be holding the lock that protects the hash table. + */ +static inline struct sfe_ipv4_connection *sfe_ipv4_find_sfe_ipv4_connection(struct sfe_ipv4 *si, u32 protocol, + __be32 src_ip, __be16 src_port, + __be32 dest_ip, __be16 dest_port) +{ + struct sfe_ipv4_connection *c; + unsigned int conn_idx = sfe_ipv4_get_connection_hash(protocol, src_ip, src_port, dest_ip, dest_port); + c = si->conn_hash[conn_idx]; + + /* + * If we don't have anything in this chain then bale. + */ + if (unlikely(!c)) { + return NULL; + } + + /* + * Hopefully the first entry is the one we want. + */ + if ((c->src_port == src_port) + && (c->dest_port == dest_port) + && (c->src_ip == src_ip) + && (c->dest_ip == dest_ip) + && (c->protocol == protocol)) { + return c; + } + + /* + * Unfortunately we didn't find it at head, so we search it in chain. + */ + do { + c = c->next; + } while (c && (c->src_port != src_port + || c->dest_port != dest_port + || c->src_ip != src_ip + || c->dest_ip != dest_ip + || c->protocol != protocol)); + + /* + * Will need connection entry for next create/destroy metadata, + * So no need to re-order entry for these requests + */ + return c; +} + +/* + * sfe_ipv4_mark_rule() + * Updates the mark for a current offloaded connection + * + * Will take hash lock upon entry + */ +void sfe_ipv4_mark_rule(struct sfe_connection_mark *mark) +{ + struct sfe_ipv4 *si = &__si; + struct sfe_ipv4_connection *c; + + spin_lock_bh(&si->lock); + c = sfe_ipv4_find_sfe_ipv4_connection(si, mark->protocol, + mark->src_ip.ip, mark->src_port, + mark->dest_ip.ip, mark->dest_port); + if (c) { + WARN_ON((0 != c->mark) && (0 == mark->mark)); + c->mark = mark->mark; + } + spin_unlock_bh(&si->lock); + + if (c) { + DEBUG_TRACE("Matching connection found for mark, " + "setting from %08x to %08x\n", + c->mark, mark->mark); + } +} + +/* + * sfe_ipv4_insert_sfe_ipv4_connection() + * Insert a connection into the hash. + * + * On entry we must be holding the lock that protects the hash table. + */ +static void sfe_ipv4_insert_sfe_ipv4_connection(struct sfe_ipv4 *si, struct sfe_ipv4_connection *c) +{ + struct sfe_ipv4_connection **hash_head; + struct sfe_ipv4_connection *prev_head; + unsigned int conn_idx; + + /* + * Insert entry into the connection hash. + */ + conn_idx = sfe_ipv4_get_connection_hash(c->protocol, c->src_ip, c->src_port, + c->dest_ip, c->dest_port); + hash_head = &si->conn_hash[conn_idx]; + prev_head = *hash_head; + c->prev = NULL; + if (prev_head) { + prev_head->prev = c; + } + + c->next = prev_head; + *hash_head = c; + + /* + * Insert entry into the "all connections" list. + */ + if (si->all_connections_tail) { + c->all_connections_prev = si->all_connections_tail; + si->all_connections_tail->all_connections_next = c; + } else { + c->all_connections_prev = NULL; + si->all_connections_head = c; + } + + si->all_connections_tail = c; + c->all_connections_next = NULL; + si->num_connections++; + + /* + * Insert the connection match objects too. + */ + sfe_ipv4_insert_sfe_ipv4_connection_match(si, c->original_match); + sfe_ipv4_insert_sfe_ipv4_connection_match(si, c->reply_match); +} + +/* + * sfe_ipv4_remove_sfe_ipv4_connection() + * Remove a sfe_ipv4_connection object from the hash. + * + * On entry we must be holding the lock that protects the hash table. + */ +static void sfe_ipv4_remove_sfe_ipv4_connection(struct sfe_ipv4 *si, struct sfe_ipv4_connection *c) +{ + /* + * Remove the connection match objects. + */ + sfe_ipv4_remove_sfe_ipv4_connection_match(si, c->reply_match); + sfe_ipv4_remove_sfe_ipv4_connection_match(si, c->original_match); + + /* + * Unlink the connection. + */ + if (c->prev) { + c->prev->next = c->next; + } else { + unsigned int conn_idx = sfe_ipv4_get_connection_hash(c->protocol, c->src_ip, c->src_port, + c->dest_ip, c->dest_port); + si->conn_hash[conn_idx] = c->next; + } + + if (c->next) { + c->next->prev = c->prev; + } + + /* + * Unlink connection from all_connections list + */ + if (c->all_connections_prev) { + c->all_connections_prev->all_connections_next = c->all_connections_next; + } else { + si->all_connections_head = c->all_connections_next; + } + + if (c->all_connections_next) { + c->all_connections_next->all_connections_prev = c->all_connections_prev; + } else { + si->all_connections_tail = c->all_connections_prev; + } + + si->num_connections--; +} + +/* + * sfe_ipv4_sync_sfe_ipv4_connection() + * Sync a connection. + * + * On entry to this function we expect that the lock for the connection is either + * already held or isn't required. + */ +static void sfe_ipv4_gen_sync_sfe_ipv4_connection(struct sfe_ipv4 *si, struct sfe_ipv4_connection *c, + struct sfe_connection_sync *sis, sfe_sync_reason_t reason, + u64 now_jiffies) +{ + struct sfe_ipv4_connection_match *original_cm; + struct sfe_ipv4_connection_match *reply_cm; + + /* + * Fill in the update message. + */ + sis->is_v6 = 0; + sis->protocol = c->protocol; + sis->src_ip.ip = c->src_ip; + sis->src_ip_xlate.ip = c->src_ip_xlate; + sis->dest_ip.ip = c->dest_ip; + sis->dest_ip_xlate.ip = c->dest_ip_xlate; + sis->src_port = c->src_port; + sis->src_port_xlate = c->src_port_xlate; + sis->dest_port = c->dest_port; + sis->dest_port_xlate = c->dest_port_xlate; + + original_cm = c->original_match; + reply_cm = c->reply_match; + sis->src_td_max_window = original_cm->protocol_state.tcp.max_win; + sis->src_td_end = original_cm->protocol_state.tcp.end; + sis->src_td_max_end = original_cm->protocol_state.tcp.max_end; + sis->dest_td_max_window = reply_cm->protocol_state.tcp.max_win; + sis->dest_td_end = reply_cm->protocol_state.tcp.end; + sis->dest_td_max_end = reply_cm->protocol_state.tcp.max_end; + + sis->src_new_packet_count = original_cm->rx_packet_count; + sis->src_new_byte_count = original_cm->rx_byte_count; + sis->dest_new_packet_count = reply_cm->rx_packet_count; + sis->dest_new_byte_count = reply_cm->rx_byte_count; + + sfe_ipv4_connection_match_update_summary_stats(original_cm); + sfe_ipv4_connection_match_update_summary_stats(reply_cm); + + sis->src_dev = original_cm->match_dev; + sis->src_packet_count = original_cm->rx_packet_count64; + sis->src_byte_count = original_cm->rx_byte_count64; + + sis->dest_dev = reply_cm->match_dev; + sis->dest_packet_count = reply_cm->rx_packet_count64; + sis->dest_byte_count = reply_cm->rx_byte_count64; + + sis->reason = reason; + + /* + * Get the time increment since our last sync. + */ + sis->delta_jiffies = now_jiffies - c->last_sync_jiffies; + c->last_sync_jiffies = now_jiffies; +} + +/* + * sfe_ipv4_flush_sfe_ipv4_connection() + * Flush a connection and free all associated resources. + * + * We need to be called with bottom halves disabled locally as we need to acquire + * the connection hash lock and release it again. In general we're actually called + * from within a BH and so we're fine, but we're also called when connections are + * torn down. + */ +static void sfe_ipv4_flush_sfe_ipv4_connection(struct sfe_ipv4 *si, + struct sfe_ipv4_connection *c, + sfe_sync_reason_t reason) +{ + struct sfe_connection_sync sis; + u64 now_jiffies; + sfe_sync_rule_callback_t sync_rule_callback; + + rcu_read_lock(); + spin_lock_bh(&si->lock); + si->connection_flushes++; + sync_rule_callback = rcu_dereference(si->sync_rule_callback); + spin_unlock_bh(&si->lock); + + if (sync_rule_callback) { + /* + * Generate a sync message and then sync. + */ + now_jiffies = get_jiffies_64(); + sfe_ipv4_gen_sync_sfe_ipv4_connection(si, c, &sis, reason, now_jiffies); + sync_rule_callback(&sis); + } + + rcu_read_unlock(); + + /* + * Release our hold of the source and dest devices and free the memory + * for our connection objects. + */ + dev_put(c->original_dev); + dev_put(c->reply_dev); + kfree(c->original_match); + kfree(c->reply_match); + kfree(c); +} + +/* + * sfe_ipv4_recv_udp() + * Handle UDP packet receives and forwarding. + */ +static int sfe_ipv4_recv_udp(struct sfe_ipv4 *si, struct sk_buff *skb, struct net_device *dev, + unsigned int len, struct sfe_ipv4_ip_hdr *iph, unsigned int ihl, bool flush_on_find) +{ + struct sfe_ipv4_udp_hdr *udph; + __be32 src_ip; + __be32 dest_ip; + __be16 src_port; + __be16 dest_port; + struct sfe_ipv4_connection_match *cm; + u8 ttl; + struct net_device *xmit_dev; + + /* + * Is our packet too short to contain a valid UDP header? + */ + if (unlikely(!pskb_may_pull(skb, (sizeof(struct sfe_ipv4_udp_hdr) + ihl)))) { + spin_lock_bh(&si->lock); + si->exception_events[SFE_IPV4_EXCEPTION_EVENT_UDP_HEADER_INCOMPLETE]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("packet too short for UDP header\n"); + return 0; + } + + /* + * Read the IP address and port information. Read the IP header data first + * because we've almost certainly got that in the cache. We may not yet have + * the UDP header cached though so allow more time for any prefetching. + */ + src_ip = iph->saddr; + dest_ip = iph->daddr; + + udph = (struct sfe_ipv4_udp_hdr *)(skb->data + ihl); + src_port = udph->source; + dest_port = udph->dest; + + spin_lock_bh(&si->lock); + + /* + * Look for a connection match. + */ +#ifdef CONFIG_NF_FLOW_COOKIE + cm = si->sfe_flow_cookie_table[skb->flow_cookie & SFE_FLOW_COOKIE_MASK].match; + if (unlikely(!cm)) { + cm = sfe_ipv4_find_sfe_ipv4_connection_match(si, dev, IPPROTO_UDP, src_ip, src_port, dest_ip, dest_port); + } +#else + cm = sfe_ipv4_find_sfe_ipv4_connection_match(si, dev, IPPROTO_UDP, src_ip, src_port, dest_ip, dest_port); +#endif + if (unlikely(!cm)) { + si->exception_events[SFE_IPV4_EXCEPTION_EVENT_UDP_NO_CONNECTION]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("no connection found\n"); + return 0; + } + + /* + * If our packet has beern marked as "flush on find" we can't actually + * forward it in the fast path, but now that we've found an associated + * connection we can flush that out before we process the packet. + */ + if (unlikely(flush_on_find)) { + struct sfe_ipv4_connection *c = cm->connection; + sfe_ipv4_remove_sfe_ipv4_connection(si, c); + si->exception_events[SFE_IPV4_EXCEPTION_EVENT_UDP_IP_OPTIONS_OR_INITIAL_FRAGMENT]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("flush on find\n"); + sfe_ipv4_flush_sfe_ipv4_connection(si, c, SFE_SYNC_REASON_FLUSH); + return 0; + } + +#ifdef CONFIG_XFRM + /* + * We can't accelerate the flow on this direction, just let it go + * through the slow path. + */ + if (unlikely(!cm->flow_accel)) { + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + return 0; + } +#endif + + /* + * Does our TTL allow forwarding? + */ + ttl = iph->ttl; + if (unlikely(ttl < 2)) { + struct sfe_ipv4_connection *c = cm->connection; + sfe_ipv4_remove_sfe_ipv4_connection(si, c); + si->exception_events[SFE_IPV4_EXCEPTION_EVENT_UDP_SMALL_TTL]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("ttl too low\n"); + sfe_ipv4_flush_sfe_ipv4_connection(si, c, SFE_SYNC_REASON_FLUSH); + return 0; + } + + /* + * If our packet is larger than the MTU of the transmit interface then + * we can't forward it easily. + */ + if (unlikely(len > cm->xmit_dev_mtu)) { + struct sfe_ipv4_connection *c = cm->connection; + sfe_ipv4_remove_sfe_ipv4_connection(si, c); + si->exception_events[SFE_IPV4_EXCEPTION_EVENT_UDP_NEEDS_FRAGMENTATION]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("larger than mtu\n"); + sfe_ipv4_flush_sfe_ipv4_connection(si, c, SFE_SYNC_REASON_FLUSH); + return 0; + } + + /* + * From this point on we're good to modify the packet. + */ + + /* + * Check if skb was cloned. If it was, unshare it. Because + * the data area is going to be written in this path and we don't want to + * change the cloned skb's data section. + */ + if (unlikely(skb_cloned(skb))) { + DEBUG_TRACE("%px: skb is a cloned skb\n", skb); + skb = skb_unshare(skb, GFP_ATOMIC); + if (!skb) { + DEBUG_WARN("Failed to unshare the cloned skb\n"); + si->exception_events[SFE_IPV4_EXCEPTION_EVENT_CLONED_SKB_UNSHARE_ERROR]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + return 0; + } + + /* + * Update the iph and udph pointers with the unshared skb's data area. + */ + iph = (struct sfe_ipv4_ip_hdr *)skb->data; + udph = (struct sfe_ipv4_udp_hdr *)(skb->data + ihl); + } + + /* + * Update DSCP + */ + if (unlikely(cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_DSCP_REMARK)) { + iph->tos = (iph->tos & SFE_IPV4_DSCP_MASK) | cm->dscp; + } + + /* + * Decrement our TTL. + */ + iph->ttl = ttl - 1; + + /* + * Do we have to perform translations of the source address/port? + */ + if (unlikely(cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_XLATE_SRC)) { + u16 udp_csum; + + iph->saddr = cm->xlate_src_ip; + udph->source = cm->xlate_src_port; + + /* + * Do we have a non-zero UDP checksum? If we do then we need + * to update it. + */ + udp_csum = udph->check; + if (likely(udp_csum)) { + u32 sum; + + if (unlikely(skb->ip_summed == CHECKSUM_PARTIAL)) { + sum = udp_csum + cm->xlate_src_partial_csum_adjustment; + } else { + sum = udp_csum + cm->xlate_src_csum_adjustment; + } + + sum = (sum & 0xffff) + (sum >> 16); + udph->check = (u16)sum; + } + } + + /* + * Do we have to perform translations of the destination address/port? + */ + if (unlikely(cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_XLATE_DEST)) { + u16 udp_csum; + + iph->daddr = cm->xlate_dest_ip; + udph->dest = cm->xlate_dest_port; + + /* + * Do we have a non-zero UDP checksum? If we do then we need + * to update it. + */ + udp_csum = udph->check; + if (likely(udp_csum)) { + u32 sum; + + if (unlikely(skb->ip_summed == CHECKSUM_PARTIAL)) { + sum = udp_csum + cm->xlate_dest_partial_csum_adjustment; + } else { + sum = udp_csum + cm->xlate_dest_csum_adjustment; + } + + sum = (sum & 0xffff) + (sum >> 16); + udph->check = (u16)sum; + } + } + + /* + * Replace the IP checksum. + */ + iph->check = sfe_ipv4_gen_ip_csum(iph); + + /* + * Update traffic stats. + */ + cm->rx_packet_count++; + cm->rx_byte_count += len; + + /* + * If we're not already on the active list then insert ourselves at the tail + * of the current list. + */ + if (unlikely(!cm->active)) { + cm->active = true; + cm->active_prev = si->active_tail; + if (likely(si->active_tail)) { + si->active_tail->active_next = cm; + } else { + si->active_head = cm; + } + si->active_tail = cm; + } + + xmit_dev = cm->xmit_dev; + skb->dev = xmit_dev; + + /* + * Check to see if we need to write a header. + */ + if (likely(cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_WRITE_L2_HDR)) { + if (unlikely(!(cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_WRITE_FAST_ETH_HDR))) { + dev_hard_header(skb, xmit_dev, ETH_P_IP, + cm->xmit_dest_mac, cm->xmit_src_mac, len); + } else { + /* + * For the simple case we write this really fast. + */ + struct sfe_ipv4_eth_hdr *eth = (struct sfe_ipv4_eth_hdr *)__skb_push(skb, ETH_HLEN); + eth->h_proto = htons(ETH_P_IP); + eth->h_dest[0] = cm->xmit_dest_mac[0]; + eth->h_dest[1] = cm->xmit_dest_mac[1]; + eth->h_dest[2] = cm->xmit_dest_mac[2]; + eth->h_source[0] = cm->xmit_src_mac[0]; + eth->h_source[1] = cm->xmit_src_mac[1]; + eth->h_source[2] = cm->xmit_src_mac[2]; + } + } + + /* + * Update priority of skb. + */ + if (unlikely(cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_PRIORITY_REMARK)) { + skb->priority = cm->priority; + } + + /* + * Mark outgoing packet. + */ + skb->mark = cm->connection->mark; + if (skb->mark) { + DEBUG_TRACE("SKB MARK is NON ZERO %x\n", skb->mark); + } + + si->packets_forwarded++; + spin_unlock_bh(&si->lock); + + /* + * We're going to check for GSO flags when we transmit the packet so + * start fetching the necessary cache line now. + */ + prefetch(skb_shinfo(skb)); + + /* + * Mark that this packet has been fast forwarded. + */ + skb->fast_forwarded = 1; + + /* + * Send the packet on its way. + */ + dev_queue_xmit(skb); + + return 1; +} + +/* + * sfe_ipv4_process_tcp_option_sack() + * Parse TCP SACK option and update ack according + */ +static bool sfe_ipv4_process_tcp_option_sack(const struct sfe_ipv4_tcp_hdr *th, const u32 data_offs, + u32 *ack) +{ + u32 length = sizeof(struct sfe_ipv4_tcp_hdr); + u8 *ptr = (u8 *)th + length; + + /* + * Ignore processing if TCP packet has only TIMESTAMP option. + */ + if (likely(data_offs == length + TCPOLEN_TIMESTAMP + 1 + 1) + && likely(ptr[0] == TCPOPT_NOP) + && likely(ptr[1] == TCPOPT_NOP) + && likely(ptr[2] == TCPOPT_TIMESTAMP) + && likely(ptr[3] == TCPOLEN_TIMESTAMP)) { + return true; + } + + /* + * TCP options. Parse SACK option. + */ + while (length < data_offs) { + u8 size; + u8 kind; + + ptr = (u8 *)th + length; + kind = *ptr; + + /* + * NOP, for padding + * Not in the switch because to fast escape and to not calculate size + */ + if (kind == TCPOPT_NOP) { + length++; + continue; + } + + if (kind == TCPOPT_SACK) { + u32 sack = 0; + u8 re = 1 + 1; + + size = *(ptr + 1); + if ((size < (1 + 1 + TCPOLEN_SACK_PERBLOCK)) + || ((size - (1 + 1)) % (TCPOLEN_SACK_PERBLOCK)) + || (size > (data_offs - length))) { + return false; + } + + re += 4; + while (re < size) { + u32 sack_re; + u8 *sptr = ptr + re; + sack_re = (sptr[0] << 24) | (sptr[1] << 16) | (sptr[2] << 8) | sptr[3]; + if (sack_re > sack) { + sack = sack_re; + } + re += TCPOLEN_SACK_PERBLOCK; + } + if (sack > *ack) { + *ack = sack; + } + length += size; + continue; + } + if (kind == TCPOPT_EOL) { + return true; + } + size = *(ptr + 1); + if (size < 2) { + return false; + } + length += size; + } + + return true; +} + +/* + * sfe_ipv4_recv_tcp() + * Handle TCP packet receives and forwarding. + */ +static int sfe_ipv4_recv_tcp(struct sfe_ipv4 *si, struct sk_buff *skb, struct net_device *dev, + unsigned int len, struct sfe_ipv4_ip_hdr *iph, unsigned int ihl, bool flush_on_find) +{ + struct sfe_ipv4_tcp_hdr *tcph; + __be32 src_ip; + __be32 dest_ip; + __be16 src_port; + __be16 dest_port; + struct sfe_ipv4_connection_match *cm; + struct sfe_ipv4_connection_match *counter_cm; + u8 ttl; + u32 flags; + struct net_device *xmit_dev; + + /* + * Is our packet too short to contain a valid UDP header? + */ + if (unlikely(!pskb_may_pull(skb, (sizeof(struct sfe_ipv4_tcp_hdr) + ihl)))) { + spin_lock_bh(&si->lock); + si->exception_events[SFE_IPV4_EXCEPTION_EVENT_TCP_HEADER_INCOMPLETE]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("packet too short for TCP header\n"); + return 0; + } + + /* + * Read the IP address and port information. Read the IP header data first + * because we've almost certainly got that in the cache. We may not yet have + * the TCP header cached though so allow more time for any prefetching. + */ + src_ip = iph->saddr; + dest_ip = iph->daddr; + + tcph = (struct sfe_ipv4_tcp_hdr *)(skb->data + ihl); + src_port = tcph->source; + dest_port = tcph->dest; + flags = tcp_flag_word(tcph); + + spin_lock_bh(&si->lock); + + /* + * Look for a connection match. + */ +#ifdef CONFIG_NF_FLOW_COOKIE + cm = si->sfe_flow_cookie_table[skb->flow_cookie & SFE_FLOW_COOKIE_MASK].match; + if (unlikely(!cm)) { + cm = sfe_ipv4_find_sfe_ipv4_connection_match(si, dev, IPPROTO_TCP, src_ip, src_port, dest_ip, dest_port); + } +#else + cm = sfe_ipv4_find_sfe_ipv4_connection_match(si, dev, IPPROTO_TCP, src_ip, src_port, dest_ip, dest_port); +#endif + if (unlikely(!cm)) { + /* + * We didn't get a connection but as TCP is connection-oriented that + * may be because this is a non-fast connection (not running established). + * For diagnostic purposes we differentiate this here. + */ + if (likely((flags & (TCP_FLAG_SYN | TCP_FLAG_RST | TCP_FLAG_FIN | TCP_FLAG_ACK)) == TCP_FLAG_ACK)) { + si->exception_events[SFE_IPV4_EXCEPTION_EVENT_TCP_NO_CONNECTION_FAST_FLAGS]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("no connection found - fast flags\n"); + return 0; + } + si->exception_events[SFE_IPV4_EXCEPTION_EVENT_TCP_NO_CONNECTION_SLOW_FLAGS]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("no connection found - slow flags: 0x%x\n", + flags & (TCP_FLAG_SYN | TCP_FLAG_RST | TCP_FLAG_FIN | TCP_FLAG_ACK)); + return 0; + } + + /* + * If our packet has beern marked as "flush on find" we can't actually + * forward it in the fast path, but now that we've found an associated + * connection we can flush that out before we process the packet. + */ + if (unlikely(flush_on_find)) { + struct sfe_ipv4_connection *c = cm->connection; + sfe_ipv4_remove_sfe_ipv4_connection(si, c); + si->exception_events[SFE_IPV4_EXCEPTION_EVENT_TCP_IP_OPTIONS_OR_INITIAL_FRAGMENT]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("flush on find\n"); + sfe_ipv4_flush_sfe_ipv4_connection(si, c, SFE_SYNC_REASON_FLUSH); + return 0; + } + +#ifdef CONFIG_XFRM + /* + * We can't accelerate the flow on this direction, just let it go + * through the slow path. + */ + if (unlikely(!cm->flow_accel)) { + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + return 0; + } +#endif + /* + * Does our TTL allow forwarding? + */ + ttl = iph->ttl; + if (unlikely(ttl < 2)) { + struct sfe_ipv4_connection *c = cm->connection; + sfe_ipv4_remove_sfe_ipv4_connection(si, c); + si->exception_events[SFE_IPV4_EXCEPTION_EVENT_TCP_SMALL_TTL]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("ttl too low\n"); + sfe_ipv4_flush_sfe_ipv4_connection(si, c, SFE_SYNC_REASON_FLUSH); + return 0; + } + + /* + * If our packet is larger than the MTU of the transmit interface then + * we can't forward it easily. + */ + if (unlikely((len > cm->xmit_dev_mtu) && !skb_is_gso(skb))) { + struct sfe_ipv4_connection *c = cm->connection; + sfe_ipv4_remove_sfe_ipv4_connection(si, c); + si->exception_events[SFE_IPV4_EXCEPTION_EVENT_TCP_NEEDS_FRAGMENTATION]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("larger than mtu\n"); + sfe_ipv4_flush_sfe_ipv4_connection(si, c, SFE_SYNC_REASON_FLUSH); + return 0; + } + + /* + * Look at our TCP flags. Anything missing an ACK or that has RST, SYN or FIN + * set is not a fast path packet. + */ + if (unlikely((flags & (TCP_FLAG_SYN | TCP_FLAG_RST | TCP_FLAG_FIN | TCP_FLAG_ACK)) != TCP_FLAG_ACK)) { + struct sfe_ipv4_connection *c = cm->connection; + sfe_ipv4_remove_sfe_ipv4_connection(si, c); + si->exception_events[SFE_IPV4_EXCEPTION_EVENT_TCP_FLAGS]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("TCP flags: 0x%x are not fast\n", + flags & (TCP_FLAG_SYN | TCP_FLAG_RST | TCP_FLAG_FIN | TCP_FLAG_ACK)); + sfe_ipv4_flush_sfe_ipv4_connection(si, c, SFE_SYNC_REASON_FLUSH); + return 0; + } + + counter_cm = cm->counter_match; + + /* + * Are we doing sequence number checking? + */ + if (likely(!(cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_NO_SEQ_CHECK))) { + u32 seq; + u32 ack; + u32 sack; + u32 data_offs; + u32 end; + u32 left_edge; + u32 scaled_win; + u32 max_end; + + /* + * Is our sequence fully past the right hand edge of the window? + */ + seq = ntohl(tcph->seq); + if (unlikely((s32)(seq - (cm->protocol_state.tcp.max_end + 1)) > 0)) { + struct sfe_ipv4_connection *c = cm->connection; + sfe_ipv4_remove_sfe_ipv4_connection(si, c); + si->exception_events[SFE_IPV4_EXCEPTION_EVENT_TCP_SEQ_EXCEEDS_RIGHT_EDGE]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("seq: %u exceeds right edge: %u\n", + seq, cm->protocol_state.tcp.max_end + 1); + sfe_ipv4_flush_sfe_ipv4_connection(si, c, SFE_SYNC_REASON_FLUSH); + return 0; + } + + /* + * Check that our TCP data offset isn't too short. + */ + data_offs = tcph->doff << 2; + if (unlikely(data_offs < sizeof(struct sfe_ipv4_tcp_hdr))) { + struct sfe_ipv4_connection *c = cm->connection; + sfe_ipv4_remove_sfe_ipv4_connection(si, c); + si->exception_events[SFE_IPV4_EXCEPTION_EVENT_TCP_SMALL_DATA_OFFS]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("TCP data offset: %u, too small\n", data_offs); + sfe_ipv4_flush_sfe_ipv4_connection(si, c, SFE_SYNC_REASON_FLUSH); + return 0; + } + + /* + * Update ACK according to any SACK option. + */ + ack = ntohl(tcph->ack_seq); + sack = ack; + if (unlikely(!sfe_ipv4_process_tcp_option_sack(tcph, data_offs, &sack))) { + struct sfe_ipv4_connection *c = cm->connection; + sfe_ipv4_remove_sfe_ipv4_connection(si, c); + si->exception_events[SFE_IPV4_EXCEPTION_EVENT_TCP_BAD_SACK]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("TCP option SACK size is wrong\n"); + sfe_ipv4_flush_sfe_ipv4_connection(si, c, SFE_SYNC_REASON_FLUSH); + return 0; + } + + /* + * Check that our TCP data offset isn't past the end of the packet. + */ + data_offs += sizeof(struct sfe_ipv4_ip_hdr); + if (unlikely(len < data_offs)) { + struct sfe_ipv4_connection *c = cm->connection; + sfe_ipv4_remove_sfe_ipv4_connection(si, c); + si->exception_events[SFE_IPV4_EXCEPTION_EVENT_TCP_BIG_DATA_OFFS]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("TCP data offset: %u, past end of packet: %u\n", + data_offs, len); + sfe_ipv4_flush_sfe_ipv4_connection(si, c, SFE_SYNC_REASON_FLUSH); + return 0; + } + + end = seq + len - data_offs; + + /* + * Is our sequence fully before the left hand edge of the window? + */ + if (unlikely((s32)(end - (cm->protocol_state.tcp.end + - counter_cm->protocol_state.tcp.max_win - 1)) < 0)) { + struct sfe_ipv4_connection *c = cm->connection; + sfe_ipv4_remove_sfe_ipv4_connection(si, c); + si->exception_events[SFE_IPV4_EXCEPTION_EVENT_TCP_SEQ_BEFORE_LEFT_EDGE]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("seq: %u before left edge: %u\n", + end, cm->protocol_state.tcp.end - counter_cm->protocol_state.tcp.max_win - 1); + sfe_ipv4_flush_sfe_ipv4_connection(si, c, SFE_SYNC_REASON_FLUSH); + return 0; + } + + /* + * Are we acking data that is to the right of what has been sent? + */ + if (unlikely((s32)(sack - (counter_cm->protocol_state.tcp.end + 1)) > 0)) { + struct sfe_ipv4_connection *c = cm->connection; + sfe_ipv4_remove_sfe_ipv4_connection(si, c); + si->exception_events[SFE_IPV4_EXCEPTION_EVENT_TCP_ACK_EXCEEDS_RIGHT_EDGE]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("ack: %u exceeds right edge: %u\n", + sack, counter_cm->protocol_state.tcp.end + 1); + sfe_ipv4_flush_sfe_ipv4_connection(si, c, SFE_SYNC_REASON_FLUSH); + return 0; + } + + /* + * Is our ack too far before the left hand edge of the window? + */ + left_edge = counter_cm->protocol_state.tcp.end + - cm->protocol_state.tcp.max_win + - SFE_IPV4_TCP_MAX_ACK_WINDOW + - 1; + if (unlikely((s32)(sack - left_edge) < 0)) { + struct sfe_ipv4_connection *c = cm->connection; + sfe_ipv4_remove_sfe_ipv4_connection(si, c); + si->exception_events[SFE_IPV4_EXCEPTION_EVENT_TCP_ACK_BEFORE_LEFT_EDGE]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("ack: %u before left edge: %u\n", sack, left_edge); + sfe_ipv4_flush_sfe_ipv4_connection(si, c, SFE_SYNC_REASON_FLUSH); + return 0; + } + + /* + * Have we just seen the largest window size yet for this connection? If yes + * then we need to record the new value. + */ + scaled_win = ntohs(tcph->window) << cm->protocol_state.tcp.win_scale; + scaled_win += (sack - ack); + if (unlikely(cm->protocol_state.tcp.max_win < scaled_win)) { + cm->protocol_state.tcp.max_win = scaled_win; + } + + /* + * If our sequence and/or ack numbers have advanced then record the new state. + */ + if (likely((s32)(end - cm->protocol_state.tcp.end) >= 0)) { + cm->protocol_state.tcp.end = end; + } + + max_end = sack + scaled_win; + if (likely((s32)(max_end - counter_cm->protocol_state.tcp.max_end) >= 0)) { + counter_cm->protocol_state.tcp.max_end = max_end; + } + } + + /* + * From this point on we're good to modify the packet. + */ + + /* + * Check if skb was cloned. If it was, unshare it. Because + * the data area is going to be written in this path and we don't want to + * change the cloned skb's data section. + */ + if (unlikely(skb_cloned(skb))) { + DEBUG_TRACE("%px: skb is a cloned skb\n", skb); + skb = skb_unshare(skb, GFP_ATOMIC); + if (!skb) { + DEBUG_WARN("Failed to unshare the cloned skb\n"); + si->exception_events[SFE_IPV4_EXCEPTION_EVENT_CLONED_SKB_UNSHARE_ERROR]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + return 0; + } + + /* + * Update the iph and tcph pointers with the unshared skb's data area. + */ + iph = (struct sfe_ipv4_ip_hdr *)skb->data; + tcph = (struct sfe_ipv4_tcp_hdr *)(skb->data + ihl); + } + + /* + * Update DSCP + */ + if (unlikely(cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_DSCP_REMARK)) { + iph->tos = (iph->tos & SFE_IPV4_DSCP_MASK) | cm->dscp; + } + + /* + * Decrement our TTL. + */ + iph->ttl = ttl - 1; + + /* + * Do we have to perform translations of the source address/port? + */ + if (unlikely(cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_XLATE_SRC)) { + u16 tcp_csum; + u32 sum; + + iph->saddr = cm->xlate_src_ip; + tcph->source = cm->xlate_src_port; + + /* + * Do we have a non-zero UDP checksum? If we do then we need + * to update it. + */ + tcp_csum = tcph->check; + if (unlikely(skb->ip_summed == CHECKSUM_PARTIAL)) { + sum = tcp_csum + cm->xlate_src_partial_csum_adjustment; + } else { + sum = tcp_csum + cm->xlate_src_csum_adjustment; + } + + sum = (sum & 0xffff) + (sum >> 16); + tcph->check = (u16)sum; + } + + /* + * Do we have to perform translations of the destination address/port? + */ + if (unlikely(cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_XLATE_DEST)) { + u16 tcp_csum; + u32 sum; + + iph->daddr = cm->xlate_dest_ip; + tcph->dest = cm->xlate_dest_port; + + /* + * Do we have a non-zero UDP checksum? If we do then we need + * to update it. + */ + tcp_csum = tcph->check; + if (unlikely(skb->ip_summed == CHECKSUM_PARTIAL)) { + sum = tcp_csum + cm->xlate_dest_partial_csum_adjustment; + } else { + sum = tcp_csum + cm->xlate_dest_csum_adjustment; + } + + sum = (sum & 0xffff) + (sum >> 16); + tcph->check = (u16)sum; + } + + /* + * Replace the IP checksum. + */ + iph->check = sfe_ipv4_gen_ip_csum(iph); + + /* + * Update traffic stats. + */ + cm->rx_packet_count++; + cm->rx_byte_count += len; + + /* + * If we're not already on the active list then insert ourselves at the tail + * of the current list. + */ + if (unlikely(!cm->active)) { + cm->active = true; + cm->active_prev = si->active_tail; + if (likely(si->active_tail)) { + si->active_tail->active_next = cm; + } else { + si->active_head = cm; + } + si->active_tail = cm; + } + + xmit_dev = cm->xmit_dev; + skb->dev = xmit_dev; + + /* + * Check to see if we need to write a header. + */ + if (likely(cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_WRITE_L2_HDR)) { + if (unlikely(!(cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_WRITE_FAST_ETH_HDR))) { + dev_hard_header(skb, xmit_dev, ETH_P_IP, + cm->xmit_dest_mac, cm->xmit_src_mac, len); + } else { + /* + * For the simple case we write this really fast. + */ + struct sfe_ipv4_eth_hdr *eth = (struct sfe_ipv4_eth_hdr *)__skb_push(skb, ETH_HLEN); + eth->h_proto = htons(ETH_P_IP); + eth->h_dest[0] = cm->xmit_dest_mac[0]; + eth->h_dest[1] = cm->xmit_dest_mac[1]; + eth->h_dest[2] = cm->xmit_dest_mac[2]; + eth->h_source[0] = cm->xmit_src_mac[0]; + eth->h_source[1] = cm->xmit_src_mac[1]; + eth->h_source[2] = cm->xmit_src_mac[2]; + } + } + + /* + * Update priority of skb. + */ + if (unlikely(cm->flags & SFE_IPV4_CONNECTION_MATCH_FLAG_PRIORITY_REMARK)) { + skb->priority = cm->priority; + } + + /* + * Mark outgoing packet + */ + skb->mark = cm->connection->mark; + if (skb->mark) { + DEBUG_TRACE("SKB MARK is NON ZERO %x\n", skb->mark); + } + + si->packets_forwarded++; + spin_unlock_bh(&si->lock); + + /* + * We're going to check for GSO flags when we transmit the packet so + * start fetching the necessary cache line now. + */ + prefetch(skb_shinfo(skb)); + + /* + * Mark that this packet has been fast forwarded. + */ + skb->fast_forwarded = 1; + + /* + * Send the packet on its way. + */ + dev_queue_xmit(skb); + + return 1; +} + +/* + * sfe_ipv4_recv_icmp() + * Handle ICMP packet receives. + * + * ICMP packets aren't handled as a "fast path" and always have us process them + * through the default Linux stack. What we do need to do is look for any errors + * about connections we are handling in the fast path. If we find any such + * connections then we want to flush their state so that the ICMP error path + * within Linux has all of the correct state should it need it. + */ +static int sfe_ipv4_recv_icmp(struct sfe_ipv4 *si, struct sk_buff *skb, struct net_device *dev, + unsigned int len, struct sfe_ipv4_ip_hdr *iph, unsigned int ihl) +{ + struct icmphdr *icmph; + struct sfe_ipv4_ip_hdr *icmp_iph; + unsigned int icmp_ihl_words; + unsigned int icmp_ihl; + u32 *icmp_trans_h; + struct sfe_ipv4_udp_hdr *icmp_udph; + struct sfe_ipv4_tcp_hdr *icmp_tcph; + __be32 src_ip; + __be32 dest_ip; + __be16 src_port; + __be16 dest_port; + struct sfe_ipv4_connection_match *cm; + struct sfe_ipv4_connection *c; + u32 pull_len = sizeof(struct icmphdr) + ihl; + + /* + * Is our packet too short to contain a valid ICMP header? + */ + len -= ihl; + if (!pskb_may_pull(skb, pull_len)) { + spin_lock_bh(&si->lock); + si->exception_events[SFE_IPV4_EXCEPTION_EVENT_ICMP_HEADER_INCOMPLETE]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("packet too short for ICMP header\n"); + return 0; + } + + /* + * We only handle "destination unreachable" and "time exceeded" messages. + */ + icmph = (struct icmphdr *)(skb->data + ihl); + if ((icmph->type != ICMP_DEST_UNREACH) + && (icmph->type != ICMP_TIME_EXCEEDED)) { + spin_lock_bh(&si->lock); + si->exception_events[SFE_IPV4_EXCEPTION_EVENT_ICMP_UNHANDLED_TYPE]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("unhandled ICMP type: 0x%x\n", icmph->type); + return 0; + } + + /* + * Do we have the full embedded IP header? + */ + len -= sizeof(struct icmphdr); + pull_len += sizeof(struct sfe_ipv4_ip_hdr); + if (!pskb_may_pull(skb, pull_len)) { + spin_lock_bh(&si->lock); + si->exception_events[SFE_IPV4_EXCEPTION_EVENT_ICMP_IPV4_HEADER_INCOMPLETE]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("Embedded IP header not complete\n"); + return 0; + } + + /* + * Is our embedded IP version wrong? + */ + icmp_iph = (struct sfe_ipv4_ip_hdr *)(icmph + 1); + if (unlikely(icmp_iph->version != 4)) { + spin_lock_bh(&si->lock); + si->exception_events[SFE_IPV4_EXCEPTION_EVENT_ICMP_IPV4_NON_V4]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("IP version: %u\n", icmp_iph->version); + return 0; + } + + /* + * Do we have the full embedded IP header, including any options? + */ + icmp_ihl_words = icmp_iph->ihl; + icmp_ihl = icmp_ihl_words << 2; + pull_len += icmp_ihl - sizeof(struct sfe_ipv4_ip_hdr); + if (!pskb_may_pull(skb, pull_len)) { + spin_lock_bh(&si->lock); + si->exception_events[SFE_IPV4_EXCEPTION_EVENT_ICMP_IPV4_IP_OPTIONS_INCOMPLETE]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("Embedded header not large enough for IP options\n"); + return 0; + } + + len -= icmp_ihl; + icmp_trans_h = ((u32 *)icmp_iph) + icmp_ihl_words; + + /* + * Handle the embedded transport layer header. + */ + switch (icmp_iph->protocol) { + case IPPROTO_UDP: + /* + * We should have 8 bytes of UDP header - that's enough to identify + * the connection. + */ + pull_len += 8; + if (!pskb_may_pull(skb, pull_len)) { + spin_lock_bh(&si->lock); + si->exception_events[SFE_IPV4_EXCEPTION_EVENT_ICMP_IPV4_UDP_HEADER_INCOMPLETE]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("Incomplete embedded UDP header\n"); + return 0; + } + + icmp_udph = (struct sfe_ipv4_udp_hdr *)icmp_trans_h; + src_port = icmp_udph->source; + dest_port = icmp_udph->dest; + break; + + case IPPROTO_TCP: + /* + * We should have 8 bytes of TCP header - that's enough to identify + * the connection. + */ + pull_len += 8; + if (!pskb_may_pull(skb, pull_len)) { + spin_lock_bh(&si->lock); + si->exception_events[SFE_IPV4_EXCEPTION_EVENT_ICMP_IPV4_TCP_HEADER_INCOMPLETE]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("Incomplete embedded TCP header\n"); + return 0; + } + + icmp_tcph = (struct sfe_ipv4_tcp_hdr *)icmp_trans_h; + src_port = icmp_tcph->source; + dest_port = icmp_tcph->dest; + break; + + default: + spin_lock_bh(&si->lock); + si->exception_events[SFE_IPV4_EXCEPTION_EVENT_ICMP_IPV4_UNHANDLED_PROTOCOL]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("Unhandled embedded IP protocol: %u\n", icmp_iph->protocol); + return 0; + } + + src_ip = icmp_iph->saddr; + dest_ip = icmp_iph->daddr; + + spin_lock_bh(&si->lock); + + /* + * Look for a connection match. Note that we reverse the source and destination + * here because our embedded message contains a packet that was sent in the + * opposite direction to the one in which we just received it. It will have + * been sent on the interface from which we received it though so that's still + * ok to use. + */ + cm = sfe_ipv4_find_sfe_ipv4_connection_match(si, dev, icmp_iph->protocol, dest_ip, dest_port, src_ip, src_port); + if (unlikely(!cm)) { + si->exception_events[SFE_IPV4_EXCEPTION_EVENT_ICMP_NO_CONNECTION]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("no connection found\n"); + return 0; + } + + /* + * We found a connection so now remove it from the connection list and flush + * its state. + */ + c = cm->connection; + sfe_ipv4_remove_sfe_ipv4_connection(si, c); + si->exception_events[SFE_IPV4_EXCEPTION_EVENT_ICMP_FLUSHED_CONNECTION]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + sfe_ipv4_flush_sfe_ipv4_connection(si, c, SFE_SYNC_REASON_FLUSH); + return 0; +} + +/* + * sfe_ipv4_recv() + * Handle packet receives and forwaring. + * + * Returns 1 if the packet is forwarded or 0 if it isn't. + */ +int sfe_ipv4_recv(struct net_device *dev, struct sk_buff *skb) +{ + struct sfe_ipv4 *si = &__si; + unsigned int len; + unsigned int tot_len; + unsigned int frag_off; + unsigned int ihl; + bool flush_on_find; + bool ip_options; + struct sfe_ipv4_ip_hdr *iph; + u32 protocol; + + /* + * Check that we have space for an IP header here. + */ + len = skb->len; + if (unlikely(!pskb_may_pull(skb, sizeof(struct sfe_ipv4_ip_hdr)))) { + spin_lock_bh(&si->lock); + si->exception_events[SFE_IPV4_EXCEPTION_EVENT_HEADER_INCOMPLETE]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("len: %u is too short\n", len); + return 0; + } + + /* + * Check that our "total length" is large enough for an IP header. + */ + iph = (struct sfe_ipv4_ip_hdr *)skb->data; + tot_len = ntohs(iph->tot_len); + if (unlikely(tot_len < sizeof(struct sfe_ipv4_ip_hdr))) { + spin_lock_bh(&si->lock); + si->exception_events[SFE_IPV4_EXCEPTION_EVENT_BAD_TOTAL_LENGTH]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("tot_len: %u is too short\n", tot_len); + return 0; + } + + /* + * Is our IP version wrong? + */ + if (unlikely(iph->version != 4)) { + spin_lock_bh(&si->lock); + si->exception_events[SFE_IPV4_EXCEPTION_EVENT_NON_V4]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("IP version: %u\n", iph->version); + return 0; + } + + /* + * Does our datagram fit inside the skb? + */ + if (unlikely(tot_len > len)) { + spin_lock_bh(&si->lock); + si->exception_events[SFE_IPV4_EXCEPTION_EVENT_DATAGRAM_INCOMPLETE]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("tot_len: %u, exceeds len: %u\n", tot_len, len); + return 0; + } + + /* + * Do we have a non-initial fragment? + */ + frag_off = ntohs(iph->frag_off); + if (unlikely(frag_off & IP_OFFSET)) { + spin_lock_bh(&si->lock); + si->exception_events[SFE_IPV4_EXCEPTION_EVENT_NON_INITIAL_FRAGMENT]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("non-initial fragment\n"); + return 0; + } + + /* + * If we have a (first) fragment then mark it to cause any connection to flush. + */ + flush_on_find = unlikely(frag_off & IP_MF) ? true : false; + + /* + * Do we have any IP options? That's definite a slow path! If we do have IP + * options we need to recheck our header size. + */ + ihl = iph->ihl << 2; + ip_options = unlikely(ihl != sizeof(struct sfe_ipv4_ip_hdr)) ? true : false; + if (unlikely(ip_options)) { + if (unlikely(len < ihl)) { + spin_lock_bh(&si->lock); + si->exception_events[SFE_IPV4_EXCEPTION_EVENT_IP_OPTIONS_INCOMPLETE]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("len: %u is too short for header of size: %u\n", len, ihl); + return 0; + } + + flush_on_find = true; + } + + protocol = iph->protocol; + if (IPPROTO_UDP == protocol) { + return sfe_ipv4_recv_udp(si, skb, dev, len, iph, ihl, flush_on_find); + } + + if (IPPROTO_TCP == protocol) { + return sfe_ipv4_recv_tcp(si, skb, dev, len, iph, ihl, flush_on_find); + } + + if (IPPROTO_ICMP == protocol) { + return sfe_ipv4_recv_icmp(si, skb, dev, len, iph, ihl); + } + + spin_lock_bh(&si->lock); + si->exception_events[SFE_IPV4_EXCEPTION_EVENT_UNHANDLED_PROTOCOL]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("not UDP, TCP or ICMP: %u\n", protocol); + return 0; +} + +static void +sfe_ipv4_update_tcp_state(struct sfe_ipv4_connection *c, + struct sfe_connection_create *sic) +{ + struct sfe_ipv4_connection_match *orig_cm; + struct sfe_ipv4_connection_match *repl_cm; + struct sfe_ipv4_tcp_connection_match *orig_tcp; + struct sfe_ipv4_tcp_connection_match *repl_tcp; + + orig_cm = c->original_match; + repl_cm = c->reply_match; + orig_tcp = &orig_cm->protocol_state.tcp; + repl_tcp = &repl_cm->protocol_state.tcp; + + /* update orig */ + if (orig_tcp->max_win < sic->src_td_max_window) { + orig_tcp->max_win = sic->src_td_max_window; + } + if ((s32)(orig_tcp->end - sic->src_td_end) < 0) { + orig_tcp->end = sic->src_td_end; + } + if ((s32)(orig_tcp->max_end - sic->src_td_max_end) < 0) { + orig_tcp->max_end = sic->src_td_max_end; + } + + /* update reply */ + if (repl_tcp->max_win < sic->dest_td_max_window) { + repl_tcp->max_win = sic->dest_td_max_window; + } + if ((s32)(repl_tcp->end - sic->dest_td_end) < 0) { + repl_tcp->end = sic->dest_td_end; + } + if ((s32)(repl_tcp->max_end - sic->dest_td_max_end) < 0) { + repl_tcp->max_end = sic->dest_td_max_end; + } + + /* update match flags */ + orig_cm->flags &= ~SFE_IPV4_CONNECTION_MATCH_FLAG_NO_SEQ_CHECK; + repl_cm->flags &= ~SFE_IPV4_CONNECTION_MATCH_FLAG_NO_SEQ_CHECK; + if (sic->flags & SFE_CREATE_FLAG_NO_SEQ_CHECK) { + orig_cm->flags |= SFE_IPV4_CONNECTION_MATCH_FLAG_NO_SEQ_CHECK; + repl_cm->flags |= SFE_IPV4_CONNECTION_MATCH_FLAG_NO_SEQ_CHECK; + } +} + +static void +sfe_ipv4_update_protocol_state(struct sfe_ipv4_connection *c, + struct sfe_connection_create *sic) +{ + switch (sic->protocol) { + case IPPROTO_TCP: + sfe_ipv4_update_tcp_state(c, sic); + break; + } +} + +void sfe_ipv4_update_rule(struct sfe_connection_create *sic) +{ + struct sfe_ipv4_connection *c; + struct sfe_ipv4 *si = &__si; + + spin_lock_bh(&si->lock); + + c = sfe_ipv4_find_sfe_ipv4_connection(si, + sic->protocol, + sic->src_ip.ip, + sic->src_port, + sic->dest_ip.ip, + sic->dest_port); + if (c != NULL) { + sfe_ipv4_update_protocol_state(c, sic); + } + + spin_unlock_bh(&si->lock); +} + +/* + * sfe_ipv4_create_rule() + * Create a forwarding rule. + */ +int sfe_ipv4_create_rule(struct sfe_connection_create *sic) +{ + struct sfe_ipv4 *si = &__si; + struct sfe_ipv4_connection *c; + struct sfe_ipv4_connection_match *original_cm; + struct sfe_ipv4_connection_match *reply_cm; + struct net_device *dest_dev; + struct net_device *src_dev; + + dest_dev = sic->dest_dev; + src_dev = sic->src_dev; + + if (unlikely((dest_dev->reg_state != NETREG_REGISTERED) || + (src_dev->reg_state != NETREG_REGISTERED))) { + return -EINVAL; + } + + spin_lock_bh(&si->lock); + si->connection_create_requests++; + + /* + * Check to see if there is already a flow that matches the rule we're + * trying to create. If there is then we can't create a new one. + */ + c = sfe_ipv4_find_sfe_ipv4_connection(si, + sic->protocol, + sic->src_ip.ip, + sic->src_port, + sic->dest_ip.ip, + sic->dest_port); + if (c != NULL) { + si->connection_create_collisions++; + + /* + * If we already have the flow then it's likely that this + * request to create the connection rule contains more + * up-to-date information. Check and update accordingly. + */ + sfe_ipv4_update_protocol_state(c, sic); + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("connection already exists - mark: %08x, p: %d\n" + " s: %s:%pxM:%pI4:%u, d: %s:%pxM:%pI4:%u\n", + sic->mark, sic->protocol, + sic->src_dev->name, sic->src_mac, &sic->src_ip.ip, ntohs(sic->src_port), + sic->dest_dev->name, sic->dest_mac, &sic->dest_ip.ip, ntohs(sic->dest_port)); + return -EADDRINUSE; + } + + /* + * Allocate the various connection tracking objects. + */ + c = (struct sfe_ipv4_connection *)kmalloc(sizeof(struct sfe_ipv4_connection), GFP_ATOMIC); + if (unlikely(!c)) { + spin_unlock_bh(&si->lock); + return -ENOMEM; + } + + original_cm = (struct sfe_ipv4_connection_match *)kmalloc(sizeof(struct sfe_ipv4_connection_match), GFP_ATOMIC); + if (unlikely(!original_cm)) { + spin_unlock_bh(&si->lock); + kfree(c); + return -ENOMEM; + } + + reply_cm = (struct sfe_ipv4_connection_match *)kmalloc(sizeof(struct sfe_ipv4_connection_match), GFP_ATOMIC); + if (unlikely(!reply_cm)) { + spin_unlock_bh(&si->lock); + kfree(original_cm); + kfree(c); + return -ENOMEM; + } + + /* + * Fill in the "original" direction connection matching object. + * Note that the transmit MAC address is "dest_mac_xlate" because + * we always know both ends of a connection by their translated + * addresses and not their public addresses. + */ + original_cm->match_dev = src_dev; + original_cm->match_protocol = sic->protocol; + original_cm->match_src_ip = sic->src_ip.ip; + original_cm->match_src_port = sic->src_port; + original_cm->match_dest_ip = sic->dest_ip.ip; + original_cm->match_dest_port = sic->dest_port; + original_cm->xlate_src_ip = sic->src_ip_xlate.ip; + original_cm->xlate_src_port = sic->src_port_xlate; + original_cm->xlate_dest_ip = sic->dest_ip_xlate.ip; + original_cm->xlate_dest_port = sic->dest_port_xlate; + original_cm->rx_packet_count = 0; + original_cm->rx_packet_count64 = 0; + original_cm->rx_byte_count = 0; + original_cm->rx_byte_count64 = 0; + original_cm->xmit_dev = dest_dev; + original_cm->xmit_dev_mtu = sic->dest_mtu; + memcpy(original_cm->xmit_src_mac, dest_dev->dev_addr, ETH_ALEN); + memcpy(original_cm->xmit_dest_mac, sic->dest_mac_xlate, ETH_ALEN); + original_cm->connection = c; + original_cm->counter_match = reply_cm; + original_cm->flags = 0; + if (sic->flags & SFE_CREATE_FLAG_REMARK_PRIORITY) { + original_cm->priority = sic->src_priority; + original_cm->flags |= SFE_IPV4_CONNECTION_MATCH_FLAG_PRIORITY_REMARK; + } + if (sic->flags & SFE_CREATE_FLAG_REMARK_DSCP) { + original_cm->dscp = sic->src_dscp << SFE_IPV4_DSCP_SHIFT; + original_cm->flags |= SFE_IPV4_CONNECTION_MATCH_FLAG_DSCP_REMARK; + } +#ifdef CONFIG_NF_FLOW_COOKIE + original_cm->flow_cookie = 0; +#endif +#ifdef CONFIG_XFRM + original_cm->flow_accel = sic->original_accel; +#endif + original_cm->active_next = NULL; + original_cm->active_prev = NULL; + original_cm->active = false; + + /* + * For PPP links we don't write an L2 header. For everything else we do. + */ + if (!(dest_dev->flags & IFF_POINTOPOINT)) { + original_cm->flags |= SFE_IPV4_CONNECTION_MATCH_FLAG_WRITE_L2_HDR; + + /* + * If our dev writes Ethernet headers then we can write a really fast + * version. + */ + if (dest_dev->header_ops) { + if (dest_dev->header_ops->create == eth_header) { + original_cm->flags |= SFE_IPV4_CONNECTION_MATCH_FLAG_WRITE_FAST_ETH_HDR; + } + } + } + + /* + * Fill in the "reply" direction connection matching object. + */ + reply_cm->match_dev = dest_dev; + reply_cm->match_protocol = sic->protocol; + reply_cm->match_src_ip = sic->dest_ip_xlate.ip; + reply_cm->match_src_port = sic->dest_port_xlate; + reply_cm->match_dest_ip = sic->src_ip_xlate.ip; + reply_cm->match_dest_port = sic->src_port_xlate; + reply_cm->xlate_src_ip = sic->dest_ip.ip; + reply_cm->xlate_src_port = sic->dest_port; + reply_cm->xlate_dest_ip = sic->src_ip.ip; + reply_cm->xlate_dest_port = sic->src_port; + reply_cm->rx_packet_count = 0; + reply_cm->rx_packet_count64 = 0; + reply_cm->rx_byte_count = 0; + reply_cm->rx_byte_count64 = 0; + reply_cm->xmit_dev = src_dev; + reply_cm->xmit_dev_mtu = sic->src_mtu; + memcpy(reply_cm->xmit_src_mac, src_dev->dev_addr, ETH_ALEN); + memcpy(reply_cm->xmit_dest_mac, sic->src_mac, ETH_ALEN); + reply_cm->connection = c; + reply_cm->counter_match = original_cm; + reply_cm->flags = 0; + if (sic->flags & SFE_CREATE_FLAG_REMARK_PRIORITY) { + reply_cm->priority = sic->dest_priority; + reply_cm->flags |= SFE_IPV4_CONNECTION_MATCH_FLAG_PRIORITY_REMARK; + } + if (sic->flags & SFE_CREATE_FLAG_REMARK_DSCP) { + reply_cm->dscp = sic->dest_dscp << SFE_IPV4_DSCP_SHIFT; + reply_cm->flags |= SFE_IPV4_CONNECTION_MATCH_FLAG_DSCP_REMARK; + } +#ifdef CONFIG_NF_FLOW_COOKIE + reply_cm->flow_cookie = 0; +#endif +#ifdef CONFIG_XFRM + reply_cm->flow_accel = sic->reply_accel; +#endif + reply_cm->active_next = NULL; + reply_cm->active_prev = NULL; + reply_cm->active = false; + + /* + * For PPP links we don't write an L2 header. For everything else we do. + */ + if (!(src_dev->flags & IFF_POINTOPOINT)) { + reply_cm->flags |= SFE_IPV4_CONNECTION_MATCH_FLAG_WRITE_L2_HDR; + + /* + * If our dev writes Ethernet headers then we can write a really fast + * version. + */ + if (src_dev->header_ops) { + if (src_dev->header_ops->create == eth_header) { + reply_cm->flags |= SFE_IPV4_CONNECTION_MATCH_FLAG_WRITE_FAST_ETH_HDR; + } + } + } + + + if (sic->dest_ip.ip != sic->dest_ip_xlate.ip || sic->dest_port != sic->dest_port_xlate) { + original_cm->flags |= SFE_IPV4_CONNECTION_MATCH_FLAG_XLATE_DEST; + reply_cm->flags |= SFE_IPV4_CONNECTION_MATCH_FLAG_XLATE_SRC; + } + + if (sic->src_ip.ip != sic->src_ip_xlate.ip || sic->src_port != sic->src_port_xlate) { + original_cm->flags |= SFE_IPV4_CONNECTION_MATCH_FLAG_XLATE_SRC; + reply_cm->flags |= SFE_IPV4_CONNECTION_MATCH_FLAG_XLATE_DEST; + } + + c->protocol = sic->protocol; + c->src_ip = sic->src_ip.ip; + c->src_ip_xlate = sic->src_ip_xlate.ip; + c->src_port = sic->src_port; + c->src_port_xlate = sic->src_port_xlate; + c->original_dev = src_dev; + c->original_match = original_cm; + c->dest_ip = sic->dest_ip.ip; + c->dest_ip_xlate = sic->dest_ip_xlate.ip; + c->dest_port = sic->dest_port; + c->dest_port_xlate = sic->dest_port_xlate; + c->reply_dev = dest_dev; + c->reply_match = reply_cm; + c->mark = sic->mark; + c->debug_read_seq = 0; + c->last_sync_jiffies = get_jiffies_64(); + + /* + * Take hold of our source and dest devices for the duration of the connection. + */ + dev_hold(c->original_dev); + dev_hold(c->reply_dev); + + /* + * Initialize the protocol-specific information that we track. + */ + switch (sic->protocol) { + case IPPROTO_TCP: + original_cm->protocol_state.tcp.win_scale = sic->src_td_window_scale; + original_cm->protocol_state.tcp.max_win = sic->src_td_max_window ? sic->src_td_max_window : 1; + original_cm->protocol_state.tcp.end = sic->src_td_end; + original_cm->protocol_state.tcp.max_end = sic->src_td_max_end; + reply_cm->protocol_state.tcp.win_scale = sic->dest_td_window_scale; + reply_cm->protocol_state.tcp.max_win = sic->dest_td_max_window ? sic->dest_td_max_window : 1; + reply_cm->protocol_state.tcp.end = sic->dest_td_end; + reply_cm->protocol_state.tcp.max_end = sic->dest_td_max_end; + if (sic->flags & SFE_CREATE_FLAG_NO_SEQ_CHECK) { + original_cm->flags |= SFE_IPV4_CONNECTION_MATCH_FLAG_NO_SEQ_CHECK; + reply_cm->flags |= SFE_IPV4_CONNECTION_MATCH_FLAG_NO_SEQ_CHECK; + } + break; + } + + sfe_ipv4_connection_match_compute_translations(original_cm); + sfe_ipv4_connection_match_compute_translations(reply_cm); + sfe_ipv4_insert_sfe_ipv4_connection(si, c); + + spin_unlock_bh(&si->lock); + + /* + * We have everything we need! + */ + DEBUG_INFO("new connection - mark: %08x, p: %d\n" + " s: %s:%pxM(%pxM):%pI4(%pI4):%u(%u)\n" + " d: %s:%pxM(%pxM):%pI4(%pI4):%u(%u)\n", + sic->mark, sic->protocol, + sic->src_dev->name, sic->src_mac, sic->src_mac_xlate, + &sic->src_ip.ip, &sic->src_ip_xlate.ip, ntohs(sic->src_port), ntohs(sic->src_port_xlate), + dest_dev->name, sic->dest_mac, sic->dest_mac_xlate, + &sic->dest_ip.ip, &sic->dest_ip_xlate.ip, ntohs(sic->dest_port), ntohs(sic->dest_port_xlate)); + + return 0; +} + +/* + * sfe_ipv4_destroy_rule() + * Destroy a forwarding rule. + */ +void sfe_ipv4_destroy_rule(struct sfe_connection_destroy *sid) +{ + struct sfe_ipv4 *si = &__si; + struct sfe_ipv4_connection *c; + + spin_lock_bh(&si->lock); + si->connection_destroy_requests++; + + /* + * Check to see if we have a flow that matches the rule we're trying + * to destroy. If there isn't then we can't destroy it. + */ + c = sfe_ipv4_find_sfe_ipv4_connection(si, sid->protocol, sid->src_ip.ip, sid->src_port, + sid->dest_ip.ip, sid->dest_port); + if (!c) { + si->connection_destroy_misses++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("connection does not exist - p: %d, s: %pI4:%u, d: %pI4:%u\n", + sid->protocol, &sid->src_ip, ntohs(sid->src_port), + &sid->dest_ip, ntohs(sid->dest_port)); + return; + } + + /* + * Remove our connection details from the hash tables. + */ + sfe_ipv4_remove_sfe_ipv4_connection(si, c); + spin_unlock_bh(&si->lock); + + sfe_ipv4_flush_sfe_ipv4_connection(si, c, SFE_SYNC_REASON_DESTROY); + + DEBUG_INFO("connection destroyed - p: %d, s: %pI4:%u, d: %pI4:%u\n", + sid->protocol, &sid->src_ip.ip, ntohs(sid->src_port), + &sid->dest_ip.ip, ntohs(sid->dest_port)); +} + +/* + * sfe_ipv4_register_sync_rule_callback() + * Register a callback for rule synchronization. + */ +void sfe_ipv4_register_sync_rule_callback(sfe_sync_rule_callback_t sync_rule_callback) +{ + struct sfe_ipv4 *si = &__si; + + spin_lock_bh(&si->lock); + rcu_assign_pointer(si->sync_rule_callback, sync_rule_callback); + spin_unlock_bh(&si->lock); +} + +/* + * sfe_ipv4_get_debug_dev() + */ +static ssize_t sfe_ipv4_get_debug_dev(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct sfe_ipv4 *si = &__si; + ssize_t count; + int num; + + spin_lock_bh(&si->lock); + num = si->debug_dev; + spin_unlock_bh(&si->lock); + + count = snprintf(buf, (ssize_t)PAGE_SIZE, "%d\n", num); + return count; +} + +/* + * sysfs attributes. + */ +static const struct device_attribute sfe_ipv4_debug_dev_attr = + __ATTR(debug_dev, S_IWUSR | S_IRUGO, sfe_ipv4_get_debug_dev, NULL); + +/* + * sfe_ipv4_destroy_all_rules_for_dev() + * Destroy all connections that match a particular device. + * + * If we pass dev as NULL then this destroys all connections. + */ +void sfe_ipv4_destroy_all_rules_for_dev(struct net_device *dev) +{ + struct sfe_ipv4 *si = &__si; + struct sfe_ipv4_connection *c; + +another_round: + spin_lock_bh(&si->lock); + + for (c = si->all_connections_head; c; c = c->all_connections_next) { + /* + * Does this connection relate to the device we are destroying? + */ + if (!dev + || (dev == c->original_dev) + || (dev == c->reply_dev)) { + break; + } + } + + if (c) { + sfe_ipv4_remove_sfe_ipv4_connection(si, c); + } + + spin_unlock_bh(&si->lock); + + if (c) { + sfe_ipv4_flush_sfe_ipv4_connection(si, c, SFE_SYNC_REASON_DESTROY); + goto another_round; + } +} + +/* + * sfe_ipv4_periodic_sync() + */ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 15, 0)) +static void sfe_ipv4_periodic_sync(unsigned long arg) +#else +static void sfe_ipv4_periodic_sync(struct timer_list *tl) +#endif +{ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 15, 0)) + struct sfe_ipv4 *si = (struct sfe_ipv4 *)arg; +#else + struct sfe_ipv4 *si = from_timer(si, tl, timer); +#endif + u64 now_jiffies; + int quota; + sfe_sync_rule_callback_t sync_rule_callback; + + now_jiffies = get_jiffies_64(); + + rcu_read_lock(); + sync_rule_callback = rcu_dereference(si->sync_rule_callback); + if (!sync_rule_callback) { + rcu_read_unlock(); + goto done; + } + + spin_lock_bh(&si->lock); + sfe_ipv4_update_summary_stats(si); + + /* + * Get an estimate of the number of connections to parse in this sync. + */ + quota = (si->num_connections + 63) / 64; + + /* + * Walk the "active" list and sync the connection state. + */ + while (quota--) { + struct sfe_ipv4_connection_match *cm; + struct sfe_ipv4_connection_match *counter_cm; + struct sfe_ipv4_connection *c; + struct sfe_connection_sync sis; + + cm = si->active_head; + if (!cm) { + break; + } + + /* + * There's a possibility that our counter match is in the active list too. + * If it is then remove it. + */ + counter_cm = cm->counter_match; + if (counter_cm->active) { + counter_cm->active = false; + + /* + * We must have a connection preceding this counter match + * because that's the one that got us to this point, so we don't have + * to worry about removing the head of the list. + */ + counter_cm->active_prev->active_next = counter_cm->active_next; + + if (likely(counter_cm->active_next)) { + counter_cm->active_next->active_prev = counter_cm->active_prev; + } else { + si->active_tail = counter_cm->active_prev; + } + + counter_cm->active_next = NULL; + counter_cm->active_prev = NULL; + } + + /* + * Now remove the head of the active scan list. + */ + cm->active = false; + si->active_head = cm->active_next; + if (likely(cm->active_next)) { + cm->active_next->active_prev = NULL; + } else { + si->active_tail = NULL; + } + cm->active_next = NULL; + + /* + * Sync the connection state. + */ + c = cm->connection; + sfe_ipv4_gen_sync_sfe_ipv4_connection(si, c, &sis, SFE_SYNC_REASON_STATS, now_jiffies); + + /* + * We don't want to be holding the lock when we sync! + */ + spin_unlock_bh(&si->lock); + sync_rule_callback(&sis); + spin_lock_bh(&si->lock); + } + + spin_unlock_bh(&si->lock); + rcu_read_unlock(); + +done: + mod_timer(&si->timer, jiffies + ((HZ + 99) / 100)); +} + +#define CHAR_DEV_MSG_SIZE 768 + +/* + * sfe_ipv4_debug_dev_read_start() + * Generate part of the XML output. + */ +static bool sfe_ipv4_debug_dev_read_start(struct sfe_ipv4 *si, char *buffer, char *msg, size_t *length, + int *total_read, struct sfe_ipv4_debug_xml_write_state *ws) +{ + int bytes_read; + + si->debug_read_seq++; + + bytes_read = snprintf(msg, CHAR_DEV_MSG_SIZE, "\n"); + if (copy_to_user(buffer + *total_read, msg, CHAR_DEV_MSG_SIZE)) { + return false; + } + + *length -= bytes_read; + *total_read += bytes_read; + + ws->state++; + return true; +} + +/* + * sfe_ipv4_debug_dev_read_connections_start() + * Generate part of the XML output. + */ +static bool sfe_ipv4_debug_dev_read_connections_start(struct sfe_ipv4 *si, char *buffer, char *msg, size_t *length, + int *total_read, struct sfe_ipv4_debug_xml_write_state *ws) +{ + int bytes_read; + + bytes_read = snprintf(msg, CHAR_DEV_MSG_SIZE, "\t\n"); + if (copy_to_user(buffer + *total_read, msg, CHAR_DEV_MSG_SIZE)) { + return false; + } + + *length -= bytes_read; + *total_read += bytes_read; + + ws->state++; + return true; +} + +/* + * sfe_ipv4_debug_dev_read_connections_connection() + * Generate part of the XML output. + */ +static bool sfe_ipv4_debug_dev_read_connections_connection(struct sfe_ipv4 *si, char *buffer, char *msg, size_t *length, + int *total_read, struct sfe_ipv4_debug_xml_write_state *ws) +{ + struct sfe_ipv4_connection *c; + struct sfe_ipv4_connection_match *original_cm; + struct sfe_ipv4_connection_match *reply_cm; + int bytes_read; + int protocol; + struct net_device *src_dev; + __be32 src_ip; + __be32 src_ip_xlate; + __be16 src_port; + __be16 src_port_xlate; + u64 src_rx_packets; + u64 src_rx_bytes; + struct net_device *dest_dev; + __be32 dest_ip; + __be32 dest_ip_xlate; + __be16 dest_port; + __be16 dest_port_xlate; + u64 dest_rx_packets; + u64 dest_rx_bytes; + u64 last_sync_jiffies; + u32 mark, src_priority, dest_priority, src_dscp, dest_dscp; +#ifdef CONFIG_NF_FLOW_COOKIE + int src_flow_cookie, dst_flow_cookie; +#endif + + spin_lock_bh(&si->lock); + + for (c = si->all_connections_head; c; c = c->all_connections_next) { + if (c->debug_read_seq < si->debug_read_seq) { + c->debug_read_seq = si->debug_read_seq; + break; + } + } + + /* + * If there were no connections then move to the next state. + */ + if (!c) { + spin_unlock_bh(&si->lock); + ws->state++; + return true; + } + + original_cm = c->original_match; + reply_cm = c->reply_match; + + protocol = c->protocol; + src_dev = c->original_dev; + src_ip = c->src_ip; + src_ip_xlate = c->src_ip_xlate; + src_port = c->src_port; + src_port_xlate = c->src_port_xlate; + src_priority = original_cm->priority; + src_dscp = original_cm->dscp >> SFE_IPV4_DSCP_SHIFT; + + sfe_ipv4_connection_match_update_summary_stats(original_cm); + sfe_ipv4_connection_match_update_summary_stats(reply_cm); + + src_rx_packets = original_cm->rx_packet_count64; + src_rx_bytes = original_cm->rx_byte_count64; + dest_dev = c->reply_dev; + dest_ip = c->dest_ip; + dest_ip_xlate = c->dest_ip_xlate; + dest_port = c->dest_port; + dest_port_xlate = c->dest_port_xlate; + dest_priority = reply_cm->priority; + dest_dscp = reply_cm->dscp >> SFE_IPV4_DSCP_SHIFT; + dest_rx_packets = reply_cm->rx_packet_count64; + dest_rx_bytes = reply_cm->rx_byte_count64; + last_sync_jiffies = get_jiffies_64() - c->last_sync_jiffies; + mark = c->mark; +#ifdef CONFIG_NF_FLOW_COOKIE + src_flow_cookie = original_cm->flow_cookie; + dst_flow_cookie = reply_cm->flow_cookie; +#endif + spin_unlock_bh(&si->lock); + + bytes_read = snprintf(msg, CHAR_DEV_MSG_SIZE, "\t\t\n", + protocol, + src_dev->name, + &src_ip, &src_ip_xlate, + ntohs(src_port), ntohs(src_port_xlate), + src_priority, src_dscp, + src_rx_packets, src_rx_bytes, + dest_dev->name, + &dest_ip, &dest_ip_xlate, + ntohs(dest_port), ntohs(dest_port_xlate), + dest_priority, dest_dscp, + dest_rx_packets, dest_rx_bytes, +#ifdef CONFIG_NF_FLOW_COOKIE + src_flow_cookie, dst_flow_cookie, +#endif + last_sync_jiffies, mark); + + if (copy_to_user(buffer + *total_read, msg, CHAR_DEV_MSG_SIZE)) { + return false; + } + + *length -= bytes_read; + *total_read += bytes_read; + + return true; +} + +/* + * sfe_ipv4_debug_dev_read_connections_end() + * Generate part of the XML output. + */ +static bool sfe_ipv4_debug_dev_read_connections_end(struct sfe_ipv4 *si, char *buffer, char *msg, size_t *length, + int *total_read, struct sfe_ipv4_debug_xml_write_state *ws) +{ + int bytes_read; + + bytes_read = snprintf(msg, CHAR_DEV_MSG_SIZE, "\t\n"); + if (copy_to_user(buffer + *total_read, msg, CHAR_DEV_MSG_SIZE)) { + return false; + } + + *length -= bytes_read; + *total_read += bytes_read; + + ws->state++; + return true; +} + +/* + * sfe_ipv4_debug_dev_read_exceptions_start() + * Generate part of the XML output. + */ +static bool sfe_ipv4_debug_dev_read_exceptions_start(struct sfe_ipv4 *si, char *buffer, char *msg, size_t *length, + int *total_read, struct sfe_ipv4_debug_xml_write_state *ws) +{ + int bytes_read; + + bytes_read = snprintf(msg, CHAR_DEV_MSG_SIZE, "\t\n"); + if (copy_to_user(buffer + *total_read, msg, CHAR_DEV_MSG_SIZE)) { + return false; + } + + *length -= bytes_read; + *total_read += bytes_read; + + ws->state++; + return true; +} + +/* + * sfe_ipv4_debug_dev_read_exceptions_exception() + * Generate part of the XML output. + */ +static bool sfe_ipv4_debug_dev_read_exceptions_exception(struct sfe_ipv4 *si, char *buffer, char *msg, size_t *length, + int *total_read, struct sfe_ipv4_debug_xml_write_state *ws) +{ + u64 ct; + + spin_lock_bh(&si->lock); + ct = si->exception_events64[ws->iter_exception]; + spin_unlock_bh(&si->lock); + + if (ct) { + int bytes_read; + + bytes_read = snprintf(msg, CHAR_DEV_MSG_SIZE, + "\t\t\n", + sfe_ipv4_exception_events_string[ws->iter_exception], + ct); + if (copy_to_user(buffer + *total_read, msg, CHAR_DEV_MSG_SIZE)) { + return false; + } + + *length -= bytes_read; + *total_read += bytes_read; + } + + ws->iter_exception++; + if (ws->iter_exception >= SFE_IPV4_EXCEPTION_EVENT_LAST) { + ws->iter_exception = 0; + ws->state++; + } + + return true; +} + +/* + * sfe_ipv4_debug_dev_read_exceptions_end() + * Generate part of the XML output. + */ +static bool sfe_ipv4_debug_dev_read_exceptions_end(struct sfe_ipv4 *si, char *buffer, char *msg, size_t *length, + int *total_read, struct sfe_ipv4_debug_xml_write_state *ws) +{ + int bytes_read; + + bytes_read = snprintf(msg, CHAR_DEV_MSG_SIZE, "\t\n"); + if (copy_to_user(buffer + *total_read, msg, CHAR_DEV_MSG_SIZE)) { + return false; + } + + *length -= bytes_read; + *total_read += bytes_read; + + ws->state++; + return true; +} + +/* + * sfe_ipv4_debug_dev_read_stats() + * Generate part of the XML output. + */ +static bool sfe_ipv4_debug_dev_read_stats(struct sfe_ipv4 *si, char *buffer, char *msg, size_t *length, + int *total_read, struct sfe_ipv4_debug_xml_write_state *ws) +{ + int bytes_read; + unsigned int num_connections; + u64 packets_forwarded; + u64 packets_not_forwarded; + u64 connection_create_requests; + u64 connection_create_collisions; + u64 connection_destroy_requests; + u64 connection_destroy_misses; + u64 connection_flushes; + u64 connection_match_hash_hits; + u64 connection_match_hash_reorders; + + spin_lock_bh(&si->lock); + sfe_ipv4_update_summary_stats(si); + + num_connections = si->num_connections; + packets_forwarded = si->packets_forwarded64; + packets_not_forwarded = si->packets_not_forwarded64; + connection_create_requests = si->connection_create_requests64; + connection_create_collisions = si->connection_create_collisions64; + connection_destroy_requests = si->connection_destroy_requests64; + connection_destroy_misses = si->connection_destroy_misses64; + connection_flushes = si->connection_flushes64; + connection_match_hash_hits = si->connection_match_hash_hits64; + connection_match_hash_reorders = si->connection_match_hash_reorders64; + spin_unlock_bh(&si->lock); + + bytes_read = snprintf(msg, CHAR_DEV_MSG_SIZE, "\t\n", + num_connections, + packets_forwarded, + packets_not_forwarded, + connection_create_requests, + connection_create_collisions, + connection_destroy_requests, + connection_destroy_misses, + connection_flushes, + connection_match_hash_hits, + connection_match_hash_reorders); + if (copy_to_user(buffer + *total_read, msg, CHAR_DEV_MSG_SIZE)) { + return false; + } + + *length -= bytes_read; + *total_read += bytes_read; + + ws->state++; + return true; +} + +/* + * sfe_ipv4_debug_dev_read_end() + * Generate part of the XML output. + */ +static bool sfe_ipv4_debug_dev_read_end(struct sfe_ipv4 *si, char *buffer, char *msg, size_t *length, + int *total_read, struct sfe_ipv4_debug_xml_write_state *ws) +{ + int bytes_read; + + bytes_read = snprintf(msg, CHAR_DEV_MSG_SIZE, "\n"); + if (copy_to_user(buffer + *total_read, msg, CHAR_DEV_MSG_SIZE)) { + return false; + } + + *length -= bytes_read; + *total_read += bytes_read; + + ws->state++; + return true; +} + +/* + * Array of write functions that write various XML elements that correspond to + * our XML output state machine. + */ +static sfe_ipv4_debug_xml_write_method_t sfe_ipv4_debug_xml_write_methods[SFE_IPV4_DEBUG_XML_STATE_DONE] = { + sfe_ipv4_debug_dev_read_start, + sfe_ipv4_debug_dev_read_connections_start, + sfe_ipv4_debug_dev_read_connections_connection, + sfe_ipv4_debug_dev_read_connections_end, + sfe_ipv4_debug_dev_read_exceptions_start, + sfe_ipv4_debug_dev_read_exceptions_exception, + sfe_ipv4_debug_dev_read_exceptions_end, + sfe_ipv4_debug_dev_read_stats, + sfe_ipv4_debug_dev_read_end, +}; + +/* + * sfe_ipv4_debug_dev_read() + * Send info to userspace upon read request from user + */ +static ssize_t sfe_ipv4_debug_dev_read(struct file *filp, char *buffer, size_t length, loff_t *offset) +{ + char msg[CHAR_DEV_MSG_SIZE]; + int total_read = 0; + struct sfe_ipv4_debug_xml_write_state *ws; + struct sfe_ipv4 *si = &__si; + + ws = (struct sfe_ipv4_debug_xml_write_state *)filp->private_data; + while ((ws->state != SFE_IPV4_DEBUG_XML_STATE_DONE) && (length > CHAR_DEV_MSG_SIZE)) { + if ((sfe_ipv4_debug_xml_write_methods[ws->state])(si, buffer, msg, &length, &total_read, ws)) { + continue; + } + } + + return total_read; +} + +/* + * sfe_ipv4_debug_dev_write() + * Write to char device resets some stats + */ +static ssize_t sfe_ipv4_debug_dev_write(struct file *filp, const char *buffer, size_t length, loff_t *offset) +{ + struct sfe_ipv4 *si = &__si; + + spin_lock_bh(&si->lock); + sfe_ipv4_update_summary_stats(si); + + si->packets_forwarded64 = 0; + si->packets_not_forwarded64 = 0; + si->connection_create_requests64 = 0; + si->connection_create_collisions64 = 0; + si->connection_destroy_requests64 = 0; + si->connection_destroy_misses64 = 0; + si->connection_flushes64 = 0; + si->connection_match_hash_hits64 = 0; + si->connection_match_hash_reorders64 = 0; + spin_unlock_bh(&si->lock); + + return length; +} + +/* + * sfe_ipv4_debug_dev_open() + */ +static int sfe_ipv4_debug_dev_open(struct inode *inode, struct file *file) +{ + struct sfe_ipv4_debug_xml_write_state *ws; + + ws = (struct sfe_ipv4_debug_xml_write_state *)file->private_data; + if (!ws) { + ws = kzalloc(sizeof(struct sfe_ipv4_debug_xml_write_state), GFP_KERNEL); + if (!ws) { + return -ENOMEM; + } + + ws->state = SFE_IPV4_DEBUG_XML_STATE_START; + file->private_data = ws; + } + + return 0; +} + +/* + * sfe_ipv4_debug_dev_release() + */ +static int sfe_ipv4_debug_dev_release(struct inode *inode, struct file *file) +{ + struct sfe_ipv4_debug_xml_write_state *ws; + + ws = (struct sfe_ipv4_debug_xml_write_state *)file->private_data; + if (ws) { + /* + * We've finished with our output so free the write state. + */ + kfree(ws); + } + + return 0; +} + +/* + * File operations used in the debug char device + */ +static struct file_operations sfe_ipv4_debug_dev_fops = { + .read = sfe_ipv4_debug_dev_read, + .write = sfe_ipv4_debug_dev_write, + .open = sfe_ipv4_debug_dev_open, + .release = sfe_ipv4_debug_dev_release +}; + +#ifdef CONFIG_NF_FLOW_COOKIE +/* + * sfe_register_flow_cookie_cb + * register a function in SFE to let SFE use this function to configure flow cookie for a flow + * + * Hardware driver which support flow cookie should register a callback function in SFE. Then SFE + * can use this function to configure flow cookie for a flow. + * return: 0, success; !=0, fail + */ +int sfe_register_flow_cookie_cb(flow_cookie_set_func_t cb) +{ + struct sfe_ipv4 *si = &__si; + + BUG_ON(!cb); + + if (si->flow_cookie_set_func) { + return -1; + } + + rcu_assign_pointer(si->flow_cookie_set_func, cb); + return 0; +} + +/* + * sfe_unregister_flow_cookie_cb + * unregister function which is used to configure flow cookie for a flow + * + * return: 0, success; !=0, fail + */ +int sfe_unregister_flow_cookie_cb(flow_cookie_set_func_t cb) +{ + struct sfe_ipv4 *si = &__si; + + RCU_INIT_POINTER(si->flow_cookie_set_func, NULL); + return 0; +} + +/* + * sfe_ipv4_get_flow_cookie() + */ +static ssize_t sfe_ipv4_get_flow_cookie(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct sfe_ipv4 *si = &__si; + return snprintf(buf, (ssize_t)PAGE_SIZE, "%d\n", si->flow_cookie_enable); +} + +/* + * sfe_ipv4_set_flow_cookie() + */ +static ssize_t sfe_ipv4_set_flow_cookie(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + struct sfe_ipv4 *si = &__si; + strict_strtol(buf, 0, (long int *)&si->flow_cookie_enable); + + return size; +} + +/* + * sysfs attributes. + */ +static const struct device_attribute sfe_ipv4_flow_cookie_attr = + __ATTR(flow_cookie_enable, S_IWUSR | S_IRUGO, sfe_ipv4_get_flow_cookie, sfe_ipv4_set_flow_cookie); +#endif /*CONFIG_NF_FLOW_COOKIE*/ + +/* + * sfe_ipv4_init() + */ +static int __init sfe_ipv4_init(void) +{ + struct sfe_ipv4 *si = &__si; + int result = -1; + + DEBUG_INFO("SFE IPv4 init\n"); + + /* + * Create sys/sfe_ipv4 + */ + si->sys_sfe_ipv4 = kobject_create_and_add("sfe_ipv4", NULL); + if (!si->sys_sfe_ipv4) { + DEBUG_ERROR("failed to register sfe_ipv4\n"); + goto exit1; + } + + /* + * Create files, one for each parameter supported by this module. + */ + result = sysfs_create_file(si->sys_sfe_ipv4, &sfe_ipv4_debug_dev_attr.attr); + if (result) { + DEBUG_ERROR("failed to register debug dev file: %d\n", result); + goto exit2; + } + +#ifdef CONFIG_NF_FLOW_COOKIE + result = sysfs_create_file(si->sys_sfe_ipv4, &sfe_ipv4_flow_cookie_attr.attr); + if (result) { + DEBUG_ERROR("failed to register flow cookie enable file: %d\n", result); + goto exit3; + } +#endif /* CONFIG_NF_FLOW_COOKIE */ + + /* + * Register our debug char device. + */ + result = register_chrdev(0, "sfe_ipv4", &sfe_ipv4_debug_dev_fops); + if (result < 0) { + DEBUG_ERROR("Failed to register chrdev: %d\n", result); + goto exit4; + } + + si->debug_dev = result; + + /* + * Create a timer to handle periodic statistics. + */ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 15, 0)) + setup_timer(&si->timer, sfe_ipv4_periodic_sync, (unsigned long)si); +#else + timer_setup(&si->timer, sfe_ipv4_periodic_sync, 0); +#endif + mod_timer(&si->timer, jiffies + ((HZ + 99) / 100)); + + spin_lock_init(&si->lock); + + return 0; + +exit4: +#ifdef CONFIG_NF_FLOW_COOKIE + sysfs_remove_file(si->sys_sfe_ipv4, &sfe_ipv4_flow_cookie_attr.attr); + +exit3: +#endif /* CONFIG_NF_FLOW_COOKIE */ + sysfs_remove_file(si->sys_sfe_ipv4, &sfe_ipv4_debug_dev_attr.attr); + +exit2: + kobject_put(si->sys_sfe_ipv4); + +exit1: + return result; +} + +/* + * sfe_ipv4_exit() + */ +static void __exit sfe_ipv4_exit(void) +{ + struct sfe_ipv4 *si = &__si; + + DEBUG_INFO("SFE IPv4 exit\n"); + + /* + * Destroy all connections. + */ + sfe_ipv4_destroy_all_rules_for_dev(NULL); + + del_timer_sync(&si->timer); + + unregister_chrdev(si->debug_dev, "sfe_ipv4"); + +#ifdef CONFIG_NF_FLOW_COOKIE + sysfs_remove_file(si->sys_sfe_ipv4, &sfe_ipv4_flow_cookie_attr.attr); +#endif /* CONFIG_NF_FLOW_COOKIE */ + sysfs_remove_file(si->sys_sfe_ipv4, &sfe_ipv4_debug_dev_attr.attr); + + kobject_put(si->sys_sfe_ipv4); + +} + +module_init(sfe_ipv4_init) +module_exit(sfe_ipv4_exit) + +EXPORT_SYMBOL(sfe_ipv4_recv); +EXPORT_SYMBOL(sfe_ipv4_create_rule); +EXPORT_SYMBOL(sfe_ipv4_destroy_rule); +EXPORT_SYMBOL(sfe_ipv4_destroy_all_rules_for_dev); +EXPORT_SYMBOL(sfe_ipv4_register_sync_rule_callback); +EXPORT_SYMBOL(sfe_ipv4_mark_rule); +EXPORT_SYMBOL(sfe_ipv4_update_rule); +#ifdef CONFIG_NF_FLOW_COOKIE +EXPORT_SYMBOL(sfe_register_flow_cookie_cb); +EXPORT_SYMBOL(sfe_unregister_flow_cookie_cb); +#endif + +MODULE_DESCRIPTION("Shortcut Forwarding Engine - IPv4 edition"); +MODULE_LICENSE("Dual BSD/GPL"); + diff --git a/shortcut-fe/shortcut-fe/src/sfe_ipv6.c b/shortcut-fe/shortcut-fe/src/sfe_ipv6.c new file mode 100644 index 000000000..ae3306693 --- /dev/null +++ b/shortcut-fe/shortcut-fe/src/sfe_ipv6.c @@ -0,0 +1,3625 @@ +/* + * sfe_ipv6.c + * Shortcut forwarding engine - IPv6 support. + * + * Copyright (c) 2015-2016, 2019-2020 The Linux Foundation. All rights reserved. + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all copies. + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT + * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "sfe.h" +#include "sfe_cm.h" + +/* + * By default Linux IP header and transport layer header structures are + * unpacked, assuming that such headers should be 32-bit aligned. + * Unfortunately some wireless adaptors can't cope with this requirement and + * some CPUs can't handle misaligned accesses. For those platforms we + * define SFE_IPV6_UNALIGNED_IP_HEADER and mark the structures as packed. + * When we do this the compiler will generate slightly worse code than for the + * aligned case (on most platforms) but will be much quicker than fixing + * things up in an unaligned trap handler. + */ +#define SFE_IPV6_UNALIGNED_IP_HEADER 1 +#if SFE_IPV6_UNALIGNED_IP_HEADER +#define SFE_IPV6_UNALIGNED_STRUCT __attribute__((packed)) +#else +#define SFE_IPV6_UNALIGNED_STRUCT +#endif + +#define CHAR_DEV_MSG_SIZE 768 + +/* + * An Ethernet header, but with an optional "packed" attribute to + * help with performance on some platforms (see the definition of + * SFE_IPV6_UNALIGNED_STRUCT) + */ +struct sfe_ipv6_eth_hdr { + __be16 h_dest[ETH_ALEN / 2]; + __be16 h_source[ETH_ALEN / 2]; + __be16 h_proto; +} SFE_IPV6_UNALIGNED_STRUCT; + +#define SFE_IPV6_DSCP_MASK 0xf03f +#define SFE_IPV6_DSCP_SHIFT 2 + +/* + * An IPv6 header, but with an optional "packed" attribute to + * help with performance on some platforms (see the definition of + * SFE_IPV6_UNALIGNED_STRUCT) + */ +struct sfe_ipv6_ip_hdr { +#if defined(__LITTLE_ENDIAN_BITFIELD) + __u8 priority:4, + version:4; +#elif defined(__BIG_ENDIAN_BITFIELD) + __u8 version:4, + priority:4; +#else +#error "Please fix " +#endif + __u8 flow_lbl[3]; + __be16 payload_len; + __u8 nexthdr; + __u8 hop_limit; + struct sfe_ipv6_addr saddr; + struct sfe_ipv6_addr daddr; + + /* + * The extension header start here. + */ +} SFE_IPV6_UNALIGNED_STRUCT; + +#define SFE_IPV6_EXT_HDR_HOP 0 +#define SFE_IPV6_EXT_HDR_ROUTING 43 +#define SFE_IPV6_EXT_HDR_FRAG 44 +#define SFE_IPV6_EXT_HDR_ESP 50 +#define SFE_IPV6_EXT_HDR_AH 51 +#define SFE_IPV6_EXT_HDR_NONE 59 +#define SFE_IPV6_EXT_HDR_DST 60 +#define SFE_IPV6_EXT_HDR_MH 135 + +/* + * fragmentation header + */ + +struct sfe_ipv6_frag_hdr { + __u8 nexthdr; + __u8 reserved; + __be16 frag_off; + __be32 identification; +}; + +#define SFE_IPV6_FRAG_OFFSET 0xfff8 + +/* + * generic IPv6 extension header + */ +struct sfe_ipv6_ext_hdr { + __u8 next_hdr; + __u8 hdr_len; + __u8 padding[6]; +} SFE_IPV6_UNALIGNED_STRUCT; + +/* + * A UDP header, but with an optional "packed" attribute to + * help with performance on some platforms (see the definition of + * SFE_IPV6_UNALIGNED_STRUCT) + */ +struct sfe_ipv6_udp_hdr { + __be16 source; + __be16 dest; + __be16 len; + __sum16 check; +} SFE_IPV6_UNALIGNED_STRUCT; + +/* + * A TCP header, but with an optional "packed" attribute to + * help with performance on some platforms (see the definition of + * SFE_IPV6_UNALIGNED_STRUCT) + */ +struct sfe_ipv6_tcp_hdr { + __be16 source; + __be16 dest; + __be32 seq; + __be32 ack_seq; +#if defined(__LITTLE_ENDIAN_BITFIELD) + __u16 res1:4, + doff:4, + fin:1, + syn:1, + rst:1, + psh:1, + ack:1, + urg:1, + ece:1, + cwr:1; +#elif defined(__BIG_ENDIAN_BITFIELD) + __u16 doff:4, + res1:4, + cwr:1, + ece:1, + urg:1, + ack:1, + psh:1, + rst:1, + syn:1, + fin:1; +#else +#error "Adjust your defines" +#endif + __be16 window; + __sum16 check; + __be16 urg_ptr; +} SFE_IPV6_UNALIGNED_STRUCT; + +/* + * Specifies the lower bound on ACK numbers carried in the TCP header + */ +#define SFE_IPV6_TCP_MAX_ACK_WINDOW 65520 + +/* + * IPv6 TCP connection match additional data. + */ +struct sfe_ipv6_tcp_connection_match { + u8 win_scale; /* Window scale */ + u32 max_win; /* Maximum window size seen */ + u32 end; /* Sequence number of the next byte to send (seq + segment length) */ + u32 max_end; /* Sequence number of the last byte to ack */ +}; + +/* + * Bit flags for IPv6 connection matching entry. + */ +#define SFE_IPV6_CONNECTION_MATCH_FLAG_XLATE_SRC (1<<0) + /* Perform source translation */ +#define SFE_IPV6_CONNECTION_MATCH_FLAG_XLATE_DEST (1<<1) + /* Perform destination translation */ +#define SFE_IPV6_CONNECTION_MATCH_FLAG_NO_SEQ_CHECK (1<<2) + /* Ignore TCP sequence numbers */ +#define SFE_IPV6_CONNECTION_MATCH_FLAG_WRITE_FAST_ETH_HDR (1<<3) + /* Fast Ethernet header write */ +#define SFE_IPV6_CONNECTION_MATCH_FLAG_WRITE_L2_HDR (1<<4) + /* Fast Ethernet header write */ +#define SFE_IPV6_CONNECTION_MATCH_FLAG_PRIORITY_REMARK (1<<5) + /* remark priority of SKB */ +#define SFE_IPV6_CONNECTION_MATCH_FLAG_DSCP_REMARK (1<<6) + /* remark DSCP of packet */ + +/* + * IPv6 connection matching structure. + */ +struct sfe_ipv6_connection_match { + /* + * References to other objects. + */ + struct sfe_ipv6_connection_match *next; + struct sfe_ipv6_connection_match *prev; + struct sfe_ipv6_connection *connection; + struct sfe_ipv6_connection_match *counter_match; + /* Matches the flow in the opposite direction as the one in connection */ + struct sfe_ipv6_connection_match *active_next; + struct sfe_ipv6_connection_match *active_prev; + bool active; /* Flag to indicate if we're on the active list */ + + /* + * Characteristics that identify flows that match this rule. + */ + struct net_device *match_dev; /* Network device */ + u8 match_protocol; /* Protocol */ + struct sfe_ipv6_addr match_src_ip[1]; /* Source IP address */ + struct sfe_ipv6_addr match_dest_ip[1]; /* Destination IP address */ + __be16 match_src_port; /* Source port/connection ident */ + __be16 match_dest_port; /* Destination port/connection ident */ + + /* + * Control the operations of the match. + */ + u32 flags; /* Bit flags */ +#ifdef CONFIG_NF_FLOW_COOKIE + u32 flow_cookie; /* used flow cookie, for debug */ +#endif +#ifdef CONFIG_XFRM + u32 flow_accel; /* The flow accelerated or not */ +#endif + + /* + * Connection state that we track once we match. + */ + union { /* Protocol-specific state */ + struct sfe_ipv6_tcp_connection_match tcp; + } protocol_state; + /* + * Stats recorded in a sync period. These stats will be added to + * rx_packet_count64/rx_byte_count64 after a sync period. + */ + u32 rx_packet_count; + u32 rx_byte_count; + + /* + * Packet translation information. + */ + struct sfe_ipv6_addr xlate_src_ip[1]; /* Address after source translation */ + __be16 xlate_src_port; /* Port/connection ident after source translation */ + u16 xlate_src_csum_adjustment; + /* Transport layer checksum adjustment after source translation */ + struct sfe_ipv6_addr xlate_dest_ip[1]; /* Address after destination translation */ + __be16 xlate_dest_port; /* Port/connection ident after destination translation */ + u16 xlate_dest_csum_adjustment; + /* Transport layer checksum adjustment after destination translation */ + + /* + * QoS information + */ + u32 priority; + u32 dscp; + + /* + * Packet transmit information. + */ + struct net_device *xmit_dev; /* Network device on which to transmit */ + unsigned short int xmit_dev_mtu; + /* Interface MTU */ + u16 xmit_dest_mac[ETH_ALEN / 2]; + /* Destination MAC address to use when forwarding */ + u16 xmit_src_mac[ETH_ALEN / 2]; + /* Source MAC address to use when forwarding */ + + /* + * Summary stats. + */ + u64 rx_packet_count64; + u64 rx_byte_count64; +}; + +/* + * Per-connection data structure. + */ +struct sfe_ipv6_connection { + struct sfe_ipv6_connection *next; + /* Pointer to the next entry in a hash chain */ + struct sfe_ipv6_connection *prev; + /* Pointer to the previous entry in a hash chain */ + int protocol; /* IP protocol number */ + struct sfe_ipv6_addr src_ip[1]; /* Src IP addr pre-translation */ + struct sfe_ipv6_addr src_ip_xlate[1]; /* Src IP addr post-translation */ + struct sfe_ipv6_addr dest_ip[1]; /* Dest IP addr pre-translation */ + struct sfe_ipv6_addr dest_ip_xlate[1]; /* Dest IP addr post-translation */ + __be16 src_port; /* Src port pre-translation */ + __be16 src_port_xlate; /* Src port post-translation */ + __be16 dest_port; /* Dest port pre-translation */ + __be16 dest_port_xlate; /* Dest port post-translation */ + struct sfe_ipv6_connection_match *original_match; + /* Original direction matching structure */ + struct net_device *original_dev; + /* Original direction source device */ + struct sfe_ipv6_connection_match *reply_match; + /* Reply direction matching structure */ + struct net_device *reply_dev; /* Reply direction source device */ + u64 last_sync_jiffies; /* Jiffies count for the last sync */ + struct sfe_ipv6_connection *all_connections_next; + /* Pointer to the next entry in the list of all connections */ + struct sfe_ipv6_connection *all_connections_prev; + /* Pointer to the previous entry in the list of all connections */ + u32 mark; /* mark for outgoing packet */ + u32 debug_read_seq; /* sequence number for debug dump */ +}; + +/* + * IPv6 connections and hash table size information. + */ +#define SFE_IPV6_CONNECTION_HASH_SHIFT 12 +#define SFE_IPV6_CONNECTION_HASH_SIZE (1 << SFE_IPV6_CONNECTION_HASH_SHIFT) +#define SFE_IPV6_CONNECTION_HASH_MASK (SFE_IPV6_CONNECTION_HASH_SIZE - 1) + +#ifdef CONFIG_NF_FLOW_COOKIE +#define SFE_FLOW_COOKIE_SIZE 2048 +#define SFE_FLOW_COOKIE_MASK 0x7ff + +struct sfe_ipv6_flow_cookie_entry { + struct sfe_ipv6_connection_match *match; + unsigned long last_clean_time; +}; +#endif + +enum sfe_ipv6_exception_events { + SFE_IPV6_EXCEPTION_EVENT_UDP_HEADER_INCOMPLETE, + SFE_IPV6_EXCEPTION_EVENT_UDP_NO_CONNECTION, + SFE_IPV6_EXCEPTION_EVENT_UDP_IP_OPTIONS_OR_INITIAL_FRAGMENT, + SFE_IPV6_EXCEPTION_EVENT_UDP_SMALL_TTL, + SFE_IPV6_EXCEPTION_EVENT_UDP_NEEDS_FRAGMENTATION, + SFE_IPV6_EXCEPTION_EVENT_TCP_HEADER_INCOMPLETE, + SFE_IPV6_EXCEPTION_EVENT_TCP_NO_CONNECTION_SLOW_FLAGS, + SFE_IPV6_EXCEPTION_EVENT_TCP_NO_CONNECTION_FAST_FLAGS, + SFE_IPV6_EXCEPTION_EVENT_TCP_IP_OPTIONS_OR_INITIAL_FRAGMENT, + SFE_IPV6_EXCEPTION_EVENT_TCP_SMALL_TTL, + SFE_IPV6_EXCEPTION_EVENT_TCP_NEEDS_FRAGMENTATION, + SFE_IPV6_EXCEPTION_EVENT_TCP_FLAGS, + SFE_IPV6_EXCEPTION_EVENT_TCP_SEQ_EXCEEDS_RIGHT_EDGE, + SFE_IPV6_EXCEPTION_EVENT_TCP_SMALL_DATA_OFFS, + SFE_IPV6_EXCEPTION_EVENT_TCP_BAD_SACK, + SFE_IPV6_EXCEPTION_EVENT_TCP_BIG_DATA_OFFS, + SFE_IPV6_EXCEPTION_EVENT_TCP_SEQ_BEFORE_LEFT_EDGE, + SFE_IPV6_EXCEPTION_EVENT_TCP_ACK_EXCEEDS_RIGHT_EDGE, + SFE_IPV6_EXCEPTION_EVENT_TCP_ACK_BEFORE_LEFT_EDGE, + SFE_IPV6_EXCEPTION_EVENT_ICMP_HEADER_INCOMPLETE, + SFE_IPV6_EXCEPTION_EVENT_ICMP_UNHANDLED_TYPE, + SFE_IPV6_EXCEPTION_EVENT_ICMP_IPV6_HEADER_INCOMPLETE, + SFE_IPV6_EXCEPTION_EVENT_ICMP_IPV6_NON_V6, + SFE_IPV6_EXCEPTION_EVENT_ICMP_IPV6_IP_OPTIONS_INCOMPLETE, + SFE_IPV6_EXCEPTION_EVENT_ICMP_IPV6_UDP_HEADER_INCOMPLETE, + SFE_IPV6_EXCEPTION_EVENT_ICMP_IPV6_TCP_HEADER_INCOMPLETE, + SFE_IPV6_EXCEPTION_EVENT_ICMP_IPV6_UNHANDLED_PROTOCOL, + SFE_IPV6_EXCEPTION_EVENT_ICMP_NO_CONNECTION, + SFE_IPV6_EXCEPTION_EVENT_ICMP_FLUSHED_CONNECTION, + SFE_IPV6_EXCEPTION_EVENT_HEADER_INCOMPLETE, + SFE_IPV6_EXCEPTION_EVENT_BAD_TOTAL_LENGTH, + SFE_IPV6_EXCEPTION_EVENT_NON_V6, + SFE_IPV6_EXCEPTION_EVENT_NON_INITIAL_FRAGMENT, + SFE_IPV6_EXCEPTION_EVENT_DATAGRAM_INCOMPLETE, + SFE_IPV6_EXCEPTION_EVENT_IP_OPTIONS_INCOMPLETE, + SFE_IPV6_EXCEPTION_EVENT_UNHANDLED_PROTOCOL, + SFE_IPV6_EXCEPTION_EVENT_FLOW_COOKIE_ADD_FAIL, + SFE_IPV6_EXCEPTION_EVENT_CLONED_SKB_UNSHARE_ERROR, + SFE_IPV6_EXCEPTION_EVENT_LAST +}; + +static char *sfe_ipv6_exception_events_string[SFE_IPV6_EXCEPTION_EVENT_LAST] = { + "UDP_HEADER_INCOMPLETE", + "UDP_NO_CONNECTION", + "UDP_IP_OPTIONS_OR_INITIAL_FRAGMENT", + "UDP_SMALL_TTL", + "UDP_NEEDS_FRAGMENTATION", + "TCP_HEADER_INCOMPLETE", + "TCP_NO_CONNECTION_SLOW_FLAGS", + "TCP_NO_CONNECTION_FAST_FLAGS", + "TCP_IP_OPTIONS_OR_INITIAL_FRAGMENT", + "TCP_SMALL_TTL", + "TCP_NEEDS_FRAGMENTATION", + "TCP_FLAGS", + "TCP_SEQ_EXCEEDS_RIGHT_EDGE", + "TCP_SMALL_DATA_OFFS", + "TCP_BAD_SACK", + "TCP_BIG_DATA_OFFS", + "TCP_SEQ_BEFORE_LEFT_EDGE", + "TCP_ACK_EXCEEDS_RIGHT_EDGE", + "TCP_ACK_BEFORE_LEFT_EDGE", + "ICMP_HEADER_INCOMPLETE", + "ICMP_UNHANDLED_TYPE", + "ICMP_IPV6_HEADER_INCOMPLETE", + "ICMP_IPV6_NON_V6", + "ICMP_IPV6_IP_OPTIONS_INCOMPLETE", + "ICMP_IPV6_UDP_HEADER_INCOMPLETE", + "ICMP_IPV6_TCP_HEADER_INCOMPLETE", + "ICMP_IPV6_UNHANDLED_PROTOCOL", + "ICMP_NO_CONNECTION", + "ICMP_FLUSHED_CONNECTION", + "HEADER_INCOMPLETE", + "BAD_TOTAL_LENGTH", + "NON_V6", + "NON_INITIAL_FRAGMENT", + "DATAGRAM_INCOMPLETE", + "IP_OPTIONS_INCOMPLETE", + "UNHANDLED_PROTOCOL", + "FLOW_COOKIE_ADD_FAIL", + "CLONED_SKB_UNSHARE_ERROR" +}; + +/* + * Per-module structure. + */ +struct sfe_ipv6 { + spinlock_t lock; /* Lock for SMP correctness */ + struct sfe_ipv6_connection_match *active_head; + /* Head of the list of recently active connections */ + struct sfe_ipv6_connection_match *active_tail; + /* Tail of the list of recently active connections */ + struct sfe_ipv6_connection *all_connections_head; + /* Head of the list of all connections */ + struct sfe_ipv6_connection *all_connections_tail; + /* Tail of the list of all connections */ + unsigned int num_connections; /* Number of connections */ + struct timer_list timer; /* Timer used for periodic sync ops */ + sfe_sync_rule_callback_t __rcu sync_rule_callback; + /* Callback function registered by a connection manager for stats syncing */ + struct sfe_ipv6_connection *conn_hash[SFE_IPV6_CONNECTION_HASH_SIZE]; + /* Connection hash table */ + struct sfe_ipv6_connection_match *conn_match_hash[SFE_IPV6_CONNECTION_HASH_SIZE]; + /* Connection match hash table */ +#ifdef CONFIG_NF_FLOW_COOKIE + struct sfe_ipv6_flow_cookie_entry sfe_flow_cookie_table[SFE_FLOW_COOKIE_SIZE]; + /* flow cookie table*/ + sfe_ipv6_flow_cookie_set_func_t flow_cookie_set_func; + /* function used to configure flow cookie in hardware*/ + int flow_cookie_enable; + /* Enable/disable flow cookie at runtime */ +#endif + + /* + * Stats recorded in a sync period. These stats will be added to + * connection_xxx64 after a sync period. + */ + u32 connection_create_requests; + /* Number of IPv6 connection create requests */ + u32 connection_create_collisions; + /* Number of IPv6 connection create requests that collided with existing hash table entries */ + u32 connection_destroy_requests; + /* Number of IPv6 connection destroy requests */ + u32 connection_destroy_misses; + /* Number of IPv6 connection destroy requests that missed our hash table */ + u32 connection_match_hash_hits; + /* Number of IPv6 connection match hash hits */ + u32 connection_match_hash_reorders; + /* Number of IPv6 connection match hash reorders */ + u32 connection_flushes; /* Number of IPv6 connection flushes */ + u32 packets_forwarded; /* Number of IPv6 packets forwarded */ + u32 packets_not_forwarded; /* Number of IPv6 packets not forwarded */ + u32 exception_events[SFE_IPV6_EXCEPTION_EVENT_LAST]; + + /* + * Summary statistics. + */ + u64 connection_create_requests64; + /* Number of IPv6 connection create requests */ + u64 connection_create_collisions64; + /* Number of IPv6 connection create requests that collided with existing hash table entries */ + u64 connection_destroy_requests64; + /* Number of IPv6 connection destroy requests */ + u64 connection_destroy_misses64; + /* Number of IPv6 connection destroy requests that missed our hash table */ + u64 connection_match_hash_hits64; + /* Number of IPv6 connection match hash hits */ + u64 connection_match_hash_reorders64; + /* Number of IPv6 connection match hash reorders */ + u64 connection_flushes64; /* Number of IPv6 connection flushes */ + u64 packets_forwarded64; /* Number of IPv6 packets forwarded */ + u64 packets_not_forwarded64; + /* Number of IPv6 packets not forwarded */ + u64 exception_events64[SFE_IPV6_EXCEPTION_EVENT_LAST]; + + /* + * Control state. + */ + struct kobject *sys_sfe_ipv6; /* sysfs linkage */ + int debug_dev; /* Major number of the debug char device */ + u32 debug_read_seq; /* sequence number for debug dump */ +}; + +/* + * Enumeration of the XML output. + */ +enum sfe_ipv6_debug_xml_states { + SFE_IPV6_DEBUG_XML_STATE_START, + SFE_IPV6_DEBUG_XML_STATE_CONNECTIONS_START, + SFE_IPV6_DEBUG_XML_STATE_CONNECTIONS_CONNECTION, + SFE_IPV6_DEBUG_XML_STATE_CONNECTIONS_END, + SFE_IPV6_DEBUG_XML_STATE_EXCEPTIONS_START, + SFE_IPV6_DEBUG_XML_STATE_EXCEPTIONS_EXCEPTION, + SFE_IPV6_DEBUG_XML_STATE_EXCEPTIONS_END, + SFE_IPV6_DEBUG_XML_STATE_STATS, + SFE_IPV6_DEBUG_XML_STATE_END, + SFE_IPV6_DEBUG_XML_STATE_DONE +}; + +/* + * XML write state. + */ +struct sfe_ipv6_debug_xml_write_state { + enum sfe_ipv6_debug_xml_states state; + /* XML output file state machine state */ + int iter_exception; /* Next exception iterator */ +}; + +typedef bool (*sfe_ipv6_debug_xml_write_method_t)(struct sfe_ipv6 *si, char *buffer, char *msg, size_t *length, + int *total_read, struct sfe_ipv6_debug_xml_write_state *ws); + +static struct sfe_ipv6 __si6; + +/* + * sfe_ipv6_get_debug_dev() + */ +static ssize_t sfe_ipv6_get_debug_dev(struct device *dev, struct device_attribute *attr, char *buf); + +/* + * sysfs attributes. + */ +static const struct device_attribute sfe_ipv6_debug_dev_attr = + __ATTR(debug_dev, S_IWUSR | S_IRUGO, sfe_ipv6_get_debug_dev, NULL); + +/* + * sfe_ipv6_is_ext_hdr() + * check if we recognize ipv6 extension header + */ +static inline bool sfe_ipv6_is_ext_hdr(u8 hdr) +{ + return (hdr == SFE_IPV6_EXT_HDR_HOP) || + (hdr == SFE_IPV6_EXT_HDR_ROUTING) || + (hdr == SFE_IPV6_EXT_HDR_FRAG) || + (hdr == SFE_IPV6_EXT_HDR_AH) || + (hdr == SFE_IPV6_EXT_HDR_DST) || + (hdr == SFE_IPV6_EXT_HDR_MH); +} + +/* + * sfe_ipv6_change_dsfield() + * change dscp field in IPv6 packet + */ +static inline void sfe_ipv6_change_dsfield(struct sfe_ipv6_ip_hdr *iph, u8 dscp) +{ + __be16 *p = (__be16 *)iph; + + *p = ((*p & htons(SFE_IPV6_DSCP_MASK)) | htons((u16)dscp << 4)); +} + +/* + * sfe_ipv6_get_connection_match_hash() + * Generate the hash used in connection match lookups. + */ +static inline unsigned int sfe_ipv6_get_connection_match_hash(struct net_device *dev, u8 protocol, + struct sfe_ipv6_addr *src_ip, __be16 src_port, + struct sfe_ipv6_addr *dest_ip, __be16 dest_port) +{ + u32 idx, hash = 0; + size_t dev_addr = (size_t)dev; + + for (idx = 0; idx < 4; idx++) { + hash ^= src_ip->addr[idx] ^ dest_ip->addr[idx]; + } + hash = ((u32)dev_addr) ^ hash ^ protocol ^ ntohs(src_port ^ dest_port); + return ((hash >> SFE_IPV6_CONNECTION_HASH_SHIFT) ^ hash) & SFE_IPV6_CONNECTION_HASH_MASK; +} + +/* + * sfe_ipv6_find_connection_match() + * Get the IPv6 flow match info that corresponds to a particular 5-tuple. + * + * On entry we must be holding the lock that protects the hash table. + */ +static struct sfe_ipv6_connection_match * +sfe_ipv6_find_connection_match(struct sfe_ipv6 *si, struct net_device *dev, u8 protocol, + struct sfe_ipv6_addr *src_ip, __be16 src_port, + struct sfe_ipv6_addr *dest_ip, __be16 dest_port) +{ + struct sfe_ipv6_connection_match *cm; + struct sfe_ipv6_connection_match *head; + unsigned int conn_match_idx; + + conn_match_idx = sfe_ipv6_get_connection_match_hash(dev, protocol, src_ip, src_port, dest_ip, dest_port); + cm = si->conn_match_hash[conn_match_idx]; + + /* + * If we don't have anything in this chain then bail. + */ + if (unlikely(!cm)) { + return NULL; + } + + /* + * Hopefully the first entry is the one we want. + */ + if ((cm->match_src_port == src_port) + && (cm->match_dest_port == dest_port) + && (sfe_ipv6_addr_equal(cm->match_src_ip, src_ip)) + && (sfe_ipv6_addr_equal(cm->match_dest_ip, dest_ip)) + && (cm->match_protocol == protocol) + && (cm->match_dev == dev)) { + si->connection_match_hash_hits++; + return cm; + } + + /* + * Unfortunately we didn't find it at head, so we search it in chain and + * move matching entry to the top of the hash chain. We presume that this + * will be reused again very quickly. + */ + head = cm; + do { + cm = cm->next; + } while (cm && (cm->match_src_port != src_port + || cm->match_dest_port != dest_port + || !sfe_ipv6_addr_equal(cm->match_src_ip, src_ip) + || !sfe_ipv6_addr_equal(cm->match_dest_ip, dest_ip) + || cm->match_protocol != protocol + || cm->match_dev != dev)); + + /* + * Not found then we're done. + */ + if (unlikely(!cm)) { + return NULL; + } + + /* + * We found a match so move it. + */ + if (cm->next) { + cm->next->prev = cm->prev; + } + cm->prev->next = cm->next; + cm->prev = NULL; + cm->next = head; + head->prev = cm; + si->conn_match_hash[conn_match_idx] = cm; + si->connection_match_hash_reorders++; + + return cm; +} + +/* + * sfe_ipv6_connection_match_update_summary_stats() + * Update the summary stats for a connection match entry. + */ +static inline void sfe_ipv6_connection_match_update_summary_stats(struct sfe_ipv6_connection_match *cm) +{ + cm->rx_packet_count64 += cm->rx_packet_count; + cm->rx_packet_count = 0; + cm->rx_byte_count64 += cm->rx_byte_count; + cm->rx_byte_count = 0; +} + +/* + * sfe_ipv6_connection_match_compute_translations() + * Compute port and address translations for a connection match entry. + */ +static void sfe_ipv6_connection_match_compute_translations(struct sfe_ipv6_connection_match *cm) +{ + u32 diff[9]; + u32 *idx_32; + u16 *idx_16; + + /* + * Before we insert the entry look to see if this is tagged as doing address + * translations. If it is then work out the adjustment that we need to apply + * to the transport checksum. + */ + if (cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_XLATE_SRC) { + u32 adj = 0; + u32 carry = 0; + + /* + * Precompute an incremental checksum adjustment so we can + * edit packets in this stream very quickly. The algorithm is from RFC1624. + */ + idx_32 = diff; + *(idx_32++) = cm->match_src_ip->addr[0]; + *(idx_32++) = cm->match_src_ip->addr[1]; + *(idx_32++) = cm->match_src_ip->addr[2]; + *(idx_32++) = cm->match_src_ip->addr[3]; + + idx_16 = (u16 *)idx_32; + *(idx_16++) = cm->match_src_port; + *(idx_16++) = ~cm->xlate_src_port; + idx_32 = (u32 *)idx_16; + + *(idx_32++) = ~cm->xlate_src_ip->addr[0]; + *(idx_32++) = ~cm->xlate_src_ip->addr[1]; + *(idx_32++) = ~cm->xlate_src_ip->addr[2]; + *(idx_32++) = ~cm->xlate_src_ip->addr[3]; + + /* + * When we compute this fold it down to a 16-bit offset + * as that way we can avoid having to do a double + * folding of the twos-complement result because the + * addition of 2 16-bit values cannot cause a double + * wrap-around! + */ + for (idx_32 = diff; idx_32 < diff + 9; idx_32++) { + u32 w = *idx_32; + adj += carry; + adj += w; + carry = (w > adj); + } + adj += carry; + adj = (adj & 0xffff) + (adj >> 16); + adj = (adj & 0xffff) + (adj >> 16); + cm->xlate_src_csum_adjustment = (u16)adj; + } + + if (cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_XLATE_DEST) { + u32 adj = 0; + u32 carry = 0; + + /* + * Precompute an incremental checksum adjustment so we can + * edit packets in this stream very quickly. The algorithm is from RFC1624. + */ + idx_32 = diff; + *(idx_32++) = cm->match_dest_ip->addr[0]; + *(idx_32++) = cm->match_dest_ip->addr[1]; + *(idx_32++) = cm->match_dest_ip->addr[2]; + *(idx_32++) = cm->match_dest_ip->addr[3]; + + idx_16 = (u16 *)idx_32; + *(idx_16++) = cm->match_dest_port; + *(idx_16++) = ~cm->xlate_dest_port; + idx_32 = (u32 *)idx_16; + + *(idx_32++) = ~cm->xlate_dest_ip->addr[0]; + *(idx_32++) = ~cm->xlate_dest_ip->addr[1]; + *(idx_32++) = ~cm->xlate_dest_ip->addr[2]; + *(idx_32++) = ~cm->xlate_dest_ip->addr[3]; + + /* + * When we compute this fold it down to a 16-bit offset + * as that way we can avoid having to do a double + * folding of the twos-complement result because the + * addition of 2 16-bit values cannot cause a double + * wrap-around! + */ + for (idx_32 = diff; idx_32 < diff + 9; idx_32++) { + u32 w = *idx_32; + adj += carry; + adj += w; + carry = (w > adj); + } + adj += carry; + adj = (adj & 0xffff) + (adj >> 16); + adj = (adj & 0xffff) + (adj >> 16); + cm->xlate_dest_csum_adjustment = (u16)adj; + } +} + +/* + * sfe_ipv6_update_summary_stats() + * Update the summary stats. + */ +static void sfe_ipv6_update_summary_stats(struct sfe_ipv6 *si) +{ + int i; + + si->connection_create_requests64 += si->connection_create_requests; + si->connection_create_requests = 0; + si->connection_create_collisions64 += si->connection_create_collisions; + si->connection_create_collisions = 0; + si->connection_destroy_requests64 += si->connection_destroy_requests; + si->connection_destroy_requests = 0; + si->connection_destroy_misses64 += si->connection_destroy_misses; + si->connection_destroy_misses = 0; + si->connection_match_hash_hits64 += si->connection_match_hash_hits; + si->connection_match_hash_hits = 0; + si->connection_match_hash_reorders64 += si->connection_match_hash_reorders; + si->connection_match_hash_reorders = 0; + si->connection_flushes64 += si->connection_flushes; + si->connection_flushes = 0; + si->packets_forwarded64 += si->packets_forwarded; + si->packets_forwarded = 0; + si->packets_not_forwarded64 += si->packets_not_forwarded; + si->packets_not_forwarded = 0; + + for (i = 0; i < SFE_IPV6_EXCEPTION_EVENT_LAST; i++) { + si->exception_events64[i] += si->exception_events[i]; + si->exception_events[i] = 0; + } +} + +/* + * sfe_ipv6_insert_connection_match() + * Insert a connection match into the hash. + * + * On entry we must be holding the lock that protects the hash table. + */ +static inline void sfe_ipv6_insert_connection_match(struct sfe_ipv6 *si, + struct sfe_ipv6_connection_match *cm) +{ + struct sfe_ipv6_connection_match **hash_head; + struct sfe_ipv6_connection_match *prev_head; + unsigned int conn_match_idx + = sfe_ipv6_get_connection_match_hash(cm->match_dev, cm->match_protocol, + cm->match_src_ip, cm->match_src_port, + cm->match_dest_ip, cm->match_dest_port); + + hash_head = &si->conn_match_hash[conn_match_idx]; + prev_head = *hash_head; + cm->prev = NULL; + if (prev_head) { + prev_head->prev = cm; + } + + cm->next = prev_head; + *hash_head = cm; + +#ifdef CONFIG_NF_FLOW_COOKIE + if (!si->flow_cookie_enable || !(cm->flags & (SFE_IPV6_CONNECTION_MATCH_FLAG_XLATE_SRC | SFE_IPV6_CONNECTION_MATCH_FLAG_XLATE_DEST))) + return; + + /* + * Configure hardware to put a flow cookie in packet of this flow, + * then we can accelerate the lookup process when we received this packet. + */ + for (conn_match_idx = 1; conn_match_idx < SFE_FLOW_COOKIE_SIZE; conn_match_idx++) { + struct sfe_ipv6_flow_cookie_entry *entry = &si->sfe_flow_cookie_table[conn_match_idx]; + + if ((NULL == entry->match) && time_is_before_jiffies(entry->last_clean_time + HZ)) { + sfe_ipv6_flow_cookie_set_func_t func; + + rcu_read_lock(); + func = rcu_dereference(si->flow_cookie_set_func); + if (func) { + if (!func(cm->match_protocol, cm->match_src_ip->addr, cm->match_src_port, + cm->match_dest_ip->addr, cm->match_dest_port, conn_match_idx)) { + entry->match = cm; + cm->flow_cookie = conn_match_idx; + } else { + si->exception_events[SFE_IPV6_EXCEPTION_EVENT_FLOW_COOKIE_ADD_FAIL]++; + } + } + rcu_read_unlock(); + + break; + } + } +#endif +} + +/* + * sfe_ipv6_remove_connection_match() + * Remove a connection match object from the hash. + * + * On entry we must be holding the lock that protects the hash table. + */ +static inline void sfe_ipv6_remove_connection_match(struct sfe_ipv6 *si, struct sfe_ipv6_connection_match *cm) +{ +#ifdef CONFIG_NF_FLOW_COOKIE + if (si->flow_cookie_enable) { + /* + * Tell hardware that we no longer need a flow cookie in packet of this flow + */ + unsigned int conn_match_idx; + + for (conn_match_idx = 1; conn_match_idx < SFE_FLOW_COOKIE_SIZE; conn_match_idx++) { + struct sfe_ipv6_flow_cookie_entry *entry = &si->sfe_flow_cookie_table[conn_match_idx]; + + if (cm == entry->match) { + sfe_ipv6_flow_cookie_set_func_t func; + + rcu_read_lock(); + func = rcu_dereference(si->flow_cookie_set_func); + if (func) { + func(cm->match_protocol, cm->match_src_ip->addr, cm->match_src_port, + cm->match_dest_ip->addr, cm->match_dest_port, 0); + } + rcu_read_unlock(); + + cm->flow_cookie = 0; + entry->match = NULL; + entry->last_clean_time = jiffies; + break; + } + } + } +#endif + + /* + * Unlink the connection match entry from the hash. + */ + if (cm->prev) { + cm->prev->next = cm->next; + } else { + unsigned int conn_match_idx + = sfe_ipv6_get_connection_match_hash(cm->match_dev, cm->match_protocol, + cm->match_src_ip, cm->match_src_port, + cm->match_dest_ip, cm->match_dest_port); + si->conn_match_hash[conn_match_idx] = cm->next; + } + + if (cm->next) { + cm->next->prev = cm->prev; + } + + /* + * If the connection match entry is in the active list remove it. + */ + if (cm->active) { + if (likely(cm->active_prev)) { + cm->active_prev->active_next = cm->active_next; + } else { + si->active_head = cm->active_next; + } + + if (likely(cm->active_next)) { + cm->active_next->active_prev = cm->active_prev; + } else { + si->active_tail = cm->active_prev; + } + } +} + +/* + * sfe_ipv6_get_connection_hash() + * Generate the hash used in connection lookups. + */ +static inline unsigned int sfe_ipv6_get_connection_hash(u8 protocol, struct sfe_ipv6_addr *src_ip, __be16 src_port, + struct sfe_ipv6_addr *dest_ip, __be16 dest_port) +{ + u32 idx, hash = 0; + + for (idx = 0; idx < 4; idx++) { + hash ^= src_ip->addr[idx] ^ dest_ip->addr[idx]; + } + hash = hash ^ protocol ^ ntohs(src_port ^ dest_port); + return ((hash >> SFE_IPV6_CONNECTION_HASH_SHIFT) ^ hash) & SFE_IPV6_CONNECTION_HASH_MASK; +} + +/* + * sfe_ipv6_find_connection() + * Get the IPv6 connection info that corresponds to a particular 5-tuple. + * + * On entry we must be holding the lock that protects the hash table. + */ +static inline struct sfe_ipv6_connection *sfe_ipv6_find_connection(struct sfe_ipv6 *si, u32 protocol, + struct sfe_ipv6_addr *src_ip, __be16 src_port, + struct sfe_ipv6_addr *dest_ip, __be16 dest_port) +{ + struct sfe_ipv6_connection *c; + unsigned int conn_idx = sfe_ipv6_get_connection_hash(protocol, src_ip, src_port, dest_ip, dest_port); + c = si->conn_hash[conn_idx]; + + /* + * If we don't have anything in this chain then bale. + */ + if (unlikely(!c)) { + return NULL; + } + + /* + * Hopefully the first entry is the one we want. + */ + if ((c->src_port == src_port) + && (c->dest_port == dest_port) + && (sfe_ipv6_addr_equal(c->src_ip, src_ip)) + && (sfe_ipv6_addr_equal(c->dest_ip, dest_ip)) + && (c->protocol == protocol)) { + return c; + } + + /* + * Unfortunately we didn't find it at head, so we search it in chain. + */ + do { + c = c->next; + } while (c && (c->src_port != src_port + || c->dest_port != dest_port + || !sfe_ipv6_addr_equal(c->src_ip, src_ip) + || !sfe_ipv6_addr_equal(c->dest_ip, dest_ip) + || c->protocol != protocol)); + + /* + * Will need connection entry for next create/destroy metadata, + * So no need to re-order entry for these requests + */ + return c; +} + +/* + * sfe_ipv6_mark_rule() + * Updates the mark for a current offloaded connection + * + * Will take hash lock upon entry + */ +void sfe_ipv6_mark_rule(struct sfe_connection_mark *mark) +{ + struct sfe_ipv6 *si = &__si6; + struct sfe_ipv6_connection *c; + + spin_lock_bh(&si->lock); + c = sfe_ipv6_find_connection(si, mark->protocol, + mark->src_ip.ip6, mark->src_port, + mark->dest_ip.ip6, mark->dest_port); + if (c) { + WARN_ON((0 != c->mark) && (0 == mark->mark)); + c->mark = mark->mark; + } + spin_unlock_bh(&si->lock); + + if (c) { + DEBUG_TRACE("Matching connection found for mark, " + "setting from %08x to %08x\n", + c->mark, mark->mark); + } +} + +/* + * sfe_ipv6_insert_connection() + * Insert a connection into the hash. + * + * On entry we must be holding the lock that protects the hash table. + */ +static void sfe_ipv6_insert_connection(struct sfe_ipv6 *si, struct sfe_ipv6_connection *c) +{ + struct sfe_ipv6_connection **hash_head; + struct sfe_ipv6_connection *prev_head; + unsigned int conn_idx; + + /* + * Insert entry into the connection hash. + */ + conn_idx = sfe_ipv6_get_connection_hash(c->protocol, c->src_ip, c->src_port, + c->dest_ip, c->dest_port); + hash_head = &si->conn_hash[conn_idx]; + prev_head = *hash_head; + c->prev = NULL; + if (prev_head) { + prev_head->prev = c; + } + + c->next = prev_head; + *hash_head = c; + + /* + * Insert entry into the "all connections" list. + */ + if (si->all_connections_tail) { + c->all_connections_prev = si->all_connections_tail; + si->all_connections_tail->all_connections_next = c; + } else { + c->all_connections_prev = NULL; + si->all_connections_head = c; + } + + si->all_connections_tail = c; + c->all_connections_next = NULL; + si->num_connections++; + + /* + * Insert the connection match objects too. + */ + sfe_ipv6_insert_connection_match(si, c->original_match); + sfe_ipv6_insert_connection_match(si, c->reply_match); +} + +/* + * sfe_ipv6_remove_connection() + * Remove a sfe_ipv6_connection object from the hash. + * + * On entry we must be holding the lock that protects the hash table. + */ +static void sfe_ipv6_remove_connection(struct sfe_ipv6 *si, struct sfe_ipv6_connection *c) +{ + /* + * Remove the connection match objects. + */ + sfe_ipv6_remove_connection_match(si, c->reply_match); + sfe_ipv6_remove_connection_match(si, c->original_match); + + /* + * Unlink the connection. + */ + if (c->prev) { + c->prev->next = c->next; + } else { + unsigned int conn_idx = sfe_ipv6_get_connection_hash(c->protocol, c->src_ip, c->src_port, + c->dest_ip, c->dest_port); + si->conn_hash[conn_idx] = c->next; + } + + if (c->next) { + c->next->prev = c->prev; + } + + /* + * Unlink connection from all_connections list + */ + if (c->all_connections_prev) { + c->all_connections_prev->all_connections_next = c->all_connections_next; + } else { + si->all_connections_head = c->all_connections_next; + } + + if (c->all_connections_next) { + c->all_connections_next->all_connections_prev = c->all_connections_prev; + } else { + si->all_connections_tail = c->all_connections_prev; + } + + si->num_connections--; +} + +/* + * sfe_ipv6_gen_sync_connection() + * Sync a connection. + * + * On entry to this function we expect that the lock for the connection is either + * already held or isn't required. + */ +static void sfe_ipv6_gen_sync_connection(struct sfe_ipv6 *si, struct sfe_ipv6_connection *c, + struct sfe_connection_sync *sis, sfe_sync_reason_t reason, + u64 now_jiffies) +{ + struct sfe_ipv6_connection_match *original_cm; + struct sfe_ipv6_connection_match *reply_cm; + + /* + * Fill in the update message. + */ + sis->is_v6 = 1; + sis->protocol = c->protocol; + sis->src_ip.ip6[0] = c->src_ip[0]; + sis->src_ip_xlate.ip6[0] = c->src_ip_xlate[0]; + sis->dest_ip.ip6[0] = c->dest_ip[0]; + sis->dest_ip_xlate.ip6[0] = c->dest_ip_xlate[0]; + sis->src_port = c->src_port; + sis->src_port_xlate = c->src_port_xlate; + sis->dest_port = c->dest_port; + sis->dest_port_xlate = c->dest_port_xlate; + + original_cm = c->original_match; + reply_cm = c->reply_match; + sis->src_td_max_window = original_cm->protocol_state.tcp.max_win; + sis->src_td_end = original_cm->protocol_state.tcp.end; + sis->src_td_max_end = original_cm->protocol_state.tcp.max_end; + sis->dest_td_max_window = reply_cm->protocol_state.tcp.max_win; + sis->dest_td_end = reply_cm->protocol_state.tcp.end; + sis->dest_td_max_end = reply_cm->protocol_state.tcp.max_end; + + sis->src_new_packet_count = original_cm->rx_packet_count; + sis->src_new_byte_count = original_cm->rx_byte_count; + sis->dest_new_packet_count = reply_cm->rx_packet_count; + sis->dest_new_byte_count = reply_cm->rx_byte_count; + + sfe_ipv6_connection_match_update_summary_stats(original_cm); + sfe_ipv6_connection_match_update_summary_stats(reply_cm); + + sis->src_dev = original_cm->match_dev; + sis->src_packet_count = original_cm->rx_packet_count64; + sis->src_byte_count = original_cm->rx_byte_count64; + + sis->dest_dev = reply_cm->match_dev; + sis->dest_packet_count = reply_cm->rx_packet_count64; + sis->dest_byte_count = reply_cm->rx_byte_count64; + + sis->reason = reason; + + /* + * Get the time increment since our last sync. + */ + sis->delta_jiffies = now_jiffies - c->last_sync_jiffies; + c->last_sync_jiffies = now_jiffies; +} + +/* + * sfe_ipv6_flush_connection() + * Flush a connection and free all associated resources. + * + * We need to be called with bottom halves disabled locally as we need to acquire + * the connection hash lock and release it again. In general we're actually called + * from within a BH and so we're fine, but we're also called when connections are + * torn down. + */ +static void sfe_ipv6_flush_connection(struct sfe_ipv6 *si, + struct sfe_ipv6_connection *c, + sfe_sync_reason_t reason) +{ + struct sfe_connection_sync sis; + u64 now_jiffies; + sfe_sync_rule_callback_t sync_rule_callback; + + rcu_read_lock(); + spin_lock_bh(&si->lock); + si->connection_flushes++; + sync_rule_callback = rcu_dereference(si->sync_rule_callback); + spin_unlock_bh(&si->lock); + + if (sync_rule_callback) { + /* + * Generate a sync message and then sync. + */ + now_jiffies = get_jiffies_64(); + sfe_ipv6_gen_sync_connection(si, c, &sis, reason, now_jiffies); + sync_rule_callback(&sis); + } + + rcu_read_unlock(); + + /* + * Release our hold of the source and dest devices and free the memory + * for our connection objects. + */ + dev_put(c->original_dev); + dev_put(c->reply_dev); + kfree(c->original_match); + kfree(c->reply_match); + kfree(c); +} + +/* + * sfe_ipv6_recv_udp() + * Handle UDP packet receives and forwarding. + */ +static int sfe_ipv6_recv_udp(struct sfe_ipv6 *si, struct sk_buff *skb, struct net_device *dev, + unsigned int len, struct sfe_ipv6_ip_hdr *iph, unsigned int ihl, bool flush_on_find) +{ + struct sfe_ipv6_udp_hdr *udph; + struct sfe_ipv6_addr *src_ip; + struct sfe_ipv6_addr *dest_ip; + __be16 src_port; + __be16 dest_port; + struct sfe_ipv6_connection_match *cm; + struct net_device *xmit_dev; + + /* + * Is our packet too short to contain a valid UDP header? + */ + if (!pskb_may_pull(skb, (sizeof(struct sfe_ipv6_udp_hdr) + ihl))) { + spin_lock_bh(&si->lock); + si->exception_events[SFE_IPV6_EXCEPTION_EVENT_UDP_HEADER_INCOMPLETE]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("packet too short for UDP header\n"); + return 0; + } + + /* + * Read the IP address and port information. Read the IP header data first + * because we've almost certainly got that in the cache. We may not yet have + * the UDP header cached though so allow more time for any prefetching. + */ + src_ip = &iph->saddr; + dest_ip = &iph->daddr; + + udph = (struct sfe_ipv6_udp_hdr *)(skb->data + ihl); + src_port = udph->source; + dest_port = udph->dest; + + spin_lock_bh(&si->lock); + + /* + * Look for a connection match. + */ +#ifdef CONFIG_NF_FLOW_COOKIE + cm = si->sfe_flow_cookie_table[skb->flow_cookie & SFE_FLOW_COOKIE_MASK].match; + if (unlikely(!cm)) { + cm = sfe_ipv6_find_connection_match(si, dev, IPPROTO_UDP, src_ip, src_port, dest_ip, dest_port); + } +#else + cm = sfe_ipv6_find_connection_match(si, dev, IPPROTO_UDP, src_ip, src_port, dest_ip, dest_port); +#endif + if (unlikely(!cm)) { + si->exception_events[SFE_IPV6_EXCEPTION_EVENT_UDP_NO_CONNECTION]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("no connection found\n"); + return 0; + } + + /* + * If our packet has beern marked as "flush on find" we can't actually + * forward it in the fast path, but now that we've found an associated + * connection we can flush that out before we process the packet. + */ + if (unlikely(flush_on_find)) { + struct sfe_ipv6_connection *c = cm->connection; + sfe_ipv6_remove_connection(si, c); + si->exception_events[SFE_IPV6_EXCEPTION_EVENT_UDP_IP_OPTIONS_OR_INITIAL_FRAGMENT]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("flush on find\n"); + sfe_ipv6_flush_connection(si, c, SFE_SYNC_REASON_FLUSH); + return 0; + } + +#ifdef CONFIG_XFRM + /* + * We can't accelerate the flow on this direction, just let it go + * through the slow path. + */ + if (unlikely(!cm->flow_accel)) { + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + return 0; + } +#endif + + /* + * Does our hop_limit allow forwarding? + */ + if (unlikely(iph->hop_limit < 2)) { + struct sfe_ipv6_connection *c = cm->connection; + sfe_ipv6_remove_connection(si, c); + si->exception_events[SFE_IPV6_EXCEPTION_EVENT_UDP_SMALL_TTL]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("hop_limit too low\n"); + sfe_ipv6_flush_connection(si, c, SFE_SYNC_REASON_FLUSH); + return 0; + } + + /* + * If our packet is larger than the MTU of the transmit interface then + * we can't forward it easily. + */ + if (unlikely(len > cm->xmit_dev_mtu)) { + struct sfe_ipv6_connection *c = cm->connection; + sfe_ipv6_remove_connection(si, c); + si->exception_events[SFE_IPV6_EXCEPTION_EVENT_UDP_NEEDS_FRAGMENTATION]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("larger than mtu\n"); + sfe_ipv6_flush_connection(si, c, SFE_SYNC_REASON_FLUSH); + return 0; + } + + /* + * From this point on we're good to modify the packet. + */ + + /* + * Check if skb was cloned. If it was, unshare it. Because + * the data area is going to be written in this path and we don't want to + * change the cloned skb's data section. + */ + if (unlikely(skb_cloned(skb))) { + DEBUG_TRACE("%px: skb is a cloned skb\n", skb); + skb = skb_unshare(skb, GFP_ATOMIC); + if (!skb) { + DEBUG_WARN("Failed to unshare the cloned skb\n"); + si->exception_events[SFE_IPV6_EXCEPTION_EVENT_CLONED_SKB_UNSHARE_ERROR]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + return 0; + } + + /* + * Update the iph and udph pointers with the unshared skb's data area. + */ + iph = (struct sfe_ipv6_ip_hdr *)skb->data; + udph = (struct sfe_ipv6_udp_hdr *)(skb->data + ihl); + } + + /* + * Update DSCP + */ + if (unlikely(cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_DSCP_REMARK)) { + sfe_ipv6_change_dsfield(iph, cm->dscp); + } + + /* + * Decrement our hop_limit. + */ + iph->hop_limit -= 1; + + /* + * Do we have to perform translations of the source address/port? + */ + if (unlikely(cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_XLATE_SRC)) { + u16 udp_csum; + + iph->saddr = cm->xlate_src_ip[0]; + udph->source = cm->xlate_src_port; + + /* + * Do we have a non-zero UDP checksum? If we do then we need + * to update it. + */ + udp_csum = udph->check; + if (likely(udp_csum)) { + u32 sum = udp_csum + cm->xlate_src_csum_adjustment; + sum = (sum & 0xffff) + (sum >> 16); + udph->check = (u16)sum; + } + } + + /* + * Do we have to perform translations of the destination address/port? + */ + if (unlikely(cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_XLATE_DEST)) { + u16 udp_csum; + + iph->daddr = cm->xlate_dest_ip[0]; + udph->dest = cm->xlate_dest_port; + + /* + * Do we have a non-zero UDP checksum? If we do then we need + * to update it. + */ + udp_csum = udph->check; + if (likely(udp_csum)) { + u32 sum = udp_csum + cm->xlate_dest_csum_adjustment; + sum = (sum & 0xffff) + (sum >> 16); + udph->check = (u16)sum; + } + } + + /* + * Update traffic stats. + */ + cm->rx_packet_count++; + cm->rx_byte_count += len; + + /* + * If we're not already on the active list then insert ourselves at the tail + * of the current list. + */ + if (unlikely(!cm->active)) { + cm->active = true; + cm->active_prev = si->active_tail; + if (likely(si->active_tail)) { + si->active_tail->active_next = cm; + } else { + si->active_head = cm; + } + si->active_tail = cm; + } + + xmit_dev = cm->xmit_dev; + skb->dev = xmit_dev; + + /* + * Check to see if we need to write a header. + */ + if (likely(cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_WRITE_L2_HDR)) { + if (unlikely(!(cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_WRITE_FAST_ETH_HDR))) { + dev_hard_header(skb, xmit_dev, ETH_P_IPV6, + cm->xmit_dest_mac, cm->xmit_src_mac, len); + } else { + /* + * For the simple case we write this really fast. + */ + struct sfe_ipv6_eth_hdr *eth = (struct sfe_ipv6_eth_hdr *)__skb_push(skb, ETH_HLEN); + eth->h_proto = htons(ETH_P_IPV6); + eth->h_dest[0] = cm->xmit_dest_mac[0]; + eth->h_dest[1] = cm->xmit_dest_mac[1]; + eth->h_dest[2] = cm->xmit_dest_mac[2]; + eth->h_source[0] = cm->xmit_src_mac[0]; + eth->h_source[1] = cm->xmit_src_mac[1]; + eth->h_source[2] = cm->xmit_src_mac[2]; + } + } + + /* + * Update priority of skb. + */ + if (unlikely(cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_PRIORITY_REMARK)) { + skb->priority = cm->priority; + } + + /* + * Mark outgoing packet. + */ + skb->mark = cm->connection->mark; + if (skb->mark) { + DEBUG_TRACE("SKB MARK is NON ZERO %x\n", skb->mark); + } + + si->packets_forwarded++; + spin_unlock_bh(&si->lock); + + /* + * We're going to check for GSO flags when we transmit the packet so + * start fetching the necessary cache line now. + */ + prefetch(skb_shinfo(skb)); + + /* + * Mark that this packet has been fast forwarded. + */ + skb->fast_forwarded = 1; + + /* + * Send the packet on its way. + */ + dev_queue_xmit(skb); + + return 1; +} + +/* + * sfe_ipv6_process_tcp_option_sack() + * Parse TCP SACK option and update ack according + */ +static bool sfe_ipv6_process_tcp_option_sack(const struct sfe_ipv6_tcp_hdr *th, const u32 data_offs, + u32 *ack) +{ + u32 length = sizeof(struct sfe_ipv6_tcp_hdr); + u8 *ptr = (u8 *)th + length; + + /* + * Ignore processing if TCP packet has only TIMESTAMP option. + */ + if (likely(data_offs == length + TCPOLEN_TIMESTAMP + 1 + 1) + && likely(ptr[0] == TCPOPT_NOP) + && likely(ptr[1] == TCPOPT_NOP) + && likely(ptr[2] == TCPOPT_TIMESTAMP) + && likely(ptr[3] == TCPOLEN_TIMESTAMP)) { + return true; + } + + /* + * TCP options. Parse SACK option. + */ + while (length < data_offs) { + u8 size; + u8 kind; + + ptr = (u8 *)th + length; + kind = *ptr; + + /* + * NOP, for padding + * Not in the switch because to fast escape and to not calculate size + */ + if (kind == TCPOPT_NOP) { + length++; + continue; + } + + if (kind == TCPOPT_SACK) { + u32 sack = 0; + u8 re = 1 + 1; + + size = *(ptr + 1); + if ((size < (1 + 1 + TCPOLEN_SACK_PERBLOCK)) + || ((size - (1 + 1)) % (TCPOLEN_SACK_PERBLOCK)) + || (size > (data_offs - length))) { + return false; + } + + re += 4; + while (re < size) { + u32 sack_re; + u8 *sptr = ptr + re; + sack_re = (sptr[0] << 24) | (sptr[1] << 16) | (sptr[2] << 8) | sptr[3]; + if (sack_re > sack) { + sack = sack_re; + } + re += TCPOLEN_SACK_PERBLOCK; + } + if (sack > *ack) { + *ack = sack; + } + length += size; + continue; + } + if (kind == TCPOPT_EOL) { + return true; + } + size = *(ptr + 1); + if (size < 2) { + return false; + } + length += size; + } + + return true; +} + +/* + * sfe_ipv6_recv_tcp() + * Handle TCP packet receives and forwarding. + */ +static int sfe_ipv6_recv_tcp(struct sfe_ipv6 *si, struct sk_buff *skb, struct net_device *dev, + unsigned int len, struct sfe_ipv6_ip_hdr *iph, unsigned int ihl, bool flush_on_find) +{ + struct sfe_ipv6_tcp_hdr *tcph; + struct sfe_ipv6_addr *src_ip; + struct sfe_ipv6_addr *dest_ip; + __be16 src_port; + __be16 dest_port; + struct sfe_ipv6_connection_match *cm; + struct sfe_ipv6_connection_match *counter_cm; + u32 flags; + struct net_device *xmit_dev; + + /* + * Is our packet too short to contain a valid UDP header? + */ + if (!pskb_may_pull(skb, (sizeof(struct sfe_ipv6_tcp_hdr) + ihl))) { + spin_lock_bh(&si->lock); + si->exception_events[SFE_IPV6_EXCEPTION_EVENT_TCP_HEADER_INCOMPLETE]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("packet too short for TCP header\n"); + return 0; + } + + /* + * Read the IP address and port information. Read the IP header data first + * because we've almost certainly got that in the cache. We may not yet have + * the TCP header cached though so allow more time for any prefetching. + */ + src_ip = &iph->saddr; + dest_ip = &iph->daddr; + + tcph = (struct sfe_ipv6_tcp_hdr *)(skb->data + ihl); + src_port = tcph->source; + dest_port = tcph->dest; + flags = tcp_flag_word(tcph); + + spin_lock_bh(&si->lock); + + /* + * Look for a connection match. + */ +#ifdef CONFIG_NF_FLOW_COOKIE + cm = si->sfe_flow_cookie_table[skb->flow_cookie & SFE_FLOW_COOKIE_MASK].match; + if (unlikely(!cm)) { + cm = sfe_ipv6_find_connection_match(si, dev, IPPROTO_TCP, src_ip, src_port, dest_ip, dest_port); + } +#else + cm = sfe_ipv6_find_connection_match(si, dev, IPPROTO_TCP, src_ip, src_port, dest_ip, dest_port); +#endif + if (unlikely(!cm)) { + /* + * We didn't get a connection but as TCP is connection-oriented that + * may be because this is a non-fast connection (not running established). + * For diagnostic purposes we differentiate this here. + */ + if (likely((flags & (TCP_FLAG_SYN | TCP_FLAG_RST | TCP_FLAG_FIN | TCP_FLAG_ACK)) == TCP_FLAG_ACK)) { + si->exception_events[SFE_IPV6_EXCEPTION_EVENT_TCP_NO_CONNECTION_FAST_FLAGS]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("no connection found - fast flags\n"); + return 0; + } + si->exception_events[SFE_IPV6_EXCEPTION_EVENT_TCP_NO_CONNECTION_SLOW_FLAGS]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("no connection found - slow flags: 0x%x\n", + flags & (TCP_FLAG_SYN | TCP_FLAG_RST | TCP_FLAG_FIN | TCP_FLAG_ACK)); + return 0; + } + + /* + * If our packet has beern marked as "flush on find" we can't actually + * forward it in the fast path, but now that we've found an associated + * connection we can flush that out before we process the packet. + */ + if (unlikely(flush_on_find)) { + struct sfe_ipv6_connection *c = cm->connection; + sfe_ipv6_remove_connection(si, c); + si->exception_events[SFE_IPV6_EXCEPTION_EVENT_TCP_IP_OPTIONS_OR_INITIAL_FRAGMENT]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("flush on find\n"); + sfe_ipv6_flush_connection(si, c, SFE_SYNC_REASON_FLUSH); + return 0; + } + +#ifdef CONFIG_XFRM + /* + * We can't accelerate the flow on this direction, just let it go + * through the slow path. + */ + if (unlikely(!cm->flow_accel)) { + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + return 0; + } +#endif + + /* + * Does our hop_limit allow forwarding? + */ + if (unlikely(iph->hop_limit < 2)) { + struct sfe_ipv6_connection *c = cm->connection; + sfe_ipv6_remove_connection(si, c); + si->exception_events[SFE_IPV6_EXCEPTION_EVENT_TCP_SMALL_TTL]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("hop_limit too low\n"); + sfe_ipv6_flush_connection(si, c, SFE_SYNC_REASON_FLUSH); + return 0; + } + + /* + * If our packet is larger than the MTU of the transmit interface then + * we can't forward it easily. + */ + if (unlikely((len > cm->xmit_dev_mtu) && !skb_is_gso(skb))) { + struct sfe_ipv6_connection *c = cm->connection; + sfe_ipv6_remove_connection(si, c); + si->exception_events[SFE_IPV6_EXCEPTION_EVENT_TCP_NEEDS_FRAGMENTATION]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("larger than mtu\n"); + sfe_ipv6_flush_connection(si, c, SFE_SYNC_REASON_FLUSH); + return 0; + } + + /* + * Look at our TCP flags. Anything missing an ACK or that has RST, SYN or FIN + * set is not a fast path packet. + */ + if (unlikely((flags & (TCP_FLAG_SYN | TCP_FLAG_RST | TCP_FLAG_FIN | TCP_FLAG_ACK)) != TCP_FLAG_ACK)) { + struct sfe_ipv6_connection *c = cm->connection; + sfe_ipv6_remove_connection(si, c); + si->exception_events[SFE_IPV6_EXCEPTION_EVENT_TCP_FLAGS]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("TCP flags: 0x%x are not fast\n", + flags & (TCP_FLAG_SYN | TCP_FLAG_RST | TCP_FLAG_FIN | TCP_FLAG_ACK)); + sfe_ipv6_flush_connection(si, c, SFE_SYNC_REASON_FLUSH); + return 0; + } + + counter_cm = cm->counter_match; + + /* + * Are we doing sequence number checking? + */ + if (likely(!(cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_NO_SEQ_CHECK))) { + u32 seq; + u32 ack; + u32 sack; + u32 data_offs; + u32 end; + u32 left_edge; + u32 scaled_win; + u32 max_end; + + /* + * Is our sequence fully past the right hand edge of the window? + */ + seq = ntohl(tcph->seq); + if (unlikely((s32)(seq - (cm->protocol_state.tcp.max_end + 1)) > 0)) { + struct sfe_ipv6_connection *c = cm->connection; + sfe_ipv6_remove_connection(si, c); + si->exception_events[SFE_IPV6_EXCEPTION_EVENT_TCP_SEQ_EXCEEDS_RIGHT_EDGE]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("seq: %u exceeds right edge: %u\n", + seq, cm->protocol_state.tcp.max_end + 1); + sfe_ipv6_flush_connection(si, c, SFE_SYNC_REASON_FLUSH); + return 0; + } + + /* + * Check that our TCP data offset isn't too short. + */ + data_offs = tcph->doff << 2; + if (unlikely(data_offs < sizeof(struct sfe_ipv6_tcp_hdr))) { + struct sfe_ipv6_connection *c = cm->connection; + sfe_ipv6_remove_connection(si, c); + si->exception_events[SFE_IPV6_EXCEPTION_EVENT_TCP_SMALL_DATA_OFFS]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("TCP data offset: %u, too small\n", data_offs); + sfe_ipv6_flush_connection(si, c, SFE_SYNC_REASON_FLUSH); + return 0; + } + + /* + * Update ACK according to any SACK option. + */ + ack = ntohl(tcph->ack_seq); + sack = ack; + if (unlikely(!sfe_ipv6_process_tcp_option_sack(tcph, data_offs, &sack))) { + struct sfe_ipv6_connection *c = cm->connection; + sfe_ipv6_remove_connection(si, c); + si->exception_events[SFE_IPV6_EXCEPTION_EVENT_TCP_BAD_SACK]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("TCP option SACK size is wrong\n"); + sfe_ipv6_flush_connection(si, c, SFE_SYNC_REASON_FLUSH); + return 0; + } + + /* + * Check that our TCP data offset isn't past the end of the packet. + */ + data_offs += sizeof(struct sfe_ipv6_ip_hdr); + if (unlikely(len < data_offs)) { + struct sfe_ipv6_connection *c = cm->connection; + sfe_ipv6_remove_connection(si, c); + si->exception_events[SFE_IPV6_EXCEPTION_EVENT_TCP_BIG_DATA_OFFS]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("TCP data offset: %u, past end of packet: %u\n", + data_offs, len); + sfe_ipv6_flush_connection(si, c, SFE_SYNC_REASON_FLUSH); + return 0; + } + + end = seq + len - data_offs; + + /* + * Is our sequence fully before the left hand edge of the window? + */ + if (unlikely((s32)(end - (cm->protocol_state.tcp.end + - counter_cm->protocol_state.tcp.max_win - 1)) < 0)) { + struct sfe_ipv6_connection *c = cm->connection; + sfe_ipv6_remove_connection(si, c); + si->exception_events[SFE_IPV6_EXCEPTION_EVENT_TCP_SEQ_BEFORE_LEFT_EDGE]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("seq: %u before left edge: %u\n", + end, cm->protocol_state.tcp.end - counter_cm->protocol_state.tcp.max_win - 1); + sfe_ipv6_flush_connection(si, c, SFE_SYNC_REASON_FLUSH); + return 0; + } + + /* + * Are we acking data that is to the right of what has been sent? + */ + if (unlikely((s32)(sack - (counter_cm->protocol_state.tcp.end + 1)) > 0)) { + struct sfe_ipv6_connection *c = cm->connection; + sfe_ipv6_remove_connection(si, c); + si->exception_events[SFE_IPV6_EXCEPTION_EVENT_TCP_ACK_EXCEEDS_RIGHT_EDGE]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("ack: %u exceeds right edge: %u\n", + sack, counter_cm->protocol_state.tcp.end + 1); + sfe_ipv6_flush_connection(si, c, SFE_SYNC_REASON_FLUSH); + return 0; + } + + /* + * Is our ack too far before the left hand edge of the window? + */ + left_edge = counter_cm->protocol_state.tcp.end + - cm->protocol_state.tcp.max_win + - SFE_IPV6_TCP_MAX_ACK_WINDOW + - 1; + if (unlikely((s32)(sack - left_edge) < 0)) { + struct sfe_ipv6_connection *c = cm->connection; + sfe_ipv6_remove_connection(si, c); + si->exception_events[SFE_IPV6_EXCEPTION_EVENT_TCP_ACK_BEFORE_LEFT_EDGE]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("ack: %u before left edge: %u\n", sack, left_edge); + sfe_ipv6_flush_connection(si, c, SFE_SYNC_REASON_FLUSH); + return 0; + } + + /* + * Have we just seen the largest window size yet for this connection? If yes + * then we need to record the new value. + */ + scaled_win = ntohs(tcph->window) << cm->protocol_state.tcp.win_scale; + scaled_win += (sack - ack); + if (unlikely(cm->protocol_state.tcp.max_win < scaled_win)) { + cm->protocol_state.tcp.max_win = scaled_win; + } + + /* + * If our sequence and/or ack numbers have advanced then record the new state. + */ + if (likely((s32)(end - cm->protocol_state.tcp.end) >= 0)) { + cm->protocol_state.tcp.end = end; + } + + max_end = sack + scaled_win; + if (likely((s32)(max_end - counter_cm->protocol_state.tcp.max_end) >= 0)) { + counter_cm->protocol_state.tcp.max_end = max_end; + } + } + + /* + * From this point on we're good to modify the packet. + */ + + /* + * Check if skb was cloned. If it was, unshare it. Because + * the data area is going to be written in this path and we don't want to + * change the cloned skb's data section. + */ + if (unlikely(skb_cloned(skb))) { + DEBUG_TRACE("%px: skb is a cloned skb\n", skb); + skb = skb_unshare(skb, GFP_ATOMIC); + if (!skb) { + DEBUG_WARN("Failed to unshare the cloned skb\n"); + si->exception_events[SFE_IPV6_EXCEPTION_EVENT_CLONED_SKB_UNSHARE_ERROR]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + return 0; + } + + /* + * Update the iph and tcph pointers with the unshared skb's data area. + */ + iph = (struct sfe_ipv6_ip_hdr *)skb->data; + tcph = (struct sfe_ipv6_tcp_hdr *)(skb->data + ihl); + } + + /* + * Update DSCP + */ + if (unlikely(cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_DSCP_REMARK)) { + sfe_ipv6_change_dsfield(iph, cm->dscp); + } + + /* + * Decrement our hop_limit. + */ + iph->hop_limit -= 1; + + /* + * Do we have to perform translations of the source address/port? + */ + if (unlikely(cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_XLATE_SRC)) { + u16 tcp_csum; + u32 sum; + + iph->saddr = cm->xlate_src_ip[0]; + tcph->source = cm->xlate_src_port; + + /* + * Do we have a non-zero UDP checksum? If we do then we need + * to update it. + */ + tcp_csum = tcph->check; + sum = tcp_csum + cm->xlate_src_csum_adjustment; + sum = (sum & 0xffff) + (sum >> 16); + tcph->check = (u16)sum; + } + + /* + * Do we have to perform translations of the destination address/port? + */ + if (unlikely(cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_XLATE_DEST)) { + u16 tcp_csum; + u32 sum; + + iph->daddr = cm->xlate_dest_ip[0]; + tcph->dest = cm->xlate_dest_port; + + /* + * Do we have a non-zero UDP checksum? If we do then we need + * to update it. + */ + tcp_csum = tcph->check; + sum = tcp_csum + cm->xlate_dest_csum_adjustment; + sum = (sum & 0xffff) + (sum >> 16); + tcph->check = (u16)sum; + } + + /* + * Update traffic stats. + */ + cm->rx_packet_count++; + cm->rx_byte_count += len; + + /* + * If we're not already on the active list then insert ourselves at the tail + * of the current list. + */ + if (unlikely(!cm->active)) { + cm->active = true; + cm->active_prev = si->active_tail; + if (likely(si->active_tail)) { + si->active_tail->active_next = cm; + } else { + si->active_head = cm; + } + si->active_tail = cm; + } + + xmit_dev = cm->xmit_dev; + skb->dev = xmit_dev; + + /* + * Check to see if we need to write a header. + */ + if (likely(cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_WRITE_L2_HDR)) { + if (unlikely(!(cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_WRITE_FAST_ETH_HDR))) { + dev_hard_header(skb, xmit_dev, ETH_P_IPV6, + cm->xmit_dest_mac, cm->xmit_src_mac, len); + } else { + /* + * For the simple case we write this really fast. + */ + struct sfe_ipv6_eth_hdr *eth = (struct sfe_ipv6_eth_hdr *)__skb_push(skb, ETH_HLEN); + eth->h_proto = htons(ETH_P_IPV6); + eth->h_dest[0] = cm->xmit_dest_mac[0]; + eth->h_dest[1] = cm->xmit_dest_mac[1]; + eth->h_dest[2] = cm->xmit_dest_mac[2]; + eth->h_source[0] = cm->xmit_src_mac[0]; + eth->h_source[1] = cm->xmit_src_mac[1]; + eth->h_source[2] = cm->xmit_src_mac[2]; + } + } + + /* + * Update priority of skb. + */ + if (unlikely(cm->flags & SFE_IPV6_CONNECTION_MATCH_FLAG_PRIORITY_REMARK)) { + skb->priority = cm->priority; + } + + /* + * Mark outgoing packet + */ + skb->mark = cm->connection->mark; + if (skb->mark) { + DEBUG_TRACE("SKB MARK is NON ZERO %x\n", skb->mark); + } + + si->packets_forwarded++; + spin_unlock_bh(&si->lock); + + /* + * We're going to check for GSO flags when we transmit the packet so + * start fetching the necessary cache line now. + */ + prefetch(skb_shinfo(skb)); + + /* + * Mark that this packet has been fast forwarded. + */ + skb->fast_forwarded = 1; + + /* + * Send the packet on its way. + */ + dev_queue_xmit(skb); + + return 1; +} + +/* + * sfe_ipv6_recv_icmp() + * Handle ICMP packet receives. + * + * ICMP packets aren't handled as a "fast path" and always have us process them + * through the default Linux stack. What we do need to do is look for any errors + * about connections we are handling in the fast path. If we find any such + * connections then we want to flush their state so that the ICMP error path + * within Linux has all of the correct state should it need it. + */ +static int sfe_ipv6_recv_icmp(struct sfe_ipv6 *si, struct sk_buff *skb, struct net_device *dev, + unsigned int len, struct sfe_ipv6_ip_hdr *iph, unsigned int ihl) +{ + struct icmp6hdr *icmph; + struct sfe_ipv6_ip_hdr *icmp_iph; + struct sfe_ipv6_udp_hdr *icmp_udph; + struct sfe_ipv6_tcp_hdr *icmp_tcph; + struct sfe_ipv6_addr *src_ip; + struct sfe_ipv6_addr *dest_ip; + __be16 src_port; + __be16 dest_port; + struct sfe_ipv6_connection_match *cm; + struct sfe_ipv6_connection *c; + u8 next_hdr; + + /* + * Is our packet too short to contain a valid ICMP header? + */ + len -= ihl; + if (!pskb_may_pull(skb, ihl + sizeof(struct icmp6hdr))) { + spin_lock_bh(&si->lock); + si->exception_events[SFE_IPV6_EXCEPTION_EVENT_ICMP_HEADER_INCOMPLETE]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("packet too short for ICMP header\n"); + return 0; + } + + /* + * We only handle "destination unreachable" and "time exceeded" messages. + */ + icmph = (struct icmp6hdr *)(skb->data + ihl); + if ((icmph->icmp6_type != ICMPV6_DEST_UNREACH) + && (icmph->icmp6_type != ICMPV6_TIME_EXCEED)) { + spin_lock_bh(&si->lock); + si->exception_events[SFE_IPV6_EXCEPTION_EVENT_ICMP_UNHANDLED_TYPE]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("unhandled ICMP type: 0x%x\n", icmph->icmp6_type); + return 0; + } + + /* + * Do we have the full embedded IP header? + * We should have 8 bytes of next L4 header - that's enough to identify + * the connection. + */ + len -= sizeof(struct icmp6hdr); + ihl += sizeof(struct icmp6hdr); + if (!pskb_may_pull(skb, ihl + sizeof(struct sfe_ipv6_ip_hdr) + sizeof(struct sfe_ipv6_ext_hdr))) { + spin_lock_bh(&si->lock); + si->exception_events[SFE_IPV6_EXCEPTION_EVENT_ICMP_IPV6_HEADER_INCOMPLETE]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("Embedded IP header not complete\n"); + return 0; + } + + /* + * Is our embedded IP version wrong? + */ + icmp_iph = (struct sfe_ipv6_ip_hdr *)(icmph + 1); + if (unlikely(icmp_iph->version != 6)) { + spin_lock_bh(&si->lock); + si->exception_events[SFE_IPV6_EXCEPTION_EVENT_ICMP_IPV6_NON_V6]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("IP version: %u\n", icmp_iph->version); + return 0; + } + + len -= sizeof(struct sfe_ipv6_ip_hdr); + ihl += sizeof(struct sfe_ipv6_ip_hdr); + next_hdr = icmp_iph->nexthdr; + while (unlikely(sfe_ipv6_is_ext_hdr(next_hdr))) { + struct sfe_ipv6_ext_hdr *ext_hdr; + unsigned int ext_hdr_len; + + ext_hdr = (struct sfe_ipv6_ext_hdr *)(skb->data + ihl); + if (next_hdr == SFE_IPV6_EXT_HDR_FRAG) { + struct sfe_ipv6_frag_hdr *frag_hdr = (struct sfe_ipv6_frag_hdr *)ext_hdr; + unsigned int frag_off = ntohs(frag_hdr->frag_off); + + if (frag_off & SFE_IPV6_FRAG_OFFSET) { + spin_lock_bh(&si->lock); + si->exception_events[SFE_IPV6_EXCEPTION_EVENT_NON_INITIAL_FRAGMENT]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("non-initial fragment\n"); + return 0; + } + } + + ext_hdr_len = ext_hdr->hdr_len; + ext_hdr_len <<= 3; + ext_hdr_len += sizeof(struct sfe_ipv6_ext_hdr); + len -= ext_hdr_len; + ihl += ext_hdr_len; + /* + * We should have 8 bytes of next header - that's enough to identify + * the connection. + */ + if (!pskb_may_pull(skb, ihl + sizeof(struct sfe_ipv6_ext_hdr))) { + spin_lock_bh(&si->lock); + si->exception_events[SFE_IPV6_EXCEPTION_EVENT_HEADER_INCOMPLETE]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("extension header %d not completed\n", next_hdr); + return 0; + } + + next_hdr = ext_hdr->next_hdr; + } + + /* + * Handle the embedded transport layer header. + */ + switch (next_hdr) { + case IPPROTO_UDP: + icmp_udph = (struct sfe_ipv6_udp_hdr *)(skb->data + ihl); + src_port = icmp_udph->source; + dest_port = icmp_udph->dest; + break; + + case IPPROTO_TCP: + icmp_tcph = (struct sfe_ipv6_tcp_hdr *)(skb->data + ihl); + src_port = icmp_tcph->source; + dest_port = icmp_tcph->dest; + break; + + default: + spin_lock_bh(&si->lock); + si->exception_events[SFE_IPV6_EXCEPTION_EVENT_ICMP_IPV6_UNHANDLED_PROTOCOL]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("Unhandled embedded IP protocol: %u\n", next_hdr); + return 0; + } + + src_ip = &icmp_iph->saddr; + dest_ip = &icmp_iph->daddr; + + spin_lock_bh(&si->lock); + + /* + * Look for a connection match. Note that we reverse the source and destination + * here because our embedded message contains a packet that was sent in the + * opposite direction to the one in which we just received it. It will have + * been sent on the interface from which we received it though so that's still + * ok to use. + */ + cm = sfe_ipv6_find_connection_match(si, dev, icmp_iph->nexthdr, dest_ip, dest_port, src_ip, src_port); + if (unlikely(!cm)) { + si->exception_events[SFE_IPV6_EXCEPTION_EVENT_ICMP_NO_CONNECTION]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("no connection found\n"); + return 0; + } + + /* + * We found a connection so now remove it from the connection list and flush + * its state. + */ + c = cm->connection; + sfe_ipv6_remove_connection(si, c); + si->exception_events[SFE_IPV6_EXCEPTION_EVENT_ICMP_FLUSHED_CONNECTION]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + sfe_ipv6_flush_connection(si, c, SFE_SYNC_REASON_FLUSH); + return 0; +} + +/* + * sfe_ipv6_recv() + * Handle packet receives and forwaring. + * + * Returns 1 if the packet is forwarded or 0 if it isn't. + */ +int sfe_ipv6_recv(struct net_device *dev, struct sk_buff *skb) +{ + struct sfe_ipv6 *si = &__si6; + unsigned int len; + unsigned int payload_len; + unsigned int ihl = sizeof(struct sfe_ipv6_ip_hdr); + bool flush_on_find = false; + struct sfe_ipv6_ip_hdr *iph; + u8 next_hdr; + + /* + * Check that we have space for an IP header and an uplayer header here. + */ + len = skb->len; + if (!pskb_may_pull(skb, ihl + sizeof(struct sfe_ipv6_ext_hdr))) { + spin_lock_bh(&si->lock); + si->exception_events[SFE_IPV6_EXCEPTION_EVENT_HEADER_INCOMPLETE]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("len: %u is too short\n", len); + return 0; + } + + /* + * Is our IP version wrong? + */ + iph = (struct sfe_ipv6_ip_hdr *)skb->data; + if (unlikely(iph->version != 6)) { + spin_lock_bh(&si->lock); + si->exception_events[SFE_IPV6_EXCEPTION_EVENT_NON_V6]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("IP version: %u\n", iph->version); + return 0; + } + + /* + * Does our datagram fit inside the skb? + */ + payload_len = ntohs(iph->payload_len); + if (unlikely(payload_len > (len - ihl))) { + spin_lock_bh(&si->lock); + si->exception_events[SFE_IPV6_EXCEPTION_EVENT_DATAGRAM_INCOMPLETE]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("payload_len: %u, exceeds len: %u\n", payload_len, (len - (unsigned int)sizeof(struct sfe_ipv6_ip_hdr))); + return 0; + } + + next_hdr = iph->nexthdr; + while (unlikely(sfe_ipv6_is_ext_hdr(next_hdr))) { + struct sfe_ipv6_ext_hdr *ext_hdr; + unsigned int ext_hdr_len; + + ext_hdr = (struct sfe_ipv6_ext_hdr *)(skb->data + ihl); + if (next_hdr == SFE_IPV6_EXT_HDR_FRAG) { + struct sfe_ipv6_frag_hdr *frag_hdr = (struct sfe_ipv6_frag_hdr *)ext_hdr; + unsigned int frag_off = ntohs(frag_hdr->frag_off); + + if (frag_off & SFE_IPV6_FRAG_OFFSET) { + spin_lock_bh(&si->lock); + si->exception_events[SFE_IPV6_EXCEPTION_EVENT_NON_INITIAL_FRAGMENT]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("non-initial fragment\n"); + return 0; + } + } + + ext_hdr_len = ext_hdr->hdr_len; + ext_hdr_len <<= 3; + ext_hdr_len += sizeof(struct sfe_ipv6_ext_hdr); + ihl += ext_hdr_len; + if (!pskb_may_pull(skb, ihl + sizeof(struct sfe_ipv6_ext_hdr))) { + spin_lock_bh(&si->lock); + si->exception_events[SFE_IPV6_EXCEPTION_EVENT_HEADER_INCOMPLETE]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("extension header %d not completed\n", next_hdr); + return 0; + } + + flush_on_find = true; + next_hdr = ext_hdr->next_hdr; + } + + if (IPPROTO_UDP == next_hdr) { + return sfe_ipv6_recv_udp(si, skb, dev, len, iph, ihl, flush_on_find); + } + + if (IPPROTO_TCP == next_hdr) { + return sfe_ipv6_recv_tcp(si, skb, dev, len, iph, ihl, flush_on_find); + } + + if (IPPROTO_ICMPV6 == next_hdr) { + return sfe_ipv6_recv_icmp(si, skb, dev, len, iph, ihl); + } + + spin_lock_bh(&si->lock); + si->exception_events[SFE_IPV6_EXCEPTION_EVENT_UNHANDLED_PROTOCOL]++; + si->packets_not_forwarded++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("not UDP, TCP or ICMP: %u\n", next_hdr); + return 0; +} + +/* + * sfe_ipv6_update_tcp_state() + * update TCP window variables. + */ +static void +sfe_ipv6_update_tcp_state(struct sfe_ipv6_connection *c, + struct sfe_connection_create *sic) +{ + struct sfe_ipv6_connection_match *orig_cm; + struct sfe_ipv6_connection_match *repl_cm; + struct sfe_ipv6_tcp_connection_match *orig_tcp; + struct sfe_ipv6_tcp_connection_match *repl_tcp; + + orig_cm = c->original_match; + repl_cm = c->reply_match; + orig_tcp = &orig_cm->protocol_state.tcp; + repl_tcp = &repl_cm->protocol_state.tcp; + + /* update orig */ + if (orig_tcp->max_win < sic->src_td_max_window) { + orig_tcp->max_win = sic->src_td_max_window; + } + if ((s32)(orig_tcp->end - sic->src_td_end) < 0) { + orig_tcp->end = sic->src_td_end; + } + if ((s32)(orig_tcp->max_end - sic->src_td_max_end) < 0) { + orig_tcp->max_end = sic->src_td_max_end; + } + + /* update reply */ + if (repl_tcp->max_win < sic->dest_td_max_window) { + repl_tcp->max_win = sic->dest_td_max_window; + } + if ((s32)(repl_tcp->end - sic->dest_td_end) < 0) { + repl_tcp->end = sic->dest_td_end; + } + if ((s32)(repl_tcp->max_end - sic->dest_td_max_end) < 0) { + repl_tcp->max_end = sic->dest_td_max_end; + } + + /* update match flags */ + orig_cm->flags &= ~SFE_IPV6_CONNECTION_MATCH_FLAG_NO_SEQ_CHECK; + repl_cm->flags &= ~SFE_IPV6_CONNECTION_MATCH_FLAG_NO_SEQ_CHECK; + if (sic->flags & SFE_CREATE_FLAG_NO_SEQ_CHECK) { + orig_cm->flags |= SFE_IPV6_CONNECTION_MATCH_FLAG_NO_SEQ_CHECK; + repl_cm->flags |= SFE_IPV6_CONNECTION_MATCH_FLAG_NO_SEQ_CHECK; + } +} + +/* + * sfe_ipv6_update_protocol_state() + * update protocol specified state machine. + */ +static void +sfe_ipv6_update_protocol_state(struct sfe_ipv6_connection *c, + struct sfe_connection_create *sic) +{ + switch (sic->protocol) { + case IPPROTO_TCP: + sfe_ipv6_update_tcp_state(c, sic); + break; + } +} + +/* + * sfe_ipv6_update_rule() + * update forwarding rule after rule is created. + */ +void sfe_ipv6_update_rule(struct sfe_connection_create *sic) +{ + struct sfe_ipv6_connection *c; + struct sfe_ipv6 *si = &__si6; + + spin_lock_bh(&si->lock); + + c = sfe_ipv6_find_connection(si, + sic->protocol, + sic->src_ip.ip6, + sic->src_port, + sic->dest_ip.ip6, + sic->dest_port); + if (c != NULL) { + sfe_ipv6_update_protocol_state(c, sic); + } + + spin_unlock_bh(&si->lock); +} + +/* + * sfe_ipv6_create_rule() + * Create a forwarding rule. + */ +int sfe_ipv6_create_rule(struct sfe_connection_create *sic) +{ + struct sfe_ipv6 *si = &__si6; + struct sfe_ipv6_connection *c; + struct sfe_ipv6_connection_match *original_cm; + struct sfe_ipv6_connection_match *reply_cm; + struct net_device *dest_dev; + struct net_device *src_dev; + + dest_dev = sic->dest_dev; + src_dev = sic->src_dev; + + if (unlikely((dest_dev->reg_state != NETREG_REGISTERED) || + (src_dev->reg_state != NETREG_REGISTERED))) { + return -EINVAL; + } + + spin_lock_bh(&si->lock); + si->connection_create_requests++; + + /* + * Check to see if there is already a flow that matches the rule we're + * trying to create. If there is then we can't create a new one. + */ + c = sfe_ipv6_find_connection(si, + sic->protocol, + sic->src_ip.ip6, + sic->src_port, + sic->dest_ip.ip6, + sic->dest_port); + if (c != NULL) { + si->connection_create_collisions++; + + /* + * If we already have the flow then it's likely that this + * request to create the connection rule contains more + * up-to-date information. Check and update accordingly. + */ + sfe_ipv6_update_protocol_state(c, sic); + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("connection already exists - mark: %08x, p: %d\n" + " s: %s:%pxM:%pI6:%u, d: %s:%pxM:%pI6:%u\n", + sic->mark, sic->protocol, + sic->src_dev->name, sic->src_mac, sic->src_ip.ip6, ntohs(sic->src_port), + sic->dest_dev->name, sic->dest_mac, sic->dest_ip.ip6, ntohs(sic->dest_port)); + return -EADDRINUSE; + } + + /* + * Allocate the various connection tracking objects. + */ + c = (struct sfe_ipv6_connection *)kmalloc(sizeof(struct sfe_ipv6_connection), GFP_ATOMIC); + if (unlikely(!c)) { + spin_unlock_bh(&si->lock); + return -ENOMEM; + } + + original_cm = (struct sfe_ipv6_connection_match *)kmalloc(sizeof(struct sfe_ipv6_connection_match), GFP_ATOMIC); + if (unlikely(!original_cm)) { + spin_unlock_bh(&si->lock); + kfree(c); + return -ENOMEM; + } + + reply_cm = (struct sfe_ipv6_connection_match *)kmalloc(sizeof(struct sfe_ipv6_connection_match), GFP_ATOMIC); + if (unlikely(!reply_cm)) { + spin_unlock_bh(&si->lock); + kfree(original_cm); + kfree(c); + return -ENOMEM; + } + + /* + * Fill in the "original" direction connection matching object. + * Note that the transmit MAC address is "dest_mac_xlate" because + * we always know both ends of a connection by their translated + * addresses and not their public addresses. + */ + original_cm->match_dev = src_dev; + original_cm->match_protocol = sic->protocol; + original_cm->match_src_ip[0] = sic->src_ip.ip6[0]; + original_cm->match_src_port = sic->src_port; + original_cm->match_dest_ip[0] = sic->dest_ip.ip6[0]; + original_cm->match_dest_port = sic->dest_port; + original_cm->xlate_src_ip[0] = sic->src_ip_xlate.ip6[0]; + original_cm->xlate_src_port = sic->src_port_xlate; + original_cm->xlate_dest_ip[0] = sic->dest_ip_xlate.ip6[0]; + original_cm->xlate_dest_port = sic->dest_port_xlate; + original_cm->rx_packet_count = 0; + original_cm->rx_packet_count64 = 0; + original_cm->rx_byte_count = 0; + original_cm->rx_byte_count64 = 0; + original_cm->xmit_dev = dest_dev; + original_cm->xmit_dev_mtu = sic->dest_mtu; + memcpy(original_cm->xmit_src_mac, dest_dev->dev_addr, ETH_ALEN); + memcpy(original_cm->xmit_dest_mac, sic->dest_mac_xlate, ETH_ALEN); + original_cm->connection = c; + original_cm->counter_match = reply_cm; + original_cm->flags = 0; + if (sic->flags & SFE_CREATE_FLAG_REMARK_PRIORITY) { + original_cm->priority = sic->src_priority; + original_cm->flags |= SFE_IPV6_CONNECTION_MATCH_FLAG_PRIORITY_REMARK; + } + if (sic->flags & SFE_CREATE_FLAG_REMARK_DSCP) { + original_cm->dscp = sic->src_dscp << SFE_IPV6_DSCP_SHIFT; + original_cm->flags |= SFE_IPV6_CONNECTION_MATCH_FLAG_DSCP_REMARK; + } +#ifdef CONFIG_NF_FLOW_COOKIE + original_cm->flow_cookie = 0; +#endif +#ifdef CONFIG_XFRM + original_cm->flow_accel = sic->original_accel; +#endif + original_cm->active_next = NULL; + original_cm->active_prev = NULL; + original_cm->active = false; + + /* + * For PPP links we don't write an L2 header. For everything else we do. + */ + if (!(dest_dev->flags & IFF_POINTOPOINT)) { + original_cm->flags |= SFE_IPV6_CONNECTION_MATCH_FLAG_WRITE_L2_HDR; + + /* + * If our dev writes Ethernet headers then we can write a really fast + * version. + */ + if (dest_dev->header_ops) { + if (dest_dev->header_ops->create == eth_header) { + original_cm->flags |= SFE_IPV6_CONNECTION_MATCH_FLAG_WRITE_FAST_ETH_HDR; + } + } + } + + /* + * Fill in the "reply" direction connection matching object. + */ + reply_cm->match_dev = dest_dev; + reply_cm->match_protocol = sic->protocol; + reply_cm->match_src_ip[0] = sic->dest_ip_xlate.ip6[0]; + reply_cm->match_src_port = sic->dest_port_xlate; + reply_cm->match_dest_ip[0] = sic->src_ip_xlate.ip6[0]; + reply_cm->match_dest_port = sic->src_port_xlate; + reply_cm->xlate_src_ip[0] = sic->dest_ip.ip6[0]; + reply_cm->xlate_src_port = sic->dest_port; + reply_cm->xlate_dest_ip[0] = sic->src_ip.ip6[0]; + reply_cm->xlate_dest_port = sic->src_port; + reply_cm->rx_packet_count = 0; + reply_cm->rx_packet_count64 = 0; + reply_cm->rx_byte_count = 0; + reply_cm->rx_byte_count64 = 0; + reply_cm->xmit_dev = src_dev; + reply_cm->xmit_dev_mtu = sic->src_mtu; + memcpy(reply_cm->xmit_src_mac, src_dev->dev_addr, ETH_ALEN); + memcpy(reply_cm->xmit_dest_mac, sic->src_mac, ETH_ALEN); + reply_cm->connection = c; + reply_cm->counter_match = original_cm; + reply_cm->flags = 0; + if (sic->flags & SFE_CREATE_FLAG_REMARK_PRIORITY) { + reply_cm->priority = sic->dest_priority; + reply_cm->flags |= SFE_IPV6_CONNECTION_MATCH_FLAG_PRIORITY_REMARK; + } + if (sic->flags & SFE_CREATE_FLAG_REMARK_DSCP) { + reply_cm->dscp = sic->dest_dscp << SFE_IPV6_DSCP_SHIFT; + reply_cm->flags |= SFE_IPV6_CONNECTION_MATCH_FLAG_DSCP_REMARK; + } +#ifdef CONFIG_NF_FLOW_COOKIE + reply_cm->flow_cookie = 0; +#endif +#ifdef CONFIG_XFRM + reply_cm->flow_accel = sic->reply_accel; +#endif + reply_cm->active_next = NULL; + reply_cm->active_prev = NULL; + reply_cm->active = false; + + /* + * For PPP links we don't write an L2 header. For everything else we do. + */ + if (!(src_dev->flags & IFF_POINTOPOINT)) { + reply_cm->flags |= SFE_IPV6_CONNECTION_MATCH_FLAG_WRITE_L2_HDR; + + /* + * If our dev writes Ethernet headers then we can write a really fast + * version. + */ + if (src_dev->header_ops) { + if (src_dev->header_ops->create == eth_header) { + reply_cm->flags |= SFE_IPV6_CONNECTION_MATCH_FLAG_WRITE_FAST_ETH_HDR; + } + } + } + + + if (!sfe_ipv6_addr_equal(sic->dest_ip.ip6, sic->dest_ip_xlate.ip6) || sic->dest_port != sic->dest_port_xlate) { + original_cm->flags |= SFE_IPV6_CONNECTION_MATCH_FLAG_XLATE_DEST; + reply_cm->flags |= SFE_IPV6_CONNECTION_MATCH_FLAG_XLATE_SRC; + } + + if (!sfe_ipv6_addr_equal(sic->src_ip.ip6, sic->src_ip_xlate.ip6) || sic->src_port != sic->src_port_xlate) { + original_cm->flags |= SFE_IPV6_CONNECTION_MATCH_FLAG_XLATE_SRC; + reply_cm->flags |= SFE_IPV6_CONNECTION_MATCH_FLAG_XLATE_DEST; + } + + c->protocol = sic->protocol; + c->src_ip[0] = sic->src_ip.ip6[0]; + c->src_ip_xlate[0] = sic->src_ip_xlate.ip6[0]; + c->src_port = sic->src_port; + c->src_port_xlate = sic->src_port_xlate; + c->original_dev = src_dev; + c->original_match = original_cm; + c->dest_ip[0] = sic->dest_ip.ip6[0]; + c->dest_ip_xlate[0] = sic->dest_ip_xlate.ip6[0]; + c->dest_port = sic->dest_port; + c->dest_port_xlate = sic->dest_port_xlate; + c->reply_dev = dest_dev; + c->reply_match = reply_cm; + c->mark = sic->mark; + c->debug_read_seq = 0; + c->last_sync_jiffies = get_jiffies_64(); + + /* + * Take hold of our source and dest devices for the duration of the connection. + */ + dev_hold(c->original_dev); + dev_hold(c->reply_dev); + + /* + * Initialize the protocol-specific information that we track. + */ + switch (sic->protocol) { + case IPPROTO_TCP: + original_cm->protocol_state.tcp.win_scale = sic->src_td_window_scale; + original_cm->protocol_state.tcp.max_win = sic->src_td_max_window ? sic->src_td_max_window : 1; + original_cm->protocol_state.tcp.end = sic->src_td_end; + original_cm->protocol_state.tcp.max_end = sic->src_td_max_end; + reply_cm->protocol_state.tcp.win_scale = sic->dest_td_window_scale; + reply_cm->protocol_state.tcp.max_win = sic->dest_td_max_window ? sic->dest_td_max_window : 1; + reply_cm->protocol_state.tcp.end = sic->dest_td_end; + reply_cm->protocol_state.tcp.max_end = sic->dest_td_max_end; + if (sic->flags & SFE_CREATE_FLAG_NO_SEQ_CHECK) { + original_cm->flags |= SFE_IPV6_CONNECTION_MATCH_FLAG_NO_SEQ_CHECK; + reply_cm->flags |= SFE_IPV6_CONNECTION_MATCH_FLAG_NO_SEQ_CHECK; + } + break; + } + + sfe_ipv6_connection_match_compute_translations(original_cm); + sfe_ipv6_connection_match_compute_translations(reply_cm); + sfe_ipv6_insert_connection(si, c); + + spin_unlock_bh(&si->lock); + + /* + * We have everything we need! + */ + DEBUG_INFO("new connection - mark: %08x, p: %d\n" + " s: %s:%pxM(%pxM):%pI6(%pI6):%u(%u)\n" + " d: %s:%pxM(%pxM):%pI6(%pI6):%u(%u)\n", + sic->mark, sic->protocol, + sic->src_dev->name, sic->src_mac, sic->src_mac_xlate, + sic->src_ip.ip6, sic->src_ip_xlate.ip6, ntohs(sic->src_port), ntohs(sic->src_port_xlate), + dest_dev->name, sic->dest_mac, sic->dest_mac_xlate, + sic->dest_ip.ip6, sic->dest_ip_xlate.ip6, ntohs(sic->dest_port), ntohs(sic->dest_port_xlate)); + + return 0; +} + +/* + * sfe_ipv6_destroy_rule() + * Destroy a forwarding rule. + */ +void sfe_ipv6_destroy_rule(struct sfe_connection_destroy *sid) +{ + struct sfe_ipv6 *si = &__si6; + struct sfe_ipv6_connection *c; + + spin_lock_bh(&si->lock); + si->connection_destroy_requests++; + + /* + * Check to see if we have a flow that matches the rule we're trying + * to destroy. If there isn't then we can't destroy it. + */ + c = sfe_ipv6_find_connection(si, sid->protocol, sid->src_ip.ip6, sid->src_port, + sid->dest_ip.ip6, sid->dest_port); + if (!c) { + si->connection_destroy_misses++; + spin_unlock_bh(&si->lock); + + DEBUG_TRACE("connection does not exist - p: %d, s: %pI6:%u, d: %pI6:%u\n", + sid->protocol, sid->src_ip.ip6, ntohs(sid->src_port), + sid->dest_ip.ip6, ntohs(sid->dest_port)); + return; + } + + /* + * Remove our connection details from the hash tables. + */ + sfe_ipv6_remove_connection(si, c); + spin_unlock_bh(&si->lock); + + sfe_ipv6_flush_connection(si, c, SFE_SYNC_REASON_DESTROY); + + DEBUG_INFO("connection destroyed - p: %d, s: %pI6:%u, d: %pI6:%u\n", + sid->protocol, sid->src_ip.ip6, ntohs(sid->src_port), + sid->dest_ip.ip6, ntohs(sid->dest_port)); +} + +/* + * sfe_ipv6_register_sync_rule_callback() + * Register a callback for rule synchronization. + */ +void sfe_ipv6_register_sync_rule_callback(sfe_sync_rule_callback_t sync_rule_callback) +{ + struct sfe_ipv6 *si = &__si6; + + spin_lock_bh(&si->lock); + rcu_assign_pointer(si->sync_rule_callback, sync_rule_callback); + spin_unlock_bh(&si->lock); +} + +/* + * sfe_ipv6_get_debug_dev() + */ +static ssize_t sfe_ipv6_get_debug_dev(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct sfe_ipv6 *si = &__si6; + ssize_t count; + int num; + + spin_lock_bh(&si->lock); + num = si->debug_dev; + spin_unlock_bh(&si->lock); + + count = snprintf(buf, (ssize_t)PAGE_SIZE, "%d\n", num); + return count; +} + +/* + * sfe_ipv6_destroy_all_rules_for_dev() + * Destroy all connections that match a particular device. + * + * If we pass dev as NULL then this destroys all connections. + */ +void sfe_ipv6_destroy_all_rules_for_dev(struct net_device *dev) +{ + struct sfe_ipv6 *si = &__si6; + struct sfe_ipv6_connection *c; + +another_round: + spin_lock_bh(&si->lock); + + for (c = si->all_connections_head; c; c = c->all_connections_next) { + /* + * Does this connection relate to the device we are destroying? + */ + if (!dev + || (dev == c->original_dev) + || (dev == c->reply_dev)) { + break; + } + } + + if (c) { + sfe_ipv6_remove_connection(si, c); + } + + spin_unlock_bh(&si->lock); + + if (c) { + sfe_ipv6_flush_connection(si, c, SFE_SYNC_REASON_DESTROY); + goto another_round; + } +} + +/* + * sfe_ipv6_periodic_sync() + */ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 15, 0)) +static void sfe_ipv6_periodic_sync(unsigned long arg) +#else +static void sfe_ipv6_periodic_sync(struct timer_list *tl) +#endif +{ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 15, 0)) + struct sfe_ipv6 *si = (struct sfe_ipv6 *)arg; +#else + struct sfe_ipv6 *si = from_timer(si, tl, timer); +#endif + u64 now_jiffies; + int quota; + sfe_sync_rule_callback_t sync_rule_callback; + + now_jiffies = get_jiffies_64(); + + rcu_read_lock(); + sync_rule_callback = rcu_dereference(si->sync_rule_callback); + if (!sync_rule_callback) { + rcu_read_unlock(); + goto done; + } + + spin_lock_bh(&si->lock); + sfe_ipv6_update_summary_stats(si); + + /* + * Get an estimate of the number of connections to parse in this sync. + */ + quota = (si->num_connections + 63) / 64; + + /* + * Walk the "active" list and sync the connection state. + */ + while (quota--) { + struct sfe_ipv6_connection_match *cm; + struct sfe_ipv6_connection_match *counter_cm; + struct sfe_ipv6_connection *c; + struct sfe_connection_sync sis; + + cm = si->active_head; + if (!cm) { + break; + } + + /* + * There's a possibility that our counter match is in the active list too. + * If it is then remove it. + */ + counter_cm = cm->counter_match; + if (counter_cm->active) { + counter_cm->active = false; + + /* + * We must have a connection preceding this counter match + * because that's the one that got us to this point, so we don't have + * to worry about removing the head of the list. + */ + counter_cm->active_prev->active_next = counter_cm->active_next; + + if (likely(counter_cm->active_next)) { + counter_cm->active_next->active_prev = counter_cm->active_prev; + } else { + si->active_tail = counter_cm->active_prev; + } + + counter_cm->active_next = NULL; + counter_cm->active_prev = NULL; + } + + /* + * Now remove the head of the active scan list. + */ + cm->active = false; + si->active_head = cm->active_next; + if (likely(cm->active_next)) { + cm->active_next->active_prev = NULL; + } else { + si->active_tail = NULL; + } + cm->active_next = NULL; + + /* + * Sync the connection state. + */ + c = cm->connection; + sfe_ipv6_gen_sync_connection(si, c, &sis, SFE_SYNC_REASON_STATS, now_jiffies); + + /* + * We don't want to be holding the lock when we sync! + */ + spin_unlock_bh(&si->lock); + sync_rule_callback(&sis); + spin_lock_bh(&si->lock); + } + + spin_unlock_bh(&si->lock); + rcu_read_unlock(); + +done: + mod_timer(&si->timer, jiffies + ((HZ + 99) / 100)); +} + +/* + * sfe_ipv6_debug_dev_read_start() + * Generate part of the XML output. + */ +static bool sfe_ipv6_debug_dev_read_start(struct sfe_ipv6 *si, char *buffer, char *msg, size_t *length, + int *total_read, struct sfe_ipv6_debug_xml_write_state *ws) +{ + int bytes_read; + + si->debug_read_seq++; + + bytes_read = snprintf(msg, CHAR_DEV_MSG_SIZE, "\n"); + if (copy_to_user(buffer + *total_read, msg, CHAR_DEV_MSG_SIZE)) { + return false; + } + + *length -= bytes_read; + *total_read += bytes_read; + + ws->state++; + return true; +} + +/* + * sfe_ipv6_debug_dev_read_connections_start() + * Generate part of the XML output. + */ +static bool sfe_ipv6_debug_dev_read_connections_start(struct sfe_ipv6 *si, char *buffer, char *msg, size_t *length, + int *total_read, struct sfe_ipv6_debug_xml_write_state *ws) +{ + int bytes_read; + + bytes_read = snprintf(msg, CHAR_DEV_MSG_SIZE, "\t\n"); + if (copy_to_user(buffer + *total_read, msg, CHAR_DEV_MSG_SIZE)) { + return false; + } + + *length -= bytes_read; + *total_read += bytes_read; + + ws->state++; + return true; +} + +/* + * sfe_ipv6_debug_dev_read_connections_connection() + * Generate part of the XML output. + */ +static bool sfe_ipv6_debug_dev_read_connections_connection(struct sfe_ipv6 *si, char *buffer, char *msg, size_t *length, + int *total_read, struct sfe_ipv6_debug_xml_write_state *ws) +{ + struct sfe_ipv6_connection *c; + struct sfe_ipv6_connection_match *original_cm; + struct sfe_ipv6_connection_match *reply_cm; + int bytes_read; + int protocol; + struct net_device *src_dev; + struct sfe_ipv6_addr src_ip; + struct sfe_ipv6_addr src_ip_xlate; + __be16 src_port; + __be16 src_port_xlate; + u64 src_rx_packets; + u64 src_rx_bytes; + struct net_device *dest_dev; + struct sfe_ipv6_addr dest_ip; + struct sfe_ipv6_addr dest_ip_xlate; + __be16 dest_port; + __be16 dest_port_xlate; + u64 dest_rx_packets; + u64 dest_rx_bytes; + u64 last_sync_jiffies; + u32 mark, src_priority, dest_priority, src_dscp, dest_dscp; +#ifdef CONFIG_NF_FLOW_COOKIE + int src_flow_cookie, dst_flow_cookie; +#endif + + spin_lock_bh(&si->lock); + + for (c = si->all_connections_head; c; c = c->all_connections_next) { + if (c->debug_read_seq < si->debug_read_seq) { + c->debug_read_seq = si->debug_read_seq; + break; + } + } + + /* + * If there were no connections then move to the next state. + */ + if (!c) { + spin_unlock_bh(&si->lock); + ws->state++; + return true; + } + + original_cm = c->original_match; + reply_cm = c->reply_match; + + protocol = c->protocol; + src_dev = c->original_dev; + src_ip = c->src_ip[0]; + src_ip_xlate = c->src_ip_xlate[0]; + src_port = c->src_port; + src_port_xlate = c->src_port_xlate; + src_priority = original_cm->priority; + src_dscp = original_cm->dscp >> SFE_IPV6_DSCP_SHIFT; + + sfe_ipv6_connection_match_update_summary_stats(original_cm); + sfe_ipv6_connection_match_update_summary_stats(reply_cm); + + src_rx_packets = original_cm->rx_packet_count64; + src_rx_bytes = original_cm->rx_byte_count64; + dest_dev = c->reply_dev; + dest_ip = c->dest_ip[0]; + dest_ip_xlate = c->dest_ip_xlate[0]; + dest_port = c->dest_port; + dest_port_xlate = c->dest_port_xlate; + dest_priority = reply_cm->priority; + dest_dscp = reply_cm->dscp >> SFE_IPV6_DSCP_SHIFT; + dest_rx_packets = reply_cm->rx_packet_count64; + dest_rx_bytes = reply_cm->rx_byte_count64; + last_sync_jiffies = get_jiffies_64() - c->last_sync_jiffies; + mark = c->mark; +#ifdef CONFIG_NF_FLOW_COOKIE + src_flow_cookie = original_cm->flow_cookie; + dst_flow_cookie = reply_cm->flow_cookie; +#endif + spin_unlock_bh(&si->lock); + + bytes_read = snprintf(msg, CHAR_DEV_MSG_SIZE, "\t\t\n", + protocol, + src_dev->name, + &src_ip, &src_ip_xlate, + ntohs(src_port), ntohs(src_port_xlate), + src_priority, src_dscp, + src_rx_packets, src_rx_bytes, + dest_dev->name, + &dest_ip, &dest_ip_xlate, + ntohs(dest_port), ntohs(dest_port_xlate), + dest_priority, dest_dscp, + dest_rx_packets, dest_rx_bytes, +#ifdef CONFIG_NF_FLOW_COOKIE + src_flow_cookie, dst_flow_cookie, +#endif + last_sync_jiffies, mark); + + if (copy_to_user(buffer + *total_read, msg, CHAR_DEV_MSG_SIZE)) { + return false; + } + + *length -= bytes_read; + *total_read += bytes_read; + + return true; +} + +/* + * sfe_ipv6_debug_dev_read_connections_end() + * Generate part of the XML output. + */ +static bool sfe_ipv6_debug_dev_read_connections_end(struct sfe_ipv6 *si, char *buffer, char *msg, size_t *length, + int *total_read, struct sfe_ipv6_debug_xml_write_state *ws) +{ + int bytes_read; + + bytes_read = snprintf(msg, CHAR_DEV_MSG_SIZE, "\t\n"); + if (copy_to_user(buffer + *total_read, msg, CHAR_DEV_MSG_SIZE)) { + return false; + } + + *length -= bytes_read; + *total_read += bytes_read; + + ws->state++; + return true; +} + +/* + * sfe_ipv6_debug_dev_read_exceptions_start() + * Generate part of the XML output. + */ +static bool sfe_ipv6_debug_dev_read_exceptions_start(struct sfe_ipv6 *si, char *buffer, char *msg, size_t *length, + int *total_read, struct sfe_ipv6_debug_xml_write_state *ws) +{ + int bytes_read; + + bytes_read = snprintf(msg, CHAR_DEV_MSG_SIZE, "\t\n"); + if (copy_to_user(buffer + *total_read, msg, CHAR_DEV_MSG_SIZE)) { + return false; + } + + *length -= bytes_read; + *total_read += bytes_read; + + ws->state++; + return true; +} + +/* + * sfe_ipv6_debug_dev_read_exceptions_exception() + * Generate part of the XML output. + */ +static bool sfe_ipv6_debug_dev_read_exceptions_exception(struct sfe_ipv6 *si, char *buffer, char *msg, size_t *length, + int *total_read, struct sfe_ipv6_debug_xml_write_state *ws) +{ + u64 ct; + + spin_lock_bh(&si->lock); + ct = si->exception_events64[ws->iter_exception]; + spin_unlock_bh(&si->lock); + + if (ct) { + int bytes_read; + + bytes_read = snprintf(msg, CHAR_DEV_MSG_SIZE, + "\t\t\n", + sfe_ipv6_exception_events_string[ws->iter_exception], + ct); + if (copy_to_user(buffer + *total_read, msg, CHAR_DEV_MSG_SIZE)) { + return false; + } + + *length -= bytes_read; + *total_read += bytes_read; + } + + ws->iter_exception++; + if (ws->iter_exception >= SFE_IPV6_EXCEPTION_EVENT_LAST) { + ws->iter_exception = 0; + ws->state++; + } + + return true; +} + +/* + * sfe_ipv6_debug_dev_read_exceptions_end() + * Generate part of the XML output. + */ +static bool sfe_ipv6_debug_dev_read_exceptions_end(struct sfe_ipv6 *si, char *buffer, char *msg, size_t *length, + int *total_read, struct sfe_ipv6_debug_xml_write_state *ws) +{ + int bytes_read; + + bytes_read = snprintf(msg, CHAR_DEV_MSG_SIZE, "\t\n"); + if (copy_to_user(buffer + *total_read, msg, CHAR_DEV_MSG_SIZE)) { + return false; + } + + *length -= bytes_read; + *total_read += bytes_read; + + ws->state++; + return true; +} + +/* + * sfe_ipv6_debug_dev_read_stats() + * Generate part of the XML output. + */ +static bool sfe_ipv6_debug_dev_read_stats(struct sfe_ipv6 *si, char *buffer, char *msg, size_t *length, + int *total_read, struct sfe_ipv6_debug_xml_write_state *ws) +{ + int bytes_read; + unsigned int num_connections; + u64 packets_forwarded; + u64 packets_not_forwarded; + u64 connection_create_requests; + u64 connection_create_collisions; + u64 connection_destroy_requests; + u64 connection_destroy_misses; + u64 connection_flushes; + u64 connection_match_hash_hits; + u64 connection_match_hash_reorders; + + spin_lock_bh(&si->lock); + sfe_ipv6_update_summary_stats(si); + + num_connections = si->num_connections; + packets_forwarded = si->packets_forwarded64; + packets_not_forwarded = si->packets_not_forwarded64; + connection_create_requests = si->connection_create_requests64; + connection_create_collisions = si->connection_create_collisions64; + connection_destroy_requests = si->connection_destroy_requests64; + connection_destroy_misses = si->connection_destroy_misses64; + connection_flushes = si->connection_flushes64; + connection_match_hash_hits = si->connection_match_hash_hits64; + connection_match_hash_reorders = si->connection_match_hash_reorders64; + spin_unlock_bh(&si->lock); + + bytes_read = snprintf(msg, CHAR_DEV_MSG_SIZE, "\t\n", + num_connections, + packets_forwarded, + packets_not_forwarded, + connection_create_requests, + connection_create_collisions, + connection_destroy_requests, + connection_destroy_misses, + connection_flushes, + connection_match_hash_hits, + connection_match_hash_reorders); + if (copy_to_user(buffer + *total_read, msg, CHAR_DEV_MSG_SIZE)) { + return false; + } + + *length -= bytes_read; + *total_read += bytes_read; + + ws->state++; + return true; +} + +/* + * sfe_ipv6_debug_dev_read_end() + * Generate part of the XML output. + */ +static bool sfe_ipv6_debug_dev_read_end(struct sfe_ipv6 *si, char *buffer, char *msg, size_t *length, + int *total_read, struct sfe_ipv6_debug_xml_write_state *ws) +{ + int bytes_read; + + bytes_read = snprintf(msg, CHAR_DEV_MSG_SIZE, "\n"); + if (copy_to_user(buffer + *total_read, msg, CHAR_DEV_MSG_SIZE)) { + return false; + } + + *length -= bytes_read; + *total_read += bytes_read; + + ws->state++; + return true; +} + +/* + * Array of write functions that write various XML elements that correspond to + * our XML output state machine. + */ +static sfe_ipv6_debug_xml_write_method_t sfe_ipv6_debug_xml_write_methods[SFE_IPV6_DEBUG_XML_STATE_DONE] = { + sfe_ipv6_debug_dev_read_start, + sfe_ipv6_debug_dev_read_connections_start, + sfe_ipv6_debug_dev_read_connections_connection, + sfe_ipv6_debug_dev_read_connections_end, + sfe_ipv6_debug_dev_read_exceptions_start, + sfe_ipv6_debug_dev_read_exceptions_exception, + sfe_ipv6_debug_dev_read_exceptions_end, + sfe_ipv6_debug_dev_read_stats, + sfe_ipv6_debug_dev_read_end, +}; + +/* + * sfe_ipv6_debug_dev_read() + * Send info to userspace upon read request from user + */ +static ssize_t sfe_ipv6_debug_dev_read(struct file *filp, char *buffer, size_t length, loff_t *offset) +{ + char msg[CHAR_DEV_MSG_SIZE]; + int total_read = 0; + struct sfe_ipv6_debug_xml_write_state *ws; + struct sfe_ipv6 *si = &__si6; + + ws = (struct sfe_ipv6_debug_xml_write_state *)filp->private_data; + while ((ws->state != SFE_IPV6_DEBUG_XML_STATE_DONE) && (length > CHAR_DEV_MSG_SIZE)) { + if ((sfe_ipv6_debug_xml_write_methods[ws->state])(si, buffer, msg, &length, &total_read, ws)) { + continue; + } + } + + return total_read; +} + +/* + * sfe_ipv6_debug_dev_write() + * Write to char device resets some stats + */ +static ssize_t sfe_ipv6_debug_dev_write(struct file *filp, const char *buffer, size_t length, loff_t *offset) +{ + struct sfe_ipv6 *si = &__si6; + + spin_lock_bh(&si->lock); + sfe_ipv6_update_summary_stats(si); + + si->packets_forwarded64 = 0; + si->packets_not_forwarded64 = 0; + si->connection_create_requests64 = 0; + si->connection_create_collisions64 = 0; + si->connection_destroy_requests64 = 0; + si->connection_destroy_misses64 = 0; + si->connection_flushes64 = 0; + si->connection_match_hash_hits64 = 0; + si->connection_match_hash_reorders64 = 0; + spin_unlock_bh(&si->lock); + + return length; +} + +/* + * sfe_ipv6_debug_dev_open() + */ +static int sfe_ipv6_debug_dev_open(struct inode *inode, struct file *file) +{ + struct sfe_ipv6_debug_xml_write_state *ws; + + ws = (struct sfe_ipv6_debug_xml_write_state *)file->private_data; + if (ws) { + return 0; + } + + ws = kzalloc(sizeof(struct sfe_ipv6_debug_xml_write_state), GFP_KERNEL); + if (!ws) { + return -ENOMEM; + } + + ws->state = SFE_IPV6_DEBUG_XML_STATE_START; + file->private_data = ws; + + return 0; +} + +/* + * sfe_ipv6_debug_dev_release() + */ +static int sfe_ipv6_debug_dev_release(struct inode *inode, struct file *file) +{ + struct sfe_ipv6_debug_xml_write_state *ws; + + ws = (struct sfe_ipv6_debug_xml_write_state *)file->private_data; + if (ws) { + /* + * We've finished with our output so free the write state. + */ + kfree(ws); + } + + return 0; +} + +/* + * File operations used in the debug char device + */ +static struct file_operations sfe_ipv6_debug_dev_fops = { + .read = sfe_ipv6_debug_dev_read, + .write = sfe_ipv6_debug_dev_write, + .open = sfe_ipv6_debug_dev_open, + .release = sfe_ipv6_debug_dev_release +}; + +#ifdef CONFIG_NF_FLOW_COOKIE +/* + * sfe_ipv6_register_flow_cookie_cb + * register a function in SFE to let SFE use this function to configure flow cookie for a flow + * + * Hardware driver which support flow cookie should register a callback function in SFE. Then SFE + * can use this function to configure flow cookie for a flow. + * return: 0, success; !=0, fail + */ +int sfe_ipv6_register_flow_cookie_cb(sfe_ipv6_flow_cookie_set_func_t cb) +{ + struct sfe_ipv6 *si = &__si6; + + BUG_ON(!cb); + + if (si->flow_cookie_set_func) { + return -1; + } + + rcu_assign_pointer(si->flow_cookie_set_func, cb); + return 0; +} + +/* + * sfe_ipv6_unregister_flow_cookie_cb + * unregister function which is used to configure flow cookie for a flow + * + * return: 0, success; !=0, fail + */ +int sfe_ipv6_unregister_flow_cookie_cb(sfe_ipv6_flow_cookie_set_func_t cb) +{ + struct sfe_ipv6 *si = &__si6; + + RCU_INIT_POINTER(si->flow_cookie_set_func, NULL); + return 0; +} + +/* + * sfe_ipv6_get_flow_cookie() + */ +static ssize_t sfe_ipv6_get_flow_cookie(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct sfe_ipv6 *si = &__si6; + return snprintf(buf, (ssize_t)PAGE_SIZE, "%d\n", si->flow_cookie_enable); +} + +/* + * sfe_ipv6_set_flow_cookie() + */ +static ssize_t sfe_ipv6_set_flow_cookie(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + struct sfe_ipv6 *si = &__si6; + strict_strtol(buf, 0, (long int *)&si->flow_cookie_enable); + + return size; +} + +/* + * sysfs attributes. + */ +static const struct device_attribute sfe_ipv6_flow_cookie_attr = + __ATTR(flow_cookie_enable, S_IWUSR | S_IRUGO, sfe_ipv6_get_flow_cookie, sfe_ipv6_set_flow_cookie); +#endif /*CONFIG_NF_FLOW_COOKIE*/ + +/* + * sfe_ipv6_init() + */ +static int __init sfe_ipv6_init(void) +{ + struct sfe_ipv6 *si = &__si6; + int result = -1; + + DEBUG_INFO("SFE IPv6 init\n"); + + /* + * Create sys/sfe_ipv6 + */ + si->sys_sfe_ipv6 = kobject_create_and_add("sfe_ipv6", NULL); + if (!si->sys_sfe_ipv6) { + DEBUG_ERROR("failed to register sfe_ipv6\n"); + goto exit1; + } + + /* + * Create files, one for each parameter supported by this module. + */ + result = sysfs_create_file(si->sys_sfe_ipv6, &sfe_ipv6_debug_dev_attr.attr); + if (result) { + DEBUG_ERROR("failed to register debug dev file: %d\n", result); + goto exit2; + } + +#ifdef CONFIG_NF_FLOW_COOKIE + result = sysfs_create_file(si->sys_sfe_ipv6, &sfe_ipv6_flow_cookie_attr.attr); + if (result) { + DEBUG_ERROR("failed to register flow cookie enable file: %d\n", result); + goto exit3; + } +#endif /* CONFIG_NF_FLOW_COOKIE */ + + /* + * Register our debug char device. + */ + result = register_chrdev(0, "sfe_ipv6", &sfe_ipv6_debug_dev_fops); + if (result < 0) { + DEBUG_ERROR("Failed to register chrdev: %d\n", result); + goto exit4; + } + + si->debug_dev = result; + + /* + * Create a timer to handle periodic statistics. + */ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 15, 0)) + setup_timer(&si->timer, sfe_ipv6_periodic_sync, (unsigned long)si); +#else + timer_setup(&si->timer, sfe_ipv6_periodic_sync, 0); +#endif + mod_timer(&si->timer, jiffies + ((HZ + 99) / 100)); + + spin_lock_init(&si->lock); + + return 0; + +exit4: +#ifdef CONFIG_NF_FLOW_COOKIE + sysfs_remove_file(si->sys_sfe_ipv6, &sfe_ipv6_flow_cookie_attr.attr); + +exit3: +#endif /* CONFIG_NF_FLOW_COOKIE */ + sysfs_remove_file(si->sys_sfe_ipv6, &sfe_ipv6_debug_dev_attr.attr); + +exit2: + kobject_put(si->sys_sfe_ipv6); + +exit1: + return result; +} + +/* + * sfe_ipv6_exit() + */ +static void __exit sfe_ipv6_exit(void) +{ + struct sfe_ipv6 *si = &__si6; + + DEBUG_INFO("SFE IPv6 exit\n"); + + /* + * Destroy all connections. + */ + sfe_ipv6_destroy_all_rules_for_dev(NULL); + + del_timer_sync(&si->timer); + + unregister_chrdev(si->debug_dev, "sfe_ipv6"); + +#ifdef CONFIG_NF_FLOW_COOKIE + sysfs_remove_file(si->sys_sfe_ipv6, &sfe_ipv6_flow_cookie_attr.attr); +#endif /* CONFIG_NF_FLOW_COOKIE */ + sysfs_remove_file(si->sys_sfe_ipv6, &sfe_ipv6_debug_dev_attr.attr); + + kobject_put(si->sys_sfe_ipv6); +} + +module_init(sfe_ipv6_init) +module_exit(sfe_ipv6_exit) + +EXPORT_SYMBOL(sfe_ipv6_recv); +EXPORT_SYMBOL(sfe_ipv6_create_rule); +EXPORT_SYMBOL(sfe_ipv6_destroy_rule); +EXPORT_SYMBOL(sfe_ipv6_destroy_all_rules_for_dev); +EXPORT_SYMBOL(sfe_ipv6_register_sync_rule_callback); +EXPORT_SYMBOL(sfe_ipv6_mark_rule); +EXPORT_SYMBOL(sfe_ipv6_update_rule); +#ifdef CONFIG_NF_FLOW_COOKIE +EXPORT_SYMBOL(sfe_ipv6_register_flow_cookie_cb); +EXPORT_SYMBOL(sfe_ipv6_unregister_flow_cookie_cb); +#endif + +MODULE_DESCRIPTION("Shortcut Forwarding Engine - IPv6 support"); +MODULE_LICENSE("Dual BSD/GPL"); + diff --git a/shortcut-fe/simulated-driver/Makefile b/shortcut-fe/simulated-driver/Makefile new file mode 100644 index 000000000..ecf9c41bd --- /dev/null +++ b/shortcut-fe/simulated-driver/Makefile @@ -0,0 +1,60 @@ +# +# Copyright (c) 2015,2016 The Linux Foundation. All rights reserved. +# Permission to use, copy, modify, and/or distribute this software for +# any purpose with or without fee is hereby granted, provided that the +# above copyright notice and this permission notice appear in all copies. +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT +# OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +# + +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/kernel.mk + +PKG_NAME:=shortcut-fe-simulated-driver +PKG_RELEASE:=1 + +PKG_SOURCE_URL:=https://source.codeaurora.org/quic/qsdk/oss/lklm/shortcut-fe +PKG_SOURCE_PROTO:=git +PKG_SOURCE_DATE:=2021-03-17 +PKG_SOURCE_VERSION:=697977d8d0ccf0ab596e5692d08608a75dd7f33d +PKG_MIRROR_HASH:=659fa82a431e15af797a6c7069faeee02810453ad8b576c51c29f95a1761a045 + +include $(INCLUDE_DIR)/package.mk + +define KernelPackage/shortcut-fe-drv + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Support + DEPENDS:=@TARGET_ipq806x||TARGET_ipq807x +kmod-shortcut-fe + KCONFIG:= \ + CONFIG_NET_CLS_ACT=y \ + CONFIG_XFRM=y + TITLE:=Simulated sfe driver for ECM + FILES:=$(PKG_BUILD_DIR)/simulated-driver/shortcut-fe-drv.ko +endef + +define KernelPackage/shortcut-fe-drv/Description +Simulated sfe driver which act as an adapter to convert message +between a connection manager and the SFE core engine. +endef + +define Build/Compile + $(MAKE) $(PKG_JOBS) -C "$(LINUX_DIR)" \ + $(KERNEL_MAKE_FLAGS) \ + $(PKG_MAKE_FLAGS) \ + M="$(PKG_BUILD_DIR)/simulated-driver" \ + EXTRA_CFLAGS="-DSFE_SUPPORT_IPV6" \ + modules +endef + +define Build/InstallDev + $(INSTALL_DIR) $(1)/usr/include/shortcut-fe + $(CP) -rf $(PKG_BUILD_DIR)/simulated-driver/sfe_drv.h $(1)/usr/include/shortcut-fe +endef + +$(eval $(call KernelPackage,shortcut-fe-drv)) diff --git a/shortcut-fe/simulated-driver/patches/200-nss-qdisc-support.patch b/shortcut-fe/simulated-driver/patches/200-nss-qdisc-support.patch new file mode 100644 index 000000000..638ad8a84 --- /dev/null +++ b/shortcut-fe/simulated-driver/patches/200-nss-qdisc-support.patch @@ -0,0 +1,11 @@ +--- ./simulated-driver/sfe_drv.c.orig 2020-06-16 12:49:47.680153371 +0800 ++++ ./simulated-driver/sfe_drv.c 2020-06-16 12:50:18.540153371 +0800 +@@ -1167,7 +1167,7 @@ int sfe_drv_recv(struct sk_buff *skb) + * If ingress Qdisc configured, and packet not processed by ingress Qdisc yet + * We can not accelerate this packet. + */ +- if (dev->ingress_queue && !(skb->tc_verd & TC_NCLS)) { ++ if (dev->ingress_queue && !(skb->tc_verd_qca_nss & TC_NCLS)) { + return 0; + } + #endif diff --git a/upx/Makefile b/upx/Makefile new file mode 100644 index 000000000..b58bd8cd2 --- /dev/null +++ b/upx/Makefile @@ -0,0 +1,66 @@ +# +# Copyright (C) 2011-2020 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +include $(TOPDIR)/rules.mk + +PKG_NAME:=upx +PKG_RELEASE:=1 + +PKG_MAINTAINER:=Xingwang Liao +PKG_LICENSE:=GPL-2.0-only +PKG_LICENSE_FILES:=COPYING LICENSE + +PKG_SOURCE_PROTO:=git +PKG_SOURCE_DATE:=2022-01-15 +PKG_SOURCE_VERSION:=a46b63817a9c6ad5af7cf519332e859f11558592 +PKG_SOURCE_URL:=https://github.com/upx/upx.git +PKG_SOURCE:=$(PKG_NAME)-$(PKG_SOURCE_DATE).tar.gz + +HOST_BUILD_DEPENDS:=ucl/host + +include $(INCLUDE_DIR)/host-build.mk +include $(INCLUDE_DIR)/package.mk + +define Host/Compile + UPX_UCLDIR=$(STAGING_DIR_HOST) \ + $(MAKE) -C $(HOST_BUILD_DIR)/src \ + CXXFLAGS_WERROR="" LDFLAGS="$(HOST_LDFLAGS)" \ + CXX="$(HOSTCXX)" +endef + +define Host/Install + $(CP) $(HOST_BUILD_DIR)/src/upx.out $(STAGING_DIR_HOST)/bin/upx +endef + +define Host/Clean + rm -f $(STAGING_DIR_HOST)/bin/upx +endef + +define Package/upx + SECTION:=utils + CATEGORY:=Utilities + DEPENDS:=+libucl +libstdcpp +zlib + TITLE:=The Ultimate Packer for eXecutables + URL:=https://upx.github.io/ +endef + +define Package/upx/description +UPX is a free, portable, extendable, high-performance executable packer for +several different executable formats. It achieves an excellent compression ratio +and offers very fast decompression. Your executables suffer no memory overhead +or other drawbacks for most of the formats supported, because of in-place +decompression. +endef + +MAKE_PATH := src + +define Package/upx/install + $(INSTALL_DIR) $(1)/usr/bin + $(INSTALL_BIN) $(PKG_BUILD_DIR)/src/upx.out $(1)/usr/bin/upx +endef + +$(eval $(call HostBuild)) +$(eval $(call BuildPackage,upx)) From 877531db7a338b0caa3701057785eab1785d1a4d Mon Sep 17 00:00:00 2001 From: suyuan <175338101@qq.com> Date: Mon, 29 Aug 2022 01:29:22 +0800 Subject: [PATCH 07/19] fix --- netifd/files/sbin/ifdown | 1 - 1 file changed, 1 deletion(-) diff --git a/netifd/files/sbin/ifdown b/netifd/files/sbin/ifdown index a0e5c176a..e69de29bb 120000 --- a/netifd/files/sbin/ifdown +++ b/netifd/files/sbin/ifdown @@ -1 +0,0 @@ -ifup \ No newline at end of file From 10e1226f4844326759b914c2735d7860e824018f Mon Sep 17 00:00:00 2001 From: suyuan <175338101@qq.com> Date: Mon, 29 Aug 2022 02:22:08 +0800 Subject: [PATCH 08/19] Revert "fix" This reverts commit 5228ba68cfb4d394dfd589444c330750867e2674. --- netifd/files/sbin/ifdown | 1 + 1 file changed, 1 insertion(+) diff --git a/netifd/files/sbin/ifdown b/netifd/files/sbin/ifdown index e69de29bb..a0e5c176a 120000 --- a/netifd/files/sbin/ifdown +++ b/netifd/files/sbin/ifdown @@ -0,0 +1 @@ +ifup \ No newline at end of file From 55f8e1debd9a626667212ce9c37d5040c4fa4ad9 Mon Sep 17 00:00:00 2001 From: suyuan <175338101@qq.com> Date: Wed, 31 Aug 2022 01:28:33 +0800 Subject: [PATCH 09/19] Update 1990-omr-tracker --- openmptcprouter/files/etc/uci-defaults/1990-omr-tracker | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openmptcprouter/files/etc/uci-defaults/1990-omr-tracker b/openmptcprouter/files/etc/uci-defaults/1990-omr-tracker index 882e4b0a7..648dbaa17 100755 --- a/openmptcprouter/files/etc/uci-defaults/1990-omr-tracker +++ b/openmptcprouter/files/etc/uci-defaults/1990-omr-tracker @@ -4,7 +4,7 @@ if [ "$(uci -q get omr-tracker.omrvpn)" = "" ]; then uci -q batch <<-EOF >/dev/null delete omr-tracker.glorytun set omr-tracker.omrvpn=interface - set omr-tracker.omrvpn.type="none" + set omr-tracker.omrvpn.type="ping" set omr-tracker.omrvpn.timeout=10 set omr-tracker.omrvpn.tries=3 set omr-tracker.omrvpn.interval=5 From 6d3d740bceb27554def088ac39f9e8efdf3157d4 Mon Sep 17 00:00:00 2001 From: suyuan <175338101@qq.com> Date: Wed, 31 Aug 2022 03:05:32 +0800 Subject: [PATCH 10/19] Update 1990-omr-tracker --- openmptcprouter/files/etc/uci-defaults/1990-omr-tracker | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/openmptcprouter/files/etc/uci-defaults/1990-omr-tracker b/openmptcprouter/files/etc/uci-defaults/1990-omr-tracker index 648dbaa17..3f276254a 100755 --- a/openmptcprouter/files/etc/uci-defaults/1990-omr-tracker +++ b/openmptcprouter/files/etc/uci-defaults/1990-omr-tracker @@ -15,6 +15,10 @@ if [ "$(uci -q get omr-tracker.omrvpn)" = "" ]; then set omr-tracker.omrvpn.restart_down=0 add_list omr-tracker.omrvpn.hosts='4.2.2.1' add_list omr-tracker.omrvpn.hosts='8.8.8.8' + add_list omr-tracker.omrvpn.hosts='223.5.5.5' + add_list omr-tracker.omrvpn.hosts='223.6.6.6' + add_list omr-tracker.omrvpn.hosts='114.114.114.114' + add_list omr-tracker.omrvpn.hosts='180.76.76.76' commit omr-tracker EOF fi From e49e949296d4ad5bd48e7a5b78622b88e87d1dd0 Mon Sep 17 00:00:00 2001 From: suyuan <175338101@qq.com> Date: Wed, 31 Aug 2022 22:33:53 +0800 Subject: [PATCH 11/19] fix --- omr-tracker/files/etc/config/omr-tracker | 2 +- openmptcprouter/files/etc/uci-defaults/1990-omr-tracker | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/omr-tracker/files/etc/config/omr-tracker b/omr-tracker/files/etc/config/omr-tracker index f07da7b35..8d17aaa37 100755 --- a/omr-tracker/files/etc/config/omr-tracker +++ b/omr-tracker/files/etc/config/omr-tracker @@ -26,7 +26,7 @@ config defaults 'defaults' option type 'ping' option wait_test '0' option server_http_test '0' - option restart_down '0' + option restart_down '1' option mail_alert '0' config proxy 'proxy' diff --git a/openmptcprouter/files/etc/uci-defaults/1990-omr-tracker b/openmptcprouter/files/etc/uci-defaults/1990-omr-tracker index 3f276254a..ff353a7b7 100755 --- a/openmptcprouter/files/etc/uci-defaults/1990-omr-tracker +++ b/openmptcprouter/files/etc/uci-defaults/1990-omr-tracker @@ -12,7 +12,7 @@ if [ "$(uci -q get omr-tracker.omrvpn)" = "" ]; then set omr-tracker.omrvpn.enabled=1 set omr-tracker.omrvpn.wait-test=0 set omr-tracker.omrvpn.server_http_test=1 - set omr-tracker.omrvpn.restart_down=0 + set omr-tracker.omrvpn.restart_down=1 add_list omr-tracker.omrvpn.hosts='4.2.2.1' add_list omr-tracker.omrvpn.hosts='8.8.8.8' add_list omr-tracker.omrvpn.hosts='223.5.5.5' From 754b131bea6ac2ccc483923d8f3ee271fdf62eae Mon Sep 17 00:00:00 2001 From: suyuan <175338101@qq.com> Date: Thu, 1 Sep 2022 04:03:41 +0800 Subject: [PATCH 12/19] Update 1990-omr-tracker --- openmptcprouter/files/etc/uci-defaults/1990-omr-tracker | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openmptcprouter/files/etc/uci-defaults/1990-omr-tracker b/openmptcprouter/files/etc/uci-defaults/1990-omr-tracker index ff353a7b7..88e8394df 100755 --- a/openmptcprouter/files/etc/uci-defaults/1990-omr-tracker +++ b/openmptcprouter/files/etc/uci-defaults/1990-omr-tracker @@ -4,7 +4,7 @@ if [ "$(uci -q get omr-tracker.omrvpn)" = "" ]; then uci -q batch <<-EOF >/dev/null delete omr-tracker.glorytun set omr-tracker.omrvpn=interface - set omr-tracker.omrvpn.type="ping" + set omr-tracker.omrvpn.type="none" set omr-tracker.omrvpn.timeout=10 set omr-tracker.omrvpn.tries=3 set omr-tracker.omrvpn.interval=5 @@ -12,7 +12,7 @@ if [ "$(uci -q get omr-tracker.omrvpn)" = "" ]; then set omr-tracker.omrvpn.enabled=1 set omr-tracker.omrvpn.wait-test=0 set omr-tracker.omrvpn.server_http_test=1 - set omr-tracker.omrvpn.restart_down=1 + set omr-tracker.omrvpn.restart_down=0 add_list omr-tracker.omrvpn.hosts='4.2.2.1' add_list omr-tracker.omrvpn.hosts='8.8.8.8' add_list omr-tracker.omrvpn.hosts='223.5.5.5' From 083306174ff8577d9fd09c9da7c15e5713f5828b Mon Sep 17 00:00:00 2001 From: suyuan <175338101@qq.com> Date: Thu, 1 Sep 2022 04:12:32 +0800 Subject: [PATCH 13/19] Update header.htm --- luci-theme-ezengreen/luasrc/view/themes/ezengreen/header.htm | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/luci-theme-ezengreen/luasrc/view/themes/ezengreen/header.htm b/luci-theme-ezengreen/luasrc/view/themes/ezengreen/header.htm index e5c4c9f97..f4a63ebaf 100755 --- a/luci-theme-ezengreen/luasrc/view/themes/ezengreen/header.htm +++ b/luci-theme-ezengreen/luasrc/view/themes/ezengreen/header.htm @@ -70,7 +70,7 @@ <%- if current_omr_version ~= "" and latest_omr_version ~= "" and current_omr_version < latest_omr_version then -%> <%- end -%>
    From 218fb8a6e5165f8016b24a8e9fbf2300579e74d2 Mon Sep 17 00:00:00 2001 From: "Ycarus (Yannick Chabanois)" Date: Mon, 12 Sep 2022 19:55:17 +0200 Subject: [PATCH 14/19] Various small fixes --- luci-app-mptcp/luasrc/view/mptcp/multipath.htm | 1 + .../luasrc/controller/openmptcprouter.lua | 6 ++++-- openmptcprouter/files/etc/init.d/openmptcprouter-vps | 6 +++++- 3 files changed, 10 insertions(+), 3 deletions(-) diff --git a/luci-app-mptcp/luasrc/view/mptcp/multipath.htm b/luci-app-mptcp/luasrc/view/mptcp/multipath.htm index 97ea6e956..01abf6a7f 100644 --- a/luci-app-mptcp/luasrc/view/mptcp/multipath.htm +++ b/luci-app-mptcp/luasrc/view/mptcp/multipath.htm @@ -85,6 +85,7 @@ function bandwidth_label(bytes, br) { + if (bytes < 0) bytes = 0; var uby = '<%:kB/s%>'; var kby = (bytes / 1024); diff --git a/luci-app-openmptcprouter/luasrc/controller/openmptcprouter.lua b/luci-app-openmptcprouter/luasrc/controller/openmptcprouter.lua index 00c421517..ec1dbcd6b 100644 --- a/luci-app-openmptcprouter/luasrc/controller/openmptcprouter.lua +++ b/luci-app-openmptcprouter/luasrc/controller/openmptcprouter.lua @@ -634,6 +634,8 @@ function wizard_add() ucic:set("unbound","ub_main","dns64","0") end + ucic:save("unbound") + ucic:commit("unbound") -- Get Proxy set by default local default_proxy = luci.http.formvalue("default_proxy") or "shadowsocks" @@ -981,7 +983,7 @@ function wizard_add() ucic:set("openvpn","omr","enabled",1) ucic:set("network","omrvpn","proto","none") else - ucic:set("openvpn","omr","enabled",0) + ucic:delete("openvpn","omr","enabled") end ucic:save("openvpn") ucic:commit("openvpn") @@ -1156,7 +1158,7 @@ function settings_add() ucic:set("openmptcprouter","settings","shadowsocksudp",shadowsocksudp) -- Enable/disable v2ray udp - local shadowsocksudp = luci.http.formvalue("v2rayudp") or "1" + local v2rayudp = luci.http.formvalue("v2rayudp") or "1" ucic:set("v2ray","main_transparent_proxy","redirect_udp",v2rayudp) -- Enable/disable nDPI diff --git a/openmptcprouter/files/etc/init.d/openmptcprouter-vps b/openmptcprouter/files/etc/init.d/openmptcprouter-vps index 9ac1e17b2..d49d3aed9 100755 --- a/openmptcprouter/files/etc/init.d/openmptcprouter-vps +++ b/openmptcprouter/files/etc/init.d/openmptcprouter-vps @@ -1461,8 +1461,12 @@ _set_config_from_vps() { uci -q batch <<-EOF >/dev/null set openvpn.omr.port=$openvpn_port set openvpn.omr.secret="/etc/luci-uploads/openvpn.key" - set openvpn.omr.enabled=$openvpn_state EOF + if [ "$openvpn_state" = "1" ]; then + uci -q set openvpn.omr.enabled=$openvpn_state + else + uci -q del openvpn.omr.enabled + fi if [ "$(uci -q get openvpn.omr.remote)" != "127.0.0.1" ]; then uci -q set openvpn.omr.remote="$vpsip" fi From 8f8028cb7f7bdc60ae6a9c688500c5b6d6c01dbc Mon Sep 17 00:00:00 2001 From: suyuan <175338101@qq.com> Date: Tue, 13 Sep 2022 12:59:02 +0800 Subject: [PATCH 15/19] add qca --- qca/aq-fw-download/Makefile | 26 + qca/aq-fw-download/src/Makefile | 14 + qca/aq-fw-download/src/include/AQ_API.h | 246 + .../src/include/AQ_PhyInterface.h | 171 + .../src/include/AQ_PlatformRoutines.h | 71 + qca/aq-fw-download/src/include/AQ_RegMacro.h | 323 + .../src/include/AQ_ReturnCodes.h | 113 + qca/aq-fw-download/src/include/AQ_User.h | 97 + .../APPIA/AQ_APPIA_Global_registers.h | 5581 +++++++ .../APPIA/AQ_APPIA_Global_registers_Defines.h | 2134 +++ .../AQ_APPIA_Global_registers_reversed.h | 5581 +++++++ .../include/registerMap/AQ_RegGroupMaxSizes.h | 387 + .../src/include/registerMap/AQ_RegMaps.h | 69 + .../registerMap/HHD/AQ_HHD_Global_registers.h | 12123 ++++++++++++++++ .../HHD/AQ_HHD_Global_registers_Defines.h | 4413 ++++++ .../HHD/AQ_HHD_Global_registers_reversed.h | 12123 ++++++++++++++++ qca/aq-fw-download/src/mdioBootLoadCLD.c | 193 + qca/aq-fw-download/src/src/AQ_API.c | 1021 ++ qca/aq-fw-download/src/src/AQ_PhyInterface.c | 141 + qca/nss-eip-firmware/Makefile | 34 + qca/nss-eip-firmware/src/.gitkeep | 0 qca/nss-firmware/Makefile | 72 + qca/qca-nss-cfi/Makefile | 71 + .../patches/100-remove-noise-logs.patch | 30 + qca/qca-nss-clients/Makefile | 102 + qca/qca-nss-clients/files/qca-nss-ipsec | 214 + qca/qca-nss-clients/files/qca-nss-mirred.init | 28 + qca/qca-nss-clients/files/qca-nss-ovpn.init | 69 + qca/qca-nss-crypto/Makefile | 72 + ...1-nss-crypto-fix-SHA1-header-include.patch | 32 + ...replace-ioremap_nocache-with-ioremap.patch | 69 + ...rypto-fix-SHA-header-include-in-5.15.patch | 51 + qca/qca-nss-dp/Makefile | 56 + ...port-newer-kernels-time-stamping-API.patch | 44 + ...-phy-mode-code-compatible-with-newer.patch | 48 + ...03-Drop-_nocache-variants-of-ioremap.patch | 48 + .../0004-EDMA-Fix-NAPI-packet-counting.patch | 31 + ...-Use-NAPI_POLL_WEIGHT-as-NAPI-weight.patch | 41 + .../0006-NSS-DP-fix-of_get_mac_address.patch | 46 + ...07-NSS-DP-implement-ethernet-IOCTL-s.patch | 29 + ...dev-remove-the-transaction-structure.patch | 48 + ...09-switchdev-use-new-switchdev-flags.patch | 51 + .../0010-switchdev-fix-FDB-roaming.patch | 110 + ...fusing-printing-of-registered-netdev.patch | 48 + ...syn-xgmac-silence-debug-log-on-probe.patch | 28 + ...a-phy-handle-property-to-connect-to-.patch | 189 + ...p-edma-v1-switch-to-napi_gro_receive.patch | 46 + qca/qca-nss-drv/Makefile | 129 + qca/qca-nss-drv/files/qca-nss-drv.conf | 6 + qca/qca-nss-drv/files/qca-nss-drv.debug | 26 + qca/qca-nss-drv/files/qca-nss-drv.hotplug | 70 + qca/qca-nss-drv/files/qca-nss-drv.init | 50 + qca/qca-nss-drv/files/qca-nss-drv.sysctl | 4 + ...ore-add-5.10-kernel-to-version-check.patch | 25 + ...replace-ioremap_nocache-with-ioremap.patch | 181 + ...0003-DMA-Fix-NULL-pointer-exceptions.patch | 49 + ...-rework-NSS_CORE_DMA_CACHE_MAINT-ops.patch | 573 + ...-nss-drv-add-support-for-kernel-5.15.patch | 70 + ...dard-skb_skip_tc_classify-instead-of.patch | 30 + ...Makefile-modularize-driver-even-more.patch | 172 + qca/qca-nss-ecm/Makefile | 97 + qca/qca-nss-ecm/files/ecm_dump.sh | 95 + qca/qca-nss-ecm/files/on-demand-down | 6 + qca/qca-nss-ecm/files/qca-nss-ecm.defaults | 28 + qca/qca-nss-ecm/files/qca-nss-ecm.firewall | 18 + qca/qca-nss-ecm/files/qca-nss-ecm.init | 142 + qca/qca-nss-ecm/files/qca-nss-ecm.sysctl | 2 + qca/qca-nss-ecm/files/qca-nss-ecm.uci | 2 + ...de-componentize-the-module-even-more.patch | 335 + .../patches/100-kernel-5.10-support.patch | 831 ++ .../patches/200-resolve-high-load.patch | 61 + .../203-rework-nfct-notification.patch | 25 + .../patches/204-More-compile-fixes.patch | 49 + .../patches/205-resolve-high-load.patch | 55 + qca/qca-ssdk-shell/Makefile | 48 + qca/qca-ssdk/Makefile | 91 + qca/qca-ssdk/files/qca-ssdk | 206 + .../0001-SSDK-config-add-kernel-5.10.patch | 56 + ...replace-ioremap_nocache-with-ioremap.patch | 102 + ...use-of_mdio_find_bus-to-get-MDIO-bus.patch | 40 + ...0005-SSDK-dts-fix-of_get_mac_address.patch | 42 + .../0006-SSDK-config-add-kernel-5.15.patch | 56 + ...07-qca8081-convert-to-5.11-IRQ-model.patch | 83 + ...7x-add-a-LED-quirk-for-Xiaomi-AX9000.patch | 74 + ...7x-add-a-LED-quirk-for-Xiaomi-AX3600.patch | 29 + ...mpilation-error-for-parse_uci_option.patch | 27 + 86 files changed, 50519 insertions(+) create mode 100644 qca/aq-fw-download/Makefile create mode 100644 qca/aq-fw-download/src/Makefile create mode 100644 qca/aq-fw-download/src/include/AQ_API.h create mode 100644 qca/aq-fw-download/src/include/AQ_PhyInterface.h create mode 100644 qca/aq-fw-download/src/include/AQ_PlatformRoutines.h create mode 100644 qca/aq-fw-download/src/include/AQ_RegMacro.h create mode 100644 qca/aq-fw-download/src/include/AQ_ReturnCodes.h create mode 100644 qca/aq-fw-download/src/include/AQ_User.h create mode 100644 qca/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers.h create mode 100644 qca/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers_Defines.h create mode 100644 qca/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers_reversed.h create mode 100644 qca/aq-fw-download/src/include/registerMap/AQ_RegGroupMaxSizes.h create mode 100644 qca/aq-fw-download/src/include/registerMap/AQ_RegMaps.h create mode 100644 qca/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers.h create mode 100644 qca/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers_Defines.h create mode 100644 qca/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers_reversed.h create mode 100644 qca/aq-fw-download/src/mdioBootLoadCLD.c create mode 100644 qca/aq-fw-download/src/src/AQ_API.c create mode 100644 qca/aq-fw-download/src/src/AQ_PhyInterface.c create mode 100644 qca/nss-eip-firmware/Makefile create mode 100644 qca/nss-eip-firmware/src/.gitkeep create mode 100644 qca/nss-firmware/Makefile create mode 100644 qca/qca-nss-cfi/Makefile create mode 100644 qca/qca-nss-cfi/patches/100-remove-noise-logs.patch create mode 100644 qca/qca-nss-clients/Makefile create mode 100644 qca/qca-nss-clients/files/qca-nss-ipsec create mode 100644 qca/qca-nss-clients/files/qca-nss-mirred.init create mode 100644 qca/qca-nss-clients/files/qca-nss-ovpn.init create mode 100644 qca/qca-nss-crypto/Makefile create mode 100644 qca/qca-nss-crypto/patches/0001-nss-crypto-fix-SHA1-header-include.patch create mode 100644 qca/qca-nss-crypto/patches/0002-nss-crypto-replace-ioremap_nocache-with-ioremap.patch create mode 100644 qca/qca-nss-crypto/patches/0003-nss-crypto-fix-SHA-header-include-in-5.15.patch create mode 100644 qca/qca-nss-dp/Makefile create mode 100644 qca/qca-nss-dp/patches/0001-edma_tx_rx-support-newer-kernels-time-stamping-API.patch create mode 100644 qca/qca-nss-dp/patches/0002-nss_dp_main-make-phy-mode-code-compatible-with-newer.patch create mode 100644 qca/qca-nss-dp/patches/0003-Drop-_nocache-variants-of-ioremap.patch create mode 100644 qca/qca-nss-dp/patches/0004-EDMA-Fix-NAPI-packet-counting.patch create mode 100644 qca/qca-nss-dp/patches/0005-EDMA-Use-NAPI_POLL_WEIGHT-as-NAPI-weight.patch create mode 100644 qca/qca-nss-dp/patches/0006-NSS-DP-fix-of_get_mac_address.patch create mode 100644 qca/qca-nss-dp/patches/0007-NSS-DP-implement-ethernet-IOCTL-s.patch create mode 100644 qca/qca-nss-dp/patches/0008-switchdev-remove-the-transaction-structure.patch create mode 100644 qca/qca-nss-dp/patches/0009-switchdev-use-new-switchdev-flags.patch create mode 100644 qca/qca-nss-dp/patches/0010-switchdev-fix-FDB-roaming.patch create mode 100644 qca/qca-nss-dp/patches/0011-treewide-fix-confusing-printing-of-registered-netdev.patch create mode 100644 qca/qca-nss-dp/patches/0012-gmac-syn-xgmac-silence-debug-log-on-probe.patch create mode 100644 qca/qca-nss-dp/patches/0013-nss_dp_main-Use-a-phy-handle-property-to-connect-to-.patch create mode 100644 qca/qca-nss-dp/patches/0014-nss-dp-edma-v1-switch-to-napi_gro_receive.patch create mode 100644 qca/qca-nss-drv/Makefile create mode 100644 qca/qca-nss-drv/files/qca-nss-drv.conf create mode 100644 qca/qca-nss-drv/files/qca-nss-drv.debug create mode 100644 qca/qca-nss-drv/files/qca-nss-drv.hotplug create mode 100644 qca/qca-nss-drv/files/qca-nss-drv.init create mode 100644 qca/qca-nss-drv/files/qca-nss-drv.sysctl create mode 100644 qca/qca-nss-drv/patches/0001-core-add-5.10-kernel-to-version-check.patch create mode 100644 qca/qca-nss-drv/patches/0002-nss-drv-replace-ioremap_nocache-with-ioremap.patch create mode 100644 qca/qca-nss-drv/patches/0003-DMA-Fix-NULL-pointer-exceptions.patch create mode 100644 qca/qca-nss-drv/patches/0004-nss-drv-rework-NSS_CORE_DMA_CACHE_MAINT-ops.patch create mode 100644 qca/qca-nss-drv/patches/0005-nss-drv-add-support-for-kernel-5.15.patch create mode 100644 qca/qca-nss-drv/patches/0005-nss-drv-use-standard-skb_skip_tc_classify-instead-of.patch create mode 100644 qca/qca-nss-drv/patches/0008-Makefile-modularize-driver-even-more.patch create mode 100644 qca/qca-nss-ecm/Makefile create mode 100644 qca/qca-nss-ecm/files/ecm_dump.sh create mode 100644 qca/qca-nss-ecm/files/on-demand-down create mode 100644 qca/qca-nss-ecm/files/qca-nss-ecm.defaults create mode 100644 qca/qca-nss-ecm/files/qca-nss-ecm.firewall create mode 100644 qca/qca-nss-ecm/files/qca-nss-ecm.init create mode 100644 qca/qca-nss-ecm/files/qca-nss-ecm.sysctl create mode 100644 qca/qca-nss-ecm/files/qca-nss-ecm.uci create mode 100644 qca/qca-nss-ecm/patches/001-treewide-componentize-the-module-even-more.patch create mode 100644 qca/qca-nss-ecm/patches/100-kernel-5.10-support.patch create mode 100644 qca/qca-nss-ecm/patches/200-resolve-high-load.patch create mode 100644 qca/qca-nss-ecm/patches/203-rework-nfct-notification.patch create mode 100644 qca/qca-nss-ecm/patches/204-More-compile-fixes.patch create mode 100644 qca/qca-nss-ecm/patches/205-resolve-high-load.patch create mode 100644 qca/qca-ssdk-shell/Makefile create mode 100644 qca/qca-ssdk/Makefile create mode 100644 qca/qca-ssdk/files/qca-ssdk create mode 100644 qca/qca-ssdk/patches/0001-SSDK-config-add-kernel-5.10.patch create mode 100644 qca/qca-ssdk/patches/0002-SSDK-replace-ioremap_nocache-with-ioremap.patch create mode 100644 qca/qca-ssdk/patches/0004-platform-use-of_mdio_find_bus-to-get-MDIO-bus.patch create mode 100644 qca/qca-ssdk/patches/0005-SSDK-dts-fix-of_get_mac_address.patch create mode 100644 qca/qca-ssdk/patches/0006-SSDK-config-add-kernel-5.15.patch create mode 100644 qca/qca-ssdk/patches/0007-qca8081-convert-to-5.11-IRQ-model.patch create mode 100644 qca/qca-ssdk/patches/0008-qca807x-add-a-LED-quirk-for-Xiaomi-AX9000.patch create mode 100644 qca/qca-ssdk/patches/0009-qca807x-add-a-LED-quirk-for-Xiaomi-AX3600.patch create mode 100644 qca/qca-ssdk/patches/0012-include-fix-compilation-error-for-parse_uci_option.patch diff --git a/qca/aq-fw-download/Makefile b/qca/aq-fw-download/Makefile new file mode 100644 index 000000000..97270688b --- /dev/null +++ b/qca/aq-fw-download/Makefile @@ -0,0 +1,26 @@ +include $(TOPDIR)/rules.mk + +PKG_NAME:=aq-fw-download +PKG_RELEASE:=$(AUTORELEASE) + +PKG_FLAGS:=nonshared + +include $(INCLUDE_DIR)/package.mk + +define Package/aq-fw-download + SECTION:=firmware + CATEGORY:=Firmware + DEPENDS:=@TARGET_ipq807x + TITLE:=Aquantia FW downloader utitlity +endef + +define Package/aq-fw-download/description + Aquantia FW downloader utitlity +endef + +define Package/aq-fw-download/install + $(INSTALL_DIR) $(1)/sbin + $(INSTALL_BIN) $(PKG_BUILD_DIR)/aq-fw-download $(1)/sbin/aq-fw-download +endef + +$(eval $(call BuildPackage,aq-fw-download)) diff --git a/qca/aq-fw-download/src/Makefile b/qca/aq-fw-download/src/Makefile new file mode 100644 index 000000000..dc141be0e --- /dev/null +++ b/qca/aq-fw-download/src/Makefile @@ -0,0 +1,14 @@ +ifndef CFLAGS +CFLAGS = -O2 -g +endif +INCLUDES=-Iinclude -Iinclude/registerMap \ + -Iinclude/registerMap/APPIA \ + -Iinclude/registerMap/HHD + +all: aq-fw-download + +%.o: %.c + $(CC) $(INCLUDES) $(CFLAGS) -c -o $@ $^ + +aq-fw-download: mdioBootLoadCLD.o src/AQ_PhyInterface.o src/AQ_API.o + $(CC) $(LDFLAGS) -o $@ $^ $(LIBS) diff --git a/qca/aq-fw-download/src/include/AQ_API.h b/qca/aq-fw-download/src/include/AQ_API.h new file mode 100644 index 000000000..9a0b4c20a --- /dev/null +++ b/qca/aq-fw-download/src/include/AQ_API.h @@ -0,0 +1,246 @@ +/* +* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +*/ + +/*! \file + This file contains the AQ_API function and datatype declarations. */ + + +#ifndef AQ_API_TOKEN +#define AQ_API_TOKEN + +#include + +#include "AQ_User.h" +#include "AQ_ReturnCodes.h" + +/******************************************************************* + General +*******************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/*! This typedef defines the bool datatype which takes the values +true and false.*/ +typedef enum {False = 0, True = 1} AQ_boolean; + + +/*@}*/ + + +/******************************************************************* + Device Identity +*******************************************************************/ + +/*! \defgroup deviceIdentity Device Identity +All AQ_API functions accept a parameter identifying the target PHY that +should be acted upon. */ +/*@{*/ + + +/*! This enumeration is used to describe the different types of + Aquantia PHY.*/ +typedef enum +{ + /*! 1/2/4-port package, 40nm architechture.*/ + AQ_DEVICE_APPIA, + /*! 1/2/4-port package, 28nm architechture.*/ + AQ_DEVICE_HHD +} AQ_API_Device; + +/*! This structure is used to specify a particular Aquantia PHY port + within the system.*/ +typedef struct +{ + /*! The type of Aquantia PHY*/ + AQ_API_Device device; + /*! Uniquely identifies the port within the system. AQ_Port must be + defined to whatever data type is suitable for the platform. + AQ_API functions will never do anything with PHY_ID other than + pass it down to the platform's PHY register read/write + functions.*/ + AQ_Port PHY_ID; +} AQ_API_Port; + +/*@}*/ + + +/*! This function boot-loads the instruction and data memory (IRAM and + DRAM) of a set of Aquantia PHYs from a .cld format image file (the + same image file used to burn the FLASH). During boot-load of each + Aquantia PHY, the processor is halted, and after programming is + complete the processor is released. Note that calling this + function leaves the daisy-chain disabled to prevent RAM over- + write. To exit MDIO boot-load mode, use the function + AQ_API_EnableDaisyChain. + Unlike most of the other functions in this API, this function can + operate on a group of PHYs simultaneously. This is referred to as + gang-loading. To facilitate this, this function takes as + parameters 3 parallel arrays: PHY_IDs, provisioningAddresses, and + resultCodes. The length of these arrays must be identical, and is + specified by the num_PHY_IDs parameter. + In order to check the integrity of the boot-load operation, a + CRC-16 value is calculated over the IRAM and DRAM. After the image + has been loaded, this value is directly compared against each + PHY's Mailbox CRC-16 in 1E.0201. + The value of register 1E.C441 must be the same for all the boot- + loaded PHYs. This will be checked before the boot-load is + performed, and if a non-uniform value is read from any of the + PHYs, the function will fail before any writes are performed. + A separate result code is returned for each of the boot-loaded + PHYs, in the OUT parameter, resultCodes. + Individual Port Return codes: + AQ_RET_BOOTLOAD_PROVADDR_OOR: The specified provisioning address + was outside of the permitted range. + AQ_RET_BOOTLOAD_NONUNIFORM_REGVALS: The values of the register(s) + that must be uniform across the ports being bootloaded were not + uniform. + AQ_RET_BOOTLOAD_CRC_MISMATCH: The image was completely loaded into + memory, but the after the port exited bootload the running + checksum that was read from the uP memory mailbox was not the + expected value. This indicates that the memory has potentially + been corrupted, and the PHY should be reset before trying the + bootload again. + Overall Return codes (the return value from the function call): + AQ_RET_OK: all ports were successfully bootloaded. + AQ_RET_ERROR: One or more ports were not successfully bootloaded. + */ +AQ_Retcode AQ_API_WriteBootLoadImage +( + /*! An array identifying the target PHY ports.*/ + AQ_API_Port** ports, + /*! The length of the arrays ports, provisioningAddresses, and + resultCodes. These are parallel arrays, and must all be of the + same length.*/ + unsigned int numPorts, + /*! The provisioning addresses of each of the PHYs specified in + ports. This can range from 0 through 47, and is also known as + the daisy-chain address or the hop-count. If the PHYs are + connected to a FLASH using the daisy-chain, this is the distance + from the PHY to the FLASH, and is used to identify customized + provisioning for each PHY from the provisioning data within the + image. Otherwise, it is an arbitrary number. The length of this + array must match the length of ports.*/ + unsigned int* provisioningAddresses, + /*! OUT: The result code indicating success or failure of boot- + loading each of the PHYs specified in ports.*/ + AQ_Retcode* resultCodes, + /*! A pointer to the size of the image (in bytes) that is being + loaded into the Aquantia PHY.*/ + uint32_t* imageSizePointer, + /*! The image being loaded into the Aquantia PHY. This is the same + regardless of whether the target is internal RAM or FLASH.*/ + uint8_t* image, + /*! The 5-bit address to be used during the gang-loading operation. + During the boot-loading process, each of the PHYs specified in + ports will be changed such that they are addressed on the MDIO + bus at gangloadAddress. This allows all the PHYs to be loaded + simultaneously. Before returning, each PHY will be moved back to + its original MDIO address. If ports contains only a single + element, callers will probably want to use the PHY's original + MDIO address for this parameter.*/ + uint8_t gangload_MDIO_address, + /*! The address of the PHYs while in gangload mode. This is + ultimately some combination of the system address and the + gangload MDIO address, specified by gangload_MDIO_address. For + most platforms, gangload_MDIO_address and gangload_PHY_ID should + have the same value.*/ + AQ_API_Port* gangloadPort +); + +/*! This function boot-loads the instruction and data memory (IRAM and + DRAM) of a set of Aquantia PHYs from a .cld format image file (the + same image file used to burn the FLASH), as well as a separately + provided provisioning table image file.The provisioning table + image allows additional provisioning to be provided, beyond what + is built in to the .cld image. If provTableSizePointer or + provTableImage are NULL, this function behaves like + AQ_API_WriteBootLoadImage. + Aside from the additional provisioing table, this function behaves + exactly the same as AQ_API_WriteBootLoadImage. For additional + documentation and information on return codes, refer to + AQ_API_WriteBootLoadImage. + Individual Port Return codes (same as AQ_API_WriteBootLoadImage, + plus): + AQ_RET_BOOTLOAD_PROVTABLE_TOO_LARGE: The supplied provisioning + table image does not fit within the alloted space.*/ +AQ_Retcode AQ_API_WriteBootLoadImageWithProvTable +( + /*! An array identifying the target PHY ports.*/ + AQ_API_Port** ports, + /*! The length of the arrays ports, provisioningAddresses, and + resultCodes. These are parallel arrays, and must all be of the + same length.*/ + unsigned int numPorts, + /*! The provisioning addresses of each of the PHYs specified in + ports. This can range from 0 through 47, and is also known as + the daisy-chain address or the hop-count. If the PHYs are + connected to a FLASH using the daisy-chain, this is the distance + from the PHY to the FLASH, and is used to identify customized + provisioning for each PHY from the provisioning data within the + image. Otherwise, it is an arbitrary number. The length of this + array must match the length of ports.*/ + unsigned int* provisioningAddresses, + /*! OUT: The result code indicating success or failure of boot- + loading each of the PHYs specified in ports.*/ + AQ_Retcode* resultCodes, + /*! A pointer to the size of the image (in bytes) that is being + loaded into the Aquantia PHY.*/ + uint32_t* imageSizePointer, + /*! The image being loaded into the Aquantia PHY. This is the same + regardless of whether the target is internal RAM or FLASH.*/ + uint8_t* image, + /*! The 5-bit address to be used during the gang-loading operation. + During the boot-loading process, each of the PHYs specified in + ports will be changed such that they are addressed on the MDIO + bus at gangloadAddress. This allows all the PHYs to be loaded + simultaneously. Before returning, each PHY will be moved back to + its original MDIO address. If ports contains only a single + element, callers will probably want to use the PHY's original + MDIO address for this parameter.*/ + uint8_t gangload_MDIO_address, + /*! The address of the PHYs while in gangload mode. This is + ultimately some combination of the system address and the + gangload MDIO address, specified by gangload_MDIO_address. For + most platforms, gangload_MDIO_address and gangload_PHY_ID should + have the same value.*/ + AQ_API_Port* gangloadPort, + /*! A pointer to the size of the provTableImage (in bytes) that is + being loaded into the Aquantia PHY.*/ + uint32_t* provTableSizePointer, + /*! The additional provisioning table image being loaded into the + Aquantia PHY.*/ + uint8_t* provTableImage +); + +/*! Calling this function disables boot-loading and enables the daisy- + chain. This would typically be called after using MDIO boot- + loading on a daisy-chain enabled PHY. Re-enabling the daisy-chain + after performing an MDIO bootload will cause the PHY to reboot + from FLASH.*/ +AQ_Retcode AQ_API_EnableDaisyChain +( + /*! The target PHY port.*/ + AQ_API_Port* port +); + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/qca/aq-fw-download/src/include/AQ_PhyInterface.h b/qca/aq-fw-download/src/include/AQ_PhyInterface.h new file mode 100644 index 000000000..66eb817be --- /dev/null +++ b/qca/aq-fw-download/src/include/AQ_PhyInterface.h @@ -0,0 +1,171 @@ +/* AQ_PhyInterface.h */ + +/*********************************************************************** +* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +* +* Description: +* +* Declares the base PHY register read and write functions that are +* called by the API functions. The platform integrator must provide +* the implementation of these routines. +* +***********************************************************************/ + + +/*! \file + * Declares the base PHY register read and write functions that are + * called by the API functions. The platform integrator must provide + * the implementation of these routines. */ + + +#ifndef AQ_PHY_INTERFACE_TOKEN +#define AQ_PHY_INTERFACE_TOKEN + + +#include "AQ_API.h" +#include "AQ_User.h" + + +#ifdef __cplusplus +extern "C" { +#endif + + +/******************************************************************* + MDIO Access Functions +*******************************************************************/ + +/*! \defgroup mdioAccessFunctions MDIO Access Functions +The MDIO access functions are required by the API to access the register space +of each Aquantia PHY deployed in a system. The body of these functions needs to +be written by the system designer, as the method of accessing the PHY will +be unique to the target system. They are designed to be generic read and +write access functions, as the MDIO addressing scheme relies on each +MMD to maintain a 16 bit address pointer that determines the register where +the next read or write is coming from. Consequently, various levels of +optimization of the MDIO interface are possible: from re-writing the MMD +address pointer on every transaction, to storing shadow copies of the MMD +address pointers and only updating the MMD address pointer as necessary. +Thus these functions leave the MDIO optimization to the system engineer. + */ +/*@{*/ + + +/*! Provides generic synchronous PHY register write functionality. It is the + * responsibility of the system designer to provide the specific MDIO address + * pointer updates, etc. in order to accomplish this write operation. + * It will be assumed that the write has been completed by the time this + * function returns.*/ +void AQ_API_MDIO_Write +( + /*! Uniquely identifies the port within the system. AQ_Port must be + * defined to a whatever data type is suitable for the platform.*/ + AQ_Port PHY_ID, + /*! The address of the MMD within the target PHY. */ + unsigned int MMD, + /*! The 16-bit address of the PHY register being written. */ + unsigned int address, + /*! The 16-bits of data to write to the specified PHY register. */ + unsigned int data +); + +/*! Provides generic synchronous PHY register read functionality. It is the + * responsibility of the system designer to provide the specific MDIO address + * pointer updates, etc. in order to accomplish this read operation.*/ +unsigned int AQ_API_MDIO_Read +( + /*! Uniquely identifies the port within the system. AQ_Port must be + * defined to a whatever data type is suitable for the platform.*/ + AQ_Port PHY_ID, + /*! The address of the MMD within the target PHY. */ + unsigned int MMD, + /*! The 16-bit address of the PHY register being read. */ + unsigned int address +); + +#ifdef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE + +/*! Provides generic asynchronous/buffered PHY register write functionality. + * It is the responsibility of the system designer to provide the specific + * MDIO address pointer updates, etc. in order to accomplish this write + * operation. The write need not necessarily have been completed by the time + * this function returns. All register reads and writes to a particular PHY_ID + * that are requested by calling AQ_API_MDIO_BlockWrite or AQ_API_MDIO_BlockRead + * MUST be performed in the order that the calls are made. */ +void AQ_API_MDIO_BlockWrite +( + /*! Uniquely identifies the port within the system. AQ_Port must be + * defined to a whatever data type is suitable for the platform.*/ + AQ_Port PHY_ID, + /*! The address of the MMD within the target PHY. */ + unsigned int MMD, + /*! The 16-bit address of the PHY register being written. */ + unsigned int address, + /*! The 16-bits of data to write to the specified PHY register. */ + unsigned int data +); + +/*! Provides generic asynchronous/buffered PHY register read functionality. + * It is the responsibility of the system designer to provide the specific + * MDIO address pointer updates, etc. in order to accomplish this read + * operation. All register reads and writes to a particular PHY_ID that + * are requested by calling AQ_API_MDIO_BlockWrite or AQ_API_MDIO_BlockRead + * MUST be performed in the order that the calls are made. The register value + * may subsequently be fetched by calling AQ_API_MDIO_BlockOperationExecute.*/ +void AQ_API_MDIO_BlockRead +( + /*! Uniquely identifies the port within the system. AQ_Port must be + * defined to a whatever data type is suitable for the platform.*/ + AQ_Port PHY_ID, + /*! The address of the MMD within the target PHY. */ + unsigned int MMD, + /*! The 16-bit address of the PHY register being read. */ + unsigned int address +); + +/* Retrieve the results of all PHY register reads to PHY_ID previously + * requested via calls to AQ_API_MDIO_BlockRead. The read and write + * operations previously performed by calls to AQ_API_MDIO_BlockRead and + * AQ_API_MDIO_BlockRead must have all been completed by the time this + * function returns, in the order that the calls were performed. The + * return value is an array representing the fetched results of all + * pending calls to AQ_API_MDIO_BlockRead, in the order that the calls + * were performed. Callers should track the number of pending block + * reads to determine the size of the returned array. */ +unsigned int * AQ_API_MDIO_BlockOperationExecute +( + /*! Uniquely identifies the port within the system. AQ_Port must be + * defined to a whatever data type is suitable for the platform.*/ + AQ_Port PHY_ID +); + +/* Returns the maximum number of asynchronous/buffered PHY register + * read/write operations. Callers will call AQ_API_MDIO_BlockOperationExecute + * before issuing additional calls to AQ_API_MDIO_BlockWrite or + * AQ_API_MDIO_BlockRead to avoid a buffer overflow. */ +unsigned int AQ_API_MDIO_MaxBlockOperations +( +); + +#endif + +/*@}*/ + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/qca/aq-fw-download/src/include/AQ_PlatformRoutines.h b/qca/aq-fw-download/src/include/AQ_PlatformRoutines.h new file mode 100644 index 000000000..9a16d6408 --- /dev/null +++ b/qca/aq-fw-download/src/include/AQ_PlatformRoutines.h @@ -0,0 +1,71 @@ +/*AQ_PlatformRoutines.h*/ + +/************************************************************************************ +* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +* +* Description: +* +* Declares the platform interface functions that will be called by AQ_API +* functions. The platform integrator must provide the implementation of +* these functions. +* +************************************************************************************/ + +/*! \file + * Declares the platform interface functions that will be called by AQ_API + * functions. The platform integrator must provide the implementation of + * these functions. */ + + +#ifndef AQ_PHY_PLATFORMROUTINES_TOKEN +#define AQ_PHY_PLATFORMROUTINES_TOKEN + +#include + +#include "AQ_API.h" +#include "AQ_User.h" +#include "AQ_ReturnCodes.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/******************************************************************* + Time Delay +*******************************************************************/ + +/*! \defgroup delay Time Delay + @{ +*/ + +/*! Returns after at least milliseconds have elapsed. This must be implemented + * in a platform-approriate way. AQ_API functions will call this function to + * block for the specified period of time. If necessary, PHY register reads + * may be performed on port to busy-wait. */ +void AQ_API_Wait +( + uint32_t milliseconds, /*!< The delay in milliseconds */ + AQ_API_Port* port /*!< The PHY to use if delay reads are necessary*/ +); + +/*@}*/ + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/qca/aq-fw-download/src/include/AQ_RegMacro.h b/qca/aq-fw-download/src/include/AQ_RegMacro.h new file mode 100644 index 000000000..8dcca522b --- /dev/null +++ b/qca/aq-fw-download/src/include/AQ_RegMacro.h @@ -0,0 +1,323 @@ +/* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +*/ +/*! \file + This file contains macros for accessing the AQ PHYs' registers + using the device-specific register map data structures and definitions. +*/ + +#ifndef AQ_REG_MACRO_TOKEN +#define AQ_REG_MACRO_TOKEN + +#include "AQ_PhyInterface.h" + + +#define AQ_API_ReadRegister(id,reg,wd) AQ_API_ReadRegister_DeviceRestricted(APPIA_HHD,id,reg,wd) + +#define AQ_API_ReadRegister_DeviceRestricted(devices,id,reg,wd) AQ_API_ReadRegister_Devs_ ## devices(id,reg,wd) + +#define AQ_API_ReadRegister_Devs_APPIA(id,reg,wd) \ + ((port->device == AQ_DEVICE_APPIA) ? AQ_API_MDIO_Read (id,reg ## _APPIA_mmdAddress,(reg ## _APPIA_baseRegisterAddress + wd)) : \ + (0)) + +#define AQ_API_ReadRegister_Devs_HHD(id,reg,wd) \ + ((port->device == AQ_DEVICE_HHD) ? AQ_API_MDIO_Read (id,reg ## _HHD_mmdAddress,(reg ## _HHD_baseRegisterAddress + wd)) : \ + (0)) + +#define AQ_API_ReadRegister_Devs_APPIA_HHD(id,reg,wd) \ + ((port->device == AQ_DEVICE_HHD) ? AQ_API_MDIO_Read (id,reg ## _HHD_mmdAddress,(reg ## _HHD_baseRegisterAddress + wd)) : \ + ((port->device == AQ_DEVICE_APPIA) ? AQ_API_MDIO_Read (id,reg ## _APPIA_mmdAddress,(reg ## _APPIA_baseRegisterAddress + wd)) : \ + (0))) + +#define AQ_API_ReadRegister_Devs_HHD_APPIA(id,reg,wd) AQ_API_ReadRegister_Devs_APPIA_HHD(id,reg,wd) + + +#define AQ_API_WriteRegister(id,reg,wd,value) AQ_API_WriteRegister_DeviceRestricted(APPIA_HHD,id,reg,wd,value) + +#define AQ_API_WriteRegister_DeviceRestricted(devices,id,reg,wd,value) AQ_API_WriteRegister_Devs_ ## devices(id,reg,wd,value) + +#define AQ_API_WriteRegister_Devs_APPIA(id,reg,wd,value) \ + ((port->device == AQ_DEVICE_APPIA) ? AQ_API_MDIO_Write (id,reg ## _APPIA_mmdAddress,(reg ## _APPIA_baseRegisterAddress + wd),value) : \ + ((void)0)) + +#define AQ_API_WriteRegister_Devs_HHD(id,reg,wd,value) \ + ((port->device == AQ_DEVICE_HHD) ? AQ_API_MDIO_Write (id,reg ## _HHD_mmdAddress,(reg ## _HHD_baseRegisterAddress + wd),value) : \ + ((void)0)) + +#define AQ_API_WriteRegister_Devs_APPIA_HHD(id,reg,wd,value) \ + ((port->device == AQ_DEVICE_HHD) ? AQ_API_MDIO_Write (id,reg ## _HHD_mmdAddress,(reg ## _HHD_baseRegisterAddress + wd),value) : \ + ((port->device == AQ_DEVICE_APPIA) ? AQ_API_MDIO_Write (id,reg ## _APPIA_mmdAddress,(reg ## _APPIA_baseRegisterAddress + wd),value) : \ + ((void)0))) + +#define AQ_API_WriteRegister_Devs_HHD_APPIA(id,reg,wd,value) AQ_API_WriteRegister_Devs_APPIA_HHD(id,reg,wd,value) + + +#ifdef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE + +#define AQ_API_BlockReadRegister(id,reg,wd) AQ_API_BlockReadRegister_DeviceRestricted(APPIA_HHD,id,reg,wd) + +#define AQ_API_BlockReadRegister_DeviceRestricted(devices,id,reg,wd) AQ_API_BlockReadRegister_Devs_ ## devices(id,reg,wd) + +#define AQ_API_BlockReadRegister_Devs_APPIA(id,reg,wd) \ + ((port->device == AQ_DEVICE_APPIA) ? AQ_API_MDIO_BlockRead (id,reg ## _APPIA_mmdAddress,(reg ## _APPIA_baseRegisterAddress + wd)) : \ + ((void)0)) + +#define AQ_API_BlockReadRegister_Devs_HHD(id,reg,wd) \ + ((port->device == AQ_DEVICE_HHD) ? AQ_API_MDIO_BlockRead (id,reg ## _HHD_mmdAddress,(reg ## _HHD_baseRegisterAddress + wd)) : \ + ((void)0)) + +#define AQ_API_BlockReadRegister_Devs_APPIA_HHD(id,reg,wd) \ + ((port->device == AQ_DEVICE_HHD) ? AQ_API_MDIO_BlockRead (id,reg ## _HHD_mmdAddress,(reg ## _HHD_baseRegisterAddress + wd)) : \ + ((port->device == AQ_DEVICE_APPIA) ? AQ_API_MDIO_BlockRead (id,reg ## _APPIA_mmdAddress,(reg ## _APPIA_baseRegisterAddress + wd)) : \ + ((void)0))) + +#define AQ_API_BlockReadRegister_Devs_HHD_APPIA(id,reg,wd) AQ_API_BlockReadRegister_Devs_APPIA_HHD(id,reg,wd) + + +#define AQ_API_BlockWriteRegister(id,reg,wd,value) AQ_API_BlockWriteRegister_DeviceRestricted(APPIA_HHD,id,reg,wd,value) + +#define AQ_API_BlockWriteRegister_DeviceRestricted(devices,id,reg,wd,value) AQ_API_BlockWriteRegister_Devs_ ## devices(id,reg,wd,value) + +#define AQ_API_BlockWriteRegister_Devs_APPIA(id,reg,wd,value) \ + ((port->device == AQ_DEVICE_APPIA) ? AQ_API_MDIO_BlockWrite (id,reg ## _APPIA_mmdAddress,(reg ## _APPIA_baseRegisterAddress + wd),value) : \ + ((void)0)) + +#define AQ_API_BlockWriteRegister_Devs_HHD(id,reg,wd,value) \ + ((port->device == AQ_DEVICE_HHD) ? AQ_API_MDIO_BlockWrite (id,reg ## _HHD_mmdAddress,(reg ## _HHD_baseRegisterAddress + wd),value) : \ + ((void)0)) + +#define AQ_API_BlockWriteRegister_Devs_APPIA_HHD(id,reg,wd,value) \ + ((port->device == AQ_DEVICE_HHD) ? AQ_API_MDIO_BlockWrite (id,reg ## _HHD_mmdAddress,(reg ## _HHD_baseRegisterAddress + wd),value) : \ + ((port->device == AQ_DEVICE_APPIA) ? AQ_API_MDIO_BlockWrite (id,reg ## _APPIA_mmdAddress,(reg ## _APPIA_baseRegisterAddress + wd),value) : \ + ((void)0))) + +#define AQ_API_BlockWriteRegister_Devs_HHD_APPIA(id,reg,wd,value) AQ_API_BlockWriteRegister_Devs_APPIA_HHD(id,reg,wd,value) + + +#endif + +#define AQ_API_Variable(reg) AQ_API_Variable_DeviceRestricted(APPIA_HHD,reg) + +#define AQ_API_Variable_DeviceRestricted(devices,reg) AQ_API_Variable_Devs_ ## devices(reg) + +#define AQ_API_Variable_Devs_APPIA(reg) uint8_t _local ## reg ## _space[ sizeof(reg ## _BiggestVersion) ];\ + reg ## _APPIA* _local ## reg ## _APPIA = (reg ## _APPIA*) _local ## reg ## _space; \ + +#define AQ_API_Variable_Devs_HHD(reg) uint8_t _local ## reg ## _space[ sizeof(reg ## _BiggestVersion) ];\ + reg ## _HHD* _local ## reg ## _HHD = (reg ## _HHD*) _local ## reg ## _space; \ + +#define AQ_API_Variable_Devs_APPIA_HHD(reg) uint8_t _local ## reg ## _space[ sizeof(reg ## _BiggestVersion) ];\ + reg ## _APPIA* _local ## reg ## _APPIA = (reg ## _APPIA*) _local ## reg ## _space; \ + reg ## _HHD* _local ## reg ## _HHD = (reg ## _HHD*) _local ## reg ## _space; \ + +#define AQ_API_Variable_Devs_HHD_APPIA(reg) AQ_API_Variable_Devs_APPIA_HHD(reg) + + +#define AQ_API_DeclareLocalStruct(reg,localvar) AQ_API_DeclareLocalStruct_DeviceRestricted(APPIA_HHD,reg,localvar) + +#define AQ_API_DeclareLocalStruct_DeviceRestricted(devices,reg,localvar) AQ_API_DeclareLocalStruct_Devs_ ## devices(reg,localvar) + +#define AQ_API_DeclareLocalStruct_Devs_APPIA(reg,localvar) uint8_t localvar ## _space[ sizeof(reg ## _BiggestVersion) ];\ + reg ## _APPIA* localvar ## _APPIA = (reg ## _APPIA*) localvar ## _space; \ + +#define AQ_API_DeclareLocalStruct_Devs_HHD(reg,localvar) uint8_t localvar ## _space[ sizeof(reg ## _BiggestVersion) ];\ + reg ## _HHD* localvar ## _HHD = (reg ## _HHD*) localvar ## _space; \ + +#define AQ_API_DeclareLocalStruct_Devs_APPIA_HHD(reg,localvar) uint8_t localvar ## _space[ sizeof(reg ## _BiggestVersion) ];\ + reg ## _APPIA* localvar ## _APPIA = (reg ## _APPIA*) localvar ## _space; \ + reg ## _HHD* localvar ## _HHD = (reg ## _HHD*) localvar ## _space; \ + +#define AQ_API_DeclareLocalStruct_Devs_HHD_APPIA(reg,localvar) AQ_API_DeclareLocalStruct_Devs_APPIA_HHD(reg,localvar) + + +#define AQ_API_Set(id,reg,field,value) AQ_API_Set_DeviceRestricted(APPIA_HHD,id,reg,field,value) + +#define AQ_API_Set_DeviceRestricted(devices,id,reg,field,value) AQ_API_Set_Devs_ ## devices(id,reg,field,value) + +#define AQ_API_Set_Devs_APPIA(id,reg,field,value) { \ + switch (port->device) { \ + case AQ_DEVICE_APPIA: \ + _local ## reg ## _APPIA->word_ ## reg ## _APPIA_ ## field = AQ_API_ReadRegister_Devs_APPIA(id,reg,reg ## _APPIA_ ## field); \ + if (_local ## reg ## _APPIA->bits_ ## reg ## _APPIA_ ## field.field != value) \ + { \ + _local ## reg ## _APPIA->bits_ ## reg ## _APPIA_ ## field.field = value; \ + AQ_API_WriteRegister_Devs_APPIA(id,reg,reg ## _APPIA_ ## field,_local ## reg ## _APPIA->word_ ## reg ## _APPIA_ ## field); \ + } \ + break; \ + default: break; \ + } \ +} + +#define AQ_API_Set_Devs_HHD(id,reg,field,value) { \ + switch (port->device) { \ + case AQ_DEVICE_HHD: \ + _local ## reg ## _HHD->word_ ## reg ## _HHD_ ## field = AQ_API_ReadRegister_Devs_HHD(id,reg,reg ## _HHD_ ## field); \ + if (_local ## reg ## _HHD->bits_ ## reg ## _HHD_ ## field.field != value) \ + { \ + _local ## reg ## _HHD->bits_ ## reg ## _HHD_ ## field.field = value; \ + AQ_API_WriteRegister_Devs_HHD(id,reg,reg ## _HHD_ ## field,_local ## reg ## _HHD->word_ ## reg ## _HHD_ ## field); \ + } \ + break; \ + default: break; \ + } \ +} + +#define AQ_API_Set_Devs_APPIA_HHD(id,reg,field,value) { \ + switch (port->device) { \ + case AQ_DEVICE_APPIA: \ + _local ## reg ## _APPIA->word_ ## reg ## _APPIA_ ## field = AQ_API_ReadRegister_Devs_APPIA_HHD(id,reg,reg ## _APPIA_ ## field); \ + if (_local ## reg ## _APPIA->bits_ ## reg ## _APPIA_ ## field.field != value) \ + { \ + _local ## reg ## _APPIA->bits_ ## reg ## _APPIA_ ## field.field = value; \ + AQ_API_WriteRegister_Devs_APPIA_HHD(id,reg,reg ## _APPIA_ ## field,_local ## reg ## _APPIA->word_ ## reg ## _APPIA_ ## field); \ + } \ + break; \ + case AQ_DEVICE_HHD: \ + _local ## reg ## _HHD->word_ ## reg ## _HHD_ ## field = AQ_API_ReadRegister_Devs_APPIA_HHD(id,reg,reg ## _HHD_ ## field); \ + if (_local ## reg ## _HHD->bits_ ## reg ## _HHD_ ## field.field != value) \ + { \ + _local ## reg ## _HHD->bits_ ## reg ## _HHD_ ## field.field = value; \ + AQ_API_WriteRegister_Devs_APPIA_HHD(id,reg,reg ## _HHD_ ## field,_local ## reg ## _HHD->word_ ## reg ## _HHD_ ## field); \ + } \ + break; \ + default: break; \ + } \ +} + +#define AQ_API_Set_Devs_HHD_APPIA(id,reg,field,value) AQ_API_Set_Devs_APPIA_HHD(id,reg,field,value) + + +#define AQ_API_Get(id,reg,field,value) AQ_API_Get_DeviceRestricted(APPIA_HHD,id,reg,field,value) + +#define AQ_API_Get_DeviceRestricted(devices,id,reg,field,value) AQ_API_Get_Devs_ ## devices(id,reg,field,value) + +#define AQ_API_Get_Devs_APPIA(id,reg,field,value) { \ + switch (port->device) { \ + case AQ_DEVICE_APPIA: \ + _local ## reg ## _APPIA->word_ ## reg ## _APPIA_ ## field = AQ_API_ReadRegister_Devs_APPIA(id,reg,reg ## _APPIA_ ## field); \ + value = _local ## reg ## _APPIA->bits_ ## reg ## _APPIA_ ## field.field; \ + break; \ + default: value = 0; break; \ + } \ +} + +#define AQ_API_Get_Devs_HHD(id,reg,field,value) { \ + switch (port->device) { \ + case AQ_DEVICE_HHD: \ + _local ## reg ## _HHD->word_ ## reg ## _HHD_ ## field = AQ_API_ReadRegister_Devs_HHD(id,reg,reg ## _HHD_ ## field); \ + value = _local ## reg ## _HHD->bits_ ## reg ## _HHD_ ## field.field; \ + break; \ + default: value = 0; break; \ + } \ +} + +#define AQ_API_Get_Devs_APPIA_HHD(id,reg,field,value) { \ + switch (port->device) { \ + case AQ_DEVICE_APPIA: \ + _local ## reg ## _APPIA->word_ ## reg ## _APPIA_ ## field = AQ_API_ReadRegister_Devs_APPIA_HHD(id,reg,reg ## _APPIA_ ## field); \ + value = _local ## reg ## _APPIA->bits_ ## reg ## _APPIA_ ## field.field; \ + break; \ + case AQ_DEVICE_HHD: \ + _local ## reg ## _HHD->word_ ## reg ## _HHD_ ## field = AQ_API_ReadRegister_Devs_APPIA_HHD(id,reg,reg ## _HHD_ ## field); \ + value = _local ## reg ## _HHD->bits_ ## reg ## _HHD_ ## field.field; \ + break; \ + default: value = 0; break; \ + } \ +} + +#define AQ_API_Get_Devs_HHD_APPIA(id,reg,field,value) AQ_API_Get_Devs_APPIA_HHD(id,reg,field,value) + + +#define AQ_API_BitfieldOfLocalStruct(reg,localvar,field) AQ_API_BitfieldOfLocalStruct_DeviceRestricted(APPIA_HHD,reg,localvar,field) + +#define AQ_API_BitfieldOfLocalStruct_DeviceRestricted(devices,reg,localvar,field) AQ_API_BitfieldOfLocalStruct_Devs_ ## devices(reg,localvar,field) + +#define AQ_API_BitfieldOfLocalStruct_Devs_APPIA(reg,localvar,field) \ + ((port->device == AQ_DEVICE_APPIA) ? ((localvar ## _APPIA)->bits_ ## reg ## _APPIA ## _ ## field.field) : \ + (0)) + +#define AQ_API_BitfieldOfLocalStruct_Devs_HHD(reg,localvar,field) \ + ((port->device == AQ_DEVICE_HHD) ? ((localvar ## _HHD)->bits_ ## reg ## _HHD ## _ ## field.field) : \ + (0)) + +#define AQ_API_BitfieldOfLocalStruct_Devs_APPIA_HHD(reg,localvar,field) \ + ((port->device == AQ_DEVICE_HHD) ? ((localvar ## _HHD)->bits_ ## reg ## _HHD ## _ ## field.field) : \ + ((port->device == AQ_DEVICE_APPIA) ? ((localvar ## _APPIA)->bits_ ## reg ## _APPIA ## _ ## field.field) : \ + (0))) + +#define AQ_API_BitfieldOfLocalStruct_Devs_HHD_APPIA(reg,localvar,field) AQ_API_BitfieldOfLocalStruct_Devs_APPIA_HHD(reg,localvar,field) + + +#define AQ_API_AssignBitfieldOfLocalStruct(reg,localvar,field,value) AQ_API_AssignBitfieldOfLocalStruct_DeviceRestricted(APPIA_HHD,reg,localvar,field,value) + +#define AQ_API_AssignBitfieldOfLocalStruct_DeviceRestricted(devices,reg,localvar,field,value) AQ_API_AssignBitfieldOfLocalStruct_Devs_ ## devices(reg,localvar,field,value) + +#define AQ_API_AssignBitfieldOfLocalStruct_Devs_APPIA(reg,localvar,field,value) \ + ((port->device == AQ_DEVICE_APPIA) ? ((localvar ## _APPIA)->bits_ ## reg ## _APPIA ## _ ## field.field = value) : \ + (0)) + +#define AQ_API_AssignBitfieldOfLocalStruct_Devs_HHD(reg,localvar,field,value) \ + ((port->device == AQ_DEVICE_HHD) ? ((localvar ## _HHD)->bits_ ## reg ## _HHD ## _ ## field.field = value) : \ + (0)) + +#define AQ_API_AssignBitfieldOfLocalStruct_Devs_APPIA_HHD(reg,localvar,field,value) \ + ((port->device == AQ_DEVICE_HHD) ? ((localvar ## _HHD)->bits_ ## reg ## _HHD ## _ ## field.field = value) : \ + ((port->device == AQ_DEVICE_APPIA) ? ((localvar ## _APPIA)->bits_ ## reg ## _APPIA ## _ ## field.field = value) : \ + (0))) + +#define AQ_API_AssignBitfieldOfLocalStruct_Devs_HHD_APPIA(reg,localvar,field,value) AQ_API_AssignBitfieldOfLocalStruct_Devs_APPIA_HHD(reg,localvar,field,value) + + +#define AQ_API_WordOfLocalStruct(localvar,wd) AQ_API_WordOfLocalStruct_DeviceRestricted(APPIA_HHD,localvar,wd) + +#define AQ_API_WordOfLocalStruct_DeviceRestricted(devices,localvar,wd) AQ_API_WordOfLocalStruct_Devs_ ## devices(localvar,wd) + +#define AQ_API_WordOfLocalStruct_Devs_APPIA(localvar,wd) \ + ((port->device == AQ_DEVICE_APPIA) ? ((localvar ## _APPIA)->u ## wd.word_ ## wd) : \ + (0)) + +#define AQ_API_WordOfLocalStruct_Devs_HHD(localvar,wd) \ + ((port->device == AQ_DEVICE_HHD) ? ((localvar ## _HHD)->u ## wd.word_ ## wd) : \ + (0)) + +#define AQ_API_WordOfLocalStruct_Devs_APPIA_HHD(localvar,wd) \ + ((port->device == AQ_DEVICE_HHD) ? ((localvar ## _HHD)->u ## wd.word_ ## wd) : \ + ((port->device == AQ_DEVICE_APPIA) ? ((localvar ## _APPIA)->u ## wd.word_ ## wd) : \ + (0))) + +#define AQ_API_WordOfLocalStruct_Devs_HHD_APPIA(localvar,wd) AQ_API_WordOfLocalStruct_Devs_APPIA_HHD(localvar,wd) + + +#define AQ_API_AssignWordOfLocalStruct(localvar,wd,value) AQ_API_AssignWordOfLocalStruct_DeviceRestricted(APPIA_HHD,localvar,wd,value) + +#define AQ_API_AssignWordOfLocalStruct_DeviceRestricted(devices,localvar,wd,value) AQ_API_AssignWordOfLocalStruct_Devs_ ## devices(localvar,wd,value) + +#define AQ_API_AssignWordOfLocalStruct_Devs_APPIA(localvar,wd,value) \ + ((port->device == AQ_DEVICE_APPIA) ? ((localvar ## _APPIA)->u ## wd.word_ ## wd = value) : \ + (0)) + +#define AQ_API_AssignWordOfLocalStruct_Devs_HHD(localvar,wd,value) \ + ((port->device == AQ_DEVICE_HHD) ? ((localvar ## _HHD)->u ## wd.word_ ## wd = value) : \ + (0)) + +#define AQ_API_AssignWordOfLocalStruct_Devs_APPIA_HHD(localvar,wd,value) \ + ((port->device == AQ_DEVICE_HHD) ? ((localvar ## _HHD)->u ## wd.word_ ## wd = value) : \ + ((port->device == AQ_DEVICE_APPIA) ? ((localvar ## _APPIA)->u ## wd.word_ ## wd = value) : \ + (0))) + +#define AQ_API_AssignWordOfLocalStruct_Devs_HHD_APPIA(localvar,wd,value) AQ_API_AssignWordOfLocalStruct_Devs_APPIA_HHD(localvar,wd,value) + + +#endif + diff --git a/qca/aq-fw-download/src/include/AQ_ReturnCodes.h b/qca/aq-fw-download/src/include/AQ_ReturnCodes.h new file mode 100644 index 000000000..bff083b03 --- /dev/null +++ b/qca/aq-fw-download/src/include/AQ_ReturnCodes.h @@ -0,0 +1,113 @@ +/* AQ_ReturnCodes.h */ + +/************************************************************************************ +* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +* +* Description: +* +* This file defines the AQ_API functions' integral return codes. +* +* +************************************************************************************/ + +/*! \file + This file defines the AQ_API functions' integral return codes. +*/ + +#ifndef AQ_RETURNCODES_TOKEN +#define AQ_RETURNCODES_TOKEN + + +/*! \defgroup ReturnCodes + @{ +*/ + +/*! Most AQ_API functions return AQ_Retcode to report success or failure. + * The values used are defined as preprocessor symbols in AQ_ReturnCodes.h. + * Callers should prefer to test the return values by equivalence to these + * symbols, rather than using the integer values directly, as these may + * not be stable across releases. The set of possible return codes that may + * be returned by a particular API function can be found in the function's + * documentation, as well as information on how to interpret each of the + * possible return codes. */ +typedef unsigned int AQ_Retcode; + +/*! \defgroup Success + @{ */ +#define AQ_RET_OK 0 +/*@}*/ + + +/*! \defgroup GeneralErrors + @{ */ +#define AQ_RET_ERROR 100 +#define AQ_RET_UP_BUSY_TIMEOUT 101 +/*@}*/ + +/*! \defgroup FunctionSpecificResults + @{ */ +#define AQ_RET_FLASH_READY 200 +#define AQ_RET_FLASH_READINESS_TIMEOUT 204 + +#define AQ_RET_FLASHINTF_READY 201 +#define AQ_RET_FLASHINTF_NOTREADY 202 +#define AQ_RET_FLASHINTF_READINESS_TIMEOUT 203 + +#define AQ_RET_FLASH_TYPE_UNKNOWN 205 +#define AQ_RET_FLASH_TYPE_BAD 206 + +#define AQ_RET_FLASH_IMAGE_CORRUPT 207 +#define AQ_RET_FLASH_IMAGE_TOO_LARGE 208 +#define AQ_RET_FLASH_IMAGE_MISMATCH 209 + +#define AQ_RET_FLASH_PAGE_SIZE_CHANGED 210 + +#define AQ_RET_BOOTLOAD_PROVADDR_OOR 211 +#define AQ_RET_BOOTLOAD_NONUNIFORM_REGVALS 212 +#define AQ_RET_BOOTLOAD_CRC_MISMATCH 213 +#define AQ_RET_BOOTLOAD_PROVTABLE_TOO_LARGE 228 + +#define AQ_RET_LOOPBACK_BAD_ENTRY_STATE 214 + +#define AQ_RET_DEBUGTRACE_FREEZE_TIMEOUT 215 +#define AQ_RET_DEBUGTRACE_UNFREEZE_TIMEOUT 216 + +#define AQ_RET_CABLEDIAG_ALREADY_RUNNING 217 +#define AQ_RET_CABLEDIAG_STILL_RUNNING 218 +#define AQ_RET_CABLEDIAG_BAD_PAIRSTATUS 219 +#define AQ_RET_CABLEDIAG_RESULTS_ALREDY_COLLECTED 220 +#define AQ_RET_CABLEDIAG_BAD_NUM_SAMPLES 221 +#define AQ_RET_CABLEDIAG_REPORTEDPAIR_MISMATCH 222 +#define AQ_RET_CABLEDIAG_REPORTEDPAIR_OOR 223 +#define AQ_RET_CABLEDIAG_STARTED_PAIR_B 224 +#define AQ_RET_CABLEDIAG_STARTED_PAIR_C 225 +#define AQ_RET_CABLEDIAG_STARTED_PAIR_D 226 +#define AQ_RET_CABLEDIAG_TXENABLE_MISMATCH 227 + +#define AQ_RET_SERDESEYE_BAD_SERDES_MODE 229 +#define AQ_RET_SERDESEYE_BAD_MEAS_COUNT 230 +#define AQ_RET_SERDESEYE_MEAS_TIMEOUT 231 +#define AQ_RET_SERDESEYE_LANE_OOR 232 +#define AQ_RET_SERDESEYE_COORD_OOR 233 + +#define AQ_RET_PIFMAILBOX_ERROR 234 +#define AQ_RET_PIFMAILBOX_TIMEOUT 235 + +#define AQ_RET_SEC_TABLE_INDEX_OOR 236 +/*@}*/ + +/*@}*/ + +#endif diff --git a/qca/aq-fw-download/src/include/AQ_User.h b/qca/aq-fw-download/src/include/AQ_User.h new file mode 100644 index 000000000..c7526a7cb --- /dev/null +++ b/qca/aq-fw-download/src/include/AQ_User.h @@ -0,0 +1,97 @@ +/*AQ_User.h*/ + +/************************************************************************************ +* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +* +* Description: +* +* This file contains preprocessor symbol definitions and type definitions +* for the platform-integrator controlled compile-time AQ_API options. +* +************************************************************************************/ + +/*! \file + This file contains preprocessor symbol definitions and type definitions + for the platform-integrator controlled compile-time AQ_API options. +*/ + +#ifndef AQ_USER_TOKEN +#define AQ_USER_TOKEN + +/*! \defgroup User User Definitions +This module contains the definitions used to configure AQ_API behavior as desired. */ +/*@{*/ + + +/*! Specify the proper data type for AQ_Port. This will depend on the + * platform-specific implementation of the PHY register read/write functions.*/ +typedef unsigned int AQ_Port; + + +/*! If defined, AQ_API functions will print various error and info messages + * to stdout. If not, nothing will be printed and AQ_API.c will NOT include + * stdio.h. */ +#define AQ_VERBOSE + + +/*! If defined, the PHY interface supports block (asynchronous) read/write + * operation. If AQ_PHY_SUPPORTS_BLOCK_READ_WRITE is defined, then + * the API will call the block-operation functions and so implementations + * for each must be provided. If AQ_PHY_SUPPORTS_BLOCK_READ_WRITE is not + * defined, they will not be called, and need not be implemented. */ +#undef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE + + +/*! If defined, time.h exists, and so the associated functions wil be used to + * compute the elapsed time spent in a polling loop, to ensure that the + * maximum time-out period will not be exceeded. If not defined, then + * AQ_MDIO_READS_PER_SECOND will be used to calculate the minimum possible + * elapsed time. */ +#define AQ_TIME_T_EXISTS + + +/*! The maximum number of synchronous PHY register reads that can be performed + * per second. A worst case number can be derived as follows: + * + * AQ_MDIO_READS_PER_SECOND = MDIO Clock Frequency / 64 + * + * If using MDIO preamble suppression, multiply this number by 2 + * + * For instance, if a 5MHz MDIO clock is being used without preamble supression + * AQ_MDIO_READS_PER_SECOND = 78125 + * + * If AQ_TIME_T_EXISTS is defined, this will be ignored and need not be + * defined. If AQ_TIME_T_EXISTS is not defined, this must be defined. */ +#define AQ_MDIO_READS_PER_SECOND 78125 + + +/*! If defined, after writing to one of the registers that can trigger a + * processor-intensive MDIO operation, AQ_API functions will poll the + * the "processor intensive MDIO operation in progress" bit and wait for it + * to be zero before proceeding. */ +#define AQ_ENABLE_UP_BUSY_CHECKS + + +/*! If defined, the register map header files containing reverse-packed + * structs will be included. If not, the register map header files containing + * non-reverse-packed structs will be included. The proper choice is typically + * a function of the endianness of the platform; on big-endian systems the + * reverse-packed structs should be used, and on little-endian systems the + * non-reverse-packed structs should be used. */ +/*#define AQ_REVERSED_BITFIELD_ORDERING*/ + +/*@}*/ +#endif + diff --git a/qca/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers.h b/qca/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers.h new file mode 100644 index 000000000..a9485f5a4 --- /dev/null +++ b/qca/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers.h @@ -0,0 +1,5581 @@ +/*! \file +* This file contains the data structures and doxygen comments +* for the Global Registers block. + */ + +/*! \addtogroup registerMap + @{ +*/ + +/*! \defgroup Global_registers Global Registers +* This module contains the data structures and doxygen comments +* for the Global Registers block. + */ +/*********************************************************************** +* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +* +* $Date: 2014/04/08 $ +* +* $Label: $ +* +* Description: +* +* This file contains the c header structures for the registers contained in the Global Registers block. +* +* The bit fields in this structure are from LSbit to MSbit +* +***********************************************************************/ + + +/*@{*/ +#ifndef AQ_APPIA_GLOBAL_REGS_HEADER +#define AQ_APPIA_GLOBAL_REGS_HEADER + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Control 1: 1E.0000 */ +/* Global Standard Control 1: 1E.0000 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Control 1 */ + union + { + struct + { + unsigned int reserved1 : 11; + /*! \brief 1E.0000.B R/WPD Low Power + AQ_GlobalStandardControl_1_APPIA.u0.bits_0.lowPower + + Provisionable Default = 0x0 + + 1 = Low-power mode + 0 = Normal operation + + + Notes: + A one written to this register causes the chip to enter low-power mode. This bit puts the entire chip in low-power mode, with only the MDIO and microprocessor functioning, and turns off the analog front-end: i.e. places it in high-impedance mode. Setting this bit also sets all of the Low Power bits in the other MMDs. */ + unsigned int lowPower : 1; /* 1E.0000.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Low-power mode + 0 = Normal operation + */ + unsigned int reserved0 : 2; + /*! \brief 1E.0000.E R/WSC Hard Reset + AQ_GlobalStandardControl_1_APPIA.u0.bits_0.hardReset + + Default = 0x0 + + 1 = Global hard reset + 0 = Normal operation + + + Notes: + Setting this bit initiates a global hard reset, equivalent to pulling the reset pin low. This is a level sensitive pin that connects into the power-on reset generation circuitry to initiate a complete power-on reset. */ + unsigned int hardReset : 1; /* 1E.0000.E R/WSC Default = 0x0 */ + /* 1 = Global hard reset + 0 = Normal operation + */ + /*! \brief 1E.0000.F R/WSC Soft Reset + AQ_GlobalStandardControl_1_APPIA.u0.bits_0.softReset + + Default = 0x1 + + 1 = Global soft reset + 0 = Normal operation + + + Notes: + Setting this bit initiates a global soft reset on all of the digital logic, including the microprocessor. Upon completion of the reset sequence, this bit is set back to 0. */ + unsigned int softReset : 1; /* 1E.0000.F R/WSC Default = 0x1 */ + /* 1 = Global soft reset + 0 = Normal operation + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardControl_1_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Device Identifier: 1E.0002 */ +/* Global Standard Device Identifier: 1E.0002 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Device Identifier */ + union + { + struct + { + /*! \brief 1E.0002.F:0 RO Device ID MSW [1F:10] + AQ_GlobalStandardDeviceIdentifier_APPIA.u0.bits_0.deviceIdMSW + + + + Bits 31 - 16 of Device ID + */ + unsigned int deviceIdMSW : 16; /* 1E.0002.F:0 RO */ + /* Bits 31 - 16 of Device ID */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Standard Device Identifier */ + union + { + struct + { + /*! \brief 1E.0003.F:0 RO Device ID LSW [F:0] + AQ_GlobalStandardDeviceIdentifier_APPIA.u1.bits_1.deviceIdLSW + + + + Bits 15 - 0 of Device ID + */ + unsigned int deviceIdLSW : 16; /* 1E.0003.F:0 RO */ + /* Bits 15 - 0 of Device ID */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalStandardDeviceIdentifier_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Devices in Package: 1E.0005 */ +/* Global Standard Devices in Package: 1E.0005 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Devices in Package */ + union + { + struct + { + /*! \brief 1E.0005.0 ROS Clause 22 Registers Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.clause_22RegistersPresent + + Default = 0x0 + + 1 = Clause 22 registers are present in package + 0 = Clause 22 registers are not present in package + + Notes: + This is always set to 0 in the PHY, as there are no Clause 22 registers in the device. */ + unsigned int clause_22RegistersPresent : 1; /* 1E.0005.0 ROS Default = 0x0 */ + /* 1 = Clause 22 registers are present in package + 0 = Clause 22 registers are not present in package */ + /*! \brief 1E.0005.1 ROS PMA Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.pmaPresent + + Default = 0x1 + + 1 = PMA is present in package + 0 = PMA is not present + + Notes: + This is always set to 1 as there is PMA functionality in the PHY. */ + unsigned int pmaPresent : 1; /* 1E.0005.1 ROS Default = 0x1 */ + /* 1 = PMA is present in package + 0 = PMA is not present */ + /*! \brief 1E.0005.2 ROS WIS Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.wisPresent + + Default = 0x0 + + 1 = WIS is present in package + 0 = WIS is not present in package + + Notes: + This is always set to 0, as there is no WIS functionality in the PHY. */ + unsigned int wisPresent : 1; /* 1E.0005.2 ROS Default = 0x0 */ + /* 1 = WIS is present in package + 0 = WIS is not present in package */ + /*! \brief 1E.0005.3 ROS PCS Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.pcsPresent + + Default = 0x1 + + 1 = PCS is present in package + 0 = PCS is not present in package + + Notes: + This is always set to 1 as there is PCS functionality in the PHY. */ + unsigned int pcsPresent : 1; /* 1E.0005.3 ROS Default = 0x1 */ + /* 1 = PCS is present in package + 0 = PCS is not present in package */ + /*! \brief 1E.0005.4 ROS PHY XS Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.phyXS_Present + + Default = 0x1 + + 1 = PHY XS is present in package + 0 = PHY XS is not present in package + + Notes: + This is always set to 1 as there is a PHY XS interface in the PHY. */ + unsigned int phyXS_Present : 1; /* 1E.0005.4 ROS Default = 0x1 */ + /* 1 = PHY XS is present in package + 0 = PHY XS is not present in package */ + /*! \brief 1E.0005.5 ROS DTE XS Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.dteXsPresent + + Default = 0x0 + + 1 = DTE XS is present in package + 0 = DTE XS is not present in package + + + Notes: + This is always set to 0, as there is no DTE XAUI interface in the PHY. */ + unsigned int dteXsPresent : 1; /* 1E.0005.5 ROS Default = 0x0 */ + /* 1 = DTE XS is present in package + 0 = DTE XS is not present in package + */ + /*! \brief 1E.0005.6 ROS TC Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.tcPresent + + Default = 0x0 + + 1 = TC is present in package + 0 = TC is not present in package + + Notes: + This is always set to 0, as there is no TC functionality in the PHY. */ + unsigned int tcPresent : 1; /* 1E.0005.6 ROS Default = 0x0 */ + /* 1 = TC is present in package + 0 = TC is not present in package */ + /*! \brief 1E.0005.7 ROS Autonegotiation Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.autonegotiationPresent + + Default = 0x1 + + 1 = Autonegotiation is present in package + 0 = Autonegotiation is not present in package + + Notes: + This is always set to 1, as there is Autonegotiation in the PHY. */ + unsigned int autonegotiationPresent : 1; /* 1E.0005.7 ROS Default = 0x1 */ + /* 1 = Autonegotiation is present in package + 0 = Autonegotiation is not present in package */ + unsigned int reserved0 : 8; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardDevicesInPackage_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Vendor Devices in Package: 1E.0006 */ +/* Global Standard Vendor Devices in Package: 1E.0006 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Vendor Devices in Package */ + union + { + struct + { + unsigned int reserved0 : 13; + /*! \brief 1E.0006.D ROS Clause 22 Extension Present + AQ_GlobalStandardVendorDevicesInPackage_APPIA.u0.bits_0.clause_22ExtensionPresent + + Default = 0x1 + + 1 = Clause 22 Extension is present in package + 0 = Clause 22 Extension is not present in package + + Notes: + This is always set to 1 as the PHY utilizes this device for the GbE registers. */ + unsigned int clause_22ExtensionPresent : 1; /* 1E.0006.D ROS Default = 0x1 */ + /* 1 = Clause 22 Extension is present in package + 0 = Clause 22 Extension is not present in package */ + /*! \brief 1E.0006.E ROS Vendor Specific Device #1 Present + AQ_GlobalStandardVendorDevicesInPackage_APPIA.u0.bits_0.vendorSpecificDevice_1Present + + Default = 0x1 + + 1 = Device #1 is present in package + 0 = Device #1 is not present in package + + Notes: + This is always set to 1 as the PHY utilizes this device for the global control registers. */ + unsigned int vendorSpecificDevice_1Present : 1; /* 1E.0006.E ROS Default = 0x1 */ + /* 1 = Device #1 is present in package + 0 = Device #1 is not present in package */ + /*! \brief 1E.0006.F ROS Vendor Specific Device #2 Present + AQ_GlobalStandardVendorDevicesInPackage_APPIA.u0.bits_0.vendorSpecificDevice_2Present + + Default = 0x1 + + 1 = Device #2 is present in package + 0 = Device #2 is not present in package + + Notes: + This is always set to 1 as the PHY utilizes this device for the DSP PMA registers. */ + unsigned int vendorSpecificDevice_2Present : 1; /* 1E.0006.F ROS Default = 0x1 */ + /* 1 = Device #2 is present in package + 0 = Device #2 is not present in package */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardVendorDevicesInPackage_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Status 2: 1E.0008 */ +/* Global Standard Status 2: 1E.0008 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Status 2 */ + union + { + struct + { + unsigned int reserved0 : 14; + /*! \brief 1E.0008.F:E ROS Device Present [1:0] + AQ_GlobalStandardStatus_2_APPIA.u0.bits_0.devicePresent + + Default = 0x2 + + [F:E] + 0x3 = No device at this address + 0x2 = Device present at this address + 0x1 = No device at this address + 0x0 = No device at this address + + Notes: + This field is always set to 0x2, as the Global MMD resides here in the PHY. */ + unsigned int devicePresent : 2; /* 1E.0008.F:E ROS Default = 0x2 */ + /* [F:E] + 0x3 = No device at this address + 0x2 = Device present at this address + 0x1 = No device at this address + 0x0 = No device at this address */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardStatus_2_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Package Identifier: 1E.000E */ +/* Global Standard Package Identifier: 1E.000E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Package Identifier */ + union + { + struct + { + /*! \brief 1E.000E.F:0 RO Package ID MSW [1F:10] + AQ_GlobalStandardPackageIdentifier_APPIA.u0.bits_0.packageIdMSW + + + + Bits 31- 16 of Package ID + */ + unsigned int packageIdMSW : 16; /* 1E.000E.F:0 RO */ + /* Bits 31- 16 of Package ID */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Standard Package Identifier */ + union + { + struct + { + /*! \brief 1E.000F.F:0 RO Package ID LSW [F:0] + AQ_GlobalStandardPackageIdentifier_APPIA.u1.bits_1.packageIdLSW + + + + Bits 15 - 0 of Package ID + */ + unsigned int packageIdLSW : 16; /* 1E.000F.F:0 RO */ + /* Bits 15 - 0 of Package ID */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalStandardPackageIdentifier_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Firmware ID: 1E.0020 */ +/* Global Firmware ID: 1E.0020 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Firmware ID */ + union + { + struct + { + /*! \brief 1E.0020.7:0 RO Firmware Minor Revision Number [7:0] + AQ_GlobalFirmwareID_APPIA.u0.bits_0.firmwareMinorRevisionNumber + + + + [7:0] = Minor revision number + + Notes: + + + The lower six bits of major and minor firmware revision are exchanged in autonegotiation when the PHYID message is sent. */ + unsigned int firmwareMinorRevisionNumber : 8; /* 1E.0020.7:0 RO */ + /* [7:0] = Minor revision number */ + /*! \brief 1E.0020.F:8 RO Firmware Major Revision Number [7:0] + AQ_GlobalFirmwareID_APPIA.u0.bits_0.firmwareMajorRevisionNumber + + + + [F:8] = Major revision number + + Notes: + + + The lower six bits of major and minor firmware revision are exchanged in autonegotiation when the PHYID message is sent. */ + unsigned int firmwareMajorRevisionNumber : 8; /* 1E.0020.F:8 RO */ + /* [F:8] = Major revision number */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalFirmwareID_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Chip Identification: 1E.0021 */ +/* Global Chip Identification: 1E.0021 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Chip Identification */ + union + { + struct + { + /*! \brief 1E.0021.F:0 RO Chip Identification [F:0] + AQ_GlobalChipIdentification_APPIA.u0.bits_0.chipIdentification + + + + Hardware Chip ID + + Notes: + This value is a hard-coded chip ID */ + unsigned int chipIdentification : 16; /* 1E.0021.F:0 RO */ + /* Hardware Chip ID */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalChipIdentification_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Chip Revision: 1E.0022 */ +/* Global Chip Revision: 1E.0022 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Chip Revision */ + union + { + struct + { + /*! \brief 1E.0022.F:0 RO Chip Revision [F:0] + AQ_GlobalChipRevision_APPIA.u0.bits_0.chipRevision + + + + Hardware Chip Revision + + Notes: + This value is a hard-coded chip revision */ + unsigned int chipRevision : 16; /* 1E.0022.F:0 RO */ + /* Hardware Chip Revision */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalChipRevision_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global NVR Interface: 1E.0100 */ +/* Global NVR Interface: 1E.0100 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0100.7:0 R/W NVR Opcode [7:0] + AQ_GlobalNvrInterface_APPIA.u0.bits_0.nvrOpcode + + Default = 0x03 + + NVR instruction opcode + + */ + unsigned int nvrOpcode : 8; /* 1E.0100.7:0 R/W Default = 0x03 */ + /* NVR instruction opcode + */ + /*! \brief 1E.0100.8 RO NVR Busy + AQ_GlobalNvrInterface_APPIA.u0.bits_0.nvrBusy + + + + 1 = NVR is busy + 0 = NVR is ready + + + Notes: + When set to 1, the NVR is busy. A new NVR operation should not occur until this bit is 0. If the NVR clock is greater than 64/63 of the MDIO clock, this bit never needs to be polled when operating over the MDIO. */ + unsigned int nvrBusy : 1; /* 1E.0100.8 RO */ + /* 1 = NVR is busy + 0 = NVR is ready + */ + unsigned int reserved1 : 1; + /*! \brief 1E.0100.A R/W NVR Burst + AQ_GlobalNvrInterface_APPIA.u0.bits_0.nvrBurst + + Default = 0x0 + + 0 = Single read or write operation of up to 4 bytes + 1 = Burst operation + + + Notes: + When this bit is set, the operation is a burst operation where more than 32-bits is read from the NVR or written to the NVR. This bit should be set to one until the last burst in the read or write operation, when it should be set to zero. It operates by gating the SPI clock, and not restarting it until new data is ready to be written, or the previous contents have been read. Each burst of data requires the NVR Execute Operation bit to be set to initiate the next phase. */ + unsigned int nvrBurst : 1; /* 1E.0100.A R/W Default = 0x0 */ + /* 0 = Single read or write operation of up to 4 bytes + 1 = Burst operation + */ + unsigned int reserved0 : 1; + /*! \brief 1E.0100.C R/WSC Reset NVR CRC + AQ_GlobalNvrInterface_APPIA.u0.bits_0.resetNvrCrc + + Default = 0x0 + + 1 = Reset NVR Mailbox CRC calculation register + + + Notes: + To prevent an erroneous answer, this bit should not be set at the same time the See NVR Operation Valid bit is set. */ + unsigned int resetNvrCrc : 1; /* 1E.0100.C R/WSC Default = 0x0 */ + /* 1 = Reset NVR Mailbox CRC calculation register + */ + /*! \brief 1E.0100.D R/W Freeze NVR CRC + AQ_GlobalNvrInterface_APPIA.u0.bits_0.freezeNvrCrc + + Default = 0x0 + + 1 = Freeze NVR Mailbox CRC calculation register + + + Notes: + To prevent an erroneous answer, this bit should not be set at the same time the See NVR Operation Valid bit is set. */ + unsigned int freezeNvrCrc : 1; /* 1E.0100.D R/W Default = 0x0 */ + /* 1 = Freeze NVR Mailbox CRC calculation register + */ + /*! \brief 1E.0100.E R/W NVR Write Mode + AQ_GlobalNvrInterface_APPIA.u0.bits_0.nvrWriteMode + + Default = 0x0 + + 1 = Write to NVR + 0 = Read from NVR + + */ + unsigned int nvrWriteMode : 1; /* 1E.0100.E R/W Default = 0x0 */ + /* 1 = Write to NVR + 0 = Read from NVR + */ + /*! \brief 1E.0100.F R/WSC NVR Execute Operation + AQ_GlobalNvrInterface_APPIA.u0.bits_0.nvrExecuteOperation + + Default = 0x0 + + 1 = Start NVR Operation + + + Notes: + When set to 1, the NVR operation will begin. Ensure that the uP is stalled using the See MCP Run Stall bit to ensure no NVR contention. */ + unsigned int nvrExecuteOperation : 1; /* 1E.0100.F R/WSC Default = 0x0 */ + /* 1 = Start NVR Operation + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0101.F:0 RO NVR Mailbox CRC [F:0] + AQ_GlobalNvrInterface_APPIA.u1.bits_1.nvrMailboxCrc + + + + The running CRC-16 of everything passing through the NVR interface + + + Notes: + The CRC-16 over all data written or read through the NVR interface. The CRC-16 is calculated by dividing the data by: + x^16 + x^12 + x^5 + 1 */ + unsigned int nvrMailboxCrc : 16; /* 1E.0101.F:0 RO */ + /* The running CRC-16 of everything passing through the NVR interface + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0102.7:0 R/W NVR Address MSW [17:10] + AQ_GlobalNvrInterface_APPIA.u2.bits_2.nvrAddressMSW + + Default = 0x00 + + NVR address MSW bits [17:10] + + + Notes: + The address of where to read and write from in the NVR. This is self-incrementing and will automatically increment after each read or write operation. The increment amount is based on the data length (i.e. increments by 4 if the data length is 4 bytes) */ + unsigned int nvrAddressMSW : 8; /* 1E.0102.7:0 R/W Default = 0x00 */ + /* NVR address MSW bits [17:10] + */ + unsigned int reserved0 : 8; + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0103.F:0 R/W NVR Address LSW [F:0] + AQ_GlobalNvrInterface_APPIA.u3.bits_3.nvrAddressLSW + + Default = 0x0000 + + NVR address LSW bits [F:0] + + + Notes: + The address of where to read and write from in the NVR. This is self-incrementing and will automatically increment after each read or write operation. */ + unsigned int nvrAddressLSW : 16; /* 1E.0103.F:0 R/W Default = 0x0000 */ + /* NVR address LSW bits [F:0] + */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0104.F:0 R/W NVR Data MSW [1F:10] + AQ_GlobalNvrInterface_APPIA.u4.bits_4.nvrDataMSW + + Default = 0x0000 + + NVR data MSW bits [1F:10] + + + Notes: + Data is stored and read-out from these registers in little-endian format for operations such as FLASH device ID, and for programming the processor. + + For instance the 64K Atmel device code reads out as two bytes 0x651F into the LSW register, whereas the datasheet indicates that 1F is the first byte read, followed by 65 as the second byte. + + To burst read and write these 4 bytes in the correct order (where DD is written to address x), they should be stored as: + + AA BB in the MSW + CC DD in the LSW. */ + unsigned int nvrDataMSW : 16; /* 1E.0104.F:0 R/W Default = 0x0000 */ + /* NVR data MSW bits [1F:10] + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0105.F:0 R/W NVR Data LSW [F:0] + AQ_GlobalNvrInterface_APPIA.u5.bits_5.nvrDataLSW + + Default = 0x0000 + + NVR data LSW bits [F:0] + + + Notes: + Data is stored and read-out from these registers in little-endian format for operations such as FLASH device ID, and for programming the processor. + + For instance the 64K Atmel device code reads out as two bytes 0x651F into the LSW register, whereas the datasheet indicates that 1F is the first byte read, followed by 65 as the second byte. + To burst read and write these 4 bytes in the correct order (where DD is written to address x), they should be stored as: + + AA BB in the MSW + CC DD in the LSW. */ + unsigned int nvrDataLSW : 16; /* 1E.0105.F:0 R/W Default = 0x0000 */ + /* NVR data LSW bits [F:0] + */ + } bits_5; + uint16_t word_5; + } u5; +} AQ_GlobalNvrInterface_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Mailbox Interface: 1E.0200 */ +/* Global Mailbox Interface: 1E.0200 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Mailbox Interface */ + union + { + struct + { + unsigned int reserved2 : 8; + /*! \brief 1E.0200.8 RO uP Mailbox Busy + AQ_GlobalMailboxInterface_APPIA.u0.bits_0.upMailboxBusy + + + + 1 = uP mailbox busy + 0 = uP mailbox ready + + + Notes: + In general the uP will respond within a few processor cycles to any PIF slave request, much faster than the MDIO. If the busy is asserted over multiple MDIO polling cycles, then a H/W error may have occured and a Global S/W reset or uP reset is required. */ + unsigned int upMailboxBusy : 1; /* 1E.0200.8 RO */ + /* 1 = uP mailbox busy + 0 = uP mailbox ready + */ + unsigned int reserved1 : 3; + /*! \brief 1E.0200.C R/WSC Reset uP Mailbox CRC + AQ_GlobalMailboxInterface_APPIA.u0.bits_0.resetUpMailboxCrc + + Default = 0x0 + + 1 = Reset uP mailbox CRC calculation register + + */ + unsigned int resetUpMailboxCrc : 1; /* 1E.0200.C R/WSC Default = 0x0 */ + /* 1 = Reset uP mailbox CRC calculation register + */ + unsigned int reserved0 : 1; + /*! \brief 1E.0200.E R/W uP Mailbox Write Mode + AQ_GlobalMailboxInterface_APPIA.u0.bits_0.upMailboxWriteMode + + Default = 0x0 + + 1 = Write + 0 = Read + + + Notes: + Mailbox direction */ + unsigned int upMailboxWriteMode : 1; /* 1E.0200.E R/W Default = 0x0 */ + /* 1 = Write + 0 = Read + */ + /*! \brief 1E.0200.F R/WSC uP Mailbox Execute Operation + AQ_GlobalMailboxInterface_APPIA.u0.bits_0.upMailboxExecuteOperation + + Default = 0x0 + + 1 = Start of mailbox Operation + + + Notes: + Indicates mailbox is loaded and ready */ + unsigned int upMailboxExecuteOperation : 1; /* 1E.0200.F R/WSC Default = 0x0 */ + /* 1 = Start of mailbox Operation + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0201.F:0 RO uP Mailbox CRC [F:0] + AQ_GlobalMailboxInterface_APPIA.u1.bits_1.upMailboxCrc + + + + The running CRC-16 of everything passing through the mailbox interface + + */ + unsigned int upMailboxCrc : 16; /* 1E.0201.F:0 RO */ + /* The running CRC-16 of everything passing through the mailbox interface + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0202.F:0 R/W uP Mailbox Address MSW [1F:10] + AQ_GlobalMailboxInterface_APPIA.u2.bits_2.upMailboxAddressMSW + + Default = 0x0000 + + uP Mailbox MSW address + + + Notes: + The address of where to read and write from in the Microcontroller Mailbox. This is self-incrementing and automatically increments after each read and write operation.PHY */ + unsigned int upMailboxAddressMSW : 16; /* 1E.0202.F:0 R/W Default = 0x0000 */ + /* uP Mailbox MSW address + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0203.1:0 RO uP Mailbox Address LSW Don't Care [1:0] + AQ_GlobalMailboxInterface_APPIA.u3.bits_3.upMailboxAddressLSW_Don_tCare + + + + Least significant uP LSW Mailbox address bits [1:0] + + + Notes: + These bits are always set to 0 since each memory access is on a 4-byte boundary. */ + unsigned int upMailboxAddressLSW_Don_tCare : 2; /* 1E.0203.1:0 RO */ + /* Least significant uP LSW Mailbox address bits [1:0] + */ + /*! \brief 1E.0203.F:2 R/W uP Mailbox Address LSW [F:2] + AQ_GlobalMailboxInterface_APPIA.u3.bits_3.upMailboxAddressLSW + + Default = 0x0000 + + uP LSW Mailbox address [F:2] + + + Notes: + The address of where to read and write from in the Microcontroller Mailbox. This is self-incrementing and automatically increments after each read and write operation.PHY */ + unsigned int upMailboxAddressLSW : 14; /* 1E.0203.F:2 R/W Default = 0x0000 */ + /* uP LSW Mailbox address [F:2] + */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0204.F:0 R/W uP Mailbox Data MSW [1F:10] + AQ_GlobalMailboxInterface_APPIA.u4.bits_4.upMailboxDataMSW + + Default = 0x0000 + + uP Mailbox data MSW + + */ + unsigned int upMailboxDataMSW : 16; /* 1E.0204.F:0 R/W Default = 0x0000 */ + /* uP Mailbox data MSW + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0205.F:0 R/W uP Mailbox Data LSW [F:0] + AQ_GlobalMailboxInterface_APPIA.u5.bits_5.upMailboxDataLSW + + Default = 0x0000 + + uP Mailbox data LSW + + */ + unsigned int upMailboxDataLSW : 16; /* 1E.0205.F:0 R/W Default = 0x0000 */ + /* uP Mailbox data LSW + */ + } bits_5; + uint16_t word_5; + } u5; +} AQ_GlobalMailboxInterface_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Microprocessor Scratch Pad: 1E.0300 */ +/* Global Microprocessor Scratch Pad: 1E.0300 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Microprocessor Scratch Pad */ + union + { + struct + { + /*! \brief 1E.0300.F:0 R/W Scratch Pad 1[F:0] + AQ_GlobalMicroprocessorScratchPad_APPIA.u0.bits_0.scratchPad_1 + + Default = 0x0000 + + General Purpose Scratch Pad1 + */ + unsigned int scratchPad_1 : 16; /* 1E.0300.F:0 R/W Default = 0x0000 */ + /* General Purpose Scratch Pad1 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Microprocessor Scratch Pad */ + union + { + struct + { + /*! \brief 1E.0301.F:0 R/W Scratch Pad 2 [F:0] + AQ_GlobalMicroprocessorScratchPad_APPIA.u1.bits_1.scratchPad_2 + + Default = 0x0000 + + General Purpose Scratch P + */ + unsigned int scratchPad_2 : 16; /* 1E.0301.F:0 R/W Default = 0x0000 */ + /* General Purpose Scratch P */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalMicroprocessorScratchPad_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Control: 1E.C000 */ +/* Global Control: 1E.C000 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Control */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Control */ + union + { + struct + { + /*! \brief 1E.C001.0 R/W uP Run Stall + AQ_GlobalControl_APPIA.u1.bits_1.upRunStall + + Default = 0x0 + + 1 = uP Run Stall + 0 = uP normal mode + + + Notes: + Deactivates the uP. The PIF slave bus for inbound requests will still be active. This bit is muliplexed with the "MDIO Boot Load" pin with the See uP Run Stall Override bit as the select. When the "MDIO Boot Load" pin is asserted, the uP will be in Run Stall mode after reset. */ + unsigned int upRunStall : 1; /* 1E.C001.0 R/W Default = 0x0 */ + /* 1 = uP Run Stall + 0 = uP normal mode + */ + unsigned int reserved1 : 5; + /*! \brief 1E.C001.6 R/W uP Run Stall Override + AQ_GlobalControl_APPIA.u1.bits_1.upRunStallOverride + + Default = 0x0 + + 0 = uP Run Stall from "MDIO Boot Load" pin. + 1 = uP Run Stall from See MCP Run Stall bit + + + Notes: + This bit selects the uP Run Stall from either the "MDIO Boot Load" pin or the See MCP Run Stall bit. */ + unsigned int upRunStallOverride : 1; /* 1E.C001.6 R/W Default = 0x0 */ + /* 0 = uP Run Stall from "MDIO Boot Load" pin. + 1 = uP Run Stall from See MCP Run Stall bit + */ + unsigned int reserved0 : 8; + /*! \brief 1E.C001.F R/W uP Reset + AQ_GlobalControl_APPIA.u1.bits_1.upReset + + Default = 0x0 + + 1 = Reset + + + Notes: + Resets the uP and the PIF master and slave bus. Will be active for a minimum of 100 microseconds. */ + unsigned int upReset : 1; /* 1E.C001.F R/W Default = 0x0 */ + /* 1 = Reset + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalControl_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Reset Control: 1E.C006 */ +/* Global Reset Control: 1E.C006 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Reset Control */ + union + { + struct + { + unsigned int reserved1 : 14; + /*! \brief 1E.C006.E R/WPD Global MMD Reset Disable + AQ_GlobalResetControl_APPIA.u0.bits_0.globalMMD_ResetDisable + + Provisionable Default = 0x0 + + 1 = Disable the S/W reset to the Global MMD registers + 0 = Enable the S/W reset to the Global MMD registers + + + Notes: + Setting this bit prevents a Global S/W reset or Global S/W reset from resetting the Global MMD registers */ + unsigned int globalMMD_ResetDisable : 1; /* 1E.C006.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Disable the S/W reset to the Global MMD registers + 0 = Enable the S/W reset to the Global MMD registers + */ + unsigned int reserved0 : 1; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalResetControl_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Diagnostic Provisioning: 1E.C400 */ +/* Global Diagnostic Provisioning: 1E.C400 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Diagnostic Provisioning */ + union + { + struct + { + unsigned int reserved0 : 15; + /*! \brief 1E.C400.F R/WPD Enable Diagnostics + AQ_GlobalDiagnosticProvisioning_APPIA.u0.bits_0.enableDiagnostics + + Provisionable Default = 0x1 + + 1 = Chip performs diagnostics on power-up + */ + unsigned int enableDiagnostics : 1; /* 1E.C400.F R/WPD Provisionable Default = 0x1 */ + /* 1 = Chip performs diagnostics on power-up */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalDiagnosticProvisioning_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Thermal Provisioning: 1E.C420 */ +/* Global Thermal Provisioning: 1E.C420 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C420.F:0 R/WPD Reserved 0 [F:0] + AQ_GlobalThermalProvisioning_APPIA.u0.bits_0.reserved_0 + + Provisionable Default = 0x0000 + + Internal reserved - do not modify + + */ + unsigned int reserved_0 : 16; /* 1E.C420.F:0 R/WPD Provisionable Default = 0x0000 */ + /* Internal reserved - do not modify + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C421.F:0 R/WPD High Temp Failure Threshold [F:0] + AQ_GlobalThermalProvisioning_APPIA.u1.bits_1.highTempFailureThreshold + + Provisionable Default = 0x4600 + + [F:0] of high temperature failure threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 70 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A000 - 1.A001: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. - High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int highTempFailureThreshold : 16; /* 1E.C421.F:0 R/WPD Provisionable Default = 0x4600 */ + /* [F:0] of high temperature failure threshold */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C422.F:0 R/WPD Low Temp Failure Threshold [F:0] + AQ_GlobalThermalProvisioning_APPIA.u2.bits_2.lowTempFailureThreshold + + Provisionable Default = 0x0000 + + [F:0] of low temperature failure threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 0 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A002 - 1.A003: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. - High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int lowTempFailureThreshold : 16; /* 1E.C422.F:0 R/WPD Provisionable Default = 0x0000 */ + /* [F:0] of low temperature failure threshold */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C423.F:0 R/WPD High Temp Warning Threshold [F:0] + AQ_GlobalThermalProvisioning_APPIA.u3.bits_3.highTempWarningThreshold + + Provisionable Default = 0x3C00 + + [F:0] of high temperature warning threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD008. Default is 60 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A004 - 1.A005: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. - High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int highTempWarningThreshold : 16; /* 1E.C423.F:0 R/WPD Provisionable Default = 0x3C00 */ + /* [F:0] of high temperature warning threshold */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C424.F:0 R/WPD Low Temp Warning Threshold [F:0] + AQ_GlobalThermalProvisioning_APPIA.u4.bits_4.lowTempWarningThreshold + + Provisionable Default = 0x0A00 + + [F:0] of low temperature warning threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 10 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A006 - 1.A007: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. - High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int lowTempWarningThreshold : 16; /* 1E.C424.F:0 R/WPD Provisionable Default = 0x0A00 */ + /* [F:0] of low temperature warning threshold */ + } bits_4; + uint16_t word_4; + } u4; +} AQ_GlobalThermalProvisioning_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global LED Provisioning: 1E.C430 */ +/* Global LED Provisioning: 1E.C430 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C430.1:0 R/WPD LED #0 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_0ActivityStretch : 2; /* 1E.C430.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + /*! \brief 1E.C430.2 R/WPD LED #0 Transmit Activity + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_0TransmitActivity : 1; /* 1E.C430.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C430.3 R/WPD LED #0 Receive Activity + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_0ReceiveActivity : 1; /* 1E.C430.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C430.4 R/WPD LED #0 Connecting + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_0Connecting : 1; /* 1E.C430.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C430.5 R/WPD LED #0 100 Mb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s + + */ + unsigned int led_0_100Mb_sLinkEstablished : 1; /* 1E.C430.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s + */ + /*! \brief 1E.C430.6 R/WPD LED #0 1 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_0_1Gb_sLinkEstablished : 1; /* 1E.C430.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C430.7 R/WPD LED #0 10 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_0_10Gb_sLinkEstablished : 1; /* 1E.C430.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C430.8 R/WPD LED #0 Manual Set + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_0ManualSet : 1; /* 1E.C430.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + unsigned int reserved0 : 7; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C431.1:0 R/WPD LED #1 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_1ActivityStretch : 2; /* 1E.C431.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + /*! \brief 1E.C431.2 R/WPD LED #1 Transmit Activity + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_1TransmitActivity : 1; /* 1E.C431.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C431.3 R/WPD LED #1 Receive Activity + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_1ReceiveActivity : 1; /* 1E.C431.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C431.4 R/WPD LED #1 Connecting + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_1Connecting : 1; /* 1E.C431.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C431.5 R/WPD LED #1 100 Mb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s + + */ + unsigned int led_1_100Mb_sLinkEstablished : 1; /* 1E.C431.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s + */ + /*! \brief 1E.C431.6 R/WPD LED #1 1 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_1_1Gb_sLinkEstablished : 1; /* 1E.C431.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C431.7 R/WPD LED #1 10 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_1_10Gb_sLinkEstablished : 1; /* 1E.C431.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C431.8 R/WPD LED #1 Manual Set + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_1ManualSet : 1; /* 1E.C431.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + unsigned int reserved0 : 7; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C432.1:0 R/WPD LED #2 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_2ActivityStretch : 2; /* 1E.C432.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + /*! \brief 1E.C432.2 R/WPD LED #2 Transmit Activity + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_2TransmitActivity : 1; /* 1E.C432.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C432.3 R/WPD LED #2 Receive Activity + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_2ReceiveActivity : 1; /* 1E.C432.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C432.4 R/WPD LED #2 Connecting + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_2Connecting : 1; /* 1E.C432.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C432.5 R/WPD LED #2 100 Mb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s + + */ + unsigned int led_2_100Mb_sLinkEstablished : 1; /* 1E.C432.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s + */ + /*! \brief 1E.C432.6 R/WPD LED #2 1 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_2_1Gb_sLinkEstablished : 1; /* 1E.C432.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C432.7 R/WPD LED #2 10 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_2_10Gb_sLinkEstablished : 1; /* 1E.C432.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C432.8 R/WPD LED #2 Manual Set + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_2ManualSet : 1; /* 1E.C432.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + unsigned int reserved0 : 7; + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C433.1:0 R/WPD LED #3 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_3ActivityStretch : 2; /* 1E.C433.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + /*! \brief 1E.C433.2 R/WPD LED #3 Transmit Activity + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_3TransmitActivity : 1; /* 1E.C433.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C433.3 R/WPD LED #3 Receive Activity + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_3ReceiveActivity : 1; /* 1E.C433.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C433.4 R/WPD LED #3 Connecting + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_3Connecting : 1; /* 1E.C433.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C433.5 R/WPD LED #3 100 Mb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s + + */ + unsigned int led_3_100Mb_sLinkEstablished : 1; /* 1E.C433.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s + */ + /*! \brief 1E.C433.6 R/WPD LED #3 1 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_3_1Gb_sLinkEstablished : 1; /* 1E.C433.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C433.7 R/WPD LED #3 10 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_3_10Gb_sLinkEstablished : 1; /* 1E.C433.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C433.8 R/WPD LED #3 Manual Set + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_3ManualSet : 1; /* 1E.C433.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + unsigned int reserved0 : 7; + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C434.1:0 R/WPD LED #4 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_4ActivityStretch : 2; /* 1E.C434.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + /*! \brief 1E.C434.2 R/WPD LED #4 Transmit Activity + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_4TransmitActivity : 1; /* 1E.C434.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C434.3 R/WPD LED #4 Receive Activity + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_4ReceiveActivity : 1; /* 1E.C434.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C434.4 R/WPD LED #4 Connecting + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_4Connecting : 1; /* 1E.C434.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C434.5 R/WPD LED #4 100 Mb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s + + */ + unsigned int led_4_100Mb_sLinkEstablished : 1; /* 1E.C434.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s + */ + /*! \brief 1E.C434.6 R/WPD LED #4 1 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_4_1Gb_sLinkEstablished : 1; /* 1E.C434.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C434.7 R/WPD LED #4 10 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_4_10Gb_sLinkEstablished : 1; /* 1E.C434.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C434.8 R/WPD LED #4 Manual Set + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_4ManualSet : 1; /* 1E.C434.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + unsigned int reserved0 : 7; + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C435.1:0 R/WPD LED #5 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_5ActivityStretch : 2; /* 1E.C435.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + /*! \brief 1E.C435.2 R/WPD LED #5 Transmit Activity + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_5TransmitActivity : 1; /* 1E.C435.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C435.3 R/WPD LED #5 Receive Activity + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_5ReceiveActivity : 1; /* 1E.C435.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C435.4 R/WPD LED #5 Connecting + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_5Connecting : 1; /* 1E.C435.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C435.5 R/WPD LED #5 100 Mb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s + + */ + unsigned int led_5_100Mb_sLinkEstablished : 1; /* 1E.C435.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s + */ + /*! \brief 1E.C435.6 R/WPD LED #5 1 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_5_1Gb_sLinkEstablished : 1; /* 1E.C435.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C435.7 R/WPD LED #5 10 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_5_10Gb_sLinkEstablished : 1; /* 1E.C435.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C435.8 R/WPD LED #5 Manual Set + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_5ManualSet : 1; /* 1E.C435.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + unsigned int reserved0 : 7; + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C437.0 R/WPD LED Operation Mode + AQ_GlobalLedProvisioning_APPIA.u7.bits_7.ledOperationMode + + Provisionable Default = 0x0 + + 1 = LED link activity in Mode #2 + 0 = LED link activity in classic mode + + + Notes: + When set to 1, the LED blinking rate is based on Mode #2 algorithm. When set to 0, the LED blinking rate is based on the classic algorithm. */ + unsigned int ledOperationMode : 1; /* 1E.C437.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED link activity in Mode #2 + 0 = LED link activity in classic mode + */ + unsigned int reserved0 : 15; + } bits_7; + uint16_t word_7; + } u7; + /*! \brief Union for bit and word level access of word 8 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C438.0 R/WPD LED #0 Manual Active Select + AQ_GlobalLedProvisioning_APPIA.u8.bits_8.led_0ManualActiveSelect + + Provisionable Default = 0x0 + + 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + + */ + unsigned int led_0ManualActiveSelect : 1; /* 1E.C438.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + */ + /*! \brief 1E.C438.1 R/WPD LED #0 Active High Select + AQ_GlobalLedProvisioning_APPIA.u8.bits_8.led_0ActiveHighSelect + + Provisionable Default = 0x0 + + 1 = LED active high + 0 = LED active low + + + Notes: + The See LED #0 Manual Active Select bit must be 1 for this bit to take affect. */ + unsigned int led_0ActiveHighSelect : 1; /* 1E.C438.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED active high + 0 = LED active low + */ + /*! \brief 1E.C438.2 R/WPD LED #0 Drive Three State Select + AQ_GlobalLedProvisioning_APPIA.u8.bits_8.led_0DriveThreeStateSelect + + Provisionable Default = 0x0 + + 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + + */ + unsigned int led_0DriveThreeStateSelect : 1; /* 1E.C438.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + */ + unsigned int reserved0 : 13; + } bits_8; + uint16_t word_8; + } u8; + /*! \brief Union for bit and word level access of word 9 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C439.0 R/WPD LED #1 Manual Active Select + AQ_GlobalLedProvisioning_APPIA.u9.bits_9.led_1ManualActiveSelect + + Provisionable Default = 0x0 + + 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + + */ + unsigned int led_1ManualActiveSelect : 1; /* 1E.C439.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + */ + /*! \brief 1E.C439.1 R/WPD LED #1 Active High Select + AQ_GlobalLedProvisioning_APPIA.u9.bits_9.led_1ActiveHighSelect + + Provisionable Default = 0x0 + + 1 = LED active high + 0 = LED active low + + + Notes: + The See LED #1 Manual Active Select bit must be 1 for this bit to take affect. */ + unsigned int led_1ActiveHighSelect : 1; /* 1E.C439.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED active high + 0 = LED active low + */ + /*! \brief 1E.C439.2 R/WPD LED #1 Drive Three State Select + AQ_GlobalLedProvisioning_APPIA.u9.bits_9.led_1DriveThreeStateSelect + + Provisionable Default = 0x0 + + 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + + */ + unsigned int led_1DriveThreeStateSelect : 1; /* 1E.C439.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + */ + unsigned int reserved0 : 13; + } bits_9; + uint16_t word_9; + } u9; + /*! \brief Union for bit and word level access of word 10 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C43A.0 R/WPD LED #2 Manual Active Select + AQ_GlobalLedProvisioning_APPIA.u10.bits_10.led_2ManualActiveSelect + + Provisionable Default = 0x0 + + 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + + */ + unsigned int led_2ManualActiveSelect : 1; /* 1E.C43A.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + */ + /*! \brief 1E.C43A.1 R/WPD LED #2 Active High Select + AQ_GlobalLedProvisioning_APPIA.u10.bits_10.led_2ActiveHighSelect + + Provisionable Default = 0x0 + + 1 = LED active high + 0 = LED active low + + + Notes: + The See LED #2 Manual Active Select bit must be 1 for this bit to take affect. */ + unsigned int led_2ActiveHighSelect : 1; /* 1E.C43A.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED active high + 0 = LED active low + */ + /*! \brief 1E.C43A.2 R/WPD LED #2 Drive Three State Select + AQ_GlobalLedProvisioning_APPIA.u10.bits_10.led_2DriveThreeStateSelect + + Provisionable Default = 0x0 + + 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + + */ + unsigned int led_2DriveThreeStateSelect : 1; /* 1E.C43A.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + */ + unsigned int reserved0 : 13; + } bits_10; + uint16_t word_10; + } u10; + /*! \brief Union for bit and word level access of word 11 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C43B.0 R/WPD LED #3 Manual Active Select + AQ_GlobalLedProvisioning_APPIA.u11.bits_11.led_3ManualActiveSelect + + Provisionable Default = 0x0 + + 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + + */ + unsigned int led_3ManualActiveSelect : 1; /* 1E.C43B.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + */ + /*! \brief 1E.C43B.1 R/WPD LED #3 Active High Select + AQ_GlobalLedProvisioning_APPIA.u11.bits_11.led_3ActiveHighSelect + + Provisionable Default = 0x0 + + 1 = LED active high + 0 = LED active low + + + Notes: + The See LED #3 Manual Active Select bit must be 1 for this bit to take affect. */ + unsigned int led_3ActiveHighSelect : 1; /* 1E.C43B.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED active high + 0 = LED active low + */ + /*! \brief 1E.C43B.2 R/WPD LED #3 Drive Three State Select + AQ_GlobalLedProvisioning_APPIA.u11.bits_11.led_3DriveThreeStateSelect + + Provisionable Default = 0x0 + + 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + + */ + unsigned int led_3DriveThreeStateSelect : 1; /* 1E.C43B.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + */ + unsigned int reserved0 : 13; + } bits_11; + uint16_t word_11; + } u11; + /*! \brief Union for bit and word level access of word 12 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C43C.0 R/WPD LED #4 Manual Active Select + AQ_GlobalLedProvisioning_APPIA.u12.bits_12.led_4ManualActiveSelect + + Provisionable Default = 0x0 + + 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + + */ + unsigned int led_4ManualActiveSelect : 1; /* 1E.C43C.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + */ + /*! \brief 1E.C43C.1 R/WPD LED #4 Active High Select + AQ_GlobalLedProvisioning_APPIA.u12.bits_12.led_4ActiveHighSelect + + Provisionable Default = 0x0 + + 1 = LED active high + 0 = LED active low + + + Notes: + The See LED #4 Manual Active Select bit must be 1 for this bit to take affect. */ + unsigned int led_4ActiveHighSelect : 1; /* 1E.C43C.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED active high + 0 = LED active low + */ + /*! \brief 1E.C43C.2 R/WPD LED #4 Drive Three State Select + AQ_GlobalLedProvisioning_APPIA.u12.bits_12.led_4DriveThreeStateSelect + + Provisionable Default = 0x0 + + 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + + */ + unsigned int led_4DriveThreeStateSelect : 1; /* 1E.C43C.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + */ + unsigned int reserved0 : 13; + } bits_12; + uint16_t word_12; + } u12; + /*! \brief Union for bit and word level access of word 13 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C43D.0 R/WPD LED #5 Manual Active Select + AQ_GlobalLedProvisioning_APPIA.u13.bits_13.led_5ManualActiveSelect + + Provisionable Default = 0x0 + + 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + + */ + unsigned int led_5ManualActiveSelect : 1; /* 1E.C43D.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + */ + /*! \brief 1E.C43D.1 R/WPD LED #5 Active High Select + AQ_GlobalLedProvisioning_APPIA.u13.bits_13.led_5ActiveHighSelect + + Provisionable Default = 0x0 + + 1 = LED active high + 0 = LED active low + + + Notes: + The See LED #5 Manual Active Select bit must be 1 for this bit to take affect. */ + unsigned int led_5ActiveHighSelect : 1; /* 1E.C43D.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED active high + 0 = LED active low + */ + /*! \brief 1E.C43D.2 R/WPD LED #5 Drive Three State Select + AQ_GlobalLedProvisioning_APPIA.u13.bits_13.led_5DriveThreeStateSelect + + Provisionable Default = 0x0 + + 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + + */ + unsigned int led_5DriveThreeStateSelect : 1; /* 1E.C43D.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + */ + unsigned int reserved0 : 13; + } bits_13; + uint16_t word_13; + } u13; +} AQ_GlobalLedProvisioning_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global General Provisioning: 1E.C440 */ +/* Global General Provisioning: 1E.C440 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global General Provisioning */ + union + { + struct + { + /*! \brief 1E.C440.0 RO Gang Load MDIO Write Only + AQ_GlobalGeneralProvisioning_APPIA.u0.bits_0.gangLoadMdioWriteOnly + + + + 1 = MDIO gang load enable + + + Notes: + This bit enables gang load operation with the address specified in Bits 8:4. */ + unsigned int gangLoadMdioWriteOnly : 1; /* 1E.C440.0 RO */ + /* 1 = MDIO gang load enable + */ + unsigned int reserved1 : 3; + /*! \brief 1E.C440.8:4 R/WPD Gang Load MDIO Address [4:0] + AQ_GlobalGeneralProvisioning_APPIA.u0.bits_0.gangLoadMdioAddress + + Provisionable Default = 0x00 + + MDIO Address to be used during gang load operation + + + Notes: + Gang load operation is used to load data into multiple PHYs all connected to the same MDIO bus. The address for gang load operation is provided by these bits (8:4), and enabling is done by writing Bit 0. Disabling of gang load mode is done by writing the See MDIO Address Reset (1E.C441.2) bit. These will revert the PHY's MDIO address back to the address provided by the MDIO Address pins. During gang load operation, MDIO reads are disabled to prevent bus contention. */ + unsigned int gangLoadMdioAddress : 5; /* 1E.C440.8:4 R/WPD Provisionable Default = 0x00 */ + /* MDIO Address to be used during gang load operation + */ + unsigned int reserved0 : 7; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved2 : 2; + /*! \brief 1E.C441.2 R/WSC MDIO Address Reset + AQ_GlobalGeneralProvisioning_APPIA.u1.bits_1.mdioAddressReset + + Default = 0x0 + + 1 = Load MDIO Address with the address on the MDIO address pins + + + Notes: + Used to reset the address after gang load and enable MDIO reads again. */ + unsigned int mdioAddressReset : 1; /* 1E.C441.2 R/WSC Default = 0x0 */ + /* 1 = Load MDIO Address with the address on the MDIO address pins + */ + /*! \brief 1E.C441.3 R/WPD MDIO Preamble Detection Disable + AQ_GlobalGeneralProvisioning_APPIA.u1.bits_1.mdioPreambleDetectionDisable + + Provisionable Default = 0x0 + + 1 = Suppress preamble detection on MDIO + 0 = Enable preamble detection on MDIO + + */ + unsigned int mdioPreambleDetectionDisable : 1; /* 1E.C441.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = Suppress preamble detection on MDIO + 0 = Enable preamble detection on MDIO + */ + /*! \brief 1E.C441.4 R/WPD MDIO Drive Configuration + AQ_GlobalGeneralProvisioning_APPIA.u1.bits_1.mdioDriveConfiguration + + Provisionable Default = 0x0 + + 0 = MDIO driver is in normal mode + 1 = MDIO driver is in open drain mode + + + Notes: + When the MDIO driver is in open drain mode during a read cycle, "0" data will be actively driven out of the MDIO, "1" data will set the MDIO driver in high impedance state and an external pullup will set the MDIO line to "1". The Turn-Around "0" will also be actively driven out of the MDIO, therefore in open drain mode, the Turn-Around is still "Z0". */ + unsigned int mdioDriveConfiguration : 1; /* 1E.C441.4 R/WPD Provisionable Default = 0x0 */ + /* 0 = MDIO driver is in normal mode + 1 = MDIO driver is in open drain mode + */ + unsigned int reserved1 : 8; + /*! \brief 1E.C441.D R/WPD MDIO Read MSW First Enable + AQ_GlobalGeneralProvisioning_APPIA.u1.bits_1.mdioReadMSW_FirstEnable + + Provisionable Default = 0x0 + + 1 = MSW of counter must be read first + 0 = LSW of counter must be read first + + + Notes: + This bit configures whether the MSW or LSW must be read first for counters greater than 16 bits. */ + unsigned int mdioReadMSW_FirstEnable : 1; /* 1E.C441.D R/WPD Provisionable Default = 0x0 */ + /* 1 = MSW of counter must be read first + 0 = LSW of counter must be read first + */ + /*! \brief 1E.C441.E R/WPD MDIO Broadcast Mode Enable + AQ_GlobalGeneralProvisioning_APPIA.u1.bits_1.mdioBroadcastModeEnable + + Provisionable Default = 0x0 + + 1 = Enable broadcast on Address 0 + 0 = Disable broadcast on Address 0 + + + Notes: + When set, this bit enables gang-load operation on address zero, simultaneous with normal MDIO operation. Obviously, this requires that no PHY use address 0 as its normal operating address. As well, reads on MDIO Address 0 are disabled to prevent bus contention. */ + unsigned int mdioBroadcastModeEnable : 1; /* 1E.C441.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable broadcast on Address 0 + 0 = Disable broadcast on Address 0 + */ + unsigned int reserved0 : 1; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global General Provisioning */ + union + { + struct + { + /*! \brief 1E.C442.0 R/W Daisy Chain Reset + AQ_GlobalGeneralProvisioning_APPIA.u2.bits_2.daisyChainReset + + Default = 0x0 + + 1 = Reset the daisy chain + + + Notes: + Toggling this bit from 0 to 1 will reload the IRAM and DRAM and reset the uP. The uP will be in uP run stall during the reload process. After the reload process, uP run stall will be de-asserted adn the uP reset will be asserted. Note that before setting this bit, the See Soft Reset bit needs to be de-asserted. */ + unsigned int daisyChainReset : 1; /* 1E.C442.0 R/W Default = 0x0 */ + /* 1 = Reset the daisy chain + */ + unsigned int reserved0 : 15; + } bits_2; + uint16_t word_2; + } u2; +} AQ_GlobalGeneralProvisioning_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global NVR Provisioning: 1E.C450 */ +/* Global NVR Provisioning: 1E.C450 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global NVR Provisioning */ + union + { + struct + { + /*! \brief 1E.C450.1:0 R/WPD NVR Address Length [1:0] + AQ_GlobalNvrProvisioning_APPIA.u0.bits_0.nvrAddressLength + + Provisionable Default = 0x2 + + NVR address length ranges from 0 bytes up to 3 bytes. + + + Notes: + This sets the length of the address field used in read and write operations. Use of this field is enabled via Bit 8 of See Global NVR Provisioning 2: Address 1E.C451 . + */ + unsigned int nvrAddressLength : 2; /* 1E.C450.1:0 R/WPD Provisionable Default = 0x2 */ + /* NVR address length ranges from 0 bytes up to 3 bytes. + */ + unsigned int reserved2 : 2; + /*! \brief 1E.C450.6:4 R/WPD NVR Dummy Length [2:0] + AQ_GlobalNvrProvisioning_APPIA.u0.bits_0.nvrDummyLength + + Provisionable Default = 0x0 + + NVR dummy length ranges from 0 bytes to 4 bytes. + + + Notes: + This sets the length of the dummy field used in some maunfacturer's read status and write status operations. + */ + unsigned int nvrDummyLength : 3; /* 1E.C450.6:4 R/WPD Provisionable Default = 0x0 */ + /* NVR dummy length ranges from 0 bytes to 4 bytes. + */ + unsigned int reserved1 : 1; + /*! \brief 1E.C450.A:8 R/WPD NVR Data Length [2:0] + AQ_GlobalNvrProvisioning_APPIA.u0.bits_0.nvrDataLength + + Provisionable Default = 0x4 + + NVR data length ranges from 0 bytes to 4 bytes + + + Notes: + This sets the length of the data burst used in read and write operations. + */ + unsigned int nvrDataLength : 3; /* 1E.C450.A:8 R/WPD Provisionable Default = 0x4 */ + /* NVR data length ranges from 0 bytes to 4 bytes + */ + unsigned int reserved0 : 5; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global NVR Provisioning */ + union + { + struct + { + /*! \brief 1E.C451.7:0 R/WPD NVR Clock Divide [7:0] + AQ_GlobalNvrProvisioning_APPIA.u1.bits_1.nvrClockDivide + + Provisionable Default = 0xA0 + + NVR clock divide. Clock frequency is divided by the NVR clock divide + 1 + + */ + unsigned int nvrClockDivide : 8; /* 1E.C451.7:0 R/WPD Provisionable Default = 0xA0 */ + /* NVR clock divide. Clock frequency is divided by the NVR clock divide + 1 + */ + /*! \brief 1E.C451.8 R/WPD NVR Address Length Override + AQ_GlobalNvrProvisioning_APPIA.u1.bits_1.nvrAddressLengthOverride + + Provisionable Default = 0x0 + + 0 = NVR address length is based on the "NVR_SIZE" pin. + 1 = NVR address length is based on the See NVR Address Length [1:0] register. + + + Notes: + When the this bit = 0 and NVR_SIZE pin = 0, the NVR address length is 2 bytes. When this bit = 0 and the NVR_SIZE pin = 1, the NVR address length is 3 bytes. When this bit = 1 the NVR address length is from the See NVR Address Length [1:0] */ + unsigned int nvrAddressLengthOverride : 1; /* 1E.C451.8 R/WPD Provisionable Default = 0x0 */ + /* 0 = NVR address length is based on the "NVR_SIZE" pin. + 1 = NVR address length is based on the See NVR Address Length [1:0] register. + */ + unsigned int reserved0 : 7; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global NVR Provisioning */ + union + { + struct + { + /*! \brief 1E.C452.0 R/W NVR Daisy Chain Disable + AQ_GlobalNvrProvisioning_APPIA.u2.bits_2.nvrDaisyChainDisable + + Default = 0x0 + + 1 = Disable the Daisy Chain + + + Notes: + When in daisy chain master mode, the daisy chain and MDIO can both access the SPI. Setting this bit to 1 will disable the dasiy chain from accessing the SPI and force it into a reset state. */ + unsigned int nvrDaisyChainDisable : 1; /* 1E.C452.0 R/W Default = 0x0 */ + /* 1 = Disable the Daisy Chain + */ + /*! \brief 1E.C452.1 R/W NVR Daisy Chain Clock Divide Override + AQ_GlobalNvrProvisioning_APPIA.u2.bits_2.nvrDaisyChainClockDivideOverride + + Default = 0x0 + + 1 = Override NVR clock divide when in daisy chain master mode + + + + Notes: + When in daisy chain master mode, the clock divide configuration is received from the flash. This bit will override the clock divide configuration from the flash with the See NVR Clock Divide [7:0] . */ + unsigned int nvrDaisyChainClockDivideOverride : 1; /* 1E.C452.1 R/W Default = 0x0 */ + /* 1 = Override NVR clock divide when in daisy chain master mode + + */ + unsigned int reserved0 : 14; + } bits_2; + uint16_t word_2; + } u2; +} AQ_GlobalNvrProvisioning_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Reserved Provisioning: 1E.C470 */ +/* Global Reserved Provisioning: 1E.C470 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved2 : 4; + /*! \brief 1E.C470.4 R/WSC Initiate Cable Diagnostics + AQ_GlobalReservedProvisioning_APPIA.u0.bits_0.initiateCableDiagnostics + + Default = 0x0 + + 1 = Perform cable diagnostics + + + Notes: + Perform cable diagnostics regardless of link state. If link is up, setting this bit will cause the link to drop while diagnostics are performed. This bit is self-clearing upon completion of the cable diagnostics. Further MDIO writes should be avoided until this bit has self-cleared, indicating completion of the diagnostic routine. */ + unsigned int initiateCableDiagnostics : 1; /* 1E.C470.4 R/WSC Default = 0x0 */ + /* 1 = Perform cable diagnostics + */ + /*! \brief 1E.C470.5 R/WSC Initiate Component Diagnostics + AQ_GlobalReservedProvisioning_APPIA.u0.bits_0.initiateComponentDiagnostics + + Default = 0x0 + + 1 = Perform component diagnostics + + + Notes: + Perform component diagnostics regardless of link state. If link is up, setting this bit will cause the link to drop while diagnostics are performed. This bit is self-clearing upon completion of the component diagnostics. Further MDIO writes should be avoided until this bit has self-cleared, indicating completion of the diagnostic routine. */ + unsigned int initiateComponentDiagnostics : 1; /* 1E.C470.5 R/WSC Default = 0x0 */ + /* 1 = Perform component diagnostics + */ + unsigned int reserved1 : 2; + unsigned int reserved0 : 5; + /*! \brief 1E.C470.E:D R/WPD Extended MDI Diagnostics Select [1:0] + AQ_GlobalReservedProvisioning_APPIA.u0.bits_0.extendedMdiDiagnosticsSelect + + Provisionable Default = 0x0 + + 0x0 = TDR Data + 0x1 = RFI Channel PSD + 0x2 = Noise PSD while the local Tx is Off + 0x3 = Noise PSD while the local Tx is On + + + Notes: + These bits select what sort of cable diagnostics to perform. For regular cable diagnostics, Bit F is set to zero, and the diagnostics are triggered by setting Bit 4. For extended diagnostics, Bit F is set to 1, and the desired extended diagnostics are selected by Bits E:D. The routine is then triggered by setting Bit 4. Each of the extended diagnostic routines present data for all for MDI pairs (A, B, C, D) consecutively, and after the data for each channel is gathered Bits F:D are reset. To get the data for the next pair, Bits F:D must be set back to the desired value (which must be the same as the initial channel). This continues until the data for all channels has been gathered. The address in memory where the data is stored is given in 1E.C802 and 1E.C804. + + For the case of PSD, the structure is as follows: + Int32 info + Int16 data[Len] + Info = Len << 16 | TxEnable << 8 | Pair (0 = A, etc.) + + For TDR: + Int32 info + Int16 tdr_A[Len] + Int16 tdr_B[Len] + Int16 tdr_C[Len] + Int16 tdr_D[Len] + + Info = Len << 16 | Channel + + TDR data is from the current pair to all other pairs. + + At the end of retrieving extended MDI diag data, the part will be reset. Conversly the only way to exit this routine once it starts is to issue a PMA reset. */ + unsigned int extendedMdiDiagnosticsSelect : 2; /* 1E.C470.E:D R/WPD Provisionable Default = 0x0 */ + /* 0x0 = TDR Data + 0x1 = RFI Channel PSD + 0x2 = Noise PSD while the local Tx is Off + 0x3 = Noise PSD while the local Tx is On + */ + /*! \brief 1E.C470.F R/WPD Diagnostics Select + AQ_GlobalReservedProvisioning_APPIA.u0.bits_0.diagnosticsSelect + + Provisionable Default = 0x0 + + 1 = Provide Extended MDI Diagnostics Information. + 0 = Provide normal cable diagnostics + + + Notes: + These bits select what sort of cable diagnostics to perform. For regular cable diagnostics, Bit F is set to zero, and the diagnostics are triggered by setting Bit 4. For extended diagnostics, Bit F is set to 1, and the desired extended diagnostics are selected by Bits E:D. The routine is then triggered by setting Bit 4. Each of the extended diagnostic routines present data for all for MDI pairs (A, B, C, D) consecutively, and after the data for each channel is gathered Bits F:D are reset. To get the data for the next pair, Bits F:D must be set back to the desired value (which must be the same as the initial channel). This continues until the data for all channels has been gathered. The address in memory where the data is stored is given in 1E.C802 and 1E.C804. + + For the case of PSD, the structure is as follows: + Int32 info + Int16 data[Len] + Info = Len << 16 | TxEnable << 8 | Pair (0 = A, etc.) + + For TDR: + Int32 info + Int16 tdr_A[Len] + Int16 tdr_B[Len] + Int16 tdr_C[Len] + Int16 tdr_D[Len] + + Info = Len << 16 | Channel + + TDR data is from the current pair to all other pairs. + + At the end of retrieving extended MDI diag data, the part will be reset. Conversly the only way to exit this routine once it starts is to issue a PMA reset. */ + unsigned int diagnosticsSelect : 1; /* 1E.C470.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Provide Extended MDI Diagnostics Information. + 0 = Provide normal cable diagnostics + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C471.5:0 R/WuP Daisy-Chain Hop-Count Override Value [5:0] + AQ_GlobalReservedProvisioning_APPIA.u1.bits_1.daisy_chainHop_countOverrideValue + + Default = 0x00 + + The value to use for the PHY's daisy-chain hop-count. Valid values are from 0 -> 47 + + + Notes: + Daisy-Chain Hop-Count Override should be used during MDIO boot-load operation, as the daisy-chain hop-count does not function when the daisy-chain is disabled (1E.C452.0). Setting this bit tells the processor where in the diasy-chain it is, so that the provisioning operation will function correctly. */ + unsigned int daisy_chainHop_countOverrideValue : 6; /* 1E.C471.5:0 R/WuP Default = 0x00 */ + /* The value to use for the PHY's daisy-chain hop-count. Valid values are from 0 -> 47 + */ + /*! \brief 1E.C471.6 R/WuP Enable Daisy-Chain Hop-Count Override + AQ_GlobalReservedProvisioning_APPIA.u1.bits_1.enableDaisy_chainHop_countOverride + + Default = 0x0 + + 1 = Hop-count is set by Bits 5:0 + 0 = Hop-count is determined by the daisy-chain + + + Notes: + Daisy-Chain Hop-Count Override should be used during MDIO boot-load operation, as the daisy-chain hop-count does not function when the daisy-chain is disabled (1E.C452.0). Setting this bit tells the processor where in the diasy-chain it is, so that the provisioning operation will function correctly. */ + unsigned int enableDaisy_chainHop_countOverride : 1; /* 1E.C471.6 R/WuP Default = 0x0 */ + /* 1 = Hop-count is set by Bits 5:0 + 0 = Hop-count is determined by the daisy-chain + */ + /*! \brief 1E.C471.F:7 R/WPD Reserved Provisioning 2 [8:0] + AQ_GlobalReservedProvisioning_APPIA.u1.bits_1.reservedProvisioning_2 + + Provisionable Default = 0x000 + + Reserved for future use + + */ + unsigned int reservedProvisioning_2 : 9; /* 1E.C471.F:7 R/WPD Provisionable Default = 0x000 */ + /* Reserved for future use + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C472.0 R/WPDuP Enable 5th Channel RFI Cancellation + AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.enable_5thChannelRfiCancellation + + Provisionable Default = 0x0 + + 1 = 5th channel and RFI cancellers operation enabled + 0 = 5th channel AFE is powered down, 5th channel digital is clock gated, RFI cancellers are disabled + + + Notes: + Note: The value of this bit at the time of Autonegotiation sets the local PHY behavior until the next time Autonegotiation occurs. */ + unsigned int enable_5thChannelRfiCancellation : 1; /* 1E.C472.0 R/WPDuP Provisionable Default = 0x0 */ + /* 1 = 5th channel and RFI cancellers operation enabled + 0 = 5th channel AFE is powered down, 5th channel digital is clock gated, RFI cancellers are disabled + */ + /*! \brief 1E.C472.1 R/WPDuP Enable XENPAK Register Space + AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.enableXenpakRegisterSpace + + Provisionable Default = 0x0 + + 1 = XENPAK register space enabled + 0 = XENPAK register space disabled + + */ + unsigned int enableXenpakRegisterSpace : 1; /* 1E.C472.1 R/WPDuP Provisionable Default = 0x0 */ + /* 1 = XENPAK register space enabled + 0 = XENPAK register space disabled + */ + unsigned int reserved1 : 4; + /*! \brief 1E.C472.6 R/WPD Tunable External VDD Power Supply Present + AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.tunableExternalVddPowerSupplyPresent + + Provisionable Default = 0x0 + + 1 = Tunable external VDD power supply present + 0 = No tunable external VDD power supply present + + + Notes: + + + + These bits must be set if tuning of external power supplies is desired (see Bits 7:6) */ + unsigned int tunableExternalVddPowerSupplyPresent : 1; /* 1E.C472.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Tunable external VDD power supply present + 0 = No tunable external VDD power supply present + */ + /*! \brief 1E.C472.7 R/WPD Tunable External LVDD Power Supply Present + AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.tunableExternalLvddPowerSupplyPresent + + Provisionable Default = 0x0 + + 1 = Tunable external LVDD power supply present + 0 = No tunable external LVDD power supply present + + + Notes: + + + + These bits must be set if tuning of external power supplies is desired (see Bits 7:6) */ + unsigned int tunableExternalLvddPowerSupplyPresent : 1; /* 1E.C472.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = Tunable external LVDD power supply present + 0 = No tunable external LVDD power supply present + */ + unsigned int reserved0 : 6; + /*! \brief 1E.C472.E R/WPD Enable VDD Power Supply Tuning + AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.enableVddPowerSupplyTuning + + Provisionable Default = 0x0 + + 1 = Enable external VDD power supply tuning + 0 = Disable external VDD power supply tuning is disabled + + + Notes: + + + + These bits control whether the PHY attempts to tune the external VDD and LVDD power supplies via the PMBus. These bits are only operational if the external supplies are present (see Bits 7:6) */ + unsigned int enableVddPowerSupplyTuning : 1; /* 1E.C472.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable external VDD power supply tuning + 0 = Disable external VDD power supply tuning is disabled + */ + /*! \brief 1E.C472.F R/WPD Enable LVDD Power Supply Tuning + AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.enableLvddPowerSupplyTuning + + Provisionable Default = 0x0 + + 1 = Enable external LVDD power supply tuning + 0 = Disable external LVDD power supply tuning is disabled + + + Notes: + + + + These bits control whether the PHY attempts to tune the external VDD and LVDD power supplies via the PMBus. These bits are only operational if the external supplies are present (see Bits 7:6) */ + unsigned int enableLvddPowerSupplyTuning : 1; /* 1E.C472.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable external LVDD power supply tuning + 0 = Disable external LVDD power supply tuning is disabled + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C474.7:0 R/WPD Training SNR [7:0] + AQ_GlobalReservedProvisioning_APPIA.u4.bits_4.trainingSNR + + Provisionable Default = 0x00 + + SNR during 10G training on the worst channel. SNR is in steps of 0.1dB + + + Notes: + The SNR margin that is enjoyed by the worst channel, over and above the minimum SNR required to operate at a BER of 10-12. It is reported with 0.1 dB of resolution to an accuracy of 0.5 dB within the range of -12.7 dB to 12.7 dB. The number is in offset binary, with 0.0 dB represented by 0x8000. + */ + unsigned int trainingSNR : 8; /* 1E.C474.7:0 R/WPD Provisionable Default = 0x00 */ + /* SNR during 10G training on the worst channel. SNR is in steps of 0.1dB + */ + unsigned int reserved0 : 8; + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved1 : 2; + /*! \brief 1E.C475.2 R/WPD Smart Power-Down Enable + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.smartPower_downEnable + + Provisionable Default = 0x0 + + 1 = Enable smart power down mode + 0 = Smart power-down mode disabled + + + Notes: + Smart power down (SPD) is the lowest power mode at which PHY is able to autonegotiate. SPD can be enabled with bit 1E.C475.2 */ + unsigned int smartPower_downEnable : 1; /* 1E.C475.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable smart power down mode + 0 = Smart power-down mode disabled + */ + /*! \brief 1E.C475.3 R/WPD Deadlock Avoidance Enable + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.deadlockAvoidanceEnable + + Provisionable Default = 0x0 + + 1 = SPD with deadlock avoidance: PHY transmits autonegotiation pulses (FLPs) at a slower rate (~ 1 FLP/ 100ms) than specified by autonegotiation standard (~1 FLP / 8.25ms). Receiver is active and able to detect the pulses. + 0 = SPD without deadlock avoidance: PHY transmitter is shut down, no autonegotiation pulses are sent on the line but the receiver is active and able to detect the pulses + + */ + unsigned int deadlockAvoidanceEnable : 1; /* 1E.C475.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = SPD with deadlock avoidance: PHY transmits autonegotiation pulses (FLPs) at a slower rate (~ 1 FLP/ 100ms) than specified by autonegotiation standard (~1 FLP / 8.25ms). Receiver is active and able to detect the pulses. + 0 = SPD without deadlock avoidance: PHY transmitter is shut down, no autonegotiation pulses are sent on the line but the receiver is active and able to detect the pulses + */ + /*! \brief 1E.C475.4 R/WPD CFR Support + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrSupport + + Provisionable Default = 0x0 + + 1 = Local PHY supports Cisco Fast Retrain + 0 = Local PHY does support Cisco Fast Retrain + + */ + unsigned int cfrSupport : 1; /* 1E.C475.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY supports Cisco Fast Retrain + 0 = Local PHY does support Cisco Fast Retrain + */ + /*! \brief 1E.C475.5 R/WPD CFR THP + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrTHP + + Provisionable Default = 0x0 + + 1 = Local PHY requires local PHY to enable THP + 0 = Local PHY does not require local PHY to enable THP + + */ + unsigned int cfrTHP : 1; /* 1E.C475.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY requires local PHY to enable THP + 0 = Local PHY does not require local PHY to enable THP + */ + /*! \brief 1E.C475.6 R/WPD CFR Extended Maxwait + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrExtendedMaxwait + + Provisionable Default = 0x0 + + 1 = Local PHY requires extended maxwait + 0 = Local PHY does not require extended maxwait + + */ + unsigned int cfrExtendedMaxwait : 1; /* 1E.C475.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY requires extended maxwait + 0 = Local PHY does not require extended maxwait + */ + /*! \brief 1E.C475.7 R/WPD CFR Disable Timer + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrDisableTimer + + Provisionable Default = 0x0 + + 1 = Local PHY requires cfr_disable timer + 0 = Local PHY does not require cfr_disable timer + + */ + unsigned int cfrDisableTimer : 1; /* 1E.C475.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY requires cfr_disable timer + 0 = Local PHY does not require cfr_disable timer + */ + /*! \brief 1E.C475.8 R/WPD CFR LP Support + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrLpSupport + + Provisionable Default = 0x0 + + 1 = Link partner supports Cisco Fast Retrain + 0 = Link partner does support Cisco Fast Retrain + + */ + unsigned int cfrLpSupport : 1; /* 1E.C475.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner supports Cisco Fast Retrain + 0 = Link partner does support Cisco Fast Retrain + */ + /*! \brief 1E.C475.9 R/WPD CFR LP THP + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrLpTHP + + Provisionable Default = 0x0 + + 1 = Link partner requires local PHY to enable THP + 0 = Link partner does not require local PHY to enable THP + + */ + unsigned int cfrLpTHP : 1; /* 1E.C475.9 R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner requires local PHY to enable THP + 0 = Link partner does not require local PHY to enable THP + */ + /*! \brief 1E.C475.A R/WPD CFR LP Extended Maxwait + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrLpExtendedMaxwait + + Provisionable Default = 0x0 + + 1 = Link partner requires extended maxwait + 0 = Link partner does not require extended maxwait + + */ + unsigned int cfrLpExtendedMaxwait : 1; /* 1E.C475.A R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner requires extended maxwait + 0 = Link partner does not require extended maxwait + */ + /*! \brief 1E.C475.B R/WPD CFR LP Disable Timer + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrLpDisableTimer + + Provisionable Default = 0x0 + + 1 = Link partner requires cfr_disable timer + 0 = Link partner does not require cfr_disable timer + + */ + unsigned int cfrLpDisableTimer : 1; /* 1E.C475.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner requires cfr_disable timer + 0 = Link partner does not require cfr_disable timer + */ + /*! \brief 1E.C475.C R/WPD Reserved Provisioning 6 + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.reservedProvisioning_6 + + Provisionable Default = 0x0 + + Reserved for future use + + */ + unsigned int reservedProvisioning_6 : 1; /* 1E.C475.C R/WPD Provisionable Default = 0x0 */ + /* Reserved for future use + */ + /*! \brief 1E.C475.D R/WPD Smart Power-Down Status + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.smartPower_downStatus + + Provisionable Default = 0x0 + + 1 = Smart Power-Down Active + 0 = Smart Power-Down Inactive + + */ + unsigned int smartPower_downStatus : 1; /* 1E.C475.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Smart Power-Down Active + 0 = Smart Power-Down Inactive + */ + unsigned int reserved0 : 2; + } bits_5; + uint16_t word_5; + } u5; +} AQ_GlobalReservedProvisioning_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Cable Diagnostic Status: 1E.C800 */ +/* Global Cable Diagnostic Status: 1E.C800 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C800.2:0 RO Pair D Status [2:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u0.bits_0.pairDStatus + + + + (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair C + 010= Connected to Pair B + 001= Connected to Pair A + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK + + Notes: + This bitfield reports the result, for pair D, of running either cable diagnostics or component diagnostics. */ + unsigned int pairDStatus : 3; /* 1E.C800.2:0 RO */ + /* (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair C + 010= Connected to Pair B + 001= Connected to Pair A + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK */ + unsigned int reserved3 : 1; + /*! \brief 1E.C800.6:4 RO Pair C Status [2:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u0.bits_0.pairCStatus + + + + (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair B + 010= Connected to Pair A + 001= Connected to Pair D + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK + + Notes: + This bitfield reports the result, for pair C, of running either cable diagnostics or component diagnostics. */ + unsigned int pairCStatus : 3; /* 1E.C800.6:4 RO */ + /* (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair B + 010= Connected to Pair A + 001= Connected to Pair D + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK */ + unsigned int reserved2 : 1; + /*! \brief 1E.C800.A:8 RO Pair B Status [2:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u0.bits_0.pairBStatus + + + + (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair A + 010= Connected to Pair D + 001= Connected to Pair C + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK + + Notes: + This bitfield reports the result, for pair B, of running either cable diagnostics or component diagnostics. */ + unsigned int pairBStatus : 3; /* 1E.C800.A:8 RO */ + /* (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair A + 010= Connected to Pair D + 001= Connected to Pair C + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK */ + unsigned int reserved1 : 1; + /*! \brief 1E.C800.E:C RO Pair A Status [2:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u0.bits_0.pairAStatus + + + + (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair D + 010= Connected to Pair C + 001= Connected to Pair B + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK + + Notes: + This bitfield reports the result, for pair A, of running either cable diagnostics or component diagnostics. */ + unsigned int pairAStatus : 3; /* 1E.C800.E:C RO */ + /* (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair D + 010= Connected to Pair C + 001= Connected to Pair B + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK */ + unsigned int reserved0 : 1; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C801.7:0 RO Pair A Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u1.bits_1.pairAReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair A + + Notes: + The distance to this reflection is given in See Global Reserved Status 1: Address 1E.C870 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairAReflection_2 : 8; /* 1E.C801.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair A */ + /*! \brief 1E.C801.F:8 RO Pair A Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u1.bits_1.pairAReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair A + + Notes: + The distance to this reflection is given in See Global Reserved Status 1: Address 1E.C870 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairAReflection_1 : 8; /* 1E.C801.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair A */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C802.F:0 RO Impulse Response MSW [F:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u2.bits_2.impulseResponseMSW + + + + The MSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type in 1E.C470.E:D + + + Notes: + See 1E.C470 for more information */ + unsigned int impulseResponseMSW : 16; /* 1E.C802.F:0 RO */ + /* The MSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type in 1E.C470.E:D + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C803.7:0 RO Pair B Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u3.bits_3.pairBReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair B + + Notes: + The distance to this reflection is given in See Global Reserved Status 2: Address 1E.C871 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairBReflection_2 : 8; /* 1E.C803.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair B */ + /*! \brief 1E.C803.F:8 RO Pair B Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u3.bits_3.pairBReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair B + + Notes: + The distance to this reflection is given in See Global Reserved Status 2: Address 1E.C871 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairBReflection_1 : 8; /* 1E.C803.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair B */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C804.F:0 RO Impulse Response LSW [F:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u4.bits_4.impulseResponseLSW + + + + The LSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type specified in 1E.C470.E:D + + + Notes: + See 1E.C470 for more information */ + unsigned int impulseResponseLSW : 16; /* 1E.C804.F:0 RO */ + /* The LSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type specified in 1E.C470.E:D + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C805.7:0 RO Pair C Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u5.bits_5.pairCReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair C + + Notes: + The distance to this reflection is given in See Global Reserved Status 3: Address 1E.C872 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairCReflection_2 : 8; /* 1E.C805.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair C */ + /*! \brief 1E.C805.F:8 RO Pair C Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u5.bits_5.pairCReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair C + + Notes: + The distance to this reflection is given in See Global Reserved Status 3: Address 1E.C872 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairCReflection_1 : 8; /* 1E.C805.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair C */ + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C806.F:0 RO Reserved 1 [F:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u6.bits_6.reserved_1 + + + + Reserved for future use + + */ + unsigned int reserved_1 : 16; /* 1E.C806.F:0 RO */ + /* Reserved for future use + */ + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C807.7:0 RO Pair D Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u7.bits_7.pairDReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair D + + Notes: + The distance to this reflection is given in See Global Reserved Status 4: Address 1E.C873 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairDReflection_2 : 8; /* 1E.C807.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair D */ + /*! \brief 1E.C807.F:8 RO Pair D Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u7.bits_7.pairDReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair D + + Notes: + The distance to this reflection is given in See Global Reserved Status 4: Address 1E.C873 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairDReflection_1 : 8; /* 1E.C807.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair D */ + } bits_7; + uint16_t word_7; + } u7; + /*! \brief Union for bit and word level access of word 8 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C808.F:0 RO Reserved 2[F:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u8.bits_8.reserved_2 + + + + Reserved for future use + + */ + unsigned int reserved_2 : 16; /* 1E.C808.F:0 RO */ + /* Reserved for future use + */ + } bits_8; + uint16_t word_8; + } u8; +} AQ_GlobalCableDiagnosticStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Thermal Status: 1E.C820 */ +/* Global Thermal Status: 1E.C820 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Thermal Status */ + union + { + struct + { + /*! \brief 1E.C820.F:0 RO Temperature [F:0] + AQ_GlobalThermalStatus_APPIA.u0.bits_0.temperature + + + + [F:0] of temperature + + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 70 degreesC. This is a mirror of the XENPAK register 1.A060 - 1.A061. The mirror is performed in H/W. */ + unsigned int temperature : 16; /* 1E.C820.F:0 RO */ + /* [F:0] of temperature + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Thermal Status */ + union + { + struct + { + /*! \brief 1E.C821.0 RO Temperature Ready + AQ_GlobalThermalStatus_APPIA.u1.bits_1.temperatureReady + + + + 1 = Temperature measurement is valid + + + Notes: + This is a mirror of the XENPAK register 1.A06E. */ + unsigned int temperatureReady : 1; /* 1E.C821.0 RO */ + /* 1 = Temperature measurement is valid + */ + unsigned int reserved0 : 15; + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalThermalStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global General Status: 1E.C830 */ +/* Global General Status: 1E.C830 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global General Status */ + union + { + struct + { + unsigned int reserved1 : 11; + /*! \brief 1E.C830.B RO Low Temperature Warning State + AQ_GlobalGeneralStatus_APPIA.u0.bits_0.lowTemperatureWarningState + + + + 1 = Low temperature warning threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A074.6 register. + + */ + unsigned int lowTemperatureWarningState : 1; /* 1E.C830.B RO */ + /* 1 = Low temperature warning threshold has been exceeded */ + /*! \brief 1E.C830.C RO High Temperature Warning State + AQ_GlobalGeneralStatus_APPIA.u0.bits_0.highTemperatureWarningState + + + + 1 = High temperature warning threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A074.7 register. + + */ + unsigned int highTemperatureWarningState : 1; /* 1E.C830.C RO */ + /* 1 = High temperature warning threshold has been exceeded */ + /*! \brief 1E.C830.D RO Low Temperature Failure State + AQ_GlobalGeneralStatus_APPIA.u0.bits_0.lowTemperatureFailureState + + + + 1 = Low temperature failure threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A070.6 register. + + */ + unsigned int lowTemperatureFailureState : 1; /* 1E.C830.D RO */ + /* 1 = Low temperature failure threshold has been exceeded */ + /*! \brief 1E.C830.E RO High Temperature Failure State + AQ_GlobalGeneralStatus_APPIA.u0.bits_0.highTemperatureFailureState + + + + 1 = High temperature failure threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A070.7 register. + + */ + unsigned int highTemperatureFailureState : 1; /* 1E.C830.E RO */ + /* 1 = High temperature failure threshold has been exceeded */ + unsigned int reserved0 : 1; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global General Status */ + union + { + struct + { + unsigned int reserved0 : 15; + /*! \brief 1E.C831.F RO Processor Intensive MDIO Operation In- Progress + AQ_GlobalGeneralStatus_APPIA.u1.bits_1.processorIntensiveMdioOperationIn_Progress + + + + 1 = PHY microprocessor is busy with a processor-intensive MDIO operation + 0 = Processor-intensive MDIO operation completed + + + Notes: + This bit should may be used with certain processor-intensive MDIO commands (such as Loopbacks, Test Modes, Low power modes, Tx-Disable, Restart autoneg, Cable Diagnostics, etc.) that take longer than an MDIO cycle to complete. Upon receiving an MDIO command that involves the PHY's microprocessor, this bit is set, and when the command is completed, this bit is cleared. + + NOTE!!! This bit should be checked only after 1 ms of issuing a processor-intensive MDIO operation. + + The list of operations that set this bit are as follows: + + 1.0.0, PMA Loopback + 1.0.B, Low power mode + 1.9.4:0, Tx Disable + 1.84, 10G Test modes + 1.8000.5, XENPAK Control + 1.9000, XENPAK Rx Fault Enable + 1.9002, XENPAK Alarm Enable + 1.E400.F, External loopback + 3.0.B, Low power mode + 3.0.E, System PCS loopback + 3.C471.5, PRBS Test + 3.C471.6, PRBS Test + 3.E471.5, PRBS Test + 3.E471.6, PRBS Test + 4.0.B, Low power mode + 4.0.E, PHY-XS network loopback + 4.C440, Output clock control, Load SERDES parameters + 4.F802.E, System loopback + 4.C444.F:B, Loopback Control + 4.C444.4:2, Packet generation + 4.C445.C, SERDES calibration + 7.0.9, Restart autonegotiation + 1D.C280, 1G/100M Network loopback + 1D.C500, 1G System loopback + 1D.C501, 1G / 100M Test modes */ + unsigned int processorIntensiveMdioOperationIn_Progress : 1; /* 1E.C831.F RO */ + /* 1 = PHY microprocessor is busy with a processor-intensive MDIO operation + 0 = Processor-intensive MDIO operation completed + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalGeneralStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Pin Status: 1E.C840 */ +/* Global Pin Status: 1E.C840 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Pin Status */ + union + { + struct + { + /*! \brief 1E.C840.5:0 RO LED Pullup State [5:0] + AQ_GlobalPinStatus_APPIA.u0.bits_0.ledPullupState + + + + 1 = LED output pin is pulled high + 0 = LED output pin is pulled low + + */ + unsigned int ledPullupState : 6; /* 1E.C840.5:0 RO */ + /* 1 = LED output pin is pulled high + 0 = LED output pin is pulled low + */ + unsigned int reserved3 : 1; + /*! \brief 1E.C840.7 RO Tx Enable + AQ_GlobalPinStatus_APPIA.u0.bits_0.txEnable + + + + Current Value of Tx Enable pin + + + Notes: + 0 = Disable Transmitter */ + unsigned int txEnable : 1; /* 1E.C840.7 RO */ + /* Current Value of Tx Enable pin + */ + unsigned int reserved2 : 1; + /*! \brief 1E.C840.9 RO Package Connectivity + AQ_GlobalPinStatus_APPIA.u0.bits_0.packageConnectivity + + + + Value of the package connection pin + + */ + unsigned int packageConnectivity : 1; /* 1E.C840.9 RO */ + /* Value of the package connection pin + */ + unsigned int reserved1 : 3; + /*! \brief 1E.C840.E:D RO MDIO Boot Load [1:0] + AQ_GlobalPinStatus_APPIA.u0.bits_0.mdioBootLoad + + + + Value of MDIO Boot Load pins + + 0x3 = PHY #0 Slave Daisy Chain Boot + 0x2 = PHY #0 Master Daisy Chain Boot from Flash + 0x1 = MDIO Boot Load + 0x0 = Boot from Flash (PHY #0 only) + + + Notes: + NOTES: + + PHY #0 is the primary PHY, and PHY #1 is the secondary PHY + + PHY #1 is always in Slave Daisy Chain Boot from Flash when set to 0x2 or 0x3. */ + unsigned int mdioBootLoad : 2; /* 1E.C840.E:D RO */ + /* Value of MDIO Boot Load pins + + 0x3 = PHY #0 Slave Daisy Chain Boot + 0x2 = PHY #0 Master Daisy Chain Boot from Flash + 0x1 = MDIO Boot Load + 0x0 = Boot from Flash (PHY #0 only) + */ + unsigned int reserved0 : 1; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalPinStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Daisy Chain Status: 1E.C842 */ +/* Global Daisy Chain Status: 1E.C842 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Daisy Chain Status */ + union + { + struct + { + /*! \brief 1E.C842.F:0 RO Rx Daisy Chain Calculated CRC [F:0] + AQ_GlobalDaisyChainStatus_APPIA.u0.bits_0.rxDaisyChainCalculatedCrc + + + + Rx Daisy Chain Calculated CRC + + + Notes: + This is the calculated daisy chain CRC. */ + unsigned int rxDaisyChainCalculatedCrc : 16; /* 1E.C842.F:0 RO */ + /* Rx Daisy Chain Calculated CRC + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalDaisyChainStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Fault Message: 1E.C850 */ +/* Global Fault Message: 1E.C850 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Fault Message */ + union + { + struct + { + /*! \brief 1E.C850.F:0 RO Message [F:0] + AQ_GlobalFaultMessage_APPIA.u0.bits_0.message + + + + Error code describing fault + + Notes: + Code 0x8001: Firmware not compatible with chip architecture. This fault occurs when firmware compiled for a different Tensilica core is loaded. + Code 0x8002: VCO calibration failed. This occurs when the main PLLs on chip fail to lock: this is not possible to trigger. + Code 0x8003: XAUI calibration failed. This occurs when the XAUI PLLs fail to lock: this is not possible to trigger. + Code 0x8004: Failed to set operating voltages via PMBus. This only occurs when the processor has control over power supply voltage via an attached PMBus device and there is a protocol error on the I2C bus: this is not possible to trigger. + Code 0x8005: Unexpected device ID. This occurs if the device ID programmed into the internal E-Fuse registers in not valid: this is not possible to trigger. + Code 0x8006: Computed checksum does not match expected checksum. This occurs when the FLASH checksum check performed at boot time fails. This only occurs when the system boots from FLASH. + Code 0x8007: Detected a bit error in static memory. To trigger, corrupt one of the static regions. + Code 0xC001: Illegal Instruction exception. This occurs when the processor attempts to execute an illegal instruction. To trigger this, write an illegal instruction to program memory. It's possible that the bit error check will trigger before the illegal instruction is executed. + Code 0xC002 Instruction Fetch Error. Internal physical address or a data error during instruction fetch: this is not possible to trigger. + Code 0xC003 Load Store Error. Internal physical address or data error during load store operation: this is not possible to trigger.. + Code 0xC004 Privileged Instruction. Attempt to execute a privileged operation without sufficient privilege: this is not possible to trigger. + Code 0xC005 Unaligned Load or Store. Attempt to load or store data at an address which cannot be handled due to alignment: this is not possible to trigger. + Code 0xC006 Instruction fetch from prohibited space: this is not possible to trigger. + Code 0xC007 Data load from prohibited space: this is not possible to trigger. + Code 0xC008 Data store into prohibited space: this is not possible to trigger. */ + unsigned int message : 16; /* 1E.C850.F:0 RO */ + /* Error code describing fault */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalFaultMessage_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Primary Status: 1E.C851 */ +/* Global Primary Status: 1E.C851 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Primary Status */ + union + { + struct + { + /*! \brief 1E.C851.0 RO Primary Status + AQ_GlobalPrimaryStatus_APPIA.u0.bits_0.primaryStatus + + + + 1 = PHY is the primary PHY + 0 = PHY is is secondary PHY + + */ + unsigned int primaryStatus : 1; /* 1E.C851.0 RO */ + /* 1 = PHY is the primary PHY + 0 = PHY is is secondary PHY + */ + unsigned int reserved0 : 15; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalPrimaryStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Cable Diagnostic Impedance: 1E.C880 */ +/* Global Cable Diagnostic Impedance: 1E.C880 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C880.2:0 RO Pair A Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.pairAReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_4 : 3; /* 1E.C880.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C880.3 RO Reserved 4 + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.reserved_4 + + + + Reserved for future use + + */ + unsigned int reserved_4 : 1; /* 1E.C880.3 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C880.6:4 RO Pair A Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.pairAReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_3 : 3; /* 1E.C880.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C880.7 RO Reserved 3 + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.reserved_3 + + + + Reserved for future use + + */ + unsigned int reserved_3 : 1; /* 1E.C880.7 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C880.A:8 RO Pair A Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.pairAReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_2 : 3; /* 1E.C880.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C880.B RO Reserved 2 + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.reserved_2 + + + + Reserved for future use + + */ + unsigned int reserved_2 : 1; /* 1E.C880.B RO */ + /* Reserved for future use + */ + /*! \brief 1E.C880.E:C RO Pair A Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.pairAReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_1 : 3; /* 1E.C880.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C880.F RO Reserved 1 + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.reserved_1 + + + + Reserved for future use + + */ + unsigned int reserved_1 : 1; /* 1E.C880.F RO */ + /* Reserved for future use + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C881.2:0 RO Pair B Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.pairBReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_4 : 3; /* 1E.C881.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C881.3 RO Reserved 8 + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.reserved_8 + + + + Reserved for future use + + */ + unsigned int reserved_8 : 1; /* 1E.C881.3 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C881.6:4 RO Pair B Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.pairBReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_3 : 3; /* 1E.C881.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C881.7 RO Reserved 7 + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.reserved_7 + + + + Reserved for future use + + */ + unsigned int reserved_7 : 1; /* 1E.C881.7 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C881.A:8 RO Pair B Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.pairBReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_2 : 3; /* 1E.C881.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C881.B RO Reserved 6 + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.reserved_6 + + + + Reserved for future use + + */ + unsigned int reserved_6 : 1; /* 1E.C881.B RO */ + /* Reserved for future use + */ + /*! \brief 1E.C881.E:C RO Pair B Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.pairBReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_1 : 3; /* 1E.C881.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C881.F RO Reserved 5 + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.reserved_5 + + + + Reserved for future use + + */ + unsigned int reserved_5 : 1; /* 1E.C881.F RO */ + /* Reserved for future use + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C882.2:0 RO Pair C Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.pairCReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_4 : 3; /* 1E.C882.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C882.3 RO Reserved 12 + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.reserved_12 + + + + Reserved for future use + + */ + unsigned int reserved_12 : 1; /* 1E.C882.3 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C882.6:4 RO Pair C Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.pairCReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_3 : 3; /* 1E.C882.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C882.7 RO Reserved 11 + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.reserved_11 + + + + Reserved for future use + + */ + unsigned int reserved_11 : 1; /* 1E.C882.7 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C882.A:8 RO Pair C Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.pairCReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_2 : 3; /* 1E.C882.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C882.B RO Reserved 10 + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.reserved_10 + + + + Reserved for future use + + */ + unsigned int reserved_10 : 1; /* 1E.C882.B RO */ + /* Reserved for future use + */ + /*! \brief 1E.C882.E:C RO Pair C Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.pairCReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_1 : 3; /* 1E.C882.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C882.F RO Reserved 9 + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.reserved_9 + + + + Reserved for future use + + */ + unsigned int reserved_9 : 1; /* 1E.C882.F RO */ + /* Reserved for future use + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C883.2:0 RO Pair D Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.pairDReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_4 : 3; /* 1E.C883.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C883.3 RO Reserved 16 + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.reserved_16 + + + + Reserved for future use + + */ + unsigned int reserved_16 : 1; /* 1E.C883.3 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C883.6:4 RO Pair D Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.pairDReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_3 : 3; /* 1E.C883.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C883.7 RO Reserved 15 + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.reserved_15 + + + + Reserved for future use + + */ + unsigned int reserved_15 : 1; /* 1E.C883.7 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C883.A:8 RO Pair D Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.pairDReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_2 : 3; /* 1E.C883.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C883.B RO Reserved 14 + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.reserved_14 + + + + Reserved for future use + + */ + unsigned int reserved_14 : 1; /* 1E.C883.B RO */ + /* Reserved for future use + */ + /*! \brief 1E.C883.E:C RO Pair D Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.pairDReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_1 : 3; /* 1E.C883.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C883.F RO Reserved 13 + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.reserved_13 + + + + Reserved for future use + + */ + unsigned int reserved_13 : 1; /* 1E.C883.F RO */ + /* Reserved for future use + */ + } bits_3; + uint16_t word_3; + } u3; +} AQ_GlobalCableDiagnosticImpedance_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Status: 1E.C884 */ +/* Global Status: 1E.C884 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Status */ + union + { + struct + { + /*! \brief 1E.C884.7:0 RO Cable Length [7:0] + AQ_GlobalStatus_APPIA.u0.bits_0.cableLength + + + + The estimated length of the cable in meters + + + Notes: + The length of the cable shown here is estimated from the cable diagnostic engine and should be accurate to +/-1m. */ + unsigned int cableLength : 8; /* 1E.C884.7:0 RO */ + /* The estimated length of the cable in meters + */ + /*! \brief 1E.C884.F:8 RO Reserved Status 0 [7:0] + AQ_GlobalStatus_APPIA.u0.bits_0.reservedStatus_0 + + + + Reserved for future use + + */ + unsigned int reservedStatus_0 : 8; /* 1E.C884.F:8 RO */ + /* Reserved for future use + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Reserved Status: 1E.C885 */ +/* Global Reserved Status: 1E.C885 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Reserved Status */ + union + { + struct + { + /*! \brief 1E.C885.7:0 ROSPD ROM Revision [7:0] + AQ_GlobalReservedStatus_APPIA.u0.bits_0.romRevision + + Provisionable Default = 0x00 + + ROM Revision Number + + + Notes: + Customers may receive multiple ROM images that differ only in their provisioning. This field is used to differentiate those images. This field is used in conjunction with the firmware major and minor revision numbers to uniquely identify ROM images. */ + unsigned int romRevision : 8; /* 1E.C885.7:0 ROSPD Provisionable Default = 0x00 */ + /* ROM Revision Number + */ + /*! \brief 1E.C885.9:8 ROSPD XENPAK NVR Status [1:0] + AQ_GlobalReservedStatus_APPIA.u0.bits_0.xenpakNvrStatus + + Provisionable Default = 0x0 + + Status of XENPAK NVR: + 0: NVR not enabled + 1: Last NVR operation succeeded + 2: Last NVR operation failed + 3: Reserved + + + Notes: + XENPAK register space is mirrored in NVR (SPI ROM). This register indicates the status of the last NVR operation. */ + unsigned int xenpakNvrStatus : 2; /* 1E.C885.9:8 ROSPD Provisionable Default = 0x0 */ + /* Status of XENPAK NVR: + 0: NVR not enabled + 1: Last NVR operation succeeded + 2: Last NVR operation failed + 3: Reserved + */ + /*! \brief 1E.C885.F:A RO Nearly Seconds MSW[5:0] + AQ_GlobalReservedStatus_APPIA.u0.bits_0.nearlySecondsMSW + + + + Bits 16 to 21 of the 22 bit "Nearly Seconds" uptime counter. + + + Notes: + The "Nearly Seconds" counter is incremented every 1024 milliseconds. */ + unsigned int nearlySecondsMSW : 6; /* 1E.C885.F:A RO */ + /* Bits 16 to 21 of the 22 bit "Nearly Seconds" uptime counter. + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Reserved Status */ + union + { + struct + { + /*! \brief 1E.C886.F:0 RO Nearly Seconds LSW[F:0] + AQ_GlobalReservedStatus_APPIA.u1.bits_1.nearlySecondsLSW + + + + Bits 0 to 15 of the 22 bit "Nearly Seconds" uptime counter. + + + Notes: + The "Nearly Seconds" counter is incremented every 1024 milliseconds. */ + unsigned int nearlySecondsLSW : 16; /* 1E.C886.F:0 RO */ + /* Bits 0 to 15 of the 22 bit "Nearly Seconds" uptime counter. + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalReservedStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Alarms: 1E.CC00 */ +/* Global Alarms: 1E.CC00 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Alarms */ + union + { + struct + { + /*! \brief 1E.CC00.0 LH Reserved Alarm D + AQ_GlobalAlarms_APPIA.u0.bits_0.reservedAlarmD + + + + Reserved for future use + + */ + unsigned int reservedAlarmD : 1; /* 1E.CC00.0 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC00.1 LH Reserved Alarm C + AQ_GlobalAlarms_APPIA.u0.bits_0.reservedAlarmC + + + + Reserved for future use + + */ + unsigned int reservedAlarmC : 1; /* 1E.CC00.1 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC00.2 LH Reserved Alarm B + AQ_GlobalAlarms_APPIA.u0.bits_0.reservedAlarmB + + + + Reserved for future use + + */ + unsigned int reservedAlarmB : 1; /* 1E.CC00.2 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC00.3 LH Reserved Alarm A + AQ_GlobalAlarms_APPIA.u0.bits_0.reservedAlarmA + + + + Reserved for future use + + */ + unsigned int reservedAlarmA : 1; /* 1E.CC00.3 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC00.4 LH Device Fault + AQ_GlobalAlarms_APPIA.u0.bits_0.deviceFault + + + + 1 = Fault + + Notes: + When set, a fault has been detected by the uP and the associated 16 bit error code is visible in See Global Configuration Fault Message: Address 1E.C850 */ + unsigned int deviceFault : 1; /* 1E.CC00.4 LH */ + /* 1 = Fault */ + unsigned int reserved2 : 1; + /*! \brief 1E.CC00.6 LH Reset completed + AQ_GlobalAlarms_APPIA.u0.bits_0.resetCompleted + + + + 1 = Chip wide reset completed + + Notes: + This bit is set by the microprocessor when it has completed it's initialization sequence. This bit is mirrored in 1.CC02.0 */ + unsigned int resetCompleted : 1; /* 1E.CC00.6 LH */ + /* 1 = Chip wide reset completed */ + unsigned int reserved1 : 4; + /*! \brief 1E.CC00.B LH Low Temperature Warning + AQ_GlobalAlarms_APPIA.u0.bits_0.lowTemperatureWarning + + + + 1 = Low temperature warning threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int lowTemperatureWarning : 1; /* 1E.CC00.B LH */ + /* 1 = Low temperature warning threshold has been exceeded + */ + /*! \brief 1E.CC00.C LH High Temperature Warning + AQ_GlobalAlarms_APPIA.u0.bits_0.highTemperatureWarning + + + + 1 = High temperature warning threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int highTemperatureWarning : 1; /* 1E.CC00.C LH */ + /* 1 = High temperature warning threshold has been exceeded + */ + /*! \brief 1E.CC00.D LH Low Temperature Failure + AQ_GlobalAlarms_APPIA.u0.bits_0.lowTemperatureFailure + + + + 1 = Low temperature failure threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int lowTemperatureFailure : 1; /* 1E.CC00.D LH */ + /* 1 = Low temperature failure threshold has been exceeded + */ + /*! \brief 1E.CC00.E LH High Temperature Failure + AQ_GlobalAlarms_APPIA.u0.bits_0.highTemperatureFailure + + + + 1 = High temperature failure threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int highTemperatureFailure : 1; /* 1E.CC00.E LH */ + /* 1 = High temperature failure threshold has been exceeded + */ + unsigned int reserved0 : 1; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Alarms */ + union + { + struct + { + /*! \brief 1E.CC01.0 LH Diagnostic Alarm + AQ_GlobalAlarms_APPIA.u1.bits_1.diagnosticAlarm + + + + 1 = Alarm triggered by a write to 1E.C470.7 + + + Notes: + A diagnostic alarm use to test system alarm circuitry */ + unsigned int diagnosticAlarm : 1; /* 1E.CC01.0 LH */ + /* 1 = Alarm triggered by a write to 1E.C470.7 + */ + unsigned int reserved1 : 6; + /*! \brief 1E.CC01.7 LH MDIO Command Handling Overflow + AQ_GlobalAlarms_APPIA.u1.bits_1.mdioCommandHandlingOverflow + + + + 1 = PHY was issued more MDIO requests than it could service in it's request buffer + + + Notes: + Assertion of this bit means that more MDIO commands were issued than FW could handle. */ + unsigned int mdioCommandHandlingOverflow : 1; /* 1E.CC01.7 LH */ + /* 1 = PHY was issued more MDIO requests than it could service in it's request buffer + */ + /*! \brief 1E.CC01.C:8 LH Reserved Alarms [4:0] + AQ_GlobalAlarms_APPIA.u1.bits_1.reservedAlarms + + + + Reserved for future use + + */ + unsigned int reservedAlarms : 5; /* 1E.CC01.C:8 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC01.D RO XENPAK Alarm + AQ_GlobalAlarms_APPIA.u1.bits_1.xenpakAlarm + + + + 1 = XENPAK Alarm + + + Notes: + This alarm is performed by H/W. */ + unsigned int xenpakAlarm : 1; /* 1E.CC01.D RO */ + /* 1 = XENPAK Alarm + */ + /*! \brief 1E.CC01.E LH Smart Power-Down Entered + AQ_GlobalAlarms_APPIA.u1.bits_1.smartPower_downEntered + + + + 1 = Smart Power-Down State Entered + + + Notes: + When this bit is set, it indicates that the Smart Power-Down state was entered */ + unsigned int smartPower_downEntered : 1; /* 1E.CC01.E LH */ + /* 1 = Smart Power-Down State Entered + */ + unsigned int reserved0 : 1; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Alarms */ + union + { + struct + { + /*! \brief 1E.CC02.0 LH Watchdog Timer Alarm + AQ_GlobalAlarms_APPIA.u2.bits_2.watchdogTimerAlarm + + + + 1 = Watchdog timer alarm + + */ + unsigned int watchdogTimerAlarm : 1; /* 1E.CC02.0 LH */ + /* 1 = Watchdog timer alarm + */ + /*! \brief 1E.CC02.1 LH MDIO Timeout Error + AQ_GlobalAlarms_APPIA.u2.bits_2.mdioTimeoutError + + + + 1 = MDIO timeout detected + + */ + unsigned int mdioTimeoutError : 1; /* 1E.CC02.1 LH */ + /* 1 = MDIO timeout detected + */ + /*! \brief 1E.CC02.2 LH MDIO MMD Error + AQ_GlobalAlarms_APPIA.u2.bits_2.mdioMMD_Error + + + + 1 = Invalid MMD address detected + + */ + unsigned int mdioMMD_Error : 1; /* 1E.CC02.2 LH */ + /* 1 = Invalid MMD address detected + */ + unsigned int reserved2 : 2; + /*! \brief 1E.CC02.5 LRF Tx Enable State Change + AQ_GlobalAlarms_APPIA.u2.bits_2.txEnableStateChange + + + + 1 = TX_EN pin has changed state + + */ + unsigned int txEnableStateChange : 1; /* 1E.CC02.5 LRF */ + /* 1 = TX_EN pin has changed state + */ + unsigned int reserved1 : 2; + /*! \brief 1E.CC02.9:8 LH uP IRAM Parity Error [1:0] + AQ_GlobalAlarms_APPIA.u2.bits_2.upIramParityError + + + + 1 = Parity error detected in the uP IRAM + + + Notes: + Bit 0 indicates a parity error was detected in the uP IRAM but was corrected. + Bit 1 indicates a multiple parity errors were detected in the uP IRAM and could not be corrected. + The uP IRAM is protected with ECC. */ + unsigned int upIramParityError : 2; /* 1E.CC02.9:8 LH */ + /* 1 = Parity error detected in the uP IRAM + */ + /*! \brief 1E.CC02.A LH uP DRAM Parity Error + AQ_GlobalAlarms_APPIA.u2.bits_2.upDramParityError + + + + 1 = Parity error detected in the uP DRAM + + */ + unsigned int upDramParityError : 1; /* 1E.CC02.A LH */ + /* 1 = Parity error detected in the uP DRAM + */ + unsigned int reserved0 : 3; + /*! \brief 1E.CC02.E LH Mailbox Operation: Complete + AQ_GlobalAlarms_APPIA.u2.bits_2.mailboxOperation_Complete + + + + 1 = Mailbox operation is complete + + + Notes: + Mailbox interface is ready interrupt for registers See Global Vendor Specific Control - Address 1E.C000 - See Global Vendor Specific Provisioning 5 - Address 1E.C404 */ + unsigned int mailboxOperation_Complete : 1; /* 1E.CC02.E LH */ + /* 1 = Mailbox operation is complete + */ + /*! \brief 1E.CC02.F LH NVR Operation Complete + AQ_GlobalAlarms_APPIA.u2.bits_2.nvrOperationComplete + + + + 1 = NVR operation is complete + + + Notes: + NVR interface is ready interrupt for registers See Global NVR Interface 1: Address 1E.100 - See Global NVR Provisioning Data MSW - Address 1E.17 . */ + unsigned int nvrOperationComplete : 1; /* 1E.CC02.F LH */ + /* 1 = NVR operation is complete + */ + } bits_2; + uint16_t word_2; + } u2; +} AQ_GlobalAlarms_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Interrupt Mask: 1E.D400 */ +/* Global Interrupt Mask: 1E.D400 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Interrupt Mask */ + union + { + struct + { + /*! \brief 1E.D400.0 R/WPD Reserved Alarm D Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.reservedAlarmDMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmDMask : 1; /* 1E.D400.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D400.1 R/WPD Reserved Alarm C Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.reservedAlarmCMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmCMask : 1; /* 1E.D400.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D400.2 R/WPD Reserved Alarm B Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.reservedAlarmBMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmBMask : 1; /* 1E.D400.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D400.3 R/WPD Reserved Alarm A Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.reservedAlarmAMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmAMask : 1; /* 1E.D400.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D400.4 R/WPD Device Fault Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.deviceFaultMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int deviceFaultMask : 1; /* 1E.D400.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved2 : 1; + /*! \brief 1E.D400.6 R/WPD Reset completed Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.resetCompletedMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int resetCompletedMask : 1; /* 1E.D400.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved1 : 4; + /*! \brief 1E.D400.B R/WPD Low Temperature Warning Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.lowTemperatureWarningMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int lowTemperatureWarningMask : 1; /* 1E.D400.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D400.C R/WPD High Temperature Warning Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.highTemperatureWarningMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int highTemperatureWarningMask : 1; /* 1E.D400.C R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D400.D R/WPD Low Temperature Failure Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.lowTemperatureFailureMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int lowTemperatureFailureMask : 1; /* 1E.D400.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D400.E R/WPD High Temperature Failure Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.highTemperatureFailureMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int highTemperatureFailureMask : 1; /* 1E.D400.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved0 : 1; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Interrupt Mask */ + union + { + struct + { + /*! \brief 1E.D401.0 R/WPD Diagnostic Alarm Mask + AQ_GlobalInterruptMask_APPIA.u1.bits_1.diagnosticAlarmMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int diagnosticAlarmMask : 1; /* 1E.D401.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int reserved1 : 6; + /*! \brief 1E.D401.7 R/WPD MDIO Command Handling Overflow Mask + AQ_GlobalInterruptMask_APPIA.u1.bits_1.mdioCommandHandlingOverflowMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int mdioCommandHandlingOverflowMask : 1; /* 1E.D401.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D401.C:8 R/WPD Reserved Alarms Mask [4:0] + AQ_GlobalInterruptMask_APPIA.u1.bits_1.reservedAlarmsMask + + Provisionable Default = 0x00 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmsMask : 5; /* 1E.D401.C:8 R/WPD Provisionable Default = 0x00 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D401.D R/WPD XENPAK Alarm Mask + AQ_GlobalInterruptMask_APPIA.u1.bits_1.xenpakAlarmMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int xenpakAlarmMask : 1; /* 1E.D401.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D401.E R/WPD Smart Power-Down Entered Mask + AQ_GlobalInterruptMask_APPIA.u1.bits_1.smartPower_downEnteredMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int smartPower_downEnteredMask : 1; /* 1E.D401.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int reserved0 : 1; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Interrupt Mask */ + union + { + struct + { + /*! \brief 1E.D402.0 R/WPD Watchdog Timer Alarm Mask + AQ_GlobalInterruptMask_APPIA.u2.bits_2.watchdogTimerAlarmMask + + Provisionable Default = 0x1 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int watchdogTimerAlarmMask : 1; /* 1E.D402.0 R/WPD Provisionable Default = 0x1 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D402.1 R/WPD MDIO Timeout Error Mask + AQ_GlobalInterruptMask_APPIA.u2.bits_2.mdioTimeoutErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int mdioTimeoutErrorMask : 1; /* 1E.D402.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D402.2 R/WPD MDIO MMD Error Mask + AQ_GlobalInterruptMask_APPIA.u2.bits_2.mdioMMD_ErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int mdioMMD_ErrorMask : 1; /* 1E.D402.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved2 : 2; + /*! \brief 1E.D402.5 R/WPD Tx Enable State Change Mask + AQ_GlobalInterruptMask_APPIA.u2.bits_2.txEnableStateChangeMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int txEnableStateChangeMask : 1; /* 1E.D402.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved1 : 2; + /*! \brief 1E.D402.9:8 R/WPD uP IRAM Parity Error Mask [1:0] + AQ_GlobalInterruptMask_APPIA.u2.bits_2.upIramParityErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int upIramParityErrorMask : 2; /* 1E.D402.9:8 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D402.A R/WPD uP DRAM Parity Error Mask + AQ_GlobalInterruptMask_APPIA.u2.bits_2.upDramParityErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int upDramParityErrorMask : 1; /* 1E.D402.A R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int reserved0 : 3; + /*! \brief 1E.D402.E R/WPD Mailbox Operation Complete Mask + AQ_GlobalInterruptMask_APPIA.u2.bits_2.mailboxOperationCompleteMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + Notes: + Mailbox interface is ready interrupt for registers See Global Vendor Specific Control - Address 1E.C000 - See Global Vendor Specific Provisioning 5 - Address 1E.C404 */ + unsigned int mailboxOperationCompleteMask : 1; /* 1E.D402.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D402.F R/WPD NVR Operation Complete Mask + AQ_GlobalInterruptMask_APPIA.u2.bits_2.nvrOperationCompleteMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + Notes: + NVR interface is ready interrupt for registers See Global NVR Interface 1: Address 1E.100 - See Global NVR Provisioning Data MSW - Address 1E.17 */ + unsigned int nvrOperationCompleteMask : 1; /* 1E.D402.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + } bits_2; + uint16_t word_2; + } u2; +} AQ_GlobalInterruptMask_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Chip-Wide Standard Interrupt Flags: 1E.FC00 */ +/* Global Chip-Wide Standard Interrupt Flags: 1E.FC00 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Chip-Wide Standard Interrupt Flags */ + union + { + struct + { + /*! \brief 1E.FC00.0 RO All Vendor Alarms Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.allVendorAlarmsInterrupt + + + + 1 = Interrupt in all vendor alarms + + + Notes: + An interrupt was generated from status register ( See Global Chip-Wide LASI Vendor Interrupt Flags: Address 1E.FC01 ) and the corresponding mask register. ( See Global Interrupt LASI Mask: Address 1E.FF01 ) */ + unsigned int allVendorAlarmsInterrupt : 1; /* 1E.FC00.0 RO */ + /* 1 = Interrupt in all vendor alarms + */ + unsigned int reserved0 : 5; + /*! \brief 1E.FC00.6 RO GbE Standard Alarms Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.gbeStandardAlarmsInterrupt + + + + 1 = Interrupt in GbE standard alarms + + + Notes: + An interrupt was generated from the TGE core. */ + unsigned int gbeStandardAlarmsInterrupt : 1; /* 1E.FC00.6 RO */ + /* 1 = Interrupt in GbE standard alarms + */ + /*! \brief 1E.FC00.7 RO Autonegotiation Standard Alarms 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.autonegotiationStandardAlarms_2Interrupt + + + + 1 = Interrupt in Autonegotiation standard alarms 2 + + + Notes: + An interrupt was generated from status register ( See Autonegotiation 10GBASE-T Status Register - Address 7.21 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int autonegotiationStandardAlarms_2Interrupt : 1; /* 1E.FC00.7 RO */ + /* 1 = Interrupt in Autonegotiation standard alarms 2 + */ + /*! \brief 1E.FC00.8 RO Autonegotiation Standard Alarms 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.autonegotiationStandardAlarms_1Interrupt + + + + 1 = Interrupt in Autonegotiation standard alarms 1 + + + Notes: + An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See Autonegotiation Standard LASI Interrupt Mask 1: Address 7.D000 ) */ + unsigned int autonegotiationStandardAlarms_1Interrupt : 1; /* 1E.FC00.8 RO */ + /* 1 = Interrupt in Autonegotiation standard alarms 1 + */ + /*! \brief 1E.FC00.9 RO PHY XS Standard Alarms 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.phyXS_StandardAlarms_2Interrupt + + + + 1 = Interrupt in PHY XS standard alarms 2 + + + Notes: + An interrupt was generated from the status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int phyXS_StandardAlarms_2Interrupt : 1; /* 1E.FC00.9 RO */ + /* 1 = Interrupt in PHY XS standard alarms 2 + */ + /*! \brief 1E.FC00.A RO PHY XS Standard Alarms 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.phyXS_StandardAlarms_1Interrupt + + + + 1 = Interrupt in PHY XS standard alarms 1 + + + Notes: + An interrupt was generated from the status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ + unsigned int phyXS_StandardAlarms_1Interrupt : 1; /* 1E.FC00.A RO */ + /* 1 = Interrupt in PHY XS standard alarms 1 + */ + /*! \brief 1E.FC00.B RO PCS Standard Alarm 3 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.pcsStandardAlarm_3Interrupt + + + + 1 = Interrupt in PCS standard alarms 3 + + + Notes: + An interrupt was generated from status register ( See PCS 10GBASE-T Status 2 - Address 3.21 ) and the corresponding mask register. ( See PCS Standard Interrupt Mask 1 - Address 3.E021 ) */ + unsigned int pcsStandardAlarm_3Interrupt : 1; /* 1E.FC00.B RO */ + /* 1 = Interrupt in PCS standard alarms 3 + */ + /*! \brief 1E.FC00.C RO PCS Standard Alarm 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.pcsStandardAlarm_2Interrupt + + + + 1 = Interrupt in PCS standard alarms 2 + + + Notes: + An interrupt was generated from status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int pcsStandardAlarm_2Interrupt : 1; /* 1E.FC00.C RO */ + /* 1 = Interrupt in PCS standard alarms 2 + */ + /*! \brief 1E.FC00.D RO PCS Standard Alarm 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.pcsStandardAlarm_1Interrupt + + + + 1 = Interrupt in PCS standard alarms 1 + + + Notes: + An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ + unsigned int pcsStandardAlarm_1Interrupt : 1; /* 1E.FC00.D RO */ + /* 1 = Interrupt in PCS standard alarms 1 + */ + /*! \brief 1E.FC00.E RO PMA Standard Alarm 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.pmaStandardAlarm_2Interrupt + + + + 1 = Interrupt in PMA standard alarms 2 + + + Notes: + An interrupt was generated from either bit 1.8.B or 1.8.A. + An interrupt was generated from status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int pmaStandardAlarm_2Interrupt : 1; /* 1E.FC00.E RO */ + /* 1 = Interrupt in PMA standard alarms 2 + */ + /*! \brief 1E.FC00.F RO PMA Standard Alarm 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.pmaStandardAlarm_1Interrupt + + + + 1 = Interrupt in PMA standard alarms 1 + + + Notes: + An interrupt was generated from bit 1.1.2. + An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ + unsigned int pmaStandardAlarm_1Interrupt : 1; /* 1E.FC00.F RO */ + /* 1 = Interrupt in PMA standard alarms 1 + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalChip_wideStandardInterruptFlags_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Chip-Wide Vendor Interrupt Flags: 1E.FC01 */ +/* Global Chip-Wide Vendor Interrupt Flags: 1E.FC01 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Chip-Wide Vendor Interrupt Flags */ + union + { + struct + { + /*! \brief 1E.FC01.0 RO Global Alarms 3 Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.globalAlarms_3Interrupt + + + + 1 = Interrupt in Global alarms 3 + + + Notes: + An interrupt was generated from status register ( See Global Vendor Alarms 2: Address 1E.CC01 ) and the corresponding mask register. ( See Global LASI Interrupt Mask 2: Address 1E.D401 ) */ + unsigned int globalAlarms_3Interrupt : 1; /* 1E.FC01.0 RO */ + /* 1 = Interrupt in Global alarms 3 + */ + /*! \brief 1E.FC01.1 RO Global Alarms 2 Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.globalAlarms_2Interrupt + + + + 1 = Interrupt in Global alarms 2 + + + Notes: + An interrupt was generated from status register ( See Global Alarms 2: Address 1E.CC01 ) and the corresponding mask register. ( See Global LASI Interrupt Mask 2: Address 1E.D401 ) */ + unsigned int globalAlarms_2Interrupt : 1; /* 1E.FC01.1 RO */ + /* 1 = Interrupt in Global alarms 2 + */ + /*! \brief 1E.FC01.2 RO Global Alarms 1 Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.globalAlarms_1Interrupt + + + + 1 = Interrupt in Global alarms 1 + + + Notes: + An interrupt was generated from status register ( See Global Vendor Alarms 1 - Address 1E.CC00 ) and the corresponding mask register. ( See Global Vendor Interrupt Mask - Address 1E.D400 ) */ + unsigned int globalAlarms_1Interrupt : 1; /* 1E.FC01.2 RO */ + /* 1 = Interrupt in Global alarms 1 + */ + unsigned int reserved0 : 8; + /*! \brief 1E.FC01.B RO GbE Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.gbeVendorAlarmInterrupt + + + + 1 = Interrupt in GbE vendor specific alarm + + + Notes: + A GbE alarm was generated. ( See GbE PHY Vendor Global LASI Interrupt Flags 1: Address 1D.FC00 ) */ + unsigned int gbeVendorAlarmInterrupt : 1; /* 1E.FC01.B RO */ + /* 1 = Interrupt in GbE vendor specific alarm + */ + /*! \brief 1E.FC01.C RO Autonegotiation Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.autonegotiationVendorAlarmInterrupt + + + + 1 = Interrupt in Autonegotiation vendor specific alarm + + + Notes: + An Autonegotiation alarm was generated. ( See Autonegotiation Vendor Global LASI Interrupt Flags 1: Address 7.FC00 ) */ + unsigned int autonegotiationVendorAlarmInterrupt : 1; /* 1E.FC01.C RO */ + /* 1 = Interrupt in Autonegotiation vendor specific alarm + */ + /*! \brief 1E.FC01.D RO PHY XS Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.phyXS_VendorAlarmInterrupt + + + + 1 = Interrupt in PHY XS vendor specific alarm + + + Notes: + A PHY XS alarm was generated. ( See PHY XS Vendor Global LASI Interrupt Flags 1: Address 4.FC00 ) */ + unsigned int phyXS_VendorAlarmInterrupt : 1; /* 1E.FC01.D RO */ + /* 1 = Interrupt in PHY XS vendor specific alarm + */ + /*! \brief 1E.FC01.E RO PCS Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.pcsVendorAlarmInterrupt + + + + 1 = Interrupt in PCS vendor specific alarm + + + Notes: + A PCS alarm was generated. ( See PHY XS Vendor Global Interrupt Flags 1- Address 4.F800 ) */ + unsigned int pcsVendorAlarmInterrupt : 1; /* 1E.FC01.E RO */ + /* 1 = Interrupt in PCS vendor specific alarm + */ + /*! \brief 1E.FC01.F RO PMA Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.pmaVendorAlarmInterrupt + + + + 1 = Interrupt in PMA vendor specific alarm + + + Notes: + A PMA alarm was generated. ( See PHY XS Vendor Global Interrupt Flags 1- Address 4.F800 ) */ + unsigned int pmaVendorAlarmInterrupt : 1; /* 1E.FC01.F RO */ + /* 1 = Interrupt in PMA vendor specific alarm + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalChip_wideVendorInterruptFlags_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Interrupt Chip-Wide Standard Mask: 1E.FF00 */ +/* Global Interrupt Chip-Wide Standard Mask: 1E.FF00 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Interrupt Chip-Wide Standard Mask */ + union + { + struct + { + /*! \brief 1E.FF00.0 R/WPD All Vendor Alarms Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.allVendorAlarmsInterruptMask + + Provisionable Default = 0x1 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int allVendorAlarmsInterruptMask : 1; /* 1E.FF00.0 R/WPD Provisionable Default = 0x1 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved0 : 5; + /*! \brief 1E.FF00.6 R/WPD Gbe Standard Alarms Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.gbeStandardAlarmsInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int gbeStandardAlarmsInterruptMask : 1; /* 1E.FF00.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.7 R/WPD Autonegotiation Standard Alarms 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.autonegotiationStandardAlarms_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int autonegotiationStandardAlarms_2InterruptMask : 1; /* 1E.FF00.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.8 R/WPD Autonegotiation Standard Alarms 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.autonegotiationStandardAlarms_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int autonegotiationStandardAlarms_1InterruptMask : 1; /* 1E.FF00.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.9 R/WPD PHY XS Standard Alarms 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.phyXS_StandardAlarms_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int phyXS_StandardAlarms_2InterruptMask : 1; /* 1E.FF00.9 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.A R/WPD PHY XS Standard Alarms 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.phyXS_StandardAlarms_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int phyXS_StandardAlarms_1InterruptMask : 1; /* 1E.FF00.A R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.B R/WPD PCS Standard Alarm 3 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.pcsStandardAlarm_3InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsStandardAlarm_3InterruptMask : 1; /* 1E.FF00.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.C R/WPD PCS Standard Alarm 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.pcsStandardAlarm_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsStandardAlarm_2InterruptMask : 1; /* 1E.FF00.C R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.D R/WPD PCS Standard Alarm 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.pcsStandardAlarm_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsStandardAlarm_1InterruptMask : 1; /* 1E.FF00.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.E R/WPD PMA Standard Alarm 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.pmaStandardAlarm_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pmaStandardAlarm_2InterruptMask : 1; /* 1E.FF00.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.F R/WPD PMA Standard Alarm 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.pmaStandardAlarm_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pmaStandardAlarm_1InterruptMask : 1; /* 1E.FF00.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalInterruptChip_wideStandardMask_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Interrupt Chip-Wide Vendor Mask: 1E.FF01 */ +/* Global Interrupt Chip-Wide Vendor Mask: 1E.FF01 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Interrupt Chip-Wide Vendor Mask */ + union + { + struct + { + /*! \brief 1E.FF01.0 R/WPD Global Alarms 3 Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.globalAlarms_3InterruptMask + + Provisionable Default = 0x1 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int globalAlarms_3InterruptMask : 1; /* 1E.FF01.0 R/WPD Provisionable Default = 0x1 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.1 R/WPD Global Alarms 2 Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.globalAlarms_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int globalAlarms_2InterruptMask : 1; /* 1E.FF01.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.2 R/WPD Global Alarms 1 Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.globalAlarms_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int globalAlarms_1InterruptMask : 1; /* 1E.FF01.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved0 : 8; + /*! \brief 1E.FF01.B R/WPD GbE Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.gbeVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int gbeVendorAlarmInterruptMask : 1; /* 1E.FF01.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.C R/WPD Autonegotiation Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.autonegotiationVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int autonegotiationVendorAlarmInterruptMask : 1; /* 1E.FF01.C R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.D R/WPD PHY XS Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.phyXS_VendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int phyXS_VendorAlarmInterruptMask : 1; /* 1E.FF01.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.E R/WPD PCS Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.pcsVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsVendorAlarmInterruptMask : 1; /* 1E.FF01.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.F R/WPD PMA Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.pmaVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pmaVendorAlarmInterruptMask : 1; /* 1E.FF01.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalInterruptChip_wideVendorMask_APPIA; + +#endif +/*@}*/ +/*@}*/ diff --git a/qca/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers_Defines.h b/qca/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers_Defines.h new file mode 100644 index 000000000..9c7bb5cb5 --- /dev/null +++ b/qca/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers_Defines.h @@ -0,0 +1,2134 @@ +/*! \file +* This file contains the compiler assist macros and doxygen comments +* for the Global Registers block. +*/ + +/*! \defgroup Global_registers_Defines Global Registers Defines +* This module contains the compiler assist macros and doxygen comments +* for the Global Registers block. +*/ +/*********************************************************************** +* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +* +* $File: //depot/icm/proj/Dena/rev1.0/c/Systems/tools/windows/regMapParser/src/gencheaders.py $ +* +* $Revision: #10 $ +* +* $DateTime: 2014/04/08 16:55:58 $ +* +* $Author: joshd $ +* +* $Label: $ +* +* Description: +* +* This file contains the compiler assist macros for the registers contained in the Global Registers block. +* +* +***********************************************************************/ + + +/*@{*/ +#ifndef AQ_APPIA_GLOBAL_REGS_DEFINES_HEADER +#define AQ_APPIA_GLOBAL_REGS_DEFINES_HEADER + + +/*-----------------------------------------------------------------------------*/ +/*Access macro definitions */ +/*-----------------------------------------------------------------------------*/ +/*! \brief Base register address of structure AQ_GlobalStandardControl_1_APPIA */ +#define AQ_GlobalStandardControl_1_APPIA_baseRegisterAddress 0x0000 +/*! \brief MMD address of structure AQ_GlobalStandardControl_1_APPIA */ +#define AQ_GlobalStandardControl_1_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure softReset in AQ_GlobalStandardControl_1_APPIA */ +#define AQ_GlobalStandardControl_1_APPIA_softReset 0 +/*! \brief Preprocessor variable to relate field to bit position in structure softReset in AQ_GlobalStandardControl_1_APPIA */ +#define bits_AQ_GlobalStandardControl_1_APPIA_softReset u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure softReset in AQ_GlobalStandardControl_1_APPIA */ +#define word_AQ_GlobalStandardControl_1_APPIA_softReset u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure hardReset in AQ_GlobalStandardControl_1_APPIA */ +#define AQ_GlobalStandardControl_1_APPIA_hardReset 0 +/*! \brief Preprocessor variable to relate field to bit position in structure hardReset in AQ_GlobalStandardControl_1_APPIA */ +#define bits_AQ_GlobalStandardControl_1_APPIA_hardReset u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure hardReset in AQ_GlobalStandardControl_1_APPIA */ +#define word_AQ_GlobalStandardControl_1_APPIA_hardReset u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure lowPower in AQ_GlobalStandardControl_1_APPIA */ +#define AQ_GlobalStandardControl_1_APPIA_lowPower 0 +/*! \brief Preprocessor variable to relate field to bit position in structure lowPower in AQ_GlobalStandardControl_1_APPIA */ +#define bits_AQ_GlobalStandardControl_1_APPIA_lowPower u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure lowPower in AQ_GlobalStandardControl_1_APPIA */ +#define word_AQ_GlobalStandardControl_1_APPIA_lowPower u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalStandardDeviceIdentifier_APPIA */ +#define AQ_GlobalStandardDeviceIdentifier_APPIA_baseRegisterAddress 0x0002 +/*! \brief MMD address of structure AQ_GlobalStandardDeviceIdentifier_APPIA */ +#define AQ_GlobalStandardDeviceIdentifier_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure deviceIdMSW in AQ_GlobalStandardDeviceIdentifier_APPIA */ +#define AQ_GlobalStandardDeviceIdentifier_APPIA_deviceIdMSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure deviceIdMSW in AQ_GlobalStandardDeviceIdentifier_APPIA */ +#define bits_AQ_GlobalStandardDeviceIdentifier_APPIA_deviceIdMSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure deviceIdMSW in AQ_GlobalStandardDeviceIdentifier_APPIA */ +#define word_AQ_GlobalStandardDeviceIdentifier_APPIA_deviceIdMSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure deviceIdLSW in AQ_GlobalStandardDeviceIdentifier_APPIA */ +#define AQ_GlobalStandardDeviceIdentifier_APPIA_deviceIdLSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure deviceIdLSW in AQ_GlobalStandardDeviceIdentifier_APPIA */ +#define bits_AQ_GlobalStandardDeviceIdentifier_APPIA_deviceIdLSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure deviceIdLSW in AQ_GlobalStandardDeviceIdentifier_APPIA */ +#define word_AQ_GlobalStandardDeviceIdentifier_APPIA_deviceIdLSW u1.word_1 + +/*! \brief Base register address of structure AQ_GlobalStandardDevicesInPackage_APPIA */ +#define AQ_GlobalStandardDevicesInPackage_APPIA_baseRegisterAddress 0x0005 +/*! \brief MMD address of structure AQ_GlobalStandardDevicesInPackage_APPIA */ +#define AQ_GlobalStandardDevicesInPackage_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define AQ_GlobalStandardDevicesInPackage_APPIA_autonegotiationPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define bits_AQ_GlobalStandardDevicesInPackage_APPIA_autonegotiationPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define word_AQ_GlobalStandardDevicesInPackage_APPIA_autonegotiationPresent u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure tcPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define AQ_GlobalStandardDevicesInPackage_APPIA_tcPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure tcPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define bits_AQ_GlobalStandardDevicesInPackage_APPIA_tcPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure tcPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define word_AQ_GlobalStandardDevicesInPackage_APPIA_tcPresent u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure dteXsPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define AQ_GlobalStandardDevicesInPackage_APPIA_dteXsPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure dteXsPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define bits_AQ_GlobalStandardDevicesInPackage_APPIA_dteXsPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure dteXsPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define word_AQ_GlobalStandardDevicesInPackage_APPIA_dteXsPresent u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure phyXS_Present in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define AQ_GlobalStandardDevicesInPackage_APPIA_phyXS_Present 0 +/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_Present in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define bits_AQ_GlobalStandardDevicesInPackage_APPIA_phyXS_Present u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure phyXS_Present in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define word_AQ_GlobalStandardDevicesInPackage_APPIA_phyXS_Present u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define AQ_GlobalStandardDevicesInPackage_APPIA_pcsPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define bits_AQ_GlobalStandardDevicesInPackage_APPIA_pcsPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define word_AQ_GlobalStandardDevicesInPackage_APPIA_pcsPresent u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure wisPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define AQ_GlobalStandardDevicesInPackage_APPIA_wisPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure wisPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define bits_AQ_GlobalStandardDevicesInPackage_APPIA_wisPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure wisPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define word_AQ_GlobalStandardDevicesInPackage_APPIA_wisPresent u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pmaPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define AQ_GlobalStandardDevicesInPackage_APPIA_pmaPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pmaPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define bits_AQ_GlobalStandardDevicesInPackage_APPIA_pmaPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pmaPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define word_AQ_GlobalStandardDevicesInPackage_APPIA_pmaPresent u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure clause_22RegistersPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define AQ_GlobalStandardDevicesInPackage_APPIA_clause_22RegistersPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure clause_22RegistersPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define bits_AQ_GlobalStandardDevicesInPackage_APPIA_clause_22RegistersPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure clause_22RegistersPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define word_AQ_GlobalStandardDevicesInPackage_APPIA_clause_22RegistersPresent u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalStandardVendorDevicesInPackage_APPIA */ +#define AQ_GlobalStandardVendorDevicesInPackage_APPIA_baseRegisterAddress 0x0006 +/*! \brief MMD address of structure AQ_GlobalStandardVendorDevicesInPackage_APPIA */ +#define AQ_GlobalStandardVendorDevicesInPackage_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure vendorSpecificDevice_2Present in AQ_GlobalStandardVendorDevicesInPackage_APPIA */ +#define AQ_GlobalStandardVendorDevicesInPackage_APPIA_vendorSpecificDevice_2Present 0 +/*! \brief Preprocessor variable to relate field to bit position in structure vendorSpecificDevice_2Present in AQ_GlobalStandardVendorDevicesInPackage_APPIA */ +#define bits_AQ_GlobalStandardVendorDevicesInPackage_APPIA_vendorSpecificDevice_2Present u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure vendorSpecificDevice_2Present in AQ_GlobalStandardVendorDevicesInPackage_APPIA */ +#define word_AQ_GlobalStandardVendorDevicesInPackage_APPIA_vendorSpecificDevice_2Present u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure vendorSpecificDevice_1Present in AQ_GlobalStandardVendorDevicesInPackage_APPIA */ +#define AQ_GlobalStandardVendorDevicesInPackage_APPIA_vendorSpecificDevice_1Present 0 +/*! \brief Preprocessor variable to relate field to bit position in structure vendorSpecificDevice_1Present in AQ_GlobalStandardVendorDevicesInPackage_APPIA */ +#define bits_AQ_GlobalStandardVendorDevicesInPackage_APPIA_vendorSpecificDevice_1Present u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure vendorSpecificDevice_1Present in AQ_GlobalStandardVendorDevicesInPackage_APPIA */ +#define word_AQ_GlobalStandardVendorDevicesInPackage_APPIA_vendorSpecificDevice_1Present u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure clause_22ExtensionPresent in AQ_GlobalStandardVendorDevicesInPackage_APPIA */ +#define AQ_GlobalStandardVendorDevicesInPackage_APPIA_clause_22ExtensionPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure clause_22ExtensionPresent in AQ_GlobalStandardVendorDevicesInPackage_APPIA */ +#define bits_AQ_GlobalStandardVendorDevicesInPackage_APPIA_clause_22ExtensionPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure clause_22ExtensionPresent in AQ_GlobalStandardVendorDevicesInPackage_APPIA */ +#define word_AQ_GlobalStandardVendorDevicesInPackage_APPIA_clause_22ExtensionPresent u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalStandardStatus_2_APPIA */ +#define AQ_GlobalStandardStatus_2_APPIA_baseRegisterAddress 0x0008 +/*! \brief MMD address of structure AQ_GlobalStandardStatus_2_APPIA */ +#define AQ_GlobalStandardStatus_2_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure devicePresent in AQ_GlobalStandardStatus_2_APPIA */ +#define AQ_GlobalStandardStatus_2_APPIA_devicePresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure devicePresent in AQ_GlobalStandardStatus_2_APPIA */ +#define bits_AQ_GlobalStandardStatus_2_APPIA_devicePresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure devicePresent in AQ_GlobalStandardStatus_2_APPIA */ +#define word_AQ_GlobalStandardStatus_2_APPIA_devicePresent u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalStandardPackageIdentifier_APPIA */ +#define AQ_GlobalStandardPackageIdentifier_APPIA_baseRegisterAddress 0x000E +/*! \brief MMD address of structure AQ_GlobalStandardPackageIdentifier_APPIA */ +#define AQ_GlobalStandardPackageIdentifier_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure packageIdMSW in AQ_GlobalStandardPackageIdentifier_APPIA */ +#define AQ_GlobalStandardPackageIdentifier_APPIA_packageIdMSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure packageIdMSW in AQ_GlobalStandardPackageIdentifier_APPIA */ +#define bits_AQ_GlobalStandardPackageIdentifier_APPIA_packageIdMSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure packageIdMSW in AQ_GlobalStandardPackageIdentifier_APPIA */ +#define word_AQ_GlobalStandardPackageIdentifier_APPIA_packageIdMSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure packageIdLSW in AQ_GlobalStandardPackageIdentifier_APPIA */ +#define AQ_GlobalStandardPackageIdentifier_APPIA_packageIdLSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure packageIdLSW in AQ_GlobalStandardPackageIdentifier_APPIA */ +#define bits_AQ_GlobalStandardPackageIdentifier_APPIA_packageIdLSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure packageIdLSW in AQ_GlobalStandardPackageIdentifier_APPIA */ +#define word_AQ_GlobalStandardPackageIdentifier_APPIA_packageIdLSW u1.word_1 + +/*! \brief Base register address of structure AQ_GlobalFirmwareID_APPIA */ +#define AQ_GlobalFirmwareID_APPIA_baseRegisterAddress 0x0020 +/*! \brief MMD address of structure AQ_GlobalFirmwareID_APPIA */ +#define AQ_GlobalFirmwareID_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure firmwareMajorRevisionNumber in AQ_GlobalFirmwareID_APPIA */ +#define AQ_GlobalFirmwareID_APPIA_firmwareMajorRevisionNumber 0 +/*! \brief Preprocessor variable to relate field to bit position in structure firmwareMajorRevisionNumber in AQ_GlobalFirmwareID_APPIA */ +#define bits_AQ_GlobalFirmwareID_APPIA_firmwareMajorRevisionNumber u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure firmwareMajorRevisionNumber in AQ_GlobalFirmwareID_APPIA */ +#define word_AQ_GlobalFirmwareID_APPIA_firmwareMajorRevisionNumber u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure firmwareMinorRevisionNumber in AQ_GlobalFirmwareID_APPIA */ +#define AQ_GlobalFirmwareID_APPIA_firmwareMinorRevisionNumber 0 +/*! \brief Preprocessor variable to relate field to bit position in structure firmwareMinorRevisionNumber in AQ_GlobalFirmwareID_APPIA */ +#define bits_AQ_GlobalFirmwareID_APPIA_firmwareMinorRevisionNumber u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure firmwareMinorRevisionNumber in AQ_GlobalFirmwareID_APPIA */ +#define word_AQ_GlobalFirmwareID_APPIA_firmwareMinorRevisionNumber u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalChipIdentification_APPIA */ +#define AQ_GlobalChipIdentification_APPIA_baseRegisterAddress 0x0021 +/*! \brief MMD address of structure AQ_GlobalChipIdentification_APPIA */ +#define AQ_GlobalChipIdentification_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure chipIdentification in AQ_GlobalChipIdentification_APPIA */ +#define AQ_GlobalChipIdentification_APPIA_chipIdentification 0 +/*! \brief Preprocessor variable to relate field to bit position in structure chipIdentification in AQ_GlobalChipIdentification_APPIA */ +#define bits_AQ_GlobalChipIdentification_APPIA_chipIdentification u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure chipIdentification in AQ_GlobalChipIdentification_APPIA */ +#define word_AQ_GlobalChipIdentification_APPIA_chipIdentification u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalChipRevision_APPIA */ +#define AQ_GlobalChipRevision_APPIA_baseRegisterAddress 0x0022 +/*! \brief MMD address of structure AQ_GlobalChipRevision_APPIA */ +#define AQ_GlobalChipRevision_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure chipRevision in AQ_GlobalChipRevision_APPIA */ +#define AQ_GlobalChipRevision_APPIA_chipRevision 0 +/*! \brief Preprocessor variable to relate field to bit position in structure chipRevision in AQ_GlobalChipRevision_APPIA */ +#define bits_AQ_GlobalChipRevision_APPIA_chipRevision u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure chipRevision in AQ_GlobalChipRevision_APPIA */ +#define word_AQ_GlobalChipRevision_APPIA_chipRevision u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalNvrInterface_APPIA */ +#define AQ_GlobalNvrInterface_APPIA_baseRegisterAddress 0x0100 +/*! \brief MMD address of structure AQ_GlobalNvrInterface_APPIA */ +#define AQ_GlobalNvrInterface_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure nvrExecuteOperation in AQ_GlobalNvrInterface_APPIA */ +#define AQ_GlobalNvrInterface_APPIA_nvrExecuteOperation 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrExecuteOperation in AQ_GlobalNvrInterface_APPIA */ +#define bits_AQ_GlobalNvrInterface_APPIA_nvrExecuteOperation u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrExecuteOperation in AQ_GlobalNvrInterface_APPIA */ +#define word_AQ_GlobalNvrInterface_APPIA_nvrExecuteOperation u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrWriteMode in AQ_GlobalNvrInterface_APPIA */ +#define AQ_GlobalNvrInterface_APPIA_nvrWriteMode 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrWriteMode in AQ_GlobalNvrInterface_APPIA */ +#define bits_AQ_GlobalNvrInterface_APPIA_nvrWriteMode u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrWriteMode in AQ_GlobalNvrInterface_APPIA */ +#define word_AQ_GlobalNvrInterface_APPIA_nvrWriteMode u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure freezeNvrCrc in AQ_GlobalNvrInterface_APPIA */ +#define AQ_GlobalNvrInterface_APPIA_freezeNvrCrc 0 +/*! \brief Preprocessor variable to relate field to bit position in structure freezeNvrCrc in AQ_GlobalNvrInterface_APPIA */ +#define bits_AQ_GlobalNvrInterface_APPIA_freezeNvrCrc u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure freezeNvrCrc in AQ_GlobalNvrInterface_APPIA */ +#define word_AQ_GlobalNvrInterface_APPIA_freezeNvrCrc u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure resetNvrCrc in AQ_GlobalNvrInterface_APPIA */ +#define AQ_GlobalNvrInterface_APPIA_resetNvrCrc 0 +/*! \brief Preprocessor variable to relate field to bit position in structure resetNvrCrc in AQ_GlobalNvrInterface_APPIA */ +#define bits_AQ_GlobalNvrInterface_APPIA_resetNvrCrc u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure resetNvrCrc in AQ_GlobalNvrInterface_APPIA */ +#define word_AQ_GlobalNvrInterface_APPIA_resetNvrCrc u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrBurst in AQ_GlobalNvrInterface_APPIA */ +#define AQ_GlobalNvrInterface_APPIA_nvrBurst 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrBurst in AQ_GlobalNvrInterface_APPIA */ +#define bits_AQ_GlobalNvrInterface_APPIA_nvrBurst u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrBurst in AQ_GlobalNvrInterface_APPIA */ +#define word_AQ_GlobalNvrInterface_APPIA_nvrBurst u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrBusy in AQ_GlobalNvrInterface_APPIA */ +#define AQ_GlobalNvrInterface_APPIA_nvrBusy 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrBusy in AQ_GlobalNvrInterface_APPIA */ +#define bits_AQ_GlobalNvrInterface_APPIA_nvrBusy u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrBusy in AQ_GlobalNvrInterface_APPIA */ +#define word_AQ_GlobalNvrInterface_APPIA_nvrBusy u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrOpcode in AQ_GlobalNvrInterface_APPIA */ +#define AQ_GlobalNvrInterface_APPIA_nvrOpcode 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrOpcode in AQ_GlobalNvrInterface_APPIA */ +#define bits_AQ_GlobalNvrInterface_APPIA_nvrOpcode u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrOpcode in AQ_GlobalNvrInterface_APPIA */ +#define word_AQ_GlobalNvrInterface_APPIA_nvrOpcode u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrMailboxCrc in AQ_GlobalNvrInterface_APPIA */ +#define AQ_GlobalNvrInterface_APPIA_nvrMailboxCrc 1 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrMailboxCrc in AQ_GlobalNvrInterface_APPIA */ +#define bits_AQ_GlobalNvrInterface_APPIA_nvrMailboxCrc u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure nvrMailboxCrc in AQ_GlobalNvrInterface_APPIA */ +#define word_AQ_GlobalNvrInterface_APPIA_nvrMailboxCrc u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure nvrAddressMSW in AQ_GlobalNvrInterface_APPIA */ +#define AQ_GlobalNvrInterface_APPIA_nvrAddressMSW 2 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrAddressMSW in AQ_GlobalNvrInterface_APPIA */ +#define bits_AQ_GlobalNvrInterface_APPIA_nvrAddressMSW u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure nvrAddressMSW in AQ_GlobalNvrInterface_APPIA */ +#define word_AQ_GlobalNvrInterface_APPIA_nvrAddressMSW u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure nvrAddressLSW in AQ_GlobalNvrInterface_APPIA */ +#define AQ_GlobalNvrInterface_APPIA_nvrAddressLSW 3 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrAddressLSW in AQ_GlobalNvrInterface_APPIA */ +#define bits_AQ_GlobalNvrInterface_APPIA_nvrAddressLSW u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure nvrAddressLSW in AQ_GlobalNvrInterface_APPIA */ +#define word_AQ_GlobalNvrInterface_APPIA_nvrAddressLSW u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure nvrDataMSW in AQ_GlobalNvrInterface_APPIA */ +#define AQ_GlobalNvrInterface_APPIA_nvrDataMSW 4 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrDataMSW in AQ_GlobalNvrInterface_APPIA */ +#define bits_AQ_GlobalNvrInterface_APPIA_nvrDataMSW u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure nvrDataMSW in AQ_GlobalNvrInterface_APPIA */ +#define word_AQ_GlobalNvrInterface_APPIA_nvrDataMSW u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure nvrDataLSW in AQ_GlobalNvrInterface_APPIA */ +#define AQ_GlobalNvrInterface_APPIA_nvrDataLSW 5 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrDataLSW in AQ_GlobalNvrInterface_APPIA */ +#define bits_AQ_GlobalNvrInterface_APPIA_nvrDataLSW u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure nvrDataLSW in AQ_GlobalNvrInterface_APPIA */ +#define word_AQ_GlobalNvrInterface_APPIA_nvrDataLSW u5.word_5 + +/*! \brief Base register address of structure AQ_GlobalMailboxInterface_APPIA */ +#define AQ_GlobalMailboxInterface_APPIA_baseRegisterAddress 0x0200 +/*! \brief MMD address of structure AQ_GlobalMailboxInterface_APPIA */ +#define AQ_GlobalMailboxInterface_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxExecuteOperation in AQ_GlobalMailboxInterface_APPIA */ +#define AQ_GlobalMailboxInterface_APPIA_upMailboxExecuteOperation 0 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxExecuteOperation in AQ_GlobalMailboxInterface_APPIA */ +#define bits_AQ_GlobalMailboxInterface_APPIA_upMailboxExecuteOperation u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxExecuteOperation in AQ_GlobalMailboxInterface_APPIA */ +#define word_AQ_GlobalMailboxInterface_APPIA_upMailboxExecuteOperation u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxWriteMode in AQ_GlobalMailboxInterface_APPIA */ +#define AQ_GlobalMailboxInterface_APPIA_upMailboxWriteMode 0 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxWriteMode in AQ_GlobalMailboxInterface_APPIA */ +#define bits_AQ_GlobalMailboxInterface_APPIA_upMailboxWriteMode u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxWriteMode in AQ_GlobalMailboxInterface_APPIA */ +#define word_AQ_GlobalMailboxInterface_APPIA_upMailboxWriteMode u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure resetUpMailboxCrc in AQ_GlobalMailboxInterface_APPIA */ +#define AQ_GlobalMailboxInterface_APPIA_resetUpMailboxCrc 0 +/*! \brief Preprocessor variable to relate field to bit position in structure resetUpMailboxCrc in AQ_GlobalMailboxInterface_APPIA */ +#define bits_AQ_GlobalMailboxInterface_APPIA_resetUpMailboxCrc u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure resetUpMailboxCrc in AQ_GlobalMailboxInterface_APPIA */ +#define word_AQ_GlobalMailboxInterface_APPIA_resetUpMailboxCrc u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxBusy in AQ_GlobalMailboxInterface_APPIA */ +#define AQ_GlobalMailboxInterface_APPIA_upMailboxBusy 0 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxBusy in AQ_GlobalMailboxInterface_APPIA */ +#define bits_AQ_GlobalMailboxInterface_APPIA_upMailboxBusy u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxBusy in AQ_GlobalMailboxInterface_APPIA */ +#define word_AQ_GlobalMailboxInterface_APPIA_upMailboxBusy u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxCrc in AQ_GlobalMailboxInterface_APPIA */ +#define AQ_GlobalMailboxInterface_APPIA_upMailboxCrc 1 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxCrc in AQ_GlobalMailboxInterface_APPIA */ +#define bits_AQ_GlobalMailboxInterface_APPIA_upMailboxCrc u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxCrc in AQ_GlobalMailboxInterface_APPIA */ +#define word_AQ_GlobalMailboxInterface_APPIA_upMailboxCrc u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxAddressMSW in AQ_GlobalMailboxInterface_APPIA */ +#define AQ_GlobalMailboxInterface_APPIA_upMailboxAddressMSW 2 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxAddressMSW in AQ_GlobalMailboxInterface_APPIA */ +#define bits_AQ_GlobalMailboxInterface_APPIA_upMailboxAddressMSW u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxAddressMSW in AQ_GlobalMailboxInterface_APPIA */ +#define word_AQ_GlobalMailboxInterface_APPIA_upMailboxAddressMSW u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxAddressLSW in AQ_GlobalMailboxInterface_APPIA */ +#define AQ_GlobalMailboxInterface_APPIA_upMailboxAddressLSW 3 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxAddressLSW in AQ_GlobalMailboxInterface_APPIA */ +#define bits_AQ_GlobalMailboxInterface_APPIA_upMailboxAddressLSW u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxAddressLSW in AQ_GlobalMailboxInterface_APPIA */ +#define word_AQ_GlobalMailboxInterface_APPIA_upMailboxAddressLSW u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxAddressLSW_Don_tCare in AQ_GlobalMailboxInterface_APPIA */ +#define AQ_GlobalMailboxInterface_APPIA_upMailboxAddressLSW_Don_tCare 3 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxAddressLSW_Don_tCare in AQ_GlobalMailboxInterface_APPIA */ +#define bits_AQ_GlobalMailboxInterface_APPIA_upMailboxAddressLSW_Don_tCare u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxAddressLSW_Don_tCare in AQ_GlobalMailboxInterface_APPIA */ +#define word_AQ_GlobalMailboxInterface_APPIA_upMailboxAddressLSW_Don_tCare u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxDataMSW in AQ_GlobalMailboxInterface_APPIA */ +#define AQ_GlobalMailboxInterface_APPIA_upMailboxDataMSW 4 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxDataMSW in AQ_GlobalMailboxInterface_APPIA */ +#define bits_AQ_GlobalMailboxInterface_APPIA_upMailboxDataMSW u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxDataMSW in AQ_GlobalMailboxInterface_APPIA */ +#define word_AQ_GlobalMailboxInterface_APPIA_upMailboxDataMSW u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxDataLSW in AQ_GlobalMailboxInterface_APPIA */ +#define AQ_GlobalMailboxInterface_APPIA_upMailboxDataLSW 5 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxDataLSW in AQ_GlobalMailboxInterface_APPIA */ +#define bits_AQ_GlobalMailboxInterface_APPIA_upMailboxDataLSW u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxDataLSW in AQ_GlobalMailboxInterface_APPIA */ +#define word_AQ_GlobalMailboxInterface_APPIA_upMailboxDataLSW u5.word_5 + +/*! \brief Base register address of structure AQ_GlobalMicroprocessorScratchPad_APPIA */ +#define AQ_GlobalMicroprocessorScratchPad_APPIA_baseRegisterAddress 0x0300 +/*! \brief MMD address of structure AQ_GlobalMicroprocessorScratchPad_APPIA */ +#define AQ_GlobalMicroprocessorScratchPad_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure scratchPad_1 in AQ_GlobalMicroprocessorScratchPad_APPIA */ +#define AQ_GlobalMicroprocessorScratchPad_APPIA_scratchPad_1 0 +/*! \brief Preprocessor variable to relate field to bit position in structure scratchPad_1 in AQ_GlobalMicroprocessorScratchPad_APPIA */ +#define bits_AQ_GlobalMicroprocessorScratchPad_APPIA_scratchPad_1 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure scratchPad_1 in AQ_GlobalMicroprocessorScratchPad_APPIA */ +#define word_AQ_GlobalMicroprocessorScratchPad_APPIA_scratchPad_1 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure scratchPad_2 in AQ_GlobalMicroprocessorScratchPad_APPIA */ +#define AQ_GlobalMicroprocessorScratchPad_APPIA_scratchPad_2 1 +/*! \brief Preprocessor variable to relate field to bit position in structure scratchPad_2 in AQ_GlobalMicroprocessorScratchPad_APPIA */ +#define bits_AQ_GlobalMicroprocessorScratchPad_APPIA_scratchPad_2 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure scratchPad_2 in AQ_GlobalMicroprocessorScratchPad_APPIA */ +#define word_AQ_GlobalMicroprocessorScratchPad_APPIA_scratchPad_2 u1.word_1 + +/*! \brief Base register address of structure AQ_GlobalControl_APPIA */ +#define AQ_GlobalControl_APPIA_baseRegisterAddress 0xC000 +/*! \brief MMD address of structure AQ_GlobalControl_APPIA */ +#define AQ_GlobalControl_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure upReset in AQ_GlobalControl_APPIA */ +#define AQ_GlobalControl_APPIA_upReset 1 +/*! \brief Preprocessor variable to relate field to bit position in structure upReset in AQ_GlobalControl_APPIA */ +#define bits_AQ_GlobalControl_APPIA_upReset u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure upReset in AQ_GlobalControl_APPIA */ +#define word_AQ_GlobalControl_APPIA_upReset u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure upRunStallOverride in AQ_GlobalControl_APPIA */ +#define AQ_GlobalControl_APPIA_upRunStallOverride 1 +/*! \brief Preprocessor variable to relate field to bit position in structure upRunStallOverride in AQ_GlobalControl_APPIA */ +#define bits_AQ_GlobalControl_APPIA_upRunStallOverride u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure upRunStallOverride in AQ_GlobalControl_APPIA */ +#define word_AQ_GlobalControl_APPIA_upRunStallOverride u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure upRunStall in AQ_GlobalControl_APPIA */ +#define AQ_GlobalControl_APPIA_upRunStall 1 +/*! \brief Preprocessor variable to relate field to bit position in structure upRunStall in AQ_GlobalControl_APPIA */ +#define bits_AQ_GlobalControl_APPIA_upRunStall u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure upRunStall in AQ_GlobalControl_APPIA */ +#define word_AQ_GlobalControl_APPIA_upRunStall u1.word_1 + +/*! \brief Base register address of structure AQ_GlobalResetControl_APPIA */ +#define AQ_GlobalResetControl_APPIA_baseRegisterAddress 0xC006 +/*! \brief MMD address of structure AQ_GlobalResetControl_APPIA */ +#define AQ_GlobalResetControl_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure globalMMD_ResetDisable in AQ_GlobalResetControl_APPIA */ +#define AQ_GlobalResetControl_APPIA_globalMMD_ResetDisable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure globalMMD_ResetDisable in AQ_GlobalResetControl_APPIA */ +#define bits_AQ_GlobalResetControl_APPIA_globalMMD_ResetDisable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure globalMMD_ResetDisable in AQ_GlobalResetControl_APPIA */ +#define word_AQ_GlobalResetControl_APPIA_globalMMD_ResetDisable u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalDiagnosticProvisioning_APPIA */ +#define AQ_GlobalDiagnosticProvisioning_APPIA_baseRegisterAddress 0xC400 +/*! \brief MMD address of structure AQ_GlobalDiagnosticProvisioning_APPIA */ +#define AQ_GlobalDiagnosticProvisioning_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure enableDiagnostics in AQ_GlobalDiagnosticProvisioning_APPIA */ +#define AQ_GlobalDiagnosticProvisioning_APPIA_enableDiagnostics 0 +/*! \brief Preprocessor variable to relate field to bit position in structure enableDiagnostics in AQ_GlobalDiagnosticProvisioning_APPIA */ +#define bits_AQ_GlobalDiagnosticProvisioning_APPIA_enableDiagnostics u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure enableDiagnostics in AQ_GlobalDiagnosticProvisioning_APPIA */ +#define word_AQ_GlobalDiagnosticProvisioning_APPIA_enableDiagnostics u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalThermalProvisioning_APPIA */ +#define AQ_GlobalThermalProvisioning_APPIA_baseRegisterAddress 0xC420 +/*! \brief MMD address of structure AQ_GlobalThermalProvisioning_APPIA */ +#define AQ_GlobalThermalProvisioning_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure reserved_0 in AQ_GlobalThermalProvisioning_APPIA */ +#define AQ_GlobalThermalProvisioning_APPIA_reserved_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_0 in AQ_GlobalThermalProvisioning_APPIA */ +#define bits_AQ_GlobalThermalProvisioning_APPIA_reserved_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_0 in AQ_GlobalThermalProvisioning_APPIA */ +#define word_AQ_GlobalThermalProvisioning_APPIA_reserved_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure highTempFailureThreshold in AQ_GlobalThermalProvisioning_APPIA */ +#define AQ_GlobalThermalProvisioning_APPIA_highTempFailureThreshold 1 +/*! \brief Preprocessor variable to relate field to bit position in structure highTempFailureThreshold in AQ_GlobalThermalProvisioning_APPIA */ +#define bits_AQ_GlobalThermalProvisioning_APPIA_highTempFailureThreshold u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure highTempFailureThreshold in AQ_GlobalThermalProvisioning_APPIA */ +#define word_AQ_GlobalThermalProvisioning_APPIA_highTempFailureThreshold u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure lowTempFailureThreshold in AQ_GlobalThermalProvisioning_APPIA */ +#define AQ_GlobalThermalProvisioning_APPIA_lowTempFailureThreshold 2 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTempFailureThreshold in AQ_GlobalThermalProvisioning_APPIA */ +#define bits_AQ_GlobalThermalProvisioning_APPIA_lowTempFailureThreshold u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure lowTempFailureThreshold in AQ_GlobalThermalProvisioning_APPIA */ +#define word_AQ_GlobalThermalProvisioning_APPIA_lowTempFailureThreshold u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure highTempWarningThreshold in AQ_GlobalThermalProvisioning_APPIA */ +#define AQ_GlobalThermalProvisioning_APPIA_highTempWarningThreshold 3 +/*! \brief Preprocessor variable to relate field to bit position in structure highTempWarningThreshold in AQ_GlobalThermalProvisioning_APPIA */ +#define bits_AQ_GlobalThermalProvisioning_APPIA_highTempWarningThreshold u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure highTempWarningThreshold in AQ_GlobalThermalProvisioning_APPIA */ +#define word_AQ_GlobalThermalProvisioning_APPIA_highTempWarningThreshold u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure lowTempWarningThreshold in AQ_GlobalThermalProvisioning_APPIA */ +#define AQ_GlobalThermalProvisioning_APPIA_lowTempWarningThreshold 4 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTempWarningThreshold in AQ_GlobalThermalProvisioning_APPIA */ +#define bits_AQ_GlobalThermalProvisioning_APPIA_lowTempWarningThreshold u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure lowTempWarningThreshold in AQ_GlobalThermalProvisioning_APPIA */ +#define word_AQ_GlobalThermalProvisioning_APPIA_lowTempWarningThreshold u4.word_4 + +/*! \brief Base register address of structure AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_baseRegisterAddress 0xC430 +/*! \brief MMD address of structure AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure led_0ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_0ManualSet 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_0ManualSet u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_0ManualSet u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_0_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_0_10Gb_sLinkEstablished 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_0_10Gb_sLinkEstablished u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_0_10Gb_sLinkEstablished u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_0_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_0_1Gb_sLinkEstablished 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_0_1Gb_sLinkEstablished u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_0_1Gb_sLinkEstablished u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_0_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_0_100Mb_sLinkEstablished 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_0_100Mb_sLinkEstablished u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_0_100Mb_sLinkEstablished u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_0Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_0Connecting 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_0Connecting u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_0Connecting u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_0ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_0ReceiveActivity 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_0ReceiveActivity u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_0ReceiveActivity u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_0TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_0TransmitActivity 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_0TransmitActivity u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_0TransmitActivity u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_0ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_0ActivityStretch 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_0ActivityStretch u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_0ActivityStretch u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_1ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_1ManualSet 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_1ManualSet u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_1ManualSet u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_1_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_1_10Gb_sLinkEstablished 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_1_10Gb_sLinkEstablished u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_1_10Gb_sLinkEstablished u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_1_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_1_1Gb_sLinkEstablished 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_1_1Gb_sLinkEstablished u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_1_1Gb_sLinkEstablished u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_1_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_1_100Mb_sLinkEstablished 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_1_100Mb_sLinkEstablished u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_1_100Mb_sLinkEstablished u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_1Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_1Connecting 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_1Connecting u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_1Connecting u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_1ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_1ReceiveActivity 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_1ReceiveActivity u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_1ReceiveActivity u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_1TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_1TransmitActivity 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_1TransmitActivity u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_1TransmitActivity u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_1ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_1ActivityStretch 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_1ActivityStretch u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_1ActivityStretch u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_2ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_2ManualSet 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_2ManualSet u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_2ManualSet u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_2_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_2_10Gb_sLinkEstablished 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_2_10Gb_sLinkEstablished u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_2_10Gb_sLinkEstablished u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_2_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_2_1Gb_sLinkEstablished 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_2_1Gb_sLinkEstablished u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_2_1Gb_sLinkEstablished u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_2_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_2_100Mb_sLinkEstablished 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_2_100Mb_sLinkEstablished u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_2_100Mb_sLinkEstablished u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_2Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_2Connecting 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_2Connecting u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_2Connecting u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_2ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_2ReceiveActivity 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_2ReceiveActivity u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_2ReceiveActivity u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_2TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_2TransmitActivity 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_2TransmitActivity u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_2TransmitActivity u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_2ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_2ActivityStretch 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_2ActivityStretch u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_2ActivityStretch u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_3ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_3ManualSet 3 +/*! \brief Preprocessor variable to relate field to bit position in structure led_3ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_3ManualSet u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure led_3ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_3ManualSet u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure led_3_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_3_10Gb_sLinkEstablished 3 +/*! \brief Preprocessor variable to relate field to bit position in structure led_3_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_3_10Gb_sLinkEstablished u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure led_3_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_3_10Gb_sLinkEstablished u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure led_3_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_3_1Gb_sLinkEstablished 3 +/*! \brief Preprocessor variable to relate field to bit position in structure led_3_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_3_1Gb_sLinkEstablished u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure led_3_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_3_1Gb_sLinkEstablished u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure led_3_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_3_100Mb_sLinkEstablished 3 +/*! \brief Preprocessor variable to relate field to bit position in structure led_3_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_3_100Mb_sLinkEstablished u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure led_3_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_3_100Mb_sLinkEstablished u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure led_3Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_3Connecting 3 +/*! \brief Preprocessor variable to relate field to bit position in structure led_3Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_3Connecting u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure led_3Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_3Connecting u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure led_3ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_3ReceiveActivity 3 +/*! \brief Preprocessor variable to relate field to bit position in structure led_3ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_3ReceiveActivity u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure led_3ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_3ReceiveActivity u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure led_3TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_3TransmitActivity 3 +/*! \brief Preprocessor variable to relate field to bit position in structure led_3TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_3TransmitActivity u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure led_3TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_3TransmitActivity u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure led_3ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_3ActivityStretch 3 +/*! \brief Preprocessor variable to relate field to bit position in structure led_3ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_3ActivityStretch u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure led_3ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_3ActivityStretch u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure led_4ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_4ManualSet 4 +/*! \brief Preprocessor variable to relate field to bit position in structure led_4ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_4ManualSet u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure led_4ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_4ManualSet u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure led_4_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_4_10Gb_sLinkEstablished 4 +/*! \brief Preprocessor variable to relate field to bit position in structure led_4_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_4_10Gb_sLinkEstablished u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure led_4_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_4_10Gb_sLinkEstablished u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure led_4_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_4_1Gb_sLinkEstablished 4 +/*! \brief Preprocessor variable to relate field to bit position in structure led_4_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_4_1Gb_sLinkEstablished u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure led_4_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_4_1Gb_sLinkEstablished u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure led_4_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_4_100Mb_sLinkEstablished 4 +/*! \brief Preprocessor variable to relate field to bit position in structure led_4_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_4_100Mb_sLinkEstablished u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure led_4_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_4_100Mb_sLinkEstablished u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure led_4Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_4Connecting 4 +/*! \brief Preprocessor variable to relate field to bit position in structure led_4Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_4Connecting u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure led_4Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_4Connecting u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure led_4ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_4ReceiveActivity 4 +/*! \brief Preprocessor variable to relate field to bit position in structure led_4ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_4ReceiveActivity u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure led_4ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_4ReceiveActivity u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure led_4TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_4TransmitActivity 4 +/*! \brief Preprocessor variable to relate field to bit position in structure led_4TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_4TransmitActivity u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure led_4TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_4TransmitActivity u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure led_4ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_4ActivityStretch 4 +/*! \brief Preprocessor variable to relate field to bit position in structure led_4ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_4ActivityStretch u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure led_4ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_4ActivityStretch u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure led_5ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_5ManualSet 5 +/*! \brief Preprocessor variable to relate field to bit position in structure led_5ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_5ManualSet u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure led_5ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_5ManualSet u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure led_5_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_5_10Gb_sLinkEstablished 5 +/*! \brief Preprocessor variable to relate field to bit position in structure led_5_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_5_10Gb_sLinkEstablished u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure led_5_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_5_10Gb_sLinkEstablished u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure led_5_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_5_1Gb_sLinkEstablished 5 +/*! \brief Preprocessor variable to relate field to bit position in structure led_5_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_5_1Gb_sLinkEstablished u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure led_5_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_5_1Gb_sLinkEstablished u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure led_5_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_5_100Mb_sLinkEstablished 5 +/*! \brief Preprocessor variable to relate field to bit position in structure led_5_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_5_100Mb_sLinkEstablished u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure led_5_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_5_100Mb_sLinkEstablished u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure led_5Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_5Connecting 5 +/*! \brief Preprocessor variable to relate field to bit position in structure led_5Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_5Connecting u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure led_5Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_5Connecting u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure led_5ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_5ReceiveActivity 5 +/*! \brief Preprocessor variable to relate field to bit position in structure led_5ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_5ReceiveActivity u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure led_5ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_5ReceiveActivity u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure led_5TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_5TransmitActivity 5 +/*! \brief Preprocessor variable to relate field to bit position in structure led_5TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_5TransmitActivity u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure led_5TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_5TransmitActivity u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure led_5ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_5ActivityStretch 5 +/*! \brief Preprocessor variable to relate field to bit position in structure led_5ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_5ActivityStretch u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure led_5ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_5ActivityStretch u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure ledOperationMode in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_ledOperationMode 7 +/*! \brief Preprocessor variable to relate field to bit position in structure ledOperationMode in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_ledOperationMode u7.bits_7 +/*! \brief Preprocessor variable to relate field to word position in structure ledOperationMode in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_ledOperationMode u7.word_7 +/*! \brief Preprocessor variable to relate field to word number in structure led_0DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_0DriveThreeStateSelect 8 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_0DriveThreeStateSelect u8.bits_8 +/*! \brief Preprocessor variable to relate field to word position in structure led_0DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_0DriveThreeStateSelect u8.word_8 +/*! \brief Preprocessor variable to relate field to word number in structure led_0ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_0ActiveHighSelect 8 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_0ActiveHighSelect u8.bits_8 +/*! \brief Preprocessor variable to relate field to word position in structure led_0ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_0ActiveHighSelect u8.word_8 +/*! \brief Preprocessor variable to relate field to word number in structure led_0ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_0ManualActiveSelect 8 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_0ManualActiveSelect u8.bits_8 +/*! \brief Preprocessor variable to relate field to word position in structure led_0ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_0ManualActiveSelect u8.word_8 +/*! \brief Preprocessor variable to relate field to word number in structure led_1DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_1DriveThreeStateSelect 9 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_1DriveThreeStateSelect u9.bits_9 +/*! \brief Preprocessor variable to relate field to word position in structure led_1DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_1DriveThreeStateSelect u9.word_9 +/*! \brief Preprocessor variable to relate field to word number in structure led_1ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_1ActiveHighSelect 9 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_1ActiveHighSelect u9.bits_9 +/*! \brief Preprocessor variable to relate field to word position in structure led_1ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_1ActiveHighSelect u9.word_9 +/*! \brief Preprocessor variable to relate field to word number in structure led_1ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_1ManualActiveSelect 9 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_1ManualActiveSelect u9.bits_9 +/*! \brief Preprocessor variable to relate field to word position in structure led_1ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_1ManualActiveSelect u9.word_9 +/*! \brief Preprocessor variable to relate field to word number in structure led_2DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_2DriveThreeStateSelect 10 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_2DriveThreeStateSelect u10.bits_10 +/*! \brief Preprocessor variable to relate field to word position in structure led_2DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_2DriveThreeStateSelect u10.word_10 +/*! \brief Preprocessor variable to relate field to word number in structure led_2ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_2ActiveHighSelect 10 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_2ActiveHighSelect u10.bits_10 +/*! \brief Preprocessor variable to relate field to word position in structure led_2ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_2ActiveHighSelect u10.word_10 +/*! \brief Preprocessor variable to relate field to word number in structure led_2ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_2ManualActiveSelect 10 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_2ManualActiveSelect u10.bits_10 +/*! \brief Preprocessor variable to relate field to word position in structure led_2ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_2ManualActiveSelect u10.word_10 +/*! \brief Preprocessor variable to relate field to word number in structure led_3DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_3DriveThreeStateSelect 11 +/*! \brief Preprocessor variable to relate field to bit position in structure led_3DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_3DriveThreeStateSelect u11.bits_11 +/*! \brief Preprocessor variable to relate field to word position in structure led_3DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_3DriveThreeStateSelect u11.word_11 +/*! \brief Preprocessor variable to relate field to word number in structure led_3ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_3ActiveHighSelect 11 +/*! \brief Preprocessor variable to relate field to bit position in structure led_3ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_3ActiveHighSelect u11.bits_11 +/*! \brief Preprocessor variable to relate field to word position in structure led_3ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_3ActiveHighSelect u11.word_11 +/*! \brief Preprocessor variable to relate field to word number in structure led_3ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_3ManualActiveSelect 11 +/*! \brief Preprocessor variable to relate field to bit position in structure led_3ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_3ManualActiveSelect u11.bits_11 +/*! \brief Preprocessor variable to relate field to word position in structure led_3ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_3ManualActiveSelect u11.word_11 +/*! \brief Preprocessor variable to relate field to word number in structure led_4DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_4DriveThreeStateSelect 12 +/*! \brief Preprocessor variable to relate field to bit position in structure led_4DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_4DriveThreeStateSelect u12.bits_12 +/*! \brief Preprocessor variable to relate field to word position in structure led_4DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_4DriveThreeStateSelect u12.word_12 +/*! \brief Preprocessor variable to relate field to word number in structure led_4ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_4ActiveHighSelect 12 +/*! \brief Preprocessor variable to relate field to bit position in structure led_4ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_4ActiveHighSelect u12.bits_12 +/*! \brief Preprocessor variable to relate field to word position in structure led_4ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_4ActiveHighSelect u12.word_12 +/*! \brief Preprocessor variable to relate field to word number in structure led_4ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_4ManualActiveSelect 12 +/*! \brief Preprocessor variable to relate field to bit position in structure led_4ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_4ManualActiveSelect u12.bits_12 +/*! \brief Preprocessor variable to relate field to word position in structure led_4ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_4ManualActiveSelect u12.word_12 +/*! \brief Preprocessor variable to relate field to word number in structure led_5DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_5DriveThreeStateSelect 13 +/*! \brief Preprocessor variable to relate field to bit position in structure led_5DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_5DriveThreeStateSelect u13.bits_13 +/*! \brief Preprocessor variable to relate field to word position in structure led_5DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_5DriveThreeStateSelect u13.word_13 +/*! \brief Preprocessor variable to relate field to word number in structure led_5ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_5ActiveHighSelect 13 +/*! \brief Preprocessor variable to relate field to bit position in structure led_5ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_5ActiveHighSelect u13.bits_13 +/*! \brief Preprocessor variable to relate field to word position in structure led_5ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_5ActiveHighSelect u13.word_13 +/*! \brief Preprocessor variable to relate field to word number in structure led_5ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_5ManualActiveSelect 13 +/*! \brief Preprocessor variable to relate field to bit position in structure led_5ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_5ManualActiveSelect u13.bits_13 +/*! \brief Preprocessor variable to relate field to word position in structure led_5ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_5ManualActiveSelect u13.word_13 + +/*! \brief Base register address of structure AQ_GlobalGeneralProvisioning_APPIA */ +#define AQ_GlobalGeneralProvisioning_APPIA_baseRegisterAddress 0xC440 +/*! \brief MMD address of structure AQ_GlobalGeneralProvisioning_APPIA */ +#define AQ_GlobalGeneralProvisioning_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure gangLoadMdioAddress in AQ_GlobalGeneralProvisioning_APPIA */ +#define AQ_GlobalGeneralProvisioning_APPIA_gangLoadMdioAddress 0 +/*! \brief Preprocessor variable to relate field to bit position in structure gangLoadMdioAddress in AQ_GlobalGeneralProvisioning_APPIA */ +#define bits_AQ_GlobalGeneralProvisioning_APPIA_gangLoadMdioAddress u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure gangLoadMdioAddress in AQ_GlobalGeneralProvisioning_APPIA */ +#define word_AQ_GlobalGeneralProvisioning_APPIA_gangLoadMdioAddress u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure gangLoadMdioWriteOnly in AQ_GlobalGeneralProvisioning_APPIA */ +#define AQ_GlobalGeneralProvisioning_APPIA_gangLoadMdioWriteOnly 0 +/*! \brief Preprocessor variable to relate field to bit position in structure gangLoadMdioWriteOnly in AQ_GlobalGeneralProvisioning_APPIA */ +#define bits_AQ_GlobalGeneralProvisioning_APPIA_gangLoadMdioWriteOnly u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure gangLoadMdioWriteOnly in AQ_GlobalGeneralProvisioning_APPIA */ +#define word_AQ_GlobalGeneralProvisioning_APPIA_gangLoadMdioWriteOnly u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mdioBroadcastModeEnable in AQ_GlobalGeneralProvisioning_APPIA */ +#define AQ_GlobalGeneralProvisioning_APPIA_mdioBroadcastModeEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioBroadcastModeEnable in AQ_GlobalGeneralProvisioning_APPIA */ +#define bits_AQ_GlobalGeneralProvisioning_APPIA_mdioBroadcastModeEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mdioBroadcastModeEnable in AQ_GlobalGeneralProvisioning_APPIA */ +#define word_AQ_GlobalGeneralProvisioning_APPIA_mdioBroadcastModeEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mdioReadMSW_FirstEnable in AQ_GlobalGeneralProvisioning_APPIA */ +#define AQ_GlobalGeneralProvisioning_APPIA_mdioReadMSW_FirstEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioReadMSW_FirstEnable in AQ_GlobalGeneralProvisioning_APPIA */ +#define bits_AQ_GlobalGeneralProvisioning_APPIA_mdioReadMSW_FirstEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mdioReadMSW_FirstEnable in AQ_GlobalGeneralProvisioning_APPIA */ +#define word_AQ_GlobalGeneralProvisioning_APPIA_mdioReadMSW_FirstEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mdioDriveConfiguration in AQ_GlobalGeneralProvisioning_APPIA */ +#define AQ_GlobalGeneralProvisioning_APPIA_mdioDriveConfiguration 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioDriveConfiguration in AQ_GlobalGeneralProvisioning_APPIA */ +#define bits_AQ_GlobalGeneralProvisioning_APPIA_mdioDriveConfiguration u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mdioDriveConfiguration in AQ_GlobalGeneralProvisioning_APPIA */ +#define word_AQ_GlobalGeneralProvisioning_APPIA_mdioDriveConfiguration u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mdioPreambleDetectionDisable in AQ_GlobalGeneralProvisioning_APPIA */ +#define AQ_GlobalGeneralProvisioning_APPIA_mdioPreambleDetectionDisable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioPreambleDetectionDisable in AQ_GlobalGeneralProvisioning_APPIA */ +#define bits_AQ_GlobalGeneralProvisioning_APPIA_mdioPreambleDetectionDisable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mdioPreambleDetectionDisable in AQ_GlobalGeneralProvisioning_APPIA */ +#define word_AQ_GlobalGeneralProvisioning_APPIA_mdioPreambleDetectionDisable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mdioAddressReset in AQ_GlobalGeneralProvisioning_APPIA */ +#define AQ_GlobalGeneralProvisioning_APPIA_mdioAddressReset 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioAddressReset in AQ_GlobalGeneralProvisioning_APPIA */ +#define bits_AQ_GlobalGeneralProvisioning_APPIA_mdioAddressReset u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mdioAddressReset in AQ_GlobalGeneralProvisioning_APPIA */ +#define word_AQ_GlobalGeneralProvisioning_APPIA_mdioAddressReset u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure daisyChainReset in AQ_GlobalGeneralProvisioning_APPIA */ +#define AQ_GlobalGeneralProvisioning_APPIA_daisyChainReset 2 +/*! \brief Preprocessor variable to relate field to bit position in structure daisyChainReset in AQ_GlobalGeneralProvisioning_APPIA */ +#define bits_AQ_GlobalGeneralProvisioning_APPIA_daisyChainReset u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure daisyChainReset in AQ_GlobalGeneralProvisioning_APPIA */ +#define word_AQ_GlobalGeneralProvisioning_APPIA_daisyChainReset u2.word_2 + +/*! \brief Base register address of structure AQ_GlobalNvrProvisioning_APPIA */ +#define AQ_GlobalNvrProvisioning_APPIA_baseRegisterAddress 0xC450 +/*! \brief MMD address of structure AQ_GlobalNvrProvisioning_APPIA */ +#define AQ_GlobalNvrProvisioning_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure nvrDataLength in AQ_GlobalNvrProvisioning_APPIA */ +#define AQ_GlobalNvrProvisioning_APPIA_nvrDataLength 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrDataLength in AQ_GlobalNvrProvisioning_APPIA */ +#define bits_AQ_GlobalNvrProvisioning_APPIA_nvrDataLength u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrDataLength in AQ_GlobalNvrProvisioning_APPIA */ +#define word_AQ_GlobalNvrProvisioning_APPIA_nvrDataLength u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrDummyLength in AQ_GlobalNvrProvisioning_APPIA */ +#define AQ_GlobalNvrProvisioning_APPIA_nvrDummyLength 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrDummyLength in AQ_GlobalNvrProvisioning_APPIA */ +#define bits_AQ_GlobalNvrProvisioning_APPIA_nvrDummyLength u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrDummyLength in AQ_GlobalNvrProvisioning_APPIA */ +#define word_AQ_GlobalNvrProvisioning_APPIA_nvrDummyLength u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrAddressLength in AQ_GlobalNvrProvisioning_APPIA */ +#define AQ_GlobalNvrProvisioning_APPIA_nvrAddressLength 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrAddressLength in AQ_GlobalNvrProvisioning_APPIA */ +#define bits_AQ_GlobalNvrProvisioning_APPIA_nvrAddressLength u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrAddressLength in AQ_GlobalNvrProvisioning_APPIA */ +#define word_AQ_GlobalNvrProvisioning_APPIA_nvrAddressLength u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrAddressLengthOverride in AQ_GlobalNvrProvisioning_APPIA */ +#define AQ_GlobalNvrProvisioning_APPIA_nvrAddressLengthOverride 1 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrAddressLengthOverride in AQ_GlobalNvrProvisioning_APPIA */ +#define bits_AQ_GlobalNvrProvisioning_APPIA_nvrAddressLengthOverride u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure nvrAddressLengthOverride in AQ_GlobalNvrProvisioning_APPIA */ +#define word_AQ_GlobalNvrProvisioning_APPIA_nvrAddressLengthOverride u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure nvrClockDivide in AQ_GlobalNvrProvisioning_APPIA */ +#define AQ_GlobalNvrProvisioning_APPIA_nvrClockDivide 1 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrClockDivide in AQ_GlobalNvrProvisioning_APPIA */ +#define bits_AQ_GlobalNvrProvisioning_APPIA_nvrClockDivide u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure nvrClockDivide in AQ_GlobalNvrProvisioning_APPIA */ +#define word_AQ_GlobalNvrProvisioning_APPIA_nvrClockDivide u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure nvrDaisyChainClockDivideOverride in AQ_GlobalNvrProvisioning_APPIA */ +#define AQ_GlobalNvrProvisioning_APPIA_nvrDaisyChainClockDivideOverride 2 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrDaisyChainClockDivideOverride in AQ_GlobalNvrProvisioning_APPIA */ +#define bits_AQ_GlobalNvrProvisioning_APPIA_nvrDaisyChainClockDivideOverride u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure nvrDaisyChainClockDivideOverride in AQ_GlobalNvrProvisioning_APPIA */ +#define word_AQ_GlobalNvrProvisioning_APPIA_nvrDaisyChainClockDivideOverride u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure nvrDaisyChainDisable in AQ_GlobalNvrProvisioning_APPIA */ +#define AQ_GlobalNvrProvisioning_APPIA_nvrDaisyChainDisable 2 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrDaisyChainDisable in AQ_GlobalNvrProvisioning_APPIA */ +#define bits_AQ_GlobalNvrProvisioning_APPIA_nvrDaisyChainDisable u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure nvrDaisyChainDisable in AQ_GlobalNvrProvisioning_APPIA */ +#define word_AQ_GlobalNvrProvisioning_APPIA_nvrDaisyChainDisable u2.word_2 + +/*! \brief Base register address of structure AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_baseRegisterAddress 0xC470 +/*! \brief MMD address of structure AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure diagnosticsSelect in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_diagnosticsSelect 0 +/*! \brief Preprocessor variable to relate field to bit position in structure diagnosticsSelect in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_diagnosticsSelect u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure diagnosticsSelect in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_diagnosticsSelect u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure extendedMdiDiagnosticsSelect in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_extendedMdiDiagnosticsSelect 0 +/*! \brief Preprocessor variable to relate field to bit position in structure extendedMdiDiagnosticsSelect in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_extendedMdiDiagnosticsSelect u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure extendedMdiDiagnosticsSelect in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_extendedMdiDiagnosticsSelect u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure initiateComponentDiagnostics in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_initiateComponentDiagnostics 0 +/*! \brief Preprocessor variable to relate field to bit position in structure initiateComponentDiagnostics in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_initiateComponentDiagnostics u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure initiateComponentDiagnostics in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_initiateComponentDiagnostics u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure initiateCableDiagnostics in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_initiateCableDiagnostics 0 +/*! \brief Preprocessor variable to relate field to bit position in structure initiateCableDiagnostics in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_initiateCableDiagnostics u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure initiateCableDiagnostics in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_initiateCableDiagnostics u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioning_2 in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_reservedProvisioning_2 1 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioning_2 in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_reservedProvisioning_2 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioning_2 in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_reservedProvisioning_2 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure enableDaisy_chainHop_countOverride in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_enableDaisy_chainHop_countOverride 1 +/*! \brief Preprocessor variable to relate field to bit position in structure enableDaisy_chainHop_countOverride in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_enableDaisy_chainHop_countOverride u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure enableDaisy_chainHop_countOverride in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_enableDaisy_chainHop_countOverride u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure daisy_chainHop_countOverrideValue in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_daisy_chainHop_countOverrideValue 1 +/*! \brief Preprocessor variable to relate field to bit position in structure daisy_chainHop_countOverrideValue in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_daisy_chainHop_countOverrideValue u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure daisy_chainHop_countOverrideValue in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_daisy_chainHop_countOverrideValue u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure enableLvddPowerSupplyTuning in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_enableLvddPowerSupplyTuning 2 +/*! \brief Preprocessor variable to relate field to bit position in structure enableLvddPowerSupplyTuning in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_enableLvddPowerSupplyTuning u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure enableLvddPowerSupplyTuning in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_enableLvddPowerSupplyTuning u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure enableVddPowerSupplyTuning in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_enableVddPowerSupplyTuning 2 +/*! \brief Preprocessor variable to relate field to bit position in structure enableVddPowerSupplyTuning in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_enableVddPowerSupplyTuning u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure enableVddPowerSupplyTuning in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_enableVddPowerSupplyTuning u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure tunableExternalLvddPowerSupplyPresent in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_tunableExternalLvddPowerSupplyPresent 2 +/*! \brief Preprocessor variable to relate field to bit position in structure tunableExternalLvddPowerSupplyPresent in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_tunableExternalLvddPowerSupplyPresent u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure tunableExternalLvddPowerSupplyPresent in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_tunableExternalLvddPowerSupplyPresent u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure tunableExternalVddPowerSupplyPresent in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_tunableExternalVddPowerSupplyPresent 2 +/*! \brief Preprocessor variable to relate field to bit position in structure tunableExternalVddPowerSupplyPresent in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_tunableExternalVddPowerSupplyPresent u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure tunableExternalVddPowerSupplyPresent in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_tunableExternalVddPowerSupplyPresent u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure enableXenpakRegisterSpace in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_enableXenpakRegisterSpace 2 +/*! \brief Preprocessor variable to relate field to bit position in structure enableXenpakRegisterSpace in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_enableXenpakRegisterSpace u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure enableXenpakRegisterSpace in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_enableXenpakRegisterSpace u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure enable_5thChannelRfiCancellation in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_enable_5thChannelRfiCancellation 2 +/*! \brief Preprocessor variable to relate field to bit position in structure enable_5thChannelRfiCancellation in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_enable_5thChannelRfiCancellation u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure enable_5thChannelRfiCancellation in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_enable_5thChannelRfiCancellation u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure trainingSNR in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_trainingSNR 4 +/*! \brief Preprocessor variable to relate field to bit position in structure trainingSNR in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_trainingSNR u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure trainingSNR in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_trainingSNR u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure smartPower_downStatus in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_smartPower_downStatus 5 +/*! \brief Preprocessor variable to relate field to bit position in structure smartPower_downStatus in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_smartPower_downStatus u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure smartPower_downStatus in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_smartPower_downStatus u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioning_6 in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_reservedProvisioning_6 5 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioning_6 in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_reservedProvisioning_6 u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioning_6 in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_reservedProvisioning_6 u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrLpDisableTimer in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_cfrLpDisableTimer 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrLpDisableTimer in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_cfrLpDisableTimer u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrLpDisableTimer in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_cfrLpDisableTimer u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrLpExtendedMaxwait in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_cfrLpExtendedMaxwait 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrLpExtendedMaxwait in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_cfrLpExtendedMaxwait u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrLpExtendedMaxwait in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_cfrLpExtendedMaxwait u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrLpTHP in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_cfrLpTHP 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrLpTHP in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_cfrLpTHP u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrLpTHP in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_cfrLpTHP u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrLpSupport in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_cfrLpSupport 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrLpSupport in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_cfrLpSupport u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrLpSupport in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_cfrLpSupport u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrDisableTimer in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_cfrDisableTimer 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrDisableTimer in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_cfrDisableTimer u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrDisableTimer in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_cfrDisableTimer u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrExtendedMaxwait in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_cfrExtendedMaxwait 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrExtendedMaxwait in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_cfrExtendedMaxwait u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrExtendedMaxwait in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_cfrExtendedMaxwait u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrTHP in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_cfrTHP 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrTHP in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_cfrTHP u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrTHP in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_cfrTHP u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrSupport in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_cfrSupport 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrSupport in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_cfrSupport u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrSupport in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_cfrSupport u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure deadlockAvoidanceEnable in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_deadlockAvoidanceEnable 5 +/*! \brief Preprocessor variable to relate field to bit position in structure deadlockAvoidanceEnable in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_deadlockAvoidanceEnable u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure deadlockAvoidanceEnable in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_deadlockAvoidanceEnable u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure smartPower_downEnable in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_smartPower_downEnable 5 +/*! \brief Preprocessor variable to relate field to bit position in structure smartPower_downEnable in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_smartPower_downEnable u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure smartPower_downEnable in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_smartPower_downEnable u5.word_5 + +/*! \brief Base register address of structure AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_baseRegisterAddress 0xC800 +/*! \brief MMD address of structure AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure pairAStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_pairAStatus 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairAStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairAStatus u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairAStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairAStatus u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairBStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_pairBStatus 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairBStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairBStatus u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairBStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairBStatus u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairCStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_pairCStatus 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairCStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairCStatus u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairCStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairCStatus u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairDStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_pairDStatus 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairDStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairDStatus u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairDStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairDStatus u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_pairAReflection_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairAReflection_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairAReflection_1 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_pairAReflection_2 1 +/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairAReflection_2 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairAReflection_2 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure impulseResponseMSW in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_impulseResponseMSW 2 +/*! \brief Preprocessor variable to relate field to bit position in structure impulseResponseMSW in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_impulseResponseMSW u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure impulseResponseMSW in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_impulseResponseMSW u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_pairBReflection_1 3 +/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairBReflection_1 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairBReflection_1 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_pairBReflection_2 3 +/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairBReflection_2 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairBReflection_2 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure impulseResponseLSW in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_impulseResponseLSW 4 +/*! \brief Preprocessor variable to relate field to bit position in structure impulseResponseLSW in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_impulseResponseLSW u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure impulseResponseLSW in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_impulseResponseLSW u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_pairCReflection_1 5 +/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairCReflection_1 u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairCReflection_1 u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_pairCReflection_2 5 +/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairCReflection_2 u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairCReflection_2 u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_reserved_1 6 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_reserved_1 u6.bits_6 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_reserved_1 u6.word_6 +/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_pairDReflection_1 7 +/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairDReflection_1 u7.bits_7 +/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairDReflection_1 u7.word_7 +/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_pairDReflection_2 7 +/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairDReflection_2 u7.bits_7 +/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairDReflection_2 u7.word_7 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_reserved_2 8 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_reserved_2 u8.bits_8 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_reserved_2 u8.word_8 + +/*! \brief Base register address of structure AQ_GlobalThermalStatus_APPIA */ +#define AQ_GlobalThermalStatus_APPIA_baseRegisterAddress 0xC820 +/*! \brief MMD address of structure AQ_GlobalThermalStatus_APPIA */ +#define AQ_GlobalThermalStatus_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure temperature in AQ_GlobalThermalStatus_APPIA */ +#define AQ_GlobalThermalStatus_APPIA_temperature 0 +/*! \brief Preprocessor variable to relate field to bit position in structure temperature in AQ_GlobalThermalStatus_APPIA */ +#define bits_AQ_GlobalThermalStatus_APPIA_temperature u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure temperature in AQ_GlobalThermalStatus_APPIA */ +#define word_AQ_GlobalThermalStatus_APPIA_temperature u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure temperatureReady in AQ_GlobalThermalStatus_APPIA */ +#define AQ_GlobalThermalStatus_APPIA_temperatureReady 1 +/*! \brief Preprocessor variable to relate field to bit position in structure temperatureReady in AQ_GlobalThermalStatus_APPIA */ +#define bits_AQ_GlobalThermalStatus_APPIA_temperatureReady u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure temperatureReady in AQ_GlobalThermalStatus_APPIA */ +#define word_AQ_GlobalThermalStatus_APPIA_temperatureReady u1.word_1 + +/*! \brief Base register address of structure AQ_GlobalGeneralStatus_APPIA */ +#define AQ_GlobalGeneralStatus_APPIA_baseRegisterAddress 0xC830 +/*! \brief MMD address of structure AQ_GlobalGeneralStatus_APPIA */ +#define AQ_GlobalGeneralStatus_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureFailureState in AQ_GlobalGeneralStatus_APPIA */ +#define AQ_GlobalGeneralStatus_APPIA_highTemperatureFailureState 0 +/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureFailureState in AQ_GlobalGeneralStatus_APPIA */ +#define bits_AQ_GlobalGeneralStatus_APPIA_highTemperatureFailureState u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureFailureState in AQ_GlobalGeneralStatus_APPIA */ +#define word_AQ_GlobalGeneralStatus_APPIA_highTemperatureFailureState u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureFailureState in AQ_GlobalGeneralStatus_APPIA */ +#define AQ_GlobalGeneralStatus_APPIA_lowTemperatureFailureState 0 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureFailureState in AQ_GlobalGeneralStatus_APPIA */ +#define bits_AQ_GlobalGeneralStatus_APPIA_lowTemperatureFailureState u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureFailureState in AQ_GlobalGeneralStatus_APPIA */ +#define word_AQ_GlobalGeneralStatus_APPIA_lowTemperatureFailureState u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureWarningState in AQ_GlobalGeneralStatus_APPIA */ +#define AQ_GlobalGeneralStatus_APPIA_highTemperatureWarningState 0 +/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureWarningState in AQ_GlobalGeneralStatus_APPIA */ +#define bits_AQ_GlobalGeneralStatus_APPIA_highTemperatureWarningState u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureWarningState in AQ_GlobalGeneralStatus_APPIA */ +#define word_AQ_GlobalGeneralStatus_APPIA_highTemperatureWarningState u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureWarningState in AQ_GlobalGeneralStatus_APPIA */ +#define AQ_GlobalGeneralStatus_APPIA_lowTemperatureWarningState 0 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureWarningState in AQ_GlobalGeneralStatus_APPIA */ +#define bits_AQ_GlobalGeneralStatus_APPIA_lowTemperatureWarningState u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureWarningState in AQ_GlobalGeneralStatus_APPIA */ +#define word_AQ_GlobalGeneralStatus_APPIA_lowTemperatureWarningState u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure processorIntensiveMdioOperationIn_Progress in AQ_GlobalGeneralStatus_APPIA */ +#define AQ_GlobalGeneralStatus_APPIA_processorIntensiveMdioOperationIn_Progress 1 +/*! \brief Preprocessor variable to relate field to bit position in structure processorIntensiveMdioOperationIn_Progress in AQ_GlobalGeneralStatus_APPIA */ +#define bits_AQ_GlobalGeneralStatus_APPIA_processorIntensiveMdioOperationIn_Progress u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure processorIntensiveMdioOperationIn_Progress in AQ_GlobalGeneralStatus_APPIA */ +#define word_AQ_GlobalGeneralStatus_APPIA_processorIntensiveMdioOperationIn_Progress u1.word_1 + +/*! \brief Base register address of structure AQ_GlobalPinStatus_APPIA */ +#define AQ_GlobalPinStatus_APPIA_baseRegisterAddress 0xC840 +/*! \brief MMD address of structure AQ_GlobalPinStatus_APPIA */ +#define AQ_GlobalPinStatus_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mdioBootLoad in AQ_GlobalPinStatus_APPIA */ +#define AQ_GlobalPinStatus_APPIA_mdioBootLoad 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioBootLoad in AQ_GlobalPinStatus_APPIA */ +#define bits_AQ_GlobalPinStatus_APPIA_mdioBootLoad u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mdioBootLoad in AQ_GlobalPinStatus_APPIA */ +#define word_AQ_GlobalPinStatus_APPIA_mdioBootLoad u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure packageConnectivity in AQ_GlobalPinStatus_APPIA */ +#define AQ_GlobalPinStatus_APPIA_packageConnectivity 0 +/*! \brief Preprocessor variable to relate field to bit position in structure packageConnectivity in AQ_GlobalPinStatus_APPIA */ +#define bits_AQ_GlobalPinStatus_APPIA_packageConnectivity u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure packageConnectivity in AQ_GlobalPinStatus_APPIA */ +#define word_AQ_GlobalPinStatus_APPIA_packageConnectivity u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure txEnable in AQ_GlobalPinStatus_APPIA */ +#define AQ_GlobalPinStatus_APPIA_txEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure txEnable in AQ_GlobalPinStatus_APPIA */ +#define bits_AQ_GlobalPinStatus_APPIA_txEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure txEnable in AQ_GlobalPinStatus_APPIA */ +#define word_AQ_GlobalPinStatus_APPIA_txEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure ledPullupState in AQ_GlobalPinStatus_APPIA */ +#define AQ_GlobalPinStatus_APPIA_ledPullupState 0 +/*! \brief Preprocessor variable to relate field to bit position in structure ledPullupState in AQ_GlobalPinStatus_APPIA */ +#define bits_AQ_GlobalPinStatus_APPIA_ledPullupState u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure ledPullupState in AQ_GlobalPinStatus_APPIA */ +#define word_AQ_GlobalPinStatus_APPIA_ledPullupState u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalDaisyChainStatus_APPIA */ +#define AQ_GlobalDaisyChainStatus_APPIA_baseRegisterAddress 0xC842 +/*! \brief MMD address of structure AQ_GlobalDaisyChainStatus_APPIA */ +#define AQ_GlobalDaisyChainStatus_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure rxDaisyChainCalculatedCrc in AQ_GlobalDaisyChainStatus_APPIA */ +#define AQ_GlobalDaisyChainStatus_APPIA_rxDaisyChainCalculatedCrc 0 +/*! \brief Preprocessor variable to relate field to bit position in structure rxDaisyChainCalculatedCrc in AQ_GlobalDaisyChainStatus_APPIA */ +#define bits_AQ_GlobalDaisyChainStatus_APPIA_rxDaisyChainCalculatedCrc u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure rxDaisyChainCalculatedCrc in AQ_GlobalDaisyChainStatus_APPIA */ +#define word_AQ_GlobalDaisyChainStatus_APPIA_rxDaisyChainCalculatedCrc u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalFaultMessage_APPIA */ +#define AQ_GlobalFaultMessage_APPIA_baseRegisterAddress 0xC850 +/*! \brief MMD address of structure AQ_GlobalFaultMessage_APPIA */ +#define AQ_GlobalFaultMessage_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure message in AQ_GlobalFaultMessage_APPIA */ +#define AQ_GlobalFaultMessage_APPIA_message 0 +/*! \brief Preprocessor variable to relate field to bit position in structure message in AQ_GlobalFaultMessage_APPIA */ +#define bits_AQ_GlobalFaultMessage_APPIA_message u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure message in AQ_GlobalFaultMessage_APPIA */ +#define word_AQ_GlobalFaultMessage_APPIA_message u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalPrimaryStatus_APPIA */ +#define AQ_GlobalPrimaryStatus_APPIA_baseRegisterAddress 0xC851 +/*! \brief MMD address of structure AQ_GlobalPrimaryStatus_APPIA */ +#define AQ_GlobalPrimaryStatus_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure primaryStatus in AQ_GlobalPrimaryStatus_APPIA */ +#define AQ_GlobalPrimaryStatus_APPIA_primaryStatus 0 +/*! \brief Preprocessor variable to relate field to bit position in structure primaryStatus in AQ_GlobalPrimaryStatus_APPIA */ +#define bits_AQ_GlobalPrimaryStatus_APPIA_primaryStatus u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure primaryStatus in AQ_GlobalPrimaryStatus_APPIA */ +#define word_AQ_GlobalPrimaryStatus_APPIA_primaryStatus u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_baseRegisterAddress 0xC880 +/*! \brief MMD address of structure AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure reserved_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_1 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_1 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_1 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_1 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_1 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_1 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_2 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_2 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_2 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_2 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_2 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_2 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_3 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_3 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_3 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_3 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_3 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_3 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_4 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_4 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_4 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_4 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_4 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_4 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_5 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_5 1 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_5 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_5 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_5 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_5 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_1 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_6 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_6 1 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_6 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_6 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_6 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_6 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_2 1 +/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_2 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_2 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_7 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_7 1 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_7 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_7 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_7 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_7 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_3 1 +/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_3 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_3 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_8 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_8 1 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_8 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_8 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_8 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_8 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_4 1 +/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_4 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_4 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_9 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_9 2 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_9 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_9 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_9 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_9 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_1 2 +/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_1 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_1 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_10 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_10 2 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_10 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_10 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_10 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_10 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_2 2 +/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_2 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_2 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_11 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_11 2 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_11 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_11 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_11 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_11 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_3 2 +/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_3 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_3 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_12 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_12 2 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_12 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_12 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_12 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_12 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_4 2 +/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_4 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_4 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_13 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_13 3 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_13 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_13 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_13 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_13 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_1 3 +/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_1 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_1 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_14 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_14 3 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_14 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_14 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_14 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_14 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_2 3 +/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_2 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_2 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_15 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_15 3 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_15 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_15 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_15 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_15 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_3 3 +/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_3 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_3 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_16 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_16 3 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_16 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_16 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_16 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_16 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_4 3 +/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_4 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_4 u3.word_3 + +/*! \brief Base register address of structure AQ_GlobalStatus_APPIA */ +#define AQ_GlobalStatus_APPIA_baseRegisterAddress 0xC884 +/*! \brief MMD address of structure AQ_GlobalStatus_APPIA */ +#define AQ_GlobalStatus_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure reservedStatus_0 in AQ_GlobalStatus_APPIA */ +#define AQ_GlobalStatus_APPIA_reservedStatus_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedStatus_0 in AQ_GlobalStatus_APPIA */ +#define bits_AQ_GlobalStatus_APPIA_reservedStatus_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedStatus_0 in AQ_GlobalStatus_APPIA */ +#define word_AQ_GlobalStatus_APPIA_reservedStatus_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure cableLength in AQ_GlobalStatus_APPIA */ +#define AQ_GlobalStatus_APPIA_cableLength 0 +/*! \brief Preprocessor variable to relate field to bit position in structure cableLength in AQ_GlobalStatus_APPIA */ +#define bits_AQ_GlobalStatus_APPIA_cableLength u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure cableLength in AQ_GlobalStatus_APPIA */ +#define word_AQ_GlobalStatus_APPIA_cableLength u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalReservedStatus_APPIA */ +#define AQ_GlobalReservedStatus_APPIA_baseRegisterAddress 0xC885 +/*! \brief MMD address of structure AQ_GlobalReservedStatus_APPIA */ +#define AQ_GlobalReservedStatus_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure nearlySecondsMSW in AQ_GlobalReservedStatus_APPIA */ +#define AQ_GlobalReservedStatus_APPIA_nearlySecondsMSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nearlySecondsMSW in AQ_GlobalReservedStatus_APPIA */ +#define bits_AQ_GlobalReservedStatus_APPIA_nearlySecondsMSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nearlySecondsMSW in AQ_GlobalReservedStatus_APPIA */ +#define word_AQ_GlobalReservedStatus_APPIA_nearlySecondsMSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure xenpakNvrStatus in AQ_GlobalReservedStatus_APPIA */ +#define AQ_GlobalReservedStatus_APPIA_xenpakNvrStatus 0 +/*! \brief Preprocessor variable to relate field to bit position in structure xenpakNvrStatus in AQ_GlobalReservedStatus_APPIA */ +#define bits_AQ_GlobalReservedStatus_APPIA_xenpakNvrStatus u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure xenpakNvrStatus in AQ_GlobalReservedStatus_APPIA */ +#define word_AQ_GlobalReservedStatus_APPIA_xenpakNvrStatus u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure romRevision in AQ_GlobalReservedStatus_APPIA */ +#define AQ_GlobalReservedStatus_APPIA_romRevision 0 +/*! \brief Preprocessor variable to relate field to bit position in structure romRevision in AQ_GlobalReservedStatus_APPIA */ +#define bits_AQ_GlobalReservedStatus_APPIA_romRevision u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure romRevision in AQ_GlobalReservedStatus_APPIA */ +#define word_AQ_GlobalReservedStatus_APPIA_romRevision u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nearlySecondsLSW in AQ_GlobalReservedStatus_APPIA */ +#define AQ_GlobalReservedStatus_APPIA_nearlySecondsLSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure nearlySecondsLSW in AQ_GlobalReservedStatus_APPIA */ +#define bits_AQ_GlobalReservedStatus_APPIA_nearlySecondsLSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure nearlySecondsLSW in AQ_GlobalReservedStatus_APPIA */ +#define word_AQ_GlobalReservedStatus_APPIA_nearlySecondsLSW u1.word_1 + +/*! \brief Base register address of structure AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_baseRegisterAddress 0xCC00 +/*! \brief MMD address of structure AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureFailure in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_highTemperatureFailure 0 +/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureFailure in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_highTemperatureFailure u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureFailure in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_highTemperatureFailure u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureFailure in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_lowTemperatureFailure 0 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureFailure in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_lowTemperatureFailure u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureFailure in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_lowTemperatureFailure u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureWarning in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_highTemperatureWarning 0 +/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureWarning in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_highTemperatureWarning u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureWarning in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_highTemperatureWarning u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureWarning in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_lowTemperatureWarning 0 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureWarning in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_lowTemperatureWarning u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureWarning in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_lowTemperatureWarning u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure resetCompleted in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_resetCompleted 0 +/*! \brief Preprocessor variable to relate field to bit position in structure resetCompleted in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_resetCompleted u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure resetCompleted in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_resetCompleted u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure deviceFault in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_deviceFault 0 +/*! \brief Preprocessor variable to relate field to bit position in structure deviceFault in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_deviceFault u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure deviceFault in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_deviceFault u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmA in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_reservedAlarmA 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmA in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_reservedAlarmA u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmA in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_reservedAlarmA u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmB in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_reservedAlarmB 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmB in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_reservedAlarmB u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmB in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_reservedAlarmB u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmC in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_reservedAlarmC 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmC in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_reservedAlarmC u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmC in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_reservedAlarmC u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmD in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_reservedAlarmD 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmD in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_reservedAlarmD u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmD in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_reservedAlarmD u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure smartPower_downEntered in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_smartPower_downEntered 1 +/*! \brief Preprocessor variable to relate field to bit position in structure smartPower_downEntered in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_smartPower_downEntered u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure smartPower_downEntered in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_smartPower_downEntered u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure xenpakAlarm in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_xenpakAlarm 1 +/*! \brief Preprocessor variable to relate field to bit position in structure xenpakAlarm in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_xenpakAlarm u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure xenpakAlarm in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_xenpakAlarm u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarms in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_reservedAlarms 1 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarms in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_reservedAlarms u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarms in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_reservedAlarms u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mdioCommandHandlingOverflow in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_mdioCommandHandlingOverflow 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioCommandHandlingOverflow in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_mdioCommandHandlingOverflow u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mdioCommandHandlingOverflow in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_mdioCommandHandlingOverflow u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure diagnosticAlarm in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_diagnosticAlarm 1 +/*! \brief Preprocessor variable to relate field to bit position in structure diagnosticAlarm in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_diagnosticAlarm u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure diagnosticAlarm in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_diagnosticAlarm u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure nvrOperationComplete in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_nvrOperationComplete 2 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrOperationComplete in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_nvrOperationComplete u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure nvrOperationComplete in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_nvrOperationComplete u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure mailboxOperation_Complete in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_mailboxOperation_Complete 2 +/*! \brief Preprocessor variable to relate field to bit position in structure mailboxOperation_Complete in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_mailboxOperation_Complete u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure mailboxOperation_Complete in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_mailboxOperation_Complete u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure upDramParityError in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_upDramParityError 2 +/*! \brief Preprocessor variable to relate field to bit position in structure upDramParityError in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_upDramParityError u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure upDramParityError in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_upDramParityError u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure upIramParityError in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_upIramParityError 2 +/*! \brief Preprocessor variable to relate field to bit position in structure upIramParityError in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_upIramParityError u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure upIramParityError in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_upIramParityError u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure txEnableStateChange in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_txEnableStateChange 2 +/*! \brief Preprocessor variable to relate field to bit position in structure txEnableStateChange in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_txEnableStateChange u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure txEnableStateChange in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_txEnableStateChange u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure mdioMMD_Error in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_mdioMMD_Error 2 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioMMD_Error in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_mdioMMD_Error u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure mdioMMD_Error in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_mdioMMD_Error u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure mdioTimeoutError in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_mdioTimeoutError 2 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioTimeoutError in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_mdioTimeoutError u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure mdioTimeoutError in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_mdioTimeoutError u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure watchdogTimerAlarm in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_watchdogTimerAlarm 2 +/*! \brief Preprocessor variable to relate field to bit position in structure watchdogTimerAlarm in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_watchdogTimerAlarm u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure watchdogTimerAlarm in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_watchdogTimerAlarm u2.word_2 + +/*! \brief Base register address of structure AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_baseRegisterAddress 0xD400 +/*! \brief MMD address of structure AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureFailureMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_highTemperatureFailureMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureFailureMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_highTemperatureFailureMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureFailureMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_highTemperatureFailureMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureFailureMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_lowTemperatureFailureMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureFailureMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_lowTemperatureFailureMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureFailureMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_lowTemperatureFailureMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureWarningMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_highTemperatureWarningMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureWarningMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_highTemperatureWarningMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureWarningMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_highTemperatureWarningMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureWarningMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_lowTemperatureWarningMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureWarningMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_lowTemperatureWarningMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureWarningMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_lowTemperatureWarningMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure resetCompletedMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_resetCompletedMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure resetCompletedMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_resetCompletedMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure resetCompletedMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_resetCompletedMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure deviceFaultMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_deviceFaultMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure deviceFaultMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_deviceFaultMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure deviceFaultMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_deviceFaultMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmAMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_reservedAlarmAMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmAMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_reservedAlarmAMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmAMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_reservedAlarmAMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmBMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_reservedAlarmBMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmBMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_reservedAlarmBMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmBMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_reservedAlarmBMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmCMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_reservedAlarmCMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmCMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_reservedAlarmCMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmCMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_reservedAlarmCMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmDMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_reservedAlarmDMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmDMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_reservedAlarmDMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmDMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_reservedAlarmDMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure smartPower_downEnteredMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_smartPower_downEnteredMask 1 +/*! \brief Preprocessor variable to relate field to bit position in structure smartPower_downEnteredMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_smartPower_downEnteredMask u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure smartPower_downEnteredMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_smartPower_downEnteredMask u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure xenpakAlarmMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_xenpakAlarmMask 1 +/*! \brief Preprocessor variable to relate field to bit position in structure xenpakAlarmMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_xenpakAlarmMask u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure xenpakAlarmMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_xenpakAlarmMask u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmsMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_reservedAlarmsMask 1 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmsMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_reservedAlarmsMask u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmsMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_reservedAlarmsMask u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mdioCommandHandlingOverflowMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_mdioCommandHandlingOverflowMask 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioCommandHandlingOverflowMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_mdioCommandHandlingOverflowMask u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mdioCommandHandlingOverflowMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_mdioCommandHandlingOverflowMask u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure diagnosticAlarmMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_diagnosticAlarmMask 1 +/*! \brief Preprocessor variable to relate field to bit position in structure diagnosticAlarmMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_diagnosticAlarmMask u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure diagnosticAlarmMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_diagnosticAlarmMask u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure nvrOperationCompleteMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_nvrOperationCompleteMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrOperationCompleteMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_nvrOperationCompleteMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure nvrOperationCompleteMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_nvrOperationCompleteMask u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure mailboxOperationCompleteMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_mailboxOperationCompleteMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure mailboxOperationCompleteMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_mailboxOperationCompleteMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure mailboxOperationCompleteMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_mailboxOperationCompleteMask u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure upDramParityErrorMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_upDramParityErrorMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure upDramParityErrorMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_upDramParityErrorMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure upDramParityErrorMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_upDramParityErrorMask u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure upIramParityErrorMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_upIramParityErrorMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure upIramParityErrorMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_upIramParityErrorMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure upIramParityErrorMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_upIramParityErrorMask u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure txEnableStateChangeMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_txEnableStateChangeMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure txEnableStateChangeMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_txEnableStateChangeMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure txEnableStateChangeMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_txEnableStateChangeMask u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure mdioMMD_ErrorMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_mdioMMD_ErrorMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioMMD_ErrorMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_mdioMMD_ErrorMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure mdioMMD_ErrorMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_mdioMMD_ErrorMask u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure mdioTimeoutErrorMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_mdioTimeoutErrorMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioTimeoutErrorMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_mdioTimeoutErrorMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure mdioTimeoutErrorMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_mdioTimeoutErrorMask u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure watchdogTimerAlarmMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_watchdogTimerAlarmMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure watchdogTimerAlarmMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_watchdogTimerAlarmMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure watchdogTimerAlarmMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_watchdogTimerAlarmMask u2.word_2 + +/*! \brief Base register address of structure AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_baseRegisterAddress 0xFC00 +/*! \brief MMD address of structure AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure pmaStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pmaStandardAlarm_1Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pmaStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pmaStandardAlarm_1Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pmaStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pmaStandardAlarm_1Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pmaStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pmaStandardAlarm_2Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pmaStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pmaStandardAlarm_2Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pmaStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pmaStandardAlarm_2Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pcsStandardAlarm_1Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pcsStandardAlarm_1Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pcsStandardAlarm_1Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pcsStandardAlarm_2Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pcsStandardAlarm_2Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pcsStandardAlarm_2Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_3Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pcsStandardAlarm_3Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_3Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pcsStandardAlarm_3Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_3Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pcsStandardAlarm_3Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure phyXS_StandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_phyXS_StandardAlarms_1Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_StandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_phyXS_StandardAlarms_1Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure phyXS_StandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_phyXS_StandardAlarms_1Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure phyXS_StandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_phyXS_StandardAlarms_2Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_StandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_phyXS_StandardAlarms_2Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure phyXS_StandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_phyXS_StandardAlarms_2Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationStandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_autonegotiationStandardAlarms_1Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationStandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_autonegotiationStandardAlarms_1Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationStandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_autonegotiationStandardAlarms_1Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationStandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_autonegotiationStandardAlarms_2Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationStandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_autonegotiationStandardAlarms_2Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationStandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_autonegotiationStandardAlarms_2Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure gbeStandardAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_gbeStandardAlarmsInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure gbeStandardAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_gbeStandardAlarmsInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure gbeStandardAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_gbeStandardAlarmsInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure allVendorAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_allVendorAlarmsInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure allVendorAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_allVendorAlarmsInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure allVendorAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_allVendorAlarmsInterrupt u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideVendorInterruptFlags_APPIA_baseRegisterAddress 0xFC01 +/*! \brief MMD address of structure AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideVendorInterruptFlags_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure pmaVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideVendorInterruptFlags_APPIA_pmaVendorAlarmInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pmaVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_pmaVendorAlarmInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pmaVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_pmaVendorAlarmInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideVendorInterruptFlags_APPIA_pcsVendorAlarmInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_pcsVendorAlarmInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_pcsVendorAlarmInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure phyXS_VendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideVendorInterruptFlags_APPIA_phyXS_VendorAlarmInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_VendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_phyXS_VendorAlarmInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure phyXS_VendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_phyXS_VendorAlarmInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideVendorInterruptFlags_APPIA_autonegotiationVendorAlarmInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_autonegotiationVendorAlarmInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_autonegotiationVendorAlarmInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure gbeVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideVendorInterruptFlags_APPIA_gbeVendorAlarmInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure gbeVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_gbeVendorAlarmInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure gbeVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_gbeVendorAlarmInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_1Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideVendorInterruptFlags_APPIA_globalAlarms_1Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_1Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_globalAlarms_1Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_1Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_globalAlarms_1Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_2Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideVendorInterruptFlags_APPIA_globalAlarms_2Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_2Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_globalAlarms_2Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_2Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_globalAlarms_2Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_3Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideVendorInterruptFlags_APPIA_globalAlarms_3Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_3Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_globalAlarms_3Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_3Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_globalAlarms_3Interrupt u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_baseRegisterAddress 0xFF00 +/*! \brief MMD address of structure AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure pmaStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_pmaStandardAlarm_1InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pmaStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_pmaStandardAlarm_1InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pmaStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_pmaStandardAlarm_1InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pmaStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_pmaStandardAlarm_2InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pmaStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_pmaStandardAlarm_2InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pmaStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_pmaStandardAlarm_2InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_pcsStandardAlarm_1InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_pcsStandardAlarm_1InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_pcsStandardAlarm_1InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_pcsStandardAlarm_2InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_pcsStandardAlarm_2InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_pcsStandardAlarm_2InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_3InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_pcsStandardAlarm_3InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_3InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_pcsStandardAlarm_3InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_3InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_pcsStandardAlarm_3InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure phyXS_StandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_phyXS_StandardAlarms_1InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_StandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_phyXS_StandardAlarms_1InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure phyXS_StandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_phyXS_StandardAlarms_1InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure phyXS_StandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_phyXS_StandardAlarms_2InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_StandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_phyXS_StandardAlarms_2InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure phyXS_StandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_phyXS_StandardAlarms_2InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationStandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_autonegotiationStandardAlarms_1InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationStandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_autonegotiationStandardAlarms_1InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationStandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_autonegotiationStandardAlarms_1InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationStandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_autonegotiationStandardAlarms_2InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationStandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_autonegotiationStandardAlarms_2InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationStandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_autonegotiationStandardAlarms_2InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure gbeStandardAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_gbeStandardAlarmsInterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure gbeStandardAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_gbeStandardAlarmsInterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure gbeStandardAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_gbeStandardAlarmsInterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure allVendorAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_allVendorAlarmsInterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure allVendorAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_allVendorAlarmsInterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure allVendorAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_allVendorAlarmsInterruptMask u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define AQ_GlobalInterruptChip_wideVendorMask_APPIA_baseRegisterAddress 0xFF01 +/*! \brief MMD address of structure AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define AQ_GlobalInterruptChip_wideVendorMask_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure pmaVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define AQ_GlobalInterruptChip_wideVendorMask_APPIA_pmaVendorAlarmInterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pmaVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_APPIA_pmaVendorAlarmInterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pmaVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_APPIA_pmaVendorAlarmInterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define AQ_GlobalInterruptChip_wideVendorMask_APPIA_pcsVendorAlarmInterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_APPIA_pcsVendorAlarmInterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_APPIA_pcsVendorAlarmInterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure phyXS_VendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define AQ_GlobalInterruptChip_wideVendorMask_APPIA_phyXS_VendorAlarmInterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_VendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_APPIA_phyXS_VendorAlarmInterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure phyXS_VendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_APPIA_phyXS_VendorAlarmInterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define AQ_GlobalInterruptChip_wideVendorMask_APPIA_autonegotiationVendorAlarmInterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_APPIA_autonegotiationVendorAlarmInterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_APPIA_autonegotiationVendorAlarmInterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure gbeVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define AQ_GlobalInterruptChip_wideVendorMask_APPIA_gbeVendorAlarmInterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure gbeVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_APPIA_gbeVendorAlarmInterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure gbeVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_APPIA_gbeVendorAlarmInterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define AQ_GlobalInterruptChip_wideVendorMask_APPIA_globalAlarms_1InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_APPIA_globalAlarms_1InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_APPIA_globalAlarms_1InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define AQ_GlobalInterruptChip_wideVendorMask_APPIA_globalAlarms_2InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_APPIA_globalAlarms_2InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_APPIA_globalAlarms_2InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_3InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define AQ_GlobalInterruptChip_wideVendorMask_APPIA_globalAlarms_3InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_3InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_APPIA_globalAlarms_3InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_3InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_APPIA_globalAlarms_3InterruptMask u0.word_0 +#endif +/*@}*/ +/*@}*/ diff --git a/qca/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers_reversed.h b/qca/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers_reversed.h new file mode 100644 index 000000000..89e02c325 --- /dev/null +++ b/qca/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers_reversed.h @@ -0,0 +1,5581 @@ +/*! \file +* This file contains the data structures and doxygen comments +* for the Global Registers block. + */ + +/*! \addtogroup registerMap + @{ +*/ + +/*! \defgroup Global_registers Global Registers +* This module contains the data structures and doxygen comments +* for the Global Registers block. + */ +/*********************************************************************** +* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +* +* $Date: 2014/04/08 $ +* +* $Label: $ +* +* Description: +* +* This file contains the c header structures for the registers contained in the Global Registers block. +* +* The bit fields in this structure are from MSbit to LSbit +* +***********************************************************************/ + + +/*@{*/ +#ifndef AQ_APPIA_GLOBAL_REGS_HEADER +#define AQ_APPIA_GLOBAL_REGS_HEADER + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Control 1: 1E.0000 */ +/* Global Standard Control 1: 1E.0000 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Control 1 */ + union + { + struct + { + /*! \brief 1E.0000.F R/WSC Soft Reset + AQ_GlobalStandardControl_1_APPIA.u0.bits_0.softReset + + Default = 0x1 + + 1 = Global soft reset + 0 = Normal operation + + + Notes: + Setting this bit initiates a global soft reset on all of the digital logic, including the microprocessor. Upon completion of the reset sequence, this bit is set back to 0. */ + unsigned int softReset : 1; /* 1E.0000.F R/WSC Default = 0x1 */ + /* 1 = Global soft reset + 0 = Normal operation + */ + /*! \brief 1E.0000.E R/WSC Hard Reset + AQ_GlobalStandardControl_1_APPIA.u0.bits_0.hardReset + + Default = 0x0 + + 1 = Global hard reset + 0 = Normal operation + + + Notes: + Setting this bit initiates a global hard reset, equivalent to pulling the reset pin low. This is a level sensitive pin that connects into the power-on reset generation circuitry to initiate a complete power-on reset. */ + unsigned int hardReset : 1; /* 1E.0000.E R/WSC Default = 0x0 */ + /* 1 = Global hard reset + 0 = Normal operation + */ + unsigned int reserved0 : 2; + /*! \brief 1E.0000.B R/WPD Low Power + AQ_GlobalStandardControl_1_APPIA.u0.bits_0.lowPower + + Provisionable Default = 0x0 + + 1 = Low-power mode + 0 = Normal operation + + + Notes: + A one written to this register causes the chip to enter low-power mode. This bit puts the entire chip in low-power mode, with only the MDIO and microprocessor functioning, and turns off the analog front-end: i.e. places it in high-impedance mode. Setting this bit also sets all of the Low Power bits in the other MMDs. */ + unsigned int lowPower : 1; /* 1E.0000.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Low-power mode + 0 = Normal operation + */ + unsigned int reserved1 : 11; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardControl_1_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Device Identifier: 1E.0002 */ +/* Global Standard Device Identifier: 1E.0002 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Device Identifier */ + union + { + struct + { + /*! \brief 1E.0002.F:0 RO Device ID MSW [1F:10] + AQ_GlobalStandardDeviceIdentifier_APPIA.u0.bits_0.deviceIdMSW + + + + Bits 31 - 16 of Device ID + */ + unsigned int deviceIdMSW : 16; /* 1E.0002.F:0 RO */ + /* Bits 31 - 16 of Device ID */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Standard Device Identifier */ + union + { + struct + { + /*! \brief 1E.0003.F:0 RO Device ID LSW [F:0] + AQ_GlobalStandardDeviceIdentifier_APPIA.u1.bits_1.deviceIdLSW + + + + Bits 15 - 0 of Device ID + */ + unsigned int deviceIdLSW : 16; /* 1E.0003.F:0 RO */ + /* Bits 15 - 0 of Device ID */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalStandardDeviceIdentifier_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Devices in Package: 1E.0005 */ +/* Global Standard Devices in Package: 1E.0005 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Devices in Package */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.0005.7 ROS Autonegotiation Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.autonegotiationPresent + + Default = 0x1 + + 1 = Autonegotiation is present in package + 0 = Autonegotiation is not present in package + + Notes: + This is always set to 1, as there is Autonegotiation in the PHY. */ + unsigned int autonegotiationPresent : 1; /* 1E.0005.7 ROS Default = 0x1 */ + /* 1 = Autonegotiation is present in package + 0 = Autonegotiation is not present in package */ + /*! \brief 1E.0005.6 ROS TC Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.tcPresent + + Default = 0x0 + + 1 = TC is present in package + 0 = TC is not present in package + + Notes: + This is always set to 0, as there is no TC functionality in the PHY. */ + unsigned int tcPresent : 1; /* 1E.0005.6 ROS Default = 0x0 */ + /* 1 = TC is present in package + 0 = TC is not present in package */ + /*! \brief 1E.0005.5 ROS DTE XS Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.dteXsPresent + + Default = 0x0 + + 1 = DTE XS is present in package + 0 = DTE XS is not present in package + + + Notes: + This is always set to 0, as there is no DTE XAUI interface in the PHY. */ + unsigned int dteXsPresent : 1; /* 1E.0005.5 ROS Default = 0x0 */ + /* 1 = DTE XS is present in package + 0 = DTE XS is not present in package + */ + /*! \brief 1E.0005.4 ROS PHY XS Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.phyXS_Present + + Default = 0x1 + + 1 = PHY XS is present in package + 0 = PHY XS is not present in package + + Notes: + This is always set to 1 as there is a PHY XS interface in the PHY. */ + unsigned int phyXS_Present : 1; /* 1E.0005.4 ROS Default = 0x1 */ + /* 1 = PHY XS is present in package + 0 = PHY XS is not present in package */ + /*! \brief 1E.0005.3 ROS PCS Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.pcsPresent + + Default = 0x1 + + 1 = PCS is present in package + 0 = PCS is not present in package + + Notes: + This is always set to 1 as there is PCS functionality in the PHY. */ + unsigned int pcsPresent : 1; /* 1E.0005.3 ROS Default = 0x1 */ + /* 1 = PCS is present in package + 0 = PCS is not present in package */ + /*! \brief 1E.0005.2 ROS WIS Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.wisPresent + + Default = 0x0 + + 1 = WIS is present in package + 0 = WIS is not present in package + + Notes: + This is always set to 0, as there is no WIS functionality in the PHY. */ + unsigned int wisPresent : 1; /* 1E.0005.2 ROS Default = 0x0 */ + /* 1 = WIS is present in package + 0 = WIS is not present in package */ + /*! \brief 1E.0005.1 ROS PMA Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.pmaPresent + + Default = 0x1 + + 1 = PMA is present in package + 0 = PMA is not present + + Notes: + This is always set to 1 as there is PMA functionality in the PHY. */ + unsigned int pmaPresent : 1; /* 1E.0005.1 ROS Default = 0x1 */ + /* 1 = PMA is present in package + 0 = PMA is not present */ + /*! \brief 1E.0005.0 ROS Clause 22 Registers Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.clause_22RegistersPresent + + Default = 0x0 + + 1 = Clause 22 registers are present in package + 0 = Clause 22 registers are not present in package + + Notes: + This is always set to 0 in the PHY, as there are no Clause 22 registers in the device. */ + unsigned int clause_22RegistersPresent : 1; /* 1E.0005.0 ROS Default = 0x0 */ + /* 1 = Clause 22 registers are present in package + 0 = Clause 22 registers are not present in package */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardDevicesInPackage_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Vendor Devices in Package: 1E.0006 */ +/* Global Standard Vendor Devices in Package: 1E.0006 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Vendor Devices in Package */ + union + { + struct + { + /*! \brief 1E.0006.F ROS Vendor Specific Device #2 Present + AQ_GlobalStandardVendorDevicesInPackage_APPIA.u0.bits_0.vendorSpecificDevice_2Present + + Default = 0x1 + + 1 = Device #2 is present in package + 0 = Device #2 is not present in package + + Notes: + This is always set to 1 as the PHY utilizes this device for the DSP PMA registers. */ + unsigned int vendorSpecificDevice_2Present : 1; /* 1E.0006.F ROS Default = 0x1 */ + /* 1 = Device #2 is present in package + 0 = Device #2 is not present in package */ + /*! \brief 1E.0006.E ROS Vendor Specific Device #1 Present + AQ_GlobalStandardVendorDevicesInPackage_APPIA.u0.bits_0.vendorSpecificDevice_1Present + + Default = 0x1 + + 1 = Device #1 is present in package + 0 = Device #1 is not present in package + + Notes: + This is always set to 1 as the PHY utilizes this device for the global control registers. */ + unsigned int vendorSpecificDevice_1Present : 1; /* 1E.0006.E ROS Default = 0x1 */ + /* 1 = Device #1 is present in package + 0 = Device #1 is not present in package */ + /*! \brief 1E.0006.D ROS Clause 22 Extension Present + AQ_GlobalStandardVendorDevicesInPackage_APPIA.u0.bits_0.clause_22ExtensionPresent + + Default = 0x1 + + 1 = Clause 22 Extension is present in package + 0 = Clause 22 Extension is not present in package + + Notes: + This is always set to 1 as the PHY utilizes this device for the GbE registers. */ + unsigned int clause_22ExtensionPresent : 1; /* 1E.0006.D ROS Default = 0x1 */ + /* 1 = Clause 22 Extension is present in package + 0 = Clause 22 Extension is not present in package */ + unsigned int reserved0 : 13; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardVendorDevicesInPackage_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Status 2: 1E.0008 */ +/* Global Standard Status 2: 1E.0008 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Status 2 */ + union + { + struct + { + /*! \brief 1E.0008.F:E ROS Device Present [1:0] + AQ_GlobalStandardStatus_2_APPIA.u0.bits_0.devicePresent + + Default = 0x2 + + [F:E] + 0x3 = No device at this address + 0x2 = Device present at this address + 0x1 = No device at this address + 0x0 = No device at this address + + Notes: + This field is always set to 0x2, as the Global MMD resides here in the PHY. */ + unsigned int devicePresent : 2; /* 1E.0008.F:E ROS Default = 0x2 */ + /* [F:E] + 0x3 = No device at this address + 0x2 = Device present at this address + 0x1 = No device at this address + 0x0 = No device at this address */ + unsigned int reserved0 : 14; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardStatus_2_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Package Identifier: 1E.000E */ +/* Global Standard Package Identifier: 1E.000E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Package Identifier */ + union + { + struct + { + /*! \brief 1E.000E.F:0 RO Package ID MSW [1F:10] + AQ_GlobalStandardPackageIdentifier_APPIA.u0.bits_0.packageIdMSW + + + + Bits 31- 16 of Package ID + */ + unsigned int packageIdMSW : 16; /* 1E.000E.F:0 RO */ + /* Bits 31- 16 of Package ID */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Standard Package Identifier */ + union + { + struct + { + /*! \brief 1E.000F.F:0 RO Package ID LSW [F:0] + AQ_GlobalStandardPackageIdentifier_APPIA.u1.bits_1.packageIdLSW + + + + Bits 15 - 0 of Package ID + */ + unsigned int packageIdLSW : 16; /* 1E.000F.F:0 RO */ + /* Bits 15 - 0 of Package ID */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalStandardPackageIdentifier_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Firmware ID: 1E.0020 */ +/* Global Firmware ID: 1E.0020 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Firmware ID */ + union + { + struct + { + /*! \brief 1E.0020.F:8 RO Firmware Major Revision Number [7:0] + AQ_GlobalFirmwareID_APPIA.u0.bits_0.firmwareMajorRevisionNumber + + + + [F:8] = Major revision number + + Notes: + + + The lower six bits of major and minor firmware revision are exchanged in autonegotiation when the PHYID message is sent. */ + unsigned int firmwareMajorRevisionNumber : 8; /* 1E.0020.F:8 RO */ + /* [F:8] = Major revision number */ + /*! \brief 1E.0020.7:0 RO Firmware Minor Revision Number [7:0] + AQ_GlobalFirmwareID_APPIA.u0.bits_0.firmwareMinorRevisionNumber + + + + [7:0] = Minor revision number + + Notes: + + + The lower six bits of major and minor firmware revision are exchanged in autonegotiation when the PHYID message is sent. */ + unsigned int firmwareMinorRevisionNumber : 8; /* 1E.0020.7:0 RO */ + /* [7:0] = Minor revision number */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalFirmwareID_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Chip Identification: 1E.0021 */ +/* Global Chip Identification: 1E.0021 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Chip Identification */ + union + { + struct + { + /*! \brief 1E.0021.F:0 RO Chip Identification [F:0] + AQ_GlobalChipIdentification_APPIA.u0.bits_0.chipIdentification + + + + Hardware Chip ID + + Notes: + This value is a hard-coded chip ID */ + unsigned int chipIdentification : 16; /* 1E.0021.F:0 RO */ + /* Hardware Chip ID */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalChipIdentification_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Chip Revision: 1E.0022 */ +/* Global Chip Revision: 1E.0022 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Chip Revision */ + union + { + struct + { + /*! \brief 1E.0022.F:0 RO Chip Revision [F:0] + AQ_GlobalChipRevision_APPIA.u0.bits_0.chipRevision + + + + Hardware Chip Revision + + Notes: + This value is a hard-coded chip revision */ + unsigned int chipRevision : 16; /* 1E.0022.F:0 RO */ + /* Hardware Chip Revision */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalChipRevision_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global NVR Interface: 1E.0100 */ +/* Global NVR Interface: 1E.0100 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0100.F R/WSC NVR Execute Operation + AQ_GlobalNvrInterface_APPIA.u0.bits_0.nvrExecuteOperation + + Default = 0x0 + + 1 = Start NVR Operation + + + Notes: + When set to 1, the NVR operation will begin. Ensure that the uP is stalled using the See MCP Run Stall bit to ensure no NVR contention. */ + unsigned int nvrExecuteOperation : 1; /* 1E.0100.F R/WSC Default = 0x0 */ + /* 1 = Start NVR Operation + */ + /*! \brief 1E.0100.E R/W NVR Write Mode + AQ_GlobalNvrInterface_APPIA.u0.bits_0.nvrWriteMode + + Default = 0x0 + + 1 = Write to NVR + 0 = Read from NVR + + */ + unsigned int nvrWriteMode : 1; /* 1E.0100.E R/W Default = 0x0 */ + /* 1 = Write to NVR + 0 = Read from NVR + */ + /*! \brief 1E.0100.D R/W Freeze NVR CRC + AQ_GlobalNvrInterface_APPIA.u0.bits_0.freezeNvrCrc + + Default = 0x0 + + 1 = Freeze NVR Mailbox CRC calculation register + + + Notes: + To prevent an erroneous answer, this bit should not be set at the same time the See NVR Operation Valid bit is set. */ + unsigned int freezeNvrCrc : 1; /* 1E.0100.D R/W Default = 0x0 */ + /* 1 = Freeze NVR Mailbox CRC calculation register + */ + /*! \brief 1E.0100.C R/WSC Reset NVR CRC + AQ_GlobalNvrInterface_APPIA.u0.bits_0.resetNvrCrc + + Default = 0x0 + + 1 = Reset NVR Mailbox CRC calculation register + + + Notes: + To prevent an erroneous answer, this bit should not be set at the same time the See NVR Operation Valid bit is set. */ + unsigned int resetNvrCrc : 1; /* 1E.0100.C R/WSC Default = 0x0 */ + /* 1 = Reset NVR Mailbox CRC calculation register + */ + unsigned int reserved0 : 1; + /*! \brief 1E.0100.A R/W NVR Burst + AQ_GlobalNvrInterface_APPIA.u0.bits_0.nvrBurst + + Default = 0x0 + + 0 = Single read or write operation of up to 4 bytes + 1 = Burst operation + + + Notes: + When this bit is set, the operation is a burst operation where more than 32-bits is read from the NVR or written to the NVR. This bit should be set to one until the last burst in the read or write operation, when it should be set to zero. It operates by gating the SPI clock, and not restarting it until new data is ready to be written, or the previous contents have been read. Each burst of data requires the NVR Execute Operation bit to be set to initiate the next phase. */ + unsigned int nvrBurst : 1; /* 1E.0100.A R/W Default = 0x0 */ + /* 0 = Single read or write operation of up to 4 bytes + 1 = Burst operation + */ + unsigned int reserved1 : 1; + /*! \brief 1E.0100.8 RO NVR Busy + AQ_GlobalNvrInterface_APPIA.u0.bits_0.nvrBusy + + + + 1 = NVR is busy + 0 = NVR is ready + + + Notes: + When set to 1, the NVR is busy. A new NVR operation should not occur until this bit is 0. If the NVR clock is greater than 64/63 of the MDIO clock, this bit never needs to be polled when operating over the MDIO. */ + unsigned int nvrBusy : 1; /* 1E.0100.8 RO */ + /* 1 = NVR is busy + 0 = NVR is ready + */ + /*! \brief 1E.0100.7:0 R/W NVR Opcode [7:0] + AQ_GlobalNvrInterface_APPIA.u0.bits_0.nvrOpcode + + Default = 0x03 + + NVR instruction opcode + + */ + unsigned int nvrOpcode : 8; /* 1E.0100.7:0 R/W Default = 0x03 */ + /* NVR instruction opcode + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0101.F:0 RO NVR Mailbox CRC [F:0] + AQ_GlobalNvrInterface_APPIA.u1.bits_1.nvrMailboxCrc + + + + The running CRC-16 of everything passing through the NVR interface + + + Notes: + The CRC-16 over all data written or read through the NVR interface. The CRC-16 is calculated by dividing the data by: + x^16 + x^12 + x^5 + 1 */ + unsigned int nvrMailboxCrc : 16; /* 1E.0101.F:0 RO */ + /* The running CRC-16 of everything passing through the NVR interface + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global NVR Interface */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.0102.7:0 R/W NVR Address MSW [17:10] + AQ_GlobalNvrInterface_APPIA.u2.bits_2.nvrAddressMSW + + Default = 0x00 + + NVR address MSW bits [17:10] + + + Notes: + The address of where to read and write from in the NVR. This is self-incrementing and will automatically increment after each read or write operation. The increment amount is based on the data length (i.e. increments by 4 if the data length is 4 bytes) */ + unsigned int nvrAddressMSW : 8; /* 1E.0102.7:0 R/W Default = 0x00 */ + /* NVR address MSW bits [17:10] + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0103.F:0 R/W NVR Address LSW [F:0] + AQ_GlobalNvrInterface_APPIA.u3.bits_3.nvrAddressLSW + + Default = 0x0000 + + NVR address LSW bits [F:0] + + + Notes: + The address of where to read and write from in the NVR. This is self-incrementing and will automatically increment after each read or write operation. */ + unsigned int nvrAddressLSW : 16; /* 1E.0103.F:0 R/W Default = 0x0000 */ + /* NVR address LSW bits [F:0] + */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0104.F:0 R/W NVR Data MSW [1F:10] + AQ_GlobalNvrInterface_APPIA.u4.bits_4.nvrDataMSW + + Default = 0x0000 + + NVR data MSW bits [1F:10] + + + Notes: + Data is stored and read-out from these registers in little-endian format for operations such as FLASH device ID, and for programming the processor. + + For instance the 64K Atmel device code reads out as two bytes 0x651F into the LSW register, whereas the datasheet indicates that 1F is the first byte read, followed by 65 as the second byte. + + To burst read and write these 4 bytes in the correct order (where DD is written to address x), they should be stored as: + + AA BB in the MSW + CC DD in the LSW. */ + unsigned int nvrDataMSW : 16; /* 1E.0104.F:0 R/W Default = 0x0000 */ + /* NVR data MSW bits [1F:10] + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0105.F:0 R/W NVR Data LSW [F:0] + AQ_GlobalNvrInterface_APPIA.u5.bits_5.nvrDataLSW + + Default = 0x0000 + + NVR data LSW bits [F:0] + + + Notes: + Data is stored and read-out from these registers in little-endian format for operations such as FLASH device ID, and for programming the processor. + + For instance the 64K Atmel device code reads out as two bytes 0x651F into the LSW register, whereas the datasheet indicates that 1F is the first byte read, followed by 65 as the second byte. + To burst read and write these 4 bytes in the correct order (where DD is written to address x), they should be stored as: + + AA BB in the MSW + CC DD in the LSW. */ + unsigned int nvrDataLSW : 16; /* 1E.0105.F:0 R/W Default = 0x0000 */ + /* NVR data LSW bits [F:0] + */ + } bits_5; + uint16_t word_5; + } u5; +} AQ_GlobalNvrInterface_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Mailbox Interface: 1E.0200 */ +/* Global Mailbox Interface: 1E.0200 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0200.F R/WSC uP Mailbox Execute Operation + AQ_GlobalMailboxInterface_APPIA.u0.bits_0.upMailboxExecuteOperation + + Default = 0x0 + + 1 = Start of mailbox Operation + + + Notes: + Indicates mailbox is loaded and ready */ + unsigned int upMailboxExecuteOperation : 1; /* 1E.0200.F R/WSC Default = 0x0 */ + /* 1 = Start of mailbox Operation + */ + /*! \brief 1E.0200.E R/W uP Mailbox Write Mode + AQ_GlobalMailboxInterface_APPIA.u0.bits_0.upMailboxWriteMode + + Default = 0x0 + + 1 = Write + 0 = Read + + + Notes: + Mailbox direction */ + unsigned int upMailboxWriteMode : 1; /* 1E.0200.E R/W Default = 0x0 */ + /* 1 = Write + 0 = Read + */ + unsigned int reserved0 : 1; + /*! \brief 1E.0200.C R/WSC Reset uP Mailbox CRC + AQ_GlobalMailboxInterface_APPIA.u0.bits_0.resetUpMailboxCrc + + Default = 0x0 + + 1 = Reset uP mailbox CRC calculation register + + */ + unsigned int resetUpMailboxCrc : 1; /* 1E.0200.C R/WSC Default = 0x0 */ + /* 1 = Reset uP mailbox CRC calculation register + */ + unsigned int reserved1 : 3; + /*! \brief 1E.0200.8 RO uP Mailbox Busy + AQ_GlobalMailboxInterface_APPIA.u0.bits_0.upMailboxBusy + + + + 1 = uP mailbox busy + 0 = uP mailbox ready + + + Notes: + In general the uP will respond within a few processor cycles to any PIF slave request, much faster than the MDIO. If the busy is asserted over multiple MDIO polling cycles, then a H/W error may have occured and a Global S/W reset or uP reset is required. */ + unsigned int upMailboxBusy : 1; /* 1E.0200.8 RO */ + /* 1 = uP mailbox busy + 0 = uP mailbox ready + */ + unsigned int reserved2 : 8; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0201.F:0 RO uP Mailbox CRC [F:0] + AQ_GlobalMailboxInterface_APPIA.u1.bits_1.upMailboxCrc + + + + The running CRC-16 of everything passing through the mailbox interface + + */ + unsigned int upMailboxCrc : 16; /* 1E.0201.F:0 RO */ + /* The running CRC-16 of everything passing through the mailbox interface + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0202.F:0 R/W uP Mailbox Address MSW [1F:10] + AQ_GlobalMailboxInterface_APPIA.u2.bits_2.upMailboxAddressMSW + + Default = 0x0000 + + uP Mailbox MSW address + + + Notes: + The address of where to read and write from in the Microcontroller Mailbox. This is self-incrementing and automatically increments after each read and write operation.PHY */ + unsigned int upMailboxAddressMSW : 16; /* 1E.0202.F:0 R/W Default = 0x0000 */ + /* uP Mailbox MSW address + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0203.F:2 R/W uP Mailbox Address LSW [F:2] + AQ_GlobalMailboxInterface_APPIA.u3.bits_3.upMailboxAddressLSW + + Default = 0x0000 + + uP LSW Mailbox address [F:2] + + + Notes: + The address of where to read and write from in the Microcontroller Mailbox. This is self-incrementing and automatically increments after each read and write operation.PHY */ + unsigned int upMailboxAddressLSW : 14; /* 1E.0203.F:2 R/W Default = 0x0000 */ + /* uP LSW Mailbox address [F:2] + */ + /*! \brief 1E.0203.1:0 RO uP Mailbox Address LSW Don't Care [1:0] + AQ_GlobalMailboxInterface_APPIA.u3.bits_3.upMailboxAddressLSW_Don_tCare + + + + Least significant uP LSW Mailbox address bits [1:0] + + + Notes: + These bits are always set to 0 since each memory access is on a 4-byte boundary. */ + unsigned int upMailboxAddressLSW_Don_tCare : 2; /* 1E.0203.1:0 RO */ + /* Least significant uP LSW Mailbox address bits [1:0] + */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0204.F:0 R/W uP Mailbox Data MSW [1F:10] + AQ_GlobalMailboxInterface_APPIA.u4.bits_4.upMailboxDataMSW + + Default = 0x0000 + + uP Mailbox data MSW + + */ + unsigned int upMailboxDataMSW : 16; /* 1E.0204.F:0 R/W Default = 0x0000 */ + /* uP Mailbox data MSW + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0205.F:0 R/W uP Mailbox Data LSW [F:0] + AQ_GlobalMailboxInterface_APPIA.u5.bits_5.upMailboxDataLSW + + Default = 0x0000 + + uP Mailbox data LSW + + */ + unsigned int upMailboxDataLSW : 16; /* 1E.0205.F:0 R/W Default = 0x0000 */ + /* uP Mailbox data LSW + */ + } bits_5; + uint16_t word_5; + } u5; +} AQ_GlobalMailboxInterface_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Microprocessor Scratch Pad: 1E.0300 */ +/* Global Microprocessor Scratch Pad: 1E.0300 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Microprocessor Scratch Pad */ + union + { + struct + { + /*! \brief 1E.0300.F:0 R/W Scratch Pad 1[F:0] + AQ_GlobalMicroprocessorScratchPad_APPIA.u0.bits_0.scratchPad_1 + + Default = 0x0000 + + General Purpose Scratch Pad1 + */ + unsigned int scratchPad_1 : 16; /* 1E.0300.F:0 R/W Default = 0x0000 */ + /* General Purpose Scratch Pad1 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Microprocessor Scratch Pad */ + union + { + struct + { + /*! \brief 1E.0301.F:0 R/W Scratch Pad 2 [F:0] + AQ_GlobalMicroprocessorScratchPad_APPIA.u1.bits_1.scratchPad_2 + + Default = 0x0000 + + General Purpose Scratch P + */ + unsigned int scratchPad_2 : 16; /* 1E.0301.F:0 R/W Default = 0x0000 */ + /* General Purpose Scratch P */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalMicroprocessorScratchPad_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Control: 1E.C000 */ +/* Global Control: 1E.C000 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Control */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Control */ + union + { + struct + { + /*! \brief 1E.C001.F R/W uP Reset + AQ_GlobalControl_APPIA.u1.bits_1.upReset + + Default = 0x0 + + 1 = Reset + + + Notes: + Resets the uP and the PIF master and slave bus. Will be active for a minimum of 100 microseconds. */ + unsigned int upReset : 1; /* 1E.C001.F R/W Default = 0x0 */ + /* 1 = Reset + */ + unsigned int reserved0 : 8; + /*! \brief 1E.C001.6 R/W uP Run Stall Override + AQ_GlobalControl_APPIA.u1.bits_1.upRunStallOverride + + Default = 0x0 + + 0 = uP Run Stall from "MDIO Boot Load" pin. + 1 = uP Run Stall from See MCP Run Stall bit + + + Notes: + This bit selects the uP Run Stall from either the "MDIO Boot Load" pin or the See MCP Run Stall bit. */ + unsigned int upRunStallOverride : 1; /* 1E.C001.6 R/W Default = 0x0 */ + /* 0 = uP Run Stall from "MDIO Boot Load" pin. + 1 = uP Run Stall from See MCP Run Stall bit + */ + unsigned int reserved1 : 5; + /*! \brief 1E.C001.0 R/W uP Run Stall + AQ_GlobalControl_APPIA.u1.bits_1.upRunStall + + Default = 0x0 + + 1 = uP Run Stall + 0 = uP normal mode + + + Notes: + Deactivates the uP. The PIF slave bus for inbound requests will still be active. This bit is muliplexed with the "MDIO Boot Load" pin with the See uP Run Stall Override bit as the select. When the "MDIO Boot Load" pin is asserted, the uP will be in Run Stall mode after reset. */ + unsigned int upRunStall : 1; /* 1E.C001.0 R/W Default = 0x0 */ + /* 1 = uP Run Stall + 0 = uP normal mode + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalControl_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Reset Control: 1E.C006 */ +/* Global Reset Control: 1E.C006 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Reset Control */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.C006.E R/WPD Global MMD Reset Disable + AQ_GlobalResetControl_APPIA.u0.bits_0.globalMMD_ResetDisable + + Provisionable Default = 0x0 + + 1 = Disable the S/W reset to the Global MMD registers + 0 = Enable the S/W reset to the Global MMD registers + + + Notes: + Setting this bit prevents a Global S/W reset or Global S/W reset from resetting the Global MMD registers */ + unsigned int globalMMD_ResetDisable : 1; /* 1E.C006.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Disable the S/W reset to the Global MMD registers + 0 = Enable the S/W reset to the Global MMD registers + */ + unsigned int reserved1 : 14; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalResetControl_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Diagnostic Provisioning: 1E.C400 */ +/* Global Diagnostic Provisioning: 1E.C400 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Diagnostic Provisioning */ + union + { + struct + { + /*! \brief 1E.C400.F R/WPD Enable Diagnostics + AQ_GlobalDiagnosticProvisioning_APPIA.u0.bits_0.enableDiagnostics + + Provisionable Default = 0x1 + + 1 = Chip performs diagnostics on power-up + */ + unsigned int enableDiagnostics : 1; /* 1E.C400.F R/WPD Provisionable Default = 0x1 */ + /* 1 = Chip performs diagnostics on power-up */ + unsigned int reserved0 : 15; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalDiagnosticProvisioning_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Thermal Provisioning: 1E.C420 */ +/* Global Thermal Provisioning: 1E.C420 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C420.F:0 R/WPD Reserved 0 [F:0] + AQ_GlobalThermalProvisioning_APPIA.u0.bits_0.reserved_0 + + Provisionable Default = 0x0000 + + Internal reserved - do not modify + + */ + unsigned int reserved_0 : 16; /* 1E.C420.F:0 R/WPD Provisionable Default = 0x0000 */ + /* Internal reserved - do not modify + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C421.F:0 R/WPD High Temp Failure Threshold [F:0] + AQ_GlobalThermalProvisioning_APPIA.u1.bits_1.highTempFailureThreshold + + Provisionable Default = 0x4600 + + [F:0] of high temperature failure threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 70 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A000 - 1.A001: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. - High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int highTempFailureThreshold : 16; /* 1E.C421.F:0 R/WPD Provisionable Default = 0x4600 */ + /* [F:0] of high temperature failure threshold */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C422.F:0 R/WPD Low Temp Failure Threshold [F:0] + AQ_GlobalThermalProvisioning_APPIA.u2.bits_2.lowTempFailureThreshold + + Provisionable Default = 0x0000 + + [F:0] of low temperature failure threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 0 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A002 - 1.A003: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. - High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int lowTempFailureThreshold : 16; /* 1E.C422.F:0 R/WPD Provisionable Default = 0x0000 */ + /* [F:0] of low temperature failure threshold */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C423.F:0 R/WPD High Temp Warning Threshold [F:0] + AQ_GlobalThermalProvisioning_APPIA.u3.bits_3.highTempWarningThreshold + + Provisionable Default = 0x3C00 + + [F:0] of high temperature warning threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD008. Default is 60 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A004 - 1.A005: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. - High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int highTempWarningThreshold : 16; /* 1E.C423.F:0 R/WPD Provisionable Default = 0x3C00 */ + /* [F:0] of high temperature warning threshold */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C424.F:0 R/WPD Low Temp Warning Threshold [F:0] + AQ_GlobalThermalProvisioning_APPIA.u4.bits_4.lowTempWarningThreshold + + Provisionable Default = 0x0A00 + + [F:0] of low temperature warning threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 10 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A006 - 1.A007: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. - High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int lowTempWarningThreshold : 16; /* 1E.C424.F:0 R/WPD Provisionable Default = 0x0A00 */ + /* [F:0] of low temperature warning threshold */ + } bits_4; + uint16_t word_4; + } u4; +} AQ_GlobalThermalProvisioning_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global LED Provisioning: 1E.C430 */ +/* Global LED Provisioning: 1E.C430 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 7; + /*! \brief 1E.C430.8 R/WPD LED #0 Manual Set + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_0ManualSet : 1; /* 1E.C430.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + /*! \brief 1E.C430.7 R/WPD LED #0 10 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_0_10Gb_sLinkEstablished : 1; /* 1E.C430.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C430.6 R/WPD LED #0 1 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_0_1Gb_sLinkEstablished : 1; /* 1E.C430.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C430.5 R/WPD LED #0 100 Mb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s + + */ + unsigned int led_0_100Mb_sLinkEstablished : 1; /* 1E.C430.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s + */ + /*! \brief 1E.C430.4 R/WPD LED #0 Connecting + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_0Connecting : 1; /* 1E.C430.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C430.3 R/WPD LED #0 Receive Activity + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_0ReceiveActivity : 1; /* 1E.C430.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C430.2 R/WPD LED #0 Transmit Activity + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_0TransmitActivity : 1; /* 1E.C430.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C430.1:0 R/WPD LED #0 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_0ActivityStretch : 2; /* 1E.C430.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 7; + /*! \brief 1E.C431.8 R/WPD LED #1 Manual Set + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_1ManualSet : 1; /* 1E.C431.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + /*! \brief 1E.C431.7 R/WPD LED #1 10 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_1_10Gb_sLinkEstablished : 1; /* 1E.C431.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C431.6 R/WPD LED #1 1 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_1_1Gb_sLinkEstablished : 1; /* 1E.C431.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C431.5 R/WPD LED #1 100 Mb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s + + */ + unsigned int led_1_100Mb_sLinkEstablished : 1; /* 1E.C431.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s + */ + /*! \brief 1E.C431.4 R/WPD LED #1 Connecting + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_1Connecting : 1; /* 1E.C431.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C431.3 R/WPD LED #1 Receive Activity + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_1ReceiveActivity : 1; /* 1E.C431.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C431.2 R/WPD LED #1 Transmit Activity + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_1TransmitActivity : 1; /* 1E.C431.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C431.1:0 R/WPD LED #1 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_1ActivityStretch : 2; /* 1E.C431.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 7; + /*! \brief 1E.C432.8 R/WPD LED #2 Manual Set + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_2ManualSet : 1; /* 1E.C432.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + /*! \brief 1E.C432.7 R/WPD LED #2 10 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_2_10Gb_sLinkEstablished : 1; /* 1E.C432.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C432.6 R/WPD LED #2 1 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_2_1Gb_sLinkEstablished : 1; /* 1E.C432.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C432.5 R/WPD LED #2 100 Mb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s + + */ + unsigned int led_2_100Mb_sLinkEstablished : 1; /* 1E.C432.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s + */ + /*! \brief 1E.C432.4 R/WPD LED #2 Connecting + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_2Connecting : 1; /* 1E.C432.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C432.3 R/WPD LED #2 Receive Activity + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_2ReceiveActivity : 1; /* 1E.C432.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C432.2 R/WPD LED #2 Transmit Activity + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_2TransmitActivity : 1; /* 1E.C432.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C432.1:0 R/WPD LED #2 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_2ActivityStretch : 2; /* 1E.C432.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 7; + /*! \brief 1E.C433.8 R/WPD LED #3 Manual Set + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_3ManualSet : 1; /* 1E.C433.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + /*! \brief 1E.C433.7 R/WPD LED #3 10 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_3_10Gb_sLinkEstablished : 1; /* 1E.C433.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C433.6 R/WPD LED #3 1 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_3_1Gb_sLinkEstablished : 1; /* 1E.C433.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C433.5 R/WPD LED #3 100 Mb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s + + */ + unsigned int led_3_100Mb_sLinkEstablished : 1; /* 1E.C433.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s + */ + /*! \brief 1E.C433.4 R/WPD LED #3 Connecting + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_3Connecting : 1; /* 1E.C433.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C433.3 R/WPD LED #3 Receive Activity + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_3ReceiveActivity : 1; /* 1E.C433.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C433.2 R/WPD LED #3 Transmit Activity + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_3TransmitActivity : 1; /* 1E.C433.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C433.1:0 R/WPD LED #3 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_3ActivityStretch : 2; /* 1E.C433.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 7; + /*! \brief 1E.C434.8 R/WPD LED #4 Manual Set + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_4ManualSet : 1; /* 1E.C434.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + /*! \brief 1E.C434.7 R/WPD LED #4 10 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_4_10Gb_sLinkEstablished : 1; /* 1E.C434.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C434.6 R/WPD LED #4 1 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_4_1Gb_sLinkEstablished : 1; /* 1E.C434.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C434.5 R/WPD LED #4 100 Mb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s + + */ + unsigned int led_4_100Mb_sLinkEstablished : 1; /* 1E.C434.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s + */ + /*! \brief 1E.C434.4 R/WPD LED #4 Connecting + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_4Connecting : 1; /* 1E.C434.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C434.3 R/WPD LED #4 Receive Activity + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_4ReceiveActivity : 1; /* 1E.C434.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C434.2 R/WPD LED #4 Transmit Activity + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_4TransmitActivity : 1; /* 1E.C434.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C434.1:0 R/WPD LED #4 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_4ActivityStretch : 2; /* 1E.C434.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 7; + /*! \brief 1E.C435.8 R/WPD LED #5 Manual Set + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_5ManualSet : 1; /* 1E.C435.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + /*! \brief 1E.C435.7 R/WPD LED #5 10 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_5_10Gb_sLinkEstablished : 1; /* 1E.C435.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C435.6 R/WPD LED #5 1 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_5_1Gb_sLinkEstablished : 1; /* 1E.C435.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C435.5 R/WPD LED #5 100 Mb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s + + */ + unsigned int led_5_100Mb_sLinkEstablished : 1; /* 1E.C435.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s + */ + /*! \brief 1E.C435.4 R/WPD LED #5 Connecting + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_5Connecting : 1; /* 1E.C435.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C435.3 R/WPD LED #5 Receive Activity + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_5ReceiveActivity : 1; /* 1E.C435.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C435.2 R/WPD LED #5 Transmit Activity + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_5TransmitActivity : 1; /* 1E.C435.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C435.1:0 R/WPD LED #5 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_5ActivityStretch : 2; /* 1E.C435.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 15; + /*! \brief 1E.C437.0 R/WPD LED Operation Mode + AQ_GlobalLedProvisioning_APPIA.u7.bits_7.ledOperationMode + + Provisionable Default = 0x0 + + 1 = LED link activity in Mode #2 + 0 = LED link activity in classic mode + + + Notes: + When set to 1, the LED blinking rate is based on Mode #2 algorithm. When set to 0, the LED blinking rate is based on the classic algorithm. */ + unsigned int ledOperationMode : 1; /* 1E.C437.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED link activity in Mode #2 + 0 = LED link activity in classic mode + */ + } bits_7; + uint16_t word_7; + } u7; + /*! \brief Union for bit and word level access of word 8 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 13; + /*! \brief 1E.C438.2 R/WPD LED #0 Drive Three State Select + AQ_GlobalLedProvisioning_APPIA.u8.bits_8.led_0DriveThreeStateSelect + + Provisionable Default = 0x0 + + 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + + */ + unsigned int led_0DriveThreeStateSelect : 1; /* 1E.C438.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + */ + /*! \brief 1E.C438.1 R/WPD LED #0 Active High Select + AQ_GlobalLedProvisioning_APPIA.u8.bits_8.led_0ActiveHighSelect + + Provisionable Default = 0x0 + + 1 = LED active high + 0 = LED active low + + + Notes: + The See LED #0 Manual Active Select bit must be 1 for this bit to take affect. */ + unsigned int led_0ActiveHighSelect : 1; /* 1E.C438.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED active high + 0 = LED active low + */ + /*! \brief 1E.C438.0 R/WPD LED #0 Manual Active Select + AQ_GlobalLedProvisioning_APPIA.u8.bits_8.led_0ManualActiveSelect + + Provisionable Default = 0x0 + + 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + + */ + unsigned int led_0ManualActiveSelect : 1; /* 1E.C438.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + */ + } bits_8; + uint16_t word_8; + } u8; + /*! \brief Union for bit and word level access of word 9 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 13; + /*! \brief 1E.C439.2 R/WPD LED #1 Drive Three State Select + AQ_GlobalLedProvisioning_APPIA.u9.bits_9.led_1DriveThreeStateSelect + + Provisionable Default = 0x0 + + 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + + */ + unsigned int led_1DriveThreeStateSelect : 1; /* 1E.C439.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + */ + /*! \brief 1E.C439.1 R/WPD LED #1 Active High Select + AQ_GlobalLedProvisioning_APPIA.u9.bits_9.led_1ActiveHighSelect + + Provisionable Default = 0x0 + + 1 = LED active high + 0 = LED active low + + + Notes: + The See LED #1 Manual Active Select bit must be 1 for this bit to take affect. */ + unsigned int led_1ActiveHighSelect : 1; /* 1E.C439.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED active high + 0 = LED active low + */ + /*! \brief 1E.C439.0 R/WPD LED #1 Manual Active Select + AQ_GlobalLedProvisioning_APPIA.u9.bits_9.led_1ManualActiveSelect + + Provisionable Default = 0x0 + + 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + + */ + unsigned int led_1ManualActiveSelect : 1; /* 1E.C439.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + */ + } bits_9; + uint16_t word_9; + } u9; + /*! \brief Union for bit and word level access of word 10 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 13; + /*! \brief 1E.C43A.2 R/WPD LED #2 Drive Three State Select + AQ_GlobalLedProvisioning_APPIA.u10.bits_10.led_2DriveThreeStateSelect + + Provisionable Default = 0x0 + + 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + + */ + unsigned int led_2DriveThreeStateSelect : 1; /* 1E.C43A.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + */ + /*! \brief 1E.C43A.1 R/WPD LED #2 Active High Select + AQ_GlobalLedProvisioning_APPIA.u10.bits_10.led_2ActiveHighSelect + + Provisionable Default = 0x0 + + 1 = LED active high + 0 = LED active low + + + Notes: + The See LED #2 Manual Active Select bit must be 1 for this bit to take affect. */ + unsigned int led_2ActiveHighSelect : 1; /* 1E.C43A.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED active high + 0 = LED active low + */ + /*! \brief 1E.C43A.0 R/WPD LED #2 Manual Active Select + AQ_GlobalLedProvisioning_APPIA.u10.bits_10.led_2ManualActiveSelect + + Provisionable Default = 0x0 + + 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + + */ + unsigned int led_2ManualActiveSelect : 1; /* 1E.C43A.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + */ + } bits_10; + uint16_t word_10; + } u10; + /*! \brief Union for bit and word level access of word 11 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 13; + /*! \brief 1E.C43B.2 R/WPD LED #3 Drive Three State Select + AQ_GlobalLedProvisioning_APPIA.u11.bits_11.led_3DriveThreeStateSelect + + Provisionable Default = 0x0 + + 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + + */ + unsigned int led_3DriveThreeStateSelect : 1; /* 1E.C43B.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + */ + /*! \brief 1E.C43B.1 R/WPD LED #3 Active High Select + AQ_GlobalLedProvisioning_APPIA.u11.bits_11.led_3ActiveHighSelect + + Provisionable Default = 0x0 + + 1 = LED active high + 0 = LED active low + + + Notes: + The See LED #3 Manual Active Select bit must be 1 for this bit to take affect. */ + unsigned int led_3ActiveHighSelect : 1; /* 1E.C43B.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED active high + 0 = LED active low + */ + /*! \brief 1E.C43B.0 R/WPD LED #3 Manual Active Select + AQ_GlobalLedProvisioning_APPIA.u11.bits_11.led_3ManualActiveSelect + + Provisionable Default = 0x0 + + 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + + */ + unsigned int led_3ManualActiveSelect : 1; /* 1E.C43B.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + */ + } bits_11; + uint16_t word_11; + } u11; + /*! \brief Union for bit and word level access of word 12 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 13; + /*! \brief 1E.C43C.2 R/WPD LED #4 Drive Three State Select + AQ_GlobalLedProvisioning_APPIA.u12.bits_12.led_4DriveThreeStateSelect + + Provisionable Default = 0x0 + + 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + + */ + unsigned int led_4DriveThreeStateSelect : 1; /* 1E.C43C.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + */ + /*! \brief 1E.C43C.1 R/WPD LED #4 Active High Select + AQ_GlobalLedProvisioning_APPIA.u12.bits_12.led_4ActiveHighSelect + + Provisionable Default = 0x0 + + 1 = LED active high + 0 = LED active low + + + Notes: + The See LED #4 Manual Active Select bit must be 1 for this bit to take affect. */ + unsigned int led_4ActiveHighSelect : 1; /* 1E.C43C.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED active high + 0 = LED active low + */ + /*! \brief 1E.C43C.0 R/WPD LED #4 Manual Active Select + AQ_GlobalLedProvisioning_APPIA.u12.bits_12.led_4ManualActiveSelect + + Provisionable Default = 0x0 + + 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + + */ + unsigned int led_4ManualActiveSelect : 1; /* 1E.C43C.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + */ + } bits_12; + uint16_t word_12; + } u12; + /*! \brief Union for bit and word level access of word 13 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 13; + /*! \brief 1E.C43D.2 R/WPD LED #5 Drive Three State Select + AQ_GlobalLedProvisioning_APPIA.u13.bits_13.led_5DriveThreeStateSelect + + Provisionable Default = 0x0 + + 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + + */ + unsigned int led_5DriveThreeStateSelect : 1; /* 1E.C43D.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + */ + /*! \brief 1E.C43D.1 R/WPD LED #5 Active High Select + AQ_GlobalLedProvisioning_APPIA.u13.bits_13.led_5ActiveHighSelect + + Provisionable Default = 0x0 + + 1 = LED active high + 0 = LED active low + + + Notes: + The See LED #5 Manual Active Select bit must be 1 for this bit to take affect. */ + unsigned int led_5ActiveHighSelect : 1; /* 1E.C43D.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED active high + 0 = LED active low + */ + /*! \brief 1E.C43D.0 R/WPD LED #5 Manual Active Select + AQ_GlobalLedProvisioning_APPIA.u13.bits_13.led_5ManualActiveSelect + + Provisionable Default = 0x0 + + 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + + */ + unsigned int led_5ManualActiveSelect : 1; /* 1E.C43D.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + */ + } bits_13; + uint16_t word_13; + } u13; +} AQ_GlobalLedProvisioning_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global General Provisioning: 1E.C440 */ +/* Global General Provisioning: 1E.C440 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 7; + /*! \brief 1E.C440.8:4 R/WPD Gang Load MDIO Address [4:0] + AQ_GlobalGeneralProvisioning_APPIA.u0.bits_0.gangLoadMdioAddress + + Provisionable Default = 0x00 + + MDIO Address to be used during gang load operation + + + Notes: + Gang load operation is used to load data into multiple PHYs all connected to the same MDIO bus. The address for gang load operation is provided by these bits (8:4), and enabling is done by writing Bit 0. Disabling of gang load mode is done by writing the See MDIO Address Reset (1E.C441.2) bit. These will revert the PHY's MDIO address back to the address provided by the MDIO Address pins. During gang load operation, MDIO reads are disabled to prevent bus contention. */ + unsigned int gangLoadMdioAddress : 5; /* 1E.C440.8:4 R/WPD Provisionable Default = 0x00 */ + /* MDIO Address to be used during gang load operation + */ + unsigned int reserved1 : 3; + /*! \brief 1E.C440.0 RO Gang Load MDIO Write Only + AQ_GlobalGeneralProvisioning_APPIA.u0.bits_0.gangLoadMdioWriteOnly + + + + 1 = MDIO gang load enable + + + Notes: + This bit enables gang load operation with the address specified in Bits 8:4. */ + unsigned int gangLoadMdioWriteOnly : 1; /* 1E.C440.0 RO */ + /* 1 = MDIO gang load enable + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.C441.E R/WPD MDIO Broadcast Mode Enable + AQ_GlobalGeneralProvisioning_APPIA.u1.bits_1.mdioBroadcastModeEnable + + Provisionable Default = 0x0 + + 1 = Enable broadcast on Address 0 + 0 = Disable broadcast on Address 0 + + + Notes: + When set, this bit enables gang-load operation on address zero, simultaneous with normal MDIO operation. Obviously, this requires that no PHY use address 0 as its normal operating address. As well, reads on MDIO Address 0 are disabled to prevent bus contention. */ + unsigned int mdioBroadcastModeEnable : 1; /* 1E.C441.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable broadcast on Address 0 + 0 = Disable broadcast on Address 0 + */ + /*! \brief 1E.C441.D R/WPD MDIO Read MSW First Enable + AQ_GlobalGeneralProvisioning_APPIA.u1.bits_1.mdioReadMSW_FirstEnable + + Provisionable Default = 0x0 + + 1 = MSW of counter must be read first + 0 = LSW of counter must be read first + + + Notes: + This bit configures whether the MSW or LSW must be read first for counters greater than 16 bits. */ + unsigned int mdioReadMSW_FirstEnable : 1; /* 1E.C441.D R/WPD Provisionable Default = 0x0 */ + /* 1 = MSW of counter must be read first + 0 = LSW of counter must be read first + */ + unsigned int reserved1 : 8; + /*! \brief 1E.C441.4 R/WPD MDIO Drive Configuration + AQ_GlobalGeneralProvisioning_APPIA.u1.bits_1.mdioDriveConfiguration + + Provisionable Default = 0x0 + + 0 = MDIO driver is in normal mode + 1 = MDIO driver is in open drain mode + + + Notes: + When the MDIO driver is in open drain mode during a read cycle, "0" data will be actively driven out of the MDIO, "1" data will set the MDIO driver in high impedance state and an external pullup will set the MDIO line to "1". The Turn-Around "0" will also be actively driven out of the MDIO, therefore in open drain mode, the Turn-Around is still "Z0". */ + unsigned int mdioDriveConfiguration : 1; /* 1E.C441.4 R/WPD Provisionable Default = 0x0 */ + /* 0 = MDIO driver is in normal mode + 1 = MDIO driver is in open drain mode + */ + /*! \brief 1E.C441.3 R/WPD MDIO Preamble Detection Disable + AQ_GlobalGeneralProvisioning_APPIA.u1.bits_1.mdioPreambleDetectionDisable + + Provisionable Default = 0x0 + + 1 = Suppress preamble detection on MDIO + 0 = Enable preamble detection on MDIO + + */ + unsigned int mdioPreambleDetectionDisable : 1; /* 1E.C441.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = Suppress preamble detection on MDIO + 0 = Enable preamble detection on MDIO + */ + /*! \brief 1E.C441.2 R/WSC MDIO Address Reset + AQ_GlobalGeneralProvisioning_APPIA.u1.bits_1.mdioAddressReset + + Default = 0x0 + + 1 = Load MDIO Address with the address on the MDIO address pins + + + Notes: + Used to reset the address after gang load and enable MDIO reads again. */ + unsigned int mdioAddressReset : 1; /* 1E.C441.2 R/WSC Default = 0x0 */ + /* 1 = Load MDIO Address with the address on the MDIO address pins + */ + unsigned int reserved2 : 2; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 15; + /*! \brief 1E.C442.0 R/W Daisy Chain Reset + AQ_GlobalGeneralProvisioning_APPIA.u2.bits_2.daisyChainReset + + Default = 0x0 + + 1 = Reset the daisy chain + + + Notes: + Toggling this bit from 0 to 1 will reload the IRAM and DRAM and reset the uP. The uP will be in uP run stall during the reload process. After the reload process, uP run stall will be de-asserted adn the uP reset will be asserted. Note that before setting this bit, the See Soft Reset bit needs to be de-asserted. */ + unsigned int daisyChainReset : 1; /* 1E.C442.0 R/W Default = 0x0 */ + /* 1 = Reset the daisy chain + */ + } bits_2; + uint16_t word_2; + } u2; +} AQ_GlobalGeneralProvisioning_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global NVR Provisioning: 1E.C450 */ +/* Global NVR Provisioning: 1E.C450 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global NVR Provisioning */ + union + { + struct + { + unsigned int reserved0 : 5; + /*! \brief 1E.C450.A:8 R/WPD NVR Data Length [2:0] + AQ_GlobalNvrProvisioning_APPIA.u0.bits_0.nvrDataLength + + Provisionable Default = 0x4 + + NVR data length ranges from 0 bytes to 4 bytes + + + Notes: + This sets the length of the data burst used in read and write operations. + */ + unsigned int nvrDataLength : 3; /* 1E.C450.A:8 R/WPD Provisionable Default = 0x4 */ + /* NVR data length ranges from 0 bytes to 4 bytes + */ + unsigned int reserved1 : 1; + /*! \brief 1E.C450.6:4 R/WPD NVR Dummy Length [2:0] + AQ_GlobalNvrProvisioning_APPIA.u0.bits_0.nvrDummyLength + + Provisionable Default = 0x0 + + NVR dummy length ranges from 0 bytes to 4 bytes. + + + Notes: + This sets the length of the dummy field used in some maunfacturer's read status and write status operations. + */ + unsigned int nvrDummyLength : 3; /* 1E.C450.6:4 R/WPD Provisionable Default = 0x0 */ + /* NVR dummy length ranges from 0 bytes to 4 bytes. + */ + unsigned int reserved2 : 2; + /*! \brief 1E.C450.1:0 R/WPD NVR Address Length [1:0] + AQ_GlobalNvrProvisioning_APPIA.u0.bits_0.nvrAddressLength + + Provisionable Default = 0x2 + + NVR address length ranges from 0 bytes up to 3 bytes. + + + Notes: + This sets the length of the address field used in read and write operations. Use of this field is enabled via Bit 8 of See Global NVR Provisioning 2: Address 1E.C451 . + */ + unsigned int nvrAddressLength : 2; /* 1E.C450.1:0 R/WPD Provisionable Default = 0x2 */ + /* NVR address length ranges from 0 bytes up to 3 bytes. + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global NVR Provisioning */ + union + { + struct + { + unsigned int reserved0 : 7; + /*! \brief 1E.C451.8 R/WPD NVR Address Length Override + AQ_GlobalNvrProvisioning_APPIA.u1.bits_1.nvrAddressLengthOverride + + Provisionable Default = 0x0 + + 0 = NVR address length is based on the "NVR_SIZE" pin. + 1 = NVR address length is based on the See NVR Address Length [1:0] register. + + + Notes: + When the this bit = 0 and NVR_SIZE pin = 0, the NVR address length is 2 bytes. When this bit = 0 and the NVR_SIZE pin = 1, the NVR address length is 3 bytes. When this bit = 1 the NVR address length is from the See NVR Address Length [1:0] */ + unsigned int nvrAddressLengthOverride : 1; /* 1E.C451.8 R/WPD Provisionable Default = 0x0 */ + /* 0 = NVR address length is based on the "NVR_SIZE" pin. + 1 = NVR address length is based on the See NVR Address Length [1:0] register. + */ + /*! \brief 1E.C451.7:0 R/WPD NVR Clock Divide [7:0] + AQ_GlobalNvrProvisioning_APPIA.u1.bits_1.nvrClockDivide + + Provisionable Default = 0xA0 + + NVR clock divide. Clock frequency is divided by the NVR clock divide + 1 + + */ + unsigned int nvrClockDivide : 8; /* 1E.C451.7:0 R/WPD Provisionable Default = 0xA0 */ + /* NVR clock divide. Clock frequency is divided by the NVR clock divide + 1 + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global NVR Provisioning */ + union + { + struct + { + unsigned int reserved0 : 14; + /*! \brief 1E.C452.1 R/W NVR Daisy Chain Clock Divide Override + AQ_GlobalNvrProvisioning_APPIA.u2.bits_2.nvrDaisyChainClockDivideOverride + + Default = 0x0 + + 1 = Override NVR clock divide when in daisy chain master mode + + + + Notes: + When in daisy chain master mode, the clock divide configuration is received from the flash. This bit will override the clock divide configuration from the flash with the See NVR Clock Divide [7:0] . */ + unsigned int nvrDaisyChainClockDivideOverride : 1; /* 1E.C452.1 R/W Default = 0x0 */ + /* 1 = Override NVR clock divide when in daisy chain master mode + + */ + /*! \brief 1E.C452.0 R/W NVR Daisy Chain Disable + AQ_GlobalNvrProvisioning_APPIA.u2.bits_2.nvrDaisyChainDisable + + Default = 0x0 + + 1 = Disable the Daisy Chain + + + Notes: + When in daisy chain master mode, the daisy chain and MDIO can both access the SPI. Setting this bit to 1 will disable the dasiy chain from accessing the SPI and force it into a reset state. */ + unsigned int nvrDaisyChainDisable : 1; /* 1E.C452.0 R/W Default = 0x0 */ + /* 1 = Disable the Daisy Chain + */ + } bits_2; + uint16_t word_2; + } u2; +} AQ_GlobalNvrProvisioning_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Reserved Provisioning: 1E.C470 */ +/* Global Reserved Provisioning: 1E.C470 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C470.F R/WPD Diagnostics Select + AQ_GlobalReservedProvisioning_APPIA.u0.bits_0.diagnosticsSelect + + Provisionable Default = 0x0 + + 1 = Provide Extended MDI Diagnostics Information. + 0 = Provide normal cable diagnostics + + + Notes: + These bits select what sort of cable diagnostics to perform. For regular cable diagnostics, Bit F is set to zero, and the diagnostics are triggered by setting Bit 4. For extended diagnostics, Bit F is set to 1, and the desired extended diagnostics are selected by Bits E:D. The routine is then triggered by setting Bit 4. Each of the extended diagnostic routines present data for all for MDI pairs (A, B, C, D) consecutively, and after the data for each channel is gathered Bits F:D are reset. To get the data for the next pair, Bits F:D must be set back to the desired value (which must be the same as the initial channel). This continues until the data for all channels has been gathered. The address in memory where the data is stored is given in 1E.C802 and 1E.C804. + + For the case of PSD, the structure is as follows: + Int32 info + Int16 data[Len] + Info = Len << 16 | TxEnable << 8 | Pair (0 = A, etc.) + + For TDR: + Int32 info + Int16 tdr_A[Len] + Int16 tdr_B[Len] + Int16 tdr_C[Len] + Int16 tdr_D[Len] + + Info = Len << 16 | Channel + + TDR data is from the current pair to all other pairs. + + At the end of retrieving extended MDI diag data, the part will be reset. Conversly the only way to exit this routine once it starts is to issue a PMA reset. */ + unsigned int diagnosticsSelect : 1; /* 1E.C470.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Provide Extended MDI Diagnostics Information. + 0 = Provide normal cable diagnostics + */ + /*! \brief 1E.C470.E:D R/WPD Extended MDI Diagnostics Select [1:0] + AQ_GlobalReservedProvisioning_APPIA.u0.bits_0.extendedMdiDiagnosticsSelect + + Provisionable Default = 0x0 + + 0x0 = TDR Data + 0x1 = RFI Channel PSD + 0x2 = Noise PSD while the local Tx is Off + 0x3 = Noise PSD while the local Tx is On + + + Notes: + These bits select what sort of cable diagnostics to perform. For regular cable diagnostics, Bit F is set to zero, and the diagnostics are triggered by setting Bit 4. For extended diagnostics, Bit F is set to 1, and the desired extended diagnostics are selected by Bits E:D. The routine is then triggered by setting Bit 4. Each of the extended diagnostic routines present data for all for MDI pairs (A, B, C, D) consecutively, and after the data for each channel is gathered Bits F:D are reset. To get the data for the next pair, Bits F:D must be set back to the desired value (which must be the same as the initial channel). This continues until the data for all channels has been gathered. The address in memory where the data is stored is given in 1E.C802 and 1E.C804. + + For the case of PSD, the structure is as follows: + Int32 info + Int16 data[Len] + Info = Len << 16 | TxEnable << 8 | Pair (0 = A, etc.) + + For TDR: + Int32 info + Int16 tdr_A[Len] + Int16 tdr_B[Len] + Int16 tdr_C[Len] + Int16 tdr_D[Len] + + Info = Len << 16 | Channel + + TDR data is from the current pair to all other pairs. + + At the end of retrieving extended MDI diag data, the part will be reset. Conversly the only way to exit this routine once it starts is to issue a PMA reset. */ + unsigned int extendedMdiDiagnosticsSelect : 2; /* 1E.C470.E:D R/WPD Provisionable Default = 0x0 */ + /* 0x0 = TDR Data + 0x1 = RFI Channel PSD + 0x2 = Noise PSD while the local Tx is Off + 0x3 = Noise PSD while the local Tx is On + */ + unsigned int reserved0 : 5; + unsigned int reserved1 : 2; + /*! \brief 1E.C470.5 R/WSC Initiate Component Diagnostics + AQ_GlobalReservedProvisioning_APPIA.u0.bits_0.initiateComponentDiagnostics + + Default = 0x0 + + 1 = Perform component diagnostics + + + Notes: + Perform component diagnostics regardless of link state. If link is up, setting this bit will cause the link to drop while diagnostics are performed. This bit is self-clearing upon completion of the component diagnostics. Further MDIO writes should be avoided until this bit has self-cleared, indicating completion of the diagnostic routine. */ + unsigned int initiateComponentDiagnostics : 1; /* 1E.C470.5 R/WSC Default = 0x0 */ + /* 1 = Perform component diagnostics + */ + /*! \brief 1E.C470.4 R/WSC Initiate Cable Diagnostics + AQ_GlobalReservedProvisioning_APPIA.u0.bits_0.initiateCableDiagnostics + + Default = 0x0 + + 1 = Perform cable diagnostics + + + Notes: + Perform cable diagnostics regardless of link state. If link is up, setting this bit will cause the link to drop while diagnostics are performed. This bit is self-clearing upon completion of the cable diagnostics. Further MDIO writes should be avoided until this bit has self-cleared, indicating completion of the diagnostic routine. */ + unsigned int initiateCableDiagnostics : 1; /* 1E.C470.4 R/WSC Default = 0x0 */ + /* 1 = Perform cable diagnostics + */ + unsigned int reserved2 : 4; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C471.F:7 R/WPD Reserved Provisioning 2 [8:0] + AQ_GlobalReservedProvisioning_APPIA.u1.bits_1.reservedProvisioning_2 + + Provisionable Default = 0x000 + + Reserved for future use + + */ + unsigned int reservedProvisioning_2 : 9; /* 1E.C471.F:7 R/WPD Provisionable Default = 0x000 */ + /* Reserved for future use + */ + /*! \brief 1E.C471.6 R/WuP Enable Daisy-Chain Hop-Count Override + AQ_GlobalReservedProvisioning_APPIA.u1.bits_1.enableDaisy_chainHop_countOverride + + Default = 0x0 + + 1 = Hop-count is set by Bits 5:0 + 0 = Hop-count is determined by the daisy-chain + + + Notes: + Daisy-Chain Hop-Count Override should be used during MDIO boot-load operation, as the daisy-chain hop-count does not function when the daisy-chain is disabled (1E.C452.0). Setting this bit tells the processor where in the diasy-chain it is, so that the provisioning operation will function correctly. */ + unsigned int enableDaisy_chainHop_countOverride : 1; /* 1E.C471.6 R/WuP Default = 0x0 */ + /* 1 = Hop-count is set by Bits 5:0 + 0 = Hop-count is determined by the daisy-chain + */ + /*! \brief 1E.C471.5:0 R/WuP Daisy-Chain Hop-Count Override Value [5:0] + AQ_GlobalReservedProvisioning_APPIA.u1.bits_1.daisy_chainHop_countOverrideValue + + Default = 0x00 + + The value to use for the PHY's daisy-chain hop-count. Valid values are from 0 -> 47 + + + Notes: + Daisy-Chain Hop-Count Override should be used during MDIO boot-load operation, as the daisy-chain hop-count does not function when the daisy-chain is disabled (1E.C452.0). Setting this bit tells the processor where in the diasy-chain it is, so that the provisioning operation will function correctly. */ + unsigned int daisy_chainHop_countOverrideValue : 6; /* 1E.C471.5:0 R/WuP Default = 0x00 */ + /* The value to use for the PHY's daisy-chain hop-count. Valid values are from 0 -> 47 + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C472.F R/WPD Enable LVDD Power Supply Tuning + AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.enableLvddPowerSupplyTuning + + Provisionable Default = 0x0 + + 1 = Enable external LVDD power supply tuning + 0 = Disable external LVDD power supply tuning is disabled + + + Notes: + + + + These bits control whether the PHY attempts to tune the external VDD and LVDD power supplies via the PMBus. These bits are only operational if the external supplies are present (see Bits 7:6) */ + unsigned int enableLvddPowerSupplyTuning : 1; /* 1E.C472.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable external LVDD power supply tuning + 0 = Disable external LVDD power supply tuning is disabled + */ + /*! \brief 1E.C472.E R/WPD Enable VDD Power Supply Tuning + AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.enableVddPowerSupplyTuning + + Provisionable Default = 0x0 + + 1 = Enable external VDD power supply tuning + 0 = Disable external VDD power supply tuning is disabled + + + Notes: + + + + These bits control whether the PHY attempts to tune the external VDD and LVDD power supplies via the PMBus. These bits are only operational if the external supplies are present (see Bits 7:6) */ + unsigned int enableVddPowerSupplyTuning : 1; /* 1E.C472.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable external VDD power supply tuning + 0 = Disable external VDD power supply tuning is disabled + */ + unsigned int reserved0 : 6; + /*! \brief 1E.C472.7 R/WPD Tunable External LVDD Power Supply Present + AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.tunableExternalLvddPowerSupplyPresent + + Provisionable Default = 0x0 + + 1 = Tunable external LVDD power supply present + 0 = No tunable external LVDD power supply present + + + Notes: + + + + These bits must be set if tuning of external power supplies is desired (see Bits 7:6) */ + unsigned int tunableExternalLvddPowerSupplyPresent : 1; /* 1E.C472.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = Tunable external LVDD power supply present + 0 = No tunable external LVDD power supply present + */ + /*! \brief 1E.C472.6 R/WPD Tunable External VDD Power Supply Present + AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.tunableExternalVddPowerSupplyPresent + + Provisionable Default = 0x0 + + 1 = Tunable external VDD power supply present + 0 = No tunable external VDD power supply present + + + Notes: + + + + These bits must be set if tuning of external power supplies is desired (see Bits 7:6) */ + unsigned int tunableExternalVddPowerSupplyPresent : 1; /* 1E.C472.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Tunable external VDD power supply present + 0 = No tunable external VDD power supply present + */ + unsigned int reserved1 : 4; + /*! \brief 1E.C472.1 R/WPDuP Enable XENPAK Register Space + AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.enableXenpakRegisterSpace + + Provisionable Default = 0x0 + + 1 = XENPAK register space enabled + 0 = XENPAK register space disabled + + */ + unsigned int enableXenpakRegisterSpace : 1; /* 1E.C472.1 R/WPDuP Provisionable Default = 0x0 */ + /* 1 = XENPAK register space enabled + 0 = XENPAK register space disabled + */ + /*! \brief 1E.C472.0 R/WPDuP Enable 5th Channel RFI Cancellation + AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.enable_5thChannelRfiCancellation + + Provisionable Default = 0x0 + + 1 = 5th channel and RFI cancellers operation enabled + 0 = 5th channel AFE is powered down, 5th channel digital is clock gated, RFI cancellers are disabled + + + Notes: + Note: The value of this bit at the time of Autonegotiation sets the local PHY behavior until the next time Autonegotiation occurs. */ + unsigned int enable_5thChannelRfiCancellation : 1; /* 1E.C472.0 R/WPDuP Provisionable Default = 0x0 */ + /* 1 = 5th channel and RFI cancellers operation enabled + 0 = 5th channel AFE is powered down, 5th channel digital is clock gated, RFI cancellers are disabled + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.C474.7:0 R/WPD Training SNR [7:0] + AQ_GlobalReservedProvisioning_APPIA.u4.bits_4.trainingSNR + + Provisionable Default = 0x00 + + SNR during 10G training on the worst channel. SNR is in steps of 0.1dB + + + Notes: + The SNR margin that is enjoyed by the worst channel, over and above the minimum SNR required to operate at a BER of 10-12. It is reported with 0.1 dB of resolution to an accuracy of 0.5 dB within the range of -12.7 dB to 12.7 dB. The number is in offset binary, with 0.0 dB represented by 0x8000. + */ + unsigned int trainingSNR : 8; /* 1E.C474.7:0 R/WPD Provisionable Default = 0x00 */ + /* SNR during 10G training on the worst channel. SNR is in steps of 0.1dB + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved0 : 2; + /*! \brief 1E.C475.D R/WPD Smart Power-Down Status + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.smartPower_downStatus + + Provisionable Default = 0x0 + + 1 = Smart Power-Down Active + 0 = Smart Power-Down Inactive + + */ + unsigned int smartPower_downStatus : 1; /* 1E.C475.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Smart Power-Down Active + 0 = Smart Power-Down Inactive + */ + /*! \brief 1E.C475.C R/WPD Reserved Provisioning 6 + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.reservedProvisioning_6 + + Provisionable Default = 0x0 + + Reserved for future use + + */ + unsigned int reservedProvisioning_6 : 1; /* 1E.C475.C R/WPD Provisionable Default = 0x0 */ + /* Reserved for future use + */ + /*! \brief 1E.C475.B R/WPD CFR LP Disable Timer + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrLpDisableTimer + + Provisionable Default = 0x0 + + 1 = Link partner requires cfr_disable timer + 0 = Link partner does not require cfr_disable timer + + */ + unsigned int cfrLpDisableTimer : 1; /* 1E.C475.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner requires cfr_disable timer + 0 = Link partner does not require cfr_disable timer + */ + /*! \brief 1E.C475.A R/WPD CFR LP Extended Maxwait + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrLpExtendedMaxwait + + Provisionable Default = 0x0 + + 1 = Link partner requires extended maxwait + 0 = Link partner does not require extended maxwait + + */ + unsigned int cfrLpExtendedMaxwait : 1; /* 1E.C475.A R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner requires extended maxwait + 0 = Link partner does not require extended maxwait + */ + /*! \brief 1E.C475.9 R/WPD CFR LP THP + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrLpTHP + + Provisionable Default = 0x0 + + 1 = Link partner requires local PHY to enable THP + 0 = Link partner does not require local PHY to enable THP + + */ + unsigned int cfrLpTHP : 1; /* 1E.C475.9 R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner requires local PHY to enable THP + 0 = Link partner does not require local PHY to enable THP + */ + /*! \brief 1E.C475.8 R/WPD CFR LP Support + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrLpSupport + + Provisionable Default = 0x0 + + 1 = Link partner supports Cisco Fast Retrain + 0 = Link partner does support Cisco Fast Retrain + + */ + unsigned int cfrLpSupport : 1; /* 1E.C475.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner supports Cisco Fast Retrain + 0 = Link partner does support Cisco Fast Retrain + */ + /*! \brief 1E.C475.7 R/WPD CFR Disable Timer + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrDisableTimer + + Provisionable Default = 0x0 + + 1 = Local PHY requires cfr_disable timer + 0 = Local PHY does not require cfr_disable timer + + */ + unsigned int cfrDisableTimer : 1; /* 1E.C475.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY requires cfr_disable timer + 0 = Local PHY does not require cfr_disable timer + */ + /*! \brief 1E.C475.6 R/WPD CFR Extended Maxwait + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrExtendedMaxwait + + Provisionable Default = 0x0 + + 1 = Local PHY requires extended maxwait + 0 = Local PHY does not require extended maxwait + + */ + unsigned int cfrExtendedMaxwait : 1; /* 1E.C475.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY requires extended maxwait + 0 = Local PHY does not require extended maxwait + */ + /*! \brief 1E.C475.5 R/WPD CFR THP + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrTHP + + Provisionable Default = 0x0 + + 1 = Local PHY requires local PHY to enable THP + 0 = Local PHY does not require local PHY to enable THP + + */ + unsigned int cfrTHP : 1; /* 1E.C475.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY requires local PHY to enable THP + 0 = Local PHY does not require local PHY to enable THP + */ + /*! \brief 1E.C475.4 R/WPD CFR Support + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrSupport + + Provisionable Default = 0x0 + + 1 = Local PHY supports Cisco Fast Retrain + 0 = Local PHY does support Cisco Fast Retrain + + */ + unsigned int cfrSupport : 1; /* 1E.C475.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY supports Cisco Fast Retrain + 0 = Local PHY does support Cisco Fast Retrain + */ + /*! \brief 1E.C475.3 R/WPD Deadlock Avoidance Enable + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.deadlockAvoidanceEnable + + Provisionable Default = 0x0 + + 1 = SPD with deadlock avoidance: PHY transmits autonegotiation pulses (FLPs) at a slower rate (~ 1 FLP/ 100ms) than specified by autonegotiation standard (~1 FLP / 8.25ms). Receiver is active and able to detect the pulses. + 0 = SPD without deadlock avoidance: PHY transmitter is shut down, no autonegotiation pulses are sent on the line but the receiver is active and able to detect the pulses + + */ + unsigned int deadlockAvoidanceEnable : 1; /* 1E.C475.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = SPD with deadlock avoidance: PHY transmits autonegotiation pulses (FLPs) at a slower rate (~ 1 FLP/ 100ms) than specified by autonegotiation standard (~1 FLP / 8.25ms). Receiver is active and able to detect the pulses. + 0 = SPD without deadlock avoidance: PHY transmitter is shut down, no autonegotiation pulses are sent on the line but the receiver is active and able to detect the pulses + */ + /*! \brief 1E.C475.2 R/WPD Smart Power-Down Enable + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.smartPower_downEnable + + Provisionable Default = 0x0 + + 1 = Enable smart power down mode + 0 = Smart power-down mode disabled + + + Notes: + Smart power down (SPD) is the lowest power mode at which PHY is able to autonegotiate. SPD can be enabled with bit 1E.C475.2 */ + unsigned int smartPower_downEnable : 1; /* 1E.C475.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable smart power down mode + 0 = Smart power-down mode disabled + */ + unsigned int reserved1 : 2; + } bits_5; + uint16_t word_5; + } u5; +} AQ_GlobalReservedProvisioning_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Cable Diagnostic Status: 1E.C800 */ +/* Global Cable Diagnostic Status: 1E.C800 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Cable Diagnostic Status */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.C800.E:C RO Pair A Status [2:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u0.bits_0.pairAStatus + + + + (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair D + 010= Connected to Pair C + 001= Connected to Pair B + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK + + Notes: + This bitfield reports the result, for pair A, of running either cable diagnostics or component diagnostics. */ + unsigned int pairAStatus : 3; /* 1E.C800.E:C RO */ + /* (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair D + 010= Connected to Pair C + 001= Connected to Pair B + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK */ + unsigned int reserved1 : 1; + /*! \brief 1E.C800.A:8 RO Pair B Status [2:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u0.bits_0.pairBStatus + + + + (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair A + 010= Connected to Pair D + 001= Connected to Pair C + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK + + Notes: + This bitfield reports the result, for pair B, of running either cable diagnostics or component diagnostics. */ + unsigned int pairBStatus : 3; /* 1E.C800.A:8 RO */ + /* (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair A + 010= Connected to Pair D + 001= Connected to Pair C + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK */ + unsigned int reserved2 : 1; + /*! \brief 1E.C800.6:4 RO Pair C Status [2:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u0.bits_0.pairCStatus + + + + (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair B + 010= Connected to Pair A + 001= Connected to Pair D + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK + + Notes: + This bitfield reports the result, for pair C, of running either cable diagnostics or component diagnostics. */ + unsigned int pairCStatus : 3; /* 1E.C800.6:4 RO */ + /* (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair B + 010= Connected to Pair A + 001= Connected to Pair D + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK */ + unsigned int reserved3 : 1; + /*! \brief 1E.C800.2:0 RO Pair D Status [2:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u0.bits_0.pairDStatus + + + + (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair C + 010= Connected to Pair B + 001= Connected to Pair A + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK + + Notes: + This bitfield reports the result, for pair D, of running either cable diagnostics or component diagnostics. */ + unsigned int pairDStatus : 3; /* 1E.C800.2:0 RO */ + /* (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair C + 010= Connected to Pair B + 001= Connected to Pair A + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C801.F:8 RO Pair A Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u1.bits_1.pairAReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair A + + Notes: + The distance to this reflection is given in See Global Reserved Status 1: Address 1E.C870 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairAReflection_1 : 8; /* 1E.C801.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair A */ + /*! \brief 1E.C801.7:0 RO Pair A Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u1.bits_1.pairAReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair A + + Notes: + The distance to this reflection is given in See Global Reserved Status 1: Address 1E.C870 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairAReflection_2 : 8; /* 1E.C801.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair A */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C802.F:0 RO Impulse Response MSW [F:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u2.bits_2.impulseResponseMSW + + + + The MSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type in 1E.C470.E:D + + + Notes: + See 1E.C470 for more information */ + unsigned int impulseResponseMSW : 16; /* 1E.C802.F:0 RO */ + /* The MSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type in 1E.C470.E:D + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C803.F:8 RO Pair B Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u3.bits_3.pairBReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair B + + Notes: + The distance to this reflection is given in See Global Reserved Status 2: Address 1E.C871 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairBReflection_1 : 8; /* 1E.C803.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair B */ + /*! \brief 1E.C803.7:0 RO Pair B Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u3.bits_3.pairBReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair B + + Notes: + The distance to this reflection is given in See Global Reserved Status 2: Address 1E.C871 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairBReflection_2 : 8; /* 1E.C803.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair B */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C804.F:0 RO Impulse Response LSW [F:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u4.bits_4.impulseResponseLSW + + + + The LSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type specified in 1E.C470.E:D + + + Notes: + See 1E.C470 for more information */ + unsigned int impulseResponseLSW : 16; /* 1E.C804.F:0 RO */ + /* The LSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type specified in 1E.C470.E:D + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C805.F:8 RO Pair C Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u5.bits_5.pairCReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair C + + Notes: + The distance to this reflection is given in See Global Reserved Status 3: Address 1E.C872 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairCReflection_1 : 8; /* 1E.C805.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair C */ + /*! \brief 1E.C805.7:0 RO Pair C Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u5.bits_5.pairCReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair C + + Notes: + The distance to this reflection is given in See Global Reserved Status 3: Address 1E.C872 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairCReflection_2 : 8; /* 1E.C805.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair C */ + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C806.F:0 RO Reserved 1 [F:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u6.bits_6.reserved_1 + + + + Reserved for future use + + */ + unsigned int reserved_1 : 16; /* 1E.C806.F:0 RO */ + /* Reserved for future use + */ + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C807.F:8 RO Pair D Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u7.bits_7.pairDReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair D + + Notes: + The distance to this reflection is given in See Global Reserved Status 4: Address 1E.C873 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairDReflection_1 : 8; /* 1E.C807.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair D */ + /*! \brief 1E.C807.7:0 RO Pair D Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u7.bits_7.pairDReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair D + + Notes: + The distance to this reflection is given in See Global Reserved Status 4: Address 1E.C873 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairDReflection_2 : 8; /* 1E.C807.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair D */ + } bits_7; + uint16_t word_7; + } u7; + /*! \brief Union for bit and word level access of word 8 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C808.F:0 RO Reserved 2[F:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u8.bits_8.reserved_2 + + + + Reserved for future use + + */ + unsigned int reserved_2 : 16; /* 1E.C808.F:0 RO */ + /* Reserved for future use + */ + } bits_8; + uint16_t word_8; + } u8; +} AQ_GlobalCableDiagnosticStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Thermal Status: 1E.C820 */ +/* Global Thermal Status: 1E.C820 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Thermal Status */ + union + { + struct + { + /*! \brief 1E.C820.F:0 RO Temperature [F:0] + AQ_GlobalThermalStatus_APPIA.u0.bits_0.temperature + + + + [F:0] of temperature + + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 70 degreesC. This is a mirror of the XENPAK register 1.A060 - 1.A061. The mirror is performed in H/W. */ + unsigned int temperature : 16; /* 1E.C820.F:0 RO */ + /* [F:0] of temperature + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Thermal Status */ + union + { + struct + { + unsigned int reserved0 : 15; + /*! \brief 1E.C821.0 RO Temperature Ready + AQ_GlobalThermalStatus_APPIA.u1.bits_1.temperatureReady + + + + 1 = Temperature measurement is valid + + + Notes: + This is a mirror of the XENPAK register 1.A06E. */ + unsigned int temperatureReady : 1; /* 1E.C821.0 RO */ + /* 1 = Temperature measurement is valid + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalThermalStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global General Status: 1E.C830 */ +/* Global General Status: 1E.C830 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global General Status */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.C830.E RO High Temperature Failure State + AQ_GlobalGeneralStatus_APPIA.u0.bits_0.highTemperatureFailureState + + + + 1 = High temperature failure threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A070.7 register. + + */ + unsigned int highTemperatureFailureState : 1; /* 1E.C830.E RO */ + /* 1 = High temperature failure threshold has been exceeded */ + /*! \brief 1E.C830.D RO Low Temperature Failure State + AQ_GlobalGeneralStatus_APPIA.u0.bits_0.lowTemperatureFailureState + + + + 1 = Low temperature failure threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A070.6 register. + + */ + unsigned int lowTemperatureFailureState : 1; /* 1E.C830.D RO */ + /* 1 = Low temperature failure threshold has been exceeded */ + /*! \brief 1E.C830.C RO High Temperature Warning State + AQ_GlobalGeneralStatus_APPIA.u0.bits_0.highTemperatureWarningState + + + + 1 = High temperature warning threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A074.7 register. + + */ + unsigned int highTemperatureWarningState : 1; /* 1E.C830.C RO */ + /* 1 = High temperature warning threshold has been exceeded */ + /*! \brief 1E.C830.B RO Low Temperature Warning State + AQ_GlobalGeneralStatus_APPIA.u0.bits_0.lowTemperatureWarningState + + + + 1 = Low temperature warning threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A074.6 register. + + */ + unsigned int lowTemperatureWarningState : 1; /* 1E.C830.B RO */ + /* 1 = Low temperature warning threshold has been exceeded */ + unsigned int reserved1 : 11; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global General Status */ + union + { + struct + { + /*! \brief 1E.C831.F RO Processor Intensive MDIO Operation In- Progress + AQ_GlobalGeneralStatus_APPIA.u1.bits_1.processorIntensiveMdioOperationIn_Progress + + + + 1 = PHY microprocessor is busy with a processor-intensive MDIO operation + 0 = Processor-intensive MDIO operation completed + + + Notes: + This bit should may be used with certain processor-intensive MDIO commands (such as Loopbacks, Test Modes, Low power modes, Tx-Disable, Restart autoneg, Cable Diagnostics, etc.) that take longer than an MDIO cycle to complete. Upon receiving an MDIO command that involves the PHY's microprocessor, this bit is set, and when the command is completed, this bit is cleared. + + NOTE!!! This bit should be checked only after 1 ms of issuing a processor-intensive MDIO operation. + + The list of operations that set this bit are as follows: + + 1.0.0, PMA Loopback + 1.0.B, Low power mode + 1.9.4:0, Tx Disable + 1.84, 10G Test modes + 1.8000.5, XENPAK Control + 1.9000, XENPAK Rx Fault Enable + 1.9002, XENPAK Alarm Enable + 1.E400.F, External loopback + 3.0.B, Low power mode + 3.0.E, System PCS loopback + 3.C471.5, PRBS Test + 3.C471.6, PRBS Test + 3.E471.5, PRBS Test + 3.E471.6, PRBS Test + 4.0.B, Low power mode + 4.0.E, PHY-XS network loopback + 4.C440, Output clock control, Load SERDES parameters + 4.F802.E, System loopback + 4.C444.F:B, Loopback Control + 4.C444.4:2, Packet generation + 4.C445.C, SERDES calibration + 7.0.9, Restart autonegotiation + 1D.C280, 1G/100M Network loopback + 1D.C500, 1G System loopback + 1D.C501, 1G / 100M Test modes */ + unsigned int processorIntensiveMdioOperationIn_Progress : 1; /* 1E.C831.F RO */ + /* 1 = PHY microprocessor is busy with a processor-intensive MDIO operation + 0 = Processor-intensive MDIO operation completed + */ + unsigned int reserved0 : 15; + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalGeneralStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Pin Status: 1E.C840 */ +/* Global Pin Status: 1E.C840 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Pin Status */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.C840.E:D RO MDIO Boot Load [1:0] + AQ_GlobalPinStatus_APPIA.u0.bits_0.mdioBootLoad + + + + Value of MDIO Boot Load pins + + 0x3 = PHY #0 Slave Daisy Chain Boot + 0x2 = PHY #0 Master Daisy Chain Boot from Flash + 0x1 = MDIO Boot Load + 0x0 = Boot from Flash (PHY #0 only) + + + Notes: + NOTES: + + PHY #0 is the primary PHY, and PHY #1 is the secondary PHY + + PHY #1 is always in Slave Daisy Chain Boot from Flash when set to 0x2 or 0x3. */ + unsigned int mdioBootLoad : 2; /* 1E.C840.E:D RO */ + /* Value of MDIO Boot Load pins + + 0x3 = PHY #0 Slave Daisy Chain Boot + 0x2 = PHY #0 Master Daisy Chain Boot from Flash + 0x1 = MDIO Boot Load + 0x0 = Boot from Flash (PHY #0 only) + */ + unsigned int reserved1 : 3; + /*! \brief 1E.C840.9 RO Package Connectivity + AQ_GlobalPinStatus_APPIA.u0.bits_0.packageConnectivity + + + + Value of the package connection pin + + */ + unsigned int packageConnectivity : 1; /* 1E.C840.9 RO */ + /* Value of the package connection pin + */ + unsigned int reserved2 : 1; + /*! \brief 1E.C840.7 RO Tx Enable + AQ_GlobalPinStatus_APPIA.u0.bits_0.txEnable + + + + Current Value of Tx Enable pin + + + Notes: + 0 = Disable Transmitter */ + unsigned int txEnable : 1; /* 1E.C840.7 RO */ + /* Current Value of Tx Enable pin + */ + unsigned int reserved3 : 1; + /*! \brief 1E.C840.5:0 RO LED Pullup State [5:0] + AQ_GlobalPinStatus_APPIA.u0.bits_0.ledPullupState + + + + 1 = LED output pin is pulled high + 0 = LED output pin is pulled low + + */ + unsigned int ledPullupState : 6; /* 1E.C840.5:0 RO */ + /* 1 = LED output pin is pulled high + 0 = LED output pin is pulled low + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalPinStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Daisy Chain Status: 1E.C842 */ +/* Global Daisy Chain Status: 1E.C842 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Daisy Chain Status */ + union + { + struct + { + /*! \brief 1E.C842.F:0 RO Rx Daisy Chain Calculated CRC [F:0] + AQ_GlobalDaisyChainStatus_APPIA.u0.bits_0.rxDaisyChainCalculatedCrc + + + + Rx Daisy Chain Calculated CRC + + + Notes: + This is the calculated daisy chain CRC. */ + unsigned int rxDaisyChainCalculatedCrc : 16; /* 1E.C842.F:0 RO */ + /* Rx Daisy Chain Calculated CRC + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalDaisyChainStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Fault Message: 1E.C850 */ +/* Global Fault Message: 1E.C850 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Fault Message */ + union + { + struct + { + /*! \brief 1E.C850.F:0 RO Message [F:0] + AQ_GlobalFaultMessage_APPIA.u0.bits_0.message + + + + Error code describing fault + + Notes: + Code 0x8001: Firmware not compatible with chip architecture. This fault occurs when firmware compiled for a different Tensilica core is loaded. + Code 0x8002: VCO calibration failed. This occurs when the main PLLs on chip fail to lock: this is not possible to trigger. + Code 0x8003: XAUI calibration failed. This occurs when the XAUI PLLs fail to lock: this is not possible to trigger. + Code 0x8004: Failed to set operating voltages via PMBus. This only occurs when the processor has control over power supply voltage via an attached PMBus device and there is a protocol error on the I2C bus: this is not possible to trigger. + Code 0x8005: Unexpected device ID. This occurs if the device ID programmed into the internal E-Fuse registers in not valid: this is not possible to trigger. + Code 0x8006: Computed checksum does not match expected checksum. This occurs when the FLASH checksum check performed at boot time fails. This only occurs when the system boots from FLASH. + Code 0x8007: Detected a bit error in static memory. To trigger, corrupt one of the static regions. + Code 0xC001: Illegal Instruction exception. This occurs when the processor attempts to execute an illegal instruction. To trigger this, write an illegal instruction to program memory. It's possible that the bit error check will trigger before the illegal instruction is executed. + Code 0xC002 Instruction Fetch Error. Internal physical address or a data error during instruction fetch: this is not possible to trigger. + Code 0xC003 Load Store Error. Internal physical address or data error during load store operation: this is not possible to trigger.. + Code 0xC004 Privileged Instruction. Attempt to execute a privileged operation without sufficient privilege: this is not possible to trigger. + Code 0xC005 Unaligned Load or Store. Attempt to load or store data at an address which cannot be handled due to alignment: this is not possible to trigger. + Code 0xC006 Instruction fetch from prohibited space: this is not possible to trigger. + Code 0xC007 Data load from prohibited space: this is not possible to trigger. + Code 0xC008 Data store into prohibited space: this is not possible to trigger. */ + unsigned int message : 16; /* 1E.C850.F:0 RO */ + /* Error code describing fault */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalFaultMessage_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Primary Status: 1E.C851 */ +/* Global Primary Status: 1E.C851 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Primary Status */ + union + { + struct + { + unsigned int reserved0 : 15; + /*! \brief 1E.C851.0 RO Primary Status + AQ_GlobalPrimaryStatus_APPIA.u0.bits_0.primaryStatus + + + + 1 = PHY is the primary PHY + 0 = PHY is is secondary PHY + + */ + unsigned int primaryStatus : 1; /* 1E.C851.0 RO */ + /* 1 = PHY is the primary PHY + 0 = PHY is is secondary PHY + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalPrimaryStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Cable Diagnostic Impedance: 1E.C880 */ +/* Global Cable Diagnostic Impedance: 1E.C880 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C880.F RO Reserved 1 + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.reserved_1 + + + + Reserved for future use + + */ + unsigned int reserved_1 : 1; /* 1E.C880.F RO */ + /* Reserved for future use + */ + /*! \brief 1E.C880.E:C RO Pair A Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.pairAReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_1 : 3; /* 1E.C880.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C880.B RO Reserved 2 + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.reserved_2 + + + + Reserved for future use + + */ + unsigned int reserved_2 : 1; /* 1E.C880.B RO */ + /* Reserved for future use + */ + /*! \brief 1E.C880.A:8 RO Pair A Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.pairAReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_2 : 3; /* 1E.C880.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C880.7 RO Reserved 3 + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.reserved_3 + + + + Reserved for future use + + */ + unsigned int reserved_3 : 1; /* 1E.C880.7 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C880.6:4 RO Pair A Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.pairAReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_3 : 3; /* 1E.C880.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C880.3 RO Reserved 4 + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.reserved_4 + + + + Reserved for future use + + */ + unsigned int reserved_4 : 1; /* 1E.C880.3 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C880.2:0 RO Pair A Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.pairAReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_4 : 3; /* 1E.C880.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C881.F RO Reserved 5 + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.reserved_5 + + + + Reserved for future use + + */ + unsigned int reserved_5 : 1; /* 1E.C881.F RO */ + /* Reserved for future use + */ + /*! \brief 1E.C881.E:C RO Pair B Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.pairBReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_1 : 3; /* 1E.C881.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C881.B RO Reserved 6 + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.reserved_6 + + + + Reserved for future use + + */ + unsigned int reserved_6 : 1; /* 1E.C881.B RO */ + /* Reserved for future use + */ + /*! \brief 1E.C881.A:8 RO Pair B Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.pairBReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_2 : 3; /* 1E.C881.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C881.7 RO Reserved 7 + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.reserved_7 + + + + Reserved for future use + + */ + unsigned int reserved_7 : 1; /* 1E.C881.7 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C881.6:4 RO Pair B Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.pairBReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_3 : 3; /* 1E.C881.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C881.3 RO Reserved 8 + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.reserved_8 + + + + Reserved for future use + + */ + unsigned int reserved_8 : 1; /* 1E.C881.3 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C881.2:0 RO Pair B Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.pairBReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_4 : 3; /* 1E.C881.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C882.F RO Reserved 9 + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.reserved_9 + + + + Reserved for future use + + */ + unsigned int reserved_9 : 1; /* 1E.C882.F RO */ + /* Reserved for future use + */ + /*! \brief 1E.C882.E:C RO Pair C Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.pairCReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_1 : 3; /* 1E.C882.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C882.B RO Reserved 10 + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.reserved_10 + + + + Reserved for future use + + */ + unsigned int reserved_10 : 1; /* 1E.C882.B RO */ + /* Reserved for future use + */ + /*! \brief 1E.C882.A:8 RO Pair C Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.pairCReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_2 : 3; /* 1E.C882.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C882.7 RO Reserved 11 + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.reserved_11 + + + + Reserved for future use + + */ + unsigned int reserved_11 : 1; /* 1E.C882.7 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C882.6:4 RO Pair C Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.pairCReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_3 : 3; /* 1E.C882.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C882.3 RO Reserved 12 + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.reserved_12 + + + + Reserved for future use + + */ + unsigned int reserved_12 : 1; /* 1E.C882.3 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C882.2:0 RO Pair C Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.pairCReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_4 : 3; /* 1E.C882.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C883.F RO Reserved 13 + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.reserved_13 + + + + Reserved for future use + + */ + unsigned int reserved_13 : 1; /* 1E.C883.F RO */ + /* Reserved for future use + */ + /*! \brief 1E.C883.E:C RO Pair D Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.pairDReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_1 : 3; /* 1E.C883.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C883.B RO Reserved 14 + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.reserved_14 + + + + Reserved for future use + + */ + unsigned int reserved_14 : 1; /* 1E.C883.B RO */ + /* Reserved for future use + */ + /*! \brief 1E.C883.A:8 RO Pair D Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.pairDReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_2 : 3; /* 1E.C883.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C883.7 RO Reserved 15 + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.reserved_15 + + + + Reserved for future use + + */ + unsigned int reserved_15 : 1; /* 1E.C883.7 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C883.6:4 RO Pair D Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.pairDReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_3 : 3; /* 1E.C883.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C883.3 RO Reserved 16 + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.reserved_16 + + + + Reserved for future use + + */ + unsigned int reserved_16 : 1; /* 1E.C883.3 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C883.2:0 RO Pair D Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.pairDReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_4 : 3; /* 1E.C883.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + } bits_3; + uint16_t word_3; + } u3; +} AQ_GlobalCableDiagnosticImpedance_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Status: 1E.C884 */ +/* Global Status: 1E.C884 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Status */ + union + { + struct + { + /*! \brief 1E.C884.F:8 RO Reserved Status 0 [7:0] + AQ_GlobalStatus_APPIA.u0.bits_0.reservedStatus_0 + + + + Reserved for future use + + */ + unsigned int reservedStatus_0 : 8; /* 1E.C884.F:8 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C884.7:0 RO Cable Length [7:0] + AQ_GlobalStatus_APPIA.u0.bits_0.cableLength + + + + The estimated length of the cable in meters + + + Notes: + The length of the cable shown here is estimated from the cable diagnostic engine and should be accurate to +/-1m. */ + unsigned int cableLength : 8; /* 1E.C884.7:0 RO */ + /* The estimated length of the cable in meters + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Reserved Status: 1E.C885 */ +/* Global Reserved Status: 1E.C885 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Reserved Status */ + union + { + struct + { + /*! \brief 1E.C885.F:A RO Nearly Seconds MSW[5:0] + AQ_GlobalReservedStatus_APPIA.u0.bits_0.nearlySecondsMSW + + + + Bits 16 to 21 of the 22 bit "Nearly Seconds" uptime counter. + + + Notes: + The "Nearly Seconds" counter is incremented every 1024 milliseconds. */ + unsigned int nearlySecondsMSW : 6; /* 1E.C885.F:A RO */ + /* Bits 16 to 21 of the 22 bit "Nearly Seconds" uptime counter. + */ + /*! \brief 1E.C885.9:8 ROSPD XENPAK NVR Status [1:0] + AQ_GlobalReservedStatus_APPIA.u0.bits_0.xenpakNvrStatus + + Provisionable Default = 0x0 + + Status of XENPAK NVR: + 0: NVR not enabled + 1: Last NVR operation succeeded + 2: Last NVR operation failed + 3: Reserved + + + Notes: + XENPAK register space is mirrored in NVR (SPI ROM). This register indicates the status of the last NVR operation. */ + unsigned int xenpakNvrStatus : 2; /* 1E.C885.9:8 ROSPD Provisionable Default = 0x0 */ + /* Status of XENPAK NVR: + 0: NVR not enabled + 1: Last NVR operation succeeded + 2: Last NVR operation failed + 3: Reserved + */ + /*! \brief 1E.C885.7:0 ROSPD ROM Revision [7:0] + AQ_GlobalReservedStatus_APPIA.u0.bits_0.romRevision + + Provisionable Default = 0x00 + + ROM Revision Number + + + Notes: + Customers may receive multiple ROM images that differ only in their provisioning. This field is used to differentiate those images. This field is used in conjunction with the firmware major and minor revision numbers to uniquely identify ROM images. */ + unsigned int romRevision : 8; /* 1E.C885.7:0 ROSPD Provisionable Default = 0x00 */ + /* ROM Revision Number + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Reserved Status */ + union + { + struct + { + /*! \brief 1E.C886.F:0 RO Nearly Seconds LSW[F:0] + AQ_GlobalReservedStatus_APPIA.u1.bits_1.nearlySecondsLSW + + + + Bits 0 to 15 of the 22 bit "Nearly Seconds" uptime counter. + + + Notes: + The "Nearly Seconds" counter is incremented every 1024 milliseconds. */ + unsigned int nearlySecondsLSW : 16; /* 1E.C886.F:0 RO */ + /* Bits 0 to 15 of the 22 bit "Nearly Seconds" uptime counter. + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalReservedStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Alarms: 1E.CC00 */ +/* Global Alarms: 1E.CC00 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Alarms */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.CC00.E LH High Temperature Failure + AQ_GlobalAlarms_APPIA.u0.bits_0.highTemperatureFailure + + + + 1 = High temperature failure threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int highTemperatureFailure : 1; /* 1E.CC00.E LH */ + /* 1 = High temperature failure threshold has been exceeded + */ + /*! \brief 1E.CC00.D LH Low Temperature Failure + AQ_GlobalAlarms_APPIA.u0.bits_0.lowTemperatureFailure + + + + 1 = Low temperature failure threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int lowTemperatureFailure : 1; /* 1E.CC00.D LH */ + /* 1 = Low temperature failure threshold has been exceeded + */ + /*! \brief 1E.CC00.C LH High Temperature Warning + AQ_GlobalAlarms_APPIA.u0.bits_0.highTemperatureWarning + + + + 1 = High temperature warning threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int highTemperatureWarning : 1; /* 1E.CC00.C LH */ + /* 1 = High temperature warning threshold has been exceeded + */ + /*! \brief 1E.CC00.B LH Low Temperature Warning + AQ_GlobalAlarms_APPIA.u0.bits_0.lowTemperatureWarning + + + + 1 = Low temperature warning threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int lowTemperatureWarning : 1; /* 1E.CC00.B LH */ + /* 1 = Low temperature warning threshold has been exceeded + */ + unsigned int reserved1 : 4; + /*! \brief 1E.CC00.6 LH Reset completed + AQ_GlobalAlarms_APPIA.u0.bits_0.resetCompleted + + + + 1 = Chip wide reset completed + + Notes: + This bit is set by the microprocessor when it has completed it's initialization sequence. This bit is mirrored in 1.CC02.0 */ + unsigned int resetCompleted : 1; /* 1E.CC00.6 LH */ + /* 1 = Chip wide reset completed */ + unsigned int reserved2 : 1; + /*! \brief 1E.CC00.4 LH Device Fault + AQ_GlobalAlarms_APPIA.u0.bits_0.deviceFault + + + + 1 = Fault + + Notes: + When set, a fault has been detected by the uP and the associated 16 bit error code is visible in See Global Configuration Fault Message: Address 1E.C850 */ + unsigned int deviceFault : 1; /* 1E.CC00.4 LH */ + /* 1 = Fault */ + /*! \brief 1E.CC00.3 LH Reserved Alarm A + AQ_GlobalAlarms_APPIA.u0.bits_0.reservedAlarmA + + + + Reserved for future use + + */ + unsigned int reservedAlarmA : 1; /* 1E.CC00.3 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC00.2 LH Reserved Alarm B + AQ_GlobalAlarms_APPIA.u0.bits_0.reservedAlarmB + + + + Reserved for future use + + */ + unsigned int reservedAlarmB : 1; /* 1E.CC00.2 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC00.1 LH Reserved Alarm C + AQ_GlobalAlarms_APPIA.u0.bits_0.reservedAlarmC + + + + Reserved for future use + + */ + unsigned int reservedAlarmC : 1; /* 1E.CC00.1 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC00.0 LH Reserved Alarm D + AQ_GlobalAlarms_APPIA.u0.bits_0.reservedAlarmD + + + + Reserved for future use + + */ + unsigned int reservedAlarmD : 1; /* 1E.CC00.0 LH */ + /* Reserved for future use + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Alarms */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.CC01.E LH Smart Power-Down Entered + AQ_GlobalAlarms_APPIA.u1.bits_1.smartPower_downEntered + + + + 1 = Smart Power-Down State Entered + + + Notes: + When this bit is set, it indicates that the Smart Power-Down state was entered */ + unsigned int smartPower_downEntered : 1; /* 1E.CC01.E LH */ + /* 1 = Smart Power-Down State Entered + */ + /*! \brief 1E.CC01.D RO XENPAK Alarm + AQ_GlobalAlarms_APPIA.u1.bits_1.xenpakAlarm + + + + 1 = XENPAK Alarm + + + Notes: + This alarm is performed by H/W. */ + unsigned int xenpakAlarm : 1; /* 1E.CC01.D RO */ + /* 1 = XENPAK Alarm + */ + /*! \brief 1E.CC01.C:8 LH Reserved Alarms [4:0] + AQ_GlobalAlarms_APPIA.u1.bits_1.reservedAlarms + + + + Reserved for future use + + */ + unsigned int reservedAlarms : 5; /* 1E.CC01.C:8 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC01.7 LH MDIO Command Handling Overflow + AQ_GlobalAlarms_APPIA.u1.bits_1.mdioCommandHandlingOverflow + + + + 1 = PHY was issued more MDIO requests than it could service in it's request buffer + + + Notes: + Assertion of this bit means that more MDIO commands were issued than FW could handle. */ + unsigned int mdioCommandHandlingOverflow : 1; /* 1E.CC01.7 LH */ + /* 1 = PHY was issued more MDIO requests than it could service in it's request buffer + */ + unsigned int reserved1 : 6; + /*! \brief 1E.CC01.0 LH Diagnostic Alarm + AQ_GlobalAlarms_APPIA.u1.bits_1.diagnosticAlarm + + + + 1 = Alarm triggered by a write to 1E.C470.7 + + + Notes: + A diagnostic alarm use to test system alarm circuitry */ + unsigned int diagnosticAlarm : 1; /* 1E.CC01.0 LH */ + /* 1 = Alarm triggered by a write to 1E.C470.7 + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Alarms */ + union + { + struct + { + /*! \brief 1E.CC02.F LH NVR Operation Complete + AQ_GlobalAlarms_APPIA.u2.bits_2.nvrOperationComplete + + + + 1 = NVR operation is complete + + + Notes: + NVR interface is ready interrupt for registers See Global NVR Interface 1: Address 1E.100 - See Global NVR Provisioning Data MSW - Address 1E.17 . */ + unsigned int nvrOperationComplete : 1; /* 1E.CC02.F LH */ + /* 1 = NVR operation is complete + */ + /*! \brief 1E.CC02.E LH Mailbox Operation: Complete + AQ_GlobalAlarms_APPIA.u2.bits_2.mailboxOperation_Complete + + + + 1 = Mailbox operation is complete + + + Notes: + Mailbox interface is ready interrupt for registers See Global Vendor Specific Control - Address 1E.C000 - See Global Vendor Specific Provisioning 5 - Address 1E.C404 */ + unsigned int mailboxOperation_Complete : 1; /* 1E.CC02.E LH */ + /* 1 = Mailbox operation is complete + */ + unsigned int reserved0 : 3; + /*! \brief 1E.CC02.A LH uP DRAM Parity Error + AQ_GlobalAlarms_APPIA.u2.bits_2.upDramParityError + + + + 1 = Parity error detected in the uP DRAM + + */ + unsigned int upDramParityError : 1; /* 1E.CC02.A LH */ + /* 1 = Parity error detected in the uP DRAM + */ + /*! \brief 1E.CC02.9:8 LH uP IRAM Parity Error [1:0] + AQ_GlobalAlarms_APPIA.u2.bits_2.upIramParityError + + + + 1 = Parity error detected in the uP IRAM + + + Notes: + Bit 0 indicates a parity error was detected in the uP IRAM but was corrected. + Bit 1 indicates a multiple parity errors were detected in the uP IRAM and could not be corrected. + The uP IRAM is protected with ECC. */ + unsigned int upIramParityError : 2; /* 1E.CC02.9:8 LH */ + /* 1 = Parity error detected in the uP IRAM + */ + unsigned int reserved1 : 2; + /*! \brief 1E.CC02.5 LRF Tx Enable State Change + AQ_GlobalAlarms_APPIA.u2.bits_2.txEnableStateChange + + + + 1 = TX_EN pin has changed state + + */ + unsigned int txEnableStateChange : 1; /* 1E.CC02.5 LRF */ + /* 1 = TX_EN pin has changed state + */ + unsigned int reserved2 : 2; + /*! \brief 1E.CC02.2 LH MDIO MMD Error + AQ_GlobalAlarms_APPIA.u2.bits_2.mdioMMD_Error + + + + 1 = Invalid MMD address detected + + */ + unsigned int mdioMMD_Error : 1; /* 1E.CC02.2 LH */ + /* 1 = Invalid MMD address detected + */ + /*! \brief 1E.CC02.1 LH MDIO Timeout Error + AQ_GlobalAlarms_APPIA.u2.bits_2.mdioTimeoutError + + + + 1 = MDIO timeout detected + + */ + unsigned int mdioTimeoutError : 1; /* 1E.CC02.1 LH */ + /* 1 = MDIO timeout detected + */ + /*! \brief 1E.CC02.0 LH Watchdog Timer Alarm + AQ_GlobalAlarms_APPIA.u2.bits_2.watchdogTimerAlarm + + + + 1 = Watchdog timer alarm + + */ + unsigned int watchdogTimerAlarm : 1; /* 1E.CC02.0 LH */ + /* 1 = Watchdog timer alarm + */ + } bits_2; + uint16_t word_2; + } u2; +} AQ_GlobalAlarms_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Interrupt Mask: 1E.D400 */ +/* Global Interrupt Mask: 1E.D400 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Interrupt Mask */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.D400.E R/WPD High Temperature Failure Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.highTemperatureFailureMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int highTemperatureFailureMask : 1; /* 1E.D400.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D400.D R/WPD Low Temperature Failure Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.lowTemperatureFailureMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int lowTemperatureFailureMask : 1; /* 1E.D400.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D400.C R/WPD High Temperature Warning Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.highTemperatureWarningMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int highTemperatureWarningMask : 1; /* 1E.D400.C R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D400.B R/WPD Low Temperature Warning Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.lowTemperatureWarningMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int lowTemperatureWarningMask : 1; /* 1E.D400.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved1 : 4; + /*! \brief 1E.D400.6 R/WPD Reset completed Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.resetCompletedMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int resetCompletedMask : 1; /* 1E.D400.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved2 : 1; + /*! \brief 1E.D400.4 R/WPD Device Fault Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.deviceFaultMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int deviceFaultMask : 1; /* 1E.D400.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D400.3 R/WPD Reserved Alarm A Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.reservedAlarmAMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmAMask : 1; /* 1E.D400.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D400.2 R/WPD Reserved Alarm B Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.reservedAlarmBMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmBMask : 1; /* 1E.D400.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D400.1 R/WPD Reserved Alarm C Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.reservedAlarmCMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmCMask : 1; /* 1E.D400.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D400.0 R/WPD Reserved Alarm D Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.reservedAlarmDMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmDMask : 1; /* 1E.D400.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Interrupt Mask */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.D401.E R/WPD Smart Power-Down Entered Mask + AQ_GlobalInterruptMask_APPIA.u1.bits_1.smartPower_downEnteredMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int smartPower_downEnteredMask : 1; /* 1E.D401.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D401.D R/WPD XENPAK Alarm Mask + AQ_GlobalInterruptMask_APPIA.u1.bits_1.xenpakAlarmMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int xenpakAlarmMask : 1; /* 1E.D401.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D401.C:8 R/WPD Reserved Alarms Mask [4:0] + AQ_GlobalInterruptMask_APPIA.u1.bits_1.reservedAlarmsMask + + Provisionable Default = 0x00 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmsMask : 5; /* 1E.D401.C:8 R/WPD Provisionable Default = 0x00 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D401.7 R/WPD MDIO Command Handling Overflow Mask + AQ_GlobalInterruptMask_APPIA.u1.bits_1.mdioCommandHandlingOverflowMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int mdioCommandHandlingOverflowMask : 1; /* 1E.D401.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int reserved1 : 6; + /*! \brief 1E.D401.0 R/WPD Diagnostic Alarm Mask + AQ_GlobalInterruptMask_APPIA.u1.bits_1.diagnosticAlarmMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int diagnosticAlarmMask : 1; /* 1E.D401.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Interrupt Mask */ + union + { + struct + { + /*! \brief 1E.D402.F R/WPD NVR Operation Complete Mask + AQ_GlobalInterruptMask_APPIA.u2.bits_2.nvrOperationCompleteMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + Notes: + NVR interface is ready interrupt for registers See Global NVR Interface 1: Address 1E.100 - See Global NVR Provisioning Data MSW - Address 1E.17 */ + unsigned int nvrOperationCompleteMask : 1; /* 1E.D402.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D402.E R/WPD Mailbox Operation Complete Mask + AQ_GlobalInterruptMask_APPIA.u2.bits_2.mailboxOperationCompleteMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + Notes: + Mailbox interface is ready interrupt for registers See Global Vendor Specific Control - Address 1E.C000 - See Global Vendor Specific Provisioning 5 - Address 1E.C404 */ + unsigned int mailboxOperationCompleteMask : 1; /* 1E.D402.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved0 : 3; + /*! \brief 1E.D402.A R/WPD uP DRAM Parity Error Mask + AQ_GlobalInterruptMask_APPIA.u2.bits_2.upDramParityErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int upDramParityErrorMask : 1; /* 1E.D402.A R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D402.9:8 R/WPD uP IRAM Parity Error Mask [1:0] + AQ_GlobalInterruptMask_APPIA.u2.bits_2.upIramParityErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int upIramParityErrorMask : 2; /* 1E.D402.9:8 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int reserved1 : 2; + /*! \brief 1E.D402.5 R/WPD Tx Enable State Change Mask + AQ_GlobalInterruptMask_APPIA.u2.bits_2.txEnableStateChangeMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int txEnableStateChangeMask : 1; /* 1E.D402.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved2 : 2; + /*! \brief 1E.D402.2 R/WPD MDIO MMD Error Mask + AQ_GlobalInterruptMask_APPIA.u2.bits_2.mdioMMD_ErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int mdioMMD_ErrorMask : 1; /* 1E.D402.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D402.1 R/WPD MDIO Timeout Error Mask + AQ_GlobalInterruptMask_APPIA.u2.bits_2.mdioTimeoutErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int mdioTimeoutErrorMask : 1; /* 1E.D402.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D402.0 R/WPD Watchdog Timer Alarm Mask + AQ_GlobalInterruptMask_APPIA.u2.bits_2.watchdogTimerAlarmMask + + Provisionable Default = 0x1 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int watchdogTimerAlarmMask : 1; /* 1E.D402.0 R/WPD Provisionable Default = 0x1 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + } bits_2; + uint16_t word_2; + } u2; +} AQ_GlobalInterruptMask_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Chip-Wide Standard Interrupt Flags: 1E.FC00 */ +/* Global Chip-Wide Standard Interrupt Flags: 1E.FC00 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Chip-Wide Standard Interrupt Flags */ + union + { + struct + { + /*! \brief 1E.FC00.F RO PMA Standard Alarm 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.pmaStandardAlarm_1Interrupt + + + + 1 = Interrupt in PMA standard alarms 1 + + + Notes: + An interrupt was generated from bit 1.1.2. + An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ + unsigned int pmaStandardAlarm_1Interrupt : 1; /* 1E.FC00.F RO */ + /* 1 = Interrupt in PMA standard alarms 1 + */ + /*! \brief 1E.FC00.E RO PMA Standard Alarm 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.pmaStandardAlarm_2Interrupt + + + + 1 = Interrupt in PMA standard alarms 2 + + + Notes: + An interrupt was generated from either bit 1.8.B or 1.8.A. + An interrupt was generated from status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int pmaStandardAlarm_2Interrupt : 1; /* 1E.FC00.E RO */ + /* 1 = Interrupt in PMA standard alarms 2 + */ + /*! \brief 1E.FC00.D RO PCS Standard Alarm 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.pcsStandardAlarm_1Interrupt + + + + 1 = Interrupt in PCS standard alarms 1 + + + Notes: + An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ + unsigned int pcsStandardAlarm_1Interrupt : 1; /* 1E.FC00.D RO */ + /* 1 = Interrupt in PCS standard alarms 1 + */ + /*! \brief 1E.FC00.C RO PCS Standard Alarm 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.pcsStandardAlarm_2Interrupt + + + + 1 = Interrupt in PCS standard alarms 2 + + + Notes: + An interrupt was generated from status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int pcsStandardAlarm_2Interrupt : 1; /* 1E.FC00.C RO */ + /* 1 = Interrupt in PCS standard alarms 2 + */ + /*! \brief 1E.FC00.B RO PCS Standard Alarm 3 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.pcsStandardAlarm_3Interrupt + + + + 1 = Interrupt in PCS standard alarms 3 + + + Notes: + An interrupt was generated from status register ( See PCS 10GBASE-T Status 2 - Address 3.21 ) and the corresponding mask register. ( See PCS Standard Interrupt Mask 1 - Address 3.E021 ) */ + unsigned int pcsStandardAlarm_3Interrupt : 1; /* 1E.FC00.B RO */ + /* 1 = Interrupt in PCS standard alarms 3 + */ + /*! \brief 1E.FC00.A RO PHY XS Standard Alarms 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.phyXS_StandardAlarms_1Interrupt + + + + 1 = Interrupt in PHY XS standard alarms 1 + + + Notes: + An interrupt was generated from the status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ + unsigned int phyXS_StandardAlarms_1Interrupt : 1; /* 1E.FC00.A RO */ + /* 1 = Interrupt in PHY XS standard alarms 1 + */ + /*! \brief 1E.FC00.9 RO PHY XS Standard Alarms 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.phyXS_StandardAlarms_2Interrupt + + + + 1 = Interrupt in PHY XS standard alarms 2 + + + Notes: + An interrupt was generated from the status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int phyXS_StandardAlarms_2Interrupt : 1; /* 1E.FC00.9 RO */ + /* 1 = Interrupt in PHY XS standard alarms 2 + */ + /*! \brief 1E.FC00.8 RO Autonegotiation Standard Alarms 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.autonegotiationStandardAlarms_1Interrupt + + + + 1 = Interrupt in Autonegotiation standard alarms 1 + + + Notes: + An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See Autonegotiation Standard LASI Interrupt Mask 1: Address 7.D000 ) */ + unsigned int autonegotiationStandardAlarms_1Interrupt : 1; /* 1E.FC00.8 RO */ + /* 1 = Interrupt in Autonegotiation standard alarms 1 + */ + /*! \brief 1E.FC00.7 RO Autonegotiation Standard Alarms 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.autonegotiationStandardAlarms_2Interrupt + + + + 1 = Interrupt in Autonegotiation standard alarms 2 + + + Notes: + An interrupt was generated from status register ( See Autonegotiation 10GBASE-T Status Register - Address 7.21 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int autonegotiationStandardAlarms_2Interrupt : 1; /* 1E.FC00.7 RO */ + /* 1 = Interrupt in Autonegotiation standard alarms 2 + */ + /*! \brief 1E.FC00.6 RO GbE Standard Alarms Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.gbeStandardAlarmsInterrupt + + + + 1 = Interrupt in GbE standard alarms + + + Notes: + An interrupt was generated from the TGE core. */ + unsigned int gbeStandardAlarmsInterrupt : 1; /* 1E.FC00.6 RO */ + /* 1 = Interrupt in GbE standard alarms + */ + unsigned int reserved0 : 5; + /*! \brief 1E.FC00.0 RO All Vendor Alarms Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.allVendorAlarmsInterrupt + + + + 1 = Interrupt in all vendor alarms + + + Notes: + An interrupt was generated from status register ( See Global Chip-Wide LASI Vendor Interrupt Flags: Address 1E.FC01 ) and the corresponding mask register. ( See Global Interrupt LASI Mask: Address 1E.FF01 ) */ + unsigned int allVendorAlarmsInterrupt : 1; /* 1E.FC00.0 RO */ + /* 1 = Interrupt in all vendor alarms + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalChip_wideStandardInterruptFlags_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Chip-Wide Vendor Interrupt Flags: 1E.FC01 */ +/* Global Chip-Wide Vendor Interrupt Flags: 1E.FC01 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Chip-Wide Vendor Interrupt Flags */ + union + { + struct + { + /*! \brief 1E.FC01.F RO PMA Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.pmaVendorAlarmInterrupt + + + + 1 = Interrupt in PMA vendor specific alarm + + + Notes: + A PMA alarm was generated. ( See PHY XS Vendor Global Interrupt Flags 1- Address 4.F800 ) */ + unsigned int pmaVendorAlarmInterrupt : 1; /* 1E.FC01.F RO */ + /* 1 = Interrupt in PMA vendor specific alarm + */ + /*! \brief 1E.FC01.E RO PCS Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.pcsVendorAlarmInterrupt + + + + 1 = Interrupt in PCS vendor specific alarm + + + Notes: + A PCS alarm was generated. ( See PHY XS Vendor Global Interrupt Flags 1- Address 4.F800 ) */ + unsigned int pcsVendorAlarmInterrupt : 1; /* 1E.FC01.E RO */ + /* 1 = Interrupt in PCS vendor specific alarm + */ + /*! \brief 1E.FC01.D RO PHY XS Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.phyXS_VendorAlarmInterrupt + + + + 1 = Interrupt in PHY XS vendor specific alarm + + + Notes: + A PHY XS alarm was generated. ( See PHY XS Vendor Global LASI Interrupt Flags 1: Address 4.FC00 ) */ + unsigned int phyXS_VendorAlarmInterrupt : 1; /* 1E.FC01.D RO */ + /* 1 = Interrupt in PHY XS vendor specific alarm + */ + /*! \brief 1E.FC01.C RO Autonegotiation Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.autonegotiationVendorAlarmInterrupt + + + + 1 = Interrupt in Autonegotiation vendor specific alarm + + + Notes: + An Autonegotiation alarm was generated. ( See Autonegotiation Vendor Global LASI Interrupt Flags 1: Address 7.FC00 ) */ + unsigned int autonegotiationVendorAlarmInterrupt : 1; /* 1E.FC01.C RO */ + /* 1 = Interrupt in Autonegotiation vendor specific alarm + */ + /*! \brief 1E.FC01.B RO GbE Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.gbeVendorAlarmInterrupt + + + + 1 = Interrupt in GbE vendor specific alarm + + + Notes: + A GbE alarm was generated. ( See GbE PHY Vendor Global LASI Interrupt Flags 1: Address 1D.FC00 ) */ + unsigned int gbeVendorAlarmInterrupt : 1; /* 1E.FC01.B RO */ + /* 1 = Interrupt in GbE vendor specific alarm + */ + unsigned int reserved0 : 8; + /*! \brief 1E.FC01.2 RO Global Alarms 1 Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.globalAlarms_1Interrupt + + + + 1 = Interrupt in Global alarms 1 + + + Notes: + An interrupt was generated from status register ( See Global Vendor Alarms 1 - Address 1E.CC00 ) and the corresponding mask register. ( See Global Vendor Interrupt Mask - Address 1E.D400 ) */ + unsigned int globalAlarms_1Interrupt : 1; /* 1E.FC01.2 RO */ + /* 1 = Interrupt in Global alarms 1 + */ + /*! \brief 1E.FC01.1 RO Global Alarms 2 Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.globalAlarms_2Interrupt + + + + 1 = Interrupt in Global alarms 2 + + + Notes: + An interrupt was generated from status register ( See Global Alarms 2: Address 1E.CC01 ) and the corresponding mask register. ( See Global LASI Interrupt Mask 2: Address 1E.D401 ) */ + unsigned int globalAlarms_2Interrupt : 1; /* 1E.FC01.1 RO */ + /* 1 = Interrupt in Global alarms 2 + */ + /*! \brief 1E.FC01.0 RO Global Alarms 3 Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.globalAlarms_3Interrupt + + + + 1 = Interrupt in Global alarms 3 + + + Notes: + An interrupt was generated from status register ( See Global Vendor Alarms 2: Address 1E.CC01 ) and the corresponding mask register. ( See Global LASI Interrupt Mask 2: Address 1E.D401 ) */ + unsigned int globalAlarms_3Interrupt : 1; /* 1E.FC01.0 RO */ + /* 1 = Interrupt in Global alarms 3 + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalChip_wideVendorInterruptFlags_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Interrupt Chip-Wide Standard Mask: 1E.FF00 */ +/* Global Interrupt Chip-Wide Standard Mask: 1E.FF00 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Interrupt Chip-Wide Standard Mask */ + union + { + struct + { + /*! \brief 1E.FF00.F R/WPD PMA Standard Alarm 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.pmaStandardAlarm_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pmaStandardAlarm_1InterruptMask : 1; /* 1E.FF00.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.E R/WPD PMA Standard Alarm 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.pmaStandardAlarm_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pmaStandardAlarm_2InterruptMask : 1; /* 1E.FF00.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.D R/WPD PCS Standard Alarm 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.pcsStandardAlarm_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsStandardAlarm_1InterruptMask : 1; /* 1E.FF00.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.C R/WPD PCS Standard Alarm 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.pcsStandardAlarm_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsStandardAlarm_2InterruptMask : 1; /* 1E.FF00.C R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.B R/WPD PCS Standard Alarm 3 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.pcsStandardAlarm_3InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsStandardAlarm_3InterruptMask : 1; /* 1E.FF00.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.A R/WPD PHY XS Standard Alarms 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.phyXS_StandardAlarms_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int phyXS_StandardAlarms_1InterruptMask : 1; /* 1E.FF00.A R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.9 R/WPD PHY XS Standard Alarms 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.phyXS_StandardAlarms_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int phyXS_StandardAlarms_2InterruptMask : 1; /* 1E.FF00.9 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.8 R/WPD Autonegotiation Standard Alarms 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.autonegotiationStandardAlarms_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int autonegotiationStandardAlarms_1InterruptMask : 1; /* 1E.FF00.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.7 R/WPD Autonegotiation Standard Alarms 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.autonegotiationStandardAlarms_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int autonegotiationStandardAlarms_2InterruptMask : 1; /* 1E.FF00.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.6 R/WPD Gbe Standard Alarms Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.gbeStandardAlarmsInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int gbeStandardAlarmsInterruptMask : 1; /* 1E.FF00.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved0 : 5; + /*! \brief 1E.FF00.0 R/WPD All Vendor Alarms Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.allVendorAlarmsInterruptMask + + Provisionable Default = 0x1 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int allVendorAlarmsInterruptMask : 1; /* 1E.FF00.0 R/WPD Provisionable Default = 0x1 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalInterruptChip_wideStandardMask_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Interrupt Chip-Wide Vendor Mask: 1E.FF01 */ +/* Global Interrupt Chip-Wide Vendor Mask: 1E.FF01 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Interrupt Chip-Wide Vendor Mask */ + union + { + struct + { + /*! \brief 1E.FF01.F R/WPD PMA Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.pmaVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pmaVendorAlarmInterruptMask : 1; /* 1E.FF01.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.E R/WPD PCS Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.pcsVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsVendorAlarmInterruptMask : 1; /* 1E.FF01.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.D R/WPD PHY XS Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.phyXS_VendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int phyXS_VendorAlarmInterruptMask : 1; /* 1E.FF01.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.C R/WPD Autonegotiation Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.autonegotiationVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int autonegotiationVendorAlarmInterruptMask : 1; /* 1E.FF01.C R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.B R/WPD GbE Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.gbeVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int gbeVendorAlarmInterruptMask : 1; /* 1E.FF01.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved0 : 8; + /*! \brief 1E.FF01.2 R/WPD Global Alarms 1 Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.globalAlarms_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int globalAlarms_1InterruptMask : 1; /* 1E.FF01.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.1 R/WPD Global Alarms 2 Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.globalAlarms_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int globalAlarms_2InterruptMask : 1; /* 1E.FF01.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.0 R/WPD Global Alarms 3 Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.globalAlarms_3InterruptMask + + Provisionable Default = 0x1 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int globalAlarms_3InterruptMask : 1; /* 1E.FF01.0 R/WPD Provisionable Default = 0x1 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalInterruptChip_wideVendorMask_APPIA; + +#endif +/*@}*/ +/*@}*/ diff --git a/qca/aq-fw-download/src/include/registerMap/AQ_RegGroupMaxSizes.h b/qca/aq-fw-download/src/include/registerMap/AQ_RegGroupMaxSizes.h new file mode 100644 index 000000000..08e255860 --- /dev/null +++ b/qca/aq-fw-download/src/include/registerMap/AQ_RegGroupMaxSizes.h @@ -0,0 +1,387 @@ +/* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +*/ +#ifndef AQ_REG_GROUP_MAX_SIZES +#define AQ_REG_GROUP_MAX_SIZES + +#define AQ_Autonegotiation10GBaseT_ControlRegister_BiggestVersion AQ_Autonegotiation10GBaseT_ControlRegister_HHD +#define AQ_Autonegotiation10GBaseT_StatusRegister_BiggestVersion AQ_Autonegotiation10GBaseT_StatusRegister_HHD +#define AQ_AutonegotiationAdvertisementRegister_BiggestVersion AQ_AutonegotiationAdvertisementRegister_HHD +#define AQ_AutonegotiationEeeAdvertisementRegister_BiggestVersion AQ_AutonegotiationEeeAdvertisementRegister_HHD +#define AQ_AutonegotiationEeeLinkPartnerAbilityRegister_BiggestVersion AQ_AutonegotiationEeeLinkPartnerAbilityRegister_HHD +#define AQ_AutonegotiationExtendedNextPageTransmitRegister_BiggestVersion AQ_AutonegotiationExtendedNextPageTransmitRegister_HHD +#define AQ_AutonegotiationExtendedNextPageUnformattedCodeRegister_BiggestVersion AQ_AutonegotiationExtendedNextPageUnformattedCodeRegister_HHD +#define AQ_AutonegotiationLinkPartnerBasePageAbilityRegister_BiggestVersion AQ_AutonegotiationLinkPartnerBasePageAbilityRegister_HHD +#define AQ_AutonegotiationLinkPartnerExtendedNextPageAbilityRegister_BiggestVersion AQ_AutonegotiationLinkPartnerExtendedNextPageAbilityRegister_HHD +#define AQ_AutonegotiationLinkPartnerExtendedNextPageUnformattedCodeRegister_BiggestVersion AQ_AutonegotiationLinkPartnerExtendedNextPageUnformattedCodeRegister_HHD +#define AQ_AutonegotiationReceiveLinkPartnerStatus_BiggestVersion AQ_AutonegotiationReceiveLinkPartnerStatus_HHD +#define AQ_AutonegotiationReceiveReservedVendorProvisioning_BiggestVersion AQ_AutonegotiationReceiveReservedVendorProvisioning_APPIA +#define AQ_AutonegotiationReceiveReservedVendorStatus_BiggestVersion AQ_AutonegotiationReceiveReservedVendorStatus_HHD +#define AQ_AutonegotiationReceiveVendorAlarms_BiggestVersion AQ_AutonegotiationReceiveVendorAlarms_HHD +#define AQ_AutonegotiationReceiveVendorInterruptMask_BiggestVersion AQ_AutonegotiationReceiveVendorInterruptMask_HHD +#define AQ_AutonegotiationReservedVendorProvisioning_BiggestVersion AQ_AutonegotiationReservedVendorProvisioning_HHD +#define AQ_AutonegotiationReservedVendorStatus_BiggestVersion AQ_AutonegotiationReservedVendorStatus_HHD +#define AQ_AutonegotiationStandardControl_1_BiggestVersion AQ_AutonegotiationStandardControl_1_HHD +#define AQ_AutonegotiationStandardDeviceIdentifier_BiggestVersion AQ_AutonegotiationStandardDeviceIdentifier_HHD +#define AQ_AutonegotiationStandardDevicesInPackage_BiggestVersion AQ_AutonegotiationStandardDevicesInPackage_HHD +#define AQ_AutonegotiationStandardInterruptMask_BiggestVersion AQ_AutonegotiationStandardInterruptMask_HHD +#define AQ_AutonegotiationStandardPackageIdentifier_BiggestVersion AQ_AutonegotiationStandardPackageIdentifier_HHD +#define AQ_AutonegotiationStandardStatus_1_BiggestVersion AQ_AutonegotiationStandardStatus_1_HHD +#define AQ_AutonegotiationStandardStatus_2_BiggestVersion AQ_AutonegotiationStandardStatus_2_HHD +#define AQ_AutonegotiationTransmitVendorAlarms_BiggestVersion AQ_AutonegotiationTransmitVendorAlarms_APPIA +#define AQ_AutonegotiationTransmitVendorInterruptMask_BiggestVersion AQ_AutonegotiationTransmitVendorInterruptMask_HHD +#define AQ_AutonegotiationVendorGlobalInterruptFlags_BiggestVersion AQ_AutonegotiationVendorGlobalInterruptFlags_HHD +#define AQ_AutonegotiationVendorProvisioning_BiggestVersion AQ_AutonegotiationVendorProvisioning_HHD +#define AQ_AutonegotiationVendorStatus_BiggestVersion AQ_AutonegotiationVendorStatus_HHD +#define AQ_GbePhyExtendedWolControl_BiggestVersion AQ_GbePhyExtendedWolControl_HHD +#define AQ_GbePhySgmii0RxStatus_BiggestVersion AQ_GbePhySgmii0RxStatus_HHD +#define AQ_GbePhySgmii0TxStatus_BiggestVersion AQ_GbePhySgmii0TxStatus_HHD +#define AQ_GbePhySgmii1RxStatus_BiggestVersion AQ_GbePhySgmii1RxStatus_HHD +#define AQ_GbePhySgmii1TxStatus_BiggestVersion AQ_GbePhySgmii1TxStatus_HHD +#define AQ_GbePhySgmii1WolStatus_BiggestVersion AQ_GbePhySgmii1WolStatus_HHD +#define AQ_GbePhySgmiiRxAlarms_BiggestVersion AQ_GbePhySgmiiRxAlarms_HHD +#define AQ_GbePhySgmiiRxInterruptMask_BiggestVersion AQ_GbePhySgmiiRxInterruptMask_HHD +#define AQ_GbePhySgmiiTestControl_BiggestVersion AQ_GbePhySgmiiTestControl_HHD +#define AQ_GbePhySgmiiTxAlarms_BiggestVersion AQ_GbePhySgmiiTxAlarms_HHD +#define AQ_GbePhySgmiiTxInterruptMask_BiggestVersion AQ_GbePhySgmiiTxInterruptMask_HHD +#define AQ_GbePhySgmiiWolStatus_BiggestVersion AQ_GbePhySgmiiWolStatus_HHD +#define AQ_GbePhyVendorGlobalInterruptFlags_BiggestVersion AQ_GbePhyVendorGlobalInterruptFlags_HHD +#define AQ_GbePhyWolControl_BiggestVersion AQ_GbePhyWolControl_HHD +#define AQ_GbePhysgmii1WolStatus_BiggestVersion AQ_GbePhysgmii1WolStatus_APPIA +#define AQ_GbeReservedProvisioning_BiggestVersion AQ_GbeReservedProvisioning_HHD +#define AQ_GbeStandardDeviceIdentifier_BiggestVersion AQ_GbeStandardDeviceIdentifier_HHD +#define AQ_GbeStandardDevicesInPackage_BiggestVersion AQ_GbeStandardDevicesInPackage_HHD +#define AQ_GbeStandardPackageIdentifier_BiggestVersion AQ_GbeStandardPackageIdentifier_HHD +#define AQ_GbeStandardStatus_2_BiggestVersion AQ_GbeStandardStatus_2_HHD +#define AQ_GbeStandardVendorDevicesInPackage_BiggestVersion AQ_GbeStandardVendorDevicesInPackage_HHD +#define AQ_GlobalAlarms_BiggestVersion AQ_GlobalAlarms_HHD +#define AQ_GlobalCableDiagnosticImpedance_BiggestVersion AQ_GlobalCableDiagnosticImpedance_HHD +#define AQ_GlobalCableDiagnosticStatus_BiggestVersion AQ_GlobalCableDiagnosticStatus_APPIA +#define AQ_GlobalChipIdentification_BiggestVersion AQ_GlobalChipIdentification_APPIA +#define AQ_GlobalChipRevision_BiggestVersion AQ_GlobalChipRevision_APPIA +#define AQ_GlobalChip_wideStandardInterruptFlags_BiggestVersion AQ_GlobalChip_wideStandardInterruptFlags_HHD +#define AQ_GlobalChip_wideVendorInterruptFlags_BiggestVersion AQ_GlobalChip_wideVendorInterruptFlags_HHD +#define AQ_GlobalControl_BiggestVersion AQ_GlobalControl_HHD +#define AQ_GlobalDaisyChainStatus_BiggestVersion AQ_GlobalDaisyChainStatus_HHD +#define AQ_GlobalDiagnosticProvisioning_BiggestVersion AQ_GlobalDiagnosticProvisioning_HHD +#define AQ_GlobalEeeProvisioning_BiggestVersion AQ_GlobalEeeProvisioning_HHD +#define AQ_GlobalFaultMessage_BiggestVersion AQ_GlobalFaultMessage_HHD +#define AQ_GlobalFirmwareID_BiggestVersion AQ_GlobalFirmwareID_HHD +#define AQ_GlobalGeneralProvisioning_BiggestVersion AQ_GlobalGeneralProvisioning_HHD +#define AQ_GlobalGeneralStatus_BiggestVersion AQ_GlobalGeneralStatus_HHD +#define AQ_GlobalInterruptChip_wideStandardMask_BiggestVersion AQ_GlobalInterruptChip_wideStandardMask_HHD +#define AQ_GlobalInterruptChip_wideVendorMask_BiggestVersion AQ_GlobalInterruptChip_wideVendorMask_HHD +#define AQ_GlobalInterruptMask_BiggestVersion AQ_GlobalInterruptMask_HHD +#define AQ_GlobalLedProvisioning_BiggestVersion AQ_GlobalLedProvisioning_HHD +#define AQ_GlobalMailboxInterface_BiggestVersion AQ_GlobalMailboxInterface_HHD +#define AQ_GlobalMicroprocessorScratchPad_BiggestVersion AQ_GlobalMicroprocessorScratchPad_HHD +#define AQ_GlobalNvrInterface_BiggestVersion AQ_GlobalNvrInterface_HHD +#define AQ_GlobalNvrProvisioning_BiggestVersion AQ_GlobalNvrProvisioning_HHD +#define AQ_GlobalPinStatus_BiggestVersion AQ_GlobalPinStatus_HHD +#define AQ_GlobalPrimaryStatus_BiggestVersion AQ_GlobalPrimaryStatus_APPIA +#define AQ_GlobalReservedProvisioning_BiggestVersion AQ_GlobalReservedProvisioning_HHD +#define AQ_GlobalReservedStatus_BiggestVersion AQ_GlobalReservedStatus_HHD +#define AQ_GlobalResetControl_BiggestVersion AQ_GlobalResetControl_HHD +#define AQ_GlobalSmbus_0Provisioning_BiggestVersion AQ_GlobalSmbus_0Provisioning_HHD +#define AQ_GlobalSmbus_1Provisioning_BiggestVersion AQ_GlobalSmbus_1Provisioning_HHD +#define AQ_GlobalStandardControl_1_BiggestVersion AQ_GlobalStandardControl_1_HHD +#define AQ_GlobalStandardDeviceIdentifier_BiggestVersion AQ_GlobalStandardDeviceIdentifier_HHD +#define AQ_GlobalStandardDevicesInPackage_BiggestVersion AQ_GlobalStandardDevicesInPackage_HHD +#define AQ_GlobalStandardPackageIdentifier_BiggestVersion AQ_GlobalStandardPackageIdentifier_HHD +#define AQ_GlobalStandardStatus_2_BiggestVersion AQ_GlobalStandardStatus_2_HHD +#define AQ_GlobalStandardVendorDevicesInPackage_BiggestVersion AQ_GlobalStandardVendorDevicesInPackage_HHD +#define AQ_GlobalStatus_BiggestVersion AQ_GlobalStatus_HHD +#define AQ_GlobalThermalProvisioning_BiggestVersion AQ_GlobalThermalProvisioning_HHD +#define AQ_GlobalThermalStatus_BiggestVersion AQ_GlobalThermalStatus_HHD +#define AQ_Kr0AutonegotiationAdvertisementWord_BiggestVersion AQ_Kr0AutonegotiationAdvertisementWord_HHD +#define AQ_Kr0AutonegotiationControl_BiggestVersion AQ_Kr0AutonegotiationControl_HHD +#define AQ_Kr0AutonegotiationExtendedNextPageAdvertisementWord_BiggestVersion AQ_Kr0AutonegotiationExtendedNextPageAdvertisementWord_HHD +#define AQ_Kr0AutonegotiationStatus_BiggestVersion AQ_Kr0AutonegotiationStatus_HHD +#define AQ_Kr0LinkPartnerAutonegotiationAdvertisementWord_BiggestVersion AQ_Kr0LinkPartnerAutonegotiationAdvertisementWord_HHD +#define AQ_Kr0LinkPartnerAutonegotiationExtendedNextPageAdvertisementWord_BiggestVersion AQ_Kr0LinkPartnerAutonegotiationExtendedNextPageAdvertisementWord_HHD +#define AQ_Kr1AutonegotiationAdvertisementWord_BiggestVersion AQ_Kr1AutonegotiationAdvertisementWord_HHD +#define AQ_Kr1AutonegotiationControl_BiggestVersion AQ_Kr1AutonegotiationControl_HHD +#define AQ_Kr1AutonegotiationExtendedNextPageAdvertisementWord_BiggestVersion AQ_Kr1AutonegotiationExtendedNextPageAdvertisementWord_HHD +#define AQ_Kr1AutonegotiationStatus_BiggestVersion AQ_Kr1AutonegotiationStatus_HHD +#define AQ_Kr1LinkPartnerAutonegotiationAdvertisementWord_BiggestVersion AQ_Kr1LinkPartnerAutonegotiationAdvertisementWord_HHD +#define AQ_Kr1LinkPartnerAutonegotiationExtendedNextPageAdvertisementWord_BiggestVersion AQ_Kr1LinkPartnerAutonegotiationExtendedNextPageAdvertisementWord_HHD +#define AQ_MsmLineFifoControlRegister_BiggestVersion AQ_MsmLineFifoControlRegister_HHD +#define AQ_MsmLineGeneralControlRegister_BiggestVersion AQ_MsmLineGeneralControlRegister_HHD +#define AQ_MsmLineGeneralStatusRegister_BiggestVersion AQ_MsmLineGeneralStatusRegister_HHD +#define AQ_MsmLineRxAlignmentErrorsCounterRegister_BiggestVersion AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD +#define AQ_MsmLineRxBroadcastFramesCounterRegister_BiggestVersion AQ_MsmLineRxBroadcastFramesCounterRegister_HHD +#define AQ_MsmLineRxErrorsCounterRegister_BiggestVersion AQ_MsmLineRxErrorsCounterRegister_HHD +#define AQ_MsmLineRxFcsErrorsCounterRegister_BiggestVersion AQ_MsmLineRxFcsErrorsCounterRegister_HHD +#define AQ_MsmLineRxGoodFramesCounterRegister_BiggestVersion AQ_MsmLineRxGoodFramesCounterRegister_HHD +#define AQ_MsmLineRxInRangeLengthErrorsCounterRegister_BiggestVersion AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD +#define AQ_MsmLineRxMulticastFramesCounterRegister_BiggestVersion AQ_MsmLineRxMulticastFramesCounterRegister_HHD +#define AQ_MsmLineRxOctetsCounterRegister_BiggestVersion AQ_MsmLineRxOctetsCounterRegister_HHD +#define AQ_MsmLineRxPauseFramesCounterRegister_BiggestVersion AQ_MsmLineRxPauseFramesCounterRegister_HHD +#define AQ_MsmLineRxTooLongErrorsCounterRegister_BiggestVersion AQ_MsmLineRxTooLongErrorsCounterRegister_HHD +#define AQ_MsmLineRxUnicastFramesCounterRegister_BiggestVersion AQ_MsmLineRxUnicastFramesCounterRegister_HHD +#define AQ_MsmLineRxVlanFramesCounterRegister_BiggestVersion AQ_MsmLineRxVlanFramesCounterRegister_HHD +#define AQ_MsmLineTxBroadcastFramesCounterRegister_BiggestVersion AQ_MsmLineTxBroadcastFramesCounterRegister_HHD +#define AQ_MsmLineTxErrorsCounterRegister_BiggestVersion AQ_MsmLineTxErrorsCounterRegister_HHD +#define AQ_MsmLineTxGoodFramesCounterRegister_BiggestVersion AQ_MsmLineTxGoodFramesCounterRegister_HHD +#define AQ_MsmLineTxIpgControlRegister_BiggestVersion AQ_MsmLineTxIpgControlRegister_HHD +#define AQ_MsmLineTxMulticastFramesCounterRegister_BiggestVersion AQ_MsmLineTxMulticastFramesCounterRegister_HHD +#define AQ_MsmLineTxOctetsCounterRegister_BiggestVersion AQ_MsmLineTxOctetsCounterRegister_HHD +#define AQ_MsmLineTxPauseFramesCounterRegister_BiggestVersion AQ_MsmLineTxPauseFramesCounterRegister_HHD +#define AQ_MsmLineTxUnicastFramesCounterRegister_BiggestVersion AQ_MsmLineTxUnicastFramesCounterRegister_HHD +#define AQ_MsmLineTxVlanFramesCounterRegister_BiggestVersion AQ_MsmLineTxVlanFramesCounterRegister_HHD +#define AQ_MsmSystemFifoControlRegister_BiggestVersion AQ_MsmSystemFifoControlRegister_HHD +#define AQ_MsmSystemGeneralControlRegister_BiggestVersion AQ_MsmSystemGeneralControlRegister_HHD +#define AQ_MsmSystemGeneralStatusRegister_BiggestVersion AQ_MsmSystemGeneralStatusRegister_HHD +#define AQ_MsmSystemRxAlignmentErrorsCounterRegister_BiggestVersion AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD +#define AQ_MsmSystemRxBroadcastFramesCounterRegister_BiggestVersion AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD +#define AQ_MsmSystemRxErrorsCounterRegister_BiggestVersion AQ_MsmSystemRxErrorsCounterRegister_HHD +#define AQ_MsmSystemRxFcsErrorsCounterRegister_BiggestVersion AQ_MsmSystemRxFcsErrorsCounterRegister_HHD +#define AQ_MsmSystemRxGoodFramesCounterRegister_BiggestVersion AQ_MsmSystemRxGoodFramesCounterRegister_HHD +#define AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_BiggestVersion AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD +#define AQ_MsmSystemRxMulticastFramesCounterRegister_BiggestVersion AQ_MsmSystemRxMulticastFramesCounterRegister_HHD +#define AQ_MsmSystemRxOctetsCounterRegister_BiggestVersion AQ_MsmSystemRxOctetsCounterRegister_HHD +#define AQ_MsmSystemRxPauseFramesCounterRegister_BiggestVersion AQ_MsmSystemRxPauseFramesCounterRegister_HHD +#define AQ_MsmSystemRxTooLongErrorsCounterRegister_BiggestVersion AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD +#define AQ_MsmSystemRxUnicastFramesCounterRegister_BiggestVersion AQ_MsmSystemRxUnicastFramesCounterRegister_HHD +#define AQ_MsmSystemRxVlanFramesCounterRegister_BiggestVersion AQ_MsmSystemRxVlanFramesCounterRegister_HHD +#define AQ_MsmSystemTxBroadcastFramesCounterRegister_BiggestVersion AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD +#define AQ_MsmSystemTxErrorsCounterRegister_BiggestVersion AQ_MsmSystemTxErrorsCounterRegister_HHD +#define AQ_MsmSystemTxGoodFramesCounterRegister_BiggestVersion AQ_MsmSystemTxGoodFramesCounterRegister_HHD +#define AQ_MsmSystemTxIpgControlRegister_BiggestVersion AQ_MsmSystemTxIpgControlRegister_HHD +#define AQ_MsmSystemTxMulticastFramesCounterRegister_BiggestVersion AQ_MsmSystemTxMulticastFramesCounterRegister_HHD +#define AQ_MsmSystemTxOctetsCounterRegister_BiggestVersion AQ_MsmSystemTxOctetsCounterRegister_HHD +#define AQ_MsmSystemTxPauseFramesCounterRegister_BiggestVersion AQ_MsmSystemTxPauseFramesCounterRegister_HHD +#define AQ_MsmSystemTxUnicastFramesCounterRegister_BiggestVersion AQ_MsmSystemTxUnicastFramesCounterRegister_HHD +#define AQ_MsmSystemTxVlanFramesCounterRegister_BiggestVersion AQ_MsmSystemTxVlanFramesCounterRegister_HHD +#define AQ_MssEgressControlRegister_BiggestVersion AQ_MssEgressControlRegister_HHD +#define AQ_MssEgressEccInterruptStatusRegister_BiggestVersion AQ_MssEgressEccInterruptStatusRegister_HHD +#define AQ_MssEgressInterruptMaskRegister_BiggestVersion AQ_MssEgressInterruptMaskRegister_HHD +#define AQ_MssEgressInterruptStatusRegister_BiggestVersion AQ_MssEgressInterruptStatusRegister_HHD +#define AQ_MssEgressLutAddressControlRegister_BiggestVersion AQ_MssEgressLutAddressControlRegister_HHD +#define AQ_MssEgressLutControlRegister_BiggestVersion AQ_MssEgressLutControlRegister_HHD +#define AQ_MssEgressLutDataControlRegister_BiggestVersion AQ_MssEgressLutDataControlRegister_HHD +#define AQ_MssEgressMtuSizeControlRegister_BiggestVersion AQ_MssEgressMtuSizeControlRegister_HHD +#define AQ_MssEgressPnControlRegister_BiggestVersion AQ_MssEgressPnControlRegister_HHD +#define AQ_MssEgressSaExpiredStatusRegister_BiggestVersion AQ_MssEgressSaExpiredStatusRegister_HHD +#define AQ_MssEgressSaThresholdExpiredStatusRegister_BiggestVersion AQ_MssEgressSaThresholdExpiredStatusRegister_HHD +#define AQ_MssEgressVlanControlRegister_BiggestVersion AQ_MssEgressVlanControlRegister_HHD +#define AQ_MssEgressVlanTpid_0Register_BiggestVersion AQ_MssEgressVlanTpid_0Register_HHD +#define AQ_MssEgressVlanTpid_1Register_BiggestVersion AQ_MssEgressVlanTpid_1Register_HHD +#define AQ_MssIngressControlRegister_BiggestVersion AQ_MssIngressControlRegister_HHD +#define AQ_MssIngressEccInterruptStatusRegister_BiggestVersion AQ_MssIngressEccInterruptStatusRegister_HHD +#define AQ_MssIngressInterruptMaskRegister_BiggestVersion AQ_MssIngressInterruptMaskRegister_HHD +#define AQ_MssIngressInterruptStatusRegister_BiggestVersion AQ_MssIngressInterruptStatusRegister_HHD +#define AQ_MssIngressLutAddressControlRegister_BiggestVersion AQ_MssIngressLutAddressControlRegister_HHD +#define AQ_MssIngressLutControlRegister_BiggestVersion AQ_MssIngressLutControlRegister_HHD +#define AQ_MssIngressLutDataControlRegister_BiggestVersion AQ_MssIngressLutDataControlRegister_HHD +#define AQ_MssIngressMtuSizeControlRegister_BiggestVersion AQ_MssIngressMtuSizeControlRegister_HHD +#define AQ_MssIngressSaControlRegister_BiggestVersion AQ_MssIngressSaControlRegister_HHD +#define AQ_MssIngressSaExpiredStatusRegister_BiggestVersion AQ_MssIngressSaExpiredStatusRegister_HHD +#define AQ_MssIngressSaIcvErrorStatusRegister_BiggestVersion AQ_MssIngressSaIcvErrorStatusRegister_HHD +#define AQ_MssIngressSaReplayErrorStatusRegister_BiggestVersion AQ_MssIngressSaReplayErrorStatusRegister_HHD +#define AQ_MssIngressSaThresholdExpiredStatusRegister_BiggestVersion AQ_MssIngressSaThresholdExpiredStatusRegister_HHD +#define AQ_MssIngressVlanControlRegister_BiggestVersion AQ_MssIngressVlanControlRegister_HHD +#define AQ_MssIngressVlanTpid_0Register_BiggestVersion AQ_MssIngressVlanTpid_0Register_HHD +#define AQ_MssIngressVlanTpid_1Register_BiggestVersion AQ_MssIngressVlanTpid_1Register_HHD +#define AQ_Pcs10GBaseT_Status_BiggestVersion AQ_Pcs10GBaseT_Status_APPIA +#define AQ_Pcs10G_Status_BiggestVersion AQ_Pcs10G_Status_HHD +#define AQ_Pcs10G_base_rPcsTest_patternControl_BiggestVersion AQ_Pcs10G_base_rPcsTest_patternControl_HHD +#define AQ_Pcs10G_base_rPcsTest_patternErrorCounter_BiggestVersion AQ_Pcs10G_base_rPcsTest_patternErrorCounter_HHD +#define AQ_Pcs10G_base_rTestPatternSeedA_BiggestVersion AQ_Pcs10G_base_rTestPatternSeedA_HHD +#define AQ_Pcs10G_base_rTestPatternSeedB_BiggestVersion AQ_Pcs10G_base_rTestPatternSeedB_HHD +#define AQ_PcsEeeCapabilityRegister_BiggestVersion AQ_PcsEeeCapabilityRegister_HHD +#define AQ_PcsEeeWakeErrorCounter_BiggestVersion AQ_PcsEeeWakeErrorCounter_HHD +#define AQ_PcsReceiveStandardInterruptMask_BiggestVersion AQ_PcsReceiveStandardInterruptMask_APPIA +#define AQ_PcsReceiveVendorAlarms_BiggestVersion AQ_PcsReceiveVendorAlarms_HHD +#define AQ_PcsReceiveVendorCorrectedFrame_1IterationCounter_BiggestVersion AQ_PcsReceiveVendorCorrectedFrame_1IterationCounter_HHD +#define AQ_PcsReceiveVendorCorrectedFrame_2IterationCounter_BiggestVersion AQ_PcsReceiveVendorCorrectedFrame_2IterationCounter_HHD +#define AQ_PcsReceiveVendorCorrectedFrame_3IterationCounter_BiggestVersion AQ_PcsReceiveVendorCorrectedFrame_3IterationCounter_HHD +#define AQ_PcsReceiveVendorCorrectedFrame_4IterationCounter_BiggestVersion AQ_PcsReceiveVendorCorrectedFrame_4IterationCounter_HHD +#define AQ_PcsReceiveVendorCorrectedFrame_5IterationCounter_BiggestVersion AQ_PcsReceiveVendorCorrectedFrame_5IterationCounter_HHD +#define AQ_PcsReceiveVendorCorrectedFrame_6IterationCounter_BiggestVersion AQ_PcsReceiveVendorCorrectedFrame_6IterationCounter_HHD +#define AQ_PcsReceiveVendorCorrectedFrame_7IterationCounter_BiggestVersion AQ_PcsReceiveVendorCorrectedFrame_7IterationCounter_HHD +#define AQ_PcsReceiveVendorCorrectedFrame_8IterationCounter_BiggestVersion AQ_PcsReceiveVendorCorrectedFrame_8IterationCounter_HHD +#define AQ_PcsReceiveVendorCrc_8ErrorCounter_BiggestVersion AQ_PcsReceiveVendorCrc_8ErrorCounter_HHD +#define AQ_PcsReceiveVendorDebug_BiggestVersion AQ_PcsReceiveVendorDebug_HHD +#define AQ_PcsReceiveVendorFcsErrorFrameCounter_BiggestVersion AQ_PcsReceiveVendorFcsErrorFrameCounter_HHD +#define AQ_PcsReceiveVendorFcsNoErrorFrameCounter_BiggestVersion AQ_PcsReceiveVendorFcsNoErrorFrameCounter_HHD +#define AQ_PcsReceiveVendorInterruptMask_BiggestVersion AQ_PcsReceiveVendorInterruptMask_HHD +#define AQ_PcsReceiveVendorProvisioning_BiggestVersion AQ_PcsReceiveVendorProvisioning_HHD +#define AQ_PcsReceiveVendorState_BiggestVersion AQ_PcsReceiveVendorState_HHD +#define AQ_PcsReceiveVendorUncorrectedFrameCounter_BiggestVersion AQ_PcsReceiveVendorUncorrectedFrameCounter_HHD +#define AQ_PcsReceiveXfi0Provisioning_BiggestVersion AQ_PcsReceiveXfi0Provisioning_HHD +#define AQ_PcsReceiveXfi0VendorState_BiggestVersion AQ_PcsReceiveXfi0VendorState_HHD +#define AQ_PcsReceiveXfi1Provisioning_BiggestVersion AQ_PcsReceiveXfi1Provisioning_HHD +#define AQ_PcsReceiveXfi1VendorState_BiggestVersion AQ_PcsReceiveXfi1VendorState_HHD +#define AQ_PcsSerdesMuxSwapTxrxRegister_BiggestVersion AQ_PcsSerdesMuxSwapTxrxRegister_HHD +#define AQ_PcsStandardControl_1_BiggestVersion AQ_PcsStandardControl_1_HHD +#define AQ_PcsStandardControl_2_BiggestVersion AQ_PcsStandardControl_2_HHD +#define AQ_PcsStandardDeviceIdentifier_BiggestVersion AQ_PcsStandardDeviceIdentifier_HHD +#define AQ_PcsStandardDevicesInPackage_BiggestVersion AQ_PcsStandardDevicesInPackage_HHD +#define AQ_PcsStandardInterruptMask_BiggestVersion AQ_PcsStandardInterruptMask_HHD +#define AQ_PcsStandardPackageIdentifier_BiggestVersion AQ_PcsStandardPackageIdentifier_HHD +#define AQ_PcsStandardSpeedAbility_BiggestVersion AQ_PcsStandardSpeedAbility_HHD +#define AQ_PcsStandardStatus_1_BiggestVersion AQ_PcsStandardStatus_1_HHD +#define AQ_PcsStandardStatus_2_BiggestVersion AQ_PcsStandardStatus_2_HHD +#define AQ_PcsTransmitReservedVendorProvisioning_BiggestVersion AQ_PcsTransmitReservedVendorProvisioning_HHD +#define AQ_PcsTransmitVendorAlarms_BiggestVersion AQ_PcsTransmitVendorAlarms_APPIA +#define AQ_PcsTransmitVendorDebug_BiggestVersion AQ_PcsTransmitVendorDebug_HHD +#define AQ_PcsTransmitVendorFcsErrorFrameCounter_BiggestVersion AQ_PcsTransmitVendorFcsErrorFrameCounter_HHD +#define AQ_PcsTransmitVendorFcsNoErrorFrameCounter_BiggestVersion AQ_PcsTransmitVendorFcsNoErrorFrameCounter_HHD +#define AQ_PcsTransmitVendorInterruptMask_BiggestVersion AQ_PcsTransmitVendorInterruptMask_APPIA +#define AQ_PcsTransmitVendorProvisioning_BiggestVersion AQ_PcsTransmitVendorProvisioning_HHD +#define AQ_PcsTransmitXfi0VendorProvisioning_BiggestVersion AQ_PcsTransmitXfi0VendorProvisioning_HHD +#define AQ_PcsTransmitXfi0VendorState_BiggestVersion AQ_PcsTransmitXfi0VendorState_HHD +#define AQ_PcsTransmitXfi1VendorProvisioning_BiggestVersion AQ_PcsTransmitXfi1VendorProvisioning_HHD +#define AQ_PcsTransmitXfi1VendorState_BiggestVersion AQ_PcsTransmitXfi1VendorState_HHD +#define AQ_PcsTransmitXfiVendorProvisioning_BiggestVersion AQ_PcsTransmitXfiVendorProvisioning_HHD +#define AQ_PcsTransmitXgsVendorState_BiggestVersion AQ_PcsTransmitXgsVendorState_HHD +#define AQ_PcsVendorGlobalInterruptFlags_BiggestVersion AQ_PcsVendorGlobalInterruptFlags_HHD +#define AQ_PhyXS_EeeCapabilityRegister_BiggestVersion AQ_PhyXS_EeeCapabilityRegister_HHD +#define AQ_PhyXS_EeeWakeErrorCounter_BiggestVersion AQ_PhyXS_EeeWakeErrorCounter_HHD +#define AQ_PhyXS_Receive_xauiTx_PcsStatus_BiggestVersion AQ_PhyXS_Receive_xauiTx_PcsStatus_HHD +#define AQ_PhyXS_Receive_xauiTx_ReservedVendorProvisioning_BiggestVersion AQ_PhyXS_Receive_xauiTx_ReservedVendorProvisioning_HHD +#define AQ_PhyXS_Receive_xauiTx_VendorAlarms_BiggestVersion AQ_PhyXS_Receive_xauiTx_VendorAlarms_HHD +#define AQ_PhyXS_Receive_xauiTx_VendorDebug_BiggestVersion AQ_PhyXS_Receive_xauiTx_VendorDebug_HHD +#define AQ_PhyXS_Receive_xauiTx_VendorInterruptMask_BiggestVersion AQ_PhyXS_Receive_xauiTx_VendorInterruptMask_HHD +#define AQ_PhyXS_SerdesConfiguration_BiggestVersion AQ_PhyXS_SerdesConfiguration_HHD +#define AQ_PhyXS_SerdesLane_0Configuration_BiggestVersion AQ_PhyXS_SerdesLane_0Configuration_HHD +#define AQ_PhyXS_SerdesLane_1Configuration_BiggestVersion AQ_PhyXS_SerdesLane_1Configuration_HHD +#define AQ_PhyXS_SerdesLane_2Configuration_BiggestVersion AQ_PhyXS_SerdesLane_2Configuration_HHD +#define AQ_PhyXS_SerdesLane_3Configuration_BiggestVersion AQ_PhyXS_SerdesLane_3Configuration_HHD +#define AQ_PhyXS_SerdesLut_BiggestVersion AQ_PhyXS_SerdesLut_HHD +#define AQ_PhyXS_StandardControl_1_BiggestVersion AQ_PhyXS_StandardControl_1_HHD +#define AQ_PhyXS_StandardDeviceIdentifier_BiggestVersion AQ_PhyXS_StandardDeviceIdentifier_HHD +#define AQ_PhyXS_StandardDevicesInPackage_BiggestVersion AQ_PhyXS_StandardDevicesInPackage_HHD +#define AQ_PhyXS_StandardPackageIdentifier_BiggestVersion AQ_PhyXS_StandardPackageIdentifier_HHD +#define AQ_PhyXS_StandardSpeedAbility_BiggestVersion AQ_PhyXS_StandardSpeedAbility_HHD +#define AQ_PhyXS_StandardStatus_1_BiggestVersion AQ_PhyXS_StandardStatus_1_HHD +#define AQ_PhyXS_StandardStatus_2_BiggestVersion AQ_PhyXS_StandardStatus_2_HHD +#define AQ_PhyXS_StandardXGXS_LaneStatus_BiggestVersion AQ_PhyXS_StandardXGXS_LaneStatus_HHD +#define AQ_PhyXS_StandardXGXS_TestControl_BiggestVersion AQ_PhyXS_StandardXGXS_TestControl_HHD +#define AQ_PhyXS_SystemInterfaceConnectionStatus_BiggestVersion AQ_PhyXS_SystemInterfaceConnectionStatus_HHD +#define AQ_PhyXS_Transmit_xauiRx_PcsStatus_BiggestVersion AQ_PhyXS_Transmit_xauiRx_PcsStatus_HHD +#define AQ_PhyXS_Transmit_xauiRx_ReservedVendorProvisioning_BiggestVersion AQ_PhyXS_Transmit_xauiRx_ReservedVendorProvisioning_HHD +#define AQ_PhyXS_Transmit_xauiRx_ReservedVendorState_BiggestVersion AQ_PhyXS_Transmit_xauiRx_ReservedVendorState_HHD +#define AQ_PhyXS_Transmit_xauiRx_StandardInterruptMask_BiggestVersion AQ_PhyXS_Transmit_xauiRx_StandardInterruptMask_HHD +#define AQ_PhyXS_Transmit_xauiRx_TestPatternErrorCounter_BiggestVersion AQ_PhyXS_Transmit_xauiRx_TestPatternErrorCounter_HHD +#define AQ_PhyXS_Transmit_xauiRx_VendorAlarms_BiggestVersion AQ_PhyXS_Transmit_xauiRx_VendorAlarms_HHD +#define AQ_PhyXS_Transmit_xauiRx_VendorDebug_BiggestVersion AQ_PhyXS_Transmit_xauiRx_VendorDebug_HHD +#define AQ_PhyXS_Transmit_xauiRx_VendorInterruptMask_BiggestVersion AQ_PhyXS_Transmit_xauiRx_VendorInterruptMask_HHD +#define AQ_PhyXS_VendorGlobalInterruptFlags_BiggestVersion AQ_PhyXS_VendorGlobalInterruptFlags_HHD +#define AQ_PifMailboxControl_BiggestVersion AQ_PifMailboxControl_HHD +#define AQ_Pma10GBaseT_FastRetrainStatusAndControl_BiggestVersion AQ_Pma10GBaseT_FastRetrainStatusAndControl_HHD +#define AQ_Pma10GBaseT_PairSwapAndPolarityStatus_BiggestVersion AQ_Pma10GBaseT_PairSwapAndPolarityStatus_HHD +#define AQ_Pma10GBaseT_ReceiveSignalPowerChannelA_BiggestVersion AQ_Pma10GBaseT_ReceiveSignalPowerChannelA_HHD +#define AQ_Pma10GBaseT_ReceiveSignalPowerChannelB_BiggestVersion AQ_Pma10GBaseT_ReceiveSignalPowerChannelB_HHD +#define AQ_Pma10GBaseT_ReceiveSignalPowerChannelC_BiggestVersion AQ_Pma10GBaseT_ReceiveSignalPowerChannelC_HHD +#define AQ_Pma10GBaseT_ReceiveSignalPowerChannelD_BiggestVersion AQ_Pma10GBaseT_ReceiveSignalPowerChannelD_HHD +#define AQ_Pma10GBaseT_SNR_MinimumOperatingMarginChannelA_BiggestVersion AQ_Pma10GBaseT_SNR_MinimumOperatingMarginChannelA_HHD +#define AQ_Pma10GBaseT_SNR_MinimumOperatingMarginChannelB_BiggestVersion AQ_Pma10GBaseT_SNR_MinimumOperatingMarginChannelB_HHD +#define AQ_Pma10GBaseT_SNR_MinimumOperatingMarginChannelC_BiggestVersion AQ_Pma10GBaseT_SNR_MinimumOperatingMarginChannelC_HHD +#define AQ_Pma10GBaseT_SNR_MinimumOperatingMarginChannelD_BiggestVersion AQ_Pma10GBaseT_SNR_MinimumOperatingMarginChannelD_HHD +#define AQ_Pma10GBaseT_SNR_OperatingMarginChannelA_BiggestVersion AQ_Pma10GBaseT_SNR_OperatingMarginChannelA_HHD +#define AQ_Pma10GBaseT_SNR_OperatingMarginChannelB_BiggestVersion AQ_Pma10GBaseT_SNR_OperatingMarginChannelB_HHD +#define AQ_Pma10GBaseT_SNR_OperatingMarginChannelC_BiggestVersion AQ_Pma10GBaseT_SNR_OperatingMarginChannelC_HHD +#define AQ_Pma10GBaseT_SNR_OperatingMarginChannelD_BiggestVersion AQ_Pma10GBaseT_SNR_OperatingMarginChannelD_HHD +#define AQ_Pma10GBaseT_SkewDelay_BiggestVersion AQ_Pma10GBaseT_SkewDelay_HHD +#define AQ_Pma10GBaseT_Status_BiggestVersion AQ_Pma10GBaseT_Status_HHD +#define AQ_Pma10GBaseT_TestModes_BiggestVersion AQ_Pma10GBaseT_TestModes_HHD +#define AQ_Pma10GBaseT_TxPowerBackoffAndShortReachSetting_BiggestVersion AQ_Pma10GBaseT_TxPowerBackoffAndShortReachSetting_HHD +#define AQ_PmaReceiveReservedVendorProvisioning_BiggestVersion AQ_PmaReceiveReservedVendorProvisioning_HHD +#define AQ_PmaReceiveReservedVendorState_BiggestVersion AQ_PmaReceiveReservedVendorState_HHD +#define AQ_PmaReceiveVendorState_BiggestVersion AQ_PmaReceiveVendorState_HHD +#define AQ_PmaStandardControl_1_BiggestVersion AQ_PmaStandardControl_1_HHD +#define AQ_PmaStandardControl_2_BiggestVersion AQ_PmaStandardControl_2_HHD +#define AQ_PmaStandardDeviceIdentifier_BiggestVersion AQ_PmaStandardDeviceIdentifier_HHD +#define AQ_PmaStandardDevicesInPackage_BiggestVersion AQ_PmaStandardDevicesInPackage_HHD +#define AQ_PmaStandardPackageIdentifier_BiggestVersion AQ_PmaStandardPackageIdentifier_HHD +#define AQ_PmaStandardSpeedAbility_BiggestVersion AQ_PmaStandardSpeedAbility_HHD +#define AQ_PmaStandardStatus_1_BiggestVersion AQ_PmaStandardStatus_1_HHD +#define AQ_PmaStandardStatus_2_BiggestVersion AQ_PmaStandardStatus_2_HHD +#define AQ_PmaTransmitReservedVendorProvisioning_BiggestVersion AQ_PmaTransmitReservedVendorProvisioning_HHD +#define AQ_PmaTransmitStandardInterruptMask_BiggestVersion AQ_PmaTransmitStandardInterruptMask_HHD +#define AQ_PmaTransmitVendorAlarms_BiggestVersion AQ_PmaTransmitVendorAlarms_HHD +#define AQ_PmaTransmitVendorDebug_BiggestVersion AQ_PmaTransmitVendorDebug_HHD +#define AQ_PmaTransmitVendorLASI_InterruptMask_BiggestVersion AQ_PmaTransmitVendorLASI_InterruptMask_HHD +#define AQ_PmaVendorGlobalInterruptFlags_BiggestVersion AQ_PmaVendorGlobalInterruptFlags_HHD +#define AQ_PmdStandard10G_ExtendedAbilityRegister_BiggestVersion AQ_PmdStandard10G_ExtendedAbilityRegister_HHD +#define AQ_PmdStandardSignalDetect_BiggestVersion AQ_PmdStandardSignalDetect_HHD +#define AQ_PmdStandardTransmitDisableControl_BiggestVersion AQ_PmdStandardTransmitDisableControl_HHD +#define AQ_Sgmii0WolStatus_BiggestVersion AQ_Sgmii0WolStatus_HHD +#define AQ_TimesyncPcsCapability_BiggestVersion AQ_TimesyncPcsCapability_HHD +#define AQ_TimesyncPcsReceivePathDataDelay_BiggestVersion AQ_TimesyncPcsReceivePathDataDelay_HHD +#define AQ_TimesyncPcsTransmitPathDataDelay_BiggestVersion AQ_TimesyncPcsTransmitPathDataDelay_HHD +#define AQ_TimesyncPhyXsCapability_BiggestVersion AQ_TimesyncPhyXsCapability_HHD +#define AQ_TimesyncPhyXsReceivePathDataDelay_BiggestVersion AQ_TimesyncPhyXsReceivePathDataDelay_HHD +#define AQ_TimesyncPhyXsTransmitPathDataDelay_BiggestVersion AQ_TimesyncPhyXsTransmitPathDataDelay_HHD +#define AQ_TimesyncPmaCapability_BiggestVersion AQ_TimesyncPmaCapability_HHD +#define AQ_TimesyncPmaReceivePathDataDelay_BiggestVersion AQ_TimesyncPmaReceivePathDataDelay_HHD +#define AQ_TimesyncPmaTransmitPathDataDelay_BiggestVersion AQ_TimesyncPmaTransmitPathDataDelay_HHD +#define AQ_XenpakBasic_ApsLoading_BiggestVersion AQ_XenpakBasic_ApsLoading_HHD +#define AQ_XenpakBasic_ApsVoltage_BiggestVersion AQ_XenpakBasic_ApsVoltage_HHD +#define AQ_XenpakBasic_BitRate_BiggestVersion AQ_XenpakBasic_BitRate_HHD +#define AQ_XenpakBasic_Checksum_BiggestVersion AQ_XenpakBasic_Checksum_HHD +#define AQ_XenpakBasic_ConnectorType_BiggestVersion AQ_XenpakBasic_ConnectorType_HHD +#define AQ_XenpakBasic_DomCapability_BiggestVersion AQ_XenpakBasic_DomCapability_HHD +#define AQ_XenpakBasic_Encoding_BiggestVersion AQ_XenpakBasic_Encoding_HHD +#define AQ_XenpakBasic_Low_powerStartupCapability_BiggestVersion AQ_XenpakBasic_Low_powerStartupCapability_HHD +#define AQ_XenpakBasic_PackageIdentifier_BiggestVersion AQ_XenpakBasic_PackageIdentifier_HHD +#define AQ_XenpakBasic_Protocol_BiggestVersion AQ_XenpakBasic_Protocol_HHD +#define AQ_XenpakBasic_Reserved_0x11_BiggestVersion AQ_XenpakBasic_Reserved_0x11_HHD +#define AQ_XenpakBasic_Reserved_0x19_BiggestVersion AQ_XenpakBasic_Reserved_0x19_HHD +#define AQ_XenpakBasic_Reserved_0x7c_BiggestVersion AQ_XenpakBasic_Reserved_0x7c_HHD +#define AQ_XenpakBasic_StandardsComplianceCodes_BiggestVersion AQ_XenpakBasic_StandardsComplianceCodes_HHD +#define AQ_XenpakBasic_TransceiverType_BiggestVersion AQ_XenpakBasic_TransceiverType_HHD +#define AQ_XenpakBasic_VendorDateCode_BiggestVersion AQ_XenpakBasic_VendorDateCode_HHD +#define AQ_XenpakBasic_VendorIdentifier_BiggestVersion AQ_XenpakBasic_VendorIdentifier_HHD +#define AQ_XenpakBasic_VendorName_BiggestVersion AQ_XenpakBasic_VendorName_HHD +#define AQ_XenpakBasic_VendorPartNumber_BiggestVersion AQ_XenpakBasic_VendorPartNumber_HHD +#define AQ_XenpakBasic_VendorPartRevisionNumber_BiggestVersion AQ_XenpakBasic_VendorPartRevisionNumber_HHD +#define AQ_XenpakBasic_VendorSerialNumber_BiggestVersion AQ_XenpakBasic_VendorSerialNumber_HHD +#define AQ_XenpakBasic__3_3vLoading_BiggestVersion AQ_XenpakBasic__3_3vLoading_HHD +#define AQ_XenpakBasic__5vLoading_BiggestVersion AQ_XenpakBasic__5vLoading_HHD +#define AQ_XenpakControl_BiggestVersion AQ_XenpakControl_HHD +#define AQ_XenpakCustomer_Reserved_0x7e_BiggestVersion AQ_XenpakCustomer_Reserved_0x7e_HHD +#define AQ_XenpakDom_Alarms_BiggestVersion AQ_XenpakDom_Alarms_HHD +#define AQ_XenpakDom_Capability_BiggestVersion AQ_XenpakDom_Capability_HHD +#define AQ_XenpakDom_ControlAndStatus_BiggestVersion AQ_XenpakDom_ControlAndStatus_HHD +#define AQ_XenpakDom_HighTemperatureAlarmThresholdLSW_BiggestVersion AQ_XenpakDom_HighTemperatureAlarmThresholdLSW_HHD +#define AQ_XenpakDom_HighTemperatureAlarmThresholdMSW_BiggestVersion AQ_XenpakDom_HighTemperatureAlarmThresholdMSW_HHD +#define AQ_XenpakDom_HighTemperatureWarningThresholdLSW_BiggestVersion AQ_XenpakDom_HighTemperatureWarningThresholdLSW_HHD +#define AQ_XenpakDom_HighTemperatureWarningThresholdMSW_BiggestVersion AQ_XenpakDom_HighTemperatureWarningThresholdMSW_HHD +#define AQ_XenpakDom_LowTemperatureAlarmThresholdLSW_BiggestVersion AQ_XenpakDom_LowTemperatureAlarmThresholdLSW_HHD +#define AQ_XenpakDom_LowTemperatureAlarmThresholdMSW_BiggestVersion AQ_XenpakDom_LowTemperatureAlarmThresholdMSW_HHD +#define AQ_XenpakDom_LowTemperatureWarningThresholdLSW_BiggestVersion AQ_XenpakDom_LowTemperatureWarningThresholdLSW_HHD +#define AQ_XenpakDom_LowTemperatureWarningThresholdMSW_BiggestVersion AQ_XenpakDom_LowTemperatureWarningThresholdMSW_HHD +#define AQ_XenpakDom_Status_BiggestVersion AQ_XenpakDom_Status_HHD +#define AQ_XenpakDom_TemperatureLSW_BiggestVersion AQ_XenpakDom_TemperatureLSW_HHD +#define AQ_XenpakDom_TemperatureMSW_BiggestVersion AQ_XenpakDom_TemperatureMSW_HHD +#define AQ_XenpakDom_TxControl_BiggestVersion AQ_XenpakDom_TxControl_HHD +#define AQ_XenpakHeader_BasicMemoryStartAddress_BiggestVersion AQ_XenpakHeader_BasicMemoryStartAddress_HHD +#define AQ_XenpakHeader_CustomerMemoryOffset_BiggestVersion AQ_XenpakHeader_CustomerMemoryOffset_HHD +#define AQ_XenpakHeader_ExtendedVendorMemoryOffset_BiggestVersion AQ_XenpakHeader_ExtendedVendorMemoryOffset_HHD +#define AQ_XenpakHeader_MemoryUsed_BiggestVersion AQ_XenpakHeader_MemoryUsed_HHD +#define AQ_XenpakHeader_NvrSize_BiggestVersion AQ_XenpakHeader_NvrSize_HHD +#define AQ_XenpakHeader_VendorMemoryStartAddress_BiggestVersion AQ_XenpakHeader_VendorMemoryStartAddress_HHD +#define AQ_XenpakHeader_XenpakMsaVersionSupported_BiggestVersion AQ_XenpakHeader_XenpakMsaVersionSupported_HHD +#define AQ_XenpakLASI__Control_BiggestVersion AQ_XenpakLASI__Control_HHD +#define AQ_XenpakLASI__Status_BiggestVersion AQ_XenpakLASI__Status_HHD +#define AQ_XenpakRxAlarm_Control_BiggestVersion AQ_XenpakRxAlarm_Control_HHD +#define AQ_XenpakRxAlarm_Status_BiggestVersion AQ_XenpakRxAlarm_Status_HHD +#define AQ_XenpakTxAlarm_Control_BiggestVersion AQ_XenpakTxAlarm_Control_HHD +#define AQ_XenpakTxAlarm_Status_BiggestVersion AQ_XenpakTxAlarm_Status_HHD +#define AQ_XenpakVendor_Reserved_0xae_BiggestVersion AQ_XenpakVendor_Reserved_0xae_HHD + +#endif diff --git a/qca/aq-fw-download/src/include/registerMap/AQ_RegMaps.h b/qca/aq-fw-download/src/include/registerMap/AQ_RegMaps.h new file mode 100644 index 000000000..52a24e385 --- /dev/null +++ b/qca/aq-fw-download/src/include/registerMap/AQ_RegMaps.h @@ -0,0 +1,69 @@ +/*AQ_RegMaps.h*/ + +/************************************************************************************ +* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +* +* Description: +* +* This file contains includes all appropriate Aquantia PHY device-specific +* register map headers. +* +************************************************************************************/ + +/*! \file +* This file contains includes all appropriate Aquantia PHY device-specific +* register map headers. + */ + +#ifndef AQ_REGISTERMAPS_HEADER +#define AQ_REGISTERMAPS_HEADER + +#include "AQ_User.h" +#include "AQ_RegGroupMaxSizes.h" + + +#ifndef AQ_REVERSED_BITFIELD_ORDERING +/* + * Include non-reversed header files (bitfields ordered from LSbit to MSbit) + */ + +/* APPIA */ +#include "AQ_APPIA_Global_registers.h" + +#include "AQ_APPIA_Global_registers_Defines.h" + +/* HHD */ +#include "AQ_HHD_Global_registers.h" + +#include "AQ_HHD_Global_registers_Defines.h" + +#else +/* + * Include reversed header files (bitfields ordered from MSbit to LSbit) + */ + +/* APPIA */ +#include "AQ_APPIA_Global_registers_reversed.h" + +#include "AQ_APPIA_Global_registers_Defines.h" + +/* HHD */ +#include "AQ_HHD_Global_registers_reversed.h" + +#include "AQ_HHD_Global_registers_Defines.h" + +#endif + +#endif diff --git a/qca/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers.h b/qca/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers.h new file mode 100644 index 000000000..e0a2fa27b --- /dev/null +++ b/qca/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers.h @@ -0,0 +1,12123 @@ +/*! \file +* This file contains the data structures and doxygen comments +* for the Global Registers block. + */ + +/*! \addtogroup registerMap + @{ +*/ + +/*! \defgroup Global_registers Global Registers +* This module contains the data structures and doxygen comments +* for the Global Registers block. + */ +/*********************************************************************** +* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +* +* $Date: 2014/04/08 $ +* +* $Label: $ +* +* Description: +* +* This file contains the c header structures for the registers contained in the Global Registers block. +* +* The bit fields in this structure are from LSbit to MSbit +* +***********************************************************************/ + + +/*@{*/ +#ifndef AQ_HHD_GLOBAL_REGS_HEADER +#define AQ_HHD_GLOBAL_REGS_HEADER + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Control 1: 1E.0000 */ +/* Global Standard Control 1: 1E.0000 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Control 1 */ + union + { + struct + { + unsigned int reserved1 : 11; + /*! \brief 1E.0000.B R/WPD Low Power + AQ_GlobalStandardControl_1_HHD.u0.bits_0.lowPower + + Provisionable Default = 0x0 + + 1 = Low-power mode + 0 = Normal operation + + + Notes: + A one written to this register causes the chip to enter low-power mode. This bit puts the entire chip in low-power mode, with only the MDIO and microprocessor functioning, and turns off the analog front-end: i.e. places it in high-impedance mode. Setting this bit also sets all of the Low Power bits in the other MMDs. */ + unsigned int lowPower : 1; /* 1E.0000.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Low-power mode + 0 = Normal operation + */ + unsigned int reserved0 : 3; + /*! \brief 1E.0000.F R/WSC Soft Reset + AQ_GlobalStandardControl_1_HHD.u0.bits_0.softReset + + Default = 0x1 + + 1 = Global soft reset + 0 = Normal operation + + + Notes: + Resets the entire PHY. + Setting this bit initiates a global soft reset on all of the digital logic not including the microprocessor (i.e. microprocessor is not reset). Upon completion of the reset sequence, this bit is set back to 0by the microprocessor. Note this bit is OR'ed with the individual MMD resets. This bit should be set to 0 before setting the individual MMD resets. */ + unsigned int softReset : 1; /* 1E.0000.F R/WSC Default = 0x1 */ + /* 1 = Global soft reset + 0 = Normal operation + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardControl_1_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Device Identifier: 1E.0002 */ +/* Global Standard Device Identifier: 1E.0002 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Device Identifier */ + union + { + struct + { + /*! \brief 1E.0002.F:0 RO Device ID MSW [1F:10] + AQ_GlobalStandardDeviceIdentifier_HHD.u0.bits_0.deviceIdMSW + + + + Bits 31 - 16 of Device ID + */ + unsigned int deviceIdMSW : 16; /* 1E.0002.F:0 RO */ + /* Bits 31 - 16 of Device ID */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Standard Device Identifier */ + union + { + struct + { + /*! \brief 1E.0003.F:0 RO Device ID LSW [F:0] + AQ_GlobalStandardDeviceIdentifier_HHD.u1.bits_1.deviceIdLSW + + + + Bits 15 - 0 of Device ID + */ + unsigned int deviceIdLSW : 16; /* 1E.0003.F:0 RO */ + /* Bits 15 - 0 of Device ID */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalStandardDeviceIdentifier_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Devices in Package: 1E.0005 */ +/* Global Standard Devices in Package: 1E.0005 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Devices in Package */ + union + { + struct + { + /*! \brief 1E.0005.0 ROS Clause 22 Registers Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.clause_22RegistersPresent + + Default = 0x0 + + 1 = Clause 22 registers are present in package + 0 = Clause 22 registers are not present in package + + Notes: + This is always set to 0 in the PHY, as there are no Clause 22 registers in the device. */ + unsigned int clause_22RegistersPresent : 1; /* 1E.0005.0 ROS Default = 0x0 */ + /* 1 = Clause 22 registers are present in package + 0 = Clause 22 registers are not present in package */ + /*! \brief 1E.0005.1 ROS PMA Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.pmaPresent + + Default = 0x1 + + 1 = PMA is present in package + 0 = PMA is not present + + Notes: + This is always set to 1 as there is PMA functionality in the PHY. */ + unsigned int pmaPresent : 1; /* 1E.0005.1 ROS Default = 0x1 */ + /* 1 = PMA is present in package + 0 = PMA is not present */ + /*! \brief 1E.0005.2 ROS WIS Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.wisPresent + + Default = 0x0 + + 1 = WIS is present in package + 0 = WIS is not present in package + + Notes: + This is always set to 0, as there is no WIS functionality in the PHY. */ + unsigned int wisPresent : 1; /* 1E.0005.2 ROS Default = 0x0 */ + /* 1 = WIS is present in package + 0 = WIS is not present in package */ + /*! \brief 1E.0005.3 ROS PCS Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.pcsPresent + + Default = 0x1 + + 1 = PCS is present in package + 0 = PCS is not present in package + + Notes: + This is always set to 1 as there is PCS functionality in the PHY. */ + unsigned int pcsPresent : 1; /* 1E.0005.3 ROS Default = 0x1 */ + /* 1 = PCS is present in package + 0 = PCS is not present in package */ + /*! \brief 1E.0005.4 ROS PHY XS Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.phyXS_Present + + Default = 0x1 + + 1 = PHY XS is present in package + 0 = PHY XS is not present in package + + Notes: + This is always set to 1 as there is a PHY XS interface in the PHY. */ + unsigned int phyXS_Present : 1; /* 1E.0005.4 ROS Default = 0x1 */ + /* 1 = PHY XS is present in package + 0 = PHY XS is not present in package */ + /*! \brief 1E.0005.5 ROS DTE XS Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.dteXsPresent + + Default = 0x0 + + 1 = DTE XS is present in package + 0 = DTE XS is not present in package + + + Notes: + This is always set to 0, as there is no DTE XAUI interface in the PHY. */ + unsigned int dteXsPresent : 1; /* 1E.0005.5 ROS Default = 0x0 */ + /* 1 = DTE XS is present in package + 0 = DTE XS is not present in package + */ + /*! \brief 1E.0005.6 ROS TC Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.tcPresent + + Default = 0x0 + + 1 = TC is present in package + 0 = TC is not present in package + + Notes: + This is always set to 0, as there is no TC functionality in the PHY. */ + unsigned int tcPresent : 1; /* 1E.0005.6 ROS Default = 0x0 */ + /* 1 = TC is present in package + 0 = TC is not present in package */ + /*! \brief 1E.0005.7 ROS Autonegotiation Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.autonegotiationPresent + + Default = 0x1 + + 1 = Autonegotiation is present in package + 0 = Autonegotiation is not present in package + + Notes: + This is always set to 1, as there is Autonegotiation in the PHY. */ + unsigned int autonegotiationPresent : 1; /* 1E.0005.7 ROS Default = 0x1 */ + /* 1 = Autonegotiation is present in package + 0 = Autonegotiation is not present in package */ + unsigned int reserved0 : 8; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardDevicesInPackage_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Vendor Devices in Package: 1E.0006 */ +/* Global Standard Vendor Devices in Package: 1E.0006 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Vendor Devices in Package */ + union + { + struct + { + unsigned int reserved0 : 13; + /*! \brief 1E.0006.D ROS Clause 22 Extension Present + AQ_GlobalStandardVendorDevicesInPackage_HHD.u0.bits_0.clause_22ExtensionPresent + + Default = 0x1 + + 1 = Clause 22 Extension is present in package + 0 = Clause 22 Extension is not present in package + + Notes: + This is always set to 1 as the PHY utilizes this device for the GbE registers. */ + unsigned int clause_22ExtensionPresent : 1; /* 1E.0006.D ROS Default = 0x1 */ + /* 1 = Clause 22 Extension is present in package + 0 = Clause 22 Extension is not present in package */ + /*! \brief 1E.0006.E ROS Vendor Specific Device #1 Present + AQ_GlobalStandardVendorDevicesInPackage_HHD.u0.bits_0.vendorSpecificDevice_1Present + + Default = 0x1 + + 1 = Device #1 is present in package + 0 = Device #1 is not present in package + + Notes: + This is always set to 1 as the PHY utilizes this device for the global control registers. */ + unsigned int vendorSpecificDevice_1Present : 1; /* 1E.0006.E ROS Default = 0x1 */ + /* 1 = Device #1 is present in package + 0 = Device #1 is not present in package */ + /*! \brief 1E.0006.F ROS Vendor Specific Device #2 Present + AQ_GlobalStandardVendorDevicesInPackage_HHD.u0.bits_0.vendorSpecificDevice_2Present + + Default = 0x1 + + 1 = Device #2 is present in package + 0 = Device #2 is not present in package + + Notes: + This is always set to 1 as the PHY utilizes this device for the DSP PMA registers. */ + unsigned int vendorSpecificDevice_2Present : 1; /* 1E.0006.F ROS Default = 0x1 */ + /* 1 = Device #2 is present in package + 0 = Device #2 is not present in package */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardVendorDevicesInPackage_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Status 2: 1E.0008 */ +/* Global Standard Status 2: 1E.0008 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Status 2 */ + union + { + struct + { + unsigned int reserved0 : 14; + /*! \brief 1E.0008.F:E ROS Device Present [1:0] + AQ_GlobalStandardStatus_2_HHD.u0.bits_0.devicePresent + + Default = 0x2 + + [F:E] + 0x3 = No device at this address + 0x2 = Device present at this address + 0x1 = No device at this address + 0x0 = No device at this address + + Notes: + This field is always set to 0x2, as the Global MMD resides here in the PHY. */ + unsigned int devicePresent : 2; /* 1E.0008.F:E ROS Default = 0x2 */ + /* [F:E] + 0x3 = No device at this address + 0x2 = Device present at this address + 0x1 = No device at this address + 0x0 = No device at this address */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardStatus_2_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Package Identifier: 1E.000E */ +/* Global Standard Package Identifier: 1E.000E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Package Identifier */ + union + { + struct + { + /*! \brief 1E.000E.F:0 RO Package ID MSW [1F:10] + AQ_GlobalStandardPackageIdentifier_HHD.u0.bits_0.packageIdMSW + + + + Bits 31- 16 of Package ID + */ + unsigned int packageIdMSW : 16; /* 1E.000E.F:0 RO */ + /* Bits 31- 16 of Package ID */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Standard Package Identifier */ + union + { + struct + { + /*! \brief 1E.000F.F:0 RO Package ID LSW [F:0] + AQ_GlobalStandardPackageIdentifier_HHD.u1.bits_1.packageIdLSW + + + + Bits 15 - 0 of Package ID + */ + unsigned int packageIdLSW : 16; /* 1E.000F.F:0 RO */ + /* Bits 15 - 0 of Package ID */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalStandardPackageIdentifier_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Firmware ID: 1E.0020 */ +/* Global Firmware ID: 1E.0020 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Firmware ID */ + union + { + struct + { + /*! \brief 1E.0020.7:0 RO Firmware Minor Revision Number [7:0] + AQ_GlobalFirmwareID_HHD.u0.bits_0.firmwareMinorRevisionNumber + + + + [7:0] = Minor revision number + + Notes: + + + The lower six bits of major and minor firmware revision are exchanged in autonegotiation when the PHYID message is sent. */ + unsigned int firmwareMinorRevisionNumber : 8; /* 1E.0020.7:0 RO */ + /* [7:0] = Minor revision number */ + /*! \brief 1E.0020.F:8 RO Firmware Major Revision Number [7:0] + AQ_GlobalFirmwareID_HHD.u0.bits_0.firmwareMajorRevisionNumber + + + + [F:8] = Major revision number + + Notes: + + + The lower six bits of major and minor firmware revision are exchanged in autonegotiation when the PHYID message is sent. */ + unsigned int firmwareMajorRevisionNumber : 8; /* 1E.0020.F:8 RO */ + /* [F:8] = Major revision number */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalFirmwareID_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global NVR Interface: 1E.0100 */ +/* Global NVR Interface: 1E.0100 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0100.7:0 R/W NVR Opcode [7:0] + AQ_GlobalNvrInterface_HHD.u0.bits_0.nvrOpcode + + Default = 0x03 + + NVR instruction opcode + + */ + unsigned int nvrOpcode : 8; /* 1E.0100.7:0 R/W Default = 0x03 */ + /* NVR instruction opcode + */ + /*! \brief 1E.0100.8 RO NVR Busy + AQ_GlobalNvrInterface_HHD.u0.bits_0.nvrBusy + + + + 1 = NVR is busy + 0 = NVR is ready + + + Notes: + When set to 1, the NVR is busy. A new NVR operation should not occur until this bit is 0. If the NVR clock is greater than 64/63 of the MDIO clock, this bit never needs to be polled when operating over the MDIO. */ + unsigned int nvrBusy : 1; /* 1E.0100.8 RO */ + /* 1 = NVR is busy + 0 = NVR is ready + */ + unsigned int reserved1 : 1; + /*! \brief 1E.0100.A R/W NVR Burst + AQ_GlobalNvrInterface_HHD.u0.bits_0.nvrBurst + + Default = 0x0 + + 0 = Single read or write operation of up to 4 bytes + 1 = Burst operation + + + Notes: + When this bit is set, the operation is a burst operation where more than 32-bits is read from the NVR or written to the NVR. This bit should be set to one until the last burst in the read or write operation, when it should be set to zero. It operates by gating the SPI clock, and not restarting it until new data is ready to be written, or the previous contents have been read. Each burst of data requires the NVR Execute Operation bit to be set to initiate the next phase. */ + unsigned int nvrBurst : 1; /* 1E.0100.A R/W Default = 0x0 */ + /* 0 = Single read or write operation of up to 4 bytes + 1 = Burst operation + */ + unsigned int reserved0 : 1; + /*! \brief 1E.0100.C R/WSC Reset NVR CRC + AQ_GlobalNvrInterface_HHD.u0.bits_0.resetNvrCrc + + Default = 0x0 + + 1 = Reset NVR Mailbox CRC calculation register + + + + Notes: + To prevent an erroneous answer, this bit should not be set at the same time the See NVR Operation Valid bit is set. */ + unsigned int resetNvrCrc : 1; /* 1E.0100.C R/WSC Default = 0x0 */ + /* 1 = Reset NVR Mailbox CRC calculation register + + */ + /*! \brief 1E.0100.D R/W Freeze NVR CRC + AQ_GlobalNvrInterface_HHD.u0.bits_0.freezeNvrCrc + + Default = 0x0 + + 1 = Freeze NVR Mailbox CRC calculation register + + + Notes: + To prevent an erroneous answer, this bit should not be set at the same time the See NVR Operation Valid bit is set. */ + unsigned int freezeNvrCrc : 1; /* 1E.0100.D R/W Default = 0x0 */ + /* 1 = Freeze NVR Mailbox CRC calculation register + */ + /*! \brief 1E.0100.E R/W NVR Write Mode + AQ_GlobalNvrInterface_HHD.u0.bits_0.nvrWriteMode + + Default = 0x0 + + 1 = Write to NVR + 0 = Read from NVR + + */ + unsigned int nvrWriteMode : 1; /* 1E.0100.E R/W Default = 0x0 */ + /* 1 = Write to NVR + 0 = Read from NVR + */ + /*! \brief 1E.0100.F R/WSC NVR Execute Operation + AQ_GlobalNvrInterface_HHD.u0.bits_0.nvrExecuteOperation + + Default = 0x0 + + 1 = Start NVR Operation + + + + Notes: + When set to 1, the NVR operation will begin. Ensure that the uP is stalled using the See MCP Run Stall bit to ensure no NVR contention. */ + unsigned int nvrExecuteOperation : 1; /* 1E.0100.F R/WSC Default = 0x0 */ + /* 1 = Start NVR Operation + + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0101.F:0 RO NVR Mailbox CRC [F:0] + AQ_GlobalNvrInterface_HHD.u1.bits_1.nvrMailboxCrc + + + + The running CRC-16 of everything passing through the NVR interface + + + Notes: + The CRC-16 over all data written or read through the NVR interface. The CRC-16 is calculated by dividing the data by: + x^16 + x^12 + x^5 + 1 */ + unsigned int nvrMailboxCrc : 16; /* 1E.0101.F:0 RO */ + /* The running CRC-16 of everything passing through the NVR interface + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0102.7:0 R/W NVR Address MSW [17:10] + AQ_GlobalNvrInterface_HHD.u2.bits_2.nvrAddressMSW + + Default = 0x00 + + NVR address MSW bits [17:10] + + + Notes: + The address of where to read and write from in the NVR. This is self-incrementing and will automatically increment after each read or write operation. The increment amount is based on the data length (i.e. increments by 4 if the data length is 4 bytes) */ + unsigned int nvrAddressMSW : 8; /* 1E.0102.7:0 R/W Default = 0x00 */ + /* NVR address MSW bits [17:10] + */ + unsigned int reserved0 : 8; + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0103.F:0 R/W NVR Address LSW [F:0] + AQ_GlobalNvrInterface_HHD.u3.bits_3.nvrAddressLSW + + Default = 0x0000 + + NVR address LSW bits [F:0] + + + Notes: + The address of where to read and write from in the NVR. This is self-incrementing and will automatically increment after each read or write operation. */ + unsigned int nvrAddressLSW : 16; /* 1E.0103.F:0 R/W Default = 0x0000 */ + /* NVR address LSW bits [F:0] + */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0104.F:0 R/W NVR Data MSW [1F:10] + AQ_GlobalNvrInterface_HHD.u4.bits_4.nvrDataMSW + + Default = 0x0000 + + NVR data MSW bits [1F:10] + + + Notes: + Data is stored and read-out from these registers in little-endian format for operations such as FLASH device ID, and for programming the processor. + + For instance the 64K Atmel device code reads out as two bytes 0x651F into the LSW register, whereas the datasheet indicates that 1F is the first byte read, followed by 65 as the second byte. + + To burst read and write these 4 bytes in the correct order (where DD is written to address x), they should be stored as: + + AA BB in the MSW + CC DD in the LSW. */ + unsigned int nvrDataMSW : 16; /* 1E.0104.F:0 R/W Default = 0x0000 */ + /* NVR data MSW bits [1F:10] + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0105.F:0 R/W NVR Data LSW [F:0] + AQ_GlobalNvrInterface_HHD.u5.bits_5.nvrDataLSW + + Default = 0x0000 + + NVR data LSW bits [F:0] + + + Notes: + Data is stored and read-out from these registers in little-endian format for operations such as FLASH device ID, and for programming the processor. + + For instance the 64K Atmel device code reads out as two bytes 0x651F into the LSW register, whereas the datasheet indicates that 1F is the first byte read, followed by 65 as the second byte. + To burst read and write these 4 bytes in the correct order (where DD is written to address x), they should be stored as: + + AA BB in the MSW + CC DD in the LSW. */ + unsigned int nvrDataLSW : 16; /* 1E.0105.F:0 R/W Default = 0x0000 */ + /* NVR data LSW bits [F:0] + */ + } bits_5; + uint16_t word_5; + } u5; +} AQ_GlobalNvrInterface_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Mailbox Interface: 1E.0200 */ +/* Global Mailbox Interface: 1E.0200 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Mailbox Interface */ + union + { + struct + { + unsigned int reserved2 : 8; + /*! \brief 1E.0200.8 RO uP Mailbox Busy + AQ_GlobalMailboxInterface_HHD.u0.bits_0.upMailboxBusy + + + + 1 = uP mailbox busy + 0 = uP mailbox ready + + + Notes: + In general the uP will respond within a few processor cycles to any PIF slave request, much faster than the MDIO. If the busy is asserted over multiple MDIO polling cycles, then a H/W error may have occurred and a Global S/W reset or uP reset is required. */ + unsigned int upMailboxBusy : 1; /* 1E.0200.8 RO */ + /* 1 = uP mailbox busy + 0 = uP mailbox ready + */ + unsigned int reserved1 : 3; + /*! \brief 1E.0200.C R/WSC Reset uP Mailbox CRC + AQ_GlobalMailboxInterface_HHD.u0.bits_0.resetUpMailboxCrc + + Default = 0x0 + + 1 = Reset uP mailbox CRC calculation register + + + */ + unsigned int resetUpMailboxCrc : 1; /* 1E.0200.C R/WSC Default = 0x0 */ + /* 1 = Reset uP mailbox CRC calculation register + + */ + unsigned int reserved0 : 1; + /*! \brief 1E.0200.E R/W uP Mailbox Write Mode + AQ_GlobalMailboxInterface_HHD.u0.bits_0.upMailboxWriteMode + + Default = 0x0 + + 1 = Write + 0 = Read + + + Notes: + Mailbox direction */ + unsigned int upMailboxWriteMode : 1; /* 1E.0200.E R/W Default = 0x0 */ + /* 1 = Write + 0 = Read + */ + /*! \brief 1E.0200.F R/WSC uP Mailbox Execute Operation + AQ_GlobalMailboxInterface_HHD.u0.bits_0.upMailboxExecuteOperation + + Default = 0x0 + + 1 = Start of mailbox Operation + + + + Notes: + Indicates mailbox is loaded and ready */ + unsigned int upMailboxExecuteOperation : 1; /* 1E.0200.F R/WSC Default = 0x0 */ + /* 1 = Start of mailbox Operation + + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0201.F:0 RO uP Mailbox CRC [F:0] + AQ_GlobalMailboxInterface_HHD.u1.bits_1.upMailboxCrc + + + + The running CRC-16 of everything passing through the mailbox interface + + */ + unsigned int upMailboxCrc : 16; /* 1E.0201.F:0 RO */ + /* The running CRC-16 of everything passing through the mailbox interface + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0202.F:0 R/W uP Mailbox Address MSW [1F:10] + AQ_GlobalMailboxInterface_HHD.u2.bits_2.upMailboxAddressMSW + + Default = 0x0000 + + uP Mailbox MSW address + + + Notes: + The address of where to read and write from in the Microcontroller Mailbox. This is self-incrementing and automatically increments after each read and write operation.PHY */ + unsigned int upMailboxAddressMSW : 16; /* 1E.0202.F:0 R/W Default = 0x0000 */ + /* uP Mailbox MSW address + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0203.1:0 RO uP Mailbox Address LSW Don't Care [1:0] + AQ_GlobalMailboxInterface_HHD.u3.bits_3.upMailboxAddressLSW_Don_tCare + + + + Least significant uP LSW Mailbox address bits [1:0] + + + Notes: + These bits are always set to 0 since each memory access is on a 4-byte boundary. */ + unsigned int upMailboxAddressLSW_Don_tCare : 2; /* 1E.0203.1:0 RO */ + /* Least significant uP LSW Mailbox address bits [1:0] + */ + /*! \brief 1E.0203.F:2 R/W uP Mailbox Address LSW [F:2] + AQ_GlobalMailboxInterface_HHD.u3.bits_3.upMailboxAddressLSW + + Default = 0x0000 + + uP LSW Mailbox address [F:2] + + + Notes: + The address of where to read and write from in the Microcontroller Mailbox. This is self-incrementing and automatically increments after each read and write operation.PHY */ + unsigned int upMailboxAddressLSW : 14; /* 1E.0203.F:2 R/W Default = 0x0000 */ + /* uP LSW Mailbox address [F:2] + */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0204.F:0 R/W uP Mailbox Data MSW [1F:10] + AQ_GlobalMailboxInterface_HHD.u4.bits_4.upMailboxDataMSW + + Default = 0x0000 + + uP Mailbox data MSW + + */ + unsigned int upMailboxDataMSW : 16; /* 1E.0204.F:0 R/W Default = 0x0000 */ + /* uP Mailbox data MSW + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0205.F:0 R/W uP Mailbox Data LSW [F:0] + AQ_GlobalMailboxInterface_HHD.u5.bits_5.upMailboxDataLSW + + Default = 0x0000 + + uP Mailbox data LSW + + */ + unsigned int upMailboxDataLSW : 16; /* 1E.0205.F:0 R/W Default = 0x0000 */ + /* uP Mailbox data LSW + */ + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of Global Mailbox Interface */ + union + { + struct + { + unsigned int reserved1 : 1; + /*! \brief 1E.0206.1 R/W uP Mailbox CRC Read Enable + AQ_GlobalMailboxInterface_HHD.u6.bits_6.upMailboxCrcReadEnable + + Default = 0x0 + + 1 = Update uP mailbox CRC on read + + */ + unsigned int upMailboxCrcReadEnable : 1; /* 1E.0206.1 R/W Default = 0x0 */ + /* 1 = Update uP mailbox CRC on read + */ + unsigned int reserved0 : 14; + } bits_6; + uint16_t word_6; + } u6; +} AQ_GlobalMailboxInterface_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Microprocessor Scratch Pad: 1E.0300 */ +/* Global Microprocessor Scratch Pad: 1E.0300 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Microprocessor Scratch Pad */ + union + { + struct + { + /*! \brief 1E.0300.F:0 R/W Scratch Pad 1[F:0] + AQ_GlobalMicroprocessorScratchPad_HHD.u0.bits_0.scratchPad_1 + + Default = 0x0000 + + General Purpose Scratch Pad + */ + unsigned int scratchPad_1 : 16; /* 1E.0300.F:0 R/W Default = 0x0000 */ + /* General Purpose Scratch Pad */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Microprocessor Scratch Pad */ + union + { + struct + { + /*! \brief 1E.0301.F:0 R/W Scratch Pad 2 [F:0] + AQ_GlobalMicroprocessorScratchPad_HHD.u1.bits_1.scratchPad_2 + + Default = 0x0000 + + General Purpose Scratch Pad + */ + unsigned int scratchPad_2 : 16; /* 1E.0301.F:0 R/W Default = 0x0000 */ + /* General Purpose Scratch Pad */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalMicroprocessorScratchPad_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress Control Register: 1E.5002 */ +/* MSS Egress Control Register: 1E.5002 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress Control Register */ + union + { + struct + { + /*! \brief 1E.5002.0 R/W MSS Egress Soft Reset + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressSoftReset + + Default = 0x0 + + 1 = Soft reset + + + Notes: + S/W reset */ + unsigned int mssEgressSoftReset : 1; /* 1E.5002.0 R/W Default = 0x0 */ + /* 1 = Soft reset + */ + /*! \brief 1E.5002.1 R/W MSS Egress Drop KAY Packet + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressDropKayPacket + + Default = 0x0 + + 1 = Drop KAY packet + + + Notes: + Decides whether KAY packets have to be dropped */ + unsigned int mssEgressDropKayPacket : 1; /* 1E.5002.1 R/W Default = 0x0 */ + /* 1 = Drop KAY packet + */ + /*! \brief 1E.5002.2 R/W MSS Egress Drop EGPRC LUT Miss + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressDropEgprcLutMiss + + Default = 0x0 + + 1 = Drop Egress Classification LUT miss packets + + + + Notes: + Decides whether Egress Pre-Security Classification (EGPRC) LUT miss packets are to be dropped */ + unsigned int mssEgressDropEgprcLutMiss : 1; /* 1E.5002.2 R/W Default = 0x0 */ + /* 1 = Drop Egress Classification LUT miss packets + + */ + /*! \brief 1E.5002.3 R/W MSS Egress GCM Start + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressGcmStart + + Default = 0x0 + + 1 = Start GCM + + + + Notes: + Indicates GCM to start */ + unsigned int mssEgressGcmStart : 1; /* 1E.5002.3 R/W Default = 0x0 */ + /* 1 = Start GCM + + */ + /*! \brief 1E.5002.4 R/W MSS Egresss GCM Test Mode + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgresssGcmTestMode + + Default = 0x0 + + 1 = Enable GCM test mode + + + + Notes: + Enables GCM test mode */ + unsigned int mssEgresssGcmTestMode : 1; /* 1E.5002.4 R/W Default = 0x0 */ + /* 1 = Enable GCM test mode + + */ + /*! \brief 1E.5002.5 R/W MSS Egress Unmatched Use SC 0 + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressUnmatchedUseSc_0 + + Default = 0x0 + + 1 = Use SC 0 for unmatched packets + 0 = Unmatched packets are uncontrolled packets + + + + Notes: + Use SC-Index 0 as default SC for unmatched packets. Otherwise the packets are treated as uncontrolled packets. */ + unsigned int mssEgressUnmatchedUseSc_0 : 1; /* 1E.5002.5 R/W Default = 0x0 */ + /* 1 = Use SC 0 for unmatched packets + 0 = Unmatched packets are uncontrolled packets + + */ + /*! \brief 1E.5002.6 R/W MSS Egress Drop Invalid SA/SC Packets + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressDropInvalidSa_scPackets + + Default = 0x0 + + 1 = Drop invalid SA/SC packets + + + + Notes: + Enables dropping of invalid SA/SC packets. */ + unsigned int mssEgressDropInvalidSa_scPackets : 1; /* 1E.5002.6 R/W Default = 0x0 */ + /* 1 = Drop invalid SA/SC packets + + */ + /*! \brief 1E.5002.7 R/W MSS Egress Explicit SECTag Report Short Length + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressExplicitSectagReportShortLength + + Default = 0x0 + + Reserved + + + + Notes: + Unused. */ + unsigned int mssEgressExplicitSectagReportShortLength : 1; /* 1E.5002.7 R/W Default = 0x0 */ + /* Reserved + + */ + /*! \brief 1E.5002.8 R/W MSS Egress External Classification Enable + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressExternalClassificationEnable + + Default = 0x0 + + 1 = Drop EGPRC miss packets + + + + Notes: + If set, internal classification is bypassed. Should always be set to 0. */ + unsigned int mssEgressExternalClassificationEnable : 1; /* 1E.5002.8 R/W Default = 0x0 */ + /* 1 = Drop EGPRC miss packets + + */ + /*! \brief 1E.5002.9 R/W MSS Egress ICV LSB 8 Bytes Enable + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressIcvLsb_8BytesEnable + + Default = 0x0 + + 1 = Use LSB + 0 = Use MSB + + + + Notes: + This bit selects MSB or LSB 8 bytes selection in the case where the ICV is 8 bytes. + 0 = MSB is used. */ + unsigned int mssEgressIcvLsb_8BytesEnable : 1; /* 1E.5002.9 R/W Default = 0x0 */ + /* 1 = Use LSB + 0 = Use MSB + + */ + /*! \brief 1E.5002.A R/W MSS Egress High Priority + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressHighPriority + + Default = 0x0 + + 1 = MIB counter clear on read enable + + + + Notes: + If this bit is set to 1, read is given high priority and the MIB count value becomes 0 after read. */ + unsigned int mssEgressHighPriority : 1; /* 1E.5002.A R/W Default = 0x0 */ + /* 1 = MIB counter clear on read enable + + */ + /*! \brief 1E.5002.B R/W MSS Egress Clear Counter + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressClearCounter + + Default = 0x0 + + 1 = Clear all MIB counters + + + + Notes: + If this bit is set to 1, all MIB counters will be cleared. */ + unsigned int mssEgressClearCounter : 1; /* 1E.5002.B R/W Default = 0x0 */ + /* 1 = Clear all MIB counters + + */ + /*! \brief 1E.5002.C R/W MSS Egress Clear Global Time + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressClearGlobalTime + + Default = 0x0 + + 1 = Clear global time + + + + Notes: + Clear global time. */ + unsigned int mssEgressClearGlobalTime : 1; /* 1E.5002.C R/W Default = 0x0 */ + /* 1 = Clear global time + + */ + /*! \brief 1E.5002.F:D R/W MSS Egress Ethertype Explicit SECTag LSB [2:0] + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressEthertypeExplicitSectagLsb + + Default = 0x0 + + Ethertype for explicit SECTag bits 2:0. + + + Notes: + Ethertype for explicity SECTag. */ + unsigned int mssEgressEthertypeExplicitSectagLsb : 3; /* 1E.5002.F:D R/W Default = 0x0 */ + /* Ethertype for explicit SECTag bits 2:0. + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress Control Register */ + union + { + struct + { + /*! \brief 1E.5003.C:0 R/W MSS Egress Ethertype Explicit SECTag MSB [F:3] + AQ_MssEgressControlRegister_HHD.u1.bits_1.mssEgressEthertypeExplicitSectagMsb + + Default = 0x0000 + + Ethertype for explicit SECTag bits 15:3. + + + Notes: + Ethertype for explicity SECTag. */ + unsigned int mssEgressEthertypeExplicitSectagMsb : 13; /* 1E.5003.C:0 R/W Default = 0x0000 */ + /* Ethertype for explicit SECTag bits 15:3. + */ + unsigned int reserved0 : 3; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress VLAN TPID 0 Register: 1E.5008 */ +/* MSS Egress VLAN TPID 0 Register: 1E.5008 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress VLAN TPID 0 Register */ + union + { + struct + { + /*! \brief 1E.5008.F:0 R/W MSS Egress VLAN STag TPID [F:0] + AQ_MssEgressVlanTpid_0Register_HHD.u0.bits_0.mssEgressVlanStagTpid + + Default = 0x0000 + + STag TPID + + + Notes: + Service Tag Protocol Identifier (TPID) values to identify a VLAN tag. The " See SEC Egress VLAN CP Tag Parse STag " bit must be set to 1 for the incoming packet's TPID to be parsed. */ + unsigned int mssEgressVlanStagTpid : 16; /* 1E.5008.F:0 R/W Default = 0x0000 */ + /* STag TPID + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress VLAN TPID 0 Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressVlanTpid_0Register_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress VLAN TPID 1 Register: 1E.500A */ +/* MSS Egress VLAN TPID 1 Register: 1E.500A */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress VLAN TPID 1 Register */ + union + { + struct + { + /*! \brief 1E.500A.F:0 R/W MSS Egress VLAN QTag TPID [F:0] + AQ_MssEgressVlanTpid_1Register_HHD.u0.bits_0.mssEgressVlanQtagTpid + + Default = 0x0000 + + QTag TPID + + + Notes: + Customer Tag Protocol Identifier (TPID) values to identify a VLAN tag. The " See SEC Egress VLAN CP Tag Parse QTag " bit must be set to 1 for the incoming packet's TPID to be parsed. */ + unsigned int mssEgressVlanQtagTpid : 16; /* 1E.500A.F:0 R/W Default = 0x0000 */ + /* QTag TPID + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress VLAN TPID 1 Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressVlanTpid_1Register_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress VLAN Control Register: 1E.500C */ +/* MSS Egress VLAN Control Register: 1E.500C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress VLAN Control Register */ + union + { + struct + { + /*! \brief 1E.500C.F:0 R/W MSS Egress VLAN UP Map Table [F:0] + AQ_MssEgressVlanControlRegister_HHD.u0.bits_0.mssEgressVlanUpMapTable + + Default = 0x0000 + + UP Map table bits 15:0 + + + Notes: + If there is a customer TPID Tag match and no service TPID Tag match or the service TPID Tag match is disabled, the outer TAG's PCP is used to index into this map table to generate the packets user priority. + 2:0 : UP value for customer Tag PCP 0x0 + 5:3: UP value for customer Tag PCP 0x0 + 8:6 : UP value for customer Tag PCP 0x0 + 11:9 : UP value for customer Tag PCP 0x0 + 14:12 : UP value for customer Tag PCP 0x0 + 17:15 : UP value for customer Tag PCP 0x0 + 20:18 : UP value for customer Tag PCP 0x0 + 23:21 : UP value for customer Tag PCP 0x0 */ + unsigned int mssEgressVlanUpMapTable : 16; /* 1E.500C.F:0 R/W Default = 0x0000 */ + /* UP Map table bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress VLAN Control Register */ + union + { + struct + { + /*! \brief 1E.500D.7:0 R/W MSS Egress VLAN UP Map Table MSW [17:10] + AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanUpMapTableMSW + + Default = 0x00 + + UP Map table bits 23:16 + + + Notes: + If there is a customer TPID Tag match and no service TPID Tag match or the service TPID Tag match is disabled, the outer TAG's PCP is used to index into this map table to generate the packets user priority. + 2:0 : UP value for customer Tag PCP 0x0 + 5:3: UP value for customer Tag PCP 0x0 + 8:6 : UP value for customer Tag PCP 0x0 + 11:9 : UP value for customer Tag PCP 0x0 + 14:12 : UP value for customer Tag PCP 0x0 + 17:15 : UP value for customer Tag PCP 0x0 + 20:18 : UP value for customer Tag PCP 0x0 + 23:21 : UP value for customer Tag PCP 0x0 */ + unsigned int mssEgressVlanUpMapTableMSW : 8; /* 1E.500D.7:0 R/W Default = 0x00 */ + /* UP Map table bits 23:16 + */ + /*! \brief 1E.500D.A:8 R/W MSS Egress VLAN UP Default [2:0] + AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanUpDefault + + Default = 0x0 + + UP default + + + Notes: + User priority default */ + unsigned int mssEgressVlanUpDefault : 3; /* 1E.500D.A:8 R/W Default = 0x0 */ + /* UP default + */ + /*! \brief 1E.500D.B R/W MSS Egress VLAN STag UP Parse Enable + AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanStagUpParseEnable + + Default = 0x0 + + VLAN CP Tag STag UP enable + + + Notes: + Enable controlled port service VLAN service Tag user priority field parsing. */ + unsigned int mssEgressVlanStagUpParseEnable : 1; /* 1E.500D.B R/W Default = 0x0 */ + /* VLAN CP Tag STag UP enable + */ + /*! \brief 1E.500D.C R/W MSS Egress VLAN QTag UP Parse Enable + AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanQtagUpParseEnable + + Default = 0x0 + + VLAN CP Tag QTag UP enable + + + Notes: + Enable controlled port customer VLAN customer Tag user priority field parsing. */ + unsigned int mssEgressVlanQtagUpParseEnable : 1; /* 1E.500D.C R/W Default = 0x0 */ + /* VLAN CP Tag QTag UP enable + */ + /*! \brief 1E.500D.D R/W MSS Egress VLAN QinQ Parse Enable + AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanQinqParseEnable + + Default = 0x0 + + VLAN CP Tag Parse QinQ + + + Notes: + Enable controlled port VLAN QinQ Tag parsing. When this bit is set to 1 both the outer and inner VLAN Tags will be parsed. */ + unsigned int mssEgressVlanQinqParseEnable : 1; /* 1E.500D.D R/W Default = 0x0 */ + /* VLAN CP Tag Parse QinQ + */ + /*! \brief 1E.500D.E R/W MSS Egress VLAN STag Parse Enable + AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanStagParseEnable + + Default = 0x0 + + 1 = Enable VLAN STag parsing + + + Notes: + Enable controlled port VLAN service Tag parsing. When this bit is set to 1, the incoming packets outer TPID will be compared with the configured " See SEC Egress TPID 0 [F:0] " for matching. If the " See SEC Egress VLAN CP Tag Parse QinQ " bit is set to1, this will also be used to compare the incoming packet's inner TPID. */ + unsigned int mssEgressVlanStagParseEnable : 1; /* 1E.500D.E R/W Default = 0x0 */ + /* 1 = Enable VLAN STag parsing + */ + /*! \brief 1E.500D.F R/W MSS Egress VLAN QTag Parse Enable + AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanQtagParseEnable + + Default = 0x0 + + 1 = Enable VLAN QTag parsing + + + Notes: + Enable controlled port VLAN customer Tag parsing. When this bit is set to 1, the incoming packet's outer TPID will be compared with the configured " See SEC Egress TPID 1 [F:0] " for matching. If the " See SEC Egress VLAN CP Tag Parse QinQ " bit is set to1, this will also be used to compare the incoming packet's inner TPID. */ + unsigned int mssEgressVlanQtagParseEnable : 1; /* 1E.500D.F R/W Default = 0x0 */ + /* 1 = Enable VLAN QTag parsing + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressVlanControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress PN Control Register: 1E.500E */ +/* MSS Egress PN Control Register: 1E.500E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress PN Control Register */ + union + { + struct + { + /*! \brief 1E.500E.F:0 R/W MSS Egress SA PN Threshold LSW [F:0] + AQ_MssEgressPnControlRegister_HHD.u0.bits_0.mssEgressSaPnThresholdLSW + + Default = 0x0000 + + PN threshold bits 15:0 + + + Notes: + Egress PN threshold to generate SA threshold interrupt. */ + unsigned int mssEgressSaPnThresholdLSW : 16; /* 1E.500E.F:0 R/W Default = 0x0000 */ + /* PN threshold bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress PN Control Register */ + union + { + struct + { + /*! \brief 1E.500F.F:0 R/W MSS Egress SA PN Threshold MSW [1F:10] + AQ_MssEgressPnControlRegister_HHD.u1.bits_1.mssEgressSaPnThresholdMSW + + Default = 0x0000 + + PN threshold bits 31:16 + + + Notes: + Egress PN threshold to generate SA threshold interrupt. */ + unsigned int mssEgressSaPnThresholdMSW : 16; /* 1E.500F.F:0 R/W Default = 0x0000 */ + /* PN threshold bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressPnControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress MTU Size Control Register: 1E.5010 */ +/* MSS Egress MTU Size Control Register: 1E.5010 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress MTU Size Control Register */ + union + { + struct + { + /*! \brief 1E.5010.F:0 R/W MSS Egress Controlled Packet MTU Size [F:0] + AQ_MssEgressMtuSizeControlRegister_HHD.u0.bits_0.mssEgressControlledPacketMtuSize + + Default = 0x05DC + + Maximum transmission unit for controlled packet + + + Notes: + Maximum transmission unit of controlled packet */ + unsigned int mssEgressControlledPacketMtuSize : 16; /* 1E.5010.F:0 R/W Default = 0x05DC */ + /* Maximum transmission unit for controlled packet + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress MTU Size Control Register */ + union + { + struct + { + /*! \brief 1E.5011.F:0 R/W MSS Egress Uncontrolled Packet MTU Size [F:0] + AQ_MssEgressMtuSizeControlRegister_HHD.u1.bits_1.mssEgressUncontrolledPacketMtuSize + + Default = 0x05DC + + Maximum transmission unit for uncontrolled packet + + + Notes: + Maximum transmission unit of uncontrolled packet */ + unsigned int mssEgressUncontrolledPacketMtuSize : 16; /* 1E.5011.F:0 R/W Default = 0x05DC */ + /* Maximum transmission unit for uncontrolled packet + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressMtuSizeControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress Interrupt Status Register: 1E.505C */ +/* MSS Egress Interrupt Status Register: 1E.505C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress Interrupt Status Register */ + union + { + struct + { + /*! \brief 1E.505C.0 COW MSS Egress Master Interrupt + AQ_MssEgressInterruptStatusRegister_HHD.u0.bits_0.mssEgressMasterInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when any one of the above interrupt and the corresponding interrupt enable are both set. The interrupt enable for this bit must also be set for this bit to be set. */ + unsigned int mssEgressMasterInterrupt : 1; /* 1E.505C.0 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.505C.1 COW MSS Egress SA Expired Interrupt + AQ_MssEgressInterruptStatusRegister_HHD.u0.bits_0.mssEgressSaExpiredInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when the SA PN reaches all ones saturation. */ + unsigned int mssEgressSaExpiredInterrupt : 1; /* 1E.505C.1 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.505C.2 COW MSS Egress SA Threshold Expired Interrupt + AQ_MssEgressInterruptStatusRegister_HHD.u0.bits_0.mssEgressSaThresholdExpiredInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when the SA PN reaches the See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . */ + unsigned int mssEgressSaThresholdExpiredInterrupt : 1; /* 1E.505C.2 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.505C.3 COW MSS Egress MIB Saturation Interrupt + AQ_MssEgressInterruptStatusRegister_HHD.u0.bits_0.mssEgressMibSaturationInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when the MIB counters reaches all ones saturation. */ + unsigned int mssEgressMibSaturationInterrupt : 1; /* 1E.505C.3 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.505C.4 COW MSS Egress ECC Error Interrupt + AQ_MssEgressInterruptStatusRegister_HHD.u0.bits_0.mssEgressEccErrorInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when anyone of the memories detects an ECC error. */ + unsigned int mssEgressEccErrorInterrupt : 1; /* 1E.505C.4 COW Default = 0x0 */ + /* 1 = Interrupt + */ + unsigned int reserved0 : 11; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress Interrupt Status Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressInterruptStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress Interrupt Mask Register: 1E.505E */ +/* MSS Egress Interrupt Mask Register: 1E.505E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress Interrupt Mask Register */ + union + { + struct + { + /*! \brief 1E.505E.0 COW MSS Egress Master Interrupt Enable + AQ_MssEgressInterruptMaskRegister_HHD.u0.bits_0.mssEgressMasterInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + + Notes: + Write to 1 to clear. */ + unsigned int mssEgressMasterInterruptEnable : 1; /* 1E.505E.0 COW Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.505E.1 COW MSS Egress SA Expired Interrupt Enable + AQ_MssEgressInterruptMaskRegister_HHD.u0.bits_0.mssEgressSaExpiredInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + + Notes: + Write to 1 to clear. This bit is set when the SA PN reaches all ones saturation. */ + unsigned int mssEgressSaExpiredInterruptEnable : 1; /* 1E.505E.1 COW Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.505E.2 COW MSS Egress SA Expired Threshold Interrupt Enable + AQ_MssEgressInterruptMaskRegister_HHD.u0.bits_0.mssEgressSaExpiredThresholdInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + + Notes: + Write to 1 to clear. This bit is set when the SA PN reaches the configured threshold See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . */ + unsigned int mssEgressSaExpiredThresholdInterruptEnable : 1; /* 1E.505E.2 COW Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.505E.3 COW MSS Egress MIB Saturation Interrupt Enable + AQ_MssEgressInterruptMaskRegister_HHD.u0.bits_0.mssEgressMibSaturationInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + + Notes: + Write to 1 to clear. This bit is set when the MIB counters reaches all ones saturation. */ + unsigned int mssEgressMibSaturationInterruptEnable : 1; /* 1E.505E.3 COW Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.505E.4 COW MSS Egress ECC Error Interrupt Enable + AQ_MssEgressInterruptMaskRegister_HHD.u0.bits_0.mssEgressEccErrorInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + + Notes: + Write to 1 to clear. This bit is set when anyone of the memories detects an ECC error. */ + unsigned int mssEgressEccErrorInterruptEnable : 1; /* 1E.505E.4 COW Default = 0x0 */ + /* 1 = Interrupt enabled + */ + unsigned int reserved0 : 11; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress Interrupt Mask Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressInterruptMaskRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress SA Expired Status Register: 1E.5060 */ +/* MSS Egress SA Expired Status Register: 1E.5060 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress SA Expired Status Register */ + union + { + struct + { + /*! \brief 1E.5060.F:0 COW MSS Egress SA Expired LSW [F:0] + AQ_MssEgressSaExpiredStatusRegister_HHD.u0.bits_0.mssEgressSaExpiredLSW + + Default = 0x0000 + + SA expired bits 15:0 + + + Notes: + Write these bits to 1 to clear. + When set, these bits identify the SA that has expired when the SA PN reaches all-ones saturation. */ + unsigned int mssEgressSaExpiredLSW : 16; /* 1E.5060.F:0 COW Default = 0x0000 */ + /* SA expired bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress SA Expired Status Register */ + union + { + struct + { + /*! \brief 1E.5061.F:0 COW MSS Egress SA Expired MSW [1F:10] + AQ_MssEgressSaExpiredStatusRegister_HHD.u1.bits_1.mssEgressSaExpiredMSW + + Default = 0x0000 + + SA expired bits 31:16 + + + Notes: + Write these bits to 1 to clear. + When set, these bits identify the SA that has expired when the SA PN reaches all-ones saturation. */ + unsigned int mssEgressSaExpiredMSW : 16; /* 1E.5061.F:0 COW Default = 0x0000 */ + /* SA expired bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressSaExpiredStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress SA Threshold Expired Status Register: 1E.5062 */ +/* MSS Egress SA Threshold Expired Status Register: 1E.5062 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress SA Threshold Expired Status Register */ + union + { + struct + { + /*! \brief 1E.5062.F:0 COW MSS Egress SA Threshold Expired LSW [F:0] + AQ_MssEgressSaThresholdExpiredStatusRegister_HHD.u0.bits_0.mssEgressSaThresholdExpiredLSW + + Default = 0x0000 + + SA threshold expired bits 15:0 + + + Notes: + Write these bits to 1 to clear. + When set, these bits identify the SA that has expired when the SA PN has reached the configured threshold See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . */ + unsigned int mssEgressSaThresholdExpiredLSW : 16; /* 1E.5062.F:0 COW Default = 0x0000 */ + /* SA threshold expired bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress SA Threshold Expired Status Register */ + union + { + struct + { + /*! \brief 1E.5063.F:0 COW MSS Egress SA Threshold Expired MSW [1F:10] + AQ_MssEgressSaThresholdExpiredStatusRegister_HHD.u1.bits_1.mssEgressSaThresholdExpiredMSW + + Default = 0x0000 + + SA threshold expired bits 31:16 + + + Notes: + Write these bits to 1 to clear. + When set, these bits identify the SA that has expired when the SA PN has reached the configured threshold See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . */ + unsigned int mssEgressSaThresholdExpiredMSW : 16; /* 1E.5063.F:0 COW Default = 0x0000 */ + /* SA threshold expired bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressSaThresholdExpiredStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress ECC Interrupt Status Register: 1E.5064 */ +/* MSS Egress ECC Interrupt Status Register: 1E.5064 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress ECC Interrupt Status Register */ + union + { + struct + { + /*! \brief 1E.5064.F:0 COW MSS Egress SA ECC Error Interrupt LSW [F:0] + AQ_MssEgressEccInterruptStatusRegister_HHD.u0.bits_0.mssEgressSaEccErrorInterruptLSW + + Default = 0x0000 + + SA ECC error interrupt bits 15:0 + + + Notes: + Write these bits to 1 to clear. + When set to 1, indicates that an ECC error occured for the SA. */ + unsigned int mssEgressSaEccErrorInterruptLSW : 16; /* 1E.5064.F:0 COW Default = 0x0000 */ + /* SA ECC error interrupt bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress ECC Interrupt Status Register */ + union + { + struct + { + /*! \brief 1E.5065.F:0 COW MSS Egress SA ECC Error Interrupt MSW [1F:10] + AQ_MssEgressEccInterruptStatusRegister_HHD.u1.bits_1.mssEgressSaEccErrorInterruptMSW + + Default = 0x0000 + + SA ECC error interrupt bits 31:16 + + + Notes: + Write these bits to 1 to clear. + When set to 1, indicates that an ECC error occured for the SA. */ + unsigned int mssEgressSaEccErrorInterruptMSW : 16; /* 1E.5065.F:0 COW Default = 0x0000 */ + /* SA ECC error interrupt bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressEccInterruptStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress LUT Address Control Register: 1E.5080 */ +/* MSS Egress LUT Address Control Register: 1E.5080 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress LUT Address Control Register */ + union + { + struct + { + /*! \brief 1E.5080.8:0 R/W MSS Egress LUT Address [8:0] + AQ_MssEgressLutAddressControlRegister_HHD.u0.bits_0.mssEgressLutAddress + + Default = 0x000 + + LUT address + + */ + unsigned int mssEgressLutAddress : 9; /* 1E.5080.8:0 R/W Default = 0x000 */ + /* LUT address + */ + unsigned int reserved0 : 3; + /*! \brief 1E.5080.F:C R/W MSS Egress LUT Select [3:0] + AQ_MssEgressLutAddressControlRegister_HHD.u0.bits_0.mssEgressLutSelect + + Default = 0x0 + + LUT select + + + Notes: + 0x0 : Egress MAC Control FIlter (CTLF) LUT + 0x1 : Egress Classification LUT + 0x2 : Egress SC/SA LUT + 0x3 : Egress SMIB */ + unsigned int mssEgressLutSelect : 4; /* 1E.5080.F:C R/W Default = 0x0 */ + /* LUT select + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_MssEgressLutAddressControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress LUT Control Register: 1E.5081 */ +/* MSS Egress LUT Control Register: 1E.5081 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress LUT Control Register */ + union + { + struct + { + unsigned int reserved0 : 14; + /*! \brief 1E.5081.E R/W MSS Egress LUT Read + AQ_MssEgressLutControlRegister_HHD.u0.bits_0.mssEgressLutRead + + Default = 0x0 + + 1 = LUT read + + + Notes: + Setting this bit to 1, will read the LUT. This bit will automatically clear to 0. */ + unsigned int mssEgressLutRead : 1; /* 1E.5081.E R/W Default = 0x0 */ + /* 1 = LUT read + */ + /*! \brief 1E.5081.F R/W MSS Egress LUT Write + AQ_MssEgressLutControlRegister_HHD.u0.bits_0.mssEgressLutWrite + + Default = 0x0 + + 1 = LUT write + + + Notes: + Setting this bit to 1, will write the LUT. This bit will automatically clear to 0. */ + unsigned int mssEgressLutWrite : 1; /* 1E.5081.F R/W Default = 0x0 */ + /* 1 = LUT write + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_MssEgressLutControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress LUT Data Control Register: 1E.50A0 */ +/* MSS Egress LUT Data Control Register: 1E.50A0 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A0.F:0 R/W MSS Egress LUT Data 0 [F:0] + AQ_MssEgressLutDataControlRegister_HHD.u0.bits_0.mssEgressLutData_0 + + Default = 0x0000 + + LUT data bits 15:0 + + */ + unsigned int mssEgressLutData_0 : 16; /* 1E.50A0.F:0 R/W Default = 0x0000 */ + /* LUT data bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A1.F:0 R/W MSS Egress LUT Data 1 [1F:10] + AQ_MssEgressLutDataControlRegister_HHD.u1.bits_1.mssEgressLutData_1 + + Default = 0x0000 + + LUT data bits 31:16 + + */ + unsigned int mssEgressLutData_1 : 16; /* 1E.50A1.F:0 R/W Default = 0x0000 */ + /* LUT data bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A2.F:0 R/W MSS Egress LUT Data 2 [2F:20] + AQ_MssEgressLutDataControlRegister_HHD.u2.bits_2.mssEgressLutData_2 + + Default = 0x0000 + + LUT data bits 47:32 + + */ + unsigned int mssEgressLutData_2 : 16; /* 1E.50A2.F:0 R/W Default = 0x0000 */ + /* LUT data bits 47:32 + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A3.F:0 R/W MSS Egress LUT Data 3 [3F:30] + AQ_MssEgressLutDataControlRegister_HHD.u3.bits_3.mssEgressLutData_3 + + Default = 0x0000 + + LUT data bits 63:48 + + */ + unsigned int mssEgressLutData_3 : 16; /* 1E.50A3.F:0 R/W Default = 0x0000 */ + /* LUT data bits 63:48 + */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A4.F:0 R/W MSS Egress LUT Data 4 [4F:40] + AQ_MssEgressLutDataControlRegister_HHD.u4.bits_4.mssEgressLutData_4 + + Default = 0x0000 + + LUT data bits 79:64 + + */ + unsigned int mssEgressLutData_4 : 16; /* 1E.50A4.F:0 R/W Default = 0x0000 */ + /* LUT data bits 79:64 + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A5.F:0 R/W MSS Egress LUT Data 5 [5F:50] + AQ_MssEgressLutDataControlRegister_HHD.u5.bits_5.mssEgressLutData_5 + + Default = 0x0000 + + LUT data bits 95:80 + + */ + unsigned int mssEgressLutData_5 : 16; /* 1E.50A5.F:0 R/W Default = 0x0000 */ + /* LUT data bits 95:80 + */ + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A6.F:0 R/W MSS Egress LUT Data 6 [6F:60] + AQ_MssEgressLutDataControlRegister_HHD.u6.bits_6.mssEgressLutData_6 + + Default = 0x0000 + + LUT data bits 111:96 + + */ + unsigned int mssEgressLutData_6 : 16; /* 1E.50A6.F:0 R/W Default = 0x0000 */ + /* LUT data bits 111:96 + */ + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A7.F:0 R/W MSS Egress LUT Data 7 [7F:70] + AQ_MssEgressLutDataControlRegister_HHD.u7.bits_7.mssEgressLutData_7 + + Default = 0x0000 + + LUT data bits 127:112 + + */ + unsigned int mssEgressLutData_7 : 16; /* 1E.50A7.F:0 R/W Default = 0x0000 */ + /* LUT data bits 127:112 + */ + } bits_7; + uint16_t word_7; + } u7; + /*! \brief Union for bit and word level access of word 8 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A8.F:0 R/W MSS Egress LUT Data 8 [8F:80] + AQ_MssEgressLutDataControlRegister_HHD.u8.bits_8.mssEgressLutData_8 + + Default = 0x0000 + + LUT data bits 143:128 + + */ + unsigned int mssEgressLutData_8 : 16; /* 1E.50A8.F:0 R/W Default = 0x0000 */ + /* LUT data bits 143:128 + */ + } bits_8; + uint16_t word_8; + } u8; + /*! \brief Union for bit and word level access of word 9 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A9.F:0 R/W MSS Egress LUT Data 9 [9F:90] + AQ_MssEgressLutDataControlRegister_HHD.u9.bits_9.mssEgressLutData_9 + + Default = 0x0000 + + LUT data bits 159:144 + + */ + unsigned int mssEgressLutData_9 : 16; /* 1E.50A9.F:0 R/W Default = 0x0000 */ + /* LUT data bits 159:144 + */ + } bits_9; + uint16_t word_9; + } u9; + /*! \brief Union for bit and word level access of word 10 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50AA.F:0 R/W MSS Egress LUT Data 10 [AF:A0] + AQ_MssEgressLutDataControlRegister_HHD.u10.bits_10.mssEgressLutData_10 + + Default = 0x0000 + + LUT data bits 175:160 + + */ + unsigned int mssEgressLutData_10 : 16; /* 1E.50AA.F:0 R/W Default = 0x0000 */ + /* LUT data bits 175:160 + */ + } bits_10; + uint16_t word_10; + } u10; + /*! \brief Union for bit and word level access of word 11 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50AB.F:0 R/W MSS Egress LUT Data 11 [BF:B0] + AQ_MssEgressLutDataControlRegister_HHD.u11.bits_11.mssEgressLutData_11 + + Default = 0x0000 + + LUT data bits 191:176 + + */ + unsigned int mssEgressLutData_11 : 16; /* 1E.50AB.F:0 R/W Default = 0x0000 */ + /* LUT data bits 191:176 + */ + } bits_11; + uint16_t word_11; + } u11; + /*! \brief Union for bit and word level access of word 12 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50AC.F:0 R/W MSS Egress LUT Data 12 [CF:C0] + AQ_MssEgressLutDataControlRegister_HHD.u12.bits_12.mssEgressLutData_12 + + Default = 0x0000 + + LUT data bits 207:192 + + */ + unsigned int mssEgressLutData_12 : 16; /* 1E.50AC.F:0 R/W Default = 0x0000 */ + /* LUT data bits 207:192 + */ + } bits_12; + uint16_t word_12; + } u12; + /*! \brief Union for bit and word level access of word 13 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50AD.F:0 R/W MSS Egress LUT Data 13 [DF:D0] + AQ_MssEgressLutDataControlRegister_HHD.u13.bits_13.mssEgressLutData_13 + + Default = 0x0000 + + LUT data bits 223:208 + + */ + unsigned int mssEgressLutData_13 : 16; /* 1E.50AD.F:0 R/W Default = 0x0000 */ + /* LUT data bits 223:208 + */ + } bits_13; + uint16_t word_13; + } u13; + /*! \brief Union for bit and word level access of word 14 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50AE.F:0 R/W MSS Egress LUT Data 14 [EF:E0] + AQ_MssEgressLutDataControlRegister_HHD.u14.bits_14.mssEgressLutData_14 + + Default = 0x0000 + + LUT data bits 239:224 + + */ + unsigned int mssEgressLutData_14 : 16; /* 1E.50AE.F:0 R/W Default = 0x0000 */ + /* LUT data bits 239:224 + */ + } bits_14; + uint16_t word_14; + } u14; + /*! \brief Union for bit and word level access of word 15 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50AF.F:0 R/W MSS Egress LUT Data 15 [FF:F0] + AQ_MssEgressLutDataControlRegister_HHD.u15.bits_15.mssEgressLutData_15 + + Default = 0x0000 + + LUT data bits 255:240 + + */ + unsigned int mssEgressLutData_15 : 16; /* 1E.50AF.F:0 R/W Default = 0x0000 */ + /* LUT data bits 255:240 + */ + } bits_15; + uint16_t word_15; + } u15; + /*! \brief Union for bit and word level access of word 16 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B0.F:0 R/W MSS Egress LUT Data 16 [10F:100] + AQ_MssEgressLutDataControlRegister_HHD.u16.bits_16.mssEgressLutData_16 + + Default = 0x0000 + + LUT data bits 271:256 + + */ + unsigned int mssEgressLutData_16 : 16; /* 1E.50B0.F:0 R/W Default = 0x0000 */ + /* LUT data bits 271:256 + */ + } bits_16; + uint16_t word_16; + } u16; + /*! \brief Union for bit and word level access of word 17 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B1.F:0 R/W MSS Egress LUT Data 17 [11F:110] + AQ_MssEgressLutDataControlRegister_HHD.u17.bits_17.mssEgressLutData_17 + + Default = 0x0000 + + LUT data bits 287:272 + + */ + unsigned int mssEgressLutData_17 : 16; /* 1E.50B1.F:0 R/W Default = 0x0000 */ + /* LUT data bits 287:272 + */ + } bits_17; + uint16_t word_17; + } u17; + /*! \brief Union for bit and word level access of word 18 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B2.F:0 R/W MSS Egress LUT Data 18 [12F:120] + AQ_MssEgressLutDataControlRegister_HHD.u18.bits_18.mssEgressLutData_18 + + Default = 0x0000 + + LUT data bits 303:288 + + */ + unsigned int mssEgressLutData_18 : 16; /* 1E.50B2.F:0 R/W Default = 0x0000 */ + /* LUT data bits 303:288 + */ + } bits_18; + uint16_t word_18; + } u18; + /*! \brief Union for bit and word level access of word 19 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B3.F:0 R/W MSS Egress LUT Data 19 [13F:130] + AQ_MssEgressLutDataControlRegister_HHD.u19.bits_19.mssEgressLutData_19 + + Default = 0x0000 + + LUT data bits 319:304 + + */ + unsigned int mssEgressLutData_19 : 16; /* 1E.50B3.F:0 R/W Default = 0x0000 */ + /* LUT data bits 319:304 + */ + } bits_19; + uint16_t word_19; + } u19; + /*! \brief Union for bit and word level access of word 20 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B4.F:0 R/W MSS Egress LUT Data 20 [14F:140] + AQ_MssEgressLutDataControlRegister_HHD.u20.bits_20.mssEgressLutData_20 + + Default = 0x0000 + + LUT data bits 335:320 + + */ + unsigned int mssEgressLutData_20 : 16; /* 1E.50B4.F:0 R/W Default = 0x0000 */ + /* LUT data bits 335:320 + */ + } bits_20; + uint16_t word_20; + } u20; + /*! \brief Union for bit and word level access of word 21 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B5.F:0 R/W MSS Egress LUT Data 21 [15F:150] + AQ_MssEgressLutDataControlRegister_HHD.u21.bits_21.mssEgressLutData_21 + + Default = 0x0000 + + LUT data bits 351:336 + + */ + unsigned int mssEgressLutData_21 : 16; /* 1E.50B5.F:0 R/W Default = 0x0000 */ + /* LUT data bits 351:336 + */ + } bits_21; + uint16_t word_21; + } u21; + /*! \brief Union for bit and word level access of word 22 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B6.F:0 R/W MSS Egress LUT Data 22 [16F:160] + AQ_MssEgressLutDataControlRegister_HHD.u22.bits_22.mssEgressLutData_22 + + Default = 0x0000 + + LUT data bits 367:352 + + */ + unsigned int mssEgressLutData_22 : 16; /* 1E.50B6.F:0 R/W Default = 0x0000 */ + /* LUT data bits 367:352 + */ + } bits_22; + uint16_t word_22; + } u22; + /*! \brief Union for bit and word level access of word 23 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B7.F:0 R/W MSS Egress LUT Data 23 [17F:170] + AQ_MssEgressLutDataControlRegister_HHD.u23.bits_23.mssEgressLutData_23 + + Default = 0x0000 + + LUT data bits 383:368 + + */ + unsigned int mssEgressLutData_23 : 16; /* 1E.50B7.F:0 R/W Default = 0x0000 */ + /* LUT data bits 383:368 + */ + } bits_23; + uint16_t word_23; + } u23; + /*! \brief Union for bit and word level access of word 24 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B8.F:0 R/W MSS Egress LUT Data 24 [18F:180] + AQ_MssEgressLutDataControlRegister_HHD.u24.bits_24.mssEgressLutData_24 + + Default = 0x0000 + + LUT data bits 399:384 + + */ + unsigned int mssEgressLutData_24 : 16; /* 1E.50B8.F:0 R/W Default = 0x0000 */ + /* LUT data bits 399:384 + */ + } bits_24; + uint16_t word_24; + } u24; + /*! \brief Union for bit and word level access of word 25 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B9.F:0 R/W MSS Egress LUT Data 25 [19F:190] + AQ_MssEgressLutDataControlRegister_HHD.u25.bits_25.mssEgressLutData_25 + + Default = 0x0000 + + LUT data bits 415:400 + + */ + unsigned int mssEgressLutData_25 : 16; /* 1E.50B9.F:0 R/W Default = 0x0000 */ + /* LUT data bits 415:400 + */ + } bits_25; + uint16_t word_25; + } u25; + /*! \brief Union for bit and word level access of word 26 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50BA.F:0 R/W MSS Egress LUT Data 26 [1AF:1A0] + AQ_MssEgressLutDataControlRegister_HHD.u26.bits_26.mssEgressLutData_26 + + Default = 0x0000 + + LUT data bits 431:416 + + */ + unsigned int mssEgressLutData_26 : 16; /* 1E.50BA.F:0 R/W Default = 0x0000 */ + /* LUT data bits 431:416 + */ + } bits_26; + uint16_t word_26; + } u26; + /*! \brief Union for bit and word level access of word 27 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50BB.F:0 R/W MSS Egress LUT Data 27 [1BF:1B0] + AQ_MssEgressLutDataControlRegister_HHD.u27.bits_27.mssEgressLutData_27 + + Default = 0x0000 + + LUT data bits 447:432 + + */ + unsigned int mssEgressLutData_27 : 16; /* 1E.50BB.F:0 R/W Default = 0x0000 */ + /* LUT data bits 447:432 + */ + } bits_27; + uint16_t word_27; + } u27; +} AQ_MssEgressLutDataControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System General Control Register: 1E.6004 */ +/* MSM System General Control Register: 1E.6004 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System General Control Register */ + union + { + struct + { + /*! \brief 1E.6004.0 R/W MSM System Tx Enable + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemTxEnable + + Default = 0x0 + + 1 = Tx enable + + Notes: + MAC Rx path enable. Should be set to 1 to enable the MAC Rx path. Should be set to 0 to disable the MAC Rx path. */ + unsigned int msmSystemTxEnable : 1; /* 1E.6004.0 R/W Default = 0x0 */ + /* 1 = Tx enable */ + /*! \brief 1E.6004.1 R/W MSM System Rx Enable + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemRxEnable + + Default = 0x0 + + 1 = Rx enable + + Notes: + MAC Tx path enable. Should be set to 1 to enable the MAC Tx path. Should be set to 0 to disable the MAC Tx path. */ + unsigned int msmSystemRxEnable : 1; /* 1E.6004.1 R/W Default = 0x0 */ + /* 1 = Rx enable */ + unsigned int reserved0 : 1; + /*! \brief 1E.6004.3 R/W MSM System WAN Mode + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemWanMode + + Default = 0x0 + + 1 = WAN mode + 0 = LAN mode + + + Notes: + WAN mode enable. Sets WAN mode when set to 1 and LAN mode when set to 0. Note: When changing the mode, verifiy correct setting of the Tx IPG. */ + unsigned int msmSystemWanMode : 1; /* 1E.6004.3 R/W Default = 0x0 */ + /* 1 = WAN mode + 0 = LAN mode + */ + /*! \brief 1E.6004.4 R/W MSM System Promiscuous Mode + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemPromiscuousMode + + Default = 0x0 + + 1 = Promiscuous mode + + + Notes: + When set to 1, all frames are received without any MAC address filtering. */ + unsigned int msmSystemPromiscuousMode : 1; /* 1E.6004.4 R/W Default = 0x0 */ + /* 1 = Promiscuous mode + */ + /*! \brief 1E.6004.5 R/W MSM System PAD Enable + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemPadEnable + + Default = 0x0 + + 1 = Enable frame padding removal on Rx + + + Notes: + When set to 1, enable frame padding removal on the Rx path. If enabled, padding is removed before the frame is transferred to the MAC client application. If disabled, no padding is removed on the Rx by the MAC. + Note : On Tx, the MAC always adds padding as required. */ + unsigned int msmSystemPadEnable : 1; /* 1E.6004.5 R/W Default = 0x0 */ + /* 1 = Enable frame padding removal on Rx + */ + /*! \brief 1E.6004.6 R/W MSM System CRC Forward + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemCrcForward + + Default = 0x0 + + 1 = Enable CRC forwarding + + + Notes: + When set to 1, the CRC field of the received frames is forwarded with the frame to the user application. If disabled, the CRC field is stripped from the frame. + Note : If padding is enabled ( See MAC PAD Enable set to 1), this bit is ignored. */ + unsigned int msmSystemCrcForward : 1; /* 1E.6004.6 R/W Default = 0x0 */ + /* 1 = Enable CRC forwarding + */ + /*! \brief 1E.6004.7 R/W MSM System Pause Forward + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemPauseForward + + Default = 0x0 + + 1 = Enable Pause forwarding + + + Notes: + Terminate or forward pause frames. If set to 1, pause frames are forwarded to the user application. In normal mode, when set to 0, pause frames are terminated and discarded within the MAC. */ + unsigned int msmSystemPauseForward : 1; /* 1E.6004.7 R/W Default = 0x0 */ + /* 1 = Enable Pause forwarding + */ + /*! \brief 1E.6004.8 R/W MSM System Pause Ignore + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemPauseIgnore + + Default = 0x0 + + 1 = Ignore pause frames + + + Notes: + Ignore pause frame quanta. If set to 1, received pause frames are ignored by the MAC. When set to 0, the Tx is stopped for the amount of time specified in the pause quanta received within the pause frame. */ + unsigned int msmSystemPauseIgnore : 1; /* 1E.6004.8 R/W Default = 0x0 */ + /* 1 = Ignore pause frames + */ + /*! \brief 1E.6004.9 R/W MSM System Tx Address Insert Enable + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemTxAddressInsertEnable + + Default = 0x0 + + 1 = Insert Tx MAC source address + + + Notes: + Set the source MAC address on transmit. If set to 1, the MAC overwrites the source MAC address with the MAC programmed address in all transmitted frames. When set to 0, the source MAC address is transmitted unmodified from the MAC Tx client application. */ + unsigned int msmSystemTxAddressInsertEnable : 1; /* 1E.6004.9 R/W Default = 0x0 */ + /* 1 = Insert Tx MAC source address + */ + /*! \brief 1E.6004.A R/W MSM System Tx CRC Append + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemTxCrcAppend + + Default = 0x0 + + 1 = Append Tx CRC + + + Notes: + Permanently enable CRC append on transmit. If set to 1, the Tx will append a CRC to all transmitted frames. If set to 0, CRC append can be controlled on a per frame basis using the pin ff_tx_crc. + This configuration bit is OR'ed with the external ff_tx_crc pin to instruct the Tx to append a CRC to transmitted frames. The ff_tx_crc pin is tied to 0. */ + unsigned int msmSystemTxCrcAppend : 1; /* 1E.6004.A R/W Default = 0x0 */ + /* 1 = Append Tx CRC + */ + /*! \brief 1E.6004.B R/W MSM System Tx Pad Enable + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemTxPadEnable + + Default = 0x1 + + 1 = Enable Tx padding + + + Notes: + When set to 1, enable padding of frames in the Tx direction. When set to 0, the MAC will not extend frames from the application to a minimum of 64 bytes, allowing to transmit short frames (violating the Ethernet mimimum size requirements). Must be set to 1 for normal operation. */ + unsigned int msmSystemTxPadEnable : 1; /* 1E.6004.B R/W Default = 0x1 */ + /* 1 = Enable Tx padding + */ + /*! \brief 1E.6004.C R/WSC MSM System Soft Reset + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemSoftReset + + Default = 0x0 + + 1 = Soft reset + + + Notes: + Software reset. Self clearing bit. When set to 1, resets all statistic counters as well as the Tx and Rx FIFOs. It should be issued after all traffic has been stopped as a result of clearing the Rx/Tx enable bits ( See MAC Rx Enable set to 0 and See MAC Tx Enable set to 0). + Note : Can lead to an Rx interface (ff_rx_xxx) violations to the application if the reset is issued in the middle of a receive frame transfer. Then the end of packet (assertion of ff_rx_eop) is lost and the application should be prepeared to handle this exception. */ + unsigned int msmSystemSoftReset : 1; /* 1E.6004.C R/WSC Default = 0x0 */ + /* 1 = Soft reset + */ + /*! \brief 1E.6004.D R/W MSM System Control Frame Enable + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemControlFrameEnable + + Default = 0x0 + + 1 = Control frame enabled + + + Notes: + MAC control frame enable. When set to 1, the MAC control frames with any Opcode other than 0x0001 are accepted and forwarded to the client interface. When set to 0, MAC control frames with any opcode other than 0x0001 are silently discarded. */ + unsigned int msmSystemControlFrameEnable : 1; /* 1E.6004.D R/W Default = 0x0 */ + /* 1 = Control frame enabled + */ + /*! \brief 1E.6004.E R/W MSM System Rx Error Discard + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemRxErrorDiscard + + Default = 0x0 + + 1 = Enable discard of received errored frames + + + Notes: + Rx errored frame discard enable. When set to 1, any frame received with an error is discarded and not forwarded to the client interface. When set to 0, errored frames are forwarded to the client interface with ff_rx_err asserted. + Note : It is recommended to set this bit to 1 only when store and forward operation is enabled (RX_SECTION_FULL TBD). */ + unsigned int msmSystemRxErrorDiscard : 1; /* 1E.6004.E R/W Default = 0x0 */ + /* 1 = Enable discard of received errored frames + */ + /*! \brief 1E.6004.F R/W MSM System PHY Tx Enable + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemPhyTxEnable + + Default = 0x0 + + 1 = Enable PHY Tx + + + Notes: + Directly controls the phy_tx_ena pin. */ + unsigned int msmSystemPhyTxEnable : 1; /* 1E.6004.F R/W Default = 0x0 */ + /* 1 = Enable PHY Tx + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System General Control Register */ + union + { + struct + { + /*! \brief 1E.6005.0 R/W MSM System Force Send IDLE + AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemForceSendIdle + + Default = 0x0 + + 1 = Force send idle + + Notes: + When set to 1, suppress any frame transmissions and forces IDLE n the Tx interface instead of frames. This control affects the MAC reconciliation layer (RS) which acts after all MAC datapath has processed the frame. + Note : Does not have an effect on fault handling (i.e. reception of local fault will still cause transmit of remote fault). + Must be 0 for normal operation. */ + unsigned int msmSystemForceSendIdle : 1; /* 1E.6005.0 R/W Default = 0x0 */ + /* 1 = Force send idle */ + /*! \brief 1E.6005.1 R/W MSM System Length Check Disable + AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemLengthCheckDisable + + Default = 0x0 + + 1 = Disable length check + + Notes: + Payload length check disable. When set to 0, the MAC checks the frames payload length with the frame length/type field. When set to 1, the payload length check is disabled. */ + unsigned int msmSystemLengthCheckDisable : 1; /* 1E.6005.1 R/W Default = 0x0 */ + /* 1 = Disable length check */ + /*! \brief 1E.6005.2 R/W MSM System IDLE Column Count Extend + AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemIdleColumnCountExtend + + Default = 0x0 + + 1 = Extend IDLE column count + + Notes: + When set to 1, extends the RS layer IDLE column counter by 2x. The IEEE 802.3ae defines the fault condition to be cleared after 128 columns of IDLE have been received. If the MAC operates together with a WAN mode PCS (WIS) it may may happen (depending on PCS) that this period is too short to bridge the IDLE stuffing occurring in this mode, leading to a toggling fault indication. In this case, extending the counter helps to aoivd toggling fault indications. */ + unsigned int msmSystemIdleColumnCountExtend : 1; /* 1E.6005.2 R/W Default = 0x0 */ + /* 1 = Extend IDLE column count */ + /*! \brief 1E.6005.3 R/W MSM System Priority Flow Control Enable + AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemPriorityFlowControlEnable + + Default = 0x0 + + 1 = Enable priority flow control + 0 = Enable link flow control + + + Notes: + Enable priority flow control (PFC) mode of operation. When set to 0, the MAC uses standard link pause frames. When set to 1, the MAC will transmit and accept PFC frames. */ + unsigned int msmSystemPriorityFlowControlEnable : 1; /* 1E.6005.3 R/W Default = 0x0 */ + /* 1 = Enable priority flow control + 0 = Enable link flow control + */ + unsigned int reserved2 : 1; + /*! \brief 1E.6005.5 R/W MSM System SFD Check Disable + AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemSfdCheckDisable + + Default = 0x0 + + 1 = Disable SFD check + + + Notes: + Disable check of SFD (0xD5) character at frame start. When set to 1, the frame is accepted even if the SFD byte following the preamble is not 0xD5. When set to 0, a frame is accepted only if the SFD byte is found with the value 0xD5. */ + unsigned int msmSystemSfdCheckDisable : 1; /* 1E.6005.5 R/W Default = 0x0 */ + /* 1 = Disable SFD check + */ + unsigned int reserved1 : 1; + /*! \brief 1E.6005.7 R/W MSM System Tx Low Power IDLE Enable + AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemTxLowPowerIdleEnable + + Default = 0x0 + + 1 = Transmit LPI enable + + + Notes: + Transmit low power IDLE enable. When set to 1, the MAC completes the transmission of the current frame and generates low power IDLE sequences (LPI) to the XGMII/SGMII. When set to 0, the MAC operates in normal mode. This bit is OR'ed with the reg_lowp_ena pin. */ + unsigned int msmSystemTxLowPowerIdleEnable : 1; /* 1E.6005.7 R/W Default = 0x0 */ + /* 1 = Transmit LPI enable + */ + unsigned int reserved0 : 8; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemGeneralControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System FIFO Control Register: 1E.600E */ +/* MSM System FIFO Control Register: 1E.600E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.600E.7:0 R/W MSM System Rx FIFO Full Threshold [7:0] + AQ_MsmSystemFifoControlRegister_HHD.u0.bits_0.msmSystemRxFifoFullThreshold + + Default = 0x08 + + Rx FIFO full threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmSystemRxFifoFullThreshold : 8; /* 1E.600E.7:0 R/W Default = 0x08 */ + /* Rx FIFO full threshold */ + unsigned int reserved0 : 8; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.600F.7:0 R/W MSM System Rx FIFO Empty Threshold [7:0] + AQ_MsmSystemFifoControlRegister_HHD.u1.bits_1.msmSystemRxFifoEmptyThreshold + + Default = 0x00 + + Rx FIFO empty threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmSystemRxFifoEmptyThreshold : 8; /* 1E.600F.7:0 R/W Default = 0x00 */ + /* Rx FIFO empty threshold */ + unsigned int reserved0 : 8; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of MSM System FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.6010.5:0 R/W MSM System Tx FIFO Full Threshold [5:0] + AQ_MsmSystemFifoControlRegister_HHD.u2.bits_2.msmSystemTxFifoFullThreshold + + Default = 0x08 + + Tx FIFO full threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmSystemTxFifoFullThreshold : 6; /* 1E.6010.5:0 R/W Default = 0x08 */ + /* Tx FIFO full threshold */ + unsigned int reserved0 : 10; + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of MSM System FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.6011.5:0 R/W MSM System Tx FIFO Empty Threshold [5:0] + AQ_MsmSystemFifoControlRegister_HHD.u3.bits_3.msmSystemTxFifoEmptyThreshold + + Default = 0x00 + + Tx FIFO empty threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmSystemTxFifoEmptyThreshold : 6; /* 1E.6011.5:0 R/W Default = 0x00 */ + /* Tx FIFO empty threshold */ + unsigned int reserved0 : 10; + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of MSM System FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.6012.7:0 ROS MSM System Rx FIFO Almost Full Threshold [7:0] + AQ_MsmSystemFifoControlRegister_HHD.u4.bits_4.msmSystemRxFifoAlmostFullThreshold + + Default = 0x00 + + Rx FIFO almost full threshold + + Notes: + Unused. */ + unsigned int msmSystemRxFifoAlmostFullThreshold : 8; /* 1E.6012.7:0 ROS Default = 0x00 */ + /* Rx FIFO almost full threshold */ + unsigned int reserved0 : 8; + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of MSM System FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.6013.7:0 ROS MSM System Rx FIFO Almost Empty Threshold [7:0] + AQ_MsmSystemFifoControlRegister_HHD.u5.bits_5.msmSystemRxFifoAlmostEmptyThreshold + + Default = 0x00 + + Rx FIFO almost empty threshold + + Notes: + Unused. */ + unsigned int msmSystemRxFifoAlmostEmptyThreshold : 8; /* 1E.6013.7:0 ROS Default = 0x00 */ + /* Rx FIFO almost empty threshold */ + unsigned int reserved0 : 8; + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of MSM System FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.6014.7:0 ROS MSM System Tx FIFO Almost Full Threshold [7:0] + AQ_MsmSystemFifoControlRegister_HHD.u6.bits_6.msmSystemTxFifoAlmostFullThreshold + + Default = 0x00 + + Tx FIFO almost full threshold + + Notes: + Unused. */ + unsigned int msmSystemTxFifoAlmostFullThreshold : 8; /* 1E.6014.7:0 ROS Default = 0x00 */ + /* Tx FIFO almost full threshold */ + unsigned int reserved0 : 8; + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of MSM System FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.6015.7:0 ROS MSM System Tx FIFO Almost Empty Threshold [7:0] + AQ_MsmSystemFifoControlRegister_HHD.u7.bits_7.msmSystemTxFifoAlmostEmptyThreshold + + Default = 0x00 + + Tx FIFO almost empty threshold + + Notes: + Unused. */ + unsigned int msmSystemTxFifoAlmostEmptyThreshold : 8; /* 1E.6015.7:0 ROS Default = 0x00 */ + /* Tx FIFO almost empty threshold */ + unsigned int reserved0 : 8; + } bits_7; + uint16_t word_7; + } u7; +} AQ_MsmSystemFifoControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System General Status Register: 1E.6020 */ +/* MSM System General Status Register: 1E.6020 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System General Status Register */ + union + { + struct + { + /*! \brief 1E.6020.0 BLH MSM System Rx Local Fault + AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemRxLocalFault + + + + Rx local fault detected + + Notes: + Latch high local fault status. Set to 1, whent he MAC detects Rx local fault sequences on the Rx interface. Reset to 0 after read and after reset. */ + unsigned int msmSystemRxLocalFault : 1; /* 1E.6020.0 BLH */ + /* Rx local fault detected */ + /*! \brief 1E.6020.1 BLH MSM System Rx Remote Fault + AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemRxRemoteFault + + + + Rx remote fault detected + + Notes: + Latch high local fault status. Set to 1, whent he MAC detects Rx local fault sequences on the Rx interface. Reset to 0 after read and after reset. */ + unsigned int msmSystemRxRemoteFault : 1; /* 1E.6020.1 BLH */ + /* Rx remote fault detected */ + /*! \brief 1E.6020.2 RO MSM System PHY Loss of Signal + AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemPhyLossOfSignal + + + + PHY loss of signal + + Notes: + PHY indicates loss of signal. This is the value of pin phy_los which is tied to 0. */ + unsigned int msmSystemPhyLossOfSignal : 1; /* 1E.6020.2 RO */ + /* PHY loss of signal */ + /*! \brief 1E.6020.3 R/W MSM System Timestamp Available + AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemTimestampAvailable + + Default = 0x0 + + Timestamp available + + Notes: + Transmit timestamp available. Indicates that the timestamp of the last transmitted event frame (which had ff_tx_ts_frm=1) is available in the register See MAC Time Stamp Status 0 [F:0] and See MAC Time Stamp Status 1 [F:0] . To clear this bit, the bit must be written with a 1. + */ + unsigned int msmSystemTimestampAvailable : 1; /* 1E.6020.3 R/W Default = 0x0 */ + /* Timestamp available */ + /*! \brief 1E.6020.4 RO MSM System Rx Low Power IDLE + AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemRxLowPowerIdle + + + + Rx LPI detected + + Notes: + Receive low power IDLE (LPI). Set to 1 when LPI is currently detected on the MAC Rx interface. Set to 0, when the MAC currently operates in normal mode. */ + unsigned int msmSystemRxLowPowerIdle : 1; /* 1E.6020.4 RO */ + /* Rx LPI detected */ + /*! \brief 1E.6020.5 RO MSM System Tx FIFO Empty + AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemTxFifoEmpty + + + + Tx FIFO empty + + Notes: + When set to 1, indicates the Tx FIFO is empty. When set to 0, Tx FIFO is non-empty. */ + unsigned int msmSystemTxFifoEmpty : 1; /* 1E.6020.5 RO */ + /* Tx FIFO empty */ + unsigned int reserved0 : 10; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System General Status Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemGeneralStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx IPG Control Register: 1E.6022 */ +/* MSM System Tx IPG Control Register: 1E.6022 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx IPG Control Register */ + union + { + struct + { + /*! \brief 1E.6022.5:0 R/W MSM System Tx IPG Length [5:0] + AQ_MsmSystemTxIpgControlRegister_HHD.u0.bits_0.msmSystemTxIpgLength + + Default = 0x0C + + Tx IPG length + + Notes: + Tx inter-packet gap (IPG) value. Depending on LAN or WAN mode of operation. + LAN Mode : Number of octets in steps of 4. Valid values are 8, 12, 16,..., 100. DIC is supported for any setting > 8. A default of 12 must be set to conform to IEEE802.3ae. + WAN Mode : Stretch factor. Valid values are 4 ... 15. The stretch factor is calculated as (value+1)*8. A default of 12 must be set to conform to IEEE802.3ae (i.e. 13*8=104). A larger value shrinks the IPG (increasing bandwidth). + The reset value of 12 leads to IEEE802.3ae conformant behavior in both modes. + Note : WAN mode is only available in 10G mode of operation. */ + unsigned int msmSystemTxIpgLength : 6; /* 1E.6022.5:0 R/W Default = 0x0C */ + /* Tx IPG length */ + unsigned int reserved0 : 10; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx IPG Control Register */ + union + { + struct + { + /*! \brief 1E.6023.F:0 MSM System Tx IPG Reserved + AQ_MsmSystemTxIpgControlRegister_HHD.u1.bits_1.msmSystemTxIpgReserved + + + + Value always 0, writes ignored + */ + unsigned int msmSystemTxIpgReserved : 16; /* 1E.6023.F:0 */ + /* Value always 0, writes ignored */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxIpgControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx Good Frames Counter Register: 1E.6040 */ +/* MSM System Tx Good Frames Counter Register: 1E.6040 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6040.F:0 ROS MSM System Tx Good Frames Counter 0 [F:0] + AQ_MsmSystemTxGoodFramesCounterRegister_HHD.u0.bits_0.msmSystemTxGoodFramesCounter_0 + + Default = 0x0000 + + Tx good frame counter bits 15:0 + + Notes: + Count of frames transmitted without error (Including pause frames). */ + unsigned int msmSystemTxGoodFramesCounter_0 : 16; /* 1E.6040.F:0 ROS Default = 0x0000 */ + /* Tx good frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6041.F:0 ROS MSM System Tx Good Frames Counter 1 [F:0] + AQ_MsmSystemTxGoodFramesCounterRegister_HHD.u1.bits_1.msmSystemTxGoodFramesCounter_1 + + Default = 0x0000 + + Tx good frame counter bits 31:16 + + + Notes: + Count of frames transmitted without error (Including pause frames). */ + unsigned int msmSystemTxGoodFramesCounter_1 : 16; /* 1E.6041.F:0 ROS Default = 0x0000 */ + /* Tx good frame counter bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxGoodFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Good Frames Counter Register: 1E.6044 */ +/* MSM System Rx Good Frames Counter Register: 1E.6044 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6044.F:0 ROS MSM System Rx Good Frames Counter 0 [F:0] + AQ_MsmSystemRxGoodFramesCounterRegister_HHD.u0.bits_0.msmSystemRxGoodFramesCounter_0 + + Default = 0x0000 + + Rx good frame counter bits 15:0 + + Notes: + Count of frames received without error (Including pause frames). */ + unsigned int msmSystemRxGoodFramesCounter_0 : 16; /* 1E.6044.F:0 ROS Default = 0x0000 */ + /* Rx good frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6045.F:0 ROS MSM System Rx Good Frames Counter 1 [F:0] + AQ_MsmSystemRxGoodFramesCounterRegister_HHD.u1.bits_1.msmSystemRxGoodFramesCounter_1 + + Default = 0x0000 + + Rx good frame counter bits 31:16 + + Notes: + Count of frames received without error (Including pause frames). */ + unsigned int msmSystemRxGoodFramesCounter_1 : 16; /* 1E.6045.F:0 ROS Default = 0x0000 */ + /* Rx good frame counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxGoodFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx FCS Errors Counter Register: 1E.6048 */ +/* MSM System Rx FCS Errors Counter Register: 1E.6048 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx FCS Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.6048.F:0 ROS MSM System FCS Error Counter 0 [F:0] + AQ_MsmSystemRxFcsErrorsCounterRegister_HHD.u0.bits_0.msmSystemFcsErrorCounter_0 + + Default = 0x0000 + + Frame check sequence error counter bits 15:0 + + Notes: + Count of frames for which a CRC-32 Error is detected but the frame is otherwise of correct length. */ + unsigned int msmSystemFcsErrorCounter_0 : 16; /* 1E.6048.F:0 ROS Default = 0x0000 */ + /* Frame check sequence error counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx FCS Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.6049.F:0 ROS MSM System FCS Error Counter 1 [F:0] + AQ_MsmSystemRxFcsErrorsCounterRegister_HHD.u1.bits_1.msmSystemFcsErrorCounter_1 + + Default = 0x0000 + + Frame check sequence error counter bits 31:16 + + Notes: + Count of frames for which a CRC-32 Error is detected but the frame is otherwise of correct length. */ + unsigned int msmSystemFcsErrorCounter_1 : 16; /* 1E.6049.F:0 ROS Default = 0x0000 */ + /* Frame check sequence error counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxFcsErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Alignment Errors Counter Register: 1E.604C */ +/* MSM System Rx Alignment Errors Counter Register: 1E.604C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Alignment Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.604C.F:0 ROS MSM System Alignment Error Counter 0 [F:0] + AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD.u0.bits_0.msmSystemAlignmentErrorCounter_0 + + Default = 0x0000 + + Alignment error counter bits 15:0 + + Notes: + Count of frames received with an alignment error. */ + unsigned int msmSystemAlignmentErrorCounter_0 : 16; /* 1E.604C.F:0 ROS Default = 0x0000 */ + /* Alignment error counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Alignment Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.604D.F:0 ROS MSM System Alignment Error Counter 1 [F:0] + AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD.u1.bits_1.msmSystemAlignmentErrorCounter_1 + + Default = 0x0000 + + Alignment error counter bits 31:16 + + Notes: + Count of frames received with an alignment error. */ + unsigned int msmSystemAlignmentErrorCounter_1 : 16; /* 1E.604D.F:0 ROS Default = 0x0000 */ + /* Alignment error counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx Pause Frames Counter Register: 1E.6050 */ +/* MSM System Tx Pause Frames Counter Register: 1E.6050 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6050.F:0 ROS MSM System Tx Pause Frames Counter 0 [F:0] + AQ_MsmSystemTxPauseFramesCounterRegister_HHD.u0.bits_0.msmSystemTxPauseFramesCounter_0 + + Default = 0x0000 + + Tx pause frame counter bits 15:0 + + Notes: + Valid pause frames transmitted. */ + unsigned int msmSystemTxPauseFramesCounter_0 : 16; /* 1E.6050.F:0 ROS Default = 0x0000 */ + /* Tx pause frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6051.F:0 ROS MSM System Tx Pause Frames Counter 1 [F:0] + AQ_MsmSystemTxPauseFramesCounterRegister_HHD.u1.bits_1.msmSystemTxPauseFramesCounter_1 + + Default = 0x0000 + + Tx pause frame counter bits 31:16 + + + Notes: + Valid pause frames transmitted. */ + unsigned int msmSystemTxPauseFramesCounter_1 : 16; /* 1E.6051.F:0 ROS Default = 0x0000 */ + /* Tx pause frame counter bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxPauseFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Pause Frames Counter Register: 1E.6054 */ +/* MSM System Rx Pause Frames Counter Register: 1E.6054 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6054.F:0 ROS MSM System Rx Pause Frames Counter 0 [F:0] + AQ_MsmSystemRxPauseFramesCounterRegister_HHD.u0.bits_0.msmSystemRxPauseFramesCounter_0 + + Default = 0x0000 + + Rx pause frame counter bits 15:0 + + Notes: + Valid pause frames received. */ + unsigned int msmSystemRxPauseFramesCounter_0 : 16; /* 1E.6054.F:0 ROS Default = 0x0000 */ + /* Rx pause frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6055.F:0 ROS MSM System Rx Pause Frames Counter 1 [F:0] + AQ_MsmSystemRxPauseFramesCounterRegister_HHD.u1.bits_1.msmSystemRxPauseFramesCounter_1 + + Default = 0x0000 + + Rx pause frame counter bits 31:16 + + Notes: + Valid pause frames received. */ + unsigned int msmSystemRxPauseFramesCounter_1 : 16; /* 1E.6055.F:0 ROS Default = 0x0000 */ + /* Rx pause frame counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxPauseFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Too Long Errors Counter Register: 1E.6058 */ +/* MSM System Rx Too Long Errors Counter Register: 1E.6058 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Too Long Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.6058.F:0 ROS MSM System Rx Too Long Errors Counter 0 [F:0] + AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD.u0.bits_0.msmSystemRxTooLongErrorsCounter_0 + + Default = 0x0000 + + Too-long errors counter bits 15:0 + + Notes: + Frame received exceeded the maximum length programmed with register FRM_LGTH. */ + unsigned int msmSystemRxTooLongErrorsCounter_0 : 16; /* 1E.6058.F:0 ROS Default = 0x0000 */ + /* Too-long errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Too Long Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.6059.F:0 ROS MSM System Rx Too Long Errors Counter 1 [F:0] + AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD.u1.bits_1.msmSystemRxTooLongErrorsCounter_1 + + Default = 0x0000 + + Too-long errors counter bits 31:16 + + Notes: + Frame received exceeded the maximum length programmed with register FRM_LGTH. */ + unsigned int msmSystemRxTooLongErrorsCounter_1 : 16; /* 1E.6059.F:0 ROS Default = 0x0000 */ + /* Too-long errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx In Range Length Errors Counter Register: 1E.605C */ +/* MSM System Rx In Range Length Errors Counter Register: 1E.605C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx In Range Length Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.605C.F:0 ROS MSM System Rx In Range Length Errors Counter 0 [F:0] + AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD.u0.bits_0.msmSystemRxInRangeLengthErrorsCounter_0 + + Default = 0x0000 + + In-range-length errors counter bits 15:0 + + Notes: + A count of frames with a length/type field value between 46 (VLAN: 42) and less than 0x0600, that does not match the number of payload data octets received. Should count also if length/type field is less than 46 (VLAN: 42) and the frame is longer than 64 bytes. */ + unsigned int msmSystemRxInRangeLengthErrorsCounter_0 : 16; /* 1E.605C.F:0 ROS Default = 0x0000 */ + /* In-range-length errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx In Range Length Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.605D.F:0 ROS MSM System Rx In Range Length Errors Counter 1 [F:0] + AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD.u1.bits_1.msmSystemRxInRangeLengthErrorsCounter_1 + + Default = 0x0000 + + In-range-length errors counter bits 31:16 + + Notes: + A count of frames with a length/type field value between 46 (VLAN: 42) and less than 0x0600, that does not match the number of payload data octets received. Should count also if length/type field is less than 46 (VLAN: 42) and the frame is longer than 64 bytes. */ + unsigned int msmSystemRxInRangeLengthErrorsCounter_1 : 16; /* 1E.605D.F:0 ROS Default = 0x0000 */ + /* In-range-length errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx VLAN Frames Counter Register: 1E.6060 */ +/* MSM System Tx VLAN Frames Counter Register: 1E.6060 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6060.F:0 ROS MSM System Tx VLAN Frames Counter 0 [F:0] + AQ_MsmSystemTxVlanFramesCounterRegister_HHD.u0.bits_0.msmSystemTxVlanFramesCounter_0 + + Default = 0x0000 + + Tx VLAN frames counter bits 15:0 + + Notes: + Valid VLAN tagged frames transmitted. */ + unsigned int msmSystemTxVlanFramesCounter_0 : 16; /* 1E.6060.F:0 ROS Default = 0x0000 */ + /* Tx VLAN frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6061.F:0 ROS MSM System Tx VLAN Frames Counter 1 [F:0] + AQ_MsmSystemTxVlanFramesCounterRegister_HHD.u1.bits_1.msmSystemTxVlanFramesCounter_1 + + Default = 0x0000 + + Tx VLAN frames counter bits 31:16 + + Notes: + Valid VLAN tagged frames transmitted. */ + unsigned int msmSystemTxVlanFramesCounter_1 : 16; /* 1E.6061.F:0 ROS Default = 0x0000 */ + /* Tx VLAN frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxVlanFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx VLAN Frames Counter Register: 1E.6064 */ +/* MSM System Rx VLAN Frames Counter Register: 1E.6064 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6064.F:0 ROS MSM System Rx VLAN Frames Counter 0 [F:0] + AQ_MsmSystemRxVlanFramesCounterRegister_HHD.u0.bits_0.msmSystemRxVlanFramesCounter_0 + + Default = 0x0000 + + Rx VLAN frames counter bits 15:0 + + Notes: + Valid VLAN tagged frames received. */ + unsigned int msmSystemRxVlanFramesCounter_0 : 16; /* 1E.6064.F:0 ROS Default = 0x0000 */ + /* Rx VLAN frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6065.F:0 ROS MSM System Rx VLAN Frames Counter 1 [F:0] + AQ_MsmSystemRxVlanFramesCounterRegister_HHD.u1.bits_1.msmSystemRxVlanFramesCounter_1 + + Default = 0x0000 + + Rx VLAN frames counter bits 31:16 + + Notes: + Valid VLAN tagged frames received. */ + unsigned int msmSystemRxVlanFramesCounter_1 : 16; /* 1E.6065.F:0 ROS Default = 0x0000 */ + /* Rx VLAN frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxVlanFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx Octets Counter Register: 1E.6068 */ +/* MSM System Tx Octets Counter Register: 1E.6068 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.6068.F:0 ROS MSM System Tx Octets Counter 0 [F:0] + AQ_MsmSystemTxOctetsCounterRegister_HHD.u0.bits_0.msmSystemTxOctetsCounter_0 + + Default = 0x0000 + + Tx octets counter bits 15:0 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmSystemTxOctetsCounter_0 : 16; /* 1E.6068.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.6069.F:0 ROS MSM System Tx Octets Counter 1 [F:0] + AQ_MsmSystemTxOctetsCounterRegister_HHD.u1.bits_1.msmSystemTxOctetsCounter_1 + + Default = 0x0000 + + Tx octets counter bits 31:16 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmSystemTxOctetsCounter_1 : 16; /* 1E.6069.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of MSM System Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.606A.F:0 ROS MSM System Tx Octets Counter 2 [F:0] + AQ_MsmSystemTxOctetsCounterRegister_HHD.u2.bits_2.msmSystemTxOctetsCounter_2 + + Default = 0x0000 + + Tx octets counter bits 47:32 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmSystemTxOctetsCounter_2 : 16; /* 1E.606A.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 47:32 */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of MSM System Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.606B.F:0 ROS MSM System Tx Octets Counter 3 [F:0] + AQ_MsmSystemTxOctetsCounterRegister_HHD.u3.bits_3.msmSystemTxOctetsCounter_3 + + Default = 0x0000 + + Tx octets counter bits 63:48 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmSystemTxOctetsCounter_3 : 16; /* 1E.606B.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 63:48 */ + } bits_3; + uint16_t word_3; + } u3; +} AQ_MsmSystemTxOctetsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Octets Counter Register: 1E.606C */ +/* MSM System Rx Octets Counter Register: 1E.606C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.606C.F:0 ROS MSM System Rx Octets Counter 0 [F:0] + AQ_MsmSystemRxOctetsCounterRegister_HHD.u0.bits_0.msmSystemRxOctetsCounter_0 + + Default = 0x0000 + + Rx octets counter bits 15:0 + + Notes: + All octets received except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames received. */ + unsigned int msmSystemRxOctetsCounter_0 : 16; /* 1E.606C.F:0 ROS Default = 0x0000 */ + /* Rx octets counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.606D.F:0 ROS MSM System Rx Octets Counter 1 [F:0] + AQ_MsmSystemRxOctetsCounterRegister_HHD.u1.bits_1.msmSystemRxOctetsCounter_1 + + Default = 0x0000 + + Rx octets counter bits 31:16 + + Notes: + All octets received except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames received. */ + unsigned int msmSystemRxOctetsCounter_1 : 16; /* 1E.606D.F:0 ROS Default = 0x0000 */ + /* Rx octets counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxOctetsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Unicast Frames Counter Register: 1E.6070 */ +/* MSM System Rx Unicast Frames Counter Register: 1E.6070 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6070.F:0 ROS MSM System Rx Unicast Frames Counter 0 [F:0] + AQ_MsmSystemRxUnicastFramesCounterRegister_HHD.u0.bits_0.msmSystemRxUnicastFramesCounter_0 + + Default = 0x0000 + + Rx unicast frames counter bits 15:0 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '0'. */ + unsigned int msmSystemRxUnicastFramesCounter_0 : 16; /* 1E.6070.F:0 ROS Default = 0x0000 */ + /* Rx unicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6071.F:0 ROS MSM System Rx Unicast Frames Counter 1 [F:0] + AQ_MsmSystemRxUnicastFramesCounterRegister_HHD.u1.bits_1.msmSystemRxUnicastFramesCounter_1 + + Default = 0x0000 + + Rx unicast frames counter bits 31:16 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '0'. */ + unsigned int msmSystemRxUnicastFramesCounter_1 : 16; /* 1E.6071.F:0 ROS Default = 0x0000 */ + /* Rx unicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxUnicastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Multicast Frames Counter Register: 1E.6074 */ +/* MSM System Rx Multicast Frames Counter Register: 1E.6074 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6074.F:0 ROS MSM System Rx Multicast Frames Counter 0 [F:0] + AQ_MsmSystemRxMulticastFramesCounterRegister_HHD.u0.bits_0.msmSystemRxMulticastFramesCounter_0 + + Default = 0x0000 + + Rx multicast frames counter bits 15:0 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '1' but not the broadcast address (all bits set '1' ). Pause frames are not counted. */ + unsigned int msmSystemRxMulticastFramesCounter_0 : 16; /* 1E.6074.F:0 ROS Default = 0x0000 */ + /* Rx multicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6075.F:0 ROS MSM System Rx Multicast Frames Counter 1 [F:0] + AQ_MsmSystemRxMulticastFramesCounterRegister_HHD.u1.bits_1.msmSystemRxMulticastFramesCounter_1 + + Default = 0x0000 + + Rx multicast frames counter bits 31:16 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '1' but not the broadcast address (all bits set '1' ). Pause frames are not counted. */ + unsigned int msmSystemRxMulticastFramesCounter_1 : 16; /* 1E.6075.F:0 ROS Default = 0x0000 */ + /* Rx multicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxMulticastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Broadcast Frames Counter Register: 1E.6078 */ +/* MSM System Rx Broadcast Frames Counter Register: 1E.6078 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6078.F:0 ROS MSM System Rx Broadcast Frames Counter 0 [F:0] + AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD.u0.bits_0.msmSystemRxBroadcastFramesCounter_0 + + Default = 0x0000 + + Rx broadcast frames counter bits 15:0 + + Notes: + Incremented with each valid frame received on the receive FIFO interface (FIFO) and all bits of the destination address were set '1'. */ + unsigned int msmSystemRxBroadcastFramesCounter_0 : 16; /* 1E.6078.F:0 ROS Default = 0x0000 */ + /* Rx broadcast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6079.F:0 ROS MSM System Rx Broadcast Frames Counter 1 [F:0] + AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD.u1.bits_1.msmSystemRxBroadcastFramesCounter_1 + + Default = 0x0000 + + Rx broadcast frames counter bits 31:16 + + Notes: + Incremented with each valid frame received on the receive FIFO interface (FIFO) and all bits of the destination address were set '1'. */ + unsigned int msmSystemRxBroadcastFramesCounter_1 : 16; /* 1E.6079.F:0 ROS Default = 0x0000 */ + /* Rx broadcast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx Errors Counter Register: 1E.607C */ +/* MSM System Tx Errors Counter Register: 1E.607C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.607C.F:0 ROS MSM System Tx Errors Counter 0 [F:0] + AQ_MsmSystemTxErrorsCounterRegister_HHD.u0.bits_0.msmSystemTxErrorsCounter_0 + + Default = 0x0000 + + Rx errors counter bits 15:0 + + Notes: + Number of frames transmitted with error: + - FIFO Overflow Errors + - FIFO Underflow Errors */ + unsigned int msmSystemTxErrorsCounter_0 : 16; /* 1E.607C.F:0 ROS Default = 0x0000 */ + /* Rx errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.607D.F:0 ROS MSM System Tx Errors Counter 1 [F:0] + AQ_MsmSystemTxErrorsCounterRegister_HHD.u1.bits_1.msmSystemTxErrorsCounter_1 + + Default = 0x0000 + + Tx errors counter bits 31:16 + + Notes: + Number of frames transmitted with error: + - FIFO Overflow Errors + - FIFO Underflow Errors */ + unsigned int msmSystemTxErrorsCounter_1 : 16; /* 1E.607D.F:0 ROS Default = 0x0000 */ + /* Tx errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx Unicast Frames Counter Register: 1E.6084 */ +/* MSM System Tx Unicast Frames Counter Register: 1E.6084 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6084.F:0 ROS MSM System Tx Unicast Frames Counter 0 [F:0] + AQ_MsmSystemTxUnicastFramesCounterRegister_HHD.u0.bits_0.msmSystemTxUnicastFramesCounter_0 + + Default = 0x0000 + + Tx unicast frames counter bits 15:0 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '0'. */ + unsigned int msmSystemTxUnicastFramesCounter_0 : 16; /* 1E.6084.F:0 ROS Default = 0x0000 */ + /* Tx unicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6085.F:0 ROS MSM System Tx Unicast Frames Counter 1 [F:0] + AQ_MsmSystemTxUnicastFramesCounterRegister_HHD.u1.bits_1.msmSystemTxUnicastFramesCounter_1 + + Default = 0x0000 + + Tx unicast frames counter bits 31:16 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '0'. */ + unsigned int msmSystemTxUnicastFramesCounter_1 : 16; /* 1E.6085.F:0 ROS Default = 0x0000 */ + /* Tx unicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxUnicastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx Multicast Frames Counter Register: 1E.6088 */ +/* MSM System Tx Multicast Frames Counter Register: 1E.6088 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6088.F:0 ROS MSM System Tx Multicast Frames Counter 0 [F:0] + AQ_MsmSystemTxMulticastFramesCounterRegister_HHD.u0.bits_0.msmSystemTxMulticastFramesCounter_0 + + Default = 0x0000 + + Tx multicast frames counter bits 15:0 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '1' but not the broadcast address (all bits '1'). */ + unsigned int msmSystemTxMulticastFramesCounter_0 : 16; /* 1E.6088.F:0 ROS Default = 0x0000 */ + /* Tx multicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6089.F:0 ROS MSM System Tx Multicast Frames Counter 1 [F:0] + AQ_MsmSystemTxMulticastFramesCounterRegister_HHD.u1.bits_1.msmSystemTxMulticastFramesCounter_1 + + Default = 0x0000 + + Tx multicast frames counter bits 31:16 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '1' but not the broadcast address (all bits '1'). */ + unsigned int msmSystemTxMulticastFramesCounter_1 : 16; /* 1E.6089.F:0 ROS Default = 0x0000 */ + /* Tx multicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxMulticastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx Broadcast Frames Counter Register: 1E.608C */ +/* MSM System Tx Broadcast Frames Counter Register: 1E.608C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.608C.F:0 ROS MSM System Tx Broadcast Frames Counter 0 [F:0] + AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD.u0.bits_0.msmSystemTxBroadcastFramesCounter_0 + + Default = 0x0000 + + Tx broadcast frames counter bits 15:0 + + Notes: + Incremented with each frame written to the FIFO interface and all bits of the destination address set to '1'. */ + unsigned int msmSystemTxBroadcastFramesCounter_0 : 16; /* 1E.608C.F:0 ROS Default = 0x0000 */ + /* Tx broadcast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.608D.F:0 ROS MSM System Tx Broadcast Frames Counter 1 [F:0] + AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD.u1.bits_1.msmSystemTxBroadcastFramesCounter_1 + + Default = 0x0000 + + Tx broadcast frames counter bits 31:16 + + Notes: + Incremented with each frame written to the FIFO interface and all bits of the destination address set to '1'. */ + unsigned int msmSystemTxBroadcastFramesCounter_1 : 16; /* 1E.608D.F:0 ROS Default = 0x0000 */ + /* Tx broadcast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Errors Counter Register: 1E.60C8 */ +/* MSM System Rx Errors Counter Register: 1E.60C8 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.60C8.F:0 ROS MSM System Rx Errors Counter 0 [F:0] + AQ_MsmSystemRxErrorsCounterRegister_HHD.u0.bits_0.msmSystemRxErrorsCounter_0 + + Default = 0x0000 + + Rx errors counter bits 15:0 + + Notes: + Number of frames received with error: + - FIFO Overflow Errors + - CRC Errors + - Payload Length Errors + - Jabber and Oversized Errors + - Alignment Errors + - The dedicated Error Code (0xfe, not a code error) was received */ + unsigned int msmSystemRxErrorsCounter_0 : 16; /* 1E.60C8.F:0 ROS Default = 0x0000 */ + /* Rx errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.60C9.F:0 ROS MSM System Rx Errors Counter 1 [F:0] + AQ_MsmSystemRxErrorsCounterRegister_HHD.u1.bits_1.msmSystemRxErrorsCounter_1 + + Default = 0x0000 + + Rx errors counter bits 31:16 + + Notes: + Number of frames received with error: + - FIFO Overflow Errors + - CRC Errors + - Payload Length Errors + - Jabber and Oversized Errors + - Alignment Errors + - The dedicated Error Code (0xfe, not a code error) was received */ + unsigned int msmSystemRxErrorsCounter_1 : 16; /* 1E.60C9.F:0 ROS Default = 0x0000 */ + /* Rx errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress VLAN TPID 0 Register: 1E.8006 */ +/* MSS Ingress VLAN TPID 0 Register: 1E.8006 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress VLAN TPID 0 Register */ + union + { + struct + { + /*! \brief 1E.8006.F:0 R/W MSS Ingress VLAN STag [F:0] + AQ_MssIngressVlanTpid_0Register_HHD.u0.bits_0.mssIngressVlanStag + + Default = 0x0000 + + STag TPID + + + Notes: + Service Tag Protocol Identifier (TPID) values to identify a VLAN tag. The " See SEC Egress VLAN CP Tag Parse STag " bit must be set to 1 for the incoming packet's TPID to be parsed. */ + unsigned int mssIngressVlanStag : 16; /* 1E.8006.F:0 R/W Default = 0x0000 */ + /* STag TPID + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress VLAN TPID 0 Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressVlanTpid_0Register_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress VLAN TPID 1 Register: 1E.8008 */ +/* MSS Ingress VLAN TPID 1 Register: 1E.8008 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress VLAN TPID 1 Register */ + union + { + struct + { + /*! \brief 1E.8008.F:0 R/W MSS Ingress VLAN QTag [F:0] + AQ_MssIngressVlanTpid_1Register_HHD.u0.bits_0.mssIngressVlanQtag + + Default = 0x0000 + + QTag TPID + + + Notes: + Customer Tag Protocol Identifier (TPID) values to identify a VLAN tag. The " See SEC Egress VLAN CP Tag Parse QTag " bit must be set to 1 for the incoming packet's TPID to be parsed. */ + unsigned int mssIngressVlanQtag : 16; /* 1E.8008.F:0 R/W Default = 0x0000 */ + /* QTag TPID + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress VLAN TPID 1 Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressVlanTpid_1Register_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress VLAN Control Register: 1E.800A */ +/* MSS Ingress VLAN Control Register: 1E.800A */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress VLAN Control Register */ + union + { + struct + { + /*! \brief 1E.800A.F:0 R/W MSS Ingress VLAN UP Map Table LSW [F:0] + AQ_MssIngressVlanControlRegister_HHD.u0.bits_0.mssIngressVlanUpMapTableLSW + + Default = 0x0000 + + Map table bits 15:0 + + + Notes: + If there is a customer TPID Tag match and no service TPID Tag match or the service TPID Tag match is disabled, the outer TAG's PCP is used to index into this map table to generate the packets user priority. + 2:0 : UP value for customer Tag PCP 0x0 + 5:3: UP value for customer Tag PCP 0x0 + 8:6 : UP value for customer Tag PCP 0x0 + 11:9 : UP value for customer Tag PCP 0x0 + 14:12 : UP value for customer Tag PCP 0x0 + 17:15 : UP value for customer Tag PCP 0x0 */ + unsigned int mssIngressVlanUpMapTableLSW : 16; /* 1E.800A.F:0 R/W Default = 0x0000 */ + /* Map table bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress VLAN Control Register */ + union + { + struct + { + /*! \brief 1E.800B.7:0 R/W MSS Ingress VLAN UP Map Table MSW [17:10] + AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanUpMapTableMSW + + Default = 0x00 + + UP Map table bits 23:16 + + + Notes: + If there is a customer TPID Tag match and no service TPID Tag match or the service TPID Tag match is disabled, the outer TAG's PCP is used to index into this map table to generate the packets user priority. + 2:0 : UP value for customer Tag PCP 0x0 + 5:3: UP value for customer Tag PCP 0x0 + 8:6 : UP value for customer Tag PCP 0x0 + 11:9 : UP value for customer Tag PCP 0x0 + 14:12 : UP value for customer Tag PCP 0x0 + 17:15 : UP value for customer Tag PCP 0x0 + 20:18 : UP value for customer Tag PCP 0x0 + 23:21 : UP value for customer Tag PCP 0x0 */ + unsigned int mssIngressVlanUpMapTableMSW : 8; /* 1E.800B.7:0 R/W Default = 0x00 */ + /* UP Map table bits 23:16 + */ + /*! \brief 1E.800B.A:8 R/W MSS Ingress VLAN UP Default [2:0] + AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanUpDefault + + Default = 0x0 + + UP default + + + Notes: + User priority default */ + unsigned int mssIngressVlanUpDefault : 3; /* 1E.800B.A:8 R/W Default = 0x0 */ + /* UP default + */ + /*! \brief 1E.800B.B R/W MSS Ingress VLAN STag UP Parse Enable + AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanStagUpParseEnable + + Default = 0x0 + + VLAN CP Tag STag UP enable + + + Notes: + Enable controlled port service VLAN service Tag user priority field parsing. */ + unsigned int mssIngressVlanStagUpParseEnable : 1; /* 1E.800B.B R/W Default = 0x0 */ + /* VLAN CP Tag STag UP enable + */ + /*! \brief 1E.800B.C R/W MSS Ingress VLAN QTag UP Parse Enable + AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanQtagUpParseEnable + + Default = 0x0 + + VLAN CP Tag QTag UP enable + + + Notes: + Enable controlled port customer VLAN customer Tag user priority field parsing. */ + unsigned int mssIngressVlanQtagUpParseEnable : 1; /* 1E.800B.C R/W Default = 0x0 */ + /* VLAN CP Tag QTag UP enable + */ + /*! \brief 1E.800B.D R/W MSS Ingress VLAN QinQ Parse Enable + AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanQinqParseEnable + + Default = 0x0 + + VLAN CP Tag Parse QinQ + + + Notes: + Enable controlled port VLAN QinQ Tag parsing. When this bit is set to 1 both the outer and inner VLAN Tags will be parsed. */ + unsigned int mssIngressVlanQinqParseEnable : 1; /* 1E.800B.D R/W Default = 0x0 */ + /* VLAN CP Tag Parse QinQ + */ + /*! \brief 1E.800B.E R/W MSS Ingress VLAN STag Parse Enable + AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanStagParseEnable + + Default = 0x0 + + 1 = Enable VLAN STag parsing + + + Notes: + Enable controlled port VLAN service Tag parsing. When this bit is set to 1, the incoming packets outer TPID will be compared with the configured " See MSS Ingress VLAN Stag [F:0] " for matching. If the " See SEC Egress VLAN CP Tag Parse QinQ " bit is set to1, this will also be used to compare the incoming packet's inner TPID. */ + unsigned int mssIngressVlanStagParseEnable : 1; /* 1E.800B.E R/W Default = 0x0 */ + /* 1 = Enable VLAN STag parsing + */ + /*! \brief 1E.800B.F R/W MSS Ingress VLAN QTag Parse Enable + AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanQtagParseEnable + + Default = 0x0 + + 1 = Enable VLAN QTag parsing + + + Notes: + Enable controlled port VLAN customer Tag parsing. When this bit is set to 1, the incoming packet's outer TPID will be compared with the configured " See MSS Ingress VLAN QTag [F:0] " for matching. If the " See SEC Egress VLAN CP Tag Parse QinQ " bit is set to1, this will also be used to compare the incoming packet's inner TPID. */ + unsigned int mssIngressVlanQtagParseEnable : 1; /* 1E.800B.F R/W Default = 0x0 */ + /* 1 = Enable VLAN QTag parsing + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressVlanControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress MTU Size Control Register: 1E.800C */ +/* MSS Ingress MTU Size Control Register: 1E.800C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress MTU Size Control Register */ + union + { + struct + { + /*! \brief 1E.800C.F:0 R/W MSS Ingress Controlled Packet MTU Size [F:0] + AQ_MssIngressMtuSizeControlRegister_HHD.u0.bits_0.mssIngressControlledPacketMtuSize + + Default = 0x05DC + + Maximum transmission unit for controlled packet + + + Notes: + Maximum transmission unit of controlled packet */ + unsigned int mssIngressControlledPacketMtuSize : 16; /* 1E.800C.F:0 R/W Default = 0x05DC */ + /* Maximum transmission unit for controlled packet + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress MTU Size Control Register */ + union + { + struct + { + /*! \brief 1E.800D.F:0 R/W MSS Ingress Uncontrolled Packet MTU Size [F:0] + AQ_MssIngressMtuSizeControlRegister_HHD.u1.bits_1.mssIngressUncontrolledPacketMtuSize + + Default = 0x05DC + + Maximum transmission unit for uncontrolled packet + + + Notes: + Maximum transmission unit of uncontrolled packet */ + unsigned int mssIngressUncontrolledPacketMtuSize : 16; /* 1E.800D.F:0 R/W Default = 0x05DC */ + /* Maximum transmission unit for uncontrolled packet + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressMtuSizeControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress Control Register: 1E.800E */ +/* MSS Ingress Control Register: 1E.800E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress Control Register */ + union + { + struct + { + /*! \brief 1E.800E.0 R/W MSS Ingress Soft Reset + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressSoftReset + + Default = 0x0 + + 1 = Soft reset + + + Notes: + S/W reset */ + unsigned int mssIngressSoftReset : 1; /* 1E.800E.0 R/W Default = 0x0 */ + /* 1 = Soft reset + */ + /*! \brief 1E.800E.1 R/W MSS Ingress Operation Point To Point + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressOperationPointToPoint + + Default = 0x0 + + 1 = Enable the SCI for authorization default + + + Notes: + The default SCI for authorization is configured in See MSS Ingress SCI Default [F:0] See MSS Ingress SCI Default [1F:10] , See MSS Ingress SCI Default [2F:20] , and See MSS Ingress SCI Default [3F:30] . */ + unsigned int mssIngressOperationPointToPoint : 1; /* 1E.800E.1 R/W Default = 0x0 */ + /* 1 = Enable the SCI for authorization default + */ + /*! \brief 1E.800E.2 R/W MSS Ingress Create SCI + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressCreateSci + + Default = 0x0 + + 0 = SCI from IGPRC LUT + + + Notes: + If the SCI is not in the packet and this bit is set to 0, the SCI will be taken from the IGPRC LUT. */ + unsigned int mssIngressCreateSci : 1; /* 1E.800E.2 R/W Default = 0x0 */ + /* 0 = SCI from IGPRC LUT + */ + /*! \brief 1E.800E.3 R/W MSS Ingress Mask Short Length Error + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressMaskShortLengthError + + Default = 0x0 + + Unused + + + Notes: + Unused */ + unsigned int mssIngressMaskShortLengthError : 1; /* 1E.800E.3 R/W Default = 0x0 */ + /* Unused + */ + /*! \brief 1E.800E.4 R/W MSS Ingress Drop Kay Packet + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressDropKayPacket + + Default = 0x0 + + 1 = Drop KaY packets + + + Notes: + Decides whether KaY packets have to be dropped */ + unsigned int mssIngressDropKayPacket : 1; /* 1E.800E.4 R/W Default = 0x0 */ + /* 1 = Drop KaY packets + */ + /*! \brief 1E.800E.5 R/W MSS Ingress Drop IGPRC Miss + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressDropIgprcMiss + + Default = 0x0 + + 1 = Drop IGPRC miss packets + + + Notes: + Decides whether Ingress Pre-Security Classification (IGPRC) LUT miss packets are to be dropped */ + unsigned int mssIngressDropIgprcMiss : 1; /* 1E.800E.5 R/W Default = 0x0 */ + /* 1 = Drop IGPRC miss packets + */ + /*! \brief 1E.800E.6 R/W MSS Ingress Check ICV + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressCheckIcv + + Default = 0x0 + + Unused + + + Notes: + Unused */ + unsigned int mssIngressCheckIcv : 1; /* 1E.800E.6 R/W Default = 0x0 */ + /* Unused + */ + /*! \brief 1E.800E.7 R/W MSS Ingress Clear Global Time + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressClearGlobalTime + + Default = 0x0 + + 1 = Clear global time + + + Notes: + Clear global time */ + unsigned int mssIngressClearGlobalTime : 1; /* 1E.800E.7 R/W Default = 0x0 */ + /* 1 = Clear global time + */ + /*! \brief 1E.800E.8 R/W MSS Ingress Clear Count + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressClearCount + + Default = 0x0 + + 1 = Clear all MIB counters + + + Notes: + If this bit is set to 1, all MIB counters will be cleared. */ + unsigned int mssIngressClearCount : 1; /* 1E.800E.8 R/W Default = 0x0 */ + /* 1 = Clear all MIB counters + */ + /*! \brief 1E.800E.9 R/W MSS Ingress High Priority + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressHighPriority + + Default = 0x0 + + 1 = MIB counter clear on read enable + + + Notes: + If this bit is set to 1, read is given high priority and the MIB count value becomes 0 after read. */ + unsigned int mssIngressHighPriority : 1; /* 1E.800E.9 R/W Default = 0x0 */ + /* 1 = MIB counter clear on read enable + */ + /*! \brief 1E.800E.A R/W MSS Ingress Remove SECTag + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressRemoveSectag + + Default = 0x0 + + 1 = Enable removal of SECTag + + + Notes: + If this bit is set and either of the following two conditions occurs, the SECTag will be removed. + Controlled packet and either the SA or SC is invalid. + IGPRC miss. */ + unsigned int mssIngressRemoveSectag : 1; /* 1E.800E.A R/W Default = 0x0 */ + /* 1 = Enable removal of SECTag + */ + /*! \brief 1E.800E.C:B R/W MSS Ingress Global Validate Frames [1:0] + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressGlobalValidateFrames + + Default = 0x0 + + Default validate frames configuration + + + Notes: + If the SC is invalid or if an IGPRC miss packet condition occurs, this default will be used for the validate frames configuration instead of the validate frame entry in the Ingress SC Table (IGSCT). */ + unsigned int mssIngressGlobalValidateFrames : 2; /* 1E.800E.C:B R/W Default = 0x0 */ + /* Default validate frames configuration + */ + /*! \brief 1E.800E.D R/W MSS Ingress ICV LSB 8 Bytes Enable + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressIcvLsb_8BytesEnable + + Default = 0x0 + + 1 = Use LSB + 0 = Use MSB + + + + Notes: + This bit selects MSB or LSB 8 bytes selection in the case where the ICV is 8 bytes. + 0 = MSB is used. */ + unsigned int mssIngressIcvLsb_8BytesEnable : 1; /* 1E.800E.D R/W Default = 0x0 */ + /* 1 = Use LSB + 0 = Use MSB + + */ + unsigned int reserved0 : 2; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress Control Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress SA Control Register: 1E.8010 */ +/* MSS Ingress SA Control Register: 1E.8010 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress SA Control Register */ + union + { + struct + { + /*! \brief 1E.8010.F:0 R/W MSS Ingress SA Threshold LSW [F:0] + AQ_MssIngressSaControlRegister_HHD.u0.bits_0.mssIngressSaThresholdLSW + + Default = 0x0000 + + SA threshold bits 15:0 + + + Notes: + Ingress PN threshold to generate SA threshold interrupt. */ + unsigned int mssIngressSaThresholdLSW : 16; /* 1E.8010.F:0 R/W Default = 0x0000 */ + /* SA threshold bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress SA Control Register */ + union + { + struct + { + /*! \brief 1E.8011.F:0 R/W MSS Ingress SA Threshold MSW [1F:10] + AQ_MssIngressSaControlRegister_HHD.u1.bits_1.mssIngressSaThresholdMSW + + Default = 0x0000 + + SA threshold bits 31:16 + + + Notes: + Ingress PN threshold to generate SA threshold interrupt. */ + unsigned int mssIngressSaThresholdMSW : 16; /* 1E.8011.F:0 R/W Default = 0x0000 */ + /* SA threshold bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressSaControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress Interrupt Status Register: 1E.802E */ +/* MSS Ingress Interrupt Status Register: 1E.802E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress Interrupt Status Register */ + union + { + struct + { + /*! \brief 1E.802E.0 COW MSS Master Ingress Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssMasterIngressInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when any one of the above interrupt and the corresponding interrupt enable are both set. The interrupt enable for this bit must also be set for this bit to be set. */ + unsigned int mssMasterIngressInterrupt : 1; /* 1E.802E.0 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.1 COW MSS Ingress SA Expired Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressSaExpiredInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when the SA PN reaches all ones saturation. */ + unsigned int mssIngressSaExpiredInterrupt : 1; /* 1E.802E.1 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.2 COW MSS Ingress SA Threshold Expired Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressSaThresholdExpiredInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when the SA PN reaches the See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . */ + unsigned int mssIngressSaThresholdExpiredInterrupt : 1; /* 1E.802E.2 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.3 COW MSS Ingress ICV Error Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressIcvErrorInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. */ + unsigned int mssIngressIcvErrorInterrupt : 1; /* 1E.802E.3 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.4 COW MSS Ingress Replay Error Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressReplayErrorInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. */ + unsigned int mssIngressReplayErrorInterrupt : 1; /* 1E.802E.4 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.5 COW MSS Ingress MIB Saturation Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressMibSaturationInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when the MIB counters reaches all ones saturation. */ + unsigned int mssIngressMibSaturationInterrupt : 1; /* 1E.802E.5 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.6 COW MSS Ingress ECC Error Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressEccErrorInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. */ + unsigned int mssIngressEccErrorInterrupt : 1; /* 1E.802E.6 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.7 COW MSS Ingress TCI E/C Error Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressTciE_cErrorInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This error occurs when the TCI E bit is 1 and the TCI C bit is 0. The packet is not dropped, uncontrolled, or untagged. */ + unsigned int mssIngressTciE_cErrorInterrupt : 1; /* 1E.802E.7 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.8 COW MSS Ingress IGPOC Miss Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressIgpocMissInterrupt + + Default = 0x0 + + 1 = Interrupt + + */ + unsigned int mssIngressIgpocMissInterrupt : 1; /* 1E.802E.8 COW Default = 0x0 */ + /* 1 = Interrupt + */ + unsigned int reserved0 : 7; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress Interrupt Status Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressInterruptStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress Interrupt Mask Register: 1E.8030 */ +/* MSS Ingress Interrupt Mask Register: 1E.8030 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress Interrupt Mask Register */ + union + { + struct + { + /*! \brief 1E.8030.0 R/W MSS Ingress Master Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressMasterInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressMasterInterruptEnable : 1; /* 1E.8030.0 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.1 R/W MSS Ingress SA Expired Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressSaExpiredInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressSaExpiredInterruptEnable : 1; /* 1E.8030.1 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.2 R/W MSS Ingress SA Threshold Expired Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressSaThresholdExpiredInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressSaThresholdExpiredInterruptEnable : 1; /* 1E.8030.2 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.3 R/W MSS Ingress ICV Error Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressIcvErrorInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressIcvErrorInterruptEnable : 1; /* 1E.8030.3 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.4 R/W MSS Ingress Replay Error Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressReplayErrorInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressReplayErrorInterruptEnable : 1; /* 1E.8030.4 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.5 R/W MSS Ingress MIB Saturation Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressMibSaturationInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressMibSaturationInterruptEnable : 1; /* 1E.8030.5 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.6 R/W MSS Ingress ECC Error Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressEccErrorInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressEccErrorInterruptEnable : 1; /* 1E.8030.6 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.7 R/W MSS Ingress TCI E/C Error Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressTciE_cErrorInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressTciE_cErrorInterruptEnable : 1; /* 1E.8030.7 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.8 R/W MSS Ingress IGPOC Miss Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressIgpocMissInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressIgpocMissInterruptEnable : 1; /* 1E.8030.8 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + unsigned int reserved0 : 7; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress Interrupt Mask Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressInterruptMaskRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress SA ICV Error Status Register: 1E.8032 */ +/* MSS Ingress SA ICV Error Status Register: 1E.8032 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress SA ICV Error Status Register */ + union + { + struct + { + /*! \brief 1E.8032.F:0 COW MSS Ingress SA ICV Error LSW [F:0] + AQ_MssIngressSaIcvErrorStatusRegister_HHD.u0.bits_0.mssIngressSaIcvErrorLSW + + Default = 0x0000 + + SA ICV error bits 15:0 + + + Notes: + When set, these bits identify the SA that has an ICV error. Write these bits to 1 to clear. */ + unsigned int mssIngressSaIcvErrorLSW : 16; /* 1E.8032.F:0 COW Default = 0x0000 */ + /* SA ICV error bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress SA ICV Error Status Register */ + union + { + struct + { + /*! \brief 1E.8033.F:0 COW MSS Ingress SA ICV Error MSW [1F:10] + AQ_MssIngressSaIcvErrorStatusRegister_HHD.u1.bits_1.mssIngressSaIcvErrorMSW + + Default = 0x0000 + + SA ICV error bits 31:16 + + + Notes: + When set, these bits identify the SA that has an ICV error. Write these bits to 1 to clear. */ + unsigned int mssIngressSaIcvErrorMSW : 16; /* 1E.8033.F:0 COW Default = 0x0000 */ + /* SA ICV error bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressSaIcvErrorStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress SA Replay Error Status Register: 1E.8034 */ +/* MSS Ingress SA Replay Error Status Register: 1E.8034 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress SA Replay Error Status Register */ + union + { + struct + { + /*! \brief 1E.8034.F:0 COW MSS Ingress SA Replay Error LSW [F:0] + AQ_MssIngressSaReplayErrorStatusRegister_HHD.u0.bits_0.mssIngressSaReplayErrorLSW + + Default = 0x0000 + + SA replay error bits 15:0 + + + Notes: + When set, these bits identify the SA that has a replay error. Write these bits to 1 to clear. */ + unsigned int mssIngressSaReplayErrorLSW : 16; /* 1E.8034.F:0 COW Default = 0x0000 */ + /* SA replay error bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress SA Replay Error Status Register */ + union + { + struct + { + /*! \brief 1E.8035.F:0 COW MSS Ingress SA Replay Error MSW [1F:10] + AQ_MssIngressSaReplayErrorStatusRegister_HHD.u1.bits_1.mssIngressSaReplayErrorMSW + + Default = 0x0000 + + SA replay error bits 31:16 + + + Notes: + When set, these bits identify the SA that has a replay error. Write these bits to 1 to clear. */ + unsigned int mssIngressSaReplayErrorMSW : 16; /* 1E.8035.F:0 COW Default = 0x0000 */ + /* SA replay error bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressSaReplayErrorStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress SA Expired Status Register: 1E.8036 */ +/* MSS Ingress SA Expired Status Register: 1E.8036 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress SA Expired Status Register */ + union + { + struct + { + /*! \brief 1E.8036.F:0 ROS MSS Ingress SA Expired LSW [F:0] + AQ_MssIngressSaExpiredStatusRegister_HHD.u0.bits_0.mssIngressSaExpiredLSW + + Default = 0x0000 + + SA expired bits 15:0 + + + Notes: + When set, these bits identify the SA that has expired when the SA PN reaches all-ones saturation. Write these bits to 1 to clear. */ + unsigned int mssIngressSaExpiredLSW : 16; /* 1E.8036.F:0 ROS Default = 0x0000 */ + /* SA expired bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress SA Expired Status Register */ + union + { + struct + { + /*! \brief 1E.8037.F:0 ROS MSS Ingress SA Expired MSW [1F:10] + AQ_MssIngressSaExpiredStatusRegister_HHD.u1.bits_1.mssIngressSaExpiredMSW + + Default = 0x0000 + + SA expired bits 31:16 + + + Notes: + When set, these bits identify the SA that has expired when the SA PN reaches all-ones saturation. Write these bits to 1 to clear. */ + unsigned int mssIngressSaExpiredMSW : 16; /* 1E.8037.F:0 ROS Default = 0x0000 */ + /* SA expired bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressSaExpiredStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress SA Threshold Expired Status Register: 1E.8038 */ +/* MSS Ingress SA Threshold Expired Status Register: 1E.8038 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress SA Threshold Expired Status Register */ + union + { + struct + { + /*! \brief 1E.8038.F:0 ROS MSS Ingress SA Threshold Expired LSW [F:0] + AQ_MssIngressSaThresholdExpiredStatusRegister_HHD.u0.bits_0.mssIngressSaThresholdExpiredLSW + + Default = 0x0000 + + SA threshold expired bits 15:0 + + + Notes: + When set, these bits identify the SA that has expired when the SA PN has reached the configured threshold See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . Write these bits to 1 to clear. */ + unsigned int mssIngressSaThresholdExpiredLSW : 16; /* 1E.8038.F:0 ROS Default = 0x0000 */ + /* SA threshold expired bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress SA Threshold Expired Status Register */ + union + { + struct + { + /*! \brief 1E.8039.F:0 ROS MSS Ingress SA Threshold Expired MSW [1F:10] + AQ_MssIngressSaThresholdExpiredStatusRegister_HHD.u1.bits_1.mssIngressSaThresholdExpiredMSW + + Default = 0x0000 + + SA threshold expired bits 31:16 + + + Notes: + When set, these bits identify the SA that has expired when the SA PN has reached the configured threshold See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . Write these bits to 1 to clear. */ + unsigned int mssIngressSaThresholdExpiredMSW : 16; /* 1E.8039.F:0 ROS Default = 0x0000 */ + /* SA threshold expired bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressSaThresholdExpiredStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress ECC Interrupt Status Register: 1E.803A */ +/* MSS Ingress ECC Interrupt Status Register: 1E.803A */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress ECC Interrupt Status Register */ + union + { + struct + { + /*! \brief 1E.803A.F:0 R/W MSS Ingress SA ECC Error Interrupt LSW [F:0] + AQ_MssIngressEccInterruptStatusRegister_HHD.u0.bits_0.mssIngressSaEccErrorInterruptLSW + + Default = 0x0000 + + SA ECC error interrupt bits 15:0 + + + Notes: + When set to 1, indicates that an ECC error occured for the SA. */ + unsigned int mssIngressSaEccErrorInterruptLSW : 16; /* 1E.803A.F:0 R/W Default = 0x0000 */ + /* SA ECC error interrupt bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress ECC Interrupt Status Register */ + union + { + struct + { + /*! \brief 1E.803B.F:0 R/W MSS Ingress SA ECC Error Interrupt MSW [1F:10] + AQ_MssIngressEccInterruptStatusRegister_HHD.u1.bits_1.mssIngressSaEccErrorInterruptMSW + + Default = 0x0000 + + SA ECC error interrupt bits 31:16 + + + Notes: + When set to 1, indicates that an ECC error occured for the SA. */ + unsigned int mssIngressSaEccErrorInterruptMSW : 16; /* 1E.803B.F:0 R/W Default = 0x0000 */ + /* SA ECC error interrupt bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressEccInterruptStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress LUT Address Control Register: 1E.8080 */ +/* MSS Ingress LUT Address Control Register: 1E.8080 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress LUT Address Control Register */ + union + { + struct + { + /*! \brief 1E.8080.8:0 R/W MSS Ingress LUT Address [8:0] + AQ_MssIngressLutAddressControlRegister_HHD.u0.bits_0.mssIngressLutAddress + + Default = 0x000 + + LUT address + + */ + unsigned int mssIngressLutAddress : 9; /* 1E.8080.8:0 R/W Default = 0x000 */ + /* LUT address + */ + unsigned int reserved0 : 3; + /*! \brief 1E.8080.F:C R/W MSS Ingress LUT Select [3:0] + AQ_MssIngressLutAddressControlRegister_HHD.u0.bits_0.mssIngressLutSelect + + Default = 0x0 + + LUT select + + + Notes: + 0x0 : Ingress Pre-Security MAC Control FIlter (IGPRCTLF) LUT + 0x1 : Ingress Pre-Security Classification LUT (IGPRC) + 0x2 : Ingress Packet Format (IGPFMT) SAKey LUT + 0x3 : Ingress Packet Format (IGPFMT) SC/SA LUT + 0x4 : Ingress Post-Security Classification LUT (IGPOC) + 0x5 : Ingress Post-Security MAC Control Filter (IGPOCTLF) LUT + 0x6 : Ingress MIB (IGMIB) */ + unsigned int mssIngressLutSelect : 4; /* 1E.8080.F:C R/W Default = 0x0 */ + /* LUT select + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_MssIngressLutAddressControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress LUT Control Register: 1E.8081 */ +/* MSS Ingress LUT Control Register: 1E.8081 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress LUT Control Register */ + union + { + struct + { + unsigned int reserved0 : 14; + /*! \brief 1E.8081.E R/W MSS Ingress LUT Read + AQ_MssIngressLutControlRegister_HHD.u0.bits_0.mssIngressLutRead + + Default = 0x0 + + 1 = LUT read + + + Notes: + Setting this bit to 1, will read the LUT. This bit will automatically clear to 0. */ + unsigned int mssIngressLutRead : 1; /* 1E.8081.E R/W Default = 0x0 */ + /* 1 = LUT read + */ + /*! \brief 1E.8081.F R/W MSS Ingress LUT Write + AQ_MssIngressLutControlRegister_HHD.u0.bits_0.mssIngressLutWrite + + Default = 0x0 + + 1 = LUT write + + + Notes: + Setting this bit to 1, will write the LUT. This bit will automatically clear to 0. */ + unsigned int mssIngressLutWrite : 1; /* 1E.8081.F R/W Default = 0x0 */ + /* 1 = LUT write + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_MssIngressLutControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress LUT Data Control Register: 1E.80A0 */ +/* MSS Ingress LUT Data Control Register: 1E.80A0 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A0.F:0 R/W MSS Ingress LUT Data 0 [F:0] + AQ_MssIngressLutDataControlRegister_HHD.u0.bits_0.mssIngressLutData_0 + + Default = 0x0000 + + LUT data bits 15:0 + + */ + unsigned int mssIngressLutData_0 : 16; /* 1E.80A0.F:0 R/W Default = 0x0000 */ + /* LUT data bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A1.F:0 R/W MSS Ingress LUT Data 1 [1F:10] + AQ_MssIngressLutDataControlRegister_HHD.u1.bits_1.mssIngressLutData_1 + + Default = 0x0000 + + LUT data bits 31:16 + + */ + unsigned int mssIngressLutData_1 : 16; /* 1E.80A1.F:0 R/W Default = 0x0000 */ + /* LUT data bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A2.F:0 R/W MSS Ingress LUT Data 2 [2F:20] + AQ_MssIngressLutDataControlRegister_HHD.u2.bits_2.mssIngressLutData_2 + + Default = 0x0000 + + LUT data bits 47:32 + + */ + unsigned int mssIngressLutData_2 : 16; /* 1E.80A2.F:0 R/W Default = 0x0000 */ + /* LUT data bits 47:32 + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A3.F:0 R/W MSS Ingress LUT Data 3 [3F:30] + AQ_MssIngressLutDataControlRegister_HHD.u3.bits_3.mssIngressLutData_3 + + Default = 0x0000 + + LUT data bits 63:48 + + */ + unsigned int mssIngressLutData_3 : 16; /* 1E.80A3.F:0 R/W Default = 0x0000 */ + /* LUT data bits 63:48 + */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A4.F:0 R/W MSS Ingress LUT Data 4 [4F:40] + AQ_MssIngressLutDataControlRegister_HHD.u4.bits_4.mssIngressLutData_4 + + Default = 0x0000 + + LUT data bits 79:64 + + */ + unsigned int mssIngressLutData_4 : 16; /* 1E.80A4.F:0 R/W Default = 0x0000 */ + /* LUT data bits 79:64 + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A5.F:0 R/W MSS Ingress LUT Data 5 [5F:50] + AQ_MssIngressLutDataControlRegister_HHD.u5.bits_5.mssIngressLutData_5 + + Default = 0x0000 + + LUT data bits 95:80 + + */ + unsigned int mssIngressLutData_5 : 16; /* 1E.80A5.F:0 R/W Default = 0x0000 */ + /* LUT data bits 95:80 + */ + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A6.F:0 R/W MSS Ingress LUT Data 6 [6F:60] + AQ_MssIngressLutDataControlRegister_HHD.u6.bits_6.mssIngressLutData_6 + + Default = 0x0000 + + LUT data bits 111:96 + + */ + unsigned int mssIngressLutData_6 : 16; /* 1E.80A6.F:0 R/W Default = 0x0000 */ + /* LUT data bits 111:96 + */ + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A7.F:0 R/W MSS Ingress LUT Data 7 [7F:70] + AQ_MssIngressLutDataControlRegister_HHD.u7.bits_7.mssIngressLutData_7 + + Default = 0x0000 + + LUT data bits 127:112 + + */ + unsigned int mssIngressLutData_7 : 16; /* 1E.80A7.F:0 R/W Default = 0x0000 */ + /* LUT data bits 127:112 + */ + } bits_7; + uint16_t word_7; + } u7; + /*! \brief Union for bit and word level access of word 8 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A8.F:0 R/W MSS Ingress LUT Data 8 [8F:80] + AQ_MssIngressLutDataControlRegister_HHD.u8.bits_8.mssIngressLutData_8 + + Default = 0x0000 + + LUT data bits 143:128 + + */ + unsigned int mssIngressLutData_8 : 16; /* 1E.80A8.F:0 R/W Default = 0x0000 */ + /* LUT data bits 143:128 + */ + } bits_8; + uint16_t word_8; + } u8; + /*! \brief Union for bit and word level access of word 9 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A9.F:0 R/W MSS Ingress LUT Data 9 [9F:90] + AQ_MssIngressLutDataControlRegister_HHD.u9.bits_9.mssIngressLutData_9 + + Default = 0x0000 + + LUT data bits 159:144 + + */ + unsigned int mssIngressLutData_9 : 16; /* 1E.80A9.F:0 R/W Default = 0x0000 */ + /* LUT data bits 159:144 + */ + } bits_9; + uint16_t word_9; + } u9; + /*! \brief Union for bit and word level access of word 10 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80AA.F:0 R/W MSS Ingress LUT Data 10 [AF:A0] + AQ_MssIngressLutDataControlRegister_HHD.u10.bits_10.mssIngressLutData_10 + + Default = 0x0000 + + LUT data bits 175:160 + + */ + unsigned int mssIngressLutData_10 : 16; /* 1E.80AA.F:0 R/W Default = 0x0000 */ + /* LUT data bits 175:160 + */ + } bits_10; + uint16_t word_10; + } u10; + /*! \brief Union for bit and word level access of word 11 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80AB.F:0 R/W MSS Ingress LUT Data 11 [BF:B0] + AQ_MssIngressLutDataControlRegister_HHD.u11.bits_11.mssIngressLutData_11 + + Default = 0x0000 + + LUT data bits 191:176 + + */ + unsigned int mssIngressLutData_11 : 16; /* 1E.80AB.F:0 R/W Default = 0x0000 */ + /* LUT data bits 191:176 + */ + } bits_11; + uint16_t word_11; + } u11; + /*! \brief Union for bit and word level access of word 12 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80AC.F:0 R/W MSS Ingress LUT Data 12 [CF:C0] + AQ_MssIngressLutDataControlRegister_HHD.u12.bits_12.mssIngressLutData_12 + + Default = 0x0000 + + LUT data bits 207:192 + + */ + unsigned int mssIngressLutData_12 : 16; /* 1E.80AC.F:0 R/W Default = 0x0000 */ + /* LUT data bits 207:192 + */ + } bits_12; + uint16_t word_12; + } u12; + /*! \brief Union for bit and word level access of word 13 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80AD.F:0 R/W MSS Ingress LUT Data 13 [DF:D0] + AQ_MssIngressLutDataControlRegister_HHD.u13.bits_13.mssIngressLutData_13 + + Default = 0x0000 + + LUT data bits 223:208 + + */ + unsigned int mssIngressLutData_13 : 16; /* 1E.80AD.F:0 R/W Default = 0x0000 */ + /* LUT data bits 223:208 + */ + } bits_13; + uint16_t word_13; + } u13; + /*! \brief Union for bit and word level access of word 14 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80AE.F:0 R/W MSS Ingress LUT Data 14 [EF:E0] + AQ_MssIngressLutDataControlRegister_HHD.u14.bits_14.mssIngressLutData_14 + + Default = 0x0000 + + LUT data bits 239:224 + + */ + unsigned int mssIngressLutData_14 : 16; /* 1E.80AE.F:0 R/W Default = 0x0000 */ + /* LUT data bits 239:224 + */ + } bits_14; + uint16_t word_14; + } u14; + /*! \brief Union for bit and word level access of word 15 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80AF.F:0 R/W MSS Ingress LUT Data 15 [FF:F0] + AQ_MssIngressLutDataControlRegister_HHD.u15.bits_15.mssIngressLutData_15 + + Default = 0x0000 + + LUT data bits 255:240 + + */ + unsigned int mssIngressLutData_15 : 16; /* 1E.80AF.F:0 R/W Default = 0x0000 */ + /* LUT data bits 255:240 + */ + } bits_15; + uint16_t word_15; + } u15; + /*! \brief Union for bit and word level access of word 16 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B0.F:0 R/W MSS Ingress LUT Data 16 [10F:100] + AQ_MssIngressLutDataControlRegister_HHD.u16.bits_16.mssIngressLutData_16 + + Default = 0x0000 + + LUT data bits 271:256 + + */ + unsigned int mssIngressLutData_16 : 16; /* 1E.80B0.F:0 R/W Default = 0x0000 */ + /* LUT data bits 271:256 + */ + } bits_16; + uint16_t word_16; + } u16; + /*! \brief Union for bit and word level access of word 17 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B1.F:0 R/W MSS Ingress LUT Data 17 [11F:110] + AQ_MssIngressLutDataControlRegister_HHD.u17.bits_17.mssIngressLutData_17 + + Default = 0x0000 + + LUT data bits 287:272 + + */ + unsigned int mssIngressLutData_17 : 16; /* 1E.80B1.F:0 R/W Default = 0x0000 */ + /* LUT data bits 287:272 + */ + } bits_17; + uint16_t word_17; + } u17; + /*! \brief Union for bit and word level access of word 18 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B2.F:0 R/W MSS Ingress LUT Data 18 [12F:120] + AQ_MssIngressLutDataControlRegister_HHD.u18.bits_18.mssIngressLutData_18 + + Default = 0x0000 + + LUT data bits 303:288 + + */ + unsigned int mssIngressLutData_18 : 16; /* 1E.80B2.F:0 R/W Default = 0x0000 */ + /* LUT data bits 303:288 + */ + } bits_18; + uint16_t word_18; + } u18; + /*! \brief Union for bit and word level access of word 19 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B3.F:0 R/W MSS Ingress LUT Data 19 [13F:130] + AQ_MssIngressLutDataControlRegister_HHD.u19.bits_19.mssIngressLutData_19 + + Default = 0x0000 + + LUT data bits 319:304 + + */ + unsigned int mssIngressLutData_19 : 16; /* 1E.80B3.F:0 R/W Default = 0x0000 */ + /* LUT data bits 319:304 + */ + } bits_19; + uint16_t word_19; + } u19; + /*! \brief Union for bit and word level access of word 20 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B4.F:0 R/W MSS Ingress LUT Data 20 [14F:140] + AQ_MssIngressLutDataControlRegister_HHD.u20.bits_20.mssIngressLutData_20 + + Default = 0x0000 + + LUT data bits 335:320 + + */ + unsigned int mssIngressLutData_20 : 16; /* 1E.80B4.F:0 R/W Default = 0x0000 */ + /* LUT data bits 335:320 + */ + } bits_20; + uint16_t word_20; + } u20; + /*! \brief Union for bit and word level access of word 21 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B5.F:0 R/W MSS Ingress LUT Data 21 [15F:150] + AQ_MssIngressLutDataControlRegister_HHD.u21.bits_21.mssIngressLutData_21 + + Default = 0x0000 + + LUT data bits 351:336 + + */ + unsigned int mssIngressLutData_21 : 16; /* 1E.80B5.F:0 R/W Default = 0x0000 */ + /* LUT data bits 351:336 + */ + } bits_21; + uint16_t word_21; + } u21; + /*! \brief Union for bit and word level access of word 22 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B6.F:0 R/W MSS Ingress LUT Data 22 [16F:160] + AQ_MssIngressLutDataControlRegister_HHD.u22.bits_22.mssIngressLutData_22 + + Default = 0x0000 + + LUT data bits 367:352 + + */ + unsigned int mssIngressLutData_22 : 16; /* 1E.80B6.F:0 R/W Default = 0x0000 */ + /* LUT data bits 367:352 + */ + } bits_22; + uint16_t word_22; + } u22; + /*! \brief Union for bit and word level access of word 23 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B7.F:0 R/W MSS Ingress LUT Data 23 [17F:170] + AQ_MssIngressLutDataControlRegister_HHD.u23.bits_23.mssIngressLutData_23 + + Default = 0x0000 + + LUT data bits 383:368 + + */ + unsigned int mssIngressLutData_23 : 16; /* 1E.80B7.F:0 R/W Default = 0x0000 */ + /* LUT data bits 383:368 + */ + } bits_23; + uint16_t word_23; + } u23; +} AQ_MssIngressLutDataControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line General Control Register: 1E.9004 */ +/* MSM Line General Control Register: 1E.9004 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line General Control Register */ + union + { + struct + { + /*! \brief 1E.9004.0 R/W MSM Line Tx Enable + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineTxEnable + + Default = 0x0 + + 1 = Tx enable + + Notes: + MAC Rx path enable. Should be set to 1 to enable the MAC Rx path. Should be set to 0 to disable the MAC Rx path. */ + unsigned int msmLineTxEnable : 1; /* 1E.9004.0 R/W Default = 0x0 */ + /* 1 = Tx enable */ + /*! \brief 1E.9004.1 R/W MSM Line Rx Enable + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineRxEnable + + Default = 0x0 + + 1 = Rx enable + + Notes: + MAC Tx path enable. Should be set to 1 to enable the MAC Tx path. Should be set to 0 to disable the MAC Tx path. */ + unsigned int msmLineRxEnable : 1; /* 1E.9004.1 R/W Default = 0x0 */ + /* 1 = Rx enable */ + unsigned int reserved0 : 1; + /*! \brief 1E.9004.3 R/W MSM Line WAN Mode + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineWanMode + + Default = 0x0 + + 1 = WAN mode + 0 = LAN mode + + + Notes: + WAN mode enable. Sets WAN mode when set to 1 and LAN mode when set to 0. Note: When changing the mode, verifiy correct setting of the Tx IPG. */ + unsigned int msmLineWanMode : 1; /* 1E.9004.3 R/W Default = 0x0 */ + /* 1 = WAN mode + 0 = LAN mode + */ + /*! \brief 1E.9004.4 R/W MSM Line Promiscuous Mode + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLinePromiscuousMode + + Default = 0x0 + + 1 = Promiscuous mode + + + Notes: + When set to 1, all frames are received without any MAC address filtering. */ + unsigned int msmLinePromiscuousMode : 1; /* 1E.9004.4 R/W Default = 0x0 */ + /* 1 = Promiscuous mode + */ + /*! \brief 1E.9004.5 R/W MSM Line PAD Enable + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLinePadEnable + + Default = 0x0 + + 1 = Enable frame padding removal on Rx + + + Notes: + When set to 1, enable frame padding removal on the Rx path. If enabled, padding is removed before the frame is transferred to the MAC client application. If disabled, no padding is removed on the Rx by the MAC. + Note : On Tx, the MAC always adds padding as required. */ + unsigned int msmLinePadEnable : 1; /* 1E.9004.5 R/W Default = 0x0 */ + /* 1 = Enable frame padding removal on Rx + */ + /*! \brief 1E.9004.6 R/W MSM Line CRC Forward + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineCrcForward + + Default = 0x0 + + 1 = Enable CRC forwarding + + + Notes: + When set to 1, the CRC field of the received frames is forwarded with the frame to the user application. If disabled, the CRC field is stripped from the frame. + Note : If padding is enabled ( See MAC PAD Enable set to 1), this bit is ignored. */ + unsigned int msmLineCrcForward : 1; /* 1E.9004.6 R/W Default = 0x0 */ + /* 1 = Enable CRC forwarding + */ + /*! \brief 1E.9004.7 R/W MSM Line Pause Forward + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLinePauseForward + + Default = 0x0 + + 1 = Enable Pause forwarding + + + Notes: + Terminate or forward pause frames. If set to 1, pause frames are forwarded to the user application. In normal mode, when set to 0, pause frames are terminated and discarded within the MAC. */ + unsigned int msmLinePauseForward : 1; /* 1E.9004.7 R/W Default = 0x0 */ + /* 1 = Enable Pause forwarding + */ + /*! \brief 1E.9004.8 R/W MSM Line Pause Ignore + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLinePauseIgnore + + Default = 0x0 + + 1 = Ignore pause frames + + + Notes: + Ignore pause frame quanta. If set to 1, received pause frames are ignored by the MAC. When set to 0, the Tx is stopped for the amount of time specified in the pause quanta received within the pause frame. */ + unsigned int msmLinePauseIgnore : 1; /* 1E.9004.8 R/W Default = 0x0 */ + /* 1 = Ignore pause frames + */ + /*! \brief 1E.9004.9 R/W MSM Line Tx Address Insert Enable + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineTxAddressInsertEnable + + Default = 0x0 + + 1 = Insert Tx MAC source address + + + Notes: + Set the source MAC address on transmit. If set to 1, the MAC overwrites the source MAC address with the MAC programmed address in all transmitted frames. When set to 0, the source MAC address is transmitted unmodified from the MAC Tx client application. */ + unsigned int msmLineTxAddressInsertEnable : 1; /* 1E.9004.9 R/W Default = 0x0 */ + /* 1 = Insert Tx MAC source address + */ + /*! \brief 1E.9004.A R/W MSM Line Tx CRC Append + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineTxCrcAppend + + Default = 0x0 + + 1 = Append Tx CRC + + + Notes: + Permanently enable CRC append on transmit. If set to 1, the Tx will append a CRC to all transmitted frames. If set to 0, CRC append can be controlled on a per frame basis using the pin ff_tx_crc. + This configuration bit is OR'ed with the external ff_tx_crc pin to instruct the Tx to append a CRC to transmitted frames. The ff_tx_crc pin is tied to 0. */ + unsigned int msmLineTxCrcAppend : 1; /* 1E.9004.A R/W Default = 0x0 */ + /* 1 = Append Tx CRC + */ + /*! \brief 1E.9004.B R/W MSM Line Tx Pad Enable + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineTxPadEnable + + Default = 0x1 + + 1 = Enable Tx padding + + + Notes: + When set to 1, enable padding of frames in the Tx direction. When set to 0, the MAC will not extend frames from the application to a minimum of 64 bytes, allowing to transmit short frames (violating the Ethernet mimimum size requirements). Must be set to 1 for normal operation. */ + unsigned int msmLineTxPadEnable : 1; /* 1E.9004.B R/W Default = 0x1 */ + /* 1 = Enable Tx padding + */ + /*! \brief 1E.9004.C R/WSC MSM Line Soft Reset + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineSoftReset + + Default = 0x0 + + 1 = Soft reset + + + Notes: + Software reset. Self clearing bit. When set to 1, resets all statistic counters as well as the Tx and Rx FIFOs. It should be issued after all traffic has been stopped as a result of clearing the Rx/Tx enable bits ( See MAC Rx Enable set to 0 and See MAC Tx Enable set to 0). + Note : Can lead to an Rx interface (ff_rx_xxx) violations to the application if the reset is issued in the middle of a receive frame transfer. Then the end of packet (assertion of ff_rx_eop) is lost and the application should be prepeared to handle this exception. */ + unsigned int msmLineSoftReset : 1; /* 1E.9004.C R/WSC Default = 0x0 */ + /* 1 = Soft reset + */ + /*! \brief 1E.9004.D R/W MSM Line Control Frame Enable + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineControlFrameEnable + + Default = 0x0 + + 1 = Control frame enabled + + + Notes: + MAC control frame enable. When set to 1, the MAC control frames with any Opcode other than 0x0001 are accepted and forwarded to the client interface. When set to 0, MAC control frames with any opcode other than 0x0001 are silently discarded. */ + unsigned int msmLineControlFrameEnable : 1; /* 1E.9004.D R/W Default = 0x0 */ + /* 1 = Control frame enabled + */ + /*! \brief 1E.9004.E R/W MSM Line Rx Error Discard + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineRxErrorDiscard + + Default = 0x0 + + 1 = Enable discard of received errored frames + + + Notes: + Rx errored frame discard enable. When set to 1, any frame received with an error is discarded and not forwarded to the client interface. When set to 0, errored frames are forwarded to the client interface with ff_rx_err asserted. + Note : It is recommended to set this bit to 1 only when store and forward operation is enabled (RX_SECTION_FULL TBD). */ + unsigned int msmLineRxErrorDiscard : 1; /* 1E.9004.E R/W Default = 0x0 */ + /* 1 = Enable discard of received errored frames + */ + /*! \brief 1E.9004.F R/W MSM Line PHY Tx Enable + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLinePhyTxEnable + + Default = 0x0 + + 1 = Enable PHY Tx + + + Notes: + Directly controls the phy_tx_ena pin. */ + unsigned int msmLinePhyTxEnable : 1; /* 1E.9004.F R/W Default = 0x0 */ + /* 1 = Enable PHY Tx + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line General Control Register */ + union + { + struct + { + /*! \brief 1E.9005.0 R/W MSM Line Force Send IDLE + AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLineForceSendIdle + + Default = 0x0 + + 1 = Force send idle + + Notes: + When set to 1, suppress any frame transmissions and forces IDLE n the Tx interface instead of frames. This control affects the MAC reconciliation layer (RS) which acts after all MAC datapath has processed the frame. + Note : Does not have an effect on fault handling (i.e. reception of local fault will still cause transmit of remote fault). + Must be 0 for normal operation. */ + unsigned int msmLineForceSendIdle : 1; /* 1E.9005.0 R/W Default = 0x0 */ + /* 1 = Force send idle */ + /*! \brief 1E.9005.1 R/W MSM Line Length Check Disable + AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLineLengthCheckDisable + + Default = 0x0 + + 1 = Disable length check + + Notes: + Payload length check disable. When set to 0, the MAC checks the frames payload length with the frame length/type field. When set to 1, the payload length check is disabled. */ + unsigned int msmLineLengthCheckDisable : 1; /* 1E.9005.1 R/W Default = 0x0 */ + /* 1 = Disable length check */ + /*! \brief 1E.9005.2 R/W MSM Line IDLE Column Count Extend + AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLineIdleColumnCountExtend + + Default = 0x0 + + 1 = Extend IDLE column count + + Notes: + When set to 1, extends the RS layer IDLE column counter by 2x. The IEEE 802.3ae defines the fault condition to be cleared after 128 columns of IDLE have been received. If the MAC operates together with a WAN mode PCS (WIS) it may may happen (depending on PCS) that this period is too short to bridge the IDLE stuffing occurring in this mode, leading to a toggling fault indication. In this case, extending the counter helps to aoivd toggling fault indications. */ + unsigned int msmLineIdleColumnCountExtend : 1; /* 1E.9005.2 R/W Default = 0x0 */ + /* 1 = Extend IDLE column count */ + /*! \brief 1E.9005.3 R/W MSM Line Priority Flow Control Enable + AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLinePriorityFlowControlEnable + + Default = 0x0 + + 1 = Enable priority flow control + 0 = Enable link flow control + + + Notes: + Enable priority flow control (PFC) mode of operation. When set to 0, the MAC uses standard link pause frames. When set to 1, the MAC will transmit and accept PFC frames. */ + unsigned int msmLinePriorityFlowControlEnable : 1; /* 1E.9005.3 R/W Default = 0x0 */ + /* 1 = Enable priority flow control + 0 = Enable link flow control + */ + unsigned int reserved2 : 1; + /*! \brief 1E.9005.5 R/W MSM Line SFD Check Disable + AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLineSfdCheckDisable + + Default = 0x0 + + 1 = Disable SFD check + + + Notes: + Disable check of SFD (0xD5) character at frame start. When set to 1, the frame is accepted even if the SFD byte following the preamble is not 0xD5. When set to 0, a frame is accepted only if the SFD byte is found with the value 0xD5. */ + unsigned int msmLineSfdCheckDisable : 1; /* 1E.9005.5 R/W Default = 0x0 */ + /* 1 = Disable SFD check + */ + unsigned int reserved1 : 1; + /*! \brief 1E.9005.7 R/W MSM Line Tx Low Power IDLE Enable + AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLineTxLowPowerIdleEnable + + Default = 0x0 + + 1 = Transmit LPI enable + + + Notes: + Transmit low power IDLE enable. When set to 1, the MAC completes the transmission of the current frame and generates low power IDLE sequences (LPI) to the XGMII/SGMII. When set to 0, the MAC operates in normal mode. This bit is OR'ed with the reg_lowp_ena pin. */ + unsigned int msmLineTxLowPowerIdleEnable : 1; /* 1E.9005.7 R/W Default = 0x0 */ + /* 1 = Transmit LPI enable + */ + unsigned int reserved0 : 8; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineGeneralControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line FIFO Control Register: 1E.900E */ +/* MSM Line FIFO Control Register: 1E.900E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.900E.7:0 R/W MSM Line Rx FIFO Full Threshold [7:0] + AQ_MsmLineFifoControlRegister_HHD.u0.bits_0.msmLineRxFifoFullThreshold + + Default = 0x08 + + Rx FIFO full threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmLineRxFifoFullThreshold : 8; /* 1E.900E.7:0 R/W Default = 0x08 */ + /* Rx FIFO full threshold */ + unsigned int reserved0 : 8; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.900F.7:0 R/W MSM Line Rx FIFO Empty Threshold [7:0] + AQ_MsmLineFifoControlRegister_HHD.u1.bits_1.msmLineRxFifoEmptyThreshold + + Default = 0x00 + + Rx FIFO empty threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmLineRxFifoEmptyThreshold : 8; /* 1E.900F.7:0 R/W Default = 0x00 */ + /* Rx FIFO empty threshold */ + unsigned int reserved0 : 8; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of MSM Line FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.9010.5:0 R/W MSM Line Tx FIFO Full Threshold [5:0] + AQ_MsmLineFifoControlRegister_HHD.u2.bits_2.msmLineTxFifoFullThreshold + + Default = 0x08 + + Tx FIFO full threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmLineTxFifoFullThreshold : 6; /* 1E.9010.5:0 R/W Default = 0x08 */ + /* Tx FIFO full threshold */ + unsigned int reserved0 : 10; + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of MSM Line FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.9011.5:0 R/W MSM Line Tx FIFO Empty Threshold [5:0] + AQ_MsmLineFifoControlRegister_HHD.u3.bits_3.msmLineTxFifoEmptyThreshold + + Default = 0x00 + + Tx FIFO empty threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmLineTxFifoEmptyThreshold : 6; /* 1E.9011.5:0 R/W Default = 0x00 */ + /* Tx FIFO empty threshold */ + unsigned int reserved0 : 10; + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of MSM Line FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.9012.7:0 ROS MSM Line Rx FIFO Almost Full Threshold [7:0] + AQ_MsmLineFifoControlRegister_HHD.u4.bits_4.msmLineRxFifoAlmostFullThreshold + + Default = 0x00 + + Rx FIFO almost full threshold + + Notes: + Unused. */ + unsigned int msmLineRxFifoAlmostFullThreshold : 8; /* 1E.9012.7:0 ROS Default = 0x00 */ + /* Rx FIFO almost full threshold */ + unsigned int reserved0 : 8; + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of MSM Line FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.9013.7:0 ROS MSM Line Rx FIFO Almost Empty Threshold [7:0] + AQ_MsmLineFifoControlRegister_HHD.u5.bits_5.msmLineRxFifoAlmostEmptyThreshold + + Default = 0x00 + + Rx FIFO almost empty threshold + + Notes: + Unused. */ + unsigned int msmLineRxFifoAlmostEmptyThreshold : 8; /* 1E.9013.7:0 ROS Default = 0x00 */ + /* Rx FIFO almost empty threshold */ + unsigned int reserved0 : 8; + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of MSM Line FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.9014.7:0 ROS MSM Line Tx FIFO Almost Full Threshold [7:0] + AQ_MsmLineFifoControlRegister_HHD.u6.bits_6.msmLineTxFifoAlmostFullThreshold + + Default = 0x00 + + Tx FIFO almost full threshold + + Notes: + Unused. */ + unsigned int msmLineTxFifoAlmostFullThreshold : 8; /* 1E.9014.7:0 ROS Default = 0x00 */ + /* Tx FIFO almost full threshold */ + unsigned int reserved0 : 8; + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of MSM Line FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.9015.7:0 ROS MSM Line Tx FIFO Almost Empty Threshold [7:0] + AQ_MsmLineFifoControlRegister_HHD.u7.bits_7.msmLineTxFifoAlmostEmptyThreshold + + Default = 0x00 + + Tx FIFO almost empty threshold + + Notes: + Unused. */ + unsigned int msmLineTxFifoAlmostEmptyThreshold : 8; /* 1E.9015.7:0 ROS Default = 0x00 */ + /* Tx FIFO almost empty threshold */ + unsigned int reserved0 : 8; + } bits_7; + uint16_t word_7; + } u7; +} AQ_MsmLineFifoControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line General Status Register: 1E.9020 */ +/* MSM Line General Status Register: 1E.9020 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line General Status Register */ + union + { + struct + { + /*! \brief 1E.9020.0 BLH MSM Line Rx Local Fault + AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLineRxLocalFault + + + + Rx local fault detected + + Notes: + Latch high local fault status. Set to 1, whent he MAC detects Rx local fault sequences on the Rx interface. Reset to 0 after read and after reset. */ + unsigned int msmLineRxLocalFault : 1; /* 1E.9020.0 BLH */ + /* Rx local fault detected */ + /*! \brief 1E.9020.1 BLH MSM Line Rx Remote Fault + AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLineRxRemoteFault + + + + Rx remote fault detected + + Notes: + Latch high local fault status. Set to 1, whent he MAC detects Rx local fault sequences on the Rx interface. Reset to 0 after read and after reset. */ + unsigned int msmLineRxRemoteFault : 1; /* 1E.9020.1 BLH */ + /* Rx remote fault detected */ + /*! \brief 1E.9020.2 RO MSM Line PHY Loss of Signal + AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLinePhyLossOfSignal + + + + PHY loss of signal + + Notes: + PHY indicates loss of signal. This is the value of pin phy_los which is tied to 0. */ + unsigned int msmLinePhyLossOfSignal : 1; /* 1E.9020.2 RO */ + /* PHY loss of signal */ + /*! \brief 1E.9020.3 R/W MSM Line Timestamp Available + AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLineTimestampAvailable + + Default = 0x0 + + Timestamp available + + Notes: + Transmit timestamp available. Indicates that the timestamp of the last transmitted event frame (which had ff_tx_ts_frm=1) is available in the register See MAC Time Stamp Status 0 [F:0] and See MAC Time Stamp Status 1 [F:0] . To clear this bit, the bit must be written with a 1. + */ + unsigned int msmLineTimestampAvailable : 1; /* 1E.9020.3 R/W Default = 0x0 */ + /* Timestamp available */ + /*! \brief 1E.9020.4 RO MSM Line Rx Low Power IDLE + AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLineRxLowPowerIdle + + + + Rx LPI detected + + Notes: + Receive low power IDLE (LPI). Set to 1 when LPI is currently detected on the MAC Rx interface. Set to 0, when the MAC currently operates in normal mode. */ + unsigned int msmLineRxLowPowerIdle : 1; /* 1E.9020.4 RO */ + /* Rx LPI detected */ + /*! \brief 1E.9020.5 RO MSM Line Tx FIFO Empty + AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLineTxFifoEmpty + + + + Tx FIFO empty + + Notes: + When set to 1, indicates the Tx FIFO is empty. When set to 0, Tx FIFO is non-empty. */ + unsigned int msmLineTxFifoEmpty : 1; /* 1E.9020.5 RO */ + /* Tx FIFO empty */ + unsigned int reserved0 : 10; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line General Status Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineGeneralStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx IPG Control Register: 1E.9022 */ +/* MSM Line Tx IPG Control Register: 1E.9022 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx IPG Control Register */ + union + { + struct + { + /*! \brief 1E.9022.5:0 R/W MSM Line Tx IPG Length [5:0] + AQ_MsmLineTxIpgControlRegister_HHD.u0.bits_0.msmLineTxIpgLength + + Default = 0x0C + + Tx IPG length + + Notes: + Tx inter-packet gap (IPG) value. Depending on LAN or WAN mode of operation. + LAN Mode : Number of octets in steps of 4. Valid values are 8, 12, 16,..., 100. DIC is supported for any setting > 8. A default of 12 must be set to conform to IEEE802.3ae. + WAN Mode : Stretch factor. Valid values are 4 ... 15. The stretch factor is calculated as (value+1)*8. A default of 12 must be set to conform to IEEE802.3ae (i.e. 13*8=104). A larger value shrinks the IPG (increasing bandwidth). + The reset value of 12 leads to IEEE802.3ae conformant behavior in both modes. + Note : WAN mode is only available in 10G mode of operation. */ + unsigned int msmLineTxIpgLength : 6; /* 1E.9022.5:0 R/W Default = 0x0C */ + /* Tx IPG length */ + unsigned int reserved0 : 10; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx IPG Control Register */ + union + { + struct + { + /*! \brief 1E.9023.F:0 MSM Line Tx IPG Reserved + AQ_MsmLineTxIpgControlRegister_HHD.u1.bits_1.msmLineTxIpgReserved + + + + Value always 0, writes ignored + */ + unsigned int msmLineTxIpgReserved : 16; /* 1E.9023.F:0 */ + /* Value always 0, writes ignored */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxIpgControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx Good Frames Counter Register: 1E.9040 */ +/* MSM Line Tx Good Frames Counter Register: 1E.9040 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9040.F:0 ROS MSM Line Tx Good Frames Counter 0 [F:0] + AQ_MsmLineTxGoodFramesCounterRegister_HHD.u0.bits_0.msmLineTxGoodFramesCounter_0 + + Default = 0x0000 + + Tx good frame counter bits 15:0 + + Notes: + Count of frames transmitted without error (Including pause frames). */ + unsigned int msmLineTxGoodFramesCounter_0 : 16; /* 1E.9040.F:0 ROS Default = 0x0000 */ + /* Tx good frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9041.F:0 ROS MSM Line Tx Good Frames Counter 1 [F:0] + AQ_MsmLineTxGoodFramesCounterRegister_HHD.u1.bits_1.msmLineTxGoodFramesCounter_1 + + Default = 0x0000 + + Tx good frame counter bits 31:16 + + + Notes: + Count of frames transmitted without error (Including pause frames). */ + unsigned int msmLineTxGoodFramesCounter_1 : 16; /* 1E.9041.F:0 ROS Default = 0x0000 */ + /* Tx good frame counter bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxGoodFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Good Frames Counter Register: 1E.9044 */ +/* MSM Line Rx Good Frames Counter Register: 1E.9044 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9044.F:0 ROS MSM Line Rx Good Frames Counter 0 [F:0] + AQ_MsmLineRxGoodFramesCounterRegister_HHD.u0.bits_0.msmLineRxGoodFramesCounter_0 + + Default = 0x0000 + + Rx good frame counter bits 15:0 + + Notes: + Count of frames received without error (Including pause frames). */ + unsigned int msmLineRxGoodFramesCounter_0 : 16; /* 1E.9044.F:0 ROS Default = 0x0000 */ + /* Rx good frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9045.F:0 ROS MSM Line Rx Good Frames Counter 1 [F:0] + AQ_MsmLineRxGoodFramesCounterRegister_HHD.u1.bits_1.msmLineRxGoodFramesCounter_1 + + Default = 0x0000 + + Rx good frame counter bits 31:16 + + Notes: + Count of frames received without error (Including pause frames). */ + unsigned int msmLineRxGoodFramesCounter_1 : 16; /* 1E.9045.F:0 ROS Default = 0x0000 */ + /* Rx good frame counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxGoodFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx FCS Errors Counter Register: 1E.9048 */ +/* MSM Line Rx FCS Errors Counter Register: 1E.9048 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx FCS Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.9048.F:0 ROS MSM Line FCS Error Counter 0 [F:0] + AQ_MsmLineRxFcsErrorsCounterRegister_HHD.u0.bits_0.msmLineFcsErrorCounter_0 + + Default = 0x0000 + + Frame check sequence error counter bits 15:0 + + Notes: + Count of frames for which a CRC-32 Error is detected but the frame is otherwise of correct length. */ + unsigned int msmLineFcsErrorCounter_0 : 16; /* 1E.9048.F:0 ROS Default = 0x0000 */ + /* Frame check sequence error counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx FCS Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.9049.F:0 ROS MSM Line FCS Error Counter 1 [F:0] + AQ_MsmLineRxFcsErrorsCounterRegister_HHD.u1.bits_1.msmLineFcsErrorCounter_1 + + Default = 0x0000 + + Frame check sequence error counter bits 31:16 + + Notes: + Count of frames for which a CRC-32 Error is detected but the frame is otherwise of correct length. */ + unsigned int msmLineFcsErrorCounter_1 : 16; /* 1E.9049.F:0 ROS Default = 0x0000 */ + /* Frame check sequence error counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxFcsErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Alignment Errors Counter Register: 1E.904C */ +/* MSM Line Rx Alignment Errors Counter Register: 1E.904C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Alignment Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.904C.F:0 ROS MSM Line Alignment Error Counter 0 [F:0] + AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD.u0.bits_0.msmLineAlignmentErrorCounter_0 + + Default = 0x0000 + + Alignment error counter bits 15:0 + + Notes: + Count of frames received with an alignment error. */ + unsigned int msmLineAlignmentErrorCounter_0 : 16; /* 1E.904C.F:0 ROS Default = 0x0000 */ + /* Alignment error counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Alignment Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.904D.F:0 ROS MSM Line Alignment Error Counter 1 [F:0] + AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD.u1.bits_1.msmLineAlignmentErrorCounter_1 + + Default = 0x0000 + + Alignment error counter bits 31:16 + + Notes: + Count of frames received with an alignment error. */ + unsigned int msmLineAlignmentErrorCounter_1 : 16; /* 1E.904D.F:0 ROS Default = 0x0000 */ + /* Alignment error counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx Pause Frames Counter Register: 1E.9050 */ +/* MSM Line Tx Pause Frames Counter Register: 1E.9050 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9050.F:0 ROS MSM Line Tx Pause Frames Counter 0 [F:0] + AQ_MsmLineTxPauseFramesCounterRegister_HHD.u0.bits_0.msmLineTxPauseFramesCounter_0 + + Default = 0x0000 + + Tx pause frame counter bits 15:0 + + Notes: + Valid pause frames transmitted. */ + unsigned int msmLineTxPauseFramesCounter_0 : 16; /* 1E.9050.F:0 ROS Default = 0x0000 */ + /* Tx pause frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9051.F:0 ROS MSM Line Tx Pause Frames Counter 1 [F:0] + AQ_MsmLineTxPauseFramesCounterRegister_HHD.u1.bits_1.msmLineTxPauseFramesCounter_1 + + Default = 0x0000 + + Tx pause frame counter bits 31:16 + + + Notes: + Valid pause frames transmitted. */ + unsigned int msmLineTxPauseFramesCounter_1 : 16; /* 1E.9051.F:0 ROS Default = 0x0000 */ + /* Tx pause frame counter bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxPauseFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Pause Frames Counter Register: 1E.9054 */ +/* MSM Line Rx Pause Frames Counter Register: 1E.9054 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9054.F:0 ROS MSM Line Rx Pause Frames Counter 0 [F:0] + AQ_MsmLineRxPauseFramesCounterRegister_HHD.u0.bits_0.msmLineRxPauseFramesCounter_0 + + Default = 0x0000 + + Rx pause frame counter bits 15:0 + + Notes: + Valid pause frames received. */ + unsigned int msmLineRxPauseFramesCounter_0 : 16; /* 1E.9054.F:0 ROS Default = 0x0000 */ + /* Rx pause frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9055.F:0 ROS MSM Line Rx Pause Frames Counter 1 [F:0] + AQ_MsmLineRxPauseFramesCounterRegister_HHD.u1.bits_1.msmLineRxPauseFramesCounter_1 + + Default = 0x0000 + + Rx pause frame counter bits 31:16 + + Notes: + Valid pause frames received. */ + unsigned int msmLineRxPauseFramesCounter_1 : 16; /* 1E.9055.F:0 ROS Default = 0x0000 */ + /* Rx pause frame counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxPauseFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Too Long Errors Counter Register: 1E.9058 */ +/* MSM Line Rx Too Long Errors Counter Register: 1E.9058 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Too Long Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.9058.F:0 ROS MSM Line Rx Too Long Errors Counter 0 [F:0] + AQ_MsmLineRxTooLongErrorsCounterRegister_HHD.u0.bits_0.msmLineRxTooLongErrorsCounter_0 + + Default = 0x0000 + + Too-long errors counter bits 15:0 + + Notes: + Frame received exceeded the maximum length programmed with register FRM_LGTH. */ + unsigned int msmLineRxTooLongErrorsCounter_0 : 16; /* 1E.9058.F:0 ROS Default = 0x0000 */ + /* Too-long errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Too Long Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.9059.F:0 ROS MSM Line Rx Too Long Errors Counter 1 [F:0] + AQ_MsmLineRxTooLongErrorsCounterRegister_HHD.u1.bits_1.msmLineRxTooLongErrorsCounter_1 + + Default = 0x0000 + + Too-long errors counter bits 31:16 + + Notes: + Frame received exceeded the maximum length programmed with register FRM_LGTH. */ + unsigned int msmLineRxTooLongErrorsCounter_1 : 16; /* 1E.9059.F:0 ROS Default = 0x0000 */ + /* Too-long errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxTooLongErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx In Range Length Errors Counter Register: 1E.905C */ +/* MSM Line Rx In Range Length Errors Counter Register: 1E.905C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx In Range Length Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.905C.F:0 ROS MSM Line Rx In Range Length Errors Counter 0 [F:0] + AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD.u0.bits_0.msmLineRxInRangeLengthErrorsCounter_0 + + Default = 0x0000 + + In-range-length errors counter bits 15:0 + + Notes: + A count of frames with a length/type field value between 46 (VLAN: 42) and less than 0x0600, that does not match the number of payload data octets received. Should count also if length/type field is less than 46 (VLAN: 42) and the frame is longer than 64 bytes. */ + unsigned int msmLineRxInRangeLengthErrorsCounter_0 : 16; /* 1E.905C.F:0 ROS Default = 0x0000 */ + /* In-range-length errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx In Range Length Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.905D.F:0 ROS MSM Line Rx In Range Length Errors Counter 1 [F:0] + AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD.u1.bits_1.msmLineRxInRangeLengthErrorsCounter_1 + + Default = 0x0000 + + In-range-length errors counter bits 31:16 + + Notes: + A count of frames with a length/type field value between 46 (VLAN: 42) and less than 0x0600, that does not match the number of payload data octets received. Should count also if length/type field is less than 46 (VLAN: 42) and the frame is longer than 64 bytes. */ + unsigned int msmLineRxInRangeLengthErrorsCounter_1 : 16; /* 1E.905D.F:0 ROS Default = 0x0000 */ + /* In-range-length errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx VLAN Frames Counter Register: 1E.9060 */ +/* MSM Line Tx VLAN Frames Counter Register: 1E.9060 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9060.F:0 ROS MSM Line Tx VLAN Frames Counter 0 [F:0] + AQ_MsmLineTxVlanFramesCounterRegister_HHD.u0.bits_0.msmLineTxVlanFramesCounter_0 + + Default = 0x0000 + + Tx VLAN frames counter bits 15:0 + + Notes: + Valid VLAN tagged frames transmitted. */ + unsigned int msmLineTxVlanFramesCounter_0 : 16; /* 1E.9060.F:0 ROS Default = 0x0000 */ + /* Tx VLAN frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9061.F:0 ROS MSM Line Tx VLAN Frames Counter 1 [F:0] + AQ_MsmLineTxVlanFramesCounterRegister_HHD.u1.bits_1.msmLineTxVlanFramesCounter_1 + + Default = 0x0000 + + Tx VLAN frames counter bits 31:16 + + Notes: + Valid VLAN tagged frames transmitted. */ + unsigned int msmLineTxVlanFramesCounter_1 : 16; /* 1E.9061.F:0 ROS Default = 0x0000 */ + /* Tx VLAN frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxVlanFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx VLAN Frames Counter Register: 1E.9064 */ +/* MSM Line Rx VLAN Frames Counter Register: 1E.9064 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9064.F:0 ROS MSM Line Rx VLAN Frames Counter 0 [F:0] + AQ_MsmLineRxVlanFramesCounterRegister_HHD.u0.bits_0.msmLineRxVlanFramesCounter_0 + + Default = 0x0000 + + Rx VLAN frames counter bits 15:0 + + Notes: + Valid VLAN tagged frames received. */ + unsigned int msmLineRxVlanFramesCounter_0 : 16; /* 1E.9064.F:0 ROS Default = 0x0000 */ + /* Rx VLAN frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9065.F:0 ROS MSM Line Rx VLAN Frames Counter 1 [F:0] + AQ_MsmLineRxVlanFramesCounterRegister_HHD.u1.bits_1.msmLineRxVlanFramesCounter_1 + + Default = 0x0000 + + Rx VLAN frames counter bits 31:16 + + Notes: + Valid VLAN tagged frames received. */ + unsigned int msmLineRxVlanFramesCounter_1 : 16; /* 1E.9065.F:0 ROS Default = 0x0000 */ + /* Rx VLAN frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxVlanFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx Octets Counter Register: 1E.9068 */ +/* MSM Line Tx Octets Counter Register: 1E.9068 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.9068.F:0 ROS MSM Line Tx Octets Counter 0 [F:0] + AQ_MsmLineTxOctetsCounterRegister_HHD.u0.bits_0.msmLineTxOctetsCounter_0 + + Default = 0x0000 + + Tx octets counter bits 15:0 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmLineTxOctetsCounter_0 : 16; /* 1E.9068.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.9069.F:0 ROS MSM Line Tx Octets Counter 1 [F:0] + AQ_MsmLineTxOctetsCounterRegister_HHD.u1.bits_1.msmLineTxOctetsCounter_1 + + Default = 0x0000 + + Tx octets counter bits 31:16 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmLineTxOctetsCounter_1 : 16; /* 1E.9069.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of MSM Line Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.906A.F:0 ROS MSM Line Tx Octets Counter 2 [F:0] + AQ_MsmLineTxOctetsCounterRegister_HHD.u2.bits_2.msmLineTxOctetsCounter_2 + + Default = 0x0000 + + Tx octets counter bits 47:32 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmLineTxOctetsCounter_2 : 16; /* 1E.906A.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 47:32 */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of MSM Line Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.906B.F:0 ROS MSM Line Tx Octets Counter 3 [F:0] + AQ_MsmLineTxOctetsCounterRegister_HHD.u3.bits_3.msmLineTxOctetsCounter_3 + + Default = 0x0000 + + Tx octets counter bits 63:48 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmLineTxOctetsCounter_3 : 16; /* 1E.906B.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 63:48 */ + } bits_3; + uint16_t word_3; + } u3; +} AQ_MsmLineTxOctetsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Octets Counter Register: 1E.906C */ +/* MSM Line Rx Octets Counter Register: 1E.906C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.906C.F:0 ROS MSM Line Rx Octets Counter 0 [F:0] + AQ_MsmLineRxOctetsCounterRegister_HHD.u0.bits_0.msmLineRxOctetsCounter_0 + + Default = 0x0000 + + Rx octets counter bits 15:0 + + Notes: + All octets received except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames received. */ + unsigned int msmLineRxOctetsCounter_0 : 16; /* 1E.906C.F:0 ROS Default = 0x0000 */ + /* Rx octets counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.906D.F:0 ROS MSM Line Rx Octets Counter 1 [F:0] + AQ_MsmLineRxOctetsCounterRegister_HHD.u1.bits_1.msmLineRxOctetsCounter_1 + + Default = 0x0000 + + Rx octets counter bits 31:16 + + Notes: + All octets received except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames received. */ + unsigned int msmLineRxOctetsCounter_1 : 16; /* 1E.906D.F:0 ROS Default = 0x0000 */ + /* Rx octets counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxOctetsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Unicast Frames Counter Register: 1E.9070 */ +/* MSM Line Rx Unicast Frames Counter Register: 1E.9070 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9070.F:0 ROS MSM Line Rx Unicast Frames Counter 0 [F:0] + AQ_MsmLineRxUnicastFramesCounterRegister_HHD.u0.bits_0.msmLineRxUnicastFramesCounter_0 + + Default = 0x0000 + + Rx unicast frames counter bits 15:0 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '0'. */ + unsigned int msmLineRxUnicastFramesCounter_0 : 16; /* 1E.9070.F:0 ROS Default = 0x0000 */ + /* Rx unicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9071.F:0 ROS MSM Line Rx Unicast Frames Counter 1 [F:0] + AQ_MsmLineRxUnicastFramesCounterRegister_HHD.u1.bits_1.msmLineRxUnicastFramesCounter_1 + + Default = 0x0000 + + Rx unicast frames counter bits 31:16 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '0'. */ + unsigned int msmLineRxUnicastFramesCounter_1 : 16; /* 1E.9071.F:0 ROS Default = 0x0000 */ + /* Rx unicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxUnicastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Multicast Frames Counter Register: 1E.9074 */ +/* MSM Line Rx Multicast Frames Counter Register: 1E.9074 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9074.F:0 ROS MSM Line Rx Multicast Frames Counter 0 [F:0] + AQ_MsmLineRxMulticastFramesCounterRegister_HHD.u0.bits_0.msmLineRxMulticastFramesCounter_0 + + Default = 0x0000 + + Rx multicast frames counter bits 15:0 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '1' but not the broadcast address (all bits set '1' ). Pause frames are not counted. */ + unsigned int msmLineRxMulticastFramesCounter_0 : 16; /* 1E.9074.F:0 ROS Default = 0x0000 */ + /* Rx multicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9075.F:0 ROS MSM Line Rx Multicast Frames Counter 1 [F:0] + AQ_MsmLineRxMulticastFramesCounterRegister_HHD.u1.bits_1.msmLineRxMulticastFramesCounter_1 + + Default = 0x0000 + + Rx multicast frames counter bits 31:16 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '1' but not the broadcast address (all bits set '1' ). Pause frames are not counted. */ + unsigned int msmLineRxMulticastFramesCounter_1 : 16; /* 1E.9075.F:0 ROS Default = 0x0000 */ + /* Rx multicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxMulticastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Broadcast Frames Counter Register: 1E.9078 */ +/* MSM Line Rx Broadcast Frames Counter Register: 1E.9078 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9078.F:0 ROS MSM Line Rx Broadcast Frames Counter 0 [F:0] + AQ_MsmLineRxBroadcastFramesCounterRegister_HHD.u0.bits_0.msmLineRxBroadcastFramesCounter_0 + + Default = 0x0000 + + Rx broadcast frames counter bits 15:0 + + Notes: + Incremented with each valid frame received on the receive FIFO interface (FIFO) and all bits of the destination address were set '1'. */ + unsigned int msmLineRxBroadcastFramesCounter_0 : 16; /* 1E.9078.F:0 ROS Default = 0x0000 */ + /* Rx broadcast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9079.F:0 ROS MSM Line Rx Broadcast Frames Counter 1 [F:0] + AQ_MsmLineRxBroadcastFramesCounterRegister_HHD.u1.bits_1.msmLineRxBroadcastFramesCounter_1 + + Default = 0x0000 + + Rx broadcast frames counter bits 31:16 + + Notes: + Incremented with each valid frame received on the receive FIFO interface (FIFO) and all bits of the destination address were set '1'. */ + unsigned int msmLineRxBroadcastFramesCounter_1 : 16; /* 1E.9079.F:0 ROS Default = 0x0000 */ + /* Rx broadcast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxBroadcastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx Errors Counter Register: 1E.907C */ +/* MSM Line Tx Errors Counter Register: 1E.907C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.907C.F:0 ROS MSM Line Tx Errors Counter 0 [F:0] + AQ_MsmLineTxErrorsCounterRegister_HHD.u0.bits_0.msmLineTxErrorsCounter_0 + + Default = 0x0000 + + Rx errors counter bits 15:0 + + Notes: + Number of frames transmitted with error: + - FIFO Overflow Errors + - FIFO Underflow Errors */ + unsigned int msmLineTxErrorsCounter_0 : 16; /* 1E.907C.F:0 ROS Default = 0x0000 */ + /* Rx errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.907D.F:0 ROS MSM Line Tx Errors Counter 1 [F:0] + AQ_MsmLineTxErrorsCounterRegister_HHD.u1.bits_1.msmLineTxErrorsCounter_1 + + Default = 0x0000 + + Tx errors counter bits 31:16 + + Notes: + Number of frames transmitted with error: + - FIFO Overflow Errors + - FIFO Underflow Errors */ + unsigned int msmLineTxErrorsCounter_1 : 16; /* 1E.907D.F:0 ROS Default = 0x0000 */ + /* Tx errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx Unicast Frames Counter Register: 1E.9084 */ +/* MSM Line Tx Unicast Frames Counter Register: 1E.9084 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9084.F:0 ROS MSM Line Tx Unicast Frames Counter 0 [F:0] + AQ_MsmLineTxUnicastFramesCounterRegister_HHD.u0.bits_0.msmLineTxUnicastFramesCounter_0 + + Default = 0x0000 + + Tx unicast frames counter bits 15:0 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '0'. */ + unsigned int msmLineTxUnicastFramesCounter_0 : 16; /* 1E.9084.F:0 ROS Default = 0x0000 */ + /* Tx unicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9085.F:0 ROS MSM Line Tx Unicast Frames Counter 1 [F:0] + AQ_MsmLineTxUnicastFramesCounterRegister_HHD.u1.bits_1.msmLineTxUnicastFramesCounter_1 + + Default = 0x0000 + + Tx unicast frames counter bits 31:16 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '0'. */ + unsigned int msmLineTxUnicastFramesCounter_1 : 16; /* 1E.9085.F:0 ROS Default = 0x0000 */ + /* Tx unicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxUnicastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx Multicast Frames Counter Register: 1E.9088 */ +/* MSM Line Tx Multicast Frames Counter Register: 1E.9088 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9088.F:0 ROS MSM Line Tx Multicast Frames Counter 0 [F:0] + AQ_MsmLineTxMulticastFramesCounterRegister_HHD.u0.bits_0.msmLineTxMulticastFramesCounter_0 + + Default = 0x0000 + + Tx multicast frames counter bits 15:0 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '1' but not the broadcast address (all bits '1'). */ + unsigned int msmLineTxMulticastFramesCounter_0 : 16; /* 1E.9088.F:0 ROS Default = 0x0000 */ + /* Tx multicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9089.F:0 ROS MSM Line Tx Multicast Frames Counter 1 [F:0] + AQ_MsmLineTxMulticastFramesCounterRegister_HHD.u1.bits_1.msmLineTxMulticastFramesCounter_1 + + Default = 0x0000 + + Tx multicast frames counter bits 31:16 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '1' but not the broadcast address (all bits '1'). */ + unsigned int msmLineTxMulticastFramesCounter_1 : 16; /* 1E.9089.F:0 ROS Default = 0x0000 */ + /* Tx multicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxMulticastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx Broadcast Frames Counter Register: 1E.908C */ +/* MSM Line Tx Broadcast Frames Counter Register: 1E.908C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.908C.F:0 ROS MSM Line Tx Broadcast Frames Counter 0 [F:0] + AQ_MsmLineTxBroadcastFramesCounterRegister_HHD.u0.bits_0.msmLineTxBroadcastFramesCounter_0 + + Default = 0x0000 + + Tx broadcast frames counter bits 15:0 + + Notes: + Incremented with each frame written to the FIFO interface and all bits of the destination address set to '1'. */ + unsigned int msmLineTxBroadcastFramesCounter_0 : 16; /* 1E.908C.F:0 ROS Default = 0x0000 */ + /* Tx broadcast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.908D.F:0 ROS MSM Line Tx Broadcast Frames Counter 1 [F:0] + AQ_MsmLineTxBroadcastFramesCounterRegister_HHD.u1.bits_1.msmLineTxBroadcastFramesCounter_1 + + Default = 0x0000 + + Tx broadcast frames counter bits 31:16 + + Notes: + Incremented with each frame written to the FIFO interface and all bits of the destination address set to '1'. */ + unsigned int msmLineTxBroadcastFramesCounter_1 : 16; /* 1E.908D.F:0 ROS Default = 0x0000 */ + /* Tx broadcast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxBroadcastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Errors Counter Register: 1E.90C8 */ +/* MSM Line Rx Errors Counter Register: 1E.90C8 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.90C8.F:0 ROS MSM Line Rx Errors Counter 0 [F:0] + AQ_MsmLineRxErrorsCounterRegister_HHD.u0.bits_0.msmLineRxErrorsCounter_0 + + Default = 0x0000 + + Rx errors counter bits 15:0 + + Notes: + Number of frames received with error: + - FIFO Overflow Errors + - CRC Errors + - Payload Length Errors + - Jabber and Oversized Errors + - Alignment Errors + - The dedicated Error Code (0xfe, not a code error) was received */ + unsigned int msmLineRxErrorsCounter_0 : 16; /* 1E.90C8.F:0 ROS Default = 0x0000 */ + /* Rx errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.90C9.F:0 ROS MSM Line Rx Errors Counter 1 [F:0] + AQ_MsmLineRxErrorsCounterRegister_HHD.u1.bits_1.msmLineRxErrorsCounter_1 + + Default = 0x0000 + + Rx errors counter bits 31:16 + + Notes: + Number of frames received with error: + - FIFO Overflow Errors + - CRC Errors + - Payload Length Errors + - Jabber and Oversized Errors + - Alignment Errors + - The dedicated Error Code (0xfe, not a code error) was received */ + unsigned int msmLineRxErrorsCounter_1 : 16; /* 1E.90C9.F:0 ROS Default = 0x0000 */ + /* Rx errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Control: 1E.C000 */ +/* Global Control: 1E.C000 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Control */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Control */ + union + { + struct + { + /*! \brief 1E.C001.0 R/W uP Run Stall + AQ_GlobalControl_HHD.u1.bits_1.upRunStall + + Default = 0x0 + + 1 = uP Run Stall + 0 = uP normal mode + + + Notes: + Deactivates the uP. */ + unsigned int upRunStall : 1; /* 1E.C001.0 R/W Default = 0x0 */ + /* 1 = uP Run Stall + 0 = uP normal mode + */ + unsigned int reserved1 : 5; + /*! \brief 1E.C001.6 R/W uP Run Stall Override + AQ_GlobalControl_HHD.u1.bits_1.upRunStallOverride + + Default = 0x0 + + 0 = uP Run Stall from "MDIO Boot Load" pin. + 1 = uP Run Stall from See MCP Run Stall bit + + + + Notes: + This bit selects the uP Run Stall from either the "MDIO Boot Load" pin or the See MCP Run Stall bit. Pin no longer brought out as deprecated. */ + unsigned int upRunStallOverride : 1; /* 1E.C001.6 R/W Default = 0x0 */ + /* 0 = uP Run Stall from "MDIO Boot Load" pin. + 1 = uP Run Stall from See MCP Run Stall bit + + */ + unsigned int reserved0 : 8; + /*! \brief 1E.C001.F R/W uP Reset + AQ_GlobalControl_HHD.u1.bits_1.upReset + + Default = 0x0 + + 1 = Reset + + + Notes: + Resets the uP and the PIF master and slave bus. Will be active for a minimum of 100 microseconds. */ + unsigned int upReset : 1; /* 1E.C001.F R/W Default = 0x0 */ + /* 1 = Reset + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalControl_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Reset Control: 1E.C006 */ +/* Global Reset Control: 1E.C006 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Reset Control */ + union + { + struct + { + unsigned int reserved1 : 14; + /*! \brief 1E.C006.E R/WPD Global MMD Reset Disable + AQ_GlobalResetControl_HHD.u0.bits_0.globalMMD_ResetDisable + + Provisionable Default = 0x0 + + 1 = Disable the S/W reset to the Global MMD registers + 0 = Enable the S/W reset to the Global MMD registers + + + Notes: + Setting this bit prevents a Global S/W reset or Global S/W reset from resetting the Global MMD registers */ + unsigned int globalMMD_ResetDisable : 1; /* 1E.C006.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Disable the S/W reset to the Global MMD registers + 0 = Enable the S/W reset to the Global MMD registers + */ + unsigned int reserved0 : 1; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalResetControl_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Diagnostic Provisioning: 1E.C400 */ +/* Global Diagnostic Provisioning: 1E.C400 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Diagnostic Provisioning */ + union + { + struct + { + unsigned int reserved0 : 15; + /*! \brief 1E.C400.F R/WPD Enable Diagnostics + AQ_GlobalDiagnosticProvisioning_HHD.u0.bits_0.enableDiagnostics + + Provisionable Default = 0x1 + + 1 = Chip performs diagnostics on power-up + */ + unsigned int enableDiagnostics : 1; /* 1E.C400.F R/WPD Provisionable Default = 0x1 */ + /* 1 = Chip performs diagnostics on power-up */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalDiagnosticProvisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Thermal Provisioning: 1E.C420 */ +/* Global Thermal Provisioning: 1E.C420 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C420.F:0 R/WPD Reserved 0 [F:0] + AQ_GlobalThermalProvisioning_HHD.u0.bits_0.reserved_0 + + Provisionable Default = 0x0000 + + Internal reserved - do not modify + + */ + unsigned int reserved_0 : 16; /* 1E.C420.F:0 R/WPD Provisionable Default = 0x0000 */ + /* Internal reserved - do not modify + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C421.F:0 R/WPD High Temp Failure Threshold [F:0] + AQ_GlobalThermalProvisioning_HHD.u1.bits_1.highTempFailureThreshold + + Provisionable Default = 0x4600 + + [F:0] of high temperature failure threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 70 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A000 - 1.A001: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int highTempFailureThreshold : 16; /* 1E.C421.F:0 R/WPD Provisionable Default = 0x4600 */ + /* [F:0] of high temperature failure threshold */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C422.F:0 R/WPD Low Temp Failure Threshold [F:0] + AQ_GlobalThermalProvisioning_HHD.u2.bits_2.lowTempFailureThreshold + + Provisionable Default = 0x0000 + + [F:0] of low temperature failure threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 0 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A002 - 1.A003: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int lowTempFailureThreshold : 16; /* 1E.C422.F:0 R/WPD Provisionable Default = 0x0000 */ + /* [F:0] of low temperature failure threshold */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C423.F:0 R/WPD High Temp Warning Threshold [F:0] + AQ_GlobalThermalProvisioning_HHD.u3.bits_3.highTempWarningThreshold + + Provisionable Default = 0x3C00 + + [F:0] of high temperature warning threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD008. Default is 60 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A004 - 1.A005: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int highTempWarningThreshold : 16; /* 1E.C423.F:0 R/WPD Provisionable Default = 0x3C00 */ + /* [F:0] of high temperature warning threshold */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C424.F:0 R/WPD Low Temp Warning Threshold [F:0] + AQ_GlobalThermalProvisioning_HHD.u4.bits_4.lowTempWarningThreshold + + Provisionable Default = 0x0A00 + + [F:0] of low temperature warning threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 10 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A006 - 1.A007: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int lowTempWarningThreshold : 16; /* 1E.C424.F:0 R/WPD Provisionable Default = 0x0A00 */ + /* [F:0] of low temperature warning threshold */ + } bits_4; + uint16_t word_4; + } u4; +} AQ_GlobalThermalProvisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global LED Provisioning: 1E.C430 */ +/* Global LED Provisioning: 1E.C430 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C430.1:0 R/WPD LED #0 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_0ActivityStretch : 2; /* 1E.C430.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + /*! \brief 1E.C430.2 R/WPD LED #0 Transmit Activity + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_0TransmitActivity : 1; /* 1E.C430.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C430.3 R/WPD LED #0 Receive Activity + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_0ReceiveActivity : 1; /* 1E.C430.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C430.4 R/WPD LED #0 Connecting + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_0Connecting : 1; /* 1E.C430.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C430.5 R/WPD LED #0 100 Mb/s Link Established + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s. + + */ + unsigned int led_0_100Mb_sLinkEstablished : 1; /* 1E.C430.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s. + */ + /*! \brief 1E.C430.6 R/WPD LED #0 1 Gb/s Link Established + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_0_1Gb_sLinkEstablished : 1; /* 1E.C430.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C430.7 R/WPD LED #0 10 Gb/s Link Established + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_0_10Gb_sLinkEstablished : 1; /* 1E.C430.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C430.8 R/WPD LED #0 Manual Set + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_0ManualSet : 1; /* 1E.C430.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + /*! \brief 1E.C430.D:9 R/WPD Reserved Provisioning C430 [4:0] + AQ_GlobalLedProvisioning_HHD.u0.bits_0.reservedProvisioningC430 + + Provisionable Default = 0x00 + + Reserved for future use + */ + unsigned int reservedProvisioningC430 : 5; /* 1E.C430.D:9 R/WPD Provisionable Default = 0x00 */ + /* Reserved for future use */ + unsigned int reserved0 : 2; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C431.1:0 R/WPD LED #1 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_1ActivityStretch : 2; /* 1E.C431.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + /*! \brief 1E.C431.2 R/WPD LED #1 Transmit Activity + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_1TransmitActivity : 1; /* 1E.C431.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C431.3 R/WPD LED #1 Receive Activity + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_1ReceiveActivity : 1; /* 1E.C431.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C431.4 R/WPD LED #1 Connecting + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_1Connecting : 1; /* 1E.C431.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C431.5 R/WPD LED #1 100 Mb/s Link Established + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s. + + */ + unsigned int led_1_100Mb_sLinkEstablished : 1; /* 1E.C431.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s. + */ + /*! \brief 1E.C431.6 R/WPD LED #1 1 Gb/s Link Established + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_1_1Gb_sLinkEstablished : 1; /* 1E.C431.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C431.7 R/WPD LED #1 10 Gb/s Link Established + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_1_10Gb_sLinkEstablished : 1; /* 1E.C431.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C431.8 R/WPD LED #1 Manual Set + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_1ManualSet : 1; /* 1E.C431.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + /*! \brief 1E.C431.D:9 R/WPD Reserved Provisioning C431 [4:0] + AQ_GlobalLedProvisioning_HHD.u1.bits_1.reservedProvisioningC431 + + Provisionable Default = 0x00 + + Reserved for future use + */ + unsigned int reservedProvisioningC431 : 5; /* 1E.C431.D:9 R/WPD Provisionable Default = 0x00 */ + /* Reserved for future use */ + unsigned int reserved0 : 2; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C432.1:0 R/WPD LED #2 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_2ActivityStretch : 2; /* 1E.C432.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + /*! \brief 1E.C432.2 R/WPD LED #2 Transmit Activity + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_2TransmitActivity : 1; /* 1E.C432.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C432.3 R/WPD LED #2 Receive Activity + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_2ReceiveActivity : 1; /* 1E.C432.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C432.4 R/WPD LED #2 Connecting + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_2Connecting : 1; /* 1E.C432.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C432.5 R/WPD LED #2 100 Mb/s Link Established + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s. + */ + unsigned int led_2_100Mb_sLinkEstablished : 1; /* 1E.C432.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s. */ + /*! \brief 1E.C432.6 R/WPD LED #2 1 Gb/s Link Established + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_2_1Gb_sLinkEstablished : 1; /* 1E.C432.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C432.7 R/WPD LED #2 10 Gb/s Link Established + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_2_10Gb_sLinkEstablished : 1; /* 1E.C432.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C432.8 R/WPD LED #2 Manual Set + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_2ManualSet : 1; /* 1E.C432.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + /*! \brief 1E.C432.D:9 R/WPD Reserved Provisioning C432 [4:0] + AQ_GlobalLedProvisioning_HHD.u2.bits_2.reservedProvisioningC432 + + Provisionable Default = 0x00 + + Reserved for future use + */ + unsigned int reservedProvisioningC432 : 5; /* 1E.C432.D:9 R/WPD Provisionable Default = 0x00 */ + /* Reserved for future use */ + unsigned int reserved0 : 2; + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C437.0 R/WPD LED Operation Mode + AQ_GlobalLedProvisioning_HHD.u7.bits_7.ledOperationMode + + Provisionable Default = 0x0 + + 1 = LED link activity in Mode #2 + 0 = LED link activity in Aquantia classic mode + + + Notes: + When set to 1, the LED blinking rate is based on Mode #2 algorithm. When set to 0, the LED blinking rate is based on the classic Aquantia algorithm. */ + unsigned int ledOperationMode : 1; /* 1E.C437.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED link activity in Mode #2 + 0 = LED link activity in Aquantia classic mode + */ + unsigned int reserved0 : 15; + } bits_7; + uint16_t word_7; + } u7; + /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_8; + uint16_t word_8; + } u8; + /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_9; + uint16_t word_9; + } u9; + /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_10; + uint16_t word_10; + } u10; + /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_11; + uint16_t word_11; + } u11; + /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_12; + uint16_t word_12; + } u12; + /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_13; + uint16_t word_13; + } u13; + /*! \brief Union for bit and word level access of word 14 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_14; + uint16_t word_14; + } u14; +} AQ_GlobalLedProvisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global General Provisioning: 1E.C440 */ +/* Global General Provisioning: 1E.C440 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved3 : 2; + unsigned int reserved2 : 1; + /*! \brief 1E.C441.3 R/WPD MDIO Preamble Detection Disable + AQ_GlobalGeneralProvisioning_HHD.u1.bits_1.mdioPreambleDetectionDisable + + Provisionable Default = 0x0 + + 1 = Suppress preamble detection on MDIO + 0 = Enable preamble detection on MDIO + + */ + unsigned int mdioPreambleDetectionDisable : 1; /* 1E.C441.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = Suppress preamble detection on MDIO + 0 = Enable preamble detection on MDIO + */ + /*! \brief 1E.C441.4 R/WPD MDIO Drive Configuration + AQ_GlobalGeneralProvisioning_HHD.u1.bits_1.mdioDriveConfiguration + + Provisionable Default = 0x0 + + 0 = MDIO driver is in normal mode + 1 = MDIO driver is in open drain mode + + + Notes: + When the MDIO driver is in open drain mode during a read cycle, "0" data will be actively driven out of the MDIO, "1" data will set the MDIO driver in high impedance state and an external pullup will set the MDIO line to "1". The Turn-Around "0" will also be actively driven out of the MDIO, therefore in open drain mode, the Turn-Around is still "Z0". */ + unsigned int mdioDriveConfiguration : 1; /* 1E.C441.4 R/WPD Provisionable Default = 0x0 */ + /* 0 = MDIO driver is in normal mode + 1 = MDIO driver is in open drain mode + */ + unsigned int reserved1 : 8; + /*! \brief 1E.C441.D R/WPD MDIO Read MSW First Enable + AQ_GlobalGeneralProvisioning_HHD.u1.bits_1.mdioReadMSW_FirstEnable + + Provisionable Default = 0x0 + + 1 = MSW of counter must be read first + 0 = LSW of counter must be read first + + + Notes: + This bit configures whether the MSW or LSW must be read first for counters greater than 16 bits. */ + unsigned int mdioReadMSW_FirstEnable : 1; /* 1E.C441.D R/WPD Provisionable Default = 0x0 */ + /* 1 = MSW of counter must be read first + 0 = LSW of counter must be read first + */ + /*! \brief 1E.C441.E R/WPD MDIO Broadcast Mode Enable + AQ_GlobalGeneralProvisioning_HHD.u1.bits_1.mdioBroadcastModeEnable + + Provisionable Default = 0x0 + + 1 = Enable broadcast on address set in 1E.C446 + 0 = Disable broadcast on n address set in 1E.C446 + + + Notes: + When enabled, writes and load MMD address opcodes are supported. Read opcodes are ignored. */ + unsigned int mdioBroadcastModeEnable : 1; /* 1E.C441.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable broadcast on address set in 1E.C446 + 0 = Disable broadcast on n address set in 1E.C446 + */ + unsigned int reserved0 : 1; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global General Provisioning */ + union + { + struct + { + /*! \brief 1E.C442.0 R/W Daisy Chain Reset + AQ_GlobalGeneralProvisioning_HHD.u2.bits_2.daisyChainReset + + Default = 0x0 + + 1 = Reset the daisy chain + + + Notes: + Toggling this bit from 0 to 1 will reload the IRAM and DRAM and reset the uP. The uP will be in uP run stall during the reload process. After the reload process, uP run stall will be de-asserted and the uP reset will be asserted. Note that before setting this bit, the See Soft Reset bit needs to be de-asserted. */ + unsigned int daisyChainReset : 1; /* 1E.C442.0 R/W Default = 0x0 */ + /* 1 = Reset the daisy chain + */ + unsigned int reserved0 : 15; + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of Global General Provisioning */ + union + { + struct + { + /*! \brief 1E.C447.4:0 R/WPD MDIO Broadcast Address Configuration [4:0] + AQ_GlobalGeneralProvisioning_HHD.u7.bits_7.mdioBroadcastAddressConfiguration + + Provisionable Default = 0x1F + + Broadcast address + + + Notes: + Allows setting the broadcast address. By default this is set to 0x1F */ + unsigned int mdioBroadcastAddressConfiguration : 5; /* 1E.C447.4:0 R/WPD Provisionable Default = 0x1F */ + /* Broadcast address + */ + unsigned int reserved0 : 11; + } bits_7; + uint16_t word_7; + } u7; + /*! \brief Union for bit and word level access of word 8 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_8; + uint16_t word_8; + } u8; + /*! \brief Union for bit and word level access of word 9 of Global General Provisioning */ + union + { + struct + { + /*! \brief 1E.C449.6:0 R/W MDIO Preamble Length [6:0] + AQ_GlobalGeneralProvisioning_HHD.u9.bits_9.mdioPreambleLength + + Default = 0x02 + + MDIO Preamble Length + + */ + unsigned int mdioPreambleLength : 7; /* 1E.C449.6:0 R/W Default = 0x02 */ + /* MDIO Preamble Length + */ + unsigned int reserved0 : 9; + } bits_9; + uint16_t word_9; + } u9; +} AQ_GlobalGeneralProvisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global NVR Provisioning: 1E.C450 */ +/* Global NVR Provisioning: 1E.C450 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global NVR Provisioning */ + union + { + struct + { + /*! \brief 1E.C450.1:0 R/WPD NVR Address Length [1:0] + AQ_GlobalNvrProvisioning_HHD.u0.bits_0.nvrAddressLength + + Provisionable Default = 0x2 + + NVR address length ranges from 0 bytes up to 3 bytes + + + Notes: + This sets the length of the address field used in read and write operations. Use of this field is enabled via Bit 8 of See Global NVR Provisioning 2: Address 1E.C451 . + */ + unsigned int nvrAddressLength : 2; /* 1E.C450.1:0 R/WPD Provisionable Default = 0x2 */ + /* NVR address length ranges from 0 bytes up to 3 bytes + */ + unsigned int reserved2 : 2; + /*! \brief 1E.C450.6:4 R/WPD NVR Dummy Length [2:0] + AQ_GlobalNvrProvisioning_HHD.u0.bits_0.nvrDummyLength + + Provisionable Default = 0x0 + + NVR dummy length ranges from 0 bytes to 4 bytes + + + Notes: + This sets the length of the dummy field used in some manufacturer's read status and write status operations. + */ + unsigned int nvrDummyLength : 3; /* 1E.C450.6:4 R/WPD Provisionable Default = 0x0 */ + /* NVR dummy length ranges from 0 bytes to 4 bytes + */ + unsigned int reserved1 : 1; + /*! \brief 1E.C450.A:8 R/WPD NVR Data Length [2:0] + AQ_GlobalNvrProvisioning_HHD.u0.bits_0.nvrDataLength + + Provisionable Default = 0x4 + + NVR data length ranges from 0 bytes to 4 bytes + + + Notes: + This sets the length of the data burst used in read and write operations. + */ + unsigned int nvrDataLength : 3; /* 1E.C450.A:8 R/WPD Provisionable Default = 0x4 */ + /* NVR data length ranges from 0 bytes to 4 bytes + */ + unsigned int reserved0 : 5; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global NVR Provisioning */ + union + { + struct + { + /*! \brief 1E.C451.7:0 R/WPD NVR Clock Divide [7:0] + AQ_GlobalNvrProvisioning_HHD.u1.bits_1.nvrClockDivide + + Provisionable Default = 0xA0 + + NVR clock divide. Clock frequency is divided by the NVR clock divide + 1 + + */ + unsigned int nvrClockDivide : 8; /* 1E.C451.7:0 R/WPD Provisionable Default = 0xA0 */ + /* NVR clock divide. Clock frequency is divided by the NVR clock divide + 1 + */ + /*! \brief 1E.C451.8 R/WPD NVR Address Length Override + AQ_GlobalNvrProvisioning_HHD.u1.bits_1.nvrAddressLengthOverride + + Provisionable Default = 0x0 + + 0 = NVR address length is based on the "NVR_SIZE" pin. + 1 = NVR address length is based on the See NVR Address Length [1:0] register + + + Notes: + When this bit = 0 and NVR_SIZE pin = 0, the NVR address length is 2 bytes. When this bit = 0 and the NVR_SIZE pin = 1, the NVR address length is 3 bytes. When this bit = 1 the NVR address length is from the See NVR Address Length [1:0] */ + unsigned int nvrAddressLengthOverride : 1; /* 1E.C451.8 R/WPD Provisionable Default = 0x0 */ + /* 0 = NVR address length is based on the "NVR_SIZE" pin. + 1 = NVR address length is based on the See NVR Address Length [1:0] register + */ + unsigned int reserved0 : 7; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global NVR Provisioning */ + union + { + struct + { + /*! \brief 1E.C452.0 R/W NVR Daisy Chain Disable + AQ_GlobalNvrProvisioning_HHD.u2.bits_2.nvrDaisyChainDisable + + Default = 0x0 + + 1 = Disable the Daisy Chain + + + Notes: + When in daisy chain master mode, the daisy chain and MDIO can both access the SPI. Setting this bit to 1 will disable the daisy chain from accessing the SPI and force it into a reset state. */ + unsigned int nvrDaisyChainDisable : 1; /* 1E.C452.0 R/W Default = 0x0 */ + /* 1 = Disable the Daisy Chain + */ + /*! \brief 1E.C452.1 R/W NVR Daisy Chain Clock Divide Override + AQ_GlobalNvrProvisioning_HHD.u2.bits_2.nvrDaisyChainClockDivideOverride + + Default = 0x0 + + 1 = Override NVR clock divide when in daisy chain master mode + + + Notes: + When in daisy chain master mode, the clock divide configuration is received from the FLASH. This bit will override the clock divide configuration from the FLASH with the See NVR Clock Divide [7:0] . */ + unsigned int nvrDaisyChainClockDivideOverride : 1; /* 1E.C452.1 R/W Default = 0x0 */ + /* 1 = Override NVR clock divide when in daisy chain master mode + */ + unsigned int reserved0 : 14; + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global NVR Provisioning */ + union + { + struct + { + unsigned int reserved1 : 4; + /*! \brief 1E.C453.4 R/W NVR Reset + AQ_GlobalNvrProvisioning_HHD.u3.bits_3.nvrReset + + Default = 0x0 + + 1 = Reset SPI + + */ + unsigned int nvrReset : 1; /* 1E.C453.4 R/W Default = 0x0 */ + /* 1 = Reset SPI + */ + unsigned int reserved0 : 11; + } bits_3; + uint16_t word_3; + } u3; +} AQ_GlobalNvrProvisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Reserved Provisioning: 1E.C470 */ +/* Global Reserved Provisioning: 1E.C470 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved2 : 4; + /*! \brief 1E.C470.4 R/WSC Initiate Cable Diagnostics + AQ_GlobalReservedProvisioning_HHD.u0.bits_0.initiateCableDiagnostics + + Default = 0x0 + + 1 = Perform cable diagnostics + + + Notes: + Perform cable diagnostics regardless of link state. If link is up, setting this bit will cause the link to drop while diagnostics are performed. This bit is self-clearing upon completion of the cable diagnostics. + + NOTE!! This is a processor intensive operation. Completion of this operation can also be monitored via 1E.C831.F */ + unsigned int initiateCableDiagnostics : 1; /* 1E.C470.4 R/WSC Default = 0x0 */ + /* 1 = Perform cable diagnostics + */ + unsigned int reserved1 : 3; + unsigned int reserved0 : 5; + /*! \brief 1E.C470.E:D R/WPD Extended MDI Diagnostics Select [1:0] + AQ_GlobalReservedProvisioning_HHD.u0.bits_0.extendedMdiDiagnosticsSelect + + Provisionable Default = 0x0 + + 0x0 = TDR Data + 0x1 = RFI Channel PSD + 0x2 = Noise PSD while the local Tx is Off + 0x3 = Noise PSD while the local Tx is On + + + Notes: + These bits select what sort of cable diagnostics to perform. For regular cable diagnostics, Bit F is set to zero, and the diagnostics are triggered by setting Bit 4. For extended diagnostics, Bit F is set to 1, and the desired extended diagnostics are selected by Bits E:D. The routine is then triggered by setting Bit 4. Each of the extended diagnostic routines present data for all for MDI pairs (A, B, C, D) consecutively, and after the data for each channel is gathered Bits F:D are reset. To get the data for the next pair, Bits F:D must be set back to the desired value (which must be the same as the initial channel). This continues until the data for all channels has been gathered. The address in memory where the data is stored is given in 1E.C802 and 1E.C804. + + For the case of PSD, the structure is as follows: + Int32 info + Int16 data[Len] + Info = Len << 16 | TxEnable << 8 | Pair (0 = A, etc.) + + For TDR: + Int32 info + Int16 tdr_A[Len] + Int16 tdr_B[Len] + Int16 tdr_C[Len] + Int16 tdr_D[Len] + + Info = Len << 16 | Channel + + TDR data is from the current pair to all other pairs. + + At the end of retrieving extended MDI diag data, the part will be reset. Conversely the only way to exit this routine once it starts is to issue a PMA reset. */ + unsigned int extendedMdiDiagnosticsSelect : 2; /* 1E.C470.E:D R/WPD Provisionable Default = 0x0 */ + /* 0x0 = TDR Data + 0x1 = RFI Channel PSD + 0x2 = Noise PSD while the local Tx is Off + 0x3 = Noise PSD while the local Tx is On + */ + /*! \brief 1E.C470.F R/WPD Diagnostics Select + AQ_GlobalReservedProvisioning_HHD.u0.bits_0.diagnosticsSelect + + Provisionable Default = 0x0 + + 1 = Provide Extended MDI Diagnostics Information. + 0 = Provide normal cable diagnostics + + + Notes: + These bits select what sort of cable diagnostics to perform. For regular cable diagnostics, Bit F is set to zero, and the diagnostics are triggered by setting Bit 4. For extended diagnostics, Bit F is set to 1, and the desired extended diagnostics are selected by Bits E:D. The routine is then triggered by setting Bit 4. Each of the extended diagnostic routines present data for all for MDI pairs (A, B, C, D) consecutively, and after the data for each channel is gathered Bits F:D are reset. To get the data for the next pair, Bits F:D must be set back to the desired value (which must be the same as the initial channel). This continues until the data for all channels has been gathered. The address in memory where the data is stored is given in 1E.C802 and 1E.C804. + + For the case of PSD, the structure is as follows: + Int32 info + Int16 data[Len] + Info = Len << 16 | TxEnable << 8 | Pair (0 = A, etc.) + + For TDR: + Int32 info + Int16 tdr_A[Len] + Int16 tdr_B[Len] + Int16 tdr_C[Len] + Int16 tdr_D[Len] + + Info = Len << 16 | Channel + + TDR data is from the current pair to all other pairs. + + At the end of retrieving extended MDI diag data, the part will be reset. Conversely the only way to exit this routine once it starts is to issue a PMA reset. */ + unsigned int diagnosticsSelect : 1; /* 1E.C470.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Provide Extended MDI Diagnostics Information. + 0 = Provide normal cable diagnostics + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C471.5:0 R/WuP Daisy-Chain Hop-Count Override Value [5:0] + AQ_GlobalReservedProvisioning_HHD.u1.bits_1.daisy_chainHop_countOverrideValue + + Default = 0x00 + + The value to use for the PHY's daisy-chain hop-count. Valid values are from 0 -> 47 + + + Notes: + Daisy-Chain Hop-Count Override should be used during MDIO boot-load operation, as the daisy-chain hop-count does not function when the daisy-chain is disabled (1E.C452.0). Setting this bit tells the processor where in the daisy-chain it is, so that the provisioning operation will function correctly. */ + unsigned int daisy_chainHop_countOverrideValue : 6; /* 1E.C471.5:0 R/WuP Default = 0x00 */ + /* The value to use for the PHY's daisy-chain hop-count. Valid values are from 0 -> 47 + */ + /*! \brief 1E.C471.6 R/WuP Enable Daisy-Chain Hop-Count Override + AQ_GlobalReservedProvisioning_HHD.u1.bits_1.enableDaisy_chainHop_countOverride + + Default = 0x0 + + 1 = Hop-count is set by Bits 5:0 + 0 = Hop-count is determined by the daisy-chain + + + Notes: + Daisy-Chain Hop-Count Override should be used during MDIO boot-load operation, as the daisy-chain hop-count does not function when the daisy-chain is disabled (1E.C452.0). Setting this bit tells the processor where in the daisy-chain it is, so that the provisioning operation will function correctly. */ + unsigned int enableDaisy_chainHop_countOverride : 1; /* 1E.C471.6 R/WuP Default = 0x0 */ + /* 1 = Hop-count is set by Bits 5:0 + 0 = Hop-count is determined by the daisy-chain + */ + unsigned int reserved0 : 9; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C472.0 R/WPDuP Enable 5th Channel RFI Cancellation + AQ_GlobalReservedProvisioning_HHD.u2.bits_2.enable_5thChannelRfiCancellation + + Provisionable Default = 0x0 + + 1 = 5th channel and RFI cancellers operation enabled + 0 = 5th channel AFE is powered down, 5th channel digital is clock gated, RFI cancellers are disabled + + + Notes: + Note: The value of this bit at the time of Autonegotiation sets the local PHY behavior until the next time Autonegotiation occurs. */ + unsigned int enable_5thChannelRfiCancellation : 1; /* 1E.C472.0 R/WPDuP Provisionable Default = 0x0 */ + /* 1 = 5th channel and RFI cancellers operation enabled + 0 = 5th channel AFE is powered down, 5th channel digital is clock gated, RFI cancellers are disabled + */ + /*! \brief 1E.C472.1 R/WPDuP Enable XENPAK Register Space + AQ_GlobalReservedProvisioning_HHD.u2.bits_2.enableXenpakRegisterSpace + + Provisionable Default = 0x0 + + 1 = XENPAK register space enabled + 0 = XENPAK register space disabled + + */ + unsigned int enableXenpakRegisterSpace : 1; /* 1E.C472.1 R/WPDuP Provisionable Default = 0x0 */ + /* 1 = XENPAK register space enabled + 0 = XENPAK register space disabled + */ + /*! \brief 1E.C472.5:2 R/WPD External VDD Change Request [3:0] + AQ_GlobalReservedProvisioning_HHD.u2.bits_2.externalVddChangeRequest + + Provisionable Default = 0x0 + + The amount of VDD change requested by firmware, in mV (2's complement value). + + */ + unsigned int externalVddChangeRequest : 4; /* 1E.C472.5:2 R/WPD Provisionable Default = 0x0 */ + /* The amount of VDD change requested by firmware, in mV (2's complement value). + */ + /*! \brief 1E.C472.6 R/WPD Tunable External VDD Power Supply Present + AQ_GlobalReservedProvisioning_HHD.u2.bits_2.tunableExternalVddPowerSupplyPresent + + Provisionable Default = 0x0 + + 1 = Tunable external VDD power supply present + 0 = No tunable external VDD power supply present + + + Notes: + This bit must be set if tuning of external power supply is desired. */ + unsigned int tunableExternalVddPowerSupplyPresent : 1; /* 1E.C472.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Tunable external VDD power supply present + 0 = No tunable external VDD power supply present + */ + unsigned int reserved1 : 7; + /*! \brief 1E.C472.E R/WPD Enable VDD Power Supply Tuning + AQ_GlobalReservedProvisioning_HHD.u2.bits_2.enableVddPowerSupplyTuning + + Provisionable Default = 0x0 + + 1 = Enable external VDD power supply tuning + 0 = Disable external VDD power supply tuning is disabled + + + Notes: + This bit controls whether the PHY attempts to tune the external VDD power supply via the SMBus. This bit is only operational if the external supply is present. (See 1E.C472.6) */ + unsigned int enableVddPowerSupplyTuning : 1; /* 1E.C472.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable external VDD power supply tuning + 0 = Disable external VDD power supply tuning is disabled + */ + unsigned int reserved0 : 1; + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C473.7:0 R/WPD Training SNR [7:0] + AQ_GlobalReservedProvisioning_HHD.u3.bits_3.trainingSNR + + Provisionable Default = 0x00 + + SNR during 10G training on the worst channel. SNR is in steps of 0.1dB + + + Notes: + The SNR margin that is enjoyed by the worst channel, over and above the minimum SNR required to operate at a BER of 10-12. It is reported with 0.1 dB of resolution to an accuracy of 0.5 dB within the range of -12.7 dB to 12.7 dB. The number is in offset binary, with 0.0 dB represented by 0x8000. */ + unsigned int trainingSNR : 8; /* 1E.C473.7:0 R/WPD Provisionable Default = 0x00 */ + /* SNR during 10G training on the worst channel. SNR is in steps of 0.1dB + */ + /*! \brief 1E.C473.A:8 R/WPD Rate Transition Request [2:0] + AQ_GlobalReservedProvisioning_HHD.u3.bits_3.rateTransitionRequest + + Provisionable Default = 0x0 + + 0 = No Transition + 1 = Reserved + 2 = Reserved + 3 = Retrain at 10G + 4 = Retrain at 5G + 5 = Retrain at 2.5G + 6 = Retrain at 1G + 7 = Reserved + + */ + unsigned int rateTransitionRequest : 3; /* 1E.C473.A:8 R/WPD Provisionable Default = 0x0 */ + /* 0 = No Transition + 1 = Reserved + 2 = Reserved + 3 = Retrain at 10G + 4 = Retrain at 5G + 5 = Retrain at 2.5G + 6 = Retrain at 1G + 7 = Reserved + */ + unsigned int reserved0 : 5; + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C474.0 R/W NVR Daisy Chain Kickstart + AQ_GlobalReservedProvisioning_HHD.u4.bits_4.nvrDaisyChainKickstart + + Default = 0x0 + + 1 = Kickstart the Daisy Chain + + + Notes: + When in daisy chain master mode, the PHY0 can kickstart the daisy chain. The kickstart will not reload the IRAM/DRAM or reset the uP for PHY0. It will just read the FLASH and transfer the FLASH data to the daisy chain. */ + unsigned int nvrDaisyChainKickstart : 1; /* 1E.C474.0 R/W Default = 0x0 */ + /* 1 = Kickstart the Daisy Chain + */ + /*! \brief 1E.C474.F:1 R/WPD Reserved Provisioning 5 [F:1] + AQ_GlobalReservedProvisioning_HHD.u4.bits_4.reservedProvisioning_5 + + Provisionable Default = 0x0000 + + Reserved for future use + + */ + unsigned int reservedProvisioning_5 : 15; /* 1E.C474.F:1 R/WPD Provisionable Default = 0x0000 */ + /* Reserved for future use + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved1 : 2; + /*! \brief 1E.C475.2 R/WPD Smart Power-Down Enable + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.smartPower_downEnable + + Provisionable Default = 0x0 + + 1 = Enable smart power down mode + 0 = Smart power-down mode disabled + + + Notes: + Smart power down (SPD) is the lowest power mode at which PHY is able to autonegotiate. SPD can be enabled with bit 1E.C475.2 */ + unsigned int smartPower_downEnable : 1; /* 1E.C475.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable smart power down mode + 0 = Smart power-down mode disabled + */ + /*! \brief 1E.C475.3 R/WPD Deadlock Avoidance Enable + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.deadlockAvoidanceEnable + + Provisionable Default = 0x0 + + 1 = SPD with deadlock avoidance: PHY transmits autonegotiation pulses (FLPs) at a slower rate (~ 1 FLP/ 100ms) than specified by autonegotiation standard (~1 FLP / 8.25ms). Receiver is active and able to detect the pulses. + 0 = SPD without deadlock avoidance: PHY transmitter is shut down, no autonegotiation pulses are sent on the line but the receiver is active and able to detect the pulses + + */ + unsigned int deadlockAvoidanceEnable : 1; /* 1E.C475.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = SPD with deadlock avoidance: PHY transmits autonegotiation pulses (FLPs) at a slower rate (~ 1 FLP/ 100ms) than specified by autonegotiation standard (~1 FLP / 8.25ms). Receiver is active and able to detect the pulses. + 0 = SPD without deadlock avoidance: PHY transmitter is shut down, no autonegotiation pulses are sent on the line but the receiver is active and able to detect the pulses + */ + /*! \brief 1E.C475.4 R/WPD CFR Support + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrSupport + + Provisionable Default = 0x0 + + 1 = Local PHY supports Cisco Fast Retrain + 0 = Local PHY does support Cisco Fast Retrain + + */ + unsigned int cfrSupport : 1; /* 1E.C475.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY supports Cisco Fast Retrain + 0 = Local PHY does support Cisco Fast Retrain + */ + /*! \brief 1E.C475.5 R/WPD CFR THP + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrTHP + + Provisionable Default = 0x0 + + 1 = Local PHY requires local PHY to enable THP + 0 = Local PHY does not require local PHY to enable THP + + */ + unsigned int cfrTHP : 1; /* 1E.C475.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY requires local PHY to enable THP + 0 = Local PHY does not require local PHY to enable THP + */ + /*! \brief 1E.C475.6 R/WPD CFR Extended Maxwait + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrExtendedMaxwait + + Provisionable Default = 0x0 + + 1 = Local PHY requires extended maxwait + 0 = Local PHY does not require extended maxwait + + */ + unsigned int cfrExtendedMaxwait : 1; /* 1E.C475.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY requires extended maxwait + 0 = Local PHY does not require extended maxwait + */ + /*! \brief 1E.C475.7 R/WPD CFR Disable Timer + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrDisableTimer + + Provisionable Default = 0x0 + + 1 = Local PHY requires cfr_disable timer + 0 = Local PHY does not require cfr_disable timer + + */ + unsigned int cfrDisableTimer : 1; /* 1E.C475.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY requires cfr_disable timer + 0 = Local PHY does not require cfr_disable timer + */ + /*! \brief 1E.C475.8 R/WPD CFR LP Support + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrLpSupport + + Provisionable Default = 0x0 + + 1 = Link partner supports Cisco Fast Retrain + 0 = Link partner does support Cisco Fast Retrain + + */ + unsigned int cfrLpSupport : 1; /* 1E.C475.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner supports Cisco Fast Retrain + 0 = Link partner does support Cisco Fast Retrain + */ + /*! \brief 1E.C475.9 R/WPD CFR LP THP + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrLpTHP + + Provisionable Default = 0x0 + + 1 = Link partner requires local PHY to enable THP + 0 = Link partner does not require local PHY to enable THP + + */ + unsigned int cfrLpTHP : 1; /* 1E.C475.9 R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner requires local PHY to enable THP + 0 = Link partner does not require local PHY to enable THP + */ + /*! \brief 1E.C475.A R/WPD CFR LP Extended Maxwait + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrLpExtendedMaxwait + + Provisionable Default = 0x0 + + 1 = Link partner requires extended maxwait + 0 = Link partner does not require extended maxwait + + */ + unsigned int cfrLpExtendedMaxwait : 1; /* 1E.C475.A R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner requires extended maxwait + 0 = Link partner does not require extended maxwait + */ + /*! \brief 1E.C475.B R/WPD CFR LP Disable Timer + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrLpDisableTimer + + Provisionable Default = 0x0 + + 1 = Link partner requires cfr_disable timer + 0 = Link partner does not require cfr_disable timer + + */ + unsigned int cfrLpDisableTimer : 1; /* 1E.C475.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner requires cfr_disable timer + 0 = Link partner does not require cfr_disable timer + */ + /*! \brief 1E.C475.C R/WPD Reserved Provisioning 6 + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.reservedProvisioning_6 + + Provisionable Default = 0x0 + + Internal reserved - do not modify + + */ + unsigned int reservedProvisioning_6 : 1; /* 1E.C475.C R/WPD Provisionable Default = 0x0 */ + /* Internal reserved - do not modify + */ + /*! \brief 1E.C475.D R/WPD Smart Power-Down Status + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.smartPower_downStatus + + Provisionable Default = 0x0 + + 1 = Smart Power-Down Active + 0 = Smart Power-Down Inactive + + */ + unsigned int smartPower_downStatus : 1; /* 1E.C475.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Smart Power-Down Active + 0 = Smart Power-Down Inactive + */ + unsigned int reserved0 : 2; + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Dummy union to fill space in the structure Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Dummy union to fill space in the structure Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_7; + uint16_t word_7; + } u7; + /*! \brief Union for bit and word level access of word 8 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C478.A:0 R/WPD Reserved Provisioning 9 [A:0] + AQ_GlobalReservedProvisioning_HHD.u8.bits_8.reservedProvisioning_9 + + Provisionable Default = 0x000 + + Reserved for future use + + */ + unsigned int reservedProvisioning_9 : 11; /* 1E.C478.A:0 R/WPD Provisionable Default = 0x000 */ + /* Reserved for future use + */ + /*! \brief 1E.C478.E:B R/WPD DTE Drop Reporting Timer [3:0] + AQ_GlobalReservedProvisioning_HHD.u8.bits_8.dteDropReportingTimer + + Provisionable Default = 0x0 + + Number of seconds between loss of link partner filter and assertion of no-power-needed state, in 5 second increments (e.g. 0x4 = 20 seconds). + + + Notes: + These bits are used to set how long the PHY waits after it no longer detects the link partner filter before declaring that power is not needed. */ + unsigned int dteDropReportingTimer : 4; /* 1E.C478.E:B R/WPD Provisionable Default = 0x0 */ + /* Number of seconds between loss of link partner filter and assertion of no-power-needed state, in 5 second increments (e.g. 0x4 = 20 seconds). + */ + /*! \brief 1E.C478.F R/WPD DTE Enable + AQ_GlobalReservedProvisioning_HHD.u8.bits_8.dteEnable + + Provisionable Default = 0x0 + + 1 = Enable DTE + 0 = Disable DTE + + */ + unsigned int dteEnable : 1; /* 1E.C478.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable DTE + 0 = Disable DTE + */ + } bits_8; + uint16_t word_8; + } u8; + /*! \brief Union for bit and word level access of word 9 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C479.E:0 R/WPD Reserved Provisioning 10 [E:0] + AQ_GlobalReservedProvisioning_HHD.u9.bits_9.reservedProvisioning_10 + + Provisionable Default = 0x0000 + + Reserved for future use + + */ + unsigned int reservedProvisioning_10 : 15; /* 1E.C479.E:0 R/WPD Provisionable Default = 0x0000 */ + /* Reserved for future use + */ + /*! \brief 1E.C479.F R/WPD Power Up Stall + AQ_GlobalReservedProvisioning_HHD.u9.bits_9.powerUpStall + + Provisionable Default = 0x0 + + 1 = Stall FW at Power Up + 0 = Unstall the FW + + + Notes: + This bit needs to be provisioned in Power Up Init for firmware to stall. */ + unsigned int powerUpStall : 1; /* 1E.C479.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Stall FW at Power Up + 0 = Unstall the FW + */ + } bits_9; + uint16_t word_9; + } u9; + /*! \brief Union for bit and word level access of word 10 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C47A.1:0 R/WPD Rate [1:0] + AQ_GlobalReservedProvisioning_HHD.u10.bits_10.rate + + Provisionable Default = 0x0 + + 0x3 = 10G + 0x2 = 1G + 0x1 = 100M + 0x0 = reserved + + + Notes: + These bits select the rate for the loopback and packet generation. SERDES configuration, as well autonegotiation is controlled accordingly when a loopback is selected. For instance, if 100M system loopback on the network interface is selected, SGMII on the system interface is enabled to connect at 100M, and if passthrough is enabled 100BASE-TX will be the only advertised rate and will force a re-autonegotiation if not already connected at 100M. + + NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F + + The controls in this register are identical to, and mirrored with, the controls in 4.C444. */ + unsigned int rate : 2; /* 1E.C47A.1:0 R/WPD Provisionable Default = 0x0 */ + /* 0x3 = 10G + 0x2 = 1G + 0x1 = 100M + 0x0 = reserved + */ + /*! \brief 1E.C47A.2 R/WPD Reserved Provisioning 11a + AQ_GlobalReservedProvisioning_HHD.u10.bits_10.reservedProvisioning_11a + + Provisionable Default = 0x0 + + Reserved for future use + + */ + unsigned int reservedProvisioning_11a : 1; /* 1E.C47A.2 R/WPD Provisionable Default = 0x0 */ + /* Reserved for future use + */ + /*! \brief 1E.C47A.3 R/WPD System I/F Packet Generation + AQ_GlobalReservedProvisioning_HHD.u10.bits_10.systemI_fPacketGeneration + + Provisionable Default = 0x0 + + 1 = CRPAT packet generation out 10G system interface + 0 = No CRPAT packet generation out 10G system interface + + + Notes: + Selecting this mode of operation causes the CRPAT packet generator in the PHY to output CRPAT packets on the selected 10G system interface (4.C441.F:E) + + NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F + + The controls in this register are identical to, and mirrored with, the controls in 4.C444. */ + unsigned int systemI_fPacketGeneration : 1; /* 1E.C47A.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = CRPAT packet generation out 10G system interface + 0 = No CRPAT packet generation out 10G system interface + */ + /*! \brief 1E.C47A.4 R/WPD Look-Aside Port Packet Generation + AQ_GlobalReservedProvisioning_HHD.u10.bits_10.look_asidePortPacketGeneration + + Provisionable Default = 0x0 + + 1 = CRPAT packet generation out 10G look-aside interface (KR0) + 0 = No CRPAT packet generation out 10G look-aside interface (KR0) + + + Notes: + Selecting this mode of operation causes the CRPAT packet generator in the PHY to output on KR0. + + NOTE!! This only functions if KR1 (SERDES2) is selected as the system interface in (4.C441.F:E). + + NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F + + The controls in this register are identical to, and mirrored with, the controls in 4.C444. */ + unsigned int look_asidePortPacketGeneration : 1; /* 1E.C47A.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = CRPAT packet generation out 10G look-aside interface (KR0) + 0 = No CRPAT packet generation out 10G look-aside interface (KR0) + */ + /*! \brief 1E.C47A.5 R/WPD MDI Packet Generation + AQ_GlobalReservedProvisioning_HHD.u10.bits_10.mdiPacketGeneration + + Provisionable Default = 0x0 + + 1 = CRPAT packet generation out MDI interface + 0 = No CRPAT packet generation out MDI interface + + + Notes: + Selecting this mode of operation causes the CRPAT packet generator in the PHY to output on the MDI interface at the selected rate. + + NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F + + The controls in this register are identical to, and mirrored with, the controls in 4.C444. */ + unsigned int mdiPacketGeneration : 1; /* 1E.C47A.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = CRPAT packet generation out MDI interface + 0 = No CRPAT packet generation out MDI interface + */ + /*! \brief 1E.C47A.A:6 R/WPD Reserved Provisioning 11 [4:0] + AQ_GlobalReservedProvisioning_HHD.u10.bits_10.reservedProvisioning_11 + + Provisionable Default = 0x00 + + Reserved for future use + + */ + unsigned int reservedProvisioning_11 : 5; /* 1E.C47A.A:6 R/WPD Provisionable Default = 0x00 */ + /* Reserved for future use + */ + /*! \brief 1E.C47A.F:B R/WPD Loopback Control [4:0] + AQ_GlobalReservedProvisioning_HHD.u10.bits_10.loopbackControl + + Provisionable Default = 0x00 + + 0x00 = No loopback + 0x01 = System Interface - System Loopback + 0x02 = System Interface - System Loopback with Passthrough + 0x03 = System Interface - Network Loopback + 0x04 = System Interface - Network Loopback with Passthrough + 0x05 = System Interface - Network Loopback with Passthrough and Merge + 0x06 = System Interface - Peer-to-peer loopback + 0x07 - 0x08 = Reserved + 0x09 = Network Interface - System Loopback + 0x0A = Network Interface - System Loopback with Passthrough + 0x0B = Network Interface - Network Loopback + 0x0C = Network Interface - Network Loopback with Passthrough + 0x0D = Network Interface - Peer-to-peer loopback + 0x0E - 0x0F = Reserved + 0x10 = Cross-connect System Loopback + 0x11 = Cross-connect Network Loopback + 0x12 - 0x13 = Reserved + 0x14 = Network Interface - System Loopback via Loopback Plug + 0x15 - 0x1F = Reserved + + + Notes: + These bits, in conjunction with the chip configuration and the rate (Bits 1:0), select the loopback to configure for the chip. Setting one of these loopbacks provisions the chip for the specified loopback. Upon clearing the loopback, the chip returns to it's configuration prior to entering loopback (irregardless of whether other loopbacks were selected after the initial loopback). + + NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F. + + The controls in this register are identical to, and mirrored with, the controls in 4.C444. + */ + unsigned int loopbackControl : 5; /* 1E.C47A.F:B R/WPD Provisionable Default = 0x00 */ + /* 0x00 = No loopback + 0x01 = System Interface - System Loopback + 0x02 = System Interface - System Loopback with Passthrough + 0x03 = System Interface - Network Loopback + 0x04 = System Interface - Network Loopback with Passthrough + 0x05 = System Interface - Network Loopback with Passthrough and Merge + 0x06 = System Interface - Peer-to-peer loopback + 0x07 - 0x08 = Reserved + 0x09 = Network Interface - System Loopback + 0x0A = Network Interface - System Loopback with Passthrough + 0x0B = Network Interface - Network Loopback + 0x0C = Network Interface - Network Loopback with Passthrough + 0x0D = Network Interface - Peer-to-peer loopback + 0x0E - 0x0F = Reserved + 0x10 = Cross-connect System Loopback + 0x11 = Cross-connect Network Loopback + 0x12 - 0x13 = Reserved + 0x14 = Network Interface - System Loopback via Loopback Plug + 0x15 - 0x1F = Reserved + */ + } bits_10; + uint16_t word_10; + } u10; + /*! \brief Union for bit and word level access of word 11 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C47B.0 R/WPD Enable PTP + AQ_GlobalReservedProvisioning_HHD.u11.bits_11.enablePtp + + Provisionable Default = 0x0 + + 1 = PTP functionality is enabled + 0 = PTP functionality is disabled + + + Notes: + If this bit is 1, the PTP/SEC block will be included in the data path, regardless of operating mode. */ + unsigned int enablePtp : 1; /* 1E.C47B.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = PTP functionality is enabled + 0 = PTP functionality is disabled + */ + /*! \brief 1E.C47B.1 R/WPD Enable MACSec + AQ_GlobalReservedProvisioning_HHD.u11.bits_11.enableMacsec + + Provisionable Default = 0x0 + + 1 = MACSec functionality is enabled + 0 = MACSec functionality is disabled + + + Notes: + If this bit is 1, the PTP/SEC block will be included in the data path, regardless of operating mode. */ + unsigned int enableMacsec : 1; /* 1E.C47B.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = MACSec functionality is enabled + 0 = MACSec functionality is disabled + */ + /*! \brief 1E.C47B.F:2 R/WPD Reserved Provisioning 12 [D:0] + AQ_GlobalReservedProvisioning_HHD.u11.bits_11.reservedProvisioning_12 + + Provisionable Default = 0x0000 + + Reserved for future use + + */ + unsigned int reservedProvisioning_12 : 14; /* 1E.C47B.F:2 R/WPD Provisionable Default = 0x0000 */ + /* Reserved for future use + */ + } bits_11; + uint16_t word_11; + } u11; +} AQ_GlobalReservedProvisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief PIF Mailbox Control: 1E.C47C */ +/* PIF Mailbox Control: 1E.C47C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of PIF Mailbox Control */ + union + { + struct + { + /*! \brief 1E.C47C.F:0 R/WPDuP PIF Mailbox Address [F:0] + AQ_PifMailboxControl_HHD.u0.bits_0.pifMailboxAddress + + Provisionable Default = 0x0000 + + The least 16 bits of the PIF address to read or write. + + */ + unsigned int pifMailboxAddress : 16; /* 1E.C47C.F:0 R/WPDuP Provisionable Default = 0x0000 */ + /* The least 16 bits of the PIF address to read or write. + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of PIF Mailbox Control */ + union + { + struct + { + /*! \brief 1E.C47D.F:0 R/WPDuP PIF Mailbox Data [F:0] + AQ_PifMailboxControl_HHD.u1.bits_1.pifMailboxData + + Provisionable Default = 0x0000 + + The data to be written, or that had been read. + + */ + unsigned int pifMailboxData : 16; /* 1E.C47D.F:0 R/WPDuP Provisionable Default = 0x0000 */ + /* The data to be written, or that had been read. + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of PIF Mailbox Control */ + union + { + struct + { + /*! \brief 1E.C47E.7:0 R/WPDuP PIF Mailbox MMD [7:0] + AQ_PifMailboxControl_HHD.u2.bits_2.pifMailboxMMD + + Provisionable Default = 0x00 + + MMD (upper 8 bits) of the PID address to read or write. + + */ + unsigned int pifMailboxMMD : 8; /* 1E.C47E.7:0 R/WPDuP Provisionable Default = 0x00 */ + /* MMD (upper 8 bits) of the PID address to read or write. + */ + /*! \brief 1E.C47E.B:8 R/WPDuP PIF Mailbox Command Type [3:0] + AQ_PifMailboxControl_HHD.u2.bits_2.pifMailboxCommandType + + Provisionable Default = 0x0 + + 0 = No Action + 1 = Read + 2 = Write + + + Notes: + System SW writes non-zero value to start a PIF command. */ + unsigned int pifMailboxCommandType : 4; /* 1E.C47E.B:8 R/WPDuP Provisionable Default = 0x0 */ + /* 0 = No Action + 1 = Read + 2 = Write + */ + /*! \brief 1E.C47E.F:C R/WPD Reserved PIF Mailbox Control 3 [3:0] + AQ_PifMailboxControl_HHD.u2.bits_2.reservedPifMailboxControl_3 + + Provisionable Default = 0x0 + + Reserved for future use + + */ + unsigned int reservedPifMailboxControl_3 : 4; /* 1E.C47E.F:C R/WPD Provisionable Default = 0x0 */ + /* Reserved for future use + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of PIF Mailbox Control */ + union + { + struct + { + /*! \brief 1E.C47F.3:0 R/WPDuP PIF Mailbox Command Status [3:0] + AQ_PifMailboxControl_HHD.u3.bits_3.pifMailboxCommandStatus + + Provisionable Default = 0x0 + + 0 = Idle + 1 = Command completed + 2 = Command did not complete + + + Notes: + System SW should write 0 before writing Command Type to clear completion status */ + unsigned int pifMailboxCommandStatus : 4; /* 1E.C47F.3:0 R/WPDuP Provisionable Default = 0x0 */ + /* 0 = Idle + 1 = Command completed + 2 = Command did not complete + */ + /*! \brief 1E.C47F.F:4 R/WPD Reserved PIF Mailbox Control 4 [B:0] + AQ_PifMailboxControl_HHD.u3.bits_3.reservedPifMailboxControl_4 + + Provisionable Default = 0x000 + + Reserved for future use + + */ + unsigned int reservedPifMailboxControl_4 : 12; /* 1E.C47F.F:4 R/WPD Provisionable Default = 0x000 */ + /* Reserved for future use + */ + } bits_3; + uint16_t word_3; + } u3; +} AQ_PifMailboxControl_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global SMBus 0 Provisioning: 1E.C485 */ +/* Global SMBus 0 Provisioning: 1E.C485 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global SMBus 0 Provisioning */ + union + { + struct + { + unsigned int reserved1 : 1; + /*! \brief 1E.C485.7:1 R/W SMB 0 Slave Address [7:1] + AQ_GlobalSmbus_0Provisioning_HHD.u0.bits_0.smb_0SlaveAddress + + Default = 0x00 + + SMB slave address configuration + + */ + unsigned int smb_0SlaveAddress : 7; /* 1E.C485.7:1 R/W Default = 0x00 */ + /* SMB slave address configuration + */ + unsigned int reserved0 : 8; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalSmbus_0Provisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global SMBus 1 Provisioning: 1E.C495 */ +/* Global SMBus 1 Provisioning: 1E.C495 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global SMBus 1 Provisioning */ + union + { + struct + { + unsigned int reserved1 : 1; + /*! \brief 1E.C495.7:1 R/W SMB 1 Slave Address [7:1] + AQ_GlobalSmbus_1Provisioning_HHD.u0.bits_0.smb_1SlaveAddress + + Default = 0x00 + + SMB slave address configuration + + */ + unsigned int smb_1SlaveAddress : 7; /* 1E.C495.7:1 R/W Default = 0x00 */ + /* SMB slave address configuration + */ + unsigned int reserved0 : 8; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalSmbus_1Provisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global EEE Provisioning: 1E.C4A0 */ +/* Global EEE Provisioning: 1E.C4A0 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global EEE Provisioning */ + union + { + struct + { + /*! \brief 1E.C4A0.0 R/WPD EEE Mode + AQ_GlobalEeeProvisioning_HHD.u0.bits_0.eeeMode + + Provisionable Default = 0x0 + + 1 = EEE mode of operation + + + Notes: + EEE mode of operation (0=disable, 1=enable, default:0) */ + unsigned int eeeMode : 1; /* 1E.C4A0.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = EEE mode of operation + */ + unsigned int reserved0 : 15; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalEeeProvisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Cable Diagnostic Status: 1E.C800 */ +/* Global Cable Diagnostic Status: 1E.C800 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C800.2:0 RO Pair D Status [2:0] + AQ_GlobalCableDiagnosticStatus_HHD.u0.bits_0.pairDStatus + + + + [6:4] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair C + 010= Connected to Pair B + 001= Connected to Pair A + 000= OK + + Notes: + This register summarizes the worst impairment on Pair D. */ + unsigned int pairDStatus : 3; /* 1E.C800.2:0 RO */ + /* [6:4] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair C + 010= Connected to Pair B + 001= Connected to Pair A + 000= OK */ + unsigned int reserved3 : 1; + /*! \brief 1E.C800.6:4 RO Pair C Status [2:0] + AQ_GlobalCableDiagnosticStatus_HHD.u0.bits_0.pairCStatus + + + + [9:7] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair B + 010= Connected to Pair A + 001= Connected to Pair D + 000= OK + + Notes: + This register summarizes the worst impairment on Pair C. */ + unsigned int pairCStatus : 3; /* 1E.C800.6:4 RO */ + /* [9:7] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair B + 010= Connected to Pair A + 001= Connected to Pair D + 000= OK */ + unsigned int reserved2 : 1; + /*! \brief 1E.C800.A:8 RO Pair B Status [2:0] + AQ_GlobalCableDiagnosticStatus_HHD.u0.bits_0.pairBStatus + + + + [C:A] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair A + 010= Connected to Pair D + 001= Connected to Pair C + 000= OK + + Notes: + This register summarizes the worst impairment on Pair B. */ + unsigned int pairBStatus : 3; /* 1E.C800.A:8 RO */ + /* [C:A] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair A + 010= Connected to Pair D + 001= Connected to Pair C + 000= OK */ + unsigned int reserved1 : 1; + /*! \brief 1E.C800.E:C RO Pair A Status [2:0] + AQ_GlobalCableDiagnosticStatus_HHD.u0.bits_0.pairAStatus + + + + [F:D] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair D + 010= Connected to Pair C + 001= Connected to Pair B + 000= OK + + Notes: + This register summarizes the worst impairment on Pair A. */ + unsigned int pairAStatus : 3; /* 1E.C800.E:C RO */ + /* [F:D] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair D + 010= Connected to Pair C + 001= Connected to Pair B + 000= OK */ + unsigned int reserved0 : 1; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C801.7:0 RO Pair A Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u1.bits_1.pairAReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair A + + Notes: + The distance to this reflection is given in See Global Reserved Status 1: Address 1E.C870 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairAReflection_2 : 8; /* 1E.C801.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair A */ + /*! \brief 1E.C801.F:8 RO Pair A Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u1.bits_1.pairAReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair A + + Notes: + The distance to this reflection is given in See Global Reserved Status 1: Address 1E.C870 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairAReflection_1 : 8; /* 1E.C801.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair A */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C802.F:0 RO Impulse Response MSW [F:0] + AQ_GlobalCableDiagnosticStatus_HHD.u2.bits_2.impulseResponseMSW + + + + The MSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type in 1E.C470.E:D + + Notes: + See 1E.C470 for more information */ + unsigned int impulseResponseMSW : 16; /* 1E.C802.F:0 RO */ + /* The MSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type in 1E.C470.E:D */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C803.7:0 RO Pair B Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u3.bits_3.pairBReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair B + + Notes: + The distance to this reflection is given in See Global Reserved Status 2: Address 1E.C871 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairBReflection_2 : 8; /* 1E.C803.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair B */ + /*! \brief 1E.C803.F:8 RO Pair B Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u3.bits_3.pairBReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair B + + Notes: + The distance to this reflection is given in See Global Reserved Status 2: Address 1E.C871 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairBReflection_1 : 8; /* 1E.C803.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair B */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C804.F:0 RO Impulse Response LSW [F:0] + AQ_GlobalCableDiagnosticStatus_HHD.u4.bits_4.impulseResponseLSW + + + + The LSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type specified in 1E.C470.E:D + + Notes: + See 1E.C470 for more information */ + unsigned int impulseResponseLSW : 16; /* 1E.C804.F:0 RO */ + /* The LSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type specified in 1E.C470.E:D */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C805.7:0 RO Pair C Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u5.bits_5.pairCReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair C + + Notes: + The distance to this reflection is given in See Global Reserved Status 3: Address 1E.C872 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairCReflection_2 : 8; /* 1E.C805.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair C */ + /*! \brief 1E.C805.F:8 RO Pair C Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u5.bits_5.pairCReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair C + + Notes: + The distance to this reflection is given in See Global Reserved Status 3: Address 1E.C872 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairCReflection_1 : 8; /* 1E.C805.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair C */ + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C806.F:0 RO Reserved 1 [F:0] + AQ_GlobalCableDiagnosticStatus_HHD.u6.bits_6.reserved_1 + + + + Reserved for future use + */ + unsigned int reserved_1 : 16; /* 1E.C806.F:0 RO */ + /* Reserved for future use */ + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C807.7:0 RO Pair D Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u7.bits_7.pairDReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair D + + Notes: + The distance to this reflection is given in See Global Reserved Status 4: Address 1E.C873 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairDReflection_2 : 8; /* 1E.C807.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair D */ + /*! \brief 1E.C807.F:8 RO Pair D Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u7.bits_7.pairDReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair D + + Notes: + The distance to this reflection is given in See Global Reserved Status 4: Address 1E.C873 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairDReflection_1 : 8; /* 1E.C807.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair D */ + } bits_7; + uint16_t word_7; + } u7; +} AQ_GlobalCableDiagnosticStatus_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Thermal Status: 1E.C820 */ +/* Global Thermal Status: 1E.C820 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Thermal Status */ + union + { + struct + { + /*! \brief 1E.C820.F:0 RO Temperature [F:0] + AQ_GlobalThermalStatus_HHD.u0.bits_0.temperature + + + + [F:0] of temperature + + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 70 degreesC. This is a mirror of the XENPAK register 1.A060 - 1.A061. The mirror is performed in H/W. */ + unsigned int temperature : 16; /* 1E.C820.F:0 RO */ + /* [F:0] of temperature + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Thermal Status */ + union + { + struct + { + /*! \brief 1E.C821.0 RO Temperature Ready + AQ_GlobalThermalStatus_HHD.u1.bits_1.temperatureReady + + + + 1 = Temperature measurement is valid + + + Notes: + This is a mirror of the XENPAK register 1.A06E. */ + unsigned int temperatureReady : 1; /* 1E.C821.0 RO */ + /* 1 = Temperature measurement is valid + */ + unsigned int reserved0 : 15; + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalThermalStatus_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global General Status: 1E.C830 */ +/* Global General Status: 1E.C830 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global General Status */ + union + { + struct + { + unsigned int reserved1 : 11; + /*! \brief 1E.C830.B RO Low Temperature Warning State + AQ_GlobalGeneralStatus_HHD.u0.bits_0.lowTemperatureWarningState + + + + 1 = Low temperature warning threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A074.6 register. + + */ + unsigned int lowTemperatureWarningState : 1; /* 1E.C830.B RO */ + /* 1 = Low temperature warning threshold has been exceeded */ + /*! \brief 1E.C830.C RO High Temperature Warning State + AQ_GlobalGeneralStatus_HHD.u0.bits_0.highTemperatureWarningState + + + + 1 = High temperature warning threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A074.7 register. + + */ + unsigned int highTemperatureWarningState : 1; /* 1E.C830.C RO */ + /* 1 = High temperature warning threshold has been exceeded */ + /*! \brief 1E.C830.D RO Low Temperature Failure State + AQ_GlobalGeneralStatus_HHD.u0.bits_0.lowTemperatureFailureState + + + + 1 = Low temperature failure threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A070.6 register. + + */ + unsigned int lowTemperatureFailureState : 1; /* 1E.C830.D RO */ + /* 1 = Low temperature failure threshold has been exceeded */ + /*! \brief 1E.C830.E RO High Temperature Failure State + AQ_GlobalGeneralStatus_HHD.u0.bits_0.highTemperatureFailureState + + + + 1 = High temperature failure threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A070.7 register. + + */ + unsigned int highTemperatureFailureState : 1; /* 1E.C830.E RO */ + /* 1 = High temperature failure threshold has been exceeded */ + unsigned int reserved0 : 1; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global General Status */ + union + { + struct + { + unsigned int reserved0 : 15; + /*! \brief 1E.C831.F RO Processor Intensive MDIO Operation In- Progress + AQ_GlobalGeneralStatus_HHD.u1.bits_1.processorIntensiveMdioOperationIn_Progress + + + + 1 = PHY microprocessor is busy with a processor-intensive MDIO operation + 0 = Processor-intensive MDIO operation completed + + + Notes: + This bit should may be used with certain processor-intensive MDIO commands (such as Loopbacks, Test Modes, Low power modes, Tx-Disable, Restart autonegotiation, Cable Diagnostics, etc.) that take longer than an MDIO cycle to complete. Upon receiving an MDIO command that involves the PHY's microprocessor, this bit is set, and when the command is completed, this bit is cleared. + + NOTE!!! This bit should be checked only after 1 ms of issuing a processor-intensive MDIO operation. + + The list of operations that set this bit are as follows: + + 1.0.0, PMA Loopback + 1.0.B, Low power mode + 1.9.4:0, Tx Disable + 1.84, 10G Test modes + 1.8000.5, XENPAK Control + 1.9000, XENPAK Rx Fault Enable + 1.9002, XENPAK Alarm Enable + 1.E400.F, External loopback + 3.0.B, Low power mode + 3.0.E, System PCS loopback + 3.C471.5, PRBS Test + 3.C471.6, PRBS Test + 3.E471.5, PRBS Test + 3.E471.6, PRBS Test + 4.0.B, Low power mode + 4.0.E, PHY-XS network loopback + 4.C440, Output clock control, Load SERDES parameters + 4.F802.E, System loopback + 4.C444.F:B, Loopback Control + 4.C444.4:2, Packet generation + 4.C445.C, SERDES calibration + 7.0.9, Restart autonegotiation + 1D.C280, 1G/100M Network loopback + 1D.C500, 1G System loopback + 1D.C501, 1G / 100M Test modes + 1E.C470.4, Cable diagnostics + 1E.C47A.F:B, Loopback Control + 1E.C47A.4:2, Packet generation */ + unsigned int processorIntensiveMdioOperationIn_Progress : 1; /* 1E.C831.F RO */ + /* 1 = PHY microprocessor is busy with a processor-intensive MDIO operation + 0 = Processor-intensive MDIO operation completed + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalGeneralStatus_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Pin Status: 1E.C840 */ +/* Global Pin Status: 1E.C840 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Pin Status */ + union + { + struct + { + /*! \brief 1E.C840.5:0 RO LED Pullup State [5:0] + AQ_GlobalPinStatus_HHD.u0.bits_0.ledPullupState + + + + 1 = LED output pin is pulled high + 0 = LED output pin is pulled low + + */ + unsigned int ledPullupState : 6; /* 1E.C840.5:0 RO */ + /* 1 = LED output pin is pulled high + 0 = LED output pin is pulled low + */ + unsigned int reserved4 : 1; + /*! \brief 1E.C840.7 RO Tx Enable + AQ_GlobalPinStatus_HHD.u0.bits_0.txEnable + + + + Current Value of Tx Enable pin + + + Notes: + 0 = Disable Transmitter */ + unsigned int txEnable : 1; /* 1E.C840.7 RO */ + /* Current Value of Tx Enable pin + */ + unsigned int reserved3 : 1; + /*! \brief 1E.C840.9 RO Package Connectivity + AQ_GlobalPinStatus_HHD.u0.bits_0.packageConnectivity + + + + Value of the package connection pin + + */ + unsigned int packageConnectivity : 1; /* 1E.C840.9 RO */ + /* Value of the package connection pin + */ + unsigned int reserved2 : 3; + /*! \brief 1E.C840.D RO DC_MASTER_N + AQ_GlobalPinStatus_HHD.u0.bits_0.dcMasterN + + + + Value of DC_MASTER_N pin: + + 0x1 = PHY Slave Daisy Chain Boot + 0x0 = PHY Master Daisy Chain Boot from FLASH + */ + unsigned int dcMasterN : 1; /* 1E.C840.D RO */ + /* Value of DC_MASTER_N pin: + + 0x1 = PHY Slave Daisy Chain Boot + 0x0 = PHY Master Daisy Chain Boot from FLASH */ + unsigned int reserved1 : 1; + unsigned int reserved0 : 1; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalPinStatus_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Daisy Chain Status: 1E.C842 */ +/* Global Daisy Chain Status: 1E.C842 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Daisy Chain Status */ + union + { + struct + { + /*! \brief 1E.C842.F:0 RO Rx Daisy Chain Calculated CRC [F:0] + AQ_GlobalDaisyChainStatus_HHD.u0.bits_0.rxDaisyChainCalculatedCrc + + + + Rx Daisy Chain Calculated CRC + + + Notes: + This is the calculated daisy chain CRC. */ + unsigned int rxDaisyChainCalculatedCrc : 16; /* 1E.C842.F:0 RO */ + /* Rx Daisy Chain Calculated CRC + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalDaisyChainStatus_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Fault Message: 1E.C850 */ +/* Global Fault Message: 1E.C850 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Fault Message */ + union + { + struct + { + /*! \brief 1E.C850.F:0 RO Message [F:0] + AQ_GlobalFaultMessage_HHD.u0.bits_0.message + + + + Error code describing fault + + Notes: + Code 0x8001: Firmware not compatible with chip architecture. This fault occurs when firmware compiled for a different microprocessor core is loaded. + Code 0x8002: VCO calibration failed. This occurs when the main PLLs on chip fail to lock: this is not possible to trigger. + Code 0x8003: XAUI calibration failed. This occurs when the XAUI PLLs fail to lock: this is not possible to trigger. + Code 0x8005: Unexpected device ID. This occurs if the device ID programmed into the internal E-Fuse registers in not valid: this is not possible to trigger. + Code 0x8006: Computed checksum does not match expected checksum. This occurs when the FLASH checksum check performed at boot time fails. This only occurs when the system boots from FLASH. + Code 0x8007: Detected a bit error in static memory. To trigger, corrupt one of the static regions. + Code 0xC001: Illegal Instruction exception. This occurs when the processor attempts to execute an illegal instruction. To trigger this, write an illegal instruction to program memory. It's possible that the bit error check will trigger before the illegal instruction is executed. + Code 0xC002 Instruction Fetch Error. Internal physical address or a data error during instruction fetch: this is not possible to trigger. + Code 0xC003 Load Store Error. Internal physical address or data error during load store operation: this is not possible to trigger.. + Code 0xC004 Privileged Instruction. Attempt to execute a privileged operation without sufficient privilege: this is not possible to trigger. + Code 0xC005 Unaligned Load or Store. Attempt to load or store data at an address which cannot be handled due to alignment: this is not possible to trigger. + Code 0xC006 Instruction fetch from prohibited space: this is not possible to trigger. + Code 0xC007 Data load from prohibited space: this is not possible to trigger. + Code 0xC008 Data store into prohibited space: this is not possible to trigger. */ + unsigned int message : 16; /* 1E.C850.F:0 RO */ + /* Error code describing fault */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalFaultMessage_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Cable Diagnostic Impedance: 1E.C880 */ +/* Global Cable Diagnostic Impedance: 1E.C880 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C880.2:0 RO Pair A Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.pairAReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_4 : 3; /* 1E.C880.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C880.3 RO Reserved 4 + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.reserved_4 + + + + Reserved + + */ + unsigned int reserved_4 : 1; /* 1E.C880.3 RO */ + /* Reserved + */ + /*! \brief 1E.C880.6:4 RO Pair A Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.pairAReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_3 : 3; /* 1E.C880.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C880.7 RO Reserved 3 + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.reserved_3 + + + + Reserved + + */ + unsigned int reserved_3 : 1; /* 1E.C880.7 RO */ + /* Reserved + */ + /*! \brief 1E.C880.A:8 RO Pair A Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.pairAReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_2 : 3; /* 1E.C880.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C880.B RO Reserved 2 + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.reserved_2 + + + + Reserved + + */ + unsigned int reserved_2 : 1; /* 1E.C880.B RO */ + /* Reserved + */ + /*! \brief 1E.C880.E:C RO Pair A Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.pairAReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_1 : 3; /* 1E.C880.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C880.F RO Reserved 1 + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.reserved_1 + + + + Reserved + + */ + unsigned int reserved_1 : 1; /* 1E.C880.F RO */ + /* Reserved + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C881.2:0 RO Pair B Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.pairBReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_4 : 3; /* 1E.C881.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C881.3 RO Reserved 8 + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.reserved_8 + + + + Reserved + + */ + unsigned int reserved_8 : 1; /* 1E.C881.3 RO */ + /* Reserved + */ + /*! \brief 1E.C881.6:4 RO Pair B Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.pairBReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_3 : 3; /* 1E.C881.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C881.7 RO Reserved 7 + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.reserved_7 + + + + Reserved + + */ + unsigned int reserved_7 : 1; /* 1E.C881.7 RO */ + /* Reserved + */ + /*! \brief 1E.C881.A:8 RO Pair B Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.pairBReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_2 : 3; /* 1E.C881.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C881.B RO Reserved 6 + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.reserved_6 + + + + Reserved + + */ + unsigned int reserved_6 : 1; /* 1E.C881.B RO */ + /* Reserved + */ + /*! \brief 1E.C881.E:C RO Pair B Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.pairBReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_1 : 3; /* 1E.C881.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C881.F RO Reserved 5 + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.reserved_5 + + + + Reserved + + */ + unsigned int reserved_5 : 1; /* 1E.C881.F RO */ + /* Reserved + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C882.2:0 RO Pair C Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.pairCReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_4 : 3; /* 1E.C882.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C882.3 RO Reserved 12 + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.reserved_12 + + + + Reserved + + */ + unsigned int reserved_12 : 1; /* 1E.C882.3 RO */ + /* Reserved + */ + /*! \brief 1E.C882.6:4 RO Pair C Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.pairCReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_3 : 3; /* 1E.C882.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C882.7 RO Reserved 11 + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.reserved_11 + + + + Reserved + + */ + unsigned int reserved_11 : 1; /* 1E.C882.7 RO */ + /* Reserved + */ + /*! \brief 1E.C882.A:8 RO Pair C Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.pairCReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_2 : 3; /* 1E.C882.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C882.B RO Reserved 10 + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.reserved_10 + + + + Reserved + + */ + unsigned int reserved_10 : 1; /* 1E.C882.B RO */ + /* Reserved + */ + /*! \brief 1E.C882.E:C RO Pair C Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.pairCReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_1 : 3; /* 1E.C882.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C882.F RO Reserved 9 + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.reserved_9 + + + + Reserved + + */ + unsigned int reserved_9 : 1; /* 1E.C882.F RO */ + /* Reserved + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C883.2:0 RO Pair D Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.pairDReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_4 : 3; /* 1E.C883.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C883.3 RO Reserved 16 + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.reserved_16 + + + + Reserved + + */ + unsigned int reserved_16 : 1; /* 1E.C883.3 RO */ + /* Reserved + */ + /*! \brief 1E.C883.6:4 RO Pair D Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.pairDReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_3 : 3; /* 1E.C883.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C883.7 RO Reserved 15 + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.reserved_15 + + + + Reserved + + */ + unsigned int reserved_15 : 1; /* 1E.C883.7 RO */ + /* Reserved + */ + /*! \brief 1E.C883.A:8 RO Pair D Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.pairDReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_2 : 3; /* 1E.C883.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C883.B RO Reserved 14 + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.reserved_14 + + + + Reserved + + */ + unsigned int reserved_14 : 1; /* 1E.C883.B RO */ + /* Reserved + */ + /*! \brief 1E.C883.E:C RO Pair D Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.pairDReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_1 : 3; /* 1E.C883.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C883.F RO Reserved 13 + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.reserved_13 + + + + Reserved + + */ + unsigned int reserved_13 : 1; /* 1E.C883.F RO */ + /* Reserved + */ + } bits_3; + uint16_t word_3; + } u3; +} AQ_GlobalCableDiagnosticImpedance_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Status: 1E.C884 */ +/* Global Status: 1E.C884 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Status */ + union + { + struct + { + /*! \brief 1E.C884.7:0 RO Cable Length [7:0] + AQ_GlobalStatus_HHD.u0.bits_0.cableLength + + + + The estimated length of the cable in meters + + + Notes: + The length of the cable shown here is estimated from the cable diagnostic engine and should be accurate to +/-1m. */ + unsigned int cableLength : 8; /* 1E.C884.7:0 RO */ + /* The estimated length of the cable in meters + */ + /*! \brief 1E.C884.F:8 RO Reserved Status 0 [7:0] + AQ_GlobalStatus_HHD.u0.bits_0.reservedStatus_0 + + + + Reserved + + */ + unsigned int reservedStatus_0 : 8; /* 1E.C884.F:8 RO */ + /* Reserved + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStatus_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Reserved Status: 1E.C885 */ +/* Global Reserved Status: 1E.C885 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Reserved Status */ + union + { + struct + { + /*! \brief 1E.C885.3:0 ROSPD Provisioning ID [3:0] + AQ_GlobalReservedStatus_HHD.u0.bits_0.provisioningID + + Provisionable Default = 0x0 + + Provisioning ID + + + Notes: + Customers may receive multiple ROM images that differ only in their provisioning. This field is used to differentiate those images. This field is used in conjunction with the firmware major and minor revision numbers to uniquely identify ROM images. */ + unsigned int provisioningID : 4; /* 1E.C885.3:0 ROSPD Provisionable Default = 0x0 */ + /* Provisioning ID + */ + /*! \brief 1E.C885.7:4 ROSPD Firmware Build ID [3:0] + AQ_GlobalReservedStatus_HHD.u0.bits_0.firmwareBuildID + + Provisionable Default = 0x0 + + Firmware Build ID + + + Notes: + Customers may receive multiple ROM images that differ only in their provisioning. This field is used to differentiate those images. This field is used in conjunction with the firmware major and minor revision numbers to uniquely identify ROM images. */ + unsigned int firmwareBuildID : 4; /* 1E.C885.7:4 ROSPD Provisionable Default = 0x0 */ + /* Firmware Build ID + */ + /*! \brief 1E.C885.9:8 ROSPD XENPAK NVR Status [1:0] + AQ_GlobalReservedStatus_HHD.u0.bits_0.xenpakNvrStatus + + Provisionable Default = 0x0 + + Status of XENPAK NVR: + 0: NVR not enabled + 1: Last NVR operation succeeded + 2: Last NVR operation failed + 3: Reserved + + + Notes: + XENPAK register space is mirrored in NVR (SPI ROM). This register indicates the status of the last NVR operation. */ + unsigned int xenpakNvrStatus : 2; /* 1E.C885.9:8 ROSPD Provisionable Default = 0x0 */ + /* Status of XENPAK NVR: + 0: NVR not enabled + 1: Last NVR operation succeeded + 2: Last NVR operation failed + 3: Reserved + */ + /*! \brief 1E.C885.F:A RO Nearly Seconds MSW[5:0] + AQ_GlobalReservedStatus_HHD.u0.bits_0.nearlySecondsMSW + + + + Bits 16 to 21 of the 22 bit "Nearly Seconds" uptime counter. + + + Notes: + The "Nearly Seconds" counter is incremented every 1024 milliseconds. */ + unsigned int nearlySecondsMSW : 6; /* 1E.C885.F:A RO */ + /* Bits 16 to 21 of the 22 bit "Nearly Seconds" uptime counter. + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Reserved Status */ + union + { + struct + { + /*! \brief 1E.C886.F:0 RO Nearly Seconds LSW [F:0] + AQ_GlobalReservedStatus_HHD.u1.bits_1.nearlySecondsLSW + + + + Bits 0 to 15 of the 22 bit "Nearly Seconds" uptime counter + + + Notes: + The "Nearly Seconds" counter is incremented every 1024 milliseconds. */ + unsigned int nearlySecondsLSW : 16; /* 1E.C886.F:0 RO */ + /* Bits 0 to 15 of the 22 bit "Nearly Seconds" uptime counter + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Reserved Status */ + union + { + struct + { + /*! \brief 1E.C887.D:0 RO Reserved Status 3 [D:0] + AQ_GlobalReservedStatus_HHD.u2.bits_2.reservedStatus_3 + + + + Reserved for future use + + */ + unsigned int reservedStatus_3 : 14; /* 1E.C887.D:0 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C887.E ROS Power Up Stall Status + AQ_GlobalReservedStatus_HHD.u2.bits_2.powerUpStallStatus + + Default = 0x0 + + 1 = FW is stalled at power up + 0 = Firmware is unstalled + + */ + unsigned int powerUpStallStatus : 1; /* 1E.C887.E ROS Default = 0x0 */ + /* 1 = FW is stalled at power up + 0 = Firmware is unstalled + */ + /*! \brief 1E.C887.F ROS DTE Status + AQ_GlobalReservedStatus_HHD.u2.bits_2.dteStatus + + Default = 0x0 + + 1 = Need power + 0 = Don't need power + + */ + unsigned int dteStatus : 1; /* 1E.C887.F ROS Default = 0x0 */ + /* 1 = Need power + 0 = Don't need power + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Reserved Status */ + union + { + struct + { + /*! \brief 1E.C888.1:0 RO Rate [1:0] + AQ_GlobalReservedStatus_HHD.u3.bits_3.rate + + Default = 0x0 + + 0x3 = 10G + 0x2 = 1G + 0x1 = 100M + 0x0 = invalid + + + Notes: + These bits report the selected rate for the loopback and packet generation. */ + unsigned int rate : 2; /* 1E.C888.1:0 RO Default = 0x0 */ + /* 0x3 = 10G + 0x2 = 1G + 0x1 = 100M + 0x0 = invalid + */ + /*! \brief 1E.C888.2 RO Reserved Status 4a + AQ_GlobalReservedStatus_HHD.u3.bits_3.reservedStatus_4a + + Default = 0x0 + + Reserved for future use + + */ + unsigned int reservedStatus_4a : 1; /* 1E.C888.2 RO Default = 0x0 */ + /* Reserved for future use + */ + /*! \brief 1E.C888.3 RO System I/F Packet Generation Status + AQ_GlobalReservedStatus_HHD.u3.bits_3.systemI_fPacketGenerationStatus + + Default = 0x0 + + 1 = CRPAT packet generation out 10G system interface + 0 = No CRPAT packet generation out 10G system interface + + + Notes: + Reports whether the CRPAT packet generator in the PHY outputs on the selected system interface at the selected rate. */ + unsigned int systemI_fPacketGenerationStatus : 1; /* 1E.C888.3 RO Default = 0x0 */ + /* 1 = CRPAT packet generation out 10G system interface + 0 = No CRPAT packet generation out 10G system interface + */ + /*! \brief 1E.C888.4 RO Look-Aside Port Packet Generation Status + AQ_GlobalReservedStatus_HHD.u3.bits_3.look_asidePortPacketGenerationStatus + + Default = 0x0 + + 1 = CRPAT packet generation out 10G look-aside interface (KR0) + 0 = No CRPAT packet generation out 10G look-aside interface (KR0) + + + Notes: + Reports whether the CRPAT packet generator in the PHY outputs on the KR0 interface at the selected rate. */ + unsigned int look_asidePortPacketGenerationStatus : 1; /* 1E.C888.4 RO Default = 0x0 */ + /* 1 = CRPAT packet generation out 10G look-aside interface (KR0) + 0 = No CRPAT packet generation out 10G look-aside interface (KR0) + */ + /*! \brief 1E.C888.5 RO MDI Packet Generation Status + AQ_GlobalReservedStatus_HHD.u3.bits_3.mdiPacketGenerationStatus + + Default = 0x0 + + 1 = CRPAT packet generation out MDI interface + 0 = No CRPAT packet generation out MDI interface + + + Notes: + Reports whether the CRPAT packet generator in the PHY outputs on the MDI interface at the selected rate. */ + unsigned int mdiPacketGenerationStatus : 1; /* 1E.C888.5 RO Default = 0x0 */ + /* 1 = CRPAT packet generation out MDI interface + 0 = No CRPAT packet generation out MDI interface + */ + /*! \brief 1E.C888.A:6 RO Reserved Status 4 [4:0] + AQ_GlobalReservedStatus_HHD.u3.bits_3.reservedStatus_4 + + Default = 0x00 + + Reserved for future use + + */ + unsigned int reservedStatus_4 : 5; /* 1E.C888.A:6 RO Default = 0x00 */ + /* Reserved for future use + */ + /*! \brief 1E.C888.F:B RO Loopback Status [4:0] + AQ_GlobalReservedStatus_HHD.u3.bits_3.loopbackStatus + + Default = 0x00 + + 0x00 = No loopback + 0x01 = System Interface - System Loopback + 0x02 = System Interface - System Loopback with Passthrough + 0x03 = System Interface - Network Loopback + 0x04 = System Interface - Network Loopback with Passthrough + 0x05 = System Interface - Network Loopback with Passthrough and Merge + 0x06 = System Interface - Peer-to-peer loopback + 0x07 - 0x08 = Reserved + 0x09 = Network Interface - System Loopback + 0x0A = Network Interface - System Loopback with Passthrough + 0x0B = Network Interface - Network Loopback + 0x0C = Network Interface - Network Loopback with Passthrough + 0x0D = Network Interface - Peer-to-peer loopback + 0x0E - 0x0F = Reserved + 0x10 = Cross-connect System Loopback + 0x11 = Cross-connect Network Loopback + 0x12 - 0x13 = Reserved + 0x14 = Network Interface - System Loopback via Loopback Plug + 0x15 - 0x1F = Reserved + + + Notes: + These bits, in conjunction with the chip configuration and the rate (Bits 1:0), report the selected loopback. + + */ + unsigned int loopbackStatus : 5; /* 1E.C888.F:B RO Default = 0x00 */ + /* 0x00 = No loopback + 0x01 = System Interface - System Loopback + 0x02 = System Interface - System Loopback with Passthrough + 0x03 = System Interface - Network Loopback + 0x04 = System Interface - Network Loopback with Passthrough + 0x05 = System Interface - Network Loopback with Passthrough and Merge + 0x06 = System Interface - Peer-to-peer loopback + 0x07 - 0x08 = Reserved + 0x09 = Network Interface - System Loopback + 0x0A = Network Interface - System Loopback with Passthrough + 0x0B = Network Interface - Network Loopback + 0x0C = Network Interface - Network Loopback with Passthrough + 0x0D = Network Interface - Peer-to-peer loopback + 0x0E - 0x0F = Reserved + 0x10 = Cross-connect System Loopback + 0x11 = Cross-connect Network Loopback + 0x12 - 0x13 = Reserved + 0x14 = Network Interface - System Loopback via Loopback Plug + 0x15 - 0x1F = Reserved + */ + } bits_3; + uint16_t word_3; + } u3; +} AQ_GlobalReservedStatus_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Alarms: 1E.CC00 */ +/* Global Alarms: 1E.CC00 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Alarms */ + union + { + struct + { + /*! \brief 1E.CC00.0 LH Reserved Alarm D + AQ_GlobalAlarms_HHD.u0.bits_0.reservedAlarmD + + + + Reserved for future use + + */ + unsigned int reservedAlarmD : 1; /* 1E.CC00.0 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC00.1 LH Reserved Alarm C + AQ_GlobalAlarms_HHD.u0.bits_0.reservedAlarmC + + + + Reserved for future use + + */ + unsigned int reservedAlarmC : 1; /* 1E.CC00.1 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC00.2 LH Reserved Alarm B + AQ_GlobalAlarms_HHD.u0.bits_0.reservedAlarmB + + + + Reserved for future use + + */ + unsigned int reservedAlarmB : 1; /* 1E.CC00.2 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC00.3 LH Reserved Alarm A + AQ_GlobalAlarms_HHD.u0.bits_0.reservedAlarmA + + + + Reserved for future use + + */ + unsigned int reservedAlarmA : 1; /* 1E.CC00.3 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC00.4 LH Device Fault + AQ_GlobalAlarms_HHD.u0.bits_0.deviceFault + + + + 1 = Fault + + Notes: + When set, a fault has been detected by the uP and the associated 16 bit error code is visible in See Global Configuration Fault Message: Address 1E.C850 */ + unsigned int deviceFault : 1; /* 1E.CC00.4 LH */ + /* 1 = Fault */ + unsigned int reserved2 : 1; + /*! \brief 1E.CC00.6 LH Reset completed + AQ_GlobalAlarms_HHD.u0.bits_0.resetCompleted + + + + 1 = Chip wide reset completed + + Notes: + This bit is set by the microprocessor when it has completed it's initialization sequence. This bit is mirrored in 1.CC02.0 */ + unsigned int resetCompleted : 1; /* 1E.CC00.6 LH */ + /* 1 = Chip wide reset completed */ + unsigned int reserved1 : 4; + /*! \brief 1E.CC00.B LH Low Temperature Warning + AQ_GlobalAlarms_HHD.u0.bits_0.lowTemperatureWarning + + + + 1 = Low temperature warning threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int lowTemperatureWarning : 1; /* 1E.CC00.B LH */ + /* 1 = Low temperature warning threshold has been exceeded + */ + /*! \brief 1E.CC00.C LH High Temperature Warning + AQ_GlobalAlarms_HHD.u0.bits_0.highTemperatureWarning + + + + 1 = High temperature warning threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int highTemperatureWarning : 1; /* 1E.CC00.C LH */ + /* 1 = High temperature warning threshold has been exceeded + */ + /*! \brief 1E.CC00.D LH Low Temperature Failure + AQ_GlobalAlarms_HHD.u0.bits_0.lowTemperatureFailure + + + + 1 = Low temperature failure threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int lowTemperatureFailure : 1; /* 1E.CC00.D LH */ + /* 1 = Low temperature failure threshold has been exceeded + */ + /*! \brief 1E.CC00.E LH High Temperature Failure + AQ_GlobalAlarms_HHD.u0.bits_0.highTemperatureFailure + + + + 1 = High temperature failure threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int highTemperatureFailure : 1; /* 1E.CC00.E LH */ + /* 1 = High temperature failure threshold has been exceeded + */ + unsigned int reserved0 : 1; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Alarms */ + union + { + struct + { + unsigned int reserved2 : 1; + unsigned int reserved1 : 6; + /*! \brief 1E.CC01.7 LH MDIO Command Handling Overflow + AQ_GlobalAlarms_HHD.u1.bits_1.mdioCommandHandlingOverflow + + + + 1 = PHY was issued more MDIO requests than it could service in it's request buffer + + + Notes: + Assertion of this bit means that more MDIO commands were issued than FW could handle. */ + unsigned int mdioCommandHandlingOverflow : 1; /* 1E.CC01.7 LH */ + /* 1 = PHY was issued more MDIO requests than it could service in it's request buffer + */ + /*! \brief 1E.CC01.A:8 LH Reserved Alarms [2:0] + AQ_GlobalAlarms_HHD.u1.bits_1.reservedAlarms + + + + Reserved + + + */ + unsigned int reservedAlarms : 3; /* 1E.CC01.A:8 LH */ + /* Reserved + + */ + /*! \brief 1E.CC01.B LH DTE Status Change + AQ_GlobalAlarms_HHD.u1.bits_1.dteStatusChange + + + + 1 = DTE status change + + + Notes: + Change in 1E.C887[F]. */ + unsigned int dteStatusChange : 1; /* 1E.CC01.B LH */ + /* 1 = DTE status change + */ + /*! \brief 1E.CC01.C LH IP Phone Detect + AQ_GlobalAlarms_HHD.u1.bits_1.ipPhoneDetect + + + + 1 = IP Phone Detect + + + Notes: + Assertion of this bit means that the presence of an IP Phone has been detected. */ + unsigned int ipPhoneDetect : 1; /* 1E.CC01.C LH */ + /* 1 = IP Phone Detect + */ + /*! \brief 1E.CC01.D RO XENPAK Alarm + AQ_GlobalAlarms_HHD.u1.bits_1.xenpakAlarm + + + + 1 = XENPAK Alarm + + */ + unsigned int xenpakAlarm : 1; /* 1E.CC01.D RO */ + /* 1 = XENPAK Alarm + */ + /*! \brief 1E.CC01.E LH Smart Power-Down Entered + AQ_GlobalAlarms_HHD.u1.bits_1.smartPower_downEntered + + + + 1 = Smart Power-Down State Entered + + + Notes: + When this bit is set, it indicates that the Smart Power-Down state was entered */ + unsigned int smartPower_downEntered : 1; /* 1E.CC01.E LH */ + /* 1 = Smart Power-Down State Entered + */ + unsigned int reserved0 : 1; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Alarms */ + union + { + struct + { + /*! \brief 1E.CC02.0 LH Watchdog Timer Alarm + AQ_GlobalAlarms_HHD.u2.bits_2.watchdogTimerAlarm + + + + 1 = Watchdog timer alarm + + */ + unsigned int watchdogTimerAlarm : 1; /* 1E.CC02.0 LH */ + /* 1 = Watchdog timer alarm + */ + /*! \brief 1E.CC02.1 LH MDIO Timeout Error + AQ_GlobalAlarms_HHD.u2.bits_2.mdioTimeoutError + + + + 1 = MDIO timeout detected + + */ + unsigned int mdioTimeoutError : 1; /* 1E.CC02.1 LH */ + /* 1 = MDIO timeout detected + */ + /*! \brief 1E.CC02.2 LH MDIO MMD Error + AQ_GlobalAlarms_HHD.u2.bits_2.mdioMMD_Error + + + + 1 = Invalid MMD address detected + + */ + unsigned int mdioMMD_Error : 1; /* 1E.CC02.2 LH */ + /* 1 = Invalid MMD address detected + */ + unsigned int reserved2 : 2; + /*! \brief 1E.CC02.5 LRF Tx Enable State Change + AQ_GlobalAlarms_HHD.u2.bits_2.txEnableStateChange + + + + 1 = TX_EN pin has changed state + + */ + unsigned int txEnableStateChange : 1; /* 1E.CC02.5 LRF */ + /* 1 = TX_EN pin has changed state + */ + unsigned int reserved1 : 2; + /*! \brief 1E.CC02.9:8 LH uP IRAM Parity Error [1:0] + AQ_GlobalAlarms_HHD.u2.bits_2.upIramParityError + + + + 1 = Parity error detected in the uP IRAM + + + Notes: + Bit 0 indicates a parity error was detected in the uP IRAM but was corrected. + Bit 1 indicates a multiple parity errors were detected in the uP IRAM and could not be corrected. + The uP IRAM is protected with ECC. */ + unsigned int upIramParityError : 2; /* 1E.CC02.9:8 LH */ + /* 1 = Parity error detected in the uP IRAM + */ + /*! \brief 1E.CC02.A LH uP DRAM Parity Error + AQ_GlobalAlarms_HHD.u2.bits_2.upDramParityError + + + + 1 = Parity error detected in the uP DRAM + + */ + unsigned int upDramParityError : 1; /* 1E.CC02.A LH */ + /* 1 = Parity error detected in the uP DRAM + */ + unsigned int reserved0 : 3; + /*! \brief 1E.CC02.E LH Mailbox Operation: Complete + AQ_GlobalAlarms_HHD.u2.bits_2.mailboxOperation_Complete + + + + 1 = Mailbox operation is complete + + + Notes: + Mailbox interface is ready interrupt for registers See Global Vendor Specific Control - Address 1E.C000 - See Global Vendor Specific Provisioning 5 - Address 1E.C404 */ + unsigned int mailboxOperation_Complete : 1; /* 1E.CC02.E LH */ + /* 1 = Mailbox operation is complete + */ + /*! \brief 1E.CC02.F LH NVR Operation Complete + AQ_GlobalAlarms_HHD.u2.bits_2.nvrOperationComplete + + + + 1 = NVR operation is complete + + + Notes: + NVR interface is ready interrupt for registers See Global NVR Interface 1: Address 1E.100 - See Global NVR Provisioning Data MSW - Address 1E.17 . */ + unsigned int nvrOperationComplete : 1; /* 1E.CC02.F LH */ + /* 1 = NVR operation is complete + */ + } bits_2; + uint16_t word_2; + } u2; +} AQ_GlobalAlarms_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Interrupt Mask: 1E.D400 */ +/* Global Interrupt Mask: 1E.D400 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Interrupt Mask */ + union + { + struct + { + /*! \brief 1E.D400.0 R/WPD Reserved Alarm D Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.reservedAlarmDMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmDMask : 1; /* 1E.D400.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D400.1 R/WPD Reserved Alarm C Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.reservedAlarmCMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmCMask : 1; /* 1E.D400.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D400.2 R/WPD Reserved Alarm B Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.reservedAlarmBMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmBMask : 1; /* 1E.D400.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D400.3 R/WPD Reserved Alarm A Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.reservedAlarmAMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmAMask : 1; /* 1E.D400.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D400.4 R/WPD Device Fault Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.deviceFaultMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int deviceFaultMask : 1; /* 1E.D400.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved2 : 1; + /*! \brief 1E.D400.6 R/WPD Reset completed Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.resetCompletedMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int resetCompletedMask : 1; /* 1E.D400.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved1 : 4; + /*! \brief 1E.D400.B R/WPD Low Temperature Warning Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.lowTemperatureWarningMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int lowTemperatureWarningMask : 1; /* 1E.D400.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D400.C R/WPD High Temperature Warning Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.highTemperatureWarningMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int highTemperatureWarningMask : 1; /* 1E.D400.C R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D400.D R/WPD Low Temperature Failure Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.lowTemperatureFailureMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int lowTemperatureFailureMask : 1; /* 1E.D400.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D400.E R/WPD High Temperature Failure Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.highTemperatureFailureMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int highTemperatureFailureMask : 1; /* 1E.D400.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved0 : 1; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Interrupt Mask */ + union + { + struct + { + /*! \brief 1E.D401.0 R/WPD Diagnostic Alarm Mask + AQ_GlobalInterruptMask_HHD.u1.bits_1.diagnosticAlarmMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int diagnosticAlarmMask : 1; /* 1E.D401.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int reserved1 : 6; + /*! \brief 1E.D401.7 R/WPD MDIO Command Handling Overflow Mask + AQ_GlobalInterruptMask_HHD.u1.bits_1.mdioCommandHandlingOverflowMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int mdioCommandHandlingOverflowMask : 1; /* 1E.D401.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D401.A:8 R/WPD Reserved Alarms Mask [2:0] + AQ_GlobalInterruptMask_HHD.u1.bits_1.reservedAlarmsMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmsMask : 3; /* 1E.D401.A:8 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D401.B R/WPD DTE Status Change Mask + AQ_GlobalInterruptMask_HHD.u1.bits_1.dteStatusChangeMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int dteStatusChangeMask : 1; /* 1E.D401.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D401.C R/WPD IP Phone Detect Mask + AQ_GlobalInterruptMask_HHD.u1.bits_1.ipPhoneDetectMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int ipPhoneDetectMask : 1; /* 1E.D401.C R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D401.D R/WPD XENPAK Alarm Mask + AQ_GlobalInterruptMask_HHD.u1.bits_1.xenpakAlarmMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int xenpakAlarmMask : 1; /* 1E.D401.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D401.E R/WPD Smart Power-Down Entered Mask + AQ_GlobalInterruptMask_HHD.u1.bits_1.smartPower_downEnteredMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int smartPower_downEnteredMask : 1; /* 1E.D401.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int reserved0 : 1; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Interrupt Mask */ + union + { + struct + { + /*! \brief 1E.D402.0 R/WPD Watchdog Timer Alarm Mask + AQ_GlobalInterruptMask_HHD.u2.bits_2.watchdogTimerAlarmMask + + Provisionable Default = 0x1 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int watchdogTimerAlarmMask : 1; /* 1E.D402.0 R/WPD Provisionable Default = 0x1 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D402.1 R/WPD MDIO Timeout Error Mask + AQ_GlobalInterruptMask_HHD.u2.bits_2.mdioTimeoutErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int mdioTimeoutErrorMask : 1; /* 1E.D402.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D402.2 R/WPD MDIO MMD Error Mask + AQ_GlobalInterruptMask_HHD.u2.bits_2.mdioMMD_ErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int mdioMMD_ErrorMask : 1; /* 1E.D402.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved2 : 2; + /*! \brief 1E.D402.5 R/WPD Tx Enable State Change Mask + AQ_GlobalInterruptMask_HHD.u2.bits_2.txEnableStateChangeMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int txEnableStateChangeMask : 1; /* 1E.D402.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved1 : 2; + /*! \brief 1E.D402.9:8 R/WPD uP IRAM Parity Error Mask [1:0] + AQ_GlobalInterruptMask_HHD.u2.bits_2.upIramParityErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int upIramParityErrorMask : 2; /* 1E.D402.9:8 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D402.A R/WPD uP DRAM Parity Error Mask + AQ_GlobalInterruptMask_HHD.u2.bits_2.upDramParityErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int upDramParityErrorMask : 1; /* 1E.D402.A R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int reserved0 : 3; + /*! \brief 1E.D402.E R/WPD Mailbox Operation Complete Mask + AQ_GlobalInterruptMask_HHD.u2.bits_2.mailboxOperationCompleteMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + Notes: + Mailbox interface is ready interrupt for registers See Global Vendor Specific Control - Address 1E.C000 - See Global Vendor Specific Provisioning 5 - Address 1E.C404 */ + unsigned int mailboxOperationCompleteMask : 1; /* 1E.D402.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D402.F R/WPD NVR Operation Complete Mask + AQ_GlobalInterruptMask_HHD.u2.bits_2.nvrOperationCompleteMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + Notes: + NVR interface is ready interrupt for registers See Global NVR Interface 1: Address 1E.100 - See Global NVR Provisioning Data MSW - Address 1E.17 */ + unsigned int nvrOperationCompleteMask : 1; /* 1E.D402.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + } bits_2; + uint16_t word_2; + } u2; +} AQ_GlobalInterruptMask_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Chip-Wide Standard Interrupt Flags: 1E.FC00 */ +/* Global Chip-Wide Standard Interrupt Flags: 1E.FC00 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Chip-Wide Standard Interrupt Flags */ + union + { + struct + { + /*! \brief 1E.FC00.0 RO All Vendor Alarms Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.allVendorAlarmsInterrupt + + + + 1 = Interrupt in all vendor alarms + + + Notes: + An interrupt was generated from status register ( See Global Chip-Wide LASI Vendor Interrupt Flags: Address 1E.FC01 ) and the corresponding mask register. ( See Global Interrupt LASI Mask: Address 1E.FF01 ) */ + unsigned int allVendorAlarmsInterrupt : 1; /* 1E.FC00.0 RO */ + /* 1 = Interrupt in all vendor alarms + */ + unsigned int reserved0 : 5; + /*! \brief 1E.FC00.6 RO GbE Standard Alarms Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.gbeStandardAlarmsInterrupt + + + + 1 = Interrupt in GbE standard alarms + + + Notes: + An interrupt was generated from the TGE core. */ + unsigned int gbeStandardAlarmsInterrupt : 1; /* 1E.FC00.6 RO */ + /* 1 = Interrupt in GbE standard alarms + */ + /*! \brief 1E.FC00.7 RO Autonegotiation Standard Alarms 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.autonegotiationStandardAlarms_2Interrupt + + + + 1 = Interrupt in Autonegotiation standard alarms 2 + + + Notes: + An interrupt was generated from status register ( See Autonegotiation 10GBASE-T Status Register - Address 7.21 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int autonegotiationStandardAlarms_2Interrupt : 1; /* 1E.FC00.7 RO */ + /* 1 = Interrupt in Autonegotiation standard alarms 2 + */ + /*! \brief 1E.FC00.8 RO Autonegotiation Standard Alarms 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.autonegotiationStandardAlarms_1Interrupt + + + + 1 = Interrupt in Autonegotiation standard alarms 1 + + + Notes: + An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See Autonegotiation Standard LASI Interrupt Mask 1: Address 7.D000 ) */ + unsigned int autonegotiationStandardAlarms_1Interrupt : 1; /* 1E.FC00.8 RO */ + /* 1 = Interrupt in Autonegotiation standard alarms 1 + */ + /*! \brief 1E.FC00.9 RO PHY XS Standard Alarms 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.phyXS_StandardAlarms_2Interrupt + + + + 1 = Interrupt in PHY XS standard alarms 2 + + + Notes: + An interrupt was generated from the status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int phyXS_StandardAlarms_2Interrupt : 1; /* 1E.FC00.9 RO */ + /* 1 = Interrupt in PHY XS standard alarms 2 + */ + /*! \brief 1E.FC00.A RO PHY XS Standard Alarms 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.phyXS_StandardAlarms_1Interrupt + + + + 1 = Interrupt in PHY XS standard alarms 1 + + + Notes: + An interrupt was generated from the status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ + unsigned int phyXS_StandardAlarms_1Interrupt : 1; /* 1E.FC00.A RO */ + /* 1 = Interrupt in PHY XS standard alarms 1 + */ + /*! \brief 1E.FC00.B RO PCS Standard Alarm 3 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.pcsStandardAlarm_3Interrupt + + + + 1 = Interrupt in PCS standard alarms 3 + + + Notes: + An interrupt was generated from status register ( See PCS 10GBASE-T Status 2 - Address 3.21 ) and the corresponding mask register. ( See PCS Standard Interrupt Mask 1 - Address 3.E021 ) */ + unsigned int pcsStandardAlarm_3Interrupt : 1; /* 1E.FC00.B RO */ + /* 1 = Interrupt in PCS standard alarms 3 + */ + /*! \brief 1E.FC00.C RO PCS Standard Alarm 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.pcsStandardAlarm_2Interrupt + + + + 1 = Interrupt in PCS standard alarms 2 + + + Notes: + An interrupt was generated from status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int pcsStandardAlarm_2Interrupt : 1; /* 1E.FC00.C RO */ + /* 1 = Interrupt in PCS standard alarms 2 + */ + /*! \brief 1E.FC00.D RO PCS Standard Alarm 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.pcsStandardAlarm_1Interrupt + + + + 1 = Interrupt in PCS standard alarms 1 + + + Notes: + An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ + unsigned int pcsStandardAlarm_1Interrupt : 1; /* 1E.FC00.D RO */ + /* 1 = Interrupt in PCS standard alarms 1 + */ + /*! \brief 1E.FC00.E RO PMA Standard Alarm 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.pmaStandardAlarm_2Interrupt + + + + 1 = Interrupt in PMA standard alarms 2 + + + Notes: + An interrupt was generated from either bit 1.8.B or 1.8.A. + An interrupt was generated from status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int pmaStandardAlarm_2Interrupt : 1; /* 1E.FC00.E RO */ + /* 1 = Interrupt in PMA standard alarms 2 + */ + /*! \brief 1E.FC00.F RO PMA Standard Alarm 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.pmaStandardAlarm_1Interrupt + + + + 1 = Interrupt in PMA standard alarms 1 + + + Notes: + An interrupt was generated from bit 1.1.2. + An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ + unsigned int pmaStandardAlarm_1Interrupt : 1; /* 1E.FC00.F RO */ + /* 1 = Interrupt in PMA standard alarms 1 + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalChip_wideStandardInterruptFlags_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Chip-Wide Vendor Interrupt Flags: 1E.FC01 */ +/* Global Chip-Wide Vendor Interrupt Flags: 1E.FC01 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Chip-Wide Vendor Interrupt Flags */ + union + { + struct + { + /*! \brief 1E.FC01.0 RO Global Alarms 3 Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.globalAlarms_3Interrupt + + + + 1 = Interrupt in Global alarms 3 + + + Notes: + An interrupt was generated from status register ( See Global Vendor Alarms 2: Address 1E.CC01 ) and the corresponding mask register. ( See Global LASI Interrupt Mask 2: Address 1E.D401 ) */ + unsigned int globalAlarms_3Interrupt : 1; /* 1E.FC01.0 RO */ + /* 1 = Interrupt in Global alarms 3 + */ + /*! \brief 1E.FC01.1 RO Global Alarms 2 Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.globalAlarms_2Interrupt + + + + 1 = Interrupt in Global alarms 2 + + + Notes: + An interrupt was generated from status register ( See Global Alarms 2: Address 1E.CC01 ) and the corresponding mask register. ( See Global LASI Interrupt Mask 2: Address 1E.D401 ) */ + unsigned int globalAlarms_2Interrupt : 1; /* 1E.FC01.1 RO */ + /* 1 = Interrupt in Global alarms 2 + */ + /*! \brief 1E.FC01.2 RO Global Alarms 1 Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.globalAlarms_1Interrupt + + + + 1 = Interrupt in Global alarms 1 + + + Notes: + An interrupt was generated from status register ( See Global Vendor Alarms 1 - Address 1E.CC00 ) and the corresponding mask register. ( See Global Vendor Interrupt Mask - Address 1E.D400 ) */ + unsigned int globalAlarms_1Interrupt : 1; /* 1E.FC01.2 RO */ + /* 1 = Interrupt in Global alarms 1 + */ + unsigned int reserved0 : 8; + /*! \brief 1E.FC01.B RO GbE Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.gbeVendorAlarmInterrupt + + + + 1 = Interrupt in GbE vendor specific alarm + + + Notes: + A GbE alarm was generated. ( See GbE PHY Vendor Global LASI Interrupt Flags 1: Address 1D.FC00 ) */ + unsigned int gbeVendorAlarmInterrupt : 1; /* 1E.FC01.B RO */ + /* 1 = Interrupt in GbE vendor specific alarm + */ + /*! \brief 1E.FC01.C RO Autonegotiation Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.autonegotiationVendorAlarmInterrupt + + + + 1 = Interrupt in Autonegotiation vendor specific alarm + + + Notes: + An Autonegotiation alarm was generated. ( See Autonegotiation Vendor Global LASI Interrupt Flags 1: Address 7.FC00 ) */ + unsigned int autonegotiationVendorAlarmInterrupt : 1; /* 1E.FC01.C RO */ + /* 1 = Interrupt in Autonegotiation vendor specific alarm + */ + /*! \brief 1E.FC01.D RO PHY XS Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.phyXS_VendorAlarmInterrupt + + + + 1 = Interrupt in PHY XS vendor specific alarm + + + Notes: + A PHY XS alarm was generated. ( See PHY XS Vendor Global LASI Interrupt Flags 1: Address 4.FC00 ) */ + unsigned int phyXS_VendorAlarmInterrupt : 1; /* 1E.FC01.D RO */ + /* 1 = Interrupt in PHY XS vendor specific alarm + */ + /*! \brief 1E.FC01.E RO PCS Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.pcsVendorAlarmInterrupt + + + + 1 = Interrupt in PCS vendor specific alarm + + + Notes: + A PCS alarm was generated. ( See PHY XS Vendor Global Interrupt Flags 1- Address 4.F800 ) */ + unsigned int pcsVendorAlarmInterrupt : 1; /* 1E.FC01.E RO */ + /* 1 = Interrupt in PCS vendor specific alarm + */ + /*! \brief 1E.FC01.F RO PMA Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.pmaVendorAlarmInterrupt + + + + 1 = Interrupt in PMA vendor specific alarm + + + Notes: + A PMA alarm was generated. ( See PHY XS Vendor Global Interrupt Flags 1- Address 4.F800 ) */ + unsigned int pmaVendorAlarmInterrupt : 1; /* 1E.FC01.F RO */ + /* 1 = Interrupt in PMA vendor specific alarm + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalChip_wideVendorInterruptFlags_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Interrupt Chip-Wide Standard Mask: 1E.FF00 */ +/* Global Interrupt Chip-Wide Standard Mask: 1E.FF00 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Interrupt Chip-Wide Standard Mask */ + union + { + struct + { + /*! \brief 1E.FF00.0 R/WPD All Vendor Alarms Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.allVendorAlarmsInterruptMask + + Provisionable Default = 0x1 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int allVendorAlarmsInterruptMask : 1; /* 1E.FF00.0 R/WPD Provisionable Default = 0x1 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved0 : 5; + /*! \brief 1E.FF00.6 R/WPD Gbe Standard Alarms Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.gbeStandardAlarmsInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int gbeStandardAlarmsInterruptMask : 1; /* 1E.FF00.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.7 R/WPD Autonegotiation Standard Alarms 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.autonegotiationStandardAlarms_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int autonegotiationStandardAlarms_2InterruptMask : 1; /* 1E.FF00.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.8 R/WPD Autonegotiation Standard Alarms 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.autonegotiationStandardAlarms_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int autonegotiationStandardAlarms_1InterruptMask : 1; /* 1E.FF00.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.9 R/WPD PHY XS Standard Alarms 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.phyXS_StandardAlarms_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int phyXS_StandardAlarms_2InterruptMask : 1; /* 1E.FF00.9 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.A R/WPD PHY XS Standard Alarms 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.phyXS_StandardAlarms_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int phyXS_StandardAlarms_1InterruptMask : 1; /* 1E.FF00.A R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.B R/WPD PCS Standard Alarm 3 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.pcsStandardAlarm_3InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsStandardAlarm_3InterruptMask : 1; /* 1E.FF00.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.C R/WPD PCS Standard Alarm 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.pcsStandardAlarm_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsStandardAlarm_2InterruptMask : 1; /* 1E.FF00.C R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.D R/WPD PCS Standard Alarm 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.pcsStandardAlarm_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsStandardAlarm_1InterruptMask : 1; /* 1E.FF00.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.E R/WPD PMA Standard Alarm 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.pmaStandardAlarm_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pmaStandardAlarm_2InterruptMask : 1; /* 1E.FF00.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.F R/WPD PMA Standard Alarm 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.pmaStandardAlarm_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pmaStandardAlarm_1InterruptMask : 1; /* 1E.FF00.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalInterruptChip_wideStandardMask_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Interrupt Chip-Wide Vendor Mask: 1E.FF01 */ +/* Global Interrupt Chip-Wide Vendor Mask: 1E.FF01 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Interrupt Chip-Wide Vendor Mask */ + union + { + struct + { + /*! \brief 1E.FF01.0 R/WPD Global Alarms 3 Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.globalAlarms_3InterruptMask + + Provisionable Default = 0x1 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int globalAlarms_3InterruptMask : 1; /* 1E.FF01.0 R/WPD Provisionable Default = 0x1 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.1 R/WPD Global Alarms 2 Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.globalAlarms_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int globalAlarms_2InterruptMask : 1; /* 1E.FF01.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.2 R/WPD Global Alarms 1 Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.globalAlarms_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int globalAlarms_1InterruptMask : 1; /* 1E.FF01.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved0 : 8; + /*! \brief 1E.FF01.B R/WPD GbE Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.gbeVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int gbeVendorAlarmInterruptMask : 1; /* 1E.FF01.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.C R/WPD Autonegotiation Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.autonegotiationVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int autonegotiationVendorAlarmInterruptMask : 1; /* 1E.FF01.C R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.D R/WPD PHY XS Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.phyXS_VendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int phyXS_VendorAlarmInterruptMask : 1; /* 1E.FF01.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.E R/WPD PCS Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.pcsVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsVendorAlarmInterruptMask : 1; /* 1E.FF01.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.F R/WPD PMA Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.pmaVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pmaVendorAlarmInterruptMask : 1; /* 1E.FF01.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalInterruptChip_wideVendorMask_HHD; + +#endif +/*@}*/ +/*@}*/ diff --git a/qca/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers_Defines.h b/qca/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers_Defines.h new file mode 100644 index 000000000..d9a4429d5 --- /dev/null +++ b/qca/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers_Defines.h @@ -0,0 +1,4413 @@ +/*! \file +* This file contains the compiler assist macros and doxygen comments +* for the Global Registers block. +*/ + +/*! \defgroup Global_registers_Defines Global Registers Defines +* This module contains the compiler assist macros and doxygen comments +* for the Global Registers block. +*/ +/*********************************************************************** +* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +* +* $File: //depot/icm/proj/Dena/rev1.0/c/Systems/tools/windows/regMapParser/src/gencheaders.py $ +* +* $Revision: #10 $ +* +* $DateTime: 2014/04/08 16:55:58 $ +* +* $Author: joshd $ +* +* $Label: $ +* +* Description: +* +* This file contains the compiler assist macros for the registers contained in the Global Registers block. +* +* +***********************************************************************/ + + +/*@{*/ +#ifndef AQ_HHD_GLOBAL_REGS_DEFINES_HEADER +#define AQ_HHD_GLOBAL_REGS_DEFINES_HEADER + + +/*-----------------------------------------------------------------------------*/ +/*Access macro definitions */ +/*-----------------------------------------------------------------------------*/ +/*! \brief Base register address of structure AQ_GlobalStandardControl_1_HHD */ +#define AQ_GlobalStandardControl_1_HHD_baseRegisterAddress 0x0000 +/*! \brief MMD address of structure AQ_GlobalStandardControl_1_HHD */ +#define AQ_GlobalStandardControl_1_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure softReset in AQ_GlobalStandardControl_1_HHD */ +#define AQ_GlobalStandardControl_1_HHD_softReset 0 +/*! \brief Preprocessor variable to relate field to bit position in structure softReset in AQ_GlobalStandardControl_1_HHD */ +#define bits_AQ_GlobalStandardControl_1_HHD_softReset u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure softReset in AQ_GlobalStandardControl_1_HHD */ +#define word_AQ_GlobalStandardControl_1_HHD_softReset u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure lowPower in AQ_GlobalStandardControl_1_HHD */ +#define AQ_GlobalStandardControl_1_HHD_lowPower 0 +/*! \brief Preprocessor variable to relate field to bit position in structure lowPower in AQ_GlobalStandardControl_1_HHD */ +#define bits_AQ_GlobalStandardControl_1_HHD_lowPower u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure lowPower in AQ_GlobalStandardControl_1_HHD */ +#define word_AQ_GlobalStandardControl_1_HHD_lowPower u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalStandardDeviceIdentifier_HHD */ +#define AQ_GlobalStandardDeviceIdentifier_HHD_baseRegisterAddress 0x0002 +/*! \brief MMD address of structure AQ_GlobalStandardDeviceIdentifier_HHD */ +#define AQ_GlobalStandardDeviceIdentifier_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure deviceIdMSW in AQ_GlobalStandardDeviceIdentifier_HHD */ +#define AQ_GlobalStandardDeviceIdentifier_HHD_deviceIdMSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure deviceIdMSW in AQ_GlobalStandardDeviceIdentifier_HHD */ +#define bits_AQ_GlobalStandardDeviceIdentifier_HHD_deviceIdMSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure deviceIdMSW in AQ_GlobalStandardDeviceIdentifier_HHD */ +#define word_AQ_GlobalStandardDeviceIdentifier_HHD_deviceIdMSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure deviceIdLSW in AQ_GlobalStandardDeviceIdentifier_HHD */ +#define AQ_GlobalStandardDeviceIdentifier_HHD_deviceIdLSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure deviceIdLSW in AQ_GlobalStandardDeviceIdentifier_HHD */ +#define bits_AQ_GlobalStandardDeviceIdentifier_HHD_deviceIdLSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure deviceIdLSW in AQ_GlobalStandardDeviceIdentifier_HHD */ +#define word_AQ_GlobalStandardDeviceIdentifier_HHD_deviceIdLSW u1.word_1 + +/*! \brief Base register address of structure AQ_GlobalStandardDevicesInPackage_HHD */ +#define AQ_GlobalStandardDevicesInPackage_HHD_baseRegisterAddress 0x0005 +/*! \brief MMD address of structure AQ_GlobalStandardDevicesInPackage_HHD */ +#define AQ_GlobalStandardDevicesInPackage_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define AQ_GlobalStandardDevicesInPackage_HHD_autonegotiationPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define bits_AQ_GlobalStandardDevicesInPackage_HHD_autonegotiationPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define word_AQ_GlobalStandardDevicesInPackage_HHD_autonegotiationPresent u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure tcPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define AQ_GlobalStandardDevicesInPackage_HHD_tcPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure tcPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define bits_AQ_GlobalStandardDevicesInPackage_HHD_tcPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure tcPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define word_AQ_GlobalStandardDevicesInPackage_HHD_tcPresent u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure dteXsPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define AQ_GlobalStandardDevicesInPackage_HHD_dteXsPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure dteXsPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define bits_AQ_GlobalStandardDevicesInPackage_HHD_dteXsPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure dteXsPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define word_AQ_GlobalStandardDevicesInPackage_HHD_dteXsPresent u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure phyXS_Present in AQ_GlobalStandardDevicesInPackage_HHD */ +#define AQ_GlobalStandardDevicesInPackage_HHD_phyXS_Present 0 +/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_Present in AQ_GlobalStandardDevicesInPackage_HHD */ +#define bits_AQ_GlobalStandardDevicesInPackage_HHD_phyXS_Present u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure phyXS_Present in AQ_GlobalStandardDevicesInPackage_HHD */ +#define word_AQ_GlobalStandardDevicesInPackage_HHD_phyXS_Present u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define AQ_GlobalStandardDevicesInPackage_HHD_pcsPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define bits_AQ_GlobalStandardDevicesInPackage_HHD_pcsPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define word_AQ_GlobalStandardDevicesInPackage_HHD_pcsPresent u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure wisPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define AQ_GlobalStandardDevicesInPackage_HHD_wisPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure wisPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define bits_AQ_GlobalStandardDevicesInPackage_HHD_wisPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure wisPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define word_AQ_GlobalStandardDevicesInPackage_HHD_wisPresent u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pmaPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define AQ_GlobalStandardDevicesInPackage_HHD_pmaPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pmaPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define bits_AQ_GlobalStandardDevicesInPackage_HHD_pmaPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pmaPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define word_AQ_GlobalStandardDevicesInPackage_HHD_pmaPresent u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure clause_22RegistersPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define AQ_GlobalStandardDevicesInPackage_HHD_clause_22RegistersPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure clause_22RegistersPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define bits_AQ_GlobalStandardDevicesInPackage_HHD_clause_22RegistersPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure clause_22RegistersPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define word_AQ_GlobalStandardDevicesInPackage_HHD_clause_22RegistersPresent u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalStandardVendorDevicesInPackage_HHD */ +#define AQ_GlobalStandardVendorDevicesInPackage_HHD_baseRegisterAddress 0x0006 +/*! \brief MMD address of structure AQ_GlobalStandardVendorDevicesInPackage_HHD */ +#define AQ_GlobalStandardVendorDevicesInPackage_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure vendorSpecificDevice_2Present in AQ_GlobalStandardVendorDevicesInPackage_HHD */ +#define AQ_GlobalStandardVendorDevicesInPackage_HHD_vendorSpecificDevice_2Present 0 +/*! \brief Preprocessor variable to relate field to bit position in structure vendorSpecificDevice_2Present in AQ_GlobalStandardVendorDevicesInPackage_HHD */ +#define bits_AQ_GlobalStandardVendorDevicesInPackage_HHD_vendorSpecificDevice_2Present u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure vendorSpecificDevice_2Present in AQ_GlobalStandardVendorDevicesInPackage_HHD */ +#define word_AQ_GlobalStandardVendorDevicesInPackage_HHD_vendorSpecificDevice_2Present u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure vendorSpecificDevice_1Present in AQ_GlobalStandardVendorDevicesInPackage_HHD */ +#define AQ_GlobalStandardVendorDevicesInPackage_HHD_vendorSpecificDevice_1Present 0 +/*! \brief Preprocessor variable to relate field to bit position in structure vendorSpecificDevice_1Present in AQ_GlobalStandardVendorDevicesInPackage_HHD */ +#define bits_AQ_GlobalStandardVendorDevicesInPackage_HHD_vendorSpecificDevice_1Present u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure vendorSpecificDevice_1Present in AQ_GlobalStandardVendorDevicesInPackage_HHD */ +#define word_AQ_GlobalStandardVendorDevicesInPackage_HHD_vendorSpecificDevice_1Present u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure clause_22ExtensionPresent in AQ_GlobalStandardVendorDevicesInPackage_HHD */ +#define AQ_GlobalStandardVendorDevicesInPackage_HHD_clause_22ExtensionPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure clause_22ExtensionPresent in AQ_GlobalStandardVendorDevicesInPackage_HHD */ +#define bits_AQ_GlobalStandardVendorDevicesInPackage_HHD_clause_22ExtensionPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure clause_22ExtensionPresent in AQ_GlobalStandardVendorDevicesInPackage_HHD */ +#define word_AQ_GlobalStandardVendorDevicesInPackage_HHD_clause_22ExtensionPresent u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalStandardStatus_2_HHD */ +#define AQ_GlobalStandardStatus_2_HHD_baseRegisterAddress 0x0008 +/*! \brief MMD address of structure AQ_GlobalStandardStatus_2_HHD */ +#define AQ_GlobalStandardStatus_2_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure devicePresent in AQ_GlobalStandardStatus_2_HHD */ +#define AQ_GlobalStandardStatus_2_HHD_devicePresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure devicePresent in AQ_GlobalStandardStatus_2_HHD */ +#define bits_AQ_GlobalStandardStatus_2_HHD_devicePresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure devicePresent in AQ_GlobalStandardStatus_2_HHD */ +#define word_AQ_GlobalStandardStatus_2_HHD_devicePresent u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalStandardPackageIdentifier_HHD */ +#define AQ_GlobalStandardPackageIdentifier_HHD_baseRegisterAddress 0x000E +/*! \brief MMD address of structure AQ_GlobalStandardPackageIdentifier_HHD */ +#define AQ_GlobalStandardPackageIdentifier_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure packageIdMSW in AQ_GlobalStandardPackageIdentifier_HHD */ +#define AQ_GlobalStandardPackageIdentifier_HHD_packageIdMSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure packageIdMSW in AQ_GlobalStandardPackageIdentifier_HHD */ +#define bits_AQ_GlobalStandardPackageIdentifier_HHD_packageIdMSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure packageIdMSW in AQ_GlobalStandardPackageIdentifier_HHD */ +#define word_AQ_GlobalStandardPackageIdentifier_HHD_packageIdMSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure packageIdLSW in AQ_GlobalStandardPackageIdentifier_HHD */ +#define AQ_GlobalStandardPackageIdentifier_HHD_packageIdLSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure packageIdLSW in AQ_GlobalStandardPackageIdentifier_HHD */ +#define bits_AQ_GlobalStandardPackageIdentifier_HHD_packageIdLSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure packageIdLSW in AQ_GlobalStandardPackageIdentifier_HHD */ +#define word_AQ_GlobalStandardPackageIdentifier_HHD_packageIdLSW u1.word_1 + +/*! \brief Base register address of structure AQ_GlobalFirmwareID_HHD */ +#define AQ_GlobalFirmwareID_HHD_baseRegisterAddress 0x0020 +/*! \brief MMD address of structure AQ_GlobalFirmwareID_HHD */ +#define AQ_GlobalFirmwareID_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure firmwareMajorRevisionNumber in AQ_GlobalFirmwareID_HHD */ +#define AQ_GlobalFirmwareID_HHD_firmwareMajorRevisionNumber 0 +/*! \brief Preprocessor variable to relate field to bit position in structure firmwareMajorRevisionNumber in AQ_GlobalFirmwareID_HHD */ +#define bits_AQ_GlobalFirmwareID_HHD_firmwareMajorRevisionNumber u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure firmwareMajorRevisionNumber in AQ_GlobalFirmwareID_HHD */ +#define word_AQ_GlobalFirmwareID_HHD_firmwareMajorRevisionNumber u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure firmwareMinorRevisionNumber in AQ_GlobalFirmwareID_HHD */ +#define AQ_GlobalFirmwareID_HHD_firmwareMinorRevisionNumber 0 +/*! \brief Preprocessor variable to relate field to bit position in structure firmwareMinorRevisionNumber in AQ_GlobalFirmwareID_HHD */ +#define bits_AQ_GlobalFirmwareID_HHD_firmwareMinorRevisionNumber u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure firmwareMinorRevisionNumber in AQ_GlobalFirmwareID_HHD */ +#define word_AQ_GlobalFirmwareID_HHD_firmwareMinorRevisionNumber u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalNvrInterface_HHD */ +#define AQ_GlobalNvrInterface_HHD_baseRegisterAddress 0x0100 +/*! \brief MMD address of structure AQ_GlobalNvrInterface_HHD */ +#define AQ_GlobalNvrInterface_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure nvrExecuteOperation in AQ_GlobalNvrInterface_HHD */ +#define AQ_GlobalNvrInterface_HHD_nvrExecuteOperation 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrExecuteOperation in AQ_GlobalNvrInterface_HHD */ +#define bits_AQ_GlobalNvrInterface_HHD_nvrExecuteOperation u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrExecuteOperation in AQ_GlobalNvrInterface_HHD */ +#define word_AQ_GlobalNvrInterface_HHD_nvrExecuteOperation u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrWriteMode in AQ_GlobalNvrInterface_HHD */ +#define AQ_GlobalNvrInterface_HHD_nvrWriteMode 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrWriteMode in AQ_GlobalNvrInterface_HHD */ +#define bits_AQ_GlobalNvrInterface_HHD_nvrWriteMode u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrWriteMode in AQ_GlobalNvrInterface_HHD */ +#define word_AQ_GlobalNvrInterface_HHD_nvrWriteMode u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure freezeNvrCrc in AQ_GlobalNvrInterface_HHD */ +#define AQ_GlobalNvrInterface_HHD_freezeNvrCrc 0 +/*! \brief Preprocessor variable to relate field to bit position in structure freezeNvrCrc in AQ_GlobalNvrInterface_HHD */ +#define bits_AQ_GlobalNvrInterface_HHD_freezeNvrCrc u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure freezeNvrCrc in AQ_GlobalNvrInterface_HHD */ +#define word_AQ_GlobalNvrInterface_HHD_freezeNvrCrc u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure resetNvrCrc in AQ_GlobalNvrInterface_HHD */ +#define AQ_GlobalNvrInterface_HHD_resetNvrCrc 0 +/*! \brief Preprocessor variable to relate field to bit position in structure resetNvrCrc in AQ_GlobalNvrInterface_HHD */ +#define bits_AQ_GlobalNvrInterface_HHD_resetNvrCrc u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure resetNvrCrc in AQ_GlobalNvrInterface_HHD */ +#define word_AQ_GlobalNvrInterface_HHD_resetNvrCrc u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrBurst in AQ_GlobalNvrInterface_HHD */ +#define AQ_GlobalNvrInterface_HHD_nvrBurst 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrBurst in AQ_GlobalNvrInterface_HHD */ +#define bits_AQ_GlobalNvrInterface_HHD_nvrBurst u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrBurst in AQ_GlobalNvrInterface_HHD */ +#define word_AQ_GlobalNvrInterface_HHD_nvrBurst u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrBusy in AQ_GlobalNvrInterface_HHD */ +#define AQ_GlobalNvrInterface_HHD_nvrBusy 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrBusy in AQ_GlobalNvrInterface_HHD */ +#define bits_AQ_GlobalNvrInterface_HHD_nvrBusy u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrBusy in AQ_GlobalNvrInterface_HHD */ +#define word_AQ_GlobalNvrInterface_HHD_nvrBusy u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrOpcode in AQ_GlobalNvrInterface_HHD */ +#define AQ_GlobalNvrInterface_HHD_nvrOpcode 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrOpcode in AQ_GlobalNvrInterface_HHD */ +#define bits_AQ_GlobalNvrInterface_HHD_nvrOpcode u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrOpcode in AQ_GlobalNvrInterface_HHD */ +#define word_AQ_GlobalNvrInterface_HHD_nvrOpcode u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrMailboxCrc in AQ_GlobalNvrInterface_HHD */ +#define AQ_GlobalNvrInterface_HHD_nvrMailboxCrc 1 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrMailboxCrc in AQ_GlobalNvrInterface_HHD */ +#define bits_AQ_GlobalNvrInterface_HHD_nvrMailboxCrc u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure nvrMailboxCrc in AQ_GlobalNvrInterface_HHD */ +#define word_AQ_GlobalNvrInterface_HHD_nvrMailboxCrc u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure nvrAddressMSW in AQ_GlobalNvrInterface_HHD */ +#define AQ_GlobalNvrInterface_HHD_nvrAddressMSW 2 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrAddressMSW in AQ_GlobalNvrInterface_HHD */ +#define bits_AQ_GlobalNvrInterface_HHD_nvrAddressMSW u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure nvrAddressMSW in AQ_GlobalNvrInterface_HHD */ +#define word_AQ_GlobalNvrInterface_HHD_nvrAddressMSW u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure nvrAddressLSW in AQ_GlobalNvrInterface_HHD */ +#define AQ_GlobalNvrInterface_HHD_nvrAddressLSW 3 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrAddressLSW in AQ_GlobalNvrInterface_HHD */ +#define bits_AQ_GlobalNvrInterface_HHD_nvrAddressLSW u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure nvrAddressLSW in AQ_GlobalNvrInterface_HHD */ +#define word_AQ_GlobalNvrInterface_HHD_nvrAddressLSW u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure nvrDataMSW in AQ_GlobalNvrInterface_HHD */ +#define AQ_GlobalNvrInterface_HHD_nvrDataMSW 4 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrDataMSW in AQ_GlobalNvrInterface_HHD */ +#define bits_AQ_GlobalNvrInterface_HHD_nvrDataMSW u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure nvrDataMSW in AQ_GlobalNvrInterface_HHD */ +#define word_AQ_GlobalNvrInterface_HHD_nvrDataMSW u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure nvrDataLSW in AQ_GlobalNvrInterface_HHD */ +#define AQ_GlobalNvrInterface_HHD_nvrDataLSW 5 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrDataLSW in AQ_GlobalNvrInterface_HHD */ +#define bits_AQ_GlobalNvrInterface_HHD_nvrDataLSW u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure nvrDataLSW in AQ_GlobalNvrInterface_HHD */ +#define word_AQ_GlobalNvrInterface_HHD_nvrDataLSW u5.word_5 + +/*! \brief Base register address of structure AQ_GlobalMailboxInterface_HHD */ +#define AQ_GlobalMailboxInterface_HHD_baseRegisterAddress 0x0200 +/*! \brief MMD address of structure AQ_GlobalMailboxInterface_HHD */ +#define AQ_GlobalMailboxInterface_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxExecuteOperation in AQ_GlobalMailboxInterface_HHD */ +#define AQ_GlobalMailboxInterface_HHD_upMailboxExecuteOperation 0 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxExecuteOperation in AQ_GlobalMailboxInterface_HHD */ +#define bits_AQ_GlobalMailboxInterface_HHD_upMailboxExecuteOperation u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxExecuteOperation in AQ_GlobalMailboxInterface_HHD */ +#define word_AQ_GlobalMailboxInterface_HHD_upMailboxExecuteOperation u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxWriteMode in AQ_GlobalMailboxInterface_HHD */ +#define AQ_GlobalMailboxInterface_HHD_upMailboxWriteMode 0 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxWriteMode in AQ_GlobalMailboxInterface_HHD */ +#define bits_AQ_GlobalMailboxInterface_HHD_upMailboxWriteMode u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxWriteMode in AQ_GlobalMailboxInterface_HHD */ +#define word_AQ_GlobalMailboxInterface_HHD_upMailboxWriteMode u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure resetUpMailboxCrc in AQ_GlobalMailboxInterface_HHD */ +#define AQ_GlobalMailboxInterface_HHD_resetUpMailboxCrc 0 +/*! \brief Preprocessor variable to relate field to bit position in structure resetUpMailboxCrc in AQ_GlobalMailboxInterface_HHD */ +#define bits_AQ_GlobalMailboxInterface_HHD_resetUpMailboxCrc u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure resetUpMailboxCrc in AQ_GlobalMailboxInterface_HHD */ +#define word_AQ_GlobalMailboxInterface_HHD_resetUpMailboxCrc u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxBusy in AQ_GlobalMailboxInterface_HHD */ +#define AQ_GlobalMailboxInterface_HHD_upMailboxBusy 0 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxBusy in AQ_GlobalMailboxInterface_HHD */ +#define bits_AQ_GlobalMailboxInterface_HHD_upMailboxBusy u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxBusy in AQ_GlobalMailboxInterface_HHD */ +#define word_AQ_GlobalMailboxInterface_HHD_upMailboxBusy u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxCrc in AQ_GlobalMailboxInterface_HHD */ +#define AQ_GlobalMailboxInterface_HHD_upMailboxCrc 1 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxCrc in AQ_GlobalMailboxInterface_HHD */ +#define bits_AQ_GlobalMailboxInterface_HHD_upMailboxCrc u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxCrc in AQ_GlobalMailboxInterface_HHD */ +#define word_AQ_GlobalMailboxInterface_HHD_upMailboxCrc u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxAddressMSW in AQ_GlobalMailboxInterface_HHD */ +#define AQ_GlobalMailboxInterface_HHD_upMailboxAddressMSW 2 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxAddressMSW in AQ_GlobalMailboxInterface_HHD */ +#define bits_AQ_GlobalMailboxInterface_HHD_upMailboxAddressMSW u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxAddressMSW in AQ_GlobalMailboxInterface_HHD */ +#define word_AQ_GlobalMailboxInterface_HHD_upMailboxAddressMSW u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxAddressLSW in AQ_GlobalMailboxInterface_HHD */ +#define AQ_GlobalMailboxInterface_HHD_upMailboxAddressLSW 3 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxAddressLSW in AQ_GlobalMailboxInterface_HHD */ +#define bits_AQ_GlobalMailboxInterface_HHD_upMailboxAddressLSW u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxAddressLSW in AQ_GlobalMailboxInterface_HHD */ +#define word_AQ_GlobalMailboxInterface_HHD_upMailboxAddressLSW u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxAddressLSW_Don_tCare in AQ_GlobalMailboxInterface_HHD */ +#define AQ_GlobalMailboxInterface_HHD_upMailboxAddressLSW_Don_tCare 3 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxAddressLSW_Don_tCare in AQ_GlobalMailboxInterface_HHD */ +#define bits_AQ_GlobalMailboxInterface_HHD_upMailboxAddressLSW_Don_tCare u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxAddressLSW_Don_tCare in AQ_GlobalMailboxInterface_HHD */ +#define word_AQ_GlobalMailboxInterface_HHD_upMailboxAddressLSW_Don_tCare u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxDataMSW in AQ_GlobalMailboxInterface_HHD */ +#define AQ_GlobalMailboxInterface_HHD_upMailboxDataMSW 4 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxDataMSW in AQ_GlobalMailboxInterface_HHD */ +#define bits_AQ_GlobalMailboxInterface_HHD_upMailboxDataMSW u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxDataMSW in AQ_GlobalMailboxInterface_HHD */ +#define word_AQ_GlobalMailboxInterface_HHD_upMailboxDataMSW u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxDataLSW in AQ_GlobalMailboxInterface_HHD */ +#define AQ_GlobalMailboxInterface_HHD_upMailboxDataLSW 5 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxDataLSW in AQ_GlobalMailboxInterface_HHD */ +#define bits_AQ_GlobalMailboxInterface_HHD_upMailboxDataLSW u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxDataLSW in AQ_GlobalMailboxInterface_HHD */ +#define word_AQ_GlobalMailboxInterface_HHD_upMailboxDataLSW u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxCrcReadEnable in AQ_GlobalMailboxInterface_HHD */ +#define AQ_GlobalMailboxInterface_HHD_upMailboxCrcReadEnable 6 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxCrcReadEnable in AQ_GlobalMailboxInterface_HHD */ +#define bits_AQ_GlobalMailboxInterface_HHD_upMailboxCrcReadEnable u6.bits_6 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxCrcReadEnable in AQ_GlobalMailboxInterface_HHD */ +#define word_AQ_GlobalMailboxInterface_HHD_upMailboxCrcReadEnable u6.word_6 + +/*! \brief Base register address of structure AQ_GlobalMicroprocessorScratchPad_HHD */ +#define AQ_GlobalMicroprocessorScratchPad_HHD_baseRegisterAddress 0x0300 +/*! \brief MMD address of structure AQ_GlobalMicroprocessorScratchPad_HHD */ +#define AQ_GlobalMicroprocessorScratchPad_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure scratchPad_1 in AQ_GlobalMicroprocessorScratchPad_HHD */ +#define AQ_GlobalMicroprocessorScratchPad_HHD_scratchPad_1 0 +/*! \brief Preprocessor variable to relate field to bit position in structure scratchPad_1 in AQ_GlobalMicroprocessorScratchPad_HHD */ +#define bits_AQ_GlobalMicroprocessorScratchPad_HHD_scratchPad_1 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure scratchPad_1 in AQ_GlobalMicroprocessorScratchPad_HHD */ +#define word_AQ_GlobalMicroprocessorScratchPad_HHD_scratchPad_1 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure scratchPad_2 in AQ_GlobalMicroprocessorScratchPad_HHD */ +#define AQ_GlobalMicroprocessorScratchPad_HHD_scratchPad_2 1 +/*! \brief Preprocessor variable to relate field to bit position in structure scratchPad_2 in AQ_GlobalMicroprocessorScratchPad_HHD */ +#define bits_AQ_GlobalMicroprocessorScratchPad_HHD_scratchPad_2 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure scratchPad_2 in AQ_GlobalMicroprocessorScratchPad_HHD */ +#define word_AQ_GlobalMicroprocessorScratchPad_HHD_scratchPad_2 u1.word_1 + +/*! \brief Base register address of structure AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_baseRegisterAddress 0x5002 +/*! \brief MMD address of structure AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressEthertypeExplicitSectagLsb in AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mssEgressEthertypeExplicitSectagLsb 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressEthertypeExplicitSectagLsb in AQ_MssEgressControlRegister_HHD */ +#define bits_AQ_MssEgressControlRegister_HHD_mssEgressEthertypeExplicitSectagLsb u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressEthertypeExplicitSectagLsb in AQ_MssEgressControlRegister_HHD */ +#define word_AQ_MssEgressControlRegister_HHD_mssEgressEthertypeExplicitSectagLsb u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressClearGlobalTime in AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mssEgressClearGlobalTime 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressClearGlobalTime in AQ_MssEgressControlRegister_HHD */ +#define bits_AQ_MssEgressControlRegister_HHD_mssEgressClearGlobalTime u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressClearGlobalTime in AQ_MssEgressControlRegister_HHD */ +#define word_AQ_MssEgressControlRegister_HHD_mssEgressClearGlobalTime u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressClearCounter in AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mssEgressClearCounter 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressClearCounter in AQ_MssEgressControlRegister_HHD */ +#define bits_AQ_MssEgressControlRegister_HHD_mssEgressClearCounter u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressClearCounter in AQ_MssEgressControlRegister_HHD */ +#define word_AQ_MssEgressControlRegister_HHD_mssEgressClearCounter u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressHighPriority in AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mssEgressHighPriority 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressHighPriority in AQ_MssEgressControlRegister_HHD */ +#define bits_AQ_MssEgressControlRegister_HHD_mssEgressHighPriority u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressHighPriority in AQ_MssEgressControlRegister_HHD */ +#define word_AQ_MssEgressControlRegister_HHD_mssEgressHighPriority u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressIcvLsb_8BytesEnable in AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mssEgressIcvLsb_8BytesEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressIcvLsb_8BytesEnable in AQ_MssEgressControlRegister_HHD */ +#define bits_AQ_MssEgressControlRegister_HHD_mssEgressIcvLsb_8BytesEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressIcvLsb_8BytesEnable in AQ_MssEgressControlRegister_HHD */ +#define word_AQ_MssEgressControlRegister_HHD_mssEgressIcvLsb_8BytesEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressExternalClassificationEnable in AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mssEgressExternalClassificationEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressExternalClassificationEnable in AQ_MssEgressControlRegister_HHD */ +#define bits_AQ_MssEgressControlRegister_HHD_mssEgressExternalClassificationEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressExternalClassificationEnable in AQ_MssEgressControlRegister_HHD */ +#define word_AQ_MssEgressControlRegister_HHD_mssEgressExternalClassificationEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressExplicitSectagReportShortLength in AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mssEgressExplicitSectagReportShortLength 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressExplicitSectagReportShortLength in AQ_MssEgressControlRegister_HHD */ +#define bits_AQ_MssEgressControlRegister_HHD_mssEgressExplicitSectagReportShortLength u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressExplicitSectagReportShortLength in AQ_MssEgressControlRegister_HHD */ +#define word_AQ_MssEgressControlRegister_HHD_mssEgressExplicitSectagReportShortLength u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressDropInvalidSa_scPackets in AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mssEgressDropInvalidSa_scPackets 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressDropInvalidSa_scPackets in AQ_MssEgressControlRegister_HHD */ +#define bits_AQ_MssEgressControlRegister_HHD_mssEgressDropInvalidSa_scPackets u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressDropInvalidSa_scPackets in AQ_MssEgressControlRegister_HHD */ +#define word_AQ_MssEgressControlRegister_HHD_mssEgressDropInvalidSa_scPackets u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressUnmatchedUseSc_0 in AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mssEgressUnmatchedUseSc_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressUnmatchedUseSc_0 in AQ_MssEgressControlRegister_HHD */ +#define bits_AQ_MssEgressControlRegister_HHD_mssEgressUnmatchedUseSc_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressUnmatchedUseSc_0 in AQ_MssEgressControlRegister_HHD */ +#define word_AQ_MssEgressControlRegister_HHD_mssEgressUnmatchedUseSc_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgresssGcmTestMode in AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mssEgresssGcmTestMode 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgresssGcmTestMode in AQ_MssEgressControlRegister_HHD */ +#define bits_AQ_MssEgressControlRegister_HHD_mssEgresssGcmTestMode u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgresssGcmTestMode in AQ_MssEgressControlRegister_HHD */ +#define word_AQ_MssEgressControlRegister_HHD_mssEgresssGcmTestMode u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressGcmStart in AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mssEgressGcmStart 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressGcmStart in AQ_MssEgressControlRegister_HHD */ +#define bits_AQ_MssEgressControlRegister_HHD_mssEgressGcmStart u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressGcmStart in AQ_MssEgressControlRegister_HHD */ +#define word_AQ_MssEgressControlRegister_HHD_mssEgressGcmStart u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressDropEgprcLutMiss in AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mssEgressDropEgprcLutMiss 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressDropEgprcLutMiss in AQ_MssEgressControlRegister_HHD */ +#define bits_AQ_MssEgressControlRegister_HHD_mssEgressDropEgprcLutMiss u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressDropEgprcLutMiss in AQ_MssEgressControlRegister_HHD */ +#define word_AQ_MssEgressControlRegister_HHD_mssEgressDropEgprcLutMiss u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressDropKayPacket in AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mssEgressDropKayPacket 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressDropKayPacket in AQ_MssEgressControlRegister_HHD */ +#define bits_AQ_MssEgressControlRegister_HHD_mssEgressDropKayPacket u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressDropKayPacket in AQ_MssEgressControlRegister_HHD */ +#define word_AQ_MssEgressControlRegister_HHD_mssEgressDropKayPacket u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSoftReset in AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mssEgressSoftReset 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSoftReset in AQ_MssEgressControlRegister_HHD */ +#define bits_AQ_MssEgressControlRegister_HHD_mssEgressSoftReset u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSoftReset in AQ_MssEgressControlRegister_HHD */ +#define word_AQ_MssEgressControlRegister_HHD_mssEgressSoftReset u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressEthertypeExplicitSectagMsb in AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mssEgressEthertypeExplicitSectagMsb 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressEthertypeExplicitSectagMsb in AQ_MssEgressControlRegister_HHD */ +#define bits_AQ_MssEgressControlRegister_HHD_mssEgressEthertypeExplicitSectagMsb u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressEthertypeExplicitSectagMsb in AQ_MssEgressControlRegister_HHD */ +#define word_AQ_MssEgressControlRegister_HHD_mssEgressEthertypeExplicitSectagMsb u1.word_1 + +/*! \brief Base register address of structure AQ_MssEgressVlanTpid_0Register_HHD */ +#define AQ_MssEgressVlanTpid_0Register_HHD_baseRegisterAddress 0x5008 +/*! \brief MMD address of structure AQ_MssEgressVlanTpid_0Register_HHD */ +#define AQ_MssEgressVlanTpid_0Register_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressVlanStagTpid in AQ_MssEgressVlanTpid_0Register_HHD */ +#define AQ_MssEgressVlanTpid_0Register_HHD_mssEgressVlanStagTpid 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressVlanStagTpid in AQ_MssEgressVlanTpid_0Register_HHD */ +#define bits_AQ_MssEgressVlanTpid_0Register_HHD_mssEgressVlanStagTpid u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressVlanStagTpid in AQ_MssEgressVlanTpid_0Register_HHD */ +#define word_AQ_MssEgressVlanTpid_0Register_HHD_mssEgressVlanStagTpid u0.word_0 + +/*! \brief Base register address of structure AQ_MssEgressVlanTpid_1Register_HHD */ +#define AQ_MssEgressVlanTpid_1Register_HHD_baseRegisterAddress 0x500A +/*! \brief MMD address of structure AQ_MssEgressVlanTpid_1Register_HHD */ +#define AQ_MssEgressVlanTpid_1Register_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressVlanQtagTpid in AQ_MssEgressVlanTpid_1Register_HHD */ +#define AQ_MssEgressVlanTpid_1Register_HHD_mssEgressVlanQtagTpid 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressVlanQtagTpid in AQ_MssEgressVlanTpid_1Register_HHD */ +#define bits_AQ_MssEgressVlanTpid_1Register_HHD_mssEgressVlanQtagTpid u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressVlanQtagTpid in AQ_MssEgressVlanTpid_1Register_HHD */ +#define word_AQ_MssEgressVlanTpid_1Register_HHD_mssEgressVlanQtagTpid u0.word_0 + +/*! \brief Base register address of structure AQ_MssEgressVlanControlRegister_HHD */ +#define AQ_MssEgressVlanControlRegister_HHD_baseRegisterAddress 0x500C +/*! \brief MMD address of structure AQ_MssEgressVlanControlRegister_HHD */ +#define AQ_MssEgressVlanControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressVlanUpMapTable in AQ_MssEgressVlanControlRegister_HHD */ +#define AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanUpMapTable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressVlanUpMapTable in AQ_MssEgressVlanControlRegister_HHD */ +#define bits_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanUpMapTable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressVlanUpMapTable in AQ_MssEgressVlanControlRegister_HHD */ +#define word_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanUpMapTable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressVlanQtagParseEnable in AQ_MssEgressVlanControlRegister_HHD */ +#define AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanQtagParseEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressVlanQtagParseEnable in AQ_MssEgressVlanControlRegister_HHD */ +#define bits_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanQtagParseEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressVlanQtagParseEnable in AQ_MssEgressVlanControlRegister_HHD */ +#define word_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanQtagParseEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressVlanStagParseEnable in AQ_MssEgressVlanControlRegister_HHD */ +#define AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanStagParseEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressVlanStagParseEnable in AQ_MssEgressVlanControlRegister_HHD */ +#define bits_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanStagParseEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressVlanStagParseEnable in AQ_MssEgressVlanControlRegister_HHD */ +#define word_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanStagParseEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressVlanQinqParseEnable in AQ_MssEgressVlanControlRegister_HHD */ +#define AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanQinqParseEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressVlanQinqParseEnable in AQ_MssEgressVlanControlRegister_HHD */ +#define bits_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanQinqParseEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressVlanQinqParseEnable in AQ_MssEgressVlanControlRegister_HHD */ +#define word_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanQinqParseEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressVlanQtagUpParseEnable in AQ_MssEgressVlanControlRegister_HHD */ +#define AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanQtagUpParseEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressVlanQtagUpParseEnable in AQ_MssEgressVlanControlRegister_HHD */ +#define bits_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanQtagUpParseEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressVlanQtagUpParseEnable in AQ_MssEgressVlanControlRegister_HHD */ +#define word_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanQtagUpParseEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressVlanStagUpParseEnable in AQ_MssEgressVlanControlRegister_HHD */ +#define AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanStagUpParseEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressVlanStagUpParseEnable in AQ_MssEgressVlanControlRegister_HHD */ +#define bits_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanStagUpParseEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressVlanStagUpParseEnable in AQ_MssEgressVlanControlRegister_HHD */ +#define word_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanStagUpParseEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressVlanUpDefault in AQ_MssEgressVlanControlRegister_HHD */ +#define AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanUpDefault 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressVlanUpDefault in AQ_MssEgressVlanControlRegister_HHD */ +#define bits_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanUpDefault u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressVlanUpDefault in AQ_MssEgressVlanControlRegister_HHD */ +#define word_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanUpDefault u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressVlanUpMapTableMSW in AQ_MssEgressVlanControlRegister_HHD */ +#define AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanUpMapTableMSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressVlanUpMapTableMSW in AQ_MssEgressVlanControlRegister_HHD */ +#define bits_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanUpMapTableMSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressVlanUpMapTableMSW in AQ_MssEgressVlanControlRegister_HHD */ +#define word_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanUpMapTableMSW u1.word_1 + +/*! \brief Base register address of structure AQ_MssEgressPnControlRegister_HHD */ +#define AQ_MssEgressPnControlRegister_HHD_baseRegisterAddress 0x500E +/*! \brief MMD address of structure AQ_MssEgressPnControlRegister_HHD */ +#define AQ_MssEgressPnControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaPnThresholdLSW in AQ_MssEgressPnControlRegister_HHD */ +#define AQ_MssEgressPnControlRegister_HHD_mssEgressSaPnThresholdLSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaPnThresholdLSW in AQ_MssEgressPnControlRegister_HHD */ +#define bits_AQ_MssEgressPnControlRegister_HHD_mssEgressSaPnThresholdLSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaPnThresholdLSW in AQ_MssEgressPnControlRegister_HHD */ +#define word_AQ_MssEgressPnControlRegister_HHD_mssEgressSaPnThresholdLSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaPnThresholdMSW in AQ_MssEgressPnControlRegister_HHD */ +#define AQ_MssEgressPnControlRegister_HHD_mssEgressSaPnThresholdMSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaPnThresholdMSW in AQ_MssEgressPnControlRegister_HHD */ +#define bits_AQ_MssEgressPnControlRegister_HHD_mssEgressSaPnThresholdMSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaPnThresholdMSW in AQ_MssEgressPnControlRegister_HHD */ +#define word_AQ_MssEgressPnControlRegister_HHD_mssEgressSaPnThresholdMSW u1.word_1 + +/*! \brief Base register address of structure AQ_MssEgressMtuSizeControlRegister_HHD */ +#define AQ_MssEgressMtuSizeControlRegister_HHD_baseRegisterAddress 0x5010 +/*! \brief MMD address of structure AQ_MssEgressMtuSizeControlRegister_HHD */ +#define AQ_MssEgressMtuSizeControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressControlledPacketMtuSize in AQ_MssEgressMtuSizeControlRegister_HHD */ +#define AQ_MssEgressMtuSizeControlRegister_HHD_mssEgressControlledPacketMtuSize 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressControlledPacketMtuSize in AQ_MssEgressMtuSizeControlRegister_HHD */ +#define bits_AQ_MssEgressMtuSizeControlRegister_HHD_mssEgressControlledPacketMtuSize u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressControlledPacketMtuSize in AQ_MssEgressMtuSizeControlRegister_HHD */ +#define word_AQ_MssEgressMtuSizeControlRegister_HHD_mssEgressControlledPacketMtuSize u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressUncontrolledPacketMtuSize in AQ_MssEgressMtuSizeControlRegister_HHD */ +#define AQ_MssEgressMtuSizeControlRegister_HHD_mssEgressUncontrolledPacketMtuSize 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressUncontrolledPacketMtuSize in AQ_MssEgressMtuSizeControlRegister_HHD */ +#define bits_AQ_MssEgressMtuSizeControlRegister_HHD_mssEgressUncontrolledPacketMtuSize u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressUncontrolledPacketMtuSize in AQ_MssEgressMtuSizeControlRegister_HHD */ +#define word_AQ_MssEgressMtuSizeControlRegister_HHD_mssEgressUncontrolledPacketMtuSize u1.word_1 + +/*! \brief Base register address of structure AQ_MssEgressInterruptStatusRegister_HHD */ +#define AQ_MssEgressInterruptStatusRegister_HHD_baseRegisterAddress 0x505C +/*! \brief MMD address of structure AQ_MssEgressInterruptStatusRegister_HHD */ +#define AQ_MssEgressInterruptStatusRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressEccErrorInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ +#define AQ_MssEgressInterruptStatusRegister_HHD_mssEgressEccErrorInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressEccErrorInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ +#define bits_AQ_MssEgressInterruptStatusRegister_HHD_mssEgressEccErrorInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressEccErrorInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ +#define word_AQ_MssEgressInterruptStatusRegister_HHD_mssEgressEccErrorInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressMibSaturationInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ +#define AQ_MssEgressInterruptStatusRegister_HHD_mssEgressMibSaturationInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressMibSaturationInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ +#define bits_AQ_MssEgressInterruptStatusRegister_HHD_mssEgressMibSaturationInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressMibSaturationInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ +#define word_AQ_MssEgressInterruptStatusRegister_HHD_mssEgressMibSaturationInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaThresholdExpiredInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ +#define AQ_MssEgressInterruptStatusRegister_HHD_mssEgressSaThresholdExpiredInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaThresholdExpiredInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ +#define bits_AQ_MssEgressInterruptStatusRegister_HHD_mssEgressSaThresholdExpiredInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaThresholdExpiredInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ +#define word_AQ_MssEgressInterruptStatusRegister_HHD_mssEgressSaThresholdExpiredInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaExpiredInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ +#define AQ_MssEgressInterruptStatusRegister_HHD_mssEgressSaExpiredInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaExpiredInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ +#define bits_AQ_MssEgressInterruptStatusRegister_HHD_mssEgressSaExpiredInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaExpiredInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ +#define word_AQ_MssEgressInterruptStatusRegister_HHD_mssEgressSaExpiredInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressMasterInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ +#define AQ_MssEgressInterruptStatusRegister_HHD_mssEgressMasterInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressMasterInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ +#define bits_AQ_MssEgressInterruptStatusRegister_HHD_mssEgressMasterInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressMasterInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ +#define word_AQ_MssEgressInterruptStatusRegister_HHD_mssEgressMasterInterrupt u0.word_0 + +/*! \brief Base register address of structure AQ_MssEgressInterruptMaskRegister_HHD */ +#define AQ_MssEgressInterruptMaskRegister_HHD_baseRegisterAddress 0x505E +/*! \brief MMD address of structure AQ_MssEgressInterruptMaskRegister_HHD */ +#define AQ_MssEgressInterruptMaskRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressEccErrorInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ +#define AQ_MssEgressInterruptMaskRegister_HHD_mssEgressEccErrorInterruptEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressEccErrorInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ +#define bits_AQ_MssEgressInterruptMaskRegister_HHD_mssEgressEccErrorInterruptEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressEccErrorInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ +#define word_AQ_MssEgressInterruptMaskRegister_HHD_mssEgressEccErrorInterruptEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressMibSaturationInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ +#define AQ_MssEgressInterruptMaskRegister_HHD_mssEgressMibSaturationInterruptEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressMibSaturationInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ +#define bits_AQ_MssEgressInterruptMaskRegister_HHD_mssEgressMibSaturationInterruptEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressMibSaturationInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ +#define word_AQ_MssEgressInterruptMaskRegister_HHD_mssEgressMibSaturationInterruptEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaExpiredThresholdInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ +#define AQ_MssEgressInterruptMaskRegister_HHD_mssEgressSaExpiredThresholdInterruptEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaExpiredThresholdInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ +#define bits_AQ_MssEgressInterruptMaskRegister_HHD_mssEgressSaExpiredThresholdInterruptEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaExpiredThresholdInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ +#define word_AQ_MssEgressInterruptMaskRegister_HHD_mssEgressSaExpiredThresholdInterruptEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaExpiredInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ +#define AQ_MssEgressInterruptMaskRegister_HHD_mssEgressSaExpiredInterruptEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaExpiredInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ +#define bits_AQ_MssEgressInterruptMaskRegister_HHD_mssEgressSaExpiredInterruptEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaExpiredInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ +#define word_AQ_MssEgressInterruptMaskRegister_HHD_mssEgressSaExpiredInterruptEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressMasterInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ +#define AQ_MssEgressInterruptMaskRegister_HHD_mssEgressMasterInterruptEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressMasterInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ +#define bits_AQ_MssEgressInterruptMaskRegister_HHD_mssEgressMasterInterruptEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressMasterInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ +#define word_AQ_MssEgressInterruptMaskRegister_HHD_mssEgressMasterInterruptEnable u0.word_0 + +/*! \brief Base register address of structure AQ_MssEgressSaExpiredStatusRegister_HHD */ +#define AQ_MssEgressSaExpiredStatusRegister_HHD_baseRegisterAddress 0x5060 +/*! \brief MMD address of structure AQ_MssEgressSaExpiredStatusRegister_HHD */ +#define AQ_MssEgressSaExpiredStatusRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaExpiredLSW in AQ_MssEgressSaExpiredStatusRegister_HHD */ +#define AQ_MssEgressSaExpiredStatusRegister_HHD_mssEgressSaExpiredLSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaExpiredLSW in AQ_MssEgressSaExpiredStatusRegister_HHD */ +#define bits_AQ_MssEgressSaExpiredStatusRegister_HHD_mssEgressSaExpiredLSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaExpiredLSW in AQ_MssEgressSaExpiredStatusRegister_HHD */ +#define word_AQ_MssEgressSaExpiredStatusRegister_HHD_mssEgressSaExpiredLSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaExpiredMSW in AQ_MssEgressSaExpiredStatusRegister_HHD */ +#define AQ_MssEgressSaExpiredStatusRegister_HHD_mssEgressSaExpiredMSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaExpiredMSW in AQ_MssEgressSaExpiredStatusRegister_HHD */ +#define bits_AQ_MssEgressSaExpiredStatusRegister_HHD_mssEgressSaExpiredMSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaExpiredMSW in AQ_MssEgressSaExpiredStatusRegister_HHD */ +#define word_AQ_MssEgressSaExpiredStatusRegister_HHD_mssEgressSaExpiredMSW u1.word_1 + +/*! \brief Base register address of structure AQ_MssEgressSaThresholdExpiredStatusRegister_HHD */ +#define AQ_MssEgressSaThresholdExpiredStatusRegister_HHD_baseRegisterAddress 0x5062 +/*! \brief MMD address of structure AQ_MssEgressSaThresholdExpiredStatusRegister_HHD */ +#define AQ_MssEgressSaThresholdExpiredStatusRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaThresholdExpiredLSW in AQ_MssEgressSaThresholdExpiredStatusRegister_HHD */ +#define AQ_MssEgressSaThresholdExpiredStatusRegister_HHD_mssEgressSaThresholdExpiredLSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaThresholdExpiredLSW in AQ_MssEgressSaThresholdExpiredStatusRegister_HHD */ +#define bits_AQ_MssEgressSaThresholdExpiredStatusRegister_HHD_mssEgressSaThresholdExpiredLSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaThresholdExpiredLSW in AQ_MssEgressSaThresholdExpiredStatusRegister_HHD */ +#define word_AQ_MssEgressSaThresholdExpiredStatusRegister_HHD_mssEgressSaThresholdExpiredLSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaThresholdExpiredMSW in AQ_MssEgressSaThresholdExpiredStatusRegister_HHD */ +#define AQ_MssEgressSaThresholdExpiredStatusRegister_HHD_mssEgressSaThresholdExpiredMSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaThresholdExpiredMSW in AQ_MssEgressSaThresholdExpiredStatusRegister_HHD */ +#define bits_AQ_MssEgressSaThresholdExpiredStatusRegister_HHD_mssEgressSaThresholdExpiredMSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaThresholdExpiredMSW in AQ_MssEgressSaThresholdExpiredStatusRegister_HHD */ +#define word_AQ_MssEgressSaThresholdExpiredStatusRegister_HHD_mssEgressSaThresholdExpiredMSW u1.word_1 + +/*! \brief Base register address of structure AQ_MssEgressEccInterruptStatusRegister_HHD */ +#define AQ_MssEgressEccInterruptStatusRegister_HHD_baseRegisterAddress 0x5064 +/*! \brief MMD address of structure AQ_MssEgressEccInterruptStatusRegister_HHD */ +#define AQ_MssEgressEccInterruptStatusRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaEccErrorInterruptLSW in AQ_MssEgressEccInterruptStatusRegister_HHD */ +#define AQ_MssEgressEccInterruptStatusRegister_HHD_mssEgressSaEccErrorInterruptLSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaEccErrorInterruptLSW in AQ_MssEgressEccInterruptStatusRegister_HHD */ +#define bits_AQ_MssEgressEccInterruptStatusRegister_HHD_mssEgressSaEccErrorInterruptLSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaEccErrorInterruptLSW in AQ_MssEgressEccInterruptStatusRegister_HHD */ +#define word_AQ_MssEgressEccInterruptStatusRegister_HHD_mssEgressSaEccErrorInterruptLSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaEccErrorInterruptMSW in AQ_MssEgressEccInterruptStatusRegister_HHD */ +#define AQ_MssEgressEccInterruptStatusRegister_HHD_mssEgressSaEccErrorInterruptMSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaEccErrorInterruptMSW in AQ_MssEgressEccInterruptStatusRegister_HHD */ +#define bits_AQ_MssEgressEccInterruptStatusRegister_HHD_mssEgressSaEccErrorInterruptMSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaEccErrorInterruptMSW in AQ_MssEgressEccInterruptStatusRegister_HHD */ +#define word_AQ_MssEgressEccInterruptStatusRegister_HHD_mssEgressSaEccErrorInterruptMSW u1.word_1 + +/*! \brief Base register address of structure AQ_MssEgressLutAddressControlRegister_HHD */ +#define AQ_MssEgressLutAddressControlRegister_HHD_baseRegisterAddress 0x5080 +/*! \brief MMD address of structure AQ_MssEgressLutAddressControlRegister_HHD */ +#define AQ_MssEgressLutAddressControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutSelect in AQ_MssEgressLutAddressControlRegister_HHD */ +#define AQ_MssEgressLutAddressControlRegister_HHD_mssEgressLutSelect 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutSelect in AQ_MssEgressLutAddressControlRegister_HHD */ +#define bits_AQ_MssEgressLutAddressControlRegister_HHD_mssEgressLutSelect u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutSelect in AQ_MssEgressLutAddressControlRegister_HHD */ +#define word_AQ_MssEgressLutAddressControlRegister_HHD_mssEgressLutSelect u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutAddress in AQ_MssEgressLutAddressControlRegister_HHD */ +#define AQ_MssEgressLutAddressControlRegister_HHD_mssEgressLutAddress 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutAddress in AQ_MssEgressLutAddressControlRegister_HHD */ +#define bits_AQ_MssEgressLutAddressControlRegister_HHD_mssEgressLutAddress u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutAddress in AQ_MssEgressLutAddressControlRegister_HHD */ +#define word_AQ_MssEgressLutAddressControlRegister_HHD_mssEgressLutAddress u0.word_0 + +/*! \brief Base register address of structure AQ_MssEgressLutControlRegister_HHD */ +#define AQ_MssEgressLutControlRegister_HHD_baseRegisterAddress 0x5081 +/*! \brief MMD address of structure AQ_MssEgressLutControlRegister_HHD */ +#define AQ_MssEgressLutControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutWrite in AQ_MssEgressLutControlRegister_HHD */ +#define AQ_MssEgressLutControlRegister_HHD_mssEgressLutWrite 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutWrite in AQ_MssEgressLutControlRegister_HHD */ +#define bits_AQ_MssEgressLutControlRegister_HHD_mssEgressLutWrite u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutWrite in AQ_MssEgressLutControlRegister_HHD */ +#define word_AQ_MssEgressLutControlRegister_HHD_mssEgressLutWrite u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutRead in AQ_MssEgressLutControlRegister_HHD */ +#define AQ_MssEgressLutControlRegister_HHD_mssEgressLutRead 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutRead in AQ_MssEgressLutControlRegister_HHD */ +#define bits_AQ_MssEgressLutControlRegister_HHD_mssEgressLutRead u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutRead in AQ_MssEgressLutControlRegister_HHD */ +#define word_AQ_MssEgressLutControlRegister_HHD_mssEgressLutRead u0.word_0 + +/*! \brief Base register address of structure AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_baseRegisterAddress 0x50A0 +/*! \brief MMD address of structure AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_0 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_0 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_0 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_1 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_1 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_1 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_1 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_2 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_2 2 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_2 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_2 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_2 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_2 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_3 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_3 3 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_3 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_3 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_3 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_3 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_4 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_4 4 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_4 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_4 u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_4 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_4 u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_5 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_5 5 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_5 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_5 u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_5 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_5 u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_6 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_6 6 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_6 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_6 u6.bits_6 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_6 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_6 u6.word_6 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_7 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_7 7 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_7 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_7 u7.bits_7 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_7 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_7 u7.word_7 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_8 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_8 8 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_8 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_8 u8.bits_8 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_8 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_8 u8.word_8 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_9 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_9 9 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_9 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_9 u9.bits_9 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_9 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_9 u9.word_9 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_10 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_10 10 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_10 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_10 u10.bits_10 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_10 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_10 u10.word_10 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_11 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_11 11 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_11 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_11 u11.bits_11 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_11 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_11 u11.word_11 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_12 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_12 12 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_12 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_12 u12.bits_12 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_12 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_12 u12.word_12 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_13 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_13 13 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_13 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_13 u13.bits_13 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_13 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_13 u13.word_13 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_14 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_14 14 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_14 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_14 u14.bits_14 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_14 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_14 u14.word_14 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_15 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_15 15 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_15 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_15 u15.bits_15 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_15 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_15 u15.word_15 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_16 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_16 16 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_16 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_16 u16.bits_16 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_16 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_16 u16.word_16 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_17 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_17 17 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_17 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_17 u17.bits_17 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_17 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_17 u17.word_17 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_18 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_18 18 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_18 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_18 u18.bits_18 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_18 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_18 u18.word_18 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_19 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_19 19 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_19 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_19 u19.bits_19 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_19 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_19 u19.word_19 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_20 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_20 20 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_20 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_20 u20.bits_20 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_20 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_20 u20.word_20 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_21 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_21 21 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_21 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_21 u21.bits_21 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_21 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_21 u21.word_21 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_22 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_22 22 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_22 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_22 u22.bits_22 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_22 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_22 u22.word_22 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_23 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_23 23 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_23 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_23 u23.bits_23 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_23 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_23 u23.word_23 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_24 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_24 24 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_24 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_24 u24.bits_24 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_24 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_24 u24.word_24 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_25 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_25 25 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_25 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_25 u25.bits_25 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_25 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_25 u25.word_25 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_26 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_26 26 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_26 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_26 u26.bits_26 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_26 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_26 u26.word_26 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_27 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_27 27 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_27 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_27 u27.bits_27 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_27 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_27 u27.word_27 + +/*! \brief Base register address of structure AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_baseRegisterAddress 0x6004 +/*! \brief MMD address of structure AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemPhyTxEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPhyTxEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemPhyTxEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPhyTxEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemPhyTxEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPhyTxEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxErrorDiscard in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemRxErrorDiscard 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxErrorDiscard in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemRxErrorDiscard u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxErrorDiscard in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemRxErrorDiscard u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemControlFrameEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemControlFrameEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemControlFrameEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemControlFrameEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemControlFrameEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemControlFrameEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemSoftReset in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemSoftReset 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemSoftReset in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemSoftReset u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemSoftReset in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemSoftReset u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxPadEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxPadEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxPadEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxPadEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxPadEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxPadEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxCrcAppend in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxCrcAppend 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxCrcAppend in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxCrcAppend u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxCrcAppend in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxCrcAppend u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxAddressInsertEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxAddressInsertEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxAddressInsertEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxAddressInsertEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxAddressInsertEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxAddressInsertEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemPauseIgnore in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPauseIgnore 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemPauseIgnore in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPauseIgnore u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemPauseIgnore in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPauseIgnore u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemPauseForward in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPauseForward 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemPauseForward in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPauseForward u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemPauseForward in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPauseForward u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemCrcForward in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemCrcForward 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemCrcForward in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemCrcForward u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemCrcForward in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemCrcForward u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemPadEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPadEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemPadEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPadEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemPadEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPadEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemPromiscuousMode in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPromiscuousMode 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemPromiscuousMode in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPromiscuousMode u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemPromiscuousMode in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPromiscuousMode u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemWanMode in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemWanMode 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemWanMode in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemWanMode u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemWanMode in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemWanMode u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemRxEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemRxEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemRxEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxLowPowerIdleEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxLowPowerIdleEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxLowPowerIdleEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxLowPowerIdleEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxLowPowerIdleEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxLowPowerIdleEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemSfdCheckDisable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemSfdCheckDisable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemSfdCheckDisable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemSfdCheckDisable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemSfdCheckDisable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemSfdCheckDisable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemPriorityFlowControlEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPriorityFlowControlEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemPriorityFlowControlEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPriorityFlowControlEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemPriorityFlowControlEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPriorityFlowControlEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemIdleColumnCountExtend in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemIdleColumnCountExtend 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemIdleColumnCountExtend in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemIdleColumnCountExtend u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemIdleColumnCountExtend in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemIdleColumnCountExtend u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemLengthCheckDisable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemLengthCheckDisable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemLengthCheckDisable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemLengthCheckDisable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemLengthCheckDisable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemLengthCheckDisable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemForceSendIdle in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemForceSendIdle 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemForceSendIdle in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemForceSendIdle u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemForceSendIdle in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemForceSendIdle u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemFifoControlRegister_HHD */ +#define AQ_MsmSystemFifoControlRegister_HHD_baseRegisterAddress 0x600E +/*! \brief MMD address of structure AQ_MsmSystemFifoControlRegister_HHD */ +#define AQ_MsmSystemFifoControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxFifoFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoFullThreshold 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxFifoFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define bits_AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoFullThreshold u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxFifoFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define word_AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoFullThreshold u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxFifoEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoEmptyThreshold 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxFifoEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define bits_AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoEmptyThreshold u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxFifoEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define word_AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoEmptyThreshold u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxFifoFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoFullThreshold 2 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxFifoFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define bits_AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoFullThreshold u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxFifoFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define word_AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoFullThreshold u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxFifoEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoEmptyThreshold 3 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxFifoEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define bits_AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoEmptyThreshold u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxFifoEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define word_AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoEmptyThreshold u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxFifoAlmostFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoAlmostFullThreshold 4 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxFifoAlmostFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define bits_AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoAlmostFullThreshold u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxFifoAlmostFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define word_AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoAlmostFullThreshold u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxFifoAlmostEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoAlmostEmptyThreshold 5 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxFifoAlmostEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define bits_AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoAlmostEmptyThreshold u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxFifoAlmostEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define word_AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoAlmostEmptyThreshold u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxFifoAlmostFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoAlmostFullThreshold 6 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxFifoAlmostFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define bits_AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoAlmostFullThreshold u6.bits_6 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxFifoAlmostFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define word_AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoAlmostFullThreshold u6.word_6 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxFifoAlmostEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoAlmostEmptyThreshold 7 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxFifoAlmostEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define bits_AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoAlmostEmptyThreshold u7.bits_7 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxFifoAlmostEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define word_AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoAlmostEmptyThreshold u7.word_7 + +/*! \brief Base register address of structure AQ_MsmSystemGeneralStatusRegister_HHD */ +#define AQ_MsmSystemGeneralStatusRegister_HHD_baseRegisterAddress 0x6020 +/*! \brief MMD address of structure AQ_MsmSystemGeneralStatusRegister_HHD */ +#define AQ_MsmSystemGeneralStatusRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxFifoEmpty in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemTxFifoEmpty 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxFifoEmpty in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define bits_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemTxFifoEmpty u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxFifoEmpty in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define word_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemTxFifoEmpty u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxLowPowerIdle in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemRxLowPowerIdle 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxLowPowerIdle in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define bits_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemRxLowPowerIdle u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxLowPowerIdle in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define word_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemRxLowPowerIdle u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTimestampAvailable in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemTimestampAvailable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTimestampAvailable in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define bits_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemTimestampAvailable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTimestampAvailable in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define word_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemTimestampAvailable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemPhyLossOfSignal in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemPhyLossOfSignal 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemPhyLossOfSignal in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define bits_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemPhyLossOfSignal u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemPhyLossOfSignal in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define word_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemPhyLossOfSignal u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxRemoteFault in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemRxRemoteFault 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxRemoteFault in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define bits_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemRxRemoteFault u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxRemoteFault in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define word_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemRxRemoteFault u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxLocalFault in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemRxLocalFault 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxLocalFault in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define bits_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemRxLocalFault u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxLocalFault in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define word_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemRxLocalFault u0.word_0 + +/*! \brief Base register address of structure AQ_MsmSystemTxIpgControlRegister_HHD */ +#define AQ_MsmSystemTxIpgControlRegister_HHD_baseRegisterAddress 0x6022 +/*! \brief MMD address of structure AQ_MsmSystemTxIpgControlRegister_HHD */ +#define AQ_MsmSystemTxIpgControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxIpgLength in AQ_MsmSystemTxIpgControlRegister_HHD */ +#define AQ_MsmSystemTxIpgControlRegister_HHD_msmSystemTxIpgLength 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxIpgLength in AQ_MsmSystemTxIpgControlRegister_HHD */ +#define bits_AQ_MsmSystemTxIpgControlRegister_HHD_msmSystemTxIpgLength u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxIpgLength in AQ_MsmSystemTxIpgControlRegister_HHD */ +#define word_AQ_MsmSystemTxIpgControlRegister_HHD_msmSystemTxIpgLength u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxIpgReserved in AQ_MsmSystemTxIpgControlRegister_HHD */ +#define AQ_MsmSystemTxIpgControlRegister_HHD_msmSystemTxIpgReserved 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxIpgReserved in AQ_MsmSystemTxIpgControlRegister_HHD */ +#define bits_AQ_MsmSystemTxIpgControlRegister_HHD_msmSystemTxIpgReserved u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxIpgReserved in AQ_MsmSystemTxIpgControlRegister_HHD */ +#define word_AQ_MsmSystemTxIpgControlRegister_HHD_msmSystemTxIpgReserved u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemTxGoodFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxGoodFramesCounterRegister_HHD_baseRegisterAddress 0x6040 +/*! \brief MMD address of structure AQ_MsmSystemTxGoodFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxGoodFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxGoodFramesCounter_0 in AQ_MsmSystemTxGoodFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxGoodFramesCounterRegister_HHD_msmSystemTxGoodFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxGoodFramesCounter_0 in AQ_MsmSystemTxGoodFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxGoodFramesCounterRegister_HHD_msmSystemTxGoodFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxGoodFramesCounter_0 in AQ_MsmSystemTxGoodFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemTxGoodFramesCounterRegister_HHD_msmSystemTxGoodFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxGoodFramesCounter_1 in AQ_MsmSystemTxGoodFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxGoodFramesCounterRegister_HHD_msmSystemTxGoodFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxGoodFramesCounter_1 in AQ_MsmSystemTxGoodFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxGoodFramesCounterRegister_HHD_msmSystemTxGoodFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxGoodFramesCounter_1 in AQ_MsmSystemTxGoodFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemTxGoodFramesCounterRegister_HHD_msmSystemTxGoodFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemRxGoodFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxGoodFramesCounterRegister_HHD_baseRegisterAddress 0x6044 +/*! \brief MMD address of structure AQ_MsmSystemRxGoodFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxGoodFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxGoodFramesCounter_0 in AQ_MsmSystemRxGoodFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxGoodFramesCounterRegister_HHD_msmSystemRxGoodFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxGoodFramesCounter_0 in AQ_MsmSystemRxGoodFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxGoodFramesCounterRegister_HHD_msmSystemRxGoodFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxGoodFramesCounter_0 in AQ_MsmSystemRxGoodFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemRxGoodFramesCounterRegister_HHD_msmSystemRxGoodFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxGoodFramesCounter_1 in AQ_MsmSystemRxGoodFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxGoodFramesCounterRegister_HHD_msmSystemRxGoodFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxGoodFramesCounter_1 in AQ_MsmSystemRxGoodFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxGoodFramesCounterRegister_HHD_msmSystemRxGoodFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxGoodFramesCounter_1 in AQ_MsmSystemRxGoodFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemRxGoodFramesCounterRegister_HHD_msmSystemRxGoodFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemRxFcsErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxFcsErrorsCounterRegister_HHD_baseRegisterAddress 0x6048 +/*! \brief MMD address of structure AQ_MsmSystemRxFcsErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxFcsErrorsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemFcsErrorCounter_0 in AQ_MsmSystemRxFcsErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxFcsErrorsCounterRegister_HHD_msmSystemFcsErrorCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemFcsErrorCounter_0 in AQ_MsmSystemRxFcsErrorsCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxFcsErrorsCounterRegister_HHD_msmSystemFcsErrorCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemFcsErrorCounter_0 in AQ_MsmSystemRxFcsErrorsCounterRegister_HHD */ +#define word_AQ_MsmSystemRxFcsErrorsCounterRegister_HHD_msmSystemFcsErrorCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemFcsErrorCounter_1 in AQ_MsmSystemRxFcsErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxFcsErrorsCounterRegister_HHD_msmSystemFcsErrorCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemFcsErrorCounter_1 in AQ_MsmSystemRxFcsErrorsCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxFcsErrorsCounterRegister_HHD_msmSystemFcsErrorCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemFcsErrorCounter_1 in AQ_MsmSystemRxFcsErrorsCounterRegister_HHD */ +#define word_AQ_MsmSystemRxFcsErrorsCounterRegister_HHD_msmSystemFcsErrorCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD_baseRegisterAddress 0x604C +/*! \brief MMD address of structure AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemAlignmentErrorCounter_0 in AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD_msmSystemAlignmentErrorCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemAlignmentErrorCounter_0 in AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD_msmSystemAlignmentErrorCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemAlignmentErrorCounter_0 in AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD */ +#define word_AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD_msmSystemAlignmentErrorCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemAlignmentErrorCounter_1 in AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD_msmSystemAlignmentErrorCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemAlignmentErrorCounter_1 in AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD_msmSystemAlignmentErrorCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemAlignmentErrorCounter_1 in AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD */ +#define word_AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD_msmSystemAlignmentErrorCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemTxPauseFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxPauseFramesCounterRegister_HHD_baseRegisterAddress 0x6050 +/*! \brief MMD address of structure AQ_MsmSystemTxPauseFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxPauseFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxPauseFramesCounter_0 in AQ_MsmSystemTxPauseFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxPauseFramesCounterRegister_HHD_msmSystemTxPauseFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxPauseFramesCounter_0 in AQ_MsmSystemTxPauseFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxPauseFramesCounterRegister_HHD_msmSystemTxPauseFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxPauseFramesCounter_0 in AQ_MsmSystemTxPauseFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemTxPauseFramesCounterRegister_HHD_msmSystemTxPauseFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxPauseFramesCounter_1 in AQ_MsmSystemTxPauseFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxPauseFramesCounterRegister_HHD_msmSystemTxPauseFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxPauseFramesCounter_1 in AQ_MsmSystemTxPauseFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxPauseFramesCounterRegister_HHD_msmSystemTxPauseFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxPauseFramesCounter_1 in AQ_MsmSystemTxPauseFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemTxPauseFramesCounterRegister_HHD_msmSystemTxPauseFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemRxPauseFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxPauseFramesCounterRegister_HHD_baseRegisterAddress 0x6054 +/*! \brief MMD address of structure AQ_MsmSystemRxPauseFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxPauseFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxPauseFramesCounter_0 in AQ_MsmSystemRxPauseFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxPauseFramesCounterRegister_HHD_msmSystemRxPauseFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxPauseFramesCounter_0 in AQ_MsmSystemRxPauseFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxPauseFramesCounterRegister_HHD_msmSystemRxPauseFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxPauseFramesCounter_0 in AQ_MsmSystemRxPauseFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemRxPauseFramesCounterRegister_HHD_msmSystemRxPauseFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxPauseFramesCounter_1 in AQ_MsmSystemRxPauseFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxPauseFramesCounterRegister_HHD_msmSystemRxPauseFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxPauseFramesCounter_1 in AQ_MsmSystemRxPauseFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxPauseFramesCounterRegister_HHD_msmSystemRxPauseFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxPauseFramesCounter_1 in AQ_MsmSystemRxPauseFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemRxPauseFramesCounterRegister_HHD_msmSystemRxPauseFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD_baseRegisterAddress 0x6058 +/*! \brief MMD address of structure AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxTooLongErrorsCounter_0 in AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD_msmSystemRxTooLongErrorsCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxTooLongErrorsCounter_0 in AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD_msmSystemRxTooLongErrorsCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxTooLongErrorsCounter_0 in AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD */ +#define word_AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD_msmSystemRxTooLongErrorsCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxTooLongErrorsCounter_1 in AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD_msmSystemRxTooLongErrorsCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxTooLongErrorsCounter_1 in AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD_msmSystemRxTooLongErrorsCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxTooLongErrorsCounter_1 in AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD */ +#define word_AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD_msmSystemRxTooLongErrorsCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD_baseRegisterAddress 0x605C +/*! \brief MMD address of structure AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxInRangeLengthErrorsCounter_0 in AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD_msmSystemRxInRangeLengthErrorsCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxInRangeLengthErrorsCounter_0 in AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD_msmSystemRxInRangeLengthErrorsCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxInRangeLengthErrorsCounter_0 in AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD */ +#define word_AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD_msmSystemRxInRangeLengthErrorsCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxInRangeLengthErrorsCounter_1 in AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD_msmSystemRxInRangeLengthErrorsCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxInRangeLengthErrorsCounter_1 in AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD_msmSystemRxInRangeLengthErrorsCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxInRangeLengthErrorsCounter_1 in AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD */ +#define word_AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD_msmSystemRxInRangeLengthErrorsCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemTxVlanFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxVlanFramesCounterRegister_HHD_baseRegisterAddress 0x6060 +/*! \brief MMD address of structure AQ_MsmSystemTxVlanFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxVlanFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxVlanFramesCounter_0 in AQ_MsmSystemTxVlanFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxVlanFramesCounterRegister_HHD_msmSystemTxVlanFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxVlanFramesCounter_0 in AQ_MsmSystemTxVlanFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxVlanFramesCounterRegister_HHD_msmSystemTxVlanFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxVlanFramesCounter_0 in AQ_MsmSystemTxVlanFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemTxVlanFramesCounterRegister_HHD_msmSystemTxVlanFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxVlanFramesCounter_1 in AQ_MsmSystemTxVlanFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxVlanFramesCounterRegister_HHD_msmSystemTxVlanFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxVlanFramesCounter_1 in AQ_MsmSystemTxVlanFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxVlanFramesCounterRegister_HHD_msmSystemTxVlanFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxVlanFramesCounter_1 in AQ_MsmSystemTxVlanFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemTxVlanFramesCounterRegister_HHD_msmSystemTxVlanFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemRxVlanFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxVlanFramesCounterRegister_HHD_baseRegisterAddress 0x6064 +/*! \brief MMD address of structure AQ_MsmSystemRxVlanFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxVlanFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxVlanFramesCounter_0 in AQ_MsmSystemRxVlanFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxVlanFramesCounterRegister_HHD_msmSystemRxVlanFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxVlanFramesCounter_0 in AQ_MsmSystemRxVlanFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxVlanFramesCounterRegister_HHD_msmSystemRxVlanFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxVlanFramesCounter_0 in AQ_MsmSystemRxVlanFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemRxVlanFramesCounterRegister_HHD_msmSystemRxVlanFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxVlanFramesCounter_1 in AQ_MsmSystemRxVlanFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxVlanFramesCounterRegister_HHD_msmSystemRxVlanFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxVlanFramesCounter_1 in AQ_MsmSystemRxVlanFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxVlanFramesCounterRegister_HHD_msmSystemRxVlanFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxVlanFramesCounter_1 in AQ_MsmSystemRxVlanFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemRxVlanFramesCounterRegister_HHD_msmSystemRxVlanFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemTxOctetsCounterRegister_HHD */ +#define AQ_MsmSystemTxOctetsCounterRegister_HHD_baseRegisterAddress 0x6068 +/*! \brief MMD address of structure AQ_MsmSystemTxOctetsCounterRegister_HHD */ +#define AQ_MsmSystemTxOctetsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxOctetsCounter_0 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ +#define AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxOctetsCounter_0 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxOctetsCounter_0 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ +#define word_AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxOctetsCounter_1 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ +#define AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxOctetsCounter_1 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxOctetsCounter_1 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ +#define word_AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_1 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxOctetsCounter_2 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ +#define AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_2 2 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxOctetsCounter_2 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_2 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxOctetsCounter_2 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ +#define word_AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_2 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxOctetsCounter_3 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ +#define AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_3 3 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxOctetsCounter_3 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_3 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxOctetsCounter_3 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ +#define word_AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_3 u3.word_3 + +/*! \brief Base register address of structure AQ_MsmSystemRxOctetsCounterRegister_HHD */ +#define AQ_MsmSystemRxOctetsCounterRegister_HHD_baseRegisterAddress 0x606C +/*! \brief MMD address of structure AQ_MsmSystemRxOctetsCounterRegister_HHD */ +#define AQ_MsmSystemRxOctetsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxOctetsCounter_0 in AQ_MsmSystemRxOctetsCounterRegister_HHD */ +#define AQ_MsmSystemRxOctetsCounterRegister_HHD_msmSystemRxOctetsCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxOctetsCounter_0 in AQ_MsmSystemRxOctetsCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxOctetsCounterRegister_HHD_msmSystemRxOctetsCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxOctetsCounter_0 in AQ_MsmSystemRxOctetsCounterRegister_HHD */ +#define word_AQ_MsmSystemRxOctetsCounterRegister_HHD_msmSystemRxOctetsCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxOctetsCounter_1 in AQ_MsmSystemRxOctetsCounterRegister_HHD */ +#define AQ_MsmSystemRxOctetsCounterRegister_HHD_msmSystemRxOctetsCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxOctetsCounter_1 in AQ_MsmSystemRxOctetsCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxOctetsCounterRegister_HHD_msmSystemRxOctetsCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxOctetsCounter_1 in AQ_MsmSystemRxOctetsCounterRegister_HHD */ +#define word_AQ_MsmSystemRxOctetsCounterRegister_HHD_msmSystemRxOctetsCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemRxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxUnicastFramesCounterRegister_HHD_baseRegisterAddress 0x6070 +/*! \brief MMD address of structure AQ_MsmSystemRxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxUnicastFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxUnicastFramesCounter_0 in AQ_MsmSystemRxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxUnicastFramesCounterRegister_HHD_msmSystemRxUnicastFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxUnicastFramesCounter_0 in AQ_MsmSystemRxUnicastFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxUnicastFramesCounterRegister_HHD_msmSystemRxUnicastFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxUnicastFramesCounter_0 in AQ_MsmSystemRxUnicastFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemRxUnicastFramesCounterRegister_HHD_msmSystemRxUnicastFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxUnicastFramesCounter_1 in AQ_MsmSystemRxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxUnicastFramesCounterRegister_HHD_msmSystemRxUnicastFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxUnicastFramesCounter_1 in AQ_MsmSystemRxUnicastFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxUnicastFramesCounterRegister_HHD_msmSystemRxUnicastFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxUnicastFramesCounter_1 in AQ_MsmSystemRxUnicastFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemRxUnicastFramesCounterRegister_HHD_msmSystemRxUnicastFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemRxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxMulticastFramesCounterRegister_HHD_baseRegisterAddress 0x6074 +/*! \brief MMD address of structure AQ_MsmSystemRxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxMulticastFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxMulticastFramesCounter_0 in AQ_MsmSystemRxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxMulticastFramesCounterRegister_HHD_msmSystemRxMulticastFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxMulticastFramesCounter_0 in AQ_MsmSystemRxMulticastFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxMulticastFramesCounterRegister_HHD_msmSystemRxMulticastFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxMulticastFramesCounter_0 in AQ_MsmSystemRxMulticastFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemRxMulticastFramesCounterRegister_HHD_msmSystemRxMulticastFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxMulticastFramesCounter_1 in AQ_MsmSystemRxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxMulticastFramesCounterRegister_HHD_msmSystemRxMulticastFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxMulticastFramesCounter_1 in AQ_MsmSystemRxMulticastFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxMulticastFramesCounterRegister_HHD_msmSystemRxMulticastFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxMulticastFramesCounter_1 in AQ_MsmSystemRxMulticastFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemRxMulticastFramesCounterRegister_HHD_msmSystemRxMulticastFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD_baseRegisterAddress 0x6078 +/*! \brief MMD address of structure AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxBroadcastFramesCounter_0 in AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD_msmSystemRxBroadcastFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxBroadcastFramesCounter_0 in AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD_msmSystemRxBroadcastFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxBroadcastFramesCounter_0 in AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD_msmSystemRxBroadcastFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxBroadcastFramesCounter_1 in AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD_msmSystemRxBroadcastFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxBroadcastFramesCounter_1 in AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD_msmSystemRxBroadcastFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxBroadcastFramesCounter_1 in AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD_msmSystemRxBroadcastFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemTxErrorsCounterRegister_HHD */ +#define AQ_MsmSystemTxErrorsCounterRegister_HHD_baseRegisterAddress 0x607C +/*! \brief MMD address of structure AQ_MsmSystemTxErrorsCounterRegister_HHD */ +#define AQ_MsmSystemTxErrorsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxErrorsCounter_0 in AQ_MsmSystemTxErrorsCounterRegister_HHD */ +#define AQ_MsmSystemTxErrorsCounterRegister_HHD_msmSystemTxErrorsCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxErrorsCounter_0 in AQ_MsmSystemTxErrorsCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxErrorsCounterRegister_HHD_msmSystemTxErrorsCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxErrorsCounter_0 in AQ_MsmSystemTxErrorsCounterRegister_HHD */ +#define word_AQ_MsmSystemTxErrorsCounterRegister_HHD_msmSystemTxErrorsCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxErrorsCounter_1 in AQ_MsmSystemTxErrorsCounterRegister_HHD */ +#define AQ_MsmSystemTxErrorsCounterRegister_HHD_msmSystemTxErrorsCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxErrorsCounter_1 in AQ_MsmSystemTxErrorsCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxErrorsCounterRegister_HHD_msmSystemTxErrorsCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxErrorsCounter_1 in AQ_MsmSystemTxErrorsCounterRegister_HHD */ +#define word_AQ_MsmSystemTxErrorsCounterRegister_HHD_msmSystemTxErrorsCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemTxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxUnicastFramesCounterRegister_HHD_baseRegisterAddress 0x6084 +/*! \brief MMD address of structure AQ_MsmSystemTxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxUnicastFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxUnicastFramesCounter_0 in AQ_MsmSystemTxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxUnicastFramesCounterRegister_HHD_msmSystemTxUnicastFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxUnicastFramesCounter_0 in AQ_MsmSystemTxUnicastFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxUnicastFramesCounterRegister_HHD_msmSystemTxUnicastFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxUnicastFramesCounter_0 in AQ_MsmSystemTxUnicastFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemTxUnicastFramesCounterRegister_HHD_msmSystemTxUnicastFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxUnicastFramesCounter_1 in AQ_MsmSystemTxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxUnicastFramesCounterRegister_HHD_msmSystemTxUnicastFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxUnicastFramesCounter_1 in AQ_MsmSystemTxUnicastFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxUnicastFramesCounterRegister_HHD_msmSystemTxUnicastFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxUnicastFramesCounter_1 in AQ_MsmSystemTxUnicastFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemTxUnicastFramesCounterRegister_HHD_msmSystemTxUnicastFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemTxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxMulticastFramesCounterRegister_HHD_baseRegisterAddress 0x6088 +/*! \brief MMD address of structure AQ_MsmSystemTxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxMulticastFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxMulticastFramesCounter_0 in AQ_MsmSystemTxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxMulticastFramesCounterRegister_HHD_msmSystemTxMulticastFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxMulticastFramesCounter_0 in AQ_MsmSystemTxMulticastFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxMulticastFramesCounterRegister_HHD_msmSystemTxMulticastFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxMulticastFramesCounter_0 in AQ_MsmSystemTxMulticastFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemTxMulticastFramesCounterRegister_HHD_msmSystemTxMulticastFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxMulticastFramesCounter_1 in AQ_MsmSystemTxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxMulticastFramesCounterRegister_HHD_msmSystemTxMulticastFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxMulticastFramesCounter_1 in AQ_MsmSystemTxMulticastFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxMulticastFramesCounterRegister_HHD_msmSystemTxMulticastFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxMulticastFramesCounter_1 in AQ_MsmSystemTxMulticastFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemTxMulticastFramesCounterRegister_HHD_msmSystemTxMulticastFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD_baseRegisterAddress 0x608C +/*! \brief MMD address of structure AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxBroadcastFramesCounter_0 in AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD_msmSystemTxBroadcastFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxBroadcastFramesCounter_0 in AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD_msmSystemTxBroadcastFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxBroadcastFramesCounter_0 in AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD_msmSystemTxBroadcastFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxBroadcastFramesCounter_1 in AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD_msmSystemTxBroadcastFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxBroadcastFramesCounter_1 in AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD_msmSystemTxBroadcastFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxBroadcastFramesCounter_1 in AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD_msmSystemTxBroadcastFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemRxErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxErrorsCounterRegister_HHD_baseRegisterAddress 0x60C8 +/*! \brief MMD address of structure AQ_MsmSystemRxErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxErrorsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxErrorsCounter_0 in AQ_MsmSystemRxErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxErrorsCounterRegister_HHD_msmSystemRxErrorsCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxErrorsCounter_0 in AQ_MsmSystemRxErrorsCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxErrorsCounterRegister_HHD_msmSystemRxErrorsCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxErrorsCounter_0 in AQ_MsmSystemRxErrorsCounterRegister_HHD */ +#define word_AQ_MsmSystemRxErrorsCounterRegister_HHD_msmSystemRxErrorsCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxErrorsCounter_1 in AQ_MsmSystemRxErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxErrorsCounterRegister_HHD_msmSystemRxErrorsCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxErrorsCounter_1 in AQ_MsmSystemRxErrorsCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxErrorsCounterRegister_HHD_msmSystemRxErrorsCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxErrorsCounter_1 in AQ_MsmSystemRxErrorsCounterRegister_HHD */ +#define word_AQ_MsmSystemRxErrorsCounterRegister_HHD_msmSystemRxErrorsCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MssIngressVlanTpid_0Register_HHD */ +#define AQ_MssIngressVlanTpid_0Register_HHD_baseRegisterAddress 0x8006 +/*! \brief MMD address of structure AQ_MssIngressVlanTpid_0Register_HHD */ +#define AQ_MssIngressVlanTpid_0Register_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressVlanStag in AQ_MssIngressVlanTpid_0Register_HHD */ +#define AQ_MssIngressVlanTpid_0Register_HHD_mssIngressVlanStag 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressVlanStag in AQ_MssIngressVlanTpid_0Register_HHD */ +#define bits_AQ_MssIngressVlanTpid_0Register_HHD_mssIngressVlanStag u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressVlanStag in AQ_MssIngressVlanTpid_0Register_HHD */ +#define word_AQ_MssIngressVlanTpid_0Register_HHD_mssIngressVlanStag u0.word_0 + +/*! \brief Base register address of structure AQ_MssIngressVlanTpid_1Register_HHD */ +#define AQ_MssIngressVlanTpid_1Register_HHD_baseRegisterAddress 0x8008 +/*! \brief MMD address of structure AQ_MssIngressVlanTpid_1Register_HHD */ +#define AQ_MssIngressVlanTpid_1Register_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressVlanQtag in AQ_MssIngressVlanTpid_1Register_HHD */ +#define AQ_MssIngressVlanTpid_1Register_HHD_mssIngressVlanQtag 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressVlanQtag in AQ_MssIngressVlanTpid_1Register_HHD */ +#define bits_AQ_MssIngressVlanTpid_1Register_HHD_mssIngressVlanQtag u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressVlanQtag in AQ_MssIngressVlanTpid_1Register_HHD */ +#define word_AQ_MssIngressVlanTpid_1Register_HHD_mssIngressVlanQtag u0.word_0 + +/*! \brief Base register address of structure AQ_MssIngressVlanControlRegister_HHD */ +#define AQ_MssIngressVlanControlRegister_HHD_baseRegisterAddress 0x800A +/*! \brief MMD address of structure AQ_MssIngressVlanControlRegister_HHD */ +#define AQ_MssIngressVlanControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressVlanUpMapTableLSW in AQ_MssIngressVlanControlRegister_HHD */ +#define AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanUpMapTableLSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressVlanUpMapTableLSW in AQ_MssIngressVlanControlRegister_HHD */ +#define bits_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanUpMapTableLSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressVlanUpMapTableLSW in AQ_MssIngressVlanControlRegister_HHD */ +#define word_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanUpMapTableLSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressVlanQtagParseEnable in AQ_MssIngressVlanControlRegister_HHD */ +#define AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanQtagParseEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressVlanQtagParseEnable in AQ_MssIngressVlanControlRegister_HHD */ +#define bits_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanQtagParseEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressVlanQtagParseEnable in AQ_MssIngressVlanControlRegister_HHD */ +#define word_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanQtagParseEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressVlanStagParseEnable in AQ_MssIngressVlanControlRegister_HHD */ +#define AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanStagParseEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressVlanStagParseEnable in AQ_MssIngressVlanControlRegister_HHD */ +#define bits_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanStagParseEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressVlanStagParseEnable in AQ_MssIngressVlanControlRegister_HHD */ +#define word_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanStagParseEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressVlanQinqParseEnable in AQ_MssIngressVlanControlRegister_HHD */ +#define AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanQinqParseEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressVlanQinqParseEnable in AQ_MssIngressVlanControlRegister_HHD */ +#define bits_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanQinqParseEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressVlanQinqParseEnable in AQ_MssIngressVlanControlRegister_HHD */ +#define word_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanQinqParseEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressVlanQtagUpParseEnable in AQ_MssIngressVlanControlRegister_HHD */ +#define AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanQtagUpParseEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressVlanQtagUpParseEnable in AQ_MssIngressVlanControlRegister_HHD */ +#define bits_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanQtagUpParseEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressVlanQtagUpParseEnable in AQ_MssIngressVlanControlRegister_HHD */ +#define word_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanQtagUpParseEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressVlanStagUpParseEnable in AQ_MssIngressVlanControlRegister_HHD */ +#define AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanStagUpParseEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressVlanStagUpParseEnable in AQ_MssIngressVlanControlRegister_HHD */ +#define bits_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanStagUpParseEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressVlanStagUpParseEnable in AQ_MssIngressVlanControlRegister_HHD */ +#define word_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanStagUpParseEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressVlanUpDefault in AQ_MssIngressVlanControlRegister_HHD */ +#define AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanUpDefault 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressVlanUpDefault in AQ_MssIngressVlanControlRegister_HHD */ +#define bits_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanUpDefault u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressVlanUpDefault in AQ_MssIngressVlanControlRegister_HHD */ +#define word_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanUpDefault u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressVlanUpMapTableMSW in AQ_MssIngressVlanControlRegister_HHD */ +#define AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanUpMapTableMSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressVlanUpMapTableMSW in AQ_MssIngressVlanControlRegister_HHD */ +#define bits_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanUpMapTableMSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressVlanUpMapTableMSW in AQ_MssIngressVlanControlRegister_HHD */ +#define word_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanUpMapTableMSW u1.word_1 + +/*! \brief Base register address of structure AQ_MssIngressMtuSizeControlRegister_HHD */ +#define AQ_MssIngressMtuSizeControlRegister_HHD_baseRegisterAddress 0x800C +/*! \brief MMD address of structure AQ_MssIngressMtuSizeControlRegister_HHD */ +#define AQ_MssIngressMtuSizeControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressControlledPacketMtuSize in AQ_MssIngressMtuSizeControlRegister_HHD */ +#define AQ_MssIngressMtuSizeControlRegister_HHD_mssIngressControlledPacketMtuSize 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressControlledPacketMtuSize in AQ_MssIngressMtuSizeControlRegister_HHD */ +#define bits_AQ_MssIngressMtuSizeControlRegister_HHD_mssIngressControlledPacketMtuSize u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressControlledPacketMtuSize in AQ_MssIngressMtuSizeControlRegister_HHD */ +#define word_AQ_MssIngressMtuSizeControlRegister_HHD_mssIngressControlledPacketMtuSize u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressUncontrolledPacketMtuSize in AQ_MssIngressMtuSizeControlRegister_HHD */ +#define AQ_MssIngressMtuSizeControlRegister_HHD_mssIngressUncontrolledPacketMtuSize 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressUncontrolledPacketMtuSize in AQ_MssIngressMtuSizeControlRegister_HHD */ +#define bits_AQ_MssIngressMtuSizeControlRegister_HHD_mssIngressUncontrolledPacketMtuSize u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressUncontrolledPacketMtuSize in AQ_MssIngressMtuSizeControlRegister_HHD */ +#define word_AQ_MssIngressMtuSizeControlRegister_HHD_mssIngressUncontrolledPacketMtuSize u1.word_1 + +/*! \brief Base register address of structure AQ_MssIngressControlRegister_HHD */ +#define AQ_MssIngressControlRegister_HHD_baseRegisterAddress 0x800E +/*! \brief MMD address of structure AQ_MssIngressControlRegister_HHD */ +#define AQ_MssIngressControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressIcvLsb_8BytesEnable in AQ_MssIngressControlRegister_HHD */ +#define AQ_MssIngressControlRegister_HHD_mssIngressIcvLsb_8BytesEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressIcvLsb_8BytesEnable in AQ_MssIngressControlRegister_HHD */ +#define bits_AQ_MssIngressControlRegister_HHD_mssIngressIcvLsb_8BytesEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressIcvLsb_8BytesEnable in AQ_MssIngressControlRegister_HHD */ +#define word_AQ_MssIngressControlRegister_HHD_mssIngressIcvLsb_8BytesEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressGlobalValidateFrames in AQ_MssIngressControlRegister_HHD */ +#define AQ_MssIngressControlRegister_HHD_mssIngressGlobalValidateFrames 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressGlobalValidateFrames in AQ_MssIngressControlRegister_HHD */ +#define bits_AQ_MssIngressControlRegister_HHD_mssIngressGlobalValidateFrames u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressGlobalValidateFrames in AQ_MssIngressControlRegister_HHD */ +#define word_AQ_MssIngressControlRegister_HHD_mssIngressGlobalValidateFrames u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressRemoveSectag in AQ_MssIngressControlRegister_HHD */ +#define AQ_MssIngressControlRegister_HHD_mssIngressRemoveSectag 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressRemoveSectag in AQ_MssIngressControlRegister_HHD */ +#define bits_AQ_MssIngressControlRegister_HHD_mssIngressRemoveSectag u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressRemoveSectag in AQ_MssIngressControlRegister_HHD */ +#define word_AQ_MssIngressControlRegister_HHD_mssIngressRemoveSectag u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressHighPriority in AQ_MssIngressControlRegister_HHD */ +#define AQ_MssIngressControlRegister_HHD_mssIngressHighPriority 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressHighPriority in AQ_MssIngressControlRegister_HHD */ +#define bits_AQ_MssIngressControlRegister_HHD_mssIngressHighPriority u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressHighPriority in AQ_MssIngressControlRegister_HHD */ +#define word_AQ_MssIngressControlRegister_HHD_mssIngressHighPriority u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressClearCount in AQ_MssIngressControlRegister_HHD */ +#define AQ_MssIngressControlRegister_HHD_mssIngressClearCount 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressClearCount in AQ_MssIngressControlRegister_HHD */ +#define bits_AQ_MssIngressControlRegister_HHD_mssIngressClearCount u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressClearCount in AQ_MssIngressControlRegister_HHD */ +#define word_AQ_MssIngressControlRegister_HHD_mssIngressClearCount u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressClearGlobalTime in AQ_MssIngressControlRegister_HHD */ +#define AQ_MssIngressControlRegister_HHD_mssIngressClearGlobalTime 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressClearGlobalTime in AQ_MssIngressControlRegister_HHD */ +#define bits_AQ_MssIngressControlRegister_HHD_mssIngressClearGlobalTime u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressClearGlobalTime in AQ_MssIngressControlRegister_HHD */ +#define word_AQ_MssIngressControlRegister_HHD_mssIngressClearGlobalTime u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressCheckIcv in AQ_MssIngressControlRegister_HHD */ +#define AQ_MssIngressControlRegister_HHD_mssIngressCheckIcv 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressCheckIcv in AQ_MssIngressControlRegister_HHD */ +#define bits_AQ_MssIngressControlRegister_HHD_mssIngressCheckIcv u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressCheckIcv in AQ_MssIngressControlRegister_HHD */ +#define word_AQ_MssIngressControlRegister_HHD_mssIngressCheckIcv u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressDropIgprcMiss in AQ_MssIngressControlRegister_HHD */ +#define AQ_MssIngressControlRegister_HHD_mssIngressDropIgprcMiss 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressDropIgprcMiss in AQ_MssIngressControlRegister_HHD */ +#define bits_AQ_MssIngressControlRegister_HHD_mssIngressDropIgprcMiss u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressDropIgprcMiss in AQ_MssIngressControlRegister_HHD */ +#define word_AQ_MssIngressControlRegister_HHD_mssIngressDropIgprcMiss u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressDropKayPacket in AQ_MssIngressControlRegister_HHD */ +#define AQ_MssIngressControlRegister_HHD_mssIngressDropKayPacket 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressDropKayPacket in AQ_MssIngressControlRegister_HHD */ +#define bits_AQ_MssIngressControlRegister_HHD_mssIngressDropKayPacket u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressDropKayPacket in AQ_MssIngressControlRegister_HHD */ +#define word_AQ_MssIngressControlRegister_HHD_mssIngressDropKayPacket u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressMaskShortLengthError in AQ_MssIngressControlRegister_HHD */ +#define AQ_MssIngressControlRegister_HHD_mssIngressMaskShortLengthError 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressMaskShortLengthError in AQ_MssIngressControlRegister_HHD */ +#define bits_AQ_MssIngressControlRegister_HHD_mssIngressMaskShortLengthError u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressMaskShortLengthError in AQ_MssIngressControlRegister_HHD */ +#define word_AQ_MssIngressControlRegister_HHD_mssIngressMaskShortLengthError u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressCreateSci in AQ_MssIngressControlRegister_HHD */ +#define AQ_MssIngressControlRegister_HHD_mssIngressCreateSci 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressCreateSci in AQ_MssIngressControlRegister_HHD */ +#define bits_AQ_MssIngressControlRegister_HHD_mssIngressCreateSci u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressCreateSci in AQ_MssIngressControlRegister_HHD */ +#define word_AQ_MssIngressControlRegister_HHD_mssIngressCreateSci u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressOperationPointToPoint in AQ_MssIngressControlRegister_HHD */ +#define AQ_MssIngressControlRegister_HHD_mssIngressOperationPointToPoint 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressOperationPointToPoint in AQ_MssIngressControlRegister_HHD */ +#define bits_AQ_MssIngressControlRegister_HHD_mssIngressOperationPointToPoint u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressOperationPointToPoint in AQ_MssIngressControlRegister_HHD */ +#define word_AQ_MssIngressControlRegister_HHD_mssIngressOperationPointToPoint u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSoftReset in AQ_MssIngressControlRegister_HHD */ +#define AQ_MssIngressControlRegister_HHD_mssIngressSoftReset 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSoftReset in AQ_MssIngressControlRegister_HHD */ +#define bits_AQ_MssIngressControlRegister_HHD_mssIngressSoftReset u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSoftReset in AQ_MssIngressControlRegister_HHD */ +#define word_AQ_MssIngressControlRegister_HHD_mssIngressSoftReset u0.word_0 + +/*! \brief Base register address of structure AQ_MssIngressSaControlRegister_HHD */ +#define AQ_MssIngressSaControlRegister_HHD_baseRegisterAddress 0x8010 +/*! \brief MMD address of structure AQ_MssIngressSaControlRegister_HHD */ +#define AQ_MssIngressSaControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaThresholdLSW in AQ_MssIngressSaControlRegister_HHD */ +#define AQ_MssIngressSaControlRegister_HHD_mssIngressSaThresholdLSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaThresholdLSW in AQ_MssIngressSaControlRegister_HHD */ +#define bits_AQ_MssIngressSaControlRegister_HHD_mssIngressSaThresholdLSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaThresholdLSW in AQ_MssIngressSaControlRegister_HHD */ +#define word_AQ_MssIngressSaControlRegister_HHD_mssIngressSaThresholdLSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaThresholdMSW in AQ_MssIngressSaControlRegister_HHD */ +#define AQ_MssIngressSaControlRegister_HHD_mssIngressSaThresholdMSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaThresholdMSW in AQ_MssIngressSaControlRegister_HHD */ +#define bits_AQ_MssIngressSaControlRegister_HHD_mssIngressSaThresholdMSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaThresholdMSW in AQ_MssIngressSaControlRegister_HHD */ +#define word_AQ_MssIngressSaControlRegister_HHD_mssIngressSaThresholdMSW u1.word_1 + +/*! \brief Base register address of structure AQ_MssIngressInterruptStatusRegister_HHD */ +#define AQ_MssIngressInterruptStatusRegister_HHD_baseRegisterAddress 0x802E +/*! \brief MMD address of structure AQ_MssIngressInterruptStatusRegister_HHD */ +#define AQ_MssIngressInterruptStatusRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressIgpocMissInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define AQ_MssIngressInterruptStatusRegister_HHD_mssIngressIgpocMissInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressIgpocMissInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define bits_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressIgpocMissInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressIgpocMissInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define word_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressIgpocMissInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressTciE_cErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define AQ_MssIngressInterruptStatusRegister_HHD_mssIngressTciE_cErrorInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressTciE_cErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define bits_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressTciE_cErrorInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressTciE_cErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define word_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressTciE_cErrorInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressEccErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define AQ_MssIngressInterruptStatusRegister_HHD_mssIngressEccErrorInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressEccErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define bits_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressEccErrorInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressEccErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define word_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressEccErrorInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressMibSaturationInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define AQ_MssIngressInterruptStatusRegister_HHD_mssIngressMibSaturationInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressMibSaturationInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define bits_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressMibSaturationInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressMibSaturationInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define word_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressMibSaturationInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressReplayErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define AQ_MssIngressInterruptStatusRegister_HHD_mssIngressReplayErrorInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressReplayErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define bits_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressReplayErrorInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressReplayErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define word_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressReplayErrorInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressIcvErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define AQ_MssIngressInterruptStatusRegister_HHD_mssIngressIcvErrorInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressIcvErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define bits_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressIcvErrorInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressIcvErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define word_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressIcvErrorInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaThresholdExpiredInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define AQ_MssIngressInterruptStatusRegister_HHD_mssIngressSaThresholdExpiredInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaThresholdExpiredInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define bits_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressSaThresholdExpiredInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaThresholdExpiredInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define word_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressSaThresholdExpiredInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaExpiredInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define AQ_MssIngressInterruptStatusRegister_HHD_mssIngressSaExpiredInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaExpiredInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define bits_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressSaExpiredInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaExpiredInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define word_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressSaExpiredInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssMasterIngressInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define AQ_MssIngressInterruptStatusRegister_HHD_mssMasterIngressInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssMasterIngressInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define bits_AQ_MssIngressInterruptStatusRegister_HHD_mssMasterIngressInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssMasterIngressInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define word_AQ_MssIngressInterruptStatusRegister_HHD_mssMasterIngressInterrupt u0.word_0 + +/*! \brief Base register address of structure AQ_MssIngressInterruptMaskRegister_HHD */ +#define AQ_MssIngressInterruptMaskRegister_HHD_baseRegisterAddress 0x8030 +/*! \brief MMD address of structure AQ_MssIngressInterruptMaskRegister_HHD */ +#define AQ_MssIngressInterruptMaskRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressIgpocMissInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define AQ_MssIngressInterruptMaskRegister_HHD_mssIngressIgpocMissInterruptEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressIgpocMissInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define bits_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressIgpocMissInterruptEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressIgpocMissInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define word_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressIgpocMissInterruptEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressTciE_cErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define AQ_MssIngressInterruptMaskRegister_HHD_mssIngressTciE_cErrorInterruptEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressTciE_cErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define bits_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressTciE_cErrorInterruptEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressTciE_cErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define word_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressTciE_cErrorInterruptEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressEccErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define AQ_MssIngressInterruptMaskRegister_HHD_mssIngressEccErrorInterruptEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressEccErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define bits_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressEccErrorInterruptEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressEccErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define word_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressEccErrorInterruptEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressMibSaturationInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define AQ_MssIngressInterruptMaskRegister_HHD_mssIngressMibSaturationInterruptEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressMibSaturationInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define bits_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressMibSaturationInterruptEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressMibSaturationInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define word_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressMibSaturationInterruptEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressReplayErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define AQ_MssIngressInterruptMaskRegister_HHD_mssIngressReplayErrorInterruptEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressReplayErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define bits_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressReplayErrorInterruptEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressReplayErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define word_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressReplayErrorInterruptEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressIcvErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define AQ_MssIngressInterruptMaskRegister_HHD_mssIngressIcvErrorInterruptEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressIcvErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define bits_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressIcvErrorInterruptEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressIcvErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define word_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressIcvErrorInterruptEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaThresholdExpiredInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define AQ_MssIngressInterruptMaskRegister_HHD_mssIngressSaThresholdExpiredInterruptEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaThresholdExpiredInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define bits_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressSaThresholdExpiredInterruptEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaThresholdExpiredInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define word_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressSaThresholdExpiredInterruptEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaExpiredInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define AQ_MssIngressInterruptMaskRegister_HHD_mssIngressSaExpiredInterruptEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaExpiredInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define bits_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressSaExpiredInterruptEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaExpiredInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define word_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressSaExpiredInterruptEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressMasterInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define AQ_MssIngressInterruptMaskRegister_HHD_mssIngressMasterInterruptEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressMasterInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define bits_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressMasterInterruptEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressMasterInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define word_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressMasterInterruptEnable u0.word_0 + +/*! \brief Base register address of structure AQ_MssIngressSaIcvErrorStatusRegister_HHD */ +#define AQ_MssIngressSaIcvErrorStatusRegister_HHD_baseRegisterAddress 0x8032 +/*! \brief MMD address of structure AQ_MssIngressSaIcvErrorStatusRegister_HHD */ +#define AQ_MssIngressSaIcvErrorStatusRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaIcvErrorLSW in AQ_MssIngressSaIcvErrorStatusRegister_HHD */ +#define AQ_MssIngressSaIcvErrorStatusRegister_HHD_mssIngressSaIcvErrorLSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaIcvErrorLSW in AQ_MssIngressSaIcvErrorStatusRegister_HHD */ +#define bits_AQ_MssIngressSaIcvErrorStatusRegister_HHD_mssIngressSaIcvErrorLSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaIcvErrorLSW in AQ_MssIngressSaIcvErrorStatusRegister_HHD */ +#define word_AQ_MssIngressSaIcvErrorStatusRegister_HHD_mssIngressSaIcvErrorLSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaIcvErrorMSW in AQ_MssIngressSaIcvErrorStatusRegister_HHD */ +#define AQ_MssIngressSaIcvErrorStatusRegister_HHD_mssIngressSaIcvErrorMSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaIcvErrorMSW in AQ_MssIngressSaIcvErrorStatusRegister_HHD */ +#define bits_AQ_MssIngressSaIcvErrorStatusRegister_HHD_mssIngressSaIcvErrorMSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaIcvErrorMSW in AQ_MssIngressSaIcvErrorStatusRegister_HHD */ +#define word_AQ_MssIngressSaIcvErrorStatusRegister_HHD_mssIngressSaIcvErrorMSW u1.word_1 + +/*! \brief Base register address of structure AQ_MssIngressSaReplayErrorStatusRegister_HHD */ +#define AQ_MssIngressSaReplayErrorStatusRegister_HHD_baseRegisterAddress 0x8034 +/*! \brief MMD address of structure AQ_MssIngressSaReplayErrorStatusRegister_HHD */ +#define AQ_MssIngressSaReplayErrorStatusRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaReplayErrorLSW in AQ_MssIngressSaReplayErrorStatusRegister_HHD */ +#define AQ_MssIngressSaReplayErrorStatusRegister_HHD_mssIngressSaReplayErrorLSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaReplayErrorLSW in AQ_MssIngressSaReplayErrorStatusRegister_HHD */ +#define bits_AQ_MssIngressSaReplayErrorStatusRegister_HHD_mssIngressSaReplayErrorLSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaReplayErrorLSW in AQ_MssIngressSaReplayErrorStatusRegister_HHD */ +#define word_AQ_MssIngressSaReplayErrorStatusRegister_HHD_mssIngressSaReplayErrorLSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaReplayErrorMSW in AQ_MssIngressSaReplayErrorStatusRegister_HHD */ +#define AQ_MssIngressSaReplayErrorStatusRegister_HHD_mssIngressSaReplayErrorMSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaReplayErrorMSW in AQ_MssIngressSaReplayErrorStatusRegister_HHD */ +#define bits_AQ_MssIngressSaReplayErrorStatusRegister_HHD_mssIngressSaReplayErrorMSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaReplayErrorMSW in AQ_MssIngressSaReplayErrorStatusRegister_HHD */ +#define word_AQ_MssIngressSaReplayErrorStatusRegister_HHD_mssIngressSaReplayErrorMSW u1.word_1 + +/*! \brief Base register address of structure AQ_MssIngressSaExpiredStatusRegister_HHD */ +#define AQ_MssIngressSaExpiredStatusRegister_HHD_baseRegisterAddress 0x8036 +/*! \brief MMD address of structure AQ_MssIngressSaExpiredStatusRegister_HHD */ +#define AQ_MssIngressSaExpiredStatusRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaExpiredLSW in AQ_MssIngressSaExpiredStatusRegister_HHD */ +#define AQ_MssIngressSaExpiredStatusRegister_HHD_mssIngressSaExpiredLSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaExpiredLSW in AQ_MssIngressSaExpiredStatusRegister_HHD */ +#define bits_AQ_MssIngressSaExpiredStatusRegister_HHD_mssIngressSaExpiredLSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaExpiredLSW in AQ_MssIngressSaExpiredStatusRegister_HHD */ +#define word_AQ_MssIngressSaExpiredStatusRegister_HHD_mssIngressSaExpiredLSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaExpiredMSW in AQ_MssIngressSaExpiredStatusRegister_HHD */ +#define AQ_MssIngressSaExpiredStatusRegister_HHD_mssIngressSaExpiredMSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaExpiredMSW in AQ_MssIngressSaExpiredStatusRegister_HHD */ +#define bits_AQ_MssIngressSaExpiredStatusRegister_HHD_mssIngressSaExpiredMSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaExpiredMSW in AQ_MssIngressSaExpiredStatusRegister_HHD */ +#define word_AQ_MssIngressSaExpiredStatusRegister_HHD_mssIngressSaExpiredMSW u1.word_1 + +/*! \brief Base register address of structure AQ_MssIngressSaThresholdExpiredStatusRegister_HHD */ +#define AQ_MssIngressSaThresholdExpiredStatusRegister_HHD_baseRegisterAddress 0x8038 +/*! \brief MMD address of structure AQ_MssIngressSaThresholdExpiredStatusRegister_HHD */ +#define AQ_MssIngressSaThresholdExpiredStatusRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaThresholdExpiredLSW in AQ_MssIngressSaThresholdExpiredStatusRegister_HHD */ +#define AQ_MssIngressSaThresholdExpiredStatusRegister_HHD_mssIngressSaThresholdExpiredLSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaThresholdExpiredLSW in AQ_MssIngressSaThresholdExpiredStatusRegister_HHD */ +#define bits_AQ_MssIngressSaThresholdExpiredStatusRegister_HHD_mssIngressSaThresholdExpiredLSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaThresholdExpiredLSW in AQ_MssIngressSaThresholdExpiredStatusRegister_HHD */ +#define word_AQ_MssIngressSaThresholdExpiredStatusRegister_HHD_mssIngressSaThresholdExpiredLSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaThresholdExpiredMSW in AQ_MssIngressSaThresholdExpiredStatusRegister_HHD */ +#define AQ_MssIngressSaThresholdExpiredStatusRegister_HHD_mssIngressSaThresholdExpiredMSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaThresholdExpiredMSW in AQ_MssIngressSaThresholdExpiredStatusRegister_HHD */ +#define bits_AQ_MssIngressSaThresholdExpiredStatusRegister_HHD_mssIngressSaThresholdExpiredMSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaThresholdExpiredMSW in AQ_MssIngressSaThresholdExpiredStatusRegister_HHD */ +#define word_AQ_MssIngressSaThresholdExpiredStatusRegister_HHD_mssIngressSaThresholdExpiredMSW u1.word_1 + +/*! \brief Base register address of structure AQ_MssIngressEccInterruptStatusRegister_HHD */ +#define AQ_MssIngressEccInterruptStatusRegister_HHD_baseRegisterAddress 0x803A +/*! \brief MMD address of structure AQ_MssIngressEccInterruptStatusRegister_HHD */ +#define AQ_MssIngressEccInterruptStatusRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaEccErrorInterruptLSW in AQ_MssIngressEccInterruptStatusRegister_HHD */ +#define AQ_MssIngressEccInterruptStatusRegister_HHD_mssIngressSaEccErrorInterruptLSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaEccErrorInterruptLSW in AQ_MssIngressEccInterruptStatusRegister_HHD */ +#define bits_AQ_MssIngressEccInterruptStatusRegister_HHD_mssIngressSaEccErrorInterruptLSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaEccErrorInterruptLSW in AQ_MssIngressEccInterruptStatusRegister_HHD */ +#define word_AQ_MssIngressEccInterruptStatusRegister_HHD_mssIngressSaEccErrorInterruptLSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaEccErrorInterruptMSW in AQ_MssIngressEccInterruptStatusRegister_HHD */ +#define AQ_MssIngressEccInterruptStatusRegister_HHD_mssIngressSaEccErrorInterruptMSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaEccErrorInterruptMSW in AQ_MssIngressEccInterruptStatusRegister_HHD */ +#define bits_AQ_MssIngressEccInterruptStatusRegister_HHD_mssIngressSaEccErrorInterruptMSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaEccErrorInterruptMSW in AQ_MssIngressEccInterruptStatusRegister_HHD */ +#define word_AQ_MssIngressEccInterruptStatusRegister_HHD_mssIngressSaEccErrorInterruptMSW u1.word_1 + +/*! \brief Base register address of structure AQ_MssIngressLutAddressControlRegister_HHD */ +#define AQ_MssIngressLutAddressControlRegister_HHD_baseRegisterAddress 0x8080 +/*! \brief MMD address of structure AQ_MssIngressLutAddressControlRegister_HHD */ +#define AQ_MssIngressLutAddressControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutSelect in AQ_MssIngressLutAddressControlRegister_HHD */ +#define AQ_MssIngressLutAddressControlRegister_HHD_mssIngressLutSelect 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutSelect in AQ_MssIngressLutAddressControlRegister_HHD */ +#define bits_AQ_MssIngressLutAddressControlRegister_HHD_mssIngressLutSelect u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutSelect in AQ_MssIngressLutAddressControlRegister_HHD */ +#define word_AQ_MssIngressLutAddressControlRegister_HHD_mssIngressLutSelect u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutAddress in AQ_MssIngressLutAddressControlRegister_HHD */ +#define AQ_MssIngressLutAddressControlRegister_HHD_mssIngressLutAddress 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutAddress in AQ_MssIngressLutAddressControlRegister_HHD */ +#define bits_AQ_MssIngressLutAddressControlRegister_HHD_mssIngressLutAddress u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutAddress in AQ_MssIngressLutAddressControlRegister_HHD */ +#define word_AQ_MssIngressLutAddressControlRegister_HHD_mssIngressLutAddress u0.word_0 + +/*! \brief Base register address of structure AQ_MssIngressLutControlRegister_HHD */ +#define AQ_MssIngressLutControlRegister_HHD_baseRegisterAddress 0x8081 +/*! \brief MMD address of structure AQ_MssIngressLutControlRegister_HHD */ +#define AQ_MssIngressLutControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutWrite in AQ_MssIngressLutControlRegister_HHD */ +#define AQ_MssIngressLutControlRegister_HHD_mssIngressLutWrite 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutWrite in AQ_MssIngressLutControlRegister_HHD */ +#define bits_AQ_MssIngressLutControlRegister_HHD_mssIngressLutWrite u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutWrite in AQ_MssIngressLutControlRegister_HHD */ +#define word_AQ_MssIngressLutControlRegister_HHD_mssIngressLutWrite u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutRead in AQ_MssIngressLutControlRegister_HHD */ +#define AQ_MssIngressLutControlRegister_HHD_mssIngressLutRead 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutRead in AQ_MssIngressLutControlRegister_HHD */ +#define bits_AQ_MssIngressLutControlRegister_HHD_mssIngressLutRead u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutRead in AQ_MssIngressLutControlRegister_HHD */ +#define word_AQ_MssIngressLutControlRegister_HHD_mssIngressLutRead u0.word_0 + +/*! \brief Base register address of structure AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_baseRegisterAddress 0x80A0 +/*! \brief MMD address of structure AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_0 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_0 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_0 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_1 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_1 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_1 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_1 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_2 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_2 2 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_2 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_2 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_2 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_2 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_3 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_3 3 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_3 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_3 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_3 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_3 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_4 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_4 4 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_4 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_4 u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_4 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_4 u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_5 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_5 5 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_5 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_5 u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_5 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_5 u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_6 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_6 6 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_6 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_6 u6.bits_6 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_6 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_6 u6.word_6 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_7 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_7 7 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_7 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_7 u7.bits_7 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_7 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_7 u7.word_7 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_8 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_8 8 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_8 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_8 u8.bits_8 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_8 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_8 u8.word_8 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_9 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_9 9 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_9 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_9 u9.bits_9 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_9 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_9 u9.word_9 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_10 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_10 10 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_10 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_10 u10.bits_10 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_10 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_10 u10.word_10 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_11 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_11 11 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_11 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_11 u11.bits_11 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_11 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_11 u11.word_11 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_12 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_12 12 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_12 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_12 u12.bits_12 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_12 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_12 u12.word_12 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_13 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_13 13 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_13 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_13 u13.bits_13 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_13 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_13 u13.word_13 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_14 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_14 14 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_14 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_14 u14.bits_14 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_14 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_14 u14.word_14 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_15 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_15 15 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_15 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_15 u15.bits_15 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_15 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_15 u15.word_15 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_16 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_16 16 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_16 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_16 u16.bits_16 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_16 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_16 u16.word_16 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_17 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_17 17 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_17 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_17 u17.bits_17 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_17 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_17 u17.word_17 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_18 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_18 18 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_18 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_18 u18.bits_18 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_18 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_18 u18.word_18 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_19 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_19 19 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_19 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_19 u19.bits_19 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_19 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_19 u19.word_19 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_20 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_20 20 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_20 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_20 u20.bits_20 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_20 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_20 u20.word_20 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_21 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_21 21 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_21 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_21 u21.bits_21 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_21 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_21 u21.word_21 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_22 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_22 22 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_22 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_22 u22.bits_22 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_22 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_22 u22.word_22 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_23 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_23 23 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_23 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_23 u23.bits_23 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_23 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_23 u23.word_23 + +/*! \brief Base register address of structure AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_baseRegisterAddress 0x9004 +/*! \brief MMD address of structure AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLinePhyTxEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLinePhyTxEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLinePhyTxEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLinePhyTxEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLinePhyTxEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLinePhyTxEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxErrorDiscard in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLineRxErrorDiscard 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxErrorDiscard in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineRxErrorDiscard u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxErrorDiscard in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineRxErrorDiscard u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineControlFrameEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLineControlFrameEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineControlFrameEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineControlFrameEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineControlFrameEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineControlFrameEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineSoftReset in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLineSoftReset 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineSoftReset in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineSoftReset u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineSoftReset in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineSoftReset u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxPadEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLineTxPadEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxPadEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineTxPadEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxPadEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineTxPadEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxCrcAppend in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLineTxCrcAppend 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxCrcAppend in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineTxCrcAppend u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxCrcAppend in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineTxCrcAppend u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxAddressInsertEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLineTxAddressInsertEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxAddressInsertEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineTxAddressInsertEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxAddressInsertEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineTxAddressInsertEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLinePauseIgnore in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLinePauseIgnore 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLinePauseIgnore in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLinePauseIgnore u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLinePauseIgnore in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLinePauseIgnore u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLinePauseForward in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLinePauseForward 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLinePauseForward in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLinePauseForward u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLinePauseForward in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLinePauseForward u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineCrcForward in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLineCrcForward 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineCrcForward in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineCrcForward u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineCrcForward in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineCrcForward u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLinePadEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLinePadEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLinePadEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLinePadEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLinePadEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLinePadEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLinePromiscuousMode in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLinePromiscuousMode 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLinePromiscuousMode in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLinePromiscuousMode u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLinePromiscuousMode in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLinePromiscuousMode u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineWanMode in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLineWanMode 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineWanMode in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineWanMode u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineWanMode in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineWanMode u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLineRxEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineRxEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineRxEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLineTxEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineTxEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineTxEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxLowPowerIdleEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLineTxLowPowerIdleEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxLowPowerIdleEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineTxLowPowerIdleEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxLowPowerIdleEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineTxLowPowerIdleEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineSfdCheckDisable in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLineSfdCheckDisable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineSfdCheckDisable in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineSfdCheckDisable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineSfdCheckDisable in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineSfdCheckDisable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure msmLinePriorityFlowControlEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLinePriorityFlowControlEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLinePriorityFlowControlEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLinePriorityFlowControlEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLinePriorityFlowControlEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLinePriorityFlowControlEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineIdleColumnCountExtend in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLineIdleColumnCountExtend 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineIdleColumnCountExtend in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineIdleColumnCountExtend u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineIdleColumnCountExtend in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineIdleColumnCountExtend u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineLengthCheckDisable in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLineLengthCheckDisable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineLengthCheckDisable in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineLengthCheckDisable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineLengthCheckDisable in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineLengthCheckDisable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineForceSendIdle in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLineForceSendIdle 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineForceSendIdle in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineForceSendIdle u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineForceSendIdle in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineForceSendIdle u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineFifoControlRegister_HHD */ +#define AQ_MsmLineFifoControlRegister_HHD_baseRegisterAddress 0x900E +/*! \brief MMD address of structure AQ_MsmLineFifoControlRegister_HHD */ +#define AQ_MsmLineFifoControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxFifoFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoFullThreshold 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxFifoFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define bits_AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoFullThreshold u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxFifoFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define word_AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoFullThreshold u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxFifoEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoEmptyThreshold 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxFifoEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define bits_AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoEmptyThreshold u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxFifoEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define word_AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoEmptyThreshold u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxFifoFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoFullThreshold 2 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxFifoFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define bits_AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoFullThreshold u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxFifoFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define word_AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoFullThreshold u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxFifoEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoEmptyThreshold 3 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxFifoEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define bits_AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoEmptyThreshold u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxFifoEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define word_AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoEmptyThreshold u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxFifoAlmostFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoAlmostFullThreshold 4 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxFifoAlmostFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define bits_AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoAlmostFullThreshold u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxFifoAlmostFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define word_AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoAlmostFullThreshold u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxFifoAlmostEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoAlmostEmptyThreshold 5 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxFifoAlmostEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define bits_AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoAlmostEmptyThreshold u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxFifoAlmostEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define word_AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoAlmostEmptyThreshold u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxFifoAlmostFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoAlmostFullThreshold 6 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxFifoAlmostFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define bits_AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoAlmostFullThreshold u6.bits_6 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxFifoAlmostFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define word_AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoAlmostFullThreshold u6.word_6 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxFifoAlmostEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoAlmostEmptyThreshold 7 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxFifoAlmostEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define bits_AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoAlmostEmptyThreshold u7.bits_7 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxFifoAlmostEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define word_AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoAlmostEmptyThreshold u7.word_7 + +/*! \brief Base register address of structure AQ_MsmLineGeneralStatusRegister_HHD */ +#define AQ_MsmLineGeneralStatusRegister_HHD_baseRegisterAddress 0x9020 +/*! \brief MMD address of structure AQ_MsmLineGeneralStatusRegister_HHD */ +#define AQ_MsmLineGeneralStatusRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxFifoEmpty in AQ_MsmLineGeneralStatusRegister_HHD */ +#define AQ_MsmLineGeneralStatusRegister_HHD_msmLineTxFifoEmpty 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxFifoEmpty in AQ_MsmLineGeneralStatusRegister_HHD */ +#define bits_AQ_MsmLineGeneralStatusRegister_HHD_msmLineTxFifoEmpty u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxFifoEmpty in AQ_MsmLineGeneralStatusRegister_HHD */ +#define word_AQ_MsmLineGeneralStatusRegister_HHD_msmLineTxFifoEmpty u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxLowPowerIdle in AQ_MsmLineGeneralStatusRegister_HHD */ +#define AQ_MsmLineGeneralStatusRegister_HHD_msmLineRxLowPowerIdle 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxLowPowerIdle in AQ_MsmLineGeneralStatusRegister_HHD */ +#define bits_AQ_MsmLineGeneralStatusRegister_HHD_msmLineRxLowPowerIdle u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxLowPowerIdle in AQ_MsmLineGeneralStatusRegister_HHD */ +#define word_AQ_MsmLineGeneralStatusRegister_HHD_msmLineRxLowPowerIdle u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTimestampAvailable in AQ_MsmLineGeneralStatusRegister_HHD */ +#define AQ_MsmLineGeneralStatusRegister_HHD_msmLineTimestampAvailable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTimestampAvailable in AQ_MsmLineGeneralStatusRegister_HHD */ +#define bits_AQ_MsmLineGeneralStatusRegister_HHD_msmLineTimestampAvailable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTimestampAvailable in AQ_MsmLineGeneralStatusRegister_HHD */ +#define word_AQ_MsmLineGeneralStatusRegister_HHD_msmLineTimestampAvailable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLinePhyLossOfSignal in AQ_MsmLineGeneralStatusRegister_HHD */ +#define AQ_MsmLineGeneralStatusRegister_HHD_msmLinePhyLossOfSignal 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLinePhyLossOfSignal in AQ_MsmLineGeneralStatusRegister_HHD */ +#define bits_AQ_MsmLineGeneralStatusRegister_HHD_msmLinePhyLossOfSignal u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLinePhyLossOfSignal in AQ_MsmLineGeneralStatusRegister_HHD */ +#define word_AQ_MsmLineGeneralStatusRegister_HHD_msmLinePhyLossOfSignal u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxRemoteFault in AQ_MsmLineGeneralStatusRegister_HHD */ +#define AQ_MsmLineGeneralStatusRegister_HHD_msmLineRxRemoteFault 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxRemoteFault in AQ_MsmLineGeneralStatusRegister_HHD */ +#define bits_AQ_MsmLineGeneralStatusRegister_HHD_msmLineRxRemoteFault u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxRemoteFault in AQ_MsmLineGeneralStatusRegister_HHD */ +#define word_AQ_MsmLineGeneralStatusRegister_HHD_msmLineRxRemoteFault u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxLocalFault in AQ_MsmLineGeneralStatusRegister_HHD */ +#define AQ_MsmLineGeneralStatusRegister_HHD_msmLineRxLocalFault 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxLocalFault in AQ_MsmLineGeneralStatusRegister_HHD */ +#define bits_AQ_MsmLineGeneralStatusRegister_HHD_msmLineRxLocalFault u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxLocalFault in AQ_MsmLineGeneralStatusRegister_HHD */ +#define word_AQ_MsmLineGeneralStatusRegister_HHD_msmLineRxLocalFault u0.word_0 + +/*! \brief Base register address of structure AQ_MsmLineTxIpgControlRegister_HHD */ +#define AQ_MsmLineTxIpgControlRegister_HHD_baseRegisterAddress 0x9022 +/*! \brief MMD address of structure AQ_MsmLineTxIpgControlRegister_HHD */ +#define AQ_MsmLineTxIpgControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxIpgLength in AQ_MsmLineTxIpgControlRegister_HHD */ +#define AQ_MsmLineTxIpgControlRegister_HHD_msmLineTxIpgLength 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxIpgLength in AQ_MsmLineTxIpgControlRegister_HHD */ +#define bits_AQ_MsmLineTxIpgControlRegister_HHD_msmLineTxIpgLength u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxIpgLength in AQ_MsmLineTxIpgControlRegister_HHD */ +#define word_AQ_MsmLineTxIpgControlRegister_HHD_msmLineTxIpgLength u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxIpgReserved in AQ_MsmLineTxIpgControlRegister_HHD */ +#define AQ_MsmLineTxIpgControlRegister_HHD_msmLineTxIpgReserved 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxIpgReserved in AQ_MsmLineTxIpgControlRegister_HHD */ +#define bits_AQ_MsmLineTxIpgControlRegister_HHD_msmLineTxIpgReserved u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxIpgReserved in AQ_MsmLineTxIpgControlRegister_HHD */ +#define word_AQ_MsmLineTxIpgControlRegister_HHD_msmLineTxIpgReserved u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineTxGoodFramesCounterRegister_HHD */ +#define AQ_MsmLineTxGoodFramesCounterRegister_HHD_baseRegisterAddress 0x9040 +/*! \brief MMD address of structure AQ_MsmLineTxGoodFramesCounterRegister_HHD */ +#define AQ_MsmLineTxGoodFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxGoodFramesCounter_0 in AQ_MsmLineTxGoodFramesCounterRegister_HHD */ +#define AQ_MsmLineTxGoodFramesCounterRegister_HHD_msmLineTxGoodFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxGoodFramesCounter_0 in AQ_MsmLineTxGoodFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineTxGoodFramesCounterRegister_HHD_msmLineTxGoodFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxGoodFramesCounter_0 in AQ_MsmLineTxGoodFramesCounterRegister_HHD */ +#define word_AQ_MsmLineTxGoodFramesCounterRegister_HHD_msmLineTxGoodFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxGoodFramesCounter_1 in AQ_MsmLineTxGoodFramesCounterRegister_HHD */ +#define AQ_MsmLineTxGoodFramesCounterRegister_HHD_msmLineTxGoodFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxGoodFramesCounter_1 in AQ_MsmLineTxGoodFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineTxGoodFramesCounterRegister_HHD_msmLineTxGoodFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxGoodFramesCounter_1 in AQ_MsmLineTxGoodFramesCounterRegister_HHD */ +#define word_AQ_MsmLineTxGoodFramesCounterRegister_HHD_msmLineTxGoodFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineRxGoodFramesCounterRegister_HHD */ +#define AQ_MsmLineRxGoodFramesCounterRegister_HHD_baseRegisterAddress 0x9044 +/*! \brief MMD address of structure AQ_MsmLineRxGoodFramesCounterRegister_HHD */ +#define AQ_MsmLineRxGoodFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxGoodFramesCounter_0 in AQ_MsmLineRxGoodFramesCounterRegister_HHD */ +#define AQ_MsmLineRxGoodFramesCounterRegister_HHD_msmLineRxGoodFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxGoodFramesCounter_0 in AQ_MsmLineRxGoodFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineRxGoodFramesCounterRegister_HHD_msmLineRxGoodFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxGoodFramesCounter_0 in AQ_MsmLineRxGoodFramesCounterRegister_HHD */ +#define word_AQ_MsmLineRxGoodFramesCounterRegister_HHD_msmLineRxGoodFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxGoodFramesCounter_1 in AQ_MsmLineRxGoodFramesCounterRegister_HHD */ +#define AQ_MsmLineRxGoodFramesCounterRegister_HHD_msmLineRxGoodFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxGoodFramesCounter_1 in AQ_MsmLineRxGoodFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineRxGoodFramesCounterRegister_HHD_msmLineRxGoodFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxGoodFramesCounter_1 in AQ_MsmLineRxGoodFramesCounterRegister_HHD */ +#define word_AQ_MsmLineRxGoodFramesCounterRegister_HHD_msmLineRxGoodFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineRxFcsErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxFcsErrorsCounterRegister_HHD_baseRegisterAddress 0x9048 +/*! \brief MMD address of structure AQ_MsmLineRxFcsErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxFcsErrorsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineFcsErrorCounter_0 in AQ_MsmLineRxFcsErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxFcsErrorsCounterRegister_HHD_msmLineFcsErrorCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineFcsErrorCounter_0 in AQ_MsmLineRxFcsErrorsCounterRegister_HHD */ +#define bits_AQ_MsmLineRxFcsErrorsCounterRegister_HHD_msmLineFcsErrorCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineFcsErrorCounter_0 in AQ_MsmLineRxFcsErrorsCounterRegister_HHD */ +#define word_AQ_MsmLineRxFcsErrorsCounterRegister_HHD_msmLineFcsErrorCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineFcsErrorCounter_1 in AQ_MsmLineRxFcsErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxFcsErrorsCounterRegister_HHD_msmLineFcsErrorCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineFcsErrorCounter_1 in AQ_MsmLineRxFcsErrorsCounterRegister_HHD */ +#define bits_AQ_MsmLineRxFcsErrorsCounterRegister_HHD_msmLineFcsErrorCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineFcsErrorCounter_1 in AQ_MsmLineRxFcsErrorsCounterRegister_HHD */ +#define word_AQ_MsmLineRxFcsErrorsCounterRegister_HHD_msmLineFcsErrorCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD_baseRegisterAddress 0x904C +/*! \brief MMD address of structure AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineAlignmentErrorCounter_0 in AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD_msmLineAlignmentErrorCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineAlignmentErrorCounter_0 in AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD */ +#define bits_AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD_msmLineAlignmentErrorCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineAlignmentErrorCounter_0 in AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD */ +#define word_AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD_msmLineAlignmentErrorCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineAlignmentErrorCounter_1 in AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD_msmLineAlignmentErrorCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineAlignmentErrorCounter_1 in AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD */ +#define bits_AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD_msmLineAlignmentErrorCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineAlignmentErrorCounter_1 in AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD */ +#define word_AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD_msmLineAlignmentErrorCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineTxPauseFramesCounterRegister_HHD */ +#define AQ_MsmLineTxPauseFramesCounterRegister_HHD_baseRegisterAddress 0x9050 +/*! \brief MMD address of structure AQ_MsmLineTxPauseFramesCounterRegister_HHD */ +#define AQ_MsmLineTxPauseFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxPauseFramesCounter_0 in AQ_MsmLineTxPauseFramesCounterRegister_HHD */ +#define AQ_MsmLineTxPauseFramesCounterRegister_HHD_msmLineTxPauseFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxPauseFramesCounter_0 in AQ_MsmLineTxPauseFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineTxPauseFramesCounterRegister_HHD_msmLineTxPauseFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxPauseFramesCounter_0 in AQ_MsmLineTxPauseFramesCounterRegister_HHD */ +#define word_AQ_MsmLineTxPauseFramesCounterRegister_HHD_msmLineTxPauseFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxPauseFramesCounter_1 in AQ_MsmLineTxPauseFramesCounterRegister_HHD */ +#define AQ_MsmLineTxPauseFramesCounterRegister_HHD_msmLineTxPauseFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxPauseFramesCounter_1 in AQ_MsmLineTxPauseFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineTxPauseFramesCounterRegister_HHD_msmLineTxPauseFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxPauseFramesCounter_1 in AQ_MsmLineTxPauseFramesCounterRegister_HHD */ +#define word_AQ_MsmLineTxPauseFramesCounterRegister_HHD_msmLineTxPauseFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineRxPauseFramesCounterRegister_HHD */ +#define AQ_MsmLineRxPauseFramesCounterRegister_HHD_baseRegisterAddress 0x9054 +/*! \brief MMD address of structure AQ_MsmLineRxPauseFramesCounterRegister_HHD */ +#define AQ_MsmLineRxPauseFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxPauseFramesCounter_0 in AQ_MsmLineRxPauseFramesCounterRegister_HHD */ +#define AQ_MsmLineRxPauseFramesCounterRegister_HHD_msmLineRxPauseFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxPauseFramesCounter_0 in AQ_MsmLineRxPauseFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineRxPauseFramesCounterRegister_HHD_msmLineRxPauseFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxPauseFramesCounter_0 in AQ_MsmLineRxPauseFramesCounterRegister_HHD */ +#define word_AQ_MsmLineRxPauseFramesCounterRegister_HHD_msmLineRxPauseFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxPauseFramesCounter_1 in AQ_MsmLineRxPauseFramesCounterRegister_HHD */ +#define AQ_MsmLineRxPauseFramesCounterRegister_HHD_msmLineRxPauseFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxPauseFramesCounter_1 in AQ_MsmLineRxPauseFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineRxPauseFramesCounterRegister_HHD_msmLineRxPauseFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxPauseFramesCounter_1 in AQ_MsmLineRxPauseFramesCounterRegister_HHD */ +#define word_AQ_MsmLineRxPauseFramesCounterRegister_HHD_msmLineRxPauseFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineRxTooLongErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxTooLongErrorsCounterRegister_HHD_baseRegisterAddress 0x9058 +/*! \brief MMD address of structure AQ_MsmLineRxTooLongErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxTooLongErrorsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxTooLongErrorsCounter_0 in AQ_MsmLineRxTooLongErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxTooLongErrorsCounterRegister_HHD_msmLineRxTooLongErrorsCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxTooLongErrorsCounter_0 in AQ_MsmLineRxTooLongErrorsCounterRegister_HHD */ +#define bits_AQ_MsmLineRxTooLongErrorsCounterRegister_HHD_msmLineRxTooLongErrorsCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxTooLongErrorsCounter_0 in AQ_MsmLineRxTooLongErrorsCounterRegister_HHD */ +#define word_AQ_MsmLineRxTooLongErrorsCounterRegister_HHD_msmLineRxTooLongErrorsCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxTooLongErrorsCounter_1 in AQ_MsmLineRxTooLongErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxTooLongErrorsCounterRegister_HHD_msmLineRxTooLongErrorsCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxTooLongErrorsCounter_1 in AQ_MsmLineRxTooLongErrorsCounterRegister_HHD */ +#define bits_AQ_MsmLineRxTooLongErrorsCounterRegister_HHD_msmLineRxTooLongErrorsCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxTooLongErrorsCounter_1 in AQ_MsmLineRxTooLongErrorsCounterRegister_HHD */ +#define word_AQ_MsmLineRxTooLongErrorsCounterRegister_HHD_msmLineRxTooLongErrorsCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD_baseRegisterAddress 0x905C +/*! \brief MMD address of structure AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxInRangeLengthErrorsCounter_0 in AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD_msmLineRxInRangeLengthErrorsCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxInRangeLengthErrorsCounter_0 in AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD */ +#define bits_AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD_msmLineRxInRangeLengthErrorsCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxInRangeLengthErrorsCounter_0 in AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD */ +#define word_AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD_msmLineRxInRangeLengthErrorsCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxInRangeLengthErrorsCounter_1 in AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD_msmLineRxInRangeLengthErrorsCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxInRangeLengthErrorsCounter_1 in AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD */ +#define bits_AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD_msmLineRxInRangeLengthErrorsCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxInRangeLengthErrorsCounter_1 in AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD */ +#define word_AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD_msmLineRxInRangeLengthErrorsCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineTxVlanFramesCounterRegister_HHD */ +#define AQ_MsmLineTxVlanFramesCounterRegister_HHD_baseRegisterAddress 0x9060 +/*! \brief MMD address of structure AQ_MsmLineTxVlanFramesCounterRegister_HHD */ +#define AQ_MsmLineTxVlanFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxVlanFramesCounter_0 in AQ_MsmLineTxVlanFramesCounterRegister_HHD */ +#define AQ_MsmLineTxVlanFramesCounterRegister_HHD_msmLineTxVlanFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxVlanFramesCounter_0 in AQ_MsmLineTxVlanFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineTxVlanFramesCounterRegister_HHD_msmLineTxVlanFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxVlanFramesCounter_0 in AQ_MsmLineTxVlanFramesCounterRegister_HHD */ +#define word_AQ_MsmLineTxVlanFramesCounterRegister_HHD_msmLineTxVlanFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxVlanFramesCounter_1 in AQ_MsmLineTxVlanFramesCounterRegister_HHD */ +#define AQ_MsmLineTxVlanFramesCounterRegister_HHD_msmLineTxVlanFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxVlanFramesCounter_1 in AQ_MsmLineTxVlanFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineTxVlanFramesCounterRegister_HHD_msmLineTxVlanFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxVlanFramesCounter_1 in AQ_MsmLineTxVlanFramesCounterRegister_HHD */ +#define word_AQ_MsmLineTxVlanFramesCounterRegister_HHD_msmLineTxVlanFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineRxVlanFramesCounterRegister_HHD */ +#define AQ_MsmLineRxVlanFramesCounterRegister_HHD_baseRegisterAddress 0x9064 +/*! \brief MMD address of structure AQ_MsmLineRxVlanFramesCounterRegister_HHD */ +#define AQ_MsmLineRxVlanFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxVlanFramesCounter_0 in AQ_MsmLineRxVlanFramesCounterRegister_HHD */ +#define AQ_MsmLineRxVlanFramesCounterRegister_HHD_msmLineRxVlanFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxVlanFramesCounter_0 in AQ_MsmLineRxVlanFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineRxVlanFramesCounterRegister_HHD_msmLineRxVlanFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxVlanFramesCounter_0 in AQ_MsmLineRxVlanFramesCounterRegister_HHD */ +#define word_AQ_MsmLineRxVlanFramesCounterRegister_HHD_msmLineRxVlanFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxVlanFramesCounter_1 in AQ_MsmLineRxVlanFramesCounterRegister_HHD */ +#define AQ_MsmLineRxVlanFramesCounterRegister_HHD_msmLineRxVlanFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxVlanFramesCounter_1 in AQ_MsmLineRxVlanFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineRxVlanFramesCounterRegister_HHD_msmLineRxVlanFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxVlanFramesCounter_1 in AQ_MsmLineRxVlanFramesCounterRegister_HHD */ +#define word_AQ_MsmLineRxVlanFramesCounterRegister_HHD_msmLineRxVlanFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineTxOctetsCounterRegister_HHD */ +#define AQ_MsmLineTxOctetsCounterRegister_HHD_baseRegisterAddress 0x9068 +/*! \brief MMD address of structure AQ_MsmLineTxOctetsCounterRegister_HHD */ +#define AQ_MsmLineTxOctetsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxOctetsCounter_0 in AQ_MsmLineTxOctetsCounterRegister_HHD */ +#define AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxOctetsCounter_0 in AQ_MsmLineTxOctetsCounterRegister_HHD */ +#define bits_AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxOctetsCounter_0 in AQ_MsmLineTxOctetsCounterRegister_HHD */ +#define word_AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxOctetsCounter_1 in AQ_MsmLineTxOctetsCounterRegister_HHD */ +#define AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxOctetsCounter_1 in AQ_MsmLineTxOctetsCounterRegister_HHD */ +#define bits_AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxOctetsCounter_1 in AQ_MsmLineTxOctetsCounterRegister_HHD */ +#define word_AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_1 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxOctetsCounter_2 in AQ_MsmLineTxOctetsCounterRegister_HHD */ +#define AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_2 2 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxOctetsCounter_2 in AQ_MsmLineTxOctetsCounterRegister_HHD */ +#define bits_AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_2 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxOctetsCounter_2 in AQ_MsmLineTxOctetsCounterRegister_HHD */ +#define word_AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_2 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxOctetsCounter_3 in AQ_MsmLineTxOctetsCounterRegister_HHD */ +#define AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_3 3 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxOctetsCounter_3 in AQ_MsmLineTxOctetsCounterRegister_HHD */ +#define bits_AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_3 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxOctetsCounter_3 in AQ_MsmLineTxOctetsCounterRegister_HHD */ +#define word_AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_3 u3.word_3 + +/*! \brief Base register address of structure AQ_MsmLineRxOctetsCounterRegister_HHD */ +#define AQ_MsmLineRxOctetsCounterRegister_HHD_baseRegisterAddress 0x906C +/*! \brief MMD address of structure AQ_MsmLineRxOctetsCounterRegister_HHD */ +#define AQ_MsmLineRxOctetsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxOctetsCounter_0 in AQ_MsmLineRxOctetsCounterRegister_HHD */ +#define AQ_MsmLineRxOctetsCounterRegister_HHD_msmLineRxOctetsCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxOctetsCounter_0 in AQ_MsmLineRxOctetsCounterRegister_HHD */ +#define bits_AQ_MsmLineRxOctetsCounterRegister_HHD_msmLineRxOctetsCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxOctetsCounter_0 in AQ_MsmLineRxOctetsCounterRegister_HHD */ +#define word_AQ_MsmLineRxOctetsCounterRegister_HHD_msmLineRxOctetsCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxOctetsCounter_1 in AQ_MsmLineRxOctetsCounterRegister_HHD */ +#define AQ_MsmLineRxOctetsCounterRegister_HHD_msmLineRxOctetsCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxOctetsCounter_1 in AQ_MsmLineRxOctetsCounterRegister_HHD */ +#define bits_AQ_MsmLineRxOctetsCounterRegister_HHD_msmLineRxOctetsCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxOctetsCounter_1 in AQ_MsmLineRxOctetsCounterRegister_HHD */ +#define word_AQ_MsmLineRxOctetsCounterRegister_HHD_msmLineRxOctetsCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineRxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmLineRxUnicastFramesCounterRegister_HHD_baseRegisterAddress 0x9070 +/*! \brief MMD address of structure AQ_MsmLineRxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmLineRxUnicastFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxUnicastFramesCounter_0 in AQ_MsmLineRxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmLineRxUnicastFramesCounterRegister_HHD_msmLineRxUnicastFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxUnicastFramesCounter_0 in AQ_MsmLineRxUnicastFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineRxUnicastFramesCounterRegister_HHD_msmLineRxUnicastFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxUnicastFramesCounter_0 in AQ_MsmLineRxUnicastFramesCounterRegister_HHD */ +#define word_AQ_MsmLineRxUnicastFramesCounterRegister_HHD_msmLineRxUnicastFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxUnicastFramesCounter_1 in AQ_MsmLineRxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmLineRxUnicastFramesCounterRegister_HHD_msmLineRxUnicastFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxUnicastFramesCounter_1 in AQ_MsmLineRxUnicastFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineRxUnicastFramesCounterRegister_HHD_msmLineRxUnicastFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxUnicastFramesCounter_1 in AQ_MsmLineRxUnicastFramesCounterRegister_HHD */ +#define word_AQ_MsmLineRxUnicastFramesCounterRegister_HHD_msmLineRxUnicastFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineRxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmLineRxMulticastFramesCounterRegister_HHD_baseRegisterAddress 0x9074 +/*! \brief MMD address of structure AQ_MsmLineRxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmLineRxMulticastFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxMulticastFramesCounter_0 in AQ_MsmLineRxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmLineRxMulticastFramesCounterRegister_HHD_msmLineRxMulticastFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxMulticastFramesCounter_0 in AQ_MsmLineRxMulticastFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineRxMulticastFramesCounterRegister_HHD_msmLineRxMulticastFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxMulticastFramesCounter_0 in AQ_MsmLineRxMulticastFramesCounterRegister_HHD */ +#define word_AQ_MsmLineRxMulticastFramesCounterRegister_HHD_msmLineRxMulticastFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxMulticastFramesCounter_1 in AQ_MsmLineRxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmLineRxMulticastFramesCounterRegister_HHD_msmLineRxMulticastFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxMulticastFramesCounter_1 in AQ_MsmLineRxMulticastFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineRxMulticastFramesCounterRegister_HHD_msmLineRxMulticastFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxMulticastFramesCounter_1 in AQ_MsmLineRxMulticastFramesCounterRegister_HHD */ +#define word_AQ_MsmLineRxMulticastFramesCounterRegister_HHD_msmLineRxMulticastFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineRxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmLineRxBroadcastFramesCounterRegister_HHD_baseRegisterAddress 0x9078 +/*! \brief MMD address of structure AQ_MsmLineRxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmLineRxBroadcastFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxBroadcastFramesCounter_0 in AQ_MsmLineRxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmLineRxBroadcastFramesCounterRegister_HHD_msmLineRxBroadcastFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxBroadcastFramesCounter_0 in AQ_MsmLineRxBroadcastFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineRxBroadcastFramesCounterRegister_HHD_msmLineRxBroadcastFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxBroadcastFramesCounter_0 in AQ_MsmLineRxBroadcastFramesCounterRegister_HHD */ +#define word_AQ_MsmLineRxBroadcastFramesCounterRegister_HHD_msmLineRxBroadcastFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxBroadcastFramesCounter_1 in AQ_MsmLineRxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmLineRxBroadcastFramesCounterRegister_HHD_msmLineRxBroadcastFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxBroadcastFramesCounter_1 in AQ_MsmLineRxBroadcastFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineRxBroadcastFramesCounterRegister_HHD_msmLineRxBroadcastFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxBroadcastFramesCounter_1 in AQ_MsmLineRxBroadcastFramesCounterRegister_HHD */ +#define word_AQ_MsmLineRxBroadcastFramesCounterRegister_HHD_msmLineRxBroadcastFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineTxErrorsCounterRegister_HHD */ +#define AQ_MsmLineTxErrorsCounterRegister_HHD_baseRegisterAddress 0x907C +/*! \brief MMD address of structure AQ_MsmLineTxErrorsCounterRegister_HHD */ +#define AQ_MsmLineTxErrorsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxErrorsCounter_0 in AQ_MsmLineTxErrorsCounterRegister_HHD */ +#define AQ_MsmLineTxErrorsCounterRegister_HHD_msmLineTxErrorsCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxErrorsCounter_0 in AQ_MsmLineTxErrorsCounterRegister_HHD */ +#define bits_AQ_MsmLineTxErrorsCounterRegister_HHD_msmLineTxErrorsCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxErrorsCounter_0 in AQ_MsmLineTxErrorsCounterRegister_HHD */ +#define word_AQ_MsmLineTxErrorsCounterRegister_HHD_msmLineTxErrorsCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxErrorsCounter_1 in AQ_MsmLineTxErrorsCounterRegister_HHD */ +#define AQ_MsmLineTxErrorsCounterRegister_HHD_msmLineTxErrorsCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxErrorsCounter_1 in AQ_MsmLineTxErrorsCounterRegister_HHD */ +#define bits_AQ_MsmLineTxErrorsCounterRegister_HHD_msmLineTxErrorsCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxErrorsCounter_1 in AQ_MsmLineTxErrorsCounterRegister_HHD */ +#define word_AQ_MsmLineTxErrorsCounterRegister_HHD_msmLineTxErrorsCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineTxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmLineTxUnicastFramesCounterRegister_HHD_baseRegisterAddress 0x9084 +/*! \brief MMD address of structure AQ_MsmLineTxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmLineTxUnicastFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxUnicastFramesCounter_0 in AQ_MsmLineTxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmLineTxUnicastFramesCounterRegister_HHD_msmLineTxUnicastFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxUnicastFramesCounter_0 in AQ_MsmLineTxUnicastFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineTxUnicastFramesCounterRegister_HHD_msmLineTxUnicastFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxUnicastFramesCounter_0 in AQ_MsmLineTxUnicastFramesCounterRegister_HHD */ +#define word_AQ_MsmLineTxUnicastFramesCounterRegister_HHD_msmLineTxUnicastFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxUnicastFramesCounter_1 in AQ_MsmLineTxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmLineTxUnicastFramesCounterRegister_HHD_msmLineTxUnicastFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxUnicastFramesCounter_1 in AQ_MsmLineTxUnicastFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineTxUnicastFramesCounterRegister_HHD_msmLineTxUnicastFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxUnicastFramesCounter_1 in AQ_MsmLineTxUnicastFramesCounterRegister_HHD */ +#define word_AQ_MsmLineTxUnicastFramesCounterRegister_HHD_msmLineTxUnicastFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineTxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmLineTxMulticastFramesCounterRegister_HHD_baseRegisterAddress 0x9088 +/*! \brief MMD address of structure AQ_MsmLineTxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmLineTxMulticastFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxMulticastFramesCounter_0 in AQ_MsmLineTxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmLineTxMulticastFramesCounterRegister_HHD_msmLineTxMulticastFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxMulticastFramesCounter_0 in AQ_MsmLineTxMulticastFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineTxMulticastFramesCounterRegister_HHD_msmLineTxMulticastFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxMulticastFramesCounter_0 in AQ_MsmLineTxMulticastFramesCounterRegister_HHD */ +#define word_AQ_MsmLineTxMulticastFramesCounterRegister_HHD_msmLineTxMulticastFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxMulticastFramesCounter_1 in AQ_MsmLineTxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmLineTxMulticastFramesCounterRegister_HHD_msmLineTxMulticastFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxMulticastFramesCounter_1 in AQ_MsmLineTxMulticastFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineTxMulticastFramesCounterRegister_HHD_msmLineTxMulticastFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxMulticastFramesCounter_1 in AQ_MsmLineTxMulticastFramesCounterRegister_HHD */ +#define word_AQ_MsmLineTxMulticastFramesCounterRegister_HHD_msmLineTxMulticastFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineTxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmLineTxBroadcastFramesCounterRegister_HHD_baseRegisterAddress 0x908C +/*! \brief MMD address of structure AQ_MsmLineTxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmLineTxBroadcastFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxBroadcastFramesCounter_0 in AQ_MsmLineTxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmLineTxBroadcastFramesCounterRegister_HHD_msmLineTxBroadcastFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxBroadcastFramesCounter_0 in AQ_MsmLineTxBroadcastFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineTxBroadcastFramesCounterRegister_HHD_msmLineTxBroadcastFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxBroadcastFramesCounter_0 in AQ_MsmLineTxBroadcastFramesCounterRegister_HHD */ +#define word_AQ_MsmLineTxBroadcastFramesCounterRegister_HHD_msmLineTxBroadcastFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxBroadcastFramesCounter_1 in AQ_MsmLineTxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmLineTxBroadcastFramesCounterRegister_HHD_msmLineTxBroadcastFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxBroadcastFramesCounter_1 in AQ_MsmLineTxBroadcastFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineTxBroadcastFramesCounterRegister_HHD_msmLineTxBroadcastFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxBroadcastFramesCounter_1 in AQ_MsmLineTxBroadcastFramesCounterRegister_HHD */ +#define word_AQ_MsmLineTxBroadcastFramesCounterRegister_HHD_msmLineTxBroadcastFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineRxErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxErrorsCounterRegister_HHD_baseRegisterAddress 0x90C8 +/*! \brief MMD address of structure AQ_MsmLineRxErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxErrorsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxErrorsCounter_0 in AQ_MsmLineRxErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxErrorsCounterRegister_HHD_msmLineRxErrorsCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxErrorsCounter_0 in AQ_MsmLineRxErrorsCounterRegister_HHD */ +#define bits_AQ_MsmLineRxErrorsCounterRegister_HHD_msmLineRxErrorsCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxErrorsCounter_0 in AQ_MsmLineRxErrorsCounterRegister_HHD */ +#define word_AQ_MsmLineRxErrorsCounterRegister_HHD_msmLineRxErrorsCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxErrorsCounter_1 in AQ_MsmLineRxErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxErrorsCounterRegister_HHD_msmLineRxErrorsCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxErrorsCounter_1 in AQ_MsmLineRxErrorsCounterRegister_HHD */ +#define bits_AQ_MsmLineRxErrorsCounterRegister_HHD_msmLineRxErrorsCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxErrorsCounter_1 in AQ_MsmLineRxErrorsCounterRegister_HHD */ +#define word_AQ_MsmLineRxErrorsCounterRegister_HHD_msmLineRxErrorsCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_GlobalControl_HHD */ +#define AQ_GlobalControl_HHD_baseRegisterAddress 0xC000 +/*! \brief MMD address of structure AQ_GlobalControl_HHD */ +#define AQ_GlobalControl_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure upReset in AQ_GlobalControl_HHD */ +#define AQ_GlobalControl_HHD_upReset 1 +/*! \brief Preprocessor variable to relate field to bit position in structure upReset in AQ_GlobalControl_HHD */ +#define bits_AQ_GlobalControl_HHD_upReset u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure upReset in AQ_GlobalControl_HHD */ +#define word_AQ_GlobalControl_HHD_upReset u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure upRunStallOverride in AQ_GlobalControl_HHD */ +#define AQ_GlobalControl_HHD_upRunStallOverride 1 +/*! \brief Preprocessor variable to relate field to bit position in structure upRunStallOverride in AQ_GlobalControl_HHD */ +#define bits_AQ_GlobalControl_HHD_upRunStallOverride u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure upRunStallOverride in AQ_GlobalControl_HHD */ +#define word_AQ_GlobalControl_HHD_upRunStallOverride u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure upRunStall in AQ_GlobalControl_HHD */ +#define AQ_GlobalControl_HHD_upRunStall 1 +/*! \brief Preprocessor variable to relate field to bit position in structure upRunStall in AQ_GlobalControl_HHD */ +#define bits_AQ_GlobalControl_HHD_upRunStall u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure upRunStall in AQ_GlobalControl_HHD */ +#define word_AQ_GlobalControl_HHD_upRunStall u1.word_1 + +/*! \brief Base register address of structure AQ_GlobalResetControl_HHD */ +#define AQ_GlobalResetControl_HHD_baseRegisterAddress 0xC006 +/*! \brief MMD address of structure AQ_GlobalResetControl_HHD */ +#define AQ_GlobalResetControl_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure globalMMD_ResetDisable in AQ_GlobalResetControl_HHD */ +#define AQ_GlobalResetControl_HHD_globalMMD_ResetDisable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure globalMMD_ResetDisable in AQ_GlobalResetControl_HHD */ +#define bits_AQ_GlobalResetControl_HHD_globalMMD_ResetDisable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure globalMMD_ResetDisable in AQ_GlobalResetControl_HHD */ +#define word_AQ_GlobalResetControl_HHD_globalMMD_ResetDisable u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalDiagnosticProvisioning_HHD */ +#define AQ_GlobalDiagnosticProvisioning_HHD_baseRegisterAddress 0xC400 +/*! \brief MMD address of structure AQ_GlobalDiagnosticProvisioning_HHD */ +#define AQ_GlobalDiagnosticProvisioning_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure enableDiagnostics in AQ_GlobalDiagnosticProvisioning_HHD */ +#define AQ_GlobalDiagnosticProvisioning_HHD_enableDiagnostics 0 +/*! \brief Preprocessor variable to relate field to bit position in structure enableDiagnostics in AQ_GlobalDiagnosticProvisioning_HHD */ +#define bits_AQ_GlobalDiagnosticProvisioning_HHD_enableDiagnostics u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure enableDiagnostics in AQ_GlobalDiagnosticProvisioning_HHD */ +#define word_AQ_GlobalDiagnosticProvisioning_HHD_enableDiagnostics u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalThermalProvisioning_HHD */ +#define AQ_GlobalThermalProvisioning_HHD_baseRegisterAddress 0xC420 +/*! \brief MMD address of structure AQ_GlobalThermalProvisioning_HHD */ +#define AQ_GlobalThermalProvisioning_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure reserved_0 in AQ_GlobalThermalProvisioning_HHD */ +#define AQ_GlobalThermalProvisioning_HHD_reserved_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_0 in AQ_GlobalThermalProvisioning_HHD */ +#define bits_AQ_GlobalThermalProvisioning_HHD_reserved_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_0 in AQ_GlobalThermalProvisioning_HHD */ +#define word_AQ_GlobalThermalProvisioning_HHD_reserved_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure highTempFailureThreshold in AQ_GlobalThermalProvisioning_HHD */ +#define AQ_GlobalThermalProvisioning_HHD_highTempFailureThreshold 1 +/*! \brief Preprocessor variable to relate field to bit position in structure highTempFailureThreshold in AQ_GlobalThermalProvisioning_HHD */ +#define bits_AQ_GlobalThermalProvisioning_HHD_highTempFailureThreshold u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure highTempFailureThreshold in AQ_GlobalThermalProvisioning_HHD */ +#define word_AQ_GlobalThermalProvisioning_HHD_highTempFailureThreshold u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure lowTempFailureThreshold in AQ_GlobalThermalProvisioning_HHD */ +#define AQ_GlobalThermalProvisioning_HHD_lowTempFailureThreshold 2 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTempFailureThreshold in AQ_GlobalThermalProvisioning_HHD */ +#define bits_AQ_GlobalThermalProvisioning_HHD_lowTempFailureThreshold u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure lowTempFailureThreshold in AQ_GlobalThermalProvisioning_HHD */ +#define word_AQ_GlobalThermalProvisioning_HHD_lowTempFailureThreshold u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure highTempWarningThreshold in AQ_GlobalThermalProvisioning_HHD */ +#define AQ_GlobalThermalProvisioning_HHD_highTempWarningThreshold 3 +/*! \brief Preprocessor variable to relate field to bit position in structure highTempWarningThreshold in AQ_GlobalThermalProvisioning_HHD */ +#define bits_AQ_GlobalThermalProvisioning_HHD_highTempWarningThreshold u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure highTempWarningThreshold in AQ_GlobalThermalProvisioning_HHD */ +#define word_AQ_GlobalThermalProvisioning_HHD_highTempWarningThreshold u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure lowTempWarningThreshold in AQ_GlobalThermalProvisioning_HHD */ +#define AQ_GlobalThermalProvisioning_HHD_lowTempWarningThreshold 4 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTempWarningThreshold in AQ_GlobalThermalProvisioning_HHD */ +#define bits_AQ_GlobalThermalProvisioning_HHD_lowTempWarningThreshold u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure lowTempWarningThreshold in AQ_GlobalThermalProvisioning_HHD */ +#define word_AQ_GlobalThermalProvisioning_HHD_lowTempWarningThreshold u4.word_4 + +/*! \brief Base register address of structure AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_baseRegisterAddress 0xC430 +/*! \brief MMD address of structure AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioningC430 in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_reservedProvisioningC430 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioningC430 in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_reservedProvisioningC430 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioningC430 in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_reservedProvisioningC430 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_0ManualSet in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_0ManualSet 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0ManualSet in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_0ManualSet u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0ManualSet in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_0ManualSet u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_0_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_0_10Gb_sLinkEstablished 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_0_10Gb_sLinkEstablished u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_0_10Gb_sLinkEstablished u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_0_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_0_1Gb_sLinkEstablished 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_0_1Gb_sLinkEstablished u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_0_1Gb_sLinkEstablished u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_0_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_0_100Mb_sLinkEstablished 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_0_100Mb_sLinkEstablished u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_0_100Mb_sLinkEstablished u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_0Connecting in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_0Connecting 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0Connecting in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_0Connecting u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0Connecting in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_0Connecting u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_0ReceiveActivity in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_0ReceiveActivity 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0ReceiveActivity in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_0ReceiveActivity u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0ReceiveActivity in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_0ReceiveActivity u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_0TransmitActivity in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_0TransmitActivity 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0TransmitActivity in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_0TransmitActivity u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0TransmitActivity in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_0TransmitActivity u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_0ActivityStretch in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_0ActivityStretch 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0ActivityStretch in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_0ActivityStretch u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0ActivityStretch in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_0ActivityStretch u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioningC431 in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_reservedProvisioningC431 1 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioningC431 in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_reservedProvisioningC431 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioningC431 in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_reservedProvisioningC431 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_1ManualSet in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_1ManualSet 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1ManualSet in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_1ManualSet u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1ManualSet in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_1ManualSet u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_1_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_1_10Gb_sLinkEstablished 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_1_10Gb_sLinkEstablished u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_1_10Gb_sLinkEstablished u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_1_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_1_1Gb_sLinkEstablished 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_1_1Gb_sLinkEstablished u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_1_1Gb_sLinkEstablished u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_1_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_1_100Mb_sLinkEstablished 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_1_100Mb_sLinkEstablished u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_1_100Mb_sLinkEstablished u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_1Connecting in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_1Connecting 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1Connecting in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_1Connecting u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1Connecting in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_1Connecting u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_1ReceiveActivity in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_1ReceiveActivity 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1ReceiveActivity in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_1ReceiveActivity u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1ReceiveActivity in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_1ReceiveActivity u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_1TransmitActivity in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_1TransmitActivity 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1TransmitActivity in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_1TransmitActivity u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1TransmitActivity in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_1TransmitActivity u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_1ActivityStretch in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_1ActivityStretch 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1ActivityStretch in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_1ActivityStretch u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1ActivityStretch in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_1ActivityStretch u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioningC432 in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_reservedProvisioningC432 2 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioningC432 in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_reservedProvisioningC432 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioningC432 in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_reservedProvisioningC432 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_2ManualSet in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_2ManualSet 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2ManualSet in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_2ManualSet u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2ManualSet in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_2ManualSet u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_2_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_2_10Gb_sLinkEstablished 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_2_10Gb_sLinkEstablished u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_2_10Gb_sLinkEstablished u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_2_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_2_1Gb_sLinkEstablished 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_2_1Gb_sLinkEstablished u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_2_1Gb_sLinkEstablished u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_2_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_2_100Mb_sLinkEstablished 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_2_100Mb_sLinkEstablished u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_2_100Mb_sLinkEstablished u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_2Connecting in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_2Connecting 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2Connecting in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_2Connecting u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2Connecting in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_2Connecting u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_2ReceiveActivity in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_2ReceiveActivity 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2ReceiveActivity in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_2ReceiveActivity u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2ReceiveActivity in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_2ReceiveActivity u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_2TransmitActivity in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_2TransmitActivity 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2TransmitActivity in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_2TransmitActivity u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2TransmitActivity in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_2TransmitActivity u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_2ActivityStretch in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_2ActivityStretch 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2ActivityStretch in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_2ActivityStretch u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2ActivityStretch in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_2ActivityStretch u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure ledOperationMode in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_ledOperationMode 7 +/*! \brief Preprocessor variable to relate field to bit position in structure ledOperationMode in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_ledOperationMode u7.bits_7 +/*! \brief Preprocessor variable to relate field to word position in structure ledOperationMode in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_ledOperationMode u7.word_7 + +/*! \brief Base register address of structure AQ_GlobalGeneralProvisioning_HHD */ +#define AQ_GlobalGeneralProvisioning_HHD_baseRegisterAddress 0xC440 +/*! \brief MMD address of structure AQ_GlobalGeneralProvisioning_HHD */ +#define AQ_GlobalGeneralProvisioning_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mdioBroadcastModeEnable in AQ_GlobalGeneralProvisioning_HHD */ +#define AQ_GlobalGeneralProvisioning_HHD_mdioBroadcastModeEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioBroadcastModeEnable in AQ_GlobalGeneralProvisioning_HHD */ +#define bits_AQ_GlobalGeneralProvisioning_HHD_mdioBroadcastModeEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mdioBroadcastModeEnable in AQ_GlobalGeneralProvisioning_HHD */ +#define word_AQ_GlobalGeneralProvisioning_HHD_mdioBroadcastModeEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mdioReadMSW_FirstEnable in AQ_GlobalGeneralProvisioning_HHD */ +#define AQ_GlobalGeneralProvisioning_HHD_mdioReadMSW_FirstEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioReadMSW_FirstEnable in AQ_GlobalGeneralProvisioning_HHD */ +#define bits_AQ_GlobalGeneralProvisioning_HHD_mdioReadMSW_FirstEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mdioReadMSW_FirstEnable in AQ_GlobalGeneralProvisioning_HHD */ +#define word_AQ_GlobalGeneralProvisioning_HHD_mdioReadMSW_FirstEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mdioDriveConfiguration in AQ_GlobalGeneralProvisioning_HHD */ +#define AQ_GlobalGeneralProvisioning_HHD_mdioDriveConfiguration 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioDriveConfiguration in AQ_GlobalGeneralProvisioning_HHD */ +#define bits_AQ_GlobalGeneralProvisioning_HHD_mdioDriveConfiguration u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mdioDriveConfiguration in AQ_GlobalGeneralProvisioning_HHD */ +#define word_AQ_GlobalGeneralProvisioning_HHD_mdioDriveConfiguration u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mdioPreambleDetectionDisable in AQ_GlobalGeneralProvisioning_HHD */ +#define AQ_GlobalGeneralProvisioning_HHD_mdioPreambleDetectionDisable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioPreambleDetectionDisable in AQ_GlobalGeneralProvisioning_HHD */ +#define bits_AQ_GlobalGeneralProvisioning_HHD_mdioPreambleDetectionDisable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mdioPreambleDetectionDisable in AQ_GlobalGeneralProvisioning_HHD */ +#define word_AQ_GlobalGeneralProvisioning_HHD_mdioPreambleDetectionDisable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure daisyChainReset in AQ_GlobalGeneralProvisioning_HHD */ +#define AQ_GlobalGeneralProvisioning_HHD_daisyChainReset 2 +/*! \brief Preprocessor variable to relate field to bit position in structure daisyChainReset in AQ_GlobalGeneralProvisioning_HHD */ +#define bits_AQ_GlobalGeneralProvisioning_HHD_daisyChainReset u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure daisyChainReset in AQ_GlobalGeneralProvisioning_HHD */ +#define word_AQ_GlobalGeneralProvisioning_HHD_daisyChainReset u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure mdioBroadcastAddressConfiguration in AQ_GlobalGeneralProvisioning_HHD */ +#define AQ_GlobalGeneralProvisioning_HHD_mdioBroadcastAddressConfiguration 7 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioBroadcastAddressConfiguration in AQ_GlobalGeneralProvisioning_HHD */ +#define bits_AQ_GlobalGeneralProvisioning_HHD_mdioBroadcastAddressConfiguration u7.bits_7 +/*! \brief Preprocessor variable to relate field to word position in structure mdioBroadcastAddressConfiguration in AQ_GlobalGeneralProvisioning_HHD */ +#define word_AQ_GlobalGeneralProvisioning_HHD_mdioBroadcastAddressConfiguration u7.word_7 +/*! \brief Preprocessor variable to relate field to word number in structure mdioPreambleLength in AQ_GlobalGeneralProvisioning_HHD */ +#define AQ_GlobalGeneralProvisioning_HHD_mdioPreambleLength 9 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioPreambleLength in AQ_GlobalGeneralProvisioning_HHD */ +#define bits_AQ_GlobalGeneralProvisioning_HHD_mdioPreambleLength u9.bits_9 +/*! \brief Preprocessor variable to relate field to word position in structure mdioPreambleLength in AQ_GlobalGeneralProvisioning_HHD */ +#define word_AQ_GlobalGeneralProvisioning_HHD_mdioPreambleLength u9.word_9 + +/*! \brief Base register address of structure AQ_GlobalNvrProvisioning_HHD */ +#define AQ_GlobalNvrProvisioning_HHD_baseRegisterAddress 0xC450 +/*! \brief MMD address of structure AQ_GlobalNvrProvisioning_HHD */ +#define AQ_GlobalNvrProvisioning_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure nvrDataLength in AQ_GlobalNvrProvisioning_HHD */ +#define AQ_GlobalNvrProvisioning_HHD_nvrDataLength 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrDataLength in AQ_GlobalNvrProvisioning_HHD */ +#define bits_AQ_GlobalNvrProvisioning_HHD_nvrDataLength u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrDataLength in AQ_GlobalNvrProvisioning_HHD */ +#define word_AQ_GlobalNvrProvisioning_HHD_nvrDataLength u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrDummyLength in AQ_GlobalNvrProvisioning_HHD */ +#define AQ_GlobalNvrProvisioning_HHD_nvrDummyLength 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrDummyLength in AQ_GlobalNvrProvisioning_HHD */ +#define bits_AQ_GlobalNvrProvisioning_HHD_nvrDummyLength u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrDummyLength in AQ_GlobalNvrProvisioning_HHD */ +#define word_AQ_GlobalNvrProvisioning_HHD_nvrDummyLength u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrAddressLength in AQ_GlobalNvrProvisioning_HHD */ +#define AQ_GlobalNvrProvisioning_HHD_nvrAddressLength 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrAddressLength in AQ_GlobalNvrProvisioning_HHD */ +#define bits_AQ_GlobalNvrProvisioning_HHD_nvrAddressLength u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrAddressLength in AQ_GlobalNvrProvisioning_HHD */ +#define word_AQ_GlobalNvrProvisioning_HHD_nvrAddressLength u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrAddressLengthOverride in AQ_GlobalNvrProvisioning_HHD */ +#define AQ_GlobalNvrProvisioning_HHD_nvrAddressLengthOverride 1 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrAddressLengthOverride in AQ_GlobalNvrProvisioning_HHD */ +#define bits_AQ_GlobalNvrProvisioning_HHD_nvrAddressLengthOverride u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure nvrAddressLengthOverride in AQ_GlobalNvrProvisioning_HHD */ +#define word_AQ_GlobalNvrProvisioning_HHD_nvrAddressLengthOverride u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure nvrClockDivide in AQ_GlobalNvrProvisioning_HHD */ +#define AQ_GlobalNvrProvisioning_HHD_nvrClockDivide 1 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrClockDivide in AQ_GlobalNvrProvisioning_HHD */ +#define bits_AQ_GlobalNvrProvisioning_HHD_nvrClockDivide u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure nvrClockDivide in AQ_GlobalNvrProvisioning_HHD */ +#define word_AQ_GlobalNvrProvisioning_HHD_nvrClockDivide u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure nvrDaisyChainClockDivideOverride in AQ_GlobalNvrProvisioning_HHD */ +#define AQ_GlobalNvrProvisioning_HHD_nvrDaisyChainClockDivideOverride 2 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrDaisyChainClockDivideOverride in AQ_GlobalNvrProvisioning_HHD */ +#define bits_AQ_GlobalNvrProvisioning_HHD_nvrDaisyChainClockDivideOverride u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure nvrDaisyChainClockDivideOverride in AQ_GlobalNvrProvisioning_HHD */ +#define word_AQ_GlobalNvrProvisioning_HHD_nvrDaisyChainClockDivideOverride u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure nvrDaisyChainDisable in AQ_GlobalNvrProvisioning_HHD */ +#define AQ_GlobalNvrProvisioning_HHD_nvrDaisyChainDisable 2 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrDaisyChainDisable in AQ_GlobalNvrProvisioning_HHD */ +#define bits_AQ_GlobalNvrProvisioning_HHD_nvrDaisyChainDisable u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure nvrDaisyChainDisable in AQ_GlobalNvrProvisioning_HHD */ +#define word_AQ_GlobalNvrProvisioning_HHD_nvrDaisyChainDisable u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure nvrReset in AQ_GlobalNvrProvisioning_HHD */ +#define AQ_GlobalNvrProvisioning_HHD_nvrReset 3 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrReset in AQ_GlobalNvrProvisioning_HHD */ +#define bits_AQ_GlobalNvrProvisioning_HHD_nvrReset u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure nvrReset in AQ_GlobalNvrProvisioning_HHD */ +#define word_AQ_GlobalNvrProvisioning_HHD_nvrReset u3.word_3 + +/*! \brief Base register address of structure AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_baseRegisterAddress 0xC470 +/*! \brief MMD address of structure AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure diagnosticsSelect in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_diagnosticsSelect 0 +/*! \brief Preprocessor variable to relate field to bit position in structure diagnosticsSelect in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_diagnosticsSelect u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure diagnosticsSelect in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_diagnosticsSelect u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure extendedMdiDiagnosticsSelect in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_extendedMdiDiagnosticsSelect 0 +/*! \brief Preprocessor variable to relate field to bit position in structure extendedMdiDiagnosticsSelect in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_extendedMdiDiagnosticsSelect u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure extendedMdiDiagnosticsSelect in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_extendedMdiDiagnosticsSelect u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure initiateCableDiagnostics in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_initiateCableDiagnostics 0 +/*! \brief Preprocessor variable to relate field to bit position in structure initiateCableDiagnostics in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_initiateCableDiagnostics u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure initiateCableDiagnostics in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_initiateCableDiagnostics u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure enableDaisy_chainHop_countOverride in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_enableDaisy_chainHop_countOverride 1 +/*! \brief Preprocessor variable to relate field to bit position in structure enableDaisy_chainHop_countOverride in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_enableDaisy_chainHop_countOverride u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure enableDaisy_chainHop_countOverride in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_enableDaisy_chainHop_countOverride u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure daisy_chainHop_countOverrideValue in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_daisy_chainHop_countOverrideValue 1 +/*! \brief Preprocessor variable to relate field to bit position in structure daisy_chainHop_countOverrideValue in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_daisy_chainHop_countOverrideValue u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure daisy_chainHop_countOverrideValue in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_daisy_chainHop_countOverrideValue u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure enableVddPowerSupplyTuning in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_enableVddPowerSupplyTuning 2 +/*! \brief Preprocessor variable to relate field to bit position in structure enableVddPowerSupplyTuning in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_enableVddPowerSupplyTuning u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure enableVddPowerSupplyTuning in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_enableVddPowerSupplyTuning u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure tunableExternalVddPowerSupplyPresent in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_tunableExternalVddPowerSupplyPresent 2 +/*! \brief Preprocessor variable to relate field to bit position in structure tunableExternalVddPowerSupplyPresent in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_tunableExternalVddPowerSupplyPresent u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure tunableExternalVddPowerSupplyPresent in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_tunableExternalVddPowerSupplyPresent u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure externalVddChangeRequest in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_externalVddChangeRequest 2 +/*! \brief Preprocessor variable to relate field to bit position in structure externalVddChangeRequest in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_externalVddChangeRequest u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure externalVddChangeRequest in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_externalVddChangeRequest u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure enableXenpakRegisterSpace in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_enableXenpakRegisterSpace 2 +/*! \brief Preprocessor variable to relate field to bit position in structure enableXenpakRegisterSpace in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_enableXenpakRegisterSpace u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure enableXenpakRegisterSpace in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_enableXenpakRegisterSpace u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure enable_5thChannelRfiCancellation in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_enable_5thChannelRfiCancellation 2 +/*! \brief Preprocessor variable to relate field to bit position in structure enable_5thChannelRfiCancellation in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_enable_5thChannelRfiCancellation u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure enable_5thChannelRfiCancellation in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_enable_5thChannelRfiCancellation u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure rateTransitionRequest in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_rateTransitionRequest 3 +/*! \brief Preprocessor variable to relate field to bit position in structure rateTransitionRequest in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_rateTransitionRequest u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure rateTransitionRequest in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_rateTransitionRequest u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure trainingSNR in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_trainingSNR 3 +/*! \brief Preprocessor variable to relate field to bit position in structure trainingSNR in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_trainingSNR u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure trainingSNR in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_trainingSNR u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioning_5 in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_5 4 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioning_5 in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_5 u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioning_5 in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_5 u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure nvrDaisyChainKickstart in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_nvrDaisyChainKickstart 4 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrDaisyChainKickstart in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_nvrDaisyChainKickstart u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure nvrDaisyChainKickstart in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_nvrDaisyChainKickstart u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure smartPower_downStatus in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_smartPower_downStatus 5 +/*! \brief Preprocessor variable to relate field to bit position in structure smartPower_downStatus in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_smartPower_downStatus u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure smartPower_downStatus in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_smartPower_downStatus u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioning_6 in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_6 5 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioning_6 in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_6 u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioning_6 in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_6 u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrLpDisableTimer in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_cfrLpDisableTimer 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrLpDisableTimer in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_cfrLpDisableTimer u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrLpDisableTimer in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_cfrLpDisableTimer u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrLpExtendedMaxwait in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_cfrLpExtendedMaxwait 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrLpExtendedMaxwait in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_cfrLpExtendedMaxwait u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrLpExtendedMaxwait in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_cfrLpExtendedMaxwait u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrLpTHP in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_cfrLpTHP 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrLpTHP in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_cfrLpTHP u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrLpTHP in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_cfrLpTHP u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrLpSupport in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_cfrLpSupport 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrLpSupport in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_cfrLpSupport u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrLpSupport in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_cfrLpSupport u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrDisableTimer in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_cfrDisableTimer 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrDisableTimer in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_cfrDisableTimer u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrDisableTimer in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_cfrDisableTimer u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrExtendedMaxwait in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_cfrExtendedMaxwait 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrExtendedMaxwait in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_cfrExtendedMaxwait u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrExtendedMaxwait in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_cfrExtendedMaxwait u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrTHP in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_cfrTHP 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrTHP in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_cfrTHP u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrTHP in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_cfrTHP u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrSupport in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_cfrSupport 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrSupport in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_cfrSupport u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrSupport in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_cfrSupport u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure deadlockAvoidanceEnable in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_deadlockAvoidanceEnable 5 +/*! \brief Preprocessor variable to relate field to bit position in structure deadlockAvoidanceEnable in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_deadlockAvoidanceEnable u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure deadlockAvoidanceEnable in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_deadlockAvoidanceEnable u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure smartPower_downEnable in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_smartPower_downEnable 5 +/*! \brief Preprocessor variable to relate field to bit position in structure smartPower_downEnable in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_smartPower_downEnable u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure smartPower_downEnable in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_smartPower_downEnable u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure dteEnable in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_dteEnable 8 +/*! \brief Preprocessor variable to relate field to bit position in structure dteEnable in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_dteEnable u8.bits_8 +/*! \brief Preprocessor variable to relate field to word position in structure dteEnable in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_dteEnable u8.word_8 +/*! \brief Preprocessor variable to relate field to word number in structure dteDropReportingTimer in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_dteDropReportingTimer 8 +/*! \brief Preprocessor variable to relate field to bit position in structure dteDropReportingTimer in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_dteDropReportingTimer u8.bits_8 +/*! \brief Preprocessor variable to relate field to word position in structure dteDropReportingTimer in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_dteDropReportingTimer u8.word_8 +/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioning_9 in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_9 8 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioning_9 in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_9 u8.bits_8 +/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioning_9 in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_9 u8.word_8 +/*! \brief Preprocessor variable to relate field to word number in structure powerUpStall in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_powerUpStall 9 +/*! \brief Preprocessor variable to relate field to bit position in structure powerUpStall in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_powerUpStall u9.bits_9 +/*! \brief Preprocessor variable to relate field to word position in structure powerUpStall in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_powerUpStall u9.word_9 +/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioning_10 in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_10 9 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioning_10 in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_10 u9.bits_9 +/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioning_10 in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_10 u9.word_9 +/*! \brief Preprocessor variable to relate field to word number in structure loopbackControl in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_loopbackControl 10 +/*! \brief Preprocessor variable to relate field to bit position in structure loopbackControl in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_loopbackControl u10.bits_10 +/*! \brief Preprocessor variable to relate field to word position in structure loopbackControl in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_loopbackControl u10.word_10 +/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioning_11 in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_11 10 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioning_11 in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_11 u10.bits_10 +/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioning_11 in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_11 u10.word_10 +/*! \brief Preprocessor variable to relate field to word number in structure mdiPacketGeneration in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_mdiPacketGeneration 10 +/*! \brief Preprocessor variable to relate field to bit position in structure mdiPacketGeneration in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_mdiPacketGeneration u10.bits_10 +/*! \brief Preprocessor variable to relate field to word position in structure mdiPacketGeneration in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_mdiPacketGeneration u10.word_10 +/*! \brief Preprocessor variable to relate field to word number in structure look_asidePortPacketGeneration in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_look_asidePortPacketGeneration 10 +/*! \brief Preprocessor variable to relate field to bit position in structure look_asidePortPacketGeneration in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_look_asidePortPacketGeneration u10.bits_10 +/*! \brief Preprocessor variable to relate field to word position in structure look_asidePortPacketGeneration in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_look_asidePortPacketGeneration u10.word_10 +/*! \brief Preprocessor variable to relate field to word number in structure systemI_fPacketGeneration in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_systemI_fPacketGeneration 10 +/*! \brief Preprocessor variable to relate field to bit position in structure systemI_fPacketGeneration in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_systemI_fPacketGeneration u10.bits_10 +/*! \brief Preprocessor variable to relate field to word position in structure systemI_fPacketGeneration in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_systemI_fPacketGeneration u10.word_10 +/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioning_11a in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_11a 10 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioning_11a in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_11a u10.bits_10 +/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioning_11a in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_11a u10.word_10 +/*! \brief Preprocessor variable to relate field to word number in structure rate in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_rate 10 +/*! \brief Preprocessor variable to relate field to bit position in structure rate in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_rate u10.bits_10 +/*! \brief Preprocessor variable to relate field to word position in structure rate in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_rate u10.word_10 +/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioning_12 in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_12 11 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioning_12 in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_12 u11.bits_11 +/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioning_12 in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_12 u11.word_11 +/*! \brief Preprocessor variable to relate field to word number in structure enableMacsec in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_enableMacsec 11 +/*! \brief Preprocessor variable to relate field to bit position in structure enableMacsec in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_enableMacsec u11.bits_11 +/*! \brief Preprocessor variable to relate field to word position in structure enableMacsec in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_enableMacsec u11.word_11 +/*! \brief Preprocessor variable to relate field to word number in structure enablePtp in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_enablePtp 11 +/*! \brief Preprocessor variable to relate field to bit position in structure enablePtp in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_enablePtp u11.bits_11 +/*! \brief Preprocessor variable to relate field to word position in structure enablePtp in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_enablePtp u11.word_11 + +/*! \brief Base register address of structure AQ_PifMailboxControl_HHD */ +#define AQ_PifMailboxControl_HHD_baseRegisterAddress 0xC47C +/*! \brief MMD address of structure AQ_PifMailboxControl_HHD */ +#define AQ_PifMailboxControl_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure pifMailboxAddress in AQ_PifMailboxControl_HHD */ +#define AQ_PifMailboxControl_HHD_pifMailboxAddress 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pifMailboxAddress in AQ_PifMailboxControl_HHD */ +#define bits_AQ_PifMailboxControl_HHD_pifMailboxAddress u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pifMailboxAddress in AQ_PifMailboxControl_HHD */ +#define word_AQ_PifMailboxControl_HHD_pifMailboxAddress u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pifMailboxData in AQ_PifMailboxControl_HHD */ +#define AQ_PifMailboxControl_HHD_pifMailboxData 1 +/*! \brief Preprocessor variable to relate field to bit position in structure pifMailboxData in AQ_PifMailboxControl_HHD */ +#define bits_AQ_PifMailboxControl_HHD_pifMailboxData u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure pifMailboxData in AQ_PifMailboxControl_HHD */ +#define word_AQ_PifMailboxControl_HHD_pifMailboxData u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure reservedPifMailboxControl_3 in AQ_PifMailboxControl_HHD */ +#define AQ_PifMailboxControl_HHD_reservedPifMailboxControl_3 2 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedPifMailboxControl_3 in AQ_PifMailboxControl_HHD */ +#define bits_AQ_PifMailboxControl_HHD_reservedPifMailboxControl_3 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure reservedPifMailboxControl_3 in AQ_PifMailboxControl_HHD */ +#define word_AQ_PifMailboxControl_HHD_reservedPifMailboxControl_3 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure pifMailboxCommandType in AQ_PifMailboxControl_HHD */ +#define AQ_PifMailboxControl_HHD_pifMailboxCommandType 2 +/*! \brief Preprocessor variable to relate field to bit position in structure pifMailboxCommandType in AQ_PifMailboxControl_HHD */ +#define bits_AQ_PifMailboxControl_HHD_pifMailboxCommandType u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure pifMailboxCommandType in AQ_PifMailboxControl_HHD */ +#define word_AQ_PifMailboxControl_HHD_pifMailboxCommandType u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure pifMailboxMMD in AQ_PifMailboxControl_HHD */ +#define AQ_PifMailboxControl_HHD_pifMailboxMMD 2 +/*! \brief Preprocessor variable to relate field to bit position in structure pifMailboxMMD in AQ_PifMailboxControl_HHD */ +#define bits_AQ_PifMailboxControl_HHD_pifMailboxMMD u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure pifMailboxMMD in AQ_PifMailboxControl_HHD */ +#define word_AQ_PifMailboxControl_HHD_pifMailboxMMD u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure reservedPifMailboxControl_4 in AQ_PifMailboxControl_HHD */ +#define AQ_PifMailboxControl_HHD_reservedPifMailboxControl_4 3 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedPifMailboxControl_4 in AQ_PifMailboxControl_HHD */ +#define bits_AQ_PifMailboxControl_HHD_reservedPifMailboxControl_4 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure reservedPifMailboxControl_4 in AQ_PifMailboxControl_HHD */ +#define word_AQ_PifMailboxControl_HHD_reservedPifMailboxControl_4 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure pifMailboxCommandStatus in AQ_PifMailboxControl_HHD */ +#define AQ_PifMailboxControl_HHD_pifMailboxCommandStatus 3 +/*! \brief Preprocessor variable to relate field to bit position in structure pifMailboxCommandStatus in AQ_PifMailboxControl_HHD */ +#define bits_AQ_PifMailboxControl_HHD_pifMailboxCommandStatus u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure pifMailboxCommandStatus in AQ_PifMailboxControl_HHD */ +#define word_AQ_PifMailboxControl_HHD_pifMailboxCommandStatus u3.word_3 + +/*! \brief Base register address of structure AQ_GlobalSmbus_0Provisioning_HHD */ +#define AQ_GlobalSmbus_0Provisioning_HHD_baseRegisterAddress 0xC485 +/*! \brief MMD address of structure AQ_GlobalSmbus_0Provisioning_HHD */ +#define AQ_GlobalSmbus_0Provisioning_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure smb_0SlaveAddress in AQ_GlobalSmbus_0Provisioning_HHD */ +#define AQ_GlobalSmbus_0Provisioning_HHD_smb_0SlaveAddress 0 +/*! \brief Preprocessor variable to relate field to bit position in structure smb_0SlaveAddress in AQ_GlobalSmbus_0Provisioning_HHD */ +#define bits_AQ_GlobalSmbus_0Provisioning_HHD_smb_0SlaveAddress u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure smb_0SlaveAddress in AQ_GlobalSmbus_0Provisioning_HHD */ +#define word_AQ_GlobalSmbus_0Provisioning_HHD_smb_0SlaveAddress u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalSmbus_1Provisioning_HHD */ +#define AQ_GlobalSmbus_1Provisioning_HHD_baseRegisterAddress 0xC495 +/*! \brief MMD address of structure AQ_GlobalSmbus_1Provisioning_HHD */ +#define AQ_GlobalSmbus_1Provisioning_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure smb_1SlaveAddress in AQ_GlobalSmbus_1Provisioning_HHD */ +#define AQ_GlobalSmbus_1Provisioning_HHD_smb_1SlaveAddress 0 +/*! \brief Preprocessor variable to relate field to bit position in structure smb_1SlaveAddress in AQ_GlobalSmbus_1Provisioning_HHD */ +#define bits_AQ_GlobalSmbus_1Provisioning_HHD_smb_1SlaveAddress u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure smb_1SlaveAddress in AQ_GlobalSmbus_1Provisioning_HHD */ +#define word_AQ_GlobalSmbus_1Provisioning_HHD_smb_1SlaveAddress u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalEeeProvisioning_HHD */ +#define AQ_GlobalEeeProvisioning_HHD_baseRegisterAddress 0xC4A0 +/*! \brief MMD address of structure AQ_GlobalEeeProvisioning_HHD */ +#define AQ_GlobalEeeProvisioning_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure eeeMode in AQ_GlobalEeeProvisioning_HHD */ +#define AQ_GlobalEeeProvisioning_HHD_eeeMode 0 +/*! \brief Preprocessor variable to relate field to bit position in structure eeeMode in AQ_GlobalEeeProvisioning_HHD */ +#define bits_AQ_GlobalEeeProvisioning_HHD_eeeMode u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure eeeMode in AQ_GlobalEeeProvisioning_HHD */ +#define word_AQ_GlobalEeeProvisioning_HHD_eeeMode u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_baseRegisterAddress 0xC800 +/*! \brief MMD address of structure AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure pairAStatus in AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_pairAStatus 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairAStatus in AQ_GlobalCableDiagnosticStatus_HHD */ +#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairAStatus u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairAStatus in AQ_GlobalCableDiagnosticStatus_HHD */ +#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairAStatus u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairBStatus in AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_pairBStatus 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairBStatus in AQ_GlobalCableDiagnosticStatus_HHD */ +#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairBStatus u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairBStatus in AQ_GlobalCableDiagnosticStatus_HHD */ +#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairBStatus u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairCStatus in AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_pairCStatus 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairCStatus in AQ_GlobalCableDiagnosticStatus_HHD */ +#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairCStatus u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairCStatus in AQ_GlobalCableDiagnosticStatus_HHD */ +#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairCStatus u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairDStatus in AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_pairDStatus 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairDStatus in AQ_GlobalCableDiagnosticStatus_HHD */ +#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairDStatus u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairDStatus in AQ_GlobalCableDiagnosticStatus_HHD */ +#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairDStatus u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_pairAReflection_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairAReflection_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairAReflection_1 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_pairAReflection_2 1 +/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairAReflection_2 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairAReflection_2 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure impulseResponseMSW in AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_impulseResponseMSW 2 +/*! \brief Preprocessor variable to relate field to bit position in structure impulseResponseMSW in AQ_GlobalCableDiagnosticStatus_HHD */ +#define bits_AQ_GlobalCableDiagnosticStatus_HHD_impulseResponseMSW u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure impulseResponseMSW in AQ_GlobalCableDiagnosticStatus_HHD */ +#define word_AQ_GlobalCableDiagnosticStatus_HHD_impulseResponseMSW u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_pairBReflection_1 3 +/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairBReflection_1 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairBReflection_1 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_pairBReflection_2 3 +/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairBReflection_2 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairBReflection_2 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure impulseResponseLSW in AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_impulseResponseLSW 4 +/*! \brief Preprocessor variable to relate field to bit position in structure impulseResponseLSW in AQ_GlobalCableDiagnosticStatus_HHD */ +#define bits_AQ_GlobalCableDiagnosticStatus_HHD_impulseResponseLSW u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure impulseResponseLSW in AQ_GlobalCableDiagnosticStatus_HHD */ +#define word_AQ_GlobalCableDiagnosticStatus_HHD_impulseResponseLSW u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_pairCReflection_1 5 +/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairCReflection_1 u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairCReflection_1 u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_pairCReflection_2 5 +/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairCReflection_2 u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairCReflection_2 u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_1 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_reserved_1 6 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_1 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define bits_AQ_GlobalCableDiagnosticStatus_HHD_reserved_1 u6.bits_6 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_1 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define word_AQ_GlobalCableDiagnosticStatus_HHD_reserved_1 u6.word_6 +/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_pairDReflection_1 7 +/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairDReflection_1 u7.bits_7 +/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairDReflection_1 u7.word_7 +/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_pairDReflection_2 7 +/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairDReflection_2 u7.bits_7 +/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairDReflection_2 u7.word_7 + +/*! \brief Base register address of structure AQ_GlobalThermalStatus_HHD */ +#define AQ_GlobalThermalStatus_HHD_baseRegisterAddress 0xC820 +/*! \brief MMD address of structure AQ_GlobalThermalStatus_HHD */ +#define AQ_GlobalThermalStatus_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure temperature in AQ_GlobalThermalStatus_HHD */ +#define AQ_GlobalThermalStatus_HHD_temperature 0 +/*! \brief Preprocessor variable to relate field to bit position in structure temperature in AQ_GlobalThermalStatus_HHD */ +#define bits_AQ_GlobalThermalStatus_HHD_temperature u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure temperature in AQ_GlobalThermalStatus_HHD */ +#define word_AQ_GlobalThermalStatus_HHD_temperature u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure temperatureReady in AQ_GlobalThermalStatus_HHD */ +#define AQ_GlobalThermalStatus_HHD_temperatureReady 1 +/*! \brief Preprocessor variable to relate field to bit position in structure temperatureReady in AQ_GlobalThermalStatus_HHD */ +#define bits_AQ_GlobalThermalStatus_HHD_temperatureReady u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure temperatureReady in AQ_GlobalThermalStatus_HHD */ +#define word_AQ_GlobalThermalStatus_HHD_temperatureReady u1.word_1 + +/*! \brief Base register address of structure AQ_GlobalGeneralStatus_HHD */ +#define AQ_GlobalGeneralStatus_HHD_baseRegisterAddress 0xC830 +/*! \brief MMD address of structure AQ_GlobalGeneralStatus_HHD */ +#define AQ_GlobalGeneralStatus_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureFailureState in AQ_GlobalGeneralStatus_HHD */ +#define AQ_GlobalGeneralStatus_HHD_highTemperatureFailureState 0 +/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureFailureState in AQ_GlobalGeneralStatus_HHD */ +#define bits_AQ_GlobalGeneralStatus_HHD_highTemperatureFailureState u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureFailureState in AQ_GlobalGeneralStatus_HHD */ +#define word_AQ_GlobalGeneralStatus_HHD_highTemperatureFailureState u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureFailureState in AQ_GlobalGeneralStatus_HHD */ +#define AQ_GlobalGeneralStatus_HHD_lowTemperatureFailureState 0 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureFailureState in AQ_GlobalGeneralStatus_HHD */ +#define bits_AQ_GlobalGeneralStatus_HHD_lowTemperatureFailureState u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureFailureState in AQ_GlobalGeneralStatus_HHD */ +#define word_AQ_GlobalGeneralStatus_HHD_lowTemperatureFailureState u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureWarningState in AQ_GlobalGeneralStatus_HHD */ +#define AQ_GlobalGeneralStatus_HHD_highTemperatureWarningState 0 +/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureWarningState in AQ_GlobalGeneralStatus_HHD */ +#define bits_AQ_GlobalGeneralStatus_HHD_highTemperatureWarningState u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureWarningState in AQ_GlobalGeneralStatus_HHD */ +#define word_AQ_GlobalGeneralStatus_HHD_highTemperatureWarningState u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureWarningState in AQ_GlobalGeneralStatus_HHD */ +#define AQ_GlobalGeneralStatus_HHD_lowTemperatureWarningState 0 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureWarningState in AQ_GlobalGeneralStatus_HHD */ +#define bits_AQ_GlobalGeneralStatus_HHD_lowTemperatureWarningState u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureWarningState in AQ_GlobalGeneralStatus_HHD */ +#define word_AQ_GlobalGeneralStatus_HHD_lowTemperatureWarningState u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure processorIntensiveMdioOperationIn_Progress in AQ_GlobalGeneralStatus_HHD */ +#define AQ_GlobalGeneralStatus_HHD_processorIntensiveMdioOperationIn_Progress 1 +/*! \brief Preprocessor variable to relate field to bit position in structure processorIntensiveMdioOperationIn_Progress in AQ_GlobalGeneralStatus_HHD */ +#define bits_AQ_GlobalGeneralStatus_HHD_processorIntensiveMdioOperationIn_Progress u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure processorIntensiveMdioOperationIn_Progress in AQ_GlobalGeneralStatus_HHD */ +#define word_AQ_GlobalGeneralStatus_HHD_processorIntensiveMdioOperationIn_Progress u1.word_1 + +/*! \brief Base register address of structure AQ_GlobalPinStatus_HHD */ +#define AQ_GlobalPinStatus_HHD_baseRegisterAddress 0xC840 +/*! \brief MMD address of structure AQ_GlobalPinStatus_HHD */ +#define AQ_GlobalPinStatus_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure dcMasterN in AQ_GlobalPinStatus_HHD */ +#define AQ_GlobalPinStatus_HHD_dcMasterN 0 +/*! \brief Preprocessor variable to relate field to bit position in structure dcMasterN in AQ_GlobalPinStatus_HHD */ +#define bits_AQ_GlobalPinStatus_HHD_dcMasterN u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure dcMasterN in AQ_GlobalPinStatus_HHD */ +#define word_AQ_GlobalPinStatus_HHD_dcMasterN u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure packageConnectivity in AQ_GlobalPinStatus_HHD */ +#define AQ_GlobalPinStatus_HHD_packageConnectivity 0 +/*! \brief Preprocessor variable to relate field to bit position in structure packageConnectivity in AQ_GlobalPinStatus_HHD */ +#define bits_AQ_GlobalPinStatus_HHD_packageConnectivity u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure packageConnectivity in AQ_GlobalPinStatus_HHD */ +#define word_AQ_GlobalPinStatus_HHD_packageConnectivity u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure txEnable in AQ_GlobalPinStatus_HHD */ +#define AQ_GlobalPinStatus_HHD_txEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure txEnable in AQ_GlobalPinStatus_HHD */ +#define bits_AQ_GlobalPinStatus_HHD_txEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure txEnable in AQ_GlobalPinStatus_HHD */ +#define word_AQ_GlobalPinStatus_HHD_txEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure ledPullupState in AQ_GlobalPinStatus_HHD */ +#define AQ_GlobalPinStatus_HHD_ledPullupState 0 +/*! \brief Preprocessor variable to relate field to bit position in structure ledPullupState in AQ_GlobalPinStatus_HHD */ +#define bits_AQ_GlobalPinStatus_HHD_ledPullupState u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure ledPullupState in AQ_GlobalPinStatus_HHD */ +#define word_AQ_GlobalPinStatus_HHD_ledPullupState u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalDaisyChainStatus_HHD */ +#define AQ_GlobalDaisyChainStatus_HHD_baseRegisterAddress 0xC842 +/*! \brief MMD address of structure AQ_GlobalDaisyChainStatus_HHD */ +#define AQ_GlobalDaisyChainStatus_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure rxDaisyChainCalculatedCrc in AQ_GlobalDaisyChainStatus_HHD */ +#define AQ_GlobalDaisyChainStatus_HHD_rxDaisyChainCalculatedCrc 0 +/*! \brief Preprocessor variable to relate field to bit position in structure rxDaisyChainCalculatedCrc in AQ_GlobalDaisyChainStatus_HHD */ +#define bits_AQ_GlobalDaisyChainStatus_HHD_rxDaisyChainCalculatedCrc u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure rxDaisyChainCalculatedCrc in AQ_GlobalDaisyChainStatus_HHD */ +#define word_AQ_GlobalDaisyChainStatus_HHD_rxDaisyChainCalculatedCrc u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalFaultMessage_HHD */ +#define AQ_GlobalFaultMessage_HHD_baseRegisterAddress 0xC850 +/*! \brief MMD address of structure AQ_GlobalFaultMessage_HHD */ +#define AQ_GlobalFaultMessage_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure message in AQ_GlobalFaultMessage_HHD */ +#define AQ_GlobalFaultMessage_HHD_message 0 +/*! \brief Preprocessor variable to relate field to bit position in structure message in AQ_GlobalFaultMessage_HHD */ +#define bits_AQ_GlobalFaultMessage_HHD_message u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure message in AQ_GlobalFaultMessage_HHD */ +#define word_AQ_GlobalFaultMessage_HHD_message u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_baseRegisterAddress 0xC880 +/*! \brief MMD address of structure AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure reserved_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_1 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_1 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_1 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_1 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_1 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_1 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_2 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_2 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_2 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_2 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_2 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_2 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_3 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_3 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_3 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_3 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_3 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_3 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_4 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_4 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_4 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_4 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_4 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_4 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_5 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_5 1 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_5 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_5 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_5 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_5 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_1 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_6 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_6 1 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_6 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_6 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_6 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_6 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_2 1 +/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_2 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_2 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_7 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_7 1 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_7 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_7 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_7 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_7 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_3 1 +/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_3 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_3 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_8 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_8 1 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_8 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_8 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_8 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_8 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_4 1 +/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_4 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_4 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_9 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_9 2 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_9 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_9 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_9 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_9 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_1 2 +/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_1 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_1 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_10 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_10 2 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_10 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_10 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_10 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_10 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_2 2 +/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_2 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_2 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_11 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_11 2 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_11 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_11 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_11 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_11 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_3 2 +/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_3 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_3 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_12 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_12 2 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_12 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_12 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_12 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_12 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_4 2 +/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_4 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_4 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_13 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_13 3 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_13 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_13 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_13 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_13 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_1 3 +/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_1 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_1 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_14 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_14 3 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_14 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_14 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_14 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_14 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_2 3 +/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_2 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_2 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_15 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_15 3 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_15 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_15 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_15 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_15 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_3 3 +/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_3 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_3 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_16 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_16 3 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_16 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_16 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_16 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_16 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_4 3 +/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_4 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_4 u3.word_3 + +/*! \brief Base register address of structure AQ_GlobalStatus_HHD */ +#define AQ_GlobalStatus_HHD_baseRegisterAddress 0xC884 +/*! \brief MMD address of structure AQ_GlobalStatus_HHD */ +#define AQ_GlobalStatus_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure reservedStatus_0 in AQ_GlobalStatus_HHD */ +#define AQ_GlobalStatus_HHD_reservedStatus_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedStatus_0 in AQ_GlobalStatus_HHD */ +#define bits_AQ_GlobalStatus_HHD_reservedStatus_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedStatus_0 in AQ_GlobalStatus_HHD */ +#define word_AQ_GlobalStatus_HHD_reservedStatus_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure cableLength in AQ_GlobalStatus_HHD */ +#define AQ_GlobalStatus_HHD_cableLength 0 +/*! \brief Preprocessor variable to relate field to bit position in structure cableLength in AQ_GlobalStatus_HHD */ +#define bits_AQ_GlobalStatus_HHD_cableLength u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure cableLength in AQ_GlobalStatus_HHD */ +#define word_AQ_GlobalStatus_HHD_cableLength u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_baseRegisterAddress 0xC885 +/*! \brief MMD address of structure AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure nearlySecondsMSW in AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_nearlySecondsMSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nearlySecondsMSW in AQ_GlobalReservedStatus_HHD */ +#define bits_AQ_GlobalReservedStatus_HHD_nearlySecondsMSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nearlySecondsMSW in AQ_GlobalReservedStatus_HHD */ +#define word_AQ_GlobalReservedStatus_HHD_nearlySecondsMSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure xenpakNvrStatus in AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_xenpakNvrStatus 0 +/*! \brief Preprocessor variable to relate field to bit position in structure xenpakNvrStatus in AQ_GlobalReservedStatus_HHD */ +#define bits_AQ_GlobalReservedStatus_HHD_xenpakNvrStatus u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure xenpakNvrStatus in AQ_GlobalReservedStatus_HHD */ +#define word_AQ_GlobalReservedStatus_HHD_xenpakNvrStatus u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure firmwareBuildID in AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_firmwareBuildID 0 +/*! \brief Preprocessor variable to relate field to bit position in structure firmwareBuildID in AQ_GlobalReservedStatus_HHD */ +#define bits_AQ_GlobalReservedStatus_HHD_firmwareBuildID u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure firmwareBuildID in AQ_GlobalReservedStatus_HHD */ +#define word_AQ_GlobalReservedStatus_HHD_firmwareBuildID u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure provisioningID in AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_provisioningID 0 +/*! \brief Preprocessor variable to relate field to bit position in structure provisioningID in AQ_GlobalReservedStatus_HHD */ +#define bits_AQ_GlobalReservedStatus_HHD_provisioningID u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure provisioningID in AQ_GlobalReservedStatus_HHD */ +#define word_AQ_GlobalReservedStatus_HHD_provisioningID u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nearlySecondsLSW in AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_nearlySecondsLSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure nearlySecondsLSW in AQ_GlobalReservedStatus_HHD */ +#define bits_AQ_GlobalReservedStatus_HHD_nearlySecondsLSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure nearlySecondsLSW in AQ_GlobalReservedStatus_HHD */ +#define word_AQ_GlobalReservedStatus_HHD_nearlySecondsLSW u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure dteStatus in AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_dteStatus 2 +/*! \brief Preprocessor variable to relate field to bit position in structure dteStatus in AQ_GlobalReservedStatus_HHD */ +#define bits_AQ_GlobalReservedStatus_HHD_dteStatus u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure dteStatus in AQ_GlobalReservedStatus_HHD */ +#define word_AQ_GlobalReservedStatus_HHD_dteStatus u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure powerUpStallStatus in AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_powerUpStallStatus 2 +/*! \brief Preprocessor variable to relate field to bit position in structure powerUpStallStatus in AQ_GlobalReservedStatus_HHD */ +#define bits_AQ_GlobalReservedStatus_HHD_powerUpStallStatus u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure powerUpStallStatus in AQ_GlobalReservedStatus_HHD */ +#define word_AQ_GlobalReservedStatus_HHD_powerUpStallStatus u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure reservedStatus_3 in AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_reservedStatus_3 2 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedStatus_3 in AQ_GlobalReservedStatus_HHD */ +#define bits_AQ_GlobalReservedStatus_HHD_reservedStatus_3 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure reservedStatus_3 in AQ_GlobalReservedStatus_HHD */ +#define word_AQ_GlobalReservedStatus_HHD_reservedStatus_3 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure loopbackStatus in AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_loopbackStatus 3 +/*! \brief Preprocessor variable to relate field to bit position in structure loopbackStatus in AQ_GlobalReservedStatus_HHD */ +#define bits_AQ_GlobalReservedStatus_HHD_loopbackStatus u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure loopbackStatus in AQ_GlobalReservedStatus_HHD */ +#define word_AQ_GlobalReservedStatus_HHD_loopbackStatus u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure reservedStatus_4 in AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_reservedStatus_4 3 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedStatus_4 in AQ_GlobalReservedStatus_HHD */ +#define bits_AQ_GlobalReservedStatus_HHD_reservedStatus_4 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure reservedStatus_4 in AQ_GlobalReservedStatus_HHD */ +#define word_AQ_GlobalReservedStatus_HHD_reservedStatus_4 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure mdiPacketGenerationStatus in AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_mdiPacketGenerationStatus 3 +/*! \brief Preprocessor variable to relate field to bit position in structure mdiPacketGenerationStatus in AQ_GlobalReservedStatus_HHD */ +#define bits_AQ_GlobalReservedStatus_HHD_mdiPacketGenerationStatus u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure mdiPacketGenerationStatus in AQ_GlobalReservedStatus_HHD */ +#define word_AQ_GlobalReservedStatus_HHD_mdiPacketGenerationStatus u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure look_asidePortPacketGenerationStatus in AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_look_asidePortPacketGenerationStatus 3 +/*! \brief Preprocessor variable to relate field to bit position in structure look_asidePortPacketGenerationStatus in AQ_GlobalReservedStatus_HHD */ +#define bits_AQ_GlobalReservedStatus_HHD_look_asidePortPacketGenerationStatus u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure look_asidePortPacketGenerationStatus in AQ_GlobalReservedStatus_HHD */ +#define word_AQ_GlobalReservedStatus_HHD_look_asidePortPacketGenerationStatus u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure systemI_fPacketGenerationStatus in AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_systemI_fPacketGenerationStatus 3 +/*! \brief Preprocessor variable to relate field to bit position in structure systemI_fPacketGenerationStatus in AQ_GlobalReservedStatus_HHD */ +#define bits_AQ_GlobalReservedStatus_HHD_systemI_fPacketGenerationStatus u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure systemI_fPacketGenerationStatus in AQ_GlobalReservedStatus_HHD */ +#define word_AQ_GlobalReservedStatus_HHD_systemI_fPacketGenerationStatus u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure reservedStatus_4a in AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_reservedStatus_4a 3 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedStatus_4a in AQ_GlobalReservedStatus_HHD */ +#define bits_AQ_GlobalReservedStatus_HHD_reservedStatus_4a u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure reservedStatus_4a in AQ_GlobalReservedStatus_HHD */ +#define word_AQ_GlobalReservedStatus_HHD_reservedStatus_4a u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure rate in AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_rate 3 +/*! \brief Preprocessor variable to relate field to bit position in structure rate in AQ_GlobalReservedStatus_HHD */ +#define bits_AQ_GlobalReservedStatus_HHD_rate u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure rate in AQ_GlobalReservedStatus_HHD */ +#define word_AQ_GlobalReservedStatus_HHD_rate u3.word_3 + +/*! \brief Base register address of structure AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_baseRegisterAddress 0xCC00 +/*! \brief MMD address of structure AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureFailure in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_highTemperatureFailure 0 +/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureFailure in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_highTemperatureFailure u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureFailure in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_highTemperatureFailure u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureFailure in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_lowTemperatureFailure 0 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureFailure in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_lowTemperatureFailure u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureFailure in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_lowTemperatureFailure u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureWarning in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_highTemperatureWarning 0 +/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureWarning in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_highTemperatureWarning u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureWarning in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_highTemperatureWarning u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureWarning in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_lowTemperatureWarning 0 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureWarning in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_lowTemperatureWarning u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureWarning in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_lowTemperatureWarning u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure resetCompleted in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_resetCompleted 0 +/*! \brief Preprocessor variable to relate field to bit position in structure resetCompleted in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_resetCompleted u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure resetCompleted in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_resetCompleted u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure deviceFault in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_deviceFault 0 +/*! \brief Preprocessor variable to relate field to bit position in structure deviceFault in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_deviceFault u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure deviceFault in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_deviceFault u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmA in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_reservedAlarmA 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmA in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_reservedAlarmA u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmA in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_reservedAlarmA u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmB in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_reservedAlarmB 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmB in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_reservedAlarmB u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmB in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_reservedAlarmB u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmC in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_reservedAlarmC 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmC in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_reservedAlarmC u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmC in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_reservedAlarmC u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmD in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_reservedAlarmD 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmD in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_reservedAlarmD u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmD in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_reservedAlarmD u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure smartPower_downEntered in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_smartPower_downEntered 1 +/*! \brief Preprocessor variable to relate field to bit position in structure smartPower_downEntered in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_smartPower_downEntered u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure smartPower_downEntered in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_smartPower_downEntered u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure xenpakAlarm in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_xenpakAlarm 1 +/*! \brief Preprocessor variable to relate field to bit position in structure xenpakAlarm in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_xenpakAlarm u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure xenpakAlarm in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_xenpakAlarm u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure ipPhoneDetect in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_ipPhoneDetect 1 +/*! \brief Preprocessor variable to relate field to bit position in structure ipPhoneDetect in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_ipPhoneDetect u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure ipPhoneDetect in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_ipPhoneDetect u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure dteStatusChange in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_dteStatusChange 1 +/*! \brief Preprocessor variable to relate field to bit position in structure dteStatusChange in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_dteStatusChange u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure dteStatusChange in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_dteStatusChange u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarms in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_reservedAlarms 1 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarms in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_reservedAlarms u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarms in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_reservedAlarms u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mdioCommandHandlingOverflow in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_mdioCommandHandlingOverflow 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioCommandHandlingOverflow in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_mdioCommandHandlingOverflow u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mdioCommandHandlingOverflow in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_mdioCommandHandlingOverflow u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure nvrOperationComplete in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_nvrOperationComplete 2 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrOperationComplete in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_nvrOperationComplete u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure nvrOperationComplete in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_nvrOperationComplete u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure mailboxOperation_Complete in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_mailboxOperation_Complete 2 +/*! \brief Preprocessor variable to relate field to bit position in structure mailboxOperation_Complete in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_mailboxOperation_Complete u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure mailboxOperation_Complete in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_mailboxOperation_Complete u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure upDramParityError in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_upDramParityError 2 +/*! \brief Preprocessor variable to relate field to bit position in structure upDramParityError in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_upDramParityError u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure upDramParityError in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_upDramParityError u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure upIramParityError in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_upIramParityError 2 +/*! \brief Preprocessor variable to relate field to bit position in structure upIramParityError in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_upIramParityError u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure upIramParityError in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_upIramParityError u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure txEnableStateChange in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_txEnableStateChange 2 +/*! \brief Preprocessor variable to relate field to bit position in structure txEnableStateChange in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_txEnableStateChange u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure txEnableStateChange in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_txEnableStateChange u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure mdioMMD_Error in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_mdioMMD_Error 2 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioMMD_Error in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_mdioMMD_Error u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure mdioMMD_Error in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_mdioMMD_Error u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure mdioTimeoutError in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_mdioTimeoutError 2 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioTimeoutError in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_mdioTimeoutError u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure mdioTimeoutError in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_mdioTimeoutError u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure watchdogTimerAlarm in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_watchdogTimerAlarm 2 +/*! \brief Preprocessor variable to relate field to bit position in structure watchdogTimerAlarm in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_watchdogTimerAlarm u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure watchdogTimerAlarm in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_watchdogTimerAlarm u2.word_2 + +/*! \brief Base register address of structure AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_baseRegisterAddress 0xD400 +/*! \brief MMD address of structure AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureFailureMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_highTemperatureFailureMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureFailureMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_highTemperatureFailureMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureFailureMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_highTemperatureFailureMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureFailureMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_lowTemperatureFailureMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureFailureMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_lowTemperatureFailureMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureFailureMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_lowTemperatureFailureMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureWarningMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_highTemperatureWarningMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureWarningMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_highTemperatureWarningMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureWarningMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_highTemperatureWarningMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureWarningMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_lowTemperatureWarningMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureWarningMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_lowTemperatureWarningMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureWarningMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_lowTemperatureWarningMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure resetCompletedMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_resetCompletedMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure resetCompletedMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_resetCompletedMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure resetCompletedMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_resetCompletedMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure deviceFaultMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_deviceFaultMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure deviceFaultMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_deviceFaultMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure deviceFaultMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_deviceFaultMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmAMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_reservedAlarmAMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmAMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_reservedAlarmAMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmAMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_reservedAlarmAMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmBMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_reservedAlarmBMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmBMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_reservedAlarmBMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmBMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_reservedAlarmBMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmCMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_reservedAlarmCMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmCMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_reservedAlarmCMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmCMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_reservedAlarmCMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmDMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_reservedAlarmDMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmDMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_reservedAlarmDMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmDMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_reservedAlarmDMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure smartPower_downEnteredMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_smartPower_downEnteredMask 1 +/*! \brief Preprocessor variable to relate field to bit position in structure smartPower_downEnteredMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_smartPower_downEnteredMask u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure smartPower_downEnteredMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_smartPower_downEnteredMask u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure xenpakAlarmMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_xenpakAlarmMask 1 +/*! \brief Preprocessor variable to relate field to bit position in structure xenpakAlarmMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_xenpakAlarmMask u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure xenpakAlarmMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_xenpakAlarmMask u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure ipPhoneDetectMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_ipPhoneDetectMask 1 +/*! \brief Preprocessor variable to relate field to bit position in structure ipPhoneDetectMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_ipPhoneDetectMask u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure ipPhoneDetectMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_ipPhoneDetectMask u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure dteStatusChangeMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_dteStatusChangeMask 1 +/*! \brief Preprocessor variable to relate field to bit position in structure dteStatusChangeMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_dteStatusChangeMask u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure dteStatusChangeMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_dteStatusChangeMask u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmsMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_reservedAlarmsMask 1 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmsMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_reservedAlarmsMask u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmsMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_reservedAlarmsMask u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mdioCommandHandlingOverflowMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_mdioCommandHandlingOverflowMask 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioCommandHandlingOverflowMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_mdioCommandHandlingOverflowMask u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mdioCommandHandlingOverflowMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_mdioCommandHandlingOverflowMask u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure diagnosticAlarmMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_diagnosticAlarmMask 1 +/*! \brief Preprocessor variable to relate field to bit position in structure diagnosticAlarmMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_diagnosticAlarmMask u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure diagnosticAlarmMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_diagnosticAlarmMask u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure nvrOperationCompleteMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_nvrOperationCompleteMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrOperationCompleteMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_nvrOperationCompleteMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure nvrOperationCompleteMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_nvrOperationCompleteMask u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure mailboxOperationCompleteMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_mailboxOperationCompleteMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure mailboxOperationCompleteMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_mailboxOperationCompleteMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure mailboxOperationCompleteMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_mailboxOperationCompleteMask u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure upDramParityErrorMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_upDramParityErrorMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure upDramParityErrorMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_upDramParityErrorMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure upDramParityErrorMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_upDramParityErrorMask u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure upIramParityErrorMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_upIramParityErrorMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure upIramParityErrorMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_upIramParityErrorMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure upIramParityErrorMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_upIramParityErrorMask u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure txEnableStateChangeMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_txEnableStateChangeMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure txEnableStateChangeMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_txEnableStateChangeMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure txEnableStateChangeMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_txEnableStateChangeMask u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure mdioMMD_ErrorMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_mdioMMD_ErrorMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioMMD_ErrorMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_mdioMMD_ErrorMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure mdioMMD_ErrorMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_mdioMMD_ErrorMask u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure mdioTimeoutErrorMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_mdioTimeoutErrorMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioTimeoutErrorMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_mdioTimeoutErrorMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure mdioTimeoutErrorMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_mdioTimeoutErrorMask u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure watchdogTimerAlarmMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_watchdogTimerAlarmMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure watchdogTimerAlarmMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_watchdogTimerAlarmMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure watchdogTimerAlarmMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_watchdogTimerAlarmMask u2.word_2 + +/*! \brief Base register address of structure AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_baseRegisterAddress 0xFC00 +/*! \brief MMD address of structure AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure pmaStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_pmaStandardAlarm_1Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pmaStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_pmaStandardAlarm_1Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pmaStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_pmaStandardAlarm_1Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pmaStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_pmaStandardAlarm_2Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pmaStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_pmaStandardAlarm_2Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pmaStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_pmaStandardAlarm_2Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_pcsStandardAlarm_1Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_pcsStandardAlarm_1Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_pcsStandardAlarm_1Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_pcsStandardAlarm_2Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_pcsStandardAlarm_2Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_pcsStandardAlarm_2Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_3Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_pcsStandardAlarm_3Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_3Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_pcsStandardAlarm_3Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_3Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_pcsStandardAlarm_3Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure phyXS_StandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_phyXS_StandardAlarms_1Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_StandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_phyXS_StandardAlarms_1Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure phyXS_StandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_phyXS_StandardAlarms_1Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure phyXS_StandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_phyXS_StandardAlarms_2Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_StandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_phyXS_StandardAlarms_2Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure phyXS_StandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_phyXS_StandardAlarms_2Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationStandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_autonegotiationStandardAlarms_1Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationStandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_autonegotiationStandardAlarms_1Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationStandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_autonegotiationStandardAlarms_1Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationStandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_autonegotiationStandardAlarms_2Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationStandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_autonegotiationStandardAlarms_2Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationStandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_autonegotiationStandardAlarms_2Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure gbeStandardAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_gbeStandardAlarmsInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure gbeStandardAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_gbeStandardAlarmsInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure gbeStandardAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_gbeStandardAlarmsInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure allVendorAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_allVendorAlarmsInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure allVendorAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_allVendorAlarmsInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure allVendorAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_allVendorAlarmsInterrupt u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define AQ_GlobalChip_wideVendorInterruptFlags_HHD_baseRegisterAddress 0xFC01 +/*! \brief MMD address of structure AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define AQ_GlobalChip_wideVendorInterruptFlags_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure pmaVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define AQ_GlobalChip_wideVendorInterruptFlags_HHD_pmaVendorAlarmInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pmaVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_HHD_pmaVendorAlarmInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pmaVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_HHD_pmaVendorAlarmInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define AQ_GlobalChip_wideVendorInterruptFlags_HHD_pcsVendorAlarmInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_HHD_pcsVendorAlarmInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_HHD_pcsVendorAlarmInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure phyXS_VendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define AQ_GlobalChip_wideVendorInterruptFlags_HHD_phyXS_VendorAlarmInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_VendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_HHD_phyXS_VendorAlarmInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure phyXS_VendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_HHD_phyXS_VendorAlarmInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define AQ_GlobalChip_wideVendorInterruptFlags_HHD_autonegotiationVendorAlarmInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_HHD_autonegotiationVendorAlarmInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_HHD_autonegotiationVendorAlarmInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure gbeVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define AQ_GlobalChip_wideVendorInterruptFlags_HHD_gbeVendorAlarmInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure gbeVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_HHD_gbeVendorAlarmInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure gbeVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_HHD_gbeVendorAlarmInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_1Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define AQ_GlobalChip_wideVendorInterruptFlags_HHD_globalAlarms_1Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_1Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_HHD_globalAlarms_1Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_1Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_HHD_globalAlarms_1Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_2Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define AQ_GlobalChip_wideVendorInterruptFlags_HHD_globalAlarms_2Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_2Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_HHD_globalAlarms_2Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_2Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_HHD_globalAlarms_2Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_3Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define AQ_GlobalChip_wideVendorInterruptFlags_HHD_globalAlarms_3Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_3Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_HHD_globalAlarms_3Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_3Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_HHD_globalAlarms_3Interrupt u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define AQ_GlobalInterruptChip_wideStandardMask_HHD_baseRegisterAddress 0xFF00 +/*! \brief MMD address of structure AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define AQ_GlobalInterruptChip_wideStandardMask_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure pmaStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define AQ_GlobalInterruptChip_wideStandardMask_HHD_pmaStandardAlarm_1InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pmaStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_pmaStandardAlarm_1InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pmaStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_pmaStandardAlarm_1InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pmaStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define AQ_GlobalInterruptChip_wideStandardMask_HHD_pmaStandardAlarm_2InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pmaStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_pmaStandardAlarm_2InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pmaStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_pmaStandardAlarm_2InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define AQ_GlobalInterruptChip_wideStandardMask_HHD_pcsStandardAlarm_1InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_pcsStandardAlarm_1InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_pcsStandardAlarm_1InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define AQ_GlobalInterruptChip_wideStandardMask_HHD_pcsStandardAlarm_2InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_pcsStandardAlarm_2InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_pcsStandardAlarm_2InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_3InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define AQ_GlobalInterruptChip_wideStandardMask_HHD_pcsStandardAlarm_3InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_3InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_pcsStandardAlarm_3InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_3InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_pcsStandardAlarm_3InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure phyXS_StandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define AQ_GlobalInterruptChip_wideStandardMask_HHD_phyXS_StandardAlarms_1InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_StandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_phyXS_StandardAlarms_1InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure phyXS_StandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_phyXS_StandardAlarms_1InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure phyXS_StandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define AQ_GlobalInterruptChip_wideStandardMask_HHD_phyXS_StandardAlarms_2InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_StandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_phyXS_StandardAlarms_2InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure phyXS_StandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_phyXS_StandardAlarms_2InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationStandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define AQ_GlobalInterruptChip_wideStandardMask_HHD_autonegotiationStandardAlarms_1InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationStandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_autonegotiationStandardAlarms_1InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationStandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_autonegotiationStandardAlarms_1InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationStandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define AQ_GlobalInterruptChip_wideStandardMask_HHD_autonegotiationStandardAlarms_2InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationStandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_autonegotiationStandardAlarms_2InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationStandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_autonegotiationStandardAlarms_2InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure gbeStandardAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define AQ_GlobalInterruptChip_wideStandardMask_HHD_gbeStandardAlarmsInterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure gbeStandardAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_gbeStandardAlarmsInterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure gbeStandardAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_gbeStandardAlarmsInterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure allVendorAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define AQ_GlobalInterruptChip_wideStandardMask_HHD_allVendorAlarmsInterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure allVendorAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_allVendorAlarmsInterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure allVendorAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_allVendorAlarmsInterruptMask u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define AQ_GlobalInterruptChip_wideVendorMask_HHD_baseRegisterAddress 0xFF01 +/*! \brief MMD address of structure AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define AQ_GlobalInterruptChip_wideVendorMask_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure pmaVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define AQ_GlobalInterruptChip_wideVendorMask_HHD_pmaVendorAlarmInterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pmaVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_HHD_pmaVendorAlarmInterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pmaVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_HHD_pmaVendorAlarmInterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define AQ_GlobalInterruptChip_wideVendorMask_HHD_pcsVendorAlarmInterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_HHD_pcsVendorAlarmInterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_HHD_pcsVendorAlarmInterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure phyXS_VendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define AQ_GlobalInterruptChip_wideVendorMask_HHD_phyXS_VendorAlarmInterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_VendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_HHD_phyXS_VendorAlarmInterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure phyXS_VendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_HHD_phyXS_VendorAlarmInterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define AQ_GlobalInterruptChip_wideVendorMask_HHD_autonegotiationVendorAlarmInterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_HHD_autonegotiationVendorAlarmInterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_HHD_autonegotiationVendorAlarmInterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure gbeVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define AQ_GlobalInterruptChip_wideVendorMask_HHD_gbeVendorAlarmInterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure gbeVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_HHD_gbeVendorAlarmInterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure gbeVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_HHD_gbeVendorAlarmInterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define AQ_GlobalInterruptChip_wideVendorMask_HHD_globalAlarms_1InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_HHD_globalAlarms_1InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_HHD_globalAlarms_1InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define AQ_GlobalInterruptChip_wideVendorMask_HHD_globalAlarms_2InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_HHD_globalAlarms_2InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_HHD_globalAlarms_2InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_3InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define AQ_GlobalInterruptChip_wideVendorMask_HHD_globalAlarms_3InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_3InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_HHD_globalAlarms_3InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_3InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_HHD_globalAlarms_3InterruptMask u0.word_0 +#endif +/*@}*/ +/*@}*/ diff --git a/qca/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers_reversed.h b/qca/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers_reversed.h new file mode 100644 index 000000000..f6fe99831 --- /dev/null +++ b/qca/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers_reversed.h @@ -0,0 +1,12123 @@ +/*! \file +* This file contains the data structures and doxygen comments +* for the Global Registers block. + */ + +/*! \addtogroup registerMap + @{ +*/ + +/*! \defgroup Global_registers Global Registers +* This module contains the data structures and doxygen comments +* for the Global Registers block. + */ +/*********************************************************************** +* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +* +* $Date: 2014/04/08 $ +* +* $Label: $ +* +* Description: +* +* This file contains the c header structures for the registers contained in the Global Registers block. +* +* The bit fields in this structure are from MSbit to LSbit +* +***********************************************************************/ + + +/*@{*/ +#ifndef AQ_HHD_GLOBAL_REGS_HEADER +#define AQ_HHD_GLOBAL_REGS_HEADER + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Control 1: 1E.0000 */ +/* Global Standard Control 1: 1E.0000 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Control 1 */ + union + { + struct + { + /*! \brief 1E.0000.F R/WSC Soft Reset + AQ_GlobalStandardControl_1_HHD.u0.bits_0.softReset + + Default = 0x1 + + 1 = Global soft reset + 0 = Normal operation + + + Notes: + Resets the entire PHY. + Setting this bit initiates a global soft reset on all of the digital logic not including the microprocessor (i.e. microprocessor is not reset). Upon completion of the reset sequence, this bit is set back to 0by the microprocessor. Note this bit is OR'ed with the individual MMD resets. This bit should be set to 0 before setting the individual MMD resets. */ + unsigned int softReset : 1; /* 1E.0000.F R/WSC Default = 0x1 */ + /* 1 = Global soft reset + 0 = Normal operation + */ + unsigned int reserved0 : 3; + /*! \brief 1E.0000.B R/WPD Low Power + AQ_GlobalStandardControl_1_HHD.u0.bits_0.lowPower + + Provisionable Default = 0x0 + + 1 = Low-power mode + 0 = Normal operation + + + Notes: + A one written to this register causes the chip to enter low-power mode. This bit puts the entire chip in low-power mode, with only the MDIO and microprocessor functioning, and turns off the analog front-end: i.e. places it in high-impedance mode. Setting this bit also sets all of the Low Power bits in the other MMDs. */ + unsigned int lowPower : 1; /* 1E.0000.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Low-power mode + 0 = Normal operation + */ + unsigned int reserved1 : 11; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardControl_1_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Device Identifier: 1E.0002 */ +/* Global Standard Device Identifier: 1E.0002 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Device Identifier */ + union + { + struct + { + /*! \brief 1E.0002.F:0 RO Device ID MSW [1F:10] + AQ_GlobalStandardDeviceIdentifier_HHD.u0.bits_0.deviceIdMSW + + + + Bits 31 - 16 of Device ID + */ + unsigned int deviceIdMSW : 16; /* 1E.0002.F:0 RO */ + /* Bits 31 - 16 of Device ID */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Standard Device Identifier */ + union + { + struct + { + /*! \brief 1E.0003.F:0 RO Device ID LSW [F:0] + AQ_GlobalStandardDeviceIdentifier_HHD.u1.bits_1.deviceIdLSW + + + + Bits 15 - 0 of Device ID + */ + unsigned int deviceIdLSW : 16; /* 1E.0003.F:0 RO */ + /* Bits 15 - 0 of Device ID */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalStandardDeviceIdentifier_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Devices in Package: 1E.0005 */ +/* Global Standard Devices in Package: 1E.0005 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Devices in Package */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.0005.7 ROS Autonegotiation Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.autonegotiationPresent + + Default = 0x1 + + 1 = Autonegotiation is present in package + 0 = Autonegotiation is not present in package + + Notes: + This is always set to 1, as there is Autonegotiation in the PHY. */ + unsigned int autonegotiationPresent : 1; /* 1E.0005.7 ROS Default = 0x1 */ + /* 1 = Autonegotiation is present in package + 0 = Autonegotiation is not present in package */ + /*! \brief 1E.0005.6 ROS TC Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.tcPresent + + Default = 0x0 + + 1 = TC is present in package + 0 = TC is not present in package + + Notes: + This is always set to 0, as there is no TC functionality in the PHY. */ + unsigned int tcPresent : 1; /* 1E.0005.6 ROS Default = 0x0 */ + /* 1 = TC is present in package + 0 = TC is not present in package */ + /*! \brief 1E.0005.5 ROS DTE XS Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.dteXsPresent + + Default = 0x0 + + 1 = DTE XS is present in package + 0 = DTE XS is not present in package + + + Notes: + This is always set to 0, as there is no DTE XAUI interface in the PHY. */ + unsigned int dteXsPresent : 1; /* 1E.0005.5 ROS Default = 0x0 */ + /* 1 = DTE XS is present in package + 0 = DTE XS is not present in package + */ + /*! \brief 1E.0005.4 ROS PHY XS Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.phyXS_Present + + Default = 0x1 + + 1 = PHY XS is present in package + 0 = PHY XS is not present in package + + Notes: + This is always set to 1 as there is a PHY XS interface in the PHY. */ + unsigned int phyXS_Present : 1; /* 1E.0005.4 ROS Default = 0x1 */ + /* 1 = PHY XS is present in package + 0 = PHY XS is not present in package */ + /*! \brief 1E.0005.3 ROS PCS Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.pcsPresent + + Default = 0x1 + + 1 = PCS is present in package + 0 = PCS is not present in package + + Notes: + This is always set to 1 as there is PCS functionality in the PHY. */ + unsigned int pcsPresent : 1; /* 1E.0005.3 ROS Default = 0x1 */ + /* 1 = PCS is present in package + 0 = PCS is not present in package */ + /*! \brief 1E.0005.2 ROS WIS Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.wisPresent + + Default = 0x0 + + 1 = WIS is present in package + 0 = WIS is not present in package + + Notes: + This is always set to 0, as there is no WIS functionality in the PHY. */ + unsigned int wisPresent : 1; /* 1E.0005.2 ROS Default = 0x0 */ + /* 1 = WIS is present in package + 0 = WIS is not present in package */ + /*! \brief 1E.0005.1 ROS PMA Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.pmaPresent + + Default = 0x1 + + 1 = PMA is present in package + 0 = PMA is not present + + Notes: + This is always set to 1 as there is PMA functionality in the PHY. */ + unsigned int pmaPresent : 1; /* 1E.0005.1 ROS Default = 0x1 */ + /* 1 = PMA is present in package + 0 = PMA is not present */ + /*! \brief 1E.0005.0 ROS Clause 22 Registers Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.clause_22RegistersPresent + + Default = 0x0 + + 1 = Clause 22 registers are present in package + 0 = Clause 22 registers are not present in package + + Notes: + This is always set to 0 in the PHY, as there are no Clause 22 registers in the device. */ + unsigned int clause_22RegistersPresent : 1; /* 1E.0005.0 ROS Default = 0x0 */ + /* 1 = Clause 22 registers are present in package + 0 = Clause 22 registers are not present in package */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardDevicesInPackage_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Vendor Devices in Package: 1E.0006 */ +/* Global Standard Vendor Devices in Package: 1E.0006 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Vendor Devices in Package */ + union + { + struct + { + /*! \brief 1E.0006.F ROS Vendor Specific Device #2 Present + AQ_GlobalStandardVendorDevicesInPackage_HHD.u0.bits_0.vendorSpecificDevice_2Present + + Default = 0x1 + + 1 = Device #2 is present in package + 0 = Device #2 is not present in package + + Notes: + This is always set to 1 as the PHY utilizes this device for the DSP PMA registers. */ + unsigned int vendorSpecificDevice_2Present : 1; /* 1E.0006.F ROS Default = 0x1 */ + /* 1 = Device #2 is present in package + 0 = Device #2 is not present in package */ + /*! \brief 1E.0006.E ROS Vendor Specific Device #1 Present + AQ_GlobalStandardVendorDevicesInPackage_HHD.u0.bits_0.vendorSpecificDevice_1Present + + Default = 0x1 + + 1 = Device #1 is present in package + 0 = Device #1 is not present in package + + Notes: + This is always set to 1 as the PHY utilizes this device for the global control registers. */ + unsigned int vendorSpecificDevice_1Present : 1; /* 1E.0006.E ROS Default = 0x1 */ + /* 1 = Device #1 is present in package + 0 = Device #1 is not present in package */ + /*! \brief 1E.0006.D ROS Clause 22 Extension Present + AQ_GlobalStandardVendorDevicesInPackage_HHD.u0.bits_0.clause_22ExtensionPresent + + Default = 0x1 + + 1 = Clause 22 Extension is present in package + 0 = Clause 22 Extension is not present in package + + Notes: + This is always set to 1 as the PHY utilizes this device for the GbE registers. */ + unsigned int clause_22ExtensionPresent : 1; /* 1E.0006.D ROS Default = 0x1 */ + /* 1 = Clause 22 Extension is present in package + 0 = Clause 22 Extension is not present in package */ + unsigned int reserved0 : 13; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardVendorDevicesInPackage_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Status 2: 1E.0008 */ +/* Global Standard Status 2: 1E.0008 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Status 2 */ + union + { + struct + { + /*! \brief 1E.0008.F:E ROS Device Present [1:0] + AQ_GlobalStandardStatus_2_HHD.u0.bits_0.devicePresent + + Default = 0x2 + + [F:E] + 0x3 = No device at this address + 0x2 = Device present at this address + 0x1 = No device at this address + 0x0 = No device at this address + + Notes: + This field is always set to 0x2, as the Global MMD resides here in the PHY. */ + unsigned int devicePresent : 2; /* 1E.0008.F:E ROS Default = 0x2 */ + /* [F:E] + 0x3 = No device at this address + 0x2 = Device present at this address + 0x1 = No device at this address + 0x0 = No device at this address */ + unsigned int reserved0 : 14; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardStatus_2_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Package Identifier: 1E.000E */ +/* Global Standard Package Identifier: 1E.000E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Package Identifier */ + union + { + struct + { + /*! \brief 1E.000E.F:0 RO Package ID MSW [1F:10] + AQ_GlobalStandardPackageIdentifier_HHD.u0.bits_0.packageIdMSW + + + + Bits 31- 16 of Package ID + */ + unsigned int packageIdMSW : 16; /* 1E.000E.F:0 RO */ + /* Bits 31- 16 of Package ID */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Standard Package Identifier */ + union + { + struct + { + /*! \brief 1E.000F.F:0 RO Package ID LSW [F:0] + AQ_GlobalStandardPackageIdentifier_HHD.u1.bits_1.packageIdLSW + + + + Bits 15 - 0 of Package ID + */ + unsigned int packageIdLSW : 16; /* 1E.000F.F:0 RO */ + /* Bits 15 - 0 of Package ID */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalStandardPackageIdentifier_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Firmware ID: 1E.0020 */ +/* Global Firmware ID: 1E.0020 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Firmware ID */ + union + { + struct + { + /*! \brief 1E.0020.F:8 RO Firmware Major Revision Number [7:0] + AQ_GlobalFirmwareID_HHD.u0.bits_0.firmwareMajorRevisionNumber + + + + [F:8] = Major revision number + + Notes: + + + The lower six bits of major and minor firmware revision are exchanged in autonegotiation when the PHYID message is sent. */ + unsigned int firmwareMajorRevisionNumber : 8; /* 1E.0020.F:8 RO */ + /* [F:8] = Major revision number */ + /*! \brief 1E.0020.7:0 RO Firmware Minor Revision Number [7:0] + AQ_GlobalFirmwareID_HHD.u0.bits_0.firmwareMinorRevisionNumber + + + + [7:0] = Minor revision number + + Notes: + + + The lower six bits of major and minor firmware revision are exchanged in autonegotiation when the PHYID message is sent. */ + unsigned int firmwareMinorRevisionNumber : 8; /* 1E.0020.7:0 RO */ + /* [7:0] = Minor revision number */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalFirmwareID_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global NVR Interface: 1E.0100 */ +/* Global NVR Interface: 1E.0100 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0100.F R/WSC NVR Execute Operation + AQ_GlobalNvrInterface_HHD.u0.bits_0.nvrExecuteOperation + + Default = 0x0 + + 1 = Start NVR Operation + + + + Notes: + When set to 1, the NVR operation will begin. Ensure that the uP is stalled using the See MCP Run Stall bit to ensure no NVR contention. */ + unsigned int nvrExecuteOperation : 1; /* 1E.0100.F R/WSC Default = 0x0 */ + /* 1 = Start NVR Operation + + */ + /*! \brief 1E.0100.E R/W NVR Write Mode + AQ_GlobalNvrInterface_HHD.u0.bits_0.nvrWriteMode + + Default = 0x0 + + 1 = Write to NVR + 0 = Read from NVR + + */ + unsigned int nvrWriteMode : 1; /* 1E.0100.E R/W Default = 0x0 */ + /* 1 = Write to NVR + 0 = Read from NVR + */ + /*! \brief 1E.0100.D R/W Freeze NVR CRC + AQ_GlobalNvrInterface_HHD.u0.bits_0.freezeNvrCrc + + Default = 0x0 + + 1 = Freeze NVR Mailbox CRC calculation register + + + Notes: + To prevent an erroneous answer, this bit should not be set at the same time the See NVR Operation Valid bit is set. */ + unsigned int freezeNvrCrc : 1; /* 1E.0100.D R/W Default = 0x0 */ + /* 1 = Freeze NVR Mailbox CRC calculation register + */ + /*! \brief 1E.0100.C R/WSC Reset NVR CRC + AQ_GlobalNvrInterface_HHD.u0.bits_0.resetNvrCrc + + Default = 0x0 + + 1 = Reset NVR Mailbox CRC calculation register + + + + Notes: + To prevent an erroneous answer, this bit should not be set at the same time the See NVR Operation Valid bit is set. */ + unsigned int resetNvrCrc : 1; /* 1E.0100.C R/WSC Default = 0x0 */ + /* 1 = Reset NVR Mailbox CRC calculation register + + */ + unsigned int reserved0 : 1; + /*! \brief 1E.0100.A R/W NVR Burst + AQ_GlobalNvrInterface_HHD.u0.bits_0.nvrBurst + + Default = 0x0 + + 0 = Single read or write operation of up to 4 bytes + 1 = Burst operation + + + Notes: + When this bit is set, the operation is a burst operation where more than 32-bits is read from the NVR or written to the NVR. This bit should be set to one until the last burst in the read or write operation, when it should be set to zero. It operates by gating the SPI clock, and not restarting it until new data is ready to be written, or the previous contents have been read. Each burst of data requires the NVR Execute Operation bit to be set to initiate the next phase. */ + unsigned int nvrBurst : 1; /* 1E.0100.A R/W Default = 0x0 */ + /* 0 = Single read or write operation of up to 4 bytes + 1 = Burst operation + */ + unsigned int reserved1 : 1; + /*! \brief 1E.0100.8 RO NVR Busy + AQ_GlobalNvrInterface_HHD.u0.bits_0.nvrBusy + + + + 1 = NVR is busy + 0 = NVR is ready + + + Notes: + When set to 1, the NVR is busy. A new NVR operation should not occur until this bit is 0. If the NVR clock is greater than 64/63 of the MDIO clock, this bit never needs to be polled when operating over the MDIO. */ + unsigned int nvrBusy : 1; /* 1E.0100.8 RO */ + /* 1 = NVR is busy + 0 = NVR is ready + */ + /*! \brief 1E.0100.7:0 R/W NVR Opcode [7:0] + AQ_GlobalNvrInterface_HHD.u0.bits_0.nvrOpcode + + Default = 0x03 + + NVR instruction opcode + + */ + unsigned int nvrOpcode : 8; /* 1E.0100.7:0 R/W Default = 0x03 */ + /* NVR instruction opcode + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0101.F:0 RO NVR Mailbox CRC [F:0] + AQ_GlobalNvrInterface_HHD.u1.bits_1.nvrMailboxCrc + + + + The running CRC-16 of everything passing through the NVR interface + + + Notes: + The CRC-16 over all data written or read through the NVR interface. The CRC-16 is calculated by dividing the data by: + x^16 + x^12 + x^5 + 1 */ + unsigned int nvrMailboxCrc : 16; /* 1E.0101.F:0 RO */ + /* The running CRC-16 of everything passing through the NVR interface + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global NVR Interface */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.0102.7:0 R/W NVR Address MSW [17:10] + AQ_GlobalNvrInterface_HHD.u2.bits_2.nvrAddressMSW + + Default = 0x00 + + NVR address MSW bits [17:10] + + + Notes: + The address of where to read and write from in the NVR. This is self-incrementing and will automatically increment after each read or write operation. The increment amount is based on the data length (i.e. increments by 4 if the data length is 4 bytes) */ + unsigned int nvrAddressMSW : 8; /* 1E.0102.7:0 R/W Default = 0x00 */ + /* NVR address MSW bits [17:10] + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0103.F:0 R/W NVR Address LSW [F:0] + AQ_GlobalNvrInterface_HHD.u3.bits_3.nvrAddressLSW + + Default = 0x0000 + + NVR address LSW bits [F:0] + + + Notes: + The address of where to read and write from in the NVR. This is self-incrementing and will automatically increment after each read or write operation. */ + unsigned int nvrAddressLSW : 16; /* 1E.0103.F:0 R/W Default = 0x0000 */ + /* NVR address LSW bits [F:0] + */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0104.F:0 R/W NVR Data MSW [1F:10] + AQ_GlobalNvrInterface_HHD.u4.bits_4.nvrDataMSW + + Default = 0x0000 + + NVR data MSW bits [1F:10] + + + Notes: + Data is stored and read-out from these registers in little-endian format for operations such as FLASH device ID, and for programming the processor. + + For instance the 64K Atmel device code reads out as two bytes 0x651F into the LSW register, whereas the datasheet indicates that 1F is the first byte read, followed by 65 as the second byte. + + To burst read and write these 4 bytes in the correct order (where DD is written to address x), they should be stored as: + + AA BB in the MSW + CC DD in the LSW. */ + unsigned int nvrDataMSW : 16; /* 1E.0104.F:0 R/W Default = 0x0000 */ + /* NVR data MSW bits [1F:10] + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0105.F:0 R/W NVR Data LSW [F:0] + AQ_GlobalNvrInterface_HHD.u5.bits_5.nvrDataLSW + + Default = 0x0000 + + NVR data LSW bits [F:0] + + + Notes: + Data is stored and read-out from these registers in little-endian format for operations such as FLASH device ID, and for programming the processor. + + For instance the 64K Atmel device code reads out as two bytes 0x651F into the LSW register, whereas the datasheet indicates that 1F is the first byte read, followed by 65 as the second byte. + To burst read and write these 4 bytes in the correct order (where DD is written to address x), they should be stored as: + + AA BB in the MSW + CC DD in the LSW. */ + unsigned int nvrDataLSW : 16; /* 1E.0105.F:0 R/W Default = 0x0000 */ + /* NVR data LSW bits [F:0] + */ + } bits_5; + uint16_t word_5; + } u5; +} AQ_GlobalNvrInterface_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Mailbox Interface: 1E.0200 */ +/* Global Mailbox Interface: 1E.0200 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0200.F R/WSC uP Mailbox Execute Operation + AQ_GlobalMailboxInterface_HHD.u0.bits_0.upMailboxExecuteOperation + + Default = 0x0 + + 1 = Start of mailbox Operation + + + + Notes: + Indicates mailbox is loaded and ready */ + unsigned int upMailboxExecuteOperation : 1; /* 1E.0200.F R/WSC Default = 0x0 */ + /* 1 = Start of mailbox Operation + + */ + /*! \brief 1E.0200.E R/W uP Mailbox Write Mode + AQ_GlobalMailboxInterface_HHD.u0.bits_0.upMailboxWriteMode + + Default = 0x0 + + 1 = Write + 0 = Read + + + Notes: + Mailbox direction */ + unsigned int upMailboxWriteMode : 1; /* 1E.0200.E R/W Default = 0x0 */ + /* 1 = Write + 0 = Read + */ + unsigned int reserved0 : 1; + /*! \brief 1E.0200.C R/WSC Reset uP Mailbox CRC + AQ_GlobalMailboxInterface_HHD.u0.bits_0.resetUpMailboxCrc + + Default = 0x0 + + 1 = Reset uP mailbox CRC calculation register + + + */ + unsigned int resetUpMailboxCrc : 1; /* 1E.0200.C R/WSC Default = 0x0 */ + /* 1 = Reset uP mailbox CRC calculation register + + */ + unsigned int reserved1 : 3; + /*! \brief 1E.0200.8 RO uP Mailbox Busy + AQ_GlobalMailboxInterface_HHD.u0.bits_0.upMailboxBusy + + + + 1 = uP mailbox busy + 0 = uP mailbox ready + + + Notes: + In general the uP will respond within a few processor cycles to any PIF slave request, much faster than the MDIO. If the busy is asserted over multiple MDIO polling cycles, then a H/W error may have occurred and a Global S/W reset or uP reset is required. */ + unsigned int upMailboxBusy : 1; /* 1E.0200.8 RO */ + /* 1 = uP mailbox busy + 0 = uP mailbox ready + */ + unsigned int reserved2 : 8; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0201.F:0 RO uP Mailbox CRC [F:0] + AQ_GlobalMailboxInterface_HHD.u1.bits_1.upMailboxCrc + + + + The running CRC-16 of everything passing through the mailbox interface + + */ + unsigned int upMailboxCrc : 16; /* 1E.0201.F:0 RO */ + /* The running CRC-16 of everything passing through the mailbox interface + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0202.F:0 R/W uP Mailbox Address MSW [1F:10] + AQ_GlobalMailboxInterface_HHD.u2.bits_2.upMailboxAddressMSW + + Default = 0x0000 + + uP Mailbox MSW address + + + Notes: + The address of where to read and write from in the Microcontroller Mailbox. This is self-incrementing and automatically increments after each read and write operation.PHY */ + unsigned int upMailboxAddressMSW : 16; /* 1E.0202.F:0 R/W Default = 0x0000 */ + /* uP Mailbox MSW address + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0203.F:2 R/W uP Mailbox Address LSW [F:2] + AQ_GlobalMailboxInterface_HHD.u3.bits_3.upMailboxAddressLSW + + Default = 0x0000 + + uP LSW Mailbox address [F:2] + + + Notes: + The address of where to read and write from in the Microcontroller Mailbox. This is self-incrementing and automatically increments after each read and write operation.PHY */ + unsigned int upMailboxAddressLSW : 14; /* 1E.0203.F:2 R/W Default = 0x0000 */ + /* uP LSW Mailbox address [F:2] + */ + /*! \brief 1E.0203.1:0 RO uP Mailbox Address LSW Don't Care [1:0] + AQ_GlobalMailboxInterface_HHD.u3.bits_3.upMailboxAddressLSW_Don_tCare + + + + Least significant uP LSW Mailbox address bits [1:0] + + + Notes: + These bits are always set to 0 since each memory access is on a 4-byte boundary. */ + unsigned int upMailboxAddressLSW_Don_tCare : 2; /* 1E.0203.1:0 RO */ + /* Least significant uP LSW Mailbox address bits [1:0] + */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0204.F:0 R/W uP Mailbox Data MSW [1F:10] + AQ_GlobalMailboxInterface_HHD.u4.bits_4.upMailboxDataMSW + + Default = 0x0000 + + uP Mailbox data MSW + + */ + unsigned int upMailboxDataMSW : 16; /* 1E.0204.F:0 R/W Default = 0x0000 */ + /* uP Mailbox data MSW + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0205.F:0 R/W uP Mailbox Data LSW [F:0] + AQ_GlobalMailboxInterface_HHD.u5.bits_5.upMailboxDataLSW + + Default = 0x0000 + + uP Mailbox data LSW + + */ + unsigned int upMailboxDataLSW : 16; /* 1E.0205.F:0 R/W Default = 0x0000 */ + /* uP Mailbox data LSW + */ + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of Global Mailbox Interface */ + union + { + struct + { + unsigned int reserved0 : 14; + /*! \brief 1E.0206.1 R/W uP Mailbox CRC Read Enable + AQ_GlobalMailboxInterface_HHD.u6.bits_6.upMailboxCrcReadEnable + + Default = 0x0 + + 1 = Update uP mailbox CRC on read + + */ + unsigned int upMailboxCrcReadEnable : 1; /* 1E.0206.1 R/W Default = 0x0 */ + /* 1 = Update uP mailbox CRC on read + */ + unsigned int reserved1 : 1; + } bits_6; + uint16_t word_6; + } u6; +} AQ_GlobalMailboxInterface_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Microprocessor Scratch Pad: 1E.0300 */ +/* Global Microprocessor Scratch Pad: 1E.0300 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Microprocessor Scratch Pad */ + union + { + struct + { + /*! \brief 1E.0300.F:0 R/W Scratch Pad 1[F:0] + AQ_GlobalMicroprocessorScratchPad_HHD.u0.bits_0.scratchPad_1 + + Default = 0x0000 + + General Purpose Scratch Pad + */ + unsigned int scratchPad_1 : 16; /* 1E.0300.F:0 R/W Default = 0x0000 */ + /* General Purpose Scratch Pad */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Microprocessor Scratch Pad */ + union + { + struct + { + /*! \brief 1E.0301.F:0 R/W Scratch Pad 2 [F:0] + AQ_GlobalMicroprocessorScratchPad_HHD.u1.bits_1.scratchPad_2 + + Default = 0x0000 + + General Purpose Scratch Pad + */ + unsigned int scratchPad_2 : 16; /* 1E.0301.F:0 R/W Default = 0x0000 */ + /* General Purpose Scratch Pad */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalMicroprocessorScratchPad_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress Control Register: 1E.5002 */ +/* MSS Egress Control Register: 1E.5002 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress Control Register */ + union + { + struct + { + /*! \brief 1E.5002.F:D R/W MSS Egress Ethertype Explicit SECTag LSB [2:0] + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressEthertypeExplicitSectagLsb + + Default = 0x0 + + Ethertype for explicit SECTag bits 2:0. + + + Notes: + Ethertype for explicity SECTag. */ + unsigned int mssEgressEthertypeExplicitSectagLsb : 3; /* 1E.5002.F:D R/W Default = 0x0 */ + /* Ethertype for explicit SECTag bits 2:0. + */ + /*! \brief 1E.5002.C R/W MSS Egress Clear Global Time + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressClearGlobalTime + + Default = 0x0 + + 1 = Clear global time + + + + Notes: + Clear global time. */ + unsigned int mssEgressClearGlobalTime : 1; /* 1E.5002.C R/W Default = 0x0 */ + /* 1 = Clear global time + + */ + /*! \brief 1E.5002.B R/W MSS Egress Clear Counter + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressClearCounter + + Default = 0x0 + + 1 = Clear all MIB counters + + + + Notes: + If this bit is set to 1, all MIB counters will be cleared. */ + unsigned int mssEgressClearCounter : 1; /* 1E.5002.B R/W Default = 0x0 */ + /* 1 = Clear all MIB counters + + */ + /*! \brief 1E.5002.A R/W MSS Egress High Priority + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressHighPriority + + Default = 0x0 + + 1 = MIB counter clear on read enable + + + + Notes: + If this bit is set to 1, read is given high priority and the MIB count value becomes 0 after read. */ + unsigned int mssEgressHighPriority : 1; /* 1E.5002.A R/W Default = 0x0 */ + /* 1 = MIB counter clear on read enable + + */ + /*! \brief 1E.5002.9 R/W MSS Egress ICV LSB 8 Bytes Enable + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressIcvLsb_8BytesEnable + + Default = 0x0 + + 1 = Use LSB + 0 = Use MSB + + + + Notes: + This bit selects MSB or LSB 8 bytes selection in the case where the ICV is 8 bytes. + 0 = MSB is used. */ + unsigned int mssEgressIcvLsb_8BytesEnable : 1; /* 1E.5002.9 R/W Default = 0x0 */ + /* 1 = Use LSB + 0 = Use MSB + + */ + /*! \brief 1E.5002.8 R/W MSS Egress External Classification Enable + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressExternalClassificationEnable + + Default = 0x0 + + 1 = Drop EGPRC miss packets + + + + Notes: + If set, internal classification is bypassed. Should always be set to 0. */ + unsigned int mssEgressExternalClassificationEnable : 1; /* 1E.5002.8 R/W Default = 0x0 */ + /* 1 = Drop EGPRC miss packets + + */ + /*! \brief 1E.5002.7 R/W MSS Egress Explicit SECTag Report Short Length + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressExplicitSectagReportShortLength + + Default = 0x0 + + Reserved + + + + Notes: + Unused. */ + unsigned int mssEgressExplicitSectagReportShortLength : 1; /* 1E.5002.7 R/W Default = 0x0 */ + /* Reserved + + */ + /*! \brief 1E.5002.6 R/W MSS Egress Drop Invalid SA/SC Packets + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressDropInvalidSa_scPackets + + Default = 0x0 + + 1 = Drop invalid SA/SC packets + + + + Notes: + Enables dropping of invalid SA/SC packets. */ + unsigned int mssEgressDropInvalidSa_scPackets : 1; /* 1E.5002.6 R/W Default = 0x0 */ + /* 1 = Drop invalid SA/SC packets + + */ + /*! \brief 1E.5002.5 R/W MSS Egress Unmatched Use SC 0 + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressUnmatchedUseSc_0 + + Default = 0x0 + + 1 = Use SC 0 for unmatched packets + 0 = Unmatched packets are uncontrolled packets + + + + Notes: + Use SC-Index 0 as default SC for unmatched packets. Otherwise the packets are treated as uncontrolled packets. */ + unsigned int mssEgressUnmatchedUseSc_0 : 1; /* 1E.5002.5 R/W Default = 0x0 */ + /* 1 = Use SC 0 for unmatched packets + 0 = Unmatched packets are uncontrolled packets + + */ + /*! \brief 1E.5002.4 R/W MSS Egresss GCM Test Mode + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgresssGcmTestMode + + Default = 0x0 + + 1 = Enable GCM test mode + + + + Notes: + Enables GCM test mode */ + unsigned int mssEgresssGcmTestMode : 1; /* 1E.5002.4 R/W Default = 0x0 */ + /* 1 = Enable GCM test mode + + */ + /*! \brief 1E.5002.3 R/W MSS Egress GCM Start + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressGcmStart + + Default = 0x0 + + 1 = Start GCM + + + + Notes: + Indicates GCM to start */ + unsigned int mssEgressGcmStart : 1; /* 1E.5002.3 R/W Default = 0x0 */ + /* 1 = Start GCM + + */ + /*! \brief 1E.5002.2 R/W MSS Egress Drop EGPRC LUT Miss + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressDropEgprcLutMiss + + Default = 0x0 + + 1 = Drop Egress Classification LUT miss packets + + + + Notes: + Decides whether Egress Pre-Security Classification (EGPRC) LUT miss packets are to be dropped */ + unsigned int mssEgressDropEgprcLutMiss : 1; /* 1E.5002.2 R/W Default = 0x0 */ + /* 1 = Drop Egress Classification LUT miss packets + + */ + /*! \brief 1E.5002.1 R/W MSS Egress Drop KAY Packet + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressDropKayPacket + + Default = 0x0 + + 1 = Drop KAY packet + + + Notes: + Decides whether KAY packets have to be dropped */ + unsigned int mssEgressDropKayPacket : 1; /* 1E.5002.1 R/W Default = 0x0 */ + /* 1 = Drop KAY packet + */ + /*! \brief 1E.5002.0 R/W MSS Egress Soft Reset + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressSoftReset + + Default = 0x0 + + 1 = Soft reset + + + Notes: + S/W reset */ + unsigned int mssEgressSoftReset : 1; /* 1E.5002.0 R/W Default = 0x0 */ + /* 1 = Soft reset + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress Control Register */ + union + { + struct + { + unsigned int reserved0 : 3; + /*! \brief 1E.5003.C:0 R/W MSS Egress Ethertype Explicit SECTag MSB [F:3] + AQ_MssEgressControlRegister_HHD.u1.bits_1.mssEgressEthertypeExplicitSectagMsb + + Default = 0x0000 + + Ethertype for explicit SECTag bits 15:3. + + + Notes: + Ethertype for explicity SECTag. */ + unsigned int mssEgressEthertypeExplicitSectagMsb : 13; /* 1E.5003.C:0 R/W Default = 0x0000 */ + /* Ethertype for explicit SECTag bits 15:3. + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress VLAN TPID 0 Register: 1E.5008 */ +/* MSS Egress VLAN TPID 0 Register: 1E.5008 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress VLAN TPID 0 Register */ + union + { + struct + { + /*! \brief 1E.5008.F:0 R/W MSS Egress VLAN STag TPID [F:0] + AQ_MssEgressVlanTpid_0Register_HHD.u0.bits_0.mssEgressVlanStagTpid + + Default = 0x0000 + + STag TPID + + + Notes: + Service Tag Protocol Identifier (TPID) values to identify a VLAN tag. The " See SEC Egress VLAN CP Tag Parse STag " bit must be set to 1 for the incoming packet's TPID to be parsed. */ + unsigned int mssEgressVlanStagTpid : 16; /* 1E.5008.F:0 R/W Default = 0x0000 */ + /* STag TPID + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress VLAN TPID 0 Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressVlanTpid_0Register_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress VLAN TPID 1 Register: 1E.500A */ +/* MSS Egress VLAN TPID 1 Register: 1E.500A */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress VLAN TPID 1 Register */ + union + { + struct + { + /*! \brief 1E.500A.F:0 R/W MSS Egress VLAN QTag TPID [F:0] + AQ_MssEgressVlanTpid_1Register_HHD.u0.bits_0.mssEgressVlanQtagTpid + + Default = 0x0000 + + QTag TPID + + + Notes: + Customer Tag Protocol Identifier (TPID) values to identify a VLAN tag. The " See SEC Egress VLAN CP Tag Parse QTag " bit must be set to 1 for the incoming packet's TPID to be parsed. */ + unsigned int mssEgressVlanQtagTpid : 16; /* 1E.500A.F:0 R/W Default = 0x0000 */ + /* QTag TPID + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress VLAN TPID 1 Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressVlanTpid_1Register_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress VLAN Control Register: 1E.500C */ +/* MSS Egress VLAN Control Register: 1E.500C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress VLAN Control Register */ + union + { + struct + { + /*! \brief 1E.500C.F:0 R/W MSS Egress VLAN UP Map Table [F:0] + AQ_MssEgressVlanControlRegister_HHD.u0.bits_0.mssEgressVlanUpMapTable + + Default = 0x0000 + + UP Map table bits 15:0 + + + Notes: + If there is a customer TPID Tag match and no service TPID Tag match or the service TPID Tag match is disabled, the outer TAG's PCP is used to index into this map table to generate the packets user priority. + 2:0 : UP value for customer Tag PCP 0x0 + 5:3: UP value for customer Tag PCP 0x0 + 8:6 : UP value for customer Tag PCP 0x0 + 11:9 : UP value for customer Tag PCP 0x0 + 14:12 : UP value for customer Tag PCP 0x0 + 17:15 : UP value for customer Tag PCP 0x0 + 20:18 : UP value for customer Tag PCP 0x0 + 23:21 : UP value for customer Tag PCP 0x0 */ + unsigned int mssEgressVlanUpMapTable : 16; /* 1E.500C.F:0 R/W Default = 0x0000 */ + /* UP Map table bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress VLAN Control Register */ + union + { + struct + { + /*! \brief 1E.500D.F R/W MSS Egress VLAN QTag Parse Enable + AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanQtagParseEnable + + Default = 0x0 + + 1 = Enable VLAN QTag parsing + + + Notes: + Enable controlled port VLAN customer Tag parsing. When this bit is set to 1, the incoming packet's outer TPID will be compared with the configured " See SEC Egress TPID 1 [F:0] " for matching. If the " See SEC Egress VLAN CP Tag Parse QinQ " bit is set to1, this will also be used to compare the incoming packet's inner TPID. */ + unsigned int mssEgressVlanQtagParseEnable : 1; /* 1E.500D.F R/W Default = 0x0 */ + /* 1 = Enable VLAN QTag parsing + */ + /*! \brief 1E.500D.E R/W MSS Egress VLAN STag Parse Enable + AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanStagParseEnable + + Default = 0x0 + + 1 = Enable VLAN STag parsing + + + Notes: + Enable controlled port VLAN service Tag parsing. When this bit is set to 1, the incoming packets outer TPID will be compared with the configured " See SEC Egress TPID 0 [F:0] " for matching. If the " See SEC Egress VLAN CP Tag Parse QinQ " bit is set to1, this will also be used to compare the incoming packet's inner TPID. */ + unsigned int mssEgressVlanStagParseEnable : 1; /* 1E.500D.E R/W Default = 0x0 */ + /* 1 = Enable VLAN STag parsing + */ + /*! \brief 1E.500D.D R/W MSS Egress VLAN QinQ Parse Enable + AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanQinqParseEnable + + Default = 0x0 + + VLAN CP Tag Parse QinQ + + + Notes: + Enable controlled port VLAN QinQ Tag parsing. When this bit is set to 1 both the outer and inner VLAN Tags will be parsed. */ + unsigned int mssEgressVlanQinqParseEnable : 1; /* 1E.500D.D R/W Default = 0x0 */ + /* VLAN CP Tag Parse QinQ + */ + /*! \brief 1E.500D.C R/W MSS Egress VLAN QTag UP Parse Enable + AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanQtagUpParseEnable + + Default = 0x0 + + VLAN CP Tag QTag UP enable + + + Notes: + Enable controlled port customer VLAN customer Tag user priority field parsing. */ + unsigned int mssEgressVlanQtagUpParseEnable : 1; /* 1E.500D.C R/W Default = 0x0 */ + /* VLAN CP Tag QTag UP enable + */ + /*! \brief 1E.500D.B R/W MSS Egress VLAN STag UP Parse Enable + AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanStagUpParseEnable + + Default = 0x0 + + VLAN CP Tag STag UP enable + + + Notes: + Enable controlled port service VLAN service Tag user priority field parsing. */ + unsigned int mssEgressVlanStagUpParseEnable : 1; /* 1E.500D.B R/W Default = 0x0 */ + /* VLAN CP Tag STag UP enable + */ + /*! \brief 1E.500D.A:8 R/W MSS Egress VLAN UP Default [2:0] + AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanUpDefault + + Default = 0x0 + + UP default + + + Notes: + User priority default */ + unsigned int mssEgressVlanUpDefault : 3; /* 1E.500D.A:8 R/W Default = 0x0 */ + /* UP default + */ + /*! \brief 1E.500D.7:0 R/W MSS Egress VLAN UP Map Table MSW [17:10] + AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanUpMapTableMSW + + Default = 0x00 + + UP Map table bits 23:16 + + + Notes: + If there is a customer TPID Tag match and no service TPID Tag match or the service TPID Tag match is disabled, the outer TAG's PCP is used to index into this map table to generate the packets user priority. + 2:0 : UP value for customer Tag PCP 0x0 + 5:3: UP value for customer Tag PCP 0x0 + 8:6 : UP value for customer Tag PCP 0x0 + 11:9 : UP value for customer Tag PCP 0x0 + 14:12 : UP value for customer Tag PCP 0x0 + 17:15 : UP value for customer Tag PCP 0x0 + 20:18 : UP value for customer Tag PCP 0x0 + 23:21 : UP value for customer Tag PCP 0x0 */ + unsigned int mssEgressVlanUpMapTableMSW : 8; /* 1E.500D.7:0 R/W Default = 0x00 */ + /* UP Map table bits 23:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressVlanControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress PN Control Register: 1E.500E */ +/* MSS Egress PN Control Register: 1E.500E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress PN Control Register */ + union + { + struct + { + /*! \brief 1E.500E.F:0 R/W MSS Egress SA PN Threshold LSW [F:0] + AQ_MssEgressPnControlRegister_HHD.u0.bits_0.mssEgressSaPnThresholdLSW + + Default = 0x0000 + + PN threshold bits 15:0 + + + Notes: + Egress PN threshold to generate SA threshold interrupt. */ + unsigned int mssEgressSaPnThresholdLSW : 16; /* 1E.500E.F:0 R/W Default = 0x0000 */ + /* PN threshold bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress PN Control Register */ + union + { + struct + { + /*! \brief 1E.500F.F:0 R/W MSS Egress SA PN Threshold MSW [1F:10] + AQ_MssEgressPnControlRegister_HHD.u1.bits_1.mssEgressSaPnThresholdMSW + + Default = 0x0000 + + PN threshold bits 31:16 + + + Notes: + Egress PN threshold to generate SA threshold interrupt. */ + unsigned int mssEgressSaPnThresholdMSW : 16; /* 1E.500F.F:0 R/W Default = 0x0000 */ + /* PN threshold bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressPnControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress MTU Size Control Register: 1E.5010 */ +/* MSS Egress MTU Size Control Register: 1E.5010 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress MTU Size Control Register */ + union + { + struct + { + /*! \brief 1E.5010.F:0 R/W MSS Egress Controlled Packet MTU Size [F:0] + AQ_MssEgressMtuSizeControlRegister_HHD.u0.bits_0.mssEgressControlledPacketMtuSize + + Default = 0x05DC + + Maximum transmission unit for controlled packet + + + Notes: + Maximum transmission unit of controlled packet */ + unsigned int mssEgressControlledPacketMtuSize : 16; /* 1E.5010.F:0 R/W Default = 0x05DC */ + /* Maximum transmission unit for controlled packet + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress MTU Size Control Register */ + union + { + struct + { + /*! \brief 1E.5011.F:0 R/W MSS Egress Uncontrolled Packet MTU Size [F:0] + AQ_MssEgressMtuSizeControlRegister_HHD.u1.bits_1.mssEgressUncontrolledPacketMtuSize + + Default = 0x05DC + + Maximum transmission unit for uncontrolled packet + + + Notes: + Maximum transmission unit of uncontrolled packet */ + unsigned int mssEgressUncontrolledPacketMtuSize : 16; /* 1E.5011.F:0 R/W Default = 0x05DC */ + /* Maximum transmission unit for uncontrolled packet + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressMtuSizeControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress Interrupt Status Register: 1E.505C */ +/* MSS Egress Interrupt Status Register: 1E.505C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress Interrupt Status Register */ + union + { + struct + { + unsigned int reserved0 : 11; + /*! \brief 1E.505C.4 COW MSS Egress ECC Error Interrupt + AQ_MssEgressInterruptStatusRegister_HHD.u0.bits_0.mssEgressEccErrorInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when anyone of the memories detects an ECC error. */ + unsigned int mssEgressEccErrorInterrupt : 1; /* 1E.505C.4 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.505C.3 COW MSS Egress MIB Saturation Interrupt + AQ_MssEgressInterruptStatusRegister_HHD.u0.bits_0.mssEgressMibSaturationInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when the MIB counters reaches all ones saturation. */ + unsigned int mssEgressMibSaturationInterrupt : 1; /* 1E.505C.3 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.505C.2 COW MSS Egress SA Threshold Expired Interrupt + AQ_MssEgressInterruptStatusRegister_HHD.u0.bits_0.mssEgressSaThresholdExpiredInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when the SA PN reaches the See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . */ + unsigned int mssEgressSaThresholdExpiredInterrupt : 1; /* 1E.505C.2 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.505C.1 COW MSS Egress SA Expired Interrupt + AQ_MssEgressInterruptStatusRegister_HHD.u0.bits_0.mssEgressSaExpiredInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when the SA PN reaches all ones saturation. */ + unsigned int mssEgressSaExpiredInterrupt : 1; /* 1E.505C.1 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.505C.0 COW MSS Egress Master Interrupt + AQ_MssEgressInterruptStatusRegister_HHD.u0.bits_0.mssEgressMasterInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when any one of the above interrupt and the corresponding interrupt enable are both set. The interrupt enable for this bit must also be set for this bit to be set. */ + unsigned int mssEgressMasterInterrupt : 1; /* 1E.505C.0 COW Default = 0x0 */ + /* 1 = Interrupt + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress Interrupt Status Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressInterruptStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress Interrupt Mask Register: 1E.505E */ +/* MSS Egress Interrupt Mask Register: 1E.505E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress Interrupt Mask Register */ + union + { + struct + { + unsigned int reserved0 : 11; + /*! \brief 1E.505E.4 COW MSS Egress ECC Error Interrupt Enable + AQ_MssEgressInterruptMaskRegister_HHD.u0.bits_0.mssEgressEccErrorInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + + Notes: + Write to 1 to clear. This bit is set when anyone of the memories detects an ECC error. */ + unsigned int mssEgressEccErrorInterruptEnable : 1; /* 1E.505E.4 COW Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.505E.3 COW MSS Egress MIB Saturation Interrupt Enable + AQ_MssEgressInterruptMaskRegister_HHD.u0.bits_0.mssEgressMibSaturationInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + + Notes: + Write to 1 to clear. This bit is set when the MIB counters reaches all ones saturation. */ + unsigned int mssEgressMibSaturationInterruptEnable : 1; /* 1E.505E.3 COW Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.505E.2 COW MSS Egress SA Expired Threshold Interrupt Enable + AQ_MssEgressInterruptMaskRegister_HHD.u0.bits_0.mssEgressSaExpiredThresholdInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + + Notes: + Write to 1 to clear. This bit is set when the SA PN reaches the configured threshold See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . */ + unsigned int mssEgressSaExpiredThresholdInterruptEnable : 1; /* 1E.505E.2 COW Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.505E.1 COW MSS Egress SA Expired Interrupt Enable + AQ_MssEgressInterruptMaskRegister_HHD.u0.bits_0.mssEgressSaExpiredInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + + Notes: + Write to 1 to clear. This bit is set when the SA PN reaches all ones saturation. */ + unsigned int mssEgressSaExpiredInterruptEnable : 1; /* 1E.505E.1 COW Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.505E.0 COW MSS Egress Master Interrupt Enable + AQ_MssEgressInterruptMaskRegister_HHD.u0.bits_0.mssEgressMasterInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + + Notes: + Write to 1 to clear. */ + unsigned int mssEgressMasterInterruptEnable : 1; /* 1E.505E.0 COW Default = 0x0 */ + /* 1 = Interrupt enabled + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress Interrupt Mask Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressInterruptMaskRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress SA Expired Status Register: 1E.5060 */ +/* MSS Egress SA Expired Status Register: 1E.5060 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress SA Expired Status Register */ + union + { + struct + { + /*! \brief 1E.5060.F:0 COW MSS Egress SA Expired LSW [F:0] + AQ_MssEgressSaExpiredStatusRegister_HHD.u0.bits_0.mssEgressSaExpiredLSW + + Default = 0x0000 + + SA expired bits 15:0 + + + Notes: + Write these bits to 1 to clear. + When set, these bits identify the SA that has expired when the SA PN reaches all-ones saturation. */ + unsigned int mssEgressSaExpiredLSW : 16; /* 1E.5060.F:0 COW Default = 0x0000 */ + /* SA expired bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress SA Expired Status Register */ + union + { + struct + { + /*! \brief 1E.5061.F:0 COW MSS Egress SA Expired MSW [1F:10] + AQ_MssEgressSaExpiredStatusRegister_HHD.u1.bits_1.mssEgressSaExpiredMSW + + Default = 0x0000 + + SA expired bits 31:16 + + + Notes: + Write these bits to 1 to clear. + When set, these bits identify the SA that has expired when the SA PN reaches all-ones saturation. */ + unsigned int mssEgressSaExpiredMSW : 16; /* 1E.5061.F:0 COW Default = 0x0000 */ + /* SA expired bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressSaExpiredStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress SA Threshold Expired Status Register: 1E.5062 */ +/* MSS Egress SA Threshold Expired Status Register: 1E.5062 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress SA Threshold Expired Status Register */ + union + { + struct + { + /*! \brief 1E.5062.F:0 COW MSS Egress SA Threshold Expired LSW [F:0] + AQ_MssEgressSaThresholdExpiredStatusRegister_HHD.u0.bits_0.mssEgressSaThresholdExpiredLSW + + Default = 0x0000 + + SA threshold expired bits 15:0 + + + Notes: + Write these bits to 1 to clear. + When set, these bits identify the SA that has expired when the SA PN has reached the configured threshold See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . */ + unsigned int mssEgressSaThresholdExpiredLSW : 16; /* 1E.5062.F:0 COW Default = 0x0000 */ + /* SA threshold expired bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress SA Threshold Expired Status Register */ + union + { + struct + { + /*! \brief 1E.5063.F:0 COW MSS Egress SA Threshold Expired MSW [1F:10] + AQ_MssEgressSaThresholdExpiredStatusRegister_HHD.u1.bits_1.mssEgressSaThresholdExpiredMSW + + Default = 0x0000 + + SA threshold expired bits 31:16 + + + Notes: + Write these bits to 1 to clear. + When set, these bits identify the SA that has expired when the SA PN has reached the configured threshold See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . */ + unsigned int mssEgressSaThresholdExpiredMSW : 16; /* 1E.5063.F:0 COW Default = 0x0000 */ + /* SA threshold expired bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressSaThresholdExpiredStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress ECC Interrupt Status Register: 1E.5064 */ +/* MSS Egress ECC Interrupt Status Register: 1E.5064 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress ECC Interrupt Status Register */ + union + { + struct + { + /*! \brief 1E.5064.F:0 COW MSS Egress SA ECC Error Interrupt LSW [F:0] + AQ_MssEgressEccInterruptStatusRegister_HHD.u0.bits_0.mssEgressSaEccErrorInterruptLSW + + Default = 0x0000 + + SA ECC error interrupt bits 15:0 + + + Notes: + Write these bits to 1 to clear. + When set to 1, indicates that an ECC error occured for the SA. */ + unsigned int mssEgressSaEccErrorInterruptLSW : 16; /* 1E.5064.F:0 COW Default = 0x0000 */ + /* SA ECC error interrupt bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress ECC Interrupt Status Register */ + union + { + struct + { + /*! \brief 1E.5065.F:0 COW MSS Egress SA ECC Error Interrupt MSW [1F:10] + AQ_MssEgressEccInterruptStatusRegister_HHD.u1.bits_1.mssEgressSaEccErrorInterruptMSW + + Default = 0x0000 + + SA ECC error interrupt bits 31:16 + + + Notes: + Write these bits to 1 to clear. + When set to 1, indicates that an ECC error occured for the SA. */ + unsigned int mssEgressSaEccErrorInterruptMSW : 16; /* 1E.5065.F:0 COW Default = 0x0000 */ + /* SA ECC error interrupt bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressEccInterruptStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress LUT Address Control Register: 1E.5080 */ +/* MSS Egress LUT Address Control Register: 1E.5080 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress LUT Address Control Register */ + union + { + struct + { + /*! \brief 1E.5080.F:C R/W MSS Egress LUT Select [3:0] + AQ_MssEgressLutAddressControlRegister_HHD.u0.bits_0.mssEgressLutSelect + + Default = 0x0 + + LUT select + + + Notes: + 0x0 : Egress MAC Control FIlter (CTLF) LUT + 0x1 : Egress Classification LUT + 0x2 : Egress SC/SA LUT + 0x3 : Egress SMIB */ + unsigned int mssEgressLutSelect : 4; /* 1E.5080.F:C R/W Default = 0x0 */ + /* LUT select + */ + unsigned int reserved0 : 3; + /*! \brief 1E.5080.8:0 R/W MSS Egress LUT Address [8:0] + AQ_MssEgressLutAddressControlRegister_HHD.u0.bits_0.mssEgressLutAddress + + Default = 0x000 + + LUT address + + */ + unsigned int mssEgressLutAddress : 9; /* 1E.5080.8:0 R/W Default = 0x000 */ + /* LUT address + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_MssEgressLutAddressControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress LUT Control Register: 1E.5081 */ +/* MSS Egress LUT Control Register: 1E.5081 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress LUT Control Register */ + union + { + struct + { + /*! \brief 1E.5081.F R/W MSS Egress LUT Write + AQ_MssEgressLutControlRegister_HHD.u0.bits_0.mssEgressLutWrite + + Default = 0x0 + + 1 = LUT write + + + Notes: + Setting this bit to 1, will write the LUT. This bit will automatically clear to 0. */ + unsigned int mssEgressLutWrite : 1; /* 1E.5081.F R/W Default = 0x0 */ + /* 1 = LUT write + */ + /*! \brief 1E.5081.E R/W MSS Egress LUT Read + AQ_MssEgressLutControlRegister_HHD.u0.bits_0.mssEgressLutRead + + Default = 0x0 + + 1 = LUT read + + + Notes: + Setting this bit to 1, will read the LUT. This bit will automatically clear to 0. */ + unsigned int mssEgressLutRead : 1; /* 1E.5081.E R/W Default = 0x0 */ + /* 1 = LUT read + */ + unsigned int reserved0 : 14; + } bits_0; + uint16_t word_0; + } u0; +} AQ_MssEgressLutControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress LUT Data Control Register: 1E.50A0 */ +/* MSS Egress LUT Data Control Register: 1E.50A0 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A0.F:0 R/W MSS Egress LUT Data 0 [F:0] + AQ_MssEgressLutDataControlRegister_HHD.u0.bits_0.mssEgressLutData_0 + + Default = 0x0000 + + LUT data bits 15:0 + + */ + unsigned int mssEgressLutData_0 : 16; /* 1E.50A0.F:0 R/W Default = 0x0000 */ + /* LUT data bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A1.F:0 R/W MSS Egress LUT Data 1 [1F:10] + AQ_MssEgressLutDataControlRegister_HHD.u1.bits_1.mssEgressLutData_1 + + Default = 0x0000 + + LUT data bits 31:16 + + */ + unsigned int mssEgressLutData_1 : 16; /* 1E.50A1.F:0 R/W Default = 0x0000 */ + /* LUT data bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A2.F:0 R/W MSS Egress LUT Data 2 [2F:20] + AQ_MssEgressLutDataControlRegister_HHD.u2.bits_2.mssEgressLutData_2 + + Default = 0x0000 + + LUT data bits 47:32 + + */ + unsigned int mssEgressLutData_2 : 16; /* 1E.50A2.F:0 R/W Default = 0x0000 */ + /* LUT data bits 47:32 + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A3.F:0 R/W MSS Egress LUT Data 3 [3F:30] + AQ_MssEgressLutDataControlRegister_HHD.u3.bits_3.mssEgressLutData_3 + + Default = 0x0000 + + LUT data bits 63:48 + + */ + unsigned int mssEgressLutData_3 : 16; /* 1E.50A3.F:0 R/W Default = 0x0000 */ + /* LUT data bits 63:48 + */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A4.F:0 R/W MSS Egress LUT Data 4 [4F:40] + AQ_MssEgressLutDataControlRegister_HHD.u4.bits_4.mssEgressLutData_4 + + Default = 0x0000 + + LUT data bits 79:64 + + */ + unsigned int mssEgressLutData_4 : 16; /* 1E.50A4.F:0 R/W Default = 0x0000 */ + /* LUT data bits 79:64 + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A5.F:0 R/W MSS Egress LUT Data 5 [5F:50] + AQ_MssEgressLutDataControlRegister_HHD.u5.bits_5.mssEgressLutData_5 + + Default = 0x0000 + + LUT data bits 95:80 + + */ + unsigned int mssEgressLutData_5 : 16; /* 1E.50A5.F:0 R/W Default = 0x0000 */ + /* LUT data bits 95:80 + */ + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A6.F:0 R/W MSS Egress LUT Data 6 [6F:60] + AQ_MssEgressLutDataControlRegister_HHD.u6.bits_6.mssEgressLutData_6 + + Default = 0x0000 + + LUT data bits 111:96 + + */ + unsigned int mssEgressLutData_6 : 16; /* 1E.50A6.F:0 R/W Default = 0x0000 */ + /* LUT data bits 111:96 + */ + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A7.F:0 R/W MSS Egress LUT Data 7 [7F:70] + AQ_MssEgressLutDataControlRegister_HHD.u7.bits_7.mssEgressLutData_7 + + Default = 0x0000 + + LUT data bits 127:112 + + */ + unsigned int mssEgressLutData_7 : 16; /* 1E.50A7.F:0 R/W Default = 0x0000 */ + /* LUT data bits 127:112 + */ + } bits_7; + uint16_t word_7; + } u7; + /*! \brief Union for bit and word level access of word 8 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A8.F:0 R/W MSS Egress LUT Data 8 [8F:80] + AQ_MssEgressLutDataControlRegister_HHD.u8.bits_8.mssEgressLutData_8 + + Default = 0x0000 + + LUT data bits 143:128 + + */ + unsigned int mssEgressLutData_8 : 16; /* 1E.50A8.F:0 R/W Default = 0x0000 */ + /* LUT data bits 143:128 + */ + } bits_8; + uint16_t word_8; + } u8; + /*! \brief Union for bit and word level access of word 9 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A9.F:0 R/W MSS Egress LUT Data 9 [9F:90] + AQ_MssEgressLutDataControlRegister_HHD.u9.bits_9.mssEgressLutData_9 + + Default = 0x0000 + + LUT data bits 159:144 + + */ + unsigned int mssEgressLutData_9 : 16; /* 1E.50A9.F:0 R/W Default = 0x0000 */ + /* LUT data bits 159:144 + */ + } bits_9; + uint16_t word_9; + } u9; + /*! \brief Union for bit and word level access of word 10 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50AA.F:0 R/W MSS Egress LUT Data 10 [AF:A0] + AQ_MssEgressLutDataControlRegister_HHD.u10.bits_10.mssEgressLutData_10 + + Default = 0x0000 + + LUT data bits 175:160 + + */ + unsigned int mssEgressLutData_10 : 16; /* 1E.50AA.F:0 R/W Default = 0x0000 */ + /* LUT data bits 175:160 + */ + } bits_10; + uint16_t word_10; + } u10; + /*! \brief Union for bit and word level access of word 11 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50AB.F:0 R/W MSS Egress LUT Data 11 [BF:B0] + AQ_MssEgressLutDataControlRegister_HHD.u11.bits_11.mssEgressLutData_11 + + Default = 0x0000 + + LUT data bits 191:176 + + */ + unsigned int mssEgressLutData_11 : 16; /* 1E.50AB.F:0 R/W Default = 0x0000 */ + /* LUT data bits 191:176 + */ + } bits_11; + uint16_t word_11; + } u11; + /*! \brief Union for bit and word level access of word 12 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50AC.F:0 R/W MSS Egress LUT Data 12 [CF:C0] + AQ_MssEgressLutDataControlRegister_HHD.u12.bits_12.mssEgressLutData_12 + + Default = 0x0000 + + LUT data bits 207:192 + + */ + unsigned int mssEgressLutData_12 : 16; /* 1E.50AC.F:0 R/W Default = 0x0000 */ + /* LUT data bits 207:192 + */ + } bits_12; + uint16_t word_12; + } u12; + /*! \brief Union for bit and word level access of word 13 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50AD.F:0 R/W MSS Egress LUT Data 13 [DF:D0] + AQ_MssEgressLutDataControlRegister_HHD.u13.bits_13.mssEgressLutData_13 + + Default = 0x0000 + + LUT data bits 223:208 + + */ + unsigned int mssEgressLutData_13 : 16; /* 1E.50AD.F:0 R/W Default = 0x0000 */ + /* LUT data bits 223:208 + */ + } bits_13; + uint16_t word_13; + } u13; + /*! \brief Union for bit and word level access of word 14 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50AE.F:0 R/W MSS Egress LUT Data 14 [EF:E0] + AQ_MssEgressLutDataControlRegister_HHD.u14.bits_14.mssEgressLutData_14 + + Default = 0x0000 + + LUT data bits 239:224 + + */ + unsigned int mssEgressLutData_14 : 16; /* 1E.50AE.F:0 R/W Default = 0x0000 */ + /* LUT data bits 239:224 + */ + } bits_14; + uint16_t word_14; + } u14; + /*! \brief Union for bit and word level access of word 15 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50AF.F:0 R/W MSS Egress LUT Data 15 [FF:F0] + AQ_MssEgressLutDataControlRegister_HHD.u15.bits_15.mssEgressLutData_15 + + Default = 0x0000 + + LUT data bits 255:240 + + */ + unsigned int mssEgressLutData_15 : 16; /* 1E.50AF.F:0 R/W Default = 0x0000 */ + /* LUT data bits 255:240 + */ + } bits_15; + uint16_t word_15; + } u15; + /*! \brief Union for bit and word level access of word 16 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B0.F:0 R/W MSS Egress LUT Data 16 [10F:100] + AQ_MssEgressLutDataControlRegister_HHD.u16.bits_16.mssEgressLutData_16 + + Default = 0x0000 + + LUT data bits 271:256 + + */ + unsigned int mssEgressLutData_16 : 16; /* 1E.50B0.F:0 R/W Default = 0x0000 */ + /* LUT data bits 271:256 + */ + } bits_16; + uint16_t word_16; + } u16; + /*! \brief Union for bit and word level access of word 17 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B1.F:0 R/W MSS Egress LUT Data 17 [11F:110] + AQ_MssEgressLutDataControlRegister_HHD.u17.bits_17.mssEgressLutData_17 + + Default = 0x0000 + + LUT data bits 287:272 + + */ + unsigned int mssEgressLutData_17 : 16; /* 1E.50B1.F:0 R/W Default = 0x0000 */ + /* LUT data bits 287:272 + */ + } bits_17; + uint16_t word_17; + } u17; + /*! \brief Union for bit and word level access of word 18 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B2.F:0 R/W MSS Egress LUT Data 18 [12F:120] + AQ_MssEgressLutDataControlRegister_HHD.u18.bits_18.mssEgressLutData_18 + + Default = 0x0000 + + LUT data bits 303:288 + + */ + unsigned int mssEgressLutData_18 : 16; /* 1E.50B2.F:0 R/W Default = 0x0000 */ + /* LUT data bits 303:288 + */ + } bits_18; + uint16_t word_18; + } u18; + /*! \brief Union for bit and word level access of word 19 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B3.F:0 R/W MSS Egress LUT Data 19 [13F:130] + AQ_MssEgressLutDataControlRegister_HHD.u19.bits_19.mssEgressLutData_19 + + Default = 0x0000 + + LUT data bits 319:304 + + */ + unsigned int mssEgressLutData_19 : 16; /* 1E.50B3.F:0 R/W Default = 0x0000 */ + /* LUT data bits 319:304 + */ + } bits_19; + uint16_t word_19; + } u19; + /*! \brief Union for bit and word level access of word 20 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B4.F:0 R/W MSS Egress LUT Data 20 [14F:140] + AQ_MssEgressLutDataControlRegister_HHD.u20.bits_20.mssEgressLutData_20 + + Default = 0x0000 + + LUT data bits 335:320 + + */ + unsigned int mssEgressLutData_20 : 16; /* 1E.50B4.F:0 R/W Default = 0x0000 */ + /* LUT data bits 335:320 + */ + } bits_20; + uint16_t word_20; + } u20; + /*! \brief Union for bit and word level access of word 21 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B5.F:0 R/W MSS Egress LUT Data 21 [15F:150] + AQ_MssEgressLutDataControlRegister_HHD.u21.bits_21.mssEgressLutData_21 + + Default = 0x0000 + + LUT data bits 351:336 + + */ + unsigned int mssEgressLutData_21 : 16; /* 1E.50B5.F:0 R/W Default = 0x0000 */ + /* LUT data bits 351:336 + */ + } bits_21; + uint16_t word_21; + } u21; + /*! \brief Union for bit and word level access of word 22 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B6.F:0 R/W MSS Egress LUT Data 22 [16F:160] + AQ_MssEgressLutDataControlRegister_HHD.u22.bits_22.mssEgressLutData_22 + + Default = 0x0000 + + LUT data bits 367:352 + + */ + unsigned int mssEgressLutData_22 : 16; /* 1E.50B6.F:0 R/W Default = 0x0000 */ + /* LUT data bits 367:352 + */ + } bits_22; + uint16_t word_22; + } u22; + /*! \brief Union for bit and word level access of word 23 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B7.F:0 R/W MSS Egress LUT Data 23 [17F:170] + AQ_MssEgressLutDataControlRegister_HHD.u23.bits_23.mssEgressLutData_23 + + Default = 0x0000 + + LUT data bits 383:368 + + */ + unsigned int mssEgressLutData_23 : 16; /* 1E.50B7.F:0 R/W Default = 0x0000 */ + /* LUT data bits 383:368 + */ + } bits_23; + uint16_t word_23; + } u23; + /*! \brief Union for bit and word level access of word 24 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B8.F:0 R/W MSS Egress LUT Data 24 [18F:180] + AQ_MssEgressLutDataControlRegister_HHD.u24.bits_24.mssEgressLutData_24 + + Default = 0x0000 + + LUT data bits 399:384 + + */ + unsigned int mssEgressLutData_24 : 16; /* 1E.50B8.F:0 R/W Default = 0x0000 */ + /* LUT data bits 399:384 + */ + } bits_24; + uint16_t word_24; + } u24; + /*! \brief Union for bit and word level access of word 25 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B9.F:0 R/W MSS Egress LUT Data 25 [19F:190] + AQ_MssEgressLutDataControlRegister_HHD.u25.bits_25.mssEgressLutData_25 + + Default = 0x0000 + + LUT data bits 415:400 + + */ + unsigned int mssEgressLutData_25 : 16; /* 1E.50B9.F:0 R/W Default = 0x0000 */ + /* LUT data bits 415:400 + */ + } bits_25; + uint16_t word_25; + } u25; + /*! \brief Union for bit and word level access of word 26 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50BA.F:0 R/W MSS Egress LUT Data 26 [1AF:1A0] + AQ_MssEgressLutDataControlRegister_HHD.u26.bits_26.mssEgressLutData_26 + + Default = 0x0000 + + LUT data bits 431:416 + + */ + unsigned int mssEgressLutData_26 : 16; /* 1E.50BA.F:0 R/W Default = 0x0000 */ + /* LUT data bits 431:416 + */ + } bits_26; + uint16_t word_26; + } u26; + /*! \brief Union for bit and word level access of word 27 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50BB.F:0 R/W MSS Egress LUT Data 27 [1BF:1B0] + AQ_MssEgressLutDataControlRegister_HHD.u27.bits_27.mssEgressLutData_27 + + Default = 0x0000 + + LUT data bits 447:432 + + */ + unsigned int mssEgressLutData_27 : 16; /* 1E.50BB.F:0 R/W Default = 0x0000 */ + /* LUT data bits 447:432 + */ + } bits_27; + uint16_t word_27; + } u27; +} AQ_MssEgressLutDataControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System General Control Register: 1E.6004 */ +/* MSM System General Control Register: 1E.6004 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System General Control Register */ + union + { + struct + { + /*! \brief 1E.6004.F R/W MSM System PHY Tx Enable + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemPhyTxEnable + + Default = 0x0 + + 1 = Enable PHY Tx + + + Notes: + Directly controls the phy_tx_ena pin. */ + unsigned int msmSystemPhyTxEnable : 1; /* 1E.6004.F R/W Default = 0x0 */ + /* 1 = Enable PHY Tx + */ + /*! \brief 1E.6004.E R/W MSM System Rx Error Discard + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemRxErrorDiscard + + Default = 0x0 + + 1 = Enable discard of received errored frames + + + Notes: + Rx errored frame discard enable. When set to 1, any frame received with an error is discarded and not forwarded to the client interface. When set to 0, errored frames are forwarded to the client interface with ff_rx_err asserted. + Note : It is recommended to set this bit to 1 only when store and forward operation is enabled (RX_SECTION_FULL TBD). */ + unsigned int msmSystemRxErrorDiscard : 1; /* 1E.6004.E R/W Default = 0x0 */ + /* 1 = Enable discard of received errored frames + */ + /*! \brief 1E.6004.D R/W MSM System Control Frame Enable + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemControlFrameEnable + + Default = 0x0 + + 1 = Control frame enabled + + + Notes: + MAC control frame enable. When set to 1, the MAC control frames with any Opcode other than 0x0001 are accepted and forwarded to the client interface. When set to 0, MAC control frames with any opcode other than 0x0001 are silently discarded. */ + unsigned int msmSystemControlFrameEnable : 1; /* 1E.6004.D R/W Default = 0x0 */ + /* 1 = Control frame enabled + */ + /*! \brief 1E.6004.C R/WSC MSM System Soft Reset + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemSoftReset + + Default = 0x0 + + 1 = Soft reset + + + Notes: + Software reset. Self clearing bit. When set to 1, resets all statistic counters as well as the Tx and Rx FIFOs. It should be issued after all traffic has been stopped as a result of clearing the Rx/Tx enable bits ( See MAC Rx Enable set to 0 and See MAC Tx Enable set to 0). + Note : Can lead to an Rx interface (ff_rx_xxx) violations to the application if the reset is issued in the middle of a receive frame transfer. Then the end of packet (assertion of ff_rx_eop) is lost and the application should be prepeared to handle this exception. */ + unsigned int msmSystemSoftReset : 1; /* 1E.6004.C R/WSC Default = 0x0 */ + /* 1 = Soft reset + */ + /*! \brief 1E.6004.B R/W MSM System Tx Pad Enable + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemTxPadEnable + + Default = 0x1 + + 1 = Enable Tx padding + + + Notes: + When set to 1, enable padding of frames in the Tx direction. When set to 0, the MAC will not extend frames from the application to a minimum of 64 bytes, allowing to transmit short frames (violating the Ethernet mimimum size requirements). Must be set to 1 for normal operation. */ + unsigned int msmSystemTxPadEnable : 1; /* 1E.6004.B R/W Default = 0x1 */ + /* 1 = Enable Tx padding + */ + /*! \brief 1E.6004.A R/W MSM System Tx CRC Append + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemTxCrcAppend + + Default = 0x0 + + 1 = Append Tx CRC + + + Notes: + Permanently enable CRC append on transmit. If set to 1, the Tx will append a CRC to all transmitted frames. If set to 0, CRC append can be controlled on a per frame basis using the pin ff_tx_crc. + This configuration bit is OR'ed with the external ff_tx_crc pin to instruct the Tx to append a CRC to transmitted frames. The ff_tx_crc pin is tied to 0. */ + unsigned int msmSystemTxCrcAppend : 1; /* 1E.6004.A R/W Default = 0x0 */ + /* 1 = Append Tx CRC + */ + /*! \brief 1E.6004.9 R/W MSM System Tx Address Insert Enable + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemTxAddressInsertEnable + + Default = 0x0 + + 1 = Insert Tx MAC source address + + + Notes: + Set the source MAC address on transmit. If set to 1, the MAC overwrites the source MAC address with the MAC programmed address in all transmitted frames. When set to 0, the source MAC address is transmitted unmodified from the MAC Tx client application. */ + unsigned int msmSystemTxAddressInsertEnable : 1; /* 1E.6004.9 R/W Default = 0x0 */ + /* 1 = Insert Tx MAC source address + */ + /*! \brief 1E.6004.8 R/W MSM System Pause Ignore + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemPauseIgnore + + Default = 0x0 + + 1 = Ignore pause frames + + + Notes: + Ignore pause frame quanta. If set to 1, received pause frames are ignored by the MAC. When set to 0, the Tx is stopped for the amount of time specified in the pause quanta received within the pause frame. */ + unsigned int msmSystemPauseIgnore : 1; /* 1E.6004.8 R/W Default = 0x0 */ + /* 1 = Ignore pause frames + */ + /*! \brief 1E.6004.7 R/W MSM System Pause Forward + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemPauseForward + + Default = 0x0 + + 1 = Enable Pause forwarding + + + Notes: + Terminate or forward pause frames. If set to 1, pause frames are forwarded to the user application. In normal mode, when set to 0, pause frames are terminated and discarded within the MAC. */ + unsigned int msmSystemPauseForward : 1; /* 1E.6004.7 R/W Default = 0x0 */ + /* 1 = Enable Pause forwarding + */ + /*! \brief 1E.6004.6 R/W MSM System CRC Forward + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemCrcForward + + Default = 0x0 + + 1 = Enable CRC forwarding + + + Notes: + When set to 1, the CRC field of the received frames is forwarded with the frame to the user application. If disabled, the CRC field is stripped from the frame. + Note : If padding is enabled ( See MAC PAD Enable set to 1), this bit is ignored. */ + unsigned int msmSystemCrcForward : 1; /* 1E.6004.6 R/W Default = 0x0 */ + /* 1 = Enable CRC forwarding + */ + /*! \brief 1E.6004.5 R/W MSM System PAD Enable + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemPadEnable + + Default = 0x0 + + 1 = Enable frame padding removal on Rx + + + Notes: + When set to 1, enable frame padding removal on the Rx path. If enabled, padding is removed before the frame is transferred to the MAC client application. If disabled, no padding is removed on the Rx by the MAC. + Note : On Tx, the MAC always adds padding as required. */ + unsigned int msmSystemPadEnable : 1; /* 1E.6004.5 R/W Default = 0x0 */ + /* 1 = Enable frame padding removal on Rx + */ + /*! \brief 1E.6004.4 R/W MSM System Promiscuous Mode + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemPromiscuousMode + + Default = 0x0 + + 1 = Promiscuous mode + + + Notes: + When set to 1, all frames are received without any MAC address filtering. */ + unsigned int msmSystemPromiscuousMode : 1; /* 1E.6004.4 R/W Default = 0x0 */ + /* 1 = Promiscuous mode + */ + /*! \brief 1E.6004.3 R/W MSM System WAN Mode + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemWanMode + + Default = 0x0 + + 1 = WAN mode + 0 = LAN mode + + + Notes: + WAN mode enable. Sets WAN mode when set to 1 and LAN mode when set to 0. Note: When changing the mode, verifiy correct setting of the Tx IPG. */ + unsigned int msmSystemWanMode : 1; /* 1E.6004.3 R/W Default = 0x0 */ + /* 1 = WAN mode + 0 = LAN mode + */ + unsigned int reserved0 : 1; + /*! \brief 1E.6004.1 R/W MSM System Rx Enable + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemRxEnable + + Default = 0x0 + + 1 = Rx enable + + Notes: + MAC Tx path enable. Should be set to 1 to enable the MAC Tx path. Should be set to 0 to disable the MAC Tx path. */ + unsigned int msmSystemRxEnable : 1; /* 1E.6004.1 R/W Default = 0x0 */ + /* 1 = Rx enable */ + /*! \brief 1E.6004.0 R/W MSM System Tx Enable + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemTxEnable + + Default = 0x0 + + 1 = Tx enable + + Notes: + MAC Rx path enable. Should be set to 1 to enable the MAC Rx path. Should be set to 0 to disable the MAC Rx path. */ + unsigned int msmSystemTxEnable : 1; /* 1E.6004.0 R/W Default = 0x0 */ + /* 1 = Tx enable */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System General Control Register */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.6005.7 R/W MSM System Tx Low Power IDLE Enable + AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemTxLowPowerIdleEnable + + Default = 0x0 + + 1 = Transmit LPI enable + + + Notes: + Transmit low power IDLE enable. When set to 1, the MAC completes the transmission of the current frame and generates low power IDLE sequences (LPI) to the XGMII/SGMII. When set to 0, the MAC operates in normal mode. This bit is OR'ed with the reg_lowp_ena pin. */ + unsigned int msmSystemTxLowPowerIdleEnable : 1; /* 1E.6005.7 R/W Default = 0x0 */ + /* 1 = Transmit LPI enable + */ + unsigned int reserved1 : 1; + /*! \brief 1E.6005.5 R/W MSM System SFD Check Disable + AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemSfdCheckDisable + + Default = 0x0 + + 1 = Disable SFD check + + + Notes: + Disable check of SFD (0xD5) character at frame start. When set to 1, the frame is accepted even if the SFD byte following the preamble is not 0xD5. When set to 0, a frame is accepted only if the SFD byte is found with the value 0xD5. */ + unsigned int msmSystemSfdCheckDisable : 1; /* 1E.6005.5 R/W Default = 0x0 */ + /* 1 = Disable SFD check + */ + unsigned int reserved2 : 1; + /*! \brief 1E.6005.3 R/W MSM System Priority Flow Control Enable + AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemPriorityFlowControlEnable + + Default = 0x0 + + 1 = Enable priority flow control + 0 = Enable link flow control + + + Notes: + Enable priority flow control (PFC) mode of operation. When set to 0, the MAC uses standard link pause frames. When set to 1, the MAC will transmit and accept PFC frames. */ + unsigned int msmSystemPriorityFlowControlEnable : 1; /* 1E.6005.3 R/W Default = 0x0 */ + /* 1 = Enable priority flow control + 0 = Enable link flow control + */ + /*! \brief 1E.6005.2 R/W MSM System IDLE Column Count Extend + AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemIdleColumnCountExtend + + Default = 0x0 + + 1 = Extend IDLE column count + + Notes: + When set to 1, extends the RS layer IDLE column counter by 2x. The IEEE 802.3ae defines the fault condition to be cleared after 128 columns of IDLE have been received. If the MAC operates together with a WAN mode PCS (WIS) it may may happen (depending on PCS) that this period is too short to bridge the IDLE stuffing occurring in this mode, leading to a toggling fault indication. In this case, extending the counter helps to aoivd toggling fault indications. */ + unsigned int msmSystemIdleColumnCountExtend : 1; /* 1E.6005.2 R/W Default = 0x0 */ + /* 1 = Extend IDLE column count */ + /*! \brief 1E.6005.1 R/W MSM System Length Check Disable + AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemLengthCheckDisable + + Default = 0x0 + + 1 = Disable length check + + Notes: + Payload length check disable. When set to 0, the MAC checks the frames payload length with the frame length/type field. When set to 1, the payload length check is disabled. */ + unsigned int msmSystemLengthCheckDisable : 1; /* 1E.6005.1 R/W Default = 0x0 */ + /* 1 = Disable length check */ + /*! \brief 1E.6005.0 R/W MSM System Force Send IDLE + AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemForceSendIdle + + Default = 0x0 + + 1 = Force send idle + + Notes: + When set to 1, suppress any frame transmissions and forces IDLE n the Tx interface instead of frames. This control affects the MAC reconciliation layer (RS) which acts after all MAC datapath has processed the frame. + Note : Does not have an effect on fault handling (i.e. reception of local fault will still cause transmit of remote fault). + Must be 0 for normal operation. */ + unsigned int msmSystemForceSendIdle : 1; /* 1E.6005.0 R/W Default = 0x0 */ + /* 1 = Force send idle */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemGeneralControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System FIFO Control Register: 1E.600E */ +/* MSM System FIFO Control Register: 1E.600E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.600E.7:0 R/W MSM System Rx FIFO Full Threshold [7:0] + AQ_MsmSystemFifoControlRegister_HHD.u0.bits_0.msmSystemRxFifoFullThreshold + + Default = 0x08 + + Rx FIFO full threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmSystemRxFifoFullThreshold : 8; /* 1E.600E.7:0 R/W Default = 0x08 */ + /* Rx FIFO full threshold */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.600F.7:0 R/W MSM System Rx FIFO Empty Threshold [7:0] + AQ_MsmSystemFifoControlRegister_HHD.u1.bits_1.msmSystemRxFifoEmptyThreshold + + Default = 0x00 + + Rx FIFO empty threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmSystemRxFifoEmptyThreshold : 8; /* 1E.600F.7:0 R/W Default = 0x00 */ + /* Rx FIFO empty threshold */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of MSM System FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 10; + /*! \brief 1E.6010.5:0 R/W MSM System Tx FIFO Full Threshold [5:0] + AQ_MsmSystemFifoControlRegister_HHD.u2.bits_2.msmSystemTxFifoFullThreshold + + Default = 0x08 + + Tx FIFO full threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmSystemTxFifoFullThreshold : 6; /* 1E.6010.5:0 R/W Default = 0x08 */ + /* Tx FIFO full threshold */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of MSM System FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 10; + /*! \brief 1E.6011.5:0 R/W MSM System Tx FIFO Empty Threshold [5:0] + AQ_MsmSystemFifoControlRegister_HHD.u3.bits_3.msmSystemTxFifoEmptyThreshold + + Default = 0x00 + + Tx FIFO empty threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmSystemTxFifoEmptyThreshold : 6; /* 1E.6011.5:0 R/W Default = 0x00 */ + /* Tx FIFO empty threshold */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of MSM System FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.6012.7:0 ROS MSM System Rx FIFO Almost Full Threshold [7:0] + AQ_MsmSystemFifoControlRegister_HHD.u4.bits_4.msmSystemRxFifoAlmostFullThreshold + + Default = 0x00 + + Rx FIFO almost full threshold + + Notes: + Unused. */ + unsigned int msmSystemRxFifoAlmostFullThreshold : 8; /* 1E.6012.7:0 ROS Default = 0x00 */ + /* Rx FIFO almost full threshold */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of MSM System FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.6013.7:0 ROS MSM System Rx FIFO Almost Empty Threshold [7:0] + AQ_MsmSystemFifoControlRegister_HHD.u5.bits_5.msmSystemRxFifoAlmostEmptyThreshold + + Default = 0x00 + + Rx FIFO almost empty threshold + + Notes: + Unused. */ + unsigned int msmSystemRxFifoAlmostEmptyThreshold : 8; /* 1E.6013.7:0 ROS Default = 0x00 */ + /* Rx FIFO almost empty threshold */ + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of MSM System FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.6014.7:0 ROS MSM System Tx FIFO Almost Full Threshold [7:0] + AQ_MsmSystemFifoControlRegister_HHD.u6.bits_6.msmSystemTxFifoAlmostFullThreshold + + Default = 0x00 + + Tx FIFO almost full threshold + + Notes: + Unused. */ + unsigned int msmSystemTxFifoAlmostFullThreshold : 8; /* 1E.6014.7:0 ROS Default = 0x00 */ + /* Tx FIFO almost full threshold */ + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of MSM System FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.6015.7:0 ROS MSM System Tx FIFO Almost Empty Threshold [7:0] + AQ_MsmSystemFifoControlRegister_HHD.u7.bits_7.msmSystemTxFifoAlmostEmptyThreshold + + Default = 0x00 + + Tx FIFO almost empty threshold + + Notes: + Unused. */ + unsigned int msmSystemTxFifoAlmostEmptyThreshold : 8; /* 1E.6015.7:0 ROS Default = 0x00 */ + /* Tx FIFO almost empty threshold */ + } bits_7; + uint16_t word_7; + } u7; +} AQ_MsmSystemFifoControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System General Status Register: 1E.6020 */ +/* MSM System General Status Register: 1E.6020 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System General Status Register */ + union + { + struct + { + unsigned int reserved0 : 10; + /*! \brief 1E.6020.5 RO MSM System Tx FIFO Empty + AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemTxFifoEmpty + + + + Tx FIFO empty + + Notes: + When set to 1, indicates the Tx FIFO is empty. When set to 0, Tx FIFO is non-empty. */ + unsigned int msmSystemTxFifoEmpty : 1; /* 1E.6020.5 RO */ + /* Tx FIFO empty */ + /*! \brief 1E.6020.4 RO MSM System Rx Low Power IDLE + AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemRxLowPowerIdle + + + + Rx LPI detected + + Notes: + Receive low power IDLE (LPI). Set to 1 when LPI is currently detected on the MAC Rx interface. Set to 0, when the MAC currently operates in normal mode. */ + unsigned int msmSystemRxLowPowerIdle : 1; /* 1E.6020.4 RO */ + /* Rx LPI detected */ + /*! \brief 1E.6020.3 R/W MSM System Timestamp Available + AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemTimestampAvailable + + Default = 0x0 + + Timestamp available + + Notes: + Transmit timestamp available. Indicates that the timestamp of the last transmitted event frame (which had ff_tx_ts_frm=1) is available in the register See MAC Time Stamp Status 0 [F:0] and See MAC Time Stamp Status 1 [F:0] . To clear this bit, the bit must be written with a 1. + */ + unsigned int msmSystemTimestampAvailable : 1; /* 1E.6020.3 R/W Default = 0x0 */ + /* Timestamp available */ + /*! \brief 1E.6020.2 RO MSM System PHY Loss of Signal + AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemPhyLossOfSignal + + + + PHY loss of signal + + Notes: + PHY indicates loss of signal. This is the value of pin phy_los which is tied to 0. */ + unsigned int msmSystemPhyLossOfSignal : 1; /* 1E.6020.2 RO */ + /* PHY loss of signal */ + /*! \brief 1E.6020.1 BLH MSM System Rx Remote Fault + AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemRxRemoteFault + + + + Rx remote fault detected + + Notes: + Latch high local fault status. Set to 1, whent he MAC detects Rx local fault sequences on the Rx interface. Reset to 0 after read and after reset. */ + unsigned int msmSystemRxRemoteFault : 1; /* 1E.6020.1 BLH */ + /* Rx remote fault detected */ + /*! \brief 1E.6020.0 BLH MSM System Rx Local Fault + AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemRxLocalFault + + + + Rx local fault detected + + Notes: + Latch high local fault status. Set to 1, whent he MAC detects Rx local fault sequences on the Rx interface. Reset to 0 after read and after reset. */ + unsigned int msmSystemRxLocalFault : 1; /* 1E.6020.0 BLH */ + /* Rx local fault detected */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System General Status Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemGeneralStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx IPG Control Register: 1E.6022 */ +/* MSM System Tx IPG Control Register: 1E.6022 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx IPG Control Register */ + union + { + struct + { + unsigned int reserved0 : 10; + /*! \brief 1E.6022.5:0 R/W MSM System Tx IPG Length [5:0] + AQ_MsmSystemTxIpgControlRegister_HHD.u0.bits_0.msmSystemTxIpgLength + + Default = 0x0C + + Tx IPG length + + Notes: + Tx inter-packet gap (IPG) value. Depending on LAN or WAN mode of operation. + LAN Mode : Number of octets in steps of 4. Valid values are 8, 12, 16,..., 100. DIC is supported for any setting > 8. A default of 12 must be set to conform to IEEE802.3ae. + WAN Mode : Stretch factor. Valid values are 4 ... 15. The stretch factor is calculated as (value+1)*8. A default of 12 must be set to conform to IEEE802.3ae (i.e. 13*8=104). A larger value shrinks the IPG (increasing bandwidth). + The reset value of 12 leads to IEEE802.3ae conformant behavior in both modes. + Note : WAN mode is only available in 10G mode of operation. */ + unsigned int msmSystemTxIpgLength : 6; /* 1E.6022.5:0 R/W Default = 0x0C */ + /* Tx IPG length */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx IPG Control Register */ + union + { + struct + { + /*! \brief 1E.6023.F:0 MSM System Tx IPG Reserved + AQ_MsmSystemTxIpgControlRegister_HHD.u1.bits_1.msmSystemTxIpgReserved + + + + Value always 0, writes ignored + */ + unsigned int msmSystemTxIpgReserved : 16; /* 1E.6023.F:0 */ + /* Value always 0, writes ignored */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxIpgControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx Good Frames Counter Register: 1E.6040 */ +/* MSM System Tx Good Frames Counter Register: 1E.6040 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6040.F:0 ROS MSM System Tx Good Frames Counter 0 [F:0] + AQ_MsmSystemTxGoodFramesCounterRegister_HHD.u0.bits_0.msmSystemTxGoodFramesCounter_0 + + Default = 0x0000 + + Tx good frame counter bits 15:0 + + Notes: + Count of frames transmitted without error (Including pause frames). */ + unsigned int msmSystemTxGoodFramesCounter_0 : 16; /* 1E.6040.F:0 ROS Default = 0x0000 */ + /* Tx good frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6041.F:0 ROS MSM System Tx Good Frames Counter 1 [F:0] + AQ_MsmSystemTxGoodFramesCounterRegister_HHD.u1.bits_1.msmSystemTxGoodFramesCounter_1 + + Default = 0x0000 + + Tx good frame counter bits 31:16 + + + Notes: + Count of frames transmitted without error (Including pause frames). */ + unsigned int msmSystemTxGoodFramesCounter_1 : 16; /* 1E.6041.F:0 ROS Default = 0x0000 */ + /* Tx good frame counter bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxGoodFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Good Frames Counter Register: 1E.6044 */ +/* MSM System Rx Good Frames Counter Register: 1E.6044 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6044.F:0 ROS MSM System Rx Good Frames Counter 0 [F:0] + AQ_MsmSystemRxGoodFramesCounterRegister_HHD.u0.bits_0.msmSystemRxGoodFramesCounter_0 + + Default = 0x0000 + + Rx good frame counter bits 15:0 + + Notes: + Count of frames received without error (Including pause frames). */ + unsigned int msmSystemRxGoodFramesCounter_0 : 16; /* 1E.6044.F:0 ROS Default = 0x0000 */ + /* Rx good frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6045.F:0 ROS MSM System Rx Good Frames Counter 1 [F:0] + AQ_MsmSystemRxGoodFramesCounterRegister_HHD.u1.bits_1.msmSystemRxGoodFramesCounter_1 + + Default = 0x0000 + + Rx good frame counter bits 31:16 + + Notes: + Count of frames received without error (Including pause frames). */ + unsigned int msmSystemRxGoodFramesCounter_1 : 16; /* 1E.6045.F:0 ROS Default = 0x0000 */ + /* Rx good frame counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxGoodFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx FCS Errors Counter Register: 1E.6048 */ +/* MSM System Rx FCS Errors Counter Register: 1E.6048 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx FCS Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.6048.F:0 ROS MSM System FCS Error Counter 0 [F:0] + AQ_MsmSystemRxFcsErrorsCounterRegister_HHD.u0.bits_0.msmSystemFcsErrorCounter_0 + + Default = 0x0000 + + Frame check sequence error counter bits 15:0 + + Notes: + Count of frames for which a CRC-32 Error is detected but the frame is otherwise of correct length. */ + unsigned int msmSystemFcsErrorCounter_0 : 16; /* 1E.6048.F:0 ROS Default = 0x0000 */ + /* Frame check sequence error counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx FCS Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.6049.F:0 ROS MSM System FCS Error Counter 1 [F:0] + AQ_MsmSystemRxFcsErrorsCounterRegister_HHD.u1.bits_1.msmSystemFcsErrorCounter_1 + + Default = 0x0000 + + Frame check sequence error counter bits 31:16 + + Notes: + Count of frames for which a CRC-32 Error is detected but the frame is otherwise of correct length. */ + unsigned int msmSystemFcsErrorCounter_1 : 16; /* 1E.6049.F:0 ROS Default = 0x0000 */ + /* Frame check sequence error counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxFcsErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Alignment Errors Counter Register: 1E.604C */ +/* MSM System Rx Alignment Errors Counter Register: 1E.604C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Alignment Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.604C.F:0 ROS MSM System Alignment Error Counter 0 [F:0] + AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD.u0.bits_0.msmSystemAlignmentErrorCounter_0 + + Default = 0x0000 + + Alignment error counter bits 15:0 + + Notes: + Count of frames received with an alignment error. */ + unsigned int msmSystemAlignmentErrorCounter_0 : 16; /* 1E.604C.F:0 ROS Default = 0x0000 */ + /* Alignment error counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Alignment Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.604D.F:0 ROS MSM System Alignment Error Counter 1 [F:0] + AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD.u1.bits_1.msmSystemAlignmentErrorCounter_1 + + Default = 0x0000 + + Alignment error counter bits 31:16 + + Notes: + Count of frames received with an alignment error. */ + unsigned int msmSystemAlignmentErrorCounter_1 : 16; /* 1E.604D.F:0 ROS Default = 0x0000 */ + /* Alignment error counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx Pause Frames Counter Register: 1E.6050 */ +/* MSM System Tx Pause Frames Counter Register: 1E.6050 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6050.F:0 ROS MSM System Tx Pause Frames Counter 0 [F:0] + AQ_MsmSystemTxPauseFramesCounterRegister_HHD.u0.bits_0.msmSystemTxPauseFramesCounter_0 + + Default = 0x0000 + + Tx pause frame counter bits 15:0 + + Notes: + Valid pause frames transmitted. */ + unsigned int msmSystemTxPauseFramesCounter_0 : 16; /* 1E.6050.F:0 ROS Default = 0x0000 */ + /* Tx pause frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6051.F:0 ROS MSM System Tx Pause Frames Counter 1 [F:0] + AQ_MsmSystemTxPauseFramesCounterRegister_HHD.u1.bits_1.msmSystemTxPauseFramesCounter_1 + + Default = 0x0000 + + Tx pause frame counter bits 31:16 + + + Notes: + Valid pause frames transmitted. */ + unsigned int msmSystemTxPauseFramesCounter_1 : 16; /* 1E.6051.F:0 ROS Default = 0x0000 */ + /* Tx pause frame counter bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxPauseFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Pause Frames Counter Register: 1E.6054 */ +/* MSM System Rx Pause Frames Counter Register: 1E.6054 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6054.F:0 ROS MSM System Rx Pause Frames Counter 0 [F:0] + AQ_MsmSystemRxPauseFramesCounterRegister_HHD.u0.bits_0.msmSystemRxPauseFramesCounter_0 + + Default = 0x0000 + + Rx pause frame counter bits 15:0 + + Notes: + Valid pause frames received. */ + unsigned int msmSystemRxPauseFramesCounter_0 : 16; /* 1E.6054.F:0 ROS Default = 0x0000 */ + /* Rx pause frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6055.F:0 ROS MSM System Rx Pause Frames Counter 1 [F:0] + AQ_MsmSystemRxPauseFramesCounterRegister_HHD.u1.bits_1.msmSystemRxPauseFramesCounter_1 + + Default = 0x0000 + + Rx pause frame counter bits 31:16 + + Notes: + Valid pause frames received. */ + unsigned int msmSystemRxPauseFramesCounter_1 : 16; /* 1E.6055.F:0 ROS Default = 0x0000 */ + /* Rx pause frame counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxPauseFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Too Long Errors Counter Register: 1E.6058 */ +/* MSM System Rx Too Long Errors Counter Register: 1E.6058 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Too Long Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.6058.F:0 ROS MSM System Rx Too Long Errors Counter 0 [F:0] + AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD.u0.bits_0.msmSystemRxTooLongErrorsCounter_0 + + Default = 0x0000 + + Too-long errors counter bits 15:0 + + Notes: + Frame received exceeded the maximum length programmed with register FRM_LGTH. */ + unsigned int msmSystemRxTooLongErrorsCounter_0 : 16; /* 1E.6058.F:0 ROS Default = 0x0000 */ + /* Too-long errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Too Long Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.6059.F:0 ROS MSM System Rx Too Long Errors Counter 1 [F:0] + AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD.u1.bits_1.msmSystemRxTooLongErrorsCounter_1 + + Default = 0x0000 + + Too-long errors counter bits 31:16 + + Notes: + Frame received exceeded the maximum length programmed with register FRM_LGTH. */ + unsigned int msmSystemRxTooLongErrorsCounter_1 : 16; /* 1E.6059.F:0 ROS Default = 0x0000 */ + /* Too-long errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx In Range Length Errors Counter Register: 1E.605C */ +/* MSM System Rx In Range Length Errors Counter Register: 1E.605C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx In Range Length Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.605C.F:0 ROS MSM System Rx In Range Length Errors Counter 0 [F:0] + AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD.u0.bits_0.msmSystemRxInRangeLengthErrorsCounter_0 + + Default = 0x0000 + + In-range-length errors counter bits 15:0 + + Notes: + A count of frames with a length/type field value between 46 (VLAN: 42) and less than 0x0600, that does not match the number of payload data octets received. Should count also if length/type field is less than 46 (VLAN: 42) and the frame is longer than 64 bytes. */ + unsigned int msmSystemRxInRangeLengthErrorsCounter_0 : 16; /* 1E.605C.F:0 ROS Default = 0x0000 */ + /* In-range-length errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx In Range Length Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.605D.F:0 ROS MSM System Rx In Range Length Errors Counter 1 [F:0] + AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD.u1.bits_1.msmSystemRxInRangeLengthErrorsCounter_1 + + Default = 0x0000 + + In-range-length errors counter bits 31:16 + + Notes: + A count of frames with a length/type field value between 46 (VLAN: 42) and less than 0x0600, that does not match the number of payload data octets received. Should count also if length/type field is less than 46 (VLAN: 42) and the frame is longer than 64 bytes. */ + unsigned int msmSystemRxInRangeLengthErrorsCounter_1 : 16; /* 1E.605D.F:0 ROS Default = 0x0000 */ + /* In-range-length errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx VLAN Frames Counter Register: 1E.6060 */ +/* MSM System Tx VLAN Frames Counter Register: 1E.6060 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6060.F:0 ROS MSM System Tx VLAN Frames Counter 0 [F:0] + AQ_MsmSystemTxVlanFramesCounterRegister_HHD.u0.bits_0.msmSystemTxVlanFramesCounter_0 + + Default = 0x0000 + + Tx VLAN frames counter bits 15:0 + + Notes: + Valid VLAN tagged frames transmitted. */ + unsigned int msmSystemTxVlanFramesCounter_0 : 16; /* 1E.6060.F:0 ROS Default = 0x0000 */ + /* Tx VLAN frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6061.F:0 ROS MSM System Tx VLAN Frames Counter 1 [F:0] + AQ_MsmSystemTxVlanFramesCounterRegister_HHD.u1.bits_1.msmSystemTxVlanFramesCounter_1 + + Default = 0x0000 + + Tx VLAN frames counter bits 31:16 + + Notes: + Valid VLAN tagged frames transmitted. */ + unsigned int msmSystemTxVlanFramesCounter_1 : 16; /* 1E.6061.F:0 ROS Default = 0x0000 */ + /* Tx VLAN frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxVlanFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx VLAN Frames Counter Register: 1E.6064 */ +/* MSM System Rx VLAN Frames Counter Register: 1E.6064 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6064.F:0 ROS MSM System Rx VLAN Frames Counter 0 [F:0] + AQ_MsmSystemRxVlanFramesCounterRegister_HHD.u0.bits_0.msmSystemRxVlanFramesCounter_0 + + Default = 0x0000 + + Rx VLAN frames counter bits 15:0 + + Notes: + Valid VLAN tagged frames received. */ + unsigned int msmSystemRxVlanFramesCounter_0 : 16; /* 1E.6064.F:0 ROS Default = 0x0000 */ + /* Rx VLAN frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6065.F:0 ROS MSM System Rx VLAN Frames Counter 1 [F:0] + AQ_MsmSystemRxVlanFramesCounterRegister_HHD.u1.bits_1.msmSystemRxVlanFramesCounter_1 + + Default = 0x0000 + + Rx VLAN frames counter bits 31:16 + + Notes: + Valid VLAN tagged frames received. */ + unsigned int msmSystemRxVlanFramesCounter_1 : 16; /* 1E.6065.F:0 ROS Default = 0x0000 */ + /* Rx VLAN frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxVlanFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx Octets Counter Register: 1E.6068 */ +/* MSM System Tx Octets Counter Register: 1E.6068 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.6068.F:0 ROS MSM System Tx Octets Counter 0 [F:0] + AQ_MsmSystemTxOctetsCounterRegister_HHD.u0.bits_0.msmSystemTxOctetsCounter_0 + + Default = 0x0000 + + Tx octets counter bits 15:0 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmSystemTxOctetsCounter_0 : 16; /* 1E.6068.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.6069.F:0 ROS MSM System Tx Octets Counter 1 [F:0] + AQ_MsmSystemTxOctetsCounterRegister_HHD.u1.bits_1.msmSystemTxOctetsCounter_1 + + Default = 0x0000 + + Tx octets counter bits 31:16 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmSystemTxOctetsCounter_1 : 16; /* 1E.6069.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of MSM System Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.606A.F:0 ROS MSM System Tx Octets Counter 2 [F:0] + AQ_MsmSystemTxOctetsCounterRegister_HHD.u2.bits_2.msmSystemTxOctetsCounter_2 + + Default = 0x0000 + + Tx octets counter bits 47:32 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmSystemTxOctetsCounter_2 : 16; /* 1E.606A.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 47:32 */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of MSM System Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.606B.F:0 ROS MSM System Tx Octets Counter 3 [F:0] + AQ_MsmSystemTxOctetsCounterRegister_HHD.u3.bits_3.msmSystemTxOctetsCounter_3 + + Default = 0x0000 + + Tx octets counter bits 63:48 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmSystemTxOctetsCounter_3 : 16; /* 1E.606B.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 63:48 */ + } bits_3; + uint16_t word_3; + } u3; +} AQ_MsmSystemTxOctetsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Octets Counter Register: 1E.606C */ +/* MSM System Rx Octets Counter Register: 1E.606C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.606C.F:0 ROS MSM System Rx Octets Counter 0 [F:0] + AQ_MsmSystemRxOctetsCounterRegister_HHD.u0.bits_0.msmSystemRxOctetsCounter_0 + + Default = 0x0000 + + Rx octets counter bits 15:0 + + Notes: + All octets received except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames received. */ + unsigned int msmSystemRxOctetsCounter_0 : 16; /* 1E.606C.F:0 ROS Default = 0x0000 */ + /* Rx octets counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.606D.F:0 ROS MSM System Rx Octets Counter 1 [F:0] + AQ_MsmSystemRxOctetsCounterRegister_HHD.u1.bits_1.msmSystemRxOctetsCounter_1 + + Default = 0x0000 + + Rx octets counter bits 31:16 + + Notes: + All octets received except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames received. */ + unsigned int msmSystemRxOctetsCounter_1 : 16; /* 1E.606D.F:0 ROS Default = 0x0000 */ + /* Rx octets counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxOctetsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Unicast Frames Counter Register: 1E.6070 */ +/* MSM System Rx Unicast Frames Counter Register: 1E.6070 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6070.F:0 ROS MSM System Rx Unicast Frames Counter 0 [F:0] + AQ_MsmSystemRxUnicastFramesCounterRegister_HHD.u0.bits_0.msmSystemRxUnicastFramesCounter_0 + + Default = 0x0000 + + Rx unicast frames counter bits 15:0 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '0'. */ + unsigned int msmSystemRxUnicastFramesCounter_0 : 16; /* 1E.6070.F:0 ROS Default = 0x0000 */ + /* Rx unicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6071.F:0 ROS MSM System Rx Unicast Frames Counter 1 [F:0] + AQ_MsmSystemRxUnicastFramesCounterRegister_HHD.u1.bits_1.msmSystemRxUnicastFramesCounter_1 + + Default = 0x0000 + + Rx unicast frames counter bits 31:16 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '0'. */ + unsigned int msmSystemRxUnicastFramesCounter_1 : 16; /* 1E.6071.F:0 ROS Default = 0x0000 */ + /* Rx unicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxUnicastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Multicast Frames Counter Register: 1E.6074 */ +/* MSM System Rx Multicast Frames Counter Register: 1E.6074 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6074.F:0 ROS MSM System Rx Multicast Frames Counter 0 [F:0] + AQ_MsmSystemRxMulticastFramesCounterRegister_HHD.u0.bits_0.msmSystemRxMulticastFramesCounter_0 + + Default = 0x0000 + + Rx multicast frames counter bits 15:0 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '1' but not the broadcast address (all bits set '1' ). Pause frames are not counted. */ + unsigned int msmSystemRxMulticastFramesCounter_0 : 16; /* 1E.6074.F:0 ROS Default = 0x0000 */ + /* Rx multicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6075.F:0 ROS MSM System Rx Multicast Frames Counter 1 [F:0] + AQ_MsmSystemRxMulticastFramesCounterRegister_HHD.u1.bits_1.msmSystemRxMulticastFramesCounter_1 + + Default = 0x0000 + + Rx multicast frames counter bits 31:16 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '1' but not the broadcast address (all bits set '1' ). Pause frames are not counted. */ + unsigned int msmSystemRxMulticastFramesCounter_1 : 16; /* 1E.6075.F:0 ROS Default = 0x0000 */ + /* Rx multicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxMulticastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Broadcast Frames Counter Register: 1E.6078 */ +/* MSM System Rx Broadcast Frames Counter Register: 1E.6078 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6078.F:0 ROS MSM System Rx Broadcast Frames Counter 0 [F:0] + AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD.u0.bits_0.msmSystemRxBroadcastFramesCounter_0 + + Default = 0x0000 + + Rx broadcast frames counter bits 15:0 + + Notes: + Incremented with each valid frame received on the receive FIFO interface (FIFO) and all bits of the destination address were set '1'. */ + unsigned int msmSystemRxBroadcastFramesCounter_0 : 16; /* 1E.6078.F:0 ROS Default = 0x0000 */ + /* Rx broadcast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6079.F:0 ROS MSM System Rx Broadcast Frames Counter 1 [F:0] + AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD.u1.bits_1.msmSystemRxBroadcastFramesCounter_1 + + Default = 0x0000 + + Rx broadcast frames counter bits 31:16 + + Notes: + Incremented with each valid frame received on the receive FIFO interface (FIFO) and all bits of the destination address were set '1'. */ + unsigned int msmSystemRxBroadcastFramesCounter_1 : 16; /* 1E.6079.F:0 ROS Default = 0x0000 */ + /* Rx broadcast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx Errors Counter Register: 1E.607C */ +/* MSM System Tx Errors Counter Register: 1E.607C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.607C.F:0 ROS MSM System Tx Errors Counter 0 [F:0] + AQ_MsmSystemTxErrorsCounterRegister_HHD.u0.bits_0.msmSystemTxErrorsCounter_0 + + Default = 0x0000 + + Rx errors counter bits 15:0 + + Notes: + Number of frames transmitted with error: + - FIFO Overflow Errors + - FIFO Underflow Errors */ + unsigned int msmSystemTxErrorsCounter_0 : 16; /* 1E.607C.F:0 ROS Default = 0x0000 */ + /* Rx errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.607D.F:0 ROS MSM System Tx Errors Counter 1 [F:0] + AQ_MsmSystemTxErrorsCounterRegister_HHD.u1.bits_1.msmSystemTxErrorsCounter_1 + + Default = 0x0000 + + Tx errors counter bits 31:16 + + Notes: + Number of frames transmitted with error: + - FIFO Overflow Errors + - FIFO Underflow Errors */ + unsigned int msmSystemTxErrorsCounter_1 : 16; /* 1E.607D.F:0 ROS Default = 0x0000 */ + /* Tx errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx Unicast Frames Counter Register: 1E.6084 */ +/* MSM System Tx Unicast Frames Counter Register: 1E.6084 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6084.F:0 ROS MSM System Tx Unicast Frames Counter 0 [F:0] + AQ_MsmSystemTxUnicastFramesCounterRegister_HHD.u0.bits_0.msmSystemTxUnicastFramesCounter_0 + + Default = 0x0000 + + Tx unicast frames counter bits 15:0 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '0'. */ + unsigned int msmSystemTxUnicastFramesCounter_0 : 16; /* 1E.6084.F:0 ROS Default = 0x0000 */ + /* Tx unicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6085.F:0 ROS MSM System Tx Unicast Frames Counter 1 [F:0] + AQ_MsmSystemTxUnicastFramesCounterRegister_HHD.u1.bits_1.msmSystemTxUnicastFramesCounter_1 + + Default = 0x0000 + + Tx unicast frames counter bits 31:16 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '0'. */ + unsigned int msmSystemTxUnicastFramesCounter_1 : 16; /* 1E.6085.F:0 ROS Default = 0x0000 */ + /* Tx unicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxUnicastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx Multicast Frames Counter Register: 1E.6088 */ +/* MSM System Tx Multicast Frames Counter Register: 1E.6088 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6088.F:0 ROS MSM System Tx Multicast Frames Counter 0 [F:0] + AQ_MsmSystemTxMulticastFramesCounterRegister_HHD.u0.bits_0.msmSystemTxMulticastFramesCounter_0 + + Default = 0x0000 + + Tx multicast frames counter bits 15:0 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '1' but not the broadcast address (all bits '1'). */ + unsigned int msmSystemTxMulticastFramesCounter_0 : 16; /* 1E.6088.F:0 ROS Default = 0x0000 */ + /* Tx multicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6089.F:0 ROS MSM System Tx Multicast Frames Counter 1 [F:0] + AQ_MsmSystemTxMulticastFramesCounterRegister_HHD.u1.bits_1.msmSystemTxMulticastFramesCounter_1 + + Default = 0x0000 + + Tx multicast frames counter bits 31:16 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '1' but not the broadcast address (all bits '1'). */ + unsigned int msmSystemTxMulticastFramesCounter_1 : 16; /* 1E.6089.F:0 ROS Default = 0x0000 */ + /* Tx multicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxMulticastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx Broadcast Frames Counter Register: 1E.608C */ +/* MSM System Tx Broadcast Frames Counter Register: 1E.608C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.608C.F:0 ROS MSM System Tx Broadcast Frames Counter 0 [F:0] + AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD.u0.bits_0.msmSystemTxBroadcastFramesCounter_0 + + Default = 0x0000 + + Tx broadcast frames counter bits 15:0 + + Notes: + Incremented with each frame written to the FIFO interface and all bits of the destination address set to '1'. */ + unsigned int msmSystemTxBroadcastFramesCounter_0 : 16; /* 1E.608C.F:0 ROS Default = 0x0000 */ + /* Tx broadcast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.608D.F:0 ROS MSM System Tx Broadcast Frames Counter 1 [F:0] + AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD.u1.bits_1.msmSystemTxBroadcastFramesCounter_1 + + Default = 0x0000 + + Tx broadcast frames counter bits 31:16 + + Notes: + Incremented with each frame written to the FIFO interface and all bits of the destination address set to '1'. */ + unsigned int msmSystemTxBroadcastFramesCounter_1 : 16; /* 1E.608D.F:0 ROS Default = 0x0000 */ + /* Tx broadcast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Errors Counter Register: 1E.60C8 */ +/* MSM System Rx Errors Counter Register: 1E.60C8 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.60C8.F:0 ROS MSM System Rx Errors Counter 0 [F:0] + AQ_MsmSystemRxErrorsCounterRegister_HHD.u0.bits_0.msmSystemRxErrorsCounter_0 + + Default = 0x0000 + + Rx errors counter bits 15:0 + + Notes: + Number of frames received with error: + - FIFO Overflow Errors + - CRC Errors + - Payload Length Errors + - Jabber and Oversized Errors + - Alignment Errors + - The dedicated Error Code (0xfe, not a code error) was received */ + unsigned int msmSystemRxErrorsCounter_0 : 16; /* 1E.60C8.F:0 ROS Default = 0x0000 */ + /* Rx errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.60C9.F:0 ROS MSM System Rx Errors Counter 1 [F:0] + AQ_MsmSystemRxErrorsCounterRegister_HHD.u1.bits_1.msmSystemRxErrorsCounter_1 + + Default = 0x0000 + + Rx errors counter bits 31:16 + + Notes: + Number of frames received with error: + - FIFO Overflow Errors + - CRC Errors + - Payload Length Errors + - Jabber and Oversized Errors + - Alignment Errors + - The dedicated Error Code (0xfe, not a code error) was received */ + unsigned int msmSystemRxErrorsCounter_1 : 16; /* 1E.60C9.F:0 ROS Default = 0x0000 */ + /* Rx errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress VLAN TPID 0 Register: 1E.8006 */ +/* MSS Ingress VLAN TPID 0 Register: 1E.8006 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress VLAN TPID 0 Register */ + union + { + struct + { + /*! \brief 1E.8006.F:0 R/W MSS Ingress VLAN STag [F:0] + AQ_MssIngressVlanTpid_0Register_HHD.u0.bits_0.mssIngressVlanStag + + Default = 0x0000 + + STag TPID + + + Notes: + Service Tag Protocol Identifier (TPID) values to identify a VLAN tag. The " See SEC Egress VLAN CP Tag Parse STag " bit must be set to 1 for the incoming packet's TPID to be parsed. */ + unsigned int mssIngressVlanStag : 16; /* 1E.8006.F:0 R/W Default = 0x0000 */ + /* STag TPID + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress VLAN TPID 0 Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressVlanTpid_0Register_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress VLAN TPID 1 Register: 1E.8008 */ +/* MSS Ingress VLAN TPID 1 Register: 1E.8008 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress VLAN TPID 1 Register */ + union + { + struct + { + /*! \brief 1E.8008.F:0 R/W MSS Ingress VLAN QTag [F:0] + AQ_MssIngressVlanTpid_1Register_HHD.u0.bits_0.mssIngressVlanQtag + + Default = 0x0000 + + QTag TPID + + + Notes: + Customer Tag Protocol Identifier (TPID) values to identify a VLAN tag. The " See SEC Egress VLAN CP Tag Parse QTag " bit must be set to 1 for the incoming packet's TPID to be parsed. */ + unsigned int mssIngressVlanQtag : 16; /* 1E.8008.F:0 R/W Default = 0x0000 */ + /* QTag TPID + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress VLAN TPID 1 Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressVlanTpid_1Register_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress VLAN Control Register: 1E.800A */ +/* MSS Ingress VLAN Control Register: 1E.800A */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress VLAN Control Register */ + union + { + struct + { + /*! \brief 1E.800A.F:0 R/W MSS Ingress VLAN UP Map Table LSW [F:0] + AQ_MssIngressVlanControlRegister_HHD.u0.bits_0.mssIngressVlanUpMapTableLSW + + Default = 0x0000 + + Map table bits 15:0 + + + Notes: + If there is a customer TPID Tag match and no service TPID Tag match or the service TPID Tag match is disabled, the outer TAG's PCP is used to index into this map table to generate the packets user priority. + 2:0 : UP value for customer Tag PCP 0x0 + 5:3: UP value for customer Tag PCP 0x0 + 8:6 : UP value for customer Tag PCP 0x0 + 11:9 : UP value for customer Tag PCP 0x0 + 14:12 : UP value for customer Tag PCP 0x0 + 17:15 : UP value for customer Tag PCP 0x0 */ + unsigned int mssIngressVlanUpMapTableLSW : 16; /* 1E.800A.F:0 R/W Default = 0x0000 */ + /* Map table bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress VLAN Control Register */ + union + { + struct + { + /*! \brief 1E.800B.F R/W MSS Ingress VLAN QTag Parse Enable + AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanQtagParseEnable + + Default = 0x0 + + 1 = Enable VLAN QTag parsing + + + Notes: + Enable controlled port VLAN customer Tag parsing. When this bit is set to 1, the incoming packet's outer TPID will be compared with the configured " See MSS Ingress VLAN QTag [F:0] " for matching. If the " See SEC Egress VLAN CP Tag Parse QinQ " bit is set to1, this will also be used to compare the incoming packet's inner TPID. */ + unsigned int mssIngressVlanQtagParseEnable : 1; /* 1E.800B.F R/W Default = 0x0 */ + /* 1 = Enable VLAN QTag parsing + */ + /*! \brief 1E.800B.E R/W MSS Ingress VLAN STag Parse Enable + AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanStagParseEnable + + Default = 0x0 + + 1 = Enable VLAN STag parsing + + + Notes: + Enable controlled port VLAN service Tag parsing. When this bit is set to 1, the incoming packets outer TPID will be compared with the configured " See MSS Ingress VLAN Stag [F:0] " for matching. If the " See SEC Egress VLAN CP Tag Parse QinQ " bit is set to1, this will also be used to compare the incoming packet's inner TPID. */ + unsigned int mssIngressVlanStagParseEnable : 1; /* 1E.800B.E R/W Default = 0x0 */ + /* 1 = Enable VLAN STag parsing + */ + /*! \brief 1E.800B.D R/W MSS Ingress VLAN QinQ Parse Enable + AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanQinqParseEnable + + Default = 0x0 + + VLAN CP Tag Parse QinQ + + + Notes: + Enable controlled port VLAN QinQ Tag parsing. When this bit is set to 1 both the outer and inner VLAN Tags will be parsed. */ + unsigned int mssIngressVlanQinqParseEnable : 1; /* 1E.800B.D R/W Default = 0x0 */ + /* VLAN CP Tag Parse QinQ + */ + /*! \brief 1E.800B.C R/W MSS Ingress VLAN QTag UP Parse Enable + AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanQtagUpParseEnable + + Default = 0x0 + + VLAN CP Tag QTag UP enable + + + Notes: + Enable controlled port customer VLAN customer Tag user priority field parsing. */ + unsigned int mssIngressVlanQtagUpParseEnable : 1; /* 1E.800B.C R/W Default = 0x0 */ + /* VLAN CP Tag QTag UP enable + */ + /*! \brief 1E.800B.B R/W MSS Ingress VLAN STag UP Parse Enable + AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanStagUpParseEnable + + Default = 0x0 + + VLAN CP Tag STag UP enable + + + Notes: + Enable controlled port service VLAN service Tag user priority field parsing. */ + unsigned int mssIngressVlanStagUpParseEnable : 1; /* 1E.800B.B R/W Default = 0x0 */ + /* VLAN CP Tag STag UP enable + */ + /*! \brief 1E.800B.A:8 R/W MSS Ingress VLAN UP Default [2:0] + AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanUpDefault + + Default = 0x0 + + UP default + + + Notes: + User priority default */ + unsigned int mssIngressVlanUpDefault : 3; /* 1E.800B.A:8 R/W Default = 0x0 */ + /* UP default + */ + /*! \brief 1E.800B.7:0 R/W MSS Ingress VLAN UP Map Table MSW [17:10] + AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanUpMapTableMSW + + Default = 0x00 + + UP Map table bits 23:16 + + + Notes: + If there is a customer TPID Tag match and no service TPID Tag match or the service TPID Tag match is disabled, the outer TAG's PCP is used to index into this map table to generate the packets user priority. + 2:0 : UP value for customer Tag PCP 0x0 + 5:3: UP value for customer Tag PCP 0x0 + 8:6 : UP value for customer Tag PCP 0x0 + 11:9 : UP value for customer Tag PCP 0x0 + 14:12 : UP value for customer Tag PCP 0x0 + 17:15 : UP value for customer Tag PCP 0x0 + 20:18 : UP value for customer Tag PCP 0x0 + 23:21 : UP value for customer Tag PCP 0x0 */ + unsigned int mssIngressVlanUpMapTableMSW : 8; /* 1E.800B.7:0 R/W Default = 0x00 */ + /* UP Map table bits 23:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressVlanControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress MTU Size Control Register: 1E.800C */ +/* MSS Ingress MTU Size Control Register: 1E.800C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress MTU Size Control Register */ + union + { + struct + { + /*! \brief 1E.800C.F:0 R/W MSS Ingress Controlled Packet MTU Size [F:0] + AQ_MssIngressMtuSizeControlRegister_HHD.u0.bits_0.mssIngressControlledPacketMtuSize + + Default = 0x05DC + + Maximum transmission unit for controlled packet + + + Notes: + Maximum transmission unit of controlled packet */ + unsigned int mssIngressControlledPacketMtuSize : 16; /* 1E.800C.F:0 R/W Default = 0x05DC */ + /* Maximum transmission unit for controlled packet + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress MTU Size Control Register */ + union + { + struct + { + /*! \brief 1E.800D.F:0 R/W MSS Ingress Uncontrolled Packet MTU Size [F:0] + AQ_MssIngressMtuSizeControlRegister_HHD.u1.bits_1.mssIngressUncontrolledPacketMtuSize + + Default = 0x05DC + + Maximum transmission unit for uncontrolled packet + + + Notes: + Maximum transmission unit of uncontrolled packet */ + unsigned int mssIngressUncontrolledPacketMtuSize : 16; /* 1E.800D.F:0 R/W Default = 0x05DC */ + /* Maximum transmission unit for uncontrolled packet + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressMtuSizeControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress Control Register: 1E.800E */ +/* MSS Ingress Control Register: 1E.800E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress Control Register */ + union + { + struct + { + unsigned int reserved0 : 2; + /*! \brief 1E.800E.D R/W MSS Ingress ICV LSB 8 Bytes Enable + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressIcvLsb_8BytesEnable + + Default = 0x0 + + 1 = Use LSB + 0 = Use MSB + + + + Notes: + This bit selects MSB or LSB 8 bytes selection in the case where the ICV is 8 bytes. + 0 = MSB is used. */ + unsigned int mssIngressIcvLsb_8BytesEnable : 1; /* 1E.800E.D R/W Default = 0x0 */ + /* 1 = Use LSB + 0 = Use MSB + + */ + /*! \brief 1E.800E.C:B R/W MSS Ingress Global Validate Frames [1:0] + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressGlobalValidateFrames + + Default = 0x0 + + Default validate frames configuration + + + Notes: + If the SC is invalid or if an IGPRC miss packet condition occurs, this default will be used for the validate frames configuration instead of the validate frame entry in the Ingress SC Table (IGSCT). */ + unsigned int mssIngressGlobalValidateFrames : 2; /* 1E.800E.C:B R/W Default = 0x0 */ + /* Default validate frames configuration + */ + /*! \brief 1E.800E.A R/W MSS Ingress Remove SECTag + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressRemoveSectag + + Default = 0x0 + + 1 = Enable removal of SECTag + + + Notes: + If this bit is set and either of the following two conditions occurs, the SECTag will be removed. + Controlled packet and either the SA or SC is invalid. + IGPRC miss. */ + unsigned int mssIngressRemoveSectag : 1; /* 1E.800E.A R/W Default = 0x0 */ + /* 1 = Enable removal of SECTag + */ + /*! \brief 1E.800E.9 R/W MSS Ingress High Priority + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressHighPriority + + Default = 0x0 + + 1 = MIB counter clear on read enable + + + Notes: + If this bit is set to 1, read is given high priority and the MIB count value becomes 0 after read. */ + unsigned int mssIngressHighPriority : 1; /* 1E.800E.9 R/W Default = 0x0 */ + /* 1 = MIB counter clear on read enable + */ + /*! \brief 1E.800E.8 R/W MSS Ingress Clear Count + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressClearCount + + Default = 0x0 + + 1 = Clear all MIB counters + + + Notes: + If this bit is set to 1, all MIB counters will be cleared. */ + unsigned int mssIngressClearCount : 1; /* 1E.800E.8 R/W Default = 0x0 */ + /* 1 = Clear all MIB counters + */ + /*! \brief 1E.800E.7 R/W MSS Ingress Clear Global Time + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressClearGlobalTime + + Default = 0x0 + + 1 = Clear global time + + + Notes: + Clear global time */ + unsigned int mssIngressClearGlobalTime : 1; /* 1E.800E.7 R/W Default = 0x0 */ + /* 1 = Clear global time + */ + /*! \brief 1E.800E.6 R/W MSS Ingress Check ICV + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressCheckIcv + + Default = 0x0 + + Unused + + + Notes: + Unused */ + unsigned int mssIngressCheckIcv : 1; /* 1E.800E.6 R/W Default = 0x0 */ + /* Unused + */ + /*! \brief 1E.800E.5 R/W MSS Ingress Drop IGPRC Miss + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressDropIgprcMiss + + Default = 0x0 + + 1 = Drop IGPRC miss packets + + + Notes: + Decides whether Ingress Pre-Security Classification (IGPRC) LUT miss packets are to be dropped */ + unsigned int mssIngressDropIgprcMiss : 1; /* 1E.800E.5 R/W Default = 0x0 */ + /* 1 = Drop IGPRC miss packets + */ + /*! \brief 1E.800E.4 R/W MSS Ingress Drop Kay Packet + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressDropKayPacket + + Default = 0x0 + + 1 = Drop KaY packets + + + Notes: + Decides whether KaY packets have to be dropped */ + unsigned int mssIngressDropKayPacket : 1; /* 1E.800E.4 R/W Default = 0x0 */ + /* 1 = Drop KaY packets + */ + /*! \brief 1E.800E.3 R/W MSS Ingress Mask Short Length Error + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressMaskShortLengthError + + Default = 0x0 + + Unused + + + Notes: + Unused */ + unsigned int mssIngressMaskShortLengthError : 1; /* 1E.800E.3 R/W Default = 0x0 */ + /* Unused + */ + /*! \brief 1E.800E.2 R/W MSS Ingress Create SCI + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressCreateSci + + Default = 0x0 + + 0 = SCI from IGPRC LUT + + + Notes: + If the SCI is not in the packet and this bit is set to 0, the SCI will be taken from the IGPRC LUT. */ + unsigned int mssIngressCreateSci : 1; /* 1E.800E.2 R/W Default = 0x0 */ + /* 0 = SCI from IGPRC LUT + */ + /*! \brief 1E.800E.1 R/W MSS Ingress Operation Point To Point + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressOperationPointToPoint + + Default = 0x0 + + 1 = Enable the SCI for authorization default + + + Notes: + The default SCI for authorization is configured in See MSS Ingress SCI Default [F:0] See MSS Ingress SCI Default [1F:10] , See MSS Ingress SCI Default [2F:20] , and See MSS Ingress SCI Default [3F:30] . */ + unsigned int mssIngressOperationPointToPoint : 1; /* 1E.800E.1 R/W Default = 0x0 */ + /* 1 = Enable the SCI for authorization default + */ + /*! \brief 1E.800E.0 R/W MSS Ingress Soft Reset + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressSoftReset + + Default = 0x0 + + 1 = Soft reset + + + Notes: + S/W reset */ + unsigned int mssIngressSoftReset : 1; /* 1E.800E.0 R/W Default = 0x0 */ + /* 1 = Soft reset + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress Control Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress SA Control Register: 1E.8010 */ +/* MSS Ingress SA Control Register: 1E.8010 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress SA Control Register */ + union + { + struct + { + /*! \brief 1E.8010.F:0 R/W MSS Ingress SA Threshold LSW [F:0] + AQ_MssIngressSaControlRegister_HHD.u0.bits_0.mssIngressSaThresholdLSW + + Default = 0x0000 + + SA threshold bits 15:0 + + + Notes: + Ingress PN threshold to generate SA threshold interrupt. */ + unsigned int mssIngressSaThresholdLSW : 16; /* 1E.8010.F:0 R/W Default = 0x0000 */ + /* SA threshold bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress SA Control Register */ + union + { + struct + { + /*! \brief 1E.8011.F:0 R/W MSS Ingress SA Threshold MSW [1F:10] + AQ_MssIngressSaControlRegister_HHD.u1.bits_1.mssIngressSaThresholdMSW + + Default = 0x0000 + + SA threshold bits 31:16 + + + Notes: + Ingress PN threshold to generate SA threshold interrupt. */ + unsigned int mssIngressSaThresholdMSW : 16; /* 1E.8011.F:0 R/W Default = 0x0000 */ + /* SA threshold bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressSaControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress Interrupt Status Register: 1E.802E */ +/* MSS Ingress Interrupt Status Register: 1E.802E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress Interrupt Status Register */ + union + { + struct + { + unsigned int reserved0 : 7; + /*! \brief 1E.802E.8 COW MSS Ingress IGPOC Miss Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressIgpocMissInterrupt + + Default = 0x0 + + 1 = Interrupt + + */ + unsigned int mssIngressIgpocMissInterrupt : 1; /* 1E.802E.8 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.7 COW MSS Ingress TCI E/C Error Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressTciE_cErrorInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This error occurs when the TCI E bit is 1 and the TCI C bit is 0. The packet is not dropped, uncontrolled, or untagged. */ + unsigned int mssIngressTciE_cErrorInterrupt : 1; /* 1E.802E.7 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.6 COW MSS Ingress ECC Error Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressEccErrorInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. */ + unsigned int mssIngressEccErrorInterrupt : 1; /* 1E.802E.6 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.5 COW MSS Ingress MIB Saturation Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressMibSaturationInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when the MIB counters reaches all ones saturation. */ + unsigned int mssIngressMibSaturationInterrupt : 1; /* 1E.802E.5 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.4 COW MSS Ingress Replay Error Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressReplayErrorInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. */ + unsigned int mssIngressReplayErrorInterrupt : 1; /* 1E.802E.4 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.3 COW MSS Ingress ICV Error Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressIcvErrorInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. */ + unsigned int mssIngressIcvErrorInterrupt : 1; /* 1E.802E.3 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.2 COW MSS Ingress SA Threshold Expired Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressSaThresholdExpiredInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when the SA PN reaches the See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . */ + unsigned int mssIngressSaThresholdExpiredInterrupt : 1; /* 1E.802E.2 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.1 COW MSS Ingress SA Expired Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressSaExpiredInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when the SA PN reaches all ones saturation. */ + unsigned int mssIngressSaExpiredInterrupt : 1; /* 1E.802E.1 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.0 COW MSS Master Ingress Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssMasterIngressInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when any one of the above interrupt and the corresponding interrupt enable are both set. The interrupt enable for this bit must also be set for this bit to be set. */ + unsigned int mssMasterIngressInterrupt : 1; /* 1E.802E.0 COW Default = 0x0 */ + /* 1 = Interrupt + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress Interrupt Status Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressInterruptStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress Interrupt Mask Register: 1E.8030 */ +/* MSS Ingress Interrupt Mask Register: 1E.8030 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress Interrupt Mask Register */ + union + { + struct + { + unsigned int reserved0 : 7; + /*! \brief 1E.8030.8 R/W MSS Ingress IGPOC Miss Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressIgpocMissInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressIgpocMissInterruptEnable : 1; /* 1E.8030.8 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.7 R/W MSS Ingress TCI E/C Error Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressTciE_cErrorInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressTciE_cErrorInterruptEnable : 1; /* 1E.8030.7 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.6 R/W MSS Ingress ECC Error Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressEccErrorInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressEccErrorInterruptEnable : 1; /* 1E.8030.6 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.5 R/W MSS Ingress MIB Saturation Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressMibSaturationInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressMibSaturationInterruptEnable : 1; /* 1E.8030.5 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.4 R/W MSS Ingress Replay Error Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressReplayErrorInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressReplayErrorInterruptEnable : 1; /* 1E.8030.4 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.3 R/W MSS Ingress ICV Error Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressIcvErrorInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressIcvErrorInterruptEnable : 1; /* 1E.8030.3 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.2 R/W MSS Ingress SA Threshold Expired Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressSaThresholdExpiredInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressSaThresholdExpiredInterruptEnable : 1; /* 1E.8030.2 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.1 R/W MSS Ingress SA Expired Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressSaExpiredInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressSaExpiredInterruptEnable : 1; /* 1E.8030.1 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.0 R/W MSS Ingress Master Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressMasterInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressMasterInterruptEnable : 1; /* 1E.8030.0 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress Interrupt Mask Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressInterruptMaskRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress SA ICV Error Status Register: 1E.8032 */ +/* MSS Ingress SA ICV Error Status Register: 1E.8032 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress SA ICV Error Status Register */ + union + { + struct + { + /*! \brief 1E.8032.F:0 COW MSS Ingress SA ICV Error LSW [F:0] + AQ_MssIngressSaIcvErrorStatusRegister_HHD.u0.bits_0.mssIngressSaIcvErrorLSW + + Default = 0x0000 + + SA ICV error bits 15:0 + + + Notes: + When set, these bits identify the SA that has an ICV error. Write these bits to 1 to clear. */ + unsigned int mssIngressSaIcvErrorLSW : 16; /* 1E.8032.F:0 COW Default = 0x0000 */ + /* SA ICV error bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress SA ICV Error Status Register */ + union + { + struct + { + /*! \brief 1E.8033.F:0 COW MSS Ingress SA ICV Error MSW [1F:10] + AQ_MssIngressSaIcvErrorStatusRegister_HHD.u1.bits_1.mssIngressSaIcvErrorMSW + + Default = 0x0000 + + SA ICV error bits 31:16 + + + Notes: + When set, these bits identify the SA that has an ICV error. Write these bits to 1 to clear. */ + unsigned int mssIngressSaIcvErrorMSW : 16; /* 1E.8033.F:0 COW Default = 0x0000 */ + /* SA ICV error bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressSaIcvErrorStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress SA Replay Error Status Register: 1E.8034 */ +/* MSS Ingress SA Replay Error Status Register: 1E.8034 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress SA Replay Error Status Register */ + union + { + struct + { + /*! \brief 1E.8034.F:0 COW MSS Ingress SA Replay Error LSW [F:0] + AQ_MssIngressSaReplayErrorStatusRegister_HHD.u0.bits_0.mssIngressSaReplayErrorLSW + + Default = 0x0000 + + SA replay error bits 15:0 + + + Notes: + When set, these bits identify the SA that has a replay error. Write these bits to 1 to clear. */ + unsigned int mssIngressSaReplayErrorLSW : 16; /* 1E.8034.F:0 COW Default = 0x0000 */ + /* SA replay error bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress SA Replay Error Status Register */ + union + { + struct + { + /*! \brief 1E.8035.F:0 COW MSS Ingress SA Replay Error MSW [1F:10] + AQ_MssIngressSaReplayErrorStatusRegister_HHD.u1.bits_1.mssIngressSaReplayErrorMSW + + Default = 0x0000 + + SA replay error bits 31:16 + + + Notes: + When set, these bits identify the SA that has a replay error. Write these bits to 1 to clear. */ + unsigned int mssIngressSaReplayErrorMSW : 16; /* 1E.8035.F:0 COW Default = 0x0000 */ + /* SA replay error bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressSaReplayErrorStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress SA Expired Status Register: 1E.8036 */ +/* MSS Ingress SA Expired Status Register: 1E.8036 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress SA Expired Status Register */ + union + { + struct + { + /*! \brief 1E.8036.F:0 ROS MSS Ingress SA Expired LSW [F:0] + AQ_MssIngressSaExpiredStatusRegister_HHD.u0.bits_0.mssIngressSaExpiredLSW + + Default = 0x0000 + + SA expired bits 15:0 + + + Notes: + When set, these bits identify the SA that has expired when the SA PN reaches all-ones saturation. Write these bits to 1 to clear. */ + unsigned int mssIngressSaExpiredLSW : 16; /* 1E.8036.F:0 ROS Default = 0x0000 */ + /* SA expired bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress SA Expired Status Register */ + union + { + struct + { + /*! \brief 1E.8037.F:0 ROS MSS Ingress SA Expired MSW [1F:10] + AQ_MssIngressSaExpiredStatusRegister_HHD.u1.bits_1.mssIngressSaExpiredMSW + + Default = 0x0000 + + SA expired bits 31:16 + + + Notes: + When set, these bits identify the SA that has expired when the SA PN reaches all-ones saturation. Write these bits to 1 to clear. */ + unsigned int mssIngressSaExpiredMSW : 16; /* 1E.8037.F:0 ROS Default = 0x0000 */ + /* SA expired bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressSaExpiredStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress SA Threshold Expired Status Register: 1E.8038 */ +/* MSS Ingress SA Threshold Expired Status Register: 1E.8038 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress SA Threshold Expired Status Register */ + union + { + struct + { + /*! \brief 1E.8038.F:0 ROS MSS Ingress SA Threshold Expired LSW [F:0] + AQ_MssIngressSaThresholdExpiredStatusRegister_HHD.u0.bits_0.mssIngressSaThresholdExpiredLSW + + Default = 0x0000 + + SA threshold expired bits 15:0 + + + Notes: + When set, these bits identify the SA that has expired when the SA PN has reached the configured threshold See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . Write these bits to 1 to clear. */ + unsigned int mssIngressSaThresholdExpiredLSW : 16; /* 1E.8038.F:0 ROS Default = 0x0000 */ + /* SA threshold expired bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress SA Threshold Expired Status Register */ + union + { + struct + { + /*! \brief 1E.8039.F:0 ROS MSS Ingress SA Threshold Expired MSW [1F:10] + AQ_MssIngressSaThresholdExpiredStatusRegister_HHD.u1.bits_1.mssIngressSaThresholdExpiredMSW + + Default = 0x0000 + + SA threshold expired bits 31:16 + + + Notes: + When set, these bits identify the SA that has expired when the SA PN has reached the configured threshold See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . Write these bits to 1 to clear. */ + unsigned int mssIngressSaThresholdExpiredMSW : 16; /* 1E.8039.F:0 ROS Default = 0x0000 */ + /* SA threshold expired bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressSaThresholdExpiredStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress ECC Interrupt Status Register: 1E.803A */ +/* MSS Ingress ECC Interrupt Status Register: 1E.803A */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress ECC Interrupt Status Register */ + union + { + struct + { + /*! \brief 1E.803A.F:0 R/W MSS Ingress SA ECC Error Interrupt LSW [F:0] + AQ_MssIngressEccInterruptStatusRegister_HHD.u0.bits_0.mssIngressSaEccErrorInterruptLSW + + Default = 0x0000 + + SA ECC error interrupt bits 15:0 + + + Notes: + When set to 1, indicates that an ECC error occured for the SA. */ + unsigned int mssIngressSaEccErrorInterruptLSW : 16; /* 1E.803A.F:0 R/W Default = 0x0000 */ + /* SA ECC error interrupt bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress ECC Interrupt Status Register */ + union + { + struct + { + /*! \brief 1E.803B.F:0 R/W MSS Ingress SA ECC Error Interrupt MSW [1F:10] + AQ_MssIngressEccInterruptStatusRegister_HHD.u1.bits_1.mssIngressSaEccErrorInterruptMSW + + Default = 0x0000 + + SA ECC error interrupt bits 31:16 + + + Notes: + When set to 1, indicates that an ECC error occured for the SA. */ + unsigned int mssIngressSaEccErrorInterruptMSW : 16; /* 1E.803B.F:0 R/W Default = 0x0000 */ + /* SA ECC error interrupt bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressEccInterruptStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress LUT Address Control Register: 1E.8080 */ +/* MSS Ingress LUT Address Control Register: 1E.8080 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress LUT Address Control Register */ + union + { + struct + { + /*! \brief 1E.8080.F:C R/W MSS Ingress LUT Select [3:0] + AQ_MssIngressLutAddressControlRegister_HHD.u0.bits_0.mssIngressLutSelect + + Default = 0x0 + + LUT select + + + Notes: + 0x0 : Ingress Pre-Security MAC Control FIlter (IGPRCTLF) LUT + 0x1 : Ingress Pre-Security Classification LUT (IGPRC) + 0x2 : Ingress Packet Format (IGPFMT) SAKey LUT + 0x3 : Ingress Packet Format (IGPFMT) SC/SA LUT + 0x4 : Ingress Post-Security Classification LUT (IGPOC) + 0x5 : Ingress Post-Security MAC Control Filter (IGPOCTLF) LUT + 0x6 : Ingress MIB (IGMIB) */ + unsigned int mssIngressLutSelect : 4; /* 1E.8080.F:C R/W Default = 0x0 */ + /* LUT select + */ + unsigned int reserved0 : 3; + /*! \brief 1E.8080.8:0 R/W MSS Ingress LUT Address [8:0] + AQ_MssIngressLutAddressControlRegister_HHD.u0.bits_0.mssIngressLutAddress + + Default = 0x000 + + LUT address + + */ + unsigned int mssIngressLutAddress : 9; /* 1E.8080.8:0 R/W Default = 0x000 */ + /* LUT address + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_MssIngressLutAddressControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress LUT Control Register: 1E.8081 */ +/* MSS Ingress LUT Control Register: 1E.8081 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress LUT Control Register */ + union + { + struct + { + /*! \brief 1E.8081.F R/W MSS Ingress LUT Write + AQ_MssIngressLutControlRegister_HHD.u0.bits_0.mssIngressLutWrite + + Default = 0x0 + + 1 = LUT write + + + Notes: + Setting this bit to 1, will write the LUT. This bit will automatically clear to 0. */ + unsigned int mssIngressLutWrite : 1; /* 1E.8081.F R/W Default = 0x0 */ + /* 1 = LUT write + */ + /*! \brief 1E.8081.E R/W MSS Ingress LUT Read + AQ_MssIngressLutControlRegister_HHD.u0.bits_0.mssIngressLutRead + + Default = 0x0 + + 1 = LUT read + + + Notes: + Setting this bit to 1, will read the LUT. This bit will automatically clear to 0. */ + unsigned int mssIngressLutRead : 1; /* 1E.8081.E R/W Default = 0x0 */ + /* 1 = LUT read + */ + unsigned int reserved0 : 14; + } bits_0; + uint16_t word_0; + } u0; +} AQ_MssIngressLutControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress LUT Data Control Register: 1E.80A0 */ +/* MSS Ingress LUT Data Control Register: 1E.80A0 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A0.F:0 R/W MSS Ingress LUT Data 0 [F:0] + AQ_MssIngressLutDataControlRegister_HHD.u0.bits_0.mssIngressLutData_0 + + Default = 0x0000 + + LUT data bits 15:0 + + */ + unsigned int mssIngressLutData_0 : 16; /* 1E.80A0.F:0 R/W Default = 0x0000 */ + /* LUT data bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A1.F:0 R/W MSS Ingress LUT Data 1 [1F:10] + AQ_MssIngressLutDataControlRegister_HHD.u1.bits_1.mssIngressLutData_1 + + Default = 0x0000 + + LUT data bits 31:16 + + */ + unsigned int mssIngressLutData_1 : 16; /* 1E.80A1.F:0 R/W Default = 0x0000 */ + /* LUT data bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A2.F:0 R/W MSS Ingress LUT Data 2 [2F:20] + AQ_MssIngressLutDataControlRegister_HHD.u2.bits_2.mssIngressLutData_2 + + Default = 0x0000 + + LUT data bits 47:32 + + */ + unsigned int mssIngressLutData_2 : 16; /* 1E.80A2.F:0 R/W Default = 0x0000 */ + /* LUT data bits 47:32 + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A3.F:0 R/W MSS Ingress LUT Data 3 [3F:30] + AQ_MssIngressLutDataControlRegister_HHD.u3.bits_3.mssIngressLutData_3 + + Default = 0x0000 + + LUT data bits 63:48 + + */ + unsigned int mssIngressLutData_3 : 16; /* 1E.80A3.F:0 R/W Default = 0x0000 */ + /* LUT data bits 63:48 + */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A4.F:0 R/W MSS Ingress LUT Data 4 [4F:40] + AQ_MssIngressLutDataControlRegister_HHD.u4.bits_4.mssIngressLutData_4 + + Default = 0x0000 + + LUT data bits 79:64 + + */ + unsigned int mssIngressLutData_4 : 16; /* 1E.80A4.F:0 R/W Default = 0x0000 */ + /* LUT data bits 79:64 + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A5.F:0 R/W MSS Ingress LUT Data 5 [5F:50] + AQ_MssIngressLutDataControlRegister_HHD.u5.bits_5.mssIngressLutData_5 + + Default = 0x0000 + + LUT data bits 95:80 + + */ + unsigned int mssIngressLutData_5 : 16; /* 1E.80A5.F:0 R/W Default = 0x0000 */ + /* LUT data bits 95:80 + */ + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A6.F:0 R/W MSS Ingress LUT Data 6 [6F:60] + AQ_MssIngressLutDataControlRegister_HHD.u6.bits_6.mssIngressLutData_6 + + Default = 0x0000 + + LUT data bits 111:96 + + */ + unsigned int mssIngressLutData_6 : 16; /* 1E.80A6.F:0 R/W Default = 0x0000 */ + /* LUT data bits 111:96 + */ + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A7.F:0 R/W MSS Ingress LUT Data 7 [7F:70] + AQ_MssIngressLutDataControlRegister_HHD.u7.bits_7.mssIngressLutData_7 + + Default = 0x0000 + + LUT data bits 127:112 + + */ + unsigned int mssIngressLutData_7 : 16; /* 1E.80A7.F:0 R/W Default = 0x0000 */ + /* LUT data bits 127:112 + */ + } bits_7; + uint16_t word_7; + } u7; + /*! \brief Union for bit and word level access of word 8 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A8.F:0 R/W MSS Ingress LUT Data 8 [8F:80] + AQ_MssIngressLutDataControlRegister_HHD.u8.bits_8.mssIngressLutData_8 + + Default = 0x0000 + + LUT data bits 143:128 + + */ + unsigned int mssIngressLutData_8 : 16; /* 1E.80A8.F:0 R/W Default = 0x0000 */ + /* LUT data bits 143:128 + */ + } bits_8; + uint16_t word_8; + } u8; + /*! \brief Union for bit and word level access of word 9 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A9.F:0 R/W MSS Ingress LUT Data 9 [9F:90] + AQ_MssIngressLutDataControlRegister_HHD.u9.bits_9.mssIngressLutData_9 + + Default = 0x0000 + + LUT data bits 159:144 + + */ + unsigned int mssIngressLutData_9 : 16; /* 1E.80A9.F:0 R/W Default = 0x0000 */ + /* LUT data bits 159:144 + */ + } bits_9; + uint16_t word_9; + } u9; + /*! \brief Union for bit and word level access of word 10 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80AA.F:0 R/W MSS Ingress LUT Data 10 [AF:A0] + AQ_MssIngressLutDataControlRegister_HHD.u10.bits_10.mssIngressLutData_10 + + Default = 0x0000 + + LUT data bits 175:160 + + */ + unsigned int mssIngressLutData_10 : 16; /* 1E.80AA.F:0 R/W Default = 0x0000 */ + /* LUT data bits 175:160 + */ + } bits_10; + uint16_t word_10; + } u10; + /*! \brief Union for bit and word level access of word 11 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80AB.F:0 R/W MSS Ingress LUT Data 11 [BF:B0] + AQ_MssIngressLutDataControlRegister_HHD.u11.bits_11.mssIngressLutData_11 + + Default = 0x0000 + + LUT data bits 191:176 + + */ + unsigned int mssIngressLutData_11 : 16; /* 1E.80AB.F:0 R/W Default = 0x0000 */ + /* LUT data bits 191:176 + */ + } bits_11; + uint16_t word_11; + } u11; + /*! \brief Union for bit and word level access of word 12 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80AC.F:0 R/W MSS Ingress LUT Data 12 [CF:C0] + AQ_MssIngressLutDataControlRegister_HHD.u12.bits_12.mssIngressLutData_12 + + Default = 0x0000 + + LUT data bits 207:192 + + */ + unsigned int mssIngressLutData_12 : 16; /* 1E.80AC.F:0 R/W Default = 0x0000 */ + /* LUT data bits 207:192 + */ + } bits_12; + uint16_t word_12; + } u12; + /*! \brief Union for bit and word level access of word 13 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80AD.F:0 R/W MSS Ingress LUT Data 13 [DF:D0] + AQ_MssIngressLutDataControlRegister_HHD.u13.bits_13.mssIngressLutData_13 + + Default = 0x0000 + + LUT data bits 223:208 + + */ + unsigned int mssIngressLutData_13 : 16; /* 1E.80AD.F:0 R/W Default = 0x0000 */ + /* LUT data bits 223:208 + */ + } bits_13; + uint16_t word_13; + } u13; + /*! \brief Union for bit and word level access of word 14 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80AE.F:0 R/W MSS Ingress LUT Data 14 [EF:E0] + AQ_MssIngressLutDataControlRegister_HHD.u14.bits_14.mssIngressLutData_14 + + Default = 0x0000 + + LUT data bits 239:224 + + */ + unsigned int mssIngressLutData_14 : 16; /* 1E.80AE.F:0 R/W Default = 0x0000 */ + /* LUT data bits 239:224 + */ + } bits_14; + uint16_t word_14; + } u14; + /*! \brief Union for bit and word level access of word 15 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80AF.F:0 R/W MSS Ingress LUT Data 15 [FF:F0] + AQ_MssIngressLutDataControlRegister_HHD.u15.bits_15.mssIngressLutData_15 + + Default = 0x0000 + + LUT data bits 255:240 + + */ + unsigned int mssIngressLutData_15 : 16; /* 1E.80AF.F:0 R/W Default = 0x0000 */ + /* LUT data bits 255:240 + */ + } bits_15; + uint16_t word_15; + } u15; + /*! \brief Union for bit and word level access of word 16 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B0.F:0 R/W MSS Ingress LUT Data 16 [10F:100] + AQ_MssIngressLutDataControlRegister_HHD.u16.bits_16.mssIngressLutData_16 + + Default = 0x0000 + + LUT data bits 271:256 + + */ + unsigned int mssIngressLutData_16 : 16; /* 1E.80B0.F:0 R/W Default = 0x0000 */ + /* LUT data bits 271:256 + */ + } bits_16; + uint16_t word_16; + } u16; + /*! \brief Union for bit and word level access of word 17 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B1.F:0 R/W MSS Ingress LUT Data 17 [11F:110] + AQ_MssIngressLutDataControlRegister_HHD.u17.bits_17.mssIngressLutData_17 + + Default = 0x0000 + + LUT data bits 287:272 + + */ + unsigned int mssIngressLutData_17 : 16; /* 1E.80B1.F:0 R/W Default = 0x0000 */ + /* LUT data bits 287:272 + */ + } bits_17; + uint16_t word_17; + } u17; + /*! \brief Union for bit and word level access of word 18 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B2.F:0 R/W MSS Ingress LUT Data 18 [12F:120] + AQ_MssIngressLutDataControlRegister_HHD.u18.bits_18.mssIngressLutData_18 + + Default = 0x0000 + + LUT data bits 303:288 + + */ + unsigned int mssIngressLutData_18 : 16; /* 1E.80B2.F:0 R/W Default = 0x0000 */ + /* LUT data bits 303:288 + */ + } bits_18; + uint16_t word_18; + } u18; + /*! \brief Union for bit and word level access of word 19 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B3.F:0 R/W MSS Ingress LUT Data 19 [13F:130] + AQ_MssIngressLutDataControlRegister_HHD.u19.bits_19.mssIngressLutData_19 + + Default = 0x0000 + + LUT data bits 319:304 + + */ + unsigned int mssIngressLutData_19 : 16; /* 1E.80B3.F:0 R/W Default = 0x0000 */ + /* LUT data bits 319:304 + */ + } bits_19; + uint16_t word_19; + } u19; + /*! \brief Union for bit and word level access of word 20 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B4.F:0 R/W MSS Ingress LUT Data 20 [14F:140] + AQ_MssIngressLutDataControlRegister_HHD.u20.bits_20.mssIngressLutData_20 + + Default = 0x0000 + + LUT data bits 335:320 + + */ + unsigned int mssIngressLutData_20 : 16; /* 1E.80B4.F:0 R/W Default = 0x0000 */ + /* LUT data bits 335:320 + */ + } bits_20; + uint16_t word_20; + } u20; + /*! \brief Union for bit and word level access of word 21 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B5.F:0 R/W MSS Ingress LUT Data 21 [15F:150] + AQ_MssIngressLutDataControlRegister_HHD.u21.bits_21.mssIngressLutData_21 + + Default = 0x0000 + + LUT data bits 351:336 + + */ + unsigned int mssIngressLutData_21 : 16; /* 1E.80B5.F:0 R/W Default = 0x0000 */ + /* LUT data bits 351:336 + */ + } bits_21; + uint16_t word_21; + } u21; + /*! \brief Union for bit and word level access of word 22 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B6.F:0 R/W MSS Ingress LUT Data 22 [16F:160] + AQ_MssIngressLutDataControlRegister_HHD.u22.bits_22.mssIngressLutData_22 + + Default = 0x0000 + + LUT data bits 367:352 + + */ + unsigned int mssIngressLutData_22 : 16; /* 1E.80B6.F:0 R/W Default = 0x0000 */ + /* LUT data bits 367:352 + */ + } bits_22; + uint16_t word_22; + } u22; + /*! \brief Union for bit and word level access of word 23 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B7.F:0 R/W MSS Ingress LUT Data 23 [17F:170] + AQ_MssIngressLutDataControlRegister_HHD.u23.bits_23.mssIngressLutData_23 + + Default = 0x0000 + + LUT data bits 383:368 + + */ + unsigned int mssIngressLutData_23 : 16; /* 1E.80B7.F:0 R/W Default = 0x0000 */ + /* LUT data bits 383:368 + */ + } bits_23; + uint16_t word_23; + } u23; +} AQ_MssIngressLutDataControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line General Control Register: 1E.9004 */ +/* MSM Line General Control Register: 1E.9004 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line General Control Register */ + union + { + struct + { + /*! \brief 1E.9004.F R/W MSM Line PHY Tx Enable + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLinePhyTxEnable + + Default = 0x0 + + 1 = Enable PHY Tx + + + Notes: + Directly controls the phy_tx_ena pin. */ + unsigned int msmLinePhyTxEnable : 1; /* 1E.9004.F R/W Default = 0x0 */ + /* 1 = Enable PHY Tx + */ + /*! \brief 1E.9004.E R/W MSM Line Rx Error Discard + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineRxErrorDiscard + + Default = 0x0 + + 1 = Enable discard of received errored frames + + + Notes: + Rx errored frame discard enable. When set to 1, any frame received with an error is discarded and not forwarded to the client interface. When set to 0, errored frames are forwarded to the client interface with ff_rx_err asserted. + Note : It is recommended to set this bit to 1 only when store and forward operation is enabled (RX_SECTION_FULL TBD). */ + unsigned int msmLineRxErrorDiscard : 1; /* 1E.9004.E R/W Default = 0x0 */ + /* 1 = Enable discard of received errored frames + */ + /*! \brief 1E.9004.D R/W MSM Line Control Frame Enable + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineControlFrameEnable + + Default = 0x0 + + 1 = Control frame enabled + + + Notes: + MAC control frame enable. When set to 1, the MAC control frames with any Opcode other than 0x0001 are accepted and forwarded to the client interface. When set to 0, MAC control frames with any opcode other than 0x0001 are silently discarded. */ + unsigned int msmLineControlFrameEnable : 1; /* 1E.9004.D R/W Default = 0x0 */ + /* 1 = Control frame enabled + */ + /*! \brief 1E.9004.C R/WSC MSM Line Soft Reset + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineSoftReset + + Default = 0x0 + + 1 = Soft reset + + + Notes: + Software reset. Self clearing bit. When set to 1, resets all statistic counters as well as the Tx and Rx FIFOs. It should be issued after all traffic has been stopped as a result of clearing the Rx/Tx enable bits ( See MAC Rx Enable set to 0 and See MAC Tx Enable set to 0). + Note : Can lead to an Rx interface (ff_rx_xxx) violations to the application if the reset is issued in the middle of a receive frame transfer. Then the end of packet (assertion of ff_rx_eop) is lost and the application should be prepeared to handle this exception. */ + unsigned int msmLineSoftReset : 1; /* 1E.9004.C R/WSC Default = 0x0 */ + /* 1 = Soft reset + */ + /*! \brief 1E.9004.B R/W MSM Line Tx Pad Enable + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineTxPadEnable + + Default = 0x1 + + 1 = Enable Tx padding + + + Notes: + When set to 1, enable padding of frames in the Tx direction. When set to 0, the MAC will not extend frames from the application to a minimum of 64 bytes, allowing to transmit short frames (violating the Ethernet mimimum size requirements). Must be set to 1 for normal operation. */ + unsigned int msmLineTxPadEnable : 1; /* 1E.9004.B R/W Default = 0x1 */ + /* 1 = Enable Tx padding + */ + /*! \brief 1E.9004.A R/W MSM Line Tx CRC Append + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineTxCrcAppend + + Default = 0x0 + + 1 = Append Tx CRC + + + Notes: + Permanently enable CRC append on transmit. If set to 1, the Tx will append a CRC to all transmitted frames. If set to 0, CRC append can be controlled on a per frame basis using the pin ff_tx_crc. + This configuration bit is OR'ed with the external ff_tx_crc pin to instruct the Tx to append a CRC to transmitted frames. The ff_tx_crc pin is tied to 0. */ + unsigned int msmLineTxCrcAppend : 1; /* 1E.9004.A R/W Default = 0x0 */ + /* 1 = Append Tx CRC + */ + /*! \brief 1E.9004.9 R/W MSM Line Tx Address Insert Enable + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineTxAddressInsertEnable + + Default = 0x0 + + 1 = Insert Tx MAC source address + + + Notes: + Set the source MAC address on transmit. If set to 1, the MAC overwrites the source MAC address with the MAC programmed address in all transmitted frames. When set to 0, the source MAC address is transmitted unmodified from the MAC Tx client application. */ + unsigned int msmLineTxAddressInsertEnable : 1; /* 1E.9004.9 R/W Default = 0x0 */ + /* 1 = Insert Tx MAC source address + */ + /*! \brief 1E.9004.8 R/W MSM Line Pause Ignore + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLinePauseIgnore + + Default = 0x0 + + 1 = Ignore pause frames + + + Notes: + Ignore pause frame quanta. If set to 1, received pause frames are ignored by the MAC. When set to 0, the Tx is stopped for the amount of time specified in the pause quanta received within the pause frame. */ + unsigned int msmLinePauseIgnore : 1; /* 1E.9004.8 R/W Default = 0x0 */ + /* 1 = Ignore pause frames + */ + /*! \brief 1E.9004.7 R/W MSM Line Pause Forward + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLinePauseForward + + Default = 0x0 + + 1 = Enable Pause forwarding + + + Notes: + Terminate or forward pause frames. If set to 1, pause frames are forwarded to the user application. In normal mode, when set to 0, pause frames are terminated and discarded within the MAC. */ + unsigned int msmLinePauseForward : 1; /* 1E.9004.7 R/W Default = 0x0 */ + /* 1 = Enable Pause forwarding + */ + /*! \brief 1E.9004.6 R/W MSM Line CRC Forward + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineCrcForward + + Default = 0x0 + + 1 = Enable CRC forwarding + + + Notes: + When set to 1, the CRC field of the received frames is forwarded with the frame to the user application. If disabled, the CRC field is stripped from the frame. + Note : If padding is enabled ( See MAC PAD Enable set to 1), this bit is ignored. */ + unsigned int msmLineCrcForward : 1; /* 1E.9004.6 R/W Default = 0x0 */ + /* 1 = Enable CRC forwarding + */ + /*! \brief 1E.9004.5 R/W MSM Line PAD Enable + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLinePadEnable + + Default = 0x0 + + 1 = Enable frame padding removal on Rx + + + Notes: + When set to 1, enable frame padding removal on the Rx path. If enabled, padding is removed before the frame is transferred to the MAC client application. If disabled, no padding is removed on the Rx by the MAC. + Note : On Tx, the MAC always adds padding as required. */ + unsigned int msmLinePadEnable : 1; /* 1E.9004.5 R/W Default = 0x0 */ + /* 1 = Enable frame padding removal on Rx + */ + /*! \brief 1E.9004.4 R/W MSM Line Promiscuous Mode + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLinePromiscuousMode + + Default = 0x0 + + 1 = Promiscuous mode + + + Notes: + When set to 1, all frames are received without any MAC address filtering. */ + unsigned int msmLinePromiscuousMode : 1; /* 1E.9004.4 R/W Default = 0x0 */ + /* 1 = Promiscuous mode + */ + /*! \brief 1E.9004.3 R/W MSM Line WAN Mode + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineWanMode + + Default = 0x0 + + 1 = WAN mode + 0 = LAN mode + + + Notes: + WAN mode enable. Sets WAN mode when set to 1 and LAN mode when set to 0. Note: When changing the mode, verifiy correct setting of the Tx IPG. */ + unsigned int msmLineWanMode : 1; /* 1E.9004.3 R/W Default = 0x0 */ + /* 1 = WAN mode + 0 = LAN mode + */ + unsigned int reserved0 : 1; + /*! \brief 1E.9004.1 R/W MSM Line Rx Enable + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineRxEnable + + Default = 0x0 + + 1 = Rx enable + + Notes: + MAC Tx path enable. Should be set to 1 to enable the MAC Tx path. Should be set to 0 to disable the MAC Tx path. */ + unsigned int msmLineRxEnable : 1; /* 1E.9004.1 R/W Default = 0x0 */ + /* 1 = Rx enable */ + /*! \brief 1E.9004.0 R/W MSM Line Tx Enable + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineTxEnable + + Default = 0x0 + + 1 = Tx enable + + Notes: + MAC Rx path enable. Should be set to 1 to enable the MAC Rx path. Should be set to 0 to disable the MAC Rx path. */ + unsigned int msmLineTxEnable : 1; /* 1E.9004.0 R/W Default = 0x0 */ + /* 1 = Tx enable */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line General Control Register */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.9005.7 R/W MSM Line Tx Low Power IDLE Enable + AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLineTxLowPowerIdleEnable + + Default = 0x0 + + 1 = Transmit LPI enable + + + Notes: + Transmit low power IDLE enable. When set to 1, the MAC completes the transmission of the current frame and generates low power IDLE sequences (LPI) to the XGMII/SGMII. When set to 0, the MAC operates in normal mode. This bit is OR'ed with the reg_lowp_ena pin. */ + unsigned int msmLineTxLowPowerIdleEnable : 1; /* 1E.9005.7 R/W Default = 0x0 */ + /* 1 = Transmit LPI enable + */ + unsigned int reserved1 : 1; + /*! \brief 1E.9005.5 R/W MSM Line SFD Check Disable + AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLineSfdCheckDisable + + Default = 0x0 + + 1 = Disable SFD check + + + Notes: + Disable check of SFD (0xD5) character at frame start. When set to 1, the frame is accepted even if the SFD byte following the preamble is not 0xD5. When set to 0, a frame is accepted only if the SFD byte is found with the value 0xD5. */ + unsigned int msmLineSfdCheckDisable : 1; /* 1E.9005.5 R/W Default = 0x0 */ + /* 1 = Disable SFD check + */ + unsigned int reserved2 : 1; + /*! \brief 1E.9005.3 R/W MSM Line Priority Flow Control Enable + AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLinePriorityFlowControlEnable + + Default = 0x0 + + 1 = Enable priority flow control + 0 = Enable link flow control + + + Notes: + Enable priority flow control (PFC) mode of operation. When set to 0, the MAC uses standard link pause frames. When set to 1, the MAC will transmit and accept PFC frames. */ + unsigned int msmLinePriorityFlowControlEnable : 1; /* 1E.9005.3 R/W Default = 0x0 */ + /* 1 = Enable priority flow control + 0 = Enable link flow control + */ + /*! \brief 1E.9005.2 R/W MSM Line IDLE Column Count Extend + AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLineIdleColumnCountExtend + + Default = 0x0 + + 1 = Extend IDLE column count + + Notes: + When set to 1, extends the RS layer IDLE column counter by 2x. The IEEE 802.3ae defines the fault condition to be cleared after 128 columns of IDLE have been received. If the MAC operates together with a WAN mode PCS (WIS) it may may happen (depending on PCS) that this period is too short to bridge the IDLE stuffing occurring in this mode, leading to a toggling fault indication. In this case, extending the counter helps to aoivd toggling fault indications. */ + unsigned int msmLineIdleColumnCountExtend : 1; /* 1E.9005.2 R/W Default = 0x0 */ + /* 1 = Extend IDLE column count */ + /*! \brief 1E.9005.1 R/W MSM Line Length Check Disable + AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLineLengthCheckDisable + + Default = 0x0 + + 1 = Disable length check + + Notes: + Payload length check disable. When set to 0, the MAC checks the frames payload length with the frame length/type field. When set to 1, the payload length check is disabled. */ + unsigned int msmLineLengthCheckDisable : 1; /* 1E.9005.1 R/W Default = 0x0 */ + /* 1 = Disable length check */ + /*! \brief 1E.9005.0 R/W MSM Line Force Send IDLE + AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLineForceSendIdle + + Default = 0x0 + + 1 = Force send idle + + Notes: + When set to 1, suppress any frame transmissions and forces IDLE n the Tx interface instead of frames. This control affects the MAC reconciliation layer (RS) which acts after all MAC datapath has processed the frame. + Note : Does not have an effect on fault handling (i.e. reception of local fault will still cause transmit of remote fault). + Must be 0 for normal operation. */ + unsigned int msmLineForceSendIdle : 1; /* 1E.9005.0 R/W Default = 0x0 */ + /* 1 = Force send idle */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineGeneralControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line FIFO Control Register: 1E.900E */ +/* MSM Line FIFO Control Register: 1E.900E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.900E.7:0 R/W MSM Line Rx FIFO Full Threshold [7:0] + AQ_MsmLineFifoControlRegister_HHD.u0.bits_0.msmLineRxFifoFullThreshold + + Default = 0x08 + + Rx FIFO full threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmLineRxFifoFullThreshold : 8; /* 1E.900E.7:0 R/W Default = 0x08 */ + /* Rx FIFO full threshold */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.900F.7:0 R/W MSM Line Rx FIFO Empty Threshold [7:0] + AQ_MsmLineFifoControlRegister_HHD.u1.bits_1.msmLineRxFifoEmptyThreshold + + Default = 0x00 + + Rx FIFO empty threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmLineRxFifoEmptyThreshold : 8; /* 1E.900F.7:0 R/W Default = 0x00 */ + /* Rx FIFO empty threshold */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of MSM Line FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 10; + /*! \brief 1E.9010.5:0 R/W MSM Line Tx FIFO Full Threshold [5:0] + AQ_MsmLineFifoControlRegister_HHD.u2.bits_2.msmLineTxFifoFullThreshold + + Default = 0x08 + + Tx FIFO full threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmLineTxFifoFullThreshold : 6; /* 1E.9010.5:0 R/W Default = 0x08 */ + /* Tx FIFO full threshold */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of MSM Line FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 10; + /*! \brief 1E.9011.5:0 R/W MSM Line Tx FIFO Empty Threshold [5:0] + AQ_MsmLineFifoControlRegister_HHD.u3.bits_3.msmLineTxFifoEmptyThreshold + + Default = 0x00 + + Tx FIFO empty threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmLineTxFifoEmptyThreshold : 6; /* 1E.9011.5:0 R/W Default = 0x00 */ + /* Tx FIFO empty threshold */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of MSM Line FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.9012.7:0 ROS MSM Line Rx FIFO Almost Full Threshold [7:0] + AQ_MsmLineFifoControlRegister_HHD.u4.bits_4.msmLineRxFifoAlmostFullThreshold + + Default = 0x00 + + Rx FIFO almost full threshold + + Notes: + Unused. */ + unsigned int msmLineRxFifoAlmostFullThreshold : 8; /* 1E.9012.7:0 ROS Default = 0x00 */ + /* Rx FIFO almost full threshold */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of MSM Line FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.9013.7:0 ROS MSM Line Rx FIFO Almost Empty Threshold [7:0] + AQ_MsmLineFifoControlRegister_HHD.u5.bits_5.msmLineRxFifoAlmostEmptyThreshold + + Default = 0x00 + + Rx FIFO almost empty threshold + + Notes: + Unused. */ + unsigned int msmLineRxFifoAlmostEmptyThreshold : 8; /* 1E.9013.7:0 ROS Default = 0x00 */ + /* Rx FIFO almost empty threshold */ + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of MSM Line FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.9014.7:0 ROS MSM Line Tx FIFO Almost Full Threshold [7:0] + AQ_MsmLineFifoControlRegister_HHD.u6.bits_6.msmLineTxFifoAlmostFullThreshold + + Default = 0x00 + + Tx FIFO almost full threshold + + Notes: + Unused. */ + unsigned int msmLineTxFifoAlmostFullThreshold : 8; /* 1E.9014.7:0 ROS Default = 0x00 */ + /* Tx FIFO almost full threshold */ + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of MSM Line FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.9015.7:0 ROS MSM Line Tx FIFO Almost Empty Threshold [7:0] + AQ_MsmLineFifoControlRegister_HHD.u7.bits_7.msmLineTxFifoAlmostEmptyThreshold + + Default = 0x00 + + Tx FIFO almost empty threshold + + Notes: + Unused. */ + unsigned int msmLineTxFifoAlmostEmptyThreshold : 8; /* 1E.9015.7:0 ROS Default = 0x00 */ + /* Tx FIFO almost empty threshold */ + } bits_7; + uint16_t word_7; + } u7; +} AQ_MsmLineFifoControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line General Status Register: 1E.9020 */ +/* MSM Line General Status Register: 1E.9020 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line General Status Register */ + union + { + struct + { + unsigned int reserved0 : 10; + /*! \brief 1E.9020.5 RO MSM Line Tx FIFO Empty + AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLineTxFifoEmpty + + + + Tx FIFO empty + + Notes: + When set to 1, indicates the Tx FIFO is empty. When set to 0, Tx FIFO is non-empty. */ + unsigned int msmLineTxFifoEmpty : 1; /* 1E.9020.5 RO */ + /* Tx FIFO empty */ + /*! \brief 1E.9020.4 RO MSM Line Rx Low Power IDLE + AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLineRxLowPowerIdle + + + + Rx LPI detected + + Notes: + Receive low power IDLE (LPI). Set to 1 when LPI is currently detected on the MAC Rx interface. Set to 0, when the MAC currently operates in normal mode. */ + unsigned int msmLineRxLowPowerIdle : 1; /* 1E.9020.4 RO */ + /* Rx LPI detected */ + /*! \brief 1E.9020.3 R/W MSM Line Timestamp Available + AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLineTimestampAvailable + + Default = 0x0 + + Timestamp available + + Notes: + Transmit timestamp available. Indicates that the timestamp of the last transmitted event frame (which had ff_tx_ts_frm=1) is available in the register See MAC Time Stamp Status 0 [F:0] and See MAC Time Stamp Status 1 [F:0] . To clear this bit, the bit must be written with a 1. + */ + unsigned int msmLineTimestampAvailable : 1; /* 1E.9020.3 R/W Default = 0x0 */ + /* Timestamp available */ + /*! \brief 1E.9020.2 RO MSM Line PHY Loss of Signal + AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLinePhyLossOfSignal + + + + PHY loss of signal + + Notes: + PHY indicates loss of signal. This is the value of pin phy_los which is tied to 0. */ + unsigned int msmLinePhyLossOfSignal : 1; /* 1E.9020.2 RO */ + /* PHY loss of signal */ + /*! \brief 1E.9020.1 BLH MSM Line Rx Remote Fault + AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLineRxRemoteFault + + + + Rx remote fault detected + + Notes: + Latch high local fault status. Set to 1, whent he MAC detects Rx local fault sequences on the Rx interface. Reset to 0 after read and after reset. */ + unsigned int msmLineRxRemoteFault : 1; /* 1E.9020.1 BLH */ + /* Rx remote fault detected */ + /*! \brief 1E.9020.0 BLH MSM Line Rx Local Fault + AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLineRxLocalFault + + + + Rx local fault detected + + Notes: + Latch high local fault status. Set to 1, whent he MAC detects Rx local fault sequences on the Rx interface. Reset to 0 after read and after reset. */ + unsigned int msmLineRxLocalFault : 1; /* 1E.9020.0 BLH */ + /* Rx local fault detected */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line General Status Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineGeneralStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx IPG Control Register: 1E.9022 */ +/* MSM Line Tx IPG Control Register: 1E.9022 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx IPG Control Register */ + union + { + struct + { + unsigned int reserved0 : 10; + /*! \brief 1E.9022.5:0 R/W MSM Line Tx IPG Length [5:0] + AQ_MsmLineTxIpgControlRegister_HHD.u0.bits_0.msmLineTxIpgLength + + Default = 0x0C + + Tx IPG length + + Notes: + Tx inter-packet gap (IPG) value. Depending on LAN or WAN mode of operation. + LAN Mode : Number of octets in steps of 4. Valid values are 8, 12, 16,..., 100. DIC is supported for any setting > 8. A default of 12 must be set to conform to IEEE802.3ae. + WAN Mode : Stretch factor. Valid values are 4 ... 15. The stretch factor is calculated as (value+1)*8. A default of 12 must be set to conform to IEEE802.3ae (i.e. 13*8=104). A larger value shrinks the IPG (increasing bandwidth). + The reset value of 12 leads to IEEE802.3ae conformant behavior in both modes. + Note : WAN mode is only available in 10G mode of operation. */ + unsigned int msmLineTxIpgLength : 6; /* 1E.9022.5:0 R/W Default = 0x0C */ + /* Tx IPG length */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx IPG Control Register */ + union + { + struct + { + /*! \brief 1E.9023.F:0 MSM Line Tx IPG Reserved + AQ_MsmLineTxIpgControlRegister_HHD.u1.bits_1.msmLineTxIpgReserved + + + + Value always 0, writes ignored + */ + unsigned int msmLineTxIpgReserved : 16; /* 1E.9023.F:0 */ + /* Value always 0, writes ignored */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxIpgControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx Good Frames Counter Register: 1E.9040 */ +/* MSM Line Tx Good Frames Counter Register: 1E.9040 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9040.F:0 ROS MSM Line Tx Good Frames Counter 0 [F:0] + AQ_MsmLineTxGoodFramesCounterRegister_HHD.u0.bits_0.msmLineTxGoodFramesCounter_0 + + Default = 0x0000 + + Tx good frame counter bits 15:0 + + Notes: + Count of frames transmitted without error (Including pause frames). */ + unsigned int msmLineTxGoodFramesCounter_0 : 16; /* 1E.9040.F:0 ROS Default = 0x0000 */ + /* Tx good frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9041.F:0 ROS MSM Line Tx Good Frames Counter 1 [F:0] + AQ_MsmLineTxGoodFramesCounterRegister_HHD.u1.bits_1.msmLineTxGoodFramesCounter_1 + + Default = 0x0000 + + Tx good frame counter bits 31:16 + + + Notes: + Count of frames transmitted without error (Including pause frames). */ + unsigned int msmLineTxGoodFramesCounter_1 : 16; /* 1E.9041.F:0 ROS Default = 0x0000 */ + /* Tx good frame counter bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxGoodFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Good Frames Counter Register: 1E.9044 */ +/* MSM Line Rx Good Frames Counter Register: 1E.9044 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9044.F:0 ROS MSM Line Rx Good Frames Counter 0 [F:0] + AQ_MsmLineRxGoodFramesCounterRegister_HHD.u0.bits_0.msmLineRxGoodFramesCounter_0 + + Default = 0x0000 + + Rx good frame counter bits 15:0 + + Notes: + Count of frames received without error (Including pause frames). */ + unsigned int msmLineRxGoodFramesCounter_0 : 16; /* 1E.9044.F:0 ROS Default = 0x0000 */ + /* Rx good frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9045.F:0 ROS MSM Line Rx Good Frames Counter 1 [F:0] + AQ_MsmLineRxGoodFramesCounterRegister_HHD.u1.bits_1.msmLineRxGoodFramesCounter_1 + + Default = 0x0000 + + Rx good frame counter bits 31:16 + + Notes: + Count of frames received without error (Including pause frames). */ + unsigned int msmLineRxGoodFramesCounter_1 : 16; /* 1E.9045.F:0 ROS Default = 0x0000 */ + /* Rx good frame counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxGoodFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx FCS Errors Counter Register: 1E.9048 */ +/* MSM Line Rx FCS Errors Counter Register: 1E.9048 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx FCS Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.9048.F:0 ROS MSM Line FCS Error Counter 0 [F:0] + AQ_MsmLineRxFcsErrorsCounterRegister_HHD.u0.bits_0.msmLineFcsErrorCounter_0 + + Default = 0x0000 + + Frame check sequence error counter bits 15:0 + + Notes: + Count of frames for which a CRC-32 Error is detected but the frame is otherwise of correct length. */ + unsigned int msmLineFcsErrorCounter_0 : 16; /* 1E.9048.F:0 ROS Default = 0x0000 */ + /* Frame check sequence error counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx FCS Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.9049.F:0 ROS MSM Line FCS Error Counter 1 [F:0] + AQ_MsmLineRxFcsErrorsCounterRegister_HHD.u1.bits_1.msmLineFcsErrorCounter_1 + + Default = 0x0000 + + Frame check sequence error counter bits 31:16 + + Notes: + Count of frames for which a CRC-32 Error is detected but the frame is otherwise of correct length. */ + unsigned int msmLineFcsErrorCounter_1 : 16; /* 1E.9049.F:0 ROS Default = 0x0000 */ + /* Frame check sequence error counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxFcsErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Alignment Errors Counter Register: 1E.904C */ +/* MSM Line Rx Alignment Errors Counter Register: 1E.904C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Alignment Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.904C.F:0 ROS MSM Line Alignment Error Counter 0 [F:0] + AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD.u0.bits_0.msmLineAlignmentErrorCounter_0 + + Default = 0x0000 + + Alignment error counter bits 15:0 + + Notes: + Count of frames received with an alignment error. */ + unsigned int msmLineAlignmentErrorCounter_0 : 16; /* 1E.904C.F:0 ROS Default = 0x0000 */ + /* Alignment error counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Alignment Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.904D.F:0 ROS MSM Line Alignment Error Counter 1 [F:0] + AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD.u1.bits_1.msmLineAlignmentErrorCounter_1 + + Default = 0x0000 + + Alignment error counter bits 31:16 + + Notes: + Count of frames received with an alignment error. */ + unsigned int msmLineAlignmentErrorCounter_1 : 16; /* 1E.904D.F:0 ROS Default = 0x0000 */ + /* Alignment error counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx Pause Frames Counter Register: 1E.9050 */ +/* MSM Line Tx Pause Frames Counter Register: 1E.9050 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9050.F:0 ROS MSM Line Tx Pause Frames Counter 0 [F:0] + AQ_MsmLineTxPauseFramesCounterRegister_HHD.u0.bits_0.msmLineTxPauseFramesCounter_0 + + Default = 0x0000 + + Tx pause frame counter bits 15:0 + + Notes: + Valid pause frames transmitted. */ + unsigned int msmLineTxPauseFramesCounter_0 : 16; /* 1E.9050.F:0 ROS Default = 0x0000 */ + /* Tx pause frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9051.F:0 ROS MSM Line Tx Pause Frames Counter 1 [F:0] + AQ_MsmLineTxPauseFramesCounterRegister_HHD.u1.bits_1.msmLineTxPauseFramesCounter_1 + + Default = 0x0000 + + Tx pause frame counter bits 31:16 + + + Notes: + Valid pause frames transmitted. */ + unsigned int msmLineTxPauseFramesCounter_1 : 16; /* 1E.9051.F:0 ROS Default = 0x0000 */ + /* Tx pause frame counter bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxPauseFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Pause Frames Counter Register: 1E.9054 */ +/* MSM Line Rx Pause Frames Counter Register: 1E.9054 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9054.F:0 ROS MSM Line Rx Pause Frames Counter 0 [F:0] + AQ_MsmLineRxPauseFramesCounterRegister_HHD.u0.bits_0.msmLineRxPauseFramesCounter_0 + + Default = 0x0000 + + Rx pause frame counter bits 15:0 + + Notes: + Valid pause frames received. */ + unsigned int msmLineRxPauseFramesCounter_0 : 16; /* 1E.9054.F:0 ROS Default = 0x0000 */ + /* Rx pause frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9055.F:0 ROS MSM Line Rx Pause Frames Counter 1 [F:0] + AQ_MsmLineRxPauseFramesCounterRegister_HHD.u1.bits_1.msmLineRxPauseFramesCounter_1 + + Default = 0x0000 + + Rx pause frame counter bits 31:16 + + Notes: + Valid pause frames received. */ + unsigned int msmLineRxPauseFramesCounter_1 : 16; /* 1E.9055.F:0 ROS Default = 0x0000 */ + /* Rx pause frame counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxPauseFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Too Long Errors Counter Register: 1E.9058 */ +/* MSM Line Rx Too Long Errors Counter Register: 1E.9058 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Too Long Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.9058.F:0 ROS MSM Line Rx Too Long Errors Counter 0 [F:0] + AQ_MsmLineRxTooLongErrorsCounterRegister_HHD.u0.bits_0.msmLineRxTooLongErrorsCounter_0 + + Default = 0x0000 + + Too-long errors counter bits 15:0 + + Notes: + Frame received exceeded the maximum length programmed with register FRM_LGTH. */ + unsigned int msmLineRxTooLongErrorsCounter_0 : 16; /* 1E.9058.F:0 ROS Default = 0x0000 */ + /* Too-long errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Too Long Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.9059.F:0 ROS MSM Line Rx Too Long Errors Counter 1 [F:0] + AQ_MsmLineRxTooLongErrorsCounterRegister_HHD.u1.bits_1.msmLineRxTooLongErrorsCounter_1 + + Default = 0x0000 + + Too-long errors counter bits 31:16 + + Notes: + Frame received exceeded the maximum length programmed with register FRM_LGTH. */ + unsigned int msmLineRxTooLongErrorsCounter_1 : 16; /* 1E.9059.F:0 ROS Default = 0x0000 */ + /* Too-long errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxTooLongErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx In Range Length Errors Counter Register: 1E.905C */ +/* MSM Line Rx In Range Length Errors Counter Register: 1E.905C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx In Range Length Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.905C.F:0 ROS MSM Line Rx In Range Length Errors Counter 0 [F:0] + AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD.u0.bits_0.msmLineRxInRangeLengthErrorsCounter_0 + + Default = 0x0000 + + In-range-length errors counter bits 15:0 + + Notes: + A count of frames with a length/type field value between 46 (VLAN: 42) and less than 0x0600, that does not match the number of payload data octets received. Should count also if length/type field is less than 46 (VLAN: 42) and the frame is longer than 64 bytes. */ + unsigned int msmLineRxInRangeLengthErrorsCounter_0 : 16; /* 1E.905C.F:0 ROS Default = 0x0000 */ + /* In-range-length errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx In Range Length Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.905D.F:0 ROS MSM Line Rx In Range Length Errors Counter 1 [F:0] + AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD.u1.bits_1.msmLineRxInRangeLengthErrorsCounter_1 + + Default = 0x0000 + + In-range-length errors counter bits 31:16 + + Notes: + A count of frames with a length/type field value between 46 (VLAN: 42) and less than 0x0600, that does not match the number of payload data octets received. Should count also if length/type field is less than 46 (VLAN: 42) and the frame is longer than 64 bytes. */ + unsigned int msmLineRxInRangeLengthErrorsCounter_1 : 16; /* 1E.905D.F:0 ROS Default = 0x0000 */ + /* In-range-length errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx VLAN Frames Counter Register: 1E.9060 */ +/* MSM Line Tx VLAN Frames Counter Register: 1E.9060 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9060.F:0 ROS MSM Line Tx VLAN Frames Counter 0 [F:0] + AQ_MsmLineTxVlanFramesCounterRegister_HHD.u0.bits_0.msmLineTxVlanFramesCounter_0 + + Default = 0x0000 + + Tx VLAN frames counter bits 15:0 + + Notes: + Valid VLAN tagged frames transmitted. */ + unsigned int msmLineTxVlanFramesCounter_0 : 16; /* 1E.9060.F:0 ROS Default = 0x0000 */ + /* Tx VLAN frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9061.F:0 ROS MSM Line Tx VLAN Frames Counter 1 [F:0] + AQ_MsmLineTxVlanFramesCounterRegister_HHD.u1.bits_1.msmLineTxVlanFramesCounter_1 + + Default = 0x0000 + + Tx VLAN frames counter bits 31:16 + + Notes: + Valid VLAN tagged frames transmitted. */ + unsigned int msmLineTxVlanFramesCounter_1 : 16; /* 1E.9061.F:0 ROS Default = 0x0000 */ + /* Tx VLAN frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxVlanFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx VLAN Frames Counter Register: 1E.9064 */ +/* MSM Line Rx VLAN Frames Counter Register: 1E.9064 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9064.F:0 ROS MSM Line Rx VLAN Frames Counter 0 [F:0] + AQ_MsmLineRxVlanFramesCounterRegister_HHD.u0.bits_0.msmLineRxVlanFramesCounter_0 + + Default = 0x0000 + + Rx VLAN frames counter bits 15:0 + + Notes: + Valid VLAN tagged frames received. */ + unsigned int msmLineRxVlanFramesCounter_0 : 16; /* 1E.9064.F:0 ROS Default = 0x0000 */ + /* Rx VLAN frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9065.F:0 ROS MSM Line Rx VLAN Frames Counter 1 [F:0] + AQ_MsmLineRxVlanFramesCounterRegister_HHD.u1.bits_1.msmLineRxVlanFramesCounter_1 + + Default = 0x0000 + + Rx VLAN frames counter bits 31:16 + + Notes: + Valid VLAN tagged frames received. */ + unsigned int msmLineRxVlanFramesCounter_1 : 16; /* 1E.9065.F:0 ROS Default = 0x0000 */ + /* Rx VLAN frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxVlanFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx Octets Counter Register: 1E.9068 */ +/* MSM Line Tx Octets Counter Register: 1E.9068 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.9068.F:0 ROS MSM Line Tx Octets Counter 0 [F:0] + AQ_MsmLineTxOctetsCounterRegister_HHD.u0.bits_0.msmLineTxOctetsCounter_0 + + Default = 0x0000 + + Tx octets counter bits 15:0 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmLineTxOctetsCounter_0 : 16; /* 1E.9068.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.9069.F:0 ROS MSM Line Tx Octets Counter 1 [F:0] + AQ_MsmLineTxOctetsCounterRegister_HHD.u1.bits_1.msmLineTxOctetsCounter_1 + + Default = 0x0000 + + Tx octets counter bits 31:16 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmLineTxOctetsCounter_1 : 16; /* 1E.9069.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of MSM Line Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.906A.F:0 ROS MSM Line Tx Octets Counter 2 [F:0] + AQ_MsmLineTxOctetsCounterRegister_HHD.u2.bits_2.msmLineTxOctetsCounter_2 + + Default = 0x0000 + + Tx octets counter bits 47:32 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmLineTxOctetsCounter_2 : 16; /* 1E.906A.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 47:32 */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of MSM Line Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.906B.F:0 ROS MSM Line Tx Octets Counter 3 [F:0] + AQ_MsmLineTxOctetsCounterRegister_HHD.u3.bits_3.msmLineTxOctetsCounter_3 + + Default = 0x0000 + + Tx octets counter bits 63:48 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmLineTxOctetsCounter_3 : 16; /* 1E.906B.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 63:48 */ + } bits_3; + uint16_t word_3; + } u3; +} AQ_MsmLineTxOctetsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Octets Counter Register: 1E.906C */ +/* MSM Line Rx Octets Counter Register: 1E.906C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.906C.F:0 ROS MSM Line Rx Octets Counter 0 [F:0] + AQ_MsmLineRxOctetsCounterRegister_HHD.u0.bits_0.msmLineRxOctetsCounter_0 + + Default = 0x0000 + + Rx octets counter bits 15:0 + + Notes: + All octets received except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames received. */ + unsigned int msmLineRxOctetsCounter_0 : 16; /* 1E.906C.F:0 ROS Default = 0x0000 */ + /* Rx octets counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.906D.F:0 ROS MSM Line Rx Octets Counter 1 [F:0] + AQ_MsmLineRxOctetsCounterRegister_HHD.u1.bits_1.msmLineRxOctetsCounter_1 + + Default = 0x0000 + + Rx octets counter bits 31:16 + + Notes: + All octets received except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames received. */ + unsigned int msmLineRxOctetsCounter_1 : 16; /* 1E.906D.F:0 ROS Default = 0x0000 */ + /* Rx octets counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxOctetsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Unicast Frames Counter Register: 1E.9070 */ +/* MSM Line Rx Unicast Frames Counter Register: 1E.9070 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9070.F:0 ROS MSM Line Rx Unicast Frames Counter 0 [F:0] + AQ_MsmLineRxUnicastFramesCounterRegister_HHD.u0.bits_0.msmLineRxUnicastFramesCounter_0 + + Default = 0x0000 + + Rx unicast frames counter bits 15:0 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '0'. */ + unsigned int msmLineRxUnicastFramesCounter_0 : 16; /* 1E.9070.F:0 ROS Default = 0x0000 */ + /* Rx unicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9071.F:0 ROS MSM Line Rx Unicast Frames Counter 1 [F:0] + AQ_MsmLineRxUnicastFramesCounterRegister_HHD.u1.bits_1.msmLineRxUnicastFramesCounter_1 + + Default = 0x0000 + + Rx unicast frames counter bits 31:16 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '0'. */ + unsigned int msmLineRxUnicastFramesCounter_1 : 16; /* 1E.9071.F:0 ROS Default = 0x0000 */ + /* Rx unicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxUnicastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Multicast Frames Counter Register: 1E.9074 */ +/* MSM Line Rx Multicast Frames Counter Register: 1E.9074 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9074.F:0 ROS MSM Line Rx Multicast Frames Counter 0 [F:0] + AQ_MsmLineRxMulticastFramesCounterRegister_HHD.u0.bits_0.msmLineRxMulticastFramesCounter_0 + + Default = 0x0000 + + Rx multicast frames counter bits 15:0 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '1' but not the broadcast address (all bits set '1' ). Pause frames are not counted. */ + unsigned int msmLineRxMulticastFramesCounter_0 : 16; /* 1E.9074.F:0 ROS Default = 0x0000 */ + /* Rx multicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9075.F:0 ROS MSM Line Rx Multicast Frames Counter 1 [F:0] + AQ_MsmLineRxMulticastFramesCounterRegister_HHD.u1.bits_1.msmLineRxMulticastFramesCounter_1 + + Default = 0x0000 + + Rx multicast frames counter bits 31:16 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '1' but not the broadcast address (all bits set '1' ). Pause frames are not counted. */ + unsigned int msmLineRxMulticastFramesCounter_1 : 16; /* 1E.9075.F:0 ROS Default = 0x0000 */ + /* Rx multicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxMulticastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Broadcast Frames Counter Register: 1E.9078 */ +/* MSM Line Rx Broadcast Frames Counter Register: 1E.9078 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9078.F:0 ROS MSM Line Rx Broadcast Frames Counter 0 [F:0] + AQ_MsmLineRxBroadcastFramesCounterRegister_HHD.u0.bits_0.msmLineRxBroadcastFramesCounter_0 + + Default = 0x0000 + + Rx broadcast frames counter bits 15:0 + + Notes: + Incremented with each valid frame received on the receive FIFO interface (FIFO) and all bits of the destination address were set '1'. */ + unsigned int msmLineRxBroadcastFramesCounter_0 : 16; /* 1E.9078.F:0 ROS Default = 0x0000 */ + /* Rx broadcast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9079.F:0 ROS MSM Line Rx Broadcast Frames Counter 1 [F:0] + AQ_MsmLineRxBroadcastFramesCounterRegister_HHD.u1.bits_1.msmLineRxBroadcastFramesCounter_1 + + Default = 0x0000 + + Rx broadcast frames counter bits 31:16 + + Notes: + Incremented with each valid frame received on the receive FIFO interface (FIFO) and all bits of the destination address were set '1'. */ + unsigned int msmLineRxBroadcastFramesCounter_1 : 16; /* 1E.9079.F:0 ROS Default = 0x0000 */ + /* Rx broadcast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxBroadcastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx Errors Counter Register: 1E.907C */ +/* MSM Line Tx Errors Counter Register: 1E.907C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.907C.F:0 ROS MSM Line Tx Errors Counter 0 [F:0] + AQ_MsmLineTxErrorsCounterRegister_HHD.u0.bits_0.msmLineTxErrorsCounter_0 + + Default = 0x0000 + + Rx errors counter bits 15:0 + + Notes: + Number of frames transmitted with error: + - FIFO Overflow Errors + - FIFO Underflow Errors */ + unsigned int msmLineTxErrorsCounter_0 : 16; /* 1E.907C.F:0 ROS Default = 0x0000 */ + /* Rx errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.907D.F:0 ROS MSM Line Tx Errors Counter 1 [F:0] + AQ_MsmLineTxErrorsCounterRegister_HHD.u1.bits_1.msmLineTxErrorsCounter_1 + + Default = 0x0000 + + Tx errors counter bits 31:16 + + Notes: + Number of frames transmitted with error: + - FIFO Overflow Errors + - FIFO Underflow Errors */ + unsigned int msmLineTxErrorsCounter_1 : 16; /* 1E.907D.F:0 ROS Default = 0x0000 */ + /* Tx errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx Unicast Frames Counter Register: 1E.9084 */ +/* MSM Line Tx Unicast Frames Counter Register: 1E.9084 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9084.F:0 ROS MSM Line Tx Unicast Frames Counter 0 [F:0] + AQ_MsmLineTxUnicastFramesCounterRegister_HHD.u0.bits_0.msmLineTxUnicastFramesCounter_0 + + Default = 0x0000 + + Tx unicast frames counter bits 15:0 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '0'. */ + unsigned int msmLineTxUnicastFramesCounter_0 : 16; /* 1E.9084.F:0 ROS Default = 0x0000 */ + /* Tx unicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9085.F:0 ROS MSM Line Tx Unicast Frames Counter 1 [F:0] + AQ_MsmLineTxUnicastFramesCounterRegister_HHD.u1.bits_1.msmLineTxUnicastFramesCounter_1 + + Default = 0x0000 + + Tx unicast frames counter bits 31:16 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '0'. */ + unsigned int msmLineTxUnicastFramesCounter_1 : 16; /* 1E.9085.F:0 ROS Default = 0x0000 */ + /* Tx unicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxUnicastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx Multicast Frames Counter Register: 1E.9088 */ +/* MSM Line Tx Multicast Frames Counter Register: 1E.9088 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9088.F:0 ROS MSM Line Tx Multicast Frames Counter 0 [F:0] + AQ_MsmLineTxMulticastFramesCounterRegister_HHD.u0.bits_0.msmLineTxMulticastFramesCounter_0 + + Default = 0x0000 + + Tx multicast frames counter bits 15:0 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '1' but not the broadcast address (all bits '1'). */ + unsigned int msmLineTxMulticastFramesCounter_0 : 16; /* 1E.9088.F:0 ROS Default = 0x0000 */ + /* Tx multicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9089.F:0 ROS MSM Line Tx Multicast Frames Counter 1 [F:0] + AQ_MsmLineTxMulticastFramesCounterRegister_HHD.u1.bits_1.msmLineTxMulticastFramesCounter_1 + + Default = 0x0000 + + Tx multicast frames counter bits 31:16 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '1' but not the broadcast address (all bits '1'). */ + unsigned int msmLineTxMulticastFramesCounter_1 : 16; /* 1E.9089.F:0 ROS Default = 0x0000 */ + /* Tx multicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxMulticastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx Broadcast Frames Counter Register: 1E.908C */ +/* MSM Line Tx Broadcast Frames Counter Register: 1E.908C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.908C.F:0 ROS MSM Line Tx Broadcast Frames Counter 0 [F:0] + AQ_MsmLineTxBroadcastFramesCounterRegister_HHD.u0.bits_0.msmLineTxBroadcastFramesCounter_0 + + Default = 0x0000 + + Tx broadcast frames counter bits 15:0 + + Notes: + Incremented with each frame written to the FIFO interface and all bits of the destination address set to '1'. */ + unsigned int msmLineTxBroadcastFramesCounter_0 : 16; /* 1E.908C.F:0 ROS Default = 0x0000 */ + /* Tx broadcast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.908D.F:0 ROS MSM Line Tx Broadcast Frames Counter 1 [F:0] + AQ_MsmLineTxBroadcastFramesCounterRegister_HHD.u1.bits_1.msmLineTxBroadcastFramesCounter_1 + + Default = 0x0000 + + Tx broadcast frames counter bits 31:16 + + Notes: + Incremented with each frame written to the FIFO interface and all bits of the destination address set to '1'. */ + unsigned int msmLineTxBroadcastFramesCounter_1 : 16; /* 1E.908D.F:0 ROS Default = 0x0000 */ + /* Tx broadcast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxBroadcastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Errors Counter Register: 1E.90C8 */ +/* MSM Line Rx Errors Counter Register: 1E.90C8 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.90C8.F:0 ROS MSM Line Rx Errors Counter 0 [F:0] + AQ_MsmLineRxErrorsCounterRegister_HHD.u0.bits_0.msmLineRxErrorsCounter_0 + + Default = 0x0000 + + Rx errors counter bits 15:0 + + Notes: + Number of frames received with error: + - FIFO Overflow Errors + - CRC Errors + - Payload Length Errors + - Jabber and Oversized Errors + - Alignment Errors + - The dedicated Error Code (0xfe, not a code error) was received */ + unsigned int msmLineRxErrorsCounter_0 : 16; /* 1E.90C8.F:0 ROS Default = 0x0000 */ + /* Rx errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.90C9.F:0 ROS MSM Line Rx Errors Counter 1 [F:0] + AQ_MsmLineRxErrorsCounterRegister_HHD.u1.bits_1.msmLineRxErrorsCounter_1 + + Default = 0x0000 + + Rx errors counter bits 31:16 + + Notes: + Number of frames received with error: + - FIFO Overflow Errors + - CRC Errors + - Payload Length Errors + - Jabber and Oversized Errors + - Alignment Errors + - The dedicated Error Code (0xfe, not a code error) was received */ + unsigned int msmLineRxErrorsCounter_1 : 16; /* 1E.90C9.F:0 ROS Default = 0x0000 */ + /* Rx errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Control: 1E.C000 */ +/* Global Control: 1E.C000 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Control */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Control */ + union + { + struct + { + /*! \brief 1E.C001.F R/W uP Reset + AQ_GlobalControl_HHD.u1.bits_1.upReset + + Default = 0x0 + + 1 = Reset + + + Notes: + Resets the uP and the PIF master and slave bus. Will be active for a minimum of 100 microseconds. */ + unsigned int upReset : 1; /* 1E.C001.F R/W Default = 0x0 */ + /* 1 = Reset + */ + unsigned int reserved0 : 8; + /*! \brief 1E.C001.6 R/W uP Run Stall Override + AQ_GlobalControl_HHD.u1.bits_1.upRunStallOverride + + Default = 0x0 + + 0 = uP Run Stall from "MDIO Boot Load" pin. + 1 = uP Run Stall from See MCP Run Stall bit + + + + Notes: + This bit selects the uP Run Stall from either the "MDIO Boot Load" pin or the See MCP Run Stall bit. Pin no longer brought out as deprecated. */ + unsigned int upRunStallOverride : 1; /* 1E.C001.6 R/W Default = 0x0 */ + /* 0 = uP Run Stall from "MDIO Boot Load" pin. + 1 = uP Run Stall from See MCP Run Stall bit + + */ + unsigned int reserved1 : 5; + /*! \brief 1E.C001.0 R/W uP Run Stall + AQ_GlobalControl_HHD.u1.bits_1.upRunStall + + Default = 0x0 + + 1 = uP Run Stall + 0 = uP normal mode + + + Notes: + Deactivates the uP. */ + unsigned int upRunStall : 1; /* 1E.C001.0 R/W Default = 0x0 */ + /* 1 = uP Run Stall + 0 = uP normal mode + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalControl_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Reset Control: 1E.C006 */ +/* Global Reset Control: 1E.C006 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Reset Control */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.C006.E R/WPD Global MMD Reset Disable + AQ_GlobalResetControl_HHD.u0.bits_0.globalMMD_ResetDisable + + Provisionable Default = 0x0 + + 1 = Disable the S/W reset to the Global MMD registers + 0 = Enable the S/W reset to the Global MMD registers + + + Notes: + Setting this bit prevents a Global S/W reset or Global S/W reset from resetting the Global MMD registers */ + unsigned int globalMMD_ResetDisable : 1; /* 1E.C006.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Disable the S/W reset to the Global MMD registers + 0 = Enable the S/W reset to the Global MMD registers + */ + unsigned int reserved1 : 14; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalResetControl_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Diagnostic Provisioning: 1E.C400 */ +/* Global Diagnostic Provisioning: 1E.C400 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Diagnostic Provisioning */ + union + { + struct + { + /*! \brief 1E.C400.F R/WPD Enable Diagnostics + AQ_GlobalDiagnosticProvisioning_HHD.u0.bits_0.enableDiagnostics + + Provisionable Default = 0x1 + + 1 = Chip performs diagnostics on power-up + */ + unsigned int enableDiagnostics : 1; /* 1E.C400.F R/WPD Provisionable Default = 0x1 */ + /* 1 = Chip performs diagnostics on power-up */ + unsigned int reserved0 : 15; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalDiagnosticProvisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Thermal Provisioning: 1E.C420 */ +/* Global Thermal Provisioning: 1E.C420 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C420.F:0 R/WPD Reserved 0 [F:0] + AQ_GlobalThermalProvisioning_HHD.u0.bits_0.reserved_0 + + Provisionable Default = 0x0000 + + Internal reserved - do not modify + + */ + unsigned int reserved_0 : 16; /* 1E.C420.F:0 R/WPD Provisionable Default = 0x0000 */ + /* Internal reserved - do not modify + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C421.F:0 R/WPD High Temp Failure Threshold [F:0] + AQ_GlobalThermalProvisioning_HHD.u1.bits_1.highTempFailureThreshold + + Provisionable Default = 0x4600 + + [F:0] of high temperature failure threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 70 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A000 - 1.A001: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int highTempFailureThreshold : 16; /* 1E.C421.F:0 R/WPD Provisionable Default = 0x4600 */ + /* [F:0] of high temperature failure threshold */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C422.F:0 R/WPD Low Temp Failure Threshold [F:0] + AQ_GlobalThermalProvisioning_HHD.u2.bits_2.lowTempFailureThreshold + + Provisionable Default = 0x0000 + + [F:0] of low temperature failure threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 0 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A002 - 1.A003: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int lowTempFailureThreshold : 16; /* 1E.C422.F:0 R/WPD Provisionable Default = 0x0000 */ + /* [F:0] of low temperature failure threshold */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C423.F:0 R/WPD High Temp Warning Threshold [F:0] + AQ_GlobalThermalProvisioning_HHD.u3.bits_3.highTempWarningThreshold + + Provisionable Default = 0x3C00 + + [F:0] of high temperature warning threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD008. Default is 60 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A004 - 1.A005: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int highTempWarningThreshold : 16; /* 1E.C423.F:0 R/WPD Provisionable Default = 0x3C00 */ + /* [F:0] of high temperature warning threshold */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C424.F:0 R/WPD Low Temp Warning Threshold [F:0] + AQ_GlobalThermalProvisioning_HHD.u4.bits_4.lowTempWarningThreshold + + Provisionable Default = 0x0A00 + + [F:0] of low temperature warning threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 10 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A006 - 1.A007: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int lowTempWarningThreshold : 16; /* 1E.C424.F:0 R/WPD Provisionable Default = 0x0A00 */ + /* [F:0] of low temperature warning threshold */ + } bits_4; + uint16_t word_4; + } u4; +} AQ_GlobalThermalProvisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global LED Provisioning: 1E.C430 */ +/* Global LED Provisioning: 1E.C430 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 2; + /*! \brief 1E.C430.D:9 R/WPD Reserved Provisioning C430 [4:0] + AQ_GlobalLedProvisioning_HHD.u0.bits_0.reservedProvisioningC430 + + Provisionable Default = 0x00 + + Reserved for future use + */ + unsigned int reservedProvisioningC430 : 5; /* 1E.C430.D:9 R/WPD Provisionable Default = 0x00 */ + /* Reserved for future use */ + /*! \brief 1E.C430.8 R/WPD LED #0 Manual Set + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_0ManualSet : 1; /* 1E.C430.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + /*! \brief 1E.C430.7 R/WPD LED #0 10 Gb/s Link Established + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_0_10Gb_sLinkEstablished : 1; /* 1E.C430.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C430.6 R/WPD LED #0 1 Gb/s Link Established + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_0_1Gb_sLinkEstablished : 1; /* 1E.C430.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C430.5 R/WPD LED #0 100 Mb/s Link Established + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s. + + */ + unsigned int led_0_100Mb_sLinkEstablished : 1; /* 1E.C430.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s. + */ + /*! \brief 1E.C430.4 R/WPD LED #0 Connecting + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_0Connecting : 1; /* 1E.C430.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C430.3 R/WPD LED #0 Receive Activity + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_0ReceiveActivity : 1; /* 1E.C430.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C430.2 R/WPD LED #0 Transmit Activity + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_0TransmitActivity : 1; /* 1E.C430.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C430.1:0 R/WPD LED #0 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_0ActivityStretch : 2; /* 1E.C430.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 2; + /*! \brief 1E.C431.D:9 R/WPD Reserved Provisioning C431 [4:0] + AQ_GlobalLedProvisioning_HHD.u1.bits_1.reservedProvisioningC431 + + Provisionable Default = 0x00 + + Reserved for future use + */ + unsigned int reservedProvisioningC431 : 5; /* 1E.C431.D:9 R/WPD Provisionable Default = 0x00 */ + /* Reserved for future use */ + /*! \brief 1E.C431.8 R/WPD LED #1 Manual Set + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_1ManualSet : 1; /* 1E.C431.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + /*! \brief 1E.C431.7 R/WPD LED #1 10 Gb/s Link Established + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_1_10Gb_sLinkEstablished : 1; /* 1E.C431.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C431.6 R/WPD LED #1 1 Gb/s Link Established + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_1_1Gb_sLinkEstablished : 1; /* 1E.C431.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C431.5 R/WPD LED #1 100 Mb/s Link Established + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s. + + */ + unsigned int led_1_100Mb_sLinkEstablished : 1; /* 1E.C431.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s. + */ + /*! \brief 1E.C431.4 R/WPD LED #1 Connecting + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_1Connecting : 1; /* 1E.C431.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C431.3 R/WPD LED #1 Receive Activity + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_1ReceiveActivity : 1; /* 1E.C431.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C431.2 R/WPD LED #1 Transmit Activity + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_1TransmitActivity : 1; /* 1E.C431.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C431.1:0 R/WPD LED #1 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_1ActivityStretch : 2; /* 1E.C431.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 2; + /*! \brief 1E.C432.D:9 R/WPD Reserved Provisioning C432 [4:0] + AQ_GlobalLedProvisioning_HHD.u2.bits_2.reservedProvisioningC432 + + Provisionable Default = 0x00 + + Reserved for future use + */ + unsigned int reservedProvisioningC432 : 5; /* 1E.C432.D:9 R/WPD Provisionable Default = 0x00 */ + /* Reserved for future use */ + /*! \brief 1E.C432.8 R/WPD LED #2 Manual Set + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_2ManualSet : 1; /* 1E.C432.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + /*! \brief 1E.C432.7 R/WPD LED #2 10 Gb/s Link Established + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_2_10Gb_sLinkEstablished : 1; /* 1E.C432.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C432.6 R/WPD LED #2 1 Gb/s Link Established + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_2_1Gb_sLinkEstablished : 1; /* 1E.C432.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C432.5 R/WPD LED #2 100 Mb/s Link Established + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s. + */ + unsigned int led_2_100Mb_sLinkEstablished : 1; /* 1E.C432.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s. */ + /*! \brief 1E.C432.4 R/WPD LED #2 Connecting + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_2Connecting : 1; /* 1E.C432.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C432.3 R/WPD LED #2 Receive Activity + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_2ReceiveActivity : 1; /* 1E.C432.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C432.2 R/WPD LED #2 Transmit Activity + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_2TransmitActivity : 1; /* 1E.C432.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C432.1:0 R/WPD LED #2 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_2ActivityStretch : 2; /* 1E.C432.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 15; + /*! \brief 1E.C437.0 R/WPD LED Operation Mode + AQ_GlobalLedProvisioning_HHD.u7.bits_7.ledOperationMode + + Provisionable Default = 0x0 + + 1 = LED link activity in Mode #2 + 0 = LED link activity in Aquantia classic mode + + + Notes: + When set to 1, the LED blinking rate is based on Mode #2 algorithm. When set to 0, the LED blinking rate is based on the classic Aquantia algorithm. */ + unsigned int ledOperationMode : 1; /* 1E.C437.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED link activity in Mode #2 + 0 = LED link activity in Aquantia classic mode + */ + } bits_7; + uint16_t word_7; + } u7; + /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_8; + uint16_t word_8; + } u8; + /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_9; + uint16_t word_9; + } u9; + /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_10; + uint16_t word_10; + } u10; + /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_11; + uint16_t word_11; + } u11; + /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_12; + uint16_t word_12; + } u12; + /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_13; + uint16_t word_13; + } u13; + /*! \brief Union for bit and word level access of word 14 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_14; + uint16_t word_14; + } u14; +} AQ_GlobalLedProvisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global General Provisioning: 1E.C440 */ +/* Global General Provisioning: 1E.C440 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.C441.E R/WPD MDIO Broadcast Mode Enable + AQ_GlobalGeneralProvisioning_HHD.u1.bits_1.mdioBroadcastModeEnable + + Provisionable Default = 0x0 + + 1 = Enable broadcast on address set in 1E.C446 + 0 = Disable broadcast on n address set in 1E.C446 + + + Notes: + When enabled, writes and load MMD address opcodes are supported. Read opcodes are ignored. */ + unsigned int mdioBroadcastModeEnable : 1; /* 1E.C441.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable broadcast on address set in 1E.C446 + 0 = Disable broadcast on n address set in 1E.C446 + */ + /*! \brief 1E.C441.D R/WPD MDIO Read MSW First Enable + AQ_GlobalGeneralProvisioning_HHD.u1.bits_1.mdioReadMSW_FirstEnable + + Provisionable Default = 0x0 + + 1 = MSW of counter must be read first + 0 = LSW of counter must be read first + + + Notes: + This bit configures whether the MSW or LSW must be read first for counters greater than 16 bits. */ + unsigned int mdioReadMSW_FirstEnable : 1; /* 1E.C441.D R/WPD Provisionable Default = 0x0 */ + /* 1 = MSW of counter must be read first + 0 = LSW of counter must be read first + */ + unsigned int reserved1 : 8; + /*! \brief 1E.C441.4 R/WPD MDIO Drive Configuration + AQ_GlobalGeneralProvisioning_HHD.u1.bits_1.mdioDriveConfiguration + + Provisionable Default = 0x0 + + 0 = MDIO driver is in normal mode + 1 = MDIO driver is in open drain mode + + + Notes: + When the MDIO driver is in open drain mode during a read cycle, "0" data will be actively driven out of the MDIO, "1" data will set the MDIO driver in high impedance state and an external pullup will set the MDIO line to "1". The Turn-Around "0" will also be actively driven out of the MDIO, therefore in open drain mode, the Turn-Around is still "Z0". */ + unsigned int mdioDriveConfiguration : 1; /* 1E.C441.4 R/WPD Provisionable Default = 0x0 */ + /* 0 = MDIO driver is in normal mode + 1 = MDIO driver is in open drain mode + */ + /*! \brief 1E.C441.3 R/WPD MDIO Preamble Detection Disable + AQ_GlobalGeneralProvisioning_HHD.u1.bits_1.mdioPreambleDetectionDisable + + Provisionable Default = 0x0 + + 1 = Suppress preamble detection on MDIO + 0 = Enable preamble detection on MDIO + + */ + unsigned int mdioPreambleDetectionDisable : 1; /* 1E.C441.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = Suppress preamble detection on MDIO + 0 = Enable preamble detection on MDIO + */ + unsigned int reserved2 : 1; + unsigned int reserved3 : 2; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 15; + /*! \brief 1E.C442.0 R/W Daisy Chain Reset + AQ_GlobalGeneralProvisioning_HHD.u2.bits_2.daisyChainReset + + Default = 0x0 + + 1 = Reset the daisy chain + + + Notes: + Toggling this bit from 0 to 1 will reload the IRAM and DRAM and reset the uP. The uP will be in uP run stall during the reload process. After the reload process, uP run stall will be de-asserted and the uP reset will be asserted. Note that before setting this bit, the See Soft Reset bit needs to be de-asserted. */ + unsigned int daisyChainReset : 1; /* 1E.C442.0 R/W Default = 0x0 */ + /* 1 = Reset the daisy chain + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 11; + /*! \brief 1E.C447.4:0 R/WPD MDIO Broadcast Address Configuration [4:0] + AQ_GlobalGeneralProvisioning_HHD.u7.bits_7.mdioBroadcastAddressConfiguration + + Provisionable Default = 0x1F + + Broadcast address + + + Notes: + Allows setting the broadcast address. By default this is set to 0x1F */ + unsigned int mdioBroadcastAddressConfiguration : 5; /* 1E.C447.4:0 R/WPD Provisionable Default = 0x1F */ + /* Broadcast address + */ + } bits_7; + uint16_t word_7; + } u7; + /*! \brief Union for bit and word level access of word 8 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_8; + uint16_t word_8; + } u8; + /*! \brief Union for bit and word level access of word 9 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 9; + /*! \brief 1E.C449.6:0 R/W MDIO Preamble Length [6:0] + AQ_GlobalGeneralProvisioning_HHD.u9.bits_9.mdioPreambleLength + + Default = 0x02 + + MDIO Preamble Length + + */ + unsigned int mdioPreambleLength : 7; /* 1E.C449.6:0 R/W Default = 0x02 */ + /* MDIO Preamble Length + */ + } bits_9; + uint16_t word_9; + } u9; +} AQ_GlobalGeneralProvisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global NVR Provisioning: 1E.C450 */ +/* Global NVR Provisioning: 1E.C450 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global NVR Provisioning */ + union + { + struct + { + unsigned int reserved0 : 5; + /*! \brief 1E.C450.A:8 R/WPD NVR Data Length [2:0] + AQ_GlobalNvrProvisioning_HHD.u0.bits_0.nvrDataLength + + Provisionable Default = 0x4 + + NVR data length ranges from 0 bytes to 4 bytes + + + Notes: + This sets the length of the data burst used in read and write operations. + */ + unsigned int nvrDataLength : 3; /* 1E.C450.A:8 R/WPD Provisionable Default = 0x4 */ + /* NVR data length ranges from 0 bytes to 4 bytes + */ + unsigned int reserved1 : 1; + /*! \brief 1E.C450.6:4 R/WPD NVR Dummy Length [2:0] + AQ_GlobalNvrProvisioning_HHD.u0.bits_0.nvrDummyLength + + Provisionable Default = 0x0 + + NVR dummy length ranges from 0 bytes to 4 bytes + + + Notes: + This sets the length of the dummy field used in some manufacturer's read status and write status operations. + */ + unsigned int nvrDummyLength : 3; /* 1E.C450.6:4 R/WPD Provisionable Default = 0x0 */ + /* NVR dummy length ranges from 0 bytes to 4 bytes + */ + unsigned int reserved2 : 2; + /*! \brief 1E.C450.1:0 R/WPD NVR Address Length [1:0] + AQ_GlobalNvrProvisioning_HHD.u0.bits_0.nvrAddressLength + + Provisionable Default = 0x2 + + NVR address length ranges from 0 bytes up to 3 bytes + + + Notes: + This sets the length of the address field used in read and write operations. Use of this field is enabled via Bit 8 of See Global NVR Provisioning 2: Address 1E.C451 . + */ + unsigned int nvrAddressLength : 2; /* 1E.C450.1:0 R/WPD Provisionable Default = 0x2 */ + /* NVR address length ranges from 0 bytes up to 3 bytes + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global NVR Provisioning */ + union + { + struct + { + unsigned int reserved0 : 7; + /*! \brief 1E.C451.8 R/WPD NVR Address Length Override + AQ_GlobalNvrProvisioning_HHD.u1.bits_1.nvrAddressLengthOverride + + Provisionable Default = 0x0 + + 0 = NVR address length is based on the "NVR_SIZE" pin. + 1 = NVR address length is based on the See NVR Address Length [1:0] register + + + Notes: + When this bit = 0 and NVR_SIZE pin = 0, the NVR address length is 2 bytes. When this bit = 0 and the NVR_SIZE pin = 1, the NVR address length is 3 bytes. When this bit = 1 the NVR address length is from the See NVR Address Length [1:0] */ + unsigned int nvrAddressLengthOverride : 1; /* 1E.C451.8 R/WPD Provisionable Default = 0x0 */ + /* 0 = NVR address length is based on the "NVR_SIZE" pin. + 1 = NVR address length is based on the See NVR Address Length [1:0] register + */ + /*! \brief 1E.C451.7:0 R/WPD NVR Clock Divide [7:0] + AQ_GlobalNvrProvisioning_HHD.u1.bits_1.nvrClockDivide + + Provisionable Default = 0xA0 + + NVR clock divide. Clock frequency is divided by the NVR clock divide + 1 + + */ + unsigned int nvrClockDivide : 8; /* 1E.C451.7:0 R/WPD Provisionable Default = 0xA0 */ + /* NVR clock divide. Clock frequency is divided by the NVR clock divide + 1 + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global NVR Provisioning */ + union + { + struct + { + unsigned int reserved0 : 14; + /*! \brief 1E.C452.1 R/W NVR Daisy Chain Clock Divide Override + AQ_GlobalNvrProvisioning_HHD.u2.bits_2.nvrDaisyChainClockDivideOverride + + Default = 0x0 + + 1 = Override NVR clock divide when in daisy chain master mode + + + Notes: + When in daisy chain master mode, the clock divide configuration is received from the FLASH. This bit will override the clock divide configuration from the FLASH with the See NVR Clock Divide [7:0] . */ + unsigned int nvrDaisyChainClockDivideOverride : 1; /* 1E.C452.1 R/W Default = 0x0 */ + /* 1 = Override NVR clock divide when in daisy chain master mode + */ + /*! \brief 1E.C452.0 R/W NVR Daisy Chain Disable + AQ_GlobalNvrProvisioning_HHD.u2.bits_2.nvrDaisyChainDisable + + Default = 0x0 + + 1 = Disable the Daisy Chain + + + Notes: + When in daisy chain master mode, the daisy chain and MDIO can both access the SPI. Setting this bit to 1 will disable the daisy chain from accessing the SPI and force it into a reset state. */ + unsigned int nvrDaisyChainDisable : 1; /* 1E.C452.0 R/W Default = 0x0 */ + /* 1 = Disable the Daisy Chain + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global NVR Provisioning */ + union + { + struct + { + unsigned int reserved0 : 11; + /*! \brief 1E.C453.4 R/W NVR Reset + AQ_GlobalNvrProvisioning_HHD.u3.bits_3.nvrReset + + Default = 0x0 + + 1 = Reset SPI + + */ + unsigned int nvrReset : 1; /* 1E.C453.4 R/W Default = 0x0 */ + /* 1 = Reset SPI + */ + unsigned int reserved1 : 4; + } bits_3; + uint16_t word_3; + } u3; +} AQ_GlobalNvrProvisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Reserved Provisioning: 1E.C470 */ +/* Global Reserved Provisioning: 1E.C470 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C470.F R/WPD Diagnostics Select + AQ_GlobalReservedProvisioning_HHD.u0.bits_0.diagnosticsSelect + + Provisionable Default = 0x0 + + 1 = Provide Extended MDI Diagnostics Information. + 0 = Provide normal cable diagnostics + + + Notes: + These bits select what sort of cable diagnostics to perform. For regular cable diagnostics, Bit F is set to zero, and the diagnostics are triggered by setting Bit 4. For extended diagnostics, Bit F is set to 1, and the desired extended diagnostics are selected by Bits E:D. The routine is then triggered by setting Bit 4. Each of the extended diagnostic routines present data for all for MDI pairs (A, B, C, D) consecutively, and after the data for each channel is gathered Bits F:D are reset. To get the data for the next pair, Bits F:D must be set back to the desired value (which must be the same as the initial channel). This continues until the data for all channels has been gathered. The address in memory where the data is stored is given in 1E.C802 and 1E.C804. + + For the case of PSD, the structure is as follows: + Int32 info + Int16 data[Len] + Info = Len << 16 | TxEnable << 8 | Pair (0 = A, etc.) + + For TDR: + Int32 info + Int16 tdr_A[Len] + Int16 tdr_B[Len] + Int16 tdr_C[Len] + Int16 tdr_D[Len] + + Info = Len << 16 | Channel + + TDR data is from the current pair to all other pairs. + + At the end of retrieving extended MDI diag data, the part will be reset. Conversely the only way to exit this routine once it starts is to issue a PMA reset. */ + unsigned int diagnosticsSelect : 1; /* 1E.C470.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Provide Extended MDI Diagnostics Information. + 0 = Provide normal cable diagnostics + */ + /*! \brief 1E.C470.E:D R/WPD Extended MDI Diagnostics Select [1:0] + AQ_GlobalReservedProvisioning_HHD.u0.bits_0.extendedMdiDiagnosticsSelect + + Provisionable Default = 0x0 + + 0x0 = TDR Data + 0x1 = RFI Channel PSD + 0x2 = Noise PSD while the local Tx is Off + 0x3 = Noise PSD while the local Tx is On + + + Notes: + These bits select what sort of cable diagnostics to perform. For regular cable diagnostics, Bit F is set to zero, and the diagnostics are triggered by setting Bit 4. For extended diagnostics, Bit F is set to 1, and the desired extended diagnostics are selected by Bits E:D. The routine is then triggered by setting Bit 4. Each of the extended diagnostic routines present data for all for MDI pairs (A, B, C, D) consecutively, and after the data for each channel is gathered Bits F:D are reset. To get the data for the next pair, Bits F:D must be set back to the desired value (which must be the same as the initial channel). This continues until the data for all channels has been gathered. The address in memory where the data is stored is given in 1E.C802 and 1E.C804. + + For the case of PSD, the structure is as follows: + Int32 info + Int16 data[Len] + Info = Len << 16 | TxEnable << 8 | Pair (0 = A, etc.) + + For TDR: + Int32 info + Int16 tdr_A[Len] + Int16 tdr_B[Len] + Int16 tdr_C[Len] + Int16 tdr_D[Len] + + Info = Len << 16 | Channel + + TDR data is from the current pair to all other pairs. + + At the end of retrieving extended MDI diag data, the part will be reset. Conversely the only way to exit this routine once it starts is to issue a PMA reset. */ + unsigned int extendedMdiDiagnosticsSelect : 2; /* 1E.C470.E:D R/WPD Provisionable Default = 0x0 */ + /* 0x0 = TDR Data + 0x1 = RFI Channel PSD + 0x2 = Noise PSD while the local Tx is Off + 0x3 = Noise PSD while the local Tx is On + */ + unsigned int reserved0 : 5; + unsigned int reserved1 : 3; + /*! \brief 1E.C470.4 R/WSC Initiate Cable Diagnostics + AQ_GlobalReservedProvisioning_HHD.u0.bits_0.initiateCableDiagnostics + + Default = 0x0 + + 1 = Perform cable diagnostics + + + Notes: + Perform cable diagnostics regardless of link state. If link is up, setting this bit will cause the link to drop while diagnostics are performed. This bit is self-clearing upon completion of the cable diagnostics. + + NOTE!! This is a processor intensive operation. Completion of this operation can also be monitored via 1E.C831.F */ + unsigned int initiateCableDiagnostics : 1; /* 1E.C470.4 R/WSC Default = 0x0 */ + /* 1 = Perform cable diagnostics + */ + unsigned int reserved2 : 4; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved0 : 9; + /*! \brief 1E.C471.6 R/WuP Enable Daisy-Chain Hop-Count Override + AQ_GlobalReservedProvisioning_HHD.u1.bits_1.enableDaisy_chainHop_countOverride + + Default = 0x0 + + 1 = Hop-count is set by Bits 5:0 + 0 = Hop-count is determined by the daisy-chain + + + Notes: + Daisy-Chain Hop-Count Override should be used during MDIO boot-load operation, as the daisy-chain hop-count does not function when the daisy-chain is disabled (1E.C452.0). Setting this bit tells the processor where in the daisy-chain it is, so that the provisioning operation will function correctly. */ + unsigned int enableDaisy_chainHop_countOverride : 1; /* 1E.C471.6 R/WuP Default = 0x0 */ + /* 1 = Hop-count is set by Bits 5:0 + 0 = Hop-count is determined by the daisy-chain + */ + /*! \brief 1E.C471.5:0 R/WuP Daisy-Chain Hop-Count Override Value [5:0] + AQ_GlobalReservedProvisioning_HHD.u1.bits_1.daisy_chainHop_countOverrideValue + + Default = 0x00 + + The value to use for the PHY's daisy-chain hop-count. Valid values are from 0 -> 47 + + + Notes: + Daisy-Chain Hop-Count Override should be used during MDIO boot-load operation, as the daisy-chain hop-count does not function when the daisy-chain is disabled (1E.C452.0). Setting this bit tells the processor where in the daisy-chain it is, so that the provisioning operation will function correctly. */ + unsigned int daisy_chainHop_countOverrideValue : 6; /* 1E.C471.5:0 R/WuP Default = 0x00 */ + /* The value to use for the PHY's daisy-chain hop-count. Valid values are from 0 -> 47 + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.C472.E R/WPD Enable VDD Power Supply Tuning + AQ_GlobalReservedProvisioning_HHD.u2.bits_2.enableVddPowerSupplyTuning + + Provisionable Default = 0x0 + + 1 = Enable external VDD power supply tuning + 0 = Disable external VDD power supply tuning is disabled + + + Notes: + This bit controls whether the PHY attempts to tune the external VDD power supply via the SMBus. This bit is only operational if the external supply is present. (See 1E.C472.6) */ + unsigned int enableVddPowerSupplyTuning : 1; /* 1E.C472.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable external VDD power supply tuning + 0 = Disable external VDD power supply tuning is disabled + */ + unsigned int reserved1 : 7; + /*! \brief 1E.C472.6 R/WPD Tunable External VDD Power Supply Present + AQ_GlobalReservedProvisioning_HHD.u2.bits_2.tunableExternalVddPowerSupplyPresent + + Provisionable Default = 0x0 + + 1 = Tunable external VDD power supply present + 0 = No tunable external VDD power supply present + + + Notes: + This bit must be set if tuning of external power supply is desired. */ + unsigned int tunableExternalVddPowerSupplyPresent : 1; /* 1E.C472.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Tunable external VDD power supply present + 0 = No tunable external VDD power supply present + */ + /*! \brief 1E.C472.5:2 R/WPD External VDD Change Request [3:0] + AQ_GlobalReservedProvisioning_HHD.u2.bits_2.externalVddChangeRequest + + Provisionable Default = 0x0 + + The amount of VDD change requested by firmware, in mV (2's complement value). + + */ + unsigned int externalVddChangeRequest : 4; /* 1E.C472.5:2 R/WPD Provisionable Default = 0x0 */ + /* The amount of VDD change requested by firmware, in mV (2's complement value). + */ + /*! \brief 1E.C472.1 R/WPDuP Enable XENPAK Register Space + AQ_GlobalReservedProvisioning_HHD.u2.bits_2.enableXenpakRegisterSpace + + Provisionable Default = 0x0 + + 1 = XENPAK register space enabled + 0 = XENPAK register space disabled + + */ + unsigned int enableXenpakRegisterSpace : 1; /* 1E.C472.1 R/WPDuP Provisionable Default = 0x0 */ + /* 1 = XENPAK register space enabled + 0 = XENPAK register space disabled + */ + /*! \brief 1E.C472.0 R/WPDuP Enable 5th Channel RFI Cancellation + AQ_GlobalReservedProvisioning_HHD.u2.bits_2.enable_5thChannelRfiCancellation + + Provisionable Default = 0x0 + + 1 = 5th channel and RFI cancellers operation enabled + 0 = 5th channel AFE is powered down, 5th channel digital is clock gated, RFI cancellers are disabled + + + Notes: + Note: The value of this bit at the time of Autonegotiation sets the local PHY behavior until the next time Autonegotiation occurs. */ + unsigned int enable_5thChannelRfiCancellation : 1; /* 1E.C472.0 R/WPDuP Provisionable Default = 0x0 */ + /* 1 = 5th channel and RFI cancellers operation enabled + 0 = 5th channel AFE is powered down, 5th channel digital is clock gated, RFI cancellers are disabled + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved0 : 5; + /*! \brief 1E.C473.A:8 R/WPD Rate Transition Request [2:0] + AQ_GlobalReservedProvisioning_HHD.u3.bits_3.rateTransitionRequest + + Provisionable Default = 0x0 + + 0 = No Transition + 1 = Reserved + 2 = Reserved + 3 = Retrain at 10G + 4 = Retrain at 5G + 5 = Retrain at 2.5G + 6 = Retrain at 1G + 7 = Reserved + + */ + unsigned int rateTransitionRequest : 3; /* 1E.C473.A:8 R/WPD Provisionable Default = 0x0 */ + /* 0 = No Transition + 1 = Reserved + 2 = Reserved + 3 = Retrain at 10G + 4 = Retrain at 5G + 5 = Retrain at 2.5G + 6 = Retrain at 1G + 7 = Reserved + */ + /*! \brief 1E.C473.7:0 R/WPD Training SNR [7:0] + AQ_GlobalReservedProvisioning_HHD.u3.bits_3.trainingSNR + + Provisionable Default = 0x00 + + SNR during 10G training on the worst channel. SNR is in steps of 0.1dB + + + Notes: + The SNR margin that is enjoyed by the worst channel, over and above the minimum SNR required to operate at a BER of 10-12. It is reported with 0.1 dB of resolution to an accuracy of 0.5 dB within the range of -12.7 dB to 12.7 dB. The number is in offset binary, with 0.0 dB represented by 0x8000. */ + unsigned int trainingSNR : 8; /* 1E.C473.7:0 R/WPD Provisionable Default = 0x00 */ + /* SNR during 10G training on the worst channel. SNR is in steps of 0.1dB + */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C474.F:1 R/WPD Reserved Provisioning 5 [F:1] + AQ_GlobalReservedProvisioning_HHD.u4.bits_4.reservedProvisioning_5 + + Provisionable Default = 0x0000 + + Reserved for future use + + */ + unsigned int reservedProvisioning_5 : 15; /* 1E.C474.F:1 R/WPD Provisionable Default = 0x0000 */ + /* Reserved for future use + */ + /*! \brief 1E.C474.0 R/W NVR Daisy Chain Kickstart + AQ_GlobalReservedProvisioning_HHD.u4.bits_4.nvrDaisyChainKickstart + + Default = 0x0 + + 1 = Kickstart the Daisy Chain + + + Notes: + When in daisy chain master mode, the PHY0 can kickstart the daisy chain. The kickstart will not reload the IRAM/DRAM or reset the uP for PHY0. It will just read the FLASH and transfer the FLASH data to the daisy chain. */ + unsigned int nvrDaisyChainKickstart : 1; /* 1E.C474.0 R/W Default = 0x0 */ + /* 1 = Kickstart the Daisy Chain + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved0 : 2; + /*! \brief 1E.C475.D R/WPD Smart Power-Down Status + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.smartPower_downStatus + + Provisionable Default = 0x0 + + 1 = Smart Power-Down Active + 0 = Smart Power-Down Inactive + + */ + unsigned int smartPower_downStatus : 1; /* 1E.C475.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Smart Power-Down Active + 0 = Smart Power-Down Inactive + */ + /*! \brief 1E.C475.C R/WPD Reserved Provisioning 6 + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.reservedProvisioning_6 + + Provisionable Default = 0x0 + + Internal reserved - do not modify + + */ + unsigned int reservedProvisioning_6 : 1; /* 1E.C475.C R/WPD Provisionable Default = 0x0 */ + /* Internal reserved - do not modify + */ + /*! \brief 1E.C475.B R/WPD CFR LP Disable Timer + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrLpDisableTimer + + Provisionable Default = 0x0 + + 1 = Link partner requires cfr_disable timer + 0 = Link partner does not require cfr_disable timer + + */ + unsigned int cfrLpDisableTimer : 1; /* 1E.C475.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner requires cfr_disable timer + 0 = Link partner does not require cfr_disable timer + */ + /*! \brief 1E.C475.A R/WPD CFR LP Extended Maxwait + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrLpExtendedMaxwait + + Provisionable Default = 0x0 + + 1 = Link partner requires extended maxwait + 0 = Link partner does not require extended maxwait + + */ + unsigned int cfrLpExtendedMaxwait : 1; /* 1E.C475.A R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner requires extended maxwait + 0 = Link partner does not require extended maxwait + */ + /*! \brief 1E.C475.9 R/WPD CFR LP THP + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrLpTHP + + Provisionable Default = 0x0 + + 1 = Link partner requires local PHY to enable THP + 0 = Link partner does not require local PHY to enable THP + + */ + unsigned int cfrLpTHP : 1; /* 1E.C475.9 R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner requires local PHY to enable THP + 0 = Link partner does not require local PHY to enable THP + */ + /*! \brief 1E.C475.8 R/WPD CFR LP Support + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrLpSupport + + Provisionable Default = 0x0 + + 1 = Link partner supports Cisco Fast Retrain + 0 = Link partner does support Cisco Fast Retrain + + */ + unsigned int cfrLpSupport : 1; /* 1E.C475.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner supports Cisco Fast Retrain + 0 = Link partner does support Cisco Fast Retrain + */ + /*! \brief 1E.C475.7 R/WPD CFR Disable Timer + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrDisableTimer + + Provisionable Default = 0x0 + + 1 = Local PHY requires cfr_disable timer + 0 = Local PHY does not require cfr_disable timer + + */ + unsigned int cfrDisableTimer : 1; /* 1E.C475.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY requires cfr_disable timer + 0 = Local PHY does not require cfr_disable timer + */ + /*! \brief 1E.C475.6 R/WPD CFR Extended Maxwait + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrExtendedMaxwait + + Provisionable Default = 0x0 + + 1 = Local PHY requires extended maxwait + 0 = Local PHY does not require extended maxwait + + */ + unsigned int cfrExtendedMaxwait : 1; /* 1E.C475.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY requires extended maxwait + 0 = Local PHY does not require extended maxwait + */ + /*! \brief 1E.C475.5 R/WPD CFR THP + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrTHP + + Provisionable Default = 0x0 + + 1 = Local PHY requires local PHY to enable THP + 0 = Local PHY does not require local PHY to enable THP + + */ + unsigned int cfrTHP : 1; /* 1E.C475.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY requires local PHY to enable THP + 0 = Local PHY does not require local PHY to enable THP + */ + /*! \brief 1E.C475.4 R/WPD CFR Support + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrSupport + + Provisionable Default = 0x0 + + 1 = Local PHY supports Cisco Fast Retrain + 0 = Local PHY does support Cisco Fast Retrain + + */ + unsigned int cfrSupport : 1; /* 1E.C475.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY supports Cisco Fast Retrain + 0 = Local PHY does support Cisco Fast Retrain + */ + /*! \brief 1E.C475.3 R/WPD Deadlock Avoidance Enable + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.deadlockAvoidanceEnable + + Provisionable Default = 0x0 + + 1 = SPD with deadlock avoidance: PHY transmits autonegotiation pulses (FLPs) at a slower rate (~ 1 FLP/ 100ms) than specified by autonegotiation standard (~1 FLP / 8.25ms). Receiver is active and able to detect the pulses. + 0 = SPD without deadlock avoidance: PHY transmitter is shut down, no autonegotiation pulses are sent on the line but the receiver is active and able to detect the pulses + + */ + unsigned int deadlockAvoidanceEnable : 1; /* 1E.C475.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = SPD with deadlock avoidance: PHY transmits autonegotiation pulses (FLPs) at a slower rate (~ 1 FLP/ 100ms) than specified by autonegotiation standard (~1 FLP / 8.25ms). Receiver is active and able to detect the pulses. + 0 = SPD without deadlock avoidance: PHY transmitter is shut down, no autonegotiation pulses are sent on the line but the receiver is active and able to detect the pulses + */ + /*! \brief 1E.C475.2 R/WPD Smart Power-Down Enable + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.smartPower_downEnable + + Provisionable Default = 0x0 + + 1 = Enable smart power down mode + 0 = Smart power-down mode disabled + + + Notes: + Smart power down (SPD) is the lowest power mode at which PHY is able to autonegotiate. SPD can be enabled with bit 1E.C475.2 */ + unsigned int smartPower_downEnable : 1; /* 1E.C475.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable smart power down mode + 0 = Smart power-down mode disabled + */ + unsigned int reserved1 : 2; + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Dummy union to fill space in the structure Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Dummy union to fill space in the structure Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_7; + uint16_t word_7; + } u7; + /*! \brief Union for bit and word level access of word 8 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C478.F R/WPD DTE Enable + AQ_GlobalReservedProvisioning_HHD.u8.bits_8.dteEnable + + Provisionable Default = 0x0 + + 1 = Enable DTE + 0 = Disable DTE + + */ + unsigned int dteEnable : 1; /* 1E.C478.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable DTE + 0 = Disable DTE + */ + /*! \brief 1E.C478.E:B R/WPD DTE Drop Reporting Timer [3:0] + AQ_GlobalReservedProvisioning_HHD.u8.bits_8.dteDropReportingTimer + + Provisionable Default = 0x0 + + Number of seconds between loss of link partner filter and assertion of no-power-needed state, in 5 second increments (e.g. 0x4 = 20 seconds). + + + Notes: + These bits are used to set how long the PHY waits after it no longer detects the link partner filter before declaring that power is not needed. */ + unsigned int dteDropReportingTimer : 4; /* 1E.C478.E:B R/WPD Provisionable Default = 0x0 */ + /* Number of seconds between loss of link partner filter and assertion of no-power-needed state, in 5 second increments (e.g. 0x4 = 20 seconds). + */ + /*! \brief 1E.C478.A:0 R/WPD Reserved Provisioning 9 [A:0] + AQ_GlobalReservedProvisioning_HHD.u8.bits_8.reservedProvisioning_9 + + Provisionable Default = 0x000 + + Reserved for future use + + */ + unsigned int reservedProvisioning_9 : 11; /* 1E.C478.A:0 R/WPD Provisionable Default = 0x000 */ + /* Reserved for future use + */ + } bits_8; + uint16_t word_8; + } u8; + /*! \brief Union for bit and word level access of word 9 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C479.F R/WPD Power Up Stall + AQ_GlobalReservedProvisioning_HHD.u9.bits_9.powerUpStall + + Provisionable Default = 0x0 + + 1 = Stall FW at Power Up + 0 = Unstall the FW + + + Notes: + This bit needs to be provisioned in Power Up Init for firmware to stall. */ + unsigned int powerUpStall : 1; /* 1E.C479.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Stall FW at Power Up + 0 = Unstall the FW + */ + /*! \brief 1E.C479.E:0 R/WPD Reserved Provisioning 10 [E:0] + AQ_GlobalReservedProvisioning_HHD.u9.bits_9.reservedProvisioning_10 + + Provisionable Default = 0x0000 + + Reserved for future use + + */ + unsigned int reservedProvisioning_10 : 15; /* 1E.C479.E:0 R/WPD Provisionable Default = 0x0000 */ + /* Reserved for future use + */ + } bits_9; + uint16_t word_9; + } u9; + /*! \brief Union for bit and word level access of word 10 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C47A.F:B R/WPD Loopback Control [4:0] + AQ_GlobalReservedProvisioning_HHD.u10.bits_10.loopbackControl + + Provisionable Default = 0x00 + + 0x00 = No loopback + 0x01 = System Interface - System Loopback + 0x02 = System Interface - System Loopback with Passthrough + 0x03 = System Interface - Network Loopback + 0x04 = System Interface - Network Loopback with Passthrough + 0x05 = System Interface - Network Loopback with Passthrough and Merge + 0x06 = System Interface - Peer-to-peer loopback + 0x07 - 0x08 = Reserved + 0x09 = Network Interface - System Loopback + 0x0A = Network Interface - System Loopback with Passthrough + 0x0B = Network Interface - Network Loopback + 0x0C = Network Interface - Network Loopback with Passthrough + 0x0D = Network Interface - Peer-to-peer loopback + 0x0E - 0x0F = Reserved + 0x10 = Cross-connect System Loopback + 0x11 = Cross-connect Network Loopback + 0x12 - 0x13 = Reserved + 0x14 = Network Interface - System Loopback via Loopback Plug + 0x15 - 0x1F = Reserved + + + Notes: + These bits, in conjunction with the chip configuration and the rate (Bits 1:0), select the loopback to configure for the chip. Setting one of these loopbacks provisions the chip for the specified loopback. Upon clearing the loopback, the chip returns to it's configuration prior to entering loopback (irregardless of whether other loopbacks were selected after the initial loopback). + + NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F. + + The controls in this register are identical to, and mirrored with, the controls in 4.C444. + */ + unsigned int loopbackControl : 5; /* 1E.C47A.F:B R/WPD Provisionable Default = 0x00 */ + /* 0x00 = No loopback + 0x01 = System Interface - System Loopback + 0x02 = System Interface - System Loopback with Passthrough + 0x03 = System Interface - Network Loopback + 0x04 = System Interface - Network Loopback with Passthrough + 0x05 = System Interface - Network Loopback with Passthrough and Merge + 0x06 = System Interface - Peer-to-peer loopback + 0x07 - 0x08 = Reserved + 0x09 = Network Interface - System Loopback + 0x0A = Network Interface - System Loopback with Passthrough + 0x0B = Network Interface - Network Loopback + 0x0C = Network Interface - Network Loopback with Passthrough + 0x0D = Network Interface - Peer-to-peer loopback + 0x0E - 0x0F = Reserved + 0x10 = Cross-connect System Loopback + 0x11 = Cross-connect Network Loopback + 0x12 - 0x13 = Reserved + 0x14 = Network Interface - System Loopback via Loopback Plug + 0x15 - 0x1F = Reserved + */ + /*! \brief 1E.C47A.A:6 R/WPD Reserved Provisioning 11 [4:0] + AQ_GlobalReservedProvisioning_HHD.u10.bits_10.reservedProvisioning_11 + + Provisionable Default = 0x00 + + Reserved for future use + + */ + unsigned int reservedProvisioning_11 : 5; /* 1E.C47A.A:6 R/WPD Provisionable Default = 0x00 */ + /* Reserved for future use + */ + /*! \brief 1E.C47A.5 R/WPD MDI Packet Generation + AQ_GlobalReservedProvisioning_HHD.u10.bits_10.mdiPacketGeneration + + Provisionable Default = 0x0 + + 1 = CRPAT packet generation out MDI interface + 0 = No CRPAT packet generation out MDI interface + + + Notes: + Selecting this mode of operation causes the CRPAT packet generator in the PHY to output on the MDI interface at the selected rate. + + NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F + + The controls in this register are identical to, and mirrored with, the controls in 4.C444. */ + unsigned int mdiPacketGeneration : 1; /* 1E.C47A.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = CRPAT packet generation out MDI interface + 0 = No CRPAT packet generation out MDI interface + */ + /*! \brief 1E.C47A.4 R/WPD Look-Aside Port Packet Generation + AQ_GlobalReservedProvisioning_HHD.u10.bits_10.look_asidePortPacketGeneration + + Provisionable Default = 0x0 + + 1 = CRPAT packet generation out 10G look-aside interface (KR0) + 0 = No CRPAT packet generation out 10G look-aside interface (KR0) + + + Notes: + Selecting this mode of operation causes the CRPAT packet generator in the PHY to output on KR0. + + NOTE!! This only functions if KR1 (SERDES2) is selected as the system interface in (4.C441.F:E). + + NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F + + The controls in this register are identical to, and mirrored with, the controls in 4.C444. */ + unsigned int look_asidePortPacketGeneration : 1; /* 1E.C47A.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = CRPAT packet generation out 10G look-aside interface (KR0) + 0 = No CRPAT packet generation out 10G look-aside interface (KR0) + */ + /*! \brief 1E.C47A.3 R/WPD System I/F Packet Generation + AQ_GlobalReservedProvisioning_HHD.u10.bits_10.systemI_fPacketGeneration + + Provisionable Default = 0x0 + + 1 = CRPAT packet generation out 10G system interface + 0 = No CRPAT packet generation out 10G system interface + + + Notes: + Selecting this mode of operation causes the CRPAT packet generator in the PHY to output CRPAT packets on the selected 10G system interface (4.C441.F:E) + + NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F + + The controls in this register are identical to, and mirrored with, the controls in 4.C444. */ + unsigned int systemI_fPacketGeneration : 1; /* 1E.C47A.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = CRPAT packet generation out 10G system interface + 0 = No CRPAT packet generation out 10G system interface + */ + /*! \brief 1E.C47A.2 R/WPD Reserved Provisioning 11a + AQ_GlobalReservedProvisioning_HHD.u10.bits_10.reservedProvisioning_11a + + Provisionable Default = 0x0 + + Reserved for future use + + */ + unsigned int reservedProvisioning_11a : 1; /* 1E.C47A.2 R/WPD Provisionable Default = 0x0 */ + /* Reserved for future use + */ + /*! \brief 1E.C47A.1:0 R/WPD Rate [1:0] + AQ_GlobalReservedProvisioning_HHD.u10.bits_10.rate + + Provisionable Default = 0x0 + + 0x3 = 10G + 0x2 = 1G + 0x1 = 100M + 0x0 = reserved + + + Notes: + These bits select the rate for the loopback and packet generation. SERDES configuration, as well autonegotiation is controlled accordingly when a loopback is selected. For instance, if 100M system loopback on the network interface is selected, SGMII on the system interface is enabled to connect at 100M, and if passthrough is enabled 100BASE-TX will be the only advertised rate and will force a re-autonegotiation if not already connected at 100M. + + NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F + + The controls in this register are identical to, and mirrored with, the controls in 4.C444. */ + unsigned int rate : 2; /* 1E.C47A.1:0 R/WPD Provisionable Default = 0x0 */ + /* 0x3 = 10G + 0x2 = 1G + 0x1 = 100M + 0x0 = reserved + */ + } bits_10; + uint16_t word_10; + } u10; + /*! \brief Union for bit and word level access of word 11 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C47B.F:2 R/WPD Reserved Provisioning 12 [D:0] + AQ_GlobalReservedProvisioning_HHD.u11.bits_11.reservedProvisioning_12 + + Provisionable Default = 0x0000 + + Reserved for future use + + */ + unsigned int reservedProvisioning_12 : 14; /* 1E.C47B.F:2 R/WPD Provisionable Default = 0x0000 */ + /* Reserved for future use + */ + /*! \brief 1E.C47B.1 R/WPD Enable MACSec + AQ_GlobalReservedProvisioning_HHD.u11.bits_11.enableMacsec + + Provisionable Default = 0x0 + + 1 = MACSec functionality is enabled + 0 = MACSec functionality is disabled + + + Notes: + If this bit is 1, the PTP/SEC block will be included in the data path, regardless of operating mode. */ + unsigned int enableMacsec : 1; /* 1E.C47B.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = MACSec functionality is enabled + 0 = MACSec functionality is disabled + */ + /*! \brief 1E.C47B.0 R/WPD Enable PTP + AQ_GlobalReservedProvisioning_HHD.u11.bits_11.enablePtp + + Provisionable Default = 0x0 + + 1 = PTP functionality is enabled + 0 = PTP functionality is disabled + + + Notes: + If this bit is 1, the PTP/SEC block will be included in the data path, regardless of operating mode. */ + unsigned int enablePtp : 1; /* 1E.C47B.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = PTP functionality is enabled + 0 = PTP functionality is disabled + */ + } bits_11; + uint16_t word_11; + } u11; +} AQ_GlobalReservedProvisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief PIF Mailbox Control: 1E.C47C */ +/* PIF Mailbox Control: 1E.C47C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of PIF Mailbox Control */ + union + { + struct + { + /*! \brief 1E.C47C.F:0 R/WPDuP PIF Mailbox Address [F:0] + AQ_PifMailboxControl_HHD.u0.bits_0.pifMailboxAddress + + Provisionable Default = 0x0000 + + The least 16 bits of the PIF address to read or write. + + */ + unsigned int pifMailboxAddress : 16; /* 1E.C47C.F:0 R/WPDuP Provisionable Default = 0x0000 */ + /* The least 16 bits of the PIF address to read or write. + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of PIF Mailbox Control */ + union + { + struct + { + /*! \brief 1E.C47D.F:0 R/WPDuP PIF Mailbox Data [F:0] + AQ_PifMailboxControl_HHD.u1.bits_1.pifMailboxData + + Provisionable Default = 0x0000 + + The data to be written, or that had been read. + + */ + unsigned int pifMailboxData : 16; /* 1E.C47D.F:0 R/WPDuP Provisionable Default = 0x0000 */ + /* The data to be written, or that had been read. + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of PIF Mailbox Control */ + union + { + struct + { + /*! \brief 1E.C47E.F:C R/WPD Reserved PIF Mailbox Control 3 [3:0] + AQ_PifMailboxControl_HHD.u2.bits_2.reservedPifMailboxControl_3 + + Provisionable Default = 0x0 + + Reserved for future use + + */ + unsigned int reservedPifMailboxControl_3 : 4; /* 1E.C47E.F:C R/WPD Provisionable Default = 0x0 */ + /* Reserved for future use + */ + /*! \brief 1E.C47E.B:8 R/WPDuP PIF Mailbox Command Type [3:0] + AQ_PifMailboxControl_HHD.u2.bits_2.pifMailboxCommandType + + Provisionable Default = 0x0 + + 0 = No Action + 1 = Read + 2 = Write + + + Notes: + System SW writes non-zero value to start a PIF command. */ + unsigned int pifMailboxCommandType : 4; /* 1E.C47E.B:8 R/WPDuP Provisionable Default = 0x0 */ + /* 0 = No Action + 1 = Read + 2 = Write + */ + /*! \brief 1E.C47E.7:0 R/WPDuP PIF Mailbox MMD [7:0] + AQ_PifMailboxControl_HHD.u2.bits_2.pifMailboxMMD + + Provisionable Default = 0x00 + + MMD (upper 8 bits) of the PID address to read or write. + + */ + unsigned int pifMailboxMMD : 8; /* 1E.C47E.7:0 R/WPDuP Provisionable Default = 0x00 */ + /* MMD (upper 8 bits) of the PID address to read or write. + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of PIF Mailbox Control */ + union + { + struct + { + /*! \brief 1E.C47F.F:4 R/WPD Reserved PIF Mailbox Control 4 [B:0] + AQ_PifMailboxControl_HHD.u3.bits_3.reservedPifMailboxControl_4 + + Provisionable Default = 0x000 + + Reserved for future use + + */ + unsigned int reservedPifMailboxControl_4 : 12; /* 1E.C47F.F:4 R/WPD Provisionable Default = 0x000 */ + /* Reserved for future use + */ + /*! \brief 1E.C47F.3:0 R/WPDuP PIF Mailbox Command Status [3:0] + AQ_PifMailboxControl_HHD.u3.bits_3.pifMailboxCommandStatus + + Provisionable Default = 0x0 + + 0 = Idle + 1 = Command completed + 2 = Command did not complete + + + Notes: + System SW should write 0 before writing Command Type to clear completion status */ + unsigned int pifMailboxCommandStatus : 4; /* 1E.C47F.3:0 R/WPDuP Provisionable Default = 0x0 */ + /* 0 = Idle + 1 = Command completed + 2 = Command did not complete + */ + } bits_3; + uint16_t word_3; + } u3; +} AQ_PifMailboxControl_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global SMBus 0 Provisioning: 1E.C485 */ +/* Global SMBus 0 Provisioning: 1E.C485 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global SMBus 0 Provisioning */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.C485.7:1 R/W SMB 0 Slave Address [7:1] + AQ_GlobalSmbus_0Provisioning_HHD.u0.bits_0.smb_0SlaveAddress + + Default = 0x00 + + SMB slave address configuration + + */ + unsigned int smb_0SlaveAddress : 7; /* 1E.C485.7:1 R/W Default = 0x00 */ + /* SMB slave address configuration + */ + unsigned int reserved1 : 1; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalSmbus_0Provisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global SMBus 1 Provisioning: 1E.C495 */ +/* Global SMBus 1 Provisioning: 1E.C495 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global SMBus 1 Provisioning */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.C495.7:1 R/W SMB 1 Slave Address [7:1] + AQ_GlobalSmbus_1Provisioning_HHD.u0.bits_0.smb_1SlaveAddress + + Default = 0x00 + + SMB slave address configuration + + */ + unsigned int smb_1SlaveAddress : 7; /* 1E.C495.7:1 R/W Default = 0x00 */ + /* SMB slave address configuration + */ + unsigned int reserved1 : 1; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalSmbus_1Provisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global EEE Provisioning: 1E.C4A0 */ +/* Global EEE Provisioning: 1E.C4A0 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global EEE Provisioning */ + union + { + struct + { + unsigned int reserved0 : 15; + /*! \brief 1E.C4A0.0 R/WPD EEE Mode + AQ_GlobalEeeProvisioning_HHD.u0.bits_0.eeeMode + + Provisionable Default = 0x0 + + 1 = EEE mode of operation + + + Notes: + EEE mode of operation (0=disable, 1=enable, default:0) */ + unsigned int eeeMode : 1; /* 1E.C4A0.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = EEE mode of operation + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalEeeProvisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Cable Diagnostic Status: 1E.C800 */ +/* Global Cable Diagnostic Status: 1E.C800 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Cable Diagnostic Status */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.C800.E:C RO Pair A Status [2:0] + AQ_GlobalCableDiagnosticStatus_HHD.u0.bits_0.pairAStatus + + + + [F:D] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair D + 010= Connected to Pair C + 001= Connected to Pair B + 000= OK + + Notes: + This register summarizes the worst impairment on Pair A. */ + unsigned int pairAStatus : 3; /* 1E.C800.E:C RO */ + /* [F:D] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair D + 010= Connected to Pair C + 001= Connected to Pair B + 000= OK */ + unsigned int reserved1 : 1; + /*! \brief 1E.C800.A:8 RO Pair B Status [2:0] + AQ_GlobalCableDiagnosticStatus_HHD.u0.bits_0.pairBStatus + + + + [C:A] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair A + 010= Connected to Pair D + 001= Connected to Pair C + 000= OK + + Notes: + This register summarizes the worst impairment on Pair B. */ + unsigned int pairBStatus : 3; /* 1E.C800.A:8 RO */ + /* [C:A] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair A + 010= Connected to Pair D + 001= Connected to Pair C + 000= OK */ + unsigned int reserved2 : 1; + /*! \brief 1E.C800.6:4 RO Pair C Status [2:0] + AQ_GlobalCableDiagnosticStatus_HHD.u0.bits_0.pairCStatus + + + + [9:7] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair B + 010= Connected to Pair A + 001= Connected to Pair D + 000= OK + + Notes: + This register summarizes the worst impairment on Pair C. */ + unsigned int pairCStatus : 3; /* 1E.C800.6:4 RO */ + /* [9:7] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair B + 010= Connected to Pair A + 001= Connected to Pair D + 000= OK */ + unsigned int reserved3 : 1; + /*! \brief 1E.C800.2:0 RO Pair D Status [2:0] + AQ_GlobalCableDiagnosticStatus_HHD.u0.bits_0.pairDStatus + + + + [6:4] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair C + 010= Connected to Pair B + 001= Connected to Pair A + 000= OK + + Notes: + This register summarizes the worst impairment on Pair D. */ + unsigned int pairDStatus : 3; /* 1E.C800.2:0 RO */ + /* [6:4] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair C + 010= Connected to Pair B + 001= Connected to Pair A + 000= OK */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C801.F:8 RO Pair A Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u1.bits_1.pairAReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair A + + Notes: + The distance to this reflection is given in See Global Reserved Status 1: Address 1E.C870 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairAReflection_1 : 8; /* 1E.C801.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair A */ + /*! \brief 1E.C801.7:0 RO Pair A Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u1.bits_1.pairAReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair A + + Notes: + The distance to this reflection is given in See Global Reserved Status 1: Address 1E.C870 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairAReflection_2 : 8; /* 1E.C801.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair A */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C802.F:0 RO Impulse Response MSW [F:0] + AQ_GlobalCableDiagnosticStatus_HHD.u2.bits_2.impulseResponseMSW + + + + The MSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type in 1E.C470.E:D + + Notes: + See 1E.C470 for more information */ + unsigned int impulseResponseMSW : 16; /* 1E.C802.F:0 RO */ + /* The MSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type in 1E.C470.E:D */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C803.F:8 RO Pair B Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u3.bits_3.pairBReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair B + + Notes: + The distance to this reflection is given in See Global Reserved Status 2: Address 1E.C871 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairBReflection_1 : 8; /* 1E.C803.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair B */ + /*! \brief 1E.C803.7:0 RO Pair B Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u3.bits_3.pairBReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair B + + Notes: + The distance to this reflection is given in See Global Reserved Status 2: Address 1E.C871 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairBReflection_2 : 8; /* 1E.C803.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair B */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C804.F:0 RO Impulse Response LSW [F:0] + AQ_GlobalCableDiagnosticStatus_HHD.u4.bits_4.impulseResponseLSW + + + + The LSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type specified in 1E.C470.E:D + + Notes: + See 1E.C470 for more information */ + unsigned int impulseResponseLSW : 16; /* 1E.C804.F:0 RO */ + /* The LSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type specified in 1E.C470.E:D */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C805.F:8 RO Pair C Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u5.bits_5.pairCReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair C + + Notes: + The distance to this reflection is given in See Global Reserved Status 3: Address 1E.C872 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairCReflection_1 : 8; /* 1E.C805.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair C */ + /*! \brief 1E.C805.7:0 RO Pair C Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u5.bits_5.pairCReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair C + + Notes: + The distance to this reflection is given in See Global Reserved Status 3: Address 1E.C872 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairCReflection_2 : 8; /* 1E.C805.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair C */ + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C806.F:0 RO Reserved 1 [F:0] + AQ_GlobalCableDiagnosticStatus_HHD.u6.bits_6.reserved_1 + + + + Reserved for future use + */ + unsigned int reserved_1 : 16; /* 1E.C806.F:0 RO */ + /* Reserved for future use */ + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C807.F:8 RO Pair D Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u7.bits_7.pairDReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair D + + Notes: + The distance to this reflection is given in See Global Reserved Status 4: Address 1E.C873 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairDReflection_1 : 8; /* 1E.C807.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair D */ + /*! \brief 1E.C807.7:0 RO Pair D Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u7.bits_7.pairDReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair D + + Notes: + The distance to this reflection is given in See Global Reserved Status 4: Address 1E.C873 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairDReflection_2 : 8; /* 1E.C807.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair D */ + } bits_7; + uint16_t word_7; + } u7; +} AQ_GlobalCableDiagnosticStatus_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Thermal Status: 1E.C820 */ +/* Global Thermal Status: 1E.C820 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Thermal Status */ + union + { + struct + { + /*! \brief 1E.C820.F:0 RO Temperature [F:0] + AQ_GlobalThermalStatus_HHD.u0.bits_0.temperature + + + + [F:0] of temperature + + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 70 degreesC. This is a mirror of the XENPAK register 1.A060 - 1.A061. The mirror is performed in H/W. */ + unsigned int temperature : 16; /* 1E.C820.F:0 RO */ + /* [F:0] of temperature + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Thermal Status */ + union + { + struct + { + unsigned int reserved0 : 15; + /*! \brief 1E.C821.0 RO Temperature Ready + AQ_GlobalThermalStatus_HHD.u1.bits_1.temperatureReady + + + + 1 = Temperature measurement is valid + + + Notes: + This is a mirror of the XENPAK register 1.A06E. */ + unsigned int temperatureReady : 1; /* 1E.C821.0 RO */ + /* 1 = Temperature measurement is valid + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalThermalStatus_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global General Status: 1E.C830 */ +/* Global General Status: 1E.C830 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global General Status */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.C830.E RO High Temperature Failure State + AQ_GlobalGeneralStatus_HHD.u0.bits_0.highTemperatureFailureState + + + + 1 = High temperature failure threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A070.7 register. + + */ + unsigned int highTemperatureFailureState : 1; /* 1E.C830.E RO */ + /* 1 = High temperature failure threshold has been exceeded */ + /*! \brief 1E.C830.D RO Low Temperature Failure State + AQ_GlobalGeneralStatus_HHD.u0.bits_0.lowTemperatureFailureState + + + + 1 = Low temperature failure threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A070.6 register. + + */ + unsigned int lowTemperatureFailureState : 1; /* 1E.C830.D RO */ + /* 1 = Low temperature failure threshold has been exceeded */ + /*! \brief 1E.C830.C RO High Temperature Warning State + AQ_GlobalGeneralStatus_HHD.u0.bits_0.highTemperatureWarningState + + + + 1 = High temperature warning threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A074.7 register. + + */ + unsigned int highTemperatureWarningState : 1; /* 1E.C830.C RO */ + /* 1 = High temperature warning threshold has been exceeded */ + /*! \brief 1E.C830.B RO Low Temperature Warning State + AQ_GlobalGeneralStatus_HHD.u0.bits_0.lowTemperatureWarningState + + + + 1 = Low temperature warning threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A074.6 register. + + */ + unsigned int lowTemperatureWarningState : 1; /* 1E.C830.B RO */ + /* 1 = Low temperature warning threshold has been exceeded */ + unsigned int reserved1 : 11; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global General Status */ + union + { + struct + { + /*! \brief 1E.C831.F RO Processor Intensive MDIO Operation In- Progress + AQ_GlobalGeneralStatus_HHD.u1.bits_1.processorIntensiveMdioOperationIn_Progress + + + + 1 = PHY microprocessor is busy with a processor-intensive MDIO operation + 0 = Processor-intensive MDIO operation completed + + + Notes: + This bit should may be used with certain processor-intensive MDIO commands (such as Loopbacks, Test Modes, Low power modes, Tx-Disable, Restart autonegotiation, Cable Diagnostics, etc.) that take longer than an MDIO cycle to complete. Upon receiving an MDIO command that involves the PHY's microprocessor, this bit is set, and when the command is completed, this bit is cleared. + + NOTE!!! This bit should be checked only after 1 ms of issuing a processor-intensive MDIO operation. + + The list of operations that set this bit are as follows: + + 1.0.0, PMA Loopback + 1.0.B, Low power mode + 1.9.4:0, Tx Disable + 1.84, 10G Test modes + 1.8000.5, XENPAK Control + 1.9000, XENPAK Rx Fault Enable + 1.9002, XENPAK Alarm Enable + 1.E400.F, External loopback + 3.0.B, Low power mode + 3.0.E, System PCS loopback + 3.C471.5, PRBS Test + 3.C471.6, PRBS Test + 3.E471.5, PRBS Test + 3.E471.6, PRBS Test + 4.0.B, Low power mode + 4.0.E, PHY-XS network loopback + 4.C440, Output clock control, Load SERDES parameters + 4.F802.E, System loopback + 4.C444.F:B, Loopback Control + 4.C444.4:2, Packet generation + 4.C445.C, SERDES calibration + 7.0.9, Restart autonegotiation + 1D.C280, 1G/100M Network loopback + 1D.C500, 1G System loopback + 1D.C501, 1G / 100M Test modes + 1E.C470.4, Cable diagnostics + 1E.C47A.F:B, Loopback Control + 1E.C47A.4:2, Packet generation */ + unsigned int processorIntensiveMdioOperationIn_Progress : 1; /* 1E.C831.F RO */ + /* 1 = PHY microprocessor is busy with a processor-intensive MDIO operation + 0 = Processor-intensive MDIO operation completed + */ + unsigned int reserved0 : 15; + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalGeneralStatus_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Pin Status: 1E.C840 */ +/* Global Pin Status: 1E.C840 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Pin Status */ + union + { + struct + { + unsigned int reserved0 : 1; + unsigned int reserved1 : 1; + /*! \brief 1E.C840.D RO DC_MASTER_N + AQ_GlobalPinStatus_HHD.u0.bits_0.dcMasterN + + + + Value of DC_MASTER_N pin: + + 0x1 = PHY Slave Daisy Chain Boot + 0x0 = PHY Master Daisy Chain Boot from FLASH + */ + unsigned int dcMasterN : 1; /* 1E.C840.D RO */ + /* Value of DC_MASTER_N pin: + + 0x1 = PHY Slave Daisy Chain Boot + 0x0 = PHY Master Daisy Chain Boot from FLASH */ + unsigned int reserved2 : 3; + /*! \brief 1E.C840.9 RO Package Connectivity + AQ_GlobalPinStatus_HHD.u0.bits_0.packageConnectivity + + + + Value of the package connection pin + + */ + unsigned int packageConnectivity : 1; /* 1E.C840.9 RO */ + /* Value of the package connection pin + */ + unsigned int reserved3 : 1; + /*! \brief 1E.C840.7 RO Tx Enable + AQ_GlobalPinStatus_HHD.u0.bits_0.txEnable + + + + Current Value of Tx Enable pin + + + Notes: + 0 = Disable Transmitter */ + unsigned int txEnable : 1; /* 1E.C840.7 RO */ + /* Current Value of Tx Enable pin + */ + unsigned int reserved4 : 1; + /*! \brief 1E.C840.5:0 RO LED Pullup State [5:0] + AQ_GlobalPinStatus_HHD.u0.bits_0.ledPullupState + + + + 1 = LED output pin is pulled high + 0 = LED output pin is pulled low + + */ + unsigned int ledPullupState : 6; /* 1E.C840.5:0 RO */ + /* 1 = LED output pin is pulled high + 0 = LED output pin is pulled low + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalPinStatus_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Daisy Chain Status: 1E.C842 */ +/* Global Daisy Chain Status: 1E.C842 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Daisy Chain Status */ + union + { + struct + { + /*! \brief 1E.C842.F:0 RO Rx Daisy Chain Calculated CRC [F:0] + AQ_GlobalDaisyChainStatus_HHD.u0.bits_0.rxDaisyChainCalculatedCrc + + + + Rx Daisy Chain Calculated CRC + + + Notes: + This is the calculated daisy chain CRC. */ + unsigned int rxDaisyChainCalculatedCrc : 16; /* 1E.C842.F:0 RO */ + /* Rx Daisy Chain Calculated CRC + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalDaisyChainStatus_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Fault Message: 1E.C850 */ +/* Global Fault Message: 1E.C850 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Fault Message */ + union + { + struct + { + /*! \brief 1E.C850.F:0 RO Message [F:0] + AQ_GlobalFaultMessage_HHD.u0.bits_0.message + + + + Error code describing fault + + Notes: + Code 0x8001: Firmware not compatible with chip architecture. This fault occurs when firmware compiled for a different microprocessor core is loaded. + Code 0x8002: VCO calibration failed. This occurs when the main PLLs on chip fail to lock: this is not possible to trigger. + Code 0x8003: XAUI calibration failed. This occurs when the XAUI PLLs fail to lock: this is not possible to trigger. + Code 0x8005: Unexpected device ID. This occurs if the device ID programmed into the internal E-Fuse registers in not valid: this is not possible to trigger. + Code 0x8006: Computed checksum does not match expected checksum. This occurs when the FLASH checksum check performed at boot time fails. This only occurs when the system boots from FLASH. + Code 0x8007: Detected a bit error in static memory. To trigger, corrupt one of the static regions. + Code 0xC001: Illegal Instruction exception. This occurs when the processor attempts to execute an illegal instruction. To trigger this, write an illegal instruction to program memory. It's possible that the bit error check will trigger before the illegal instruction is executed. + Code 0xC002 Instruction Fetch Error. Internal physical address or a data error during instruction fetch: this is not possible to trigger. + Code 0xC003 Load Store Error. Internal physical address or data error during load store operation: this is not possible to trigger.. + Code 0xC004 Privileged Instruction. Attempt to execute a privileged operation without sufficient privilege: this is not possible to trigger. + Code 0xC005 Unaligned Load or Store. Attempt to load or store data at an address which cannot be handled due to alignment: this is not possible to trigger. + Code 0xC006 Instruction fetch from prohibited space: this is not possible to trigger. + Code 0xC007 Data load from prohibited space: this is not possible to trigger. + Code 0xC008 Data store into prohibited space: this is not possible to trigger. */ + unsigned int message : 16; /* 1E.C850.F:0 RO */ + /* Error code describing fault */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalFaultMessage_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Cable Diagnostic Impedance: 1E.C880 */ +/* Global Cable Diagnostic Impedance: 1E.C880 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C880.F RO Reserved 1 + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.reserved_1 + + + + Reserved + + */ + unsigned int reserved_1 : 1; /* 1E.C880.F RO */ + /* Reserved + */ + /*! \brief 1E.C880.E:C RO Pair A Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.pairAReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_1 : 3; /* 1E.C880.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C880.B RO Reserved 2 + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.reserved_2 + + + + Reserved + + */ + unsigned int reserved_2 : 1; /* 1E.C880.B RO */ + /* Reserved + */ + /*! \brief 1E.C880.A:8 RO Pair A Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.pairAReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_2 : 3; /* 1E.C880.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C880.7 RO Reserved 3 + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.reserved_3 + + + + Reserved + + */ + unsigned int reserved_3 : 1; /* 1E.C880.7 RO */ + /* Reserved + */ + /*! \brief 1E.C880.6:4 RO Pair A Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.pairAReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_3 : 3; /* 1E.C880.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C880.3 RO Reserved 4 + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.reserved_4 + + + + Reserved + + */ + unsigned int reserved_4 : 1; /* 1E.C880.3 RO */ + /* Reserved + */ + /*! \brief 1E.C880.2:0 RO Pair A Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.pairAReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_4 : 3; /* 1E.C880.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C881.F RO Reserved 5 + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.reserved_5 + + + + Reserved + + */ + unsigned int reserved_5 : 1; /* 1E.C881.F RO */ + /* Reserved + */ + /*! \brief 1E.C881.E:C RO Pair B Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.pairBReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_1 : 3; /* 1E.C881.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C881.B RO Reserved 6 + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.reserved_6 + + + + Reserved + + */ + unsigned int reserved_6 : 1; /* 1E.C881.B RO */ + /* Reserved + */ + /*! \brief 1E.C881.A:8 RO Pair B Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.pairBReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_2 : 3; /* 1E.C881.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C881.7 RO Reserved 7 + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.reserved_7 + + + + Reserved + + */ + unsigned int reserved_7 : 1; /* 1E.C881.7 RO */ + /* Reserved + */ + /*! \brief 1E.C881.6:4 RO Pair B Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.pairBReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_3 : 3; /* 1E.C881.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C881.3 RO Reserved 8 + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.reserved_8 + + + + Reserved + + */ + unsigned int reserved_8 : 1; /* 1E.C881.3 RO */ + /* Reserved + */ + /*! \brief 1E.C881.2:0 RO Pair B Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.pairBReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_4 : 3; /* 1E.C881.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C882.F RO Reserved 9 + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.reserved_9 + + + + Reserved + + */ + unsigned int reserved_9 : 1; /* 1E.C882.F RO */ + /* Reserved + */ + /*! \brief 1E.C882.E:C RO Pair C Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.pairCReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_1 : 3; /* 1E.C882.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C882.B RO Reserved 10 + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.reserved_10 + + + + Reserved + + */ + unsigned int reserved_10 : 1; /* 1E.C882.B RO */ + /* Reserved + */ + /*! \brief 1E.C882.A:8 RO Pair C Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.pairCReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_2 : 3; /* 1E.C882.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C882.7 RO Reserved 11 + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.reserved_11 + + + + Reserved + + */ + unsigned int reserved_11 : 1; /* 1E.C882.7 RO */ + /* Reserved + */ + /*! \brief 1E.C882.6:4 RO Pair C Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.pairCReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_3 : 3; /* 1E.C882.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C882.3 RO Reserved 12 + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.reserved_12 + + + + Reserved + + */ + unsigned int reserved_12 : 1; /* 1E.C882.3 RO */ + /* Reserved + */ + /*! \brief 1E.C882.2:0 RO Pair C Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.pairCReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_4 : 3; /* 1E.C882.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C883.F RO Reserved 13 + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.reserved_13 + + + + Reserved + + */ + unsigned int reserved_13 : 1; /* 1E.C883.F RO */ + /* Reserved + */ + /*! \brief 1E.C883.E:C RO Pair D Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.pairDReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_1 : 3; /* 1E.C883.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C883.B RO Reserved 14 + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.reserved_14 + + + + Reserved + + */ + unsigned int reserved_14 : 1; /* 1E.C883.B RO */ + /* Reserved + */ + /*! \brief 1E.C883.A:8 RO Pair D Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.pairDReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_2 : 3; /* 1E.C883.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C883.7 RO Reserved 15 + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.reserved_15 + + + + Reserved + + */ + unsigned int reserved_15 : 1; /* 1E.C883.7 RO */ + /* Reserved + */ + /*! \brief 1E.C883.6:4 RO Pair D Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.pairDReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_3 : 3; /* 1E.C883.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C883.3 RO Reserved 16 + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.reserved_16 + + + + Reserved + + */ + unsigned int reserved_16 : 1; /* 1E.C883.3 RO */ + /* Reserved + */ + /*! \brief 1E.C883.2:0 RO Pair D Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.pairDReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_4 : 3; /* 1E.C883.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + } bits_3; + uint16_t word_3; + } u3; +} AQ_GlobalCableDiagnosticImpedance_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Status: 1E.C884 */ +/* Global Status: 1E.C884 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Status */ + union + { + struct + { + /*! \brief 1E.C884.F:8 RO Reserved Status 0 [7:0] + AQ_GlobalStatus_HHD.u0.bits_0.reservedStatus_0 + + + + Reserved + + */ + unsigned int reservedStatus_0 : 8; /* 1E.C884.F:8 RO */ + /* Reserved + */ + /*! \brief 1E.C884.7:0 RO Cable Length [7:0] + AQ_GlobalStatus_HHD.u0.bits_0.cableLength + + + + The estimated length of the cable in meters + + + Notes: + The length of the cable shown here is estimated from the cable diagnostic engine and should be accurate to +/-1m. */ + unsigned int cableLength : 8; /* 1E.C884.7:0 RO */ + /* The estimated length of the cable in meters + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStatus_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Reserved Status: 1E.C885 */ +/* Global Reserved Status: 1E.C885 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Reserved Status */ + union + { + struct + { + /*! \brief 1E.C885.F:A RO Nearly Seconds MSW[5:0] + AQ_GlobalReservedStatus_HHD.u0.bits_0.nearlySecondsMSW + + + + Bits 16 to 21 of the 22 bit "Nearly Seconds" uptime counter. + + + Notes: + The "Nearly Seconds" counter is incremented every 1024 milliseconds. */ + unsigned int nearlySecondsMSW : 6; /* 1E.C885.F:A RO */ + /* Bits 16 to 21 of the 22 bit "Nearly Seconds" uptime counter. + */ + /*! \brief 1E.C885.9:8 ROSPD XENPAK NVR Status [1:0] + AQ_GlobalReservedStatus_HHD.u0.bits_0.xenpakNvrStatus + + Provisionable Default = 0x0 + + Status of XENPAK NVR: + 0: NVR not enabled + 1: Last NVR operation succeeded + 2: Last NVR operation failed + 3: Reserved + + + Notes: + XENPAK register space is mirrored in NVR (SPI ROM). This register indicates the status of the last NVR operation. */ + unsigned int xenpakNvrStatus : 2; /* 1E.C885.9:8 ROSPD Provisionable Default = 0x0 */ + /* Status of XENPAK NVR: + 0: NVR not enabled + 1: Last NVR operation succeeded + 2: Last NVR operation failed + 3: Reserved + */ + /*! \brief 1E.C885.7:4 ROSPD Firmware Build ID [3:0] + AQ_GlobalReservedStatus_HHD.u0.bits_0.firmwareBuildID + + Provisionable Default = 0x0 + + Firmware Build ID + + + Notes: + Customers may receive multiple ROM images that differ only in their provisioning. This field is used to differentiate those images. This field is used in conjunction with the firmware major and minor revision numbers to uniquely identify ROM images. */ + unsigned int firmwareBuildID : 4; /* 1E.C885.7:4 ROSPD Provisionable Default = 0x0 */ + /* Firmware Build ID + */ + /*! \brief 1E.C885.3:0 ROSPD Provisioning ID [3:0] + AQ_GlobalReservedStatus_HHD.u0.bits_0.provisioningID + + Provisionable Default = 0x0 + + Provisioning ID + + + Notes: + Customers may receive multiple ROM images that differ only in their provisioning. This field is used to differentiate those images. This field is used in conjunction with the firmware major and minor revision numbers to uniquely identify ROM images. */ + unsigned int provisioningID : 4; /* 1E.C885.3:0 ROSPD Provisionable Default = 0x0 */ + /* Provisioning ID + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Reserved Status */ + union + { + struct + { + /*! \brief 1E.C886.F:0 RO Nearly Seconds LSW [F:0] + AQ_GlobalReservedStatus_HHD.u1.bits_1.nearlySecondsLSW + + + + Bits 0 to 15 of the 22 bit "Nearly Seconds" uptime counter + + + Notes: + The "Nearly Seconds" counter is incremented every 1024 milliseconds. */ + unsigned int nearlySecondsLSW : 16; /* 1E.C886.F:0 RO */ + /* Bits 0 to 15 of the 22 bit "Nearly Seconds" uptime counter + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Reserved Status */ + union + { + struct + { + /*! \brief 1E.C887.F ROS DTE Status + AQ_GlobalReservedStatus_HHD.u2.bits_2.dteStatus + + Default = 0x0 + + 1 = Need power + 0 = Don't need power + + */ + unsigned int dteStatus : 1; /* 1E.C887.F ROS Default = 0x0 */ + /* 1 = Need power + 0 = Don't need power + */ + /*! \brief 1E.C887.E ROS Power Up Stall Status + AQ_GlobalReservedStatus_HHD.u2.bits_2.powerUpStallStatus + + Default = 0x0 + + 1 = FW is stalled at power up + 0 = Firmware is unstalled + + */ + unsigned int powerUpStallStatus : 1; /* 1E.C887.E ROS Default = 0x0 */ + /* 1 = FW is stalled at power up + 0 = Firmware is unstalled + */ + /*! \brief 1E.C887.D:0 RO Reserved Status 3 [D:0] + AQ_GlobalReservedStatus_HHD.u2.bits_2.reservedStatus_3 + + + + Reserved for future use + + */ + unsigned int reservedStatus_3 : 14; /* 1E.C887.D:0 RO */ + /* Reserved for future use + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Reserved Status */ + union + { + struct + { + /*! \brief 1E.C888.F:B RO Loopback Status [4:0] + AQ_GlobalReservedStatus_HHD.u3.bits_3.loopbackStatus + + Default = 0x00 + + 0x00 = No loopback + 0x01 = System Interface - System Loopback + 0x02 = System Interface - System Loopback with Passthrough + 0x03 = System Interface - Network Loopback + 0x04 = System Interface - Network Loopback with Passthrough + 0x05 = System Interface - Network Loopback with Passthrough and Merge + 0x06 = System Interface - Peer-to-peer loopback + 0x07 - 0x08 = Reserved + 0x09 = Network Interface - System Loopback + 0x0A = Network Interface - System Loopback with Passthrough + 0x0B = Network Interface - Network Loopback + 0x0C = Network Interface - Network Loopback with Passthrough + 0x0D = Network Interface - Peer-to-peer loopback + 0x0E - 0x0F = Reserved + 0x10 = Cross-connect System Loopback + 0x11 = Cross-connect Network Loopback + 0x12 - 0x13 = Reserved + 0x14 = Network Interface - System Loopback via Loopback Plug + 0x15 - 0x1F = Reserved + + + Notes: + These bits, in conjunction with the chip configuration and the rate (Bits 1:0), report the selected loopback. + + */ + unsigned int loopbackStatus : 5; /* 1E.C888.F:B RO Default = 0x00 */ + /* 0x00 = No loopback + 0x01 = System Interface - System Loopback + 0x02 = System Interface - System Loopback with Passthrough + 0x03 = System Interface - Network Loopback + 0x04 = System Interface - Network Loopback with Passthrough + 0x05 = System Interface - Network Loopback with Passthrough and Merge + 0x06 = System Interface - Peer-to-peer loopback + 0x07 - 0x08 = Reserved + 0x09 = Network Interface - System Loopback + 0x0A = Network Interface - System Loopback with Passthrough + 0x0B = Network Interface - Network Loopback + 0x0C = Network Interface - Network Loopback with Passthrough + 0x0D = Network Interface - Peer-to-peer loopback + 0x0E - 0x0F = Reserved + 0x10 = Cross-connect System Loopback + 0x11 = Cross-connect Network Loopback + 0x12 - 0x13 = Reserved + 0x14 = Network Interface - System Loopback via Loopback Plug + 0x15 - 0x1F = Reserved + */ + /*! \brief 1E.C888.A:6 RO Reserved Status 4 [4:0] + AQ_GlobalReservedStatus_HHD.u3.bits_3.reservedStatus_4 + + Default = 0x00 + + Reserved for future use + + */ + unsigned int reservedStatus_4 : 5; /* 1E.C888.A:6 RO Default = 0x00 */ + /* Reserved for future use + */ + /*! \brief 1E.C888.5 RO MDI Packet Generation Status + AQ_GlobalReservedStatus_HHD.u3.bits_3.mdiPacketGenerationStatus + + Default = 0x0 + + 1 = CRPAT packet generation out MDI interface + 0 = No CRPAT packet generation out MDI interface + + + Notes: + Reports whether the CRPAT packet generator in the PHY outputs on the MDI interface at the selected rate. */ + unsigned int mdiPacketGenerationStatus : 1; /* 1E.C888.5 RO Default = 0x0 */ + /* 1 = CRPAT packet generation out MDI interface + 0 = No CRPAT packet generation out MDI interface + */ + /*! \brief 1E.C888.4 RO Look-Aside Port Packet Generation Status + AQ_GlobalReservedStatus_HHD.u3.bits_3.look_asidePortPacketGenerationStatus + + Default = 0x0 + + 1 = CRPAT packet generation out 10G look-aside interface (KR0) + 0 = No CRPAT packet generation out 10G look-aside interface (KR0) + + + Notes: + Reports whether the CRPAT packet generator in the PHY outputs on the KR0 interface at the selected rate. */ + unsigned int look_asidePortPacketGenerationStatus : 1; /* 1E.C888.4 RO Default = 0x0 */ + /* 1 = CRPAT packet generation out 10G look-aside interface (KR0) + 0 = No CRPAT packet generation out 10G look-aside interface (KR0) + */ + /*! \brief 1E.C888.3 RO System I/F Packet Generation Status + AQ_GlobalReservedStatus_HHD.u3.bits_3.systemI_fPacketGenerationStatus + + Default = 0x0 + + 1 = CRPAT packet generation out 10G system interface + 0 = No CRPAT packet generation out 10G system interface + + + Notes: + Reports whether the CRPAT packet generator in the PHY outputs on the selected system interface at the selected rate. */ + unsigned int systemI_fPacketGenerationStatus : 1; /* 1E.C888.3 RO Default = 0x0 */ + /* 1 = CRPAT packet generation out 10G system interface + 0 = No CRPAT packet generation out 10G system interface + */ + /*! \brief 1E.C888.2 RO Reserved Status 4a + AQ_GlobalReservedStatus_HHD.u3.bits_3.reservedStatus_4a + + Default = 0x0 + + Reserved for future use + + */ + unsigned int reservedStatus_4a : 1; /* 1E.C888.2 RO Default = 0x0 */ + /* Reserved for future use + */ + /*! \brief 1E.C888.1:0 RO Rate [1:0] + AQ_GlobalReservedStatus_HHD.u3.bits_3.rate + + Default = 0x0 + + 0x3 = 10G + 0x2 = 1G + 0x1 = 100M + 0x0 = invalid + + + Notes: + These bits report the selected rate for the loopback and packet generation. */ + unsigned int rate : 2; /* 1E.C888.1:0 RO Default = 0x0 */ + /* 0x3 = 10G + 0x2 = 1G + 0x1 = 100M + 0x0 = invalid + */ + } bits_3; + uint16_t word_3; + } u3; +} AQ_GlobalReservedStatus_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Alarms: 1E.CC00 */ +/* Global Alarms: 1E.CC00 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Alarms */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.CC00.E LH High Temperature Failure + AQ_GlobalAlarms_HHD.u0.bits_0.highTemperatureFailure + + + + 1 = High temperature failure threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int highTemperatureFailure : 1; /* 1E.CC00.E LH */ + /* 1 = High temperature failure threshold has been exceeded + */ + /*! \brief 1E.CC00.D LH Low Temperature Failure + AQ_GlobalAlarms_HHD.u0.bits_0.lowTemperatureFailure + + + + 1 = Low temperature failure threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int lowTemperatureFailure : 1; /* 1E.CC00.D LH */ + /* 1 = Low temperature failure threshold has been exceeded + */ + /*! \brief 1E.CC00.C LH High Temperature Warning + AQ_GlobalAlarms_HHD.u0.bits_0.highTemperatureWarning + + + + 1 = High temperature warning threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int highTemperatureWarning : 1; /* 1E.CC00.C LH */ + /* 1 = High temperature warning threshold has been exceeded + */ + /*! \brief 1E.CC00.B LH Low Temperature Warning + AQ_GlobalAlarms_HHD.u0.bits_0.lowTemperatureWarning + + + + 1 = Low temperature warning threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int lowTemperatureWarning : 1; /* 1E.CC00.B LH */ + /* 1 = Low temperature warning threshold has been exceeded + */ + unsigned int reserved1 : 4; + /*! \brief 1E.CC00.6 LH Reset completed + AQ_GlobalAlarms_HHD.u0.bits_0.resetCompleted + + + + 1 = Chip wide reset completed + + Notes: + This bit is set by the microprocessor when it has completed it's initialization sequence. This bit is mirrored in 1.CC02.0 */ + unsigned int resetCompleted : 1; /* 1E.CC00.6 LH */ + /* 1 = Chip wide reset completed */ + unsigned int reserved2 : 1; + /*! \brief 1E.CC00.4 LH Device Fault + AQ_GlobalAlarms_HHD.u0.bits_0.deviceFault + + + + 1 = Fault + + Notes: + When set, a fault has been detected by the uP and the associated 16 bit error code is visible in See Global Configuration Fault Message: Address 1E.C850 */ + unsigned int deviceFault : 1; /* 1E.CC00.4 LH */ + /* 1 = Fault */ + /*! \brief 1E.CC00.3 LH Reserved Alarm A + AQ_GlobalAlarms_HHD.u0.bits_0.reservedAlarmA + + + + Reserved for future use + + */ + unsigned int reservedAlarmA : 1; /* 1E.CC00.3 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC00.2 LH Reserved Alarm B + AQ_GlobalAlarms_HHD.u0.bits_0.reservedAlarmB + + + + Reserved for future use + + */ + unsigned int reservedAlarmB : 1; /* 1E.CC00.2 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC00.1 LH Reserved Alarm C + AQ_GlobalAlarms_HHD.u0.bits_0.reservedAlarmC + + + + Reserved for future use + + */ + unsigned int reservedAlarmC : 1; /* 1E.CC00.1 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC00.0 LH Reserved Alarm D + AQ_GlobalAlarms_HHD.u0.bits_0.reservedAlarmD + + + + Reserved for future use + + */ + unsigned int reservedAlarmD : 1; /* 1E.CC00.0 LH */ + /* Reserved for future use + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Alarms */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.CC01.E LH Smart Power-Down Entered + AQ_GlobalAlarms_HHD.u1.bits_1.smartPower_downEntered + + + + 1 = Smart Power-Down State Entered + + + Notes: + When this bit is set, it indicates that the Smart Power-Down state was entered */ + unsigned int smartPower_downEntered : 1; /* 1E.CC01.E LH */ + /* 1 = Smart Power-Down State Entered + */ + /*! \brief 1E.CC01.D RO XENPAK Alarm + AQ_GlobalAlarms_HHD.u1.bits_1.xenpakAlarm + + + + 1 = XENPAK Alarm + + */ + unsigned int xenpakAlarm : 1; /* 1E.CC01.D RO */ + /* 1 = XENPAK Alarm + */ + /*! \brief 1E.CC01.C LH IP Phone Detect + AQ_GlobalAlarms_HHD.u1.bits_1.ipPhoneDetect + + + + 1 = IP Phone Detect + + + Notes: + Assertion of this bit means that the presence of an IP Phone has been detected. */ + unsigned int ipPhoneDetect : 1; /* 1E.CC01.C LH */ + /* 1 = IP Phone Detect + */ + /*! \brief 1E.CC01.B LH DTE Status Change + AQ_GlobalAlarms_HHD.u1.bits_1.dteStatusChange + + + + 1 = DTE status change + + + Notes: + Change in 1E.C887[F]. */ + unsigned int dteStatusChange : 1; /* 1E.CC01.B LH */ + /* 1 = DTE status change + */ + /*! \brief 1E.CC01.A:8 LH Reserved Alarms [2:0] + AQ_GlobalAlarms_HHD.u1.bits_1.reservedAlarms + + + + Reserved + + + */ + unsigned int reservedAlarms : 3; /* 1E.CC01.A:8 LH */ + /* Reserved + + */ + /*! \brief 1E.CC01.7 LH MDIO Command Handling Overflow + AQ_GlobalAlarms_HHD.u1.bits_1.mdioCommandHandlingOverflow + + + + 1 = PHY was issued more MDIO requests than it could service in it's request buffer + + + Notes: + Assertion of this bit means that more MDIO commands were issued than FW could handle. */ + unsigned int mdioCommandHandlingOverflow : 1; /* 1E.CC01.7 LH */ + /* 1 = PHY was issued more MDIO requests than it could service in it's request buffer + */ + unsigned int reserved1 : 6; + unsigned int reserved2 : 1; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Alarms */ + union + { + struct + { + /*! \brief 1E.CC02.F LH NVR Operation Complete + AQ_GlobalAlarms_HHD.u2.bits_2.nvrOperationComplete + + + + 1 = NVR operation is complete + + + Notes: + NVR interface is ready interrupt for registers See Global NVR Interface 1: Address 1E.100 - See Global NVR Provisioning Data MSW - Address 1E.17 . */ + unsigned int nvrOperationComplete : 1; /* 1E.CC02.F LH */ + /* 1 = NVR operation is complete + */ + /*! \brief 1E.CC02.E LH Mailbox Operation: Complete + AQ_GlobalAlarms_HHD.u2.bits_2.mailboxOperation_Complete + + + + 1 = Mailbox operation is complete + + + Notes: + Mailbox interface is ready interrupt for registers See Global Vendor Specific Control - Address 1E.C000 - See Global Vendor Specific Provisioning 5 - Address 1E.C404 */ + unsigned int mailboxOperation_Complete : 1; /* 1E.CC02.E LH */ + /* 1 = Mailbox operation is complete + */ + unsigned int reserved0 : 3; + /*! \brief 1E.CC02.A LH uP DRAM Parity Error + AQ_GlobalAlarms_HHD.u2.bits_2.upDramParityError + + + + 1 = Parity error detected in the uP DRAM + + */ + unsigned int upDramParityError : 1; /* 1E.CC02.A LH */ + /* 1 = Parity error detected in the uP DRAM + */ + /*! \brief 1E.CC02.9:8 LH uP IRAM Parity Error [1:0] + AQ_GlobalAlarms_HHD.u2.bits_2.upIramParityError + + + + 1 = Parity error detected in the uP IRAM + + + Notes: + Bit 0 indicates a parity error was detected in the uP IRAM but was corrected. + Bit 1 indicates a multiple parity errors were detected in the uP IRAM and could not be corrected. + The uP IRAM is protected with ECC. */ + unsigned int upIramParityError : 2; /* 1E.CC02.9:8 LH */ + /* 1 = Parity error detected in the uP IRAM + */ + unsigned int reserved1 : 2; + /*! \brief 1E.CC02.5 LRF Tx Enable State Change + AQ_GlobalAlarms_HHD.u2.bits_2.txEnableStateChange + + + + 1 = TX_EN pin has changed state + + */ + unsigned int txEnableStateChange : 1; /* 1E.CC02.5 LRF */ + /* 1 = TX_EN pin has changed state + */ + unsigned int reserved2 : 2; + /*! \brief 1E.CC02.2 LH MDIO MMD Error + AQ_GlobalAlarms_HHD.u2.bits_2.mdioMMD_Error + + + + 1 = Invalid MMD address detected + + */ + unsigned int mdioMMD_Error : 1; /* 1E.CC02.2 LH */ + /* 1 = Invalid MMD address detected + */ + /*! \brief 1E.CC02.1 LH MDIO Timeout Error + AQ_GlobalAlarms_HHD.u2.bits_2.mdioTimeoutError + + + + 1 = MDIO timeout detected + + */ + unsigned int mdioTimeoutError : 1; /* 1E.CC02.1 LH */ + /* 1 = MDIO timeout detected + */ + /*! \brief 1E.CC02.0 LH Watchdog Timer Alarm + AQ_GlobalAlarms_HHD.u2.bits_2.watchdogTimerAlarm + + + + 1 = Watchdog timer alarm + + */ + unsigned int watchdogTimerAlarm : 1; /* 1E.CC02.0 LH */ + /* 1 = Watchdog timer alarm + */ + } bits_2; + uint16_t word_2; + } u2; +} AQ_GlobalAlarms_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Interrupt Mask: 1E.D400 */ +/* Global Interrupt Mask: 1E.D400 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Interrupt Mask */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.D400.E R/WPD High Temperature Failure Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.highTemperatureFailureMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int highTemperatureFailureMask : 1; /* 1E.D400.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D400.D R/WPD Low Temperature Failure Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.lowTemperatureFailureMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int lowTemperatureFailureMask : 1; /* 1E.D400.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D400.C R/WPD High Temperature Warning Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.highTemperatureWarningMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int highTemperatureWarningMask : 1; /* 1E.D400.C R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D400.B R/WPD Low Temperature Warning Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.lowTemperatureWarningMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int lowTemperatureWarningMask : 1; /* 1E.D400.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved1 : 4; + /*! \brief 1E.D400.6 R/WPD Reset completed Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.resetCompletedMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int resetCompletedMask : 1; /* 1E.D400.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved2 : 1; + /*! \brief 1E.D400.4 R/WPD Device Fault Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.deviceFaultMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int deviceFaultMask : 1; /* 1E.D400.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D400.3 R/WPD Reserved Alarm A Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.reservedAlarmAMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmAMask : 1; /* 1E.D400.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D400.2 R/WPD Reserved Alarm B Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.reservedAlarmBMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmBMask : 1; /* 1E.D400.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D400.1 R/WPD Reserved Alarm C Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.reservedAlarmCMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmCMask : 1; /* 1E.D400.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D400.0 R/WPD Reserved Alarm D Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.reservedAlarmDMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmDMask : 1; /* 1E.D400.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Interrupt Mask */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.D401.E R/WPD Smart Power-Down Entered Mask + AQ_GlobalInterruptMask_HHD.u1.bits_1.smartPower_downEnteredMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int smartPower_downEnteredMask : 1; /* 1E.D401.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D401.D R/WPD XENPAK Alarm Mask + AQ_GlobalInterruptMask_HHD.u1.bits_1.xenpakAlarmMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int xenpakAlarmMask : 1; /* 1E.D401.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D401.C R/WPD IP Phone Detect Mask + AQ_GlobalInterruptMask_HHD.u1.bits_1.ipPhoneDetectMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int ipPhoneDetectMask : 1; /* 1E.D401.C R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D401.B R/WPD DTE Status Change Mask + AQ_GlobalInterruptMask_HHD.u1.bits_1.dteStatusChangeMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int dteStatusChangeMask : 1; /* 1E.D401.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D401.A:8 R/WPD Reserved Alarms Mask [2:0] + AQ_GlobalInterruptMask_HHD.u1.bits_1.reservedAlarmsMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmsMask : 3; /* 1E.D401.A:8 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D401.7 R/WPD MDIO Command Handling Overflow Mask + AQ_GlobalInterruptMask_HHD.u1.bits_1.mdioCommandHandlingOverflowMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int mdioCommandHandlingOverflowMask : 1; /* 1E.D401.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int reserved1 : 6; + /*! \brief 1E.D401.0 R/WPD Diagnostic Alarm Mask + AQ_GlobalInterruptMask_HHD.u1.bits_1.diagnosticAlarmMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int diagnosticAlarmMask : 1; /* 1E.D401.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Interrupt Mask */ + union + { + struct + { + /*! \brief 1E.D402.F R/WPD NVR Operation Complete Mask + AQ_GlobalInterruptMask_HHD.u2.bits_2.nvrOperationCompleteMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + Notes: + NVR interface is ready interrupt for registers See Global NVR Interface 1: Address 1E.100 - See Global NVR Provisioning Data MSW - Address 1E.17 */ + unsigned int nvrOperationCompleteMask : 1; /* 1E.D402.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D402.E R/WPD Mailbox Operation Complete Mask + AQ_GlobalInterruptMask_HHD.u2.bits_2.mailboxOperationCompleteMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + Notes: + Mailbox interface is ready interrupt for registers See Global Vendor Specific Control - Address 1E.C000 - See Global Vendor Specific Provisioning 5 - Address 1E.C404 */ + unsigned int mailboxOperationCompleteMask : 1; /* 1E.D402.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved0 : 3; + /*! \brief 1E.D402.A R/WPD uP DRAM Parity Error Mask + AQ_GlobalInterruptMask_HHD.u2.bits_2.upDramParityErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int upDramParityErrorMask : 1; /* 1E.D402.A R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D402.9:8 R/WPD uP IRAM Parity Error Mask [1:0] + AQ_GlobalInterruptMask_HHD.u2.bits_2.upIramParityErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int upIramParityErrorMask : 2; /* 1E.D402.9:8 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int reserved1 : 2; + /*! \brief 1E.D402.5 R/WPD Tx Enable State Change Mask + AQ_GlobalInterruptMask_HHD.u2.bits_2.txEnableStateChangeMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int txEnableStateChangeMask : 1; /* 1E.D402.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved2 : 2; + /*! \brief 1E.D402.2 R/WPD MDIO MMD Error Mask + AQ_GlobalInterruptMask_HHD.u2.bits_2.mdioMMD_ErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int mdioMMD_ErrorMask : 1; /* 1E.D402.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D402.1 R/WPD MDIO Timeout Error Mask + AQ_GlobalInterruptMask_HHD.u2.bits_2.mdioTimeoutErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int mdioTimeoutErrorMask : 1; /* 1E.D402.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D402.0 R/WPD Watchdog Timer Alarm Mask + AQ_GlobalInterruptMask_HHD.u2.bits_2.watchdogTimerAlarmMask + + Provisionable Default = 0x1 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int watchdogTimerAlarmMask : 1; /* 1E.D402.0 R/WPD Provisionable Default = 0x1 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + } bits_2; + uint16_t word_2; + } u2; +} AQ_GlobalInterruptMask_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Chip-Wide Standard Interrupt Flags: 1E.FC00 */ +/* Global Chip-Wide Standard Interrupt Flags: 1E.FC00 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Chip-Wide Standard Interrupt Flags */ + union + { + struct + { + /*! \brief 1E.FC00.F RO PMA Standard Alarm 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.pmaStandardAlarm_1Interrupt + + + + 1 = Interrupt in PMA standard alarms 1 + + + Notes: + An interrupt was generated from bit 1.1.2. + An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ + unsigned int pmaStandardAlarm_1Interrupt : 1; /* 1E.FC00.F RO */ + /* 1 = Interrupt in PMA standard alarms 1 + */ + /*! \brief 1E.FC00.E RO PMA Standard Alarm 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.pmaStandardAlarm_2Interrupt + + + + 1 = Interrupt in PMA standard alarms 2 + + + Notes: + An interrupt was generated from either bit 1.8.B or 1.8.A. + An interrupt was generated from status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int pmaStandardAlarm_2Interrupt : 1; /* 1E.FC00.E RO */ + /* 1 = Interrupt in PMA standard alarms 2 + */ + /*! \brief 1E.FC00.D RO PCS Standard Alarm 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.pcsStandardAlarm_1Interrupt + + + + 1 = Interrupt in PCS standard alarms 1 + + + Notes: + An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ + unsigned int pcsStandardAlarm_1Interrupt : 1; /* 1E.FC00.D RO */ + /* 1 = Interrupt in PCS standard alarms 1 + */ + /*! \brief 1E.FC00.C RO PCS Standard Alarm 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.pcsStandardAlarm_2Interrupt + + + + 1 = Interrupt in PCS standard alarms 2 + + + Notes: + An interrupt was generated from status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int pcsStandardAlarm_2Interrupt : 1; /* 1E.FC00.C RO */ + /* 1 = Interrupt in PCS standard alarms 2 + */ + /*! \brief 1E.FC00.B RO PCS Standard Alarm 3 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.pcsStandardAlarm_3Interrupt + + + + 1 = Interrupt in PCS standard alarms 3 + + + Notes: + An interrupt was generated from status register ( See PCS 10GBASE-T Status 2 - Address 3.21 ) and the corresponding mask register. ( See PCS Standard Interrupt Mask 1 - Address 3.E021 ) */ + unsigned int pcsStandardAlarm_3Interrupt : 1; /* 1E.FC00.B RO */ + /* 1 = Interrupt in PCS standard alarms 3 + */ + /*! \brief 1E.FC00.A RO PHY XS Standard Alarms 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.phyXS_StandardAlarms_1Interrupt + + + + 1 = Interrupt in PHY XS standard alarms 1 + + + Notes: + An interrupt was generated from the status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ + unsigned int phyXS_StandardAlarms_1Interrupt : 1; /* 1E.FC00.A RO */ + /* 1 = Interrupt in PHY XS standard alarms 1 + */ + /*! \brief 1E.FC00.9 RO PHY XS Standard Alarms 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.phyXS_StandardAlarms_2Interrupt + + + + 1 = Interrupt in PHY XS standard alarms 2 + + + Notes: + An interrupt was generated from the status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int phyXS_StandardAlarms_2Interrupt : 1; /* 1E.FC00.9 RO */ + /* 1 = Interrupt in PHY XS standard alarms 2 + */ + /*! \brief 1E.FC00.8 RO Autonegotiation Standard Alarms 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.autonegotiationStandardAlarms_1Interrupt + + + + 1 = Interrupt in Autonegotiation standard alarms 1 + + + Notes: + An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See Autonegotiation Standard LASI Interrupt Mask 1: Address 7.D000 ) */ + unsigned int autonegotiationStandardAlarms_1Interrupt : 1; /* 1E.FC00.8 RO */ + /* 1 = Interrupt in Autonegotiation standard alarms 1 + */ + /*! \brief 1E.FC00.7 RO Autonegotiation Standard Alarms 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.autonegotiationStandardAlarms_2Interrupt + + + + 1 = Interrupt in Autonegotiation standard alarms 2 + + + Notes: + An interrupt was generated from status register ( See Autonegotiation 10GBASE-T Status Register - Address 7.21 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int autonegotiationStandardAlarms_2Interrupt : 1; /* 1E.FC00.7 RO */ + /* 1 = Interrupt in Autonegotiation standard alarms 2 + */ + /*! \brief 1E.FC00.6 RO GbE Standard Alarms Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.gbeStandardAlarmsInterrupt + + + + 1 = Interrupt in GbE standard alarms + + + Notes: + An interrupt was generated from the TGE core. */ + unsigned int gbeStandardAlarmsInterrupt : 1; /* 1E.FC00.6 RO */ + /* 1 = Interrupt in GbE standard alarms + */ + unsigned int reserved0 : 5; + /*! \brief 1E.FC00.0 RO All Vendor Alarms Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.allVendorAlarmsInterrupt + + + + 1 = Interrupt in all vendor alarms + + + Notes: + An interrupt was generated from status register ( See Global Chip-Wide LASI Vendor Interrupt Flags: Address 1E.FC01 ) and the corresponding mask register. ( See Global Interrupt LASI Mask: Address 1E.FF01 ) */ + unsigned int allVendorAlarmsInterrupt : 1; /* 1E.FC00.0 RO */ + /* 1 = Interrupt in all vendor alarms + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalChip_wideStandardInterruptFlags_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Chip-Wide Vendor Interrupt Flags: 1E.FC01 */ +/* Global Chip-Wide Vendor Interrupt Flags: 1E.FC01 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Chip-Wide Vendor Interrupt Flags */ + union + { + struct + { + /*! \brief 1E.FC01.F RO PMA Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.pmaVendorAlarmInterrupt + + + + 1 = Interrupt in PMA vendor specific alarm + + + Notes: + A PMA alarm was generated. ( See PHY XS Vendor Global Interrupt Flags 1- Address 4.F800 ) */ + unsigned int pmaVendorAlarmInterrupt : 1; /* 1E.FC01.F RO */ + /* 1 = Interrupt in PMA vendor specific alarm + */ + /*! \brief 1E.FC01.E RO PCS Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.pcsVendorAlarmInterrupt + + + + 1 = Interrupt in PCS vendor specific alarm + + + Notes: + A PCS alarm was generated. ( See PHY XS Vendor Global Interrupt Flags 1- Address 4.F800 ) */ + unsigned int pcsVendorAlarmInterrupt : 1; /* 1E.FC01.E RO */ + /* 1 = Interrupt in PCS vendor specific alarm + */ + /*! \brief 1E.FC01.D RO PHY XS Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.phyXS_VendorAlarmInterrupt + + + + 1 = Interrupt in PHY XS vendor specific alarm + + + Notes: + A PHY XS alarm was generated. ( See PHY XS Vendor Global LASI Interrupt Flags 1: Address 4.FC00 ) */ + unsigned int phyXS_VendorAlarmInterrupt : 1; /* 1E.FC01.D RO */ + /* 1 = Interrupt in PHY XS vendor specific alarm + */ + /*! \brief 1E.FC01.C RO Autonegotiation Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.autonegotiationVendorAlarmInterrupt + + + + 1 = Interrupt in Autonegotiation vendor specific alarm + + + Notes: + An Autonegotiation alarm was generated. ( See Autonegotiation Vendor Global LASI Interrupt Flags 1: Address 7.FC00 ) */ + unsigned int autonegotiationVendorAlarmInterrupt : 1; /* 1E.FC01.C RO */ + /* 1 = Interrupt in Autonegotiation vendor specific alarm + */ + /*! \brief 1E.FC01.B RO GbE Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.gbeVendorAlarmInterrupt + + + + 1 = Interrupt in GbE vendor specific alarm + + + Notes: + A GbE alarm was generated. ( See GbE PHY Vendor Global LASI Interrupt Flags 1: Address 1D.FC00 ) */ + unsigned int gbeVendorAlarmInterrupt : 1; /* 1E.FC01.B RO */ + /* 1 = Interrupt in GbE vendor specific alarm + */ + unsigned int reserved0 : 8; + /*! \brief 1E.FC01.2 RO Global Alarms 1 Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.globalAlarms_1Interrupt + + + + 1 = Interrupt in Global alarms 1 + + + Notes: + An interrupt was generated from status register ( See Global Vendor Alarms 1 - Address 1E.CC00 ) and the corresponding mask register. ( See Global Vendor Interrupt Mask - Address 1E.D400 ) */ + unsigned int globalAlarms_1Interrupt : 1; /* 1E.FC01.2 RO */ + /* 1 = Interrupt in Global alarms 1 + */ + /*! \brief 1E.FC01.1 RO Global Alarms 2 Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.globalAlarms_2Interrupt + + + + 1 = Interrupt in Global alarms 2 + + + Notes: + An interrupt was generated from status register ( See Global Alarms 2: Address 1E.CC01 ) and the corresponding mask register. ( See Global LASI Interrupt Mask 2: Address 1E.D401 ) */ + unsigned int globalAlarms_2Interrupt : 1; /* 1E.FC01.1 RO */ + /* 1 = Interrupt in Global alarms 2 + */ + /*! \brief 1E.FC01.0 RO Global Alarms 3 Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.globalAlarms_3Interrupt + + + + 1 = Interrupt in Global alarms 3 + + + Notes: + An interrupt was generated from status register ( See Global Vendor Alarms 2: Address 1E.CC01 ) and the corresponding mask register. ( See Global LASI Interrupt Mask 2: Address 1E.D401 ) */ + unsigned int globalAlarms_3Interrupt : 1; /* 1E.FC01.0 RO */ + /* 1 = Interrupt in Global alarms 3 + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalChip_wideVendorInterruptFlags_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Interrupt Chip-Wide Standard Mask: 1E.FF00 */ +/* Global Interrupt Chip-Wide Standard Mask: 1E.FF00 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Interrupt Chip-Wide Standard Mask */ + union + { + struct + { + /*! \brief 1E.FF00.F R/WPD PMA Standard Alarm 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.pmaStandardAlarm_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pmaStandardAlarm_1InterruptMask : 1; /* 1E.FF00.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.E R/WPD PMA Standard Alarm 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.pmaStandardAlarm_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pmaStandardAlarm_2InterruptMask : 1; /* 1E.FF00.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.D R/WPD PCS Standard Alarm 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.pcsStandardAlarm_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsStandardAlarm_1InterruptMask : 1; /* 1E.FF00.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.C R/WPD PCS Standard Alarm 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.pcsStandardAlarm_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsStandardAlarm_2InterruptMask : 1; /* 1E.FF00.C R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.B R/WPD PCS Standard Alarm 3 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.pcsStandardAlarm_3InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsStandardAlarm_3InterruptMask : 1; /* 1E.FF00.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.A R/WPD PHY XS Standard Alarms 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.phyXS_StandardAlarms_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int phyXS_StandardAlarms_1InterruptMask : 1; /* 1E.FF00.A R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.9 R/WPD PHY XS Standard Alarms 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.phyXS_StandardAlarms_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int phyXS_StandardAlarms_2InterruptMask : 1; /* 1E.FF00.9 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.8 R/WPD Autonegotiation Standard Alarms 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.autonegotiationStandardAlarms_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int autonegotiationStandardAlarms_1InterruptMask : 1; /* 1E.FF00.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.7 R/WPD Autonegotiation Standard Alarms 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.autonegotiationStandardAlarms_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int autonegotiationStandardAlarms_2InterruptMask : 1; /* 1E.FF00.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.6 R/WPD Gbe Standard Alarms Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.gbeStandardAlarmsInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int gbeStandardAlarmsInterruptMask : 1; /* 1E.FF00.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved0 : 5; + /*! \brief 1E.FF00.0 R/WPD All Vendor Alarms Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.allVendorAlarmsInterruptMask + + Provisionable Default = 0x1 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int allVendorAlarmsInterruptMask : 1; /* 1E.FF00.0 R/WPD Provisionable Default = 0x1 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalInterruptChip_wideStandardMask_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Interrupt Chip-Wide Vendor Mask: 1E.FF01 */ +/* Global Interrupt Chip-Wide Vendor Mask: 1E.FF01 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Interrupt Chip-Wide Vendor Mask */ + union + { + struct + { + /*! \brief 1E.FF01.F R/WPD PMA Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.pmaVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pmaVendorAlarmInterruptMask : 1; /* 1E.FF01.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.E R/WPD PCS Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.pcsVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsVendorAlarmInterruptMask : 1; /* 1E.FF01.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.D R/WPD PHY XS Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.phyXS_VendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int phyXS_VendorAlarmInterruptMask : 1; /* 1E.FF01.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.C R/WPD Autonegotiation Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.autonegotiationVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int autonegotiationVendorAlarmInterruptMask : 1; /* 1E.FF01.C R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.B R/WPD GbE Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.gbeVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int gbeVendorAlarmInterruptMask : 1; /* 1E.FF01.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved0 : 8; + /*! \brief 1E.FF01.2 R/WPD Global Alarms 1 Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.globalAlarms_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int globalAlarms_1InterruptMask : 1; /* 1E.FF01.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.1 R/WPD Global Alarms 2 Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.globalAlarms_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int globalAlarms_2InterruptMask : 1; /* 1E.FF01.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.0 R/WPD Global Alarms 3 Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.globalAlarms_3InterruptMask + + Provisionable Default = 0x1 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int globalAlarms_3InterruptMask : 1; /* 1E.FF01.0 R/WPD Provisionable Default = 0x1 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalInterruptChip_wideVendorMask_HHD; + +#endif +/*@}*/ +/*@}*/ diff --git a/qca/aq-fw-download/src/mdioBootLoadCLD.c b/qca/aq-fw-download/src/mdioBootLoadCLD.c new file mode 100644 index 000000000..a8e09d8c9 --- /dev/null +++ b/qca/aq-fw-download/src/mdioBootLoadCLD.c @@ -0,0 +1,193 @@ +/* mdioBootLoadCLD.c */ + +/************************************************************************************ +* Copyright (c) 2015 Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +* +* $File: //depot/icm/proj/Dena/rev1.0/c/Systems/tools/windows/flashUtilities/src/mdioBootLoadCLD.c $ +* +* $Revision: #12 $ +* +* $DateTime: 2014/05/19 15:34:49 $ +* +* $Author: joshd $ +* +* $Label: $ +* +************************************************************************************/ + +/*! \file +This file contains the main (int, char**) file for the mdioBootLoadCLD program, which burns a flash image into a target +Aquantia PHY using the AQ_API. This program calls the API function:

    + + uint8_t AQ_API_WriteBootLoadImage (uint8_t PHY_ID, uint8_t *image, uint16_t *crc16)

    + +to boot load a cld flash image into an Aquantia PHY */ + +/*! \addtogroup mdioBootLoad +@{ +*/ + + + +/*! \def DEBUG +Uncomment this to compile in debug mode. This sets the source to an arbitrary file, defined by DEBUG_FILENAME, +and an arbitrary PHY_ID, defined by DEBUG_PHY_ID. */ +/* #define DEBUG */ + +/*! The debug source file name */ +#define DEBUG_FILENAME "HelloWorld.cld" + +/*! The debug PHY ID */ +#define DEBUG_PHY_ID 0 + + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "AQ_API.h" +#include "AQ_PhyInterface.h" + +int sock; +char devname[7]; + +int sock_init() +{ + if ((sock = socket(AF_INET, SOCK_DGRAM, 0)) < 0) { + fprintf(stderr, "Error creating socket: %s\n", strerror(errno)); + return -1; + } + + return 0; +} + +int main ( int argc, char **argp) +{ + /* declare local variables */ + FILE *pFile; + uint8_t* image; + uint8_t byte; + unsigned int PHY_ID; + AQ_Retcode resultCode; + AQ_Retcode resultCodes[4]; + uint32_t i; + uint32_t imageSize; + char sourceFileName[1000]; + AQ_API_Port targetPort0; + AQ_API_Port* targetPorts[1]; + AQ_API_Port broadcastPort; + unsigned int provisioningAddresses[1] = {0}; + uint32_t reg1, reg2; + + targetPorts[0] = &targetPort0; + + if(argc < 4) { + fprintf (stderr, "enter file name/netdev name/phy address\n"); + return (101); + } + + /*Copy the file name from command line arg*/ + if (strlcpy (sourceFileName, argp[1], sizeof(sourceFileName)) >= sizeof(sourceFileName)) { + fprintf (stderr, "Filename: %s too long \n", argp[1]); + return (101); + } + /*Copy the interface name from command line arg*/ + strlcpy (devname, argp[2], sizeof(devname)); + /*Get PHY Address from command line arg*/ + PHY_ID = (unsigned int)strtoul(argp[3], NULL, 0); + + /* FIXME: set port and device type */ + targetPort0.device = AQ_DEVICE_HHD; + targetPort0.PHY_ID = PHY_ID; + + broadcastPort.device = AQ_DEVICE_HHD; + broadcastPort.PHY_ID = PHY_ID; + + /* open the source in binary read mode */ + pFile = fopen(sourceFileName, "rb"); + if (pFile == NULL) + { + fprintf (stderr, "Unable to open source file %s\n", sourceFileName); + return (101); + } + fseek (pFile, 0, SEEK_END); + imageSize = ftell (pFile); + + image = (uint8_t*) malloc (imageSize * sizeof(uint8_t)); + fseek (pFile, 0, SEEK_SET); + + /* load the file */ + for (i = 0; i < imageSize; i++) + { + byte = (uint8_t) fgetc (pFile); + image[i] = byte; + } + fclose(pFile); + + + if (sock_init() < 0) + { + fprintf (stderr, "Unable to initialize interface\n"); + return (200); + } + + /* Write in the Auantia phy scratch pad register, + * read back the same reg and match the values written. + */ + AQ_API_MDIO_Write(PHY_ID, 0x1e, 0x300, 0xdead); + AQ_API_MDIO_Write(PHY_ID, 0x1e, 0x301, 0xbeaf); + reg1 = AQ_API_MDIO_Read(PHY_ID, 0x1e, 0x300); + reg2 = AQ_API_MDIO_Read(PHY_ID, 0x1e, 0x301); + if(reg1 != 0xdead && reg2 != 0xbeaf) { + fprintf (stderr, "Scratchpad Read/Write test fail\n"); + return (101); + } + + /* call the boot-load function */ + resultCode = AQ_API_WriteBootLoadImage(targetPorts, 1, provisioningAddresses, resultCodes, &imageSize, image, PHY_ID, &broadcastPort); + + switch (resultCode) + { + case 0: + printf("Image load good - mailbox CRC-16 matches\n"); + free (image); + close(sock); + return 0; + + case 1: + fprintf (stderr, "CRC-16 on file is bad\n"); + free (image); + close(sock); + return 1; + + case 2: + fprintf (stderr, "CRC-16 check on image load failed (mailbox CRC-16 check)\n"); + free (image); + close(sock); + return 2; + + default: + fprintf (stderr, "Invalid return code\n"); + free (image); + close(sock); + } + return 12; +} +/*@}*/ diff --git a/qca/aq-fw-download/src/src/AQ_API.c b/qca/aq-fw-download/src/src/AQ_API.c new file mode 100644 index 000000000..89e73344f --- /dev/null +++ b/qca/aq-fw-download/src/src/AQ_API.c @@ -0,0 +1,1021 @@ +/*AQ_API.c*/ + +/************************************************************************************ +* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +* +* Description: +* +* This file contains the code for all of the API functions defined in AQ_API.h +* +************************************************************************************/ + + +/*! \file +* This file contains the code for all of the API functions defined in AQ_API.h + */ + +#include +#include + +#include "AQ_API.h" +#include "AQ_User.h" +#include "AQ_RegMacro.h" +#include "AQ_PlatformRoutines.h" +#include "AQ_RegMaps.h" +#include "AQ_ReturnCodes.h" + +#ifdef AQ_VERBOSE + #include + #include +#endif + + +#ifndef AQ_TIME_T_EXISTS + #ifndef AQ_MDIO_READS_PER_SECOND + #error AQ_MDIO_READS_PER_SECOND in AQ_User.h must be defined, as AQ_TIME_T_EXISTS is currently undefined! + #endif +#endif + +#ifdef AQ_TIME_T_EXISTS + #include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef AQ_ENABLE_UP_BUSY_CHECKS + #ifdef AQ_VERBOSE + #define AQ_API_UP_BUSY_PRINT_STATEMENT printf("uP-busy check timed out.\n"); + #else + #define AQ_API_UP_BUSY_PRINT_STATEMENT /* nothing */ + #endif + + #ifdef AQ_TIME_T_EXISTS + #define AQ_API_UP_BUSY_TIMEOUT (CLOCKS_PER_SEC / 10) + + #define AQ_API_DECLARE_UP_BUSY_VARS AQ_API_Variable(AQ_GlobalGeneralStatus) \ + uint16_t uPbusy; \ + clock_t startTime; \ + AQ_boolean uPBusyTimeoutOccurred = False; + + #define AQ_API_CHECK_UP_NOT_BUSY AQ_API_Wait(1, port); \ + startTime = clock(); \ + do \ + { \ + AQ_API_Get(port->PHY_ID, AQ_GlobalGeneralStatus, processorIntensiveMdioOperationIn_Progress, uPbusy); \ + if ((clock() - startTime) > AQ_API_UP_BUSY_TIMEOUT) \ + { \ + AQ_API_UP_BUSY_PRINT_STATEMENT \ + uPBusyTimeoutOccurred = True; \ + break; \ + } \ + } while (uPbusy != 0); + #else + #define AQ_API_UP_BUSY_MAX_CHECKS (AQ_MDIO_READS_PER_SECOND * 5) + + #define AQ_API_DECLARE_UP_BUSY_VARS AQ_API_Variable(AQ_GlobalGeneralStatus) \ + uint16_t uPbusy; \ + uint32_t numChecks; \ + AQ_boolean uPBusyTimeoutOccurred = False; + + #define AQ_API_CHECK_UP_NOT_BUSY AQ_API_Wait(1, port); \ + numChecks = 0; \ + do \ + { \ + AQ_API_Get(port->PHY_ID, AQ_GlobalGeneralStatus, processorIntensiveMdioOperationIn_Progress, uPbusy); \ + if (numChecks++ > AQ_API_UP_BUSY_MAX_CHECKS) \ + { \ + AQ_API_UP_BUSY_PRINT_STATEMENT \ + uPBusyTimeoutOccurred = True; \ + break; \ + } \ + } while (uPbusy != 0); + #endif + + /* If a uP busy timeout occurred, return the corresponding return code; otherwise, return + * retval. retval should be a return code defined in AQ_ReturnCodes. */ + #define AQ_API_RETURN_UP_BUSY(retval) return (uPBusyTimeoutOccurred ? AQ_RET_UP_BUSY_TIMEOUT : retval); + +#else + #define AQ_API_DECLARE_UP_BUSY_VARS /* nothing */ + #define AQ_API_CHECK_UP_NOT_BUSY /* nothing */ + #define AQ_API_RETURN_UP_BUSY(retval) return retval; +#endif + + +/*! FW image version string maximum length. */ +#define AQ_VERSION_STRING_SIZE 0x40 + +/*! The byte offset from top of DRAM to the FW image version string. */ +#define AQ_VERSION_STRING_BLOCK_OFFSET 0x0200 + +/*! The byte address, in processor memory, of the start of the IRAM segment. */ +#define AQ_IRAM_BASE_ADDRESS 0x40000000 + +/*! The byte address, in processor memory, of the start of the DRAM segment. */ +#define AQ_DRAM_BASE_ADDRESS 0x3FFE0000 + +/*! The byte offset from the top of the PHY image to the header content (HHD devices). */ +#define AQ_PHY_IMAGE_HEADER_CONTENT_OFFSET_HHD 0x300 + +/*! The byte offset from the top of the PHY image to the header content (APPIA devices). */ +#define AQ_PHY_IMAGE_HEADER_CONTENT_OFFSET_APPIA 0 + +/*! The offset, from the start of DRAM, where the provisioning block begins. */ +#define AQ_PHY_IMAGE_PROVTABLE_OFFSET 0x680 + +/*! The offset, from the start of DRAM, where the provisioning block's ending address is recorded. */ +#define AQ_PHY_IMAGE_PROVTABLE_TERM_OFFSET 0x028C + +/*! The size of the space alloted within the PHY image for the provisioning table. */ +#define AQ_PHY_IMAGE_PROVTABLE_MAXSIZE 0x800 + +/*! The maximum number of polling cycles ever required before the FLASH interface is ready. */ +#define AQ_FLASH_INTERFACE_MAX_POLL_COUNT 20 + +/*! The maximum number of ports that can be MDIO bootloaded at once. */ +#define AQ_MAX_NUM_PHY_IDS 48 + +/*! The maximum allowed number of times to poll for debug-trace-freeze acknowledgement. */ +#define AQ_MAX_FREEZE_CHECKS 2000 + +/*! The maximum size of the debug trace buffer. */ +#define AQ_MAX_TRACE_BUFFER_LENGTH 8192 + +/*! The maximum allowed number of times to poll for SERDES Rx eye measurement done. */ +#define AQ_SERDESEYE_MAX_DONE_CHECKS 50 + +/*! The maximum allowed number of times to poll for PIF mailbox status. */ +#define MAX_NUM_COMMAND_STATUS_POLLS 700 + +/* REGDOC_START */ + + +/********************************************************************************************************************** +* MDIO Boot Load +**********************************************************************************************************************/ + +const uint16_t AQ_CRC16Table[256] = {0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50a5, 0x60c6, 0x70e7, + 0x8108, 0x9129, 0xa14a, 0xb16b, 0xc18c, 0xd1ad, 0xe1ce, 0xf1ef, + 0x1231, 0x0210, 0x3273, 0x2252, 0x52b5, 0x4294, 0x72f7, 0x62d6, + 0x9339, 0x8318, 0xb37b, 0xa35a, 0xd3bd, 0xc39c, 0xf3ff, 0xe3de, + 0x2462, 0x3443, 0x0420, 0x1401, 0x64e6, 0x74c7, 0x44a4, 0x5485, + 0xa56a, 0xb54b, 0x8528, 0x9509, 0xe5ee, 0xf5cf, 0xc5ac, 0xd58d, + 0x3653, 0x2672, 0x1611, 0x0630, 0x76d7, 0x66f6, 0x5695, 0x46b4, + 0xb75b, 0xa77a, 0x9719, 0x8738, 0xf7df, 0xe7fe, 0xd79d, 0xc7bc, + 0x48c4, 0x58e5, 0x6886, 0x78a7, 0x0840, 0x1861, 0x2802, 0x3823, + 0xc9cc, 0xd9ed, 0xe98e, 0xf9af, 0x8948, 0x9969, 0xa90a, 0xb92b, + 0x5af5, 0x4ad4, 0x7ab7, 0x6a96, 0x1a71, 0x0a50, 0x3a33, 0x2a12, + 0xdbfd, 0xcbdc, 0xfbbf, 0xeb9e, 0x9b79, 0x8b58, 0xbb3b, 0xab1a, + 0x6ca6, 0x7c87, 0x4ce4, 0x5cc5, 0x2c22, 0x3c03, 0x0c60, 0x1c41, + 0xedae, 0xfd8f, 0xcdec, 0xddcd, 0xad2a, 0xbd0b, 0x8d68, 0x9d49, + 0x7e97, 0x6eb6, 0x5ed5, 0x4ef4, 0x3e13, 0x2e32, 0x1e51, 0x0e70, + 0xff9f, 0xefbe, 0xdfdd, 0xcffc, 0xbf1b, 0xaf3a, 0x9f59, 0x8f78, + 0x9188, 0x81a9, 0xb1ca, 0xa1eb, 0xd10c, 0xc12d, 0xf14e, 0xe16f, + 0x1080, 0x00a1, 0x30c2, 0x20e3, 0x5004, 0x4025, 0x7046, 0x6067, + 0x83b9, 0x9398, 0xa3fb, 0xb3da, 0xc33d, 0xd31c, 0xe37f, 0xf35e, + 0x02b1, 0x1290, 0x22f3, 0x32d2, 0x4235, 0x5214, 0x6277, 0x7256, + 0xb5ea, 0xa5cb, 0x95a8, 0x8589, 0xf56e, 0xe54f, 0xd52c, 0xc50d, + 0x34e2, 0x24c3, 0x14a0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405, + 0xa7db, 0xb7fa, 0x8799, 0x97b8, 0xe75f, 0xf77e, 0xc71d, 0xd73c, + 0x26d3, 0x36f2, 0x0691, 0x16b0, 0x6657, 0x7676, 0x4615, 0x5634, + 0xd94c, 0xc96d, 0xf90e, 0xe92f, 0x99c8, 0x89e9, 0xb98a, 0xa9ab, + 0x5844, 0x4865, 0x7806, 0x6827, 0x18c0, 0x08e1, 0x3882, 0x28a3, + 0xcb7d, 0xdb5c, 0xeb3f, 0xfb1e, 0x8bf9, 0x9bd8, 0xabbb, 0xbb9a, + 0x4a75, 0x5a54, 0x6a37, 0x7a16, 0x0af1, 0x1ad0, 0x2ab3, 0x3a92, + 0xfd2e, 0xed0f, 0xdd6c, 0xcd4d, 0xbdaa, 0xad8b, 0x9de8, 0x8dc9, + 0x7c26, 0x6c07, 0x5c64, 0x4c45, 0x3ca2, 0x2c83, 0x1ce0, 0x0cc1, + 0xef1f, 0xff3e, 0xcf5d, 0xdf7c, 0xaf9b, 0xbfba, 0x8fd9, 0x9ff8, + 0x6e17, 0x7e36, 0x4e55, 0x5e74, 0x2e93, 0x3eb2, 0x0ed1, 0x1ef0}; + +/*! \addtogroup writingImages + @{ +*/ + +/*! Prepare the specified port for MDIO bootloading. Disables the daisy-chain, + * and explicitly sets the port's provisioningAddress. */ +void AQ_API_EnableMDIO_BootLoadMode +( + /*! The target PHY port.*/ + AQ_API_Port* port, + /*! The provisioning address to use when the FW starts and applies the + * bootloaded image's provisioned values. */ + unsigned int provisioningAddress +) +{ + AQ_API_Variable(AQ_GlobalNvrProvisioning) + + AQ_API_DeclareLocalStruct(AQ_GlobalReservedProvisioning, globalReservedProvisioning) + + + /* disable the daisy-chain */ + /* REGDOC: Read-Modify-Write bitfield (HHD/APPIA: 1E.C452.0) */ + AQ_API_Set(port->PHY_ID, AQ_GlobalNvrProvisioning, nvrDaisyChainDisable, 1); + + /* override the hop-count */ + AQ_API_AssignWordOfLocalStruct(globalReservedProvisioning, 1, + /* REGDOC: Read register (HHD/APPIA: 1E.C470 + 1) */ + AQ_API_ReadRegister(port->PHY_ID, AQ_GlobalReservedProvisioning, 1)); + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C471.5:0) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalReservedProvisioning, globalReservedProvisioning, + daisy_chainHop_countOverrideValue, provisioningAddress); + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C471.6) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalReservedProvisioning, globalReservedProvisioning, + enableDaisy_chainHop_countOverride, 1); + /* REGDOC: Write register (HHD/APPIA: 1E.C470 + 1) */ + AQ_API_WriteRegister(port->PHY_ID, AQ_GlobalReservedProvisioning, 1, + AQ_API_WordOfLocalStruct(globalReservedProvisioning, 1)); + + return; +} + + +/*! Prepare the specified port for MDIO bootloading, and set the temporary MDIO + * address to be used during the bootload process. Disables the daisy-chain, + * and explicitly sets the port's provisioningAddress. */ +void AQ_API_EnableGangLoadMode +( + /*! The target PHY port.*/ + AQ_API_Port* port, + /*! The provisioning address to use when the FW starts and applies the + * bootloaded image's provisioned values. */ + unsigned int provisioningAddress, + /*! The PHY's MDIO address will be changed to this value during the + * bootload process. */ + unsigned int gangLoadAddress +) +{ + /*AQ_API_Variable_DeviceRestricted(APPIA, AQ_GlobalGeneralProvisioning)*/ + AQ_API_Variable(AQ_GlobalGeneralProvisioning) + + + /* Get ready for MDIO bootloading. */ + AQ_API_EnableMDIO_BootLoadMode(port, provisioningAddress); + + /* Enable gangload mode. After doing this, the PHY will be + * addressable at the MDIO address indicated by gangLoadAddress. + * Now that the PHY is in gangload mode, MDIO reads are prohibited + * until AQ_API_DisableGangLoadMode is called. */ + if (AQ_DEVICE_APPIA == port->device) + { + /* REGDOC: Read-Modify-Write bitfield (APPIA: 1E.C440.8:4) */ + AQ_API_Set_DeviceRestricted(APPIA, port->PHY_ID, AQ_GlobalGeneralProvisioning, + gangLoadMdioAddress, gangLoadAddress); + } + else if (AQ_DEVICE_HHD == port->device) + { + /* REGDOC: Read-Modify-Write bitfield (HHD: 1E.C447.4:0) */ + AQ_API_Set_DeviceRestricted(HHD, port->PHY_ID, AQ_GlobalGeneralProvisioning, + mdioBroadcastAddressConfiguration, gangLoadAddress); + /* REGDOC: Read-Modify-Write bitfield (HHD: 1E.C441.E) */ + AQ_API_Set_DeviceRestricted(HHD, port->PHY_ID, AQ_GlobalGeneralProvisioning, + mdioBroadcastModeEnable, 1); + } + + return; +} + + +/*! Restore the PHY's MDIO address to the pin-specified value. Should be + * called when MDIO bootloading is complete, to return to normal MDIO + * addressing. + * This is a gang-load function, hence write-only! */ +void AQ_API_DisableGangLoadMode +( + /*! The target PHY port.*/ + AQ_API_Port* port, + /*! The value to write to of AQ_GlobalGeneralProvisioning.u1.word_1. */ + uint16_t origVal_GGP1 +) +{ + AQ_API_DeclareLocalStruct(AQ_GlobalGeneralProvisioning, globalGeneralProvisioning) + + + /* Restore the original value of globalGeneralProvisioning.u1, and set + * the MDIO address reset bit. This will cause the MDIO address to be + * reset to the value indicated by the pins. */ + AQ_API_AssignWordOfLocalStruct(globalGeneralProvisioning, 1, origVal_GGP1); + if (AQ_DEVICE_APPIA == port->device) + { + /* REGDOC: Assign to local representation of bitfield (APPIA: 1E.C441.2) */ + AQ_API_AssignBitfieldOfLocalStruct_DeviceRestricted(APPIA, AQ_GlobalGeneralProvisioning, + globalGeneralProvisioning, mdioAddressReset, 1); + } + else if (AQ_DEVICE_HHD == port->device) + { + /* REGDOC: Assign to local representation of bitfield (HHD: 1E.C441.E) */ + AQ_API_AssignBitfieldOfLocalStruct_DeviceRestricted(HHD, AQ_GlobalGeneralProvisioning, + globalGeneralProvisioning, mdioBroadcastModeEnable, 0); + } + /* REGDOC: Write register (HHD/APPIA: 1E.C440 + 1) */ + AQ_API_WriteRegister(port->PHY_ID, AQ_GlobalGeneralProvisioning, 1, + AQ_API_WordOfLocalStruct(globalGeneralProvisioning, 1)); + + /* The PHY has now exited gang-load mode. */ + return; +} + + +AQ_Retcode AQ_API_WriteBootLoadImageWithProvTable +( + AQ_API_Port** ports, + unsigned int numPorts, + unsigned int* provisioningAddresses, + AQ_Retcode* resultCodes, + uint32_t* imageSizePointer, + uint8_t* image, + uint8_t gangload_MDIO_address, + AQ_API_Port* gangloadPort, + uint32_t* provTableSizePointer, + uint8_t* provTableImage +) +{ + /*------------------------------------- NOTE!!!!!!!!!! ----------------------------------------------------------*/ + /* This function uses word level writes here as in gang-load mode we cannot do a read in a read-modify-write */ + /* operation */ + /*---------------------------------------------------------------------------------------------------------------*/ + + AQ_API_Variable_DeviceRestricted(APPIA, AQ_GlobalPinStatus) + + AQ_API_DeclareLocalStruct(AQ_GlobalControl, globalControl) + AQ_API_DeclareLocalStruct(AQ_GlobalMailboxInterface, globalMailboxInterface) + + AQ_API_Port* port; + uint32_t primaryHeaderPtr = 0x00000000; + uint32_t primaryIramPtr = 0x00000000; + uint32_t primaryDramPtr = 0x00000000; + uint32_t primaryIramSize = 0x00000000; + uint32_t primaryDramSize = 0x00000000; + uint32_t terminatorPtr = 0x00000000; + uint32_t phyImageHeaderContentOffset; + uint32_t i; + uint32_t j; + uint32_t imageSize; + uint32_t provTableImageSize = 0; + uint32_t bytePointer; + uint32_t byteSize; + uint32_t dWordSize; +#ifdef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE + uint32_t countPendingOps; /* A count of block MDIO operation pending... necessary to keep a count + in order to ensure we don't exceed the maximum pending operations. */ +#endif + uint16_t msw; + uint16_t lsw; + uint16_t crc16Calculated; + uint16_t provTableCrc16Calculated; + uint16_t fileCRC; + uint16_t provTableFileCRC; + uint16_t mailboxCRC; + uint16_t mailboxWrite; + uint16_t bootLoadMode; + uint16_t recordedGGP1Values[AQ_MAX_NUM_PHY_IDS]; /* When entering/exiting gangload mode, we record and restore + the AQ_GlobalGeneralProvisioning.u1 register values. */ + + + /* store the CRC-16 for the image, which is the last two bytes */ + imageSize = *imageSizePointer; + fileCRC = image[imageSize-2] << 8 | image[imageSize-1]; + + /*------------------------------------- Check the image integrity ------------------------------------------------*/ + crc16Calculated = 0x0000; + for (i = 0; i < imageSize-2; i++) + { + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ image[i]]; + } + + if (crc16Calculated != fileCRC) + { + #ifdef AQ_VERBOSE + printf ("CRC check failed on image file (expected 0x%X, found 0x%X)\n", + fileCRC, crc16Calculated); + #endif + for (j = 0; j < numPorts; j++) + { + /* Before returning, set ALL result codes to indicate "bad image". */ + resultCodes[j] = AQ_RET_FLASH_IMAGE_CORRUPT; + } + return AQ_RET_ERROR; + } +#ifdef AQ_VERBOSE + else + { + printf ("CRC check good on image file (0x%04X)\n", crc16Calculated); + } +#endif + + /*-------------------------------- Check the provisioning table image integrity ----------------------------------*/ + if (provTableSizePointer != NULL && provTableImage != NULL) + { + provTableImageSize = (*provTableSizePointer) - 2; + provTableFileCRC = provTableImage[provTableImageSize + 1] << 8 | + provTableImage[provTableImageSize]; + + provTableCrc16Calculated = 0x0000; + for (i = 0; i < provTableImageSize; i++) + { + provTableCrc16Calculated = ((provTableCrc16Calculated & 0xFF) << 8) ^ + AQ_CRC16Table[(provTableCrc16Calculated >> 8) ^ provTableImage[i]]; + } + + if (provTableCrc16Calculated != provTableFileCRC) + { + #ifdef AQ_VERBOSE + printf ("CRC check failed on provisioning table file (expected 0x%X, found 0x%X)\n", + provTableFileCRC, provTableCrc16Calculated); + #endif + for (j = 0; j < numPorts; j++) + { + /* Before returning, set ALL result codes to indicate "bad image". */ + resultCodes[j] = AQ_RET_FLASH_IMAGE_CORRUPT; + } + return AQ_RET_ERROR; + } + #ifdef AQ_VERBOSE + else + { + printf ("CRC check good on provisioning table file (0x%04X)\n", + provTableCrc16Calculated); + } + #endif + } + + /*------------------------ Check that all provisioning addresses are in the proper range. ------------------------*/ + for (j = 0; j < numPorts; j++) + { + if (provisioningAddresses[j] > 47) + { + #ifdef AQ_VERBOSE + printf ("Provisioning address out of range 0-47 (index %u: %d)\n", j, provisioningAddresses[j]); + #endif + for (j = 0; j < numPorts; j++) + { + /* Before returning, set ALL result codes to indicate "provisioning address out-of-range". */ + resultCodes[j] = AQ_RET_BOOTLOAD_PROVADDR_OOR; + } + return AQ_RET_ERROR; + } + } + + /*--------------------------- Store 1E.C441 values for later use. Enforce uniformity. ---------------------------*/ + for (j = 0; j < numPorts; j++) + { + /* Record the original value of AQ_GlobalGeneralProvisioning.u1.word_1, + * so that we can restore it later after exiting gangload mode. */ + port = ports[j]; + /* REGDOC: Read register (HHD/APPIA: 1E.C440 + 1) */ + recordedGGP1Values[j] = AQ_API_ReadRegister(port->PHY_ID, AQ_GlobalGeneralProvisioning, 1); + + /* If any of the PHYs' GGP1 values don't match the others, set the appropriate + * error code and return. */ + if (j > 0 && recordedGGP1Values[j] != recordedGGP1Values[0]) + { + #ifdef AQ_VERBOSE + printf ("Non-uniform value of 1E.C441 found (expected 0x%X, found 0x%X)\n", + recordedGGP1Values[0], recordedGGP1Values[j]); + #endif + for (j = 0; j < numPorts; j++) + { + /* Before returning, set ALL result codes to indicate "non-uniform GGP1 values". */ + resultCodes[j] = AQ_RET_BOOTLOAD_NONUNIFORM_REGVALS; + } + return AQ_RET_ERROR; + } + } + + /*--------------------------- Put each PHY into gangload mode at the specified address ---------------------------*/ + for (j = 0; j < numPorts; j++) + { + AQ_API_EnableGangLoadMode(ports[j], provisioningAddresses[j], gangload_MDIO_address); + } + /* Set up the port context for using device-restricted macros while in + * gangload mode. */ + port = gangloadPort; + + /*------------------------------------- Stall the uP ------------------------------------------------------------*/ + AQ_API_AssignWordOfLocalStruct(globalControl, 1, 0x0000); + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.6) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upRunStallOverride, 1); + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.0) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upRunStall, 1); + /* REGDOC: Write register (HHD/APPIA: 1E.C000 + 1) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalControl, 1, + AQ_API_WordOfLocalStruct(globalControl, 1)); + + /*------------------------------------- Initialize the mailbox write command -------------------------------------*/ + AQ_API_AssignWordOfLocalStruct(globalMailboxInterface, 0, 0x0000); + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.0200.E) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalMailboxInterface, globalMailboxInterface, upMailboxWriteMode, 1); + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.0200.F) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalMailboxInterface, globalMailboxInterface, upMailboxExecuteOperation, 1); + mailboxWrite = AQ_API_WordOfLocalStruct(globalMailboxInterface, 0); + + /*------------------------------------- Read the segment addresses and sizes -------------------------------------*/ + primaryHeaderPtr = (((image[0x9] & 0x0F) << 8) | image[0x8]) << 12; + + if (AQ_DEVICE_APPIA == port->device) + phyImageHeaderContentOffset = AQ_PHY_IMAGE_HEADER_CONTENT_OFFSET_APPIA; + else /* HHD */ + phyImageHeaderContentOffset = AQ_PHY_IMAGE_HEADER_CONTENT_OFFSET_HHD; + + primaryIramPtr = (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0x4 + 2] << 16) | + (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0x4 + 1] << 8) | + image[primaryHeaderPtr + phyImageHeaderContentOffset + 0x4]; + primaryIramSize = (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0x7 + 2] << 16) | + (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0x7 + 1] << 8) | + image[primaryHeaderPtr + phyImageHeaderContentOffset + 0x7]; + primaryDramPtr = (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0xA + 2] << 16) | + (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0xA + 1] << 8) | + image[primaryHeaderPtr + phyImageHeaderContentOffset + 0xA]; + primaryDramSize = (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0xD + 2] << 16) | + (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0xD + 1] << 8) | + image[primaryHeaderPtr + phyImageHeaderContentOffset + 0xD]; + + if (AQ_DEVICE_HHD == port->device) + { + primaryIramPtr += primaryHeaderPtr; + primaryDramPtr += primaryHeaderPtr; + } + +#ifdef AQ_VERBOSE + printf ("\nSegment Addresses and Sizes as read from the PHY ROM image header:\n\n"); + printf ("Primary Iram Address: 0x%x\n", primaryIramPtr); + printf ("Primary Iram Size: 0x%x\n", primaryIramSize); + printf ("Primary Dram Address: 0x%x\n", primaryDramPtr); + printf ("Primary Dram Size: 0x%x\n\n", primaryDramSize); +#endif + + /*----------------------------- Merge the provisioning table into the main image ---------------------------------*/ + if (provTableSizePointer != NULL && provTableImage != NULL) + { + /* Locate the terminator of the built-in provisioning table */ + terminatorPtr = primaryDramPtr + + ((image[primaryDramPtr + AQ_PHY_IMAGE_PROVTABLE_TERM_OFFSET + 1] << 8) | + image[primaryDramPtr + AQ_PHY_IMAGE_PROVTABLE_TERM_OFFSET]); + + #ifdef AQ_VERBOSE + printf("Supplied Provisioning Table At Address: 0x%x\n\n", terminatorPtr); + #endif + + /* Check that the supplied provisioning table will fit within the alloted + * space. */ + if (terminatorPtr - (primaryDramPtr + AQ_PHY_IMAGE_PROVTABLE_OFFSET) + + provTableImageSize > AQ_PHY_IMAGE_PROVTABLE_MAXSIZE) + { + for (j = 0; j < numPorts; j++) + { + /* Before returning, set ALL result codes to indicate "provisioning + * table too large". */ + resultCodes[j] = AQ_RET_BOOTLOAD_PROVTABLE_TOO_LARGE; + } + return AQ_RET_ERROR; + } + + /* Write the supplied provisioning table into the image, starting at the + * terminator address. */ + for (i = 0; i < provTableImageSize; i++) + { + image[terminatorPtr + i] = provTableImage[i]; + } + } + + /*------------------------------------- Load IRAM and DRAM -------------------------------------------------------*/ + /* clear the mailbox CRC */ + AQ_API_AssignWordOfLocalStruct(globalMailboxInterface, 0, 0x0000); + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.0200.C) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalMailboxInterface, globalMailboxInterface, resetUpMailboxCrc, 1); + /* REGDOC: Write register (HHD/APPIA: 1E.0200) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, + AQ_API_WordOfLocalStruct(globalMailboxInterface, 0)); + /* REGDOC: Write register (HHD/APPIA: 1E.0200) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, 0x0000); + + crc16Calculated = 0; /* This is to calculate what was written through the mailbox */ + + /* load the IRAM */ +#ifdef AQ_VERBOSE + printf ("\nLoading IRAM:\n\n"); +#endif + + /* dWord align the address: note the image addressing is byte based, but is properly aligned on dWord + boundaries, so the 2 LSbits of the block start are always zero. */ + msw = (uint16_t) (AQ_IRAM_BASE_ADDRESS >> 16); + AQ_API_AssignWordOfLocalStruct(globalMailboxInterface, 3, 0x0000); + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.0203.1:0) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalMailboxInterface, globalMailboxInterface, + upMailboxAddressLSW , (AQ_IRAM_BASE_ADDRESS & 0xFFFF) >> 2); + lsw = AQ_API_WordOfLocalStruct(globalMailboxInterface, 3); + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 2) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 2, msw); /* MSW */ + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 3) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 3, lsw); /* LSW */ + + + /* set block size so that there are from 0-3 bytes remaining */ + byteSize = primaryIramSize; + dWordSize = byteSize >> 2; + + bytePointer = primaryIramPtr; +#ifdef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE + countPendingOps = 0; +#endif + for (i = 0; i < dWordSize; i++) + { + /* write 4 bytes of data */ + lsw = (image[bytePointer+1] << 8) | image[bytePointer]; + bytePointer += 2; + msw = (image[bytePointer+1] << 8) | image[bytePointer]; + bytePointer += 2; + + #ifdef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE + AQ_API_BlockWriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 4, msw); + AQ_API_BlockWriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 5, lsw); + AQ_API_BlockWriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, mailboxWrite); + + countPendingOps += 3; + /* Check if we've filled our output buffer, and if so, flush. */ + if (countPendingOps >= AQ_API_MDIO_MaxBlockOperations() - 3 ) + { + AQ_API_MDIO_BlockOperationExecute (gangloadPort->PHY_ID); + countPendingOps = 0; + } + #else + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 4) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 4, msw); + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 5) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 5, lsw); + /* REGDOC: Write register (HHD/APPIA: 1E.0200) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, mailboxWrite); + #endif + + /* update the calculated CRC */ + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (msw >> 8)]; + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (msw & 0xFF)]; + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (lsw >> 8)]; + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (lsw & 0xFF)]; + + #ifdef AQ_VERBOSE + if (i && ((i % 512) == 0)) printf(" Byte: %X:\n", i << 2); + #endif + } + +#ifdef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE + /* flush the output buffer one last time. */ + AQ_API_MDIO_BlockOperationExecute(gangloadPort->PHY_ID); + countPendingOps = 0; +#endif + + /* Note: this final write right-justifies non-dWord data in the final dWord */ + switch (byteSize & 0x3) + { + case 0x1: + /* write 1 byte of data */ + lsw = image[bytePointer++]; + msw = 0x0000; + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 4) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 4, msw); + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 5) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 5, lsw); + + /* no polling */ + /* REGDOC: Write register (HHD/APPIA: 1E.0200) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, mailboxWrite); + break; + + case 0x2: + /* write 2 bytes of data */ + lsw = (image[bytePointer+1] << 8) | image[bytePointer]; + bytePointer += 2; + msw = 0x0000; + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 4) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 4, msw); + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 5) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 5, lsw); + + /* no polling */ + /* REGDOC: Write register (HHD/APPIA: 1E.0200) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, mailboxWrite); + break; + + case 0x3: + /* write 3 bytes of data */ + lsw = (image[bytePointer+1] << 8) | image[bytePointer]; + bytePointer += 2; + msw = image[bytePointer++]; + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 4) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 4, msw); + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 5) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 5, lsw); + + /* no polling */ + /* REGDOC: Write register (HHD/APPIA: 1E.0200) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, mailboxWrite); + break; + } + + if (byteSize & 0x3) + { + /* update the calculated CRC */ + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (msw >> 8)]; + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (msw & 0xFF)]; + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (lsw >> 8)]; + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (lsw & 0xFF)]; + } + + /* load the DRAM */ +#ifdef AQ_VERBOSE + printf ("\nCRC-16 after loading IRAM: 0x%X\n", crc16Calculated); + printf ("\nLoading DRAM:\n\n"); +#endif + + /* dWord align the address: note the image addressing is byte based, but is properly aligned on dWord + boundaries, so the 2 LSbits of the block start are always zero. */ + msw = (uint16_t) (AQ_DRAM_BASE_ADDRESS >> 16); + AQ_API_AssignWordOfLocalStruct(globalMailboxInterface, 3, 0x0000); + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.0203.1:0) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalMailboxInterface, globalMailboxInterface, + upMailboxAddressLSW, (AQ_DRAM_BASE_ADDRESS & 0xFFFF) >> 2); + lsw = AQ_API_WordOfLocalStruct(globalMailboxInterface, 3); + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 2) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 2, msw); /* MSW */ + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 3) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 3, lsw); /* LSW */ + + + /* set block size so that there are from 0-3 bytes remaining */ + byteSize = primaryDramSize; + dWordSize = byteSize >> 2; + + bytePointer = primaryDramPtr; + for (i = 0; i < dWordSize; i++) + { + /* write 4 bytes of data */ + lsw = (image[bytePointer+1] << 8) | image[bytePointer]; + bytePointer += 2; + msw = (image[bytePointer+1] << 8) | image[bytePointer]; + bytePointer += 2; + + #ifdef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE + AQ_API_BlockWriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 4, msw); + AQ_API_BlockWriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 5, lsw); + AQ_API_BlockWriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, mailboxWrite); + + countPendingOps += 3; + /* Check if we've filled our output buffer, and if so, flush. */ + if (countPendingOps >= AQ_API_MDIO_MaxBlockOperations() - 3 ) + { + AQ_API_MDIO_BlockOperationExecute (gangloadPort->PHY_ID); + countPendingOps = 0; + } + #else + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 4) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 4, msw); + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 5) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 5, lsw); + /* REGDOC: Write register (HHD/APPIA: 1E.0200) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, mailboxWrite); + #endif + + /* update the calculated CRC */ + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (msw >> 8)]; + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (msw & 0xFF)]; + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (lsw >> 8)]; + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (lsw & 0xFF)]; + + #ifdef AQ_VERBOSE + if (i && ((i % 512) == 0)) printf(" Byte: %X:\n", i << 2); + #endif + } + +#ifdef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE + /* flush the output buffer one last time. */ + AQ_API_MDIO_BlockOperationExecute(gangloadPort->PHY_ID); + countPendingOps = 0; +#endif + + /* Note: this final write right-justifies non-dWord data in the final dWord */ + switch (byteSize & 0x3) + { + case 0x1: + /* write 1 byte of data */ + lsw = image[bytePointer++]; + msw = 0x0000; + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 4) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 4, msw); + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 5) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 5, lsw); + + /* no polling */ + /* REGDOC: Write register (HHD/APPIA: 1E.0200) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, mailboxWrite); + break; + + case 0x2: + /* write 2 bytes of data */ + lsw = (image[bytePointer+1] << 8) | image[bytePointer]; + bytePointer += 2; + msw = 0x0000; + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 4) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 4, msw); + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 5) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 5, lsw); + + /* no polling */ + /* REGDOC: Write register (HHD/APPIA: 1E.0200) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, mailboxWrite); + break; + + case 0x3: + /* write 3 bytes of data */ + lsw = (image[bytePointer+1] << 8) | image[bytePointer]; + bytePointer += 2; + msw = image[bytePointer++]; + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 4) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 4, msw); + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 5) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 5, lsw); + + /* no polling */ + /* REGDOC: Write register (HHD/APPIA: 1E.0200) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, mailboxWrite); + break; + } + + if (byteSize & 0x3) + { + /* update the calculated CRC */ + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (msw >> 8)]; + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (msw & 0xFF)]; + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (lsw >> 8)]; + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (lsw & 0xFF)]; + } + + /*------------------------------------- Exit gangload mode -------------------------------------------------------*/ + AQ_API_DisableGangLoadMode(gangloadPort, recordedGGP1Values[0]); + + /*------------------------------------- Check mailbox CRCs -------------------------------------------------------*/ + /* check to make sure the mailbox CRC matches the calculated CRC */ + /*foundMailboxCRCMismatch = False;*/ + for (j = 0; j < numPorts; j++) + { + /* REGDOC: Read register (HHD/APPIA: 1E.0200 + 1) */ + mailboxCRC = AQ_API_ReadRegister(ports[j]->PHY_ID,AQ_GlobalMailboxInterface, 1); + if (mailboxCRC != crc16Calculated) + { + #ifdef AQ_VERBOSE + printf("\n%uth port: Mailbox CRC-16 (0x%X) does not match calculated CRC-16 (0x%X)\n", + j, mailboxCRC, crc16Calculated); + #endif + /* Note that we can't just return here, because we still need to + * release the uPs for the other PHYs that might have been + * bootloaded successfully. */ + resultCodes[j] = AQ_RET_BOOTLOAD_CRC_MISMATCH; + } + #ifdef AQ_VERBOSE + else + { + printf("\n%uth port: Image load good - mailbox CRC-16 matches (0x%X)\n", + j, mailboxCRC); + resultCodes[j] = AQ_RET_OK; + } + #endif + } + + /*------------------------------------- Clear any resets ---------------------------------------------------------*/ + for (j = 0; j < numPorts; j++) + { + /* REGDOC: Write register (HHD/APPIA: 1E.0000) */ + AQ_API_WriteRegister(ports[j]->PHY_ID,AQ_GlobalStandardControl_1, 0, 0x0000); + } + + /*------------------------------------- Release the uP -----------------------------------------------------------*/ + AQ_API_AssignWordOfLocalStruct(globalControl, 1, 0x0000); + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.6) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upRunStallOverride, 1); + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.0) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upRunStall, 1); + for (j = 0; j < numPorts; j++) + { + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.F) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upReset, 0); + /* REGDOC: Write register (HHD/APPIA: 1E.C000 + 1) */ + AQ_API_WriteRegister(ports[j]->PHY_ID,AQ_GlobalControl, 1, + AQ_API_WordOfLocalStruct(globalControl, 1)); + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.F) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upReset, 1); + /* REGDOC: Write register (HHD/APPIA: 1E.C000 + 1) */ + AQ_API_WriteRegister(ports[j]->PHY_ID,AQ_GlobalControl, 1, + AQ_API_WordOfLocalStruct(globalControl, 1)); + } + + /* Need to wait at least 100us. */ + AQ_API_Wait(1, ports[0]); + + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.F) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upReset, 0); + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.0) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upRunStall, 0); + for (j = 0; j < numPorts; j++) + { + if (AQ_DEVICE_APPIA == port->device) + { + /* If the BOOT_LD pins are set to MDIO boot load mode, we can't clear the + * uP run stall override bit. If we did, the uP would stall. */ + /* REGDOC: Read bitfield (APPIA: 1E.C840.E:D) */ + AQ_API_Get_DeviceRestricted(APPIA, j, AQ_GlobalPinStatus, mdioBootLoad, bootLoadMode); + if (bootLoadMode == 0x1) + { + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.6) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upRunStallOverride, 1); + } + else + { + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.6) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upRunStallOverride, 0); + } + } + else + { + /* For post-APPIA devices, always set the uP stall override bit to + * smooth over any packaging differences WRT the boot load pin. */ + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.6) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upRunStallOverride, 1); + } + + /* REGDOC: Write register (HHD/APPIA: 1E.C000 + 1) */ + AQ_API_WriteRegister(ports[j]->PHY_ID,AQ_GlobalControl, 1, + AQ_API_WordOfLocalStruct(globalControl, 1)); + } + + /* NOTE!!! We can't re-enable the daisy-chain here, as this will overwrite the IRAM and DRAM with the FLASH contents*/ + + /* If any of the ports was not bootloaded successfully, return AQ_RET_ERROR */ + for (j = 0; j < numPorts; j++) + { + if (resultCodes[j] != AQ_RET_OK) + return AQ_RET_ERROR; + } + + /* All ports were bootloaded successfully. */ + return AQ_RET_OK; +} + + +AQ_Retcode AQ_API_WriteBootLoadImage +( + AQ_API_Port** ports, + unsigned int numPorts, + unsigned int* provisioningAddresses, + AQ_Retcode* resultCodes, + uint32_t* imageSizePointer, + uint8_t* image, + uint8_t gangload_MDIO_address, + AQ_API_Port* gangloadPort +) +{ + return AQ_API_WriteBootLoadImageWithProvTable(ports, numPorts, + provisioningAddresses, resultCodes, imageSizePointer, image, + gangload_MDIO_address, gangloadPort, NULL, NULL); +} + + +AQ_Retcode AQ_API_EnableDaisyChain +( + /*! The target PHY port.*/ + AQ_API_Port* port +) +{ + + /* declare local variables */ + AQ_API_Variable(AQ_GlobalNvrProvisioning) + AQ_API_Variable(AQ_GlobalReservedProvisioning) + + /* disable the hop-count override */ + /* REGDOC: Read-Modify-Write bitfield (HHD/APPIA: 1E.C471.6) */ + AQ_API_Set(port->PHY_ID, AQ_GlobalReservedProvisioning, enableDaisy_chainHop_countOverride, 0); + + /* enable the daisy-chain */ + /* REGDOC: Read-Modify-Write bitfield (HHD/APPIA: 1E.C452.0) */ + AQ_API_Set(port->PHY_ID, AQ_GlobalNvrProvisioning, nvrDaisyChainDisable, 0); + + return AQ_RET_OK; +} + +/*@}*/ + + +#ifdef __cplusplus +} +#endif diff --git a/qca/aq-fw-download/src/src/AQ_PhyInterface.c b/qca/aq-fw-download/src/src/AQ_PhyInterface.c new file mode 100644 index 000000000..6a8fce125 --- /dev/null +++ b/qca/aq-fw-download/src/src/AQ_PhyInterface.c @@ -0,0 +1,141 @@ +/* AQ_PhyInterface.c */ + +/************************************************************************************ +* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +* +* $Revision: #12 $ +* +* $DateTime: 2015/02/25 15:34:49 $ +* +* $Label: $ +* +************************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include "AQ_PhyInterface.h" +#include "AQ_PlatformRoutines.h" + +#define MII_ADDR_C45 (0x8000) + +extern int sock; +extern char devname[7]; + +static struct ifreq ifr; + +/*! Provides generic synchronous PHY register write functionality. It is the + * responsibility of the system designer to provide the specific MDIO address + * pointer updates, etc. in order to accomplish this write operation. + * It will be assumed that the write has been completed by the time this + * function returns.*/ +void AQ_API_MDIO_Write( + /*! Uniquely identifies the port within the system. AQ_Port must be + * defined to a whatever data type is suitable for the platform.*/ + AQ_Port PHY_ID, + /*! The address of the MMD within the target PHY. */ + unsigned int MMD, + /*! The 16-bit address of the PHY register being written. */ + unsigned int address, + /*! The 16-bits of data to write to the specified PHY register. */ + unsigned int data) +{ + struct mii_ioctl_data mii; + + /* + * Frame the control structures + * and send the ioctl to kernel. + */ + memset(&ifr, 0, sizeof(ifr)); + strlcpy(ifr.ifr_name, devname, sizeof(ifr.ifr_name)); + memset(&mii, 0, sizeof(mii)); + memcpy(&mii, &ifr.ifr_data, sizeof(mii)); + mii.phy_id = MII_ADDR_C45 | PHY_ID << 5 | MMD; + mii.reg_num = address; + mii.val_in = data; + memcpy(&ifr.ifr_data, &mii, sizeof(mii)); + + if (ioctl(sock, SIOCSMIIREG, &ifr) < 0) { + fprintf(stderr, "SIOCSMIIREG on %s failed: %s\n", ifr.ifr_name, + strerror(errno)); + } + + return; +} + +/*! Provides generic synchronous PHY register read functionality. It is the + * responsibility of the system designer to provide the specific MDIO address + * pointer updates, etc. in order to accomplish this read operation.*/ +unsigned int AQ_API_MDIO_Read +( + /*! Uniquely identifies the port within the system. AQ_Port must be + * defined to a whatever data type is suitable for the platform.*/ + AQ_Port PHY_ID, + /*! The address of the MMD within the target PHY. */ + unsigned int MMD, + /*! The 16-bit address of the PHY register being read. */ + unsigned int address) +{ + struct mii_ioctl_data mii; + + /* + * Frame the control structures + * and send the ioctl to kernel. + */ + memset(&ifr, 0, sizeof(ifr)); + strlcpy(ifr.ifr_name, devname, sizeof(ifr.ifr_name)); + memset(&mii, 0, sizeof(mii)); + memcpy(&mii, &ifr.ifr_data, sizeof(mii)); + mii.phy_id = MII_ADDR_C45 | PHY_ID << 5 | MMD; + mii.reg_num = address; + memcpy(&ifr.ifr_data, &mii, sizeof(mii)); + + if (ioctl(sock, SIOCGMIIREG, &ifr) < 0) { + fprintf(stderr, "SIOCGMIIREG on %s failed: %s\n", ifr.ifr_name, + strerror(errno)); + return -1; + } else { + memcpy(&mii, &ifr.ifr_data, sizeof(mii)); + } + + + return mii.val_out; +} + +/*! Returns after at least milliseconds have elapsed. This must be implemented + * * in a platform-approriate way. AQ_API functions will call this function to + * * block for the specified period of time. If necessary, PHY register reads + * * may be performed on port to busy-wait. */ +void AQ_API_Wait( + uint32_t milliseconds, /*!< The delay in milliseconds */ + AQ_API_Port* port /*!< The PHY to use if delay reads are necessary*/ ) +{ + unsigned long long mirco = milliseconds *1000; + usleep(mirco); +} diff --git a/qca/nss-eip-firmware/Makefile b/qca/nss-eip-firmware/Makefile new file mode 100644 index 000000000..a20c9afd6 --- /dev/null +++ b/qca/nss-eip-firmware/Makefile @@ -0,0 +1,34 @@ +include $(TOPDIR)/rules.mk + +PKG_NAME:=nss-eip-firmware +PKG_VERSION=2.5.7 +PKG_RELEASE:=$(AUTORELEASE) + +PKG_MAINTAINER:=Robert Marko + +include $(INCLUDE_DIR)/package.mk + +define Package/nss-eip-firmware + SECTION:=firmware + CATEGORY:=Firmware + TITLE:=NSS EIP-197 firmware + DEPENDS:=@(TARGET_ipq807x||TARGET_ipq60xx) +endef + +define Build/Compile + +endef + +define Package/nss-eip-firmware/install + $(INSTALL_DIR) $(1)/lib/firmware/ + $(INSTALL_DATA) \ + $(PKG_BUILD_DIR)/ifpp.bin $(1)/lib/firmware/ifpp.bin + $(INSTALL_DATA) \ + $(PKG_BUILD_DIR)/ipue.bin $(1)/lib/firmware/ipue.bin + $(INSTALL_DATA) \ + $(PKG_BUILD_DIR)/ofpp.bin $(1)/lib/firmware/ofpp.bin + $(INSTALL_DATA) \ + $(PKG_BUILD_DIR)/opue.bin $(1)/lib/firmware/opue.bin +endef + +$(eval $(call BuildPackage,nss-eip-firmware)) diff --git a/qca/nss-eip-firmware/src/.gitkeep b/qca/nss-eip-firmware/src/.gitkeep new file mode 100644 index 000000000..e69de29bb diff --git a/qca/nss-firmware/Makefile b/qca/nss-firmware/Makefile new file mode 100644 index 000000000..eff44a8fb --- /dev/null +++ b/qca/nss-firmware/Makefile @@ -0,0 +1,72 @@ +# +# Copyright (C) 2021 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +include $(TOPDIR)/rules.mk + +PKG_NAME:=nss-firmware +PKG_SOURCE_DATE:=2022-05-16 +PKG_SOURCE_VERSION:=20c9a9b7e0ea2935b0a54f112104e433009312ca +PKG_MIRROR_HASH:=376b3605776f75bccb1da2b30dd522cc22d3f6b17dff6c954dd9b7222418d6c6 +PKG_RELEASE:=$(AUTORELEASE) + +PKG_SOURCE_PROTO:=git +PKG_SOURCE_URL:=https://github.com/quic/qca-sdk-nss-fw.git + +PKG_LICENSE_FILES:=LICENSE.md + +PKG_MAINTAINER:=Robert Marko + +include $(INCLUDE_DIR)/package.mk + +VERSION_PATH=$(PKG_BUILD_DIR)/QCA_Networking.SPF_11.5.0/CS + +define Package/nss-firmware-default + SECTION:=firmware + CATEGORY:=Firmware + URL:=$(PKG_SOURCE_URL) + DEPENDS:=@(TARGET_ipq807x||TARGET_ipq60xx) +endef + +define Package/nss-firmware-ipq6018 +$(Package/nss-firmware-default) + TITLE:=NSS firmware for IPQ6018 devices + NSS_ARCHIVE:=$(VERSION_PATH)/IPQ6018.ATH.11.4/BIN-NSS.CP.11.4.0.5-5-R.tar.bz2 +endef + +define Package/nss-firmware-ipq8074 +$(Package/nss-firmware-default) + TITLE:=NSS firmware for IPQ8074 devices + NSS_ARCHIVE:=$(VERSION_PATH)/IPQ8074.ATH.11.5.0/BIN-NSS.FW.12.0.r1-002-HK.R.tar.bz2 +endef + +define Build/Compile + +endef + +define Package/nss-firmware-ipq6018/install + mkdir -p $(PKG_BUILD_DIR)/IPQ6018 + $(TAR) -C $(PKG_BUILD_DIR)/IPQ6018 -xf $(NSS_ARCHIVE) --strip-components=1 + $(INSTALL_DIR) $(1)/lib/firmware/ + $(INSTALL_DATA) \ + $(PKG_BUILD_DIR)/IPQ6018/retail_router0.bin \ + $(1)/lib/firmware/qca-nss0-retail.bin +endef + +define Package/nss-firmware-ipq8074/install + mkdir -p $(PKG_BUILD_DIR)/IPQ8074 + $(TAR) -C $(PKG_BUILD_DIR)/IPQ8074 -xf $(NSS_ARCHIVE) --strip-components=1 + $(INSTALL_DIR) $(1)/lib/firmware/ + $(INSTALL_DATA) \ + $(PKG_BUILD_DIR)/IPQ8074/retail_router0.bin \ + $(1)/lib/firmware/qca-nss0-retail.bin + $(INSTALL_DATA) \ + $(PKG_BUILD_DIR)/IPQ8074/retail_router1.bin \ + $(1)/lib/firmware/qca-nss1-retail.bin +endef + +$(eval $(call BuildPackage,nss-firmware-ipq6018)) +$(eval $(call BuildPackage,nss-firmware-ipq8074)) diff --git a/qca/qca-nss-cfi/Makefile b/qca/qca-nss-cfi/Makefile new file mode 100644 index 000000000..64f7bd7ab --- /dev/null +++ b/qca/qca-nss-cfi/Makefile @@ -0,0 +1,71 @@ +include $(TOPDIR)/rules.mk + +PKG_NAME:=qca-nss-cfi +PKG_RELEASE:=1 + +PKG_SOURCE_PROTO:=git +PKG_SOURCE_DATE:=2021-03-22 +PKG_SOURCE_URL:=https://source.codeaurora.org/quic/qsdk/oss/lklm/nss-cfi +PKG_SOURCE_VERSION:=73f2e5f5bf93cc244036ce5641faf9f859692cdf +PKG_MIRROR_HASH:=8c8edc9b8d8c68fdd14640152245013a93c123957b6b338c06f266f6c9db8cbd + +include $(INCLUDE_DIR)/kernel.mk +include $(INCLUDE_DIR)/package.mk + +# v1.0 is for Akronite +# v2.0 is for Hawkeye/Cypress/Maple +ifneq (, $(findstring $(BOARD), ipq50xx ipq60xx ipq807x)) + CFI_OCF_DIR:=ocf/v2.0 + CFI_CRYPTOAPI_DIR:=cryptoapi/v2.0 +else + CFI_CRYPTOAPI_DIR:=cryptoapi/v1.1 + CFI_OCF_DIR:=ocf/v1.0 + CFI_IPSEC_DIR:=ipsec/v1.0 +endif + +define KernelPackage/qca-nss-cfi-cryptoapi + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + DEPENDS:=@TARGET_ipq60xx +kmod-crypto-authenc +kmod-qca-nss-crypto + TITLE:=Kernel driver for NSS cfi + FILES:=$(PKG_BUILD_DIR)/$(CFI_CRYPTOAPI_DIR)/qca-nss-cfi-cryptoapi.ko + AUTOLOAD:=$(call AutoLoad,59,qca-nss-cfi-cryptoapi) +endef + +define Build/InstallDev + $(INSTALL_DIR) $(1)/usr/include/qca-nss-cfi + $(CP) $(PKG_BUILD_DIR)/$(CFI_CRYPTOAPI_DIR)/../exports/* $(1)/usr/include/qca-nss-cfi + $(CP) $(PKG_BUILD_DIR)/include/* $(1)/usr/include/qca-nss-cfi +endef + +define KernelPackage/qca-nss-cfi/Description +This package contains a NSS cfi driver for QCA chipset +endef + +EXTRA_CFLAGS+= \ + -DCONFIG_NSS_DEBUG_LEVEL=4 \ + -I$(LINUX_DIR)/crypto/ocf \ + -I$(STAGING_DIR)/usr/include/qca-nss-crypto \ + -I$(STAGING_DIR)/usr/include/crypto \ + -I$(STAGING_DIR)/usr/include/qca-nss-drv + +ifneq (, $(findstring $(BOARD), ipq50xx ipq60xx ipq807x)) +EXTRA_CFLAGS+= -I$(STAGING_DIR)/usr/include/qca-nss-clients +endif + +define Build/Compile + $(MAKE) -C "$(LINUX_DIR)" \ + CROSS_COMPILE="$(TARGET_CROSS)" \ + EXTRA_CFLAGS="$(EXTRA_CFLAGS)" \ + CFI_CRYPTOAPI_DIR=$(CFI_CRYPTOAPI_DIR) \ + CFI_IPSEC_DIR=$(CFI_IPSEC_DIR) \ + CFI_OCF_DIR=$(CFI_OCF_DIR) \ + $(KERNEL_MAKE_FLAGS) \ + M="$(PKG_BUILD_DIR)" \ + SoC="$(BOARD)_64" \ + "cryptoapi=y" \ + modules +endef + +$(eval $(call KernelPackage,qca-nss-cfi-cryptoapi)) diff --git a/qca/qca-nss-cfi/patches/100-remove-noise-logs.patch b/qca/qca-nss-cfi/patches/100-remove-noise-logs.patch new file mode 100644 index 000000000..085aeaf24 --- /dev/null +++ b/qca/qca-nss-cfi/patches/100-remove-noise-logs.patch @@ -0,0 +1,30 @@ +--- a/cryptoapi/v2.0/nss_cryptoapi_ahash.c ++++ b/cryptoapi/v2.0/nss_cryptoapi_ahash.c +@@ -449,9 +449,12 @@ int nss_cryptoapi_ahash_digest(struct ahash_request *req) + int nss_cryptoapi_ahash_export(struct ahash_request *req, void *out) + { + struct nss_cryptoapi_ctx *ctx __attribute__((unused)) = crypto_tfm_ctx(req->base.tfm); ++ struct nss_cryptoapi_req_ctx *rctx = ahash_request_ctx(req); ++ struct nss_cryptoapi_req_ctx *state = out; ++ ++ *state = *rctx; + +- nss_cfi_warn("%px: ahash .export is not supported", ctx); +- return -ENOSYS; ++ return 0; + }; + + /* +@@ -464,7 +467,10 @@ int nss_cryptoapi_ahash_export(struct ahash_request *req, void *out) + int nss_cryptoapi_ahash_import(struct ahash_request *req, const void *in) + { + struct nss_cryptoapi_ctx *ctx __attribute__((unused)) = crypto_tfm_ctx(req->base.tfm); ++ struct nss_cryptoapi_req_ctx *rctx = ahash_request_ctx(req); ++ const struct nss_cryptoapi_req_ctx *state = in; ++ ++ *rctx = *state; + +- nss_cfi_warn("%px: ahash .import is not supported", ctx); +- return -ENOSYS; ++ return 0; + } diff --git a/qca/qca-nss-clients/Makefile b/qca/qca-nss-clients/Makefile new file mode 100644 index 000000000..274512780 --- /dev/null +++ b/qca/qca-nss-clients/Makefile @@ -0,0 +1,102 @@ +include $(TOPDIR)/rules.mk + +PKG_NAME:=qca-nss-clients +PKG_RELEASE:=$(AUTORELEASE) + +PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/nss-clients.git +PKG_SOURCE_PROTO:=git +PKG_SOURCE_DATE:=2021-07-23 +PKG_SOURCE_VERSION:=ec7a57bed8914adcbd5bf95de1f0b630296489c1 +PKG_MIRROR_HASH:=b7413c5b20a341d3d7ea49c1b86ff92b4a8795aa7c64986ca820ba18205e332d + +include $(INCLUDE_DIR)/kernel.mk +include $(INCLUDE_DIR)/package.mk + +define KernelPackage/qca-nss-drv-pppoe + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=Kernel driver for NSS (connection manager) - PPPoE + DEPENDS:=@LINUX_5_10 @TARGET_ipq807x +kmod-qca-nss-drv +kmod-ppp +kmod-pppoe + FILES:=$(PKG_BUILD_DIR)/pppoe/qca-nss-pppoe.ko + AUTOLOAD:=$(call AutoLoad,51,qca-nss-pppoe) +endef + +define KernelPackage/qca-nss-drv-pppoe/Description +Kernel modules for NSS connection manager - Support for PPPoE +endef + +define KernelPackage/qca-nss-drv-bridge-mgr + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=Kernel driver for NSS bridge manager + DEPENDS:=@LINUX_5_10 @TARGET_ipq807x +kmod-qca-nss-drv +kmod-qca-nss-drv-vlan-mgr + FILES:=$(PKG_BUILD_DIR)/bridge/qca-nss-bridge-mgr.ko + AUTOLOAD:=$(call AutoLoad,51,qca-nss-bridge-mgr) +endef + +define KernelPackage/qca-nss-drv-bridge-mgr/Description +Kernel modules for NSS bridge manager +endef + +define KernelPackage/qca-nss-drv-vlan-mgr + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=Kernel driver for NSS vlan manager + DEPENDS:=@LINUX_5_10 @TARGET_ipq807x +kmod-qca-nss-drv + FILES:=$(PKG_BUILD_DIR)/vlan/qca-nss-vlan.ko + AUTOLOAD:=$(call AutoLoad,51,qca-nss-vlan) +endef + +define KernelPackage/qca-nss-drv-vlan-mgr/Description +Kernel modules for NSS vlan manager +endef + +EXTRA_CFLAGS+= \ + -I$(STAGING_DIR)/usr/include/qca-nss-drv \ + -I$(STAGING_DIR)/usr/include/qca-nss-crypto \ + -I$(STAGING_DIR)/usr/include/qca-nss-cfi \ + -I$(STAGING_DIR)/usr/include/qca-nss-gmac \ + -I$(STAGING_DIR)/usr/include/qca-ssdk \ + -I$(STAGING_DIR)/usr/include/qca-ssdk/fal \ + -I$(STAGING_DIR)/usr/include/nat46 + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-pppoe),) +NSS_CLIENTS_MAKE_OPTS+=pppoe=y +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-bridge-mgr),) +NSS_CLIENTS_MAKE_OPTS+=bridge-mgr=y +#enable OVS bridge if ovsmgr is enabled +ifneq ($(CONFIG_PACKAGE_kmod-qca-ovsmgr),) +NSS_CLIENTS_MAKE_OPTS+= NSS_BRIDGE_MGR_OVS_ENABLE=y +EXTRA_CFLAGS+= -I$(STAGING_DIR)/usr/include/qca-ovsmgr +endif +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-vlan-mgr),) +NSS_CLIENTS_MAKE_OPTS+=vlan-mgr=y +endif + +ifeq ($(CONFIG_TARGET_BOARD), "ipq807x") + SOC="ipq807x_64" +else ifeq ($(CONFIG_TARGET_BOARD), "ipq60xx") + SOC="ipq60xx_64" +endif + +define Build/Compile + $(MAKE) -C "$(LINUX_DIR)" $(strip $(NSS_CLIENTS_MAKE_OPTS)) \ + CROSS_COMPILE="$(TARGET_CROSS)" \ + ARCH="$(LINUX_KARCH)" \ + M="$(PKG_BUILD_DIR)" \ + EXTRA_CFLAGS="$(EXTRA_CFLAGS)" \ + SoC=$(SOC) \ + $(KERNEL_MAKE_FLAGS) \ + modules +endef + +$(eval $(call KernelPackage,qca-nss-drv-pppoe)) +$(eval $(call KernelPackage,qca-nss-drv-bridge-mgr)) +$(eval $(call KernelPackage,qca-nss-drv-vlan-mgr)) diff --git a/qca/qca-nss-clients/files/qca-nss-ipsec b/qca/qca-nss-clients/files/qca-nss-ipsec new file mode 100644 index 000000000..5f682c8e9 --- /dev/null +++ b/qca/qca-nss-clients/files/qca-nss-ipsec @@ -0,0 +1,214 @@ +#!/bin/sh /etc/rc.common +# +# Copyright (c) 2018-2019, 2021 The Linux Foundation. All rights reserved. +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +NSS_IPSEC_LOG_FILE=/tmp/.nss_ipsec_log +NSS_IPSEC_LOG_STR_ECM="ECM_Loaded" +NSS_IPSEC_OL_FILE=/tmp/qca_nss_ipsec_ol + +ecm_load () { + if [ ! -d /sys/module/ecm ]; then + /etc/init.d/qca-nss-ecm start + if [ -d /sys/module/ecm ]; then + echo ${NSS_IPSEC_LOG_STR_ECM} >> ${NSS_IPSEC_LOG_FILE} + fi + fi +} + +ecm_unload () { + if [ -f /tmp/.nss_ipsec_log ]; then + str=`grep ${NSS_IPSEC_LOG_STR_ECM} ${NSS_IPSEC_LOG_FILE}` + if [[ $str == ${NSS_IPSEC_LOG_STR_ECM} ]]; then + /etc/init.d/qca-nss-ecm stop + `sed 's/${NSS_IPSEC_LOG_STR_ECM}/ /g' $NSS_IPSEC_LOG_FILE > $NSS_IPSEC_LOG_FILE` + fi + fi +} + +ecm_disable() { + + if [ ! -d /sys/module/ecm ]; then + return; + fi + + echo 1 > /sys/kernel/debug/ecm/front_end_ipv4_stop + echo 1 > /sys/kernel/debug/ecm/front_end_ipv6_stop + echo 1 > /sys/kernel/debug/ecm/ecm_db/defunct_all + sleep 2 +} + +ecm_enable() { + if [ ! -d /sys/module/ecm ]; then + return; + fi + + echo 0 > /sys/kernel/debug/ecm/ecm_db/defunct_all + echo 0 > /sys/kernel/debug/ecm/front_end_ipv4_stop + echo 0 > /sys/kernel/debug/ecm/front_end_ipv6_stop +} + +kernel_version_check_5_4() { + major_ver=$(uname -r | awk -F '.' '{print $1}') + minor_ver=$(uname -r | awk -F '.' '{print $2}') + if [ $major_ver -lt 5 ] || ([ $major_ver -eq 5 ] && [ $minor_ver -lt 4 ] ) ; then + return 1 + else + return 0 + fi +} + +start_klips() { + if kernel_version_check_5_4 + then + echo "Kernel 5.4 doesn't support klips stack." + return $? + fi + + touch $NSS_IPSEC_OL_FILE + ecm_load + + local kernel_version=$(uname -r) + + insmod /lib/modules/${kernel_version}/qca-nss-ipsec-klips.ko + if [ "$?" -gt 0 ]; then + echo "Failed to load plugin. Please start ecm if not done already" + ecm_enable + rm $NSS_IPSEC_OL_FILE + return + fi + + /etc/init.d/ipsec start + sleep 2 + ipsec eroute + + ecm_enable +} + +stop_klips() { + if kernel_version_check_5_4 + then + echo "Kernel 5.4 doesn't support klips stack." + return $? + fi + + ecm_disable + + /etc/init.d/ipsec stop + rmmod qca-nss-ipsec-klips + rm $NSS_IPSEC_OL_FILE + + ecm_unload +} + +start_xfrm() { + touch $NSS_IPSEC_OL_FILE + ecm_load + + local kernel_version=$(uname -r) + + # load all NETKEY modules first. + for mod in xfrm_ipcomp ipcomp xfrm6_tunnel ipcomp6 xfrm6_mode_tunnel xfrm6_mode_beet xfrm6_mode_ro \ + xfrm6_mode_transport xfrm4_mode_transport xfrm4_mode_tunnel \ + xfrm4_tunnel xfrm4_mode_beet esp4 esp6 ah4 ah6 af_key + do + insmod $mod 2> /dev/null + done + + # Now load the xfrm plugin + insmod /lib/modules/${kernel_version}/qca-nss-ipsec-xfrm.ko + if [ "$?" -gt 0 ]; then + echo "Failed to load plugin. Please start ecm if not done already" + ecm_enable + rm $NSS_IPSEC_OL_FILE + return + fi + + /etc/init.d/ipsec start + sleep 2 + + ecm_enable +} + +stop_xfrm() { + ecm_disable + + #Shutdown Pluto first. Then only plugin can be removed. + plutopid=/var/run/pluto/pluto.pid + if [ -f $plutopid ]; then + pid=`cat $plutopid` + if [ ! -z "$pid" ]; then + ipsec whack --shutdown | grep -v "002"; + if [ -s $plutopid ]; then + echo "Attempt to shut Pluto down failed! Trying kill:" + kill $pid; + sleep 5; + fi + fi + rm -rf $plutopid + fi + ip xfrm state flush; + ip xfrm policy flush; + sleep 2 + + #Now we can remove the plugin + retries=5 + while [ -d /sys/module/qca_nss_ipsec_xfrm ] + do + rmmod qca-nss-ipsec-xfrm + if [ "$?" -eq 0 ]; then + rm $NSS_IPSEC_OL_FILE + break + fi + + if [ ${retries} -eq 0 ]; then + echo "Failed to unload qca-nss-ipsec-xfrm plugin!" + exit + fi + + echo "XFRM plugin unload failed; retrying ${retries} times" + sleep 1 + retries=`expr ${retries} - 1` + done + + /etc/init.d/ipsec stop + ecm_unload +} + +start() { + local protostack=`uci -q get ipsec.setup.protostack` + if [ "$protostack" = "klips" ]; then + start_klips + return $? + fi + + start_xfrm + return $? +} + +stop() { + local protostack=`uci -q get ipsec.setup.protostack` + if [ "$protostack" = "klips" ]; then + stop_klips + return $? + fi + + stop_xfrm + return $? +} + +restart() { + stop + start +} diff --git a/qca/qca-nss-clients/files/qca-nss-mirred.init b/qca/qca-nss-clients/files/qca-nss-mirred.init new file mode 100644 index 000000000..1f931f090 --- /dev/null +++ b/qca/qca-nss-clients/files/qca-nss-mirred.init @@ -0,0 +1,28 @@ +#!/bin/sh /etc/rc.common + +########################################################################### +# Copyright (c) 2019, The Linux Foundation. All rights reserved. +# Permission to use, copy, modify, and/or distribute this software for +# any purpose with or without fee is hereby granted, provided that the +# above copyright notice and this permission notice appear in all copies. +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT +# OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +########################################################################### + +restart() { + rmmod act_nssmirred.ko + insmod act_nssmirred.ko +} + +start() { + insmod act_nssmirred.ko +} + +stop() { + rmmod act_nssmirred.ko +} diff --git a/qca/qca-nss-clients/files/qca-nss-ovpn.init b/qca/qca-nss-clients/files/qca-nss-ovpn.init new file mode 100644 index 000000000..622e295ee --- /dev/null +++ b/qca/qca-nss-clients/files/qca-nss-ovpn.init @@ -0,0 +1,69 @@ +#!/bin/sh /etc/rc.common + +########################################################################### +# Copyright (c) 2019, The Linux Foundation. All rights reserved. +# Permission to use, copy, modify, and/or distribute this software for +# any purpose with or without fee is hereby granted, provided that the +# above copyright notice and this permission notice appear in all copies. +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT +# OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +########################################################################### + +ecm_disable() { + if [ ! -d /sys/module/ecm ]; then + return + fi + + echo 1 > /sys/kernel/debug/ecm/front_end_ipv4_stop + echo 1 > /sys/kernel/debug/ecm/front_end_ipv6_stop + echo 1 > /sys/kernel/debug/ecm/ecm_db/defunct_all + sleep 2 +} + +ecm_enable() { + if [ ! -d /sys/module/ecm ]; then + return + fi + + echo 0 > /sys/kernel/debug/ecm/ecm_db/defunct_all + echo 0 > /sys/kernel/debug/ecm/front_end_ipv4_stop + echo 0 > /sys/kernel/debug/ecm/front_end_ipv6_stop +} + +restart() { + ecm_disable + + /etc/init.d/openvpn stop + rmmod qca-nss-ovpn-link + rmmod qca-nss-ovpn-mgr + + insmod qca-nss-ovpn-mgr + insmod qca-nss-ovpn-link + + if [ "$?" -gt 0 ]; then + echo "Failed to load plugin. Please start ecm if not done already" + ecm_enable + return + fi + + ecm_enable +} + +start() { + restart +} + +stop() { + ecm_disable + + /etc/init.d/openvpn stop + rmmod qca-nss-ovpn-link + rmmod qca-nss-ovpn-mgr + + ecm_enable +} diff --git a/qca/qca-nss-crypto/Makefile b/qca/qca-nss-crypto/Makefile new file mode 100644 index 000000000..5c1003b89 --- /dev/null +++ b/qca/qca-nss-crypto/Makefile @@ -0,0 +1,72 @@ +include $(TOPDIR)/rules.mk + +PKG_NAME:=qca-nss-crypto +PKG_RELEASE:=$(AUTORELEASE) + +PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/nss-crypto.git +PKG_SOURCE_PROTO:=git +PKG_SOURCE_DATE:=2021-03-20 +PKG_SOURCE_VERSION:=2271a3a66f7e8284d42a9e787ddec6f24a1d2e15 +PKG_MIRROR_HASH:=afd2b746779bf9abb72dfb58c755acf54d1cb51085b879013dd0edf9ba98d3c9 + +PKG_BUILD_PARALLEL:=1 + +include $(INCLUDE_DIR)/kernel.mk +include $(INCLUDE_DIR)/package.mk + +ifeq ($(CONFIG_TARGET_BOARD), "ipq807x") + SOC="ipq807x_64" +else ifeq ($(CONFIG_TARGET_BOARD), "ipq60xx") + SOC="ipq60xx_64" +endif + +# v1.0 is for Akronite +# v2.0 is for Hawkeye/Cypress/Maple +ifneq (, $(findstring $(CONFIG_TARGET_BOARD), "ipq807x" "ipq60xx")) +NSS_CRYPTO_DIR:=v2.0 +else +NSS_CRYPTO_DIR:=v1.0 +endif + +define KernelPackage/qca-nss-crypto + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Cryptographic API modules + DEPENDS:=@(TARGET_ipq807x||TARGET_ipq60xx) +kmod-qca-nss-drv +nss-eip-firmware + TITLE:=Kernel driver for NSS crypto driver + FILES:=$(PKG_BUILD_DIR)/$(NSS_CRYPTO_DIR)/src/qca-nss-crypto.ko \ + $(PKG_BUILD_DIR)/$(NSS_CRYPTO_DIR)/tool/qca-nss-crypto-tool.ko + AUTOLOAD:=$(call AutoLoad,52,qca-nss-crypto) +endef + +define KernelPackage/qca-nss-crypto/Description +This package contains a NSS crypto driver for QCA chipset +endef + +define Build/InstallDev + $(INSTALL_DIR) $(1)/usr/include/qca-nss-crypto + $(CP) $(PKG_BUILD_DIR)/$(NSS_CRYPTO_DIR)/include/* $(1)/usr/include/qca-nss-crypto +endef + +EXTRA_CFLAGS+= \ + -DCONFIG_NSS_DEBUG_LEVEL=4 \ + -I$(STAGING_DIR)/usr/include/qca-nss-crypto \ + -I$(STAGING_DIR)/usr/include/qca-nss-drv \ + -I$(PKG_BUILD_DIR)/$(NSS_CRYPTO_DIR)/include \ + -I$(PKG_BUILD_DIR)/$(NSS_CRYPTO_DIR)/src + +define Build/Compile + +$(MAKE) -C "$(LINUX_DIR)" \ + CC="$(TARGET_CC)" \ + CROSS_COMPILE="$(TARGET_CROSS)" \ + ARCH="$(LINUX_KARCH)" \ + M="$(PKG_BUILD_DIR)" \ + EXTRA_CFLAGS="$(EXTRA_CFLAGS)" \ + NSS_CRYPTO_DIR=$(NSS_CRYPTO_DIR) \ + SoC=$(SOC) \ + $(KERNEL_MAKE_FLAGS) \ + $(PKG_JOBS) \ + modules +endef + +$(eval $(call KernelPackage,qca-nss-crypto)) diff --git a/qca/qca-nss-crypto/patches/0001-nss-crypto-fix-SHA1-header-include.patch b/qca/qca-nss-crypto/patches/0001-nss-crypto-fix-SHA1-header-include.patch new file mode 100644 index 000000000..757b172ea --- /dev/null +++ b/qca/qca-nss-crypto/patches/0001-nss-crypto-fix-SHA1-header-include.patch @@ -0,0 +1,32 @@ +From 68b7776673aabc2f93bd75e73ef4b45a1ac561d9 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Sun, 13 Mar 2022 13:44:47 +0100 +Subject: [PATCH 1/3] nss-crypto: fix SHA1 header include + +SHA1 header has been merged to the generic SHA one, +and with that the cryptohash.h was dropped. + +So, fix include in kernels 5.8 and newer. + +Signed-off-by: Robert Marko +--- + v2.0/src/nss_crypto_hlos.h | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/v2.0/src/nss_crypto_hlos.h b/v2.0/src/nss_crypto_hlos.h +index 84740c2..e827f4f 100644 +--- a/v2.0/src/nss_crypto_hlos.h ++++ b/v2.0/src/nss_crypto_hlos.h +@@ -55,7 +55,9 @@ + #include + #include + #include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 8, 0) + #include ++#endif + #include + #include + #include +-- +2.35.1 + diff --git a/qca/qca-nss-crypto/patches/0002-nss-crypto-replace-ioremap_nocache-with-ioremap.patch b/qca/qca-nss-crypto/patches/0002-nss-crypto-replace-ioremap_nocache-with-ioremap.patch new file mode 100644 index 000000000..8c829c11e --- /dev/null +++ b/qca/qca-nss-crypto/patches/0002-nss-crypto-replace-ioremap_nocache-with-ioremap.patch @@ -0,0 +1,69 @@ +From 80393ab565e26d572de56b7502b069b0a944bd40 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Tue, 8 Jun 2021 22:14:34 +0200 +Subject: [PATCH 2/3] nss-crypto: replace ioremap_nocache() with ioremap + +ioremap_nocache() was dropped in kernel 5.5 as regular +ioremap() was exactly the same. + +So, simply replace all of the ioremap_nocache() calls +with ioremap(). + +Signed-off-by: Robert Marko +--- + v2.0/src/hal/ipq50xx/nss_crypto_ce5.c | 4 ++-- + v2.0/src/hal/ipq60xx/nss_crypto_eip197.c | 2 +- + v2.0/src/hal/ipq807x/nss_crypto_eip197.c | 2 +- + 3 files changed, 4 insertions(+), 4 deletions(-) + +diff --git a/v2.0/src/hal/ipq50xx/nss_crypto_ce5.c b/v2.0/src/hal/ipq50xx/nss_crypto_ce5.c +index c89cd38..a7a46e0 100644 +--- a/v2.0/src/hal/ipq50xx/nss_crypto_ce5.c ++++ b/v2.0/src/hal/ipq50xx/nss_crypto_ce5.c +@@ -288,7 +288,7 @@ int nss_crypto_ce5_engine_init(struct platform_device *pdev, struct resource *cr + * remap the I/O addresses for crypto + */ + eng->crypto_paddr = crypto_res->start; +- eng->crypto_vaddr = ioremap_nocache(crypto_res->start, resource_size(crypto_res)); ++ eng->crypto_vaddr = ioremap(crypto_res->start, resource_size(crypto_res)); + if (!eng->crypto_vaddr) { + nss_crypto_warn("%px: unable to remap crypto_addr(0x%px)\n", node, (void *)eng->crypto_paddr); + nss_crypto_engine_free(eng); +@@ -299,7 +299,7 @@ int nss_crypto_ce5_engine_init(struct platform_device *pdev, struct resource *cr + * remap the I/O addresses for bam + */ + eng->dma_paddr = bam_res->start; +- eng->dma_vaddr = ioremap_nocache(bam_res->start, resource_size(bam_res)); ++ eng->dma_vaddr = ioremap(bam_res->start, resource_size(bam_res)); + if (!eng->dma_vaddr) { + iounmap(eng->crypto_vaddr); + nss_crypto_warn("%px: unable to remap dma_addr(0x%px)\n", node, (void *)eng->dma_paddr); +diff --git a/v2.0/src/hal/ipq60xx/nss_crypto_eip197.c b/v2.0/src/hal/ipq60xx/nss_crypto_eip197.c +index 8dfc35d..79649f9 100644 +--- a/v2.0/src/hal/ipq60xx/nss_crypto_eip197.c ++++ b/v2.0/src/hal/ipq60xx/nss_crypto_eip197.c +@@ -490,7 +490,7 @@ int nss_crypto_eip197_engine_init(struct platform_device *pdev, struct device_no + * remap the I/O addresses + */ + paddr = res->start + offset; +- vaddr = ioremap_nocache(paddr, resource_size(res)); ++ vaddr = ioremap(paddr, resource_size(res)); + if (!vaddr) { + nss_crypto_warn("%px: unable to remap crypto_addr(0x%px)\n", node, (void *)paddr); + return -EIO; +diff --git a/v2.0/src/hal/ipq807x/nss_crypto_eip197.c b/v2.0/src/hal/ipq807x/nss_crypto_eip197.c +index 632adca..5e2c146 100644 +--- a/v2.0/src/hal/ipq807x/nss_crypto_eip197.c ++++ b/v2.0/src/hal/ipq807x/nss_crypto_eip197.c +@@ -490,7 +490,7 @@ int nss_crypto_eip197_engine_init(struct platform_device *pdev, struct device_no + * remap the I/O addresses + */ + paddr = res->start + offset; +- vaddr = ioremap_nocache(paddr, resource_size(res)); ++ vaddr = ioremap(paddr, resource_size(res)); + if (!vaddr) { + nss_crypto_warn("%px: unable to remap crypto_addr(0x%px)\n", node, (void *)paddr); + return -EIO; +-- +2.35.1 + diff --git a/qca/qca-nss-crypto/patches/0003-nss-crypto-fix-SHA-header-include-in-5.15.patch b/qca/qca-nss-crypto/patches/0003-nss-crypto-fix-SHA-header-include-in-5.15.patch new file mode 100644 index 000000000..311070d91 --- /dev/null +++ b/qca/qca-nss-crypto/patches/0003-nss-crypto-fix-SHA-header-include-in-5.15.patch @@ -0,0 +1,51 @@ +From 4c0cc66cde0c4a30aa049b586af311501304e9ce Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Sun, 13 Mar 2022 13:47:24 +0100 +Subject: [PATCH 3/3] nss-crypto: fix SHA header include in 5.15 + +SHA header was split into SHA-1 and SHA-2 headers in kernel 5.11, so +fix the include for newer kernels. + +Signed-off-by: Robert Marko +--- + v2.0/src/nss_crypto_ctrl.c | 6 ++++++ + v2.0/src/nss_crypto_hlos.h | 4 ++++ + 2 files changed, 10 insertions(+) + +diff --git a/v2.0/src/nss_crypto_ctrl.c b/v2.0/src/nss_crypto_ctrl.c +index 72d1602..a462705 100644 +--- a/v2.0/src/nss_crypto_ctrl.c ++++ b/v2.0/src/nss_crypto_ctrl.c +@@ -38,7 +38,13 @@ + #include + #include + #include ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 11, 0) + #include ++#else ++#include ++#include ++#endif + #include + #include + #include +diff --git a/v2.0/src/nss_crypto_hlos.h b/v2.0/src/nss_crypto_hlos.h +index e827f4f..5565472 100644 +--- a/v2.0/src/nss_crypto_hlos.h ++++ b/v2.0/src/nss_crypto_hlos.h +@@ -58,7 +58,11 @@ + #if LINUX_VERSION_CODE < KERNEL_VERSION(5, 8, 0) + #include + #endif ++#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 11, 0) + #include ++#else ++#include ++#endif + #include + #include + #include +-- +2.35.1 + diff --git a/qca/qca-nss-dp/Makefile b/qca/qca-nss-dp/Makefile new file mode 100644 index 000000000..17627674a --- /dev/null +++ b/qca/qca-nss-dp/Makefile @@ -0,0 +1,56 @@ +include $(TOPDIR)/rules.mk + +PKG_NAME:=qca-nss-dp +PKG_RELEASE:=$(AUTORELEASE) + +PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/nss-dp.git +PKG_SOURCE_PROTO:=git +PKG_SOURCE_DATE:=2022-04-30 +PKG_SOURCE_VERSION:=72e9ec4187414461cbcf6ccff100e8b5ebe5f40b +PKG_MIRROR_HASH:=805f16e59c75511132922f97740ebf6bf953845b0bbfd2089c4615456893bb37 + +PKG_BUILD_PARALLEL:=1 + +include $(INCLUDE_DIR)/kernel.mk +include $(INCLUDE_DIR)/package.mk + +define KernelPackage/qca-nss-dp + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + DEPENDS:=@(TARGET_ipq807x||TARGET_ipq60xx) +kmod-qca-ssdk-nohnat + TITLE:=Kernel driver for NSS data plane + FILES:=$(PKG_BUILD_DIR)/qca-nss-dp.ko + AUTOLOAD:=$(call AutoLoad,31,qca-nss-dp,1) +endef + +define KernelPackage/qca-nss-dp/Description +This package contains a NSS data plane driver for QCA chipset +endef + +define Build/InstallDev + mkdir -p $(1)/usr/include/qca-nss-dp + $(CP) $(PKG_BUILD_DIR)/exports/* $(1)/usr/include/qca-nss-dp/ +endef + +EXTRA_CFLAGS+= \ + -I$(STAGING_DIR)/usr/include/qca-ssdk + +NSS_DP_HAL_DIR:=$(PKG_BUILD_DIR)/hal +define Build/Configure + $(LN) $(NSS_DP_HAL_DIR)/soc_ops/$(CONFIG_TARGET_BOARD)/nss_$(CONFIG_TARGET_BOARD).h \ + $(PKG_BUILD_DIR)/exports/nss_dp_arch.h +endef + +define Build/Compile + +$(MAKE) -C "$(LINUX_DIR)" \ + CROSS_COMPILE="$(TARGET_CROSS)" \ + ARCH="$(LINUX_KARCH)" \ + M="$(PKG_BUILD_DIR)" \ + EXTRA_CFLAGS="$(EXTRA_CFLAGS)" SoC="$(CONFIG_TARGET_BOARD)" \ + $(KERNEL_MAKE_FLAGS) \ + $(PKG_JOBS) \ + modules +endef + +$(eval $(call KernelPackage,qca-nss-dp)) diff --git a/qca/qca-nss-dp/patches/0001-edma_tx_rx-support-newer-kernels-time-stamping-API.patch b/qca/qca-nss-dp/patches/0001-edma_tx_rx-support-newer-kernels-time-stamping-API.patch new file mode 100644 index 000000000..1fed4ba8a --- /dev/null +++ b/qca/qca-nss-dp/patches/0001-edma_tx_rx-support-newer-kernels-time-stamping-API.patch @@ -0,0 +1,44 @@ +From 40979666b4371012405715ffa61ab5760fcdc6b3 Mon Sep 17 00:00:00 2001 +Message-Id: <40979666b4371012405715ffa61ab5760fcdc6b3.1620066716.git.baruch@tkos.co.il> +From: Baruch Siach +Date: Mon, 3 May 2021 20:07:36 +0300 +Subject: [PATCH 1/3] edma_tx_rx: support newer kernels time stamping API + +--- + hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +--- a/hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c ++++ b/hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c +@@ -227,10 +227,16 @@ void nss_phy_tstamp_rx_buf(__attribute__ + * set to the correct PTP class value by calling ptp_classify_raw + * in drv->rxtstamp function. + */ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 6, 0)) + if (ndev && ndev->phydev && ndev->phydev->drv && + ndev->phydev->drv->rxtstamp) + if(ndev->phydev->drv->rxtstamp(ndev->phydev, skb, 0)) + return; ++#else ++ if (ndev && phy_has_rxtstamp(ndev->phydev)) ++ if (phy_rxtstamp(ndev->phydev, skb, 0)) ++ return; ++#endif + + netif_receive_skb(skb); + } +@@ -248,9 +254,14 @@ void nss_phy_tstamp_tx_buf(struct net_de + * set to the correct PTP class value by calling ptp_classify_raw + * in the drv->txtstamp function. + */ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 6, 0)) + if (ndev && ndev->phydev && ndev->phydev->drv && + ndev->phydev->drv->txtstamp) + ndev->phydev->drv->txtstamp(ndev->phydev, skb, 0); ++#else ++ if (ndev && phy_has_txtstamp(ndev->phydev)) ++ phy_rxtstamp(ndev->phydev, skb, 0); ++#endif + } + EXPORT_SYMBOL(nss_phy_tstamp_tx_buf); + diff --git a/qca/qca-nss-dp/patches/0002-nss_dp_main-make-phy-mode-code-compatible-with-newer.patch b/qca/qca-nss-dp/patches/0002-nss_dp_main-make-phy-mode-code-compatible-with-newer.patch new file mode 100644 index 000000000..04adad86f --- /dev/null +++ b/qca/qca-nss-dp/patches/0002-nss_dp_main-make-phy-mode-code-compatible-with-newer.patch @@ -0,0 +1,48 @@ +From cef7873a2d77df13ee702d902ed4e06b2248904b Mon Sep 17 00:00:00 2001 +Message-Id: +In-Reply-To: <40979666b4371012405715ffa61ab5760fcdc6b3.1620066716.git.baruch@tkos.co.il> +References: <40979666b4371012405715ffa61ab5760fcdc6b3.1620066716.git.baruch@tkos.co.il> +From: Baruch Siach +Date: Mon, 3 May 2021 20:17:22 +0300 +Subject: [PATCH 2/3] nss_dp_main: make phy mode code compatible with newer + kernels + +--- + include/nss_dp_dev.h | 4 ++-- + nss_dp_main.c | 4 ++++ + 2 files changed, 6 insertions(+), 2 deletions(-) + +--- a/include/nss_dp_dev.h ++++ b/include/nss_dp_dev.h +@@ -22,7 +22,7 @@ + #include + #include + #include +-#include ++#include + #include + + #include "nss_dp_api_if.h" +@@ -99,7 +99,7 @@ struct nss_dp_dev { + /* Phy related stuff */ + struct phy_device *phydev; /* Phy device */ + struct mii_bus *miibus; /* MII bus */ +- uint32_t phy_mii_type; /* RGMII/SGMII/QSGMII */ ++ phy_interface_t phy_mii_type; /* RGMII/SGMII/QSGMII */ + uint32_t phy_mdio_addr; /* Mdio address */ + bool link_poll; /* Link polling enable? */ + uint32_t forced_speed; /* Forced speed? */ +--- a/nss_dp_main.c ++++ b/nss_dp_main.c +@@ -584,7 +584,11 @@ static int32_t nss_dp_of_get_pdata(struc + hal_pdata->netdev = netdev; + hal_pdata->macid = dp_priv->macid; + ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 5, 0)) + dp_priv->phy_mii_type = of_get_phy_mode(np); ++#else ++ of_get_phy_mode(np, &dp_priv->phy_mii_type); ++#endif + dp_priv->link_poll = of_property_read_bool(np, "qcom,link-poll"); + if (of_property_read_u32(np, "qcom,phy-mdio-addr", + &dp_priv->phy_mdio_addr) && dp_priv->link_poll) { diff --git a/qca/qca-nss-dp/patches/0003-Drop-_nocache-variants-of-ioremap.patch b/qca/qca-nss-dp/patches/0003-Drop-_nocache-variants-of-ioremap.patch new file mode 100644 index 000000000..18bd85c8c --- /dev/null +++ b/qca/qca-nss-dp/patches/0003-Drop-_nocache-variants-of-ioremap.patch @@ -0,0 +1,48 @@ +From c8c52512ff48bee578901c381a42f027e79eadf9 Mon Sep 17 00:00:00 2001 +Message-Id: +In-Reply-To: <40979666b4371012405715ffa61ab5760fcdc6b3.1620066716.git.baruch@tkos.co.il> +References: <40979666b4371012405715ffa61ab5760fcdc6b3.1620066716.git.baruch@tkos.co.il> +From: Baruch Siach +Date: Mon, 3 May 2021 20:20:29 +0300 +Subject: [PATCH 3/3] Drop _nocache variants of ioremap() + +Recent kernels removed them. +--- + hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c | 2 +- + hal/gmac_ops/qcom/qcom_if.c | 2 +- + hal/gmac_ops/syn/xgmac/syn_if.c | 2 +- + 3 files changed, 3 insertions(+), 3 deletions(-) + +--- a/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c ++++ b/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c +@@ -279,7 +279,7 @@ int edma_init(void) + /* + * Remap register resource + */ +- edma_hw.reg_base = ioremap_nocache((edma_hw.reg_resource)->start, ++ edma_hw.reg_base = ioremap((edma_hw.reg_resource)->start, + resource_size(edma_hw.reg_resource)); + if (!edma_hw.reg_base) { + pr_warn("Unable to remap EDMA register memory.\n"); +--- a/hal/gmac_ops/qcom/qcom_if.c ++++ b/hal/gmac_ops/qcom/qcom_if.c +@@ -418,7 +418,7 @@ static void *qcom_init(struct nss_gmac_h + qhd->nghd.mac_id = gmacpdata->macid; + + /* Populate the mac base addresses */ +- qhd->nghd.mac_base = devm_ioremap_nocache(&dp_priv->pdev->dev, ++ qhd->nghd.mac_base = devm_ioremap(&dp_priv->pdev->dev, + res->start, resource_size(res)); + if (!qhd->nghd.mac_base) { + netdev_dbg(ndev, "ioremap fail.\n"); +--- a/hal/gmac_ops/syn/xgmac/syn_if.c ++++ b/hal/gmac_ops/syn/xgmac/syn_if.c +@@ -432,7 +432,7 @@ static void *syn_init(struct nss_gmac_ha + + /* Populate the mac base addresses */ + shd->nghd.mac_base = +- devm_ioremap_nocache(&dp_priv->pdev->dev, res->start, ++ devm_ioremap(&dp_priv->pdev->dev, res->start, + resource_size(res)); + if (!shd->nghd.mac_base) { + netdev_dbg(ndev, "ioremap fail.\n"); diff --git a/qca/qca-nss-dp/patches/0004-EDMA-Fix-NAPI-packet-counting.patch b/qca/qca-nss-dp/patches/0004-EDMA-Fix-NAPI-packet-counting.patch new file mode 100644 index 000000000..f7653729a --- /dev/null +++ b/qca/qca-nss-dp/patches/0004-EDMA-Fix-NAPI-packet-counting.patch @@ -0,0 +1,31 @@ +From d74920e2a7c413ef40eed72f9cf287cf6fbd5fb8 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Thu, 20 May 2021 14:56:46 +0200 +Subject: [PATCH 1/2] EDMA: Fix NAPI packet counting + +There is a bug in the NAPI packet counting that will +cause NAPI over budget warnings. + +Signed-off-by: Baruch Siach +Signed-off-by: Robert Marko +--- + hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c ++++ b/hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c +@@ -459,12 +459,12 @@ int edma_napi(struct napi_struct *napi, + + for (i = 0; i < ehw->txcmpl_rings; i++) { + txcmpl_ring = &ehw->txcmpl_ring[i]; +- work_done += edma_clean_tx(ehw, txcmpl_ring); ++ edma_clean_tx(ehw, txcmpl_ring); + } + + for (i = 0; i < ehw->rxfill_rings; i++) { + rxfill_ring = &ehw->rxfill_ring[i]; +- work_done += edma_alloc_rx_buffer(ehw, rxfill_ring); ++ edma_alloc_rx_buffer(ehw, rxfill_ring); + } + + /* diff --git a/qca/qca-nss-dp/patches/0005-EDMA-Use-NAPI_POLL_WEIGHT-as-NAPI-weight.patch b/qca/qca-nss-dp/patches/0005-EDMA-Use-NAPI_POLL_WEIGHT-as-NAPI-weight.patch new file mode 100644 index 000000000..9c22fa790 --- /dev/null +++ b/qca/qca-nss-dp/patches/0005-EDMA-Use-NAPI_POLL_WEIGHT-as-NAPI-weight.patch @@ -0,0 +1,41 @@ +From 44a30d94abcbb10aacc21db29be212518a6b1bf7 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Thu, 20 May 2021 14:57:46 +0200 +Subject: [PATCH] EDMA: Use NAPI_POLL_WEIGHT as NAPI weight + +Currently a weight of 100 is used by the EDMA, according +to upstream max of 64 should be used and that is used for +almost any driver. + +They also introduced NAPI_POLL_WEIGHT define which equals +to 64. + +So use NAPI_POLL_WEIGHT as the weight. + +Signed-off-by: Robert Marko +--- + hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c | 2 +- + hal/dp_ops/edma_dp/edma_v1/edma_data_plane.h | 1 - + 2 files changed, 1 insertion(+), 2 deletions(-) + +--- a/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c ++++ b/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c +@@ -837,7 +837,7 @@ static int edma_register_netdevice(struc + */ + if (!edma_hw.napi_added) { + netif_napi_add(netdev, &edma_hw.napi, edma_napi, +- EDMA_NAPI_WORK); ++ NAPI_POLL_WEIGHT); + /* + * Register the interrupt handlers and enable interrupts + */ +--- a/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.h ++++ b/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.h +@@ -26,7 +26,6 @@ + #define EDMA_RX_PREHDR_SIZE (sizeof(struct edma_rx_preheader)) + #define EDMA_TX_PREHDR_SIZE (sizeof(struct edma_tx_preheader)) + #define EDMA_RING_SIZE 128 +-#define EDMA_NAPI_WORK 100 + #define EDMA_START_GMACS NSS_DP_HAL_START_IFNUM + #define EDMA_MAX_GMACS NSS_DP_HAL_MAX_PORTS + #define EDMA_TX_PKT_MIN_SIZE 33 /* IPQ807x EDMA needs a minimum packet size of 33 bytes */ diff --git a/qca/qca-nss-dp/patches/0006-NSS-DP-fix-of_get_mac_address.patch b/qca/qca-nss-dp/patches/0006-NSS-DP-fix-of_get_mac_address.patch new file mode 100644 index 000000000..1d7b49129 --- /dev/null +++ b/qca/qca-nss-dp/patches/0006-NSS-DP-fix-of_get_mac_address.patch @@ -0,0 +1,46 @@ +From cadeb62a42296563141d6954eec58e34ef86778d Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Fri, 13 Aug 2021 20:12:08 +0200 +Subject: [PATCH] NSS-DP: fix of_get_mac_address() + +Recently OpenWrt backported the updated of_get_mac_address() +function which returns and error code instead. + +So, patch the SSDK to use it and fix the compilation error. + +Signed-off-by: Robert Marko +--- + nss_dp_main.c | 13 ++++--------- + 1 file changed, 4 insertions(+), 9 deletions(-) + +--- a/nss_dp_main.c ++++ b/nss_dp_main.c +@@ -555,9 +555,10 @@ static int32_t nss_dp_of_get_pdata(struc + struct net_device *netdev, + struct nss_gmac_hal_platform_data *hal_pdata) + { +- uint8_t *maddr; ++ u8 maddr[ETH_ALEN]; + struct nss_dp_dev *dp_priv; + struct resource memres_devtree = {0}; ++ int ret; + + dp_priv = netdev_priv(netdev); + +@@ -600,14 +601,8 @@ static int32_t nss_dp_of_get_pdata(struc + of_property_read_u32(np, "qcom,forced-speed", &dp_priv->forced_speed); + of_property_read_u32(np, "qcom,forced-duplex", &dp_priv->forced_duplex); + +- maddr = (uint8_t *)of_get_mac_address(np); +-#if (LINUX_VERSION_CODE > KERNEL_VERSION(5, 4, 0)) +- if (IS_ERR((void *)maddr)) { +- maddr = NULL; +- } +-#endif +- +- if (maddr && is_valid_ether_addr(maddr)) { ++ ret = of_get_mac_address(np, maddr); ++ if (!ret && is_valid_ether_addr(maddr)) { + ether_addr_copy(netdev->dev_addr, maddr); + } else { + random_ether_addr(netdev->dev_addr); diff --git a/qca/qca-nss-dp/patches/0007-NSS-DP-implement-ethernet-IOCTL-s.patch b/qca/qca-nss-dp/patches/0007-NSS-DP-implement-ethernet-IOCTL-s.patch new file mode 100644 index 000000000..824f18634 --- /dev/null +++ b/qca/qca-nss-dp/patches/0007-NSS-DP-implement-ethernet-IOCTL-s.patch @@ -0,0 +1,29 @@ +From 5da62ba19f554bf437752a44360fb5ae9f1a7f5e Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Tue, 8 Mar 2022 10:48:32 +0100 +Subject: [PATCH] NSS-DP: implement ethernet IOCTL-s + +Since kernel 5.15 ethernet/PHY related IOCTL-s have been split from the +generic IOCTL netdev op. +So, implement the new op instead of the generic one which is considered +for private IOCTL-s only now for 5.15+. + +Signed-off-by: Robert Marko +--- + nss_dp_main.c | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/nss_dp_main.c ++++ b/nss_dp_main.c +@@ -532,7 +532,11 @@ static const struct net_device_ops nss_d + .ndo_set_mac_address = nss_dp_set_mac_address, + .ndo_validate_addr = eth_validate_addr, + .ndo_change_mtu = nss_dp_change_mtu, ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 15, 0)) + .ndo_do_ioctl = nss_dp_do_ioctl, ++#else ++ .ndo_eth_ioctl = nss_dp_do_ioctl, ++#endif + + #if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 5, 0)) + .ndo_bridge_setlink = switchdev_port_bridge_setlink, diff --git a/qca/qca-nss-dp/patches/0008-switchdev-remove-the-transaction-structure.patch b/qca/qca-nss-dp/patches/0008-switchdev-remove-the-transaction-structure.patch new file mode 100644 index 000000000..220be961a --- /dev/null +++ b/qca/qca-nss-dp/patches/0008-switchdev-remove-the-transaction-structure.patch @@ -0,0 +1,48 @@ +From c9afdcdd2642485a6476906be9da2e811090fc7a Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Fri, 18 Mar 2022 18:06:03 +0100 +Subject: [PATCH] switchdev: remove the transaction structure + +Since 5.12 there is no transaction structure anymore, so drop it for +5.12 and newer. + +Signed-off-by: Robert Marko +--- + nss_dp_switchdev.c | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +--- a/nss_dp_switchdev.c ++++ b/nss_dp_switchdev.c +@@ -279,13 +279,19 @@ void nss_dp_switchdev_setup(struct net_d + * Sets attributes + */ + static int nss_dp_port_attr_set(struct net_device *dev, ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 12, 0)) + const struct switchdev_attr *attr, + struct switchdev_trans *trans) ++#else ++ const struct switchdev_attr *attr) ++#endif + { + struct nss_dp_dev *dp_priv = (struct nss_dp_dev *)netdev_priv(dev); + ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 12, 0)) + if (switchdev_trans_ph_prepare(trans)) + return 0; ++#endif + + switch (attr->id) { + case SWITCHDEV_ATTR_ID_PORT_BRIDGE_FLAGS: +@@ -309,8 +315,12 @@ static int nss_dp_switchdev_port_attr_se + { + int err; + ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 12, 0)) + err = nss_dp_port_attr_set(netdev, port_attr_info->attr, + port_attr_info->trans); ++#else ++ err = nss_dp_port_attr_set(netdev, port_attr_info->attr); ++#endif + + port_attr_info->handled = true; + return notifier_from_errno(err); diff --git a/qca/qca-nss-dp/patches/0009-switchdev-use-new-switchdev-flags.patch b/qca/qca-nss-dp/patches/0009-switchdev-use-new-switchdev-flags.patch new file mode 100644 index 000000000..ecc84c174 --- /dev/null +++ b/qca/qca-nss-dp/patches/0009-switchdev-use-new-switchdev-flags.patch @@ -0,0 +1,51 @@ +From f95868d54301c0f54e968ec9d978c9caa02ee425 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Fri, 18 Mar 2022 18:24:18 +0100 +Subject: [PATCH] switchdev: use new switchdev flags + +Since kernel 5.12 switched utilizes a new way of setting the flags by +using a dedicated structure with flags and mask. + +So fix using kernels 5.12 and later. + +Signed-off-by: Robert Marko +--- + include/nss_dp_dev.h | 7 +++++++ + nss_dp_switchdev.c | 2 +- + 2 files changed, 8 insertions(+), 1 deletion(-) + +--- a/include/nss_dp_dev.h ++++ b/include/nss_dp_dev.h +@@ -24,6 +24,9 @@ + #include + #include + #include ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 12, 0)) ++#include ++#endif + + #include "nss_dp_api_if.h" + #include "nss_dp_hal_if.h" +@@ -126,7 +129,11 @@ struct nss_dp_dev { + /* switchdev related attributes */ + #ifdef CONFIG_NET_SWITCHDEV + u8 stp_state; /* STP state of this physical port */ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 12, 0)) + unsigned long brport_flags; /* bridge port flags */ ++#else ++ struct switchdev_brport_flags brport_flags; /* bridge port flags */ ++#endif + #endif + uint32_t rx_page_mode; /* page mode for Rx processing */ + uint32_t rx_jumbo_mru; /* Jumbo mru value for Rx processing */ +--- a/nss_dp_switchdev.c ++++ b/nss_dp_switchdev.c +@@ -296,7 +296,7 @@ static int nss_dp_port_attr_set(struct n + switch (attr->id) { + case SWITCHDEV_ATTR_ID_PORT_BRIDGE_FLAGS: + dp_priv->brport_flags = attr->u.brport_flags; +- netdev_dbg(dev, "set brport_flags %lu\n", attr->u.brport_flags); ++ netdev_dbg(dev, "set brport_flags %lu\n", attr->u.brport_flags.val); + return 0; + case SWITCHDEV_ATTR_ID_PORT_STP_STATE: + return nss_dp_stp_state_set(dp_priv, attr->u.stp_state); diff --git a/qca/qca-nss-dp/patches/0010-switchdev-fix-FDB-roaming.patch b/qca/qca-nss-dp/patches/0010-switchdev-fix-FDB-roaming.patch new file mode 100644 index 000000000..19395ac42 --- /dev/null +++ b/qca/qca-nss-dp/patches/0010-switchdev-fix-FDB-roaming.patch @@ -0,0 +1,110 @@ +From d16102cad769f430144ca8094d928762b445e9b0 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Fri, 18 Mar 2022 22:02:01 +0100 +Subject: [PATCH] switchdev: fix FDB roaming + +Try and solve the roaming issue by trying to replicate what NSS bridge +module is doing, but by utilizing switchdev FDB notifiers instead of +adding new notifiers to the bridge code. + +We register a new non-blocking switchdev notifier and simply wait for +notification, and then process the SWITCHDEV_FDB_DEL_TO_DEVICE +notifications. + +Those tell us that a certain FDB entry should be removed, then a VSI ID +is fetched for the physical PPE port and using that VSI ID and the +notification provided MAC adress existing FDB entry gets removed. + +Signed-off-by: Robert Marko +--- + nss_dp_switchdev.c | 61 ++++++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 61 insertions(+) + +--- a/nss_dp_switchdev.c ++++ b/nss_dp_switchdev.c +@@ -24,6 +24,8 @@ + #include "nss_dp_dev.h" + #include "fal/fal_stp.h" + #include "fal/fal_ctrlpkt.h" ++#include "fal/fal_fdb.h" ++#include "ref/ref_vsi.h" + + #define NSS_DP_SWITCH_ID 0 + #define NSS_DP_SW_ETHTYPE_PID 0 /* PPE ethtype profile ID for slow protocols */ +@@ -348,10 +350,64 @@ static int nss_dp_switchdev_event(struct + return NOTIFY_DONE; + } + ++static int nss_dp_switchdev_fdb_del_event(struct net_device *netdev, ++ struct switchdev_notifier_fdb_info *fdb_info) ++{ ++ struct nss_dp_dev *dp_priv = (struct nss_dp_dev *)netdev_priv(netdev); ++ fal_fdb_entry_t entry; ++ a_uint32_t vsi_id; ++ sw_error_t rv; ++ ++ netdev_dbg(netdev, "FDB DEL %pM port %d\n", fdb_info->addr, dp_priv->macid); ++ ++ rv = ppe_port_vsi_get(NSS_DP_SWITCH_ID, dp_priv->macid, &vsi_id); ++ if (rv) { ++ netdev_err(netdev, "cannot get VSI ID for port %d\n", dp_priv->macid); ++ return notifier_from_errno(rv); ++ } ++ ++ memset(&entry, 0, sizeof(entry)); ++ memcpy(&entry.addr, fdb_info->addr, ETH_ALEN); ++ entry.fid = vsi_id; ++ ++ rv = fal_fdb_entry_del_bymac(NSS_DP_SWITCH_ID, &entry); ++ if (rv) { ++ netdev_err(netdev, "FDB entry delete failed with MAC %pM and fid %d\n", ++ &entry.addr, entry.fid); ++ return notifier_from_errno(rv); ++ } ++ ++ return notifier_from_errno(rv); ++} ++ ++static int nss_dp_fdb_switchdev_event(struct notifier_block *nb, ++ unsigned long event, void *ptr) ++{ ++ struct net_device *dev = switchdev_notifier_info_to_dev(ptr); ++ ++ /* ++ * Handle switchdev event only for physical devices ++ */ ++ if (!nss_dp_is_phy_dev(dev)) { ++ return NOTIFY_DONE; ++ } ++ ++ switch (event) { ++ case SWITCHDEV_FDB_DEL_TO_DEVICE: ++ return nss_dp_switchdev_fdb_del_event(dev, ptr); ++ } ++ ++ return NOTIFY_DONE; ++} ++ + static struct notifier_block nss_dp_switchdev_notifier = { + .notifier_call = nss_dp_switchdev_event, + }; + ++static struct notifier_block nss_dp_switchdev_fdb_notifier = { ++ .notifier_call = nss_dp_fdb_switchdev_event, ++}; ++ + static bool switch_init_done; + + /* +@@ -366,6 +422,11 @@ void nss_dp_switchdev_setup(struct net_d + return; + } + ++ err = register_switchdev_notifier(&nss_dp_switchdev_fdb_notifier); ++ if (err) { ++ netdev_dbg(dev, "%px:Failed to register switchdev FDB notifier\n", dev); ++ } ++ + err = register_switchdev_blocking_notifier(&nss_dp_switchdev_notifier); + if (err) { + netdev_dbg(dev, "%px:Failed to register switchdev notifier\n", dev); diff --git a/qca/qca-nss-dp/patches/0011-treewide-fix-confusing-printing-of-registered-netdev.patch b/qca/qca-nss-dp/patches/0011-treewide-fix-confusing-printing-of-registered-netdev.patch new file mode 100644 index 000000000..63fea1982 --- /dev/null +++ b/qca/qca-nss-dp/patches/0011-treewide-fix-confusing-printing-of-registered-netdev.patch @@ -0,0 +1,48 @@ +From 7e4ae2d6285095794d73d2f2ce61404f61d4e633 Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Tue, 17 May 2022 15:55:36 +0200 +Subject: [PATCH 11/11] treewide: fix confusing printing of registered netdev + +Net core implementation changed and now printing the netdev name cause +confusing printing if done before register_netdev. Move the old printing +to dbg and add an additional info log right after register_netdev to +give the user some info on correct nss-dp probe. + +Signed-off-by: Ansuel Smith +--- + hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c | 4 ++-- + nss_dp_main.c | 3 +++ + 2 files changed, 5 insertions(+), 2 deletions(-) + +diff --git a/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c b/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c +index 0af39c2..1d748db 100644 +--- a/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c ++++ b/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c +@@ -822,8 +822,8 @@ static int edma_register_netdevice(struct net_device *netdev, uint32_t macid) + return -EINVAL; + } + +- netdev_info(netdev, "nss_dp_edma: Registering netdev %s(qcom-id:%d) with EDMA\n", +- netdev->name, macid); ++ netdev_dbg(netdev, "nss_dp_edma: Registering netdev %s(qcom-id:%d) with EDMA\n", ++ netdev->name, macid); + + /* + * We expect 'macid' to correspond to ports numbers on +diff --git a/nss_dp_main.c b/nss_dp_main.c +index c0ae9d6..441c300 100644 +--- a/nss_dp_main.c ++++ b/nss_dp_main.c +@@ -875,6 +875,9 @@ static int32_t nss_dp_probe(struct platform_device *pdev) + goto phy_setup_fail; + } + ++ netdev_info(netdev, "Registered netdev %s(qcom-id:%d)\n", ++ netdev->name, port_id); ++ + dp_global_ctx.nss_dp[dp_priv->macid - 1] = dp_priv; + dp_global_ctx.slowproto_acl_bm = 0; + +-- +2.34.1 + diff --git a/qca/qca-nss-dp/patches/0012-gmac-syn-xgmac-silence-debug-log-on-probe.patch b/qca/qca-nss-dp/patches/0012-gmac-syn-xgmac-silence-debug-log-on-probe.patch new file mode 100644 index 000000000..2bc576ccb --- /dev/null +++ b/qca/qca-nss-dp/patches/0012-gmac-syn-xgmac-silence-debug-log-on-probe.patch @@ -0,0 +1,28 @@ +From fee52ef165e9fab2fca15492677082fd8e9e891f Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Thu, 19 May 2022 23:40:24 +0200 +Subject: [PATCH 12/12] gmac: syn: xgmac: silence debug log on probe + +Silence debug log set as info in xgmac port probe. + +Signed-off-by: Ansuel Smith +--- + hal/gmac_ops/syn/xgmac/syn_if.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/hal/gmac_ops/syn/xgmac/syn_if.c b/hal/gmac_ops/syn/xgmac/syn_if.c +index 1152f5c..bc2880d 100644 +--- a/hal/gmac_ops/syn/xgmac/syn_if.c ++++ b/hal/gmac_ops/syn/xgmac/syn_if.c +@@ -445,7 +445,7 @@ static void *syn_init(struct nss_gmac_hal_platform_data *gmacpdata) + + spin_lock_init(&shd->nghd.slock); + +- netdev_info(ndev, "ioremap OK.Size 0x%x Ndev base 0x%lx macbase 0x%px\n", ++ netdev_dbg(ndev, "ioremap OK.Size 0x%x Ndev base 0x%lx macbase 0x%px\n", + gmacpdata->reg_len, + ndev->base_addr, + shd->nghd.mac_base); +-- +2.34.1 + diff --git a/qca/qca-nss-dp/patches/0013-nss_dp_main-Use-a-phy-handle-property-to-connect-to-.patch b/qca/qca-nss-dp/patches/0013-nss_dp_main-Use-a-phy-handle-property-to-connect-to-.patch new file mode 100644 index 000000000..ea6993d75 --- /dev/null +++ b/qca/qca-nss-dp/patches/0013-nss_dp_main-Use-a-phy-handle-property-to-connect-to-.patch @@ -0,0 +1,189 @@ +From 8293a26ca56ee2e9a88e4efb5dcc7f647803cd8c Mon Sep 17 00:00:00 2001 +From: Alexandru Gagniuc +Date: Sun, 5 Jun 2022 21:45:09 -0500 +Subject: [PATCH] nss_dp_main: Use a 'phy-handle' property to connect to the + PHY + +The original method of connecting a PHY to the ethernet controller +requires the "qcom,link-poll", and "qcom,phy-mdio-addr" devicetree +properties. This is redundant. The PHY node already contains the MDIO +address, and attaching a PHY implies "link-poll". + +Allow using a "phy-handle" property. Remove the following properties, +as they are no longer used: + * "qcom,link-poll" + * "qcom,phy-mdio-addr" + * "mdio-bus" + * "qcom,forced-speed" + * "qcom,forced-duplex" + +Signed-off-by: Alexandru Gagniuc +--- + include/nss_dp_dev.h | 5 +-- + nss_dp_main.c | 91 +++++--------------------------------------- + 2 files changed, 10 insertions(+), 86 deletions(-) + +diff --git a/include/nss_dp_dev.h b/include/nss_dp_dev.h +index 19b3e78..63a857a 100644 +--- a/include/nss_dp_dev.h ++++ b/include/nss_dp_dev.h +@@ -100,13 +100,10 @@ struct nss_dp_dev { + unsigned long drv_flags; /* Driver specific feature flags */ + + /* Phy related stuff */ ++ struct device_node *phy_node; + struct phy_device *phydev; /* Phy device */ + struct mii_bus *miibus; /* MII bus */ + phy_interface_t phy_mii_type; /* RGMII/SGMII/QSGMII */ +- uint32_t phy_mdio_addr; /* Mdio address */ +- bool link_poll; /* Link polling enable? */ +- uint32_t forced_speed; /* Forced speed? */ +- uint32_t forced_duplex; /* Forced duplex? */ + uint32_t link_state; /* Current link state */ + uint32_t pause; /* Current flow control settings */ + +diff --git a/nss_dp_main.c b/nss_dp_main.c +index 441c300..a1e8627 100644 +--- a/nss_dp_main.c ++++ b/nss_dp_main.c +@@ -399,7 +399,7 @@ static int nss_dp_open(struct net_device *netdev) + + netif_start_queue(netdev); + +- if (!dp_priv->link_poll) { ++ if (!dp_priv->phydev) { + /* Notify data plane link is up */ + if (dp_priv->data_plane_ops->link_state(dp_priv->dpc, 1)) { + netdev_dbg(netdev, "Data plane set link failed\n"); +@@ -576,6 +576,8 @@ static int32_t nss_dp_of_get_pdata(struct device_node *np, + return -EFAULT; + } + ++ dp_priv->phy_node = of_parse_phandle(np, "phy-handle", 0); ++ + if (of_property_read_u32(np, "qcom,mactype", &hal_pdata->mactype)) { + pr_err("%s: error reading mactype\n", np->name); + return -EFAULT; +@@ -594,16 +596,6 @@ static int32_t nss_dp_of_get_pdata(struct device_node *np, + #else + of_get_phy_mode(np, &dp_priv->phy_mii_type); + #endif +- dp_priv->link_poll = of_property_read_bool(np, "qcom,link-poll"); +- if (of_property_read_u32(np, "qcom,phy-mdio-addr", +- &dp_priv->phy_mdio_addr) && dp_priv->link_poll) { +- pr_err("%s: mdio addr required if link polling is enabled\n", +- np->name); +- return -EFAULT; +- } +- +- of_property_read_u32(np, "qcom,forced-speed", &dp_priv->forced_speed); +- of_property_read_u32(np, "qcom,forced-duplex", &dp_priv->forced_duplex); + + ret = of_get_mac_address(np, maddr); + if (!ret && is_valid_ether_addr(maddr)) { +@@ -636,50 +628,6 @@ static int32_t nss_dp_of_get_pdata(struct device_node *np, + return 0; + } + +-/* +- * nss_dp_mdio_attach() +- */ +-static struct mii_bus *nss_dp_mdio_attach(struct platform_device *pdev) +-{ +- struct device_node *mdio_node; +- struct platform_device *mdio_plat; +- struct ipq40xx_mdio_data *mdio_data; +- +- /* +- * Find mii_bus using "mdio-bus" handle. +- */ +- mdio_node = of_parse_phandle(pdev->dev.of_node, "mdio-bus", 0); +- if (mdio_node) { +- return of_mdio_find_bus(mdio_node); +- } +- +- mdio_node = of_find_compatible_node(NULL, NULL, "qcom,qca-mdio"); +- if (!mdio_node) { +- mdio_node = of_find_compatible_node(NULL, NULL, +- "qcom,ipq40xx-mdio"); +- if (!mdio_node) { +- dev_err(&pdev->dev, "cannot find mdio node by phandle\n"); +- return NULL; +- } +- } +- +- mdio_plat = of_find_device_by_node(mdio_node); +- if (!mdio_plat) { +- dev_err(&pdev->dev, "cannot find platform device from mdio node\n"); +- of_node_put(mdio_node); +- return NULL; +- } +- +- mdio_data = dev_get_drvdata(&mdio_plat->dev); +- if (!mdio_data) { +- dev_err(&pdev->dev, "cannot get mii bus reference from device data\n"); +- of_node_put(mdio_node); +- return NULL; +- } +- +- return mdio_data->mii_bus; +-} +- + #ifdef CONFIG_NET_SWITCHDEV + /* + * nss_dp_is_phy_dev() +@@ -738,7 +686,6 @@ static int32_t nss_dp_probe(struct platform_device *pdev) + struct device_node *np = pdev->dev.of_node; + struct nss_gmac_hal_platform_data gmac_hal_pdata; + int32_t ret = 0; +- uint8_t phy_id[MII_BUS_ID_SIZE + 3]; + #if defined(NSS_DP_PPE_SUPPORT) + uint32_t vsi_id; + fal_port_t port_id; +@@ -813,37 +760,17 @@ static int32_t nss_dp_probe(struct platform_device *pdev) + + dp_priv->drv_flags |= NSS_DP_PRIV_FLAG(INIT_DONE); + +- if (dp_priv->link_poll) { +- dp_priv->miibus = nss_dp_mdio_attach(pdev); +- if (!dp_priv->miibus) { +- netdev_dbg(netdev, "failed to find miibus\n"); +- goto phy_setup_fail; +- } +- snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, +- dp_priv->miibus->id, dp_priv->phy_mdio_addr); +- ++ if (dp_priv->phy_node) { + SET_NETDEV_DEV(netdev, &pdev->dev); +- +- dp_priv->phydev = phy_connect(netdev, phy_id, +- &nss_dp_adjust_link, +- dp_priv->phy_mii_type); ++ dp_priv->phydev = of_phy_connect(netdev, dp_priv->phy_node, ++ &nss_dp_adjust_link, 0, ++ dp_priv->phy_mii_type); + if (IS_ERR(dp_priv->phydev)) { +- netdev_dbg(netdev, "failed to connect to phy device\n"); ++ dev_err(&pdev->dev, "Could not attach to PHY\n"); + goto phy_setup_fail; + } + +-#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 5, 0)) +- dp_priv->phydev->advertising |= +- (ADVERTISED_Pause | ADVERTISED_Asym_Pause); +- dp_priv->phydev->supported |= +- (SUPPORTED_Pause | SUPPORTED_Asym_Pause); +-#else +- linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, dp_priv->phydev->advertising); +- linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, dp_priv->phydev->advertising); +- +- linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, dp_priv->phydev->supported); +- linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, dp_priv->phydev->supported); +-#endif ++ phy_attached_info(dp_priv->phydev); + } + + #if defined(NSS_DP_PPE_SUPPORT) +-- +2.36.1 + diff --git a/qca/qca-nss-dp/patches/0014-nss-dp-edma-v1-switch-to-napi_gro_receive.patch b/qca/qca-nss-dp/patches/0014-nss-dp-edma-v1-switch-to-napi_gro_receive.patch new file mode 100644 index 000000000..3a437bd37 --- /dev/null +++ b/qca/qca-nss-dp/patches/0014-nss-dp-edma-v1-switch-to-napi_gro_receive.patch @@ -0,0 +1,46 @@ +From 57b521e876986844dfe34457f39c62dc8100424d Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Thu, 23 Jun 2022 14:18:50 +0200 +Subject: [PATCH] nss-dp: edma-v1: switch to napi_gro_receive + +Utilize napi_gro_receive instead of plain netif_receive_skb on EDMA v1. +It provides significant performance improvements when testing with iperf3. + +Signed-off-by: Robert Marko +--- + Makefile | 2 +- + hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c | 4 ++++ + 2 files changed, 5 insertions(+), 1 deletion(-) + +diff --git a/Makefile b/Makefile +index 8e81317..dcfa8ca 100644 +--- a/Makefile ++++ b/Makefile +@@ -25,7 +25,7 @@ qca-nss-dp-objs += hal/dp_ops/edma_dp/edma_v1/edma_cfg.o \ + hal/gmac_ops/qcom/qcom_if.o \ + hal/gmac_ops/syn/xgmac/syn_if.o + NSS_DP_INCLUDE += -I$(obj)/hal/dp_ops/edma_dp/edma_v1/include +-ccflags-y += -DNSS_DP_PPE_SUPPORT ++ccflags-y += -DNSS_DP_PPE_SUPPORT -DNSS_DP_ENABLE_NAPI_GRO + endif + + ifeq ($(SoC),$(filter $(SoC),ipq807x)) +diff --git a/hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c b/hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c +index 5780a30..6ee1451 100644 +--- a/hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c ++++ b/hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c +@@ -411,7 +411,11 @@ static uint32_t edma_clean_rx(struct edma_hw *ehw, + NSS_PTP_EVENT_SERVICE_CODE)) + nss_phy_tstamp_rx_buf(ndev, skb); + else ++#if defined(NSS_DP_ENABLE_NAPI_GRO) ++ napi_gro_receive(&ehw->napi, skb); ++#else + netif_receive_skb(skb); ++#endif + + next_rx_desc: + /* +-- +2.36.1 + diff --git a/qca/qca-nss-drv/Makefile b/qca/qca-nss-drv/Makefile new file mode 100644 index 000000000..92616caaa --- /dev/null +++ b/qca/qca-nss-drv/Makefile @@ -0,0 +1,129 @@ +include $(TOPDIR)/rules.mk + +PKG_NAME:=qca-nss-drv +PKG_RELEASE:=$(AUTORELEASE) + +PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/nss-drv.git +PKG_SOURCE_PROTO:=git +PKG_SOURCE_DATE:=2022-03-07 +PKG_SOURCE_VERSION:=397c88cf184e0eb011dd44ad82c2dfae60ece1b4 +PKG_MIRROR_HASH:=a3bea305d85fcec3d77f9b40d06a71b65ccf3d8b98018d9c8c23d6ad95e6aedc + +PKG_BUILD_PARALLEL:=1 + +include $(INCLUDE_DIR)/kernel.mk +include $(INCLUDE_DIR)/package.mk + +NSS_CLIENTS_DIR:=$(TOPDIR)/qca/src/qca-nss-clients + +define KernelPackage/qca-nss-drv + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + DEPENDS:=@(TARGET_ipq807x||TARGET_ipq60xx) +kmod-qca-nss-dp + TITLE:=Kernel driver for NSS (core driver) + FILES:=$(PKG_BUILD_DIR)/qca-nss-drv.ko + AUTOLOAD:=$(call AutoLoad,32,qca-nss-drv) +endef + +define KernelPackage/qca-nss-drv/install + $(INSTALL_DIR) $(1)/lib/debug + $(INSTALL_DIR) $(1)/etc/init.d + $(INSTALL_DIR) $(1)/etc/sysctl.d + $(INSTALL_DIR) $(1)/etc/hotplug.d/firmware + $(INSTALL_DIR) $(1)/etc/config + + $(INSTALL_BIN) ./files/qca-nss-drv.debug $(1)/lib/debug/qca-nss-drv + $(INSTALL_BIN) ./files/qca-nss-drv.init $(1)/etc/init.d/qca-nss-drv + $(INSTALL_BIN) ./files/qca-nss-drv.sysctl $(1)/etc/sysctl.d/qca-nss-drv.conf + $(INSTALL_BIN) ./files/qca-nss-drv.hotplug $(1)/etc/hotplug.d/firmware/10-qca-nss-fw + $(INSTALL_BIN) ./files/qca-nss-drv.conf $(1)/etc/config/nss + +endef + +define KernelPackage/qca-nss-drv/Description +This package contains a NSS driver for QCA chipset +endef + +define Build/InstallDev + mkdir -p $(1)/usr/include/qca-nss-drv + $(CP) $(PKG_BUILD_DIR)/exports/* $(1)/usr/include/qca-nss-drv/ +endef + +EXTRA_CFLAGS+= -I$(STAGING_DIR)/usr/include/qca-nss-gmac \ + -I$(STAGING_DIR)/usr/include/qca-nss-dp \ + -I$(STAGING_DIR)/usr/include/qca-ssdk \ + -Wno-unused-variable + +ifneq (, $(findstring $(CONFIG_TARGET_BOARD), "ipq807x" "ipq60xx")) +EXTRA_CFLAGS+= -DNSS_MEM_PROFILE_MEDIUM +LOW_MEM_PROFILE_MAKE_OPTS=y +endif + +ifeq ($(CONFIG_KERNEL_SKB_FIXED_SIZE_2K),y) +EXTRA_CFLAGS+= -DNSS_SKB_FIXED_SIZE_2K +endif + +DRV_MAKE_OPTS:= +ifeq ($(LOW_MEM_PROFILE_MAKE_OPTS),y) +DRV_MAKE_OPTS+= \ + NSS_DRV_C2C_ENABLE=n \ + NSS_DRV_CAPWAP_ENABLE=n \ + NSS_DRV_CLMAP_ENABLE=n \ + NSS_DRV_CRYPTO_ENABLE=y \ + NSS_DRV_DTLS_ENABLE=n \ + NSS_DRV_GRE_ENABLE=n \ + NSS_DRV_GRE_REDIR_ENABLE=n \ + NSS_DRV_GRE_TUNNEL_ENABLE=n \ + NSS_DRV_IGS_ENABLE=n \ + NSS_DRV_IPSEC_ENABLE=n \ + NSS_DRV_LAG_ENABLE=n \ + NSS_DRV_L2TP_ENABLE=n \ + NSS_DRV_MAPT_ENABLE=n \ + NSS_DRV_OAM_ENABLE=n \ + NSS_DRV_PPTP_ENABLE=n \ + NSS_DRV_PORTID_ENABLE=n \ + NSS_DRV_PVXLAN_ENABLE=n \ + NSS_DRV_QRFS_ENABLE=n \ + NSS_DRV_QVPN_ENABLE=n \ + NSS_DRV_RMNET_ENABLE=n \ + NSS_DRV_SHAPER_ENABLE=n \ + NSS_DRV_SJACK_ENABLE=n \ + NSS_DRV_TLS_ENABLE=n \ + NSS_DRV_TRUSTSEC_ENABLE=n \ + NSS_DRV_TSTAMP_ENABLE=n \ + NSS_DRV_TUN6RD_ENABLE=n \ + NSS_DRV_TUNIPIP6_ENABLE=n \ + NSS_DRV_VXLAN_ENABLE=n \ + NSS_DRV_MATCH_ENABLE=n \ + NSS_DRV_MIRROR_ENABLE=n \ + NSS_DRV_PPPOE_ENABLE=n \ + NSS_DRV_VIRT_IF_ENABLE=n \ + NSS_DRV_VLAN_ENABLE=n \ + NSS_DRV_BRIDGE_ENABLE=n \ + NSS_DRV_WIFI_EXT_VDEV_ENABLE=n \ + NSS_DRV_WIFI_MESH_ENABLE=n +endif + +ifeq ($(CONFIG_TARGET_BOARD), "ipq807x") + SOC="ipq807x_64" +else ifeq ($(CONFIG_TARGET_BOARD), "ipq60xx") + SOC="ipq60xx_64" +endif + +define Build/Configure + $(LN) arch/nss_$(SOC).h $(PKG_BUILD_DIR)/exports/nss_arch.h +endef + +define Build/Compile + +$(MAKE) -C "$(LINUX_DIR)" $(strip $(DRV_MAKE_OPTS)) \ + CROSS_COMPILE="$(TARGET_CROSS)" \ + ARCH="$(LINUX_KARCH)" \ + M="$(PKG_BUILD_DIR)" \ + EXTRA_CFLAGS="$(EXTRA_CFLAGS)" SoC=$(SOC) \ + $(KERNEL_MAKE_FLAGS) \ + $(PKG_JOBS) \ + modules +endef + +$(eval $(call KernelPackage,qca-nss-drv)) diff --git a/qca/qca-nss-drv/files/qca-nss-drv.conf b/qca/qca-nss-drv/files/qca-nss-drv.conf new file mode 100644 index 000000000..a8a1fbf40 --- /dev/null +++ b/qca/qca-nss-drv/files/qca-nss-drv.conf @@ -0,0 +1,6 @@ +config nss_firmware 'qca_nss_0' + +config nss_firmware 'qca_nss_1' + +config general + option enable_rps '1' diff --git a/qca/qca-nss-drv/files/qca-nss-drv.debug b/qca/qca-nss-drv/files/qca-nss-drv.debug new file mode 100644 index 000000000..5d435c3a7 --- /dev/null +++ b/qca/qca-nss-drv/files/qca-nss-drv.debug @@ -0,0 +1,26 @@ +#!/bin/sh /sbin/sysdebug +# +# Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +# + +log cat /sys/kernel/debug/qca-nss-drv/stats/pppoe +log cat /sys/kernel/debug/qca-nss-drv/stats/n2h +log cat /sys/kernel/debug/qca-nss-drv/stats/ipv6 +log cat /sys/kernel/debug/qca-nss-drv/stats/ipv4 +log cat /sys/kernel/debug/qca-nss-drv/stats/gmac +log cat /sys/kernel/debug/qca-nss-drv/stats/drv +log cat /sys/kernel/debug/qca-nss-drv/stats/wifi +log cat /sys/kernel/debug/qca-nss-drv/stats/wifi_if +log cat /sys/kernel/debug/qca-nss-drv/stats/eth_rx diff --git a/qca/qca-nss-drv/files/qca-nss-drv.hotplug b/qca/qca-nss-drv/files/qca-nss-drv.hotplug new file mode 100644 index 000000000..1e4813838 --- /dev/null +++ b/qca/qca-nss-drv/files/qca-nss-drv.hotplug @@ -0,0 +1,70 @@ +#!/bin/sh +# +# Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +# + +KERNEL=`uname -r` +case "${KERNEL}" in + 3.4*) + select_or_load=load_nss_fw + ;; + *) + select_or_load=select_nss_fw + ;; +esac + +load_nss_fw () { + ls -l $1 | awk ' { print $9,$5 } '> /dev/console + echo 1 > /sys/class/firmware/$DEVICENAME/loading + cat $1 > /sys/class/firmware/$DEVICENAME/data + echo 0 > /sys/class/firmware/$DEVICENAME/loading +} + +select_nss_fw () { + rm -f /lib/firmware/$DEVICENAME + ln -s $1 /lib/firmware/$DEVICENAME + ls -l /lib/firmware/$DEVICENAME | awk ' { print $9,$5 } '> /dev/console +} + +[ "$ACTION" != "add" ] && exit + +# dev name for UCI, since it doesn't let you use . or - +SDEVNAME=$(echo ${DEVICENAME} | sed s/[.-]/_/g) + +SELECTED_FW=$(uci get nss.${SDEVNAME}.firmware 2>/dev/null) +[ -e "${SELECTED_FW}" ] && { + $select_or_load ${SELECTED_FW} + exit +} + +case $DEVICENAME in + qca-nss0* | qca-nss.0*) + if [ -e /lib/firmware/qca-nss0-enterprise.bin ] ; then + $select_or_load /lib/firmware/qca-nss0-enterprise.bin + else + $select_or_load /lib/firmware/qca-nss0-retail.bin + fi + exit + ;; + qca-nss1* | qca-nss.1*) + if [ -e /lib/firmware/qca-nss1-enterprise.bin ] ; then + $select_or_load /lib/firmware/qca-nss1-enterprise.bin + else + $select_or_load /lib/firmware/qca-nss1-retail.bin + fi + exit + ;; +esac + diff --git a/qca/qca-nss-drv/files/qca-nss-drv.init b/qca/qca-nss-drv/files/qca-nss-drv.init new file mode 100644 index 000000000..de12cb6d1 --- /dev/null +++ b/qca/qca-nss-drv/files/qca-nss-drv.init @@ -0,0 +1,50 @@ +#!/bin/sh /etc/rc.common +# +# Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +# + +START=70 + +enable_rps() { + irq_nss_rps=`grep nss_queue1 /proc/interrupts | cut -d ':' -f 1 | tr -d ' '` + for entry in $irq_nss_rps + do + echo 2 > /proc/irq/$entry/smp_affinity + done + + irq_nss_rps=`grep nss_queue2 /proc/interrupts | cut -d ':' -f 1 | tr -d ' '` + for entry in $irq_nss_rps + do + echo 4 > /proc/irq/$entry/smp_affinity + done + + irq_nss_rps=`grep nss_queue3 /proc/interrupts | cut -d ':' -f 1 | tr -d ' '` + for entry in $irq_nss_rps + do + echo 8 > /proc/irq/$entry/smp_affinity + done + + # Enable NSS RPS + sysctl -w dev.nss.rps.enable=1 >/dev/null 2>/dev/null + +} + + +start() { + local rps_enabled="$(uci_get nss @general[0] enable_rps)" + if [ "$rps_enabled" -eq 1 ]; then + enable_rps + fi +} diff --git a/qca/qca-nss-drv/files/qca-nss-drv.sysctl b/qca/qca-nss-drv/files/qca-nss-drv.sysctl new file mode 100644 index 000000000..fc36c33eb --- /dev/null +++ b/qca/qca-nss-drv/files/qca-nss-drv.sysctl @@ -0,0 +1,4 @@ +# Default Number of connection configuration +dev.nss.ipv4cfg.ipv4_conn=4096 +dev.nss.ipv6cfg.ipv6_conn=4096 + diff --git a/qca/qca-nss-drv/patches/0001-core-add-5.10-kernel-to-version-check.patch b/qca/qca-nss-drv/patches/0001-core-add-5.10-kernel-to-version-check.patch new file mode 100644 index 000000000..3fea9b5ce --- /dev/null +++ b/qca/qca-nss-drv/patches/0001-core-add-5.10-kernel-to-version-check.patch @@ -0,0 +1,25 @@ +From 3885c752e12f74cad6c97888b797e5903ad1930d Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Thu, 13 May 2021 23:22:38 +0200 +Subject: [PATCH] core: add 5.10 kernel to version check + +NSS DRV has a kernel version check, so simply add +5.10 as supported. + +Signed-off-by: Robert Marko +--- + nss_core.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/nss_core.c ++++ b/nss_core.c +@@ -52,7 +52,8 @@ + (((LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0)))) || \ + (((LINUX_VERSION_CODE >= KERNEL_VERSION(3, 18, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 19, 0)))) || \ + (((LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(4, 5, 0)))) || \ +-(((LINUX_VERSION_CODE >= KERNEL_VERSION(5, 4, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 5, 0)))))) ++(((LINUX_VERSION_CODE >= KERNEL_VERSION(5, 4, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 5, 0)))) || \ ++(((LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 11, 0)))))) + #error "Check skb recycle code in this file to match Linux version" + #endif + diff --git a/qca/qca-nss-drv/patches/0002-nss-drv-replace-ioremap_nocache-with-ioremap.patch b/qca/qca-nss-drv/patches/0002-nss-drv-replace-ioremap_nocache-with-ioremap.patch new file mode 100644 index 000000000..89d650be1 --- /dev/null +++ b/qca/qca-nss-drv/patches/0002-nss-drv-replace-ioremap_nocache-with-ioremap.patch @@ -0,0 +1,181 @@ +From 0cffa7bb366a4e0ff5665d6fc2fa33c1437cb397 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Thu, 13 May 2021 23:33:18 +0200 +Subject: [PATCH 2/8] nss-drv: replace ioremap_nocache() with ioremap() + +ioremap_nocache() does not exist anymore. + +Signed-off-by: Robert Marko +--- + nss_hal/ipq50xx/nss_hal_pvt.c | 6 +++--- + nss_hal/ipq60xx/nss_hal_pvt.c | 8 ++++---- + nss_hal/ipq806x/nss_hal_pvt.c | 4 ++-- + nss_hal/ipq807x/nss_hal_pvt.c | 6 +++--- + nss_hal/nss_hal.c | 4 ++-- + nss_meminfo.c | 2 +- + nss_ppe.c | 2 +- + 7 files changed, 16 insertions(+), 16 deletions(-) + +diff --git a/nss_hal/ipq50xx/nss_hal_pvt.c b/nss_hal/ipq50xx/nss_hal_pvt.c +index 3d6dfd0..e3e4bd2 100644 +--- a/nss_hal/ipq50xx/nss_hal_pvt.c ++++ b/nss_hal/ipq50xx/nss_hal_pvt.c +@@ -184,13 +184,13 @@ static struct nss_platform_data *__nss_hal_of_get_pdata(struct platform_device * + npd->nphys = res_nphys.start; + npd->qgic_phys = res_qgic_phys.start; + +- npd->nmap = ioremap_nocache(npd->nphys, resource_size(&res_nphys)); ++ npd->nmap = ioremap(npd->nphys, resource_size(&res_nphys)); + if (!npd->nmap) { + nss_info_always("%px: nss%d: ioremap() fail for nphys\n", nss_ctx, nss_ctx->id); + goto out; + } + +- npd->qgic_map = ioremap_nocache(npd->qgic_phys, resource_size(&res_qgic_phys)); ++ npd->qgic_map = ioremap(npd->qgic_phys, resource_size(&res_qgic_phys)); + if (!npd->qgic_map) { + nss_info_always("%px: nss%d: ioremap() fail for qgic map\n", nss_ctx, nss_ctx->id); + goto out; +@@ -348,7 +348,7 @@ static int __nss_hal_common_reset(struct platform_device *nss_dev) + + of_node_put(cmn); + +- nss_misc_reset = ioremap_nocache(res_nss_misc_reset.start, resource_size(&res_nss_misc_reset)); ++ nss_misc_reset = ioremap(res_nss_misc_reset.start, resource_size(&res_nss_misc_reset)); + if (!nss_misc_reset) { + pr_err("%px: ioremap fail for nss_misc_reset\n", nss_dev); + return -EFAULT; +diff --git a/nss_hal/ipq60xx/nss_hal_pvt.c b/nss_hal/ipq60xx/nss_hal_pvt.c +index 4c84cb9..e76ef6d 100644 +--- a/nss_hal/ipq60xx/nss_hal_pvt.c ++++ b/nss_hal/ipq60xx/nss_hal_pvt.c +@@ -207,13 +207,13 @@ static struct nss_platform_data *__nss_hal_of_get_pdata(struct platform_device * + npd->nphys = res_nphys.start; + npd->qgic_phys = res_qgic_phys.start; + +- npd->nmap = ioremap_nocache(npd->nphys, resource_size(&res_nphys)); ++ npd->nmap = ioremap(npd->nphys, resource_size(&res_nphys)); + if (!npd->nmap) { + nss_info_always("%px: nss%d: ioremap() fail for nphys\n", nss_ctx, nss_ctx->id); + goto out; + } + +- npd->qgic_map = ioremap_nocache(npd->qgic_phys, resource_size(&res_qgic_phys)); ++ npd->qgic_map = ioremap(npd->qgic_phys, resource_size(&res_qgic_phys)); + if (!npd->qgic_map) { + nss_info_always("%px: nss%d: ioremap() fail for qgic map\n", nss_ctx, nss_ctx->id); + goto out; +@@ -433,13 +433,13 @@ static int __nss_hal_common_reset(struct platform_device *nss_dev) + + of_node_put(cmn); + +- nss_misc_reset = ioremap_nocache(res_nss_misc_reset.start, resource_size(&res_nss_misc_reset)); ++ nss_misc_reset = ioremap(res_nss_misc_reset.start, resource_size(&res_nss_misc_reset)); + if (!nss_misc_reset) { + pr_err("%px: ioremap fail for nss_misc_reset\n", nss_dev); + return -EFAULT; + } + +- nss_misc_reset_flag = ioremap_nocache(res_nss_misc_reset_flag.start, resource_size(&res_nss_misc_reset_flag)); ++ nss_misc_reset_flag = ioremap(res_nss_misc_reset_flag.start, resource_size(&res_nss_misc_reset_flag)); + if (!nss_misc_reset_flag) { + pr_err("%px: ioremap fail for nss_misc_reset_flag\n", nss_dev); + return -EFAULT; +diff --git a/nss_hal/ipq806x/nss_hal_pvt.c b/nss_hal/ipq806x/nss_hal_pvt.c +index b8733e0..52d63b0 100644 +--- a/nss_hal/ipq806x/nss_hal_pvt.c ++++ b/nss_hal/ipq806x/nss_hal_pvt.c +@@ -458,7 +458,7 @@ static struct nss_platform_data *__nss_hal_of_get_pdata(struct platform_device * + npd->nphys = res_nphys.start; + npd->vphys = res_vphys.start; + +- npd->nmap = ioremap_nocache(npd->nphys, resource_size(&res_nphys)); ++ npd->nmap = ioremap(npd->nphys, resource_size(&res_nphys)); + if (!npd->nmap) { + nss_info_always("%px: nss%d: ioremap() fail for nphys\n", nss_ctx, nss_ctx->id); + goto out; +@@ -711,7 +711,7 @@ static int __nss_hal_common_reset(struct platform_device *nss_dev) + } + of_node_put(cmn); + +- fpb_base = ioremap_nocache(res_nss_fpb_base.start, resource_size(&res_nss_fpb_base)); ++ fpb_base = ioremap(res_nss_fpb_base.start, resource_size(&res_nss_fpb_base)); + if (!fpb_base) { + pr_err("%px: ioremap fail for nss_fpb_base\n", nss_dev); + return -EFAULT; +diff --git a/nss_hal/ipq807x/nss_hal_pvt.c b/nss_hal/ipq807x/nss_hal_pvt.c +index b95a23c..bb8f42f 100644 +--- a/nss_hal/ipq807x/nss_hal_pvt.c ++++ b/nss_hal/ipq807x/nss_hal_pvt.c +@@ -234,7 +234,7 @@ static struct nss_platform_data *__nss_hal_of_get_pdata(struct platform_device * + npd->vphys = res_vphys.start; + npd->qgic_phys = res_qgic_phys.start; + +- npd->nmap = ioremap_nocache(npd->nphys, resource_size(&res_nphys)); ++ npd->nmap = ioremap(npd->nphys, resource_size(&res_nphys)); + if (!npd->nmap) { + nss_info_always("%px: nss%d: ioremap() fail for nphys\n", nss_ctx, nss_ctx->id); + goto out; +@@ -247,7 +247,7 @@ static struct nss_platform_data *__nss_hal_of_get_pdata(struct platform_device * + goto out; + } + +- npd->qgic_map = ioremap_nocache(npd->qgic_phys, resource_size(&res_qgic_phys)); ++ npd->qgic_map = ioremap(npd->qgic_phys, resource_size(&res_qgic_phys)); + if (!npd->qgic_map) { + nss_info_always("%px: nss%d: ioremap() fail for qgic map\n", nss_ctx, nss_ctx->id); + goto out; +@@ -467,7 +467,7 @@ static int __nss_hal_common_reset(struct platform_device *nss_dev) + } + of_node_put(cmn); + +- nss_misc_reset = ioremap_nocache(res_nss_misc_reset.start, resource_size(&res_nss_misc_reset)); ++ nss_misc_reset = ioremap(res_nss_misc_reset.start, resource_size(&res_nss_misc_reset)); + if (!nss_misc_reset) { + pr_err("%px: ioremap fail for nss_misc_reset\n", nss_dev); + return -EFAULT; +diff --git a/nss_hal/nss_hal.c b/nss_hal/nss_hal.c +index d58bb57..57974c1 100644 +--- a/nss_hal/nss_hal.c ++++ b/nss_hal/nss_hal.c +@@ -78,9 +78,9 @@ int nss_hal_firmware_load(struct nss_ctx_instance *nss_ctx, struct platform_devi + return rc; + } + +- load_mem = ioremap_nocache(npd->load_addr, nss_fw->size); ++ load_mem = ioremap(npd->load_addr, nss_fw->size); + if (!load_mem) { +- nss_info_always("%px: ioremap_nocache failed: %x", nss_ctx, npd->load_addr); ++ nss_info_always("%px: ioremap failed: %x", nss_ctx, npd->load_addr); + release_firmware(nss_fw); + return rc; + } +diff --git a/nss_meminfo.c b/nss_meminfo.c +index e24e6be..2255eae 100644 +--- a/nss_meminfo.c ++++ b/nss_meminfo.c +@@ -728,7 +728,7 @@ bool nss_meminfo_init(struct nss_ctx_instance *nss_ctx) + /* + * meminfo_start is the label where the start address of meminfo map is stored. + */ +- meminfo_start = (uint32_t *)ioremap_nocache(nss_ctx->load + NSS_MEMINFO_MAP_START_OFFSET, ++ meminfo_start = (uint32_t *)ioremap(nss_ctx->load + NSS_MEMINFO_MAP_START_OFFSET, + NSS_MEMINFO_RESERVE_AREA_SIZE); + if (!meminfo_start) { + nss_info_always("%px: cannot remap meminfo start\n", nss_ctx); +diff --git a/nss_ppe.c b/nss_ppe.c +index 46ce217..644fc98 100644 +--- a/nss_ppe.c ++++ b/nss_ppe.c +@@ -357,7 +357,7 @@ void nss_ppe_init(void) + /* + * Get the PPE base address + */ +- ppe_pvt.ppe_base = ioremap_nocache(PPE_BASE_ADDR, PPE_REG_SIZE); ++ ppe_pvt.ppe_base = ioremap(PPE_BASE_ADDR, PPE_REG_SIZE); + if (!ppe_pvt.ppe_base) { + nss_warning("DRV can't get PPE base address\n"); + return; +-- +2.34.1 + diff --git a/qca/qca-nss-drv/patches/0003-DMA-Fix-NULL-pointer-exceptions.patch b/qca/qca-nss-drv/patches/0003-DMA-Fix-NULL-pointer-exceptions.patch new file mode 100644 index 000000000..0c13a7887 --- /dev/null +++ b/qca/qca-nss-drv/patches/0003-DMA-Fix-NULL-pointer-exceptions.patch @@ -0,0 +1,49 @@ +From 62e457f262aaa0db7113ad3ccbcb7ae49d4d7ea8 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Tue, 8 Jun 2021 23:24:43 +0200 +Subject: [PATCH] DMA: Fix NULL pointer exceptions + +There are multiple instances that pass NULL instead +of device to DMA functions. +That is incorrect and will cause kernel NULL pointer +exceptions. + +So, simply pass the device structure pointers. + +Signed-off-by: Robert Marko +--- + nss_core.c | 2 +- + nss_coredump.c | 4 ++-- + 2 files changed, 3 insertions(+), 3 deletions(-) + +--- a/nss_core.c ++++ b/nss_core.c +@@ -1617,7 +1617,7 @@ static int32_t nss_core_handle_cause_que + * + */ + if (unlikely((buffer_type == N2H_BUFFER_CRYPTO_RESP))) { +- dma_unmap_single(NULL, (desc->buffer + desc->payload_offs), desc->payload_len, DMA_FROM_DEVICE); ++ dma_unmap_single(nss_ctx->dev, (desc->buffer + desc->payload_offs), desc->payload_len, DMA_FROM_DEVICE); + goto consume; + } + +--- a/nss_coredump.c ++++ b/nss_coredump.c +@@ -154,7 +154,7 @@ void nss_fw_coredump_notify(struct nss_c + dma_addr = nss_own->meminfo_ctx.logbuffer_dma; + } + +- dma_sync_single_for_cpu(NULL, dma_addr, sizeof(struct nss_log_descriptor), DMA_FROM_DEVICE); ++ dma_sync_single_for_cpu(nss_own->dev, dma_addr, sizeof(struct nss_log_descriptor), DMA_FROM_DEVICE); + + /* + * If the current entry is smaller than or equal to the number of NSS_LOG_COREDUMP_LINE_NUM, +@@ -181,7 +181,7 @@ void nss_fw_coredump_notify(struct nss_c + + offset = (index * sizeof(struct nss_log_entry)) + + offsetof(struct nss_log_descriptor, log_ring_buffer); +- dma_sync_single_for_cpu(NULL, dma_addr + offset, ++ dma_sync_single_for_cpu(nss_own->dev, dma_addr + offset, + sizeof(struct nss_log_entry), DMA_FROM_DEVICE); + nss_info_always("%px: %s\n", nss_own, nle_print->message); + nle_print++; diff --git a/qca/qca-nss-drv/patches/0004-nss-drv-rework-NSS_CORE_DMA_CACHE_MAINT-ops.patch b/qca/qca-nss-drv/patches/0004-nss-drv-rework-NSS_CORE_DMA_CACHE_MAINT-ops.patch new file mode 100644 index 000000000..6ef442aad --- /dev/null +++ b/qca/qca-nss-drv/patches/0004-nss-drv-rework-NSS_CORE_DMA_CACHE_MAINT-ops.patch @@ -0,0 +1,573 @@ +From 12cf63f66bfe509da6d845e5c716efd99dadf01e Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Tue, 5 Apr 2022 15:38:18 +0200 +Subject: [PATCH 4/8] nss-drv: rework NSS_CORE_DMA_CACHE_MAINT ops + +Rework NSS_CORE_DMA_CACHE_MAINT ops to use standard dma sync ops instead +of using the direct arch function. This permit to skip any hack/patch +needed for nss-drv to correctly compile on upstream kernel. + +We drop any NSS_CORE_DMA_CACHE_MAINT use in nss_core and we correctly +use the dma_sync_single_for_device we correctly dma addr using the new +DMA helper. +We drop sync for IOREMAP addr and we just leave a memory block. +We hope the nss_profiler is correctly ported. +We finally drop the NSS_CORE_DMA_CACHE_MAINT jus in case someone wants +to use it. + +Signed-off-by: Ansuel Smith +--- + nss_core.c | 136 +++++++++++++++++++++++++--------- + nss_core.h | 41 +++++----- + nss_hal/ipq806x/nss_hal_pvt.c | 5 +- + nss_hal/ipq807x/nss_hal_pvt.c | 5 +- + nss_meminfo.c | 5 +- + nss_profiler.c | 3 +- + 6 files changed, 127 insertions(+), 68 deletions(-) + +diff --git a/nss_core.c b/nss_core.c +index 23dc155..f9e6014 100644 +--- a/nss_core.c ++++ b/nss_core.c +@@ -1429,6 +1429,8 @@ static inline void nss_core_handle_empty_buffers(struct nss_ctx_instance *nss_ct + uint32_t count, uint32_t hlos_index, + uint16_t mask) + { ++ struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; ++ + while (count) { + /* + * Since we only return the primary skb, we have no way to unmap +@@ -1482,7 +1484,9 @@ next: + n2h_desc_ring->hlos_index = hlos_index; + if_map->n2h_hlos_index[NSS_IF_N2H_EMPTY_BUFFER_RETURN_QUEUE] = hlos_index; + +- NSS_CORE_DMA_CACHE_MAINT((void *)&if_map->n2h_hlos_index[NSS_IF_N2H_EMPTY_BUFFER_RETURN_QUEUE], sizeof(uint32_t), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, ++ n2h_hlos_index_to_dma(mem_ctx->if_map_dma, NSS_IF_N2H_EMPTY_BUFFER_RETURN_QUEUE), ++ sizeof(uint32_t), DMA_TO_DEVICE); + NSS_CORE_DSB(); + } + +@@ -1504,6 +1508,7 @@ static int32_t nss_core_handle_cause_queue(struct int_ctx_instance *int_ctx, uin + struct nss_ctx_instance *nss_ctx = int_ctx->nss_ctx; + struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; + struct nss_if_mem_map *if_map = mem_ctx->if_map; ++ int dma_size; + + qid = nss_core_cause_to_queue(cause); + +@@ -1515,7 +1520,8 @@ static int32_t nss_core_handle_cause_queue(struct int_ctx_instance *int_ctx, uin + n2h_desc_ring = &nss_ctx->n2h_desc_ring[qid]; + desc_if = &n2h_desc_ring->desc_ring; + desc_ring = desc_if->desc; +- NSS_CORE_DMA_CACHE_MAINT((void *)&if_map->n2h_nss_index[qid], sizeof(uint32_t), DMA_FROM_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, n2h_nss_index_to_dma(mem_ctx->if_map_dma, qid), ++ sizeof(uint32_t), DMA_FROM_DEVICE); + NSS_CORE_DSB(); + nss_index = if_map->n2h_nss_index[qid]; + +@@ -1544,13 +1550,23 @@ static int32_t nss_core_handle_cause_queue(struct int_ctx_instance *int_ctx, uin + start = hlos_index; + end = (hlos_index + count) & mask; + if (end > start) { +- dmac_inv_range((void *)&desc_ring[start], (void *)&desc_ring[end] + sizeof(struct n2h_descriptor)); ++ dma_size = sizeof(struct n2h_descriptor) * (end - start + 1); ++ ++ dma_sync_single_for_device(nss_ctx->dev, n2h_desc_index_to_dma(if_map, qid, start), ++ dma_size, DMA_FROM_DEVICE); + } else { + /* + * We have wrapped around + */ +- dmac_inv_range((void *)&desc_ring[start], (void *)&desc_ring[mask] + sizeof(struct n2h_descriptor)); +- dmac_inv_range((void *)&desc_ring[0], (void *)&desc_ring[end] + sizeof(struct n2h_descriptor)); ++ dma_size = sizeof(struct n2h_descriptor) * (mask - start + 1); ++ ++ dma_sync_single_for_device(nss_ctx->dev, n2h_desc_index_to_dma(if_map, qid, start), ++ dma_size, DMA_FROM_DEVICE); ++ ++ dma_size = sizeof(struct n2h_descriptor) * (end + 1); ++ ++ dma_sync_single_for_device(nss_ctx->dev, n2h_desc_index_to_dma(if_map, qid, 0), dma_size, ++ DMA_FROM_DEVICE); + } + + /* +@@ -1679,7 +1695,8 @@ next: + n2h_desc_ring->hlos_index = hlos_index; + if_map->n2h_hlos_index[qid] = hlos_index; + +- NSS_CORE_DMA_CACHE_MAINT((void *)&if_map->n2h_hlos_index[qid], sizeof(uint32_t), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, n2h_hlos_index_to_dma(mem_ctx->if_map_dma, qid), ++ sizeof(uint32_t), DMA_TO_DEVICE); + NSS_CORE_DSB(); + + return count; +@@ -1691,11 +1708,12 @@ next: + */ + static void nss_core_init_nss(struct nss_ctx_instance *nss_ctx, struct nss_if_mem_map *if_map) + { ++ struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; + struct nss_top_instance *nss_top; + int ret; + int i; + +- NSS_CORE_DMA_CACHE_MAINT((void *)if_map, sizeof(*if_map), DMA_FROM_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, mem_ctx->if_map_dma, sizeof(*if_map), DMA_FROM_DEVICE); + NSS_CORE_DSB(); + + /* +@@ -1762,6 +1780,7 @@ static void nss_core_alloc_paged_buffers(struct nss_ctx_instance *nss_ctx, struc + uint16_t count, int16_t mask, int32_t hlos_index, uint32_t alloc_fail_count, + uint32_t buffer_type, uint32_t buffer_queue, uint32_t stats_index) + { ++ struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; + struct sk_buff *nbuf; + struct page *npage; + struct hlos_h2n_desc_rings *h2n_desc_ring = &nss_ctx->h2n_desc_rings[buffer_queue]; +@@ -1831,7 +1850,9 @@ static void nss_core_alloc_paged_buffers(struct nss_ctx_instance *nss_ctx, struc + /* + * Flush the descriptor + */ +- NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, ++ h2n_desc_index_to_dma(if_map, buffer_queue, hlos_index), ++ sizeof(*desc), DMA_TO_DEVICE); + + hlos_index = (hlos_index + 1) & (mask); + count--; +@@ -1845,7 +1866,8 @@ static void nss_core_alloc_paged_buffers(struct nss_ctx_instance *nss_ctx, struc + h2n_desc_ring->hlos_index = hlos_index; + if_map->h2n_hlos_index[buffer_queue] = hlos_index; + +- NSS_CORE_DMA_CACHE_MAINT(&if_map->h2n_hlos_index[buffer_queue], sizeof(uint32_t), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, h2n_hlos_index_to_dma(mem_ctx->if_map_dma, buffer_queue), ++ sizeof(uint32_t), DMA_TO_DEVICE); + NSS_CORE_DSB(); + + NSS_PKT_STATS_INC(&nss_top->stats_drv[stats_index]); +@@ -1858,7 +1880,7 @@ static void nss_core_alloc_paged_buffers(struct nss_ctx_instance *nss_ctx, struc + static void nss_core_alloc_jumbo_mru_buffers(struct nss_ctx_instance *nss_ctx, struct nss_if_mem_map *if_map, + int jumbo_mru, uint16_t count, int16_t mask, int32_t hlos_index) + { +- ++ struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; + struct sk_buff *nbuf; + struct hlos_h2n_desc_rings *h2n_desc_ring = &nss_ctx->h2n_desc_rings[NSS_IF_H2N_EMPTY_BUFFER_QUEUE]; + struct h2n_desc_if_instance *desc_if = &h2n_desc_ring->desc_ring; +@@ -1905,7 +1927,9 @@ static void nss_core_alloc_jumbo_mru_buffers(struct nss_ctx_instance *nss_ctx, s + /* + * Flush the descriptor + */ +- NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, ++ h2n_desc_index_to_dma(if_map, NSS_IF_H2N_EMPTY_BUFFER_QUEUE, hlos_index), ++ sizeof(*desc), DMA_TO_DEVICE); + + hlos_index = (hlos_index + 1) & (mask); + count--; +@@ -1919,7 +1943,8 @@ static void nss_core_alloc_jumbo_mru_buffers(struct nss_ctx_instance *nss_ctx, s + h2n_desc_ring->hlos_index = hlos_index; + if_map->h2n_hlos_index[NSS_IF_H2N_EMPTY_BUFFER_QUEUE] = hlos_index; + +- NSS_CORE_DMA_CACHE_MAINT(&if_map->h2n_hlos_index[NSS_IF_H2N_EMPTY_BUFFER_QUEUE], sizeof(uint32_t), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, h2n_hlos_index_to_dma(mem_ctx->if_map_dma, NSS_IF_H2N_EMPTY_BUFFER_QUEUE), ++ sizeof(uint32_t), DMA_TO_DEVICE); + NSS_CORE_DSB(); + + NSS_PKT_STATS_INC(&nss_top->stats_drv[NSS_DRV_STATS_TX_EMPTY]); +@@ -1932,6 +1957,7 @@ static void nss_core_alloc_jumbo_mru_buffers(struct nss_ctx_instance *nss_ctx, s + static void nss_core_alloc_max_avail_size_buffers(struct nss_ctx_instance *nss_ctx, struct nss_if_mem_map *if_map, + uint16_t max_buf_size, uint16_t count, int16_t mask, int32_t hlos_index) + { ++ struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; + struct hlos_h2n_desc_rings *h2n_desc_ring = &nss_ctx->h2n_desc_rings[NSS_IF_H2N_EMPTY_BUFFER_QUEUE]; + struct h2n_desc_if_instance *desc_if = &h2n_desc_ring->desc_ring; + struct h2n_descriptor *desc_ring = desc_if->desc; +@@ -1939,6 +1965,7 @@ static void nss_core_alloc_max_avail_size_buffers(struct nss_ctx_instance *nss_c + uint16_t payload_len = max_buf_size + NET_SKB_PAD; + uint16_t start = hlos_index; + uint16_t prev_hlos_index; ++ int dma_size; + + while (count) { + dma_addr_t buffer; +@@ -1991,13 +2018,26 @@ static void nss_core_alloc_max_avail_size_buffers(struct nss_ctx_instance *nss_c + * Flush the descriptors, including the descriptor at prev_hlos_index. + */ + if (prev_hlos_index > start) { +- dmac_clean_range((void *)&desc_ring[start], (void *)&desc_ring[prev_hlos_index] + sizeof(struct h2n_descriptor)); ++ dma_size = sizeof(struct h2n_descriptor) * (prev_hlos_index - start + 1); ++ ++ dma_sync_single_for_device(nss_ctx->dev, ++ h2n_desc_index_to_dma(if_map, NSS_IF_H2N_EMPTY_BUFFER_QUEUE, start), ++ dma_size, DMA_TO_DEVICE); + } else { + /* + * We have wrapped around + */ +- dmac_clean_range((void *)&desc_ring[start], (void *)&desc_ring[mask] + sizeof(struct h2n_descriptor)); +- dmac_clean_range((void *)&desc_ring[0], (void *)&desc_ring[prev_hlos_index] + sizeof(struct h2n_descriptor)); ++ dma_size = sizeof(struct h2n_descriptor) * (mask - start + 1); ++ ++ dma_sync_single_for_device(nss_ctx->dev, ++ h2n_desc_index_to_dma(if_map, NSS_IF_H2N_EMPTY_BUFFER_QUEUE, start), ++ dma_size, DMA_TO_DEVICE); ++ ++ dma_size = sizeof(struct h2n_descriptor) * (prev_hlos_index + 1); ++ ++ dma_sync_single_for_device(nss_ctx->dev, ++ h2n_desc_index_to_dma(if_map, NSS_IF_H2N_EMPTY_BUFFER_QUEUE, 0), ++ dma_size, DMA_TO_DEVICE); + } + + /* +@@ -2008,7 +2048,8 @@ static void nss_core_alloc_max_avail_size_buffers(struct nss_ctx_instance *nss_c + h2n_desc_ring->hlos_index = hlos_index; + if_map->h2n_hlos_index[NSS_IF_H2N_EMPTY_BUFFER_QUEUE] = hlos_index; + +- NSS_CORE_DMA_CACHE_MAINT(&if_map->h2n_hlos_index[NSS_IF_H2N_EMPTY_BUFFER_QUEUE], sizeof(uint32_t), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, h2n_hlos_index_to_dma(mem_ctx->if_map_dma, NSS_IF_H2N_EMPTY_BUFFER_QUEUE), ++ sizeof(uint32_t), DMA_TO_DEVICE); + NSS_CORE_DSB(); + + NSS_PKT_STATS_INC(&nss_top->stats_drv[NSS_DRV_STATS_TX_EMPTY]); +@@ -2021,6 +2062,7 @@ static void nss_core_alloc_max_avail_size_buffers(struct nss_ctx_instance *nss_c + static inline void nss_core_handle_empty_buffer_sos(struct nss_ctx_instance *nss_ctx, + struct nss_if_mem_map *if_map, uint16_t max_buf_size) + { ++ struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; + uint16_t count, size, mask; + int32_t nss_index, hlos_index; + struct hlos_h2n_desc_rings *h2n_desc_ring = &nss_ctx->h2n_desc_rings[NSS_IF_H2N_EMPTY_BUFFER_QUEUE]; +@@ -2031,7 +2073,8 @@ static inline void nss_core_handle_empty_buffer_sos(struct nss_ctx_instance *nss + /* + * Check how many empty buffers could be filled in queue + */ +- NSS_CORE_DMA_CACHE_MAINT(&if_map->h2n_nss_index[NSS_IF_H2N_EMPTY_BUFFER_QUEUE], sizeof(uint32_t), DMA_FROM_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, h2n_nss_index_to_dma(mem_ctx->if_map_dma, NSS_IF_H2N_EMPTY_BUFFER_QUEUE), ++ sizeof(uint32_t), DMA_FROM_DEVICE); + NSS_CORE_DSB(); + nss_index = if_map->h2n_nss_index[NSS_IF_H2N_EMPTY_BUFFER_QUEUE]; + +@@ -2076,6 +2119,7 @@ static inline void nss_core_handle_empty_buffer_sos(struct nss_ctx_instance *nss + static inline void nss_core_handle_paged_empty_buffer_sos(struct nss_ctx_instance *nss_ctx, + struct nss_if_mem_map *if_map, uint16_t max_buf_size) + { ++ struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; + uint16_t count, size, mask; + int32_t nss_index, hlos_index; + struct hlos_h2n_desc_rings *h2n_desc_ring = &nss_ctx->h2n_desc_rings[NSS_IF_H2N_EMPTY_PAGED_BUFFER_QUEUE]; +@@ -2083,7 +2127,8 @@ static inline void nss_core_handle_paged_empty_buffer_sos(struct nss_ctx_instanc + /* + * Check how many empty buffers could be filled in queue + */ +- NSS_CORE_DMA_CACHE_MAINT((void *)&if_map->h2n_nss_index[NSS_IF_H2N_EMPTY_PAGED_BUFFER_QUEUE], sizeof(uint32_t), DMA_FROM_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, h2n_nss_index_to_dma(mem_ctx->if_map_dma, NSS_IF_H2N_EMPTY_PAGED_BUFFER_QUEUE), ++ sizeof(uint32_t), DMA_FROM_DEVICE); + NSS_CORE_DSB(); + nss_index = if_map->h2n_nss_index[NSS_IF_H2N_EMPTY_PAGED_BUFFER_QUEUE]; + +@@ -2651,9 +2696,11 @@ void nss_skb_reuse(struct sk_buff *nbuf) + * Sends one skb to NSS FW + */ + static inline int32_t nss_core_send_buffer_simple_skb(struct nss_ctx_instance *nss_ctx, +- struct h2n_desc_if_instance *desc_if, uint32_t if_num, +- struct sk_buff *nbuf, uint16_t hlos_index, uint16_t flags, uint8_t buffer_type, uint16_t mss) ++ struct h2n_desc_if_instance *desc_if, uint32_t if_num, struct sk_buff *nbuf, ++ uint16_t qid, uint16_t hlos_index, uint16_t flags, uint8_t buffer_type, uint16_t mss) + { ++ struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; ++ struct nss_if_mem_map *if_map = mem_ctx->if_map; + struct h2n_descriptor *desc_ring = desc_if->desc; + struct h2n_descriptor *desc; + uint16_t bit_flags; +@@ -2707,7 +2754,8 @@ static inline int32_t nss_core_send_buffer_simple_skb(struct nss_ctx_instance *n + (nss_ptr_t)nbuf, (uint16_t)(nbuf->data - nbuf->head), nbuf->len, + sz, (uint32_t)nbuf->priority, mss, bit_flags); + +- NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, h2n_desc_index_to_dma(if_map, qid, hlos_index), ++ sizeof(*desc), DMA_TO_DEVICE); + + /* + * We are done using the skb fields and can reuse it now +@@ -2731,7 +2779,8 @@ no_reuse: + (nss_ptr_t)nbuf, (uint16_t)(nbuf->data - nbuf->head), nbuf->len, + (uint16_t)skb_end_offset(nbuf), (uint32_t)nbuf->priority, mss, bit_flags); + +- NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, h2n_desc_index_to_dma(if_map, qid, hlos_index), ++ sizeof(*desc), DMA_TO_DEVICE); + + NSS_PKT_STATS_INC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_TX_SIMPLE]); + return 1; +@@ -2745,9 +2794,11 @@ no_reuse: + * Used to differentiate from FRAGLIST + */ + static inline int32_t nss_core_send_buffer_nr_frags(struct nss_ctx_instance *nss_ctx, +- struct h2n_desc_if_instance *desc_if, uint32_t if_num, +- struct sk_buff *nbuf, uint16_t hlos_index, uint16_t flags, uint8_t buffer_type, uint16_t mss) ++ struct h2n_desc_if_instance *desc_if, uint32_t if_num, struct sk_buff *nbuf, ++ uint16_t qid, uint16_t hlos_index, uint16_t flags, uint8_t buffer_type, uint16_t mss) + { ++ struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; ++ struct nss_if_mem_map *if_map = mem_ctx->if_map; + struct h2n_descriptor *desc_ring = desc_if->desc; + struct h2n_descriptor *desc; + const skb_frag_t *frag; +@@ -2787,7 +2838,8 @@ static inline int32_t nss_core_send_buffer_nr_frags(struct nss_ctx_instance *nss + (nss_ptr_t)NULL, nbuf->data - nbuf->head, nbuf->len - nbuf->data_len, + skb_end_offset(nbuf), (uint32_t)nbuf->priority, mss, bit_flags | H2N_BIT_FLAG_FIRST_SEGMENT); + +- NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, h2n_desc_index_to_dma(if_map, qid, hlos_index), ++ sizeof(*desc), DMA_TO_DEVICE); + + /* + * Now handle rest of the fragments. +@@ -2811,7 +2863,8 @@ static inline int32_t nss_core_send_buffer_nr_frags(struct nss_ctx_instance *nss + (nss_ptr_t)NULL, 0, skb_frag_size(frag), skb_frag_size(frag), + nbuf->priority, mss, bit_flags); + +- NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, h2n_desc_index_to_dma(if_map, qid, hlos_index), ++ sizeof(*desc), DMA_TO_DEVICE); + } + + /* +@@ -2827,7 +2880,8 @@ static inline int32_t nss_core_send_buffer_nr_frags(struct nss_ctx_instance *nss + desc->bit_flags &= ~(H2N_BIT_FLAG_DISCARD); + desc->opaque = (nss_ptr_t)nbuf; + +- NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, h2n_desc_index_to_dma(if_map, qid, hlos_index), ++ sizeof(*desc), DMA_TO_DEVICE); + + NSS_PKT_STATS_INC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_TX_NR_FRAGS]); + return i+1; +@@ -2841,9 +2895,11 @@ static inline int32_t nss_core_send_buffer_nr_frags(struct nss_ctx_instance *nss + * Used to differentiate from FRAGS + */ + static inline int32_t nss_core_send_buffer_fraglist(struct nss_ctx_instance *nss_ctx, +- struct h2n_desc_if_instance *desc_if, uint32_t if_num, +- struct sk_buff *nbuf, uint16_t hlos_index, uint16_t flags, uint8_t buffer_type, uint16_t mss) ++ struct h2n_desc_if_instance *desc_if, uint32_t if_num, struct sk_buff *nbuf, ++ uint16_t qid, uint16_t hlos_index, uint16_t flags, uint8_t buffer_type, uint16_t mss) + { ++ struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; ++ struct nss_if_mem_map *if_map = mem_ctx->if_map; + struct h2n_descriptor *desc_ring = desc_if->desc; + struct h2n_descriptor *desc; + dma_addr_t buffer; +@@ -2882,7 +2938,8 @@ static inline int32_t nss_core_send_buffer_fraglist(struct nss_ctx_instance *nss + (nss_ptr_t)nbuf, nbuf->data - nbuf->head, nbuf->len - nbuf->data_len, + skb_end_offset(nbuf), (uint32_t)nbuf->priority, mss, bit_flags | H2N_BIT_FLAG_FIRST_SEGMENT); + +- NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, h2n_desc_index_to_dma(if_map, qid, hlos_index), ++ sizeof(*desc), DMA_TO_DEVICE); + + /* + * Walk the frag_list in nbuf +@@ -2935,7 +2992,8 @@ static inline int32_t nss_core_send_buffer_fraglist(struct nss_ctx_instance *nss + (nss_ptr_t)iter, iter->data - iter->head, iter->len - iter->data_len, + skb_end_offset(iter), iter->priority, mss, bit_flags); + +- NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, h2n_desc_index_to_dma(if_map, qid, hlos_index), ++ sizeof(*desc), DMA_TO_DEVICE); + + i++; + } +@@ -2954,7 +3012,8 @@ static inline int32_t nss_core_send_buffer_fraglist(struct nss_ctx_instance *nss + * Update bit flag for last descriptor. + */ + desc->bit_flags |= H2N_BIT_FLAG_LAST_SEGMENT; +- NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, h2n_desc_index_to_dma(if_map, qid, hlos_index), ++ sizeof(*desc), DMA_TO_DEVICE); + + NSS_PKT_STATS_INC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_TX_FRAGLIST]); + return i+1; +@@ -3025,8 +3084,10 @@ int32_t nss_core_send_buffer(struct nss_ctx_instance *nss_ctx, uint32_t if_num, + * We need to work out if there's sufficent space in our transmit descriptor + * ring to place all the segments of a nbuf. + */ +- NSS_CORE_DMA_CACHE_MAINT((void *)&if_map->h2n_nss_index[qid], sizeof(uint32_t), DMA_FROM_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, h2n_nss_index_to_dma(mem_ctx->if_map_dma, qid), ++ sizeof(uint32_t), DMA_FROM_DEVICE); + NSS_CORE_DSB(); ++ + nss_index = if_map->h2n_nss_index[qid]; + h2n_desc_ring->nss_index_local = nss_index; + count = ((nss_index - hlos_index - 1) + size) & (mask); +@@ -3095,13 +3156,13 @@ int32_t nss_core_send_buffer(struct nss_ctx_instance *nss_ctx, uint32_t if_num, + count = 0; + if (likely((segments == 0) || is_bounce)) { + count = nss_core_send_buffer_simple_skb(nss_ctx, desc_if, if_num, +- nbuf, hlos_index, flags, buffer_type, mss); ++ nbuf, qid, hlos_index, flags, buffer_type, mss); + } else if (skb_has_frag_list(nbuf)) { + count = nss_core_send_buffer_fraglist(nss_ctx, desc_if, if_num, +- nbuf, hlos_index, flags, buffer_type, mss); ++ nbuf, qid, hlos_index, flags, buffer_type, mss); + } else { + count = nss_core_send_buffer_nr_frags(nss_ctx, desc_if, if_num, +- nbuf, hlos_index, flags, buffer_type, mss); ++ nbuf, qid, hlos_index, flags, buffer_type, mss); + } + + if (unlikely(count <= 0)) { +@@ -3125,7 +3186,8 @@ int32_t nss_core_send_buffer(struct nss_ctx_instance *nss_ctx, uint32_t if_num, + h2n_desc_ring->hlos_index = hlos_index; + if_map->h2n_hlos_index[qid] = hlos_index; + +- NSS_CORE_DMA_CACHE_MAINT(&if_map->h2n_hlos_index[qid], sizeof(uint32_t), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, h2n_hlos_index_to_dma(mem_ctx->if_map_dma, qid), ++ sizeof(uint32_t), DMA_TO_DEVICE); + NSS_CORE_DSB(); + + #ifdef CONFIG_DEBUG_KMEMLEAK +diff --git a/nss_core.h b/nss_core.h +index d7f62fe..7ddf6ce 100644 +--- a/nss_core.h ++++ b/nss_core.h +@@ -100,31 +100,30 @@ + #endif + + /* +- * Cache operation ++ * DMA Offset helper + */ +-#define NSS_CORE_DSB() dsb(sy) +-#define NSS_CORE_DMA_CACHE_MAINT(start, size, dir) nss_core_dma_cache_maint(start, size, dir) ++#define n2h_desc_index_offset(_index) sizeof(struct n2h_descriptor) * (_index) ++#define h2n_desc_index_offset(_index) sizeof(struct h2n_descriptor) * (_index) ++ ++#define n2h_desc_index_to_dma(_if_map_addr, _qid, _index) (_if_map_addr)->n2h_desc_if[(_qid)].desc_addr + n2h_desc_index_offset(_index) ++#define h2n_desc_index_to_dma(_if_map_addr, _qid, _index) (_if_map_addr)->h2n_desc_if[(_qid)].desc_addr + h2n_desc_index_offset(_index) ++ ++#define h2n_nss_index_offset offsetof(struct nss_if_mem_map, h2n_nss_index) ++#define n2h_nss_index_offset offsetof(struct nss_if_mem_map, n2h_nss_index) ++#define h2n_hlos_index_offset offsetof(struct nss_if_mem_map, h2n_hlos_index) ++#define n2h_hlos_index_offset offsetof(struct nss_if_mem_map, n2h_hlos_index) ++ ++#define h2n_nss_index_to_dma(_if_map_addr, _index) (_if_map_addr) + h2n_nss_index_offset + (sizeof(uint32_t) * (_index)) ++#define n2h_nss_index_to_dma(_if_map_addr, _index) (_if_map_addr) + n2h_nss_index_offset + (sizeof(uint32_t) * (_index)) ++#define h2n_hlos_index_to_dma(_if_map_addr, _index) (_if_map_addr) + h2n_hlos_index_offset + (sizeof(uint32_t) * (_index)) ++#define n2h_hlos_index_to_dma(_if_map_addr, _index) (_if_map_addr) + n2h_hlos_index_offset + (sizeof(uint32_t) * (_index)) + + /* +- * nss_core_dma_cache_maint() +- * Perform the appropriate cache op based on direction ++ * Cache operation + */ +-static inline void nss_core_dma_cache_maint(void *start, uint32_t size, int direction) +-{ +- switch (direction) { +- case DMA_FROM_DEVICE:/* invalidate only */ +- dmac_inv_range(start, start + size); +- break; +- case DMA_TO_DEVICE:/* writeback only */ +- dmac_clean_range(start, start + size); +- break; +- case DMA_BIDIRECTIONAL:/* writeback and invalidate */ +- dmac_flush_range(start, start + size); +- break; +- default: +- BUG(); +- } +-} ++#define NSS_CORE_DSB() dsb(sy) ++#define NSS_CORE_DMA_CACHE_MAINT(dev, start, size, dir) BUILD_BUG_ON_MSG(1, \ ++ "NSS_CORE_DMA_CACHE_MAINT is deprecated. Fix the code to use correct dma_sync_* API") + + #define NSS_DEVICE_IF_START NSS_PHYSICAL_IF_START + +diff --git a/nss_hal/ipq806x/nss_hal_pvt.c b/nss_hal/ipq806x/nss_hal_pvt.c +index 52d63b0..5375087 100644 +--- a/nss_hal/ipq806x/nss_hal_pvt.c ++++ b/nss_hal/ipq806x/nss_hal_pvt.c +@@ -474,10 +474,9 @@ static struct nss_platform_data *__nss_hal_of_get_pdata(struct platform_device * + /* + * Clear TCM memory used by this core + */ +- for (i = 0; i < resource_size(&res_vphys) ; i += 4) { ++ for (i = 0; i < resource_size(&res_vphys) ; i += 4) + nss_write_32(npd->vmap, i, 0); +- NSS_CORE_DMA_CACHE_MAINT((npd->vmap + i), 4, DMA_TO_DEVICE); +- } ++ + NSS_CORE_DSB(); + + /* +diff --git a/nss_hal/ipq807x/nss_hal_pvt.c b/nss_hal/ipq807x/nss_hal_pvt.c +index bb8f42f..733d7f1 100644 +--- a/nss_hal/ipq807x/nss_hal_pvt.c ++++ b/nss_hal/ipq807x/nss_hal_pvt.c +@@ -256,10 +256,9 @@ static struct nss_platform_data *__nss_hal_of_get_pdata(struct platform_device * + /* + * Clear TCM memory used by this core + */ +- for (i = 0; i < resource_size(&res_vphys) ; i += 4) { ++ for (i = 0; i < resource_size(&res_vphys) ; i += 4) + nss_write_32(npd->vmap, i, 0); +- NSS_CORE_DMA_CACHE_MAINT((npd->vmap + i), 4, DMA_TO_DEVICE); +- } ++ + NSS_CORE_DSB(); + + /* +diff --git a/nss_meminfo.c b/nss_meminfo.c +index 2255eae..d804524 100644 +--- a/nss_meminfo.c ++++ b/nss_meminfo.c +@@ -414,7 +414,6 @@ static bool nss_meminfo_init_block_lists(struct nss_ctx_instance *nss_ctx) + /* + * Flush the updated meminfo request. + */ +- NSS_CORE_DMA_CACHE_MAINT(r, sizeof(struct nss_meminfo_request), DMA_TO_DEVICE); + NSS_CORE_DSB(); + + /* +@@ -538,7 +537,7 @@ static bool nss_meminfo_configure_n2h_h2n_rings(struct nss_ctx_instance *nss_ctx + * Bring a fresh copy of if_map from memory in order to read it correctly. + */ + if_map = mem_ctx->if_map; +- NSS_CORE_DMA_CACHE_MAINT((void *)if_map, sizeof(struct nss_if_mem_map), DMA_FROM_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, mem_ctx->if_map_dma, sizeof(struct nss_if_mem_map), DMA_FROM_DEVICE); + NSS_CORE_DSB(); + + if_map->n2h_rings = NSS_N2H_RING_COUNT; +@@ -576,7 +575,7 @@ static bool nss_meminfo_configure_n2h_h2n_rings(struct nss_ctx_instance *nss_ctx + /* + * Flush the updated nss_if_mem_map. + */ +- NSS_CORE_DMA_CACHE_MAINT((void *)if_map, sizeof(struct nss_if_mem_map), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, mem_ctx->if_map_dma, sizeof(struct nss_if_mem_map), DMA_TO_DEVICE); + NSS_CORE_DSB(); + + return true; +diff --git a/nss_profiler.c b/nss_profiler.c +index 5717ac3..aadc7c9 100755 +--- a/nss_profiler.c ++++ b/nss_profiler.c +@@ -199,11 +199,12 @@ EXPORT_SYMBOL(nss_profile_dma_deregister_cb); + struct nss_profile_sdma_ctrl *nss_profile_dma_get_ctrl(struct nss_ctx_instance *nss_ctx) + { + struct nss_profile_sdma_ctrl *ctrl = nss_ctx->meminfo_ctx.sdma_ctrl; ++ int size = offsetof(struct nss_profile_sdma_ctrl, cidx); + if (!ctrl) { + return ctrl; + } + +- dmac_inv_range(ctrl, &ctrl->cidx); ++ dma_sync_single_for_device(nss_ctx->dev, (dma_addr_t) ctrl, size, DMA_FROM_DEVICE); + dsb(sy); + return ctrl; + } +-- +2.34.1 + diff --git a/qca/qca-nss-drv/patches/0005-nss-drv-add-support-for-kernel-5.15.patch b/qca/qca-nss-drv/patches/0005-nss-drv-add-support-for-kernel-5.15.patch new file mode 100644 index 000000000..0995e2a07 --- /dev/null +++ b/qca/qca-nss-drv/patches/0005-nss-drv-add-support-for-kernel-5.15.patch @@ -0,0 +1,70 @@ +From 6e65f6daecb09463688eaea0a234018a728196b8 Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Tue, 5 Apr 2022 18:10:57 +0200 +Subject: [PATCH 5/8] nss-drv: add support for kernel 5.15 + +- Fix coredump panic notifier include change. +- Fix skb ZEROCOPY flag. +- Add skb reuse support for 5.15 kernel version. + +Signed-off-by: Ansuel Smith +--- + nss_core.c | 5 +++-- + nss_coredump.c | 4 ++++ + nss_hal/nss_hal.c | 1 + + 3 files changed, 8 insertions(+), 2 deletions(-) + +diff --git a/nss_core.c b/nss_core.c +index f9e6014..8cd1d4b 100644 +--- a/nss_core.c ++++ b/nss_core.c +@@ -53,7 +53,8 @@ + (((LINUX_VERSION_CODE >= KERNEL_VERSION(3, 18, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 19, 0)))) || \ + (((LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(4, 5, 0)))) || \ + (((LINUX_VERSION_CODE >= KERNEL_VERSION(5, 4, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 5, 0)))) || \ +-(((LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 11, 0)))))) ++(((LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 11, 0)))) || \ ++(((LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 16, 0)))))) + #error "Check skb recycle code in this file to match Linux version" + #endif + +@@ -2623,7 +2624,7 @@ static inline bool nss_core_skb_can_reuse(struct nss_ctx_instance *nss_ctx, + if (unlikely(irqs_disabled())) + return false; + +- if (unlikely(skb_shinfo(nbuf)->tx_flags & SKBTX_DEV_ZEROCOPY)) ++ if (unlikely(skb_shinfo(nbuf)->flags & SKBFL_ZEROCOPY_ENABLE)) + return false; + + if (unlikely(skb_is_nonlinear(nbuf))) +diff --git a/nss_coredump.c b/nss_coredump.c +index ecad659..3ecef7e 100644 +--- a/nss_coredump.c ++++ b/nss_coredump.c +@@ -23,7 +23,11 @@ + #include "nss_hal.h" + #include "nss_log.h" + #include ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 14, 0)) + #include /* for panic_notifier_list */ ++#else ++#include ++#endif + #include /* for time */ + #include "nss_tx_rx_common.h" + +diff --git a/nss_hal/nss_hal.c b/nss_hal/nss_hal.c +index 57974c1..d8c703b 100644 +--- a/nss_hal/nss_hal.c ++++ b/nss_hal/nss_hal.c +@@ -24,6 +24,7 @@ + #include + #include + #include ++#include + + #include "nss_hal.h" + #include "nss_arch.h" +-- +2.34.1 + diff --git a/qca/qca-nss-drv/patches/0005-nss-drv-use-standard-skb_skip_tc_classify-instead-of.patch b/qca/qca-nss-drv/patches/0005-nss-drv-use-standard-skb_skip_tc_classify-instead-of.patch new file mode 100644 index 000000000..6e8b4cdfd --- /dev/null +++ b/qca/qca-nss-drv/patches/0005-nss-drv-use-standard-skb_skip_tc_classify-instead-of.patch @@ -0,0 +1,30 @@ +From 4dd701916186803172a9f35e7e982a953613ad55 Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Mon, 11 Apr 2022 21:32:41 +0200 +Subject: [PATCH 5/9] nss-drv: use standard skb_skip_tc_classify instead of + custom api + +Use skb_skip_tc_classify to skip classify for packet handled by nss +instead of custom api. + +Signed-off-by: Ansuel Smith +--- + nss_core.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/nss_core.c b/nss_core.c +index f9e6014..6ab8038 100644 +--- a/nss_core.c ++++ b/nss_core.c +@@ -1075,7 +1075,7 @@ static inline void nss_core_set_skb_classify(struct sk_buff *nbuf) + #if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0)) + nbuf->tc_verd = SET_TC_NCLS_NSS(nbuf->tc_verd); + #else +- skb_set_tc_classify_offload(nbuf); ++ skb_skip_tc_classify(nbuf); + #endif + #endif + } +-- +2.34.1 + diff --git a/qca/qca-nss-drv/patches/0008-Makefile-modularize-driver-even-more.patch b/qca/qca-nss-drv/patches/0008-Makefile-modularize-driver-even-more.patch new file mode 100644 index 000000000..eb7f27d06 --- /dev/null +++ b/qca/qca-nss-drv/patches/0008-Makefile-modularize-driver-even-more.patch @@ -0,0 +1,172 @@ +From 895de8e4119afe3cbad2aa81566b1ebcb2b39dcd Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Tue, 17 May 2022 20:23:19 +0200 +Subject: [PATCH] Makefile: modularize driver even more + +Permit to disable even more module. + +Signed-off-by: Ansuel Smith +--- + Makefile | 56 ++++++++++++++++++++++++++++++++--------------- + nss_hal/nss_hal.c | 6 +++++ + nss_init.c | 4 ++++ + 3 files changed, 48 insertions(+), 18 deletions(-) + +diff --git a/Makefile b/Makefile +index f5c4b90..0194dbd 100644 +--- a/Makefile ++++ b/Makefile +@@ -39,35 +39,55 @@ qca-nss-drv-objs := \ + nss_pm.o \ + nss_profiler.o \ + nss_project.o \ +- nss_pppoe.o \ +- nss_pppoe_log.o \ +- nss_pppoe_stats.o \ +- nss_pppoe_strings.o \ + nss_rps.o \ + nss_stats.o \ + nss_strings.o \ + nss_tx_msg_sync.o \ + nss_unaligned.o \ + nss_unaligned_log.o \ +- nss_unaligned_stats.o \ +- nss_virt_if.o \ +- nss_virt_if_stats.o \ +- nss_vlan.o \ +- nss_vlan_log.o \ +- nss_wifi.o \ +- nss_wifi_log.o \ +- nss_wifi_stats.o \ +- nss_wifi_vdev.o \ +- nss_wifili.o \ +- nss_wifili_log.o \ +- nss_wifili_stats.o \ +- nss_wifili_strings.o \ +- nss_wifi_mac_db.o ++ nss_unaligned_stats.o + + # Base NSS data plane/HAL support + qca-nss-drv-objs += nss_data_plane/nss_data_plane_common.o + qca-nss-drv-objs += nss_hal/nss_hal.o + ++ifneq "$(NSS_DRV_PPPOE_ENABLE)" "n" ++ccflags-y += -DNSS_DRV_PPPOE_ENABLE ++qca-nss-drv-objs += \ ++ nss_pppoe.o \ ++ nss_pppoe_log.o \ ++ nss_pppoe_stats.o \ ++ nss_pppoe_strings.o ++endif ++ ++ifneq "$(NSS_DRV_VIRT_IF_ENABLE)" "n" ++ccflags-y += -DNSS_DRV_VIRT_IF_ENABLE ++qca-nss-drv-objs += \ ++ nss_virt_if.o \ ++ nss_virt_if_stats.o ++endif ++ ++ifneq "$(NSS_DRV_VLAN_ENABLE)" "n" ++ccflags-y += -DNSS_DRV_VLAN_ENABLE ++qca-nss-drv-objs += \ ++ nss_vlan.o \ ++ nss_vlan_log.o ++endif ++ ++ifneq "$(NSS_DRV_WIFI_ENABLE)" "n" ++ccflags-y += -DNSS_DRV_WIFI_ENABLE ++qca-nss-drv-objs += \ ++ nss_wifi.o \ ++ nss_wifi_log.o \ ++ nss_wifi_stats.o \ ++ nss_wifi_vdev.o \ ++ nss_wifili.o \ ++ nss_wifili_log.o \ ++ nss_wifili_stats.o \ ++ nss_wifili_strings.o \ ++ nss_wifi_mac_db.o ++endif ++ + ifneq "$(NSS_DRV_BRIDGE_ENABLE)" "n" + ccflags-y += -DNSS_DRV_BRIDGE_ENABLE + qca-nss-drv-objs += \ +diff --git a/nss_hal/nss_hal.c b/nss_hal/nss_hal.c +index 7e9a044..c0051e4 100644 +--- a/nss_hal/nss_hal.c ++++ b/nss_hal/nss_hal.c +@@ -460,10 +460,12 @@ int nss_hal_probe(struct platform_device *nss_dev) + } + #endif + ++#ifdef NSS_DRV_PPPOE_ENABLE + if (npd->pppoe_enabled == NSS_FEATURE_ENABLED) { + nss_top->pppoe_handler_id = nss_dev->id; + nss_pppoe_register_handler(); + } ++#endif + + #ifdef NSS_DRV_PPE_ENABLE + if (npd->ppe_enabled == NSS_FEATURE_ENABLED) { +@@ -558,6 +560,7 @@ int nss_hal_probe(struct platform_device *nss_dev) + } + #endif + ++#ifdef NSS_DRV_WIFI_ENABLE + if (npd->wifioffload_enabled == NSS_FEATURE_ENABLED) { + nss_top->wifi_handler_id = nss_dev->id; + nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_VAP] = nss_dev->id; +@@ -585,6 +588,7 @@ int nss_hal_probe(struct platform_device *nss_dev) + */ + nss_wifili_thread_scheme_db_init(nss_dev->id); + } ++#endif + + #ifdef NSS_DRV_OAM_ENABLE + if (npd->oam_enabled == NSS_FEATURE_ENABLED) { +@@ -601,11 +605,13 @@ int nss_hal_probe(struct platform_device *nss_dev) + } + #endif + ++#ifdef NSS_DRV_VLAN_ENABLE + if (npd->vlan_enabled == NSS_FEATURE_ENABLED) { + nss_top->vlan_handler_id = nss_dev->id; + nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_VLAN] = nss_dev->id; + nss_vlan_register_handler(); + } ++#endif + + #ifdef NSS_DRV_QVPN_ENABLE + #if defined(NSS_HAL_IPQ807x_SUPPORT) || defined(NSS_HAL_IPQ60XX_SUPPORT) +diff --git a/nss_init.c b/nss_init.c +index ebd2a12..40e9351 100644 +--- a/nss_init.c ++++ b/nss_init.c +@@ -775,10 +775,12 @@ static int __init nss_init(void) + */ + nss_project_register_sysctl(); + ++#ifdef NSS_DRV_PPPOE_ENABLE + /* + * Registering sysctl for pppoe specific config. + */ + nss_pppoe_register_sysctl(); ++#endif + + /* + * Setup Runtime Sample values +@@ -913,10 +915,12 @@ static void __exit nss_cleanup(void) + nss_c2c_tx_unregister_sysctl(); + #endif + ++#ifdef NSS_DRV_PPPOE_ENABLE + /* + * Unregister pppoe specific sysctl + */ + nss_pppoe_unregister_sysctl(); ++#endif + + /* + * Unregister ipv4/6 specific sysctl and free allocated to connection tables +-- +2.34.1 + diff --git a/qca/qca-nss-ecm/Makefile b/qca/qca-nss-ecm/Makefile new file mode 100644 index 000000000..ceedc1988 --- /dev/null +++ b/qca/qca-nss-ecm/Makefile @@ -0,0 +1,97 @@ +include $(TOPDIR)/rules.mk + +PKG_NAME:=qca-nss-ecm +PKG_RELEASE:=$(AUTORELEASE) + +PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/qca-nss-ecm.git +PKG_SOURCE_PROTO:=git +PKG_SOURCE_DATE:=2021-06-15 +PKG_SOURCE_VERSION:=34267065855d32f33264dc3054efb0e8103d627b +PKG_MIRROR_HASH:=0917659d69c5f3e6067d6671b9393b4b2d6b6cd5a7bacf5e7d6cf842dc906eca + +PKG_BUILD_PARALLEL:=1 + +include $(INCLUDE_DIR)/kernel.mk +include $(INCLUDE_DIR)/package.mk + +define KernelPackage/qca-nss-ecm + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Support + DEPENDS:=@LINUX_5_10 @(TARGET_ipq807x||TARGET_ipq60xx) \ + +kmod-qca-nss-drv \ + +iptables-mod-extra \ + +kmod-ipt-conntrack \ + +kmod-ipt-physdev \ + +iptables-mod-physdev \ + +kmod-ppp \ + +kmod-pppoe + TITLE:=QCA NSS Enhanced Connection Manager (ECM) + FILES:=$(PKG_BUILD_DIR)/*.ko + KCONFIG:=CONFIG_BRIDGE_NETFILTER=y \ + CONFIG_NF_CONNTRACK_EVENTS=y \ + CONFIG_NF_CONNTRACK_CHAIN_EVENTS=n \ + CONFIG_NF_CONNTRACK_DSCPREMARK_EXT=n +endef + +define KernelPackage/qca-nss-ecm/Description +This package contains the QCA NSS Enhanced Connection Manager +endef + +define KernelPackage/qca-nss-ecm/install + $(INSTALL_DIR) $(1)/etc/firewall.d $(1)/etc/init.d $(1)/usr/bin $(1)/lib/netifd/offload $(1)/etc/config $(1)/etc/uci-defaults $(1)/etc/sysctl.d + $(INSTALL_DATA) ./files/qca-nss-ecm.firewall $(1)/etc/firewall.d/qca-nss-ecm + $(INSTALL_BIN) ./files/qca-nss-ecm.init $(1)/etc/init.d/qca-nss-ecm + $(INSTALL_BIN) ./files/ecm_dump.sh $(1)/usr/bin/ + $(INSTALL_BIN) ./files/on-demand-down $(1)/lib/netifd/offload/on-demand-down + $(INSTALL_DATA) ./files/qca-nss-ecm.uci $(1)/etc/config/ecm + $(INSTALL_DATA) ./files/qca-nss-ecm.defaults $(1)/etc/uci-defaults/99-qca-nss-ecm + $(INSTALL_BIN) ./files/qca-nss-ecm.sysctl $(1)/etc/sysctl.d/qca-nss-ecm.conf + echo 'net.netfilter.nf_conntrack_max=8192' >> $(1)/etc/sysctl.d/qca-nss-ecm.conf +endef + +EXTRA_CFLAGS+=-I$(STAGING_DIR)/usr/include/qca-nss-drv + +ifneq (, $(findstring $(CONFIG_TARGET_BOARD), "ipq807x" "ipq60xx")) +ECM_MAKE_OPTS+= ECM_FRONT_END_NSS_ENABLE=y \ + ECM_CLASSIFIER_HYFI_ENABLE=n \ + ECM_MULTICAST_ENABLE=n \ + ECM_INTERFACE_IPSEC_ENABLE=n \ + ECM_INTERFACE_PPTP_ENABLE=n \ + ECM_INTERFACE_L2TPV2_ENABLE=n \ + ECM_INTERFACE_GRE_TAP_ENABLE=n \ + ECM_INTERFACE_GRE_TUN_ENABLE=n \ + ECM_INTERFACE_SIT_ENABLE=n \ + ECM_INTERFACE_TUNIPIP6_ENABLE=n \ + ECM_INTERFACE_RAWIP_ENABLE=n \ + ECM_INTERFACE_VLAN_ENABLE=n \ + ECM_CLASSIFIER_MARK_ENABLE=n \ + ECM_CLASSIFIER_DSCP_ENABLE=n \ + ECM_CLASSIFIER_PCC_ENABLE=n \ + ECM_BAND_STEERING_ENABLE=n \ + ECM_INTERFACE_PPPOE_ENABLE=y +endif + +ifeq ($(CONFIG_TARGET_BOARD), "ipq807x") + SOC="ipq807x_64" +else ifeq ($(CONFIG_TARGET_BOARD), "ipq60xx") + SOC="ipq60xx_64" +endif + +define Build/InstallDev + mkdir -p $(1)/usr/include/qca-nss-ecm + $(CP) $(PKG_BUILD_DIR)/exports/* $(1)/usr/include/qca-nss-ecm +endef + +define Build/Compile + +$(MAKE) -C "$(LINUX_DIR)" $(strip $(ECM_MAKE_OPTS)) \ + CROSS_COMPILE="$(TARGET_CROSS)" \ + ARCH="$(LINUX_KARCH)" \ + M="$(PKG_BUILD_DIR)" \ + EXTRA_CFLAGS="$(EXTRA_CFLAGS)" SoC=$(SOC) \ + $(KERNEL_MAKE_FLAGS) \ + $(PKG_JOBS) \ + modules +endef + +$(eval $(call KernelPackage,qca-nss-ecm)) diff --git a/qca/qca-nss-ecm/files/ecm_dump.sh b/qca/qca-nss-ecm/files/ecm_dump.sh new file mode 100644 index 000000000..dbf7de753 --- /dev/null +++ b/qca/qca-nss-ecm/files/ecm_dump.sh @@ -0,0 +1,95 @@ +#!/bin/sh +# +# Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +# + +ECM_MODULE=${1:-ecm_state} +MOUNT_ROOT=/dev/ecm + +# +# usage: ecm_dump.sh [module=ecm_db] +# +# with no parameters, ecm_dump.sh will attempt to mount the +# ecm_db state file and cat its contents. +# +# example with a parameter: ecm_dump.sh ecm_classifier_default +# +# this will cause ecm_dump to attempt to find and mount the state +# file for the ecm_classifier_default module, and if successful +# cat the contents. +# + +# this is one of the state files, which happens to be the +# last module started in ecm +ECM_STATE=/sys/kernel/debug/ecm/ecm_state/state_dev_major + +# tests to see if ECM is up and ready to receive commands. +# returns 0 if ECM is fully up and ready, else 1 +ecm_is_ready() { + if [ ! -e "${ECM_STATE}" ] + then + return 1 + fi + return 0 +} + +# +# module_state_mount(module_name) +# Mounts the state file of the module, if supported +# +module_state_mount() { + local module_name=$1 + local mount_dir=$2 + local state_file="/sys/kernel/debug/ecm/${module_name}/state_dev_major" + + if [ -e "${mount_dir}/${module_name}" ] + then + # already mounted + return 0 + fi + + #echo "Mount state file for $module_name ..." + if [ ! -e "$state_file" ] + then + #echo "... $module_name does not support state" + return 1 + fi + + local major="`cat $state_file`" + #echo "... Mounting state $state_file with major: $major" + mknod "${mount_dir}/${module_name}" c $major 0 +} + +# +# main +# +ecm_is_ready || { + #echo "ECM is not running" + exit 1 +} + +# all state files are mounted under MOUNT_ROOT, so make sure it exists +mkdir -p ${MOUNT_ROOT} + +# +# attempt to mount state files for the requested module and cat it +# if the mount succeeded +# +module_state_mount ${ECM_MODULE} ${MOUNT_ROOT} && { + cat ${MOUNT_ROOT}/${ECM_MODULE} + exit 0 +} + +exit 2 diff --git a/qca/qca-nss-ecm/files/on-demand-down b/qca/qca-nss-ecm/files/on-demand-down new file mode 100644 index 000000000..02d708e03 --- /dev/null +++ b/qca/qca-nss-ecm/files/on-demand-down @@ -0,0 +1,6 @@ +#!/bin/sh +# Copyright (c) 2016 The Linux Foundation. All rights reserved. + +[ -e "/sys/kernel/debug/ecm/ecm_db/defunct_all" ] && { + echo 1 > /sys/kernel/debug/ecm/ecm_db/defunct_all +} diff --git a/qca/qca-nss-ecm/files/qca-nss-ecm.defaults b/qca/qca-nss-ecm/files/qca-nss-ecm.defaults new file mode 100644 index 000000000..308e265c9 --- /dev/null +++ b/qca/qca-nss-ecm/files/qca-nss-ecm.defaults @@ -0,0 +1,28 @@ +#!/bin/sh +# +# Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +# + +uci -q batch << EOF + delete firewall.qcanssecm + set firewall.qcanssecm=include + set firewall.qcanssecm.type=script + set firewall.qcanssecm.path=/etc/firewall.d/qca-nss-ecm + set firewall.qcanssecm.family=any + set firewall.qcanssecm.reload=1 + commit firewall +EOF + +exit 0 diff --git a/qca/qca-nss-ecm/files/qca-nss-ecm.firewall b/qca/qca-nss-ecm/files/qca-nss-ecm.firewall new file mode 100644 index 000000000..24c64def2 --- /dev/null +++ b/qca/qca-nss-ecm/files/qca-nss-ecm.firewall @@ -0,0 +1,18 @@ +#!/bin/sh +# +# Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +# + +iptables -A FORWARD -m physdev --physdev-is-bridged -j ACCEPT diff --git a/qca/qca-nss-ecm/files/qca-nss-ecm.init b/qca/qca-nss-ecm/files/qca-nss-ecm.init new file mode 100644 index 000000000..e64f077bb --- /dev/null +++ b/qca/qca-nss-ecm/files/qca-nss-ecm.init @@ -0,0 +1,142 @@ +#!/bin/sh /etc/rc.common +# +# Copyright (c) 2014, 2019-2020 The Linux Foundation. All rights reserved. +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +# The shebang above has an extra space intentially to avoid having +# openwrt build scripts automatically enable this package starting +# at boot. + +START=19 + +get_front_end_mode() { + config_load "ecm" + config_get front_end global acceleration_engine "auto" + + case $front_end in + auto) + echo '0' + ;; + nss) + echo '1' + ;; + sfe) + echo '2' + ;; + *) + echo 'uci_option_acceleration_engine is invalid' + esac +} + +support_bridge() { + #NSS support bridge acceleration + [ -d /sys/kernel/debug/ecm/ecm_nss_ipv4 ] && return 0 + #SFE doesn't support bridge acceleration + [ -d /sys/kernel/debug/ecm/ecm_sfe_ipv4 ] && return 1 +} + +load_sfe() { + local kernel_version=$(uname -r) + + [ -e "/lib/modules/$kernel_version/shortcut-fe.ko" ] && { + [ -d /sys/module/shortcut_fe ] || insmod shortcut-fe + } + + [ -e "/lib/modules/$kernel_version/shortcut-fe-ipv6.ko" ] && { + [ -d /sys/module/shortcut_fe_ipv6 ] || insmod shortcut-fe-ipv6 + } + + [ -e "/lib/modules/$kernel_version/shortcut-fe-drv.ko" ] && { + [ -d /sys/module/shortcut_fe_drv ] || insmod shortcut-fe-drv + } +} + +load_ecm() { + [ -d /sys/module/ecm ] || { + [ ! -e /proc/device-tree/MP_256 ] && load_sfe + insmod ecm front_end_selection=$(get_front_end_mode) + } + + support_bridge && { + sysctl -w net.bridge.bridge-nf-call-ip6tables=1 + sysctl -w net.bridge.bridge-nf-call-iptables=1 + } +} + +unload_ecm() { + sysctl -w net.bridge.bridge-nf-call-ip6tables=0 + sysctl -w net.bridge.bridge-nf-call-iptables=0 + + if [ -d /sys/module/ecm ]; then + # + # Stop ECM frontends + # + echo 1 > /sys/kernel/debug/ecm/front_end_ipv4_stop + echo 1 > /sys/kernel/debug/ecm/front_end_ipv6_stop + + # + # Defunct the connections + # + echo 1 > /sys/kernel/debug/ecm/ecm_db/defunct_all + sleep 5; + + rmmod ecm + sleep 1 + fi +} + +start() { + # If SFE CM is loaded, return. + if [ -d /sys/module/shortcut_fe_cm ]; then + echo "shortcut_fe CM is loaded, unload it first" + echo "cmd: /etc/init.d/shortcut_fe stop" + return + fi + + load_ecm + + # If the acceleration engine is NSS, enable wifi redirect. + [ -d /sys/kernel/debug/ecm/ecm_nss_ipv4 ] && sysctl -w dev.nss.general.redirect=1 + + support_bridge && { + if ([ -z "$(grep "net.bridge.bridge-nf-call-ip6tables=1" /etc/sysctl.d/qca-nss-ecm.conf)" ] && [ -z "$(grep "net.bridge.bridge-nf-call-iptables=1" /etc/sysctl.d/qca-nss-ecm.conf)" ]); then + echo 'net.bridge.bridge-nf-call-ip6tables=1' >> /etc/sysctl.d/qca-nss-ecm.conf + echo 'net.bridge.bridge-nf-call-iptables=1' >> /etc/sysctl.d/qca-nss-ecm.conf + fi + } + + if [ -d /sys/module/qca_ovsmgr ]; then + insmod ecm_ovs + fi + +} + +stop() { + # If ECM is already not loaded, just return. + if [ ! -d /sys/module/ecm ]; then + return + fi + + # If the acceleration engine is NSS, disable wifi redirect. + [ -d /sys/kernel/debug/ecm/ecm_nss_ipv4 ] && sysctl -w dev.nss.general.redirect=0 + + sed '/net.bridge.bridge-nf-call-ip6tables=1/d' -i /etc/sysctl.d/qca-nss-ecm.conf + sed '/net.bridge.bridge-nf-call-iptables=1/d' -i /etc/sysctl.d/qca-nss-ecm.conf + + if [ -d /sys/module/ecm_ovs ]; then + rmmod ecm_ovs + fi + + unload_ecm +} diff --git a/qca/qca-nss-ecm/files/qca-nss-ecm.sysctl b/qca/qca-nss-ecm/files/qca-nss-ecm.sysctl new file mode 100644 index 000000000..1a3d76b18 --- /dev/null +++ b/qca/qca-nss-ecm/files/qca-nss-ecm.sysctl @@ -0,0 +1,2 @@ +# nf_conntrack_tcp_no_window_check is 0 by default, set it to 1 +net.netfilter.nf_conntrack_tcp_no_window_check=1 diff --git a/qca/qca-nss-ecm/files/qca-nss-ecm.uci b/qca/qca-nss-ecm/files/qca-nss-ecm.uci new file mode 100644 index 000000000..4f2de6877 --- /dev/null +++ b/qca/qca-nss-ecm/files/qca-nss-ecm.uci @@ -0,0 +1,2 @@ +config ecm 'global' + option acceleration_engine 'auto' diff --git a/qca/qca-nss-ecm/patches/001-treewide-componentize-the-module-even-more.patch b/qca/qca-nss-ecm/patches/001-treewide-componentize-the-module-even-more.patch new file mode 100644 index 000000000..4e7932c9d --- /dev/null +++ b/qca/qca-nss-ecm/patches/001-treewide-componentize-the-module-even-more.patch @@ -0,0 +1,335 @@ +From 73345c87b28a473b35b57e673f8de963c3d73da1 Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Wed, 19 May 2021 02:38:53 +0200 +Subject: [PATCH] treewide: componentize the module even more + +Signed-off-by: Ansuel Smith +--- + Makefile | 56 +++++++++++++++++++++++++------- + ecm_db/ecm_db_connection.c | 8 +++++ + ecm_db/ecm_db_node.c | 4 +++ + ecm_interface.c | 8 +++++ + frontends/ecm_front_end_common.c | 7 ++++ + 5 files changed, 72 insertions(+), 11 deletions(-) + +--- a/Makefile ++++ b/Makefile +@@ -82,10 +82,18 @@ ccflags-$(ECM_INTERFACE_BOND_ENABLE) += + # Define ECM_INTERFACE_PPPOE_ENABLE=y in order + # to enable support for PPPoE acceleration. + # ############################################################################# +-ECM_INTERFACE_PPPOE_ENABLE=y ++ifndef $(ECM_INTERFACE_PPPOE_ENABLE) ++ ECM_INTERFACE_PPPOE_ENABLE=y ++endif + ccflags-$(ECM_INTERFACE_PPPOE_ENABLE) += -DECM_INTERFACE_PPPOE_ENABLE + + # ############################################################################# ++# Define ECM_INTERFACE_L2TPV2_PPTP_ENABLE=y in order ++# to enable support for l2tpv2 or PPTP detection. ++# ############################################################################# ++ccflags-$(ECM_INTERFACE_L2TPV2_PPTP_ENABLE) += -DECM_INTERFACE_L2TPV2_PPTP_ENABLE ++ ++# ############################################################################# + # Define ECM_INTERFACE_L2TPV2_ENABLE=y in order + # to enable support for l2tpv2 acceleration. + # ############################################################################# +@@ -118,6 +126,12 @@ ccflags-$(ECM_INTERFACE_PPP_ENABLE) += - + ccflags-$(ECM_INTERFACE_MAP_T_ENABLE) += -DECM_INTERFACE_MAP_T_ENABLE + + # ############################################################################# ++# Define ECM_INTERFACE_GRE_ENABLE=y in order ++# to enable support for GRE detection. ++# ############################################################################# ++ccflags-$(ECM_INTERFACE_GRE_ENABLE) += -DECM_INTERFACE_GRE_ENABLE ++ ++# ############################################################################# + # Define ECM_INTERFACE_GRE_TAP_ENABLE=y in order + # to enable support for GRE TAP interface. + # ############################################################################# +@@ -186,7 +200,9 @@ ccflags-$(ECM_INTERFACE_OVS_BRIDGE_ENABL + # ############################################################################# + # Define ECM_INTERFACE_VLAN_ENABLE=y in order to enable support for VLAN + # ############################################################################# +-ECM_INTERFACE_VLAN_ENABLE=y ++ifndef $(ECM_INTERFACE_VLAN_ENABLE) ++ ECM_INTERFACE_VLAN_ENABLE=y ++endif + ccflags-$(ECM_INTERFACE_VLAN_ENABLE) += -DECM_INTERFACE_VLAN_ENABLE + + # ############################################################################# +@@ -228,7 +244,9 @@ ccflags-$(ECM_CLASSIFIER_OVS_ENABLE) += + # ############################################################################# + # Define ECM_CLASSIFIER_MARK_ENABLE=y in order to enable mark classifier. + # ############################################################################# +-ECM_CLASSIFIER_MARK_ENABLE=y ++ifndef $(ECM_CLASSIFIER_MARK_ENABLE) ++ ECM_CLASSIFIER_MARK_ENABLE=y ++endif + ecm-$(ECM_CLASSIFIER_MARK_ENABLE) += ecm_classifier_mark.o + ccflags-$(ECM_CLASSIFIER_MARK_ENABLE) += -DECM_CLASSIFIER_MARK_ENABLE + +@@ -247,7 +265,9 @@ ccflags-$(ECM_CLASSIFIER_NL_ENABLE) += - + # ############################################################################# + # Define ECM_CLASSIFIER_DSCP_ENABLE=y in order to enable DSCP classifier. + # ############################################################################# +-ECM_CLASSIFIER_DSCP_ENABLE=y ++ifndef $(ECM_CLASSIFIER_DSCP_ENABLE) ++ ECM_CLASSIFIER_DSCP_ENABLE=y ++endif + ecm-$(ECM_CLASSIFIER_DSCP_ENABLE) += ecm_classifier_dscp.o + ccflags-$(ECM_CLASSIFIER_DSCP_ENABLE) += -DECM_CLASSIFIER_DSCP_ENABLE + ccflags-$(ECM_CLASSIFIER_DSCP_IGS) += -DECM_CLASSIFIER_DSCP_IGS +@@ -274,7 +294,9 @@ endif + # the Parental Controls subsystem classifier in ECM. Currently disabled until + # customers require it / if they need to integrate their Parental Controls with it. + # ############################################################################# +-ECM_CLASSIFIER_PCC_ENABLE=y ++ifndef $(ECM_CLASSIFIER_PCC_ENABLE) ++ ECM_CLASSIFIER_PCC_ENABLE=y ++endif + ecm-$(ECM_CLASSIFIER_PCC_ENABLE) += ecm_classifier_pcc.o + ccflags-$(ECM_CLASSIFIER_PCC_ENABLE) += -DECM_CLASSIFIER_PCC_ENABLE + +@@ -301,28 +323,36 @@ ccflags-$(ECM_NON_PORTED_SUPPORT_ENABLE) + # ############################################################################# + # Define ECM_STATE_OUTPUT_ENABLE=y to support XML state output + # ############################################################################# +-ECM_STATE_OUTPUT_ENABLE=y ++ifndef $(ECM_STATE_OUTPUT_ENABLE) ++ ECM_STATE_OUTPUT_ENABLE=y ++endif + ecm-$(ECM_STATE_OUTPUT_ENABLE) += ecm_state.o + ccflags-$(ECM_STATE_OUTPUT_ENABLE) += -DECM_STATE_OUTPUT_ENABLE + + # ############################################################################# + # Define ECM_DB_ADVANCED_STATS_ENABLE to support XML state output + # ############################################################################# +-ECM_DB_ADVANCED_STATS_ENABLE=y ++ifndef $(ECM_DB_ADVANCED_STATS_ENABLE) ++ ECM_DB_ADVANCED_STATS_ENABLE=y ++endif + ccflags-$(ECM_DB_ADVANCED_STATS_ENABLE) += -DECM_DB_ADVANCED_STATS_ENABLE + + # ############################################################################# + # Define ECM_DB_CONNECTION_CROSS_REFERENCING_ENABLE=y in order to enable + # the database to track relationships between objects. + # ############################################################################# +-ECM_DB_CONNECTION_CROSS_REFERENCING_ENABLE=y ++ifndef $(ECM_DB_CONNECTION_CROSS_REFERENCING_ENABLE) ++ ECM_DB_CONNECTION_CROSS_REFERENCING_ENABLE=y ++endif + ccflags-$(ECM_DB_CONNECTION_CROSS_REFERENCING_ENABLE) += -DECM_DB_XREF_ENABLE + + # ############################################################################# + # Define ECM_TRACKER_DPI_SUPPORT_ENABLE=y in order to enable support for + # deep packet inspection and tracking of data with the trackers. + # ############################################################################# +-ECM_TRACKER_DPI_SUPPORT_ENABLE=y ++ifndef $(ECM_TRACKER_DPI_SUPPORT_ENABLE) ++ ECM_TRACKER_DPI_SUPPORT_ENABLE=y ++endif + ccflags-$(ECM_TRACKER_DPI_SUPPORT_ENABLE) += -DECM_TRACKER_DPI_SUPPORT_ENABLE + + # ############################################################################# +@@ -330,14 +360,18 @@ ccflags-$(ECM_TRACKER_DPI_SUPPORT_ENABLE + # support for the database keeping lists of connections that are assigned + # on a per TYPE of classifier basis. + # ############################################################################# +-ECM_DB_CLASSIFIER_TYPE_ASSIGNMENTS_TRACK_ENABLE=y ++ifndef $(ECM_DB_CLASSIFIER_TYPE_ASSIGNMENTS_TRACK_ENABLE) ++ ECM_DB_CLASSIFIER_TYPE_ASSIGNMENTS_TRACK_ENABLE=y ++endif + ccflags-$(ECM_DB_CLASSIFIER_TYPE_ASSIGNMENTS_TRACK_ENABLE) += -DECM_DB_CTA_TRACK_ENABLE + + # ############################################################################# + # Define ECM_BAND_STEERING_ENABLE=y in order to enable + # band steering feature. + # ############################################################################# +-ECM_BAND_STEERING_ENABLE=y ++ifndef $(ECM_BAND_STEERING_ENABLE) ++ ECM_BAND_STEERING_ENABLE=y ++endif + ccflags-$(ECM_BAND_STEERING_ENABLE) += -DECM_BAND_STEERING_ENABLE + + # ############################################################################# +--- a/ecm_db/ecm_db_connection.c ++++ b/ecm_db/ecm_db_connection.c +@@ -430,7 +430,9 @@ EXPORT_SYMBOL(ecm_db_connection_make_def + */ + void ecm_db_connection_data_totals_update(struct ecm_db_connection_instance *ci, bool is_from, uint64_t size, uint64_t packets) + { ++#ifdef ECM_DB_ADVANCED_STATS_ENABLE + int32_t i; ++#endif + + DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed\n", ci); + +@@ -529,7 +531,9 @@ EXPORT_SYMBOL(ecm_db_connection_data_tot + */ + void ecm_db_connection_data_totals_update_dropped(struct ecm_db_connection_instance *ci, bool is_from, uint64_t size, uint64_t packets) + { ++#ifdef ECM_DB_ADVANCED_STATS_ENABLE + int32_t i; ++#endif + + DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed\n", ci); + +@@ -1508,6 +1512,7 @@ void ecm_db_connection_defunct_all(void) + } + EXPORT_SYMBOL(ecm_db_connection_defunct_all); + ++#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE + /* + * ecm_db_connection_defunct_by_classifier() + * Make defunct based on masked fields +@@ -1667,6 +1672,7 @@ next_ci: + ECM_IP_ADDR_TO_OCTAL(dest_addr_mask), dest_port_mask, proto_mask, cnt); + } + } ++#endif + + /* + * ecm_db_connection_defunct_by_port() +@@ -1956,6 +1962,7 @@ struct ecm_db_node_instance *ecm_db_conn + } + EXPORT_SYMBOL(ecm_db_connection_node_get_and_ref); + ++#ifdef ECM_DB_XREF_ENABLE + /* + * ecm_db_connection_mapping_get_and_ref_next() + * Return reference to next connection in the mapping chain in the specified direction. +@@ -1997,6 +2004,7 @@ struct ecm_db_connection_instance *ecm_d + return nci; + } + EXPORT_SYMBOL(ecm_db_connection_iface_get_and_ref_next); ++#endif + + /* + * ecm_db_connection_mapping_get_and_ref() +--- a/ecm_db/ecm_db_node.c ++++ b/ecm_db/ecm_db_node.c +@@ -224,9 +224,11 @@ EXPORT_SYMBOL(ecm_db_node_get_and_ref_ne + */ + int ecm_db_node_deref(struct ecm_db_node_instance *ni) + { ++#ifdef ECM_DB_XREF_ENABLE + #if (DEBUG_LEVEL >= 1) + int dir; + #endif ++#endif + DEBUG_CHECK_MAGIC(ni, ECM_DB_NODE_INSTANCE_MAGIC, "%px: magic failed\n", ni); + + spin_lock_bh(&ecm_db_lock); +@@ -486,9 +488,11 @@ EXPORT_SYMBOL(ecm_db_node_iface_get_and_ + void ecm_db_node_add(struct ecm_db_node_instance *ni, struct ecm_db_iface_instance *ii, uint8_t *address, + ecm_db_node_final_callback_t final, void *arg) + { ++#ifdef ECM_DB_XREF_ENABLE + #if (DEBUG_LEVEL >= 1) + int dir; + #endif ++#endif + ecm_db_node_hash_t hash_index; + struct ecm_db_listener_instance *li; + +--- a/ecm_interface.c ++++ b/ecm_interface.c +@@ -1343,6 +1343,7 @@ struct neighbour *ecm_interface_ipv6_nei + */ + bool ecm_interface_is_pptp(struct sk_buff *skb, const struct net_device *out) + { ++#ifdef ECM_INTERFACE_PPTP_ENABLE + struct net_device *in; + + /* +@@ -1367,6 +1368,7 @@ bool ecm_interface_is_pptp(struct sk_buf + } + + dev_put(in); ++#endif + return false; + } + +@@ -1379,6 +1381,7 @@ bool ecm_interface_is_pptp(struct sk_buf + */ + bool ecm_interface_is_l2tp_packet_by_version(struct sk_buff *skb, const struct net_device *out, int ver) + { ++#ifdef ECM_INTERFACE_L2TPV2_PPTP_ENABLE + uint32_t flag = 0; + struct net_device *in; + +@@ -1411,6 +1414,7 @@ bool ecm_interface_is_l2tp_packet_by_ver + } + + dev_put(in); ++#endif + return false; + } + +@@ -1423,6 +1427,7 @@ bool ecm_interface_is_l2tp_packet_by_ver + */ + bool ecm_interface_is_l2tp_pptp(struct sk_buff *skb, const struct net_device *out) + { ++#ifdef ECM_INTERFACE_L2TPV2_PPTP_ENABLE + struct net_device *in; + + /* +@@ -1445,6 +1450,7 @@ bool ecm_interface_is_l2tp_pptp(struct s + } + + dev_put(in); ++#endif + return false; + } + +@@ -6630,6 +6636,7 @@ static void ecm_interface_regenerate_con + return; + } + ++#ifdef ECM_DB_XREF_ENABLE + for (dir = 0; dir < ECM_DB_OBJ_DIR_MAX; dir++) { + /* + * Re-generate all connections associated with this interface +@@ -6645,6 +6652,7 @@ static void ecm_interface_regenerate_con + ci[dir] = cin; + } + } ++#endif + + #ifdef ECM_MULTICAST_ENABLE + /* +--- a/frontends/ecm_front_end_common.c ++++ b/frontends/ecm_front_end_common.c +@@ -106,6 +106,7 @@ bool ecm_front_end_gre_proto_is_accel_al + struct nf_conntrack_tuple *tuple, + int ip_version) + { ++#ifdef ECM_INTERFACE_GRE_ENABLE + struct net_device *dev; + struct gre_base_hdr *greh; + +@@ -117,10 +118,12 @@ bool ecm_front_end_gre_proto_is_accel_al + /* + * Case 1: PPTP locally terminated + */ ++#ifdef ECM_INTERFACE_PPTP_ENABLE + if (ecm_interface_is_pptp(skb, outdev)) { + DEBUG_TRACE("%px: PPTP GRE locally terminated - allow acceleration\n", skb); + return true; + } ++#endif + + /* + * Case 2: PPTP pass through +@@ -223,6 +226,10 @@ bool ecm_front_end_gre_proto_is_accel_al + */ + DEBUG_TRACE("%px: GRE IPv%d pass through - allow acceleration\n", skb, ip_version); + return true; ++#else ++ DEBUG_TRACE("%px: GRE%d feature is disabled - do not allow acceleration\n", skb, ip_version); ++ return false; ++#endif + } + + #ifdef ECM_CLASSIFIER_DSCP_ENABLE diff --git a/qca/qca-nss-ecm/patches/100-kernel-5.10-support.patch b/qca/qca-nss-ecm/patches/100-kernel-5.10-support.patch new file mode 100644 index 000000000..3729dd3b9 --- /dev/null +++ b/qca/qca-nss-ecm/patches/100-kernel-5.10-support.patch @@ -0,0 +1,831 @@ +From e8b642c23af9146c973e828a7f4e0fb56cfc8d0b Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Sat, 15 May 2021 03:51:14 +0200 +Subject: [PATCH] add support for kernel 5.10 + +Signed-off-by: Ansuel Smith +--- + ecm_classifier_default.c | 24 +++--------- + ecm_classifier_dscp.c | 8 +--- + ecm_classifier_emesh.c | 16 ++------ + ecm_classifier_hyfi.c | 7 +--- + ecm_classifier_mark.c | 8 +--- + ecm_classifier_ovs.c | 8 +--- + ecm_classifier_pcc.c | 8 +--- + ecm_conntrack_notifier.c | 8 +--- + ecm_db/ecm_db_connection.c | 7 +--- + ecm_db/ecm_db_host.c | 7 +--- + ecm_db/ecm_db_iface.c | 7 +--- + ecm_db/ecm_db_mapping.c | 7 +--- + ecm_db/ecm_db_node.c | 7 +--- + ecm_interface.c | 4 +- + ecm_state.c | 14 ++----- + frontends/ecm_front_end_common.c | 4 +- + frontends/ecm_front_end_ipv4.c | 7 +--- + frontends/ecm_front_end_ipv6.c | 7 +--- + frontends/nss/ecm_nss_bond_notifier.c | 8 +--- + frontends/nss/ecm_nss_ipv4.c | 49 +++++++------------------ + frontends/nss/ecm_nss_ipv6.c | 49 +++++++------------------ + frontends/nss/ecm_nss_multicast_ipv4.c | 7 +--- + frontends/nss/ecm_nss_multicast_ipv6.c | 7 +--- + frontends/nss/ecm_nss_non_ported_ipv4.c | 7 +--- + frontends/nss/ecm_nss_non_ported_ipv6.c | 7 +--- + frontends/nss/ecm_nss_ported_ipv4.c | 8 +--- + frontends/nss/ecm_nss_ported_ipv6.c | 8 +--- + frontends/sfe/ecm_sfe_ipv4.c | 49 +++++++------------------ + frontends/sfe/ecm_sfe_ipv6.c | 49 +++++++------------------ + frontends/sfe/ecm_sfe_non_ported_ipv4.c | 7 +--- + frontends/sfe/ecm_sfe_non_ported_ipv6.c | 7 +--- + frontends/sfe/ecm_sfe_ported_ipv4.c | 8 +--- + frontends/sfe/ecm_sfe_ported_ipv6.c | 8 +--- + 33 files changed, 122 insertions(+), 314 deletions(-) + +--- a/ecm_classifier_default.c ++++ b/ecm_classifier_default.c +@@ -776,26 +776,14 @@ int ecm_classifier_default_init(struct d + return -1; + } + +- if (!debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_default_dentry, +- (u32 *)&ecm_classifier_default_enabled)) { +- DEBUG_ERROR("Failed to create ecm deafult classifier enabled file in debugfs\n"); +- debugfs_remove_recursive(ecm_classifier_default_dentry); +- return -1; +- } ++ debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_default_dentry, ++ (u32 *)&ecm_classifier_default_enabled); + +- if (!debugfs_create_u32("accel_mode", S_IRUGO | S_IWUSR, ecm_classifier_default_dentry, +- (u32 *)&ecm_classifier_default_accel_mode)) { +- DEBUG_ERROR("Failed to create ecm deafult classifier accel_mode file in debugfs\n"); +- debugfs_remove_recursive(ecm_classifier_default_dentry); +- return -1; +- } ++ debugfs_create_u32("accel_mode", S_IRUGO | S_IWUSR, ecm_classifier_default_dentry, ++ (u32 *)&ecm_classifier_default_accel_mode); + +- if (!debugfs_create_u32("accel_delay_pkts", S_IRUGO | S_IWUSR, ecm_classifier_default_dentry, +- (u32 *)&ecm_classifier_accel_delay_pkts)) { +- DEBUG_ERROR("Failed to create accel delay packet counts in debugfs\n"); +- debugfs_remove_recursive(ecm_classifier_default_dentry); +- return -1; +- } ++ debugfs_create_u32("accel_delay_pkts", S_IRUGO | S_IWUSR, ecm_classifier_default_dentry, ++ (u32 *)&ecm_classifier_accel_delay_pkts); + + return 0; + } +--- a/ecm_classifier_dscp.c ++++ b/ecm_classifier_dscp.c +@@ -747,12 +747,8 @@ int ecm_classifier_dscp_init(struct dent + return -1; + } + +- if (!debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_dscp_dentry, +- (u32 *)&ecm_classifier_dscp_enabled)) { +- DEBUG_ERROR("Failed to create dscp enabled file in debugfs\n"); +- debugfs_remove_recursive(ecm_classifier_dscp_dentry); +- return -1; +- } ++ debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_dscp_dentry, ++ (u32 *)&ecm_classifier_dscp_enabled); + + return 0; + } +--- a/ecm_classifier_emesh.c ++++ b/ecm_classifier_emesh.c +@@ -974,19 +974,11 @@ int ecm_classifier_emesh_init(struct den + return -1; + } + +- if (!debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_emesh_dentry, +- (u32 *)&ecm_classifier_emesh_enabled)) { +- DEBUG_ERROR("Failed to create ecm emesh classifier enabled file in debugfs\n"); +- debugfs_remove_recursive(ecm_classifier_emesh_dentry); +- return -1; +- } ++ debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_emesh_dentry, ++ (u32 *)&ecm_classifier_emesh_enabled); + +- if (!debugfs_create_u32("latency_config_enabled", S_IRUGO | S_IWUSR, ecm_classifier_emesh_dentry, +- (u32 *)&ecm_classifier_emesh_latency_config_enabled)) { +- DEBUG_ERROR("Failed to create ecm emesh classifier latency config enabled file in debugfs\n"); +- debugfs_remove_recursive(ecm_classifier_emesh_dentry); +- return -1; +- } ++ debugfs_create_u32("latency_config_enabled", S_IRUGO | S_IWUSR, ecm_classifier_emesh_dentry, ++ (u32 *)&ecm_classifier_emesh_latency_config_enabled); + + /* + * Register for service prioritization notification update. +--- a/ecm_classifier_hyfi.c ++++ b/ecm_classifier_hyfi.c +@@ -1099,11 +1099,8 @@ int ecm_classifier_hyfi_rules_init(struc + goto classifier_task_cleanup; + } + +- if (!debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_hyfi_dentry, +- (u32 *)&ecm_classifier_hyfi_enabled)) { +- DEBUG_ERROR("Failed to create ecm hyfi classifier enabled file in debugfs\n"); +- goto classifier_task_cleanup; +- } ++ debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_hyfi_dentry, ++ (u32 *)&ecm_classifier_hyfi_enabled); + + if (!debugfs_create_file("cmd", S_IWUSR, ecm_classifier_hyfi_dentry, + NULL, &ecm_classifier_hyfi_cmd_fops)) { +--- a/ecm_classifier_mark.c ++++ b/ecm_classifier_mark.c +@@ -753,12 +753,8 @@ int ecm_classifier_mark_init(struct dent + return -1; + } + +- if (!debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_mark_dentry, +- (u32 *)&ecm_classifier_mark_enabled)) { +- DEBUG_ERROR("Failed to create mark enabled file in debugfs\n"); +- debugfs_remove_recursive(ecm_classifier_mark_dentry); +- return -1; +- } ++ debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_mark_dentry, ++ (u32 *)&ecm_classifier_mark_enabled); + + return 0; + } +--- a/ecm_classifier_ovs.c ++++ b/ecm_classifier_ovs.c +@@ -2200,12 +2200,8 @@ int ecm_classifier_ovs_init(struct dentr + return -1; + } + +- if (!debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_ovs_dentry, +- (u32 *)&ecm_classifier_ovs_enabled)) { +- DEBUG_ERROR("Failed to create ovs enabled file in debugfs\n"); +- debugfs_remove_recursive(ecm_classifier_ovs_dentry); +- return -1; +- } ++ debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_ovs_dentry, ++ (u32 *)&ecm_classifier_ovs_enabled); + + return 0; + } +--- a/ecm_classifier_pcc.c ++++ b/ecm_classifier_pcc.c +@@ -1308,12 +1308,8 @@ int ecm_classifier_pcc_init(struct dentr + return -1; + } + +- if (!debugfs_create_u32("enabled", S_IRUGO, ecm_classifier_pcc_dentry, +- (u32 *)&ecm_classifier_pcc_enabled)) { +- DEBUG_ERROR("Failed to create pcc enabled file in debugfs\n"); +- debugfs_remove_recursive(ecm_classifier_pcc_dentry); +- return -1; +- } ++ debugfs_create_u32("enabled", S_IRUGO, ecm_classifier_pcc_dentry, ++ (u32 *)&ecm_classifier_pcc_enabled); + + return 0; + } +--- a/ecm_conntrack_notifier.c ++++ b/ecm_conntrack_notifier.c +@@ -414,12 +414,8 @@ int ecm_conntrack_notifier_init(struct d + return -1; + } + +- if (!debugfs_create_u32("stop", S_IRUGO | S_IWUSR, ecm_conntrack_notifier_dentry, +- (u32 *)&ecm_conntrack_notifier_stopped)) { +- DEBUG_ERROR("Failed to create ecm conntrack notifier stopped file in debugfs\n"); +- debugfs_remove_recursive(ecm_conntrack_notifier_dentry); +- return -1; +- } ++ debugfs_create_u32("stop", S_IRUGO | S_IWUSR, ecm_conntrack_notifier_dentry, ++ (u32 *)&ecm_conntrack_notifier_stopped); + + #ifdef CONFIG_NF_CONNTRACK_EVENTS + /* +--- a/ecm_db/ecm_db_connection.c ++++ b/ecm_db/ecm_db_connection.c +@@ -3642,11 +3642,8 @@ static struct file_operations ecm_db_con + */ + bool ecm_db_connection_init(struct dentry *dentry) + { +- if (!debugfs_create_u32("connection_count", S_IRUGO, dentry, +- (u32 *)&ecm_db_connection_count)) { +- DEBUG_ERROR("Failed to create ecm db connection count file in debugfs\n"); +- return false; +- } ++ debugfs_create_u32("connection_count", S_IRUGO, dentry, ++ (u32 *)&ecm_db_connection_count); + + if (!debugfs_create_file("connection_count_simple", S_IRUGO, dentry, + NULL, &ecm_db_connection_count_simple_fops)) { +--- a/ecm_db/ecm_db_host.c ++++ b/ecm_db/ecm_db_host.c +@@ -770,11 +770,8 @@ EXPORT_SYMBOL(ecm_db_host_alloc); + bool ecm_db_host_init(struct dentry *dentry) + { + +- if (!debugfs_create_u32("host_count", S_IRUGO, dentry, +- (u32 *)&ecm_db_host_count)) { +- DEBUG_ERROR("Failed to create ecm db host count file in debugfs\n"); +- return false;; +- } ++ debugfs_create_u32("host_count", S_IRUGO, dentry, ++ (u32 *)&ecm_db_host_count); + + ecm_db_host_table = vzalloc(sizeof(struct ecm_db_host_instance *) * ECM_DB_HOST_HASH_SLOTS); + if (!ecm_db_host_table) { +--- a/ecm_db/ecm_db_iface.c ++++ b/ecm_db/ecm_db_iface.c +@@ -3670,11 +3670,8 @@ EXPORT_SYMBOL(ecm_db_iface_alloc); + */ + bool ecm_db_iface_init(struct dentry *dentry) + { +- if (!debugfs_create_u32("iface_count", S_IRUGO, dentry, +- (u32 *)&ecm_db_iface_count)) { +- DEBUG_ERROR("Failed to create ecm db iface count file in debugfs\n"); +- return false; +- } ++ debugfs_create_u32("iface_count", S_IRUGO, dentry, ++ (u32 *)&ecm_db_iface_count); + + return true; + } +--- a/ecm_db/ecm_db_mapping.c ++++ b/ecm_db/ecm_db_mapping.c +@@ -806,11 +806,8 @@ EXPORT_SYMBOL(ecm_db_mapping_alloc); + */ + bool ecm_db_mapping_init(struct dentry *dentry) + { +- if (!debugfs_create_u32("mapping_count", S_IRUGO, dentry, +- (u32 *)&ecm_db_mapping_count)) { +- DEBUG_ERROR("Failed to create ecm db mapping count file in debugfs\n"); +- return false; +- } ++ debugfs_create_u32("mapping_count", S_IRUGO, dentry, ++ (u32 *)&ecm_db_mapping_count); + + ecm_db_mapping_table = vzalloc(sizeof(struct ecm_db_mapping_instance *) * ECM_DB_MAPPING_HASH_SLOTS); + if (!ecm_db_mapping_table) { +--- a/ecm_db/ecm_db_node.c ++++ b/ecm_db/ecm_db_node.c +@@ -1187,11 +1187,8 @@ keep_sni_conn: + */ + bool ecm_db_node_init(struct dentry *dentry) + { +- if (!debugfs_create_u32("node_count", S_IRUGO, dentry, +- (u32 *)&ecm_db_node_count)) { +- DEBUG_ERROR("Failed to create ecm db node count file in debugfs\n"); +- return false; +- } ++ debugfs_create_u32("node_count", S_IRUGO, dentry, ++ (u32 *)&ecm_db_node_count); + + ecm_db_node_table = vzalloc(sizeof(struct ecm_db_node_instance *) * ECM_DB_NODE_HASH_SLOTS); + if (!ecm_db_node_table) { +--- a/ecm_interface.c ++++ b/ecm_interface.c +@@ -332,7 +332,7 @@ static struct net_device *ecm_interface_ + struct net_device *dev; + + ECM_IP_ADDR_TO_NIN6_ADDR(addr6, addr); +- dev = (struct net_device *)ipv6_dev_find(&init_net, &addr6, 1); ++ dev = (struct net_device *)ipv6_dev_find_and_hold(&init_net, &addr6, 1); + return dev; + } + #endif +@@ -734,7 +734,7 @@ static bool ecm_interface_mac_addr_get_i + * Get the MAC address that corresponds to IP address given. + */ + ECM_IP_ADDR_TO_NIN6_ADDR(daddr, addr); +- local_dev = ipv6_dev_find(&init_net, &daddr, 1); ++ local_dev = ipv6_dev_find_and_hold(&init_net, &daddr, 1); + if (local_dev) { + DEBUG_TRACE("%pi6 is a local address\n", &daddr); + memcpy(mac_addr, dev->dev_addr, ETH_ALEN); +--- a/ecm_state.c ++++ b/ecm_state.c +@@ -899,17 +899,11 @@ int ecm_state_init(struct dentry *dentry + return -1; + } + +- if (!debugfs_create_u32("state_dev_major", S_IRUGO, ecm_state_dentry, +- (u32 *)&ecm_state_dev_major_id)) { +- DEBUG_ERROR("Failed to create ecm state dev major file in debugfs\n"); +- goto init_cleanup; +- } ++ debugfs_create_u32("state_dev_major", S_IRUGO, ecm_state_dentry, ++ (u32 *)&ecm_state_dev_major_id); + +- if (!debugfs_create_u32("state_file_output_mask", S_IRUGO | S_IWUSR, ecm_state_dentry, +- (u32 *)&ecm_state_file_output_mask)) { +- DEBUG_ERROR("Failed to create ecm state output mask file in debugfs\n"); +- goto init_cleanup; +- } ++ debugfs_create_u32("state_file_output_mask", S_IRUGO | S_IWUSR, ecm_state_dentry, ++ (u32 *)&ecm_state_file_output_mask); + + /* + * Register a char device that we will use to provide a dump of our state +--- a/frontends/ecm_front_end_common.c ++++ b/frontends/ecm_front_end_common.c +@@ -192,7 +192,7 @@ bool ecm_front_end_gre_proto_is_accel_al + return false; + } + } else { +- dev = ipv6_dev_find(&init_net, &(tuple->src.u3.in6), 1); ++ dev = ipv6_dev_find_and_hold(&init_net, &(tuple->src.u3.in6), 1); + if (dev) { + /* + * Source IP address is local +@@ -202,7 +202,7 @@ bool ecm_front_end_gre_proto_is_accel_al + return false; + } + +- dev = ipv6_dev_find(&init_net, &(tuple->dst.u3.in6), 1); ++ dev = ipv6_dev_find_and_hold(&init_net, &(tuple->dst.u3.in6), 1); + if (dev) { + /* + * Destination IP address is local +--- a/frontends/ecm_front_end_ipv4.c ++++ b/frontends/ecm_front_end_ipv4.c +@@ -376,11 +376,8 @@ void ecm_front_end_ipv4_stop(int num) + */ + int ecm_front_end_ipv4_init(struct dentry *dentry) + { +- if (!debugfs_create_u32("front_end_ipv4_stop", S_IRUGO | S_IWUSR, dentry, +- (u32 *)&ecm_front_end_ipv4_stopped)) { +- DEBUG_ERROR("Failed to create ecm front end ipv4 stop file in debugfs\n"); +- return -1; +- } ++ debugfs_create_u32("front_end_ipv4_stop", S_IRUGO | S_IWUSR, dentry, ++ (u32 *)&ecm_front_end_ipv4_stopped); + + switch (ecm_front_end_type_get()) { + case ECM_FRONT_END_TYPE_NSS: +--- a/frontends/ecm_front_end_ipv6.c ++++ b/frontends/ecm_front_end_ipv6.c +@@ -255,11 +255,8 @@ void ecm_front_end_ipv6_stop(int num) + */ + int ecm_front_end_ipv6_init(struct dentry *dentry) + { +- if (!debugfs_create_u32("front_end_ipv6_stop", S_IRUGO | S_IWUSR, dentry, +- (u32 *)&ecm_front_end_ipv6_stopped)) { +- DEBUG_ERROR("Failed to create ecm front end ipv6 stop file in debugfs\n"); +- return -1; +- } ++ debugfs_create_u32("front_end_ipv6_stop", S_IRUGO | S_IWUSR, dentry, ++ (u32 *)&ecm_front_end_ipv6_stopped); + + switch (ecm_front_end_type_get()) { + case ECM_FRONT_END_TYPE_NSS: +--- a/frontends/nss/ecm_nss_bond_notifier.c ++++ b/frontends/nss/ecm_nss_bond_notifier.c +@@ -240,12 +240,8 @@ int ecm_nss_bond_notifier_init(struct de + return -1; + } + +- if (!debugfs_create_u32("stop", S_IRUGO | S_IWUSR, ecm_nss_bond_notifier_dentry, +- (u32 *)&ecm_nss_bond_notifier_stopped)) { +- DEBUG_ERROR("Failed to create ecm bond notifier stopped file in debugfs\n"); +- debugfs_remove_recursive(ecm_nss_bond_notifier_dentry); +- return -1; +- } ++ debugfs_create_u32("stop", S_IRUGO | S_IWUSR, ecm_nss_bond_notifier_dentry, ++ (u32 *)&ecm_nss_bond_notifier_stopped); + + /* + * Register Link Aggregation callbacks with the bonding driver +--- a/frontends/nss/ecm_nss_ipv4.c ++++ b/frontends/nss/ecm_nss_ipv4.c +@@ -2802,41 +2802,23 @@ int ecm_nss_ipv4_init(struct dentry *den + return result; + } + +- if (!debugfs_create_u32("no_action_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, +- (u32 *)&ecm_nss_ipv4_no_action_limit_default)) { +- DEBUG_ERROR("Failed to create ecm nss ipv4 no_action_limit_default file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("no_action_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, ++ (u32 *)&ecm_nss_ipv4_no_action_limit_default); + +- if (!debugfs_create_u32("driver_fail_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, +- (u32 *)&ecm_nss_ipv4_driver_fail_limit_default)) { +- DEBUG_ERROR("Failed to create ecm nss ipv4 driver_fail_limit_default file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("driver_fail_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, ++ (u32 *)&ecm_nss_ipv4_driver_fail_limit_default); + +- if (!debugfs_create_u32("nack_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, +- (u32 *)&ecm_nss_ipv4_nack_limit_default)) { +- DEBUG_ERROR("Failed to create ecm nss ipv4 nack_limit_default file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("nack_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, ++ (u32 *)&ecm_nss_ipv4_nack_limit_default); + +- if (!debugfs_create_u32("accelerated_count", S_IRUGO, ecm_nss_ipv4_dentry, +- (u32 *)&ecm_nss_ipv4_accelerated_count)) { +- DEBUG_ERROR("Failed to create ecm nss ipv4 accelerated_count file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("accelerated_count", S_IRUGO, ecm_nss_ipv4_dentry, ++ (u32 *)&ecm_nss_ipv4_accelerated_count); + +- if (!debugfs_create_u32("pending_accel_count", S_IRUGO, ecm_nss_ipv4_dentry, +- (u32 *)&ecm_nss_ipv4_pending_accel_count)) { +- DEBUG_ERROR("Failed to create ecm nss ipv4 pending_accel_count file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("pending_accel_count", S_IRUGO, ecm_nss_ipv4_dentry, ++ (u32 *)&ecm_nss_ipv4_pending_accel_count); + +- if (!debugfs_create_u32("pending_decel_count", S_IRUGO, ecm_nss_ipv4_dentry, +- (u32 *)&ecm_nss_ipv4_pending_decel_count)) { +- DEBUG_ERROR("Failed to create ecm nss ipv4 pending_decel_count file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("pending_decel_count", S_IRUGO, ecm_nss_ipv4_dentry, ++ (u32 *)&ecm_nss_ipv4_pending_decel_count); + + if (!debugfs_create_file("accel_limit_mode", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, + NULL, &ecm_nss_ipv4_accel_limit_mode_fops)) { +@@ -2867,11 +2849,8 @@ int ecm_nss_ipv4_init(struct dentry *den + goto task_cleanup; + } + +- if (!debugfs_create_u32("vlan_passthrough_set", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, +- (u32 *)&ecm_nss_ipv4_vlan_passthrough_enable)) { +- DEBUG_ERROR("Failed to create ecm nss ipv4 vlan passthrough file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("vlan_passthrough_set", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, ++ (u32 *)&ecm_nss_ipv4_vlan_passthrough_enable); + + #ifdef ECM_NON_PORTED_SUPPORT_ENABLE + if (!ecm_nss_non_ported_ipv4_debugfs_init(ecm_nss_ipv4_dentry)) { +--- a/frontends/nss/ecm_nss_ipv6.c ++++ b/frontends/nss/ecm_nss_ipv6.c +@@ -2542,41 +2542,23 @@ int ecm_nss_ipv6_init(struct dentry *den + return result; + } + +- if (!debugfs_create_u32("no_action_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, +- (u32 *)&ecm_nss_ipv6_no_action_limit_default)) { +- DEBUG_ERROR("Failed to create ecm nss ipv6 no_action_limit_default file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("no_action_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, ++ (u32 *)&ecm_nss_ipv6_no_action_limit_default); + +- if (!debugfs_create_u32("driver_fail_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, +- (u32 *)&ecm_nss_ipv6_driver_fail_limit_default)) { +- DEBUG_ERROR("Failed to create ecm nss ipv6 driver_fail_limit_default file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("driver_fail_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, ++ (u32 *)&ecm_nss_ipv6_driver_fail_limit_default); + +- if (!debugfs_create_u32("nack_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, +- (u32 *)&ecm_nss_ipv6_nack_limit_default)) { +- DEBUG_ERROR("Failed to create ecm nss ipv6 nack_limit_default file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("nack_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, ++ (u32 *)&ecm_nss_ipv6_nack_limit_default); + +- if (!debugfs_create_u32("accelerated_count", S_IRUGO, ecm_nss_ipv6_dentry, +- (u32 *)&ecm_nss_ipv6_accelerated_count)) { +- DEBUG_ERROR("Failed to create ecm nss ipv6 accelerated_count file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("accelerated_count", S_IRUGO, ecm_nss_ipv6_dentry, ++ (u32 *)&ecm_nss_ipv6_accelerated_count); + +- if (!debugfs_create_u32("pending_accel_count", S_IRUGO, ecm_nss_ipv6_dentry, +- (u32 *)&ecm_nss_ipv6_pending_accel_count)) { +- DEBUG_ERROR("Failed to create ecm nss ipv6 pending_accel_count file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("pending_accel_count", S_IRUGO, ecm_nss_ipv6_dentry, ++ (u32 *)&ecm_nss_ipv6_pending_accel_count); + +- if (!debugfs_create_u32("pending_decel_count", S_IRUGO, ecm_nss_ipv6_dentry, +- (u32 *)&ecm_nss_ipv6_pending_decel_count)) { +- DEBUG_ERROR("Failed to create ecm nss ipv6 pending_decel_count file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("pending_decel_count", S_IRUGO, ecm_nss_ipv6_dentry, ++ (u32 *)&ecm_nss_ipv6_pending_decel_count); + + if (!debugfs_create_file("accel_limit_mode", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, + NULL, &ecm_nss_ipv6_accel_limit_mode_fops)) { +@@ -2607,11 +2589,8 @@ int ecm_nss_ipv6_init(struct dentry *den + goto task_cleanup; + } + +- if (!debugfs_create_u32("vlan_passthrough_set", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, +- (u32 *)&ecm_nss_ipv6_vlan_passthrough_enable)) { +- DEBUG_ERROR("Failed to create ecm nss ipv6 vlan passthrough file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("vlan_passthrough_set", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, ++ (u32 *)&ecm_nss_ipv6_vlan_passthrough_enable); + + #ifdef ECM_NON_PORTED_SUPPORT_ENABLE + if (!ecm_nss_non_ported_ipv6_debugfs_init(ecm_nss_ipv6_dentry)) { +--- a/frontends/nss/ecm_nss_multicast_ipv4.c ++++ b/frontends/nss/ecm_nss_multicast_ipv4.c +@@ -4139,11 +4139,8 @@ void ecm_nss_multicast_ipv4_stop(int num + */ + int ecm_nss_multicast_ipv4_init(struct dentry *dentry) + { +- if (!debugfs_create_u32("ecm_nss_multicast_ipv4_stop", S_IRUGO | S_IWUSR, dentry, +- (u32 *)&ecm_front_end_ipv4_mc_stopped)) { +- DEBUG_ERROR("Failed to create ecm front end ipv4 mc stop file in debugfs\n"); +- return -1; +- } ++ debugfs_create_u32("ecm_nss_multicast_ipv4_stop", S_IRUGO | S_IWUSR, dentry, ++ (u32 *)&ecm_front_end_ipv4_mc_stopped); + + /* + * Register multicast update callback to MCS snooper +--- a/frontends/nss/ecm_nss_multicast_ipv6.c ++++ b/frontends/nss/ecm_nss_multicast_ipv6.c +@@ -3939,11 +3939,8 @@ void ecm_nss_multicast_ipv6_stop(int num + */ + int ecm_nss_multicast_ipv6_init(struct dentry *dentry) + { +- if (!debugfs_create_u32("ecm_nss_multicast_ipv6_stop", S_IRUGO | S_IWUSR, dentry, +- (u32 *)&ecm_front_end_ipv6_mc_stopped)) { +- DEBUG_ERROR("Failed to create ecm front end ipv6 mc stop file in debugfs\n"); +- return -1; +- } ++ debugfs_create_u32("ecm_nss_multicast_ipv6_stop", S_IRUGO | S_IWUSR, dentry, ++ (u32 *)&ecm_front_end_ipv6_mc_stopped); + + /* + * Register multicast update callback to MCS snooper +--- a/frontends/nss/ecm_nss_non_ported_ipv4.c ++++ b/frontends/nss/ecm_nss_non_ported_ipv4.c +@@ -2615,11 +2615,8 @@ done: + */ + bool ecm_nss_non_ported_ipv4_debugfs_init(struct dentry *dentry) + { +- if (!debugfs_create_u32("non_ported_accelerated_count", S_IRUGO, dentry, +- (u32 *)&ecm_nss_non_ported_ipv4_accelerated_count)) { +- DEBUG_ERROR("Failed to create ecm nss ipv4 non_ported_accelerated_count file in debugfs\n"); +- return false; +- } ++ debugfs_create_u32("non_ported_accelerated_count", S_IRUGO, dentry, ++ (u32 *)&ecm_nss_non_ported_ipv4_accelerated_count); + + return true; + } +--- a/frontends/nss/ecm_nss_non_ported_ipv6.c ++++ b/frontends/nss/ecm_nss_non_ported_ipv6.c +@@ -2329,11 +2329,8 @@ done: + */ + bool ecm_nss_non_ported_ipv6_debugfs_init(struct dentry *dentry) + { +- if (!debugfs_create_u32("non_ported_accelerated_count", S_IRUGO, dentry, +- (u32 *)&ecm_nss_non_ported_ipv6_accelerated_count)) { +- DEBUG_ERROR("Failed to create ecm nss ipv6 non_ported_accelerated_count file in debugfs\n"); +- return false; +- } ++ debugfs_create_u32("non_ported_accelerated_count", S_IRUGO, dentry, ++ (u32 *)&ecm_nss_non_ported_ipv6_accelerated_count); + + return true; + } +--- a/frontends/nss/ecm_nss_ported_ipv4.c ++++ b/frontends/nss/ecm_nss_ported_ipv4.c +@@ -2944,12 +2944,8 @@ bool ecm_nss_ported_ipv4_debugfs_init(st + return false; + } + +- if (!debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, +- &ecm_nss_ported_ipv4_accelerated_count[ECM_NSS_PORTED_IPV4_PROTO_TCP])) { +- DEBUG_ERROR("Failed to create ecm nss ipv4 tcp_accelerated_count file in debugfs\n"); +- debugfs_remove(udp_dentry); +- return false; +- } ++ debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, ++ &ecm_nss_ported_ipv4_accelerated_count[ECM_NSS_PORTED_IPV4_PROTO_TCP]); + + return true; + } +--- a/frontends/nss/ecm_nss_ported_ipv6.c ++++ b/frontends/nss/ecm_nss_ported_ipv6.c +@@ -2732,12 +2732,8 @@ bool ecm_nss_ported_ipv6_debugfs_init(st + return false; + } + +- if (!debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, +- &ecm_nss_ported_ipv6_accelerated_count[ECM_NSS_PORTED_IPV6_PROTO_TCP])) { +- DEBUG_ERROR("Failed to create ecm nss ipv6 tcp_accelerated_count file in debugfs\n"); +- debugfs_remove(udp_dentry); +- return false; +- } ++ debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, ++ &ecm_nss_ported_ipv6_accelerated_count[ECM_NSS_PORTED_IPV6_PROTO_TCP]); + + return true; + } +--- a/frontends/sfe/ecm_sfe_ipv4.c ++++ b/frontends/sfe/ecm_sfe_ipv4.c +@@ -1808,48 +1808,27 @@ int ecm_sfe_ipv4_init(struct dentry *den + } + + #ifdef CONFIG_XFRM +- if (!debugfs_create_u32("reject_acceleration_for_ipsec", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, +- (u32 *)&ecm_sfe_ipv4_reject_acceleration_for_ipsec)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv4 reject_acceleration_for_ipsec file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("reject_acceleration_for_ipsec", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, ++ (u32 *)&ecm_sfe_ipv4_reject_acceleration_for_ipsec); + #endif + +- if (!debugfs_create_u32("no_action_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, +- (u32 *)&ecm_sfe_ipv4_no_action_limit_default)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv4 no_action_limit_default file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("no_action_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, ++ (u32 *)&ecm_sfe_ipv4_no_action_limit_default); + +- if (!debugfs_create_u32("driver_fail_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, +- (u32 *)&ecm_sfe_ipv4_driver_fail_limit_default)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv4 driver_fail_limit_default file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("driver_fail_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, ++ (u32 *)&ecm_sfe_ipv4_driver_fail_limit_default); + +- if (!debugfs_create_u32("nack_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, +- (u32 *)&ecm_sfe_ipv4_nack_limit_default)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv4 nack_limit_default file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("nack_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, ++ (u32 *)&ecm_sfe_ipv4_nack_limit_default); + +- if (!debugfs_create_u32("accelerated_count", S_IRUGO, ecm_sfe_ipv4_dentry, +- (u32 *)&ecm_sfe_ipv4_accelerated_count)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv4 accelerated_count file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("accelerated_count", S_IRUGO, ecm_sfe_ipv4_dentry, ++ (u32 *)&ecm_sfe_ipv4_accelerated_count); + +- if (!debugfs_create_u32("pending_accel_count", S_IRUGO, ecm_sfe_ipv4_dentry, +- (u32 *)&ecm_sfe_ipv4_pending_accel_count)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv4 pending_accel_count file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("pending_accel_count", S_IRUGO, ecm_sfe_ipv4_dentry, ++ (u32 *)&ecm_sfe_ipv4_pending_accel_count); + +- if (!debugfs_create_u32("pending_decel_count", S_IRUGO, ecm_sfe_ipv4_dentry, +- (u32 *)&ecm_sfe_ipv4_pending_decel_count)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv4 pending_decel_count file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("pending_decel_count", S_IRUGO, ecm_sfe_ipv4_dentry, ++ (u32 *)&ecm_sfe_ipv4_pending_decel_count); + + if (!debugfs_create_file("accel_limit_mode", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, + NULL, &ecm_sfe_ipv4_accel_limit_mode_fops)) { +--- a/frontends/sfe/ecm_sfe_ipv6.c ++++ b/frontends/sfe/ecm_sfe_ipv6.c +@@ -1532,48 +1532,27 @@ int ecm_sfe_ipv6_init(struct dentry *den + } + + #ifdef CONFIG_XFRM +- if (!debugfs_create_u32("reject_acceleration_for_ipsec", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, +- (u32 *)&ecm_sfe_ipv6_reject_acceleration_for_ipsec)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv6 reject_acceleration_for_ipsec file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("reject_acceleration_for_ipsec", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, ++ (u32 *)&ecm_sfe_ipv6_reject_acceleration_for_ipsec); + #endif + +- if (!debugfs_create_u32("no_action_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, +- (u32 *)&ecm_sfe_ipv6_no_action_limit_default)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv6 no_action_limit_default file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("no_action_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, ++ (u32 *)&ecm_sfe_ipv6_no_action_limit_default); + +- if (!debugfs_create_u32("driver_fail_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, +- (u32 *)&ecm_sfe_ipv6_driver_fail_limit_default)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv6 driver_fail_limit_default file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("driver_fail_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, ++ (u32 *)&ecm_sfe_ipv6_driver_fail_limit_default); + +- if (!debugfs_create_u32("nack_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, +- (u32 *)&ecm_sfe_ipv6_nack_limit_default)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv6 nack_limit_default file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("nack_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, ++ (u32 *)&ecm_sfe_ipv6_nack_limit_default); + +- if (!debugfs_create_u32("accelerated_count", S_IRUGO, ecm_sfe_ipv6_dentry, +- (u32 *)&ecm_sfe_ipv6_accelerated_count)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv6 accelerated_count file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("accelerated_count", S_IRUGO, ecm_sfe_ipv6_dentry, ++ (u32 *)&ecm_sfe_ipv6_accelerated_count); + +- if (!debugfs_create_u32("pending_accel_count", S_IRUGO, ecm_sfe_ipv6_dentry, +- (u32 *)&ecm_sfe_ipv6_pending_accel_count)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv6 pending_accel_count file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("pending_accel_count", S_IRUGO, ecm_sfe_ipv6_dentry, ++ (u32 *)&ecm_sfe_ipv6_pending_accel_count); + +- if (!debugfs_create_u32("pending_decel_count", S_IRUGO, ecm_sfe_ipv6_dentry, +- (u32 *)&ecm_sfe_ipv6_pending_decel_count)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv6 pending_decel_count file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("pending_decel_count", S_IRUGO, ecm_sfe_ipv6_dentry, ++ (u32 *)&ecm_sfe_ipv6_pending_decel_count); + + if (!debugfs_create_file("accel_limit_mode", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, + NULL, &ecm_sfe_ipv6_accel_limit_mode_fops)) { +--- a/frontends/sfe/ecm_sfe_non_ported_ipv4.c ++++ b/frontends/sfe/ecm_sfe_non_ported_ipv4.c +@@ -2284,11 +2284,8 @@ done: + */ + bool ecm_sfe_non_ported_ipv4_debugfs_init(struct dentry *dentry) + { +- if (!debugfs_create_u32("non_ported_accelerated_count", S_IRUGO, dentry, +- (u32 *)&ecm_sfe_non_ported_ipv4_accelerated_count)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv4 non_ported_accelerated_count file in debugfs\n"); +- return false; +- } ++ debugfs_create_u32("non_ported_accelerated_count", S_IRUGO, dentry, ++ (u32 *)&ecm_sfe_non_ported_ipv4_accelerated_count); + + return true; + } +--- a/frontends/sfe/ecm_sfe_non_ported_ipv6.c ++++ b/frontends/sfe/ecm_sfe_non_ported_ipv6.c +@@ -2083,11 +2083,8 @@ done: + */ + bool ecm_sfe_non_ported_ipv6_debugfs_init(struct dentry *dentry) + { +- if (!debugfs_create_u32("non_ported_accelerated_count", S_IRUGO, dentry, +- (u32 *)&ecm_sfe_non_ported_ipv6_accelerated_count)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv6 non_ported_accelerated_count file in debugfs\n"); +- return false; +- } ++ debugfs_create_u32("non_ported_accelerated_count", S_IRUGO, dentry, ++ (u32 *)&ecm_sfe_non_ported_ipv6_accelerated_count); + + return true; + } +--- a/frontends/sfe/ecm_sfe_ported_ipv4.c ++++ b/frontends/sfe/ecm_sfe_ported_ipv4.c +@@ -2528,12 +2528,8 @@ bool ecm_sfe_ported_ipv4_debugfs_init(st + return false; + } + +- if (!debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, +- &ecm_sfe_ported_ipv4_accelerated_count[ECM_SFE_PORTED_IPV4_PROTO_TCP])) { +- DEBUG_ERROR("Failed to create ecm sfe ipv4 tcp_accelerated_count file in debugfs\n"); +- debugfs_remove(udp_dentry); +- return false; +- } ++ debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, ++ &ecm_sfe_ported_ipv4_accelerated_count[ECM_SFE_PORTED_IPV4_PROTO_TCP]); + + return true; + } +--- a/frontends/sfe/ecm_sfe_ported_ipv6.c ++++ b/frontends/sfe/ecm_sfe_ported_ipv6.c +@@ -2374,12 +2374,8 @@ bool ecm_sfe_ported_ipv6_debugfs_init(st + return false; + } + +- if (!debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, +- &ecm_sfe_ported_ipv6_accelerated_count[ECM_SFE_PORTED_IPV6_PROTO_TCP])) { +- DEBUG_ERROR("Failed to create ecm sfe ipv6 tcp_accelerated_count file in debugfs\n"); +- debugfs_remove(udp_dentry); +- return false; +- } ++ debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, ++ &ecm_sfe_ported_ipv6_accelerated_count[ECM_SFE_PORTED_IPV6_PROTO_TCP]); + + return true; + } diff --git a/qca/qca-nss-ecm/patches/200-resolve-high-load.patch b/qca/qca-nss-ecm/patches/200-resolve-high-load.patch new file mode 100644 index 000000000..253b450a5 --- /dev/null +++ b/qca/qca-nss-ecm/patches/200-resolve-high-load.patch @@ -0,0 +1,61 @@ +From 6924b71ed809b37fffd74d6428a8ca83e5919746 Mon Sep 17 00:00:00 2001 +From: Dirk Buchwalder +Date: Sun, 27 Jun 2021 16:52:39 +0200 +Subject: [PATCH] qca-nss-ecm: resolve the cpu high load regarding ecm + +If using ECM, cpu load goes up (around 1.0) and stucks there. +This is due to using uninterruptible sleep function, +the patch changes this to interruptible sleep function. + +Signed-off-by: Dirk Buchwalder +--- + frontends/nss/ecm_nss_ipv4.c | 4 ++-- + frontends/nss/ecm_nss_ipv6.c | 4 ++-- + 2 files changed, 4 insertions(+), 4 deletions(-) + +diff --git a/frontends/nss/ecm_nss_ipv4.c b/frontends/nss/ecm_nss_ipv4.c +index e00553c..94b39cd 100644 +--- a/frontends/nss/ecm_nss_ipv4.c ++++ b/frontends/nss/ecm_nss_ipv4.c +@@ -2471,7 +2471,7 @@ static void ecm_nss_ipv4_stats_sync_req_work(struct work_struct *work) + } + spin_unlock_bh(&ecm_nss_ipv4_lock); + +- usleep_range(ECM_NSS_IPV4_STATS_SYNC_UDELAY - 100, ECM_NSS_IPV4_STATS_SYNC_UDELAY); ++ msleep_interruptible(ECM_NSS_IPV4_STATS_SYNC_UDELAY / 1000); + + /* + * If index is 0, we are starting a new round, but if we still have time remain +@@ -2485,7 +2485,7 @@ static void ecm_nss_ipv4_stats_sync_req_work(struct work_struct *work) + } + + if (time_after(ecm_nss_ipv4_next_req_time, current_jiffies)) { +- msleep(jiffies_to_msecs(ecm_nss_ipv4_next_req_time - current_jiffies)); ++ msleep_interruptible(jiffies_to_msecs(ecm_nss_ipv4_next_req_time - current_jiffies)); + } + ecm_nss_ipv4_roll_check_jiffies = jiffies; + ecm_nss_ipv4_next_req_time = ecm_nss_ipv4_roll_check_jiffies + ECM_NSS_IPV4_STATS_SYNC_PERIOD; +diff --git a/frontends/nss/ecm_nss_ipv6.c b/frontends/nss/ecm_nss_ipv6.c +index 82e739f..30af050 100644 +--- a/frontends/nss/ecm_nss_ipv6.c ++++ b/frontends/nss/ecm_nss_ipv6.c +@@ -2210,7 +2210,7 @@ static void ecm_nss_ipv6_stats_sync_req_work(struct work_struct *work) + } + spin_unlock_bh(&ecm_nss_ipv6_lock); + +- usleep_range(ECM_NSS_IPV6_STATS_SYNC_UDELAY - 100, ECM_NSS_IPV6_STATS_SYNC_UDELAY); ++ msleep_interruptible(ECM_NSS_IPV6_STATS_SYNC_UDELAY / 1000); + + /* + * If index is 0, we are starting a new round, but if we still have time remain +@@ -2224,7 +2224,7 @@ static void ecm_nss_ipv6_stats_sync_req_work(struct work_struct *work) + } + + if (time_after(ecm_nss_ipv6_next_req_time, current_jiffies)) { +- msleep(jiffies_to_msecs(ecm_nss_ipv6_next_req_time - current_jiffies)); ++ msleep_interruptible(jiffies_to_msecs(ecm_nss_ipv6_next_req_time - current_jiffies)); + } + ecm_nss_ipv6_roll_check_jiffies = jiffies; + ecm_nss_ipv6_next_req_time = ecm_nss_ipv6_roll_check_jiffies + ECM_NSS_IPV6_STATS_SYNC_PERIOD; +-- +2.31.1 diff --git a/qca/qca-nss-ecm/patches/203-rework-nfct-notification.patch b/qca/qca-nss-ecm/patches/203-rework-nfct-notification.patch new file mode 100644 index 000000000..72005cd70 --- /dev/null +++ b/qca/qca-nss-ecm/patches/203-rework-nfct-notification.patch @@ -0,0 +1,25 @@ +--- a/ecm_conntrack_notifier.c ++++ b/ecm_conntrack_notifier.c +@@ -421,7 +421,11 @@ int ecm_conntrack_notifier_init(struct d + /* + * Eventing subsystem is available so we register a notifier hook to get fast notifications of expired connections + */ ++#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS ++ result = nf_conntrack_register_chain_notifier(&init_net, &ecm_conntrack_notifier); ++#else + result = nf_conntrack_register_notifier(&init_net, &ecm_conntrack_notifier); ++#endif + if (result < 0) { + DEBUG_ERROR("Can't register nf notifier hook.\n"); + debugfs_remove_recursive(ecm_conntrack_notifier_dentry); +@@ -439,7 +443,9 @@ EXPORT_SYMBOL(ecm_conntrack_notifier_ini + void ecm_conntrack_notifier_exit(void) + { + DEBUG_INFO("ECM Conntrack Notifier exit\n"); +-#ifdef CONFIG_NF_CONNTRACK_EVENTS ++#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS ++ nf_conntrack_unregister_chain_notifier(&init_net, &ecm_conntrack_notifier); ++#else + nf_conntrack_unregister_notifier(&init_net, &ecm_conntrack_notifier); + #endif + /* diff --git a/qca/qca-nss-ecm/patches/204-More-compile-fixes.patch b/qca/qca-nss-ecm/patches/204-More-compile-fixes.patch new file mode 100644 index 000000000..63a83c193 --- /dev/null +++ b/qca/qca-nss-ecm/patches/204-More-compile-fixes.patch @@ -0,0 +1,49 @@ +From e6d701c0d454d841366c556b2ef07a5203ffb35d Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Fri, 21 May 2021 21:41:31 +0200 +Subject: [PATCH] More compile fixes + +More runtime compile fixes. + +Signed-off-by: Robert Marko +--- + frontends/nss/ecm_nss_ported_ipv4.c | 12 +++--------- + frontends/nss/ecm_nss_ported_ipv6.c | 12 +++--------- + 2 files changed, 6 insertions(+), 18 deletions(-) + +--- a/frontends/nss/ecm_nss_ported_ipv4.c ++++ b/frontends/nss/ecm_nss_ported_ipv4.c +@@ -2935,14 +2935,8 @@ done: + */ + bool ecm_nss_ported_ipv4_debugfs_init(struct dentry *dentry) + { +- struct dentry *udp_dentry; +- +- udp_dentry = debugfs_create_u32("udp_accelerated_count", S_IRUGO, dentry, ++ debugfs_create_u32("udp_accelerated_count", S_IRUGO, dentry, + &ecm_nss_ported_ipv4_accelerated_count[ECM_NSS_PORTED_IPV4_PROTO_UDP]); +- if (!udp_dentry) { +- DEBUG_ERROR("Failed to create ecm nss ipv4 udp_accelerated_count file in debugfs\n"); +- return false; +- } + + debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, + &ecm_nss_ported_ipv4_accelerated_count[ECM_NSS_PORTED_IPV4_PROTO_TCP]); +--- a/frontends/nss/ecm_nss_ported_ipv6.c ++++ b/frontends/nss/ecm_nss_ported_ipv6.c +@@ -2723,14 +2723,8 @@ done: + */ + bool ecm_nss_ported_ipv6_debugfs_init(struct dentry *dentry) + { +- struct dentry *udp_dentry; +- +- udp_dentry = debugfs_create_u32("udp_accelerated_count", S_IRUGO, dentry, ++ debugfs_create_u32("udp_accelerated_count", S_IRUGO, dentry, + &ecm_nss_ported_ipv6_accelerated_count[ECM_NSS_PORTED_IPV6_PROTO_UDP]); +- if (!udp_dentry) { +- DEBUG_ERROR("Failed to create ecm nss ipv6 udp_accelerated_count file in debugfs\n"); +- return false; +- } + + debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, + &ecm_nss_ported_ipv6_accelerated_count[ECM_NSS_PORTED_IPV6_PROTO_TCP]); diff --git a/qca/qca-nss-ecm/patches/205-resolve-high-load.patch b/qca/qca-nss-ecm/patches/205-resolve-high-load.patch new file mode 100644 index 000000000..dd1ee13af --- /dev/null +++ b/qca/qca-nss-ecm/patches/205-resolve-high-load.patch @@ -0,0 +1,55 @@ +From 6924b71ed809b37fffd74d6428a8ca83e5919746 Mon Sep 17 00:00:00 2001 +From: Dirk Buchwalder +Date: Sun, 27 Jun 2021 16:52:39 +0200 +Subject: [PATCH] qca-nss-ecm: resolve the cpu high load regarding ecm + +If using ECM, cpu load goes up (around 1.0) and stucks there. +This is due to using uninterruptible sleep function, +the patch changes this to interruptible sleep function. + +Signed-off-by: Dirk Buchwalder buchwalder@posteo.de +--- + frontends/nss/ecm_nss_ipv4.c | 4 ++-- + frontends/nss/ecm_nss_ipv6.c | 4 ++-- + 2 files changed, 4 insertions(+), 4 deletions(-) + +--- a/frontends/nss/ecm_nss_ipv4.c ++++ b/frontends/nss/ecm_nss_ipv4.c +@@ -2471,7 +2471,7 @@ static void ecm_nss_ipv4_stats_sync_req_ + } + spin_unlock_bh(&ecm_nss_ipv4_lock); + +- usleep_range(ECM_NSS_IPV4_STATS_SYNC_UDELAY - 100, ECM_NSS_IPV4_STATS_SYNC_UDELAY); ++ msleep_interruptible(ECM_NSS_IPV4_STATS_SYNC_UDELAY / 1000); + + /* + * If index is 0, we are starting a new round, but if we still have time remain +@@ -2485,7 +2485,7 @@ static void ecm_nss_ipv4_stats_sync_req_ + } + + if (time_after(ecm_nss_ipv4_next_req_time, current_jiffies)) { +- msleep(jiffies_to_msecs(ecm_nss_ipv4_next_req_time - current_jiffies)); ++ msleep_interruptible(jiffies_to_msecs(ecm_nss_ipv4_next_req_time - current_jiffies)); + } + ecm_nss_ipv4_roll_check_jiffies = jiffies; + ecm_nss_ipv4_next_req_time = ecm_nss_ipv4_roll_check_jiffies + ECM_NSS_IPV4_STATS_SYNC_PERIOD; +--- a/frontends/nss/ecm_nss_ipv6.c ++++ b/frontends/nss/ecm_nss_ipv6.c +@@ -2210,7 +2210,7 @@ static void ecm_nss_ipv6_stats_sync_req_ + } + spin_unlock_bh(&ecm_nss_ipv6_lock); + +- usleep_range(ECM_NSS_IPV6_STATS_SYNC_UDELAY - 100, ECM_NSS_IPV6_STATS_SYNC_UDELAY); ++ msleep_interruptible(ECM_NSS_IPV6_STATS_SYNC_UDELAY / 1000); + + /* + * If index is 0, we are starting a new round, but if we still have time remain +@@ -2224,7 +2224,7 @@ static void ecm_nss_ipv6_stats_sync_req_ + } + + if (time_after(ecm_nss_ipv6_next_req_time, current_jiffies)) { +- msleep(jiffies_to_msecs(ecm_nss_ipv6_next_req_time - current_jiffies)); ++ msleep_interruptible(jiffies_to_msecs(ecm_nss_ipv6_next_req_time - current_jiffies)); + } + ecm_nss_ipv6_roll_check_jiffies = jiffies; + ecm_nss_ipv6_next_req_time = ecm_nss_ipv6_roll_check_jiffies + ECM_NSS_IPV6_STATS_SYNC_PERIOD; diff --git a/qca/qca-ssdk-shell/Makefile b/qca/qca-ssdk-shell/Makefile new file mode 100644 index 000000000..f872e431e --- /dev/null +++ b/qca/qca-ssdk-shell/Makefile @@ -0,0 +1,48 @@ +include $(TOPDIR)/rules.mk + +PKG_NAME:=qca-ssdk-shell +PKG_RELEASE:=$(AUTORELEASE) + +PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/ssdk-shell.git +PKG_SOURCE_PROTO:=git +PKG_SOURCE_DATE:=2022-03-16 +PKG_SOURCE_VERSION:=72a7dc725ae9ccbe7d99f451a6518e7c0dde4740 +PKG_MIRROR_HASH:=a591875ad05d7a6779cf9da575d890bc470889308f239c89a14721924420ac2b + +include $(INCLUDE_DIR)/kernel.mk +include $(INCLUDE_DIR)/package.mk + +define Package/qca-ssdk-shell + SECTION:=QCA + CATEGORY:=Utilities + TITLE:=Shell application for QCA SSDK +endef + + +define Package/qca-ssdk-shell/Description + This package contains a qca-ssdk shell application for QCA chipset +endef + +ifndef CONFIG_TOOLCHAIN_BIN_PATH +CONFIG_TOOLCHAIN_BIN_PATH=$(TOOLCHAIN_DIR)/bin +endif + +QCASSDK_CONFIG_OPTS+= TOOL_PATH=$(CONFIG_TOOLCHAIN_BIN_PATH) \ + SYS_PATH=$(LINUX_DIR) \ + TOOLPREFIX=$(TARGET_CROSS) \ + KVER=$(LINUX_VERSION) \ + CFLAGS="$(TARGET_CFLAGS)" \ + LDFLAGS="$(TARGET_LDFLAGS)" \ + ARCH=$(LINUX_KARCH) + +define Build/Compile + $(MAKE) -C $(PKG_BUILD_DIR) $(strip $(QCASSDK_CONFIG_OPTS)) +endef + +define Package/qca-ssdk-shell/install + $(INSTALL_DIR) $(1)/usr/sbin + $(INSTALL_BIN) $(PKG_BUILD_DIR)/build/bin/ssdk_sh $(1)/usr/sbin/ +endef + + +$(eval $(call BuildPackage,qca-ssdk-shell)) diff --git a/qca/qca-ssdk/Makefile b/qca/qca-ssdk/Makefile new file mode 100644 index 000000000..5b1a7956f --- /dev/null +++ b/qca/qca-ssdk/Makefile @@ -0,0 +1,91 @@ +include $(TOPDIR)/rules.mk + +PKG_NAME:=qca-ssdk +PKG_RELEASE:=$(AUTORELEASE) + +PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/qca-ssdk.git +PKG_SOURCE_PROTO:=git +PKG_SOURCE_DATE:=2022-04-07 +PKG_SOURCE_VERSION:=62955de3c838028d3f72313eef99c57fa4babb71 +PKG_MIRROR_HASH:=84c7de6d1ce82fb15acebea0e44158695a33ed6f18335da32ec9f248dcb4b285 + +include $(INCLUDE_DIR)/kernel.mk +include $(INCLUDE_DIR)/package.mk + +define KernelPackage/qca-ssdk-nohnat + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=Kernel driver for QCA SSDK + DEPENDS:=@(TARGET_ipq807x) + FILES:=$(PKG_BUILD_DIR)/build/bin/qca-ssdk.ko + AUTOLOAD:=$(call AutoLoad,30,qca-ssdk) +endef + +define KernelPackage/qca-ssdk-nohnat/Description +This package contains a qca-ssdk driver for QCA chipset +endef + +GCC_VERSION=$(shell echo "$(CONFIG_GCC_VERSION)" | sed 's/[^0-9.]*\([0-9.]*\).*/\1/') + +ifdef CONFIG_TOOLCHAIN_BIN_PATH +TOOLCHAIN_BIN_PATH=$(CONFIG_TOOLCHAIN_BIN_PATH) +else +TOOLCHAIN_BIN_PATH=$(TOOLCHAIN_DIR)/bin +endif + +MAKE_FLAGS+= \ + TARGET_NAME=$(CONFIG_TARGET_NAME) \ + TOOL_PATH=$(TOOLCHAIN_BIN_PATH) \ + SYS_PATH=$(LINUX_DIR) \ + TOOLPREFIX=$(TARGET_CROSS) \ + KVER=$(LINUX_VERSION) \ + ARCH=$(LINUX_KARCH) \ + TARGET_SUFFIX=$(CONFIG_TARGET_SUFFIX) \ + GCC_VERSION=$(GCC_VERSION) \ + EXTRA_CFLAGS=-fno-stack-protector -I$(STAGING_DIR)/usr/include \ + $(KERNEL_MAKE_FLAGS) + +ifneq (, $(findstring $(CONFIG_TARGET_BOARD), "ipq60xx" "ipq807x")) + MAKE_FLAGS+= PTP_FEATURE=disable SWCONFIG_FEATURE=disable +endif + +ifeq ($(CONFIG_TARGET_BOARD), "ipq807x") + MAKE_FLAGS+= CHIP_TYPE=HPPE +else ifeq ($(CONFIG_TARGET_BOARD), "ipq60xx") + MAKE_FLAGS+= CHIP_TYPE=CPPE +endif + +define Build/InstallDev + $(INSTALL_DIR) $(1)/usr/include/qca-ssdk + $(INSTALL_DIR) $(1)/usr/include/qca-ssdk/api + $(INSTALL_DIR) $(1)/usr/include/qca-ssdk/ref + $(INSTALL_DIR) $(1)/usr/include/qca-ssdk/fal + $(INSTALL_DIR) $(1)/usr/include/qca-ssdk/sal + $(INSTALL_DIR) $(1)/usr/include/qca-ssdk/init + $(CP) -rf $(PKG_BUILD_DIR)/include/api/sw_ioctl.h $(1)/usr/include/qca-ssdk/api + if [ -f $(PKG_BUILD_DIR)/include/ref/ref_vsi.h ]; then \ + $(CP) -rf $(PKG_BUILD_DIR)/include/ref/ref_vsi.h $(1)/usr/include/qca-ssdk/ref/; \ + fi + if [ -f $(PKG_BUILD_DIR)/include/ref/ref_fdb.h ]; then \ + $(CP) -rf $(PKG_BUILD_DIR)/include/ref/ref_fdb.h $(1)/usr/include/qca-ssdk/ref/; \ + fi + if [ -f $(PKG_BUILD_DIR)/include/ref/ref_port_ctrl.h ]; then \ + $(CP) -rf $(PKG_BUILD_DIR)/include/ref/ref_port_ctrl.h $(1)/usr/include/qca-ssdk/ref/; \ + fi + if [ -f $(PKG_BUILD_DIR)/include/init/ssdk_init.h ]; then \ + $(CP) -rf $(PKG_BUILD_DIR)/include/init/ssdk_init.h $(1)/usr/include/qca-ssdk/init/; \ + fi + $(CP) -rf $(PKG_BUILD_DIR)/include/fal $(1)/usr/include/qca-ssdk + $(CP) -rf $(PKG_BUILD_DIR)/include/common/*.h $(1)/usr/include/qca-ssdk + $(CP) -rf $(PKG_BUILD_DIR)/include/sal/os/linux/*.h $(1)/usr/include/qca-ssdk + $(CP) -rf $(PKG_BUILD_DIR)/include/sal/os/*.h $(1)/usr/include/qca-ssdk + +endef + +define KernelPackage/qca-ssdk-nohnat/install + $(INSTALL_DIR) $(1)/etc/init.d + $(INSTALL_BIN) ./files/qca-ssdk $(1)/etc/init.d/qca-ssdk +endef + +$(eval $(call KernelPackage,qca-ssdk-nohnat)) diff --git a/qca/qca-ssdk/files/qca-ssdk b/qca/qca-ssdk/files/qca-ssdk new file mode 100644 index 000000000..389279c0c --- /dev/null +++ b/qca/qca-ssdk/files/qca-ssdk @@ -0,0 +1,206 @@ +#!/bin/sh /etc/rc.common +# Copyright (c) 2018, The Linux Foundation. All rights reserved. +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +# + +START=16 + +#!/bin/sh +ruletype="ip4 ip6" +side="wan lan" +qwan="1 3 2 0 5 7 6 4" +qlan="0 1 2 3 4 5 6 7" + +function create_war_acl_rules(){ + for lw in $side + do + #echo $lw + if [ "$lw" == "wan" ];then + listid=254 + queue=$qwan + portmap=0x20 + else + listid=255 + queue=$qlan + portmap=0x1e + fi + #echo $queue + #echo "creating list $listid" + ssdk_sh acl list create $listid 255 + ruleid=0 + for rt in $ruletype + do + for qid in $queue + do + cmd="ssdk_sh acl rule add $listid $ruleid 1 n 0 0" + #echo $cmd + if [ "$rt" == "ip4" ];then + cmd="$cmd ip4 n n n n n n n n n n n n n n n n n n n n n n n n n n n n n" + #echo $cmd + else + cmd="$cmd ip6 n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n" + #echo $cmd + fi + if [ $ruleid -le 3 ];then + #non-zero dscp + cmd="$cmd y 0x0 0xff" + elif [ $ruleid -le 7 ];then + #zero dscp + cmd="$cmd n" + elif [ $ruleid -le 11 ];then + #non-zero dscp + cmd="$cmd y 0x0 0xff" + else + #zero dscp + cmd="$cmd n" + fi + p=$((ruleid/2)) + cmd="$cmd y mask $((ruleid%2)) 0x1 y mask $((p%2)) 0x1 n n n n n n n n n n n n n n n y n n n n n n n y $qid n n 0 0 n n n n n n n n n n n n n n n n n n n n 0" + #echo $cmd + $cmd + ruleid=`expr $ruleid + 1` + done + done + ssdk_sh acl list bind $listid 0 1 $portmap + done +} + +function create_war_cosmap(){ + ssdk_sh cosmap pri2q set 0 0 + ssdk_sh cosmap pri2q set 1 0 + ssdk_sh cosmap pri2q set 2 0 + ssdk_sh cosmap pri2q set 3 0 + ssdk_sh cosmap pri2q set 4 1 + ssdk_sh cosmap pri2q set 5 1 + ssdk_sh cosmap pri2q set 6 1 + ssdk_sh cosmap pri2q set 7 1 + ssdk_sh cosmap pri2ehq set 0 0 + ssdk_sh cosmap pri2ehq set 1 0 + ssdk_sh cosmap pri2ehq set 2 0 + ssdk_sh cosmap pri2ehq set 3 0 + ssdk_sh cosmap pri2ehq set 4 1 + ssdk_sh cosmap pri2ehq set 5 1 + ssdk_sh cosmap pri2ehq set 6 1 + ssdk_sh cosmap pri2ehq set 7 1 +} + +function create_acl_byp_egstp_rules(){ + ssdk_sh debug module_func set servcode 0xf 0x0 0x0 + ssdk_sh servcode config set 1 n 0 0xfffefc7f 0xffbdff 0 0 0 0 0 0 + ssdk_sh debug module_func set servcode 0x0 0x0 0x0 + ssdk_sh acl list create 56 48 + ssdk_sh acl rule add 56 0 1 n 0 0 mac n n n n n y 01-80-c2-00-00-00 ff-ff-ff-ff-ff-ff n n n n n n n n n n n n n n n n n n n n n n n y n n n n n n n n n n 0 0 n n n n n n n n n n n n n y n n n n n n n n n n n n y n n n n n n n n n n n n 0 + ssdk_sh acl rule add 56 1 1 n 0 0 mac n n n n n n n yes 0x8809 0xffff n n n n n n n n n n n n n n n n n n n n n y n n n n n n n n n n 0 0 n n n n n n n n n n n n n y n n n n n n n n n n n n y n n n n n n n n n n n n 0 + ssdk_sh acl rule add 56 2 1 n 0 0 mac n n n n n n n yes 0x888e 0xffff n n n n n n n n n n n n n n n n n n n n n y n n n n n n n n n n 0 0 n n n n n n n n n n n n n y n n n n n n n n n n n n y n n n n n n n n n n n n 0 + ssdk_sh acl list bind 56 0 2 1 +} + +function delete_war_acl_rules(){ + for lw in $side + do + #echo $lw + if [ "$lw" == "wan" ];then + listid=254 + queue=$qwan + portmap=0x20 + else + listid=255 + queue=$qlan + portmap=0x1e + fi + ssdk_sh acl list unbind $listid 0 1 $portmap + for rt in $ruletype + do + for qid in $queue + do + cmd="ssdk_sh acl rule del $listid 0 1" + echo $cmd + $cmd + done + done + #echo "deleting list $listid" + ssdk_sh acl list destroy $listid + done +} + +function delete_war_cosmap(){ + ssdk_sh cosmap pri2q set 0 0 + ssdk_sh cosmap pri2q set 1 0 + ssdk_sh cosmap pri2q set 2 1 + ssdk_sh cosmap pri2q set 3 1 + ssdk_sh cosmap pri2q set 4 2 + ssdk_sh cosmap pri2q set 5 2 + ssdk_sh cosmap pri2q set 6 3 + ssdk_sh cosmap pri2q set 7 3 + ssdk_sh cosmap pri2ehq set 0 1 + ssdk_sh cosmap pri2ehq set 1 0 + ssdk_sh cosmap pri2ehq set 2 2 + ssdk_sh cosmap pri2ehq set 3 2 + ssdk_sh cosmap pri2ehq set 4 3 + ssdk_sh cosmap pri2ehq set 5 3 + ssdk_sh cosmap pri2ehq set 6 4 + ssdk_sh cosmap pri2ehq set 7 5 +} + +function delete_acl_byp_egstp_rules(){ + ssdk_sh debug module_func set servcode 0xf 0x0 0x0 + ssdk_sh servcode config set 1 n 0 0xfffefcff 0xffbfff 0 0 0 0 0 0 + ssdk_sh debug module_func set servcode 0x0 0x0 0x0 + ssdk_sh acl list unbind 56 0 2 1 + ssdk_sh acl rule del 56 0 1 + ssdk_sh acl rule del 56 1 1 + ssdk_sh acl rule del 56 2 1 + ssdk_sh acl list destroy 56 +} + +function edma_war_config_add(){ + create_war_cosmap + ssdk_sh acl status set enable + create_war_acl_rules +} + +function edma_war_config_del(){ + delete_war_acl_rules + delete_war_cosmap +} + +start() { + chip_ver=`ssdk_sh debug reg get 0 4 | grep Data | tr -d 'SSDK Init OK![Data]:'` + #The following commands should be uncommented to enable EDMA WAR + if [ "$chip_ver" = "0x1401" ]; then + #edma_war_config_add + echo '' + fi + #The following commands should be uncommented to add acl egress stp bypass rules + if [ "$chip_ver" = "0x1500" ] || [ "$chip_ver" = "0x1501" ]; then + #create_acl_byp_egstp_rules + echo '' + fi + echo starting +} + +stop() { + chip_ver=`ssdk_sh debug reg get 0 4 | grep Data | tr -d 'SSDK Init OK![Data]:'` + #The following commands should be uncommented to disable EDMA WAR + if [ "$chip_ver" = "0x1401" ]; then + #edma_war_config_del + echo '' + fi + #The following commands should be uncommented to delete acl egress stp bypass rules + if [ "$chip_ver" = "0x1500" ] || [ "$chip_ver" = "0x1501" ]; then + #delete_acl_byp_egstp_rules + echo '' + fi + echo stoping +} diff --git a/qca/qca-ssdk/patches/0001-SSDK-config-add-kernel-5.10.patch b/qca/qca-ssdk/patches/0001-SSDK-config-add-kernel-5.10.patch new file mode 100644 index 000000000..8ad541ebf --- /dev/null +++ b/qca/qca-ssdk/patches/0001-SSDK-config-add-kernel-5.10.patch @@ -0,0 +1,56 @@ +From 472c0c8132784608312c80c4b02c03ea7c132235 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Wed, 12 May 2021 13:41:12 +0200 +Subject: [PATCH] SSDK: config: add kernel 5.10 + +This is purely to identify it and be able to set +flags correctly. + +Signed-off-by: Robert Marko +--- + config | 6 +++++- + make/linux_opt.mk | 4 ++-- + 2 files changed, 7 insertions(+), 3 deletions(-) + +--- a/config ++++ b/config +@@ -22,6 +22,10 @@ ifeq ($(KVER),$(filter 5.4%,$(KVER))) + OS_VER=5_4 + endif + ++ifeq ($(KVER),$(filter 5.10%,$(KVER))) ++OS_VER=5_10 ++endif ++ + ifeq ($(KVER), 3.4.0) + OS_VER=3_4 + endif +@@ -123,7 +127,7 @@ endif + endif + + ifeq ($(ARCH), arm64) +- ifeq ($(KVER),$(filter 4.1% 4.4% 4.9% 5.4%,$(KVER))) ++ ifeq ($(KVER),$(filter 4.1% 4.4% 4.9% 5.4% 5.10%,$(KVER))) + CPU_CFLAG= -DMODULE -Os -pipe -march=armv8-a -mcpu=cortex-a53+crypto -fno-caller-saves -fno-strict-aliasing -Werror -fno-common -Wno-format-security -Wno-pointer-sign -Wno-unused-but-set-variable -Wno-error=unused-result -mcmodel=large + endif + endif +--- a/make/linux_opt.mk ++++ b/make/linux_opt.mk +@@ -388,7 +388,7 @@ ifeq (KSLIB, $(MODULE_TYPE)) + KASAN_SHADOW_SCALE_SHIFT := 3 + endif + +- ifeq (5_4, $(OS_VER)) ++ ifeq ($(OS_VER),$(filter 5_4 5_10, $(OS_VER))) + ifeq ($(ARCH), arm64) + KASAN_OPTION += -DKASAN_SHADOW_SCALE_SHIFT=$(KASAN_SHADOW_SCALE_SHIFT) + endif +@@ -419,7 +419,7 @@ ifeq (KSLIB, $(MODULE_TYPE)) + + endif + +- ifeq ($(OS_VER),$(filter 4_4 5_4, $(OS_VER))) ++ ifeq ($(OS_VER),$(filter 4_4 5_4 5_10, $(OS_VER))) + MODULE_CFLAG += -DKVER34 + MODULE_CFLAG += -DKVER32 + MODULE_CFLAG += -DLNX26_22 diff --git a/qca/qca-ssdk/patches/0002-SSDK-replace-ioremap_nocache-with-ioremap.patch b/qca/qca-ssdk/patches/0002-SSDK-replace-ioremap_nocache-with-ioremap.patch new file mode 100644 index 000000000..b293ad295 --- /dev/null +++ b/qca/qca-ssdk/patches/0002-SSDK-replace-ioremap_nocache-with-ioremap.patch @@ -0,0 +1,102 @@ +From 784f2cfdfaf3bdf44917924e157049230a0ef5f8 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Wed, 12 May 2021 13:45:45 +0200 +Subject: [PATCH] SSDK: replace ioremap_nocache with ioremap + +ioremap_nocache was dropped upstream, simply use the +generic variety. + +Signed-off-by: Robert Marko +--- + src/init/ssdk_clk.c | 10 +++++----- + src/init/ssdk_init.c | 2 +- + src/init/ssdk_plat.c | 6 +++--- + 3 files changed, 9 insertions(+), 9 deletions(-) + +--- a/src/init/ssdk_clk.c ++++ b/src/init/ssdk_clk.c +@@ -623,7 +623,7 @@ ssdk_mp_tcsr_get(a_uint32_t tcsr_offset, + { + void __iomem *tcsr_base = NULL; + +- tcsr_base = ioremap_nocache(TCSR_ETH_ADDR, TCSR_ETH_SIZE); ++ tcsr_base = ioremap(TCSR_ETH_ADDR, TCSR_ETH_SIZE); + if (!tcsr_base) + { + SSDK_ERROR("Failed to map tcsr eth address!\n"); +@@ -640,7 +640,7 @@ ssdk_mp_tcsr_set(a_uint32_t tcsr_offset, + { + void __iomem *tcsr_base = NULL; + +- tcsr_base = ioremap_nocache(TCSR_ETH_ADDR, TCSR_ETH_SIZE); ++ tcsr_base = ioremap(TCSR_ETH_ADDR, TCSR_ETH_SIZE); + if (!tcsr_base) + { + SSDK_ERROR("Failed to map tcsr eth address!\n"); +@@ -688,7 +688,7 @@ ssdk_mp_cmnblk_stable_check(void) + a_uint32_t reg_val; + int i, loops = 20; + +- pll_lock = ioremap_nocache(CMN_PLL_LOCKED_ADDR, CMN_PLL_LOCKED_SIZE); ++ pll_lock = ioremap(CMN_PLL_LOCKED_ADDR, CMN_PLL_LOCKED_SIZE); + if (!pll_lock) { + SSDK_ERROR("Failed to map CMN PLL LOCK register!\n"); + return A_FALSE; +@@ -745,7 +745,7 @@ static void ssdk_cmnblk_pll_src_set(enum + void __iomem *cmn_pll_src_base = NULL; + a_uint32_t reg_val; + +- cmn_pll_src_base = ioremap_nocache(CMN_BLK_PLL_SRC_ADDR, CMN_BLK_SIZE); ++ cmn_pll_src_base = ioremap(CMN_BLK_PLL_SRC_ADDR, CMN_BLK_SIZE); + if (!cmn_pll_src_base) { + SSDK_ERROR("Failed to map cmn pll source address!\n"); + return; +@@ -766,7 +766,7 @@ static void ssdk_cmnblk_init(enum cmnblk + void __iomem *gcc_pll_base = NULL; + a_uint32_t reg_val; + +- gcc_pll_base = ioremap_nocache(CMN_BLK_ADDR, CMN_BLK_SIZE); ++ gcc_pll_base = ioremap(CMN_BLK_ADDR, CMN_BLK_SIZE); + if (!gcc_pll_base) { + SSDK_ERROR("Failed to map gcc pll address!\n"); + return; +--- a/src/init/ssdk_init.c ++++ b/src/init/ssdk_init.c +@@ -2770,7 +2770,7 @@ static int ssdk_dess_mac_mode_init(a_uin + (a_uint8_t *)®_value, 4); + mdelay(10); + /*softreset psgmii, fixme*/ +- gcc_addr = ioremap_nocache(0x1812000, 0x200); ++ gcc_addr = ioremap(0x1812000, 0x200); + if (!gcc_addr) { + SSDK_ERROR("gcc map fail!\n"); + return 0; +--- a/src/init/ssdk_plat.c ++++ b/src/init/ssdk_plat.c +@@ -1312,7 +1312,7 @@ ssdk_plat_init(ssdk_init_cfg *cfg, a_uin + reg_mode = ssdk_uniphy_reg_access_mode_get(dev_id); + if(reg_mode == HSL_REG_LOCAL_BUS) { + ssdk_uniphy_reg_map_info_get(dev_id, &map); +- qca_phy_priv_global[dev_id]->uniphy_hw_addr = ioremap_nocache(map.base_addr, ++ qca_phy_priv_global[dev_id]->uniphy_hw_addr = ioremap(map.base_addr, + map.size); + if (!qca_phy_priv_global[dev_id]->uniphy_hw_addr) { + SSDK_ERROR("%s ioremap fail.", __func__); +@@ -1327,7 +1327,7 @@ ssdk_plat_init(ssdk_init_cfg *cfg, a_uin + reg_mode = ssdk_switch_reg_access_mode_get(dev_id); + if(reg_mode == HSL_REG_LOCAL_BUS) { + ssdk_switch_reg_map_info_get(dev_id, &map); +- qca_phy_priv_global[dev_id]->hw_addr = ioremap_nocache(map.base_addr, ++ qca_phy_priv_global[dev_id]->hw_addr = ioremap(map.base_addr, + map.size); + if (!qca_phy_priv_global[dev_id]->hw_addr) { + SSDK_ERROR("%s ioremap fail.", __func__); +@@ -1358,7 +1358,7 @@ ssdk_plat_init(ssdk_init_cfg *cfg, a_uin + return -1; + } + +- qca_phy_priv_global[dev_id]->psgmii_hw_addr = ioremap_nocache(map.base_addr, ++ qca_phy_priv_global[dev_id]->psgmii_hw_addr = ioremap(map.base_addr, + map.size); + if (!qca_phy_priv_global[dev_id]->psgmii_hw_addr) { + SSDK_ERROR("%s ioremap fail.", __func__); diff --git a/qca/qca-ssdk/patches/0004-platform-use-of_mdio_find_bus-to-get-MDIO-bus.patch b/qca/qca-ssdk/patches/0004-platform-use-of_mdio_find_bus-to-get-MDIO-bus.patch new file mode 100644 index 000000000..3bcbcccf6 --- /dev/null +++ b/qca/qca-ssdk/patches/0004-platform-use-of_mdio_find_bus-to-get-MDIO-bus.patch @@ -0,0 +1,40 @@ +From b6190ca46287d01a895c7cc14de30410c09ff1b8 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Wed, 12 May 2021 17:15:46 +0200 +Subject: [PATCH] SSDK: platform: use of_mdio_find_bus() to get MDIO bus + +Kernel has a generic of_mdio_find_bus() which can get the appropriate +MDIO bus based on the DT node. +So, drop the getting MDIO from platform data, which no longer works +in 5.4 and later and use of_mdio_find_bus(). + +Signed-off-by: Baruch Siach +Signed-off-by: Robert Marko +--- + src/init/ssdk_plat.c | 8 +------- + 1 file changed, 1 insertion(+), 7 deletions(-) + +--- a/src/init/ssdk_plat.c ++++ b/src/init/ssdk_plat.c +@@ -551,7 +551,6 @@ static int miibus_get(a_uint32_t dev_id) + struct device_node *mdio_node = NULL; + struct device_node *switch_node = NULL; + struct platform_device *mdio_plat = NULL; +- struct ipq40xx_mdio_data *mdio_data = NULL; + struct qca_phy_priv *priv; + hsl_reg_mode reg_mode = HSL_REG_LOCAL_BUS; + priv = qca_phy_priv_global[dev_id]; +@@ -584,12 +583,7 @@ static int miibus_get(a_uint32_t dev_id) + + if(reg_mode == HSL_REG_LOCAL_BUS) + { +- mdio_data = dev_get_drvdata(&mdio_plat->dev); +- if (!mdio_data) { +- SSDK_ERROR("cannot get mdio_data reference from device data\n"); +- return 1; +- } +- priv->miibus = mdio_data->mii_bus; ++ priv->miibus = of_mdio_find_bus(mdio_node); + } + else + priv->miibus = dev_get_drvdata(&mdio_plat->dev); diff --git a/qca/qca-ssdk/patches/0005-SSDK-dts-fix-of_get_mac_address.patch b/qca/qca-ssdk/patches/0005-SSDK-dts-fix-of_get_mac_address.patch new file mode 100644 index 000000000..29be93128 --- /dev/null +++ b/qca/qca-ssdk/patches/0005-SSDK-dts-fix-of_get_mac_address.patch @@ -0,0 +1,42 @@ +From f3a7b93137c1a6a1b8010b86296242178eed5d9e Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Fri, 13 Aug 2021 20:03:21 +0200 +Subject: [PATCH] SSDK: dts: fix of_get_mac_address() + +Recently OpenWrt backported the updated of_get_mac_address() +function which returns and error code instead. + +So, patch the SSDK to use it and fix the compilation error. + +Signed-off-by: Robert Marko +--- + src/init/ssdk_dts.c | 7 ++++--- + 1 file changed, 4 insertions(+), 3 deletions(-) + +--- a/src/init/ssdk_dts.c ++++ b/src/init/ssdk_dts.c +@@ -779,8 +779,9 @@ static void ssdk_dt_parse_intf_mac(void) + { + struct device_node *dp_node = NULL; + a_uint32_t dp = 0; +- a_uint8_t *maddr = NULL; ++ u8 maddr[ETH_ALEN]; + char dp_name[8] = {0}; ++ int ret; + + for (dp = 1; dp <= SSDK_MAX_NR_ETH; dp++) { + snprintf(dp_name, sizeof(dp_name), "dp%d", dp); +@@ -788,11 +789,11 @@ static void ssdk_dt_parse_intf_mac(void) + if (!dp_node) { + continue; + } +- maddr = (a_uint8_t *)of_get_mac_address(dp_node); ++ ret = of_get_mac_address(dp_node, maddr); + #if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0)) + if (maddr && is_valid_ether_addr(maddr)) { + #else +- if (!IS_ERR(maddr) && is_valid_ether_addr(maddr)) { ++ if (!ret && is_valid_ether_addr(maddr)) { + #endif + ssdk_dt_global.num_intf_mac++; + ether_addr_copy(ssdk_dt_global.intf_mac[dp-1].uc, maddr); diff --git a/qca/qca-ssdk/patches/0006-SSDK-config-add-kernel-5.15.patch b/qca/qca-ssdk/patches/0006-SSDK-config-add-kernel-5.15.patch new file mode 100644 index 000000000..a4e1b2782 --- /dev/null +++ b/qca/qca-ssdk/patches/0006-SSDK-config-add-kernel-5.15.patch @@ -0,0 +1,56 @@ +From 599f19551dc8db3cb396e4c139a73bd72300ebf5 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Fri, 24 Dec 2021 19:39:02 +0100 +Subject: [PATCH] SSDK: config: add kernel 5.15 + +This is purely to identify it and be able to set +flags correctly. + +Signed-off-by: Robert Marko +--- + config | 6 +++++- + make/linux_opt.mk | 4 ++-- + 2 files changed, 7 insertions(+), 3 deletions(-) + +--- a/config ++++ b/config +@@ -26,6 +26,10 @@ ifeq ($(KVER),$(filter 5.10%,$(KVER))) + OS_VER=5_10 + endif + ++ifeq ($(KVER),$(filter 5.15%,$(KVER))) ++OS_VER=5_15 ++endif ++ + ifeq ($(KVER), 3.4.0) + OS_VER=3_4 + endif +@@ -127,7 +131,7 @@ endif + endif + + ifeq ($(ARCH), arm64) +- ifeq ($(KVER),$(filter 4.1% 4.4% 4.9% 5.4% 5.10%,$(KVER))) ++ ifeq ($(KVER),$(filter 4.1% 4.4% 4.9% 5.4% 5.10% 5.15%,$(KVER))) + CPU_CFLAG= -DMODULE -Os -pipe -march=armv8-a -mcpu=cortex-a53+crypto -fno-caller-saves -fno-strict-aliasing -Werror -fno-common -Wno-format-security -Wno-pointer-sign -Wno-unused-but-set-variable -Wno-error=unused-result -mcmodel=large + endif + endif +--- a/make/linux_opt.mk ++++ b/make/linux_opt.mk +@@ -388,7 +388,7 @@ ifeq (KSLIB, $(MODULE_TYPE)) + KASAN_SHADOW_SCALE_SHIFT := 3 + endif + +- ifeq ($(OS_VER),$(filter 5_4 5_10, $(OS_VER))) ++ ifeq ($(OS_VER),$(filter 5_4 5_10 5_15, $(OS_VER))) + ifeq ($(ARCH), arm64) + KASAN_OPTION += -DKASAN_SHADOW_SCALE_SHIFT=$(KASAN_SHADOW_SCALE_SHIFT) + endif +@@ -419,7 +419,7 @@ ifeq (KSLIB, $(MODULE_TYPE)) + + endif + +- ifeq ($(OS_VER),$(filter 4_4 5_4 5_10, $(OS_VER))) ++ ifeq ($(OS_VER),$(filter 4_4 5_4 5_10 5_15, $(OS_VER))) + MODULE_CFLAG += -DKVER34 + MODULE_CFLAG += -DKVER32 + MODULE_CFLAG += -DLNX26_22 diff --git a/qca/qca-ssdk/patches/0007-qca8081-convert-to-5.11-IRQ-model.patch b/qca/qca-ssdk/patches/0007-qca8081-convert-to-5.11-IRQ-model.patch new file mode 100644 index 000000000..b0c272b17 --- /dev/null +++ b/qca/qca-ssdk/patches/0007-qca8081-convert-to-5.11-IRQ-model.patch @@ -0,0 +1,83 @@ +From 25ff0ae02accadd7b05f1dae788505f833d5c019 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Fri, 24 Dec 2021 20:02:32 +0100 +Subject: [PATCH] qca8081: convert to 5.11 IRQ model + +Kernel 5.11 introduced new IRQ handling model for PHY-s, +so provide those if 5.11 or later is used. + +Signed-off-by: Robert Marko +--- + src/hsl/phy/qca808x.c | 46 +++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 46 insertions(+) + +--- a/src/hsl/phy/qca808x.c ++++ b/src/hsl/phy/qca808x.c +@@ -238,6 +238,7 @@ static int qca808x_config_intr(struct ph + return err; + } + ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 11, 0)) + static int qca808x_ack_interrupt(struct phy_device *phydev) + { + int err; +@@ -257,6 +258,47 @@ static int qca808x_ack_interrupt(struct + + return (err < 0) ? err : 0; + } ++#endif ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(5, 11, 0)) ++static irqreturn_t qca808x_handle_interrupt(struct phy_device *phydev) ++{ ++ a_uint16_t irq_status, int_enabled; ++ a_uint32_t dev_id = 0, phy_id = 0; ++ qca808x_priv *priv = phydev->priv; ++ const struct qca808x_phy_info *pdata = priv->phy_info; ++ ++ if (!pdata) { ++ return SW_FAIL; ++ } ++ ++ dev_id = pdata->dev_id; ++ phy_id = pdata->phy_addr; ++ ++ irq_status = qca808x_phy_reg_read(dev_id, phy_id, ++ QCA808X_PHY_INTR_STATUS); ++ if (irq_status < 0) { ++ phy_error(phydev); ++ return IRQ_NONE; ++ } ++ ++ /* Read the current enabled interrupts */ ++ int_enabled = qca808x_phy_reg_read(dev_id, phy_id, ++ QCA808X_PHY_INTR_MASK); ++ if (int_enabled < 0) { ++ phy_error(phydev); ++ return IRQ_NONE; ++ } ++ ++ /* See if this was one of our enabled interrupts */ ++ if (!(irq_status & int_enabled)) ++ return IRQ_NONE; ++ ++ phy_trigger_machine(phydev); ++ ++ return IRQ_HANDLED; ++} ++#endif + + /* switch linux negtiation capability to fal avariable */ + #if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0)) +@@ -559,7 +601,11 @@ struct phy_driver qca808x_phy_driver = { + .config_intr = qca808x_config_intr, + .config_aneg = qca808x_config_aneg, + .aneg_done = qca808x_aneg_done, ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 11, 0)) + .ack_interrupt = qca808x_ack_interrupt, ++#else ++ .handle_interrupt = qca808x_handle_interrupt, ++#endif + .read_status = qca808x_read_status, + .suspend = qca808x_suspend, + .resume = qca808x_resume, diff --git a/qca/qca-ssdk/patches/0008-qca807x-add-a-LED-quirk-for-Xiaomi-AX9000.patch b/qca/qca-ssdk/patches/0008-qca807x-add-a-LED-quirk-for-Xiaomi-AX9000.patch new file mode 100644 index 000000000..76f71be46 --- /dev/null +++ b/qca/qca-ssdk/patches/0008-qca807x-add-a-LED-quirk-for-Xiaomi-AX9000.patch @@ -0,0 +1,74 @@ +From 86624624c2b593c57999780a3838e6a9fe40b30c Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Tue, 11 Jan 2022 00:28:42 +0100 +Subject: [PATCH] qca807x: add a LED quirk for Xiaomi AX9000 + +Xiaomi AX9000 has a single LED for each of 4 gigabit ethernet ports that +are connected to QCA8075, and that LED is connected to the 100M LED pin. + +So, by default it will only work when in 10 or 100Mbit mode, this is quite +annoying and makes no sense(If they have connected it to the 1000Mbit LED +pin then it would have worked for 10/100 by default as well). + +So, to solve this add a check for system compatible as we cant parse if +from DTS in any other way and set the 100M LED to blink on 1000Base-T +as well. + +Signed-off-by: Robert Marko +--- + include/hsl/phy/malibu_phy.h | 2 ++ + src/hsl/phy/malibu_phy.c | 11 +++++++++++ + 2 files changed, 13 insertions(+) + +diff --git a/include/hsl/phy/malibu_phy.h b/include/hsl/phy/malibu_phy.h +index b7354041..ec7a0621 100755 +--- a/include/hsl/phy/malibu_phy.h ++++ b/include/hsl/phy/malibu_phy.h +@@ -94,6 +94,7 @@ extern "C" + #define MALIBU_DAC_CTRL_MASK 0x380 + #define MALIBU_DAC_CTRL_VALUE 0x280 + #define MALIBU_LED_1000_CTRL1_100_10_MASK 0x30 ++#define MALIBU_LED_100_CTRL1_1000_MASK 0x40 + + #define MALIBU_PHY_EEE_ADV_100M 0x0002 + #define MALIBU_PHY_EEE_ADV_1000M 0x0004 +@@ -118,6 +119,7 @@ extern "C" + #define MALIBU_PHY_MMD7_EGRESS_COUNTER_HIGH 0x802d + #define MALIBU_PHY_MMD7_EGRESS_COUNTER_LOW 0x802e + #define MALIBU_PHY_MMD7_EGRESS_ERROR_COUNTER 0x802f ++#define MALIBU_PHY_MMD7_LED_100_CTRL1 0x8074 + #define MALIBU_PHY_MMD7_LED_1000_CTRL1 0x8076 + + +diff --git a/src/hsl/phy/malibu_phy.c b/src/hsl/phy/malibu_phy.c +index 1f4dba15..2bef9fa3 100644 +--- a/src/hsl/phy/malibu_phy.c ++++ b/src/hsl/phy/malibu_phy.c +@@ -12,6 +12,8 @@ + * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + ++#include ++ + #include "sw.h" + #include "fal_port_ctrl.h" + #include "hsl_api.h" +@@ -2726,6 +2728,15 @@ malibu_phy_hw_init(a_uint32_t dev_id, a_uint32_t port_bmp) + led_status |= MALIBU_LED_1000_CTRL1_100_10_MASK; + malibu_phy_mmd_write(dev_id, phy_addr, MALIBU_PHY_MMD7_NUM, + MALIBU_PHY_MMD7_LED_1000_CTRL1, led_status); ++ if (of_machine_is_compatible("xiaomi,ax9000")) { ++ /* add 1000M link LED behavior for Xiaomi AX9000 */ ++ led_status = malibu_phy_mmd_read(dev_id, phy_addr, MALIBU_PHY_MMD7_NUM, ++ MALIBU_PHY_MMD7_LED_100_CTRL1); ++ led_status &= ~MALIBU_LED_100_CTRL1_1000_MASK; ++ led_status |= MALIBU_LED_100_CTRL1_1000_MASK; ++ malibu_phy_mmd_write(dev_id, phy_addr, MALIBU_PHY_MMD7_NUM, ++ MALIBU_PHY_MMD7_LED_100_CTRL1, led_status); ++ } + /*disable Extended next page*/ + phy_data = malibu_phy_reg_read(dev_id, phy_addr, MALIBU_AUTONEG_ADVERT); + phy_data &= ~MALIBU_EXTENDED_NEXT_PAGE_EN; +-- +2.34.1 + diff --git a/qca/qca-ssdk/patches/0009-qca807x-add-a-LED-quirk-for-Xiaomi-AX3600.patch b/qca/qca-ssdk/patches/0009-qca807x-add-a-LED-quirk-for-Xiaomi-AX3600.patch new file mode 100644 index 000000000..c31ea6da9 --- /dev/null +++ b/qca/qca-ssdk/patches/0009-qca807x-add-a-LED-quirk-for-Xiaomi-AX3600.patch @@ -0,0 +1,29 @@ +From 913514b9177e77836f2c8d61fc498b54f54c6775 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Wed, 26 Jan 2022 14:47:33 +0100 +Subject: [PATCH] qca807x: add a LED quirk for Xiaomi AX3600 + +AX3600 requires the same LED quirk so that PHY LED-s will blink even +once Linux resets the PHY. + +So, just check for its compatible. + +Signed-off-by: Robert Marko +--- + src/hsl/phy/malibu_phy.c | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +--- a/src/hsl/phy/malibu_phy.c ++++ b/src/hsl/phy/malibu_phy.c +@@ -2728,8 +2728,9 @@ malibu_phy_hw_init(a_uint32_t dev_id, a_ + led_status |= MALIBU_LED_1000_CTRL1_100_10_MASK; + malibu_phy_mmd_write(dev_id, phy_addr, MALIBU_PHY_MMD7_NUM, + MALIBU_PHY_MMD7_LED_1000_CTRL1, led_status); +- if (of_machine_is_compatible("xiaomi,ax9000")) { +- /* add 1000M link LED behavior for Xiaomi AX9000 */ ++ /* add 1000M link LED behavior for Xiaomi boards */ ++ if (of_machine_is_compatible("xiaomi,ax9000") || ++ of_machine_is_compatible("xiaomi,ax3600")) { + led_status = malibu_phy_mmd_read(dev_id, phy_addr, MALIBU_PHY_MMD7_NUM, + MALIBU_PHY_MMD7_LED_100_CTRL1); + led_status &= ~MALIBU_LED_100_CTRL1_1000_MASK; diff --git a/qca/qca-ssdk/patches/0012-include-fix-compilation-error-for-parse_uci_option.patch b/qca/qca-ssdk/patches/0012-include-fix-compilation-error-for-parse_uci_option.patch new file mode 100644 index 000000000..01b8deda9 --- /dev/null +++ b/qca/qca-ssdk/patches/0012-include-fix-compilation-error-for-parse_uci_option.patch @@ -0,0 +1,27 @@ +From 8e3500df074625b3eb3a8ed4e8e0b1b116f13d0c Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Sat, 7 May 2022 19:03:55 +0200 +Subject: [PATCH] include: fix compilation error for parse_uci_option + +Fix missing include for parse_uci_option + +Signed-off-by: Ansuel Smith +--- + include/ref/ref_uci.h | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/include/ref/ref_uci.h b/include/ref/ref_uci.h +index a42ea153..0906c5ba 100755 +--- a/include/ref/ref_uci.h ++++ b/include/ref/ref_uci.h +@@ -19,6 +19,7 @@ + extern "C" { + #endif /* __cplusplus */ + ++#include + + #if defined(IN_SWCONFIG) + int +-- +2.34.1 + From a48d42f30470a2e1bebcf99d8ebaf8b9cd8b8173 Mon Sep 17 00:00:00 2001 From: suyuan <175338101@qq.com> Date: Tue, 13 Sep 2022 13:54:06 +0800 Subject: [PATCH 16/19] Revert "add qca" This reverts commit 8f8028cb7f7bdc60ae6a9c688500c5b6d6c01dbc. --- qca/aq-fw-download/Makefile | 26 - qca/aq-fw-download/src/Makefile | 14 - qca/aq-fw-download/src/include/AQ_API.h | 246 - .../src/include/AQ_PhyInterface.h | 171 - .../src/include/AQ_PlatformRoutines.h | 71 - qca/aq-fw-download/src/include/AQ_RegMacro.h | 323 - .../src/include/AQ_ReturnCodes.h | 113 - qca/aq-fw-download/src/include/AQ_User.h | 97 - .../APPIA/AQ_APPIA_Global_registers.h | 5581 ------- .../APPIA/AQ_APPIA_Global_registers_Defines.h | 2134 --- .../AQ_APPIA_Global_registers_reversed.h | 5581 ------- .../include/registerMap/AQ_RegGroupMaxSizes.h | 387 - .../src/include/registerMap/AQ_RegMaps.h | 69 - .../registerMap/HHD/AQ_HHD_Global_registers.h | 12123 ---------------- .../HHD/AQ_HHD_Global_registers_Defines.h | 4413 ------ .../HHD/AQ_HHD_Global_registers_reversed.h | 12123 ---------------- qca/aq-fw-download/src/mdioBootLoadCLD.c | 193 - qca/aq-fw-download/src/src/AQ_API.c | 1021 -- qca/aq-fw-download/src/src/AQ_PhyInterface.c | 141 - qca/nss-eip-firmware/Makefile | 34 - qca/nss-eip-firmware/src/.gitkeep | 0 qca/nss-firmware/Makefile | 72 - qca/qca-nss-cfi/Makefile | 71 - .../patches/100-remove-noise-logs.patch | 30 - qca/qca-nss-clients/Makefile | 102 - qca/qca-nss-clients/files/qca-nss-ipsec | 214 - qca/qca-nss-clients/files/qca-nss-mirred.init | 28 - qca/qca-nss-clients/files/qca-nss-ovpn.init | 69 - qca/qca-nss-crypto/Makefile | 72 - ...1-nss-crypto-fix-SHA1-header-include.patch | 32 - ...replace-ioremap_nocache-with-ioremap.patch | 69 - ...rypto-fix-SHA-header-include-in-5.15.patch | 51 - qca/qca-nss-dp/Makefile | 56 - ...port-newer-kernels-time-stamping-API.patch | 44 - ...-phy-mode-code-compatible-with-newer.patch | 48 - ...03-Drop-_nocache-variants-of-ioremap.patch | 48 - .../0004-EDMA-Fix-NAPI-packet-counting.patch | 31 - ...-Use-NAPI_POLL_WEIGHT-as-NAPI-weight.patch | 41 - .../0006-NSS-DP-fix-of_get_mac_address.patch | 46 - ...07-NSS-DP-implement-ethernet-IOCTL-s.patch | 29 - ...dev-remove-the-transaction-structure.patch | 48 - ...09-switchdev-use-new-switchdev-flags.patch | 51 - .../0010-switchdev-fix-FDB-roaming.patch | 110 - ...fusing-printing-of-registered-netdev.patch | 48 - ...syn-xgmac-silence-debug-log-on-probe.patch | 28 - ...a-phy-handle-property-to-connect-to-.patch | 189 - ...p-edma-v1-switch-to-napi_gro_receive.patch | 46 - qca/qca-nss-drv/Makefile | 129 - qca/qca-nss-drv/files/qca-nss-drv.conf | 6 - qca/qca-nss-drv/files/qca-nss-drv.debug | 26 - qca/qca-nss-drv/files/qca-nss-drv.hotplug | 70 - qca/qca-nss-drv/files/qca-nss-drv.init | 50 - qca/qca-nss-drv/files/qca-nss-drv.sysctl | 4 - ...ore-add-5.10-kernel-to-version-check.patch | 25 - ...replace-ioremap_nocache-with-ioremap.patch | 181 - ...0003-DMA-Fix-NULL-pointer-exceptions.patch | 49 - ...-rework-NSS_CORE_DMA_CACHE_MAINT-ops.patch | 573 - ...-nss-drv-add-support-for-kernel-5.15.patch | 70 - ...dard-skb_skip_tc_classify-instead-of.patch | 30 - ...Makefile-modularize-driver-even-more.patch | 172 - qca/qca-nss-ecm/Makefile | 97 - qca/qca-nss-ecm/files/ecm_dump.sh | 95 - qca/qca-nss-ecm/files/on-demand-down | 6 - qca/qca-nss-ecm/files/qca-nss-ecm.defaults | 28 - qca/qca-nss-ecm/files/qca-nss-ecm.firewall | 18 - qca/qca-nss-ecm/files/qca-nss-ecm.init | 142 - qca/qca-nss-ecm/files/qca-nss-ecm.sysctl | 2 - qca/qca-nss-ecm/files/qca-nss-ecm.uci | 2 - ...de-componentize-the-module-even-more.patch | 335 - .../patches/100-kernel-5.10-support.patch | 831 -- .../patches/200-resolve-high-load.patch | 61 - .../203-rework-nfct-notification.patch | 25 - .../patches/204-More-compile-fixes.patch | 49 - .../patches/205-resolve-high-load.patch | 55 - qca/qca-ssdk-shell/Makefile | 48 - qca/qca-ssdk/Makefile | 91 - qca/qca-ssdk/files/qca-ssdk | 206 - .../0001-SSDK-config-add-kernel-5.10.patch | 56 - ...replace-ioremap_nocache-with-ioremap.patch | 102 - ...use-of_mdio_find_bus-to-get-MDIO-bus.patch | 40 - ...0005-SSDK-dts-fix-of_get_mac_address.patch | 42 - .../0006-SSDK-config-add-kernel-5.15.patch | 56 - ...07-qca8081-convert-to-5.11-IRQ-model.patch | 83 - ...7x-add-a-LED-quirk-for-Xiaomi-AX9000.patch | 74 - ...7x-add-a-LED-quirk-for-Xiaomi-AX3600.patch | 29 - ...mpilation-error-for-parse_uci_option.patch | 27 - 86 files changed, 50519 deletions(-) delete mode 100644 qca/aq-fw-download/Makefile delete mode 100644 qca/aq-fw-download/src/Makefile delete mode 100644 qca/aq-fw-download/src/include/AQ_API.h delete mode 100644 qca/aq-fw-download/src/include/AQ_PhyInterface.h delete mode 100644 qca/aq-fw-download/src/include/AQ_PlatformRoutines.h delete mode 100644 qca/aq-fw-download/src/include/AQ_RegMacro.h delete mode 100644 qca/aq-fw-download/src/include/AQ_ReturnCodes.h delete mode 100644 qca/aq-fw-download/src/include/AQ_User.h delete mode 100644 qca/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers.h delete mode 100644 qca/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers_Defines.h delete mode 100644 qca/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers_reversed.h delete mode 100644 qca/aq-fw-download/src/include/registerMap/AQ_RegGroupMaxSizes.h delete mode 100644 qca/aq-fw-download/src/include/registerMap/AQ_RegMaps.h delete mode 100644 qca/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers.h delete mode 100644 qca/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers_Defines.h delete mode 100644 qca/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers_reversed.h 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qca/qca-ssdk/patches/0006-SSDK-config-add-kernel-5.15.patch delete mode 100644 qca/qca-ssdk/patches/0007-qca8081-convert-to-5.11-IRQ-model.patch delete mode 100644 qca/qca-ssdk/patches/0008-qca807x-add-a-LED-quirk-for-Xiaomi-AX9000.patch delete mode 100644 qca/qca-ssdk/patches/0009-qca807x-add-a-LED-quirk-for-Xiaomi-AX3600.patch delete mode 100644 qca/qca-ssdk/patches/0012-include-fix-compilation-error-for-parse_uci_option.patch diff --git a/qca/aq-fw-download/Makefile b/qca/aq-fw-download/Makefile deleted file mode 100644 index 97270688b..000000000 --- a/qca/aq-fw-download/Makefile +++ /dev/null @@ -1,26 +0,0 @@ -include $(TOPDIR)/rules.mk - -PKG_NAME:=aq-fw-download -PKG_RELEASE:=$(AUTORELEASE) - -PKG_FLAGS:=nonshared - -include $(INCLUDE_DIR)/package.mk - -define Package/aq-fw-download - SECTION:=firmware - CATEGORY:=Firmware - DEPENDS:=@TARGET_ipq807x - TITLE:=Aquantia FW downloader utitlity -endef - -define Package/aq-fw-download/description - Aquantia FW downloader utitlity -endef - -define Package/aq-fw-download/install - $(INSTALL_DIR) $(1)/sbin - $(INSTALL_BIN) $(PKG_BUILD_DIR)/aq-fw-download $(1)/sbin/aq-fw-download -endef - -$(eval $(call BuildPackage,aq-fw-download)) diff --git a/qca/aq-fw-download/src/Makefile b/qca/aq-fw-download/src/Makefile deleted file mode 100644 index dc141be0e..000000000 --- a/qca/aq-fw-download/src/Makefile +++ /dev/null @@ -1,14 +0,0 @@ -ifndef CFLAGS -CFLAGS = -O2 -g -endif -INCLUDES=-Iinclude -Iinclude/registerMap \ - -Iinclude/registerMap/APPIA \ - -Iinclude/registerMap/HHD - -all: aq-fw-download - -%.o: %.c - $(CC) $(INCLUDES) $(CFLAGS) -c -o $@ $^ - -aq-fw-download: mdioBootLoadCLD.o src/AQ_PhyInterface.o src/AQ_API.o - $(CC) $(LDFLAGS) -o $@ $^ $(LIBS) diff --git a/qca/aq-fw-download/src/include/AQ_API.h b/qca/aq-fw-download/src/include/AQ_API.h deleted file mode 100644 index 9a0b4c20a..000000000 --- a/qca/aq-fw-download/src/include/AQ_API.h +++ /dev/null @@ -1,246 +0,0 @@ -/* -* Copyright (c) 2015, Aquantia -* -* Permission to use, copy, modify, and/or distribute this software for any -* purpose with or without fee is hereby granted, provided that the above -* copyright notice and this permission notice appear in all copies. -* -* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -*/ - -/*! \file - This file contains the AQ_API function and datatype declarations. */ - - -#ifndef AQ_API_TOKEN -#define AQ_API_TOKEN - -#include - -#include "AQ_User.h" -#include "AQ_ReturnCodes.h" - -/******************************************************************* - General -*******************************************************************/ - -#ifdef __cplusplus -extern "C" { -#endif - -/*! This typedef defines the bool datatype which takes the values -true and false.*/ -typedef enum {False = 0, True = 1} AQ_boolean; - - -/*@}*/ - - -/******************************************************************* - Device Identity -*******************************************************************/ - -/*! \defgroup deviceIdentity Device Identity -All AQ_API functions accept a parameter identifying the target PHY that -should be acted upon. */ -/*@{*/ - - -/*! This enumeration is used to describe the different types of - Aquantia PHY.*/ -typedef enum -{ - /*! 1/2/4-port package, 40nm architechture.*/ - AQ_DEVICE_APPIA, - /*! 1/2/4-port package, 28nm architechture.*/ - AQ_DEVICE_HHD -} AQ_API_Device; - -/*! This structure is used to specify a particular Aquantia PHY port - within the system.*/ -typedef struct -{ - /*! The type of Aquantia PHY*/ - AQ_API_Device device; - /*! Uniquely identifies the port within the system. AQ_Port must be - defined to whatever data type is suitable for the platform. - AQ_API functions will never do anything with PHY_ID other than - pass it down to the platform's PHY register read/write - functions.*/ - AQ_Port PHY_ID; -} AQ_API_Port; - -/*@}*/ - - -/*! This function boot-loads the instruction and data memory (IRAM and - DRAM) of a set of Aquantia PHYs from a .cld format image file (the - same image file used to burn the FLASH). During boot-load of each - Aquantia PHY, the processor is halted, and after programming is - complete the processor is released. Note that calling this - function leaves the daisy-chain disabled to prevent RAM over- - write. To exit MDIO boot-load mode, use the function - AQ_API_EnableDaisyChain. - Unlike most of the other functions in this API, this function can - operate on a group of PHYs simultaneously. This is referred to as - gang-loading. To facilitate this, this function takes as - parameters 3 parallel arrays: PHY_IDs, provisioningAddresses, and - resultCodes. The length of these arrays must be identical, and is - specified by the num_PHY_IDs parameter. - In order to check the integrity of the boot-load operation, a - CRC-16 value is calculated over the IRAM and DRAM. After the image - has been loaded, this value is directly compared against each - PHY's Mailbox CRC-16 in 1E.0201. - The value of register 1E.C441 must be the same for all the boot- - loaded PHYs. This will be checked before the boot-load is - performed, and if a non-uniform value is read from any of the - PHYs, the function will fail before any writes are performed. - A separate result code is returned for each of the boot-loaded - PHYs, in the OUT parameter, resultCodes. - Individual Port Return codes: - AQ_RET_BOOTLOAD_PROVADDR_OOR: The specified provisioning address - was outside of the permitted range. - AQ_RET_BOOTLOAD_NONUNIFORM_REGVALS: The values of the register(s) - that must be uniform across the ports being bootloaded were not - uniform. - AQ_RET_BOOTLOAD_CRC_MISMATCH: The image was completely loaded into - memory, but the after the port exited bootload the running - checksum that was read from the uP memory mailbox was not the - expected value. This indicates that the memory has potentially - been corrupted, and the PHY should be reset before trying the - bootload again. - Overall Return codes (the return value from the function call): - AQ_RET_OK: all ports were successfully bootloaded. - AQ_RET_ERROR: One or more ports were not successfully bootloaded. - */ -AQ_Retcode AQ_API_WriteBootLoadImage -( - /*! An array identifying the target PHY ports.*/ - AQ_API_Port** ports, - /*! The length of the arrays ports, provisioningAddresses, and - resultCodes. These are parallel arrays, and must all be of the - same length.*/ - unsigned int numPorts, - /*! The provisioning addresses of each of the PHYs specified in - ports. This can range from 0 through 47, and is also known as - the daisy-chain address or the hop-count. If the PHYs are - connected to a FLASH using the daisy-chain, this is the distance - from the PHY to the FLASH, and is used to identify customized - provisioning for each PHY from the provisioning data within the - image. Otherwise, it is an arbitrary number. The length of this - array must match the length of ports.*/ - unsigned int* provisioningAddresses, - /*! OUT: The result code indicating success or failure of boot- - loading each of the PHYs specified in ports.*/ - AQ_Retcode* resultCodes, - /*! A pointer to the size of the image (in bytes) that is being - loaded into the Aquantia PHY.*/ - uint32_t* imageSizePointer, - /*! The image being loaded into the Aquantia PHY. This is the same - regardless of whether the target is internal RAM or FLASH.*/ - uint8_t* image, - /*! The 5-bit address to be used during the gang-loading operation. - During the boot-loading process, each of the PHYs specified in - ports will be changed such that they are addressed on the MDIO - bus at gangloadAddress. This allows all the PHYs to be loaded - simultaneously. Before returning, each PHY will be moved back to - its original MDIO address. If ports contains only a single - element, callers will probably want to use the PHY's original - MDIO address for this parameter.*/ - uint8_t gangload_MDIO_address, - /*! The address of the PHYs while in gangload mode. This is - ultimately some combination of the system address and the - gangload MDIO address, specified by gangload_MDIO_address. For - most platforms, gangload_MDIO_address and gangload_PHY_ID should - have the same value.*/ - AQ_API_Port* gangloadPort -); - -/*! This function boot-loads the instruction and data memory (IRAM and - DRAM) of a set of Aquantia PHYs from a .cld format image file (the - same image file used to burn the FLASH), as well as a separately - provided provisioning table image file.The provisioning table - image allows additional provisioning to be provided, beyond what - is built in to the .cld image. If provTableSizePointer or - provTableImage are NULL, this function behaves like - AQ_API_WriteBootLoadImage. - Aside from the additional provisioing table, this function behaves - exactly the same as AQ_API_WriteBootLoadImage. For additional - documentation and information on return codes, refer to - AQ_API_WriteBootLoadImage. - Individual Port Return codes (same as AQ_API_WriteBootLoadImage, - plus): - AQ_RET_BOOTLOAD_PROVTABLE_TOO_LARGE: The supplied provisioning - table image does not fit within the alloted space.*/ -AQ_Retcode AQ_API_WriteBootLoadImageWithProvTable -( - /*! An array identifying the target PHY ports.*/ - AQ_API_Port** ports, - /*! The length of the arrays ports, provisioningAddresses, and - resultCodes. These are parallel arrays, and must all be of the - same length.*/ - unsigned int numPorts, - /*! The provisioning addresses of each of the PHYs specified in - ports. This can range from 0 through 47, and is also known as - the daisy-chain address or the hop-count. If the PHYs are - connected to a FLASH using the daisy-chain, this is the distance - from the PHY to the FLASH, and is used to identify customized - provisioning for each PHY from the provisioning data within the - image. Otherwise, it is an arbitrary number. The length of this - array must match the length of ports.*/ - unsigned int* provisioningAddresses, - /*! OUT: The result code indicating success or failure of boot- - loading each of the PHYs specified in ports.*/ - AQ_Retcode* resultCodes, - /*! A pointer to the size of the image (in bytes) that is being - loaded into the Aquantia PHY.*/ - uint32_t* imageSizePointer, - /*! The image being loaded into the Aquantia PHY. This is the same - regardless of whether the target is internal RAM or FLASH.*/ - uint8_t* image, - /*! The 5-bit address to be used during the gang-loading operation. - During the boot-loading process, each of the PHYs specified in - ports will be changed such that they are addressed on the MDIO - bus at gangloadAddress. This allows all the PHYs to be loaded - simultaneously. Before returning, each PHY will be moved back to - its original MDIO address. If ports contains only a single - element, callers will probably want to use the PHY's original - MDIO address for this parameter.*/ - uint8_t gangload_MDIO_address, - /*! The address of the PHYs while in gangload mode. This is - ultimately some combination of the system address and the - gangload MDIO address, specified by gangload_MDIO_address. For - most platforms, gangload_MDIO_address and gangload_PHY_ID should - have the same value.*/ - AQ_API_Port* gangloadPort, - /*! A pointer to the size of the provTableImage (in bytes) that is - being loaded into the Aquantia PHY.*/ - uint32_t* provTableSizePointer, - /*! The additional provisioning table image being loaded into the - Aquantia PHY.*/ - uint8_t* provTableImage -); - -/*! Calling this function disables boot-loading and enables the daisy- - chain. This would typically be called after using MDIO boot- - loading on a daisy-chain enabled PHY. Re-enabling the daisy-chain - after performing an MDIO bootload will cause the PHY to reboot - from FLASH.*/ -AQ_Retcode AQ_API_EnableDaisyChain -( - /*! The target PHY port.*/ - AQ_API_Port* port -); - - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/qca/aq-fw-download/src/include/AQ_PhyInterface.h b/qca/aq-fw-download/src/include/AQ_PhyInterface.h deleted file mode 100644 index 66eb817be..000000000 --- a/qca/aq-fw-download/src/include/AQ_PhyInterface.h +++ /dev/null @@ -1,171 +0,0 @@ -/* AQ_PhyInterface.h */ - -/*********************************************************************** -* Copyright (c) 2015, Aquantia -* -* Permission to use, copy, modify, and/or distribute this software for any -* purpose with or without fee is hereby granted, provided that the above -* copyright notice and this permission notice appear in all copies. -* -* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -* -* Description: -* -* Declares the base PHY register read and write functions that are -* called by the API functions. The platform integrator must provide -* the implementation of these routines. -* -***********************************************************************/ - - -/*! \file - * Declares the base PHY register read and write functions that are - * called by the API functions. The platform integrator must provide - * the implementation of these routines. */ - - -#ifndef AQ_PHY_INTERFACE_TOKEN -#define AQ_PHY_INTERFACE_TOKEN - - -#include "AQ_API.h" -#include "AQ_User.h" - - -#ifdef __cplusplus -extern "C" { -#endif - - -/******************************************************************* - MDIO Access Functions -*******************************************************************/ - -/*! \defgroup mdioAccessFunctions MDIO Access Functions -The MDIO access functions are required by the API to access the register space -of each Aquantia PHY deployed in a system. The body of these functions needs to -be written by the system designer, as the method of accessing the PHY will -be unique to the target system. They are designed to be generic read and -write access functions, as the MDIO addressing scheme relies on each -MMD to maintain a 16 bit address pointer that determines the register where -the next read or write is coming from. Consequently, various levels of -optimization of the MDIO interface are possible: from re-writing the MMD -address pointer on every transaction, to storing shadow copies of the MMD -address pointers and only updating the MMD address pointer as necessary. -Thus these functions leave the MDIO optimization to the system engineer. - */ -/*@{*/ - - -/*! Provides generic synchronous PHY register write functionality. It is the - * responsibility of the system designer to provide the specific MDIO address - * pointer updates, etc. in order to accomplish this write operation. - * It will be assumed that the write has been completed by the time this - * function returns.*/ -void AQ_API_MDIO_Write -( - /*! Uniquely identifies the port within the system. AQ_Port must be - * defined to a whatever data type is suitable for the platform.*/ - AQ_Port PHY_ID, - /*! The address of the MMD within the target PHY. */ - unsigned int MMD, - /*! The 16-bit address of the PHY register being written. */ - unsigned int address, - /*! The 16-bits of data to write to the specified PHY register. */ - unsigned int data -); - -/*! Provides generic synchronous PHY register read functionality. It is the - * responsibility of the system designer to provide the specific MDIO address - * pointer updates, etc. in order to accomplish this read operation.*/ -unsigned int AQ_API_MDIO_Read -( - /*! Uniquely identifies the port within the system. AQ_Port must be - * defined to a whatever data type is suitable for the platform.*/ - AQ_Port PHY_ID, - /*! The address of the MMD within the target PHY. */ - unsigned int MMD, - /*! The 16-bit address of the PHY register being read. */ - unsigned int address -); - -#ifdef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE - -/*! Provides generic asynchronous/buffered PHY register write functionality. - * It is the responsibility of the system designer to provide the specific - * MDIO address pointer updates, etc. in order to accomplish this write - * operation. The write need not necessarily have been completed by the time - * this function returns. All register reads and writes to a particular PHY_ID - * that are requested by calling AQ_API_MDIO_BlockWrite or AQ_API_MDIO_BlockRead - * MUST be performed in the order that the calls are made. */ -void AQ_API_MDIO_BlockWrite -( - /*! Uniquely identifies the port within the system. AQ_Port must be - * defined to a whatever data type is suitable for the platform.*/ - AQ_Port PHY_ID, - /*! The address of the MMD within the target PHY. */ - unsigned int MMD, - /*! The 16-bit address of the PHY register being written. */ - unsigned int address, - /*! The 16-bits of data to write to the specified PHY register. */ - unsigned int data -); - -/*! Provides generic asynchronous/buffered PHY register read functionality. - * It is the responsibility of the system designer to provide the specific - * MDIO address pointer updates, etc. in order to accomplish this read - * operation. All register reads and writes to a particular PHY_ID that - * are requested by calling AQ_API_MDIO_BlockWrite or AQ_API_MDIO_BlockRead - * MUST be performed in the order that the calls are made. The register value - * may subsequently be fetched by calling AQ_API_MDIO_BlockOperationExecute.*/ -void AQ_API_MDIO_BlockRead -( - /*! Uniquely identifies the port within the system. AQ_Port must be - * defined to a whatever data type is suitable for the platform.*/ - AQ_Port PHY_ID, - /*! The address of the MMD within the target PHY. */ - unsigned int MMD, - /*! The 16-bit address of the PHY register being read. */ - unsigned int address -); - -/* Retrieve the results of all PHY register reads to PHY_ID previously - * requested via calls to AQ_API_MDIO_BlockRead. The read and write - * operations previously performed by calls to AQ_API_MDIO_BlockRead and - * AQ_API_MDIO_BlockRead must have all been completed by the time this - * function returns, in the order that the calls were performed. The - * return value is an array representing the fetched results of all - * pending calls to AQ_API_MDIO_BlockRead, in the order that the calls - * were performed. Callers should track the number of pending block - * reads to determine the size of the returned array. */ -unsigned int * AQ_API_MDIO_BlockOperationExecute -( - /*! Uniquely identifies the port within the system. AQ_Port must be - * defined to a whatever data type is suitable for the platform.*/ - AQ_Port PHY_ID -); - -/* Returns the maximum number of asynchronous/buffered PHY register - * read/write operations. Callers will call AQ_API_MDIO_BlockOperationExecute - * before issuing additional calls to AQ_API_MDIO_BlockWrite or - * AQ_API_MDIO_BlockRead to avoid a buffer overflow. */ -unsigned int AQ_API_MDIO_MaxBlockOperations -( -); - -#endif - -/*@}*/ - - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/qca/aq-fw-download/src/include/AQ_PlatformRoutines.h b/qca/aq-fw-download/src/include/AQ_PlatformRoutines.h deleted file mode 100644 index 9a16d6408..000000000 --- a/qca/aq-fw-download/src/include/AQ_PlatformRoutines.h +++ /dev/null @@ -1,71 +0,0 @@ -/*AQ_PlatformRoutines.h*/ - -/************************************************************************************ -* Copyright (c) 2015, Aquantia -* -* Permission to use, copy, modify, and/or distribute this software for any -* purpose with or without fee is hereby granted, provided that the above -* copyright notice and this permission notice appear in all copies. -* -* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -* -* Description: -* -* Declares the platform interface functions that will be called by AQ_API -* functions. The platform integrator must provide the implementation of -* these functions. -* -************************************************************************************/ - -/*! \file - * Declares the platform interface functions that will be called by AQ_API - * functions. The platform integrator must provide the implementation of - * these functions. */ - - -#ifndef AQ_PHY_PLATFORMROUTINES_TOKEN -#define AQ_PHY_PLATFORMROUTINES_TOKEN - -#include - -#include "AQ_API.h" -#include "AQ_User.h" -#include "AQ_ReturnCodes.h" - -#ifdef __cplusplus -extern "C" { -#endif - - -/******************************************************************* - Time Delay -*******************************************************************/ - -/*! \defgroup delay Time Delay - @{ -*/ - -/*! Returns after at least milliseconds have elapsed. This must be implemented - * in a platform-approriate way. AQ_API functions will call this function to - * block for the specified period of time. If necessary, PHY register reads - * may be performed on port to busy-wait. */ -void AQ_API_Wait -( - uint32_t milliseconds, /*!< The delay in milliseconds */ - AQ_API_Port* port /*!< The PHY to use if delay reads are necessary*/ -); - -/*@}*/ - - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/qca/aq-fw-download/src/include/AQ_RegMacro.h b/qca/aq-fw-download/src/include/AQ_RegMacro.h deleted file mode 100644 index 8dcca522b..000000000 --- a/qca/aq-fw-download/src/include/AQ_RegMacro.h +++ /dev/null @@ -1,323 +0,0 @@ -/* Copyright (c) 2015, Aquantia -* -* Permission to use, copy, modify, and/or distribute this software for any -* purpose with or without fee is hereby granted, provided that the above -* copyright notice and this permission notice appear in all copies. -* -* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -*/ -/*! \file - This file contains macros for accessing the AQ PHYs' registers - using the device-specific register map data structures and definitions. -*/ - -#ifndef AQ_REG_MACRO_TOKEN -#define AQ_REG_MACRO_TOKEN - -#include "AQ_PhyInterface.h" - - -#define AQ_API_ReadRegister(id,reg,wd) AQ_API_ReadRegister_DeviceRestricted(APPIA_HHD,id,reg,wd) - -#define AQ_API_ReadRegister_DeviceRestricted(devices,id,reg,wd) AQ_API_ReadRegister_Devs_ ## devices(id,reg,wd) - -#define AQ_API_ReadRegister_Devs_APPIA(id,reg,wd) \ - ((port->device == AQ_DEVICE_APPIA) ? AQ_API_MDIO_Read (id,reg ## _APPIA_mmdAddress,(reg ## _APPIA_baseRegisterAddress + wd)) : \ - (0)) - -#define AQ_API_ReadRegister_Devs_HHD(id,reg,wd) \ - ((port->device == AQ_DEVICE_HHD) ? AQ_API_MDIO_Read (id,reg ## _HHD_mmdAddress,(reg ## _HHD_baseRegisterAddress + wd)) : \ - (0)) - -#define AQ_API_ReadRegister_Devs_APPIA_HHD(id,reg,wd) \ - ((port->device == AQ_DEVICE_HHD) ? AQ_API_MDIO_Read (id,reg ## _HHD_mmdAddress,(reg ## _HHD_baseRegisterAddress + wd)) : \ - ((port->device == AQ_DEVICE_APPIA) ? AQ_API_MDIO_Read (id,reg ## _APPIA_mmdAddress,(reg ## _APPIA_baseRegisterAddress + wd)) : \ - (0))) - -#define AQ_API_ReadRegister_Devs_HHD_APPIA(id,reg,wd) AQ_API_ReadRegister_Devs_APPIA_HHD(id,reg,wd) - - -#define AQ_API_WriteRegister(id,reg,wd,value) AQ_API_WriteRegister_DeviceRestricted(APPIA_HHD,id,reg,wd,value) - -#define AQ_API_WriteRegister_DeviceRestricted(devices,id,reg,wd,value) AQ_API_WriteRegister_Devs_ ## devices(id,reg,wd,value) - -#define AQ_API_WriteRegister_Devs_APPIA(id,reg,wd,value) \ - ((port->device == AQ_DEVICE_APPIA) ? AQ_API_MDIO_Write (id,reg ## _APPIA_mmdAddress,(reg ## _APPIA_baseRegisterAddress + wd),value) : \ - ((void)0)) - -#define AQ_API_WriteRegister_Devs_HHD(id,reg,wd,value) \ - ((port->device == AQ_DEVICE_HHD) ? AQ_API_MDIO_Write (id,reg ## _HHD_mmdAddress,(reg ## _HHD_baseRegisterAddress + wd),value) : \ - ((void)0)) - -#define AQ_API_WriteRegister_Devs_APPIA_HHD(id,reg,wd,value) \ - ((port->device == AQ_DEVICE_HHD) ? AQ_API_MDIO_Write (id,reg ## _HHD_mmdAddress,(reg ## _HHD_baseRegisterAddress + wd),value) : \ - ((port->device == AQ_DEVICE_APPIA) ? AQ_API_MDIO_Write (id,reg ## _APPIA_mmdAddress,(reg ## _APPIA_baseRegisterAddress + wd),value) : \ - ((void)0))) - -#define AQ_API_WriteRegister_Devs_HHD_APPIA(id,reg,wd,value) AQ_API_WriteRegister_Devs_APPIA_HHD(id,reg,wd,value) - - -#ifdef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE - -#define AQ_API_BlockReadRegister(id,reg,wd) AQ_API_BlockReadRegister_DeviceRestricted(APPIA_HHD,id,reg,wd) - -#define AQ_API_BlockReadRegister_DeviceRestricted(devices,id,reg,wd) AQ_API_BlockReadRegister_Devs_ ## devices(id,reg,wd) - -#define AQ_API_BlockReadRegister_Devs_APPIA(id,reg,wd) \ - ((port->device == AQ_DEVICE_APPIA) ? AQ_API_MDIO_BlockRead (id,reg ## _APPIA_mmdAddress,(reg ## _APPIA_baseRegisterAddress + wd)) : \ - ((void)0)) - -#define AQ_API_BlockReadRegister_Devs_HHD(id,reg,wd) \ - ((port->device == AQ_DEVICE_HHD) ? AQ_API_MDIO_BlockRead (id,reg ## _HHD_mmdAddress,(reg ## _HHD_baseRegisterAddress + wd)) : \ - ((void)0)) - -#define AQ_API_BlockReadRegister_Devs_APPIA_HHD(id,reg,wd) \ - ((port->device == AQ_DEVICE_HHD) ? AQ_API_MDIO_BlockRead (id,reg ## _HHD_mmdAddress,(reg ## _HHD_baseRegisterAddress + wd)) : \ - ((port->device == AQ_DEVICE_APPIA) ? AQ_API_MDIO_BlockRead (id,reg ## _APPIA_mmdAddress,(reg ## _APPIA_baseRegisterAddress + wd)) : \ - ((void)0))) - -#define AQ_API_BlockReadRegister_Devs_HHD_APPIA(id,reg,wd) AQ_API_BlockReadRegister_Devs_APPIA_HHD(id,reg,wd) - - -#define AQ_API_BlockWriteRegister(id,reg,wd,value) AQ_API_BlockWriteRegister_DeviceRestricted(APPIA_HHD,id,reg,wd,value) - -#define AQ_API_BlockWriteRegister_DeviceRestricted(devices,id,reg,wd,value) AQ_API_BlockWriteRegister_Devs_ ## devices(id,reg,wd,value) - -#define AQ_API_BlockWriteRegister_Devs_APPIA(id,reg,wd,value) \ - ((port->device == AQ_DEVICE_APPIA) ? AQ_API_MDIO_BlockWrite (id,reg ## _APPIA_mmdAddress,(reg ## _APPIA_baseRegisterAddress + wd),value) : \ - ((void)0)) - -#define AQ_API_BlockWriteRegister_Devs_HHD(id,reg,wd,value) \ - ((port->device == AQ_DEVICE_HHD) ? AQ_API_MDIO_BlockWrite (id,reg ## _HHD_mmdAddress,(reg ## _HHD_baseRegisterAddress + wd),value) : \ - ((void)0)) - -#define AQ_API_BlockWriteRegister_Devs_APPIA_HHD(id,reg,wd,value) \ - ((port->device == AQ_DEVICE_HHD) ? AQ_API_MDIO_BlockWrite (id,reg ## _HHD_mmdAddress,(reg ## _HHD_baseRegisterAddress + wd),value) : \ - ((port->device == AQ_DEVICE_APPIA) ? AQ_API_MDIO_BlockWrite (id,reg ## _APPIA_mmdAddress,(reg ## _APPIA_baseRegisterAddress + wd),value) : \ - ((void)0))) - -#define AQ_API_BlockWriteRegister_Devs_HHD_APPIA(id,reg,wd,value) AQ_API_BlockWriteRegister_Devs_APPIA_HHD(id,reg,wd,value) - - -#endif - -#define AQ_API_Variable(reg) AQ_API_Variable_DeviceRestricted(APPIA_HHD,reg) - -#define AQ_API_Variable_DeviceRestricted(devices,reg) AQ_API_Variable_Devs_ ## devices(reg) - -#define AQ_API_Variable_Devs_APPIA(reg) uint8_t _local ## reg ## _space[ sizeof(reg ## _BiggestVersion) ];\ - reg ## _APPIA* _local ## reg ## _APPIA = (reg ## _APPIA*) _local ## reg ## _space; \ - -#define AQ_API_Variable_Devs_HHD(reg) uint8_t _local ## reg ## _space[ sizeof(reg ## _BiggestVersion) ];\ - reg ## _HHD* _local ## reg ## _HHD = (reg ## _HHD*) _local ## reg ## _space; \ - -#define AQ_API_Variable_Devs_APPIA_HHD(reg) uint8_t _local ## reg ## _space[ sizeof(reg ## _BiggestVersion) ];\ - reg ## _APPIA* _local ## reg ## _APPIA = (reg ## _APPIA*) _local ## reg ## _space; \ - reg ## _HHD* _local ## reg ## _HHD = (reg ## _HHD*) _local ## reg ## _space; \ - -#define AQ_API_Variable_Devs_HHD_APPIA(reg) AQ_API_Variable_Devs_APPIA_HHD(reg) - - -#define AQ_API_DeclareLocalStruct(reg,localvar) AQ_API_DeclareLocalStruct_DeviceRestricted(APPIA_HHD,reg,localvar) - -#define AQ_API_DeclareLocalStruct_DeviceRestricted(devices,reg,localvar) AQ_API_DeclareLocalStruct_Devs_ ## devices(reg,localvar) - -#define AQ_API_DeclareLocalStruct_Devs_APPIA(reg,localvar) uint8_t localvar ## _space[ sizeof(reg ## _BiggestVersion) ];\ - reg ## _APPIA* localvar ## _APPIA = (reg ## _APPIA*) localvar ## _space; \ - -#define AQ_API_DeclareLocalStruct_Devs_HHD(reg,localvar) uint8_t localvar ## _space[ sizeof(reg ## _BiggestVersion) ];\ - reg ## _HHD* localvar ## _HHD = (reg ## _HHD*) localvar ## _space; \ - -#define AQ_API_DeclareLocalStruct_Devs_APPIA_HHD(reg,localvar) uint8_t localvar ## _space[ sizeof(reg ## _BiggestVersion) ];\ - reg ## _APPIA* localvar ## _APPIA = (reg ## _APPIA*) localvar ## _space; \ - reg ## _HHD* localvar ## _HHD = (reg ## _HHD*) localvar ## _space; \ - -#define AQ_API_DeclareLocalStruct_Devs_HHD_APPIA(reg,localvar) AQ_API_DeclareLocalStruct_Devs_APPIA_HHD(reg,localvar) - - -#define AQ_API_Set(id,reg,field,value) AQ_API_Set_DeviceRestricted(APPIA_HHD,id,reg,field,value) - -#define AQ_API_Set_DeviceRestricted(devices,id,reg,field,value) AQ_API_Set_Devs_ ## devices(id,reg,field,value) - -#define AQ_API_Set_Devs_APPIA(id,reg,field,value) { \ - switch (port->device) { \ - case AQ_DEVICE_APPIA: \ - _local ## reg ## _APPIA->word_ ## reg ## _APPIA_ ## field = AQ_API_ReadRegister_Devs_APPIA(id,reg,reg ## _APPIA_ ## field); \ - if (_local ## reg ## _APPIA->bits_ ## reg ## _APPIA_ ## field.field != value) \ - { \ - _local ## reg ## _APPIA->bits_ ## reg ## _APPIA_ ## field.field = value; \ - AQ_API_WriteRegister_Devs_APPIA(id,reg,reg ## _APPIA_ ## field,_local ## reg ## _APPIA->word_ ## reg ## _APPIA_ ## field); \ - } \ - break; \ - default: break; \ - } \ -} - -#define AQ_API_Set_Devs_HHD(id,reg,field,value) { \ - switch (port->device) { \ - case AQ_DEVICE_HHD: \ - _local ## reg ## _HHD->word_ ## reg ## _HHD_ ## field = AQ_API_ReadRegister_Devs_HHD(id,reg,reg ## _HHD_ ## field); \ - if (_local ## reg ## _HHD->bits_ ## reg ## _HHD_ ## field.field != value) \ - { \ - _local ## reg ## _HHD->bits_ ## reg ## _HHD_ ## field.field = value; \ - AQ_API_WriteRegister_Devs_HHD(id,reg,reg ## _HHD_ ## field,_local ## reg ## _HHD->word_ ## reg ## _HHD_ ## field); \ - } \ - break; \ - default: break; \ - } \ -} - -#define AQ_API_Set_Devs_APPIA_HHD(id,reg,field,value) { \ - switch (port->device) { \ - case AQ_DEVICE_APPIA: \ - _local ## reg ## _APPIA->word_ ## reg ## _APPIA_ ## field = AQ_API_ReadRegister_Devs_APPIA_HHD(id,reg,reg ## _APPIA_ ## field); \ - if (_local ## reg ## _APPIA->bits_ ## reg ## _APPIA_ ## field.field != value) \ - { \ - _local ## reg ## _APPIA->bits_ ## reg ## _APPIA_ ## field.field = value; \ - AQ_API_WriteRegister_Devs_APPIA_HHD(id,reg,reg ## _APPIA_ ## field,_local ## reg ## _APPIA->word_ ## reg ## _APPIA_ ## field); \ - } \ - break; \ - case AQ_DEVICE_HHD: \ - _local ## reg ## _HHD->word_ ## reg ## _HHD_ ## field = AQ_API_ReadRegister_Devs_APPIA_HHD(id,reg,reg ## _HHD_ ## field); \ - if (_local ## reg ## _HHD->bits_ ## reg ## _HHD_ ## field.field != value) \ - { \ - _local ## reg ## _HHD->bits_ ## reg ## _HHD_ ## field.field = value; \ - AQ_API_WriteRegister_Devs_APPIA_HHD(id,reg,reg ## _HHD_ ## field,_local ## reg ## _HHD->word_ ## reg ## _HHD_ ## field); \ - } \ - break; \ - default: break; \ - } \ -} - -#define AQ_API_Set_Devs_HHD_APPIA(id,reg,field,value) AQ_API_Set_Devs_APPIA_HHD(id,reg,field,value) - - -#define AQ_API_Get(id,reg,field,value) AQ_API_Get_DeviceRestricted(APPIA_HHD,id,reg,field,value) - -#define AQ_API_Get_DeviceRestricted(devices,id,reg,field,value) AQ_API_Get_Devs_ ## devices(id,reg,field,value) - -#define AQ_API_Get_Devs_APPIA(id,reg,field,value) { \ - switch (port->device) { \ - case AQ_DEVICE_APPIA: \ - _local ## reg ## _APPIA->word_ ## reg ## _APPIA_ ## field = AQ_API_ReadRegister_Devs_APPIA(id,reg,reg ## _APPIA_ ## field); \ - value = _local ## reg ## _APPIA->bits_ ## reg ## _APPIA_ ## field.field; \ - break; \ - default: value = 0; break; \ - } \ -} - -#define AQ_API_Get_Devs_HHD(id,reg,field,value) { \ - switch (port->device) { \ - case AQ_DEVICE_HHD: \ - _local ## reg ## _HHD->word_ ## reg ## _HHD_ ## field = AQ_API_ReadRegister_Devs_HHD(id,reg,reg ## _HHD_ ## field); \ - value = _local ## reg ## _HHD->bits_ ## reg ## _HHD_ ## field.field; \ - break; \ - default: value = 0; break; \ - } \ -} - -#define AQ_API_Get_Devs_APPIA_HHD(id,reg,field,value) { \ - switch (port->device) { \ - case AQ_DEVICE_APPIA: \ - _local ## reg ## _APPIA->word_ ## reg ## _APPIA_ ## field = AQ_API_ReadRegister_Devs_APPIA_HHD(id,reg,reg ## _APPIA_ ## field); \ - value = _local ## reg ## _APPIA->bits_ ## reg ## _APPIA_ ## field.field; \ - break; \ - case AQ_DEVICE_HHD: \ - _local ## reg ## _HHD->word_ ## reg ## _HHD_ ## field = AQ_API_ReadRegister_Devs_APPIA_HHD(id,reg,reg ## _HHD_ ## field); \ - value = _local ## reg ## _HHD->bits_ ## reg ## _HHD_ ## field.field; \ - break; \ - default: value = 0; break; \ - } \ -} - -#define AQ_API_Get_Devs_HHD_APPIA(id,reg,field,value) AQ_API_Get_Devs_APPIA_HHD(id,reg,field,value) - - -#define AQ_API_BitfieldOfLocalStruct(reg,localvar,field) AQ_API_BitfieldOfLocalStruct_DeviceRestricted(APPIA_HHD,reg,localvar,field) - -#define AQ_API_BitfieldOfLocalStruct_DeviceRestricted(devices,reg,localvar,field) AQ_API_BitfieldOfLocalStruct_Devs_ ## devices(reg,localvar,field) - -#define AQ_API_BitfieldOfLocalStruct_Devs_APPIA(reg,localvar,field) \ - ((port->device == AQ_DEVICE_APPIA) ? ((localvar ## _APPIA)->bits_ ## reg ## _APPIA ## _ ## field.field) : \ - (0)) - -#define AQ_API_BitfieldOfLocalStruct_Devs_HHD(reg,localvar,field) \ - ((port->device == AQ_DEVICE_HHD) ? ((localvar ## _HHD)->bits_ ## reg ## _HHD ## _ ## field.field) : \ - (0)) - -#define AQ_API_BitfieldOfLocalStruct_Devs_APPIA_HHD(reg,localvar,field) \ - ((port->device == AQ_DEVICE_HHD) ? ((localvar ## _HHD)->bits_ ## reg ## _HHD ## _ ## field.field) : \ - ((port->device == AQ_DEVICE_APPIA) ? ((localvar ## _APPIA)->bits_ ## reg ## _APPIA ## _ ## field.field) : \ - (0))) - -#define AQ_API_BitfieldOfLocalStruct_Devs_HHD_APPIA(reg,localvar,field) AQ_API_BitfieldOfLocalStruct_Devs_APPIA_HHD(reg,localvar,field) - - -#define AQ_API_AssignBitfieldOfLocalStruct(reg,localvar,field,value) AQ_API_AssignBitfieldOfLocalStruct_DeviceRestricted(APPIA_HHD,reg,localvar,field,value) - -#define AQ_API_AssignBitfieldOfLocalStruct_DeviceRestricted(devices,reg,localvar,field,value) AQ_API_AssignBitfieldOfLocalStruct_Devs_ ## devices(reg,localvar,field,value) - -#define AQ_API_AssignBitfieldOfLocalStruct_Devs_APPIA(reg,localvar,field,value) \ - ((port->device == AQ_DEVICE_APPIA) ? ((localvar ## _APPIA)->bits_ ## reg ## _APPIA ## _ ## field.field = value) : \ - (0)) - -#define AQ_API_AssignBitfieldOfLocalStruct_Devs_HHD(reg,localvar,field,value) \ - ((port->device == AQ_DEVICE_HHD) ? ((localvar ## _HHD)->bits_ ## reg ## _HHD ## _ ## field.field = value) : \ - (0)) - -#define AQ_API_AssignBitfieldOfLocalStruct_Devs_APPIA_HHD(reg,localvar,field,value) \ - ((port->device == AQ_DEVICE_HHD) ? ((localvar ## _HHD)->bits_ ## reg ## _HHD ## _ ## field.field = value) : \ - ((port->device == AQ_DEVICE_APPIA) ? ((localvar ## _APPIA)->bits_ ## reg ## _APPIA ## _ ## field.field = value) : \ - (0))) - -#define AQ_API_AssignBitfieldOfLocalStruct_Devs_HHD_APPIA(reg,localvar,field,value) AQ_API_AssignBitfieldOfLocalStruct_Devs_APPIA_HHD(reg,localvar,field,value) - - -#define AQ_API_WordOfLocalStruct(localvar,wd) AQ_API_WordOfLocalStruct_DeviceRestricted(APPIA_HHD,localvar,wd) - -#define AQ_API_WordOfLocalStruct_DeviceRestricted(devices,localvar,wd) AQ_API_WordOfLocalStruct_Devs_ ## devices(localvar,wd) - -#define AQ_API_WordOfLocalStruct_Devs_APPIA(localvar,wd) \ - ((port->device == AQ_DEVICE_APPIA) ? ((localvar ## _APPIA)->u ## wd.word_ ## wd) : \ - (0)) - -#define AQ_API_WordOfLocalStruct_Devs_HHD(localvar,wd) \ - ((port->device == AQ_DEVICE_HHD) ? ((localvar ## _HHD)->u ## wd.word_ ## wd) : \ - (0)) - -#define AQ_API_WordOfLocalStruct_Devs_APPIA_HHD(localvar,wd) \ - ((port->device == AQ_DEVICE_HHD) ? ((localvar ## _HHD)->u ## wd.word_ ## wd) : \ - ((port->device == AQ_DEVICE_APPIA) ? ((localvar ## _APPIA)->u ## wd.word_ ## wd) : \ - (0))) - -#define AQ_API_WordOfLocalStruct_Devs_HHD_APPIA(localvar,wd) AQ_API_WordOfLocalStruct_Devs_APPIA_HHD(localvar,wd) - - -#define AQ_API_AssignWordOfLocalStruct(localvar,wd,value) AQ_API_AssignWordOfLocalStruct_DeviceRestricted(APPIA_HHD,localvar,wd,value) - -#define AQ_API_AssignWordOfLocalStruct_DeviceRestricted(devices,localvar,wd,value) AQ_API_AssignWordOfLocalStruct_Devs_ ## devices(localvar,wd,value) - -#define AQ_API_AssignWordOfLocalStruct_Devs_APPIA(localvar,wd,value) \ - ((port->device == AQ_DEVICE_APPIA) ? ((localvar ## _APPIA)->u ## wd.word_ ## wd = value) : \ - (0)) - -#define AQ_API_AssignWordOfLocalStruct_Devs_HHD(localvar,wd,value) \ - ((port->device == AQ_DEVICE_HHD) ? ((localvar ## _HHD)->u ## wd.word_ ## wd = value) : \ - (0)) - -#define AQ_API_AssignWordOfLocalStruct_Devs_APPIA_HHD(localvar,wd,value) \ - ((port->device == AQ_DEVICE_HHD) ? ((localvar ## _HHD)->u ## wd.word_ ## wd = value) : \ - ((port->device == AQ_DEVICE_APPIA) ? ((localvar ## _APPIA)->u ## wd.word_ ## wd = value) : \ - (0))) - -#define AQ_API_AssignWordOfLocalStruct_Devs_HHD_APPIA(localvar,wd,value) AQ_API_AssignWordOfLocalStruct_Devs_APPIA_HHD(localvar,wd,value) - - -#endif - diff --git a/qca/aq-fw-download/src/include/AQ_ReturnCodes.h b/qca/aq-fw-download/src/include/AQ_ReturnCodes.h deleted file mode 100644 index bff083b03..000000000 --- a/qca/aq-fw-download/src/include/AQ_ReturnCodes.h +++ /dev/null @@ -1,113 +0,0 @@ -/* AQ_ReturnCodes.h */ - -/************************************************************************************ -* Copyright (c) 2015, Aquantia -* -* Permission to use, copy, modify, and/or distribute this software for any -* purpose with or without fee is hereby granted, provided that the above -* copyright notice and this permission notice appear in all copies. -* -* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -* -* Description: -* -* This file defines the AQ_API functions' integral return codes. -* -* -************************************************************************************/ - -/*! \file - This file defines the AQ_API functions' integral return codes. -*/ - -#ifndef AQ_RETURNCODES_TOKEN -#define AQ_RETURNCODES_TOKEN - - -/*! \defgroup ReturnCodes - @{ -*/ - -/*! Most AQ_API functions return AQ_Retcode to report success or failure. - * The values used are defined as preprocessor symbols in AQ_ReturnCodes.h. - * Callers should prefer to test the return values by equivalence to these - * symbols, rather than using the integer values directly, as these may - * not be stable across releases. The set of possible return codes that may - * be returned by a particular API function can be found in the function's - * documentation, as well as information on how to interpret each of the - * possible return codes. */ -typedef unsigned int AQ_Retcode; - -/*! \defgroup Success - @{ */ -#define AQ_RET_OK 0 -/*@}*/ - - -/*! \defgroup GeneralErrors - @{ */ -#define AQ_RET_ERROR 100 -#define AQ_RET_UP_BUSY_TIMEOUT 101 -/*@}*/ - -/*! \defgroup FunctionSpecificResults - @{ */ -#define AQ_RET_FLASH_READY 200 -#define AQ_RET_FLASH_READINESS_TIMEOUT 204 - -#define AQ_RET_FLASHINTF_READY 201 -#define AQ_RET_FLASHINTF_NOTREADY 202 -#define AQ_RET_FLASHINTF_READINESS_TIMEOUT 203 - -#define AQ_RET_FLASH_TYPE_UNKNOWN 205 -#define AQ_RET_FLASH_TYPE_BAD 206 - -#define AQ_RET_FLASH_IMAGE_CORRUPT 207 -#define AQ_RET_FLASH_IMAGE_TOO_LARGE 208 -#define AQ_RET_FLASH_IMAGE_MISMATCH 209 - -#define AQ_RET_FLASH_PAGE_SIZE_CHANGED 210 - -#define AQ_RET_BOOTLOAD_PROVADDR_OOR 211 -#define AQ_RET_BOOTLOAD_NONUNIFORM_REGVALS 212 -#define AQ_RET_BOOTLOAD_CRC_MISMATCH 213 -#define AQ_RET_BOOTLOAD_PROVTABLE_TOO_LARGE 228 - -#define AQ_RET_LOOPBACK_BAD_ENTRY_STATE 214 - -#define AQ_RET_DEBUGTRACE_FREEZE_TIMEOUT 215 -#define AQ_RET_DEBUGTRACE_UNFREEZE_TIMEOUT 216 - -#define AQ_RET_CABLEDIAG_ALREADY_RUNNING 217 -#define AQ_RET_CABLEDIAG_STILL_RUNNING 218 -#define AQ_RET_CABLEDIAG_BAD_PAIRSTATUS 219 -#define AQ_RET_CABLEDIAG_RESULTS_ALREDY_COLLECTED 220 -#define AQ_RET_CABLEDIAG_BAD_NUM_SAMPLES 221 -#define AQ_RET_CABLEDIAG_REPORTEDPAIR_MISMATCH 222 -#define AQ_RET_CABLEDIAG_REPORTEDPAIR_OOR 223 -#define AQ_RET_CABLEDIAG_STARTED_PAIR_B 224 -#define AQ_RET_CABLEDIAG_STARTED_PAIR_C 225 -#define AQ_RET_CABLEDIAG_STARTED_PAIR_D 226 -#define AQ_RET_CABLEDIAG_TXENABLE_MISMATCH 227 - -#define AQ_RET_SERDESEYE_BAD_SERDES_MODE 229 -#define AQ_RET_SERDESEYE_BAD_MEAS_COUNT 230 -#define AQ_RET_SERDESEYE_MEAS_TIMEOUT 231 -#define AQ_RET_SERDESEYE_LANE_OOR 232 -#define AQ_RET_SERDESEYE_COORD_OOR 233 - -#define AQ_RET_PIFMAILBOX_ERROR 234 -#define AQ_RET_PIFMAILBOX_TIMEOUT 235 - -#define AQ_RET_SEC_TABLE_INDEX_OOR 236 -/*@}*/ - -/*@}*/ - -#endif diff --git a/qca/aq-fw-download/src/include/AQ_User.h b/qca/aq-fw-download/src/include/AQ_User.h deleted file mode 100644 index c7526a7cb..000000000 --- a/qca/aq-fw-download/src/include/AQ_User.h +++ /dev/null @@ -1,97 +0,0 @@ -/*AQ_User.h*/ - -/************************************************************************************ -* Copyright (c) 2015, Aquantia -* -* Permission to use, copy, modify, and/or distribute this software for any -* purpose with or without fee is hereby granted, provided that the above -* copyright notice and this permission notice appear in all copies. -* -* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -* -* Description: -* -* This file contains preprocessor symbol definitions and type definitions -* for the platform-integrator controlled compile-time AQ_API options. -* -************************************************************************************/ - -/*! \file - This file contains preprocessor symbol definitions and type definitions - for the platform-integrator controlled compile-time AQ_API options. -*/ - -#ifndef AQ_USER_TOKEN -#define AQ_USER_TOKEN - -/*! \defgroup User User Definitions -This module contains the definitions used to configure AQ_API behavior as desired. */ -/*@{*/ - - -/*! Specify the proper data type for AQ_Port. This will depend on the - * platform-specific implementation of the PHY register read/write functions.*/ -typedef unsigned int AQ_Port; - - -/*! If defined, AQ_API functions will print various error and info messages - * to stdout. If not, nothing will be printed and AQ_API.c will NOT include - * stdio.h. */ -#define AQ_VERBOSE - - -/*! If defined, the PHY interface supports block (asynchronous) read/write - * operation. If AQ_PHY_SUPPORTS_BLOCK_READ_WRITE is defined, then - * the API will call the block-operation functions and so implementations - * for each must be provided. If AQ_PHY_SUPPORTS_BLOCK_READ_WRITE is not - * defined, they will not be called, and need not be implemented. */ -#undef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE - - -/*! If defined, time.h exists, and so the associated functions wil be used to - * compute the elapsed time spent in a polling loop, to ensure that the - * maximum time-out period will not be exceeded. If not defined, then - * AQ_MDIO_READS_PER_SECOND will be used to calculate the minimum possible - * elapsed time. */ -#define AQ_TIME_T_EXISTS - - -/*! The maximum number of synchronous PHY register reads that can be performed - * per second. A worst case number can be derived as follows: - * - * AQ_MDIO_READS_PER_SECOND = MDIO Clock Frequency / 64 - * - * If using MDIO preamble suppression, multiply this number by 2 - * - * For instance, if a 5MHz MDIO clock is being used without preamble supression - * AQ_MDIO_READS_PER_SECOND = 78125 - * - * If AQ_TIME_T_EXISTS is defined, this will be ignored and need not be - * defined. If AQ_TIME_T_EXISTS is not defined, this must be defined. */ -#define AQ_MDIO_READS_PER_SECOND 78125 - - -/*! If defined, after writing to one of the registers that can trigger a - * processor-intensive MDIO operation, AQ_API functions will poll the - * the "processor intensive MDIO operation in progress" bit and wait for it - * to be zero before proceeding. */ -#define AQ_ENABLE_UP_BUSY_CHECKS - - -/*! If defined, the register map header files containing reverse-packed - * structs will be included. If not, the register map header files containing - * non-reverse-packed structs will be included. The proper choice is typically - * a function of the endianness of the platform; on big-endian systems the - * reverse-packed structs should be used, and on little-endian systems the - * non-reverse-packed structs should be used. */ -/*#define AQ_REVERSED_BITFIELD_ORDERING*/ - -/*@}*/ -#endif - diff --git a/qca/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers.h b/qca/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers.h deleted file mode 100644 index a9485f5a4..000000000 --- a/qca/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers.h +++ /dev/null @@ -1,5581 +0,0 @@ -/*! \file -* This file contains the data structures and doxygen comments -* for the Global Registers block. - */ - -/*! \addtogroup registerMap - @{ -*/ - -/*! \defgroup Global_registers Global Registers -* This module contains the data structures and doxygen comments -* for the Global Registers block. - */ -/*********************************************************************** -* Copyright (c) 2015, Aquantia -* -* Permission to use, copy, modify, and/or distribute this software for any -* purpose with or without fee is hereby granted, provided that the above -* copyright notice and this permission notice appear in all copies. -* -* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -* -* $Date: 2014/04/08 $ -* -* $Label: $ -* -* Description: -* -* This file contains the c header structures for the registers contained in the Global Registers block. -* -* The bit fields in this structure are from LSbit to MSbit -* -***********************************************************************/ - - -/*@{*/ -#ifndef AQ_APPIA_GLOBAL_REGS_HEADER -#define AQ_APPIA_GLOBAL_REGS_HEADER - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Standard Control 1: 1E.0000 */ -/* Global Standard Control 1: 1E.0000 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Standard Control 1 */ - union - { - struct - { - unsigned int reserved1 : 11; - /*! \brief 1E.0000.B R/WPD Low Power - AQ_GlobalStandardControl_1_APPIA.u0.bits_0.lowPower - - Provisionable Default = 0x0 - - 1 = Low-power mode - 0 = Normal operation - - - Notes: - A one written to this register causes the chip to enter low-power mode. This bit puts the entire chip in low-power mode, with only the MDIO and microprocessor functioning, and turns off the analog front-end: i.e. places it in high-impedance mode. Setting this bit also sets all of the Low Power bits in the other MMDs. */ - unsigned int lowPower : 1; /* 1E.0000.B R/WPD Provisionable Default = 0x0 */ - /* 1 = Low-power mode - 0 = Normal operation - */ - unsigned int reserved0 : 2; - /*! \brief 1E.0000.E R/WSC Hard Reset - AQ_GlobalStandardControl_1_APPIA.u0.bits_0.hardReset - - Default = 0x0 - - 1 = Global hard reset - 0 = Normal operation - - - Notes: - Setting this bit initiates a global hard reset, equivalent to pulling the reset pin low. This is a level sensitive pin that connects into the power-on reset generation circuitry to initiate a complete power-on reset. */ - unsigned int hardReset : 1; /* 1E.0000.E R/WSC Default = 0x0 */ - /* 1 = Global hard reset - 0 = Normal operation - */ - /*! \brief 1E.0000.F R/WSC Soft Reset - AQ_GlobalStandardControl_1_APPIA.u0.bits_0.softReset - - Default = 0x1 - - 1 = Global soft reset - 0 = Normal operation - - - Notes: - Setting this bit initiates a global soft reset on all of the digital logic, including the microprocessor. Upon completion of the reset sequence, this bit is set back to 0. */ - unsigned int softReset : 1; /* 1E.0000.F R/WSC Default = 0x1 */ - /* 1 = Global soft reset - 0 = Normal operation - */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalStandardControl_1_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Standard Device Identifier: 1E.0002 */ -/* Global Standard Device Identifier: 1E.0002 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Standard Device Identifier */ - union - { - struct - { - /*! \brief 1E.0002.F:0 RO Device ID MSW [1F:10] - AQ_GlobalStandardDeviceIdentifier_APPIA.u0.bits_0.deviceIdMSW - - - - Bits 31 - 16 of Device ID - */ - unsigned int deviceIdMSW : 16; /* 1E.0002.F:0 RO */ - /* Bits 31 - 16 of Device ID */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Standard Device Identifier */ - union - { - struct - { - /*! \brief 1E.0003.F:0 RO Device ID LSW [F:0] - AQ_GlobalStandardDeviceIdentifier_APPIA.u1.bits_1.deviceIdLSW - - - - Bits 15 - 0 of Device ID - */ - unsigned int deviceIdLSW : 16; /* 1E.0003.F:0 RO */ - /* Bits 15 - 0 of Device ID */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_GlobalStandardDeviceIdentifier_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Standard Devices in Package: 1E.0005 */ -/* Global Standard Devices in Package: 1E.0005 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Standard Devices in Package */ - union - { - struct - { - /*! \brief 1E.0005.0 ROS Clause 22 Registers Present - AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.clause_22RegistersPresent - - Default = 0x0 - - 1 = Clause 22 registers are present in package - 0 = Clause 22 registers are not present in package - - Notes: - This is always set to 0 in the PHY, as there are no Clause 22 registers in the device. */ - unsigned int clause_22RegistersPresent : 1; /* 1E.0005.0 ROS Default = 0x0 */ - /* 1 = Clause 22 registers are present in package - 0 = Clause 22 registers are not present in package */ - /*! \brief 1E.0005.1 ROS PMA Present - AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.pmaPresent - - Default = 0x1 - - 1 = PMA is present in package - 0 = PMA is not present - - Notes: - This is always set to 1 as there is PMA functionality in the PHY. */ - unsigned int pmaPresent : 1; /* 1E.0005.1 ROS Default = 0x1 */ - /* 1 = PMA is present in package - 0 = PMA is not present */ - /*! \brief 1E.0005.2 ROS WIS Present - AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.wisPresent - - Default = 0x0 - - 1 = WIS is present in package - 0 = WIS is not present in package - - Notes: - This is always set to 0, as there is no WIS functionality in the PHY. */ - unsigned int wisPresent : 1; /* 1E.0005.2 ROS Default = 0x0 */ - /* 1 = WIS is present in package - 0 = WIS is not present in package */ - /*! \brief 1E.0005.3 ROS PCS Present - AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.pcsPresent - - Default = 0x1 - - 1 = PCS is present in package - 0 = PCS is not present in package - - Notes: - This is always set to 1 as there is PCS functionality in the PHY. */ - unsigned int pcsPresent : 1; /* 1E.0005.3 ROS Default = 0x1 */ - /* 1 = PCS is present in package - 0 = PCS is not present in package */ - /*! \brief 1E.0005.4 ROS PHY XS Present - AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.phyXS_Present - - Default = 0x1 - - 1 = PHY XS is present in package - 0 = PHY XS is not present in package - - Notes: - This is always set to 1 as there is a PHY XS interface in the PHY. */ - unsigned int phyXS_Present : 1; /* 1E.0005.4 ROS Default = 0x1 */ - /* 1 = PHY XS is present in package - 0 = PHY XS is not present in package */ - /*! \brief 1E.0005.5 ROS DTE XS Present - AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.dteXsPresent - - Default = 0x0 - - 1 = DTE XS is present in package - 0 = DTE XS is not present in package - - - Notes: - This is always set to 0, as there is no DTE XAUI interface in the PHY. */ - unsigned int dteXsPresent : 1; /* 1E.0005.5 ROS Default = 0x0 */ - /* 1 = DTE XS is present in package - 0 = DTE XS is not present in package - */ - /*! \brief 1E.0005.6 ROS TC Present - AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.tcPresent - - Default = 0x0 - - 1 = TC is present in package - 0 = TC is not present in package - - Notes: - This is always set to 0, as there is no TC functionality in the PHY. */ - unsigned int tcPresent : 1; /* 1E.0005.6 ROS Default = 0x0 */ - /* 1 = TC is present in package - 0 = TC is not present in package */ - /*! \brief 1E.0005.7 ROS Autonegotiation Present - AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.autonegotiationPresent - - Default = 0x1 - - 1 = Autonegotiation is present in package - 0 = Autonegotiation is not present in package - - Notes: - This is always set to 1, as there is Autonegotiation in the PHY. */ - unsigned int autonegotiationPresent : 1; /* 1E.0005.7 ROS Default = 0x1 */ - /* 1 = Autonegotiation is present in package - 0 = Autonegotiation is not present in package */ - unsigned int reserved0 : 8; - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalStandardDevicesInPackage_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Standard Vendor Devices in Package: 1E.0006 */ -/* Global Standard Vendor Devices in Package: 1E.0006 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Standard Vendor Devices in Package */ - union - { - struct - { - unsigned int reserved0 : 13; - /*! \brief 1E.0006.D ROS Clause 22 Extension Present - AQ_GlobalStandardVendorDevicesInPackage_APPIA.u0.bits_0.clause_22ExtensionPresent - - Default = 0x1 - - 1 = Clause 22 Extension is present in package - 0 = Clause 22 Extension is not present in package - - Notes: - This is always set to 1 as the PHY utilizes this device for the GbE registers. */ - unsigned int clause_22ExtensionPresent : 1; /* 1E.0006.D ROS Default = 0x1 */ - /* 1 = Clause 22 Extension is present in package - 0 = Clause 22 Extension is not present in package */ - /*! \brief 1E.0006.E ROS Vendor Specific Device #1 Present - AQ_GlobalStandardVendorDevicesInPackage_APPIA.u0.bits_0.vendorSpecificDevice_1Present - - Default = 0x1 - - 1 = Device #1 is present in package - 0 = Device #1 is not present in package - - Notes: - This is always set to 1 as the PHY utilizes this device for the global control registers. */ - unsigned int vendorSpecificDevice_1Present : 1; /* 1E.0006.E ROS Default = 0x1 */ - /* 1 = Device #1 is present in package - 0 = Device #1 is not present in package */ - /*! \brief 1E.0006.F ROS Vendor Specific Device #2 Present - AQ_GlobalStandardVendorDevicesInPackage_APPIA.u0.bits_0.vendorSpecificDevice_2Present - - Default = 0x1 - - 1 = Device #2 is present in package - 0 = Device #2 is not present in package - - Notes: - This is always set to 1 as the PHY utilizes this device for the DSP PMA registers. */ - unsigned int vendorSpecificDevice_2Present : 1; /* 1E.0006.F ROS Default = 0x1 */ - /* 1 = Device #2 is present in package - 0 = Device #2 is not present in package */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalStandardVendorDevicesInPackage_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Standard Status 2: 1E.0008 */ -/* Global Standard Status 2: 1E.0008 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Standard Status 2 */ - union - { - struct - { - unsigned int reserved0 : 14; - /*! \brief 1E.0008.F:E ROS Device Present [1:0] - AQ_GlobalStandardStatus_2_APPIA.u0.bits_0.devicePresent - - Default = 0x2 - - [F:E] - 0x3 = No device at this address - 0x2 = Device present at this address - 0x1 = No device at this address - 0x0 = No device at this address - - Notes: - This field is always set to 0x2, as the Global MMD resides here in the PHY. */ - unsigned int devicePresent : 2; /* 1E.0008.F:E ROS Default = 0x2 */ - /* [F:E] - 0x3 = No device at this address - 0x2 = Device present at this address - 0x1 = No device at this address - 0x0 = No device at this address */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalStandardStatus_2_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Standard Package Identifier: 1E.000E */ -/* Global Standard Package Identifier: 1E.000E */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Standard Package Identifier */ - union - { - struct - { - /*! \brief 1E.000E.F:0 RO Package ID MSW [1F:10] - AQ_GlobalStandardPackageIdentifier_APPIA.u0.bits_0.packageIdMSW - - - - Bits 31- 16 of Package ID - */ - unsigned int packageIdMSW : 16; /* 1E.000E.F:0 RO */ - /* Bits 31- 16 of Package ID */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Standard Package Identifier */ - union - { - struct - { - /*! \brief 1E.000F.F:0 RO Package ID LSW [F:0] - AQ_GlobalStandardPackageIdentifier_APPIA.u1.bits_1.packageIdLSW - - - - Bits 15 - 0 of Package ID - */ - unsigned int packageIdLSW : 16; /* 1E.000F.F:0 RO */ - /* Bits 15 - 0 of Package ID */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_GlobalStandardPackageIdentifier_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Firmware ID: 1E.0020 */ -/* Global Firmware ID: 1E.0020 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Firmware ID */ - union - { - struct - { - /*! \brief 1E.0020.7:0 RO Firmware Minor Revision Number [7:0] - AQ_GlobalFirmwareID_APPIA.u0.bits_0.firmwareMinorRevisionNumber - - - - [7:0] = Minor revision number - - Notes: - - - The lower six bits of major and minor firmware revision are exchanged in autonegotiation when the PHYID message is sent. */ - unsigned int firmwareMinorRevisionNumber : 8; /* 1E.0020.7:0 RO */ - /* [7:0] = Minor revision number */ - /*! \brief 1E.0020.F:8 RO Firmware Major Revision Number [7:0] - AQ_GlobalFirmwareID_APPIA.u0.bits_0.firmwareMajorRevisionNumber - - - - [F:8] = Major revision number - - Notes: - - - The lower six bits of major and minor firmware revision are exchanged in autonegotiation when the PHYID message is sent. */ - unsigned int firmwareMajorRevisionNumber : 8; /* 1E.0020.F:8 RO */ - /* [F:8] = Major revision number */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalFirmwareID_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Chip Identification: 1E.0021 */ -/* Global Chip Identification: 1E.0021 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Chip Identification */ - union - { - struct - { - /*! \brief 1E.0021.F:0 RO Chip Identification [F:0] - AQ_GlobalChipIdentification_APPIA.u0.bits_0.chipIdentification - - - - Hardware Chip ID - - Notes: - This value is a hard-coded chip ID */ - unsigned int chipIdentification : 16; /* 1E.0021.F:0 RO */ - /* Hardware Chip ID */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalChipIdentification_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Chip Revision: 1E.0022 */ -/* Global Chip Revision: 1E.0022 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Chip Revision */ - union - { - struct - { - /*! \brief 1E.0022.F:0 RO Chip Revision [F:0] - AQ_GlobalChipRevision_APPIA.u0.bits_0.chipRevision - - - - Hardware Chip Revision - - Notes: - This value is a hard-coded chip revision */ - unsigned int chipRevision : 16; /* 1E.0022.F:0 RO */ - /* Hardware Chip Revision */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalChipRevision_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global NVR Interface: 1E.0100 */ -/* Global NVR Interface: 1E.0100 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global NVR Interface */ - union - { - struct - { - /*! \brief 1E.0100.7:0 R/W NVR Opcode [7:0] - AQ_GlobalNvrInterface_APPIA.u0.bits_0.nvrOpcode - - Default = 0x03 - - NVR instruction opcode - - */ - unsigned int nvrOpcode : 8; /* 1E.0100.7:0 R/W Default = 0x03 */ - /* NVR instruction opcode - */ - /*! \brief 1E.0100.8 RO NVR Busy - AQ_GlobalNvrInterface_APPIA.u0.bits_0.nvrBusy - - - - 1 = NVR is busy - 0 = NVR is ready - - - Notes: - When set to 1, the NVR is busy. A new NVR operation should not occur until this bit is 0. If the NVR clock is greater than 64/63 of the MDIO clock, this bit never needs to be polled when operating over the MDIO. */ - unsigned int nvrBusy : 1; /* 1E.0100.8 RO */ - /* 1 = NVR is busy - 0 = NVR is ready - */ - unsigned int reserved1 : 1; - /*! \brief 1E.0100.A R/W NVR Burst - AQ_GlobalNvrInterface_APPIA.u0.bits_0.nvrBurst - - Default = 0x0 - - 0 = Single read or write operation of up to 4 bytes - 1 = Burst operation - - - Notes: - When this bit is set, the operation is a burst operation where more than 32-bits is read from the NVR or written to the NVR. This bit should be set to one until the last burst in the read or write operation, when it should be set to zero. It operates by gating the SPI clock, and not restarting it until new data is ready to be written, or the previous contents have been read. Each burst of data requires the NVR Execute Operation bit to be set to initiate the next phase. */ - unsigned int nvrBurst : 1; /* 1E.0100.A R/W Default = 0x0 */ - /* 0 = Single read or write operation of up to 4 bytes - 1 = Burst operation - */ - unsigned int reserved0 : 1; - /*! \brief 1E.0100.C R/WSC Reset NVR CRC - AQ_GlobalNvrInterface_APPIA.u0.bits_0.resetNvrCrc - - Default = 0x0 - - 1 = Reset NVR Mailbox CRC calculation register - - - Notes: - To prevent an erroneous answer, this bit should not be set at the same time the See NVR Operation Valid bit is set. */ - unsigned int resetNvrCrc : 1; /* 1E.0100.C R/WSC Default = 0x0 */ - /* 1 = Reset NVR Mailbox CRC calculation register - */ - /*! \brief 1E.0100.D R/W Freeze NVR CRC - AQ_GlobalNvrInterface_APPIA.u0.bits_0.freezeNvrCrc - - Default = 0x0 - - 1 = Freeze NVR Mailbox CRC calculation register - - - Notes: - To prevent an erroneous answer, this bit should not be set at the same time the See NVR Operation Valid bit is set. */ - unsigned int freezeNvrCrc : 1; /* 1E.0100.D R/W Default = 0x0 */ - /* 1 = Freeze NVR Mailbox CRC calculation register - */ - /*! \brief 1E.0100.E R/W NVR Write Mode - AQ_GlobalNvrInterface_APPIA.u0.bits_0.nvrWriteMode - - Default = 0x0 - - 1 = Write to NVR - 0 = Read from NVR - - */ - unsigned int nvrWriteMode : 1; /* 1E.0100.E R/W Default = 0x0 */ - /* 1 = Write to NVR - 0 = Read from NVR - */ - /*! \brief 1E.0100.F R/WSC NVR Execute Operation - AQ_GlobalNvrInterface_APPIA.u0.bits_0.nvrExecuteOperation - - Default = 0x0 - - 1 = Start NVR Operation - - - Notes: - When set to 1, the NVR operation will begin. Ensure that the uP is stalled using the See MCP Run Stall bit to ensure no NVR contention. */ - unsigned int nvrExecuteOperation : 1; /* 1E.0100.F R/WSC Default = 0x0 */ - /* 1 = Start NVR Operation - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global NVR Interface */ - union - { - struct - { - /*! \brief 1E.0101.F:0 RO NVR Mailbox CRC [F:0] - AQ_GlobalNvrInterface_APPIA.u1.bits_1.nvrMailboxCrc - - - - The running CRC-16 of everything passing through the NVR interface - - - Notes: - The CRC-16 over all data written or read through the NVR interface. The CRC-16 is calculated by dividing the data by: - x^16 + x^12 + x^5 + 1 */ - unsigned int nvrMailboxCrc : 16; /* 1E.0101.F:0 RO */ - /* The running CRC-16 of everything passing through the NVR interface - */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global NVR Interface */ - union - { - struct - { - /*! \brief 1E.0102.7:0 R/W NVR Address MSW [17:10] - AQ_GlobalNvrInterface_APPIA.u2.bits_2.nvrAddressMSW - - Default = 0x00 - - NVR address MSW bits [17:10] - - - Notes: - The address of where to read and write from in the NVR. This is self-incrementing and will automatically increment after each read or write operation. The increment amount is based on the data length (i.e. increments by 4 if the data length is 4 bytes) */ - unsigned int nvrAddressMSW : 8; /* 1E.0102.7:0 R/W Default = 0x00 */ - /* NVR address MSW bits [17:10] - */ - unsigned int reserved0 : 8; - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global NVR Interface */ - union - { - struct - { - /*! \brief 1E.0103.F:0 R/W NVR Address LSW [F:0] - AQ_GlobalNvrInterface_APPIA.u3.bits_3.nvrAddressLSW - - Default = 0x0000 - - NVR address LSW bits [F:0] - - - Notes: - The address of where to read and write from in the NVR. This is self-incrementing and will automatically increment after each read or write operation. */ - unsigned int nvrAddressLSW : 16; /* 1E.0103.F:0 R/W Default = 0x0000 */ - /* NVR address LSW bits [F:0] - */ - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of Global NVR Interface */ - union - { - struct - { - /*! \brief 1E.0104.F:0 R/W NVR Data MSW [1F:10] - AQ_GlobalNvrInterface_APPIA.u4.bits_4.nvrDataMSW - - Default = 0x0000 - - NVR data MSW bits [1F:10] - - - Notes: - Data is stored and read-out from these registers in little-endian format for operations such as FLASH device ID, and for programming the processor. - - For instance the 64K Atmel device code reads out as two bytes 0x651F into the LSW register, whereas the datasheet indicates that 1F is the first byte read, followed by 65 as the second byte. - - To burst read and write these 4 bytes in the correct order (where DD is written to address x), they should be stored as: - - AA BB in the MSW - CC DD in the LSW. */ - unsigned int nvrDataMSW : 16; /* 1E.0104.F:0 R/W Default = 0x0000 */ - /* NVR data MSW bits [1F:10] - */ - } bits_4; - uint16_t word_4; - } u4; - /*! \brief Union for bit and word level access of word 5 of Global NVR Interface */ - union - { - struct - { - /*! \brief 1E.0105.F:0 R/W NVR Data LSW [F:0] - AQ_GlobalNvrInterface_APPIA.u5.bits_5.nvrDataLSW - - Default = 0x0000 - - NVR data LSW bits [F:0] - - - Notes: - Data is stored and read-out from these registers in little-endian format for operations such as FLASH device ID, and for programming the processor. - - For instance the 64K Atmel device code reads out as two bytes 0x651F into the LSW register, whereas the datasheet indicates that 1F is the first byte read, followed by 65 as the second byte. - To burst read and write these 4 bytes in the correct order (where DD is written to address x), they should be stored as: - - AA BB in the MSW - CC DD in the LSW. */ - unsigned int nvrDataLSW : 16; /* 1E.0105.F:0 R/W Default = 0x0000 */ - /* NVR data LSW bits [F:0] - */ - } bits_5; - uint16_t word_5; - } u5; -} AQ_GlobalNvrInterface_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Mailbox Interface: 1E.0200 */ -/* Global Mailbox Interface: 1E.0200 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Mailbox Interface */ - union - { - struct - { - unsigned int reserved2 : 8; - /*! \brief 1E.0200.8 RO uP Mailbox Busy - AQ_GlobalMailboxInterface_APPIA.u0.bits_0.upMailboxBusy - - - - 1 = uP mailbox busy - 0 = uP mailbox ready - - - Notes: - In general the uP will respond within a few processor cycles to any PIF slave request, much faster than the MDIO. If the busy is asserted over multiple MDIO polling cycles, then a H/W error may have occured and a Global S/W reset or uP reset is required. */ - unsigned int upMailboxBusy : 1; /* 1E.0200.8 RO */ - /* 1 = uP mailbox busy - 0 = uP mailbox ready - */ - unsigned int reserved1 : 3; - /*! \brief 1E.0200.C R/WSC Reset uP Mailbox CRC - AQ_GlobalMailboxInterface_APPIA.u0.bits_0.resetUpMailboxCrc - - Default = 0x0 - - 1 = Reset uP mailbox CRC calculation register - - */ - unsigned int resetUpMailboxCrc : 1; /* 1E.0200.C R/WSC Default = 0x0 */ - /* 1 = Reset uP mailbox CRC calculation register - */ - unsigned int reserved0 : 1; - /*! \brief 1E.0200.E R/W uP Mailbox Write Mode - AQ_GlobalMailboxInterface_APPIA.u0.bits_0.upMailboxWriteMode - - Default = 0x0 - - 1 = Write - 0 = Read - - - Notes: - Mailbox direction */ - unsigned int upMailboxWriteMode : 1; /* 1E.0200.E R/W Default = 0x0 */ - /* 1 = Write - 0 = Read - */ - /*! \brief 1E.0200.F R/WSC uP Mailbox Execute Operation - AQ_GlobalMailboxInterface_APPIA.u0.bits_0.upMailboxExecuteOperation - - Default = 0x0 - - 1 = Start of mailbox Operation - - - Notes: - Indicates mailbox is loaded and ready */ - unsigned int upMailboxExecuteOperation : 1; /* 1E.0200.F R/WSC Default = 0x0 */ - /* 1 = Start of mailbox Operation - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Mailbox Interface */ - union - { - struct - { - /*! \brief 1E.0201.F:0 RO uP Mailbox CRC [F:0] - AQ_GlobalMailboxInterface_APPIA.u1.bits_1.upMailboxCrc - - - - The running CRC-16 of everything passing through the mailbox interface - - */ - unsigned int upMailboxCrc : 16; /* 1E.0201.F:0 RO */ - /* The running CRC-16 of everything passing through the mailbox interface - */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global Mailbox Interface */ - union - { - struct - { - /*! \brief 1E.0202.F:0 R/W uP Mailbox Address MSW [1F:10] - AQ_GlobalMailboxInterface_APPIA.u2.bits_2.upMailboxAddressMSW - - Default = 0x0000 - - uP Mailbox MSW address - - - Notes: - The address of where to read and write from in the Microcontroller Mailbox. This is self-incrementing and automatically increments after each read and write operation.PHY */ - unsigned int upMailboxAddressMSW : 16; /* 1E.0202.F:0 R/W Default = 0x0000 */ - /* uP Mailbox MSW address - */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global Mailbox Interface */ - union - { - struct - { - /*! \brief 1E.0203.1:0 RO uP Mailbox Address LSW Don't Care [1:0] - AQ_GlobalMailboxInterface_APPIA.u3.bits_3.upMailboxAddressLSW_Don_tCare - - - - Least significant uP LSW Mailbox address bits [1:0] - - - Notes: - These bits are always set to 0 since each memory access is on a 4-byte boundary. */ - unsigned int upMailboxAddressLSW_Don_tCare : 2; /* 1E.0203.1:0 RO */ - /* Least significant uP LSW Mailbox address bits [1:0] - */ - /*! \brief 1E.0203.F:2 R/W uP Mailbox Address LSW [F:2] - AQ_GlobalMailboxInterface_APPIA.u3.bits_3.upMailboxAddressLSW - - Default = 0x0000 - - uP LSW Mailbox address [F:2] - - - Notes: - The address of where to read and write from in the Microcontroller Mailbox. This is self-incrementing and automatically increments after each read and write operation.PHY */ - unsigned int upMailboxAddressLSW : 14; /* 1E.0203.F:2 R/W Default = 0x0000 */ - /* uP LSW Mailbox address [F:2] - */ - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of Global Mailbox Interface */ - union - { - struct - { - /*! \brief 1E.0204.F:0 R/W uP Mailbox Data MSW [1F:10] - AQ_GlobalMailboxInterface_APPIA.u4.bits_4.upMailboxDataMSW - - Default = 0x0000 - - uP Mailbox data MSW - - */ - unsigned int upMailboxDataMSW : 16; /* 1E.0204.F:0 R/W Default = 0x0000 */ - /* uP Mailbox data MSW - */ - } bits_4; - uint16_t word_4; - } u4; - /*! \brief Union for bit and word level access of word 5 of Global Mailbox Interface */ - union - { - struct - { - /*! \brief 1E.0205.F:0 R/W uP Mailbox Data LSW [F:0] - AQ_GlobalMailboxInterface_APPIA.u5.bits_5.upMailboxDataLSW - - Default = 0x0000 - - uP Mailbox data LSW - - */ - unsigned int upMailboxDataLSW : 16; /* 1E.0205.F:0 R/W Default = 0x0000 */ - /* uP Mailbox data LSW - */ - } bits_5; - uint16_t word_5; - } u5; -} AQ_GlobalMailboxInterface_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Microprocessor Scratch Pad: 1E.0300 */ -/* Global Microprocessor Scratch Pad: 1E.0300 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Microprocessor Scratch Pad */ - union - { - struct - { - /*! \brief 1E.0300.F:0 R/W Scratch Pad 1[F:0] - AQ_GlobalMicroprocessorScratchPad_APPIA.u0.bits_0.scratchPad_1 - - Default = 0x0000 - - General Purpose Scratch Pad1 - */ - unsigned int scratchPad_1 : 16; /* 1E.0300.F:0 R/W Default = 0x0000 */ - /* General Purpose Scratch Pad1 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Microprocessor Scratch Pad */ - union - { - struct - { - /*! \brief 1E.0301.F:0 R/W Scratch Pad 2 [F:0] - AQ_GlobalMicroprocessorScratchPad_APPIA.u1.bits_1.scratchPad_2 - - Default = 0x0000 - - General Purpose Scratch P - */ - unsigned int scratchPad_2 : 16; /* 1E.0301.F:0 R/W Default = 0x0000 */ - /* General Purpose Scratch P */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_GlobalMicroprocessorScratchPad_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Control: 1E.C000 */ -/* Global Control: 1E.C000 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Control */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Control */ - union - { - struct - { - /*! \brief 1E.C001.0 R/W uP Run Stall - AQ_GlobalControl_APPIA.u1.bits_1.upRunStall - - Default = 0x0 - - 1 = uP Run Stall - 0 = uP normal mode - - - Notes: - Deactivates the uP. The PIF slave bus for inbound requests will still be active. This bit is muliplexed with the "MDIO Boot Load" pin with the See uP Run Stall Override bit as the select. When the "MDIO Boot Load" pin is asserted, the uP will be in Run Stall mode after reset. */ - unsigned int upRunStall : 1; /* 1E.C001.0 R/W Default = 0x0 */ - /* 1 = uP Run Stall - 0 = uP normal mode - */ - unsigned int reserved1 : 5; - /*! \brief 1E.C001.6 R/W uP Run Stall Override - AQ_GlobalControl_APPIA.u1.bits_1.upRunStallOverride - - Default = 0x0 - - 0 = uP Run Stall from "MDIO Boot Load" pin. - 1 = uP Run Stall from See MCP Run Stall bit - - - Notes: - This bit selects the uP Run Stall from either the "MDIO Boot Load" pin or the See MCP Run Stall bit. */ - unsigned int upRunStallOverride : 1; /* 1E.C001.6 R/W Default = 0x0 */ - /* 0 = uP Run Stall from "MDIO Boot Load" pin. - 1 = uP Run Stall from See MCP Run Stall bit - */ - unsigned int reserved0 : 8; - /*! \brief 1E.C001.F R/W uP Reset - AQ_GlobalControl_APPIA.u1.bits_1.upReset - - Default = 0x0 - - 1 = Reset - - - Notes: - Resets the uP and the PIF master and slave bus. Will be active for a minimum of 100 microseconds. */ - unsigned int upReset : 1; /* 1E.C001.F R/W Default = 0x0 */ - /* 1 = Reset - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_GlobalControl_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Reset Control: 1E.C006 */ -/* Global Reset Control: 1E.C006 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Reset Control */ - union - { - struct - { - unsigned int reserved1 : 14; - /*! \brief 1E.C006.E R/WPD Global MMD Reset Disable - AQ_GlobalResetControl_APPIA.u0.bits_0.globalMMD_ResetDisable - - Provisionable Default = 0x0 - - 1 = Disable the S/W reset to the Global MMD registers - 0 = Enable the S/W reset to the Global MMD registers - - - Notes: - Setting this bit prevents a Global S/W reset or Global S/W reset from resetting the Global MMD registers */ - unsigned int globalMMD_ResetDisable : 1; /* 1E.C006.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Disable the S/W reset to the Global MMD registers - 0 = Enable the S/W reset to the Global MMD registers - */ - unsigned int reserved0 : 1; - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalResetControl_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Diagnostic Provisioning: 1E.C400 */ -/* Global Diagnostic Provisioning: 1E.C400 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Diagnostic Provisioning */ - union - { - struct - { - unsigned int reserved0 : 15; - /*! \brief 1E.C400.F R/WPD Enable Diagnostics - AQ_GlobalDiagnosticProvisioning_APPIA.u0.bits_0.enableDiagnostics - - Provisionable Default = 0x1 - - 1 = Chip performs diagnostics on power-up - */ - unsigned int enableDiagnostics : 1; /* 1E.C400.F R/WPD Provisionable Default = 0x1 */ - /* 1 = Chip performs diagnostics on power-up */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalDiagnosticProvisioning_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Thermal Provisioning: 1E.C420 */ -/* Global Thermal Provisioning: 1E.C420 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Thermal Provisioning */ - union - { - struct - { - /*! \brief 1E.C420.F:0 R/WPD Reserved 0 [F:0] - AQ_GlobalThermalProvisioning_APPIA.u0.bits_0.reserved_0 - - Provisionable Default = 0x0000 - - Internal reserved - do not modify - - */ - unsigned int reserved_0 : 16; /* 1E.C420.F:0 R/WPD Provisionable Default = 0x0000 */ - /* Internal reserved - do not modify - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Thermal Provisioning */ - union - { - struct - { - /*! \brief 1E.C421.F:0 R/WPD High Temp Failure Threshold [F:0] - AQ_GlobalThermalProvisioning_APPIA.u1.bits_1.highTempFailureThreshold - - Provisionable Default = 0x4600 - - [F:0] of high temperature failure threshold - - Notes: - 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 70 degreesC. - - In XENPAK mode, F/W will use the XENPAK register 1.A000 - 1.A001: instead of this register. - - NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. - High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ - unsigned int highTempFailureThreshold : 16; /* 1E.C421.F:0 R/WPD Provisionable Default = 0x4600 */ - /* [F:0] of high temperature failure threshold */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global Thermal Provisioning */ - union - { - struct - { - /*! \brief 1E.C422.F:0 R/WPD Low Temp Failure Threshold [F:0] - AQ_GlobalThermalProvisioning_APPIA.u2.bits_2.lowTempFailureThreshold - - Provisionable Default = 0x0000 - - [F:0] of low temperature failure threshold - - Notes: - 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 0 degreesC. - - In XENPAK mode, F/W will use the XENPAK register 1.A002 - 1.A003: instead of this register. - - NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. - High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ - unsigned int lowTempFailureThreshold : 16; /* 1E.C422.F:0 R/WPD Provisionable Default = 0x0000 */ - /* [F:0] of low temperature failure threshold */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global Thermal Provisioning */ - union - { - struct - { - /*! \brief 1E.C423.F:0 R/WPD High Temp Warning Threshold [F:0] - AQ_GlobalThermalProvisioning_APPIA.u3.bits_3.highTempWarningThreshold - - Provisionable Default = 0x3C00 - - [F:0] of high temperature warning threshold - - Notes: - 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD008. Default is 60 degreesC. - - In XENPAK mode, F/W will use the XENPAK register 1.A004 - 1.A005: instead of this register. - - NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. - High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ - unsigned int highTempWarningThreshold : 16; /* 1E.C423.F:0 R/WPD Provisionable Default = 0x3C00 */ - /* [F:0] of high temperature warning threshold */ - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of Global Thermal Provisioning */ - union - { - struct - { - /*! \brief 1E.C424.F:0 R/WPD Low Temp Warning Threshold [F:0] - AQ_GlobalThermalProvisioning_APPIA.u4.bits_4.lowTempWarningThreshold - - Provisionable Default = 0x0A00 - - [F:0] of low temperature warning threshold - - Notes: - 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 10 degreesC. - - In XENPAK mode, F/W will use the XENPAK register 1.A006 - 1.A007: instead of this register. - - NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. - High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ - unsigned int lowTempWarningThreshold : 16; /* 1E.C424.F:0 R/WPD Provisionable Default = 0x0A00 */ - /* [F:0] of low temperature warning threshold */ - } bits_4; - uint16_t word_4; - } u4; -} AQ_GlobalThermalProvisioning_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global LED Provisioning: 1E.C430 */ -/* Global LED Provisioning: 1E.C430 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global LED Provisioning */ - union - { - struct - { - /*! \brief 1E.C430.1:0 R/WPD LED #0 Activity Stretch [1:0] - AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0ActivityStretch - - Provisionable Default = 0x3 - - [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - - */ - unsigned int led_0ActivityStretch : 2; /* 1E.C430.1:0 R/WPD Provisionable Default = 0x3 */ - /* [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - */ - /*! \brief 1E.C430.2 R/WPD LED #0 Transmit Activity - AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0TransmitActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on transmit activity - - */ - unsigned int led_0TransmitActivity : 1; /* 1E.C430.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on transmit activity - */ - /*! \brief 1E.C430.3 R/WPD LED #0 Receive Activity - AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0ReceiveActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on receive activity - - */ - unsigned int led_0ReceiveActivity : 1; /* 1E.C430.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on receive activity - */ - /*! \brief 1E.C430.4 R/WPD LED #0 Connecting - AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0Connecting - - Provisionable Default = 0x0 - - 1 = LED is on when attempting to connect. - - */ - unsigned int led_0Connecting : 1; /* 1E.C430.4 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when attempting to connect. - */ - /*! \brief 1E.C430.5 R/WPD LED #0 100 Mb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0_100Mb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 100 Mb/s - - */ - unsigned int led_0_100Mb_sLinkEstablished : 1; /* 1E.C430.5 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 100 Mb/s - */ - /*! \brief 1E.C430.6 R/WPD LED #0 1 Gb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0_1Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 1 Gb/s - - */ - unsigned int led_0_1Gb_sLinkEstablished : 1; /* 1E.C430.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 1 Gb/s - */ - /*! \brief 1E.C430.7 R/WPD LED #0 10 Gb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0_10Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 10 Gb/s - - */ - unsigned int led_0_10Gb_sLinkEstablished : 1; /* 1E.C430.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 10 Gb/s - */ - /*! \brief 1E.C430.8 R/WPD LED #0 Manual Set - AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0ManualSet - - Provisionable Default = 0x0 - - 1 = LED On - - */ - unsigned int led_0ManualSet : 1; /* 1E.C430.8 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED On - */ - unsigned int reserved0 : 7; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global LED Provisioning */ - union - { - struct - { - /*! \brief 1E.C431.1:0 R/WPD LED #1 Activity Stretch [1:0] - AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1ActivityStretch - - Provisionable Default = 0x3 - - [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - - */ - unsigned int led_1ActivityStretch : 2; /* 1E.C431.1:0 R/WPD Provisionable Default = 0x3 */ - /* [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - */ - /*! \brief 1E.C431.2 R/WPD LED #1 Transmit Activity - AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1TransmitActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on transmit activity - - */ - unsigned int led_1TransmitActivity : 1; /* 1E.C431.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on transmit activity - */ - /*! \brief 1E.C431.3 R/WPD LED #1 Receive Activity - AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1ReceiveActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on receive activity - - */ - unsigned int led_1ReceiveActivity : 1; /* 1E.C431.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on receive activity - */ - /*! \brief 1E.C431.4 R/WPD LED #1 Connecting - AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1Connecting - - Provisionable Default = 0x0 - - 1 = LED is on when attempting to connect. - - */ - unsigned int led_1Connecting : 1; /* 1E.C431.4 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when attempting to connect. - */ - /*! \brief 1E.C431.5 R/WPD LED #1 100 Mb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1_100Mb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 100 Mb/s - - */ - unsigned int led_1_100Mb_sLinkEstablished : 1; /* 1E.C431.5 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 100 Mb/s - */ - /*! \brief 1E.C431.6 R/WPD LED #1 1 Gb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1_1Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 1 Gb/s - - */ - unsigned int led_1_1Gb_sLinkEstablished : 1; /* 1E.C431.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 1 Gb/s - */ - /*! \brief 1E.C431.7 R/WPD LED #1 10 Gb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1_10Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 10 Gb/s - - */ - unsigned int led_1_10Gb_sLinkEstablished : 1; /* 1E.C431.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 10 Gb/s - */ - /*! \brief 1E.C431.8 R/WPD LED #1 Manual Set - AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1ManualSet - - Provisionable Default = 0x0 - - 1 = LED On - - */ - unsigned int led_1ManualSet : 1; /* 1E.C431.8 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED On - */ - unsigned int reserved0 : 7; - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global LED Provisioning */ - union - { - struct - { - /*! \brief 1E.C432.1:0 R/WPD LED #2 Activity Stretch [1:0] - AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2ActivityStretch - - Provisionable Default = 0x3 - - [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - - */ - unsigned int led_2ActivityStretch : 2; /* 1E.C432.1:0 R/WPD Provisionable Default = 0x3 */ - /* [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - */ - /*! \brief 1E.C432.2 R/WPD LED #2 Transmit Activity - AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2TransmitActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on transmit activity - - */ - unsigned int led_2TransmitActivity : 1; /* 1E.C432.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on transmit activity - */ - /*! \brief 1E.C432.3 R/WPD LED #2 Receive Activity - AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2ReceiveActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on receive activity - - */ - unsigned int led_2ReceiveActivity : 1; /* 1E.C432.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on receive activity - */ - /*! \brief 1E.C432.4 R/WPD LED #2 Connecting - AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2Connecting - - Provisionable Default = 0x0 - - 1 = LED is on when attempting to connect. - - */ - unsigned int led_2Connecting : 1; /* 1E.C432.4 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when attempting to connect. - */ - /*! \brief 1E.C432.5 R/WPD LED #2 100 Mb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2_100Mb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 100 Mb/s - - */ - unsigned int led_2_100Mb_sLinkEstablished : 1; /* 1E.C432.5 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 100 Mb/s - */ - /*! \brief 1E.C432.6 R/WPD LED #2 1 Gb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2_1Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 1 Gb/s - - */ - unsigned int led_2_1Gb_sLinkEstablished : 1; /* 1E.C432.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 1 Gb/s - */ - /*! \brief 1E.C432.7 R/WPD LED #2 10 Gb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2_10Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 10 Gb/s - - */ - unsigned int led_2_10Gb_sLinkEstablished : 1; /* 1E.C432.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 10 Gb/s - */ - /*! \brief 1E.C432.8 R/WPD LED #2 Manual Set - AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2ManualSet - - Provisionable Default = 0x0 - - 1 = LED On - - */ - unsigned int led_2ManualSet : 1; /* 1E.C432.8 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED On - */ - unsigned int reserved0 : 7; - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global LED Provisioning */ - union - { - struct - { - /*! \brief 1E.C433.1:0 R/WPD LED #3 Activity Stretch [1:0] - AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3ActivityStretch - - Provisionable Default = 0x3 - - [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - - */ - unsigned int led_3ActivityStretch : 2; /* 1E.C433.1:0 R/WPD Provisionable Default = 0x3 */ - /* [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - */ - /*! \brief 1E.C433.2 R/WPD LED #3 Transmit Activity - AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3TransmitActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on transmit activity - - */ - unsigned int led_3TransmitActivity : 1; /* 1E.C433.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on transmit activity - */ - /*! \brief 1E.C433.3 R/WPD LED #3 Receive Activity - AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3ReceiveActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on receive activity - - */ - unsigned int led_3ReceiveActivity : 1; /* 1E.C433.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on receive activity - */ - /*! \brief 1E.C433.4 R/WPD LED #3 Connecting - AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3Connecting - - Provisionable Default = 0x0 - - 1 = LED is on when attempting to connect. - - */ - unsigned int led_3Connecting : 1; /* 1E.C433.4 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when attempting to connect. - */ - /*! \brief 1E.C433.5 R/WPD LED #3 100 Mb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3_100Mb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 100 Mb/s - - */ - unsigned int led_3_100Mb_sLinkEstablished : 1; /* 1E.C433.5 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 100 Mb/s - */ - /*! \brief 1E.C433.6 R/WPD LED #3 1 Gb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3_1Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 1 Gb/s - - */ - unsigned int led_3_1Gb_sLinkEstablished : 1; /* 1E.C433.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 1 Gb/s - */ - /*! \brief 1E.C433.7 R/WPD LED #3 10 Gb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3_10Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 10 Gb/s - - */ - unsigned int led_3_10Gb_sLinkEstablished : 1; /* 1E.C433.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 10 Gb/s - */ - /*! \brief 1E.C433.8 R/WPD LED #3 Manual Set - AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3ManualSet - - Provisionable Default = 0x0 - - 1 = LED On - - */ - unsigned int led_3ManualSet : 1; /* 1E.C433.8 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED On - */ - unsigned int reserved0 : 7; - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of Global LED Provisioning */ - union - { - struct - { - /*! \brief 1E.C434.1:0 R/WPD LED #4 Activity Stretch [1:0] - AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4ActivityStretch - - Provisionable Default = 0x3 - - [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - - */ - unsigned int led_4ActivityStretch : 2; /* 1E.C434.1:0 R/WPD Provisionable Default = 0x3 */ - /* [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - */ - /*! \brief 1E.C434.2 R/WPD LED #4 Transmit Activity - AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4TransmitActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on transmit activity - - */ - unsigned int led_4TransmitActivity : 1; /* 1E.C434.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on transmit activity - */ - /*! \brief 1E.C434.3 R/WPD LED #4 Receive Activity - AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4ReceiveActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on receive activity - - */ - unsigned int led_4ReceiveActivity : 1; /* 1E.C434.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on receive activity - */ - /*! \brief 1E.C434.4 R/WPD LED #4 Connecting - AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4Connecting - - Provisionable Default = 0x0 - - 1 = LED is on when attempting to connect. - - */ - unsigned int led_4Connecting : 1; /* 1E.C434.4 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when attempting to connect. - */ - /*! \brief 1E.C434.5 R/WPD LED #4 100 Mb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4_100Mb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 100 Mb/s - - */ - unsigned int led_4_100Mb_sLinkEstablished : 1; /* 1E.C434.5 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 100 Mb/s - */ - /*! \brief 1E.C434.6 R/WPD LED #4 1 Gb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4_1Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 1 Gb/s - - */ - unsigned int led_4_1Gb_sLinkEstablished : 1; /* 1E.C434.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 1 Gb/s - */ - /*! \brief 1E.C434.7 R/WPD LED #4 10 Gb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4_10Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 10 Gb/s - - */ - unsigned int led_4_10Gb_sLinkEstablished : 1; /* 1E.C434.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 10 Gb/s - */ - /*! \brief 1E.C434.8 R/WPD LED #4 Manual Set - AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4ManualSet - - Provisionable Default = 0x0 - - 1 = LED On - - */ - unsigned int led_4ManualSet : 1; /* 1E.C434.8 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED On - */ - unsigned int reserved0 : 7; - } bits_4; - uint16_t word_4; - } u4; - /*! \brief Union for bit and word level access of word 5 of Global LED Provisioning */ - union - { - struct - { - /*! \brief 1E.C435.1:0 R/WPD LED #5 Activity Stretch [1:0] - AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5ActivityStretch - - Provisionable Default = 0x3 - - [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - - */ - unsigned int led_5ActivityStretch : 2; /* 1E.C435.1:0 R/WPD Provisionable Default = 0x3 */ - /* [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - */ - /*! \brief 1E.C435.2 R/WPD LED #5 Transmit Activity - AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5TransmitActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on transmit activity - - */ - unsigned int led_5TransmitActivity : 1; /* 1E.C435.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on transmit activity - */ - /*! \brief 1E.C435.3 R/WPD LED #5 Receive Activity - AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5ReceiveActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on receive activity - - */ - unsigned int led_5ReceiveActivity : 1; /* 1E.C435.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on receive activity - */ - /*! \brief 1E.C435.4 R/WPD LED #5 Connecting - AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5Connecting - - Provisionable Default = 0x0 - - 1 = LED is on when attempting to connect. - - */ - unsigned int led_5Connecting : 1; /* 1E.C435.4 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when attempting to connect. - */ - /*! \brief 1E.C435.5 R/WPD LED #5 100 Mb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5_100Mb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 100 Mb/s - - */ - unsigned int led_5_100Mb_sLinkEstablished : 1; /* 1E.C435.5 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 100 Mb/s - */ - /*! \brief 1E.C435.6 R/WPD LED #5 1 Gb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5_1Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 1 Gb/s - - */ - unsigned int led_5_1Gb_sLinkEstablished : 1; /* 1E.C435.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 1 Gb/s - */ - /*! \brief 1E.C435.7 R/WPD LED #5 10 Gb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5_10Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 10 Gb/s - - */ - unsigned int led_5_10Gb_sLinkEstablished : 1; /* 1E.C435.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 10 Gb/s - */ - /*! \brief 1E.C435.8 R/WPD LED #5 Manual Set - AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5ManualSet - - Provisionable Default = 0x0 - - 1 = LED On - - */ - unsigned int led_5ManualSet : 1; /* 1E.C435.8 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED On - */ - unsigned int reserved0 : 7; - } bits_5; - uint16_t word_5; - } u5; - /*! \brief Union for bit and word level access of word 6 of Global LED Provisioning */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_6; - uint16_t word_6; - } u6; - /*! \brief Union for bit and word level access of word 7 of Global LED Provisioning */ - union - { - struct - { - /*! \brief 1E.C437.0 R/WPD LED Operation Mode - AQ_GlobalLedProvisioning_APPIA.u7.bits_7.ledOperationMode - - Provisionable Default = 0x0 - - 1 = LED link activity in Mode #2 - 0 = LED link activity in classic mode - - - Notes: - When set to 1, the LED blinking rate is based on Mode #2 algorithm. When set to 0, the LED blinking rate is based on the classic algorithm. */ - unsigned int ledOperationMode : 1; /* 1E.C437.0 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED link activity in Mode #2 - 0 = LED link activity in classic mode - */ - unsigned int reserved0 : 15; - } bits_7; - uint16_t word_7; - } u7; - /*! \brief Union for bit and word level access of word 8 of Global LED Provisioning */ - union - { - struct - { - /*! \brief 1E.C438.0 R/WPD LED #0 Manual Active Select - AQ_GlobalLedProvisioning_APPIA.u8.bits_8.led_0ManualActiveSelect - - Provisionable Default = 0x0 - - 1 = Manual selection of LED active high or low - 0 = Determine the active high or low based on the external pull-up or pull-down - - */ - unsigned int led_0ManualActiveSelect : 1; /* 1E.C438.0 R/WPD Provisionable Default = 0x0 */ - /* 1 = Manual selection of LED active high or low - 0 = Determine the active high or low based on the external pull-up or pull-down - */ - /*! \brief 1E.C438.1 R/WPD LED #0 Active High Select - AQ_GlobalLedProvisioning_APPIA.u8.bits_8.led_0ActiveHighSelect - - Provisionable Default = 0x0 - - 1 = LED active high - 0 = LED active low - - - Notes: - The See LED #0 Manual Active Select bit must be 1 for this bit to take affect. */ - unsigned int led_0ActiveHighSelect : 1; /* 1E.C438.1 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED active high - 0 = LED active low - */ - /*! \brief 1E.C438.2 R/WPD LED #0 Drive Three State Select - AQ_GlobalLedProvisioning_APPIA.u8.bits_8.led_0DriveThreeStateSelect - - Provisionable Default = 0x0 - - 1 = Drive LED tri-state when not active - 0 = Drive LED opposite of active level when not active - - */ - unsigned int led_0DriveThreeStateSelect : 1; /* 1E.C438.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = Drive LED tri-state when not active - 0 = Drive LED opposite of active level when not active - */ - unsigned int reserved0 : 13; - } bits_8; - uint16_t word_8; - } u8; - /*! \brief Union for bit and word level access of word 9 of Global LED Provisioning */ - union - { - struct - { - /*! \brief 1E.C439.0 R/WPD LED #1 Manual Active Select - AQ_GlobalLedProvisioning_APPIA.u9.bits_9.led_1ManualActiveSelect - - Provisionable Default = 0x0 - - 1 = Manual selection of LED active high or low - 0 = Determine the active high or low based on the external pull-up or pull-down - - */ - unsigned int led_1ManualActiveSelect : 1; /* 1E.C439.0 R/WPD Provisionable Default = 0x0 */ - /* 1 = Manual selection of LED active high or low - 0 = Determine the active high or low based on the external pull-up or pull-down - */ - /*! \brief 1E.C439.1 R/WPD LED #1 Active High Select - AQ_GlobalLedProvisioning_APPIA.u9.bits_9.led_1ActiveHighSelect - - Provisionable Default = 0x0 - - 1 = LED active high - 0 = LED active low - - - Notes: - The See LED #1 Manual Active Select bit must be 1 for this bit to take affect. */ - unsigned int led_1ActiveHighSelect : 1; /* 1E.C439.1 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED active high - 0 = LED active low - */ - /*! \brief 1E.C439.2 R/WPD LED #1 Drive Three State Select - AQ_GlobalLedProvisioning_APPIA.u9.bits_9.led_1DriveThreeStateSelect - - Provisionable Default = 0x0 - - 1 = Drive LED tri-state when not active - 0 = Drive LED opposite of active level when not active - - */ - unsigned int led_1DriveThreeStateSelect : 1; /* 1E.C439.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = Drive LED tri-state when not active - 0 = Drive LED opposite of active level when not active - */ - unsigned int reserved0 : 13; - } bits_9; - uint16_t word_9; - } u9; - /*! \brief Union for bit and word level access of word 10 of Global LED Provisioning */ - union - { - struct - { - /*! \brief 1E.C43A.0 R/WPD LED #2 Manual Active Select - AQ_GlobalLedProvisioning_APPIA.u10.bits_10.led_2ManualActiveSelect - - Provisionable Default = 0x0 - - 1 = Manual selection of LED active high or low - 0 = Determine the active high or low based on the external pull-up or pull-down - - */ - unsigned int led_2ManualActiveSelect : 1; /* 1E.C43A.0 R/WPD Provisionable Default = 0x0 */ - /* 1 = Manual selection of LED active high or low - 0 = Determine the active high or low based on the external pull-up or pull-down - */ - /*! \brief 1E.C43A.1 R/WPD LED #2 Active High Select - AQ_GlobalLedProvisioning_APPIA.u10.bits_10.led_2ActiveHighSelect - - Provisionable Default = 0x0 - - 1 = LED active high - 0 = LED active low - - - Notes: - The See LED #2 Manual Active Select bit must be 1 for this bit to take affect. */ - unsigned int led_2ActiveHighSelect : 1; /* 1E.C43A.1 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED active high - 0 = LED active low - */ - /*! \brief 1E.C43A.2 R/WPD LED #2 Drive Three State Select - AQ_GlobalLedProvisioning_APPIA.u10.bits_10.led_2DriveThreeStateSelect - - Provisionable Default = 0x0 - - 1 = Drive LED tri-state when not active - 0 = Drive LED opposite of active level when not active - - */ - unsigned int led_2DriveThreeStateSelect : 1; /* 1E.C43A.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = Drive LED tri-state when not active - 0 = Drive LED opposite of active level when not active - */ - unsigned int reserved0 : 13; - } bits_10; - uint16_t word_10; - } u10; - /*! \brief Union for bit and word level access of word 11 of Global LED Provisioning */ - union - { - struct - { - /*! \brief 1E.C43B.0 R/WPD LED #3 Manual Active Select - AQ_GlobalLedProvisioning_APPIA.u11.bits_11.led_3ManualActiveSelect - - Provisionable Default = 0x0 - - 1 = Manual selection of LED active high or low - 0 = Determine the active high or low based on the external pull-up or pull-down - - */ - unsigned int led_3ManualActiveSelect : 1; /* 1E.C43B.0 R/WPD Provisionable Default = 0x0 */ - /* 1 = Manual selection of LED active high or low - 0 = Determine the active high or low based on the external pull-up or pull-down - */ - /*! \brief 1E.C43B.1 R/WPD LED #3 Active High Select - AQ_GlobalLedProvisioning_APPIA.u11.bits_11.led_3ActiveHighSelect - - Provisionable Default = 0x0 - - 1 = LED active high - 0 = LED active low - - - Notes: - The See LED #3 Manual Active Select bit must be 1 for this bit to take affect. */ - unsigned int led_3ActiveHighSelect : 1; /* 1E.C43B.1 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED active high - 0 = LED active low - */ - /*! \brief 1E.C43B.2 R/WPD LED #3 Drive Three State Select - AQ_GlobalLedProvisioning_APPIA.u11.bits_11.led_3DriveThreeStateSelect - - Provisionable Default = 0x0 - - 1 = Drive LED tri-state when not active - 0 = Drive LED opposite of active level when not active - - */ - unsigned int led_3DriveThreeStateSelect : 1; /* 1E.C43B.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = Drive LED tri-state when not active - 0 = Drive LED opposite of active level when not active - */ - unsigned int reserved0 : 13; - } bits_11; - uint16_t word_11; - } u11; - /*! \brief Union for bit and word level access of word 12 of Global LED Provisioning */ - union - { - struct - { - /*! \brief 1E.C43C.0 R/WPD LED #4 Manual Active Select - AQ_GlobalLedProvisioning_APPIA.u12.bits_12.led_4ManualActiveSelect - - Provisionable Default = 0x0 - - 1 = Manual selection of LED active high or low - 0 = Determine the active high or low based on the external pull-up or pull-down - - */ - unsigned int led_4ManualActiveSelect : 1; /* 1E.C43C.0 R/WPD Provisionable Default = 0x0 */ - /* 1 = Manual selection of LED active high or low - 0 = Determine the active high or low based on the external pull-up or pull-down - */ - /*! \brief 1E.C43C.1 R/WPD LED #4 Active High Select - AQ_GlobalLedProvisioning_APPIA.u12.bits_12.led_4ActiveHighSelect - - Provisionable Default = 0x0 - - 1 = LED active high - 0 = LED active low - - - Notes: - The See LED #4 Manual Active Select bit must be 1 for this bit to take affect. */ - unsigned int led_4ActiveHighSelect : 1; /* 1E.C43C.1 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED active high - 0 = LED active low - */ - /*! \brief 1E.C43C.2 R/WPD LED #4 Drive Three State Select - AQ_GlobalLedProvisioning_APPIA.u12.bits_12.led_4DriveThreeStateSelect - - Provisionable Default = 0x0 - - 1 = Drive LED tri-state when not active - 0 = Drive LED opposite of active level when not active - - */ - unsigned int led_4DriveThreeStateSelect : 1; /* 1E.C43C.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = Drive LED tri-state when not active - 0 = Drive LED opposite of active level when not active - */ - unsigned int reserved0 : 13; - } bits_12; - uint16_t word_12; - } u12; - /*! \brief Union for bit and word level access of word 13 of Global LED Provisioning */ - union - { - struct - { - /*! \brief 1E.C43D.0 R/WPD LED #5 Manual Active Select - AQ_GlobalLedProvisioning_APPIA.u13.bits_13.led_5ManualActiveSelect - - Provisionable Default = 0x0 - - 1 = Manual selection of LED active high or low - 0 = Determine the active high or low based on the external pull-up or pull-down - - */ - unsigned int led_5ManualActiveSelect : 1; /* 1E.C43D.0 R/WPD Provisionable Default = 0x0 */ - /* 1 = Manual selection of LED active high or low - 0 = Determine the active high or low based on the external pull-up or pull-down - */ - /*! \brief 1E.C43D.1 R/WPD LED #5 Active High Select - AQ_GlobalLedProvisioning_APPIA.u13.bits_13.led_5ActiveHighSelect - - Provisionable Default = 0x0 - - 1 = LED active high - 0 = LED active low - - - Notes: - The See LED #5 Manual Active Select bit must be 1 for this bit to take affect. */ - unsigned int led_5ActiveHighSelect : 1; /* 1E.C43D.1 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED active high - 0 = LED active low - */ - /*! \brief 1E.C43D.2 R/WPD LED #5 Drive Three State Select - AQ_GlobalLedProvisioning_APPIA.u13.bits_13.led_5DriveThreeStateSelect - - Provisionable Default = 0x0 - - 1 = Drive LED tri-state when not active - 0 = Drive LED opposite of active level when not active - - */ - unsigned int led_5DriveThreeStateSelect : 1; /* 1E.C43D.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = Drive LED tri-state when not active - 0 = Drive LED opposite of active level when not active - */ - unsigned int reserved0 : 13; - } bits_13; - uint16_t word_13; - } u13; -} AQ_GlobalLedProvisioning_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global General Provisioning: 1E.C440 */ -/* Global General Provisioning: 1E.C440 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global General Provisioning */ - union - { - struct - { - /*! \brief 1E.C440.0 RO Gang Load MDIO Write Only - AQ_GlobalGeneralProvisioning_APPIA.u0.bits_0.gangLoadMdioWriteOnly - - - - 1 = MDIO gang load enable - - - Notes: - This bit enables gang load operation with the address specified in Bits 8:4. */ - unsigned int gangLoadMdioWriteOnly : 1; /* 1E.C440.0 RO */ - /* 1 = MDIO gang load enable - */ - unsigned int reserved1 : 3; - /*! \brief 1E.C440.8:4 R/WPD Gang Load MDIO Address [4:0] - AQ_GlobalGeneralProvisioning_APPIA.u0.bits_0.gangLoadMdioAddress - - Provisionable Default = 0x00 - - MDIO Address to be used during gang load operation - - - Notes: - Gang load operation is used to load data into multiple PHYs all connected to the same MDIO bus. The address for gang load operation is provided by these bits (8:4), and enabling is done by writing Bit 0. Disabling of gang load mode is done by writing the See MDIO Address Reset (1E.C441.2) bit. These will revert the PHY's MDIO address back to the address provided by the MDIO Address pins. During gang load operation, MDIO reads are disabled to prevent bus contention. */ - unsigned int gangLoadMdioAddress : 5; /* 1E.C440.8:4 R/WPD Provisionable Default = 0x00 */ - /* MDIO Address to be used during gang load operation - */ - unsigned int reserved0 : 7; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global General Provisioning */ - union - { - struct - { - unsigned int reserved2 : 2; - /*! \brief 1E.C441.2 R/WSC MDIO Address Reset - AQ_GlobalGeneralProvisioning_APPIA.u1.bits_1.mdioAddressReset - - Default = 0x0 - - 1 = Load MDIO Address with the address on the MDIO address pins - - - Notes: - Used to reset the address after gang load and enable MDIO reads again. */ - unsigned int mdioAddressReset : 1; /* 1E.C441.2 R/WSC Default = 0x0 */ - /* 1 = Load MDIO Address with the address on the MDIO address pins - */ - /*! \brief 1E.C441.3 R/WPD MDIO Preamble Detection Disable - AQ_GlobalGeneralProvisioning_APPIA.u1.bits_1.mdioPreambleDetectionDisable - - Provisionable Default = 0x0 - - 1 = Suppress preamble detection on MDIO - 0 = Enable preamble detection on MDIO - - */ - unsigned int mdioPreambleDetectionDisable : 1; /* 1E.C441.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = Suppress preamble detection on MDIO - 0 = Enable preamble detection on MDIO - */ - /*! \brief 1E.C441.4 R/WPD MDIO Drive Configuration - AQ_GlobalGeneralProvisioning_APPIA.u1.bits_1.mdioDriveConfiguration - - Provisionable Default = 0x0 - - 0 = MDIO driver is in normal mode - 1 = MDIO driver is in open drain mode - - - Notes: - When the MDIO driver is in open drain mode during a read cycle, "0" data will be actively driven out of the MDIO, "1" data will set the MDIO driver in high impedance state and an external pullup will set the MDIO line to "1". The Turn-Around "0" will also be actively driven out of the MDIO, therefore in open drain mode, the Turn-Around is still "Z0". */ - unsigned int mdioDriveConfiguration : 1; /* 1E.C441.4 R/WPD Provisionable Default = 0x0 */ - /* 0 = MDIO driver is in normal mode - 1 = MDIO driver is in open drain mode - */ - unsigned int reserved1 : 8; - /*! \brief 1E.C441.D R/WPD MDIO Read MSW First Enable - AQ_GlobalGeneralProvisioning_APPIA.u1.bits_1.mdioReadMSW_FirstEnable - - Provisionable Default = 0x0 - - 1 = MSW of counter must be read first - 0 = LSW of counter must be read first - - - Notes: - This bit configures whether the MSW or LSW must be read first for counters greater than 16 bits. */ - unsigned int mdioReadMSW_FirstEnable : 1; /* 1E.C441.D R/WPD Provisionable Default = 0x0 */ - /* 1 = MSW of counter must be read first - 0 = LSW of counter must be read first - */ - /*! \brief 1E.C441.E R/WPD MDIO Broadcast Mode Enable - AQ_GlobalGeneralProvisioning_APPIA.u1.bits_1.mdioBroadcastModeEnable - - Provisionable Default = 0x0 - - 1 = Enable broadcast on Address 0 - 0 = Disable broadcast on Address 0 - - - Notes: - When set, this bit enables gang-load operation on address zero, simultaneous with normal MDIO operation. Obviously, this requires that no PHY use address 0 as its normal operating address. As well, reads on MDIO Address 0 are disabled to prevent bus contention. */ - unsigned int mdioBroadcastModeEnable : 1; /* 1E.C441.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable broadcast on Address 0 - 0 = Disable broadcast on Address 0 - */ - unsigned int reserved0 : 1; - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global General Provisioning */ - union - { - struct - { - /*! \brief 1E.C442.0 R/W Daisy Chain Reset - AQ_GlobalGeneralProvisioning_APPIA.u2.bits_2.daisyChainReset - - Default = 0x0 - - 1 = Reset the daisy chain - - - Notes: - Toggling this bit from 0 to 1 will reload the IRAM and DRAM and reset the uP. The uP will be in uP run stall during the reload process. After the reload process, uP run stall will be de-asserted adn the uP reset will be asserted. Note that before setting this bit, the See Soft Reset bit needs to be de-asserted. */ - unsigned int daisyChainReset : 1; /* 1E.C442.0 R/W Default = 0x0 */ - /* 1 = Reset the daisy chain - */ - unsigned int reserved0 : 15; - } bits_2; - uint16_t word_2; - } u2; -} AQ_GlobalGeneralProvisioning_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global NVR Provisioning: 1E.C450 */ -/* Global NVR Provisioning: 1E.C450 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global NVR Provisioning */ - union - { - struct - { - /*! \brief 1E.C450.1:0 R/WPD NVR Address Length [1:0] - AQ_GlobalNvrProvisioning_APPIA.u0.bits_0.nvrAddressLength - - Provisionable Default = 0x2 - - NVR address length ranges from 0 bytes up to 3 bytes. - - - Notes: - This sets the length of the address field used in read and write operations. Use of this field is enabled via Bit 8 of See Global NVR Provisioning 2: Address 1E.C451 . - */ - unsigned int nvrAddressLength : 2; /* 1E.C450.1:0 R/WPD Provisionable Default = 0x2 */ - /* NVR address length ranges from 0 bytes up to 3 bytes. - */ - unsigned int reserved2 : 2; - /*! \brief 1E.C450.6:4 R/WPD NVR Dummy Length [2:0] - AQ_GlobalNvrProvisioning_APPIA.u0.bits_0.nvrDummyLength - - Provisionable Default = 0x0 - - NVR dummy length ranges from 0 bytes to 4 bytes. - - - Notes: - This sets the length of the dummy field used in some maunfacturer's read status and write status operations. - */ - unsigned int nvrDummyLength : 3; /* 1E.C450.6:4 R/WPD Provisionable Default = 0x0 */ - /* NVR dummy length ranges from 0 bytes to 4 bytes. - */ - unsigned int reserved1 : 1; - /*! \brief 1E.C450.A:8 R/WPD NVR Data Length [2:0] - AQ_GlobalNvrProvisioning_APPIA.u0.bits_0.nvrDataLength - - Provisionable Default = 0x4 - - NVR data length ranges from 0 bytes to 4 bytes - - - Notes: - This sets the length of the data burst used in read and write operations. - */ - unsigned int nvrDataLength : 3; /* 1E.C450.A:8 R/WPD Provisionable Default = 0x4 */ - /* NVR data length ranges from 0 bytes to 4 bytes - */ - unsigned int reserved0 : 5; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global NVR Provisioning */ - union - { - struct - { - /*! \brief 1E.C451.7:0 R/WPD NVR Clock Divide [7:0] - AQ_GlobalNvrProvisioning_APPIA.u1.bits_1.nvrClockDivide - - Provisionable Default = 0xA0 - - NVR clock divide. Clock frequency is divided by the NVR clock divide + 1 - - */ - unsigned int nvrClockDivide : 8; /* 1E.C451.7:0 R/WPD Provisionable Default = 0xA0 */ - /* NVR clock divide. Clock frequency is divided by the NVR clock divide + 1 - */ - /*! \brief 1E.C451.8 R/WPD NVR Address Length Override - AQ_GlobalNvrProvisioning_APPIA.u1.bits_1.nvrAddressLengthOverride - - Provisionable Default = 0x0 - - 0 = NVR address length is based on the "NVR_SIZE" pin. - 1 = NVR address length is based on the See NVR Address Length [1:0] register. - - - Notes: - When the this bit = 0 and NVR_SIZE pin = 0, the NVR address length is 2 bytes. When this bit = 0 and the NVR_SIZE pin = 1, the NVR address length is 3 bytes. When this bit = 1 the NVR address length is from the See NVR Address Length [1:0] */ - unsigned int nvrAddressLengthOverride : 1; /* 1E.C451.8 R/WPD Provisionable Default = 0x0 */ - /* 0 = NVR address length is based on the "NVR_SIZE" pin. - 1 = NVR address length is based on the See NVR Address Length [1:0] register. - */ - unsigned int reserved0 : 7; - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global NVR Provisioning */ - union - { - struct - { - /*! \brief 1E.C452.0 R/W NVR Daisy Chain Disable - AQ_GlobalNvrProvisioning_APPIA.u2.bits_2.nvrDaisyChainDisable - - Default = 0x0 - - 1 = Disable the Daisy Chain - - - Notes: - When in daisy chain master mode, the daisy chain and MDIO can both access the SPI. Setting this bit to 1 will disable the dasiy chain from accessing the SPI and force it into a reset state. */ - unsigned int nvrDaisyChainDisable : 1; /* 1E.C452.0 R/W Default = 0x0 */ - /* 1 = Disable the Daisy Chain - */ - /*! \brief 1E.C452.1 R/W NVR Daisy Chain Clock Divide Override - AQ_GlobalNvrProvisioning_APPIA.u2.bits_2.nvrDaisyChainClockDivideOverride - - Default = 0x0 - - 1 = Override NVR clock divide when in daisy chain master mode - - - - Notes: - When in daisy chain master mode, the clock divide configuration is received from the flash. This bit will override the clock divide configuration from the flash with the See NVR Clock Divide [7:0] . */ - unsigned int nvrDaisyChainClockDivideOverride : 1; /* 1E.C452.1 R/W Default = 0x0 */ - /* 1 = Override NVR clock divide when in daisy chain master mode - - */ - unsigned int reserved0 : 14; - } bits_2; - uint16_t word_2; - } u2; -} AQ_GlobalNvrProvisioning_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Reserved Provisioning: 1E.C470 */ -/* Global Reserved Provisioning: 1E.C470 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Reserved Provisioning */ - union - { - struct - { - unsigned int reserved2 : 4; - /*! \brief 1E.C470.4 R/WSC Initiate Cable Diagnostics - AQ_GlobalReservedProvisioning_APPIA.u0.bits_0.initiateCableDiagnostics - - Default = 0x0 - - 1 = Perform cable diagnostics - - - Notes: - Perform cable diagnostics regardless of link state. If link is up, setting this bit will cause the link to drop while diagnostics are performed. This bit is self-clearing upon completion of the cable diagnostics. Further MDIO writes should be avoided until this bit has self-cleared, indicating completion of the diagnostic routine. */ - unsigned int initiateCableDiagnostics : 1; /* 1E.C470.4 R/WSC Default = 0x0 */ - /* 1 = Perform cable diagnostics - */ - /*! \brief 1E.C470.5 R/WSC Initiate Component Diagnostics - AQ_GlobalReservedProvisioning_APPIA.u0.bits_0.initiateComponentDiagnostics - - Default = 0x0 - - 1 = Perform component diagnostics - - - Notes: - Perform component diagnostics regardless of link state. If link is up, setting this bit will cause the link to drop while diagnostics are performed. This bit is self-clearing upon completion of the component diagnostics. Further MDIO writes should be avoided until this bit has self-cleared, indicating completion of the diagnostic routine. */ - unsigned int initiateComponentDiagnostics : 1; /* 1E.C470.5 R/WSC Default = 0x0 */ - /* 1 = Perform component diagnostics - */ - unsigned int reserved1 : 2; - unsigned int reserved0 : 5; - /*! \brief 1E.C470.E:D R/WPD Extended MDI Diagnostics Select [1:0] - AQ_GlobalReservedProvisioning_APPIA.u0.bits_0.extendedMdiDiagnosticsSelect - - Provisionable Default = 0x0 - - 0x0 = TDR Data - 0x1 = RFI Channel PSD - 0x2 = Noise PSD while the local Tx is Off - 0x3 = Noise PSD while the local Tx is On - - - Notes: - These bits select what sort of cable diagnostics to perform. For regular cable diagnostics, Bit F is set to zero, and the diagnostics are triggered by setting Bit 4. For extended diagnostics, Bit F is set to 1, and the desired extended diagnostics are selected by Bits E:D. The routine is then triggered by setting Bit 4. Each of the extended diagnostic routines present data for all for MDI pairs (A, B, C, D) consecutively, and after the data for each channel is gathered Bits F:D are reset. To get the data for the next pair, Bits F:D must be set back to the desired value (which must be the same as the initial channel). This continues until the data for all channels has been gathered. The address in memory where the data is stored is given in 1E.C802 and 1E.C804. - - For the case of PSD, the structure is as follows: - Int32 info - Int16 data[Len] - Info = Len << 16 | TxEnable << 8 | Pair (0 = A, etc.) - - For TDR: - Int32 info - Int16 tdr_A[Len] - Int16 tdr_B[Len] - Int16 tdr_C[Len] - Int16 tdr_D[Len] - - Info = Len << 16 | Channel - - TDR data is from the current pair to all other pairs. - - At the end of retrieving extended MDI diag data, the part will be reset. Conversly the only way to exit this routine once it starts is to issue a PMA reset. */ - unsigned int extendedMdiDiagnosticsSelect : 2; /* 1E.C470.E:D R/WPD Provisionable Default = 0x0 */ - /* 0x0 = TDR Data - 0x1 = RFI Channel PSD - 0x2 = Noise PSD while the local Tx is Off - 0x3 = Noise PSD while the local Tx is On - */ - /*! \brief 1E.C470.F R/WPD Diagnostics Select - AQ_GlobalReservedProvisioning_APPIA.u0.bits_0.diagnosticsSelect - - Provisionable Default = 0x0 - - 1 = Provide Extended MDI Diagnostics Information. - 0 = Provide normal cable diagnostics - - - Notes: - These bits select what sort of cable diagnostics to perform. For regular cable diagnostics, Bit F is set to zero, and the diagnostics are triggered by setting Bit 4. For extended diagnostics, Bit F is set to 1, and the desired extended diagnostics are selected by Bits E:D. The routine is then triggered by setting Bit 4. Each of the extended diagnostic routines present data for all for MDI pairs (A, B, C, D) consecutively, and after the data for each channel is gathered Bits F:D are reset. To get the data for the next pair, Bits F:D must be set back to the desired value (which must be the same as the initial channel). This continues until the data for all channels has been gathered. The address in memory where the data is stored is given in 1E.C802 and 1E.C804. - - For the case of PSD, the structure is as follows: - Int32 info - Int16 data[Len] - Info = Len << 16 | TxEnable << 8 | Pair (0 = A, etc.) - - For TDR: - Int32 info - Int16 tdr_A[Len] - Int16 tdr_B[Len] - Int16 tdr_C[Len] - Int16 tdr_D[Len] - - Info = Len << 16 | Channel - - TDR data is from the current pair to all other pairs. - - At the end of retrieving extended MDI diag data, the part will be reset. Conversly the only way to exit this routine once it starts is to issue a PMA reset. */ - unsigned int diagnosticsSelect : 1; /* 1E.C470.F R/WPD Provisionable Default = 0x0 */ - /* 1 = Provide Extended MDI Diagnostics Information. - 0 = Provide normal cable diagnostics - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Reserved Provisioning */ - union - { - struct - { - /*! \brief 1E.C471.5:0 R/WuP Daisy-Chain Hop-Count Override Value [5:0] - AQ_GlobalReservedProvisioning_APPIA.u1.bits_1.daisy_chainHop_countOverrideValue - - Default = 0x00 - - The value to use for the PHY's daisy-chain hop-count. Valid values are from 0 -> 47 - - - Notes: - Daisy-Chain Hop-Count Override should be used during MDIO boot-load operation, as the daisy-chain hop-count does not function when the daisy-chain is disabled (1E.C452.0). Setting this bit tells the processor where in the diasy-chain it is, so that the provisioning operation will function correctly. */ - unsigned int daisy_chainHop_countOverrideValue : 6; /* 1E.C471.5:0 R/WuP Default = 0x00 */ - /* The value to use for the PHY's daisy-chain hop-count. Valid values are from 0 -> 47 - */ - /*! \brief 1E.C471.6 R/WuP Enable Daisy-Chain Hop-Count Override - AQ_GlobalReservedProvisioning_APPIA.u1.bits_1.enableDaisy_chainHop_countOverride - - Default = 0x0 - - 1 = Hop-count is set by Bits 5:0 - 0 = Hop-count is determined by the daisy-chain - - - Notes: - Daisy-Chain Hop-Count Override should be used during MDIO boot-load operation, as the daisy-chain hop-count does not function when the daisy-chain is disabled (1E.C452.0). Setting this bit tells the processor where in the diasy-chain it is, so that the provisioning operation will function correctly. */ - unsigned int enableDaisy_chainHop_countOverride : 1; /* 1E.C471.6 R/WuP Default = 0x0 */ - /* 1 = Hop-count is set by Bits 5:0 - 0 = Hop-count is determined by the daisy-chain - */ - /*! \brief 1E.C471.F:7 R/WPD Reserved Provisioning 2 [8:0] - AQ_GlobalReservedProvisioning_APPIA.u1.bits_1.reservedProvisioning_2 - - Provisionable Default = 0x000 - - Reserved for future use - - */ - unsigned int reservedProvisioning_2 : 9; /* 1E.C471.F:7 R/WPD Provisionable Default = 0x000 */ - /* Reserved for future use - */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global Reserved Provisioning */ - union - { - struct - { - /*! \brief 1E.C472.0 R/WPDuP Enable 5th Channel RFI Cancellation - AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.enable_5thChannelRfiCancellation - - Provisionable Default = 0x0 - - 1 = 5th channel and RFI cancellers operation enabled - 0 = 5th channel AFE is powered down, 5th channel digital is clock gated, RFI cancellers are disabled - - - Notes: - Note: The value of this bit at the time of Autonegotiation sets the local PHY behavior until the next time Autonegotiation occurs. */ - unsigned int enable_5thChannelRfiCancellation : 1; /* 1E.C472.0 R/WPDuP Provisionable Default = 0x0 */ - /* 1 = 5th channel and RFI cancellers operation enabled - 0 = 5th channel AFE is powered down, 5th channel digital is clock gated, RFI cancellers are disabled - */ - /*! \brief 1E.C472.1 R/WPDuP Enable XENPAK Register Space - AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.enableXenpakRegisterSpace - - Provisionable Default = 0x0 - - 1 = XENPAK register space enabled - 0 = XENPAK register space disabled - - */ - unsigned int enableXenpakRegisterSpace : 1; /* 1E.C472.1 R/WPDuP Provisionable Default = 0x0 */ - /* 1 = XENPAK register space enabled - 0 = XENPAK register space disabled - */ - unsigned int reserved1 : 4; - /*! \brief 1E.C472.6 R/WPD Tunable External VDD Power Supply Present - AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.tunableExternalVddPowerSupplyPresent - - Provisionable Default = 0x0 - - 1 = Tunable external VDD power supply present - 0 = No tunable external VDD power supply present - - - Notes: - - - - These bits must be set if tuning of external power supplies is desired (see Bits 7:6) */ - unsigned int tunableExternalVddPowerSupplyPresent : 1; /* 1E.C472.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = Tunable external VDD power supply present - 0 = No tunable external VDD power supply present - */ - /*! \brief 1E.C472.7 R/WPD Tunable External LVDD Power Supply Present - AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.tunableExternalLvddPowerSupplyPresent - - Provisionable Default = 0x0 - - 1 = Tunable external LVDD power supply present - 0 = No tunable external LVDD power supply present - - - Notes: - - - - These bits must be set if tuning of external power supplies is desired (see Bits 7:6) */ - unsigned int tunableExternalLvddPowerSupplyPresent : 1; /* 1E.C472.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = Tunable external LVDD power supply present - 0 = No tunable external LVDD power supply present - */ - unsigned int reserved0 : 6; - /*! \brief 1E.C472.E R/WPD Enable VDD Power Supply Tuning - AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.enableVddPowerSupplyTuning - - Provisionable Default = 0x0 - - 1 = Enable external VDD power supply tuning - 0 = Disable external VDD power supply tuning is disabled - - - Notes: - - - - These bits control whether the PHY attempts to tune the external VDD and LVDD power supplies via the PMBus. These bits are only operational if the external supplies are present (see Bits 7:6) */ - unsigned int enableVddPowerSupplyTuning : 1; /* 1E.C472.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable external VDD power supply tuning - 0 = Disable external VDD power supply tuning is disabled - */ - /*! \brief 1E.C472.F R/WPD Enable LVDD Power Supply Tuning - AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.enableLvddPowerSupplyTuning - - Provisionable Default = 0x0 - - 1 = Enable external LVDD power supply tuning - 0 = Disable external LVDD power supply tuning is disabled - - - Notes: - - - - These bits control whether the PHY attempts to tune the external VDD and LVDD power supplies via the PMBus. These bits are only operational if the external supplies are present (see Bits 7:6) */ - unsigned int enableLvddPowerSupplyTuning : 1; /* 1E.C472.F R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable external LVDD power supply tuning - 0 = Disable external LVDD power supply tuning is disabled - */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global Reserved Provisioning */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of Global Reserved Provisioning */ - union - { - struct - { - /*! \brief 1E.C474.7:0 R/WPD Training SNR [7:0] - AQ_GlobalReservedProvisioning_APPIA.u4.bits_4.trainingSNR - - Provisionable Default = 0x00 - - SNR during 10G training on the worst channel. SNR is in steps of 0.1dB - - - Notes: - The SNR margin that is enjoyed by the worst channel, over and above the minimum SNR required to operate at a BER of 10-12. It is reported with 0.1 dB of resolution to an accuracy of 0.5 dB within the range of -12.7 dB to 12.7 dB. The number is in offset binary, with 0.0 dB represented by 0x8000. - */ - unsigned int trainingSNR : 8; /* 1E.C474.7:0 R/WPD Provisionable Default = 0x00 */ - /* SNR during 10G training on the worst channel. SNR is in steps of 0.1dB - */ - unsigned int reserved0 : 8; - } bits_4; - uint16_t word_4; - } u4; - /*! \brief Union for bit and word level access of word 5 of Global Reserved Provisioning */ - union - { - struct - { - unsigned int reserved1 : 2; - /*! \brief 1E.C475.2 R/WPD Smart Power-Down Enable - AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.smartPower_downEnable - - Provisionable Default = 0x0 - - 1 = Enable smart power down mode - 0 = Smart power-down mode disabled - - - Notes: - Smart power down (SPD) is the lowest power mode at which PHY is able to autonegotiate. SPD can be enabled with bit 1E.C475.2 */ - unsigned int smartPower_downEnable : 1; /* 1E.C475.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable smart power down mode - 0 = Smart power-down mode disabled - */ - /*! \brief 1E.C475.3 R/WPD Deadlock Avoidance Enable - AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.deadlockAvoidanceEnable - - Provisionable Default = 0x0 - - 1 = SPD with deadlock avoidance: PHY transmits autonegotiation pulses (FLPs) at a slower rate (~ 1 FLP/ 100ms) than specified by autonegotiation standard (~1 FLP / 8.25ms). Receiver is active and able to detect the pulses. - 0 = SPD without deadlock avoidance: PHY transmitter is shut down, no autonegotiation pulses are sent on the line but the receiver is active and able to detect the pulses - - */ - unsigned int deadlockAvoidanceEnable : 1; /* 1E.C475.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = SPD with deadlock avoidance: PHY transmits autonegotiation pulses (FLPs) at a slower rate (~ 1 FLP/ 100ms) than specified by autonegotiation standard (~1 FLP / 8.25ms). Receiver is active and able to detect the pulses. - 0 = SPD without deadlock avoidance: PHY transmitter is shut down, no autonegotiation pulses are sent on the line but the receiver is active and able to detect the pulses - */ - /*! \brief 1E.C475.4 R/WPD CFR Support - AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrSupport - - Provisionable Default = 0x0 - - 1 = Local PHY supports Cisco Fast Retrain - 0 = Local PHY does support Cisco Fast Retrain - - */ - unsigned int cfrSupport : 1; /* 1E.C475.4 R/WPD Provisionable Default = 0x0 */ - /* 1 = Local PHY supports Cisco Fast Retrain - 0 = Local PHY does support Cisco Fast Retrain - */ - /*! \brief 1E.C475.5 R/WPD CFR THP - AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrTHP - - Provisionable Default = 0x0 - - 1 = Local PHY requires local PHY to enable THP - 0 = Local PHY does not require local PHY to enable THP - - */ - unsigned int cfrTHP : 1; /* 1E.C475.5 R/WPD Provisionable Default = 0x0 */ - /* 1 = Local PHY requires local PHY to enable THP - 0 = Local PHY does not require local PHY to enable THP - */ - /*! \brief 1E.C475.6 R/WPD CFR Extended Maxwait - AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrExtendedMaxwait - - Provisionable Default = 0x0 - - 1 = Local PHY requires extended maxwait - 0 = Local PHY does not require extended maxwait - - */ - unsigned int cfrExtendedMaxwait : 1; /* 1E.C475.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = Local PHY requires extended maxwait - 0 = Local PHY does not require extended maxwait - */ - /*! \brief 1E.C475.7 R/WPD CFR Disable Timer - AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrDisableTimer - - Provisionable Default = 0x0 - - 1 = Local PHY requires cfr_disable timer - 0 = Local PHY does not require cfr_disable timer - - */ - unsigned int cfrDisableTimer : 1; /* 1E.C475.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = Local PHY requires cfr_disable timer - 0 = Local PHY does not require cfr_disable timer - */ - /*! \brief 1E.C475.8 R/WPD CFR LP Support - AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrLpSupport - - Provisionable Default = 0x0 - - 1 = Link partner supports Cisco Fast Retrain - 0 = Link partner does support Cisco Fast Retrain - - */ - unsigned int cfrLpSupport : 1; /* 1E.C475.8 R/WPD Provisionable Default = 0x0 */ - /* 1 = Link partner supports Cisco Fast Retrain - 0 = Link partner does support Cisco Fast Retrain - */ - /*! \brief 1E.C475.9 R/WPD CFR LP THP - AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrLpTHP - - Provisionable Default = 0x0 - - 1 = Link partner requires local PHY to enable THP - 0 = Link partner does not require local PHY to enable THP - - */ - unsigned int cfrLpTHP : 1; /* 1E.C475.9 R/WPD Provisionable Default = 0x0 */ - /* 1 = Link partner requires local PHY to enable THP - 0 = Link partner does not require local PHY to enable THP - */ - /*! \brief 1E.C475.A R/WPD CFR LP Extended Maxwait - AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrLpExtendedMaxwait - - Provisionable Default = 0x0 - - 1 = Link partner requires extended maxwait - 0 = Link partner does not require extended maxwait - - */ - unsigned int cfrLpExtendedMaxwait : 1; /* 1E.C475.A R/WPD Provisionable Default = 0x0 */ - /* 1 = Link partner requires extended maxwait - 0 = Link partner does not require extended maxwait - */ - /*! \brief 1E.C475.B R/WPD CFR LP Disable Timer - AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrLpDisableTimer - - Provisionable Default = 0x0 - - 1 = Link partner requires cfr_disable timer - 0 = Link partner does not require cfr_disable timer - - */ - unsigned int cfrLpDisableTimer : 1; /* 1E.C475.B R/WPD Provisionable Default = 0x0 */ - /* 1 = Link partner requires cfr_disable timer - 0 = Link partner does not require cfr_disable timer - */ - /*! \brief 1E.C475.C R/WPD Reserved Provisioning 6 - AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.reservedProvisioning_6 - - Provisionable Default = 0x0 - - Reserved for future use - - */ - unsigned int reservedProvisioning_6 : 1; /* 1E.C475.C R/WPD Provisionable Default = 0x0 */ - /* Reserved for future use - */ - /*! \brief 1E.C475.D R/WPD Smart Power-Down Status - AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.smartPower_downStatus - - Provisionable Default = 0x0 - - 1 = Smart Power-Down Active - 0 = Smart Power-Down Inactive - - */ - unsigned int smartPower_downStatus : 1; /* 1E.C475.D R/WPD Provisionable Default = 0x0 */ - /* 1 = Smart Power-Down Active - 0 = Smart Power-Down Inactive - */ - unsigned int reserved0 : 2; - } bits_5; - uint16_t word_5; - } u5; -} AQ_GlobalReservedProvisioning_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Cable Diagnostic Status: 1E.C800 */ -/* Global Cable Diagnostic Status: 1E.C800 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C800.2:0 RO Pair D Status [2:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u0.bits_0.pairDStatus - - - - (after running cable diags) - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair C - 010= Connected to Pair B - 001= Connected to Pair A - 000= OK - - OR: - - (after running component diags) - 100 = TX pin open - 011= TX bias open - 010= Capacitor short - 001= Inductor open - 000= OK - - Notes: - This bitfield reports the result, for pair D, of running either cable diagnostics or component diagnostics. */ - unsigned int pairDStatus : 3; /* 1E.C800.2:0 RO */ - /* (after running cable diags) - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair C - 010= Connected to Pair B - 001= Connected to Pair A - 000= OK - - OR: - - (after running component diags) - 100 = TX pin open - 011= TX bias open - 010= Capacitor short - 001= Inductor open - 000= OK */ - unsigned int reserved3 : 1; - /*! \brief 1E.C800.6:4 RO Pair C Status [2:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u0.bits_0.pairCStatus - - - - (after running cable diags) - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair B - 010= Connected to Pair A - 001= Connected to Pair D - 000= OK - - OR: - - (after running component diags) - 100 = TX pin open - 011= TX bias open - 010= Capacitor short - 001= Inductor open - 000= OK - - Notes: - This bitfield reports the result, for pair C, of running either cable diagnostics or component diagnostics. */ - unsigned int pairCStatus : 3; /* 1E.C800.6:4 RO */ - /* (after running cable diags) - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair B - 010= Connected to Pair A - 001= Connected to Pair D - 000= OK - - OR: - - (after running component diags) - 100 = TX pin open - 011= TX bias open - 010= Capacitor short - 001= Inductor open - 000= OK */ - unsigned int reserved2 : 1; - /*! \brief 1E.C800.A:8 RO Pair B Status [2:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u0.bits_0.pairBStatus - - - - (after running cable diags) - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair A - 010= Connected to Pair D - 001= Connected to Pair C - 000= OK - - OR: - - (after running component diags) - 100 = TX pin open - 011= TX bias open - 010= Capacitor short - 001= Inductor open - 000= OK - - Notes: - This bitfield reports the result, for pair B, of running either cable diagnostics or component diagnostics. */ - unsigned int pairBStatus : 3; /* 1E.C800.A:8 RO */ - /* (after running cable diags) - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair A - 010= Connected to Pair D - 001= Connected to Pair C - 000= OK - - OR: - - (after running component diags) - 100 = TX pin open - 011= TX bias open - 010= Capacitor short - 001= Inductor open - 000= OK */ - unsigned int reserved1 : 1; - /*! \brief 1E.C800.E:C RO Pair A Status [2:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u0.bits_0.pairAStatus - - - - (after running cable diags) - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair D - 010= Connected to Pair C - 001= Connected to Pair B - 000= OK - - OR: - - (after running component diags) - 100 = TX pin open - 011= TX bias open - 010= Capacitor short - 001= Inductor open - 000= OK - - Notes: - This bitfield reports the result, for pair A, of running either cable diagnostics or component diagnostics. */ - unsigned int pairAStatus : 3; /* 1E.C800.E:C RO */ - /* (after running cable diags) - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair D - 010= Connected to Pair C - 001= Connected to Pair B - 000= OK - - OR: - - (after running component diags) - 100 = TX pin open - 011= TX bias open - 010= Capacitor short - 001= Inductor open - 000= OK */ - unsigned int reserved0 : 1; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C801.7:0 RO Pair A Reflection #2 [7:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u1.bits_1.pairAReflection_2 - - - - The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair A - - Notes: - The distance to this reflection is given in See Global Reserved Status 1: Address 1E.C870 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairAReflection_2 : 8; /* 1E.C801.7:0 RO */ - /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair A */ - /*! \brief 1E.C801.F:8 RO Pair A Reflection #1 [7:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u1.bits_1.pairAReflection_1 - - - - The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair A - - Notes: - The distance to this reflection is given in See Global Reserved Status 1: Address 1E.C870 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairAReflection_1 : 8; /* 1E.C801.F:8 RO */ - /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair A */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C802.F:0 RO Impulse Response MSW [F:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u2.bits_2.impulseResponseMSW - - - - The MSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type in 1E.C470.E:D - - - Notes: - See 1E.C470 for more information */ - unsigned int impulseResponseMSW : 16; /* 1E.C802.F:0 RO */ - /* The MSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type in 1E.C470.E:D - */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C803.7:0 RO Pair B Reflection #2 [7:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u3.bits_3.pairBReflection_2 - - - - The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair B - - Notes: - The distance to this reflection is given in See Global Reserved Status 2: Address 1E.C871 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairBReflection_2 : 8; /* 1E.C803.7:0 RO */ - /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair B */ - /*! \brief 1E.C803.F:8 RO Pair B Reflection #1 [7:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u3.bits_3.pairBReflection_1 - - - - The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair B - - Notes: - The distance to this reflection is given in See Global Reserved Status 2: Address 1E.C871 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairBReflection_1 : 8; /* 1E.C803.F:8 RO */ - /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair B */ - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C804.F:0 RO Impulse Response LSW [F:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u4.bits_4.impulseResponseLSW - - - - The LSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type specified in 1E.C470.E:D - - - Notes: - See 1E.C470 for more information */ - unsigned int impulseResponseLSW : 16; /* 1E.C804.F:0 RO */ - /* The LSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type specified in 1E.C470.E:D - */ - } bits_4; - uint16_t word_4; - } u4; - /*! \brief Union for bit and word level access of word 5 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C805.7:0 RO Pair C Reflection #2 [7:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u5.bits_5.pairCReflection_2 - - - - The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair C - - Notes: - The distance to this reflection is given in See Global Reserved Status 3: Address 1E.C872 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairCReflection_2 : 8; /* 1E.C805.7:0 RO */ - /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair C */ - /*! \brief 1E.C805.F:8 RO Pair C Reflection #1 [7:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u5.bits_5.pairCReflection_1 - - - - The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair C - - Notes: - The distance to this reflection is given in See Global Reserved Status 3: Address 1E.C872 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairCReflection_1 : 8; /* 1E.C805.F:8 RO */ - /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair C */ - } bits_5; - uint16_t word_5; - } u5; - /*! \brief Union for bit and word level access of word 6 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C806.F:0 RO Reserved 1 [F:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u6.bits_6.reserved_1 - - - - Reserved for future use - - */ - unsigned int reserved_1 : 16; /* 1E.C806.F:0 RO */ - /* Reserved for future use - */ - } bits_6; - uint16_t word_6; - } u6; - /*! \brief Union for bit and word level access of word 7 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C807.7:0 RO Pair D Reflection #2 [7:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u7.bits_7.pairDReflection_2 - - - - The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair D - - Notes: - The distance to this reflection is given in See Global Reserved Status 4: Address 1E.C873 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairDReflection_2 : 8; /* 1E.C807.7:0 RO */ - /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair D */ - /*! \brief 1E.C807.F:8 RO Pair D Reflection #1 [7:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u7.bits_7.pairDReflection_1 - - - - The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair D - - Notes: - The distance to this reflection is given in See Global Reserved Status 4: Address 1E.C873 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairDReflection_1 : 8; /* 1E.C807.F:8 RO */ - /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair D */ - } bits_7; - uint16_t word_7; - } u7; - /*! \brief Union for bit and word level access of word 8 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C808.F:0 RO Reserved 2[F:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u8.bits_8.reserved_2 - - - - Reserved for future use - - */ - unsigned int reserved_2 : 16; /* 1E.C808.F:0 RO */ - /* Reserved for future use - */ - } bits_8; - uint16_t word_8; - } u8; -} AQ_GlobalCableDiagnosticStatus_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Thermal Status: 1E.C820 */ -/* Global Thermal Status: 1E.C820 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Thermal Status */ - union - { - struct - { - /*! \brief 1E.C820.F:0 RO Temperature [F:0] - AQ_GlobalThermalStatus_APPIA.u0.bits_0.temperature - - - - [F:0] of temperature - - - Notes: - 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 70 degreesC. This is a mirror of the XENPAK register 1.A060 - 1.A061. The mirror is performed in H/W. */ - unsigned int temperature : 16; /* 1E.C820.F:0 RO */ - /* [F:0] of temperature - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Thermal Status */ - union - { - struct - { - /*! \brief 1E.C821.0 RO Temperature Ready - AQ_GlobalThermalStatus_APPIA.u1.bits_1.temperatureReady - - - - 1 = Temperature measurement is valid - - - Notes: - This is a mirror of the XENPAK register 1.A06E. */ - unsigned int temperatureReady : 1; /* 1E.C821.0 RO */ - /* 1 = Temperature measurement is valid - */ - unsigned int reserved0 : 15; - } bits_1; - uint16_t word_1; - } u1; -} AQ_GlobalThermalStatus_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global General Status: 1E.C830 */ -/* Global General Status: 1E.C830 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global General Status */ - union - { - struct - { - unsigned int reserved1 : 11; - /*! \brief 1E.C830.B RO Low Temperature Warning State - AQ_GlobalGeneralStatus_APPIA.u0.bits_0.lowTemperatureWarningState - - - - 1 = Low temperature warning threshold has been exceeded - - Notes: - In XENPAK mode, F/W will copy this register to the 1.A074.6 register. - - */ - unsigned int lowTemperatureWarningState : 1; /* 1E.C830.B RO */ - /* 1 = Low temperature warning threshold has been exceeded */ - /*! \brief 1E.C830.C RO High Temperature Warning State - AQ_GlobalGeneralStatus_APPIA.u0.bits_0.highTemperatureWarningState - - - - 1 = High temperature warning threshold has been exceeded - - Notes: - In XENPAK mode, F/W will copy this register to the 1.A074.7 register. - - */ - unsigned int highTemperatureWarningState : 1; /* 1E.C830.C RO */ - /* 1 = High temperature warning threshold has been exceeded */ - /*! \brief 1E.C830.D RO Low Temperature Failure State - AQ_GlobalGeneralStatus_APPIA.u0.bits_0.lowTemperatureFailureState - - - - 1 = Low temperature failure threshold has been exceeded - - Notes: - In XENPAK mode, F/W will copy this register to the 1.A070.6 register. - - */ - unsigned int lowTemperatureFailureState : 1; /* 1E.C830.D RO */ - /* 1 = Low temperature failure threshold has been exceeded */ - /*! \brief 1E.C830.E RO High Temperature Failure State - AQ_GlobalGeneralStatus_APPIA.u0.bits_0.highTemperatureFailureState - - - - 1 = High temperature failure threshold has been exceeded - - Notes: - In XENPAK mode, F/W will copy this register to the 1.A070.7 register. - - */ - unsigned int highTemperatureFailureState : 1; /* 1E.C830.E RO */ - /* 1 = High temperature failure threshold has been exceeded */ - unsigned int reserved0 : 1; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global General Status */ - union - { - struct - { - unsigned int reserved0 : 15; - /*! \brief 1E.C831.F RO Processor Intensive MDIO Operation In- Progress - AQ_GlobalGeneralStatus_APPIA.u1.bits_1.processorIntensiveMdioOperationIn_Progress - - - - 1 = PHY microprocessor is busy with a processor-intensive MDIO operation - 0 = Processor-intensive MDIO operation completed - - - Notes: - This bit should may be used with certain processor-intensive MDIO commands (such as Loopbacks, Test Modes, Low power modes, Tx-Disable, Restart autoneg, Cable Diagnostics, etc.) that take longer than an MDIO cycle to complete. Upon receiving an MDIO command that involves the PHY's microprocessor, this bit is set, and when the command is completed, this bit is cleared. - - NOTE!!! This bit should be checked only after 1 ms of issuing a processor-intensive MDIO operation. - - The list of operations that set this bit are as follows: - - 1.0.0, PMA Loopback - 1.0.B, Low power mode - 1.9.4:0, Tx Disable - 1.84, 10G Test modes - 1.8000.5, XENPAK Control - 1.9000, XENPAK Rx Fault Enable - 1.9002, XENPAK Alarm Enable - 1.E400.F, External loopback - 3.0.B, Low power mode - 3.0.E, System PCS loopback - 3.C471.5, PRBS Test - 3.C471.6, PRBS Test - 3.E471.5, PRBS Test - 3.E471.6, PRBS Test - 4.0.B, Low power mode - 4.0.E, PHY-XS network loopback - 4.C440, Output clock control, Load SERDES parameters - 4.F802.E, System loopback - 4.C444.F:B, Loopback Control - 4.C444.4:2, Packet generation - 4.C445.C, SERDES calibration - 7.0.9, Restart autonegotiation - 1D.C280, 1G/100M Network loopback - 1D.C500, 1G System loopback - 1D.C501, 1G / 100M Test modes */ - unsigned int processorIntensiveMdioOperationIn_Progress : 1; /* 1E.C831.F RO */ - /* 1 = PHY microprocessor is busy with a processor-intensive MDIO operation - 0 = Processor-intensive MDIO operation completed - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_GlobalGeneralStatus_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Pin Status: 1E.C840 */ -/* Global Pin Status: 1E.C840 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Pin Status */ - union - { - struct - { - /*! \brief 1E.C840.5:0 RO LED Pullup State [5:0] - AQ_GlobalPinStatus_APPIA.u0.bits_0.ledPullupState - - - - 1 = LED output pin is pulled high - 0 = LED output pin is pulled low - - */ - unsigned int ledPullupState : 6; /* 1E.C840.5:0 RO */ - /* 1 = LED output pin is pulled high - 0 = LED output pin is pulled low - */ - unsigned int reserved3 : 1; - /*! \brief 1E.C840.7 RO Tx Enable - AQ_GlobalPinStatus_APPIA.u0.bits_0.txEnable - - - - Current Value of Tx Enable pin - - - Notes: - 0 = Disable Transmitter */ - unsigned int txEnable : 1; /* 1E.C840.7 RO */ - /* Current Value of Tx Enable pin - */ - unsigned int reserved2 : 1; - /*! \brief 1E.C840.9 RO Package Connectivity - AQ_GlobalPinStatus_APPIA.u0.bits_0.packageConnectivity - - - - Value of the package connection pin - - */ - unsigned int packageConnectivity : 1; /* 1E.C840.9 RO */ - /* Value of the package connection pin - */ - unsigned int reserved1 : 3; - /*! \brief 1E.C840.E:D RO MDIO Boot Load [1:0] - AQ_GlobalPinStatus_APPIA.u0.bits_0.mdioBootLoad - - - - Value of MDIO Boot Load pins - - 0x3 = PHY #0 Slave Daisy Chain Boot - 0x2 = PHY #0 Master Daisy Chain Boot from Flash - 0x1 = MDIO Boot Load - 0x0 = Boot from Flash (PHY #0 only) - - - Notes: - NOTES: - - PHY #0 is the primary PHY, and PHY #1 is the secondary PHY - - PHY #1 is always in Slave Daisy Chain Boot from Flash when set to 0x2 or 0x3. */ - unsigned int mdioBootLoad : 2; /* 1E.C840.E:D RO */ - /* Value of MDIO Boot Load pins - - 0x3 = PHY #0 Slave Daisy Chain Boot - 0x2 = PHY #0 Master Daisy Chain Boot from Flash - 0x1 = MDIO Boot Load - 0x0 = Boot from Flash (PHY #0 only) - */ - unsigned int reserved0 : 1; - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalPinStatus_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Daisy Chain Status: 1E.C842 */ -/* Global Daisy Chain Status: 1E.C842 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Daisy Chain Status */ - union - { - struct - { - /*! \brief 1E.C842.F:0 RO Rx Daisy Chain Calculated CRC [F:0] - AQ_GlobalDaisyChainStatus_APPIA.u0.bits_0.rxDaisyChainCalculatedCrc - - - - Rx Daisy Chain Calculated CRC - - - Notes: - This is the calculated daisy chain CRC. */ - unsigned int rxDaisyChainCalculatedCrc : 16; /* 1E.C842.F:0 RO */ - /* Rx Daisy Chain Calculated CRC - */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalDaisyChainStatus_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Fault Message: 1E.C850 */ -/* Global Fault Message: 1E.C850 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Fault Message */ - union - { - struct - { - /*! \brief 1E.C850.F:0 RO Message [F:0] - AQ_GlobalFaultMessage_APPIA.u0.bits_0.message - - - - Error code describing fault - - Notes: - Code 0x8001: Firmware not compatible with chip architecture. This fault occurs when firmware compiled for a different Tensilica core is loaded. - Code 0x8002: VCO calibration failed. This occurs when the main PLLs on chip fail to lock: this is not possible to trigger. - Code 0x8003: XAUI calibration failed. This occurs when the XAUI PLLs fail to lock: this is not possible to trigger. - Code 0x8004: Failed to set operating voltages via PMBus. This only occurs when the processor has control over power supply voltage via an attached PMBus device and there is a protocol error on the I2C bus: this is not possible to trigger. - Code 0x8005: Unexpected device ID. This occurs if the device ID programmed into the internal E-Fuse registers in not valid: this is not possible to trigger. - Code 0x8006: Computed checksum does not match expected checksum. This occurs when the FLASH checksum check performed at boot time fails. This only occurs when the system boots from FLASH. - Code 0x8007: Detected a bit error in static memory. To trigger, corrupt one of the static regions. - Code 0xC001: Illegal Instruction exception. This occurs when the processor attempts to execute an illegal instruction. To trigger this, write an illegal instruction to program memory. It's possible that the bit error check will trigger before the illegal instruction is executed. - Code 0xC002 Instruction Fetch Error. Internal physical address or a data error during instruction fetch: this is not possible to trigger. - Code 0xC003 Load Store Error. Internal physical address or data error during load store operation: this is not possible to trigger.. - Code 0xC004 Privileged Instruction. Attempt to execute a privileged operation without sufficient privilege: this is not possible to trigger. - Code 0xC005 Unaligned Load or Store. Attempt to load or store data at an address which cannot be handled due to alignment: this is not possible to trigger. - Code 0xC006 Instruction fetch from prohibited space: this is not possible to trigger. - Code 0xC007 Data load from prohibited space: this is not possible to trigger. - Code 0xC008 Data store into prohibited space: this is not possible to trigger. */ - unsigned int message : 16; /* 1E.C850.F:0 RO */ - /* Error code describing fault */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalFaultMessage_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Primary Status: 1E.C851 */ -/* Global Primary Status: 1E.C851 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Primary Status */ - union - { - struct - { - /*! \brief 1E.C851.0 RO Primary Status - AQ_GlobalPrimaryStatus_APPIA.u0.bits_0.primaryStatus - - - - 1 = PHY is the primary PHY - 0 = PHY is is secondary PHY - - */ - unsigned int primaryStatus : 1; /* 1E.C851.0 RO */ - /* 1 = PHY is the primary PHY - 0 = PHY is is secondary PHY - */ - unsigned int reserved0 : 15; - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalPrimaryStatus_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Cable Diagnostic Impedance: 1E.C880 */ -/* Global Cable Diagnostic Impedance: 1E.C880 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Cable Diagnostic Impedance */ - union - { - struct - { - /*! \brief 1E.C880.2:0 RO Pair A Reflection #4 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.pairAReflection_4 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the fourth worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ - unsigned int pairAReflection_4 : 3; /* 1E.C880.2:0 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C880.3 RO Reserved 4 - AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.reserved_4 - - - - Reserved for future use - - */ - unsigned int reserved_4 : 1; /* 1E.C880.3 RO */ - /* Reserved for future use - */ - /*! \brief 1E.C880.6:4 RO Pair A Reflection #3 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.pairAReflection_3 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the third worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ - unsigned int pairAReflection_3 : 3; /* 1E.C880.6:4 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C880.7 RO Reserved 3 - AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.reserved_3 - - - - Reserved for future use - - */ - unsigned int reserved_3 : 1; /* 1E.C880.7 RO */ - /* Reserved for future use - */ - /*! \brief 1E.C880.A:8 RO Pair A Reflection #2 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.pairAReflection_2 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the second worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ - unsigned int pairAReflection_2 : 3; /* 1E.C880.A:8 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C880.B RO Reserved 2 - AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.reserved_2 - - - - Reserved for future use - - */ - unsigned int reserved_2 : 1; /* 1E.C880.B RO */ - /* Reserved for future use - */ - /*! \brief 1E.C880.E:C RO Pair A Reflection #1 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.pairAReflection_1 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the first worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ - unsigned int pairAReflection_1 : 3; /* 1E.C880.E:C RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C880.F RO Reserved 1 - AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.reserved_1 - - - - Reserved for future use - - */ - unsigned int reserved_1 : 1; /* 1E.C880.F RO */ - /* Reserved for future use - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Cable Diagnostic Impedance */ - union - { - struct - { - /*! \brief 1E.C881.2:0 RO Pair B Reflection #4 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.pairBReflection_4 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the fourth worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ - unsigned int pairBReflection_4 : 3; /* 1E.C881.2:0 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C881.3 RO Reserved 8 - AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.reserved_8 - - - - Reserved for future use - - */ - unsigned int reserved_8 : 1; /* 1E.C881.3 RO */ - /* Reserved for future use - */ - /*! \brief 1E.C881.6:4 RO Pair B Reflection #3 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.pairBReflection_3 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the third worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ - unsigned int pairBReflection_3 : 3; /* 1E.C881.6:4 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C881.7 RO Reserved 7 - AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.reserved_7 - - - - Reserved for future use - - */ - unsigned int reserved_7 : 1; /* 1E.C881.7 RO */ - /* Reserved for future use - */ - /*! \brief 1E.C881.A:8 RO Pair B Reflection #2 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.pairBReflection_2 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the second worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ - unsigned int pairBReflection_2 : 3; /* 1E.C881.A:8 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C881.B RO Reserved 6 - AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.reserved_6 - - - - Reserved for future use - - */ - unsigned int reserved_6 : 1; /* 1E.C881.B RO */ - /* Reserved for future use - */ - /*! \brief 1E.C881.E:C RO Pair B Reflection #1 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.pairBReflection_1 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the first worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ - unsigned int pairBReflection_1 : 3; /* 1E.C881.E:C RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C881.F RO Reserved 5 - AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.reserved_5 - - - - Reserved for future use - - */ - unsigned int reserved_5 : 1; /* 1E.C881.F RO */ - /* Reserved for future use - */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global Cable Diagnostic Impedance */ - union - { - struct - { - /*! \brief 1E.C882.2:0 RO Pair C Reflection #4 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.pairCReflection_4 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the fourth worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ - unsigned int pairCReflection_4 : 3; /* 1E.C882.2:0 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C882.3 RO Reserved 12 - AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.reserved_12 - - - - Reserved for future use - - */ - unsigned int reserved_12 : 1; /* 1E.C882.3 RO */ - /* Reserved for future use - */ - /*! \brief 1E.C882.6:4 RO Pair C Reflection #3 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.pairCReflection_3 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the third worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ - unsigned int pairCReflection_3 : 3; /* 1E.C882.6:4 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C882.7 RO Reserved 11 - AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.reserved_11 - - - - Reserved for future use - - */ - unsigned int reserved_11 : 1; /* 1E.C882.7 RO */ - /* Reserved for future use - */ - /*! \brief 1E.C882.A:8 RO Pair C Reflection #2 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.pairCReflection_2 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the second worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ - unsigned int pairCReflection_2 : 3; /* 1E.C882.A:8 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C882.B RO Reserved 10 - AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.reserved_10 - - - - Reserved for future use - - */ - unsigned int reserved_10 : 1; /* 1E.C882.B RO */ - /* Reserved for future use - */ - /*! \brief 1E.C882.E:C RO Pair C Reflection #1 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.pairCReflection_1 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the first worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ - unsigned int pairCReflection_1 : 3; /* 1E.C882.E:C RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C882.F RO Reserved 9 - AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.reserved_9 - - - - Reserved for future use - - */ - unsigned int reserved_9 : 1; /* 1E.C882.F RO */ - /* Reserved for future use - */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global Cable Diagnostic Impedance */ - union - { - struct - { - /*! \brief 1E.C883.2:0 RO Pair D Reflection #4 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.pairDReflection_4 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the fourth worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ - unsigned int pairDReflection_4 : 3; /* 1E.C883.2:0 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C883.3 RO Reserved 16 - AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.reserved_16 - - - - Reserved for future use - - */ - unsigned int reserved_16 : 1; /* 1E.C883.3 RO */ - /* Reserved for future use - */ - /*! \brief 1E.C883.6:4 RO Pair D Reflection #3 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.pairDReflection_3 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the third worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ - unsigned int pairDReflection_3 : 3; /* 1E.C883.6:4 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C883.7 RO Reserved 15 - AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.reserved_15 - - - - Reserved for future use - - */ - unsigned int reserved_15 : 1; /* 1E.C883.7 RO */ - /* Reserved for future use - */ - /*! \brief 1E.C883.A:8 RO Pair D Reflection #2 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.pairDReflection_2 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the second worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ - unsigned int pairDReflection_2 : 3; /* 1E.C883.A:8 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C883.B RO Reserved 14 - AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.reserved_14 - - - - Reserved for future use - - */ - unsigned int reserved_14 : 1; /* 1E.C883.B RO */ - /* Reserved for future use - */ - /*! \brief 1E.C883.E:C RO Pair D Reflection #1 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.pairDReflection_1 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the first worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ - unsigned int pairDReflection_1 : 3; /* 1E.C883.E:C RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C883.F RO Reserved 13 - AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.reserved_13 - - - - Reserved for future use - - */ - unsigned int reserved_13 : 1; /* 1E.C883.F RO */ - /* Reserved for future use - */ - } bits_3; - uint16_t word_3; - } u3; -} AQ_GlobalCableDiagnosticImpedance_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Status: 1E.C884 */ -/* Global Status: 1E.C884 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Status */ - union - { - struct - { - /*! \brief 1E.C884.7:0 RO Cable Length [7:0] - AQ_GlobalStatus_APPIA.u0.bits_0.cableLength - - - - The estimated length of the cable in meters - - - Notes: - The length of the cable shown here is estimated from the cable diagnostic engine and should be accurate to +/-1m. */ - unsigned int cableLength : 8; /* 1E.C884.7:0 RO */ - /* The estimated length of the cable in meters - */ - /*! \brief 1E.C884.F:8 RO Reserved Status 0 [7:0] - AQ_GlobalStatus_APPIA.u0.bits_0.reservedStatus_0 - - - - Reserved for future use - - */ - unsigned int reservedStatus_0 : 8; /* 1E.C884.F:8 RO */ - /* Reserved for future use - */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalStatus_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Reserved Status: 1E.C885 */ -/* Global Reserved Status: 1E.C885 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Reserved Status */ - union - { - struct - { - /*! \brief 1E.C885.7:0 ROSPD ROM Revision [7:0] - AQ_GlobalReservedStatus_APPIA.u0.bits_0.romRevision - - Provisionable Default = 0x00 - - ROM Revision Number - - - Notes: - Customers may receive multiple ROM images that differ only in their provisioning. This field is used to differentiate those images. This field is used in conjunction with the firmware major and minor revision numbers to uniquely identify ROM images. */ - unsigned int romRevision : 8; /* 1E.C885.7:0 ROSPD Provisionable Default = 0x00 */ - /* ROM Revision Number - */ - /*! \brief 1E.C885.9:8 ROSPD XENPAK NVR Status [1:0] - AQ_GlobalReservedStatus_APPIA.u0.bits_0.xenpakNvrStatus - - Provisionable Default = 0x0 - - Status of XENPAK NVR: - 0: NVR not enabled - 1: Last NVR operation succeeded - 2: Last NVR operation failed - 3: Reserved - - - Notes: - XENPAK register space is mirrored in NVR (SPI ROM). This register indicates the status of the last NVR operation. */ - unsigned int xenpakNvrStatus : 2; /* 1E.C885.9:8 ROSPD Provisionable Default = 0x0 */ - /* Status of XENPAK NVR: - 0: NVR not enabled - 1: Last NVR operation succeeded - 2: Last NVR operation failed - 3: Reserved - */ - /*! \brief 1E.C885.F:A RO Nearly Seconds MSW[5:0] - AQ_GlobalReservedStatus_APPIA.u0.bits_0.nearlySecondsMSW - - - - Bits 16 to 21 of the 22 bit "Nearly Seconds" uptime counter. - - - Notes: - The "Nearly Seconds" counter is incremented every 1024 milliseconds. */ - unsigned int nearlySecondsMSW : 6; /* 1E.C885.F:A RO */ - /* Bits 16 to 21 of the 22 bit "Nearly Seconds" uptime counter. - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Reserved Status */ - union - { - struct - { - /*! \brief 1E.C886.F:0 RO Nearly Seconds LSW[F:0] - AQ_GlobalReservedStatus_APPIA.u1.bits_1.nearlySecondsLSW - - - - Bits 0 to 15 of the 22 bit "Nearly Seconds" uptime counter. - - - Notes: - The "Nearly Seconds" counter is incremented every 1024 milliseconds. */ - unsigned int nearlySecondsLSW : 16; /* 1E.C886.F:0 RO */ - /* Bits 0 to 15 of the 22 bit "Nearly Seconds" uptime counter. - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_GlobalReservedStatus_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Alarms: 1E.CC00 */ -/* Global Alarms: 1E.CC00 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Alarms */ - union - { - struct - { - /*! \brief 1E.CC00.0 LH Reserved Alarm D - AQ_GlobalAlarms_APPIA.u0.bits_0.reservedAlarmD - - - - Reserved for future use - - */ - unsigned int reservedAlarmD : 1; /* 1E.CC00.0 LH */ - /* Reserved for future use - */ - /*! \brief 1E.CC00.1 LH Reserved Alarm C - AQ_GlobalAlarms_APPIA.u0.bits_0.reservedAlarmC - - - - Reserved for future use - - */ - unsigned int reservedAlarmC : 1; /* 1E.CC00.1 LH */ - /* Reserved for future use - */ - /*! \brief 1E.CC00.2 LH Reserved Alarm B - AQ_GlobalAlarms_APPIA.u0.bits_0.reservedAlarmB - - - - Reserved for future use - - */ - unsigned int reservedAlarmB : 1; /* 1E.CC00.2 LH */ - /* Reserved for future use - */ - /*! \brief 1E.CC00.3 LH Reserved Alarm A - AQ_GlobalAlarms_APPIA.u0.bits_0.reservedAlarmA - - - - Reserved for future use - - */ - unsigned int reservedAlarmA : 1; /* 1E.CC00.3 LH */ - /* Reserved for future use - */ - /*! \brief 1E.CC00.4 LH Device Fault - AQ_GlobalAlarms_APPIA.u0.bits_0.deviceFault - - - - 1 = Fault - - Notes: - When set, a fault has been detected by the uP and the associated 16 bit error code is visible in See Global Configuration Fault Message: Address 1E.C850 */ - unsigned int deviceFault : 1; /* 1E.CC00.4 LH */ - /* 1 = Fault */ - unsigned int reserved2 : 1; - /*! \brief 1E.CC00.6 LH Reset completed - AQ_GlobalAlarms_APPIA.u0.bits_0.resetCompleted - - - - 1 = Chip wide reset completed - - Notes: - This bit is set by the microprocessor when it has completed it's initialization sequence. This bit is mirrored in 1.CC02.0 */ - unsigned int resetCompleted : 1; /* 1E.CC00.6 LH */ - /* 1 = Chip wide reset completed */ - unsigned int reserved1 : 4; - /*! \brief 1E.CC00.B LH Low Temperature Warning - AQ_GlobalAlarms_APPIA.u0.bits_0.lowTemperatureWarning - - - - 1 = Low temperature warning threshold has been exceeded - - - Notes: - - - - - These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ - unsigned int lowTemperatureWarning : 1; /* 1E.CC00.B LH */ - /* 1 = Low temperature warning threshold has been exceeded - */ - /*! \brief 1E.CC00.C LH High Temperature Warning - AQ_GlobalAlarms_APPIA.u0.bits_0.highTemperatureWarning - - - - 1 = High temperature warning threshold has been exceeded - - - Notes: - - - - - These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ - unsigned int highTemperatureWarning : 1; /* 1E.CC00.C LH */ - /* 1 = High temperature warning threshold has been exceeded - */ - /*! \brief 1E.CC00.D LH Low Temperature Failure - AQ_GlobalAlarms_APPIA.u0.bits_0.lowTemperatureFailure - - - - 1 = Low temperature failure threshold has been exceeded - - - Notes: - - - - - These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ - unsigned int lowTemperatureFailure : 1; /* 1E.CC00.D LH */ - /* 1 = Low temperature failure threshold has been exceeded - */ - /*! \brief 1E.CC00.E LH High Temperature Failure - AQ_GlobalAlarms_APPIA.u0.bits_0.highTemperatureFailure - - - - 1 = High temperature failure threshold has been exceeded - - - Notes: - - - - - These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ - unsigned int highTemperatureFailure : 1; /* 1E.CC00.E LH */ - /* 1 = High temperature failure threshold has been exceeded - */ - unsigned int reserved0 : 1; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Alarms */ - union - { - struct - { - /*! \brief 1E.CC01.0 LH Diagnostic Alarm - AQ_GlobalAlarms_APPIA.u1.bits_1.diagnosticAlarm - - - - 1 = Alarm triggered by a write to 1E.C470.7 - - - Notes: - A diagnostic alarm use to test system alarm circuitry */ - unsigned int diagnosticAlarm : 1; /* 1E.CC01.0 LH */ - /* 1 = Alarm triggered by a write to 1E.C470.7 - */ - unsigned int reserved1 : 6; - /*! \brief 1E.CC01.7 LH MDIO Command Handling Overflow - AQ_GlobalAlarms_APPIA.u1.bits_1.mdioCommandHandlingOverflow - - - - 1 = PHY was issued more MDIO requests than it could service in it's request buffer - - - Notes: - Assertion of this bit means that more MDIO commands were issued than FW could handle. */ - unsigned int mdioCommandHandlingOverflow : 1; /* 1E.CC01.7 LH */ - /* 1 = PHY was issued more MDIO requests than it could service in it's request buffer - */ - /*! \brief 1E.CC01.C:8 LH Reserved Alarms [4:0] - AQ_GlobalAlarms_APPIA.u1.bits_1.reservedAlarms - - - - Reserved for future use - - */ - unsigned int reservedAlarms : 5; /* 1E.CC01.C:8 LH */ - /* Reserved for future use - */ - /*! \brief 1E.CC01.D RO XENPAK Alarm - AQ_GlobalAlarms_APPIA.u1.bits_1.xenpakAlarm - - - - 1 = XENPAK Alarm - - - Notes: - This alarm is performed by H/W. */ - unsigned int xenpakAlarm : 1; /* 1E.CC01.D RO */ - /* 1 = XENPAK Alarm - */ - /*! \brief 1E.CC01.E LH Smart Power-Down Entered - AQ_GlobalAlarms_APPIA.u1.bits_1.smartPower_downEntered - - - - 1 = Smart Power-Down State Entered - - - Notes: - When this bit is set, it indicates that the Smart Power-Down state was entered */ - unsigned int smartPower_downEntered : 1; /* 1E.CC01.E LH */ - /* 1 = Smart Power-Down State Entered - */ - unsigned int reserved0 : 1; - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global Alarms */ - union - { - struct - { - /*! \brief 1E.CC02.0 LH Watchdog Timer Alarm - AQ_GlobalAlarms_APPIA.u2.bits_2.watchdogTimerAlarm - - - - 1 = Watchdog timer alarm - - */ - unsigned int watchdogTimerAlarm : 1; /* 1E.CC02.0 LH */ - /* 1 = Watchdog timer alarm - */ - /*! \brief 1E.CC02.1 LH MDIO Timeout Error - AQ_GlobalAlarms_APPIA.u2.bits_2.mdioTimeoutError - - - - 1 = MDIO timeout detected - - */ - unsigned int mdioTimeoutError : 1; /* 1E.CC02.1 LH */ - /* 1 = MDIO timeout detected - */ - /*! \brief 1E.CC02.2 LH MDIO MMD Error - AQ_GlobalAlarms_APPIA.u2.bits_2.mdioMMD_Error - - - - 1 = Invalid MMD address detected - - */ - unsigned int mdioMMD_Error : 1; /* 1E.CC02.2 LH */ - /* 1 = Invalid MMD address detected - */ - unsigned int reserved2 : 2; - /*! \brief 1E.CC02.5 LRF Tx Enable State Change - AQ_GlobalAlarms_APPIA.u2.bits_2.txEnableStateChange - - - - 1 = TX_EN pin has changed state - - */ - unsigned int txEnableStateChange : 1; /* 1E.CC02.5 LRF */ - /* 1 = TX_EN pin has changed state - */ - unsigned int reserved1 : 2; - /*! \brief 1E.CC02.9:8 LH uP IRAM Parity Error [1:0] - AQ_GlobalAlarms_APPIA.u2.bits_2.upIramParityError - - - - 1 = Parity error detected in the uP IRAM - - - Notes: - Bit 0 indicates a parity error was detected in the uP IRAM but was corrected. - Bit 1 indicates a multiple parity errors were detected in the uP IRAM and could not be corrected. - The uP IRAM is protected with ECC. */ - unsigned int upIramParityError : 2; /* 1E.CC02.9:8 LH */ - /* 1 = Parity error detected in the uP IRAM - */ - /*! \brief 1E.CC02.A LH uP DRAM Parity Error - AQ_GlobalAlarms_APPIA.u2.bits_2.upDramParityError - - - - 1 = Parity error detected in the uP DRAM - - */ - unsigned int upDramParityError : 1; /* 1E.CC02.A LH */ - /* 1 = Parity error detected in the uP DRAM - */ - unsigned int reserved0 : 3; - /*! \brief 1E.CC02.E LH Mailbox Operation: Complete - AQ_GlobalAlarms_APPIA.u2.bits_2.mailboxOperation_Complete - - - - 1 = Mailbox operation is complete - - - Notes: - Mailbox interface is ready interrupt for registers See Global Vendor Specific Control - Address 1E.C000 - See Global Vendor Specific Provisioning 5 - Address 1E.C404 */ - unsigned int mailboxOperation_Complete : 1; /* 1E.CC02.E LH */ - /* 1 = Mailbox operation is complete - */ - /*! \brief 1E.CC02.F LH NVR Operation Complete - AQ_GlobalAlarms_APPIA.u2.bits_2.nvrOperationComplete - - - - 1 = NVR operation is complete - - - Notes: - NVR interface is ready interrupt for registers See Global NVR Interface 1: Address 1E.100 - See Global NVR Provisioning Data MSW - Address 1E.17 . */ - unsigned int nvrOperationComplete : 1; /* 1E.CC02.F LH */ - /* 1 = NVR operation is complete - */ - } bits_2; - uint16_t word_2; - } u2; -} AQ_GlobalAlarms_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Interrupt Mask: 1E.D400 */ -/* Global Interrupt Mask: 1E.D400 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Interrupt Mask */ - union - { - struct - { - /*! \brief 1E.D400.0 R/WPD Reserved Alarm D Mask - AQ_GlobalInterruptMask_APPIA.u0.bits_0.reservedAlarmDMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int reservedAlarmDMask : 1; /* 1E.D400.0 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - /*! \brief 1E.D400.1 R/WPD Reserved Alarm C Mask - AQ_GlobalInterruptMask_APPIA.u0.bits_0.reservedAlarmCMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int reservedAlarmCMask : 1; /* 1E.D400.1 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - /*! \brief 1E.D400.2 R/WPD Reserved Alarm B Mask - AQ_GlobalInterruptMask_APPIA.u0.bits_0.reservedAlarmBMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int reservedAlarmBMask : 1; /* 1E.D400.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - /*! \brief 1E.D400.3 R/WPD Reserved Alarm A Mask - AQ_GlobalInterruptMask_APPIA.u0.bits_0.reservedAlarmAMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int reservedAlarmAMask : 1; /* 1E.D400.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - /*! \brief 1E.D400.4 R/WPD Device Fault Mask - AQ_GlobalInterruptMask_APPIA.u0.bits_0.deviceFaultMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int deviceFaultMask : 1; /* 1E.D400.4 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - unsigned int reserved2 : 1; - /*! \brief 1E.D400.6 R/WPD Reset completed Mask - AQ_GlobalInterruptMask_APPIA.u0.bits_0.resetCompletedMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int resetCompletedMask : 1; /* 1E.D400.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - unsigned int reserved1 : 4; - /*! \brief 1E.D400.B R/WPD Low Temperature Warning Mask - AQ_GlobalInterruptMask_APPIA.u0.bits_0.lowTemperatureWarningMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int lowTemperatureWarningMask : 1; /* 1E.D400.B R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.D400.C R/WPD High Temperature Warning Mask - AQ_GlobalInterruptMask_APPIA.u0.bits_0.highTemperatureWarningMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int highTemperatureWarningMask : 1; /* 1E.D400.C R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.D400.D R/WPD Low Temperature Failure Mask - AQ_GlobalInterruptMask_APPIA.u0.bits_0.lowTemperatureFailureMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int lowTemperatureFailureMask : 1; /* 1E.D400.D R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.D400.E R/WPD High Temperature Failure Mask - AQ_GlobalInterruptMask_APPIA.u0.bits_0.highTemperatureFailureMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int highTemperatureFailureMask : 1; /* 1E.D400.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - unsigned int reserved0 : 1; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Interrupt Mask */ - union - { - struct - { - /*! \brief 1E.D401.0 R/WPD Diagnostic Alarm Mask - AQ_GlobalInterruptMask_APPIA.u1.bits_1.diagnosticAlarmMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int diagnosticAlarmMask : 1; /* 1E.D401.0 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int reserved1 : 6; - /*! \brief 1E.D401.7 R/WPD MDIO Command Handling Overflow Mask - AQ_GlobalInterruptMask_APPIA.u1.bits_1.mdioCommandHandlingOverflowMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int mdioCommandHandlingOverflowMask : 1; /* 1E.D401.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - /*! \brief 1E.D401.C:8 R/WPD Reserved Alarms Mask [4:0] - AQ_GlobalInterruptMask_APPIA.u1.bits_1.reservedAlarmsMask - - Provisionable Default = 0x00 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int reservedAlarmsMask : 5; /* 1E.D401.C:8 R/WPD Provisionable Default = 0x00 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - /*! \brief 1E.D401.D R/WPD XENPAK Alarm Mask - AQ_GlobalInterruptMask_APPIA.u1.bits_1.xenpakAlarmMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int xenpakAlarmMask : 1; /* 1E.D401.D R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.D401.E R/WPD Smart Power-Down Entered Mask - AQ_GlobalInterruptMask_APPIA.u1.bits_1.smartPower_downEnteredMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int smartPower_downEnteredMask : 1; /* 1E.D401.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int reserved0 : 1; - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global Interrupt Mask */ - union - { - struct - { - /*! \brief 1E.D402.0 R/WPD Watchdog Timer Alarm Mask - AQ_GlobalInterruptMask_APPIA.u2.bits_2.watchdogTimerAlarmMask - - Provisionable Default = 0x1 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int watchdogTimerAlarmMask : 1; /* 1E.D402.0 R/WPD Provisionable Default = 0x1 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.D402.1 R/WPD MDIO Timeout Error Mask - AQ_GlobalInterruptMask_APPIA.u2.bits_2.mdioTimeoutErrorMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int mdioTimeoutErrorMask : 1; /* 1E.D402.1 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.D402.2 R/WPD MDIO MMD Error Mask - AQ_GlobalInterruptMask_APPIA.u2.bits_2.mdioMMD_ErrorMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int mdioMMD_ErrorMask : 1; /* 1E.D402.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - unsigned int reserved2 : 2; - /*! \brief 1E.D402.5 R/WPD Tx Enable State Change Mask - AQ_GlobalInterruptMask_APPIA.u2.bits_2.txEnableStateChangeMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int txEnableStateChangeMask : 1; /* 1E.D402.5 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - unsigned int reserved1 : 2; - /*! \brief 1E.D402.9:8 R/WPD uP IRAM Parity Error Mask [1:0] - AQ_GlobalInterruptMask_APPIA.u2.bits_2.upIramParityErrorMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int upIramParityErrorMask : 2; /* 1E.D402.9:8 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - /*! \brief 1E.D402.A R/WPD uP DRAM Parity Error Mask - AQ_GlobalInterruptMask_APPIA.u2.bits_2.upDramParityErrorMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int upDramParityErrorMask : 1; /* 1E.D402.A R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int reserved0 : 3; - /*! \brief 1E.D402.E R/WPD Mailbox Operation Complete Mask - AQ_GlobalInterruptMask_APPIA.u2.bits_2.mailboxOperationCompleteMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - Notes: - Mailbox interface is ready interrupt for registers See Global Vendor Specific Control - Address 1E.C000 - See Global Vendor Specific Provisioning 5 - Address 1E.C404 */ - unsigned int mailboxOperationCompleteMask : 1; /* 1E.D402.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.D402.F R/WPD NVR Operation Complete Mask - AQ_GlobalInterruptMask_APPIA.u2.bits_2.nvrOperationCompleteMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - Notes: - NVR interface is ready interrupt for registers See Global NVR Interface 1: Address 1E.100 - See Global NVR Provisioning Data MSW - Address 1E.17 */ - unsigned int nvrOperationCompleteMask : 1; /* 1E.D402.F R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - } bits_2; - uint16_t word_2; - } u2; -} AQ_GlobalInterruptMask_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Chip-Wide Standard Interrupt Flags: 1E.FC00 */ -/* Global Chip-Wide Standard Interrupt Flags: 1E.FC00 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Chip-Wide Standard Interrupt Flags */ - union - { - struct - { - /*! \brief 1E.FC00.0 RO All Vendor Alarms Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.allVendorAlarmsInterrupt - - - - 1 = Interrupt in all vendor alarms - - - Notes: - An interrupt was generated from status register ( See Global Chip-Wide LASI Vendor Interrupt Flags: Address 1E.FC01 ) and the corresponding mask register. ( See Global Interrupt LASI Mask: Address 1E.FF01 ) */ - unsigned int allVendorAlarmsInterrupt : 1; /* 1E.FC00.0 RO */ - /* 1 = Interrupt in all vendor alarms - */ - unsigned int reserved0 : 5; - /*! \brief 1E.FC00.6 RO GbE Standard Alarms Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.gbeStandardAlarmsInterrupt - - - - 1 = Interrupt in GbE standard alarms - - - Notes: - An interrupt was generated from the TGE core. */ - unsigned int gbeStandardAlarmsInterrupt : 1; /* 1E.FC00.6 RO */ - /* 1 = Interrupt in GbE standard alarms - */ - /*! \brief 1E.FC00.7 RO Autonegotiation Standard Alarms 2 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.autonegotiationStandardAlarms_2Interrupt - - - - 1 = Interrupt in Autonegotiation standard alarms 2 - - - Notes: - An interrupt was generated from status register ( See Autonegotiation 10GBASE-T Status Register - Address 7.21 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ - unsigned int autonegotiationStandardAlarms_2Interrupt : 1; /* 1E.FC00.7 RO */ - /* 1 = Interrupt in Autonegotiation standard alarms 2 - */ - /*! \brief 1E.FC00.8 RO Autonegotiation Standard Alarms 1 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.autonegotiationStandardAlarms_1Interrupt - - - - 1 = Interrupt in Autonegotiation standard alarms 1 - - - Notes: - An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See Autonegotiation Standard LASI Interrupt Mask 1: Address 7.D000 ) */ - unsigned int autonegotiationStandardAlarms_1Interrupt : 1; /* 1E.FC00.8 RO */ - /* 1 = Interrupt in Autonegotiation standard alarms 1 - */ - /*! \brief 1E.FC00.9 RO PHY XS Standard Alarms 2 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.phyXS_StandardAlarms_2Interrupt - - - - 1 = Interrupt in PHY XS standard alarms 2 - - - Notes: - An interrupt was generated from the status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ - unsigned int phyXS_StandardAlarms_2Interrupt : 1; /* 1E.FC00.9 RO */ - /* 1 = Interrupt in PHY XS standard alarms 2 - */ - /*! \brief 1E.FC00.A RO PHY XS Standard Alarms 1 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.phyXS_StandardAlarms_1Interrupt - - - - 1 = Interrupt in PHY XS standard alarms 1 - - - Notes: - An interrupt was generated from the status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ - unsigned int phyXS_StandardAlarms_1Interrupt : 1; /* 1E.FC00.A RO */ - /* 1 = Interrupt in PHY XS standard alarms 1 - */ - /*! \brief 1E.FC00.B RO PCS Standard Alarm 3 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.pcsStandardAlarm_3Interrupt - - - - 1 = Interrupt in PCS standard alarms 3 - - - Notes: - An interrupt was generated from status register ( See PCS 10GBASE-T Status 2 - Address 3.21 ) and the corresponding mask register. ( See PCS Standard Interrupt Mask 1 - Address 3.E021 ) */ - unsigned int pcsStandardAlarm_3Interrupt : 1; /* 1E.FC00.B RO */ - /* 1 = Interrupt in PCS standard alarms 3 - */ - /*! \brief 1E.FC00.C RO PCS Standard Alarm 2 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.pcsStandardAlarm_2Interrupt - - - - 1 = Interrupt in PCS standard alarms 2 - - - Notes: - An interrupt was generated from status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ - unsigned int pcsStandardAlarm_2Interrupt : 1; /* 1E.FC00.C RO */ - /* 1 = Interrupt in PCS standard alarms 2 - */ - /*! \brief 1E.FC00.D RO PCS Standard Alarm 1 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.pcsStandardAlarm_1Interrupt - - - - 1 = Interrupt in PCS standard alarms 1 - - - Notes: - An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ - unsigned int pcsStandardAlarm_1Interrupt : 1; /* 1E.FC00.D RO */ - /* 1 = Interrupt in PCS standard alarms 1 - */ - /*! \brief 1E.FC00.E RO PMA Standard Alarm 2 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.pmaStandardAlarm_2Interrupt - - - - 1 = Interrupt in PMA standard alarms 2 - - - Notes: - An interrupt was generated from either bit 1.8.B or 1.8.A. - An interrupt was generated from status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ - unsigned int pmaStandardAlarm_2Interrupt : 1; /* 1E.FC00.E RO */ - /* 1 = Interrupt in PMA standard alarms 2 - */ - /*! \brief 1E.FC00.F RO PMA Standard Alarm 1 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.pmaStandardAlarm_1Interrupt - - - - 1 = Interrupt in PMA standard alarms 1 - - - Notes: - An interrupt was generated from bit 1.1.2. - An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ - unsigned int pmaStandardAlarm_1Interrupt : 1; /* 1E.FC00.F RO */ - /* 1 = Interrupt in PMA standard alarms 1 - */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalChip_wideStandardInterruptFlags_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Chip-Wide Vendor Interrupt Flags: 1E.FC01 */ -/* Global Chip-Wide Vendor Interrupt Flags: 1E.FC01 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Chip-Wide Vendor Interrupt Flags */ - union - { - struct - { - /*! \brief 1E.FC01.0 RO Global Alarms 3 Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.globalAlarms_3Interrupt - - - - 1 = Interrupt in Global alarms 3 - - - Notes: - An interrupt was generated from status register ( See Global Vendor Alarms 2: Address 1E.CC01 ) and the corresponding mask register. ( See Global LASI Interrupt Mask 2: Address 1E.D401 ) */ - unsigned int globalAlarms_3Interrupt : 1; /* 1E.FC01.0 RO */ - /* 1 = Interrupt in Global alarms 3 - */ - /*! \brief 1E.FC01.1 RO Global Alarms 2 Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.globalAlarms_2Interrupt - - - - 1 = Interrupt in Global alarms 2 - - - Notes: - An interrupt was generated from status register ( See Global Alarms 2: Address 1E.CC01 ) and the corresponding mask register. ( See Global LASI Interrupt Mask 2: Address 1E.D401 ) */ - unsigned int globalAlarms_2Interrupt : 1; /* 1E.FC01.1 RO */ - /* 1 = Interrupt in Global alarms 2 - */ - /*! \brief 1E.FC01.2 RO Global Alarms 1 Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.globalAlarms_1Interrupt - - - - 1 = Interrupt in Global alarms 1 - - - Notes: - An interrupt was generated from status register ( See Global Vendor Alarms 1 - Address 1E.CC00 ) and the corresponding mask register. ( See Global Vendor Interrupt Mask - Address 1E.D400 ) */ - unsigned int globalAlarms_1Interrupt : 1; /* 1E.FC01.2 RO */ - /* 1 = Interrupt in Global alarms 1 - */ - unsigned int reserved0 : 8; - /*! \brief 1E.FC01.B RO GbE Vendor Alarm Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.gbeVendorAlarmInterrupt - - - - 1 = Interrupt in GbE vendor specific alarm - - - Notes: - A GbE alarm was generated. ( See GbE PHY Vendor Global LASI Interrupt Flags 1: Address 1D.FC00 ) */ - unsigned int gbeVendorAlarmInterrupt : 1; /* 1E.FC01.B RO */ - /* 1 = Interrupt in GbE vendor specific alarm - */ - /*! \brief 1E.FC01.C RO Autonegotiation Vendor Alarm Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.autonegotiationVendorAlarmInterrupt - - - - 1 = Interrupt in Autonegotiation vendor specific alarm - - - Notes: - An Autonegotiation alarm was generated. ( See Autonegotiation Vendor Global LASI Interrupt Flags 1: Address 7.FC00 ) */ - unsigned int autonegotiationVendorAlarmInterrupt : 1; /* 1E.FC01.C RO */ - /* 1 = Interrupt in Autonegotiation vendor specific alarm - */ - /*! \brief 1E.FC01.D RO PHY XS Vendor Alarm Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.phyXS_VendorAlarmInterrupt - - - - 1 = Interrupt in PHY XS vendor specific alarm - - - Notes: - A PHY XS alarm was generated. ( See PHY XS Vendor Global LASI Interrupt Flags 1: Address 4.FC00 ) */ - unsigned int phyXS_VendorAlarmInterrupt : 1; /* 1E.FC01.D RO */ - /* 1 = Interrupt in PHY XS vendor specific alarm - */ - /*! \brief 1E.FC01.E RO PCS Vendor Alarm Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.pcsVendorAlarmInterrupt - - - - 1 = Interrupt in PCS vendor specific alarm - - - Notes: - A PCS alarm was generated. ( See PHY XS Vendor Global Interrupt Flags 1- Address 4.F800 ) */ - unsigned int pcsVendorAlarmInterrupt : 1; /* 1E.FC01.E RO */ - /* 1 = Interrupt in PCS vendor specific alarm - */ - /*! \brief 1E.FC01.F RO PMA Vendor Alarm Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.pmaVendorAlarmInterrupt - - - - 1 = Interrupt in PMA vendor specific alarm - - - Notes: - A PMA alarm was generated. ( See PHY XS Vendor Global Interrupt Flags 1- Address 4.F800 ) */ - unsigned int pmaVendorAlarmInterrupt : 1; /* 1E.FC01.F RO */ - /* 1 = Interrupt in PMA vendor specific alarm - */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalChip_wideVendorInterruptFlags_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Interrupt Chip-Wide Standard Mask: 1E.FF00 */ -/* Global Interrupt Chip-Wide Standard Mask: 1E.FF00 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Interrupt Chip-Wide Standard Mask */ - union - { - struct - { - /*! \brief 1E.FF00.0 R/WPD All Vendor Alarms Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.allVendorAlarmsInterruptMask - - Provisionable Default = 0x1 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int allVendorAlarmsInterruptMask : 1; /* 1E.FF00.0 R/WPD Provisionable Default = 0x1 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - unsigned int reserved0 : 5; - /*! \brief 1E.FF00.6 R/WPD Gbe Standard Alarms Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.gbeStandardAlarmsInterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int gbeStandardAlarmsInterruptMask : 1; /* 1E.FF00.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.7 R/WPD Autonegotiation Standard Alarms 2 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.autonegotiationStandardAlarms_2InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int autonegotiationStandardAlarms_2InterruptMask : 1; /* 1E.FF00.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.8 R/WPD Autonegotiation Standard Alarms 1 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.autonegotiationStandardAlarms_1InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int autonegotiationStandardAlarms_1InterruptMask : 1; /* 1E.FF00.8 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.9 R/WPD PHY XS Standard Alarms 2 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.phyXS_StandardAlarms_2InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int phyXS_StandardAlarms_2InterruptMask : 1; /* 1E.FF00.9 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.A R/WPD PHY XS Standard Alarms 1 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.phyXS_StandardAlarms_1InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int phyXS_StandardAlarms_1InterruptMask : 1; /* 1E.FF00.A R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.B R/WPD PCS Standard Alarm 3 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.pcsStandardAlarm_3InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int pcsStandardAlarm_3InterruptMask : 1; /* 1E.FF00.B R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.C R/WPD PCS Standard Alarm 2 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.pcsStandardAlarm_2InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int pcsStandardAlarm_2InterruptMask : 1; /* 1E.FF00.C R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.D R/WPD PCS Standard Alarm 1 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.pcsStandardAlarm_1InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int pcsStandardAlarm_1InterruptMask : 1; /* 1E.FF00.D R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.E R/WPD PMA Standard Alarm 2 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.pmaStandardAlarm_2InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int pmaStandardAlarm_2InterruptMask : 1; /* 1E.FF00.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.F R/WPD PMA Standard Alarm 1 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.pmaStandardAlarm_1InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int pmaStandardAlarm_1InterruptMask : 1; /* 1E.FF00.F R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalInterruptChip_wideStandardMask_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Interrupt Chip-Wide Vendor Mask: 1E.FF01 */ -/* Global Interrupt Chip-Wide Vendor Mask: 1E.FF01 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Interrupt Chip-Wide Vendor Mask */ - union - { - struct - { - /*! \brief 1E.FF01.0 R/WPD Global Alarms 3 Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.globalAlarms_3InterruptMask - - Provisionable Default = 0x1 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int globalAlarms_3InterruptMask : 1; /* 1E.FF01.0 R/WPD Provisionable Default = 0x1 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF01.1 R/WPD Global Alarms 2 Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.globalAlarms_2InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int globalAlarms_2InterruptMask : 1; /* 1E.FF01.1 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF01.2 R/WPD Global Alarms 1 Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.globalAlarms_1InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int globalAlarms_1InterruptMask : 1; /* 1E.FF01.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - unsigned int reserved0 : 8; - /*! \brief 1E.FF01.B R/WPD GbE Vendor Alarm Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.gbeVendorAlarmInterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int gbeVendorAlarmInterruptMask : 1; /* 1E.FF01.B R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF01.C R/WPD Autonegotiation Vendor Alarm Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.autonegotiationVendorAlarmInterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int autonegotiationVendorAlarmInterruptMask : 1; /* 1E.FF01.C R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF01.D R/WPD PHY XS Vendor Alarm Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.phyXS_VendorAlarmInterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int phyXS_VendorAlarmInterruptMask : 1; /* 1E.FF01.D R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF01.E R/WPD PCS Vendor Alarm Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.pcsVendorAlarmInterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int pcsVendorAlarmInterruptMask : 1; /* 1E.FF01.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF01.F R/WPD PMA Vendor Alarm Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.pmaVendorAlarmInterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int pmaVendorAlarmInterruptMask : 1; /* 1E.FF01.F R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalInterruptChip_wideVendorMask_APPIA; - -#endif -/*@}*/ -/*@}*/ diff --git a/qca/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers_Defines.h b/qca/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers_Defines.h deleted file mode 100644 index 9c7bb5cb5..000000000 --- a/qca/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers_Defines.h +++ /dev/null @@ -1,2134 +0,0 @@ -/*! \file -* This file contains the compiler assist macros and doxygen comments -* for the Global Registers block. -*/ - -/*! \defgroup Global_registers_Defines Global Registers Defines -* This module contains the compiler assist macros and doxygen comments -* for the Global Registers block. -*/ -/*********************************************************************** -* Copyright (c) 2015, Aquantia -* -* Permission to use, copy, modify, and/or distribute this software for any -* purpose with or without fee is hereby granted, provided that the above -* copyright notice and this permission notice appear in all copies. -* -* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -* -* $File: //depot/icm/proj/Dena/rev1.0/c/Systems/tools/windows/regMapParser/src/gencheaders.py $ -* -* $Revision: #10 $ -* -* $DateTime: 2014/04/08 16:55:58 $ -* -* $Author: joshd $ -* -* $Label: $ -* -* Description: -* -* This file contains the compiler assist macros for the registers contained in the Global Registers block. -* -* -***********************************************************************/ - - -/*@{*/ -#ifndef AQ_APPIA_GLOBAL_REGS_DEFINES_HEADER -#define AQ_APPIA_GLOBAL_REGS_DEFINES_HEADER - - -/*-----------------------------------------------------------------------------*/ -/*Access macro definitions */ -/*-----------------------------------------------------------------------------*/ -/*! \brief Base register address of structure AQ_GlobalStandardControl_1_APPIA */ -#define AQ_GlobalStandardControl_1_APPIA_baseRegisterAddress 0x0000 -/*! \brief MMD address of structure AQ_GlobalStandardControl_1_APPIA */ -#define AQ_GlobalStandardControl_1_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure softReset in AQ_GlobalStandardControl_1_APPIA */ -#define AQ_GlobalStandardControl_1_APPIA_softReset 0 -/*! \brief Preprocessor variable to relate field to bit position in structure softReset in AQ_GlobalStandardControl_1_APPIA */ -#define bits_AQ_GlobalStandardControl_1_APPIA_softReset u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure softReset in AQ_GlobalStandardControl_1_APPIA */ -#define word_AQ_GlobalStandardControl_1_APPIA_softReset u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure hardReset in AQ_GlobalStandardControl_1_APPIA */ -#define AQ_GlobalStandardControl_1_APPIA_hardReset 0 -/*! \brief Preprocessor variable to relate field to bit position in structure hardReset in AQ_GlobalStandardControl_1_APPIA */ -#define bits_AQ_GlobalStandardControl_1_APPIA_hardReset u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure hardReset in AQ_GlobalStandardControl_1_APPIA */ -#define word_AQ_GlobalStandardControl_1_APPIA_hardReset u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure lowPower in AQ_GlobalStandardControl_1_APPIA */ -#define AQ_GlobalStandardControl_1_APPIA_lowPower 0 -/*! \brief Preprocessor variable to relate field to bit position in structure lowPower in AQ_GlobalStandardControl_1_APPIA */ -#define bits_AQ_GlobalStandardControl_1_APPIA_lowPower u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure lowPower in AQ_GlobalStandardControl_1_APPIA */ -#define word_AQ_GlobalStandardControl_1_APPIA_lowPower u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalStandardDeviceIdentifier_APPIA */ -#define AQ_GlobalStandardDeviceIdentifier_APPIA_baseRegisterAddress 0x0002 -/*! \brief MMD address of structure AQ_GlobalStandardDeviceIdentifier_APPIA */ -#define AQ_GlobalStandardDeviceIdentifier_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure deviceIdMSW in AQ_GlobalStandardDeviceIdentifier_APPIA */ -#define AQ_GlobalStandardDeviceIdentifier_APPIA_deviceIdMSW 0 -/*! \brief Preprocessor variable to relate field to bit position in structure deviceIdMSW in AQ_GlobalStandardDeviceIdentifier_APPIA */ -#define bits_AQ_GlobalStandardDeviceIdentifier_APPIA_deviceIdMSW u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure deviceIdMSW in AQ_GlobalStandardDeviceIdentifier_APPIA */ -#define word_AQ_GlobalStandardDeviceIdentifier_APPIA_deviceIdMSW u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure deviceIdLSW in AQ_GlobalStandardDeviceIdentifier_APPIA */ -#define AQ_GlobalStandardDeviceIdentifier_APPIA_deviceIdLSW 1 -/*! \brief Preprocessor variable to relate field to bit position in structure deviceIdLSW in AQ_GlobalStandardDeviceIdentifier_APPIA */ -#define bits_AQ_GlobalStandardDeviceIdentifier_APPIA_deviceIdLSW u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure deviceIdLSW in AQ_GlobalStandardDeviceIdentifier_APPIA */ -#define word_AQ_GlobalStandardDeviceIdentifier_APPIA_deviceIdLSW u1.word_1 - -/*! \brief Base register address of structure AQ_GlobalStandardDevicesInPackage_APPIA */ -#define AQ_GlobalStandardDevicesInPackage_APPIA_baseRegisterAddress 0x0005 -/*! \brief MMD address of structure AQ_GlobalStandardDevicesInPackage_APPIA */ -#define AQ_GlobalStandardDevicesInPackage_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ -#define AQ_GlobalStandardDevicesInPackage_APPIA_autonegotiationPresent 0 -/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ -#define bits_AQ_GlobalStandardDevicesInPackage_APPIA_autonegotiationPresent u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ -#define word_AQ_GlobalStandardDevicesInPackage_APPIA_autonegotiationPresent u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure tcPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ -#define AQ_GlobalStandardDevicesInPackage_APPIA_tcPresent 0 -/*! \brief Preprocessor variable to relate field to bit position in structure tcPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ -#define bits_AQ_GlobalStandardDevicesInPackage_APPIA_tcPresent u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure tcPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ -#define word_AQ_GlobalStandardDevicesInPackage_APPIA_tcPresent u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure dteXsPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ -#define AQ_GlobalStandardDevicesInPackage_APPIA_dteXsPresent 0 -/*! \brief Preprocessor variable to relate field to bit position in structure dteXsPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ -#define bits_AQ_GlobalStandardDevicesInPackage_APPIA_dteXsPresent u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure dteXsPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ -#define word_AQ_GlobalStandardDevicesInPackage_APPIA_dteXsPresent u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure phyXS_Present in AQ_GlobalStandardDevicesInPackage_APPIA */ -#define AQ_GlobalStandardDevicesInPackage_APPIA_phyXS_Present 0 -/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_Present in AQ_GlobalStandardDevicesInPackage_APPIA */ -#define bits_AQ_GlobalStandardDevicesInPackage_APPIA_phyXS_Present u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure phyXS_Present in AQ_GlobalStandardDevicesInPackage_APPIA */ -#define word_AQ_GlobalStandardDevicesInPackage_APPIA_phyXS_Present u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pcsPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ -#define AQ_GlobalStandardDevicesInPackage_APPIA_pcsPresent 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pcsPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ -#define bits_AQ_GlobalStandardDevicesInPackage_APPIA_pcsPresent u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pcsPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ -#define word_AQ_GlobalStandardDevicesInPackage_APPIA_pcsPresent u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure wisPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ -#define AQ_GlobalStandardDevicesInPackage_APPIA_wisPresent 0 -/*! \brief Preprocessor variable to relate field to bit position in structure wisPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ -#define bits_AQ_GlobalStandardDevicesInPackage_APPIA_wisPresent u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure wisPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ -#define word_AQ_GlobalStandardDevicesInPackage_APPIA_wisPresent u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pmaPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ -#define AQ_GlobalStandardDevicesInPackage_APPIA_pmaPresent 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pmaPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ -#define bits_AQ_GlobalStandardDevicesInPackage_APPIA_pmaPresent u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pmaPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ -#define word_AQ_GlobalStandardDevicesInPackage_APPIA_pmaPresent u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure clause_22RegistersPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ -#define AQ_GlobalStandardDevicesInPackage_APPIA_clause_22RegistersPresent 0 -/*! \brief Preprocessor variable to relate field to bit position in structure clause_22RegistersPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ -#define bits_AQ_GlobalStandardDevicesInPackage_APPIA_clause_22RegistersPresent u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure clause_22RegistersPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ -#define word_AQ_GlobalStandardDevicesInPackage_APPIA_clause_22RegistersPresent u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalStandardVendorDevicesInPackage_APPIA */ -#define AQ_GlobalStandardVendorDevicesInPackage_APPIA_baseRegisterAddress 0x0006 -/*! \brief MMD address of structure AQ_GlobalStandardVendorDevicesInPackage_APPIA */ -#define AQ_GlobalStandardVendorDevicesInPackage_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure vendorSpecificDevice_2Present in AQ_GlobalStandardVendorDevicesInPackage_APPIA */ -#define AQ_GlobalStandardVendorDevicesInPackage_APPIA_vendorSpecificDevice_2Present 0 -/*! \brief Preprocessor variable to relate field to bit position in structure vendorSpecificDevice_2Present in AQ_GlobalStandardVendorDevicesInPackage_APPIA */ -#define bits_AQ_GlobalStandardVendorDevicesInPackage_APPIA_vendorSpecificDevice_2Present u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure vendorSpecificDevice_2Present in AQ_GlobalStandardVendorDevicesInPackage_APPIA */ -#define word_AQ_GlobalStandardVendorDevicesInPackage_APPIA_vendorSpecificDevice_2Present u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure vendorSpecificDevice_1Present in AQ_GlobalStandardVendorDevicesInPackage_APPIA */ -#define AQ_GlobalStandardVendorDevicesInPackage_APPIA_vendorSpecificDevice_1Present 0 -/*! \brief Preprocessor variable to relate field to bit position in structure vendorSpecificDevice_1Present in AQ_GlobalStandardVendorDevicesInPackage_APPIA */ -#define bits_AQ_GlobalStandardVendorDevicesInPackage_APPIA_vendorSpecificDevice_1Present u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure vendorSpecificDevice_1Present in AQ_GlobalStandardVendorDevicesInPackage_APPIA */ -#define word_AQ_GlobalStandardVendorDevicesInPackage_APPIA_vendorSpecificDevice_1Present u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure clause_22ExtensionPresent in AQ_GlobalStandardVendorDevicesInPackage_APPIA */ -#define AQ_GlobalStandardVendorDevicesInPackage_APPIA_clause_22ExtensionPresent 0 -/*! \brief Preprocessor variable to relate field to bit position in structure clause_22ExtensionPresent in AQ_GlobalStandardVendorDevicesInPackage_APPIA */ -#define bits_AQ_GlobalStandardVendorDevicesInPackage_APPIA_clause_22ExtensionPresent u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure clause_22ExtensionPresent in AQ_GlobalStandardVendorDevicesInPackage_APPIA */ -#define word_AQ_GlobalStandardVendorDevicesInPackage_APPIA_clause_22ExtensionPresent u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalStandardStatus_2_APPIA */ -#define AQ_GlobalStandardStatus_2_APPIA_baseRegisterAddress 0x0008 -/*! \brief MMD address of structure AQ_GlobalStandardStatus_2_APPIA */ -#define AQ_GlobalStandardStatus_2_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure devicePresent in AQ_GlobalStandardStatus_2_APPIA */ -#define AQ_GlobalStandardStatus_2_APPIA_devicePresent 0 -/*! \brief Preprocessor variable to relate field to bit position in structure devicePresent in AQ_GlobalStandardStatus_2_APPIA */ -#define bits_AQ_GlobalStandardStatus_2_APPIA_devicePresent u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure devicePresent in AQ_GlobalStandardStatus_2_APPIA */ -#define word_AQ_GlobalStandardStatus_2_APPIA_devicePresent u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalStandardPackageIdentifier_APPIA */ -#define AQ_GlobalStandardPackageIdentifier_APPIA_baseRegisterAddress 0x000E -/*! \brief MMD address of structure AQ_GlobalStandardPackageIdentifier_APPIA */ -#define AQ_GlobalStandardPackageIdentifier_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure packageIdMSW in AQ_GlobalStandardPackageIdentifier_APPIA */ -#define AQ_GlobalStandardPackageIdentifier_APPIA_packageIdMSW 0 -/*! \brief Preprocessor variable to relate field to bit position in structure packageIdMSW in AQ_GlobalStandardPackageIdentifier_APPIA */ -#define bits_AQ_GlobalStandardPackageIdentifier_APPIA_packageIdMSW u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure packageIdMSW in AQ_GlobalStandardPackageIdentifier_APPIA */ -#define word_AQ_GlobalStandardPackageIdentifier_APPIA_packageIdMSW u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure packageIdLSW in AQ_GlobalStandardPackageIdentifier_APPIA */ -#define AQ_GlobalStandardPackageIdentifier_APPIA_packageIdLSW 1 -/*! \brief Preprocessor variable to relate field to bit position in structure packageIdLSW in AQ_GlobalStandardPackageIdentifier_APPIA */ -#define bits_AQ_GlobalStandardPackageIdentifier_APPIA_packageIdLSW u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure packageIdLSW in AQ_GlobalStandardPackageIdentifier_APPIA */ -#define word_AQ_GlobalStandardPackageIdentifier_APPIA_packageIdLSW u1.word_1 - -/*! \brief Base register address of structure AQ_GlobalFirmwareID_APPIA */ -#define AQ_GlobalFirmwareID_APPIA_baseRegisterAddress 0x0020 -/*! \brief MMD address of structure AQ_GlobalFirmwareID_APPIA */ -#define AQ_GlobalFirmwareID_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure firmwareMajorRevisionNumber in AQ_GlobalFirmwareID_APPIA */ -#define AQ_GlobalFirmwareID_APPIA_firmwareMajorRevisionNumber 0 -/*! \brief Preprocessor variable to relate field to bit position in structure firmwareMajorRevisionNumber in AQ_GlobalFirmwareID_APPIA */ -#define bits_AQ_GlobalFirmwareID_APPIA_firmwareMajorRevisionNumber u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure firmwareMajorRevisionNumber in AQ_GlobalFirmwareID_APPIA */ -#define word_AQ_GlobalFirmwareID_APPIA_firmwareMajorRevisionNumber u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure firmwareMinorRevisionNumber in AQ_GlobalFirmwareID_APPIA */ -#define AQ_GlobalFirmwareID_APPIA_firmwareMinorRevisionNumber 0 -/*! \brief Preprocessor variable to relate field to bit position in structure firmwareMinorRevisionNumber in AQ_GlobalFirmwareID_APPIA */ -#define bits_AQ_GlobalFirmwareID_APPIA_firmwareMinorRevisionNumber u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure firmwareMinorRevisionNumber in AQ_GlobalFirmwareID_APPIA */ -#define word_AQ_GlobalFirmwareID_APPIA_firmwareMinorRevisionNumber u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalChipIdentification_APPIA */ -#define AQ_GlobalChipIdentification_APPIA_baseRegisterAddress 0x0021 -/*! \brief MMD address of structure AQ_GlobalChipIdentification_APPIA */ -#define AQ_GlobalChipIdentification_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure chipIdentification in AQ_GlobalChipIdentification_APPIA */ -#define AQ_GlobalChipIdentification_APPIA_chipIdentification 0 -/*! \brief Preprocessor variable to relate field to bit position in structure chipIdentification in AQ_GlobalChipIdentification_APPIA */ -#define bits_AQ_GlobalChipIdentification_APPIA_chipIdentification u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure chipIdentification in AQ_GlobalChipIdentification_APPIA */ -#define word_AQ_GlobalChipIdentification_APPIA_chipIdentification u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalChipRevision_APPIA */ -#define AQ_GlobalChipRevision_APPIA_baseRegisterAddress 0x0022 -/*! \brief MMD address of structure AQ_GlobalChipRevision_APPIA */ -#define AQ_GlobalChipRevision_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure chipRevision in AQ_GlobalChipRevision_APPIA */ -#define AQ_GlobalChipRevision_APPIA_chipRevision 0 -/*! \brief Preprocessor variable to relate field to bit position in structure chipRevision in AQ_GlobalChipRevision_APPIA */ -#define bits_AQ_GlobalChipRevision_APPIA_chipRevision u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure chipRevision in AQ_GlobalChipRevision_APPIA */ -#define word_AQ_GlobalChipRevision_APPIA_chipRevision u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalNvrInterface_APPIA */ -#define AQ_GlobalNvrInterface_APPIA_baseRegisterAddress 0x0100 -/*! \brief MMD address of structure AQ_GlobalNvrInterface_APPIA */ -#define AQ_GlobalNvrInterface_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure nvrExecuteOperation in AQ_GlobalNvrInterface_APPIA */ -#define AQ_GlobalNvrInterface_APPIA_nvrExecuteOperation 0 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrExecuteOperation in AQ_GlobalNvrInterface_APPIA */ -#define bits_AQ_GlobalNvrInterface_APPIA_nvrExecuteOperation u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure nvrExecuteOperation in AQ_GlobalNvrInterface_APPIA */ -#define word_AQ_GlobalNvrInterface_APPIA_nvrExecuteOperation u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure nvrWriteMode in AQ_GlobalNvrInterface_APPIA */ -#define AQ_GlobalNvrInterface_APPIA_nvrWriteMode 0 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrWriteMode in AQ_GlobalNvrInterface_APPIA */ -#define bits_AQ_GlobalNvrInterface_APPIA_nvrWriteMode u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure nvrWriteMode in AQ_GlobalNvrInterface_APPIA */ -#define word_AQ_GlobalNvrInterface_APPIA_nvrWriteMode u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure freezeNvrCrc in AQ_GlobalNvrInterface_APPIA */ -#define AQ_GlobalNvrInterface_APPIA_freezeNvrCrc 0 -/*! \brief Preprocessor variable to relate field to bit position in structure freezeNvrCrc in AQ_GlobalNvrInterface_APPIA */ -#define bits_AQ_GlobalNvrInterface_APPIA_freezeNvrCrc u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure freezeNvrCrc in AQ_GlobalNvrInterface_APPIA */ -#define word_AQ_GlobalNvrInterface_APPIA_freezeNvrCrc u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure resetNvrCrc in AQ_GlobalNvrInterface_APPIA */ -#define AQ_GlobalNvrInterface_APPIA_resetNvrCrc 0 -/*! \brief Preprocessor variable to relate field to bit position in structure resetNvrCrc in AQ_GlobalNvrInterface_APPIA */ -#define bits_AQ_GlobalNvrInterface_APPIA_resetNvrCrc u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure resetNvrCrc in AQ_GlobalNvrInterface_APPIA */ -#define word_AQ_GlobalNvrInterface_APPIA_resetNvrCrc u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure nvrBurst in AQ_GlobalNvrInterface_APPIA */ -#define AQ_GlobalNvrInterface_APPIA_nvrBurst 0 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrBurst in AQ_GlobalNvrInterface_APPIA */ -#define bits_AQ_GlobalNvrInterface_APPIA_nvrBurst u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure nvrBurst in AQ_GlobalNvrInterface_APPIA */ -#define word_AQ_GlobalNvrInterface_APPIA_nvrBurst u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure nvrBusy in AQ_GlobalNvrInterface_APPIA */ -#define AQ_GlobalNvrInterface_APPIA_nvrBusy 0 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrBusy in AQ_GlobalNvrInterface_APPIA */ -#define bits_AQ_GlobalNvrInterface_APPIA_nvrBusy u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure nvrBusy in AQ_GlobalNvrInterface_APPIA */ -#define word_AQ_GlobalNvrInterface_APPIA_nvrBusy u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure nvrOpcode in AQ_GlobalNvrInterface_APPIA */ -#define AQ_GlobalNvrInterface_APPIA_nvrOpcode 0 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrOpcode in AQ_GlobalNvrInterface_APPIA */ -#define bits_AQ_GlobalNvrInterface_APPIA_nvrOpcode u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure nvrOpcode in AQ_GlobalNvrInterface_APPIA */ -#define word_AQ_GlobalNvrInterface_APPIA_nvrOpcode u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure nvrMailboxCrc in AQ_GlobalNvrInterface_APPIA */ -#define AQ_GlobalNvrInterface_APPIA_nvrMailboxCrc 1 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrMailboxCrc in AQ_GlobalNvrInterface_APPIA */ -#define bits_AQ_GlobalNvrInterface_APPIA_nvrMailboxCrc u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure nvrMailboxCrc in AQ_GlobalNvrInterface_APPIA */ -#define word_AQ_GlobalNvrInterface_APPIA_nvrMailboxCrc u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure nvrAddressMSW in AQ_GlobalNvrInterface_APPIA */ -#define AQ_GlobalNvrInterface_APPIA_nvrAddressMSW 2 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrAddressMSW in AQ_GlobalNvrInterface_APPIA */ -#define bits_AQ_GlobalNvrInterface_APPIA_nvrAddressMSW u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure nvrAddressMSW in AQ_GlobalNvrInterface_APPIA */ -#define word_AQ_GlobalNvrInterface_APPIA_nvrAddressMSW u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure nvrAddressLSW in AQ_GlobalNvrInterface_APPIA */ -#define AQ_GlobalNvrInterface_APPIA_nvrAddressLSW 3 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrAddressLSW in AQ_GlobalNvrInterface_APPIA */ -#define bits_AQ_GlobalNvrInterface_APPIA_nvrAddressLSW u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure nvrAddressLSW in AQ_GlobalNvrInterface_APPIA */ -#define word_AQ_GlobalNvrInterface_APPIA_nvrAddressLSW u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure nvrDataMSW in AQ_GlobalNvrInterface_APPIA */ -#define AQ_GlobalNvrInterface_APPIA_nvrDataMSW 4 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrDataMSW in AQ_GlobalNvrInterface_APPIA */ -#define bits_AQ_GlobalNvrInterface_APPIA_nvrDataMSW u4.bits_4 -/*! \brief Preprocessor variable to relate field to word position in structure nvrDataMSW in AQ_GlobalNvrInterface_APPIA */ -#define word_AQ_GlobalNvrInterface_APPIA_nvrDataMSW u4.word_4 -/*! \brief Preprocessor variable to relate field to word number in structure nvrDataLSW in AQ_GlobalNvrInterface_APPIA */ -#define AQ_GlobalNvrInterface_APPIA_nvrDataLSW 5 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrDataLSW in AQ_GlobalNvrInterface_APPIA */ -#define bits_AQ_GlobalNvrInterface_APPIA_nvrDataLSW u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure nvrDataLSW in AQ_GlobalNvrInterface_APPIA */ -#define word_AQ_GlobalNvrInterface_APPIA_nvrDataLSW u5.word_5 - -/*! \brief Base register address of structure AQ_GlobalMailboxInterface_APPIA */ -#define AQ_GlobalMailboxInterface_APPIA_baseRegisterAddress 0x0200 -/*! \brief MMD address of structure AQ_GlobalMailboxInterface_APPIA */ -#define AQ_GlobalMailboxInterface_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure upMailboxExecuteOperation in AQ_GlobalMailboxInterface_APPIA */ -#define AQ_GlobalMailboxInterface_APPIA_upMailboxExecuteOperation 0 -/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxExecuteOperation in AQ_GlobalMailboxInterface_APPIA */ -#define bits_AQ_GlobalMailboxInterface_APPIA_upMailboxExecuteOperation u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure upMailboxExecuteOperation in AQ_GlobalMailboxInterface_APPIA */ -#define word_AQ_GlobalMailboxInterface_APPIA_upMailboxExecuteOperation u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure upMailboxWriteMode in AQ_GlobalMailboxInterface_APPIA */ -#define AQ_GlobalMailboxInterface_APPIA_upMailboxWriteMode 0 -/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxWriteMode in AQ_GlobalMailboxInterface_APPIA */ -#define bits_AQ_GlobalMailboxInterface_APPIA_upMailboxWriteMode u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure upMailboxWriteMode in AQ_GlobalMailboxInterface_APPIA */ -#define word_AQ_GlobalMailboxInterface_APPIA_upMailboxWriteMode u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure resetUpMailboxCrc in AQ_GlobalMailboxInterface_APPIA */ -#define AQ_GlobalMailboxInterface_APPIA_resetUpMailboxCrc 0 -/*! \brief Preprocessor variable to relate field to bit position in structure resetUpMailboxCrc in AQ_GlobalMailboxInterface_APPIA */ -#define bits_AQ_GlobalMailboxInterface_APPIA_resetUpMailboxCrc u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure resetUpMailboxCrc in AQ_GlobalMailboxInterface_APPIA */ -#define word_AQ_GlobalMailboxInterface_APPIA_resetUpMailboxCrc u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure upMailboxBusy in AQ_GlobalMailboxInterface_APPIA */ -#define AQ_GlobalMailboxInterface_APPIA_upMailboxBusy 0 -/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxBusy in AQ_GlobalMailboxInterface_APPIA */ -#define bits_AQ_GlobalMailboxInterface_APPIA_upMailboxBusy u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure upMailboxBusy in AQ_GlobalMailboxInterface_APPIA */ -#define word_AQ_GlobalMailboxInterface_APPIA_upMailboxBusy u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure upMailboxCrc in AQ_GlobalMailboxInterface_APPIA */ -#define AQ_GlobalMailboxInterface_APPIA_upMailboxCrc 1 -/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxCrc in AQ_GlobalMailboxInterface_APPIA */ -#define bits_AQ_GlobalMailboxInterface_APPIA_upMailboxCrc u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure upMailboxCrc in AQ_GlobalMailboxInterface_APPIA */ -#define word_AQ_GlobalMailboxInterface_APPIA_upMailboxCrc u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure upMailboxAddressMSW in AQ_GlobalMailboxInterface_APPIA */ -#define AQ_GlobalMailboxInterface_APPIA_upMailboxAddressMSW 2 -/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxAddressMSW in AQ_GlobalMailboxInterface_APPIA */ -#define bits_AQ_GlobalMailboxInterface_APPIA_upMailboxAddressMSW u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure upMailboxAddressMSW in AQ_GlobalMailboxInterface_APPIA */ -#define word_AQ_GlobalMailboxInterface_APPIA_upMailboxAddressMSW u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure upMailboxAddressLSW in AQ_GlobalMailboxInterface_APPIA */ -#define AQ_GlobalMailboxInterface_APPIA_upMailboxAddressLSW 3 -/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxAddressLSW in AQ_GlobalMailboxInterface_APPIA */ -#define bits_AQ_GlobalMailboxInterface_APPIA_upMailboxAddressLSW u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure upMailboxAddressLSW in AQ_GlobalMailboxInterface_APPIA */ -#define word_AQ_GlobalMailboxInterface_APPIA_upMailboxAddressLSW u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure upMailboxAddressLSW_Don_tCare in AQ_GlobalMailboxInterface_APPIA */ -#define AQ_GlobalMailboxInterface_APPIA_upMailboxAddressLSW_Don_tCare 3 -/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxAddressLSW_Don_tCare in AQ_GlobalMailboxInterface_APPIA */ -#define bits_AQ_GlobalMailboxInterface_APPIA_upMailboxAddressLSW_Don_tCare u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure upMailboxAddressLSW_Don_tCare in AQ_GlobalMailboxInterface_APPIA */ -#define word_AQ_GlobalMailboxInterface_APPIA_upMailboxAddressLSW_Don_tCare u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure upMailboxDataMSW in AQ_GlobalMailboxInterface_APPIA */ -#define AQ_GlobalMailboxInterface_APPIA_upMailboxDataMSW 4 -/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxDataMSW in AQ_GlobalMailboxInterface_APPIA */ -#define bits_AQ_GlobalMailboxInterface_APPIA_upMailboxDataMSW u4.bits_4 -/*! \brief Preprocessor variable to relate field to word position in structure upMailboxDataMSW in AQ_GlobalMailboxInterface_APPIA */ -#define word_AQ_GlobalMailboxInterface_APPIA_upMailboxDataMSW u4.word_4 -/*! \brief Preprocessor variable to relate field to word number in structure upMailboxDataLSW in AQ_GlobalMailboxInterface_APPIA */ -#define AQ_GlobalMailboxInterface_APPIA_upMailboxDataLSW 5 -/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxDataLSW in AQ_GlobalMailboxInterface_APPIA */ -#define bits_AQ_GlobalMailboxInterface_APPIA_upMailboxDataLSW u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure upMailboxDataLSW in AQ_GlobalMailboxInterface_APPIA */ -#define word_AQ_GlobalMailboxInterface_APPIA_upMailboxDataLSW u5.word_5 - -/*! \brief Base register address of structure AQ_GlobalMicroprocessorScratchPad_APPIA */ -#define AQ_GlobalMicroprocessorScratchPad_APPIA_baseRegisterAddress 0x0300 -/*! \brief MMD address of structure AQ_GlobalMicroprocessorScratchPad_APPIA */ -#define AQ_GlobalMicroprocessorScratchPad_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure scratchPad_1 in AQ_GlobalMicroprocessorScratchPad_APPIA */ -#define AQ_GlobalMicroprocessorScratchPad_APPIA_scratchPad_1 0 -/*! \brief Preprocessor variable to relate field to bit position in structure scratchPad_1 in AQ_GlobalMicroprocessorScratchPad_APPIA */ -#define bits_AQ_GlobalMicroprocessorScratchPad_APPIA_scratchPad_1 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure scratchPad_1 in AQ_GlobalMicroprocessorScratchPad_APPIA */ -#define word_AQ_GlobalMicroprocessorScratchPad_APPIA_scratchPad_1 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure scratchPad_2 in AQ_GlobalMicroprocessorScratchPad_APPIA */ -#define AQ_GlobalMicroprocessorScratchPad_APPIA_scratchPad_2 1 -/*! \brief Preprocessor variable to relate field to bit position in structure scratchPad_2 in AQ_GlobalMicroprocessorScratchPad_APPIA */ -#define bits_AQ_GlobalMicroprocessorScratchPad_APPIA_scratchPad_2 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure scratchPad_2 in AQ_GlobalMicroprocessorScratchPad_APPIA */ -#define word_AQ_GlobalMicroprocessorScratchPad_APPIA_scratchPad_2 u1.word_1 - -/*! \brief Base register address of structure AQ_GlobalControl_APPIA */ -#define AQ_GlobalControl_APPIA_baseRegisterAddress 0xC000 -/*! \brief MMD address of structure AQ_GlobalControl_APPIA */ -#define AQ_GlobalControl_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure upReset in AQ_GlobalControl_APPIA */ -#define AQ_GlobalControl_APPIA_upReset 1 -/*! \brief Preprocessor variable to relate field to bit position in structure upReset in AQ_GlobalControl_APPIA */ -#define bits_AQ_GlobalControl_APPIA_upReset u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure upReset in AQ_GlobalControl_APPIA */ -#define word_AQ_GlobalControl_APPIA_upReset u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure upRunStallOverride in AQ_GlobalControl_APPIA */ -#define AQ_GlobalControl_APPIA_upRunStallOverride 1 -/*! \brief Preprocessor variable to relate field to bit position in structure upRunStallOverride in AQ_GlobalControl_APPIA */ -#define bits_AQ_GlobalControl_APPIA_upRunStallOverride u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure upRunStallOverride in AQ_GlobalControl_APPIA */ -#define word_AQ_GlobalControl_APPIA_upRunStallOverride u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure upRunStall in AQ_GlobalControl_APPIA */ -#define AQ_GlobalControl_APPIA_upRunStall 1 -/*! \brief Preprocessor variable to relate field to bit position in structure upRunStall in AQ_GlobalControl_APPIA */ -#define bits_AQ_GlobalControl_APPIA_upRunStall u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure upRunStall in AQ_GlobalControl_APPIA */ -#define word_AQ_GlobalControl_APPIA_upRunStall u1.word_1 - -/*! \brief Base register address of structure AQ_GlobalResetControl_APPIA */ -#define AQ_GlobalResetControl_APPIA_baseRegisterAddress 0xC006 -/*! \brief MMD address of structure AQ_GlobalResetControl_APPIA */ -#define AQ_GlobalResetControl_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure globalMMD_ResetDisable in AQ_GlobalResetControl_APPIA */ -#define AQ_GlobalResetControl_APPIA_globalMMD_ResetDisable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure globalMMD_ResetDisable in AQ_GlobalResetControl_APPIA */ -#define bits_AQ_GlobalResetControl_APPIA_globalMMD_ResetDisable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure globalMMD_ResetDisable in AQ_GlobalResetControl_APPIA */ -#define word_AQ_GlobalResetControl_APPIA_globalMMD_ResetDisable u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalDiagnosticProvisioning_APPIA */ -#define AQ_GlobalDiagnosticProvisioning_APPIA_baseRegisterAddress 0xC400 -/*! \brief MMD address of structure AQ_GlobalDiagnosticProvisioning_APPIA */ -#define AQ_GlobalDiagnosticProvisioning_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure enableDiagnostics in AQ_GlobalDiagnosticProvisioning_APPIA */ -#define AQ_GlobalDiagnosticProvisioning_APPIA_enableDiagnostics 0 -/*! \brief Preprocessor variable to relate field to bit position in structure enableDiagnostics in AQ_GlobalDiagnosticProvisioning_APPIA */ -#define bits_AQ_GlobalDiagnosticProvisioning_APPIA_enableDiagnostics u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure enableDiagnostics in AQ_GlobalDiagnosticProvisioning_APPIA */ -#define word_AQ_GlobalDiagnosticProvisioning_APPIA_enableDiagnostics u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalThermalProvisioning_APPIA */ -#define AQ_GlobalThermalProvisioning_APPIA_baseRegisterAddress 0xC420 -/*! \brief MMD address of structure AQ_GlobalThermalProvisioning_APPIA */ -#define AQ_GlobalThermalProvisioning_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure reserved_0 in AQ_GlobalThermalProvisioning_APPIA */ -#define AQ_GlobalThermalProvisioning_APPIA_reserved_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_0 in AQ_GlobalThermalProvisioning_APPIA */ -#define bits_AQ_GlobalThermalProvisioning_APPIA_reserved_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_0 in AQ_GlobalThermalProvisioning_APPIA */ -#define word_AQ_GlobalThermalProvisioning_APPIA_reserved_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure highTempFailureThreshold in AQ_GlobalThermalProvisioning_APPIA */ -#define AQ_GlobalThermalProvisioning_APPIA_highTempFailureThreshold 1 -/*! \brief Preprocessor variable to relate field to bit position in structure highTempFailureThreshold in AQ_GlobalThermalProvisioning_APPIA */ -#define bits_AQ_GlobalThermalProvisioning_APPIA_highTempFailureThreshold u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure highTempFailureThreshold in AQ_GlobalThermalProvisioning_APPIA */ -#define word_AQ_GlobalThermalProvisioning_APPIA_highTempFailureThreshold u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure lowTempFailureThreshold in AQ_GlobalThermalProvisioning_APPIA */ -#define AQ_GlobalThermalProvisioning_APPIA_lowTempFailureThreshold 2 -/*! \brief Preprocessor variable to relate field to bit position in structure lowTempFailureThreshold in AQ_GlobalThermalProvisioning_APPIA */ -#define bits_AQ_GlobalThermalProvisioning_APPIA_lowTempFailureThreshold u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure lowTempFailureThreshold in AQ_GlobalThermalProvisioning_APPIA */ -#define word_AQ_GlobalThermalProvisioning_APPIA_lowTempFailureThreshold u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure highTempWarningThreshold in AQ_GlobalThermalProvisioning_APPIA */ -#define AQ_GlobalThermalProvisioning_APPIA_highTempWarningThreshold 3 -/*! \brief Preprocessor variable to relate field to bit position in structure highTempWarningThreshold in AQ_GlobalThermalProvisioning_APPIA */ -#define bits_AQ_GlobalThermalProvisioning_APPIA_highTempWarningThreshold u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure highTempWarningThreshold in AQ_GlobalThermalProvisioning_APPIA */ -#define word_AQ_GlobalThermalProvisioning_APPIA_highTempWarningThreshold u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure lowTempWarningThreshold in AQ_GlobalThermalProvisioning_APPIA */ -#define AQ_GlobalThermalProvisioning_APPIA_lowTempWarningThreshold 4 -/*! \brief Preprocessor variable to relate field to bit position in structure lowTempWarningThreshold in AQ_GlobalThermalProvisioning_APPIA */ -#define bits_AQ_GlobalThermalProvisioning_APPIA_lowTempWarningThreshold u4.bits_4 -/*! \brief Preprocessor variable to relate field to word position in structure lowTempWarningThreshold in AQ_GlobalThermalProvisioning_APPIA */ -#define word_AQ_GlobalThermalProvisioning_APPIA_lowTempWarningThreshold u4.word_4 - -/*! \brief Base register address of structure AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_baseRegisterAddress 0xC430 -/*! \brief MMD address of structure AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure led_0ManualSet in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_0ManualSet 0 -/*! \brief Preprocessor variable to relate field to bit position in structure led_0ManualSet in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_0ManualSet u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure led_0ManualSet in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_0ManualSet u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure led_0_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_0_10Gb_sLinkEstablished 0 -/*! \brief Preprocessor variable to relate field to bit position in structure led_0_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_0_10Gb_sLinkEstablished u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure led_0_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_0_10Gb_sLinkEstablished u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure led_0_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_0_1Gb_sLinkEstablished 0 -/*! \brief Preprocessor variable to relate field to bit position in structure led_0_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_0_1Gb_sLinkEstablished u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure led_0_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_0_1Gb_sLinkEstablished u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure led_0_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_0_100Mb_sLinkEstablished 0 -/*! \brief Preprocessor variable to relate field to bit position in structure led_0_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_0_100Mb_sLinkEstablished u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure led_0_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_0_100Mb_sLinkEstablished u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure led_0Connecting in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_0Connecting 0 -/*! \brief Preprocessor variable to relate field to bit position in structure led_0Connecting in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_0Connecting u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure led_0Connecting in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_0Connecting u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure led_0ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_0ReceiveActivity 0 -/*! \brief Preprocessor variable to relate field to bit position in structure led_0ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_0ReceiveActivity u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure led_0ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_0ReceiveActivity u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure led_0TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_0TransmitActivity 0 -/*! \brief Preprocessor variable to relate field to bit position in structure led_0TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_0TransmitActivity u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure led_0TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_0TransmitActivity u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure led_0ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_0ActivityStretch 0 -/*! \brief Preprocessor variable to relate field to bit position in structure led_0ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_0ActivityStretch u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure led_0ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_0ActivityStretch u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure led_1ManualSet in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_1ManualSet 1 -/*! \brief Preprocessor variable to relate field to bit position in structure led_1ManualSet in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_1ManualSet u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure led_1ManualSet in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_1ManualSet u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure led_1_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_1_10Gb_sLinkEstablished 1 -/*! \brief Preprocessor variable to relate field to bit position in structure led_1_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_1_10Gb_sLinkEstablished u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure led_1_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_1_10Gb_sLinkEstablished u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure led_1_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_1_1Gb_sLinkEstablished 1 -/*! \brief Preprocessor variable to relate field to bit position in structure led_1_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_1_1Gb_sLinkEstablished u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure led_1_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_1_1Gb_sLinkEstablished u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure led_1_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_1_100Mb_sLinkEstablished 1 -/*! \brief Preprocessor variable to relate field to bit position in structure led_1_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_1_100Mb_sLinkEstablished u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure led_1_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_1_100Mb_sLinkEstablished u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure led_1Connecting in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_1Connecting 1 -/*! \brief Preprocessor variable to relate field to bit position in structure led_1Connecting in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_1Connecting u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure led_1Connecting in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_1Connecting u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure led_1ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_1ReceiveActivity 1 -/*! \brief Preprocessor variable to relate field to bit position in structure led_1ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_1ReceiveActivity u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure led_1ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_1ReceiveActivity u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure led_1TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_1TransmitActivity 1 -/*! \brief Preprocessor variable to relate field to bit position in structure led_1TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_1TransmitActivity u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure led_1TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_1TransmitActivity u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure led_1ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_1ActivityStretch 1 -/*! \brief Preprocessor variable to relate field to bit position in structure led_1ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_1ActivityStretch u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure led_1ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_1ActivityStretch u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure led_2ManualSet in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_2ManualSet 2 -/*! \brief Preprocessor variable to relate field to bit position in structure led_2ManualSet in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_2ManualSet u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure led_2ManualSet in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_2ManualSet u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure led_2_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_2_10Gb_sLinkEstablished 2 -/*! \brief Preprocessor variable to relate field to bit position in structure led_2_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_2_10Gb_sLinkEstablished u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure led_2_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_2_10Gb_sLinkEstablished u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure led_2_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_2_1Gb_sLinkEstablished 2 -/*! \brief Preprocessor variable to relate field to bit position in structure led_2_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_2_1Gb_sLinkEstablished u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure led_2_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_2_1Gb_sLinkEstablished u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure led_2_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_2_100Mb_sLinkEstablished 2 -/*! \brief Preprocessor variable to relate field to bit position in structure led_2_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_2_100Mb_sLinkEstablished u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure led_2_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_2_100Mb_sLinkEstablished u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure led_2Connecting in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_2Connecting 2 -/*! \brief Preprocessor variable to relate field to bit position in structure led_2Connecting in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_2Connecting u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure led_2Connecting in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_2Connecting u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure led_2ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_2ReceiveActivity 2 -/*! \brief Preprocessor variable to relate field to bit position in structure led_2ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_2ReceiveActivity u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure led_2ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_2ReceiveActivity u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure led_2TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_2TransmitActivity 2 -/*! \brief Preprocessor variable to relate field to bit position in structure led_2TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_2TransmitActivity u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure led_2TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_2TransmitActivity u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure led_2ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_2ActivityStretch 2 -/*! \brief Preprocessor variable to relate field to bit position in structure led_2ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_2ActivityStretch u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure led_2ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_2ActivityStretch u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure led_3ManualSet in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_3ManualSet 3 -/*! \brief Preprocessor variable to relate field to bit position in structure led_3ManualSet in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_3ManualSet u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure led_3ManualSet in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_3ManualSet u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure led_3_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_3_10Gb_sLinkEstablished 3 -/*! \brief Preprocessor variable to relate field to bit position in structure led_3_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_3_10Gb_sLinkEstablished u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure led_3_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_3_10Gb_sLinkEstablished u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure led_3_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_3_1Gb_sLinkEstablished 3 -/*! \brief Preprocessor variable to relate field to bit position in structure led_3_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_3_1Gb_sLinkEstablished u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure led_3_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_3_1Gb_sLinkEstablished u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure led_3_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_3_100Mb_sLinkEstablished 3 -/*! \brief Preprocessor variable to relate field to bit position in structure led_3_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_3_100Mb_sLinkEstablished u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure led_3_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_3_100Mb_sLinkEstablished u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure led_3Connecting in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_3Connecting 3 -/*! \brief Preprocessor variable to relate field to bit position in structure led_3Connecting in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_3Connecting u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure led_3Connecting in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_3Connecting u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure led_3ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_3ReceiveActivity 3 -/*! \brief Preprocessor variable to relate field to bit position in structure led_3ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_3ReceiveActivity u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure led_3ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_3ReceiveActivity u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure led_3TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_3TransmitActivity 3 -/*! \brief Preprocessor variable to relate field to bit position in structure led_3TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_3TransmitActivity u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure led_3TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_3TransmitActivity u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure led_3ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_3ActivityStretch 3 -/*! \brief Preprocessor variable to relate field to bit position in structure led_3ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_3ActivityStretch u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure led_3ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_3ActivityStretch u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure led_4ManualSet in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_4ManualSet 4 -/*! \brief Preprocessor variable to relate field to bit position in structure led_4ManualSet in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_4ManualSet u4.bits_4 -/*! \brief Preprocessor variable to relate field to word position in structure led_4ManualSet in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_4ManualSet u4.word_4 -/*! \brief Preprocessor variable to relate field to word number in structure led_4_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_4_10Gb_sLinkEstablished 4 -/*! \brief Preprocessor variable to relate field to bit position in structure led_4_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_4_10Gb_sLinkEstablished u4.bits_4 -/*! \brief Preprocessor variable to relate field to word position in structure led_4_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_4_10Gb_sLinkEstablished u4.word_4 -/*! \brief Preprocessor variable to relate field to word number in structure led_4_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_4_1Gb_sLinkEstablished 4 -/*! \brief Preprocessor variable to relate field to bit position in structure led_4_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_4_1Gb_sLinkEstablished u4.bits_4 -/*! \brief Preprocessor variable to relate field to word position in structure led_4_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_4_1Gb_sLinkEstablished u4.word_4 -/*! \brief Preprocessor variable to relate field to word number in structure led_4_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_4_100Mb_sLinkEstablished 4 -/*! \brief Preprocessor variable to relate field to bit position in structure led_4_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_4_100Mb_sLinkEstablished u4.bits_4 -/*! \brief Preprocessor variable to relate field to word position in structure led_4_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_4_100Mb_sLinkEstablished u4.word_4 -/*! \brief Preprocessor variable to relate field to word number in structure led_4Connecting in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_4Connecting 4 -/*! \brief Preprocessor variable to relate field to bit position in structure led_4Connecting in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_4Connecting u4.bits_4 -/*! \brief Preprocessor variable to relate field to word position in structure led_4Connecting in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_4Connecting u4.word_4 -/*! \brief Preprocessor variable to relate field to word number in structure led_4ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_4ReceiveActivity 4 -/*! \brief Preprocessor variable to relate field to bit position in structure led_4ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_4ReceiveActivity u4.bits_4 -/*! \brief Preprocessor variable to relate field to word position in structure led_4ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_4ReceiveActivity u4.word_4 -/*! \brief Preprocessor variable to relate field to word number in structure led_4TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_4TransmitActivity 4 -/*! \brief Preprocessor variable to relate field to bit position in structure led_4TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_4TransmitActivity u4.bits_4 -/*! \brief Preprocessor variable to relate field to word position in structure led_4TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_4TransmitActivity u4.word_4 -/*! \brief Preprocessor variable to relate field to word number in structure led_4ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_4ActivityStretch 4 -/*! \brief Preprocessor variable to relate field to bit position in structure led_4ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_4ActivityStretch u4.bits_4 -/*! \brief Preprocessor variable to relate field to word position in structure led_4ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_4ActivityStretch u4.word_4 -/*! \brief Preprocessor variable to relate field to word number in structure led_5ManualSet in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_5ManualSet 5 -/*! \brief Preprocessor variable to relate field to bit position in structure led_5ManualSet in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_5ManualSet u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure led_5ManualSet in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_5ManualSet u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure led_5_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_5_10Gb_sLinkEstablished 5 -/*! \brief Preprocessor variable to relate field to bit position in structure led_5_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_5_10Gb_sLinkEstablished u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure led_5_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_5_10Gb_sLinkEstablished u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure led_5_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_5_1Gb_sLinkEstablished 5 -/*! \brief Preprocessor variable to relate field to bit position in structure led_5_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_5_1Gb_sLinkEstablished u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure led_5_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_5_1Gb_sLinkEstablished u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure led_5_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_5_100Mb_sLinkEstablished 5 -/*! \brief Preprocessor variable to relate field to bit position in structure led_5_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_5_100Mb_sLinkEstablished u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure led_5_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_5_100Mb_sLinkEstablished u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure led_5Connecting in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_5Connecting 5 -/*! \brief Preprocessor variable to relate field to bit position in structure led_5Connecting in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_5Connecting u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure led_5Connecting in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_5Connecting u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure led_5ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_5ReceiveActivity 5 -/*! \brief Preprocessor variable to relate field to bit position in structure led_5ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_5ReceiveActivity u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure led_5ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_5ReceiveActivity u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure led_5TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_5TransmitActivity 5 -/*! \brief Preprocessor variable to relate field to bit position in structure led_5TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_5TransmitActivity u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure led_5TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_5TransmitActivity u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure led_5ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_5ActivityStretch 5 -/*! \brief Preprocessor variable to relate field to bit position in structure led_5ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_5ActivityStretch u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure led_5ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_5ActivityStretch u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure ledOperationMode in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_ledOperationMode 7 -/*! \brief Preprocessor variable to relate field to bit position in structure ledOperationMode in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_ledOperationMode u7.bits_7 -/*! \brief Preprocessor variable to relate field to word position in structure ledOperationMode in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_ledOperationMode u7.word_7 -/*! \brief Preprocessor variable to relate field to word number in structure led_0DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_0DriveThreeStateSelect 8 -/*! \brief Preprocessor variable to relate field to bit position in structure led_0DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_0DriveThreeStateSelect u8.bits_8 -/*! \brief Preprocessor variable to relate field to word position in structure led_0DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_0DriveThreeStateSelect u8.word_8 -/*! \brief Preprocessor variable to relate field to word number in structure led_0ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_0ActiveHighSelect 8 -/*! \brief Preprocessor variable to relate field to bit position in structure led_0ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_0ActiveHighSelect u8.bits_8 -/*! \brief Preprocessor variable to relate field to word position in structure led_0ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_0ActiveHighSelect u8.word_8 -/*! \brief Preprocessor variable to relate field to word number in structure led_0ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_0ManualActiveSelect 8 -/*! \brief Preprocessor variable to relate field to bit position in structure led_0ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_0ManualActiveSelect u8.bits_8 -/*! \brief Preprocessor variable to relate field to word position in structure led_0ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_0ManualActiveSelect u8.word_8 -/*! \brief Preprocessor variable to relate field to word number in structure led_1DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_1DriveThreeStateSelect 9 -/*! \brief Preprocessor variable to relate field to bit position in structure led_1DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_1DriveThreeStateSelect u9.bits_9 -/*! \brief Preprocessor variable to relate field to word position in structure led_1DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_1DriveThreeStateSelect u9.word_9 -/*! \brief Preprocessor variable to relate field to word number in structure led_1ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_1ActiveHighSelect 9 -/*! \brief Preprocessor variable to relate field to bit position in structure led_1ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_1ActiveHighSelect u9.bits_9 -/*! \brief Preprocessor variable to relate field to word position in structure led_1ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_1ActiveHighSelect u9.word_9 -/*! \brief Preprocessor variable to relate field to word number in structure led_1ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_1ManualActiveSelect 9 -/*! \brief Preprocessor variable to relate field to bit position in structure led_1ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_1ManualActiveSelect u9.bits_9 -/*! \brief Preprocessor variable to relate field to word position in structure led_1ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_1ManualActiveSelect u9.word_9 -/*! \brief Preprocessor variable to relate field to word number in structure led_2DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_2DriveThreeStateSelect 10 -/*! \brief Preprocessor variable to relate field to bit position in structure led_2DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_2DriveThreeStateSelect u10.bits_10 -/*! \brief Preprocessor variable to relate field to word position in structure led_2DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_2DriveThreeStateSelect u10.word_10 -/*! \brief Preprocessor variable to relate field to word number in structure led_2ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_2ActiveHighSelect 10 -/*! \brief Preprocessor variable to relate field to bit position in structure led_2ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_2ActiveHighSelect u10.bits_10 -/*! \brief Preprocessor variable to relate field to word position in structure led_2ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_2ActiveHighSelect u10.word_10 -/*! \brief Preprocessor variable to relate field to word number in structure led_2ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_2ManualActiveSelect 10 -/*! \brief Preprocessor variable to relate field to bit position in structure led_2ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_2ManualActiveSelect u10.bits_10 -/*! \brief Preprocessor variable to relate field to word position in structure led_2ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_2ManualActiveSelect u10.word_10 -/*! \brief Preprocessor variable to relate field to word number in structure led_3DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_3DriveThreeStateSelect 11 -/*! \brief Preprocessor variable to relate field to bit position in structure led_3DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_3DriveThreeStateSelect u11.bits_11 -/*! \brief Preprocessor variable to relate field to word position in structure led_3DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_3DriveThreeStateSelect u11.word_11 -/*! \brief Preprocessor variable to relate field to word number in structure led_3ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_3ActiveHighSelect 11 -/*! \brief Preprocessor variable to relate field to bit position in structure led_3ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_3ActiveHighSelect u11.bits_11 -/*! \brief Preprocessor variable to relate field to word position in structure led_3ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_3ActiveHighSelect u11.word_11 -/*! \brief Preprocessor variable to relate field to word number in structure led_3ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_3ManualActiveSelect 11 -/*! \brief Preprocessor variable to relate field to bit position in structure led_3ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_3ManualActiveSelect u11.bits_11 -/*! \brief Preprocessor variable to relate field to word position in structure led_3ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_3ManualActiveSelect u11.word_11 -/*! \brief Preprocessor variable to relate field to word number in structure led_4DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_4DriveThreeStateSelect 12 -/*! \brief Preprocessor variable to relate field to bit position in structure led_4DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_4DriveThreeStateSelect u12.bits_12 -/*! \brief Preprocessor variable to relate field to word position in structure led_4DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_4DriveThreeStateSelect u12.word_12 -/*! \brief Preprocessor variable to relate field to word number in structure led_4ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_4ActiveHighSelect 12 -/*! \brief Preprocessor variable to relate field to bit position in structure led_4ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_4ActiveHighSelect u12.bits_12 -/*! \brief Preprocessor variable to relate field to word position in structure led_4ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_4ActiveHighSelect u12.word_12 -/*! \brief Preprocessor variable to relate field to word number in structure led_4ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_4ManualActiveSelect 12 -/*! \brief Preprocessor variable to relate field to bit position in structure led_4ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_4ManualActiveSelect u12.bits_12 -/*! \brief Preprocessor variable to relate field to word position in structure led_4ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_4ManualActiveSelect u12.word_12 -/*! \brief Preprocessor variable to relate field to word number in structure led_5DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_5DriveThreeStateSelect 13 -/*! \brief Preprocessor variable to relate field to bit position in structure led_5DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_5DriveThreeStateSelect u13.bits_13 -/*! \brief Preprocessor variable to relate field to word position in structure led_5DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_5DriveThreeStateSelect u13.word_13 -/*! \brief Preprocessor variable to relate field to word number in structure led_5ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_5ActiveHighSelect 13 -/*! \brief Preprocessor variable to relate field to bit position in structure led_5ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_5ActiveHighSelect u13.bits_13 -/*! \brief Preprocessor variable to relate field to word position in structure led_5ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_5ActiveHighSelect u13.word_13 -/*! \brief Preprocessor variable to relate field to word number in structure led_5ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_5ManualActiveSelect 13 -/*! \brief Preprocessor variable to relate field to bit position in structure led_5ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_5ManualActiveSelect u13.bits_13 -/*! \brief Preprocessor variable to relate field to word position in structure led_5ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_5ManualActiveSelect u13.word_13 - -/*! \brief Base register address of structure AQ_GlobalGeneralProvisioning_APPIA */ -#define AQ_GlobalGeneralProvisioning_APPIA_baseRegisterAddress 0xC440 -/*! \brief MMD address of structure AQ_GlobalGeneralProvisioning_APPIA */ -#define AQ_GlobalGeneralProvisioning_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure gangLoadMdioAddress in AQ_GlobalGeneralProvisioning_APPIA */ -#define AQ_GlobalGeneralProvisioning_APPIA_gangLoadMdioAddress 0 -/*! \brief Preprocessor variable to relate field to bit position in structure gangLoadMdioAddress in AQ_GlobalGeneralProvisioning_APPIA */ -#define bits_AQ_GlobalGeneralProvisioning_APPIA_gangLoadMdioAddress u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure gangLoadMdioAddress in AQ_GlobalGeneralProvisioning_APPIA */ -#define word_AQ_GlobalGeneralProvisioning_APPIA_gangLoadMdioAddress u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure gangLoadMdioWriteOnly in AQ_GlobalGeneralProvisioning_APPIA */ -#define AQ_GlobalGeneralProvisioning_APPIA_gangLoadMdioWriteOnly 0 -/*! \brief Preprocessor variable to relate field to bit position in structure gangLoadMdioWriteOnly in AQ_GlobalGeneralProvisioning_APPIA */ -#define bits_AQ_GlobalGeneralProvisioning_APPIA_gangLoadMdioWriteOnly u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure gangLoadMdioWriteOnly in AQ_GlobalGeneralProvisioning_APPIA */ -#define word_AQ_GlobalGeneralProvisioning_APPIA_gangLoadMdioWriteOnly u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mdioBroadcastModeEnable in AQ_GlobalGeneralProvisioning_APPIA */ -#define AQ_GlobalGeneralProvisioning_APPIA_mdioBroadcastModeEnable 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mdioBroadcastModeEnable in AQ_GlobalGeneralProvisioning_APPIA */ -#define bits_AQ_GlobalGeneralProvisioning_APPIA_mdioBroadcastModeEnable u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mdioBroadcastModeEnable in AQ_GlobalGeneralProvisioning_APPIA */ -#define word_AQ_GlobalGeneralProvisioning_APPIA_mdioBroadcastModeEnable u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure mdioReadMSW_FirstEnable in AQ_GlobalGeneralProvisioning_APPIA */ -#define AQ_GlobalGeneralProvisioning_APPIA_mdioReadMSW_FirstEnable 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mdioReadMSW_FirstEnable in AQ_GlobalGeneralProvisioning_APPIA */ -#define bits_AQ_GlobalGeneralProvisioning_APPIA_mdioReadMSW_FirstEnable u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mdioReadMSW_FirstEnable in AQ_GlobalGeneralProvisioning_APPIA */ -#define word_AQ_GlobalGeneralProvisioning_APPIA_mdioReadMSW_FirstEnable u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure mdioDriveConfiguration in AQ_GlobalGeneralProvisioning_APPIA */ -#define AQ_GlobalGeneralProvisioning_APPIA_mdioDriveConfiguration 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mdioDriveConfiguration in AQ_GlobalGeneralProvisioning_APPIA */ -#define bits_AQ_GlobalGeneralProvisioning_APPIA_mdioDriveConfiguration u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mdioDriveConfiguration in AQ_GlobalGeneralProvisioning_APPIA */ -#define word_AQ_GlobalGeneralProvisioning_APPIA_mdioDriveConfiguration u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure mdioPreambleDetectionDisable in AQ_GlobalGeneralProvisioning_APPIA */ -#define AQ_GlobalGeneralProvisioning_APPIA_mdioPreambleDetectionDisable 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mdioPreambleDetectionDisable in AQ_GlobalGeneralProvisioning_APPIA */ -#define bits_AQ_GlobalGeneralProvisioning_APPIA_mdioPreambleDetectionDisable u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mdioPreambleDetectionDisable in AQ_GlobalGeneralProvisioning_APPIA */ -#define word_AQ_GlobalGeneralProvisioning_APPIA_mdioPreambleDetectionDisable u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure mdioAddressReset in AQ_GlobalGeneralProvisioning_APPIA */ -#define AQ_GlobalGeneralProvisioning_APPIA_mdioAddressReset 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mdioAddressReset in AQ_GlobalGeneralProvisioning_APPIA */ -#define bits_AQ_GlobalGeneralProvisioning_APPIA_mdioAddressReset u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mdioAddressReset in AQ_GlobalGeneralProvisioning_APPIA */ -#define word_AQ_GlobalGeneralProvisioning_APPIA_mdioAddressReset u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure daisyChainReset in AQ_GlobalGeneralProvisioning_APPIA */ -#define AQ_GlobalGeneralProvisioning_APPIA_daisyChainReset 2 -/*! \brief Preprocessor variable to relate field to bit position in structure daisyChainReset in AQ_GlobalGeneralProvisioning_APPIA */ -#define bits_AQ_GlobalGeneralProvisioning_APPIA_daisyChainReset u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure daisyChainReset in AQ_GlobalGeneralProvisioning_APPIA */ -#define word_AQ_GlobalGeneralProvisioning_APPIA_daisyChainReset u2.word_2 - -/*! \brief Base register address of structure AQ_GlobalNvrProvisioning_APPIA */ -#define AQ_GlobalNvrProvisioning_APPIA_baseRegisterAddress 0xC450 -/*! \brief MMD address of structure AQ_GlobalNvrProvisioning_APPIA */ -#define AQ_GlobalNvrProvisioning_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure nvrDataLength in AQ_GlobalNvrProvisioning_APPIA */ -#define AQ_GlobalNvrProvisioning_APPIA_nvrDataLength 0 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrDataLength in AQ_GlobalNvrProvisioning_APPIA */ -#define bits_AQ_GlobalNvrProvisioning_APPIA_nvrDataLength u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure nvrDataLength in AQ_GlobalNvrProvisioning_APPIA */ -#define word_AQ_GlobalNvrProvisioning_APPIA_nvrDataLength u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure nvrDummyLength in AQ_GlobalNvrProvisioning_APPIA */ -#define AQ_GlobalNvrProvisioning_APPIA_nvrDummyLength 0 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrDummyLength in AQ_GlobalNvrProvisioning_APPIA */ -#define bits_AQ_GlobalNvrProvisioning_APPIA_nvrDummyLength u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure nvrDummyLength in AQ_GlobalNvrProvisioning_APPIA */ -#define word_AQ_GlobalNvrProvisioning_APPIA_nvrDummyLength u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure nvrAddressLength in AQ_GlobalNvrProvisioning_APPIA */ -#define AQ_GlobalNvrProvisioning_APPIA_nvrAddressLength 0 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrAddressLength in AQ_GlobalNvrProvisioning_APPIA */ -#define bits_AQ_GlobalNvrProvisioning_APPIA_nvrAddressLength u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure nvrAddressLength in AQ_GlobalNvrProvisioning_APPIA */ -#define word_AQ_GlobalNvrProvisioning_APPIA_nvrAddressLength u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure nvrAddressLengthOverride in AQ_GlobalNvrProvisioning_APPIA */ -#define AQ_GlobalNvrProvisioning_APPIA_nvrAddressLengthOverride 1 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrAddressLengthOverride in AQ_GlobalNvrProvisioning_APPIA */ -#define bits_AQ_GlobalNvrProvisioning_APPIA_nvrAddressLengthOverride u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure nvrAddressLengthOverride in AQ_GlobalNvrProvisioning_APPIA */ -#define word_AQ_GlobalNvrProvisioning_APPIA_nvrAddressLengthOverride u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure nvrClockDivide in AQ_GlobalNvrProvisioning_APPIA */ -#define AQ_GlobalNvrProvisioning_APPIA_nvrClockDivide 1 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrClockDivide in AQ_GlobalNvrProvisioning_APPIA */ -#define bits_AQ_GlobalNvrProvisioning_APPIA_nvrClockDivide u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure nvrClockDivide in AQ_GlobalNvrProvisioning_APPIA */ -#define word_AQ_GlobalNvrProvisioning_APPIA_nvrClockDivide u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure nvrDaisyChainClockDivideOverride in AQ_GlobalNvrProvisioning_APPIA */ -#define AQ_GlobalNvrProvisioning_APPIA_nvrDaisyChainClockDivideOverride 2 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrDaisyChainClockDivideOverride in AQ_GlobalNvrProvisioning_APPIA */ -#define bits_AQ_GlobalNvrProvisioning_APPIA_nvrDaisyChainClockDivideOverride u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure nvrDaisyChainClockDivideOverride in AQ_GlobalNvrProvisioning_APPIA */ -#define word_AQ_GlobalNvrProvisioning_APPIA_nvrDaisyChainClockDivideOverride u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure nvrDaisyChainDisable in AQ_GlobalNvrProvisioning_APPIA */ -#define AQ_GlobalNvrProvisioning_APPIA_nvrDaisyChainDisable 2 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrDaisyChainDisable in AQ_GlobalNvrProvisioning_APPIA */ -#define bits_AQ_GlobalNvrProvisioning_APPIA_nvrDaisyChainDisable u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure nvrDaisyChainDisable in AQ_GlobalNvrProvisioning_APPIA */ -#define word_AQ_GlobalNvrProvisioning_APPIA_nvrDaisyChainDisable u2.word_2 - -/*! \brief Base register address of structure AQ_GlobalReservedProvisioning_APPIA */ -#define AQ_GlobalReservedProvisioning_APPIA_baseRegisterAddress 0xC470 -/*! \brief MMD address of structure AQ_GlobalReservedProvisioning_APPIA */ -#define AQ_GlobalReservedProvisioning_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure diagnosticsSelect in AQ_GlobalReservedProvisioning_APPIA */ -#define AQ_GlobalReservedProvisioning_APPIA_diagnosticsSelect 0 -/*! \brief Preprocessor variable to relate field to bit position in structure diagnosticsSelect in AQ_GlobalReservedProvisioning_APPIA */ -#define bits_AQ_GlobalReservedProvisioning_APPIA_diagnosticsSelect u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure diagnosticsSelect in AQ_GlobalReservedProvisioning_APPIA */ -#define word_AQ_GlobalReservedProvisioning_APPIA_diagnosticsSelect u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure extendedMdiDiagnosticsSelect in AQ_GlobalReservedProvisioning_APPIA */ -#define AQ_GlobalReservedProvisioning_APPIA_extendedMdiDiagnosticsSelect 0 -/*! \brief Preprocessor variable to relate field to bit position in structure extendedMdiDiagnosticsSelect in AQ_GlobalReservedProvisioning_APPIA */ -#define bits_AQ_GlobalReservedProvisioning_APPIA_extendedMdiDiagnosticsSelect u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure extendedMdiDiagnosticsSelect in AQ_GlobalReservedProvisioning_APPIA */ -#define word_AQ_GlobalReservedProvisioning_APPIA_extendedMdiDiagnosticsSelect u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure initiateComponentDiagnostics in AQ_GlobalReservedProvisioning_APPIA */ -#define AQ_GlobalReservedProvisioning_APPIA_initiateComponentDiagnostics 0 -/*! \brief Preprocessor variable to relate field to bit position in structure initiateComponentDiagnostics in AQ_GlobalReservedProvisioning_APPIA */ -#define bits_AQ_GlobalReservedProvisioning_APPIA_initiateComponentDiagnostics u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure initiateComponentDiagnostics in AQ_GlobalReservedProvisioning_APPIA */ -#define word_AQ_GlobalReservedProvisioning_APPIA_initiateComponentDiagnostics u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure initiateCableDiagnostics in AQ_GlobalReservedProvisioning_APPIA */ -#define AQ_GlobalReservedProvisioning_APPIA_initiateCableDiagnostics 0 -/*! \brief Preprocessor variable to relate field to bit position in structure initiateCableDiagnostics in AQ_GlobalReservedProvisioning_APPIA */ -#define bits_AQ_GlobalReservedProvisioning_APPIA_initiateCableDiagnostics u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure initiateCableDiagnostics in AQ_GlobalReservedProvisioning_APPIA */ -#define word_AQ_GlobalReservedProvisioning_APPIA_initiateCableDiagnostics u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioning_2 in AQ_GlobalReservedProvisioning_APPIA */ -#define AQ_GlobalReservedProvisioning_APPIA_reservedProvisioning_2 1 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioning_2 in AQ_GlobalReservedProvisioning_APPIA */ -#define bits_AQ_GlobalReservedProvisioning_APPIA_reservedProvisioning_2 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioning_2 in AQ_GlobalReservedProvisioning_APPIA */ -#define word_AQ_GlobalReservedProvisioning_APPIA_reservedProvisioning_2 u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure enableDaisy_chainHop_countOverride in AQ_GlobalReservedProvisioning_APPIA */ -#define AQ_GlobalReservedProvisioning_APPIA_enableDaisy_chainHop_countOverride 1 -/*! \brief Preprocessor variable to relate field to bit position in structure enableDaisy_chainHop_countOverride in AQ_GlobalReservedProvisioning_APPIA */ -#define bits_AQ_GlobalReservedProvisioning_APPIA_enableDaisy_chainHop_countOverride u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure enableDaisy_chainHop_countOverride in AQ_GlobalReservedProvisioning_APPIA */ -#define word_AQ_GlobalReservedProvisioning_APPIA_enableDaisy_chainHop_countOverride u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure daisy_chainHop_countOverrideValue in AQ_GlobalReservedProvisioning_APPIA */ -#define AQ_GlobalReservedProvisioning_APPIA_daisy_chainHop_countOverrideValue 1 -/*! \brief Preprocessor variable to relate field to bit position in structure daisy_chainHop_countOverrideValue in AQ_GlobalReservedProvisioning_APPIA */ -#define bits_AQ_GlobalReservedProvisioning_APPIA_daisy_chainHop_countOverrideValue u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure daisy_chainHop_countOverrideValue in AQ_GlobalReservedProvisioning_APPIA */ -#define word_AQ_GlobalReservedProvisioning_APPIA_daisy_chainHop_countOverrideValue u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure enableLvddPowerSupplyTuning in AQ_GlobalReservedProvisioning_APPIA */ -#define AQ_GlobalReservedProvisioning_APPIA_enableLvddPowerSupplyTuning 2 -/*! \brief Preprocessor variable to relate field to bit position in structure enableLvddPowerSupplyTuning in AQ_GlobalReservedProvisioning_APPIA */ -#define bits_AQ_GlobalReservedProvisioning_APPIA_enableLvddPowerSupplyTuning u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure enableLvddPowerSupplyTuning in AQ_GlobalReservedProvisioning_APPIA */ -#define word_AQ_GlobalReservedProvisioning_APPIA_enableLvddPowerSupplyTuning u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure enableVddPowerSupplyTuning in AQ_GlobalReservedProvisioning_APPIA */ -#define AQ_GlobalReservedProvisioning_APPIA_enableVddPowerSupplyTuning 2 -/*! \brief Preprocessor variable to relate field to bit position in structure enableVddPowerSupplyTuning in AQ_GlobalReservedProvisioning_APPIA */ -#define bits_AQ_GlobalReservedProvisioning_APPIA_enableVddPowerSupplyTuning u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure enableVddPowerSupplyTuning in AQ_GlobalReservedProvisioning_APPIA */ -#define word_AQ_GlobalReservedProvisioning_APPIA_enableVddPowerSupplyTuning u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure tunableExternalLvddPowerSupplyPresent in AQ_GlobalReservedProvisioning_APPIA */ -#define AQ_GlobalReservedProvisioning_APPIA_tunableExternalLvddPowerSupplyPresent 2 -/*! \brief Preprocessor variable to relate field to bit position in structure tunableExternalLvddPowerSupplyPresent in AQ_GlobalReservedProvisioning_APPIA */ -#define bits_AQ_GlobalReservedProvisioning_APPIA_tunableExternalLvddPowerSupplyPresent u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure tunableExternalLvddPowerSupplyPresent in AQ_GlobalReservedProvisioning_APPIA */ -#define word_AQ_GlobalReservedProvisioning_APPIA_tunableExternalLvddPowerSupplyPresent u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure tunableExternalVddPowerSupplyPresent in AQ_GlobalReservedProvisioning_APPIA */ -#define AQ_GlobalReservedProvisioning_APPIA_tunableExternalVddPowerSupplyPresent 2 -/*! \brief Preprocessor variable to relate field to bit position in structure tunableExternalVddPowerSupplyPresent in AQ_GlobalReservedProvisioning_APPIA */ -#define bits_AQ_GlobalReservedProvisioning_APPIA_tunableExternalVddPowerSupplyPresent u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure tunableExternalVddPowerSupplyPresent in AQ_GlobalReservedProvisioning_APPIA */ -#define word_AQ_GlobalReservedProvisioning_APPIA_tunableExternalVddPowerSupplyPresent u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure enableXenpakRegisterSpace in AQ_GlobalReservedProvisioning_APPIA */ -#define AQ_GlobalReservedProvisioning_APPIA_enableXenpakRegisterSpace 2 -/*! \brief Preprocessor variable to relate field to bit position in structure enableXenpakRegisterSpace in AQ_GlobalReservedProvisioning_APPIA */ -#define bits_AQ_GlobalReservedProvisioning_APPIA_enableXenpakRegisterSpace u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure enableXenpakRegisterSpace in AQ_GlobalReservedProvisioning_APPIA */ -#define word_AQ_GlobalReservedProvisioning_APPIA_enableXenpakRegisterSpace u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure enable_5thChannelRfiCancellation in AQ_GlobalReservedProvisioning_APPIA */ -#define AQ_GlobalReservedProvisioning_APPIA_enable_5thChannelRfiCancellation 2 -/*! \brief Preprocessor variable to relate field to bit position in structure enable_5thChannelRfiCancellation in AQ_GlobalReservedProvisioning_APPIA */ -#define bits_AQ_GlobalReservedProvisioning_APPIA_enable_5thChannelRfiCancellation u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure enable_5thChannelRfiCancellation in AQ_GlobalReservedProvisioning_APPIA */ -#define word_AQ_GlobalReservedProvisioning_APPIA_enable_5thChannelRfiCancellation u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure trainingSNR in AQ_GlobalReservedProvisioning_APPIA */ -#define AQ_GlobalReservedProvisioning_APPIA_trainingSNR 4 -/*! \brief Preprocessor variable to relate field to bit position in structure trainingSNR in AQ_GlobalReservedProvisioning_APPIA */ -#define bits_AQ_GlobalReservedProvisioning_APPIA_trainingSNR u4.bits_4 -/*! \brief Preprocessor variable to relate field to word position in structure trainingSNR in AQ_GlobalReservedProvisioning_APPIA */ -#define word_AQ_GlobalReservedProvisioning_APPIA_trainingSNR u4.word_4 -/*! \brief Preprocessor variable to relate field to word number in structure smartPower_downStatus in AQ_GlobalReservedProvisioning_APPIA */ -#define AQ_GlobalReservedProvisioning_APPIA_smartPower_downStatus 5 -/*! \brief Preprocessor variable to relate field to bit position in structure smartPower_downStatus in AQ_GlobalReservedProvisioning_APPIA */ -#define bits_AQ_GlobalReservedProvisioning_APPIA_smartPower_downStatus u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure smartPower_downStatus in AQ_GlobalReservedProvisioning_APPIA */ -#define word_AQ_GlobalReservedProvisioning_APPIA_smartPower_downStatus u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioning_6 in AQ_GlobalReservedProvisioning_APPIA */ -#define AQ_GlobalReservedProvisioning_APPIA_reservedProvisioning_6 5 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioning_6 in AQ_GlobalReservedProvisioning_APPIA */ -#define bits_AQ_GlobalReservedProvisioning_APPIA_reservedProvisioning_6 u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioning_6 in AQ_GlobalReservedProvisioning_APPIA */ -#define word_AQ_GlobalReservedProvisioning_APPIA_reservedProvisioning_6 u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure cfrLpDisableTimer in AQ_GlobalReservedProvisioning_APPIA */ -#define AQ_GlobalReservedProvisioning_APPIA_cfrLpDisableTimer 5 -/*! \brief Preprocessor variable to relate field to bit position in structure cfrLpDisableTimer in AQ_GlobalReservedProvisioning_APPIA */ -#define bits_AQ_GlobalReservedProvisioning_APPIA_cfrLpDisableTimer u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure cfrLpDisableTimer in AQ_GlobalReservedProvisioning_APPIA */ -#define word_AQ_GlobalReservedProvisioning_APPIA_cfrLpDisableTimer u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure cfrLpExtendedMaxwait in AQ_GlobalReservedProvisioning_APPIA */ -#define AQ_GlobalReservedProvisioning_APPIA_cfrLpExtendedMaxwait 5 -/*! \brief Preprocessor variable to relate field to bit position in structure cfrLpExtendedMaxwait in AQ_GlobalReservedProvisioning_APPIA */ -#define bits_AQ_GlobalReservedProvisioning_APPIA_cfrLpExtendedMaxwait u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure cfrLpExtendedMaxwait in AQ_GlobalReservedProvisioning_APPIA */ -#define word_AQ_GlobalReservedProvisioning_APPIA_cfrLpExtendedMaxwait u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure cfrLpTHP in AQ_GlobalReservedProvisioning_APPIA */ -#define AQ_GlobalReservedProvisioning_APPIA_cfrLpTHP 5 -/*! \brief Preprocessor variable to relate field to bit position in structure cfrLpTHP in AQ_GlobalReservedProvisioning_APPIA */ -#define bits_AQ_GlobalReservedProvisioning_APPIA_cfrLpTHP u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure cfrLpTHP in AQ_GlobalReservedProvisioning_APPIA */ -#define word_AQ_GlobalReservedProvisioning_APPIA_cfrLpTHP u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure cfrLpSupport in AQ_GlobalReservedProvisioning_APPIA */ -#define AQ_GlobalReservedProvisioning_APPIA_cfrLpSupport 5 -/*! \brief Preprocessor variable to relate field to bit position in structure cfrLpSupport in AQ_GlobalReservedProvisioning_APPIA */ -#define bits_AQ_GlobalReservedProvisioning_APPIA_cfrLpSupport u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure cfrLpSupport in AQ_GlobalReservedProvisioning_APPIA */ -#define word_AQ_GlobalReservedProvisioning_APPIA_cfrLpSupport u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure cfrDisableTimer in AQ_GlobalReservedProvisioning_APPIA */ -#define AQ_GlobalReservedProvisioning_APPIA_cfrDisableTimer 5 -/*! \brief Preprocessor variable to relate field to bit position in structure cfrDisableTimer in AQ_GlobalReservedProvisioning_APPIA */ -#define bits_AQ_GlobalReservedProvisioning_APPIA_cfrDisableTimer u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure cfrDisableTimer in AQ_GlobalReservedProvisioning_APPIA */ -#define word_AQ_GlobalReservedProvisioning_APPIA_cfrDisableTimer u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure cfrExtendedMaxwait in AQ_GlobalReservedProvisioning_APPIA */ -#define AQ_GlobalReservedProvisioning_APPIA_cfrExtendedMaxwait 5 -/*! \brief Preprocessor variable to relate field to bit position in structure cfrExtendedMaxwait in AQ_GlobalReservedProvisioning_APPIA */ -#define bits_AQ_GlobalReservedProvisioning_APPIA_cfrExtendedMaxwait u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure cfrExtendedMaxwait in AQ_GlobalReservedProvisioning_APPIA */ -#define word_AQ_GlobalReservedProvisioning_APPIA_cfrExtendedMaxwait u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure cfrTHP in AQ_GlobalReservedProvisioning_APPIA */ -#define AQ_GlobalReservedProvisioning_APPIA_cfrTHP 5 -/*! \brief Preprocessor variable to relate field to bit position in structure cfrTHP in AQ_GlobalReservedProvisioning_APPIA */ -#define bits_AQ_GlobalReservedProvisioning_APPIA_cfrTHP u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure cfrTHP in AQ_GlobalReservedProvisioning_APPIA */ -#define word_AQ_GlobalReservedProvisioning_APPIA_cfrTHP u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure cfrSupport in AQ_GlobalReservedProvisioning_APPIA */ -#define AQ_GlobalReservedProvisioning_APPIA_cfrSupport 5 -/*! \brief Preprocessor variable to relate field to bit position in structure cfrSupport in AQ_GlobalReservedProvisioning_APPIA */ -#define bits_AQ_GlobalReservedProvisioning_APPIA_cfrSupport u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure cfrSupport in AQ_GlobalReservedProvisioning_APPIA */ -#define word_AQ_GlobalReservedProvisioning_APPIA_cfrSupport u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure deadlockAvoidanceEnable in AQ_GlobalReservedProvisioning_APPIA */ -#define AQ_GlobalReservedProvisioning_APPIA_deadlockAvoidanceEnable 5 -/*! \brief Preprocessor variable to relate field to bit position in structure deadlockAvoidanceEnable in AQ_GlobalReservedProvisioning_APPIA */ -#define bits_AQ_GlobalReservedProvisioning_APPIA_deadlockAvoidanceEnable u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure deadlockAvoidanceEnable in AQ_GlobalReservedProvisioning_APPIA */ -#define word_AQ_GlobalReservedProvisioning_APPIA_deadlockAvoidanceEnable u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure smartPower_downEnable in AQ_GlobalReservedProvisioning_APPIA */ -#define AQ_GlobalReservedProvisioning_APPIA_smartPower_downEnable 5 -/*! \brief Preprocessor variable to relate field to bit position in structure smartPower_downEnable in AQ_GlobalReservedProvisioning_APPIA */ -#define bits_AQ_GlobalReservedProvisioning_APPIA_smartPower_downEnable u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure smartPower_downEnable in AQ_GlobalReservedProvisioning_APPIA */ -#define word_AQ_GlobalReservedProvisioning_APPIA_smartPower_downEnable u5.word_5 - -/*! \brief Base register address of structure AQ_GlobalCableDiagnosticStatus_APPIA */ -#define AQ_GlobalCableDiagnosticStatus_APPIA_baseRegisterAddress 0xC800 -/*! \brief MMD address of structure AQ_GlobalCableDiagnosticStatus_APPIA */ -#define AQ_GlobalCableDiagnosticStatus_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure pairAStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define AQ_GlobalCableDiagnosticStatus_APPIA_pairAStatus 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pairAStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairAStatus u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pairAStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairAStatus u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pairBStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define AQ_GlobalCableDiagnosticStatus_APPIA_pairBStatus 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pairBStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairBStatus u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pairBStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairBStatus u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pairCStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define AQ_GlobalCableDiagnosticStatus_APPIA_pairCStatus 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pairCStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairCStatus u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pairCStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairCStatus u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pairDStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define AQ_GlobalCableDiagnosticStatus_APPIA_pairDStatus 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pairDStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairDStatus u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pairDStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairDStatus u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define AQ_GlobalCableDiagnosticStatus_APPIA_pairAReflection_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairAReflection_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairAReflection_1 u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define AQ_GlobalCableDiagnosticStatus_APPIA_pairAReflection_2 1 -/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairAReflection_2 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairAReflection_2 u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure impulseResponseMSW in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define AQ_GlobalCableDiagnosticStatus_APPIA_impulseResponseMSW 2 -/*! \brief Preprocessor variable to relate field to bit position in structure impulseResponseMSW in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_impulseResponseMSW u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure impulseResponseMSW in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define word_AQ_GlobalCableDiagnosticStatus_APPIA_impulseResponseMSW u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define AQ_GlobalCableDiagnosticStatus_APPIA_pairBReflection_1 3 -/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairBReflection_1 u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairBReflection_1 u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define AQ_GlobalCableDiagnosticStatus_APPIA_pairBReflection_2 3 -/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairBReflection_2 u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairBReflection_2 u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure impulseResponseLSW in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define AQ_GlobalCableDiagnosticStatus_APPIA_impulseResponseLSW 4 -/*! \brief Preprocessor variable to relate field to bit position in structure impulseResponseLSW in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_impulseResponseLSW u4.bits_4 -/*! \brief Preprocessor variable to relate field to word position in structure impulseResponseLSW in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define word_AQ_GlobalCableDiagnosticStatus_APPIA_impulseResponseLSW u4.word_4 -/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define AQ_GlobalCableDiagnosticStatus_APPIA_pairCReflection_1 5 -/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairCReflection_1 u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairCReflection_1 u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define AQ_GlobalCableDiagnosticStatus_APPIA_pairCReflection_2 5 -/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairCReflection_2 u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairCReflection_2 u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define AQ_GlobalCableDiagnosticStatus_APPIA_reserved_1 6 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_reserved_1 u6.bits_6 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define word_AQ_GlobalCableDiagnosticStatus_APPIA_reserved_1 u6.word_6 -/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define AQ_GlobalCableDiagnosticStatus_APPIA_pairDReflection_1 7 -/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairDReflection_1 u7.bits_7 -/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairDReflection_1 u7.word_7 -/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define AQ_GlobalCableDiagnosticStatus_APPIA_pairDReflection_2 7 -/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairDReflection_2 u7.bits_7 -/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairDReflection_2 u7.word_7 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define AQ_GlobalCableDiagnosticStatus_APPIA_reserved_2 8 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_reserved_2 u8.bits_8 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define word_AQ_GlobalCableDiagnosticStatus_APPIA_reserved_2 u8.word_8 - -/*! \brief Base register address of structure AQ_GlobalThermalStatus_APPIA */ -#define AQ_GlobalThermalStatus_APPIA_baseRegisterAddress 0xC820 -/*! \brief MMD address of structure AQ_GlobalThermalStatus_APPIA */ -#define AQ_GlobalThermalStatus_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure temperature in AQ_GlobalThermalStatus_APPIA */ -#define AQ_GlobalThermalStatus_APPIA_temperature 0 -/*! \brief Preprocessor variable to relate field to bit position in structure temperature in AQ_GlobalThermalStatus_APPIA */ -#define bits_AQ_GlobalThermalStatus_APPIA_temperature u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure temperature in AQ_GlobalThermalStatus_APPIA */ -#define word_AQ_GlobalThermalStatus_APPIA_temperature u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure temperatureReady in AQ_GlobalThermalStatus_APPIA */ -#define AQ_GlobalThermalStatus_APPIA_temperatureReady 1 -/*! \brief Preprocessor variable to relate field to bit position in structure temperatureReady in AQ_GlobalThermalStatus_APPIA */ -#define bits_AQ_GlobalThermalStatus_APPIA_temperatureReady u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure temperatureReady in AQ_GlobalThermalStatus_APPIA */ -#define word_AQ_GlobalThermalStatus_APPIA_temperatureReady u1.word_1 - -/*! \brief Base register address of structure AQ_GlobalGeneralStatus_APPIA */ -#define AQ_GlobalGeneralStatus_APPIA_baseRegisterAddress 0xC830 -/*! \brief MMD address of structure AQ_GlobalGeneralStatus_APPIA */ -#define AQ_GlobalGeneralStatus_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureFailureState in AQ_GlobalGeneralStatus_APPIA */ -#define AQ_GlobalGeneralStatus_APPIA_highTemperatureFailureState 0 -/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureFailureState in AQ_GlobalGeneralStatus_APPIA */ -#define bits_AQ_GlobalGeneralStatus_APPIA_highTemperatureFailureState u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureFailureState in AQ_GlobalGeneralStatus_APPIA */ -#define word_AQ_GlobalGeneralStatus_APPIA_highTemperatureFailureState u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureFailureState in AQ_GlobalGeneralStatus_APPIA */ -#define AQ_GlobalGeneralStatus_APPIA_lowTemperatureFailureState 0 -/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureFailureState in AQ_GlobalGeneralStatus_APPIA */ -#define bits_AQ_GlobalGeneralStatus_APPIA_lowTemperatureFailureState u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureFailureState in AQ_GlobalGeneralStatus_APPIA */ -#define word_AQ_GlobalGeneralStatus_APPIA_lowTemperatureFailureState u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureWarningState in AQ_GlobalGeneralStatus_APPIA */ -#define AQ_GlobalGeneralStatus_APPIA_highTemperatureWarningState 0 -/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureWarningState in AQ_GlobalGeneralStatus_APPIA */ -#define bits_AQ_GlobalGeneralStatus_APPIA_highTemperatureWarningState u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureWarningState in AQ_GlobalGeneralStatus_APPIA */ -#define word_AQ_GlobalGeneralStatus_APPIA_highTemperatureWarningState u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureWarningState in AQ_GlobalGeneralStatus_APPIA */ -#define AQ_GlobalGeneralStatus_APPIA_lowTemperatureWarningState 0 -/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureWarningState in AQ_GlobalGeneralStatus_APPIA */ -#define bits_AQ_GlobalGeneralStatus_APPIA_lowTemperatureWarningState u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureWarningState in AQ_GlobalGeneralStatus_APPIA */ -#define word_AQ_GlobalGeneralStatus_APPIA_lowTemperatureWarningState u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure processorIntensiveMdioOperationIn_Progress in AQ_GlobalGeneralStatus_APPIA */ -#define AQ_GlobalGeneralStatus_APPIA_processorIntensiveMdioOperationIn_Progress 1 -/*! \brief Preprocessor variable to relate field to bit position in structure processorIntensiveMdioOperationIn_Progress in AQ_GlobalGeneralStatus_APPIA */ -#define bits_AQ_GlobalGeneralStatus_APPIA_processorIntensiveMdioOperationIn_Progress u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure processorIntensiveMdioOperationIn_Progress in AQ_GlobalGeneralStatus_APPIA */ -#define word_AQ_GlobalGeneralStatus_APPIA_processorIntensiveMdioOperationIn_Progress u1.word_1 - -/*! \brief Base register address of structure AQ_GlobalPinStatus_APPIA */ -#define AQ_GlobalPinStatus_APPIA_baseRegisterAddress 0xC840 -/*! \brief MMD address of structure AQ_GlobalPinStatus_APPIA */ -#define AQ_GlobalPinStatus_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mdioBootLoad in AQ_GlobalPinStatus_APPIA */ -#define AQ_GlobalPinStatus_APPIA_mdioBootLoad 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mdioBootLoad in AQ_GlobalPinStatus_APPIA */ -#define bits_AQ_GlobalPinStatus_APPIA_mdioBootLoad u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mdioBootLoad in AQ_GlobalPinStatus_APPIA */ -#define word_AQ_GlobalPinStatus_APPIA_mdioBootLoad u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure packageConnectivity in AQ_GlobalPinStatus_APPIA */ -#define AQ_GlobalPinStatus_APPIA_packageConnectivity 0 -/*! \brief Preprocessor variable to relate field to bit position in structure packageConnectivity in AQ_GlobalPinStatus_APPIA */ -#define bits_AQ_GlobalPinStatus_APPIA_packageConnectivity u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure packageConnectivity in AQ_GlobalPinStatus_APPIA */ -#define word_AQ_GlobalPinStatus_APPIA_packageConnectivity u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure txEnable in AQ_GlobalPinStatus_APPIA */ -#define AQ_GlobalPinStatus_APPIA_txEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure txEnable in AQ_GlobalPinStatus_APPIA */ -#define bits_AQ_GlobalPinStatus_APPIA_txEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure txEnable in AQ_GlobalPinStatus_APPIA */ -#define word_AQ_GlobalPinStatus_APPIA_txEnable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure ledPullupState in AQ_GlobalPinStatus_APPIA */ -#define AQ_GlobalPinStatus_APPIA_ledPullupState 0 -/*! \brief Preprocessor variable to relate field to bit position in structure ledPullupState in AQ_GlobalPinStatus_APPIA */ -#define bits_AQ_GlobalPinStatus_APPIA_ledPullupState u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure ledPullupState in AQ_GlobalPinStatus_APPIA */ -#define word_AQ_GlobalPinStatus_APPIA_ledPullupState u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalDaisyChainStatus_APPIA */ -#define AQ_GlobalDaisyChainStatus_APPIA_baseRegisterAddress 0xC842 -/*! \brief MMD address of structure AQ_GlobalDaisyChainStatus_APPIA */ -#define AQ_GlobalDaisyChainStatus_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure rxDaisyChainCalculatedCrc in AQ_GlobalDaisyChainStatus_APPIA */ -#define AQ_GlobalDaisyChainStatus_APPIA_rxDaisyChainCalculatedCrc 0 -/*! \brief Preprocessor variable to relate field to bit position in structure rxDaisyChainCalculatedCrc in AQ_GlobalDaisyChainStatus_APPIA */ -#define bits_AQ_GlobalDaisyChainStatus_APPIA_rxDaisyChainCalculatedCrc u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure rxDaisyChainCalculatedCrc in AQ_GlobalDaisyChainStatus_APPIA */ -#define word_AQ_GlobalDaisyChainStatus_APPIA_rxDaisyChainCalculatedCrc u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalFaultMessage_APPIA */ -#define AQ_GlobalFaultMessage_APPIA_baseRegisterAddress 0xC850 -/*! \brief MMD address of structure AQ_GlobalFaultMessage_APPIA */ -#define AQ_GlobalFaultMessage_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure message in AQ_GlobalFaultMessage_APPIA */ -#define AQ_GlobalFaultMessage_APPIA_message 0 -/*! \brief Preprocessor variable to relate field to bit position in structure message in AQ_GlobalFaultMessage_APPIA */ -#define bits_AQ_GlobalFaultMessage_APPIA_message u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure message in AQ_GlobalFaultMessage_APPIA */ -#define word_AQ_GlobalFaultMessage_APPIA_message u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalPrimaryStatus_APPIA */ -#define AQ_GlobalPrimaryStatus_APPIA_baseRegisterAddress 0xC851 -/*! \brief MMD address of structure AQ_GlobalPrimaryStatus_APPIA */ -#define AQ_GlobalPrimaryStatus_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure primaryStatus in AQ_GlobalPrimaryStatus_APPIA */ -#define AQ_GlobalPrimaryStatus_APPIA_primaryStatus 0 -/*! \brief Preprocessor variable to relate field to bit position in structure primaryStatus in AQ_GlobalPrimaryStatus_APPIA */ -#define bits_AQ_GlobalPrimaryStatus_APPIA_primaryStatus u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure primaryStatus in AQ_GlobalPrimaryStatus_APPIA */ -#define word_AQ_GlobalPrimaryStatus_APPIA_primaryStatus u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_baseRegisterAddress 0xC880 -/*! \brief MMD address of structure AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure reserved_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_1 0 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_1 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_1 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_1 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_1 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_1 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_2 0 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_2 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_2 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_2 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_2 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_2 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_3 0 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_3 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_3 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_3 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_3 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_3 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_4 0 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_4 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_4 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_4 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_4 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_4 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_5 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_5 1 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_5 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_5 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_5 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_5 u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_1 u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_6 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_6 1 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_6 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_6 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_6 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_6 u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_2 1 -/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_2 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_2 u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_7 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_7 1 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_7 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_7 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_7 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_7 u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_3 1 -/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_3 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_3 u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_8 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_8 1 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_8 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_8 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_8 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_8 u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_4 1 -/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_4 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_4 u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_9 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_9 2 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_9 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_9 u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_9 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_9 u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_1 2 -/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_1 u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_1 u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_10 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_10 2 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_10 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_10 u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_10 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_10 u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_2 2 -/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_2 u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_2 u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_11 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_11 2 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_11 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_11 u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_11 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_11 u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_3 2 -/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_3 u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_3 u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_12 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_12 2 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_12 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_12 u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_12 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_12 u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_4 2 -/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_4 u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_4 u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_13 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_13 3 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_13 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_13 u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_13 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_13 u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_1 3 -/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_1 u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_1 u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_14 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_14 3 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_14 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_14 u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_14 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_14 u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_2 3 -/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_2 u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_2 u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_15 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_15 3 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_15 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_15 u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_15 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_15 u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_3 3 -/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_3 u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_3 u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_16 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_16 3 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_16 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_16 u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_16 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_16 u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_4 3 -/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_4 u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_4 u3.word_3 - -/*! \brief Base register address of structure AQ_GlobalStatus_APPIA */ -#define AQ_GlobalStatus_APPIA_baseRegisterAddress 0xC884 -/*! \brief MMD address of structure AQ_GlobalStatus_APPIA */ -#define AQ_GlobalStatus_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure reservedStatus_0 in AQ_GlobalStatus_APPIA */ -#define AQ_GlobalStatus_APPIA_reservedStatus_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedStatus_0 in AQ_GlobalStatus_APPIA */ -#define bits_AQ_GlobalStatus_APPIA_reservedStatus_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure reservedStatus_0 in AQ_GlobalStatus_APPIA */ -#define word_AQ_GlobalStatus_APPIA_reservedStatus_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure cableLength in AQ_GlobalStatus_APPIA */ -#define AQ_GlobalStatus_APPIA_cableLength 0 -/*! \brief Preprocessor variable to relate field to bit position in structure cableLength in AQ_GlobalStatus_APPIA */ -#define bits_AQ_GlobalStatus_APPIA_cableLength u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure cableLength in AQ_GlobalStatus_APPIA */ -#define word_AQ_GlobalStatus_APPIA_cableLength u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalReservedStatus_APPIA */ -#define AQ_GlobalReservedStatus_APPIA_baseRegisterAddress 0xC885 -/*! \brief MMD address of structure AQ_GlobalReservedStatus_APPIA */ -#define AQ_GlobalReservedStatus_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure nearlySecondsMSW in AQ_GlobalReservedStatus_APPIA */ -#define AQ_GlobalReservedStatus_APPIA_nearlySecondsMSW 0 -/*! \brief Preprocessor variable to relate field to bit position in structure nearlySecondsMSW in AQ_GlobalReservedStatus_APPIA */ -#define bits_AQ_GlobalReservedStatus_APPIA_nearlySecondsMSW u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure nearlySecondsMSW in AQ_GlobalReservedStatus_APPIA */ -#define word_AQ_GlobalReservedStatus_APPIA_nearlySecondsMSW u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure xenpakNvrStatus in AQ_GlobalReservedStatus_APPIA */ -#define AQ_GlobalReservedStatus_APPIA_xenpakNvrStatus 0 -/*! \brief Preprocessor variable to relate field to bit position in structure xenpakNvrStatus in AQ_GlobalReservedStatus_APPIA */ -#define bits_AQ_GlobalReservedStatus_APPIA_xenpakNvrStatus u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure xenpakNvrStatus in AQ_GlobalReservedStatus_APPIA */ -#define word_AQ_GlobalReservedStatus_APPIA_xenpakNvrStatus u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure romRevision in AQ_GlobalReservedStatus_APPIA */ -#define AQ_GlobalReservedStatus_APPIA_romRevision 0 -/*! \brief Preprocessor variable to relate field to bit position in structure romRevision in AQ_GlobalReservedStatus_APPIA */ -#define bits_AQ_GlobalReservedStatus_APPIA_romRevision u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure romRevision in AQ_GlobalReservedStatus_APPIA */ -#define word_AQ_GlobalReservedStatus_APPIA_romRevision u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure nearlySecondsLSW in AQ_GlobalReservedStatus_APPIA */ -#define AQ_GlobalReservedStatus_APPIA_nearlySecondsLSW 1 -/*! \brief Preprocessor variable to relate field to bit position in structure nearlySecondsLSW in AQ_GlobalReservedStatus_APPIA */ -#define bits_AQ_GlobalReservedStatus_APPIA_nearlySecondsLSW u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure nearlySecondsLSW in AQ_GlobalReservedStatus_APPIA */ -#define word_AQ_GlobalReservedStatus_APPIA_nearlySecondsLSW u1.word_1 - -/*! \brief Base register address of structure AQ_GlobalAlarms_APPIA */ -#define AQ_GlobalAlarms_APPIA_baseRegisterAddress 0xCC00 -/*! \brief MMD address of structure AQ_GlobalAlarms_APPIA */ -#define AQ_GlobalAlarms_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureFailure in AQ_GlobalAlarms_APPIA */ -#define AQ_GlobalAlarms_APPIA_highTemperatureFailure 0 -/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureFailure in AQ_GlobalAlarms_APPIA */ -#define bits_AQ_GlobalAlarms_APPIA_highTemperatureFailure u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureFailure in AQ_GlobalAlarms_APPIA */ -#define word_AQ_GlobalAlarms_APPIA_highTemperatureFailure u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureFailure in AQ_GlobalAlarms_APPIA */ -#define AQ_GlobalAlarms_APPIA_lowTemperatureFailure 0 -/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureFailure in AQ_GlobalAlarms_APPIA */ -#define bits_AQ_GlobalAlarms_APPIA_lowTemperatureFailure u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureFailure in AQ_GlobalAlarms_APPIA */ -#define word_AQ_GlobalAlarms_APPIA_lowTemperatureFailure u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureWarning in AQ_GlobalAlarms_APPIA */ -#define AQ_GlobalAlarms_APPIA_highTemperatureWarning 0 -/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureWarning in AQ_GlobalAlarms_APPIA */ -#define bits_AQ_GlobalAlarms_APPIA_highTemperatureWarning u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureWarning in AQ_GlobalAlarms_APPIA */ -#define word_AQ_GlobalAlarms_APPIA_highTemperatureWarning u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureWarning in AQ_GlobalAlarms_APPIA */ -#define AQ_GlobalAlarms_APPIA_lowTemperatureWarning 0 -/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureWarning in AQ_GlobalAlarms_APPIA */ -#define bits_AQ_GlobalAlarms_APPIA_lowTemperatureWarning u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureWarning in AQ_GlobalAlarms_APPIA */ -#define word_AQ_GlobalAlarms_APPIA_lowTemperatureWarning u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure resetCompleted in AQ_GlobalAlarms_APPIA */ -#define AQ_GlobalAlarms_APPIA_resetCompleted 0 -/*! \brief Preprocessor variable to relate field to bit position in structure resetCompleted in AQ_GlobalAlarms_APPIA */ -#define bits_AQ_GlobalAlarms_APPIA_resetCompleted u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure resetCompleted in AQ_GlobalAlarms_APPIA */ -#define word_AQ_GlobalAlarms_APPIA_resetCompleted u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure deviceFault in AQ_GlobalAlarms_APPIA */ -#define AQ_GlobalAlarms_APPIA_deviceFault 0 -/*! \brief Preprocessor variable to relate field to bit position in structure deviceFault in AQ_GlobalAlarms_APPIA */ -#define bits_AQ_GlobalAlarms_APPIA_deviceFault u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure deviceFault in AQ_GlobalAlarms_APPIA */ -#define word_AQ_GlobalAlarms_APPIA_deviceFault u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmA in AQ_GlobalAlarms_APPIA */ -#define AQ_GlobalAlarms_APPIA_reservedAlarmA 0 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmA in AQ_GlobalAlarms_APPIA */ -#define bits_AQ_GlobalAlarms_APPIA_reservedAlarmA u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmA in AQ_GlobalAlarms_APPIA */ -#define word_AQ_GlobalAlarms_APPIA_reservedAlarmA u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmB in AQ_GlobalAlarms_APPIA */ -#define AQ_GlobalAlarms_APPIA_reservedAlarmB 0 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmB in AQ_GlobalAlarms_APPIA */ -#define bits_AQ_GlobalAlarms_APPIA_reservedAlarmB u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmB in AQ_GlobalAlarms_APPIA */ -#define word_AQ_GlobalAlarms_APPIA_reservedAlarmB u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmC in AQ_GlobalAlarms_APPIA */ -#define AQ_GlobalAlarms_APPIA_reservedAlarmC 0 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmC in AQ_GlobalAlarms_APPIA */ -#define bits_AQ_GlobalAlarms_APPIA_reservedAlarmC u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmC in AQ_GlobalAlarms_APPIA */ -#define word_AQ_GlobalAlarms_APPIA_reservedAlarmC u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmD in AQ_GlobalAlarms_APPIA */ -#define AQ_GlobalAlarms_APPIA_reservedAlarmD 0 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmD in AQ_GlobalAlarms_APPIA */ -#define bits_AQ_GlobalAlarms_APPIA_reservedAlarmD u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmD in AQ_GlobalAlarms_APPIA */ -#define word_AQ_GlobalAlarms_APPIA_reservedAlarmD u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure smartPower_downEntered in AQ_GlobalAlarms_APPIA */ -#define AQ_GlobalAlarms_APPIA_smartPower_downEntered 1 -/*! \brief Preprocessor variable to relate field to bit position in structure smartPower_downEntered in AQ_GlobalAlarms_APPIA */ -#define bits_AQ_GlobalAlarms_APPIA_smartPower_downEntered u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure smartPower_downEntered in AQ_GlobalAlarms_APPIA */ -#define word_AQ_GlobalAlarms_APPIA_smartPower_downEntered u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure xenpakAlarm in AQ_GlobalAlarms_APPIA */ -#define AQ_GlobalAlarms_APPIA_xenpakAlarm 1 -/*! \brief Preprocessor variable to relate field to bit position in structure xenpakAlarm in AQ_GlobalAlarms_APPIA */ -#define bits_AQ_GlobalAlarms_APPIA_xenpakAlarm u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure xenpakAlarm in AQ_GlobalAlarms_APPIA */ -#define word_AQ_GlobalAlarms_APPIA_xenpakAlarm u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarms in AQ_GlobalAlarms_APPIA */ -#define AQ_GlobalAlarms_APPIA_reservedAlarms 1 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarms in AQ_GlobalAlarms_APPIA */ -#define bits_AQ_GlobalAlarms_APPIA_reservedAlarms u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarms in AQ_GlobalAlarms_APPIA */ -#define word_AQ_GlobalAlarms_APPIA_reservedAlarms u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure mdioCommandHandlingOverflow in AQ_GlobalAlarms_APPIA */ -#define AQ_GlobalAlarms_APPIA_mdioCommandHandlingOverflow 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mdioCommandHandlingOverflow in AQ_GlobalAlarms_APPIA */ -#define bits_AQ_GlobalAlarms_APPIA_mdioCommandHandlingOverflow u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mdioCommandHandlingOverflow in AQ_GlobalAlarms_APPIA */ -#define word_AQ_GlobalAlarms_APPIA_mdioCommandHandlingOverflow u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure diagnosticAlarm in AQ_GlobalAlarms_APPIA */ -#define AQ_GlobalAlarms_APPIA_diagnosticAlarm 1 -/*! \brief Preprocessor variable to relate field to bit position in structure diagnosticAlarm in AQ_GlobalAlarms_APPIA */ -#define bits_AQ_GlobalAlarms_APPIA_diagnosticAlarm u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure diagnosticAlarm in AQ_GlobalAlarms_APPIA */ -#define word_AQ_GlobalAlarms_APPIA_diagnosticAlarm u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure nvrOperationComplete in AQ_GlobalAlarms_APPIA */ -#define AQ_GlobalAlarms_APPIA_nvrOperationComplete 2 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrOperationComplete in AQ_GlobalAlarms_APPIA */ -#define bits_AQ_GlobalAlarms_APPIA_nvrOperationComplete u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure nvrOperationComplete in AQ_GlobalAlarms_APPIA */ -#define word_AQ_GlobalAlarms_APPIA_nvrOperationComplete u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure mailboxOperation_Complete in AQ_GlobalAlarms_APPIA */ -#define AQ_GlobalAlarms_APPIA_mailboxOperation_Complete 2 -/*! \brief Preprocessor variable to relate field to bit position in structure mailboxOperation_Complete in AQ_GlobalAlarms_APPIA */ -#define bits_AQ_GlobalAlarms_APPIA_mailboxOperation_Complete u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure mailboxOperation_Complete in AQ_GlobalAlarms_APPIA */ -#define word_AQ_GlobalAlarms_APPIA_mailboxOperation_Complete u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure upDramParityError in AQ_GlobalAlarms_APPIA */ -#define AQ_GlobalAlarms_APPIA_upDramParityError 2 -/*! \brief Preprocessor variable to relate field to bit position in structure upDramParityError in AQ_GlobalAlarms_APPIA */ -#define bits_AQ_GlobalAlarms_APPIA_upDramParityError u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure upDramParityError in AQ_GlobalAlarms_APPIA */ -#define word_AQ_GlobalAlarms_APPIA_upDramParityError u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure upIramParityError in AQ_GlobalAlarms_APPIA */ -#define AQ_GlobalAlarms_APPIA_upIramParityError 2 -/*! \brief Preprocessor variable to relate field to bit position in structure upIramParityError in AQ_GlobalAlarms_APPIA */ -#define bits_AQ_GlobalAlarms_APPIA_upIramParityError u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure upIramParityError in AQ_GlobalAlarms_APPIA */ -#define word_AQ_GlobalAlarms_APPIA_upIramParityError u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure txEnableStateChange in AQ_GlobalAlarms_APPIA */ -#define AQ_GlobalAlarms_APPIA_txEnableStateChange 2 -/*! \brief Preprocessor variable to relate field to bit position in structure txEnableStateChange in AQ_GlobalAlarms_APPIA */ -#define bits_AQ_GlobalAlarms_APPIA_txEnableStateChange u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure txEnableStateChange in AQ_GlobalAlarms_APPIA */ -#define word_AQ_GlobalAlarms_APPIA_txEnableStateChange u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure mdioMMD_Error in AQ_GlobalAlarms_APPIA */ -#define AQ_GlobalAlarms_APPIA_mdioMMD_Error 2 -/*! \brief Preprocessor variable to relate field to bit position in structure mdioMMD_Error in AQ_GlobalAlarms_APPIA */ -#define bits_AQ_GlobalAlarms_APPIA_mdioMMD_Error u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure mdioMMD_Error in AQ_GlobalAlarms_APPIA */ -#define word_AQ_GlobalAlarms_APPIA_mdioMMD_Error u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure mdioTimeoutError in AQ_GlobalAlarms_APPIA */ -#define AQ_GlobalAlarms_APPIA_mdioTimeoutError 2 -/*! \brief Preprocessor variable to relate field to bit position in structure mdioTimeoutError in AQ_GlobalAlarms_APPIA */ -#define bits_AQ_GlobalAlarms_APPIA_mdioTimeoutError u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure mdioTimeoutError in AQ_GlobalAlarms_APPIA */ -#define word_AQ_GlobalAlarms_APPIA_mdioTimeoutError u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure watchdogTimerAlarm in AQ_GlobalAlarms_APPIA */ -#define AQ_GlobalAlarms_APPIA_watchdogTimerAlarm 2 -/*! \brief Preprocessor variable to relate field to bit position in structure watchdogTimerAlarm in AQ_GlobalAlarms_APPIA */ -#define bits_AQ_GlobalAlarms_APPIA_watchdogTimerAlarm u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure watchdogTimerAlarm in AQ_GlobalAlarms_APPIA */ -#define word_AQ_GlobalAlarms_APPIA_watchdogTimerAlarm u2.word_2 - -/*! \brief Base register address of structure AQ_GlobalInterruptMask_APPIA */ -#define AQ_GlobalInterruptMask_APPIA_baseRegisterAddress 0xD400 -/*! \brief MMD address of structure AQ_GlobalInterruptMask_APPIA */ -#define AQ_GlobalInterruptMask_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureFailureMask in AQ_GlobalInterruptMask_APPIA */ -#define AQ_GlobalInterruptMask_APPIA_highTemperatureFailureMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureFailureMask in AQ_GlobalInterruptMask_APPIA */ -#define bits_AQ_GlobalInterruptMask_APPIA_highTemperatureFailureMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureFailureMask in AQ_GlobalInterruptMask_APPIA */ -#define word_AQ_GlobalInterruptMask_APPIA_highTemperatureFailureMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureFailureMask in AQ_GlobalInterruptMask_APPIA */ -#define AQ_GlobalInterruptMask_APPIA_lowTemperatureFailureMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureFailureMask in AQ_GlobalInterruptMask_APPIA */ -#define bits_AQ_GlobalInterruptMask_APPIA_lowTemperatureFailureMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureFailureMask in AQ_GlobalInterruptMask_APPIA */ -#define word_AQ_GlobalInterruptMask_APPIA_lowTemperatureFailureMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureWarningMask in AQ_GlobalInterruptMask_APPIA */ -#define AQ_GlobalInterruptMask_APPIA_highTemperatureWarningMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureWarningMask in AQ_GlobalInterruptMask_APPIA */ -#define bits_AQ_GlobalInterruptMask_APPIA_highTemperatureWarningMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureWarningMask in AQ_GlobalInterruptMask_APPIA */ -#define word_AQ_GlobalInterruptMask_APPIA_highTemperatureWarningMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureWarningMask in AQ_GlobalInterruptMask_APPIA */ -#define AQ_GlobalInterruptMask_APPIA_lowTemperatureWarningMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureWarningMask in AQ_GlobalInterruptMask_APPIA */ -#define bits_AQ_GlobalInterruptMask_APPIA_lowTemperatureWarningMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureWarningMask in AQ_GlobalInterruptMask_APPIA */ -#define word_AQ_GlobalInterruptMask_APPIA_lowTemperatureWarningMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure resetCompletedMask in AQ_GlobalInterruptMask_APPIA */ -#define AQ_GlobalInterruptMask_APPIA_resetCompletedMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure resetCompletedMask in AQ_GlobalInterruptMask_APPIA */ -#define bits_AQ_GlobalInterruptMask_APPIA_resetCompletedMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure resetCompletedMask in AQ_GlobalInterruptMask_APPIA */ -#define word_AQ_GlobalInterruptMask_APPIA_resetCompletedMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure deviceFaultMask in AQ_GlobalInterruptMask_APPIA */ -#define AQ_GlobalInterruptMask_APPIA_deviceFaultMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure deviceFaultMask in AQ_GlobalInterruptMask_APPIA */ -#define bits_AQ_GlobalInterruptMask_APPIA_deviceFaultMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure deviceFaultMask in AQ_GlobalInterruptMask_APPIA */ -#define word_AQ_GlobalInterruptMask_APPIA_deviceFaultMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmAMask in AQ_GlobalInterruptMask_APPIA */ -#define AQ_GlobalInterruptMask_APPIA_reservedAlarmAMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmAMask in AQ_GlobalInterruptMask_APPIA */ -#define bits_AQ_GlobalInterruptMask_APPIA_reservedAlarmAMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmAMask in AQ_GlobalInterruptMask_APPIA */ -#define word_AQ_GlobalInterruptMask_APPIA_reservedAlarmAMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmBMask in AQ_GlobalInterruptMask_APPIA */ -#define AQ_GlobalInterruptMask_APPIA_reservedAlarmBMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmBMask in AQ_GlobalInterruptMask_APPIA */ -#define bits_AQ_GlobalInterruptMask_APPIA_reservedAlarmBMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmBMask in AQ_GlobalInterruptMask_APPIA */ -#define word_AQ_GlobalInterruptMask_APPIA_reservedAlarmBMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmCMask in AQ_GlobalInterruptMask_APPIA */ -#define AQ_GlobalInterruptMask_APPIA_reservedAlarmCMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmCMask in AQ_GlobalInterruptMask_APPIA */ -#define bits_AQ_GlobalInterruptMask_APPIA_reservedAlarmCMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmCMask in AQ_GlobalInterruptMask_APPIA */ -#define word_AQ_GlobalInterruptMask_APPIA_reservedAlarmCMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmDMask in AQ_GlobalInterruptMask_APPIA */ -#define AQ_GlobalInterruptMask_APPIA_reservedAlarmDMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmDMask in AQ_GlobalInterruptMask_APPIA */ -#define bits_AQ_GlobalInterruptMask_APPIA_reservedAlarmDMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmDMask in AQ_GlobalInterruptMask_APPIA */ -#define word_AQ_GlobalInterruptMask_APPIA_reservedAlarmDMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure smartPower_downEnteredMask in AQ_GlobalInterruptMask_APPIA */ -#define AQ_GlobalInterruptMask_APPIA_smartPower_downEnteredMask 1 -/*! \brief Preprocessor variable to relate field to bit position in structure smartPower_downEnteredMask in AQ_GlobalInterruptMask_APPIA */ -#define bits_AQ_GlobalInterruptMask_APPIA_smartPower_downEnteredMask u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure smartPower_downEnteredMask in AQ_GlobalInterruptMask_APPIA */ -#define word_AQ_GlobalInterruptMask_APPIA_smartPower_downEnteredMask u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure xenpakAlarmMask in AQ_GlobalInterruptMask_APPIA */ -#define AQ_GlobalInterruptMask_APPIA_xenpakAlarmMask 1 -/*! \brief Preprocessor variable to relate field to bit position in structure xenpakAlarmMask in AQ_GlobalInterruptMask_APPIA */ -#define bits_AQ_GlobalInterruptMask_APPIA_xenpakAlarmMask u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure xenpakAlarmMask in AQ_GlobalInterruptMask_APPIA */ -#define word_AQ_GlobalInterruptMask_APPIA_xenpakAlarmMask u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmsMask in AQ_GlobalInterruptMask_APPIA */ -#define AQ_GlobalInterruptMask_APPIA_reservedAlarmsMask 1 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmsMask in AQ_GlobalInterruptMask_APPIA */ -#define bits_AQ_GlobalInterruptMask_APPIA_reservedAlarmsMask u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmsMask in AQ_GlobalInterruptMask_APPIA */ -#define word_AQ_GlobalInterruptMask_APPIA_reservedAlarmsMask u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure mdioCommandHandlingOverflowMask in AQ_GlobalInterruptMask_APPIA */ -#define AQ_GlobalInterruptMask_APPIA_mdioCommandHandlingOverflowMask 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mdioCommandHandlingOverflowMask in AQ_GlobalInterruptMask_APPIA */ -#define bits_AQ_GlobalInterruptMask_APPIA_mdioCommandHandlingOverflowMask u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mdioCommandHandlingOverflowMask in AQ_GlobalInterruptMask_APPIA */ -#define word_AQ_GlobalInterruptMask_APPIA_mdioCommandHandlingOverflowMask u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure diagnosticAlarmMask in AQ_GlobalInterruptMask_APPIA */ -#define AQ_GlobalInterruptMask_APPIA_diagnosticAlarmMask 1 -/*! \brief Preprocessor variable to relate field to bit position in structure diagnosticAlarmMask in AQ_GlobalInterruptMask_APPIA */ -#define bits_AQ_GlobalInterruptMask_APPIA_diagnosticAlarmMask u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure diagnosticAlarmMask in AQ_GlobalInterruptMask_APPIA */ -#define word_AQ_GlobalInterruptMask_APPIA_diagnosticAlarmMask u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure nvrOperationCompleteMask in AQ_GlobalInterruptMask_APPIA */ -#define AQ_GlobalInterruptMask_APPIA_nvrOperationCompleteMask 2 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrOperationCompleteMask in AQ_GlobalInterruptMask_APPIA */ -#define bits_AQ_GlobalInterruptMask_APPIA_nvrOperationCompleteMask u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure nvrOperationCompleteMask in AQ_GlobalInterruptMask_APPIA */ -#define word_AQ_GlobalInterruptMask_APPIA_nvrOperationCompleteMask u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure mailboxOperationCompleteMask in AQ_GlobalInterruptMask_APPIA */ -#define AQ_GlobalInterruptMask_APPIA_mailboxOperationCompleteMask 2 -/*! \brief Preprocessor variable to relate field to bit position in structure mailboxOperationCompleteMask in AQ_GlobalInterruptMask_APPIA */ -#define bits_AQ_GlobalInterruptMask_APPIA_mailboxOperationCompleteMask u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure mailboxOperationCompleteMask in AQ_GlobalInterruptMask_APPIA */ -#define word_AQ_GlobalInterruptMask_APPIA_mailboxOperationCompleteMask u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure upDramParityErrorMask in AQ_GlobalInterruptMask_APPIA */ -#define AQ_GlobalInterruptMask_APPIA_upDramParityErrorMask 2 -/*! \brief Preprocessor variable to relate field to bit position in structure upDramParityErrorMask in AQ_GlobalInterruptMask_APPIA */ -#define bits_AQ_GlobalInterruptMask_APPIA_upDramParityErrorMask u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure upDramParityErrorMask in AQ_GlobalInterruptMask_APPIA */ -#define word_AQ_GlobalInterruptMask_APPIA_upDramParityErrorMask u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure upIramParityErrorMask in AQ_GlobalInterruptMask_APPIA */ -#define AQ_GlobalInterruptMask_APPIA_upIramParityErrorMask 2 -/*! \brief Preprocessor variable to relate field to bit position in structure upIramParityErrorMask in AQ_GlobalInterruptMask_APPIA */ -#define bits_AQ_GlobalInterruptMask_APPIA_upIramParityErrorMask u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure upIramParityErrorMask in AQ_GlobalInterruptMask_APPIA */ -#define word_AQ_GlobalInterruptMask_APPIA_upIramParityErrorMask u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure txEnableStateChangeMask in AQ_GlobalInterruptMask_APPIA */ -#define AQ_GlobalInterruptMask_APPIA_txEnableStateChangeMask 2 -/*! \brief Preprocessor variable to relate field to bit position in structure txEnableStateChangeMask in AQ_GlobalInterruptMask_APPIA */ -#define bits_AQ_GlobalInterruptMask_APPIA_txEnableStateChangeMask u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure txEnableStateChangeMask in AQ_GlobalInterruptMask_APPIA */ -#define word_AQ_GlobalInterruptMask_APPIA_txEnableStateChangeMask u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure mdioMMD_ErrorMask in AQ_GlobalInterruptMask_APPIA */ -#define AQ_GlobalInterruptMask_APPIA_mdioMMD_ErrorMask 2 -/*! \brief Preprocessor variable to relate field to bit position in structure mdioMMD_ErrorMask in AQ_GlobalInterruptMask_APPIA */ -#define bits_AQ_GlobalInterruptMask_APPIA_mdioMMD_ErrorMask u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure mdioMMD_ErrorMask in AQ_GlobalInterruptMask_APPIA */ -#define word_AQ_GlobalInterruptMask_APPIA_mdioMMD_ErrorMask u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure mdioTimeoutErrorMask in AQ_GlobalInterruptMask_APPIA */ -#define AQ_GlobalInterruptMask_APPIA_mdioTimeoutErrorMask 2 -/*! \brief Preprocessor variable to relate field to bit position in structure mdioTimeoutErrorMask in AQ_GlobalInterruptMask_APPIA */ -#define bits_AQ_GlobalInterruptMask_APPIA_mdioTimeoutErrorMask u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure mdioTimeoutErrorMask in AQ_GlobalInterruptMask_APPIA */ -#define word_AQ_GlobalInterruptMask_APPIA_mdioTimeoutErrorMask u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure watchdogTimerAlarmMask in AQ_GlobalInterruptMask_APPIA */ -#define AQ_GlobalInterruptMask_APPIA_watchdogTimerAlarmMask 2 -/*! \brief Preprocessor variable to relate field to bit position in structure watchdogTimerAlarmMask in AQ_GlobalInterruptMask_APPIA */ -#define bits_AQ_GlobalInterruptMask_APPIA_watchdogTimerAlarmMask u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure watchdogTimerAlarmMask in AQ_GlobalInterruptMask_APPIA */ -#define word_AQ_GlobalInterruptMask_APPIA_watchdogTimerAlarmMask u2.word_2 - -/*! \brief Base register address of structure AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_baseRegisterAddress 0xFC00 -/*! \brief MMD address of structure AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure pmaStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pmaStandardAlarm_1Interrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pmaStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pmaStandardAlarm_1Interrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pmaStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pmaStandardAlarm_1Interrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pmaStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pmaStandardAlarm_2Interrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pmaStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pmaStandardAlarm_2Interrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pmaStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pmaStandardAlarm_2Interrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pcsStandardAlarm_1Interrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pcsStandardAlarm_1Interrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pcsStandardAlarm_1Interrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pcsStandardAlarm_2Interrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pcsStandardAlarm_2Interrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pcsStandardAlarm_2Interrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_3Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pcsStandardAlarm_3Interrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_3Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pcsStandardAlarm_3Interrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_3Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pcsStandardAlarm_3Interrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure phyXS_StandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_phyXS_StandardAlarms_1Interrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_StandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_phyXS_StandardAlarms_1Interrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure phyXS_StandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_phyXS_StandardAlarms_1Interrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure phyXS_StandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_phyXS_StandardAlarms_2Interrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_StandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_phyXS_StandardAlarms_2Interrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure phyXS_StandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_phyXS_StandardAlarms_2Interrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationStandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_autonegotiationStandardAlarms_1Interrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationStandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_autonegotiationStandardAlarms_1Interrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationStandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_autonegotiationStandardAlarms_1Interrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationStandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_autonegotiationStandardAlarms_2Interrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationStandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_autonegotiationStandardAlarms_2Interrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationStandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_autonegotiationStandardAlarms_2Interrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure gbeStandardAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_gbeStandardAlarmsInterrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure gbeStandardAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_gbeStandardAlarmsInterrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure gbeStandardAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_gbeStandardAlarmsInterrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure allVendorAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_allVendorAlarmsInterrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure allVendorAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_allVendorAlarmsInterrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure allVendorAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_allVendorAlarmsInterrupt u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ -#define AQ_GlobalChip_wideVendorInterruptFlags_APPIA_baseRegisterAddress 0xFC01 -/*! \brief MMD address of structure AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ -#define AQ_GlobalChip_wideVendorInterruptFlags_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure pmaVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ -#define AQ_GlobalChip_wideVendorInterruptFlags_APPIA_pmaVendorAlarmInterrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pmaVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ -#define bits_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_pmaVendorAlarmInterrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pmaVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ -#define word_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_pmaVendorAlarmInterrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pcsVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ -#define AQ_GlobalChip_wideVendorInterruptFlags_APPIA_pcsVendorAlarmInterrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pcsVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ -#define bits_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_pcsVendorAlarmInterrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pcsVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ -#define word_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_pcsVendorAlarmInterrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure phyXS_VendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ -#define AQ_GlobalChip_wideVendorInterruptFlags_APPIA_phyXS_VendorAlarmInterrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_VendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ -#define bits_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_phyXS_VendorAlarmInterrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure phyXS_VendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ -#define word_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_phyXS_VendorAlarmInterrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ -#define AQ_GlobalChip_wideVendorInterruptFlags_APPIA_autonegotiationVendorAlarmInterrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ -#define bits_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_autonegotiationVendorAlarmInterrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ -#define word_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_autonegotiationVendorAlarmInterrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure gbeVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ -#define AQ_GlobalChip_wideVendorInterruptFlags_APPIA_gbeVendorAlarmInterrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure gbeVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ -#define bits_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_gbeVendorAlarmInterrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure gbeVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ -#define word_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_gbeVendorAlarmInterrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_1Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ -#define AQ_GlobalChip_wideVendorInterruptFlags_APPIA_globalAlarms_1Interrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_1Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ -#define bits_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_globalAlarms_1Interrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_1Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ -#define word_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_globalAlarms_1Interrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_2Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ -#define AQ_GlobalChip_wideVendorInterruptFlags_APPIA_globalAlarms_2Interrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_2Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ -#define bits_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_globalAlarms_2Interrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_2Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ -#define word_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_globalAlarms_2Interrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_3Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ -#define AQ_GlobalChip_wideVendorInterruptFlags_APPIA_globalAlarms_3Interrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_3Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ -#define bits_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_globalAlarms_3Interrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_3Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ -#define word_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_globalAlarms_3Interrupt u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_baseRegisterAddress 0xFF00 -/*! \brief MMD address of structure AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure pmaStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_pmaStandardAlarm_1InterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pmaStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_pmaStandardAlarm_1InterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pmaStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_pmaStandardAlarm_1InterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pmaStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_pmaStandardAlarm_2InterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pmaStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_pmaStandardAlarm_2InterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pmaStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_pmaStandardAlarm_2InterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_pcsStandardAlarm_1InterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_pcsStandardAlarm_1InterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_pcsStandardAlarm_1InterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_pcsStandardAlarm_2InterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_pcsStandardAlarm_2InterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_pcsStandardAlarm_2InterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_3InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_pcsStandardAlarm_3InterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_3InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_pcsStandardAlarm_3InterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_3InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_pcsStandardAlarm_3InterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure phyXS_StandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_phyXS_StandardAlarms_1InterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_StandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_phyXS_StandardAlarms_1InterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure phyXS_StandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_phyXS_StandardAlarms_1InterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure phyXS_StandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_phyXS_StandardAlarms_2InterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_StandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_phyXS_StandardAlarms_2InterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure phyXS_StandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_phyXS_StandardAlarms_2InterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationStandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_autonegotiationStandardAlarms_1InterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationStandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_autonegotiationStandardAlarms_1InterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationStandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_autonegotiationStandardAlarms_1InterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationStandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_autonegotiationStandardAlarms_2InterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationStandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_autonegotiationStandardAlarms_2InterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationStandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_autonegotiationStandardAlarms_2InterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure gbeStandardAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_gbeStandardAlarmsInterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure gbeStandardAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_gbeStandardAlarmsInterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure gbeStandardAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_gbeStandardAlarmsInterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure allVendorAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_allVendorAlarmsInterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure allVendorAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_allVendorAlarmsInterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure allVendorAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_allVendorAlarmsInterruptMask u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalInterruptChip_wideVendorMask_APPIA */ -#define AQ_GlobalInterruptChip_wideVendorMask_APPIA_baseRegisterAddress 0xFF01 -/*! \brief MMD address of structure AQ_GlobalInterruptChip_wideVendorMask_APPIA */ -#define AQ_GlobalInterruptChip_wideVendorMask_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure pmaVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ -#define AQ_GlobalInterruptChip_wideVendorMask_APPIA_pmaVendorAlarmInterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pmaVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ -#define bits_AQ_GlobalInterruptChip_wideVendorMask_APPIA_pmaVendorAlarmInterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pmaVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ -#define word_AQ_GlobalInterruptChip_wideVendorMask_APPIA_pmaVendorAlarmInterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pcsVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ -#define AQ_GlobalInterruptChip_wideVendorMask_APPIA_pcsVendorAlarmInterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pcsVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ -#define bits_AQ_GlobalInterruptChip_wideVendorMask_APPIA_pcsVendorAlarmInterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pcsVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ -#define word_AQ_GlobalInterruptChip_wideVendorMask_APPIA_pcsVendorAlarmInterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure phyXS_VendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ -#define AQ_GlobalInterruptChip_wideVendorMask_APPIA_phyXS_VendorAlarmInterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_VendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ -#define bits_AQ_GlobalInterruptChip_wideVendorMask_APPIA_phyXS_VendorAlarmInterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure phyXS_VendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ -#define word_AQ_GlobalInterruptChip_wideVendorMask_APPIA_phyXS_VendorAlarmInterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ -#define AQ_GlobalInterruptChip_wideVendorMask_APPIA_autonegotiationVendorAlarmInterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ -#define bits_AQ_GlobalInterruptChip_wideVendorMask_APPIA_autonegotiationVendorAlarmInterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ -#define word_AQ_GlobalInterruptChip_wideVendorMask_APPIA_autonegotiationVendorAlarmInterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure gbeVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ -#define AQ_GlobalInterruptChip_wideVendorMask_APPIA_gbeVendorAlarmInterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure gbeVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ -#define bits_AQ_GlobalInterruptChip_wideVendorMask_APPIA_gbeVendorAlarmInterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure gbeVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ -#define word_AQ_GlobalInterruptChip_wideVendorMask_APPIA_gbeVendorAlarmInterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ -#define AQ_GlobalInterruptChip_wideVendorMask_APPIA_globalAlarms_1InterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ -#define bits_AQ_GlobalInterruptChip_wideVendorMask_APPIA_globalAlarms_1InterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ -#define word_AQ_GlobalInterruptChip_wideVendorMask_APPIA_globalAlarms_1InterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ -#define AQ_GlobalInterruptChip_wideVendorMask_APPIA_globalAlarms_2InterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ -#define bits_AQ_GlobalInterruptChip_wideVendorMask_APPIA_globalAlarms_2InterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ -#define word_AQ_GlobalInterruptChip_wideVendorMask_APPIA_globalAlarms_2InterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_3InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ -#define AQ_GlobalInterruptChip_wideVendorMask_APPIA_globalAlarms_3InterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_3InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ -#define bits_AQ_GlobalInterruptChip_wideVendorMask_APPIA_globalAlarms_3InterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_3InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ -#define word_AQ_GlobalInterruptChip_wideVendorMask_APPIA_globalAlarms_3InterruptMask u0.word_0 -#endif -/*@}*/ -/*@}*/ diff --git a/qca/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers_reversed.h b/qca/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers_reversed.h deleted file mode 100644 index 89e02c325..000000000 --- a/qca/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers_reversed.h +++ /dev/null @@ -1,5581 +0,0 @@ -/*! \file -* This file contains the data structures and doxygen comments -* for the Global Registers block. - */ - -/*! \addtogroup registerMap - @{ -*/ - -/*! \defgroup Global_registers Global Registers -* This module contains the data structures and doxygen comments -* for the Global Registers block. - */ -/*********************************************************************** -* Copyright (c) 2015, Aquantia -* -* Permission to use, copy, modify, and/or distribute this software for any -* purpose with or without fee is hereby granted, provided that the above -* copyright notice and this permission notice appear in all copies. -* -* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -* -* $Date: 2014/04/08 $ -* -* $Label: $ -* -* Description: -* -* This file contains the c header structures for the registers contained in the Global Registers block. -* -* The bit fields in this structure are from MSbit to LSbit -* -***********************************************************************/ - - -/*@{*/ -#ifndef AQ_APPIA_GLOBAL_REGS_HEADER -#define AQ_APPIA_GLOBAL_REGS_HEADER - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Standard Control 1: 1E.0000 */ -/* Global Standard Control 1: 1E.0000 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Standard Control 1 */ - union - { - struct - { - /*! \brief 1E.0000.F R/WSC Soft Reset - AQ_GlobalStandardControl_1_APPIA.u0.bits_0.softReset - - Default = 0x1 - - 1 = Global soft reset - 0 = Normal operation - - - Notes: - Setting this bit initiates a global soft reset on all of the digital logic, including the microprocessor. Upon completion of the reset sequence, this bit is set back to 0. */ - unsigned int softReset : 1; /* 1E.0000.F R/WSC Default = 0x1 */ - /* 1 = Global soft reset - 0 = Normal operation - */ - /*! \brief 1E.0000.E R/WSC Hard Reset - AQ_GlobalStandardControl_1_APPIA.u0.bits_0.hardReset - - Default = 0x0 - - 1 = Global hard reset - 0 = Normal operation - - - Notes: - Setting this bit initiates a global hard reset, equivalent to pulling the reset pin low. This is a level sensitive pin that connects into the power-on reset generation circuitry to initiate a complete power-on reset. */ - unsigned int hardReset : 1; /* 1E.0000.E R/WSC Default = 0x0 */ - /* 1 = Global hard reset - 0 = Normal operation - */ - unsigned int reserved0 : 2; - /*! \brief 1E.0000.B R/WPD Low Power - AQ_GlobalStandardControl_1_APPIA.u0.bits_0.lowPower - - Provisionable Default = 0x0 - - 1 = Low-power mode - 0 = Normal operation - - - Notes: - A one written to this register causes the chip to enter low-power mode. This bit puts the entire chip in low-power mode, with only the MDIO and microprocessor functioning, and turns off the analog front-end: i.e. places it in high-impedance mode. Setting this bit also sets all of the Low Power bits in the other MMDs. */ - unsigned int lowPower : 1; /* 1E.0000.B R/WPD Provisionable Default = 0x0 */ - /* 1 = Low-power mode - 0 = Normal operation - */ - unsigned int reserved1 : 11; - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalStandardControl_1_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Standard Device Identifier: 1E.0002 */ -/* Global Standard Device Identifier: 1E.0002 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Standard Device Identifier */ - union - { - struct - { - /*! \brief 1E.0002.F:0 RO Device ID MSW [1F:10] - AQ_GlobalStandardDeviceIdentifier_APPIA.u0.bits_0.deviceIdMSW - - - - Bits 31 - 16 of Device ID - */ - unsigned int deviceIdMSW : 16; /* 1E.0002.F:0 RO */ - /* Bits 31 - 16 of Device ID */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Standard Device Identifier */ - union - { - struct - { - /*! \brief 1E.0003.F:0 RO Device ID LSW [F:0] - AQ_GlobalStandardDeviceIdentifier_APPIA.u1.bits_1.deviceIdLSW - - - - Bits 15 - 0 of Device ID - */ - unsigned int deviceIdLSW : 16; /* 1E.0003.F:0 RO */ - /* Bits 15 - 0 of Device ID */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_GlobalStandardDeviceIdentifier_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Standard Devices in Package: 1E.0005 */ -/* Global Standard Devices in Package: 1E.0005 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Standard Devices in Package */ - union - { - struct - { - unsigned int reserved0 : 8; - /*! \brief 1E.0005.7 ROS Autonegotiation Present - AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.autonegotiationPresent - - Default = 0x1 - - 1 = Autonegotiation is present in package - 0 = Autonegotiation is not present in package - - Notes: - This is always set to 1, as there is Autonegotiation in the PHY. */ - unsigned int autonegotiationPresent : 1; /* 1E.0005.7 ROS Default = 0x1 */ - /* 1 = Autonegotiation is present in package - 0 = Autonegotiation is not present in package */ - /*! \brief 1E.0005.6 ROS TC Present - AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.tcPresent - - Default = 0x0 - - 1 = TC is present in package - 0 = TC is not present in package - - Notes: - This is always set to 0, as there is no TC functionality in the PHY. */ - unsigned int tcPresent : 1; /* 1E.0005.6 ROS Default = 0x0 */ - /* 1 = TC is present in package - 0 = TC is not present in package */ - /*! \brief 1E.0005.5 ROS DTE XS Present - AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.dteXsPresent - - Default = 0x0 - - 1 = DTE XS is present in package - 0 = DTE XS is not present in package - - - Notes: - This is always set to 0, as there is no DTE XAUI interface in the PHY. */ - unsigned int dteXsPresent : 1; /* 1E.0005.5 ROS Default = 0x0 */ - /* 1 = DTE XS is present in package - 0 = DTE XS is not present in package - */ - /*! \brief 1E.0005.4 ROS PHY XS Present - AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.phyXS_Present - - Default = 0x1 - - 1 = PHY XS is present in package - 0 = PHY XS is not present in package - - Notes: - This is always set to 1 as there is a PHY XS interface in the PHY. */ - unsigned int phyXS_Present : 1; /* 1E.0005.4 ROS Default = 0x1 */ - /* 1 = PHY XS is present in package - 0 = PHY XS is not present in package */ - /*! \brief 1E.0005.3 ROS PCS Present - AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.pcsPresent - - Default = 0x1 - - 1 = PCS is present in package - 0 = PCS is not present in package - - Notes: - This is always set to 1 as there is PCS functionality in the PHY. */ - unsigned int pcsPresent : 1; /* 1E.0005.3 ROS Default = 0x1 */ - /* 1 = PCS is present in package - 0 = PCS is not present in package */ - /*! \brief 1E.0005.2 ROS WIS Present - AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.wisPresent - - Default = 0x0 - - 1 = WIS is present in package - 0 = WIS is not present in package - - Notes: - This is always set to 0, as there is no WIS functionality in the PHY. */ - unsigned int wisPresent : 1; /* 1E.0005.2 ROS Default = 0x0 */ - /* 1 = WIS is present in package - 0 = WIS is not present in package */ - /*! \brief 1E.0005.1 ROS PMA Present - AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.pmaPresent - - Default = 0x1 - - 1 = PMA is present in package - 0 = PMA is not present - - Notes: - This is always set to 1 as there is PMA functionality in the PHY. */ - unsigned int pmaPresent : 1; /* 1E.0005.1 ROS Default = 0x1 */ - /* 1 = PMA is present in package - 0 = PMA is not present */ - /*! \brief 1E.0005.0 ROS Clause 22 Registers Present - AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.clause_22RegistersPresent - - Default = 0x0 - - 1 = Clause 22 registers are present in package - 0 = Clause 22 registers are not present in package - - Notes: - This is always set to 0 in the PHY, as there are no Clause 22 registers in the device. */ - unsigned int clause_22RegistersPresent : 1; /* 1E.0005.0 ROS Default = 0x0 */ - /* 1 = Clause 22 registers are present in package - 0 = Clause 22 registers are not present in package */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalStandardDevicesInPackage_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Standard Vendor Devices in Package: 1E.0006 */ -/* Global Standard Vendor Devices in Package: 1E.0006 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Standard Vendor Devices in Package */ - union - { - struct - { - /*! \brief 1E.0006.F ROS Vendor Specific Device #2 Present - AQ_GlobalStandardVendorDevicesInPackage_APPIA.u0.bits_0.vendorSpecificDevice_2Present - - Default = 0x1 - - 1 = Device #2 is present in package - 0 = Device #2 is not present in package - - Notes: - This is always set to 1 as the PHY utilizes this device for the DSP PMA registers. */ - unsigned int vendorSpecificDevice_2Present : 1; /* 1E.0006.F ROS Default = 0x1 */ - /* 1 = Device #2 is present in package - 0 = Device #2 is not present in package */ - /*! \brief 1E.0006.E ROS Vendor Specific Device #1 Present - AQ_GlobalStandardVendorDevicesInPackage_APPIA.u0.bits_0.vendorSpecificDevice_1Present - - Default = 0x1 - - 1 = Device #1 is present in package - 0 = Device #1 is not present in package - - Notes: - This is always set to 1 as the PHY utilizes this device for the global control registers. */ - unsigned int vendorSpecificDevice_1Present : 1; /* 1E.0006.E ROS Default = 0x1 */ - /* 1 = Device #1 is present in package - 0 = Device #1 is not present in package */ - /*! \brief 1E.0006.D ROS Clause 22 Extension Present - AQ_GlobalStandardVendorDevicesInPackage_APPIA.u0.bits_0.clause_22ExtensionPresent - - Default = 0x1 - - 1 = Clause 22 Extension is present in package - 0 = Clause 22 Extension is not present in package - - Notes: - This is always set to 1 as the PHY utilizes this device for the GbE registers. */ - unsigned int clause_22ExtensionPresent : 1; /* 1E.0006.D ROS Default = 0x1 */ - /* 1 = Clause 22 Extension is present in package - 0 = Clause 22 Extension is not present in package */ - unsigned int reserved0 : 13; - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalStandardVendorDevicesInPackage_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Standard Status 2: 1E.0008 */ -/* Global Standard Status 2: 1E.0008 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Standard Status 2 */ - union - { - struct - { - /*! \brief 1E.0008.F:E ROS Device Present [1:0] - AQ_GlobalStandardStatus_2_APPIA.u0.bits_0.devicePresent - - Default = 0x2 - - [F:E] - 0x3 = No device at this address - 0x2 = Device present at this address - 0x1 = No device at this address - 0x0 = No device at this address - - Notes: - This field is always set to 0x2, as the Global MMD resides here in the PHY. */ - unsigned int devicePresent : 2; /* 1E.0008.F:E ROS Default = 0x2 */ - /* [F:E] - 0x3 = No device at this address - 0x2 = Device present at this address - 0x1 = No device at this address - 0x0 = No device at this address */ - unsigned int reserved0 : 14; - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalStandardStatus_2_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Standard Package Identifier: 1E.000E */ -/* Global Standard Package Identifier: 1E.000E */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Standard Package Identifier */ - union - { - struct - { - /*! \brief 1E.000E.F:0 RO Package ID MSW [1F:10] - AQ_GlobalStandardPackageIdentifier_APPIA.u0.bits_0.packageIdMSW - - - - Bits 31- 16 of Package ID - */ - unsigned int packageIdMSW : 16; /* 1E.000E.F:0 RO */ - /* Bits 31- 16 of Package ID */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Standard Package Identifier */ - union - { - struct - { - /*! \brief 1E.000F.F:0 RO Package ID LSW [F:0] - AQ_GlobalStandardPackageIdentifier_APPIA.u1.bits_1.packageIdLSW - - - - Bits 15 - 0 of Package ID - */ - unsigned int packageIdLSW : 16; /* 1E.000F.F:0 RO */ - /* Bits 15 - 0 of Package ID */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_GlobalStandardPackageIdentifier_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Firmware ID: 1E.0020 */ -/* Global Firmware ID: 1E.0020 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Firmware ID */ - union - { - struct - { - /*! \brief 1E.0020.F:8 RO Firmware Major Revision Number [7:0] - AQ_GlobalFirmwareID_APPIA.u0.bits_0.firmwareMajorRevisionNumber - - - - [F:8] = Major revision number - - Notes: - - - The lower six bits of major and minor firmware revision are exchanged in autonegotiation when the PHYID message is sent. */ - unsigned int firmwareMajorRevisionNumber : 8; /* 1E.0020.F:8 RO */ - /* [F:8] = Major revision number */ - /*! \brief 1E.0020.7:0 RO Firmware Minor Revision Number [7:0] - AQ_GlobalFirmwareID_APPIA.u0.bits_0.firmwareMinorRevisionNumber - - - - [7:0] = Minor revision number - - Notes: - - - The lower six bits of major and minor firmware revision are exchanged in autonegotiation when the PHYID message is sent. */ - unsigned int firmwareMinorRevisionNumber : 8; /* 1E.0020.7:0 RO */ - /* [7:0] = Minor revision number */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalFirmwareID_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Chip Identification: 1E.0021 */ -/* Global Chip Identification: 1E.0021 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Chip Identification */ - union - { - struct - { - /*! \brief 1E.0021.F:0 RO Chip Identification [F:0] - AQ_GlobalChipIdentification_APPIA.u0.bits_0.chipIdentification - - - - Hardware Chip ID - - Notes: - This value is a hard-coded chip ID */ - unsigned int chipIdentification : 16; /* 1E.0021.F:0 RO */ - /* Hardware Chip ID */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalChipIdentification_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Chip Revision: 1E.0022 */ -/* Global Chip Revision: 1E.0022 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Chip Revision */ - union - { - struct - { - /*! \brief 1E.0022.F:0 RO Chip Revision [F:0] - AQ_GlobalChipRevision_APPIA.u0.bits_0.chipRevision - - - - Hardware Chip Revision - - Notes: - This value is a hard-coded chip revision */ - unsigned int chipRevision : 16; /* 1E.0022.F:0 RO */ - /* Hardware Chip Revision */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalChipRevision_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global NVR Interface: 1E.0100 */ -/* Global NVR Interface: 1E.0100 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global NVR Interface */ - union - { - struct - { - /*! \brief 1E.0100.F R/WSC NVR Execute Operation - AQ_GlobalNvrInterface_APPIA.u0.bits_0.nvrExecuteOperation - - Default = 0x0 - - 1 = Start NVR Operation - - - Notes: - When set to 1, the NVR operation will begin. Ensure that the uP is stalled using the See MCP Run Stall bit to ensure no NVR contention. */ - unsigned int nvrExecuteOperation : 1; /* 1E.0100.F R/WSC Default = 0x0 */ - /* 1 = Start NVR Operation - */ - /*! \brief 1E.0100.E R/W NVR Write Mode - AQ_GlobalNvrInterface_APPIA.u0.bits_0.nvrWriteMode - - Default = 0x0 - - 1 = Write to NVR - 0 = Read from NVR - - */ - unsigned int nvrWriteMode : 1; /* 1E.0100.E R/W Default = 0x0 */ - /* 1 = Write to NVR - 0 = Read from NVR - */ - /*! \brief 1E.0100.D R/W Freeze NVR CRC - AQ_GlobalNvrInterface_APPIA.u0.bits_0.freezeNvrCrc - - Default = 0x0 - - 1 = Freeze NVR Mailbox CRC calculation register - - - Notes: - To prevent an erroneous answer, this bit should not be set at the same time the See NVR Operation Valid bit is set. */ - unsigned int freezeNvrCrc : 1; /* 1E.0100.D R/W Default = 0x0 */ - /* 1 = Freeze NVR Mailbox CRC calculation register - */ - /*! \brief 1E.0100.C R/WSC Reset NVR CRC - AQ_GlobalNvrInterface_APPIA.u0.bits_0.resetNvrCrc - - Default = 0x0 - - 1 = Reset NVR Mailbox CRC calculation register - - - Notes: - To prevent an erroneous answer, this bit should not be set at the same time the See NVR Operation Valid bit is set. */ - unsigned int resetNvrCrc : 1; /* 1E.0100.C R/WSC Default = 0x0 */ - /* 1 = Reset NVR Mailbox CRC calculation register - */ - unsigned int reserved0 : 1; - /*! \brief 1E.0100.A R/W NVR Burst - AQ_GlobalNvrInterface_APPIA.u0.bits_0.nvrBurst - - Default = 0x0 - - 0 = Single read or write operation of up to 4 bytes - 1 = Burst operation - - - Notes: - When this bit is set, the operation is a burst operation where more than 32-bits is read from the NVR or written to the NVR. This bit should be set to one until the last burst in the read or write operation, when it should be set to zero. It operates by gating the SPI clock, and not restarting it until new data is ready to be written, or the previous contents have been read. Each burst of data requires the NVR Execute Operation bit to be set to initiate the next phase. */ - unsigned int nvrBurst : 1; /* 1E.0100.A R/W Default = 0x0 */ - /* 0 = Single read or write operation of up to 4 bytes - 1 = Burst operation - */ - unsigned int reserved1 : 1; - /*! \brief 1E.0100.8 RO NVR Busy - AQ_GlobalNvrInterface_APPIA.u0.bits_0.nvrBusy - - - - 1 = NVR is busy - 0 = NVR is ready - - - Notes: - When set to 1, the NVR is busy. A new NVR operation should not occur until this bit is 0. If the NVR clock is greater than 64/63 of the MDIO clock, this bit never needs to be polled when operating over the MDIO. */ - unsigned int nvrBusy : 1; /* 1E.0100.8 RO */ - /* 1 = NVR is busy - 0 = NVR is ready - */ - /*! \brief 1E.0100.7:0 R/W NVR Opcode [7:0] - AQ_GlobalNvrInterface_APPIA.u0.bits_0.nvrOpcode - - Default = 0x03 - - NVR instruction opcode - - */ - unsigned int nvrOpcode : 8; /* 1E.0100.7:0 R/W Default = 0x03 */ - /* NVR instruction opcode - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global NVR Interface */ - union - { - struct - { - /*! \brief 1E.0101.F:0 RO NVR Mailbox CRC [F:0] - AQ_GlobalNvrInterface_APPIA.u1.bits_1.nvrMailboxCrc - - - - The running CRC-16 of everything passing through the NVR interface - - - Notes: - The CRC-16 over all data written or read through the NVR interface. The CRC-16 is calculated by dividing the data by: - x^16 + x^12 + x^5 + 1 */ - unsigned int nvrMailboxCrc : 16; /* 1E.0101.F:0 RO */ - /* The running CRC-16 of everything passing through the NVR interface - */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global NVR Interface */ - union - { - struct - { - unsigned int reserved0 : 8; - /*! \brief 1E.0102.7:0 R/W NVR Address MSW [17:10] - AQ_GlobalNvrInterface_APPIA.u2.bits_2.nvrAddressMSW - - Default = 0x00 - - NVR address MSW bits [17:10] - - - Notes: - The address of where to read and write from in the NVR. This is self-incrementing and will automatically increment after each read or write operation. The increment amount is based on the data length (i.e. increments by 4 if the data length is 4 bytes) */ - unsigned int nvrAddressMSW : 8; /* 1E.0102.7:0 R/W Default = 0x00 */ - /* NVR address MSW bits [17:10] - */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global NVR Interface */ - union - { - struct - { - /*! \brief 1E.0103.F:0 R/W NVR Address LSW [F:0] - AQ_GlobalNvrInterface_APPIA.u3.bits_3.nvrAddressLSW - - Default = 0x0000 - - NVR address LSW bits [F:0] - - - Notes: - The address of where to read and write from in the NVR. This is self-incrementing and will automatically increment after each read or write operation. */ - unsigned int nvrAddressLSW : 16; /* 1E.0103.F:0 R/W Default = 0x0000 */ - /* NVR address LSW bits [F:0] - */ - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of Global NVR Interface */ - union - { - struct - { - /*! \brief 1E.0104.F:0 R/W NVR Data MSW [1F:10] - AQ_GlobalNvrInterface_APPIA.u4.bits_4.nvrDataMSW - - Default = 0x0000 - - NVR data MSW bits [1F:10] - - - Notes: - Data is stored and read-out from these registers in little-endian format for operations such as FLASH device ID, and for programming the processor. - - For instance the 64K Atmel device code reads out as two bytes 0x651F into the LSW register, whereas the datasheet indicates that 1F is the first byte read, followed by 65 as the second byte. - - To burst read and write these 4 bytes in the correct order (where DD is written to address x), they should be stored as: - - AA BB in the MSW - CC DD in the LSW. */ - unsigned int nvrDataMSW : 16; /* 1E.0104.F:0 R/W Default = 0x0000 */ - /* NVR data MSW bits [1F:10] - */ - } bits_4; - uint16_t word_4; - } u4; - /*! \brief Union for bit and word level access of word 5 of Global NVR Interface */ - union - { - struct - { - /*! \brief 1E.0105.F:0 R/W NVR Data LSW [F:0] - AQ_GlobalNvrInterface_APPIA.u5.bits_5.nvrDataLSW - - Default = 0x0000 - - NVR data LSW bits [F:0] - - - Notes: - Data is stored and read-out from these registers in little-endian format for operations such as FLASH device ID, and for programming the processor. - - For instance the 64K Atmel device code reads out as two bytes 0x651F into the LSW register, whereas the datasheet indicates that 1F is the first byte read, followed by 65 as the second byte. - To burst read and write these 4 bytes in the correct order (where DD is written to address x), they should be stored as: - - AA BB in the MSW - CC DD in the LSW. */ - unsigned int nvrDataLSW : 16; /* 1E.0105.F:0 R/W Default = 0x0000 */ - /* NVR data LSW bits [F:0] - */ - } bits_5; - uint16_t word_5; - } u5; -} AQ_GlobalNvrInterface_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Mailbox Interface: 1E.0200 */ -/* Global Mailbox Interface: 1E.0200 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Mailbox Interface */ - union - { - struct - { - /*! \brief 1E.0200.F R/WSC uP Mailbox Execute Operation - AQ_GlobalMailboxInterface_APPIA.u0.bits_0.upMailboxExecuteOperation - - Default = 0x0 - - 1 = Start of mailbox Operation - - - Notes: - Indicates mailbox is loaded and ready */ - unsigned int upMailboxExecuteOperation : 1; /* 1E.0200.F R/WSC Default = 0x0 */ - /* 1 = Start of mailbox Operation - */ - /*! \brief 1E.0200.E R/W uP Mailbox Write Mode - AQ_GlobalMailboxInterface_APPIA.u0.bits_0.upMailboxWriteMode - - Default = 0x0 - - 1 = Write - 0 = Read - - - Notes: - Mailbox direction */ - unsigned int upMailboxWriteMode : 1; /* 1E.0200.E R/W Default = 0x0 */ - /* 1 = Write - 0 = Read - */ - unsigned int reserved0 : 1; - /*! \brief 1E.0200.C R/WSC Reset uP Mailbox CRC - AQ_GlobalMailboxInterface_APPIA.u0.bits_0.resetUpMailboxCrc - - Default = 0x0 - - 1 = Reset uP mailbox CRC calculation register - - */ - unsigned int resetUpMailboxCrc : 1; /* 1E.0200.C R/WSC Default = 0x0 */ - /* 1 = Reset uP mailbox CRC calculation register - */ - unsigned int reserved1 : 3; - /*! \brief 1E.0200.8 RO uP Mailbox Busy - AQ_GlobalMailboxInterface_APPIA.u0.bits_0.upMailboxBusy - - - - 1 = uP mailbox busy - 0 = uP mailbox ready - - - Notes: - In general the uP will respond within a few processor cycles to any PIF slave request, much faster than the MDIO. If the busy is asserted over multiple MDIO polling cycles, then a H/W error may have occured and a Global S/W reset or uP reset is required. */ - unsigned int upMailboxBusy : 1; /* 1E.0200.8 RO */ - /* 1 = uP mailbox busy - 0 = uP mailbox ready - */ - unsigned int reserved2 : 8; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Mailbox Interface */ - union - { - struct - { - /*! \brief 1E.0201.F:0 RO uP Mailbox CRC [F:0] - AQ_GlobalMailboxInterface_APPIA.u1.bits_1.upMailboxCrc - - - - The running CRC-16 of everything passing through the mailbox interface - - */ - unsigned int upMailboxCrc : 16; /* 1E.0201.F:0 RO */ - /* The running CRC-16 of everything passing through the mailbox interface - */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global Mailbox Interface */ - union - { - struct - { - /*! \brief 1E.0202.F:0 R/W uP Mailbox Address MSW [1F:10] - AQ_GlobalMailboxInterface_APPIA.u2.bits_2.upMailboxAddressMSW - - Default = 0x0000 - - uP Mailbox MSW address - - - Notes: - The address of where to read and write from in the Microcontroller Mailbox. This is self-incrementing and automatically increments after each read and write operation.PHY */ - unsigned int upMailboxAddressMSW : 16; /* 1E.0202.F:0 R/W Default = 0x0000 */ - /* uP Mailbox MSW address - */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global Mailbox Interface */ - union - { - struct - { - /*! \brief 1E.0203.F:2 R/W uP Mailbox Address LSW [F:2] - AQ_GlobalMailboxInterface_APPIA.u3.bits_3.upMailboxAddressLSW - - Default = 0x0000 - - uP LSW Mailbox address [F:2] - - - Notes: - The address of where to read and write from in the Microcontroller Mailbox. This is self-incrementing and automatically increments after each read and write operation.PHY */ - unsigned int upMailboxAddressLSW : 14; /* 1E.0203.F:2 R/W Default = 0x0000 */ - /* uP LSW Mailbox address [F:2] - */ - /*! \brief 1E.0203.1:0 RO uP Mailbox Address LSW Don't Care [1:0] - AQ_GlobalMailboxInterface_APPIA.u3.bits_3.upMailboxAddressLSW_Don_tCare - - - - Least significant uP LSW Mailbox address bits [1:0] - - - Notes: - These bits are always set to 0 since each memory access is on a 4-byte boundary. */ - unsigned int upMailboxAddressLSW_Don_tCare : 2; /* 1E.0203.1:0 RO */ - /* Least significant uP LSW Mailbox address bits [1:0] - */ - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of Global Mailbox Interface */ - union - { - struct - { - /*! \brief 1E.0204.F:0 R/W uP Mailbox Data MSW [1F:10] - AQ_GlobalMailboxInterface_APPIA.u4.bits_4.upMailboxDataMSW - - Default = 0x0000 - - uP Mailbox data MSW - - */ - unsigned int upMailboxDataMSW : 16; /* 1E.0204.F:0 R/W Default = 0x0000 */ - /* uP Mailbox data MSW - */ - } bits_4; - uint16_t word_4; - } u4; - /*! \brief Union for bit and word level access of word 5 of Global Mailbox Interface */ - union - { - struct - { - /*! \brief 1E.0205.F:0 R/W uP Mailbox Data LSW [F:0] - AQ_GlobalMailboxInterface_APPIA.u5.bits_5.upMailboxDataLSW - - Default = 0x0000 - - uP Mailbox data LSW - - */ - unsigned int upMailboxDataLSW : 16; /* 1E.0205.F:0 R/W Default = 0x0000 */ - /* uP Mailbox data LSW - */ - } bits_5; - uint16_t word_5; - } u5; -} AQ_GlobalMailboxInterface_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Microprocessor Scratch Pad: 1E.0300 */ -/* Global Microprocessor Scratch Pad: 1E.0300 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Microprocessor Scratch Pad */ - union - { - struct - { - /*! \brief 1E.0300.F:0 R/W Scratch Pad 1[F:0] - AQ_GlobalMicroprocessorScratchPad_APPIA.u0.bits_0.scratchPad_1 - - Default = 0x0000 - - General Purpose Scratch Pad1 - */ - unsigned int scratchPad_1 : 16; /* 1E.0300.F:0 R/W Default = 0x0000 */ - /* General Purpose Scratch Pad1 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Microprocessor Scratch Pad */ - union - { - struct - { - /*! \brief 1E.0301.F:0 R/W Scratch Pad 2 [F:0] - AQ_GlobalMicroprocessorScratchPad_APPIA.u1.bits_1.scratchPad_2 - - Default = 0x0000 - - General Purpose Scratch P - */ - unsigned int scratchPad_2 : 16; /* 1E.0301.F:0 R/W Default = 0x0000 */ - /* General Purpose Scratch P */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_GlobalMicroprocessorScratchPad_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Control: 1E.C000 */ -/* Global Control: 1E.C000 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Control */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Control */ - union - { - struct - { - /*! \brief 1E.C001.F R/W uP Reset - AQ_GlobalControl_APPIA.u1.bits_1.upReset - - Default = 0x0 - - 1 = Reset - - - Notes: - Resets the uP and the PIF master and slave bus. Will be active for a minimum of 100 microseconds. */ - unsigned int upReset : 1; /* 1E.C001.F R/W Default = 0x0 */ - /* 1 = Reset - */ - unsigned int reserved0 : 8; - /*! \brief 1E.C001.6 R/W uP Run Stall Override - AQ_GlobalControl_APPIA.u1.bits_1.upRunStallOverride - - Default = 0x0 - - 0 = uP Run Stall from "MDIO Boot Load" pin. - 1 = uP Run Stall from See MCP Run Stall bit - - - Notes: - This bit selects the uP Run Stall from either the "MDIO Boot Load" pin or the See MCP Run Stall bit. */ - unsigned int upRunStallOverride : 1; /* 1E.C001.6 R/W Default = 0x0 */ - /* 0 = uP Run Stall from "MDIO Boot Load" pin. - 1 = uP Run Stall from See MCP Run Stall bit - */ - unsigned int reserved1 : 5; - /*! \brief 1E.C001.0 R/W uP Run Stall - AQ_GlobalControl_APPIA.u1.bits_1.upRunStall - - Default = 0x0 - - 1 = uP Run Stall - 0 = uP normal mode - - - Notes: - Deactivates the uP. The PIF slave bus for inbound requests will still be active. This bit is muliplexed with the "MDIO Boot Load" pin with the See uP Run Stall Override bit as the select. When the "MDIO Boot Load" pin is asserted, the uP will be in Run Stall mode after reset. */ - unsigned int upRunStall : 1; /* 1E.C001.0 R/W Default = 0x0 */ - /* 1 = uP Run Stall - 0 = uP normal mode - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_GlobalControl_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Reset Control: 1E.C006 */ -/* Global Reset Control: 1E.C006 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Reset Control */ - union - { - struct - { - unsigned int reserved0 : 1; - /*! \brief 1E.C006.E R/WPD Global MMD Reset Disable - AQ_GlobalResetControl_APPIA.u0.bits_0.globalMMD_ResetDisable - - Provisionable Default = 0x0 - - 1 = Disable the S/W reset to the Global MMD registers - 0 = Enable the S/W reset to the Global MMD registers - - - Notes: - Setting this bit prevents a Global S/W reset or Global S/W reset from resetting the Global MMD registers */ - unsigned int globalMMD_ResetDisable : 1; /* 1E.C006.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Disable the S/W reset to the Global MMD registers - 0 = Enable the S/W reset to the Global MMD registers - */ - unsigned int reserved1 : 14; - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalResetControl_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Diagnostic Provisioning: 1E.C400 */ -/* Global Diagnostic Provisioning: 1E.C400 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Diagnostic Provisioning */ - union - { - struct - { - /*! \brief 1E.C400.F R/WPD Enable Diagnostics - AQ_GlobalDiagnosticProvisioning_APPIA.u0.bits_0.enableDiagnostics - - Provisionable Default = 0x1 - - 1 = Chip performs diagnostics on power-up - */ - unsigned int enableDiagnostics : 1; /* 1E.C400.F R/WPD Provisionable Default = 0x1 */ - /* 1 = Chip performs diagnostics on power-up */ - unsigned int reserved0 : 15; - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalDiagnosticProvisioning_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Thermal Provisioning: 1E.C420 */ -/* Global Thermal Provisioning: 1E.C420 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Thermal Provisioning */ - union - { - struct - { - /*! \brief 1E.C420.F:0 R/WPD Reserved 0 [F:0] - AQ_GlobalThermalProvisioning_APPIA.u0.bits_0.reserved_0 - - Provisionable Default = 0x0000 - - Internal reserved - do not modify - - */ - unsigned int reserved_0 : 16; /* 1E.C420.F:0 R/WPD Provisionable Default = 0x0000 */ - /* Internal reserved - do not modify - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Thermal Provisioning */ - union - { - struct - { - /*! \brief 1E.C421.F:0 R/WPD High Temp Failure Threshold [F:0] - AQ_GlobalThermalProvisioning_APPIA.u1.bits_1.highTempFailureThreshold - - Provisionable Default = 0x4600 - - [F:0] of high temperature failure threshold - - Notes: - 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 70 degreesC. - - In XENPAK mode, F/W will use the XENPAK register 1.A000 - 1.A001: instead of this register. - - NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. - High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ - unsigned int highTempFailureThreshold : 16; /* 1E.C421.F:0 R/WPD Provisionable Default = 0x4600 */ - /* [F:0] of high temperature failure threshold */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global Thermal Provisioning */ - union - { - struct - { - /*! \brief 1E.C422.F:0 R/WPD Low Temp Failure Threshold [F:0] - AQ_GlobalThermalProvisioning_APPIA.u2.bits_2.lowTempFailureThreshold - - Provisionable Default = 0x0000 - - [F:0] of low temperature failure threshold - - Notes: - 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 0 degreesC. - - In XENPAK mode, F/W will use the XENPAK register 1.A002 - 1.A003: instead of this register. - - NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. - High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ - unsigned int lowTempFailureThreshold : 16; /* 1E.C422.F:0 R/WPD Provisionable Default = 0x0000 */ - /* [F:0] of low temperature failure threshold */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global Thermal Provisioning */ - union - { - struct - { - /*! \brief 1E.C423.F:0 R/WPD High Temp Warning Threshold [F:0] - AQ_GlobalThermalProvisioning_APPIA.u3.bits_3.highTempWarningThreshold - - Provisionable Default = 0x3C00 - - [F:0] of high temperature warning threshold - - Notes: - 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD008. Default is 60 degreesC. - - In XENPAK mode, F/W will use the XENPAK register 1.A004 - 1.A005: instead of this register. - - NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. - High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ - unsigned int highTempWarningThreshold : 16; /* 1E.C423.F:0 R/WPD Provisionable Default = 0x3C00 */ - /* [F:0] of high temperature warning threshold */ - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of Global Thermal Provisioning */ - union - { - struct - { - /*! \brief 1E.C424.F:0 R/WPD Low Temp Warning Threshold [F:0] - AQ_GlobalThermalProvisioning_APPIA.u4.bits_4.lowTempWarningThreshold - - Provisionable Default = 0x0A00 - - [F:0] of low temperature warning threshold - - Notes: - 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 10 degreesC. - - In XENPAK mode, F/W will use the XENPAK register 1.A006 - 1.A007: instead of this register. - - NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. - High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ - unsigned int lowTempWarningThreshold : 16; /* 1E.C424.F:0 R/WPD Provisionable Default = 0x0A00 */ - /* [F:0] of low temperature warning threshold */ - } bits_4; - uint16_t word_4; - } u4; -} AQ_GlobalThermalProvisioning_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global LED Provisioning: 1E.C430 */ -/* Global LED Provisioning: 1E.C430 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global LED Provisioning */ - union - { - struct - { - unsigned int reserved0 : 7; - /*! \brief 1E.C430.8 R/WPD LED #0 Manual Set - AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0ManualSet - - Provisionable Default = 0x0 - - 1 = LED On - - */ - unsigned int led_0ManualSet : 1; /* 1E.C430.8 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED On - */ - /*! \brief 1E.C430.7 R/WPD LED #0 10 Gb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0_10Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 10 Gb/s - - */ - unsigned int led_0_10Gb_sLinkEstablished : 1; /* 1E.C430.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 10 Gb/s - */ - /*! \brief 1E.C430.6 R/WPD LED #0 1 Gb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0_1Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 1 Gb/s - - */ - unsigned int led_0_1Gb_sLinkEstablished : 1; /* 1E.C430.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 1 Gb/s - */ - /*! \brief 1E.C430.5 R/WPD LED #0 100 Mb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0_100Mb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 100 Mb/s - - */ - unsigned int led_0_100Mb_sLinkEstablished : 1; /* 1E.C430.5 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 100 Mb/s - */ - /*! \brief 1E.C430.4 R/WPD LED #0 Connecting - AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0Connecting - - Provisionable Default = 0x0 - - 1 = LED is on when attempting to connect. - - */ - unsigned int led_0Connecting : 1; /* 1E.C430.4 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when attempting to connect. - */ - /*! \brief 1E.C430.3 R/WPD LED #0 Receive Activity - AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0ReceiveActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on receive activity - - */ - unsigned int led_0ReceiveActivity : 1; /* 1E.C430.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on receive activity - */ - /*! \brief 1E.C430.2 R/WPD LED #0 Transmit Activity - AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0TransmitActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on transmit activity - - */ - unsigned int led_0TransmitActivity : 1; /* 1E.C430.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on transmit activity - */ - /*! \brief 1E.C430.1:0 R/WPD LED #0 Activity Stretch [1:0] - AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0ActivityStretch - - Provisionable Default = 0x3 - - [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - - */ - unsigned int led_0ActivityStretch : 2; /* 1E.C430.1:0 R/WPD Provisionable Default = 0x3 */ - /* [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global LED Provisioning */ - union - { - struct - { - unsigned int reserved0 : 7; - /*! \brief 1E.C431.8 R/WPD LED #1 Manual Set - AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1ManualSet - - Provisionable Default = 0x0 - - 1 = LED On - - */ - unsigned int led_1ManualSet : 1; /* 1E.C431.8 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED On - */ - /*! \brief 1E.C431.7 R/WPD LED #1 10 Gb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1_10Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 10 Gb/s - - */ - unsigned int led_1_10Gb_sLinkEstablished : 1; /* 1E.C431.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 10 Gb/s - */ - /*! \brief 1E.C431.6 R/WPD LED #1 1 Gb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1_1Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 1 Gb/s - - */ - unsigned int led_1_1Gb_sLinkEstablished : 1; /* 1E.C431.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 1 Gb/s - */ - /*! \brief 1E.C431.5 R/WPD LED #1 100 Mb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1_100Mb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 100 Mb/s - - */ - unsigned int led_1_100Mb_sLinkEstablished : 1; /* 1E.C431.5 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 100 Mb/s - */ - /*! \brief 1E.C431.4 R/WPD LED #1 Connecting - AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1Connecting - - Provisionable Default = 0x0 - - 1 = LED is on when attempting to connect. - - */ - unsigned int led_1Connecting : 1; /* 1E.C431.4 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when attempting to connect. - */ - /*! \brief 1E.C431.3 R/WPD LED #1 Receive Activity - AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1ReceiveActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on receive activity - - */ - unsigned int led_1ReceiveActivity : 1; /* 1E.C431.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on receive activity - */ - /*! \brief 1E.C431.2 R/WPD LED #1 Transmit Activity - AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1TransmitActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on transmit activity - - */ - unsigned int led_1TransmitActivity : 1; /* 1E.C431.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on transmit activity - */ - /*! \brief 1E.C431.1:0 R/WPD LED #1 Activity Stretch [1:0] - AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1ActivityStretch - - Provisionable Default = 0x3 - - [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - - */ - unsigned int led_1ActivityStretch : 2; /* 1E.C431.1:0 R/WPD Provisionable Default = 0x3 */ - /* [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global LED Provisioning */ - union - { - struct - { - unsigned int reserved0 : 7; - /*! \brief 1E.C432.8 R/WPD LED #2 Manual Set - AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2ManualSet - - Provisionable Default = 0x0 - - 1 = LED On - - */ - unsigned int led_2ManualSet : 1; /* 1E.C432.8 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED On - */ - /*! \brief 1E.C432.7 R/WPD LED #2 10 Gb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2_10Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 10 Gb/s - - */ - unsigned int led_2_10Gb_sLinkEstablished : 1; /* 1E.C432.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 10 Gb/s - */ - /*! \brief 1E.C432.6 R/WPD LED #2 1 Gb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2_1Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 1 Gb/s - - */ - unsigned int led_2_1Gb_sLinkEstablished : 1; /* 1E.C432.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 1 Gb/s - */ - /*! \brief 1E.C432.5 R/WPD LED #2 100 Mb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2_100Mb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 100 Mb/s - - */ - unsigned int led_2_100Mb_sLinkEstablished : 1; /* 1E.C432.5 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 100 Mb/s - */ - /*! \brief 1E.C432.4 R/WPD LED #2 Connecting - AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2Connecting - - Provisionable Default = 0x0 - - 1 = LED is on when attempting to connect. - - */ - unsigned int led_2Connecting : 1; /* 1E.C432.4 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when attempting to connect. - */ - /*! \brief 1E.C432.3 R/WPD LED #2 Receive Activity - AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2ReceiveActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on receive activity - - */ - unsigned int led_2ReceiveActivity : 1; /* 1E.C432.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on receive activity - */ - /*! \brief 1E.C432.2 R/WPD LED #2 Transmit Activity - AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2TransmitActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on transmit activity - - */ - unsigned int led_2TransmitActivity : 1; /* 1E.C432.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on transmit activity - */ - /*! \brief 1E.C432.1:0 R/WPD LED #2 Activity Stretch [1:0] - AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2ActivityStretch - - Provisionable Default = 0x3 - - [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - - */ - unsigned int led_2ActivityStretch : 2; /* 1E.C432.1:0 R/WPD Provisionable Default = 0x3 */ - /* [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global LED Provisioning */ - union - { - struct - { - unsigned int reserved0 : 7; - /*! \brief 1E.C433.8 R/WPD LED #3 Manual Set - AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3ManualSet - - Provisionable Default = 0x0 - - 1 = LED On - - */ - unsigned int led_3ManualSet : 1; /* 1E.C433.8 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED On - */ - /*! \brief 1E.C433.7 R/WPD LED #3 10 Gb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3_10Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 10 Gb/s - - */ - unsigned int led_3_10Gb_sLinkEstablished : 1; /* 1E.C433.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 10 Gb/s - */ - /*! \brief 1E.C433.6 R/WPD LED #3 1 Gb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3_1Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 1 Gb/s - - */ - unsigned int led_3_1Gb_sLinkEstablished : 1; /* 1E.C433.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 1 Gb/s - */ - /*! \brief 1E.C433.5 R/WPD LED #3 100 Mb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3_100Mb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 100 Mb/s - - */ - unsigned int led_3_100Mb_sLinkEstablished : 1; /* 1E.C433.5 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 100 Mb/s - */ - /*! \brief 1E.C433.4 R/WPD LED #3 Connecting - AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3Connecting - - Provisionable Default = 0x0 - - 1 = LED is on when attempting to connect. - - */ - unsigned int led_3Connecting : 1; /* 1E.C433.4 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when attempting to connect. - */ - /*! \brief 1E.C433.3 R/WPD LED #3 Receive Activity - AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3ReceiveActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on receive activity - - */ - unsigned int led_3ReceiveActivity : 1; /* 1E.C433.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on receive activity - */ - /*! \brief 1E.C433.2 R/WPD LED #3 Transmit Activity - AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3TransmitActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on transmit activity - - */ - unsigned int led_3TransmitActivity : 1; /* 1E.C433.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on transmit activity - */ - /*! \brief 1E.C433.1:0 R/WPD LED #3 Activity Stretch [1:0] - AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3ActivityStretch - - Provisionable Default = 0x3 - - [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - - */ - unsigned int led_3ActivityStretch : 2; /* 1E.C433.1:0 R/WPD Provisionable Default = 0x3 */ - /* [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - */ - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of Global LED Provisioning */ - union - { - struct - { - unsigned int reserved0 : 7; - /*! \brief 1E.C434.8 R/WPD LED #4 Manual Set - AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4ManualSet - - Provisionable Default = 0x0 - - 1 = LED On - - */ - unsigned int led_4ManualSet : 1; /* 1E.C434.8 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED On - */ - /*! \brief 1E.C434.7 R/WPD LED #4 10 Gb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4_10Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 10 Gb/s - - */ - unsigned int led_4_10Gb_sLinkEstablished : 1; /* 1E.C434.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 10 Gb/s - */ - /*! \brief 1E.C434.6 R/WPD LED #4 1 Gb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4_1Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 1 Gb/s - - */ - unsigned int led_4_1Gb_sLinkEstablished : 1; /* 1E.C434.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 1 Gb/s - */ - /*! \brief 1E.C434.5 R/WPD LED #4 100 Mb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4_100Mb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 100 Mb/s - - */ - unsigned int led_4_100Mb_sLinkEstablished : 1; /* 1E.C434.5 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 100 Mb/s - */ - /*! \brief 1E.C434.4 R/WPD LED #4 Connecting - AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4Connecting - - Provisionable Default = 0x0 - - 1 = LED is on when attempting to connect. - - */ - unsigned int led_4Connecting : 1; /* 1E.C434.4 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when attempting to connect. - */ - /*! \brief 1E.C434.3 R/WPD LED #4 Receive Activity - AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4ReceiveActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on receive activity - - */ - unsigned int led_4ReceiveActivity : 1; /* 1E.C434.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on receive activity - */ - /*! \brief 1E.C434.2 R/WPD LED #4 Transmit Activity - AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4TransmitActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on transmit activity - - */ - unsigned int led_4TransmitActivity : 1; /* 1E.C434.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on transmit activity - */ - /*! \brief 1E.C434.1:0 R/WPD LED #4 Activity Stretch [1:0] - AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4ActivityStretch - - Provisionable Default = 0x3 - - [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - - */ - unsigned int led_4ActivityStretch : 2; /* 1E.C434.1:0 R/WPD Provisionable Default = 0x3 */ - /* [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - */ - } bits_4; - uint16_t word_4; - } u4; - /*! \brief Union for bit and word level access of word 5 of Global LED Provisioning */ - union - { - struct - { - unsigned int reserved0 : 7; - /*! \brief 1E.C435.8 R/WPD LED #5 Manual Set - AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5ManualSet - - Provisionable Default = 0x0 - - 1 = LED On - - */ - unsigned int led_5ManualSet : 1; /* 1E.C435.8 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED On - */ - /*! \brief 1E.C435.7 R/WPD LED #5 10 Gb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5_10Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 10 Gb/s - - */ - unsigned int led_5_10Gb_sLinkEstablished : 1; /* 1E.C435.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 10 Gb/s - */ - /*! \brief 1E.C435.6 R/WPD LED #5 1 Gb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5_1Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 1 Gb/s - - */ - unsigned int led_5_1Gb_sLinkEstablished : 1; /* 1E.C435.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 1 Gb/s - */ - /*! \brief 1E.C435.5 R/WPD LED #5 100 Mb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5_100Mb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 100 Mb/s - - */ - unsigned int led_5_100Mb_sLinkEstablished : 1; /* 1E.C435.5 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 100 Mb/s - */ - /*! \brief 1E.C435.4 R/WPD LED #5 Connecting - AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5Connecting - - Provisionable Default = 0x0 - - 1 = LED is on when attempting to connect. - - */ - unsigned int led_5Connecting : 1; /* 1E.C435.4 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when attempting to connect. - */ - /*! \brief 1E.C435.3 R/WPD LED #5 Receive Activity - AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5ReceiveActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on receive activity - - */ - unsigned int led_5ReceiveActivity : 1; /* 1E.C435.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on receive activity - */ - /*! \brief 1E.C435.2 R/WPD LED #5 Transmit Activity - AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5TransmitActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on transmit activity - - */ - unsigned int led_5TransmitActivity : 1; /* 1E.C435.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on transmit activity - */ - /*! \brief 1E.C435.1:0 R/WPD LED #5 Activity Stretch [1:0] - AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5ActivityStretch - - Provisionable Default = 0x3 - - [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - - */ - unsigned int led_5ActivityStretch : 2; /* 1E.C435.1:0 R/WPD Provisionable Default = 0x3 */ - /* [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - */ - } bits_5; - uint16_t word_5; - } u5; - /*! \brief Union for bit and word level access of word 6 of Global LED Provisioning */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_6; - uint16_t word_6; - } u6; - /*! \brief Union for bit and word level access of word 7 of Global LED Provisioning */ - union - { - struct - { - unsigned int reserved0 : 15; - /*! \brief 1E.C437.0 R/WPD LED Operation Mode - AQ_GlobalLedProvisioning_APPIA.u7.bits_7.ledOperationMode - - Provisionable Default = 0x0 - - 1 = LED link activity in Mode #2 - 0 = LED link activity in classic mode - - - Notes: - When set to 1, the LED blinking rate is based on Mode #2 algorithm. When set to 0, the LED blinking rate is based on the classic algorithm. */ - unsigned int ledOperationMode : 1; /* 1E.C437.0 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED link activity in Mode #2 - 0 = LED link activity in classic mode - */ - } bits_7; - uint16_t word_7; - } u7; - /*! \brief Union for bit and word level access of word 8 of Global LED Provisioning */ - union - { - struct - { - unsigned int reserved0 : 13; - /*! \brief 1E.C438.2 R/WPD LED #0 Drive Three State Select - AQ_GlobalLedProvisioning_APPIA.u8.bits_8.led_0DriveThreeStateSelect - - Provisionable Default = 0x0 - - 1 = Drive LED tri-state when not active - 0 = Drive LED opposite of active level when not active - - */ - unsigned int led_0DriveThreeStateSelect : 1; /* 1E.C438.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = Drive LED tri-state when not active - 0 = Drive LED opposite of active level when not active - */ - /*! \brief 1E.C438.1 R/WPD LED #0 Active High Select - AQ_GlobalLedProvisioning_APPIA.u8.bits_8.led_0ActiveHighSelect - - Provisionable Default = 0x0 - - 1 = LED active high - 0 = LED active low - - - Notes: - The See LED #0 Manual Active Select bit must be 1 for this bit to take affect. */ - unsigned int led_0ActiveHighSelect : 1; /* 1E.C438.1 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED active high - 0 = LED active low - */ - /*! \brief 1E.C438.0 R/WPD LED #0 Manual Active Select - AQ_GlobalLedProvisioning_APPIA.u8.bits_8.led_0ManualActiveSelect - - Provisionable Default = 0x0 - - 1 = Manual selection of LED active high or low - 0 = Determine the active high or low based on the external pull-up or pull-down - - */ - unsigned int led_0ManualActiveSelect : 1; /* 1E.C438.0 R/WPD Provisionable Default = 0x0 */ - /* 1 = Manual selection of LED active high or low - 0 = Determine the active high or low based on the external pull-up or pull-down - */ - } bits_8; - uint16_t word_8; - } u8; - /*! \brief Union for bit and word level access of word 9 of Global LED Provisioning */ - union - { - struct - { - unsigned int reserved0 : 13; - /*! \brief 1E.C439.2 R/WPD LED #1 Drive Three State Select - AQ_GlobalLedProvisioning_APPIA.u9.bits_9.led_1DriveThreeStateSelect - - Provisionable Default = 0x0 - - 1 = Drive LED tri-state when not active - 0 = Drive LED opposite of active level when not active - - */ - unsigned int led_1DriveThreeStateSelect : 1; /* 1E.C439.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = Drive LED tri-state when not active - 0 = Drive LED opposite of active level when not active - */ - /*! \brief 1E.C439.1 R/WPD LED #1 Active High Select - AQ_GlobalLedProvisioning_APPIA.u9.bits_9.led_1ActiveHighSelect - - Provisionable Default = 0x0 - - 1 = LED active high - 0 = LED active low - - - Notes: - The See LED #1 Manual Active Select bit must be 1 for this bit to take affect. */ - unsigned int led_1ActiveHighSelect : 1; /* 1E.C439.1 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED active high - 0 = LED active low - */ - /*! \brief 1E.C439.0 R/WPD LED #1 Manual Active Select - AQ_GlobalLedProvisioning_APPIA.u9.bits_9.led_1ManualActiveSelect - - Provisionable Default = 0x0 - - 1 = Manual selection of LED active high or low - 0 = Determine the active high or low based on the external pull-up or pull-down - - */ - unsigned int led_1ManualActiveSelect : 1; /* 1E.C439.0 R/WPD Provisionable Default = 0x0 */ - /* 1 = Manual selection of LED active high or low - 0 = Determine the active high or low based on the external pull-up or pull-down - */ - } bits_9; - uint16_t word_9; - } u9; - /*! \brief Union for bit and word level access of word 10 of Global LED Provisioning */ - union - { - struct - { - unsigned int reserved0 : 13; - /*! \brief 1E.C43A.2 R/WPD LED #2 Drive Three State Select - AQ_GlobalLedProvisioning_APPIA.u10.bits_10.led_2DriveThreeStateSelect - - Provisionable Default = 0x0 - - 1 = Drive LED tri-state when not active - 0 = Drive LED opposite of active level when not active - - */ - unsigned int led_2DriveThreeStateSelect : 1; /* 1E.C43A.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = Drive LED tri-state when not active - 0 = Drive LED opposite of active level when not active - */ - /*! \brief 1E.C43A.1 R/WPD LED #2 Active High Select - AQ_GlobalLedProvisioning_APPIA.u10.bits_10.led_2ActiveHighSelect - - Provisionable Default = 0x0 - - 1 = LED active high - 0 = LED active low - - - Notes: - The See LED #2 Manual Active Select bit must be 1 for this bit to take affect. */ - unsigned int led_2ActiveHighSelect : 1; /* 1E.C43A.1 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED active high - 0 = LED active low - */ - /*! \brief 1E.C43A.0 R/WPD LED #2 Manual Active Select - AQ_GlobalLedProvisioning_APPIA.u10.bits_10.led_2ManualActiveSelect - - Provisionable Default = 0x0 - - 1 = Manual selection of LED active high or low - 0 = Determine the active high or low based on the external pull-up or pull-down - - */ - unsigned int led_2ManualActiveSelect : 1; /* 1E.C43A.0 R/WPD Provisionable Default = 0x0 */ - /* 1 = Manual selection of LED active high or low - 0 = Determine the active high or low based on the external pull-up or pull-down - */ - } bits_10; - uint16_t word_10; - } u10; - /*! \brief Union for bit and word level access of word 11 of Global LED Provisioning */ - union - { - struct - { - unsigned int reserved0 : 13; - /*! \brief 1E.C43B.2 R/WPD LED #3 Drive Three State Select - AQ_GlobalLedProvisioning_APPIA.u11.bits_11.led_3DriveThreeStateSelect - - Provisionable Default = 0x0 - - 1 = Drive LED tri-state when not active - 0 = Drive LED opposite of active level when not active - - */ - unsigned int led_3DriveThreeStateSelect : 1; /* 1E.C43B.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = Drive LED tri-state when not active - 0 = Drive LED opposite of active level when not active - */ - /*! \brief 1E.C43B.1 R/WPD LED #3 Active High Select - AQ_GlobalLedProvisioning_APPIA.u11.bits_11.led_3ActiveHighSelect - - Provisionable Default = 0x0 - - 1 = LED active high - 0 = LED active low - - - Notes: - The See LED #3 Manual Active Select bit must be 1 for this bit to take affect. */ - unsigned int led_3ActiveHighSelect : 1; /* 1E.C43B.1 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED active high - 0 = LED active low - */ - /*! \brief 1E.C43B.0 R/WPD LED #3 Manual Active Select - AQ_GlobalLedProvisioning_APPIA.u11.bits_11.led_3ManualActiveSelect - - Provisionable Default = 0x0 - - 1 = Manual selection of LED active high or low - 0 = Determine the active high or low based on the external pull-up or pull-down - - */ - unsigned int led_3ManualActiveSelect : 1; /* 1E.C43B.0 R/WPD Provisionable Default = 0x0 */ - /* 1 = Manual selection of LED active high or low - 0 = Determine the active high or low based on the external pull-up or pull-down - */ - } bits_11; - uint16_t word_11; - } u11; - /*! \brief Union for bit and word level access of word 12 of Global LED Provisioning */ - union - { - struct - { - unsigned int reserved0 : 13; - /*! \brief 1E.C43C.2 R/WPD LED #4 Drive Three State Select - AQ_GlobalLedProvisioning_APPIA.u12.bits_12.led_4DriveThreeStateSelect - - Provisionable Default = 0x0 - - 1 = Drive LED tri-state when not active - 0 = Drive LED opposite of active level when not active - - */ - unsigned int led_4DriveThreeStateSelect : 1; /* 1E.C43C.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = Drive LED tri-state when not active - 0 = Drive LED opposite of active level when not active - */ - /*! \brief 1E.C43C.1 R/WPD LED #4 Active High Select - AQ_GlobalLedProvisioning_APPIA.u12.bits_12.led_4ActiveHighSelect - - Provisionable Default = 0x0 - - 1 = LED active high - 0 = LED active low - - - Notes: - The See LED #4 Manual Active Select bit must be 1 for this bit to take affect. */ - unsigned int led_4ActiveHighSelect : 1; /* 1E.C43C.1 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED active high - 0 = LED active low - */ - /*! \brief 1E.C43C.0 R/WPD LED #4 Manual Active Select - AQ_GlobalLedProvisioning_APPIA.u12.bits_12.led_4ManualActiveSelect - - Provisionable Default = 0x0 - - 1 = Manual selection of LED active high or low - 0 = Determine the active high or low based on the external pull-up or pull-down - - */ - unsigned int led_4ManualActiveSelect : 1; /* 1E.C43C.0 R/WPD Provisionable Default = 0x0 */ - /* 1 = Manual selection of LED active high or low - 0 = Determine the active high or low based on the external pull-up or pull-down - */ - } bits_12; - uint16_t word_12; - } u12; - /*! \brief Union for bit and word level access of word 13 of Global LED Provisioning */ - union - { - struct - { - unsigned int reserved0 : 13; - /*! \brief 1E.C43D.2 R/WPD LED #5 Drive Three State Select - AQ_GlobalLedProvisioning_APPIA.u13.bits_13.led_5DriveThreeStateSelect - - Provisionable Default = 0x0 - - 1 = Drive LED tri-state when not active - 0 = Drive LED opposite of active level when not active - - */ - unsigned int led_5DriveThreeStateSelect : 1; /* 1E.C43D.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = Drive LED tri-state when not active - 0 = Drive LED opposite of active level when not active - */ - /*! \brief 1E.C43D.1 R/WPD LED #5 Active High Select - AQ_GlobalLedProvisioning_APPIA.u13.bits_13.led_5ActiveHighSelect - - Provisionable Default = 0x0 - - 1 = LED active high - 0 = LED active low - - - Notes: - The See LED #5 Manual Active Select bit must be 1 for this bit to take affect. */ - unsigned int led_5ActiveHighSelect : 1; /* 1E.C43D.1 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED active high - 0 = LED active low - */ - /*! \brief 1E.C43D.0 R/WPD LED #5 Manual Active Select - AQ_GlobalLedProvisioning_APPIA.u13.bits_13.led_5ManualActiveSelect - - Provisionable Default = 0x0 - - 1 = Manual selection of LED active high or low - 0 = Determine the active high or low based on the external pull-up or pull-down - - */ - unsigned int led_5ManualActiveSelect : 1; /* 1E.C43D.0 R/WPD Provisionable Default = 0x0 */ - /* 1 = Manual selection of LED active high or low - 0 = Determine the active high or low based on the external pull-up or pull-down - */ - } bits_13; - uint16_t word_13; - } u13; -} AQ_GlobalLedProvisioning_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global General Provisioning: 1E.C440 */ -/* Global General Provisioning: 1E.C440 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global General Provisioning */ - union - { - struct - { - unsigned int reserved0 : 7; - /*! \brief 1E.C440.8:4 R/WPD Gang Load MDIO Address [4:0] - AQ_GlobalGeneralProvisioning_APPIA.u0.bits_0.gangLoadMdioAddress - - Provisionable Default = 0x00 - - MDIO Address to be used during gang load operation - - - Notes: - Gang load operation is used to load data into multiple PHYs all connected to the same MDIO bus. The address for gang load operation is provided by these bits (8:4), and enabling is done by writing Bit 0. Disabling of gang load mode is done by writing the See MDIO Address Reset (1E.C441.2) bit. These will revert the PHY's MDIO address back to the address provided by the MDIO Address pins. During gang load operation, MDIO reads are disabled to prevent bus contention. */ - unsigned int gangLoadMdioAddress : 5; /* 1E.C440.8:4 R/WPD Provisionable Default = 0x00 */ - /* MDIO Address to be used during gang load operation - */ - unsigned int reserved1 : 3; - /*! \brief 1E.C440.0 RO Gang Load MDIO Write Only - AQ_GlobalGeneralProvisioning_APPIA.u0.bits_0.gangLoadMdioWriteOnly - - - - 1 = MDIO gang load enable - - - Notes: - This bit enables gang load operation with the address specified in Bits 8:4. */ - unsigned int gangLoadMdioWriteOnly : 1; /* 1E.C440.0 RO */ - /* 1 = MDIO gang load enable - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global General Provisioning */ - union - { - struct - { - unsigned int reserved0 : 1; - /*! \brief 1E.C441.E R/WPD MDIO Broadcast Mode Enable - AQ_GlobalGeneralProvisioning_APPIA.u1.bits_1.mdioBroadcastModeEnable - - Provisionable Default = 0x0 - - 1 = Enable broadcast on Address 0 - 0 = Disable broadcast on Address 0 - - - Notes: - When set, this bit enables gang-load operation on address zero, simultaneous with normal MDIO operation. Obviously, this requires that no PHY use address 0 as its normal operating address. As well, reads on MDIO Address 0 are disabled to prevent bus contention. */ - unsigned int mdioBroadcastModeEnable : 1; /* 1E.C441.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable broadcast on Address 0 - 0 = Disable broadcast on Address 0 - */ - /*! \brief 1E.C441.D R/WPD MDIO Read MSW First Enable - AQ_GlobalGeneralProvisioning_APPIA.u1.bits_1.mdioReadMSW_FirstEnable - - Provisionable Default = 0x0 - - 1 = MSW of counter must be read first - 0 = LSW of counter must be read first - - - Notes: - This bit configures whether the MSW or LSW must be read first for counters greater than 16 bits. */ - unsigned int mdioReadMSW_FirstEnable : 1; /* 1E.C441.D R/WPD Provisionable Default = 0x0 */ - /* 1 = MSW of counter must be read first - 0 = LSW of counter must be read first - */ - unsigned int reserved1 : 8; - /*! \brief 1E.C441.4 R/WPD MDIO Drive Configuration - AQ_GlobalGeneralProvisioning_APPIA.u1.bits_1.mdioDriveConfiguration - - Provisionable Default = 0x0 - - 0 = MDIO driver is in normal mode - 1 = MDIO driver is in open drain mode - - - Notes: - When the MDIO driver is in open drain mode during a read cycle, "0" data will be actively driven out of the MDIO, "1" data will set the MDIO driver in high impedance state and an external pullup will set the MDIO line to "1". The Turn-Around "0" will also be actively driven out of the MDIO, therefore in open drain mode, the Turn-Around is still "Z0". */ - unsigned int mdioDriveConfiguration : 1; /* 1E.C441.4 R/WPD Provisionable Default = 0x0 */ - /* 0 = MDIO driver is in normal mode - 1 = MDIO driver is in open drain mode - */ - /*! \brief 1E.C441.3 R/WPD MDIO Preamble Detection Disable - AQ_GlobalGeneralProvisioning_APPIA.u1.bits_1.mdioPreambleDetectionDisable - - Provisionable Default = 0x0 - - 1 = Suppress preamble detection on MDIO - 0 = Enable preamble detection on MDIO - - */ - unsigned int mdioPreambleDetectionDisable : 1; /* 1E.C441.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = Suppress preamble detection on MDIO - 0 = Enable preamble detection on MDIO - */ - /*! \brief 1E.C441.2 R/WSC MDIO Address Reset - AQ_GlobalGeneralProvisioning_APPIA.u1.bits_1.mdioAddressReset - - Default = 0x0 - - 1 = Load MDIO Address with the address on the MDIO address pins - - - Notes: - Used to reset the address after gang load and enable MDIO reads again. */ - unsigned int mdioAddressReset : 1; /* 1E.C441.2 R/WSC Default = 0x0 */ - /* 1 = Load MDIO Address with the address on the MDIO address pins - */ - unsigned int reserved2 : 2; - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global General Provisioning */ - union - { - struct - { - unsigned int reserved0 : 15; - /*! \brief 1E.C442.0 R/W Daisy Chain Reset - AQ_GlobalGeneralProvisioning_APPIA.u2.bits_2.daisyChainReset - - Default = 0x0 - - 1 = Reset the daisy chain - - - Notes: - Toggling this bit from 0 to 1 will reload the IRAM and DRAM and reset the uP. The uP will be in uP run stall during the reload process. After the reload process, uP run stall will be de-asserted adn the uP reset will be asserted. Note that before setting this bit, the See Soft Reset bit needs to be de-asserted. */ - unsigned int daisyChainReset : 1; /* 1E.C442.0 R/W Default = 0x0 */ - /* 1 = Reset the daisy chain - */ - } bits_2; - uint16_t word_2; - } u2; -} AQ_GlobalGeneralProvisioning_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global NVR Provisioning: 1E.C450 */ -/* Global NVR Provisioning: 1E.C450 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global NVR Provisioning */ - union - { - struct - { - unsigned int reserved0 : 5; - /*! \brief 1E.C450.A:8 R/WPD NVR Data Length [2:0] - AQ_GlobalNvrProvisioning_APPIA.u0.bits_0.nvrDataLength - - Provisionable Default = 0x4 - - NVR data length ranges from 0 bytes to 4 bytes - - - Notes: - This sets the length of the data burst used in read and write operations. - */ - unsigned int nvrDataLength : 3; /* 1E.C450.A:8 R/WPD Provisionable Default = 0x4 */ - /* NVR data length ranges from 0 bytes to 4 bytes - */ - unsigned int reserved1 : 1; - /*! \brief 1E.C450.6:4 R/WPD NVR Dummy Length [2:0] - AQ_GlobalNvrProvisioning_APPIA.u0.bits_0.nvrDummyLength - - Provisionable Default = 0x0 - - NVR dummy length ranges from 0 bytes to 4 bytes. - - - Notes: - This sets the length of the dummy field used in some maunfacturer's read status and write status operations. - */ - unsigned int nvrDummyLength : 3; /* 1E.C450.6:4 R/WPD Provisionable Default = 0x0 */ - /* NVR dummy length ranges from 0 bytes to 4 bytes. - */ - unsigned int reserved2 : 2; - /*! \brief 1E.C450.1:0 R/WPD NVR Address Length [1:0] - AQ_GlobalNvrProvisioning_APPIA.u0.bits_0.nvrAddressLength - - Provisionable Default = 0x2 - - NVR address length ranges from 0 bytes up to 3 bytes. - - - Notes: - This sets the length of the address field used in read and write operations. Use of this field is enabled via Bit 8 of See Global NVR Provisioning 2: Address 1E.C451 . - */ - unsigned int nvrAddressLength : 2; /* 1E.C450.1:0 R/WPD Provisionable Default = 0x2 */ - /* NVR address length ranges from 0 bytes up to 3 bytes. - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global NVR Provisioning */ - union - { - struct - { - unsigned int reserved0 : 7; - /*! \brief 1E.C451.8 R/WPD NVR Address Length Override - AQ_GlobalNvrProvisioning_APPIA.u1.bits_1.nvrAddressLengthOverride - - Provisionable Default = 0x0 - - 0 = NVR address length is based on the "NVR_SIZE" pin. - 1 = NVR address length is based on the See NVR Address Length [1:0] register. - - - Notes: - When the this bit = 0 and NVR_SIZE pin = 0, the NVR address length is 2 bytes. When this bit = 0 and the NVR_SIZE pin = 1, the NVR address length is 3 bytes. When this bit = 1 the NVR address length is from the See NVR Address Length [1:0] */ - unsigned int nvrAddressLengthOverride : 1; /* 1E.C451.8 R/WPD Provisionable Default = 0x0 */ - /* 0 = NVR address length is based on the "NVR_SIZE" pin. - 1 = NVR address length is based on the See NVR Address Length [1:0] register. - */ - /*! \brief 1E.C451.7:0 R/WPD NVR Clock Divide [7:0] - AQ_GlobalNvrProvisioning_APPIA.u1.bits_1.nvrClockDivide - - Provisionable Default = 0xA0 - - NVR clock divide. Clock frequency is divided by the NVR clock divide + 1 - - */ - unsigned int nvrClockDivide : 8; /* 1E.C451.7:0 R/WPD Provisionable Default = 0xA0 */ - /* NVR clock divide. Clock frequency is divided by the NVR clock divide + 1 - */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global NVR Provisioning */ - union - { - struct - { - unsigned int reserved0 : 14; - /*! \brief 1E.C452.1 R/W NVR Daisy Chain Clock Divide Override - AQ_GlobalNvrProvisioning_APPIA.u2.bits_2.nvrDaisyChainClockDivideOverride - - Default = 0x0 - - 1 = Override NVR clock divide when in daisy chain master mode - - - - Notes: - When in daisy chain master mode, the clock divide configuration is received from the flash. This bit will override the clock divide configuration from the flash with the See NVR Clock Divide [7:0] . */ - unsigned int nvrDaisyChainClockDivideOverride : 1; /* 1E.C452.1 R/W Default = 0x0 */ - /* 1 = Override NVR clock divide when in daisy chain master mode - - */ - /*! \brief 1E.C452.0 R/W NVR Daisy Chain Disable - AQ_GlobalNvrProvisioning_APPIA.u2.bits_2.nvrDaisyChainDisable - - Default = 0x0 - - 1 = Disable the Daisy Chain - - - Notes: - When in daisy chain master mode, the daisy chain and MDIO can both access the SPI. Setting this bit to 1 will disable the dasiy chain from accessing the SPI and force it into a reset state. */ - unsigned int nvrDaisyChainDisable : 1; /* 1E.C452.0 R/W Default = 0x0 */ - /* 1 = Disable the Daisy Chain - */ - } bits_2; - uint16_t word_2; - } u2; -} AQ_GlobalNvrProvisioning_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Reserved Provisioning: 1E.C470 */ -/* Global Reserved Provisioning: 1E.C470 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Reserved Provisioning */ - union - { - struct - { - /*! \brief 1E.C470.F R/WPD Diagnostics Select - AQ_GlobalReservedProvisioning_APPIA.u0.bits_0.diagnosticsSelect - - Provisionable Default = 0x0 - - 1 = Provide Extended MDI Diagnostics Information. - 0 = Provide normal cable diagnostics - - - Notes: - These bits select what sort of cable diagnostics to perform. For regular cable diagnostics, Bit F is set to zero, and the diagnostics are triggered by setting Bit 4. For extended diagnostics, Bit F is set to 1, and the desired extended diagnostics are selected by Bits E:D. The routine is then triggered by setting Bit 4. Each of the extended diagnostic routines present data for all for MDI pairs (A, B, C, D) consecutively, and after the data for each channel is gathered Bits F:D are reset. To get the data for the next pair, Bits F:D must be set back to the desired value (which must be the same as the initial channel). This continues until the data for all channels has been gathered. The address in memory where the data is stored is given in 1E.C802 and 1E.C804. - - For the case of PSD, the structure is as follows: - Int32 info - Int16 data[Len] - Info = Len << 16 | TxEnable << 8 | Pair (0 = A, etc.) - - For TDR: - Int32 info - Int16 tdr_A[Len] - Int16 tdr_B[Len] - Int16 tdr_C[Len] - Int16 tdr_D[Len] - - Info = Len << 16 | Channel - - TDR data is from the current pair to all other pairs. - - At the end of retrieving extended MDI diag data, the part will be reset. Conversly the only way to exit this routine once it starts is to issue a PMA reset. */ - unsigned int diagnosticsSelect : 1; /* 1E.C470.F R/WPD Provisionable Default = 0x0 */ - /* 1 = Provide Extended MDI Diagnostics Information. - 0 = Provide normal cable diagnostics - */ - /*! \brief 1E.C470.E:D R/WPD Extended MDI Diagnostics Select [1:0] - AQ_GlobalReservedProvisioning_APPIA.u0.bits_0.extendedMdiDiagnosticsSelect - - Provisionable Default = 0x0 - - 0x0 = TDR Data - 0x1 = RFI Channel PSD - 0x2 = Noise PSD while the local Tx is Off - 0x3 = Noise PSD while the local Tx is On - - - Notes: - These bits select what sort of cable diagnostics to perform. For regular cable diagnostics, Bit F is set to zero, and the diagnostics are triggered by setting Bit 4. For extended diagnostics, Bit F is set to 1, and the desired extended diagnostics are selected by Bits E:D. The routine is then triggered by setting Bit 4. Each of the extended diagnostic routines present data for all for MDI pairs (A, B, C, D) consecutively, and after the data for each channel is gathered Bits F:D are reset. To get the data for the next pair, Bits F:D must be set back to the desired value (which must be the same as the initial channel). This continues until the data for all channels has been gathered. The address in memory where the data is stored is given in 1E.C802 and 1E.C804. - - For the case of PSD, the structure is as follows: - Int32 info - Int16 data[Len] - Info = Len << 16 | TxEnable << 8 | Pair (0 = A, etc.) - - For TDR: - Int32 info - Int16 tdr_A[Len] - Int16 tdr_B[Len] - Int16 tdr_C[Len] - Int16 tdr_D[Len] - - Info = Len << 16 | Channel - - TDR data is from the current pair to all other pairs. - - At the end of retrieving extended MDI diag data, the part will be reset. Conversly the only way to exit this routine once it starts is to issue a PMA reset. */ - unsigned int extendedMdiDiagnosticsSelect : 2; /* 1E.C470.E:D R/WPD Provisionable Default = 0x0 */ - /* 0x0 = TDR Data - 0x1 = RFI Channel PSD - 0x2 = Noise PSD while the local Tx is Off - 0x3 = Noise PSD while the local Tx is On - */ - unsigned int reserved0 : 5; - unsigned int reserved1 : 2; - /*! \brief 1E.C470.5 R/WSC Initiate Component Diagnostics - AQ_GlobalReservedProvisioning_APPIA.u0.bits_0.initiateComponentDiagnostics - - Default = 0x0 - - 1 = Perform component diagnostics - - - Notes: - Perform component diagnostics regardless of link state. If link is up, setting this bit will cause the link to drop while diagnostics are performed. This bit is self-clearing upon completion of the component diagnostics. Further MDIO writes should be avoided until this bit has self-cleared, indicating completion of the diagnostic routine. */ - unsigned int initiateComponentDiagnostics : 1; /* 1E.C470.5 R/WSC Default = 0x0 */ - /* 1 = Perform component diagnostics - */ - /*! \brief 1E.C470.4 R/WSC Initiate Cable Diagnostics - AQ_GlobalReservedProvisioning_APPIA.u0.bits_0.initiateCableDiagnostics - - Default = 0x0 - - 1 = Perform cable diagnostics - - - Notes: - Perform cable diagnostics regardless of link state. If link is up, setting this bit will cause the link to drop while diagnostics are performed. This bit is self-clearing upon completion of the cable diagnostics. Further MDIO writes should be avoided until this bit has self-cleared, indicating completion of the diagnostic routine. */ - unsigned int initiateCableDiagnostics : 1; /* 1E.C470.4 R/WSC Default = 0x0 */ - /* 1 = Perform cable diagnostics - */ - unsigned int reserved2 : 4; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Reserved Provisioning */ - union - { - struct - { - /*! \brief 1E.C471.F:7 R/WPD Reserved Provisioning 2 [8:0] - AQ_GlobalReservedProvisioning_APPIA.u1.bits_1.reservedProvisioning_2 - - Provisionable Default = 0x000 - - Reserved for future use - - */ - unsigned int reservedProvisioning_2 : 9; /* 1E.C471.F:7 R/WPD Provisionable Default = 0x000 */ - /* Reserved for future use - */ - /*! \brief 1E.C471.6 R/WuP Enable Daisy-Chain Hop-Count Override - AQ_GlobalReservedProvisioning_APPIA.u1.bits_1.enableDaisy_chainHop_countOverride - - Default = 0x0 - - 1 = Hop-count is set by Bits 5:0 - 0 = Hop-count is determined by the daisy-chain - - - Notes: - Daisy-Chain Hop-Count Override should be used during MDIO boot-load operation, as the daisy-chain hop-count does not function when the daisy-chain is disabled (1E.C452.0). Setting this bit tells the processor where in the diasy-chain it is, so that the provisioning operation will function correctly. */ - unsigned int enableDaisy_chainHop_countOverride : 1; /* 1E.C471.6 R/WuP Default = 0x0 */ - /* 1 = Hop-count is set by Bits 5:0 - 0 = Hop-count is determined by the daisy-chain - */ - /*! \brief 1E.C471.5:0 R/WuP Daisy-Chain Hop-Count Override Value [5:0] - AQ_GlobalReservedProvisioning_APPIA.u1.bits_1.daisy_chainHop_countOverrideValue - - Default = 0x00 - - The value to use for the PHY's daisy-chain hop-count. Valid values are from 0 -> 47 - - - Notes: - Daisy-Chain Hop-Count Override should be used during MDIO boot-load operation, as the daisy-chain hop-count does not function when the daisy-chain is disabled (1E.C452.0). Setting this bit tells the processor where in the diasy-chain it is, so that the provisioning operation will function correctly. */ - unsigned int daisy_chainHop_countOverrideValue : 6; /* 1E.C471.5:0 R/WuP Default = 0x00 */ - /* The value to use for the PHY's daisy-chain hop-count. Valid values are from 0 -> 47 - */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global Reserved Provisioning */ - union - { - struct - { - /*! \brief 1E.C472.F R/WPD Enable LVDD Power Supply Tuning - AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.enableLvddPowerSupplyTuning - - Provisionable Default = 0x0 - - 1 = Enable external LVDD power supply tuning - 0 = Disable external LVDD power supply tuning is disabled - - - Notes: - - - - These bits control whether the PHY attempts to tune the external VDD and LVDD power supplies via the PMBus. These bits are only operational if the external supplies are present (see Bits 7:6) */ - unsigned int enableLvddPowerSupplyTuning : 1; /* 1E.C472.F R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable external LVDD power supply tuning - 0 = Disable external LVDD power supply tuning is disabled - */ - /*! \brief 1E.C472.E R/WPD Enable VDD Power Supply Tuning - AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.enableVddPowerSupplyTuning - - Provisionable Default = 0x0 - - 1 = Enable external VDD power supply tuning - 0 = Disable external VDD power supply tuning is disabled - - - Notes: - - - - These bits control whether the PHY attempts to tune the external VDD and LVDD power supplies via the PMBus. These bits are only operational if the external supplies are present (see Bits 7:6) */ - unsigned int enableVddPowerSupplyTuning : 1; /* 1E.C472.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable external VDD power supply tuning - 0 = Disable external VDD power supply tuning is disabled - */ - unsigned int reserved0 : 6; - /*! \brief 1E.C472.7 R/WPD Tunable External LVDD Power Supply Present - AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.tunableExternalLvddPowerSupplyPresent - - Provisionable Default = 0x0 - - 1 = Tunable external LVDD power supply present - 0 = No tunable external LVDD power supply present - - - Notes: - - - - These bits must be set if tuning of external power supplies is desired (see Bits 7:6) */ - unsigned int tunableExternalLvddPowerSupplyPresent : 1; /* 1E.C472.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = Tunable external LVDD power supply present - 0 = No tunable external LVDD power supply present - */ - /*! \brief 1E.C472.6 R/WPD Tunable External VDD Power Supply Present - AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.tunableExternalVddPowerSupplyPresent - - Provisionable Default = 0x0 - - 1 = Tunable external VDD power supply present - 0 = No tunable external VDD power supply present - - - Notes: - - - - These bits must be set if tuning of external power supplies is desired (see Bits 7:6) */ - unsigned int tunableExternalVddPowerSupplyPresent : 1; /* 1E.C472.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = Tunable external VDD power supply present - 0 = No tunable external VDD power supply present - */ - unsigned int reserved1 : 4; - /*! \brief 1E.C472.1 R/WPDuP Enable XENPAK Register Space - AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.enableXenpakRegisterSpace - - Provisionable Default = 0x0 - - 1 = XENPAK register space enabled - 0 = XENPAK register space disabled - - */ - unsigned int enableXenpakRegisterSpace : 1; /* 1E.C472.1 R/WPDuP Provisionable Default = 0x0 */ - /* 1 = XENPAK register space enabled - 0 = XENPAK register space disabled - */ - /*! \brief 1E.C472.0 R/WPDuP Enable 5th Channel RFI Cancellation - AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.enable_5thChannelRfiCancellation - - Provisionable Default = 0x0 - - 1 = 5th channel and RFI cancellers operation enabled - 0 = 5th channel AFE is powered down, 5th channel digital is clock gated, RFI cancellers are disabled - - - Notes: - Note: The value of this bit at the time of Autonegotiation sets the local PHY behavior until the next time Autonegotiation occurs. */ - unsigned int enable_5thChannelRfiCancellation : 1; /* 1E.C472.0 R/WPDuP Provisionable Default = 0x0 */ - /* 1 = 5th channel and RFI cancellers operation enabled - 0 = 5th channel AFE is powered down, 5th channel digital is clock gated, RFI cancellers are disabled - */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global Reserved Provisioning */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of Global Reserved Provisioning */ - union - { - struct - { - unsigned int reserved0 : 8; - /*! \brief 1E.C474.7:0 R/WPD Training SNR [7:0] - AQ_GlobalReservedProvisioning_APPIA.u4.bits_4.trainingSNR - - Provisionable Default = 0x00 - - SNR during 10G training on the worst channel. SNR is in steps of 0.1dB - - - Notes: - The SNR margin that is enjoyed by the worst channel, over and above the minimum SNR required to operate at a BER of 10-12. It is reported with 0.1 dB of resolution to an accuracy of 0.5 dB within the range of -12.7 dB to 12.7 dB. The number is in offset binary, with 0.0 dB represented by 0x8000. - */ - unsigned int trainingSNR : 8; /* 1E.C474.7:0 R/WPD Provisionable Default = 0x00 */ - /* SNR during 10G training on the worst channel. SNR is in steps of 0.1dB - */ - } bits_4; - uint16_t word_4; - } u4; - /*! \brief Union for bit and word level access of word 5 of Global Reserved Provisioning */ - union - { - struct - { - unsigned int reserved0 : 2; - /*! \brief 1E.C475.D R/WPD Smart Power-Down Status - AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.smartPower_downStatus - - Provisionable Default = 0x0 - - 1 = Smart Power-Down Active - 0 = Smart Power-Down Inactive - - */ - unsigned int smartPower_downStatus : 1; /* 1E.C475.D R/WPD Provisionable Default = 0x0 */ - /* 1 = Smart Power-Down Active - 0 = Smart Power-Down Inactive - */ - /*! \brief 1E.C475.C R/WPD Reserved Provisioning 6 - AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.reservedProvisioning_6 - - Provisionable Default = 0x0 - - Reserved for future use - - */ - unsigned int reservedProvisioning_6 : 1; /* 1E.C475.C R/WPD Provisionable Default = 0x0 */ - /* Reserved for future use - */ - /*! \brief 1E.C475.B R/WPD CFR LP Disable Timer - AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrLpDisableTimer - - Provisionable Default = 0x0 - - 1 = Link partner requires cfr_disable timer - 0 = Link partner does not require cfr_disable timer - - */ - unsigned int cfrLpDisableTimer : 1; /* 1E.C475.B R/WPD Provisionable Default = 0x0 */ - /* 1 = Link partner requires cfr_disable timer - 0 = Link partner does not require cfr_disable timer - */ - /*! \brief 1E.C475.A R/WPD CFR LP Extended Maxwait - AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrLpExtendedMaxwait - - Provisionable Default = 0x0 - - 1 = Link partner requires extended maxwait - 0 = Link partner does not require extended maxwait - - */ - unsigned int cfrLpExtendedMaxwait : 1; /* 1E.C475.A R/WPD Provisionable Default = 0x0 */ - /* 1 = Link partner requires extended maxwait - 0 = Link partner does not require extended maxwait - */ - /*! \brief 1E.C475.9 R/WPD CFR LP THP - AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrLpTHP - - Provisionable Default = 0x0 - - 1 = Link partner requires local PHY to enable THP - 0 = Link partner does not require local PHY to enable THP - - */ - unsigned int cfrLpTHP : 1; /* 1E.C475.9 R/WPD Provisionable Default = 0x0 */ - /* 1 = Link partner requires local PHY to enable THP - 0 = Link partner does not require local PHY to enable THP - */ - /*! \brief 1E.C475.8 R/WPD CFR LP Support - AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrLpSupport - - Provisionable Default = 0x0 - - 1 = Link partner supports Cisco Fast Retrain - 0 = Link partner does support Cisco Fast Retrain - - */ - unsigned int cfrLpSupport : 1; /* 1E.C475.8 R/WPD Provisionable Default = 0x0 */ - /* 1 = Link partner supports Cisco Fast Retrain - 0 = Link partner does support Cisco Fast Retrain - */ - /*! \brief 1E.C475.7 R/WPD CFR Disable Timer - AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrDisableTimer - - Provisionable Default = 0x0 - - 1 = Local PHY requires cfr_disable timer - 0 = Local PHY does not require cfr_disable timer - - */ - unsigned int cfrDisableTimer : 1; /* 1E.C475.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = Local PHY requires cfr_disable timer - 0 = Local PHY does not require cfr_disable timer - */ - /*! \brief 1E.C475.6 R/WPD CFR Extended Maxwait - AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrExtendedMaxwait - - Provisionable Default = 0x0 - - 1 = Local PHY requires extended maxwait - 0 = Local PHY does not require extended maxwait - - */ - unsigned int cfrExtendedMaxwait : 1; /* 1E.C475.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = Local PHY requires extended maxwait - 0 = Local PHY does not require extended maxwait - */ - /*! \brief 1E.C475.5 R/WPD CFR THP - AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrTHP - - Provisionable Default = 0x0 - - 1 = Local PHY requires local PHY to enable THP - 0 = Local PHY does not require local PHY to enable THP - - */ - unsigned int cfrTHP : 1; /* 1E.C475.5 R/WPD Provisionable Default = 0x0 */ - /* 1 = Local PHY requires local PHY to enable THP - 0 = Local PHY does not require local PHY to enable THP - */ - /*! \brief 1E.C475.4 R/WPD CFR Support - AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrSupport - - Provisionable Default = 0x0 - - 1 = Local PHY supports Cisco Fast Retrain - 0 = Local PHY does support Cisco Fast Retrain - - */ - unsigned int cfrSupport : 1; /* 1E.C475.4 R/WPD Provisionable Default = 0x0 */ - /* 1 = Local PHY supports Cisco Fast Retrain - 0 = Local PHY does support Cisco Fast Retrain - */ - /*! \brief 1E.C475.3 R/WPD Deadlock Avoidance Enable - AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.deadlockAvoidanceEnable - - Provisionable Default = 0x0 - - 1 = SPD with deadlock avoidance: PHY transmits autonegotiation pulses (FLPs) at a slower rate (~ 1 FLP/ 100ms) than specified by autonegotiation standard (~1 FLP / 8.25ms). Receiver is active and able to detect the pulses. - 0 = SPD without deadlock avoidance: PHY transmitter is shut down, no autonegotiation pulses are sent on the line but the receiver is active and able to detect the pulses - - */ - unsigned int deadlockAvoidanceEnable : 1; /* 1E.C475.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = SPD with deadlock avoidance: PHY transmits autonegotiation pulses (FLPs) at a slower rate (~ 1 FLP/ 100ms) than specified by autonegotiation standard (~1 FLP / 8.25ms). Receiver is active and able to detect the pulses. - 0 = SPD without deadlock avoidance: PHY transmitter is shut down, no autonegotiation pulses are sent on the line but the receiver is active and able to detect the pulses - */ - /*! \brief 1E.C475.2 R/WPD Smart Power-Down Enable - AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.smartPower_downEnable - - Provisionable Default = 0x0 - - 1 = Enable smart power down mode - 0 = Smart power-down mode disabled - - - Notes: - Smart power down (SPD) is the lowest power mode at which PHY is able to autonegotiate. SPD can be enabled with bit 1E.C475.2 */ - unsigned int smartPower_downEnable : 1; /* 1E.C475.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable smart power down mode - 0 = Smart power-down mode disabled - */ - unsigned int reserved1 : 2; - } bits_5; - uint16_t word_5; - } u5; -} AQ_GlobalReservedProvisioning_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Cable Diagnostic Status: 1E.C800 */ -/* Global Cable Diagnostic Status: 1E.C800 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Cable Diagnostic Status */ - union - { - struct - { - unsigned int reserved0 : 1; - /*! \brief 1E.C800.E:C RO Pair A Status [2:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u0.bits_0.pairAStatus - - - - (after running cable diags) - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair D - 010= Connected to Pair C - 001= Connected to Pair B - 000= OK - - OR: - - (after running component diags) - 100 = TX pin open - 011= TX bias open - 010= Capacitor short - 001= Inductor open - 000= OK - - Notes: - This bitfield reports the result, for pair A, of running either cable diagnostics or component diagnostics. */ - unsigned int pairAStatus : 3; /* 1E.C800.E:C RO */ - /* (after running cable diags) - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair D - 010= Connected to Pair C - 001= Connected to Pair B - 000= OK - - OR: - - (after running component diags) - 100 = TX pin open - 011= TX bias open - 010= Capacitor short - 001= Inductor open - 000= OK */ - unsigned int reserved1 : 1; - /*! \brief 1E.C800.A:8 RO Pair B Status [2:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u0.bits_0.pairBStatus - - - - (after running cable diags) - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair A - 010= Connected to Pair D - 001= Connected to Pair C - 000= OK - - OR: - - (after running component diags) - 100 = TX pin open - 011= TX bias open - 010= Capacitor short - 001= Inductor open - 000= OK - - Notes: - This bitfield reports the result, for pair B, of running either cable diagnostics or component diagnostics. */ - unsigned int pairBStatus : 3; /* 1E.C800.A:8 RO */ - /* (after running cable diags) - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair A - 010= Connected to Pair D - 001= Connected to Pair C - 000= OK - - OR: - - (after running component diags) - 100 = TX pin open - 011= TX bias open - 010= Capacitor short - 001= Inductor open - 000= OK */ - unsigned int reserved2 : 1; - /*! \brief 1E.C800.6:4 RO Pair C Status [2:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u0.bits_0.pairCStatus - - - - (after running cable diags) - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair B - 010= Connected to Pair A - 001= Connected to Pair D - 000= OK - - OR: - - (after running component diags) - 100 = TX pin open - 011= TX bias open - 010= Capacitor short - 001= Inductor open - 000= OK - - Notes: - This bitfield reports the result, for pair C, of running either cable diagnostics or component diagnostics. */ - unsigned int pairCStatus : 3; /* 1E.C800.6:4 RO */ - /* (after running cable diags) - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair B - 010= Connected to Pair A - 001= Connected to Pair D - 000= OK - - OR: - - (after running component diags) - 100 = TX pin open - 011= TX bias open - 010= Capacitor short - 001= Inductor open - 000= OK */ - unsigned int reserved3 : 1; - /*! \brief 1E.C800.2:0 RO Pair D Status [2:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u0.bits_0.pairDStatus - - - - (after running cable diags) - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair C - 010= Connected to Pair B - 001= Connected to Pair A - 000= OK - - OR: - - (after running component diags) - 100 = TX pin open - 011= TX bias open - 010= Capacitor short - 001= Inductor open - 000= OK - - Notes: - This bitfield reports the result, for pair D, of running either cable diagnostics or component diagnostics. */ - unsigned int pairDStatus : 3; /* 1E.C800.2:0 RO */ - /* (after running cable diags) - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair C - 010= Connected to Pair B - 001= Connected to Pair A - 000= OK - - OR: - - (after running component diags) - 100 = TX pin open - 011= TX bias open - 010= Capacitor short - 001= Inductor open - 000= OK */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C801.F:8 RO Pair A Reflection #1 [7:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u1.bits_1.pairAReflection_1 - - - - The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair A - - Notes: - The distance to this reflection is given in See Global Reserved Status 1: Address 1E.C870 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairAReflection_1 : 8; /* 1E.C801.F:8 RO */ - /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair A */ - /*! \brief 1E.C801.7:0 RO Pair A Reflection #2 [7:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u1.bits_1.pairAReflection_2 - - - - The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair A - - Notes: - The distance to this reflection is given in See Global Reserved Status 1: Address 1E.C870 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairAReflection_2 : 8; /* 1E.C801.7:0 RO */ - /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair A */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C802.F:0 RO Impulse Response MSW [F:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u2.bits_2.impulseResponseMSW - - - - The MSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type in 1E.C470.E:D - - - Notes: - See 1E.C470 for more information */ - unsigned int impulseResponseMSW : 16; /* 1E.C802.F:0 RO */ - /* The MSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type in 1E.C470.E:D - */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C803.F:8 RO Pair B Reflection #1 [7:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u3.bits_3.pairBReflection_1 - - - - The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair B - - Notes: - The distance to this reflection is given in See Global Reserved Status 2: Address 1E.C871 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairBReflection_1 : 8; /* 1E.C803.F:8 RO */ - /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair B */ - /*! \brief 1E.C803.7:0 RO Pair B Reflection #2 [7:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u3.bits_3.pairBReflection_2 - - - - The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair B - - Notes: - The distance to this reflection is given in See Global Reserved Status 2: Address 1E.C871 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairBReflection_2 : 8; /* 1E.C803.7:0 RO */ - /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair B */ - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C804.F:0 RO Impulse Response LSW [F:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u4.bits_4.impulseResponseLSW - - - - The LSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type specified in 1E.C470.E:D - - - Notes: - See 1E.C470 for more information */ - unsigned int impulseResponseLSW : 16; /* 1E.C804.F:0 RO */ - /* The LSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type specified in 1E.C470.E:D - */ - } bits_4; - uint16_t word_4; - } u4; - /*! \brief Union for bit and word level access of word 5 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C805.F:8 RO Pair C Reflection #1 [7:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u5.bits_5.pairCReflection_1 - - - - The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair C - - Notes: - The distance to this reflection is given in See Global Reserved Status 3: Address 1E.C872 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairCReflection_1 : 8; /* 1E.C805.F:8 RO */ - /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair C */ - /*! \brief 1E.C805.7:0 RO Pair C Reflection #2 [7:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u5.bits_5.pairCReflection_2 - - - - The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair C - - Notes: - The distance to this reflection is given in See Global Reserved Status 3: Address 1E.C872 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairCReflection_2 : 8; /* 1E.C805.7:0 RO */ - /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair C */ - } bits_5; - uint16_t word_5; - } u5; - /*! \brief Union for bit and word level access of word 6 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C806.F:0 RO Reserved 1 [F:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u6.bits_6.reserved_1 - - - - Reserved for future use - - */ - unsigned int reserved_1 : 16; /* 1E.C806.F:0 RO */ - /* Reserved for future use - */ - } bits_6; - uint16_t word_6; - } u6; - /*! \brief Union for bit and word level access of word 7 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C807.F:8 RO Pair D Reflection #1 [7:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u7.bits_7.pairDReflection_1 - - - - The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair D - - Notes: - The distance to this reflection is given in See Global Reserved Status 4: Address 1E.C873 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairDReflection_1 : 8; /* 1E.C807.F:8 RO */ - /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair D */ - /*! \brief 1E.C807.7:0 RO Pair D Reflection #2 [7:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u7.bits_7.pairDReflection_2 - - - - The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair D - - Notes: - The distance to this reflection is given in See Global Reserved Status 4: Address 1E.C873 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairDReflection_2 : 8; /* 1E.C807.7:0 RO */ - /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair D */ - } bits_7; - uint16_t word_7; - } u7; - /*! \brief Union for bit and word level access of word 8 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C808.F:0 RO Reserved 2[F:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u8.bits_8.reserved_2 - - - - Reserved for future use - - */ - unsigned int reserved_2 : 16; /* 1E.C808.F:0 RO */ - /* Reserved for future use - */ - } bits_8; - uint16_t word_8; - } u8; -} AQ_GlobalCableDiagnosticStatus_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Thermal Status: 1E.C820 */ -/* Global Thermal Status: 1E.C820 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Thermal Status */ - union - { - struct - { - /*! \brief 1E.C820.F:0 RO Temperature [F:0] - AQ_GlobalThermalStatus_APPIA.u0.bits_0.temperature - - - - [F:0] of temperature - - - Notes: - 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 70 degreesC. This is a mirror of the XENPAK register 1.A060 - 1.A061. The mirror is performed in H/W. */ - unsigned int temperature : 16; /* 1E.C820.F:0 RO */ - /* [F:0] of temperature - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Thermal Status */ - union - { - struct - { - unsigned int reserved0 : 15; - /*! \brief 1E.C821.0 RO Temperature Ready - AQ_GlobalThermalStatus_APPIA.u1.bits_1.temperatureReady - - - - 1 = Temperature measurement is valid - - - Notes: - This is a mirror of the XENPAK register 1.A06E. */ - unsigned int temperatureReady : 1; /* 1E.C821.0 RO */ - /* 1 = Temperature measurement is valid - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_GlobalThermalStatus_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global General Status: 1E.C830 */ -/* Global General Status: 1E.C830 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global General Status */ - union - { - struct - { - unsigned int reserved0 : 1; - /*! \brief 1E.C830.E RO High Temperature Failure State - AQ_GlobalGeneralStatus_APPIA.u0.bits_0.highTemperatureFailureState - - - - 1 = High temperature failure threshold has been exceeded - - Notes: - In XENPAK mode, F/W will copy this register to the 1.A070.7 register. - - */ - unsigned int highTemperatureFailureState : 1; /* 1E.C830.E RO */ - /* 1 = High temperature failure threshold has been exceeded */ - /*! \brief 1E.C830.D RO Low Temperature Failure State - AQ_GlobalGeneralStatus_APPIA.u0.bits_0.lowTemperatureFailureState - - - - 1 = Low temperature failure threshold has been exceeded - - Notes: - In XENPAK mode, F/W will copy this register to the 1.A070.6 register. - - */ - unsigned int lowTemperatureFailureState : 1; /* 1E.C830.D RO */ - /* 1 = Low temperature failure threshold has been exceeded */ - /*! \brief 1E.C830.C RO High Temperature Warning State - AQ_GlobalGeneralStatus_APPIA.u0.bits_0.highTemperatureWarningState - - - - 1 = High temperature warning threshold has been exceeded - - Notes: - In XENPAK mode, F/W will copy this register to the 1.A074.7 register. - - */ - unsigned int highTemperatureWarningState : 1; /* 1E.C830.C RO */ - /* 1 = High temperature warning threshold has been exceeded */ - /*! \brief 1E.C830.B RO Low Temperature Warning State - AQ_GlobalGeneralStatus_APPIA.u0.bits_0.lowTemperatureWarningState - - - - 1 = Low temperature warning threshold has been exceeded - - Notes: - In XENPAK mode, F/W will copy this register to the 1.A074.6 register. - - */ - unsigned int lowTemperatureWarningState : 1; /* 1E.C830.B RO */ - /* 1 = Low temperature warning threshold has been exceeded */ - unsigned int reserved1 : 11; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global General Status */ - union - { - struct - { - /*! \brief 1E.C831.F RO Processor Intensive MDIO Operation In- Progress - AQ_GlobalGeneralStatus_APPIA.u1.bits_1.processorIntensiveMdioOperationIn_Progress - - - - 1 = PHY microprocessor is busy with a processor-intensive MDIO operation - 0 = Processor-intensive MDIO operation completed - - - Notes: - This bit should may be used with certain processor-intensive MDIO commands (such as Loopbacks, Test Modes, Low power modes, Tx-Disable, Restart autoneg, Cable Diagnostics, etc.) that take longer than an MDIO cycle to complete. Upon receiving an MDIO command that involves the PHY's microprocessor, this bit is set, and when the command is completed, this bit is cleared. - - NOTE!!! This bit should be checked only after 1 ms of issuing a processor-intensive MDIO operation. - - The list of operations that set this bit are as follows: - - 1.0.0, PMA Loopback - 1.0.B, Low power mode - 1.9.4:0, Tx Disable - 1.84, 10G Test modes - 1.8000.5, XENPAK Control - 1.9000, XENPAK Rx Fault Enable - 1.9002, XENPAK Alarm Enable - 1.E400.F, External loopback - 3.0.B, Low power mode - 3.0.E, System PCS loopback - 3.C471.5, PRBS Test - 3.C471.6, PRBS Test - 3.E471.5, PRBS Test - 3.E471.6, PRBS Test - 4.0.B, Low power mode - 4.0.E, PHY-XS network loopback - 4.C440, Output clock control, Load SERDES parameters - 4.F802.E, System loopback - 4.C444.F:B, Loopback Control - 4.C444.4:2, Packet generation - 4.C445.C, SERDES calibration - 7.0.9, Restart autonegotiation - 1D.C280, 1G/100M Network loopback - 1D.C500, 1G System loopback - 1D.C501, 1G / 100M Test modes */ - unsigned int processorIntensiveMdioOperationIn_Progress : 1; /* 1E.C831.F RO */ - /* 1 = PHY microprocessor is busy with a processor-intensive MDIO operation - 0 = Processor-intensive MDIO operation completed - */ - unsigned int reserved0 : 15; - } bits_1; - uint16_t word_1; - } u1; -} AQ_GlobalGeneralStatus_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Pin Status: 1E.C840 */ -/* Global Pin Status: 1E.C840 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Pin Status */ - union - { - struct - { - unsigned int reserved0 : 1; - /*! \brief 1E.C840.E:D RO MDIO Boot Load [1:0] - AQ_GlobalPinStatus_APPIA.u0.bits_0.mdioBootLoad - - - - Value of MDIO Boot Load pins - - 0x3 = PHY #0 Slave Daisy Chain Boot - 0x2 = PHY #0 Master Daisy Chain Boot from Flash - 0x1 = MDIO Boot Load - 0x0 = Boot from Flash (PHY #0 only) - - - Notes: - NOTES: - - PHY #0 is the primary PHY, and PHY #1 is the secondary PHY - - PHY #1 is always in Slave Daisy Chain Boot from Flash when set to 0x2 or 0x3. */ - unsigned int mdioBootLoad : 2; /* 1E.C840.E:D RO */ - /* Value of MDIO Boot Load pins - - 0x3 = PHY #0 Slave Daisy Chain Boot - 0x2 = PHY #0 Master Daisy Chain Boot from Flash - 0x1 = MDIO Boot Load - 0x0 = Boot from Flash (PHY #0 only) - */ - unsigned int reserved1 : 3; - /*! \brief 1E.C840.9 RO Package Connectivity - AQ_GlobalPinStatus_APPIA.u0.bits_0.packageConnectivity - - - - Value of the package connection pin - - */ - unsigned int packageConnectivity : 1; /* 1E.C840.9 RO */ - /* Value of the package connection pin - */ - unsigned int reserved2 : 1; - /*! \brief 1E.C840.7 RO Tx Enable - AQ_GlobalPinStatus_APPIA.u0.bits_0.txEnable - - - - Current Value of Tx Enable pin - - - Notes: - 0 = Disable Transmitter */ - unsigned int txEnable : 1; /* 1E.C840.7 RO */ - /* Current Value of Tx Enable pin - */ - unsigned int reserved3 : 1; - /*! \brief 1E.C840.5:0 RO LED Pullup State [5:0] - AQ_GlobalPinStatus_APPIA.u0.bits_0.ledPullupState - - - - 1 = LED output pin is pulled high - 0 = LED output pin is pulled low - - */ - unsigned int ledPullupState : 6; /* 1E.C840.5:0 RO */ - /* 1 = LED output pin is pulled high - 0 = LED output pin is pulled low - */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalPinStatus_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Daisy Chain Status: 1E.C842 */ -/* Global Daisy Chain Status: 1E.C842 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Daisy Chain Status */ - union - { - struct - { - /*! \brief 1E.C842.F:0 RO Rx Daisy Chain Calculated CRC [F:0] - AQ_GlobalDaisyChainStatus_APPIA.u0.bits_0.rxDaisyChainCalculatedCrc - - - - Rx Daisy Chain Calculated CRC - - - Notes: - This is the calculated daisy chain CRC. */ - unsigned int rxDaisyChainCalculatedCrc : 16; /* 1E.C842.F:0 RO */ - /* Rx Daisy Chain Calculated CRC - */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalDaisyChainStatus_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Fault Message: 1E.C850 */ -/* Global Fault Message: 1E.C850 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Fault Message */ - union - { - struct - { - /*! \brief 1E.C850.F:0 RO Message [F:0] - AQ_GlobalFaultMessage_APPIA.u0.bits_0.message - - - - Error code describing fault - - Notes: - Code 0x8001: Firmware not compatible with chip architecture. This fault occurs when firmware compiled for a different Tensilica core is loaded. - Code 0x8002: VCO calibration failed. This occurs when the main PLLs on chip fail to lock: this is not possible to trigger. - Code 0x8003: XAUI calibration failed. This occurs when the XAUI PLLs fail to lock: this is not possible to trigger. - Code 0x8004: Failed to set operating voltages via PMBus. This only occurs when the processor has control over power supply voltage via an attached PMBus device and there is a protocol error on the I2C bus: this is not possible to trigger. - Code 0x8005: Unexpected device ID. This occurs if the device ID programmed into the internal E-Fuse registers in not valid: this is not possible to trigger. - Code 0x8006: Computed checksum does not match expected checksum. This occurs when the FLASH checksum check performed at boot time fails. This only occurs when the system boots from FLASH. - Code 0x8007: Detected a bit error in static memory. To trigger, corrupt one of the static regions. - Code 0xC001: Illegal Instruction exception. This occurs when the processor attempts to execute an illegal instruction. To trigger this, write an illegal instruction to program memory. It's possible that the bit error check will trigger before the illegal instruction is executed. - Code 0xC002 Instruction Fetch Error. Internal physical address or a data error during instruction fetch: this is not possible to trigger. - Code 0xC003 Load Store Error. Internal physical address or data error during load store operation: this is not possible to trigger.. - Code 0xC004 Privileged Instruction. Attempt to execute a privileged operation without sufficient privilege: this is not possible to trigger. - Code 0xC005 Unaligned Load or Store. Attempt to load or store data at an address which cannot be handled due to alignment: this is not possible to trigger. - Code 0xC006 Instruction fetch from prohibited space: this is not possible to trigger. - Code 0xC007 Data load from prohibited space: this is not possible to trigger. - Code 0xC008 Data store into prohibited space: this is not possible to trigger. */ - unsigned int message : 16; /* 1E.C850.F:0 RO */ - /* Error code describing fault */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalFaultMessage_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Primary Status: 1E.C851 */ -/* Global Primary Status: 1E.C851 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Primary Status */ - union - { - struct - { - unsigned int reserved0 : 15; - /*! \brief 1E.C851.0 RO Primary Status - AQ_GlobalPrimaryStatus_APPIA.u0.bits_0.primaryStatus - - - - 1 = PHY is the primary PHY - 0 = PHY is is secondary PHY - - */ - unsigned int primaryStatus : 1; /* 1E.C851.0 RO */ - /* 1 = PHY is the primary PHY - 0 = PHY is is secondary PHY - */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalPrimaryStatus_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Cable Diagnostic Impedance: 1E.C880 */ -/* Global Cable Diagnostic Impedance: 1E.C880 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Cable Diagnostic Impedance */ - union - { - struct - { - /*! \brief 1E.C880.F RO Reserved 1 - AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.reserved_1 - - - - Reserved for future use - - */ - unsigned int reserved_1 : 1; /* 1E.C880.F RO */ - /* Reserved for future use - */ - /*! \brief 1E.C880.E:C RO Pair A Reflection #1 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.pairAReflection_1 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the first worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ - unsigned int pairAReflection_1 : 3; /* 1E.C880.E:C RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C880.B RO Reserved 2 - AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.reserved_2 - - - - Reserved for future use - - */ - unsigned int reserved_2 : 1; /* 1E.C880.B RO */ - /* Reserved for future use - */ - /*! \brief 1E.C880.A:8 RO Pair A Reflection #2 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.pairAReflection_2 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the second worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ - unsigned int pairAReflection_2 : 3; /* 1E.C880.A:8 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C880.7 RO Reserved 3 - AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.reserved_3 - - - - Reserved for future use - - */ - unsigned int reserved_3 : 1; /* 1E.C880.7 RO */ - /* Reserved for future use - */ - /*! \brief 1E.C880.6:4 RO Pair A Reflection #3 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.pairAReflection_3 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the third worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ - unsigned int pairAReflection_3 : 3; /* 1E.C880.6:4 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C880.3 RO Reserved 4 - AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.reserved_4 - - - - Reserved for future use - - */ - unsigned int reserved_4 : 1; /* 1E.C880.3 RO */ - /* Reserved for future use - */ - /*! \brief 1E.C880.2:0 RO Pair A Reflection #4 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.pairAReflection_4 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the fourth worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ - unsigned int pairAReflection_4 : 3; /* 1E.C880.2:0 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Cable Diagnostic Impedance */ - union - { - struct - { - /*! \brief 1E.C881.F RO Reserved 5 - AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.reserved_5 - - - - Reserved for future use - - */ - unsigned int reserved_5 : 1; /* 1E.C881.F RO */ - /* Reserved for future use - */ - /*! \brief 1E.C881.E:C RO Pair B Reflection #1 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.pairBReflection_1 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the first worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ - unsigned int pairBReflection_1 : 3; /* 1E.C881.E:C RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C881.B RO Reserved 6 - AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.reserved_6 - - - - Reserved for future use - - */ - unsigned int reserved_6 : 1; /* 1E.C881.B RO */ - /* Reserved for future use - */ - /*! \brief 1E.C881.A:8 RO Pair B Reflection #2 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.pairBReflection_2 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the second worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ - unsigned int pairBReflection_2 : 3; /* 1E.C881.A:8 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C881.7 RO Reserved 7 - AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.reserved_7 - - - - Reserved for future use - - */ - unsigned int reserved_7 : 1; /* 1E.C881.7 RO */ - /* Reserved for future use - */ - /*! \brief 1E.C881.6:4 RO Pair B Reflection #3 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.pairBReflection_3 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the third worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ - unsigned int pairBReflection_3 : 3; /* 1E.C881.6:4 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C881.3 RO Reserved 8 - AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.reserved_8 - - - - Reserved for future use - - */ - unsigned int reserved_8 : 1; /* 1E.C881.3 RO */ - /* Reserved for future use - */ - /*! \brief 1E.C881.2:0 RO Pair B Reflection #4 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.pairBReflection_4 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the fourth worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ - unsigned int pairBReflection_4 : 3; /* 1E.C881.2:0 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global Cable Diagnostic Impedance */ - union - { - struct - { - /*! \brief 1E.C882.F RO Reserved 9 - AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.reserved_9 - - - - Reserved for future use - - */ - unsigned int reserved_9 : 1; /* 1E.C882.F RO */ - /* Reserved for future use - */ - /*! \brief 1E.C882.E:C RO Pair C Reflection #1 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.pairCReflection_1 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the first worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ - unsigned int pairCReflection_1 : 3; /* 1E.C882.E:C RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C882.B RO Reserved 10 - AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.reserved_10 - - - - Reserved for future use - - */ - unsigned int reserved_10 : 1; /* 1E.C882.B RO */ - /* Reserved for future use - */ - /*! \brief 1E.C882.A:8 RO Pair C Reflection #2 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.pairCReflection_2 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the second worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ - unsigned int pairCReflection_2 : 3; /* 1E.C882.A:8 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C882.7 RO Reserved 11 - AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.reserved_11 - - - - Reserved for future use - - */ - unsigned int reserved_11 : 1; /* 1E.C882.7 RO */ - /* Reserved for future use - */ - /*! \brief 1E.C882.6:4 RO Pair C Reflection #3 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.pairCReflection_3 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the third worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ - unsigned int pairCReflection_3 : 3; /* 1E.C882.6:4 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C882.3 RO Reserved 12 - AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.reserved_12 - - - - Reserved for future use - - */ - unsigned int reserved_12 : 1; /* 1E.C882.3 RO */ - /* Reserved for future use - */ - /*! \brief 1E.C882.2:0 RO Pair C Reflection #4 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.pairCReflection_4 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the fourth worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ - unsigned int pairCReflection_4 : 3; /* 1E.C882.2:0 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global Cable Diagnostic Impedance */ - union - { - struct - { - /*! \brief 1E.C883.F RO Reserved 13 - AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.reserved_13 - - - - Reserved for future use - - */ - unsigned int reserved_13 : 1; /* 1E.C883.F RO */ - /* Reserved for future use - */ - /*! \brief 1E.C883.E:C RO Pair D Reflection #1 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.pairDReflection_1 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the first worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ - unsigned int pairDReflection_1 : 3; /* 1E.C883.E:C RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C883.B RO Reserved 14 - AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.reserved_14 - - - - Reserved for future use - - */ - unsigned int reserved_14 : 1; /* 1E.C883.B RO */ - /* Reserved for future use - */ - /*! \brief 1E.C883.A:8 RO Pair D Reflection #2 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.pairDReflection_2 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the second worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ - unsigned int pairDReflection_2 : 3; /* 1E.C883.A:8 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C883.7 RO Reserved 15 - AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.reserved_15 - - - - Reserved for future use - - */ - unsigned int reserved_15 : 1; /* 1E.C883.7 RO */ - /* Reserved for future use - */ - /*! \brief 1E.C883.6:4 RO Pair D Reflection #3 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.pairDReflection_3 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the third worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ - unsigned int pairDReflection_3 : 3; /* 1E.C883.6:4 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C883.3 RO Reserved 16 - AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.reserved_16 - - - - Reserved for future use - - */ - unsigned int reserved_16 : 1; /* 1E.C883.3 RO */ - /* Reserved for future use - */ - /*! \brief 1E.C883.2:0 RO Pair D Reflection #4 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.pairDReflection_4 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the fourth worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ - unsigned int pairDReflection_4 : 3; /* 1E.C883.2:0 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - } bits_3; - uint16_t word_3; - } u3; -} AQ_GlobalCableDiagnosticImpedance_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Status: 1E.C884 */ -/* Global Status: 1E.C884 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Status */ - union - { - struct - { - /*! \brief 1E.C884.F:8 RO Reserved Status 0 [7:0] - AQ_GlobalStatus_APPIA.u0.bits_0.reservedStatus_0 - - - - Reserved for future use - - */ - unsigned int reservedStatus_0 : 8; /* 1E.C884.F:8 RO */ - /* Reserved for future use - */ - /*! \brief 1E.C884.7:0 RO Cable Length [7:0] - AQ_GlobalStatus_APPIA.u0.bits_0.cableLength - - - - The estimated length of the cable in meters - - - Notes: - The length of the cable shown here is estimated from the cable diagnostic engine and should be accurate to +/-1m. */ - unsigned int cableLength : 8; /* 1E.C884.7:0 RO */ - /* The estimated length of the cable in meters - */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalStatus_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Reserved Status: 1E.C885 */ -/* Global Reserved Status: 1E.C885 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Reserved Status */ - union - { - struct - { - /*! \brief 1E.C885.F:A RO Nearly Seconds MSW[5:0] - AQ_GlobalReservedStatus_APPIA.u0.bits_0.nearlySecondsMSW - - - - Bits 16 to 21 of the 22 bit "Nearly Seconds" uptime counter. - - - Notes: - The "Nearly Seconds" counter is incremented every 1024 milliseconds. */ - unsigned int nearlySecondsMSW : 6; /* 1E.C885.F:A RO */ - /* Bits 16 to 21 of the 22 bit "Nearly Seconds" uptime counter. - */ - /*! \brief 1E.C885.9:8 ROSPD XENPAK NVR Status [1:0] - AQ_GlobalReservedStatus_APPIA.u0.bits_0.xenpakNvrStatus - - Provisionable Default = 0x0 - - Status of XENPAK NVR: - 0: NVR not enabled - 1: Last NVR operation succeeded - 2: Last NVR operation failed - 3: Reserved - - - Notes: - XENPAK register space is mirrored in NVR (SPI ROM). This register indicates the status of the last NVR operation. */ - unsigned int xenpakNvrStatus : 2; /* 1E.C885.9:8 ROSPD Provisionable Default = 0x0 */ - /* Status of XENPAK NVR: - 0: NVR not enabled - 1: Last NVR operation succeeded - 2: Last NVR operation failed - 3: Reserved - */ - /*! \brief 1E.C885.7:0 ROSPD ROM Revision [7:0] - AQ_GlobalReservedStatus_APPIA.u0.bits_0.romRevision - - Provisionable Default = 0x00 - - ROM Revision Number - - - Notes: - Customers may receive multiple ROM images that differ only in their provisioning. This field is used to differentiate those images. This field is used in conjunction with the firmware major and minor revision numbers to uniquely identify ROM images. */ - unsigned int romRevision : 8; /* 1E.C885.7:0 ROSPD Provisionable Default = 0x00 */ - /* ROM Revision Number - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Reserved Status */ - union - { - struct - { - /*! \brief 1E.C886.F:0 RO Nearly Seconds LSW[F:0] - AQ_GlobalReservedStatus_APPIA.u1.bits_1.nearlySecondsLSW - - - - Bits 0 to 15 of the 22 bit "Nearly Seconds" uptime counter. - - - Notes: - The "Nearly Seconds" counter is incremented every 1024 milliseconds. */ - unsigned int nearlySecondsLSW : 16; /* 1E.C886.F:0 RO */ - /* Bits 0 to 15 of the 22 bit "Nearly Seconds" uptime counter. - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_GlobalReservedStatus_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Alarms: 1E.CC00 */ -/* Global Alarms: 1E.CC00 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Alarms */ - union - { - struct - { - unsigned int reserved0 : 1; - /*! \brief 1E.CC00.E LH High Temperature Failure - AQ_GlobalAlarms_APPIA.u0.bits_0.highTemperatureFailure - - - - 1 = High temperature failure threshold has been exceeded - - - Notes: - - - - - These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ - unsigned int highTemperatureFailure : 1; /* 1E.CC00.E LH */ - /* 1 = High temperature failure threshold has been exceeded - */ - /*! \brief 1E.CC00.D LH Low Temperature Failure - AQ_GlobalAlarms_APPIA.u0.bits_0.lowTemperatureFailure - - - - 1 = Low temperature failure threshold has been exceeded - - - Notes: - - - - - These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ - unsigned int lowTemperatureFailure : 1; /* 1E.CC00.D LH */ - /* 1 = Low temperature failure threshold has been exceeded - */ - /*! \brief 1E.CC00.C LH High Temperature Warning - AQ_GlobalAlarms_APPIA.u0.bits_0.highTemperatureWarning - - - - 1 = High temperature warning threshold has been exceeded - - - Notes: - - - - - These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ - unsigned int highTemperatureWarning : 1; /* 1E.CC00.C LH */ - /* 1 = High temperature warning threshold has been exceeded - */ - /*! \brief 1E.CC00.B LH Low Temperature Warning - AQ_GlobalAlarms_APPIA.u0.bits_0.lowTemperatureWarning - - - - 1 = Low temperature warning threshold has been exceeded - - - Notes: - - - - - These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ - unsigned int lowTemperatureWarning : 1; /* 1E.CC00.B LH */ - /* 1 = Low temperature warning threshold has been exceeded - */ - unsigned int reserved1 : 4; - /*! \brief 1E.CC00.6 LH Reset completed - AQ_GlobalAlarms_APPIA.u0.bits_0.resetCompleted - - - - 1 = Chip wide reset completed - - Notes: - This bit is set by the microprocessor when it has completed it's initialization sequence. This bit is mirrored in 1.CC02.0 */ - unsigned int resetCompleted : 1; /* 1E.CC00.6 LH */ - /* 1 = Chip wide reset completed */ - unsigned int reserved2 : 1; - /*! \brief 1E.CC00.4 LH Device Fault - AQ_GlobalAlarms_APPIA.u0.bits_0.deviceFault - - - - 1 = Fault - - Notes: - When set, a fault has been detected by the uP and the associated 16 bit error code is visible in See Global Configuration Fault Message: Address 1E.C850 */ - unsigned int deviceFault : 1; /* 1E.CC00.4 LH */ - /* 1 = Fault */ - /*! \brief 1E.CC00.3 LH Reserved Alarm A - AQ_GlobalAlarms_APPIA.u0.bits_0.reservedAlarmA - - - - Reserved for future use - - */ - unsigned int reservedAlarmA : 1; /* 1E.CC00.3 LH */ - /* Reserved for future use - */ - /*! \brief 1E.CC00.2 LH Reserved Alarm B - AQ_GlobalAlarms_APPIA.u0.bits_0.reservedAlarmB - - - - Reserved for future use - - */ - unsigned int reservedAlarmB : 1; /* 1E.CC00.2 LH */ - /* Reserved for future use - */ - /*! \brief 1E.CC00.1 LH Reserved Alarm C - AQ_GlobalAlarms_APPIA.u0.bits_0.reservedAlarmC - - - - Reserved for future use - - */ - unsigned int reservedAlarmC : 1; /* 1E.CC00.1 LH */ - /* Reserved for future use - */ - /*! \brief 1E.CC00.0 LH Reserved Alarm D - AQ_GlobalAlarms_APPIA.u0.bits_0.reservedAlarmD - - - - Reserved for future use - - */ - unsigned int reservedAlarmD : 1; /* 1E.CC00.0 LH */ - /* Reserved for future use - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Alarms */ - union - { - struct - { - unsigned int reserved0 : 1; - /*! \brief 1E.CC01.E LH Smart Power-Down Entered - AQ_GlobalAlarms_APPIA.u1.bits_1.smartPower_downEntered - - - - 1 = Smart Power-Down State Entered - - - Notes: - When this bit is set, it indicates that the Smart Power-Down state was entered */ - unsigned int smartPower_downEntered : 1; /* 1E.CC01.E LH */ - /* 1 = Smart Power-Down State Entered - */ - /*! \brief 1E.CC01.D RO XENPAK Alarm - AQ_GlobalAlarms_APPIA.u1.bits_1.xenpakAlarm - - - - 1 = XENPAK Alarm - - - Notes: - This alarm is performed by H/W. */ - unsigned int xenpakAlarm : 1; /* 1E.CC01.D RO */ - /* 1 = XENPAK Alarm - */ - /*! \brief 1E.CC01.C:8 LH Reserved Alarms [4:0] - AQ_GlobalAlarms_APPIA.u1.bits_1.reservedAlarms - - - - Reserved for future use - - */ - unsigned int reservedAlarms : 5; /* 1E.CC01.C:8 LH */ - /* Reserved for future use - */ - /*! \brief 1E.CC01.7 LH MDIO Command Handling Overflow - AQ_GlobalAlarms_APPIA.u1.bits_1.mdioCommandHandlingOverflow - - - - 1 = PHY was issued more MDIO requests than it could service in it's request buffer - - - Notes: - Assertion of this bit means that more MDIO commands were issued than FW could handle. */ - unsigned int mdioCommandHandlingOverflow : 1; /* 1E.CC01.7 LH */ - /* 1 = PHY was issued more MDIO requests than it could service in it's request buffer - */ - unsigned int reserved1 : 6; - /*! \brief 1E.CC01.0 LH Diagnostic Alarm - AQ_GlobalAlarms_APPIA.u1.bits_1.diagnosticAlarm - - - - 1 = Alarm triggered by a write to 1E.C470.7 - - - Notes: - A diagnostic alarm use to test system alarm circuitry */ - unsigned int diagnosticAlarm : 1; /* 1E.CC01.0 LH */ - /* 1 = Alarm triggered by a write to 1E.C470.7 - */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global Alarms */ - union - { - struct - { - /*! \brief 1E.CC02.F LH NVR Operation Complete - AQ_GlobalAlarms_APPIA.u2.bits_2.nvrOperationComplete - - - - 1 = NVR operation is complete - - - Notes: - NVR interface is ready interrupt for registers See Global NVR Interface 1: Address 1E.100 - See Global NVR Provisioning Data MSW - Address 1E.17 . */ - unsigned int nvrOperationComplete : 1; /* 1E.CC02.F LH */ - /* 1 = NVR operation is complete - */ - /*! \brief 1E.CC02.E LH Mailbox Operation: Complete - AQ_GlobalAlarms_APPIA.u2.bits_2.mailboxOperation_Complete - - - - 1 = Mailbox operation is complete - - - Notes: - Mailbox interface is ready interrupt for registers See Global Vendor Specific Control - Address 1E.C000 - See Global Vendor Specific Provisioning 5 - Address 1E.C404 */ - unsigned int mailboxOperation_Complete : 1; /* 1E.CC02.E LH */ - /* 1 = Mailbox operation is complete - */ - unsigned int reserved0 : 3; - /*! \brief 1E.CC02.A LH uP DRAM Parity Error - AQ_GlobalAlarms_APPIA.u2.bits_2.upDramParityError - - - - 1 = Parity error detected in the uP DRAM - - */ - unsigned int upDramParityError : 1; /* 1E.CC02.A LH */ - /* 1 = Parity error detected in the uP DRAM - */ - /*! \brief 1E.CC02.9:8 LH uP IRAM Parity Error [1:0] - AQ_GlobalAlarms_APPIA.u2.bits_2.upIramParityError - - - - 1 = Parity error detected in the uP IRAM - - - Notes: - Bit 0 indicates a parity error was detected in the uP IRAM but was corrected. - Bit 1 indicates a multiple parity errors were detected in the uP IRAM and could not be corrected. - The uP IRAM is protected with ECC. */ - unsigned int upIramParityError : 2; /* 1E.CC02.9:8 LH */ - /* 1 = Parity error detected in the uP IRAM - */ - unsigned int reserved1 : 2; - /*! \brief 1E.CC02.5 LRF Tx Enable State Change - AQ_GlobalAlarms_APPIA.u2.bits_2.txEnableStateChange - - - - 1 = TX_EN pin has changed state - - */ - unsigned int txEnableStateChange : 1; /* 1E.CC02.5 LRF */ - /* 1 = TX_EN pin has changed state - */ - unsigned int reserved2 : 2; - /*! \brief 1E.CC02.2 LH MDIO MMD Error - AQ_GlobalAlarms_APPIA.u2.bits_2.mdioMMD_Error - - - - 1 = Invalid MMD address detected - - */ - unsigned int mdioMMD_Error : 1; /* 1E.CC02.2 LH */ - /* 1 = Invalid MMD address detected - */ - /*! \brief 1E.CC02.1 LH MDIO Timeout Error - AQ_GlobalAlarms_APPIA.u2.bits_2.mdioTimeoutError - - - - 1 = MDIO timeout detected - - */ - unsigned int mdioTimeoutError : 1; /* 1E.CC02.1 LH */ - /* 1 = MDIO timeout detected - */ - /*! \brief 1E.CC02.0 LH Watchdog Timer Alarm - AQ_GlobalAlarms_APPIA.u2.bits_2.watchdogTimerAlarm - - - - 1 = Watchdog timer alarm - - */ - unsigned int watchdogTimerAlarm : 1; /* 1E.CC02.0 LH */ - /* 1 = Watchdog timer alarm - */ - } bits_2; - uint16_t word_2; - } u2; -} AQ_GlobalAlarms_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Interrupt Mask: 1E.D400 */ -/* Global Interrupt Mask: 1E.D400 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Interrupt Mask */ - union - { - struct - { - unsigned int reserved0 : 1; - /*! \brief 1E.D400.E R/WPD High Temperature Failure Mask - AQ_GlobalInterruptMask_APPIA.u0.bits_0.highTemperatureFailureMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int highTemperatureFailureMask : 1; /* 1E.D400.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.D400.D R/WPD Low Temperature Failure Mask - AQ_GlobalInterruptMask_APPIA.u0.bits_0.lowTemperatureFailureMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int lowTemperatureFailureMask : 1; /* 1E.D400.D R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.D400.C R/WPD High Temperature Warning Mask - AQ_GlobalInterruptMask_APPIA.u0.bits_0.highTemperatureWarningMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int highTemperatureWarningMask : 1; /* 1E.D400.C R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.D400.B R/WPD Low Temperature Warning Mask - AQ_GlobalInterruptMask_APPIA.u0.bits_0.lowTemperatureWarningMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int lowTemperatureWarningMask : 1; /* 1E.D400.B R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - unsigned int reserved1 : 4; - /*! \brief 1E.D400.6 R/WPD Reset completed Mask - AQ_GlobalInterruptMask_APPIA.u0.bits_0.resetCompletedMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int resetCompletedMask : 1; /* 1E.D400.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - unsigned int reserved2 : 1; - /*! \brief 1E.D400.4 R/WPD Device Fault Mask - AQ_GlobalInterruptMask_APPIA.u0.bits_0.deviceFaultMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int deviceFaultMask : 1; /* 1E.D400.4 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.D400.3 R/WPD Reserved Alarm A Mask - AQ_GlobalInterruptMask_APPIA.u0.bits_0.reservedAlarmAMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int reservedAlarmAMask : 1; /* 1E.D400.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - /*! \brief 1E.D400.2 R/WPD Reserved Alarm B Mask - AQ_GlobalInterruptMask_APPIA.u0.bits_0.reservedAlarmBMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int reservedAlarmBMask : 1; /* 1E.D400.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - /*! \brief 1E.D400.1 R/WPD Reserved Alarm C Mask - AQ_GlobalInterruptMask_APPIA.u0.bits_0.reservedAlarmCMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int reservedAlarmCMask : 1; /* 1E.D400.1 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - /*! \brief 1E.D400.0 R/WPD Reserved Alarm D Mask - AQ_GlobalInterruptMask_APPIA.u0.bits_0.reservedAlarmDMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int reservedAlarmDMask : 1; /* 1E.D400.0 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Interrupt Mask */ - union - { - struct - { - unsigned int reserved0 : 1; - /*! \brief 1E.D401.E R/WPD Smart Power-Down Entered Mask - AQ_GlobalInterruptMask_APPIA.u1.bits_1.smartPower_downEnteredMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int smartPower_downEnteredMask : 1; /* 1E.D401.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - /*! \brief 1E.D401.D R/WPD XENPAK Alarm Mask - AQ_GlobalInterruptMask_APPIA.u1.bits_1.xenpakAlarmMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int xenpakAlarmMask : 1; /* 1E.D401.D R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.D401.C:8 R/WPD Reserved Alarms Mask [4:0] - AQ_GlobalInterruptMask_APPIA.u1.bits_1.reservedAlarmsMask - - Provisionable Default = 0x00 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int reservedAlarmsMask : 5; /* 1E.D401.C:8 R/WPD Provisionable Default = 0x00 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - /*! \brief 1E.D401.7 R/WPD MDIO Command Handling Overflow Mask - AQ_GlobalInterruptMask_APPIA.u1.bits_1.mdioCommandHandlingOverflowMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int mdioCommandHandlingOverflowMask : 1; /* 1E.D401.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int reserved1 : 6; - /*! \brief 1E.D401.0 R/WPD Diagnostic Alarm Mask - AQ_GlobalInterruptMask_APPIA.u1.bits_1.diagnosticAlarmMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int diagnosticAlarmMask : 1; /* 1E.D401.0 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global Interrupt Mask */ - union - { - struct - { - /*! \brief 1E.D402.F R/WPD NVR Operation Complete Mask - AQ_GlobalInterruptMask_APPIA.u2.bits_2.nvrOperationCompleteMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - Notes: - NVR interface is ready interrupt for registers See Global NVR Interface 1: Address 1E.100 - See Global NVR Provisioning Data MSW - Address 1E.17 */ - unsigned int nvrOperationCompleteMask : 1; /* 1E.D402.F R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.D402.E R/WPD Mailbox Operation Complete Mask - AQ_GlobalInterruptMask_APPIA.u2.bits_2.mailboxOperationCompleteMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - Notes: - Mailbox interface is ready interrupt for registers See Global Vendor Specific Control - Address 1E.C000 - See Global Vendor Specific Provisioning 5 - Address 1E.C404 */ - unsigned int mailboxOperationCompleteMask : 1; /* 1E.D402.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - unsigned int reserved0 : 3; - /*! \brief 1E.D402.A R/WPD uP DRAM Parity Error Mask - AQ_GlobalInterruptMask_APPIA.u2.bits_2.upDramParityErrorMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int upDramParityErrorMask : 1; /* 1E.D402.A R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - /*! \brief 1E.D402.9:8 R/WPD uP IRAM Parity Error Mask [1:0] - AQ_GlobalInterruptMask_APPIA.u2.bits_2.upIramParityErrorMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int upIramParityErrorMask : 2; /* 1E.D402.9:8 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int reserved1 : 2; - /*! \brief 1E.D402.5 R/WPD Tx Enable State Change Mask - AQ_GlobalInterruptMask_APPIA.u2.bits_2.txEnableStateChangeMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int txEnableStateChangeMask : 1; /* 1E.D402.5 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - unsigned int reserved2 : 2; - /*! \brief 1E.D402.2 R/WPD MDIO MMD Error Mask - AQ_GlobalInterruptMask_APPIA.u2.bits_2.mdioMMD_ErrorMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int mdioMMD_ErrorMask : 1; /* 1E.D402.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.D402.1 R/WPD MDIO Timeout Error Mask - AQ_GlobalInterruptMask_APPIA.u2.bits_2.mdioTimeoutErrorMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int mdioTimeoutErrorMask : 1; /* 1E.D402.1 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.D402.0 R/WPD Watchdog Timer Alarm Mask - AQ_GlobalInterruptMask_APPIA.u2.bits_2.watchdogTimerAlarmMask - - Provisionable Default = 0x1 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int watchdogTimerAlarmMask : 1; /* 1E.D402.0 R/WPD Provisionable Default = 0x1 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - } bits_2; - uint16_t word_2; - } u2; -} AQ_GlobalInterruptMask_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Chip-Wide Standard Interrupt Flags: 1E.FC00 */ -/* Global Chip-Wide Standard Interrupt Flags: 1E.FC00 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Chip-Wide Standard Interrupt Flags */ - union - { - struct - { - /*! \brief 1E.FC00.F RO PMA Standard Alarm 1 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.pmaStandardAlarm_1Interrupt - - - - 1 = Interrupt in PMA standard alarms 1 - - - Notes: - An interrupt was generated from bit 1.1.2. - An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ - unsigned int pmaStandardAlarm_1Interrupt : 1; /* 1E.FC00.F RO */ - /* 1 = Interrupt in PMA standard alarms 1 - */ - /*! \brief 1E.FC00.E RO PMA Standard Alarm 2 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.pmaStandardAlarm_2Interrupt - - - - 1 = Interrupt in PMA standard alarms 2 - - - Notes: - An interrupt was generated from either bit 1.8.B or 1.8.A. - An interrupt was generated from status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ - unsigned int pmaStandardAlarm_2Interrupt : 1; /* 1E.FC00.E RO */ - /* 1 = Interrupt in PMA standard alarms 2 - */ - /*! \brief 1E.FC00.D RO PCS Standard Alarm 1 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.pcsStandardAlarm_1Interrupt - - - - 1 = Interrupt in PCS standard alarms 1 - - - Notes: - An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ - unsigned int pcsStandardAlarm_1Interrupt : 1; /* 1E.FC00.D RO */ - /* 1 = Interrupt in PCS standard alarms 1 - */ - /*! \brief 1E.FC00.C RO PCS Standard Alarm 2 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.pcsStandardAlarm_2Interrupt - - - - 1 = Interrupt in PCS standard alarms 2 - - - Notes: - An interrupt was generated from status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ - unsigned int pcsStandardAlarm_2Interrupt : 1; /* 1E.FC00.C RO */ - /* 1 = Interrupt in PCS standard alarms 2 - */ - /*! \brief 1E.FC00.B RO PCS Standard Alarm 3 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.pcsStandardAlarm_3Interrupt - - - - 1 = Interrupt in PCS standard alarms 3 - - - Notes: - An interrupt was generated from status register ( See PCS 10GBASE-T Status 2 - Address 3.21 ) and the corresponding mask register. ( See PCS Standard Interrupt Mask 1 - Address 3.E021 ) */ - unsigned int pcsStandardAlarm_3Interrupt : 1; /* 1E.FC00.B RO */ - /* 1 = Interrupt in PCS standard alarms 3 - */ - /*! \brief 1E.FC00.A RO PHY XS Standard Alarms 1 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.phyXS_StandardAlarms_1Interrupt - - - - 1 = Interrupt in PHY XS standard alarms 1 - - - Notes: - An interrupt was generated from the status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ - unsigned int phyXS_StandardAlarms_1Interrupt : 1; /* 1E.FC00.A RO */ - /* 1 = Interrupt in PHY XS standard alarms 1 - */ - /*! \brief 1E.FC00.9 RO PHY XS Standard Alarms 2 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.phyXS_StandardAlarms_2Interrupt - - - - 1 = Interrupt in PHY XS standard alarms 2 - - - Notes: - An interrupt was generated from the status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ - unsigned int phyXS_StandardAlarms_2Interrupt : 1; /* 1E.FC00.9 RO */ - /* 1 = Interrupt in PHY XS standard alarms 2 - */ - /*! \brief 1E.FC00.8 RO Autonegotiation Standard Alarms 1 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.autonegotiationStandardAlarms_1Interrupt - - - - 1 = Interrupt in Autonegotiation standard alarms 1 - - - Notes: - An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See Autonegotiation Standard LASI Interrupt Mask 1: Address 7.D000 ) */ - unsigned int autonegotiationStandardAlarms_1Interrupt : 1; /* 1E.FC00.8 RO */ - /* 1 = Interrupt in Autonegotiation standard alarms 1 - */ - /*! \brief 1E.FC00.7 RO Autonegotiation Standard Alarms 2 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.autonegotiationStandardAlarms_2Interrupt - - - - 1 = Interrupt in Autonegotiation standard alarms 2 - - - Notes: - An interrupt was generated from status register ( See Autonegotiation 10GBASE-T Status Register - Address 7.21 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ - unsigned int autonegotiationStandardAlarms_2Interrupt : 1; /* 1E.FC00.7 RO */ - /* 1 = Interrupt in Autonegotiation standard alarms 2 - */ - /*! \brief 1E.FC00.6 RO GbE Standard Alarms Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.gbeStandardAlarmsInterrupt - - - - 1 = Interrupt in GbE standard alarms - - - Notes: - An interrupt was generated from the TGE core. */ - unsigned int gbeStandardAlarmsInterrupt : 1; /* 1E.FC00.6 RO */ - /* 1 = Interrupt in GbE standard alarms - */ - unsigned int reserved0 : 5; - /*! \brief 1E.FC00.0 RO All Vendor Alarms Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.allVendorAlarmsInterrupt - - - - 1 = Interrupt in all vendor alarms - - - Notes: - An interrupt was generated from status register ( See Global Chip-Wide LASI Vendor Interrupt Flags: Address 1E.FC01 ) and the corresponding mask register. ( See Global Interrupt LASI Mask: Address 1E.FF01 ) */ - unsigned int allVendorAlarmsInterrupt : 1; /* 1E.FC00.0 RO */ - /* 1 = Interrupt in all vendor alarms - */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalChip_wideStandardInterruptFlags_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Chip-Wide Vendor Interrupt Flags: 1E.FC01 */ -/* Global Chip-Wide Vendor Interrupt Flags: 1E.FC01 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Chip-Wide Vendor Interrupt Flags */ - union - { - struct - { - /*! \brief 1E.FC01.F RO PMA Vendor Alarm Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.pmaVendorAlarmInterrupt - - - - 1 = Interrupt in PMA vendor specific alarm - - - Notes: - A PMA alarm was generated. ( See PHY XS Vendor Global Interrupt Flags 1- Address 4.F800 ) */ - unsigned int pmaVendorAlarmInterrupt : 1; /* 1E.FC01.F RO */ - /* 1 = Interrupt in PMA vendor specific alarm - */ - /*! \brief 1E.FC01.E RO PCS Vendor Alarm Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.pcsVendorAlarmInterrupt - - - - 1 = Interrupt in PCS vendor specific alarm - - - Notes: - A PCS alarm was generated. ( See PHY XS Vendor Global Interrupt Flags 1- Address 4.F800 ) */ - unsigned int pcsVendorAlarmInterrupt : 1; /* 1E.FC01.E RO */ - /* 1 = Interrupt in PCS vendor specific alarm - */ - /*! \brief 1E.FC01.D RO PHY XS Vendor Alarm Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.phyXS_VendorAlarmInterrupt - - - - 1 = Interrupt in PHY XS vendor specific alarm - - - Notes: - A PHY XS alarm was generated. ( See PHY XS Vendor Global LASI Interrupt Flags 1: Address 4.FC00 ) */ - unsigned int phyXS_VendorAlarmInterrupt : 1; /* 1E.FC01.D RO */ - /* 1 = Interrupt in PHY XS vendor specific alarm - */ - /*! \brief 1E.FC01.C RO Autonegotiation Vendor Alarm Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.autonegotiationVendorAlarmInterrupt - - - - 1 = Interrupt in Autonegotiation vendor specific alarm - - - Notes: - An Autonegotiation alarm was generated. ( See Autonegotiation Vendor Global LASI Interrupt Flags 1: Address 7.FC00 ) */ - unsigned int autonegotiationVendorAlarmInterrupt : 1; /* 1E.FC01.C RO */ - /* 1 = Interrupt in Autonegotiation vendor specific alarm - */ - /*! \brief 1E.FC01.B RO GbE Vendor Alarm Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.gbeVendorAlarmInterrupt - - - - 1 = Interrupt in GbE vendor specific alarm - - - Notes: - A GbE alarm was generated. ( See GbE PHY Vendor Global LASI Interrupt Flags 1: Address 1D.FC00 ) */ - unsigned int gbeVendorAlarmInterrupt : 1; /* 1E.FC01.B RO */ - /* 1 = Interrupt in GbE vendor specific alarm - */ - unsigned int reserved0 : 8; - /*! \brief 1E.FC01.2 RO Global Alarms 1 Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.globalAlarms_1Interrupt - - - - 1 = Interrupt in Global alarms 1 - - - Notes: - An interrupt was generated from status register ( See Global Vendor Alarms 1 - Address 1E.CC00 ) and the corresponding mask register. ( See Global Vendor Interrupt Mask - Address 1E.D400 ) */ - unsigned int globalAlarms_1Interrupt : 1; /* 1E.FC01.2 RO */ - /* 1 = Interrupt in Global alarms 1 - */ - /*! \brief 1E.FC01.1 RO Global Alarms 2 Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.globalAlarms_2Interrupt - - - - 1 = Interrupt in Global alarms 2 - - - Notes: - An interrupt was generated from status register ( See Global Alarms 2: Address 1E.CC01 ) and the corresponding mask register. ( See Global LASI Interrupt Mask 2: Address 1E.D401 ) */ - unsigned int globalAlarms_2Interrupt : 1; /* 1E.FC01.1 RO */ - /* 1 = Interrupt in Global alarms 2 - */ - /*! \brief 1E.FC01.0 RO Global Alarms 3 Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.globalAlarms_3Interrupt - - - - 1 = Interrupt in Global alarms 3 - - - Notes: - An interrupt was generated from status register ( See Global Vendor Alarms 2: Address 1E.CC01 ) and the corresponding mask register. ( See Global LASI Interrupt Mask 2: Address 1E.D401 ) */ - unsigned int globalAlarms_3Interrupt : 1; /* 1E.FC01.0 RO */ - /* 1 = Interrupt in Global alarms 3 - */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalChip_wideVendorInterruptFlags_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Interrupt Chip-Wide Standard Mask: 1E.FF00 */ -/* Global Interrupt Chip-Wide Standard Mask: 1E.FF00 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Interrupt Chip-Wide Standard Mask */ - union - { - struct - { - /*! \brief 1E.FF00.F R/WPD PMA Standard Alarm 1 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.pmaStandardAlarm_1InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int pmaStandardAlarm_1InterruptMask : 1; /* 1E.FF00.F R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.E R/WPD PMA Standard Alarm 2 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.pmaStandardAlarm_2InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int pmaStandardAlarm_2InterruptMask : 1; /* 1E.FF00.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.D R/WPD PCS Standard Alarm 1 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.pcsStandardAlarm_1InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int pcsStandardAlarm_1InterruptMask : 1; /* 1E.FF00.D R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.C R/WPD PCS Standard Alarm 2 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.pcsStandardAlarm_2InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int pcsStandardAlarm_2InterruptMask : 1; /* 1E.FF00.C R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.B R/WPD PCS Standard Alarm 3 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.pcsStandardAlarm_3InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int pcsStandardAlarm_3InterruptMask : 1; /* 1E.FF00.B R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.A R/WPD PHY XS Standard Alarms 1 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.phyXS_StandardAlarms_1InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int phyXS_StandardAlarms_1InterruptMask : 1; /* 1E.FF00.A R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.9 R/WPD PHY XS Standard Alarms 2 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.phyXS_StandardAlarms_2InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int phyXS_StandardAlarms_2InterruptMask : 1; /* 1E.FF00.9 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.8 R/WPD Autonegotiation Standard Alarms 1 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.autonegotiationStandardAlarms_1InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int autonegotiationStandardAlarms_1InterruptMask : 1; /* 1E.FF00.8 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.7 R/WPD Autonegotiation Standard Alarms 2 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.autonegotiationStandardAlarms_2InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int autonegotiationStandardAlarms_2InterruptMask : 1; /* 1E.FF00.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.6 R/WPD Gbe Standard Alarms Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.gbeStandardAlarmsInterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int gbeStandardAlarmsInterruptMask : 1; /* 1E.FF00.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - unsigned int reserved0 : 5; - /*! \brief 1E.FF00.0 R/WPD All Vendor Alarms Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.allVendorAlarmsInterruptMask - - Provisionable Default = 0x1 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int allVendorAlarmsInterruptMask : 1; /* 1E.FF00.0 R/WPD Provisionable Default = 0x1 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalInterruptChip_wideStandardMask_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Interrupt Chip-Wide Vendor Mask: 1E.FF01 */ -/* Global Interrupt Chip-Wide Vendor Mask: 1E.FF01 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Interrupt Chip-Wide Vendor Mask */ - union - { - struct - { - /*! \brief 1E.FF01.F R/WPD PMA Vendor Alarm Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.pmaVendorAlarmInterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int pmaVendorAlarmInterruptMask : 1; /* 1E.FF01.F R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF01.E R/WPD PCS Vendor Alarm Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.pcsVendorAlarmInterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int pcsVendorAlarmInterruptMask : 1; /* 1E.FF01.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF01.D R/WPD PHY XS Vendor Alarm Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.phyXS_VendorAlarmInterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int phyXS_VendorAlarmInterruptMask : 1; /* 1E.FF01.D R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF01.C R/WPD Autonegotiation Vendor Alarm Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.autonegotiationVendorAlarmInterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int autonegotiationVendorAlarmInterruptMask : 1; /* 1E.FF01.C R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF01.B R/WPD GbE Vendor Alarm Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.gbeVendorAlarmInterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int gbeVendorAlarmInterruptMask : 1; /* 1E.FF01.B R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - unsigned int reserved0 : 8; - /*! \brief 1E.FF01.2 R/WPD Global Alarms 1 Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.globalAlarms_1InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int globalAlarms_1InterruptMask : 1; /* 1E.FF01.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF01.1 R/WPD Global Alarms 2 Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.globalAlarms_2InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int globalAlarms_2InterruptMask : 1; /* 1E.FF01.1 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF01.0 R/WPD Global Alarms 3 Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.globalAlarms_3InterruptMask - - Provisionable Default = 0x1 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int globalAlarms_3InterruptMask : 1; /* 1E.FF01.0 R/WPD Provisionable Default = 0x1 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalInterruptChip_wideVendorMask_APPIA; - -#endif -/*@}*/ -/*@}*/ diff --git a/qca/aq-fw-download/src/include/registerMap/AQ_RegGroupMaxSizes.h b/qca/aq-fw-download/src/include/registerMap/AQ_RegGroupMaxSizes.h deleted file mode 100644 index 08e255860..000000000 --- a/qca/aq-fw-download/src/include/registerMap/AQ_RegGroupMaxSizes.h +++ /dev/null @@ -1,387 +0,0 @@ -/* Copyright (c) 2015, Aquantia -* -* Permission to use, copy, modify, and/or distribute this software for any -* purpose with or without fee is hereby granted, provided that the above -* copyright notice and this permission notice appear in all copies. -* -* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -*/ -#ifndef AQ_REG_GROUP_MAX_SIZES -#define AQ_REG_GROUP_MAX_SIZES - -#define AQ_Autonegotiation10GBaseT_ControlRegister_BiggestVersion AQ_Autonegotiation10GBaseT_ControlRegister_HHD -#define AQ_Autonegotiation10GBaseT_StatusRegister_BiggestVersion AQ_Autonegotiation10GBaseT_StatusRegister_HHD -#define AQ_AutonegotiationAdvertisementRegister_BiggestVersion AQ_AutonegotiationAdvertisementRegister_HHD -#define AQ_AutonegotiationEeeAdvertisementRegister_BiggestVersion AQ_AutonegotiationEeeAdvertisementRegister_HHD -#define AQ_AutonegotiationEeeLinkPartnerAbilityRegister_BiggestVersion AQ_AutonegotiationEeeLinkPartnerAbilityRegister_HHD -#define AQ_AutonegotiationExtendedNextPageTransmitRegister_BiggestVersion AQ_AutonegotiationExtendedNextPageTransmitRegister_HHD -#define AQ_AutonegotiationExtendedNextPageUnformattedCodeRegister_BiggestVersion AQ_AutonegotiationExtendedNextPageUnformattedCodeRegister_HHD -#define AQ_AutonegotiationLinkPartnerBasePageAbilityRegister_BiggestVersion AQ_AutonegotiationLinkPartnerBasePageAbilityRegister_HHD -#define AQ_AutonegotiationLinkPartnerExtendedNextPageAbilityRegister_BiggestVersion AQ_AutonegotiationLinkPartnerExtendedNextPageAbilityRegister_HHD -#define AQ_AutonegotiationLinkPartnerExtendedNextPageUnformattedCodeRegister_BiggestVersion AQ_AutonegotiationLinkPartnerExtendedNextPageUnformattedCodeRegister_HHD -#define AQ_AutonegotiationReceiveLinkPartnerStatus_BiggestVersion AQ_AutonegotiationReceiveLinkPartnerStatus_HHD -#define AQ_AutonegotiationReceiveReservedVendorProvisioning_BiggestVersion AQ_AutonegotiationReceiveReservedVendorProvisioning_APPIA -#define AQ_AutonegotiationReceiveReservedVendorStatus_BiggestVersion AQ_AutonegotiationReceiveReservedVendorStatus_HHD -#define AQ_AutonegotiationReceiveVendorAlarms_BiggestVersion AQ_AutonegotiationReceiveVendorAlarms_HHD -#define AQ_AutonegotiationReceiveVendorInterruptMask_BiggestVersion AQ_AutonegotiationReceiveVendorInterruptMask_HHD -#define AQ_AutonegotiationReservedVendorProvisioning_BiggestVersion AQ_AutonegotiationReservedVendorProvisioning_HHD -#define AQ_AutonegotiationReservedVendorStatus_BiggestVersion AQ_AutonegotiationReservedVendorStatus_HHD -#define AQ_AutonegotiationStandardControl_1_BiggestVersion AQ_AutonegotiationStandardControl_1_HHD -#define AQ_AutonegotiationStandardDeviceIdentifier_BiggestVersion AQ_AutonegotiationStandardDeviceIdentifier_HHD -#define AQ_AutonegotiationStandardDevicesInPackage_BiggestVersion AQ_AutonegotiationStandardDevicesInPackage_HHD -#define AQ_AutonegotiationStandardInterruptMask_BiggestVersion AQ_AutonegotiationStandardInterruptMask_HHD -#define AQ_AutonegotiationStandardPackageIdentifier_BiggestVersion AQ_AutonegotiationStandardPackageIdentifier_HHD -#define AQ_AutonegotiationStandardStatus_1_BiggestVersion AQ_AutonegotiationStandardStatus_1_HHD -#define AQ_AutonegotiationStandardStatus_2_BiggestVersion AQ_AutonegotiationStandardStatus_2_HHD -#define AQ_AutonegotiationTransmitVendorAlarms_BiggestVersion AQ_AutonegotiationTransmitVendorAlarms_APPIA -#define AQ_AutonegotiationTransmitVendorInterruptMask_BiggestVersion AQ_AutonegotiationTransmitVendorInterruptMask_HHD -#define AQ_AutonegotiationVendorGlobalInterruptFlags_BiggestVersion AQ_AutonegotiationVendorGlobalInterruptFlags_HHD -#define AQ_AutonegotiationVendorProvisioning_BiggestVersion AQ_AutonegotiationVendorProvisioning_HHD -#define AQ_AutonegotiationVendorStatus_BiggestVersion AQ_AutonegotiationVendorStatus_HHD -#define AQ_GbePhyExtendedWolControl_BiggestVersion AQ_GbePhyExtendedWolControl_HHD -#define AQ_GbePhySgmii0RxStatus_BiggestVersion AQ_GbePhySgmii0RxStatus_HHD -#define AQ_GbePhySgmii0TxStatus_BiggestVersion AQ_GbePhySgmii0TxStatus_HHD -#define AQ_GbePhySgmii1RxStatus_BiggestVersion AQ_GbePhySgmii1RxStatus_HHD -#define AQ_GbePhySgmii1TxStatus_BiggestVersion AQ_GbePhySgmii1TxStatus_HHD -#define AQ_GbePhySgmii1WolStatus_BiggestVersion AQ_GbePhySgmii1WolStatus_HHD -#define AQ_GbePhySgmiiRxAlarms_BiggestVersion AQ_GbePhySgmiiRxAlarms_HHD -#define AQ_GbePhySgmiiRxInterruptMask_BiggestVersion AQ_GbePhySgmiiRxInterruptMask_HHD -#define AQ_GbePhySgmiiTestControl_BiggestVersion AQ_GbePhySgmiiTestControl_HHD -#define AQ_GbePhySgmiiTxAlarms_BiggestVersion AQ_GbePhySgmiiTxAlarms_HHD -#define AQ_GbePhySgmiiTxInterruptMask_BiggestVersion AQ_GbePhySgmiiTxInterruptMask_HHD -#define AQ_GbePhySgmiiWolStatus_BiggestVersion AQ_GbePhySgmiiWolStatus_HHD -#define AQ_GbePhyVendorGlobalInterruptFlags_BiggestVersion AQ_GbePhyVendorGlobalInterruptFlags_HHD -#define AQ_GbePhyWolControl_BiggestVersion AQ_GbePhyWolControl_HHD -#define AQ_GbePhysgmii1WolStatus_BiggestVersion AQ_GbePhysgmii1WolStatus_APPIA -#define AQ_GbeReservedProvisioning_BiggestVersion AQ_GbeReservedProvisioning_HHD -#define AQ_GbeStandardDeviceIdentifier_BiggestVersion AQ_GbeStandardDeviceIdentifier_HHD -#define AQ_GbeStandardDevicesInPackage_BiggestVersion AQ_GbeStandardDevicesInPackage_HHD -#define AQ_GbeStandardPackageIdentifier_BiggestVersion AQ_GbeStandardPackageIdentifier_HHD -#define AQ_GbeStandardStatus_2_BiggestVersion AQ_GbeStandardStatus_2_HHD -#define AQ_GbeStandardVendorDevicesInPackage_BiggestVersion AQ_GbeStandardVendorDevicesInPackage_HHD -#define AQ_GlobalAlarms_BiggestVersion AQ_GlobalAlarms_HHD -#define AQ_GlobalCableDiagnosticImpedance_BiggestVersion AQ_GlobalCableDiagnosticImpedance_HHD -#define AQ_GlobalCableDiagnosticStatus_BiggestVersion AQ_GlobalCableDiagnosticStatus_APPIA -#define AQ_GlobalChipIdentification_BiggestVersion AQ_GlobalChipIdentification_APPIA -#define AQ_GlobalChipRevision_BiggestVersion AQ_GlobalChipRevision_APPIA -#define AQ_GlobalChip_wideStandardInterruptFlags_BiggestVersion AQ_GlobalChip_wideStandardInterruptFlags_HHD -#define AQ_GlobalChip_wideVendorInterruptFlags_BiggestVersion AQ_GlobalChip_wideVendorInterruptFlags_HHD -#define AQ_GlobalControl_BiggestVersion AQ_GlobalControl_HHD -#define AQ_GlobalDaisyChainStatus_BiggestVersion AQ_GlobalDaisyChainStatus_HHD -#define AQ_GlobalDiagnosticProvisioning_BiggestVersion AQ_GlobalDiagnosticProvisioning_HHD -#define AQ_GlobalEeeProvisioning_BiggestVersion AQ_GlobalEeeProvisioning_HHD -#define AQ_GlobalFaultMessage_BiggestVersion AQ_GlobalFaultMessage_HHD -#define AQ_GlobalFirmwareID_BiggestVersion AQ_GlobalFirmwareID_HHD -#define AQ_GlobalGeneralProvisioning_BiggestVersion AQ_GlobalGeneralProvisioning_HHD -#define AQ_GlobalGeneralStatus_BiggestVersion AQ_GlobalGeneralStatus_HHD -#define AQ_GlobalInterruptChip_wideStandardMask_BiggestVersion AQ_GlobalInterruptChip_wideStandardMask_HHD -#define AQ_GlobalInterruptChip_wideVendorMask_BiggestVersion AQ_GlobalInterruptChip_wideVendorMask_HHD -#define AQ_GlobalInterruptMask_BiggestVersion AQ_GlobalInterruptMask_HHD -#define AQ_GlobalLedProvisioning_BiggestVersion AQ_GlobalLedProvisioning_HHD -#define AQ_GlobalMailboxInterface_BiggestVersion AQ_GlobalMailboxInterface_HHD -#define AQ_GlobalMicroprocessorScratchPad_BiggestVersion AQ_GlobalMicroprocessorScratchPad_HHD -#define AQ_GlobalNvrInterface_BiggestVersion AQ_GlobalNvrInterface_HHD -#define AQ_GlobalNvrProvisioning_BiggestVersion AQ_GlobalNvrProvisioning_HHD -#define AQ_GlobalPinStatus_BiggestVersion AQ_GlobalPinStatus_HHD -#define AQ_GlobalPrimaryStatus_BiggestVersion AQ_GlobalPrimaryStatus_APPIA -#define AQ_GlobalReservedProvisioning_BiggestVersion AQ_GlobalReservedProvisioning_HHD -#define AQ_GlobalReservedStatus_BiggestVersion AQ_GlobalReservedStatus_HHD -#define AQ_GlobalResetControl_BiggestVersion AQ_GlobalResetControl_HHD -#define AQ_GlobalSmbus_0Provisioning_BiggestVersion AQ_GlobalSmbus_0Provisioning_HHD -#define AQ_GlobalSmbus_1Provisioning_BiggestVersion AQ_GlobalSmbus_1Provisioning_HHD -#define AQ_GlobalStandardControl_1_BiggestVersion AQ_GlobalStandardControl_1_HHD -#define AQ_GlobalStandardDeviceIdentifier_BiggestVersion AQ_GlobalStandardDeviceIdentifier_HHD -#define AQ_GlobalStandardDevicesInPackage_BiggestVersion AQ_GlobalStandardDevicesInPackage_HHD -#define AQ_GlobalStandardPackageIdentifier_BiggestVersion AQ_GlobalStandardPackageIdentifier_HHD -#define AQ_GlobalStandardStatus_2_BiggestVersion AQ_GlobalStandardStatus_2_HHD -#define AQ_GlobalStandardVendorDevicesInPackage_BiggestVersion AQ_GlobalStandardVendorDevicesInPackage_HHD -#define AQ_GlobalStatus_BiggestVersion AQ_GlobalStatus_HHD -#define AQ_GlobalThermalProvisioning_BiggestVersion AQ_GlobalThermalProvisioning_HHD -#define AQ_GlobalThermalStatus_BiggestVersion AQ_GlobalThermalStatus_HHD -#define AQ_Kr0AutonegotiationAdvertisementWord_BiggestVersion AQ_Kr0AutonegotiationAdvertisementWord_HHD -#define AQ_Kr0AutonegotiationControl_BiggestVersion AQ_Kr0AutonegotiationControl_HHD -#define AQ_Kr0AutonegotiationExtendedNextPageAdvertisementWord_BiggestVersion AQ_Kr0AutonegotiationExtendedNextPageAdvertisementWord_HHD -#define AQ_Kr0AutonegotiationStatus_BiggestVersion AQ_Kr0AutonegotiationStatus_HHD -#define AQ_Kr0LinkPartnerAutonegotiationAdvertisementWord_BiggestVersion AQ_Kr0LinkPartnerAutonegotiationAdvertisementWord_HHD -#define AQ_Kr0LinkPartnerAutonegotiationExtendedNextPageAdvertisementWord_BiggestVersion AQ_Kr0LinkPartnerAutonegotiationExtendedNextPageAdvertisementWord_HHD -#define AQ_Kr1AutonegotiationAdvertisementWord_BiggestVersion AQ_Kr1AutonegotiationAdvertisementWord_HHD -#define AQ_Kr1AutonegotiationControl_BiggestVersion AQ_Kr1AutonegotiationControl_HHD -#define AQ_Kr1AutonegotiationExtendedNextPageAdvertisementWord_BiggestVersion AQ_Kr1AutonegotiationExtendedNextPageAdvertisementWord_HHD -#define AQ_Kr1AutonegotiationStatus_BiggestVersion AQ_Kr1AutonegotiationStatus_HHD -#define AQ_Kr1LinkPartnerAutonegotiationAdvertisementWord_BiggestVersion AQ_Kr1LinkPartnerAutonegotiationAdvertisementWord_HHD -#define AQ_Kr1LinkPartnerAutonegotiationExtendedNextPageAdvertisementWord_BiggestVersion AQ_Kr1LinkPartnerAutonegotiationExtendedNextPageAdvertisementWord_HHD -#define AQ_MsmLineFifoControlRegister_BiggestVersion AQ_MsmLineFifoControlRegister_HHD -#define AQ_MsmLineGeneralControlRegister_BiggestVersion AQ_MsmLineGeneralControlRegister_HHD -#define AQ_MsmLineGeneralStatusRegister_BiggestVersion AQ_MsmLineGeneralStatusRegister_HHD -#define AQ_MsmLineRxAlignmentErrorsCounterRegister_BiggestVersion AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD -#define AQ_MsmLineRxBroadcastFramesCounterRegister_BiggestVersion AQ_MsmLineRxBroadcastFramesCounterRegister_HHD -#define AQ_MsmLineRxErrorsCounterRegister_BiggestVersion AQ_MsmLineRxErrorsCounterRegister_HHD -#define AQ_MsmLineRxFcsErrorsCounterRegister_BiggestVersion AQ_MsmLineRxFcsErrorsCounterRegister_HHD -#define AQ_MsmLineRxGoodFramesCounterRegister_BiggestVersion AQ_MsmLineRxGoodFramesCounterRegister_HHD -#define AQ_MsmLineRxInRangeLengthErrorsCounterRegister_BiggestVersion AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD -#define AQ_MsmLineRxMulticastFramesCounterRegister_BiggestVersion AQ_MsmLineRxMulticastFramesCounterRegister_HHD -#define AQ_MsmLineRxOctetsCounterRegister_BiggestVersion AQ_MsmLineRxOctetsCounterRegister_HHD -#define AQ_MsmLineRxPauseFramesCounterRegister_BiggestVersion AQ_MsmLineRxPauseFramesCounterRegister_HHD -#define AQ_MsmLineRxTooLongErrorsCounterRegister_BiggestVersion AQ_MsmLineRxTooLongErrorsCounterRegister_HHD -#define AQ_MsmLineRxUnicastFramesCounterRegister_BiggestVersion AQ_MsmLineRxUnicastFramesCounterRegister_HHD -#define AQ_MsmLineRxVlanFramesCounterRegister_BiggestVersion AQ_MsmLineRxVlanFramesCounterRegister_HHD -#define AQ_MsmLineTxBroadcastFramesCounterRegister_BiggestVersion AQ_MsmLineTxBroadcastFramesCounterRegister_HHD -#define AQ_MsmLineTxErrorsCounterRegister_BiggestVersion AQ_MsmLineTxErrorsCounterRegister_HHD -#define AQ_MsmLineTxGoodFramesCounterRegister_BiggestVersion AQ_MsmLineTxGoodFramesCounterRegister_HHD -#define AQ_MsmLineTxIpgControlRegister_BiggestVersion AQ_MsmLineTxIpgControlRegister_HHD -#define AQ_MsmLineTxMulticastFramesCounterRegister_BiggestVersion AQ_MsmLineTxMulticastFramesCounterRegister_HHD -#define AQ_MsmLineTxOctetsCounterRegister_BiggestVersion AQ_MsmLineTxOctetsCounterRegister_HHD -#define AQ_MsmLineTxPauseFramesCounterRegister_BiggestVersion AQ_MsmLineTxPauseFramesCounterRegister_HHD -#define AQ_MsmLineTxUnicastFramesCounterRegister_BiggestVersion AQ_MsmLineTxUnicastFramesCounterRegister_HHD -#define AQ_MsmLineTxVlanFramesCounterRegister_BiggestVersion AQ_MsmLineTxVlanFramesCounterRegister_HHD -#define AQ_MsmSystemFifoControlRegister_BiggestVersion AQ_MsmSystemFifoControlRegister_HHD -#define AQ_MsmSystemGeneralControlRegister_BiggestVersion AQ_MsmSystemGeneralControlRegister_HHD -#define AQ_MsmSystemGeneralStatusRegister_BiggestVersion AQ_MsmSystemGeneralStatusRegister_HHD -#define AQ_MsmSystemRxAlignmentErrorsCounterRegister_BiggestVersion AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD -#define AQ_MsmSystemRxBroadcastFramesCounterRegister_BiggestVersion AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD -#define AQ_MsmSystemRxErrorsCounterRegister_BiggestVersion AQ_MsmSystemRxErrorsCounterRegister_HHD -#define AQ_MsmSystemRxFcsErrorsCounterRegister_BiggestVersion AQ_MsmSystemRxFcsErrorsCounterRegister_HHD -#define AQ_MsmSystemRxGoodFramesCounterRegister_BiggestVersion AQ_MsmSystemRxGoodFramesCounterRegister_HHD -#define AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_BiggestVersion AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD -#define AQ_MsmSystemRxMulticastFramesCounterRegister_BiggestVersion AQ_MsmSystemRxMulticastFramesCounterRegister_HHD -#define AQ_MsmSystemRxOctetsCounterRegister_BiggestVersion AQ_MsmSystemRxOctetsCounterRegister_HHD -#define AQ_MsmSystemRxPauseFramesCounterRegister_BiggestVersion AQ_MsmSystemRxPauseFramesCounterRegister_HHD -#define AQ_MsmSystemRxTooLongErrorsCounterRegister_BiggestVersion AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD -#define AQ_MsmSystemRxUnicastFramesCounterRegister_BiggestVersion AQ_MsmSystemRxUnicastFramesCounterRegister_HHD -#define AQ_MsmSystemRxVlanFramesCounterRegister_BiggestVersion AQ_MsmSystemRxVlanFramesCounterRegister_HHD -#define AQ_MsmSystemTxBroadcastFramesCounterRegister_BiggestVersion AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD -#define AQ_MsmSystemTxErrorsCounterRegister_BiggestVersion AQ_MsmSystemTxErrorsCounterRegister_HHD -#define AQ_MsmSystemTxGoodFramesCounterRegister_BiggestVersion AQ_MsmSystemTxGoodFramesCounterRegister_HHD -#define AQ_MsmSystemTxIpgControlRegister_BiggestVersion AQ_MsmSystemTxIpgControlRegister_HHD -#define AQ_MsmSystemTxMulticastFramesCounterRegister_BiggestVersion AQ_MsmSystemTxMulticastFramesCounterRegister_HHD -#define AQ_MsmSystemTxOctetsCounterRegister_BiggestVersion AQ_MsmSystemTxOctetsCounterRegister_HHD -#define AQ_MsmSystemTxPauseFramesCounterRegister_BiggestVersion AQ_MsmSystemTxPauseFramesCounterRegister_HHD -#define AQ_MsmSystemTxUnicastFramesCounterRegister_BiggestVersion AQ_MsmSystemTxUnicastFramesCounterRegister_HHD -#define AQ_MsmSystemTxVlanFramesCounterRegister_BiggestVersion AQ_MsmSystemTxVlanFramesCounterRegister_HHD -#define AQ_MssEgressControlRegister_BiggestVersion AQ_MssEgressControlRegister_HHD -#define AQ_MssEgressEccInterruptStatusRegister_BiggestVersion AQ_MssEgressEccInterruptStatusRegister_HHD -#define AQ_MssEgressInterruptMaskRegister_BiggestVersion AQ_MssEgressInterruptMaskRegister_HHD -#define AQ_MssEgressInterruptStatusRegister_BiggestVersion AQ_MssEgressInterruptStatusRegister_HHD -#define AQ_MssEgressLutAddressControlRegister_BiggestVersion AQ_MssEgressLutAddressControlRegister_HHD -#define AQ_MssEgressLutControlRegister_BiggestVersion AQ_MssEgressLutControlRegister_HHD -#define AQ_MssEgressLutDataControlRegister_BiggestVersion AQ_MssEgressLutDataControlRegister_HHD -#define AQ_MssEgressMtuSizeControlRegister_BiggestVersion AQ_MssEgressMtuSizeControlRegister_HHD -#define AQ_MssEgressPnControlRegister_BiggestVersion AQ_MssEgressPnControlRegister_HHD -#define AQ_MssEgressSaExpiredStatusRegister_BiggestVersion AQ_MssEgressSaExpiredStatusRegister_HHD -#define AQ_MssEgressSaThresholdExpiredStatusRegister_BiggestVersion AQ_MssEgressSaThresholdExpiredStatusRegister_HHD -#define AQ_MssEgressVlanControlRegister_BiggestVersion AQ_MssEgressVlanControlRegister_HHD -#define AQ_MssEgressVlanTpid_0Register_BiggestVersion AQ_MssEgressVlanTpid_0Register_HHD -#define AQ_MssEgressVlanTpid_1Register_BiggestVersion AQ_MssEgressVlanTpid_1Register_HHD -#define AQ_MssIngressControlRegister_BiggestVersion AQ_MssIngressControlRegister_HHD -#define AQ_MssIngressEccInterruptStatusRegister_BiggestVersion AQ_MssIngressEccInterruptStatusRegister_HHD -#define AQ_MssIngressInterruptMaskRegister_BiggestVersion AQ_MssIngressInterruptMaskRegister_HHD -#define AQ_MssIngressInterruptStatusRegister_BiggestVersion AQ_MssIngressInterruptStatusRegister_HHD -#define AQ_MssIngressLutAddressControlRegister_BiggestVersion AQ_MssIngressLutAddressControlRegister_HHD -#define AQ_MssIngressLutControlRegister_BiggestVersion AQ_MssIngressLutControlRegister_HHD -#define AQ_MssIngressLutDataControlRegister_BiggestVersion AQ_MssIngressLutDataControlRegister_HHD -#define AQ_MssIngressMtuSizeControlRegister_BiggestVersion AQ_MssIngressMtuSizeControlRegister_HHD -#define AQ_MssIngressSaControlRegister_BiggestVersion AQ_MssIngressSaControlRegister_HHD -#define AQ_MssIngressSaExpiredStatusRegister_BiggestVersion AQ_MssIngressSaExpiredStatusRegister_HHD -#define AQ_MssIngressSaIcvErrorStatusRegister_BiggestVersion AQ_MssIngressSaIcvErrorStatusRegister_HHD -#define AQ_MssIngressSaReplayErrorStatusRegister_BiggestVersion AQ_MssIngressSaReplayErrorStatusRegister_HHD -#define AQ_MssIngressSaThresholdExpiredStatusRegister_BiggestVersion AQ_MssIngressSaThresholdExpiredStatusRegister_HHD -#define AQ_MssIngressVlanControlRegister_BiggestVersion AQ_MssIngressVlanControlRegister_HHD -#define AQ_MssIngressVlanTpid_0Register_BiggestVersion AQ_MssIngressVlanTpid_0Register_HHD -#define AQ_MssIngressVlanTpid_1Register_BiggestVersion AQ_MssIngressVlanTpid_1Register_HHD -#define AQ_Pcs10GBaseT_Status_BiggestVersion AQ_Pcs10GBaseT_Status_APPIA -#define AQ_Pcs10G_Status_BiggestVersion AQ_Pcs10G_Status_HHD -#define AQ_Pcs10G_base_rPcsTest_patternControl_BiggestVersion AQ_Pcs10G_base_rPcsTest_patternControl_HHD -#define AQ_Pcs10G_base_rPcsTest_patternErrorCounter_BiggestVersion AQ_Pcs10G_base_rPcsTest_patternErrorCounter_HHD -#define AQ_Pcs10G_base_rTestPatternSeedA_BiggestVersion AQ_Pcs10G_base_rTestPatternSeedA_HHD -#define AQ_Pcs10G_base_rTestPatternSeedB_BiggestVersion AQ_Pcs10G_base_rTestPatternSeedB_HHD -#define AQ_PcsEeeCapabilityRegister_BiggestVersion AQ_PcsEeeCapabilityRegister_HHD -#define AQ_PcsEeeWakeErrorCounter_BiggestVersion AQ_PcsEeeWakeErrorCounter_HHD -#define AQ_PcsReceiveStandardInterruptMask_BiggestVersion AQ_PcsReceiveStandardInterruptMask_APPIA -#define AQ_PcsReceiveVendorAlarms_BiggestVersion AQ_PcsReceiveVendorAlarms_HHD -#define AQ_PcsReceiveVendorCorrectedFrame_1IterationCounter_BiggestVersion AQ_PcsReceiveVendorCorrectedFrame_1IterationCounter_HHD -#define AQ_PcsReceiveVendorCorrectedFrame_2IterationCounter_BiggestVersion AQ_PcsReceiveVendorCorrectedFrame_2IterationCounter_HHD -#define AQ_PcsReceiveVendorCorrectedFrame_3IterationCounter_BiggestVersion AQ_PcsReceiveVendorCorrectedFrame_3IterationCounter_HHD -#define AQ_PcsReceiveVendorCorrectedFrame_4IterationCounter_BiggestVersion AQ_PcsReceiveVendorCorrectedFrame_4IterationCounter_HHD -#define AQ_PcsReceiveVendorCorrectedFrame_5IterationCounter_BiggestVersion AQ_PcsReceiveVendorCorrectedFrame_5IterationCounter_HHD -#define AQ_PcsReceiveVendorCorrectedFrame_6IterationCounter_BiggestVersion AQ_PcsReceiveVendorCorrectedFrame_6IterationCounter_HHD -#define AQ_PcsReceiveVendorCorrectedFrame_7IterationCounter_BiggestVersion AQ_PcsReceiveVendorCorrectedFrame_7IterationCounter_HHD -#define AQ_PcsReceiveVendorCorrectedFrame_8IterationCounter_BiggestVersion AQ_PcsReceiveVendorCorrectedFrame_8IterationCounter_HHD -#define AQ_PcsReceiveVendorCrc_8ErrorCounter_BiggestVersion AQ_PcsReceiveVendorCrc_8ErrorCounter_HHD -#define AQ_PcsReceiveVendorDebug_BiggestVersion AQ_PcsReceiveVendorDebug_HHD -#define AQ_PcsReceiveVendorFcsErrorFrameCounter_BiggestVersion AQ_PcsReceiveVendorFcsErrorFrameCounter_HHD -#define AQ_PcsReceiveVendorFcsNoErrorFrameCounter_BiggestVersion AQ_PcsReceiveVendorFcsNoErrorFrameCounter_HHD -#define AQ_PcsReceiveVendorInterruptMask_BiggestVersion AQ_PcsReceiveVendorInterruptMask_HHD -#define AQ_PcsReceiveVendorProvisioning_BiggestVersion AQ_PcsReceiveVendorProvisioning_HHD -#define AQ_PcsReceiveVendorState_BiggestVersion AQ_PcsReceiveVendorState_HHD -#define AQ_PcsReceiveVendorUncorrectedFrameCounter_BiggestVersion AQ_PcsReceiveVendorUncorrectedFrameCounter_HHD -#define AQ_PcsReceiveXfi0Provisioning_BiggestVersion AQ_PcsReceiveXfi0Provisioning_HHD -#define AQ_PcsReceiveXfi0VendorState_BiggestVersion AQ_PcsReceiveXfi0VendorState_HHD -#define AQ_PcsReceiveXfi1Provisioning_BiggestVersion AQ_PcsReceiveXfi1Provisioning_HHD -#define AQ_PcsReceiveXfi1VendorState_BiggestVersion AQ_PcsReceiveXfi1VendorState_HHD -#define AQ_PcsSerdesMuxSwapTxrxRegister_BiggestVersion AQ_PcsSerdesMuxSwapTxrxRegister_HHD -#define AQ_PcsStandardControl_1_BiggestVersion AQ_PcsStandardControl_1_HHD -#define AQ_PcsStandardControl_2_BiggestVersion AQ_PcsStandardControl_2_HHD -#define AQ_PcsStandardDeviceIdentifier_BiggestVersion AQ_PcsStandardDeviceIdentifier_HHD -#define AQ_PcsStandardDevicesInPackage_BiggestVersion AQ_PcsStandardDevicesInPackage_HHD -#define AQ_PcsStandardInterruptMask_BiggestVersion AQ_PcsStandardInterruptMask_HHD -#define AQ_PcsStandardPackageIdentifier_BiggestVersion AQ_PcsStandardPackageIdentifier_HHD -#define AQ_PcsStandardSpeedAbility_BiggestVersion AQ_PcsStandardSpeedAbility_HHD -#define AQ_PcsStandardStatus_1_BiggestVersion AQ_PcsStandardStatus_1_HHD -#define AQ_PcsStandardStatus_2_BiggestVersion AQ_PcsStandardStatus_2_HHD -#define AQ_PcsTransmitReservedVendorProvisioning_BiggestVersion AQ_PcsTransmitReservedVendorProvisioning_HHD -#define AQ_PcsTransmitVendorAlarms_BiggestVersion AQ_PcsTransmitVendorAlarms_APPIA -#define AQ_PcsTransmitVendorDebug_BiggestVersion AQ_PcsTransmitVendorDebug_HHD -#define AQ_PcsTransmitVendorFcsErrorFrameCounter_BiggestVersion AQ_PcsTransmitVendorFcsErrorFrameCounter_HHD -#define AQ_PcsTransmitVendorFcsNoErrorFrameCounter_BiggestVersion AQ_PcsTransmitVendorFcsNoErrorFrameCounter_HHD -#define AQ_PcsTransmitVendorInterruptMask_BiggestVersion AQ_PcsTransmitVendorInterruptMask_APPIA -#define AQ_PcsTransmitVendorProvisioning_BiggestVersion AQ_PcsTransmitVendorProvisioning_HHD -#define AQ_PcsTransmitXfi0VendorProvisioning_BiggestVersion AQ_PcsTransmitXfi0VendorProvisioning_HHD -#define AQ_PcsTransmitXfi0VendorState_BiggestVersion AQ_PcsTransmitXfi0VendorState_HHD -#define AQ_PcsTransmitXfi1VendorProvisioning_BiggestVersion AQ_PcsTransmitXfi1VendorProvisioning_HHD -#define AQ_PcsTransmitXfi1VendorState_BiggestVersion AQ_PcsTransmitXfi1VendorState_HHD -#define AQ_PcsTransmitXfiVendorProvisioning_BiggestVersion AQ_PcsTransmitXfiVendorProvisioning_HHD -#define AQ_PcsTransmitXgsVendorState_BiggestVersion AQ_PcsTransmitXgsVendorState_HHD -#define AQ_PcsVendorGlobalInterruptFlags_BiggestVersion AQ_PcsVendorGlobalInterruptFlags_HHD -#define AQ_PhyXS_EeeCapabilityRegister_BiggestVersion AQ_PhyXS_EeeCapabilityRegister_HHD -#define AQ_PhyXS_EeeWakeErrorCounter_BiggestVersion AQ_PhyXS_EeeWakeErrorCounter_HHD -#define AQ_PhyXS_Receive_xauiTx_PcsStatus_BiggestVersion AQ_PhyXS_Receive_xauiTx_PcsStatus_HHD -#define AQ_PhyXS_Receive_xauiTx_ReservedVendorProvisioning_BiggestVersion AQ_PhyXS_Receive_xauiTx_ReservedVendorProvisioning_HHD -#define AQ_PhyXS_Receive_xauiTx_VendorAlarms_BiggestVersion AQ_PhyXS_Receive_xauiTx_VendorAlarms_HHD -#define AQ_PhyXS_Receive_xauiTx_VendorDebug_BiggestVersion AQ_PhyXS_Receive_xauiTx_VendorDebug_HHD -#define AQ_PhyXS_Receive_xauiTx_VendorInterruptMask_BiggestVersion AQ_PhyXS_Receive_xauiTx_VendorInterruptMask_HHD -#define AQ_PhyXS_SerdesConfiguration_BiggestVersion AQ_PhyXS_SerdesConfiguration_HHD -#define AQ_PhyXS_SerdesLane_0Configuration_BiggestVersion AQ_PhyXS_SerdesLane_0Configuration_HHD -#define AQ_PhyXS_SerdesLane_1Configuration_BiggestVersion AQ_PhyXS_SerdesLane_1Configuration_HHD -#define AQ_PhyXS_SerdesLane_2Configuration_BiggestVersion AQ_PhyXS_SerdesLane_2Configuration_HHD -#define AQ_PhyXS_SerdesLane_3Configuration_BiggestVersion AQ_PhyXS_SerdesLane_3Configuration_HHD -#define AQ_PhyXS_SerdesLut_BiggestVersion AQ_PhyXS_SerdesLut_HHD -#define AQ_PhyXS_StandardControl_1_BiggestVersion AQ_PhyXS_StandardControl_1_HHD -#define AQ_PhyXS_StandardDeviceIdentifier_BiggestVersion AQ_PhyXS_StandardDeviceIdentifier_HHD -#define AQ_PhyXS_StandardDevicesInPackage_BiggestVersion AQ_PhyXS_StandardDevicesInPackage_HHD -#define AQ_PhyXS_StandardPackageIdentifier_BiggestVersion AQ_PhyXS_StandardPackageIdentifier_HHD -#define AQ_PhyXS_StandardSpeedAbility_BiggestVersion AQ_PhyXS_StandardSpeedAbility_HHD -#define AQ_PhyXS_StandardStatus_1_BiggestVersion AQ_PhyXS_StandardStatus_1_HHD -#define AQ_PhyXS_StandardStatus_2_BiggestVersion AQ_PhyXS_StandardStatus_2_HHD -#define AQ_PhyXS_StandardXGXS_LaneStatus_BiggestVersion AQ_PhyXS_StandardXGXS_LaneStatus_HHD -#define AQ_PhyXS_StandardXGXS_TestControl_BiggestVersion AQ_PhyXS_StandardXGXS_TestControl_HHD -#define AQ_PhyXS_SystemInterfaceConnectionStatus_BiggestVersion AQ_PhyXS_SystemInterfaceConnectionStatus_HHD -#define AQ_PhyXS_Transmit_xauiRx_PcsStatus_BiggestVersion AQ_PhyXS_Transmit_xauiRx_PcsStatus_HHD -#define AQ_PhyXS_Transmit_xauiRx_ReservedVendorProvisioning_BiggestVersion AQ_PhyXS_Transmit_xauiRx_ReservedVendorProvisioning_HHD -#define AQ_PhyXS_Transmit_xauiRx_ReservedVendorState_BiggestVersion AQ_PhyXS_Transmit_xauiRx_ReservedVendorState_HHD -#define AQ_PhyXS_Transmit_xauiRx_StandardInterruptMask_BiggestVersion AQ_PhyXS_Transmit_xauiRx_StandardInterruptMask_HHD -#define AQ_PhyXS_Transmit_xauiRx_TestPatternErrorCounter_BiggestVersion AQ_PhyXS_Transmit_xauiRx_TestPatternErrorCounter_HHD -#define AQ_PhyXS_Transmit_xauiRx_VendorAlarms_BiggestVersion AQ_PhyXS_Transmit_xauiRx_VendorAlarms_HHD -#define AQ_PhyXS_Transmit_xauiRx_VendorDebug_BiggestVersion AQ_PhyXS_Transmit_xauiRx_VendorDebug_HHD -#define AQ_PhyXS_Transmit_xauiRx_VendorInterruptMask_BiggestVersion AQ_PhyXS_Transmit_xauiRx_VendorInterruptMask_HHD -#define AQ_PhyXS_VendorGlobalInterruptFlags_BiggestVersion AQ_PhyXS_VendorGlobalInterruptFlags_HHD -#define AQ_PifMailboxControl_BiggestVersion AQ_PifMailboxControl_HHD -#define AQ_Pma10GBaseT_FastRetrainStatusAndControl_BiggestVersion AQ_Pma10GBaseT_FastRetrainStatusAndControl_HHD -#define AQ_Pma10GBaseT_PairSwapAndPolarityStatus_BiggestVersion AQ_Pma10GBaseT_PairSwapAndPolarityStatus_HHD -#define AQ_Pma10GBaseT_ReceiveSignalPowerChannelA_BiggestVersion AQ_Pma10GBaseT_ReceiveSignalPowerChannelA_HHD -#define AQ_Pma10GBaseT_ReceiveSignalPowerChannelB_BiggestVersion AQ_Pma10GBaseT_ReceiveSignalPowerChannelB_HHD -#define AQ_Pma10GBaseT_ReceiveSignalPowerChannelC_BiggestVersion AQ_Pma10GBaseT_ReceiveSignalPowerChannelC_HHD -#define AQ_Pma10GBaseT_ReceiveSignalPowerChannelD_BiggestVersion AQ_Pma10GBaseT_ReceiveSignalPowerChannelD_HHD -#define AQ_Pma10GBaseT_SNR_MinimumOperatingMarginChannelA_BiggestVersion AQ_Pma10GBaseT_SNR_MinimumOperatingMarginChannelA_HHD -#define AQ_Pma10GBaseT_SNR_MinimumOperatingMarginChannelB_BiggestVersion AQ_Pma10GBaseT_SNR_MinimumOperatingMarginChannelB_HHD -#define AQ_Pma10GBaseT_SNR_MinimumOperatingMarginChannelC_BiggestVersion AQ_Pma10GBaseT_SNR_MinimumOperatingMarginChannelC_HHD -#define AQ_Pma10GBaseT_SNR_MinimumOperatingMarginChannelD_BiggestVersion AQ_Pma10GBaseT_SNR_MinimumOperatingMarginChannelD_HHD -#define AQ_Pma10GBaseT_SNR_OperatingMarginChannelA_BiggestVersion AQ_Pma10GBaseT_SNR_OperatingMarginChannelA_HHD -#define AQ_Pma10GBaseT_SNR_OperatingMarginChannelB_BiggestVersion AQ_Pma10GBaseT_SNR_OperatingMarginChannelB_HHD -#define AQ_Pma10GBaseT_SNR_OperatingMarginChannelC_BiggestVersion AQ_Pma10GBaseT_SNR_OperatingMarginChannelC_HHD -#define AQ_Pma10GBaseT_SNR_OperatingMarginChannelD_BiggestVersion AQ_Pma10GBaseT_SNR_OperatingMarginChannelD_HHD -#define AQ_Pma10GBaseT_SkewDelay_BiggestVersion AQ_Pma10GBaseT_SkewDelay_HHD -#define AQ_Pma10GBaseT_Status_BiggestVersion AQ_Pma10GBaseT_Status_HHD -#define AQ_Pma10GBaseT_TestModes_BiggestVersion AQ_Pma10GBaseT_TestModes_HHD -#define AQ_Pma10GBaseT_TxPowerBackoffAndShortReachSetting_BiggestVersion AQ_Pma10GBaseT_TxPowerBackoffAndShortReachSetting_HHD -#define AQ_PmaReceiveReservedVendorProvisioning_BiggestVersion AQ_PmaReceiveReservedVendorProvisioning_HHD -#define AQ_PmaReceiveReservedVendorState_BiggestVersion AQ_PmaReceiveReservedVendorState_HHD -#define AQ_PmaReceiveVendorState_BiggestVersion AQ_PmaReceiveVendorState_HHD -#define AQ_PmaStandardControl_1_BiggestVersion AQ_PmaStandardControl_1_HHD -#define AQ_PmaStandardControl_2_BiggestVersion AQ_PmaStandardControl_2_HHD -#define AQ_PmaStandardDeviceIdentifier_BiggestVersion AQ_PmaStandardDeviceIdentifier_HHD -#define AQ_PmaStandardDevicesInPackage_BiggestVersion AQ_PmaStandardDevicesInPackage_HHD -#define AQ_PmaStandardPackageIdentifier_BiggestVersion AQ_PmaStandardPackageIdentifier_HHD -#define AQ_PmaStandardSpeedAbility_BiggestVersion AQ_PmaStandardSpeedAbility_HHD -#define AQ_PmaStandardStatus_1_BiggestVersion AQ_PmaStandardStatus_1_HHD -#define AQ_PmaStandardStatus_2_BiggestVersion AQ_PmaStandardStatus_2_HHD -#define AQ_PmaTransmitReservedVendorProvisioning_BiggestVersion AQ_PmaTransmitReservedVendorProvisioning_HHD -#define AQ_PmaTransmitStandardInterruptMask_BiggestVersion AQ_PmaTransmitStandardInterruptMask_HHD -#define AQ_PmaTransmitVendorAlarms_BiggestVersion AQ_PmaTransmitVendorAlarms_HHD -#define AQ_PmaTransmitVendorDebug_BiggestVersion AQ_PmaTransmitVendorDebug_HHD -#define AQ_PmaTransmitVendorLASI_InterruptMask_BiggestVersion AQ_PmaTransmitVendorLASI_InterruptMask_HHD -#define AQ_PmaVendorGlobalInterruptFlags_BiggestVersion AQ_PmaVendorGlobalInterruptFlags_HHD -#define AQ_PmdStandard10G_ExtendedAbilityRegister_BiggestVersion AQ_PmdStandard10G_ExtendedAbilityRegister_HHD -#define AQ_PmdStandardSignalDetect_BiggestVersion AQ_PmdStandardSignalDetect_HHD -#define AQ_PmdStandardTransmitDisableControl_BiggestVersion AQ_PmdStandardTransmitDisableControl_HHD -#define AQ_Sgmii0WolStatus_BiggestVersion AQ_Sgmii0WolStatus_HHD -#define AQ_TimesyncPcsCapability_BiggestVersion AQ_TimesyncPcsCapability_HHD -#define AQ_TimesyncPcsReceivePathDataDelay_BiggestVersion AQ_TimesyncPcsReceivePathDataDelay_HHD -#define AQ_TimesyncPcsTransmitPathDataDelay_BiggestVersion AQ_TimesyncPcsTransmitPathDataDelay_HHD -#define AQ_TimesyncPhyXsCapability_BiggestVersion AQ_TimesyncPhyXsCapability_HHD -#define AQ_TimesyncPhyXsReceivePathDataDelay_BiggestVersion AQ_TimesyncPhyXsReceivePathDataDelay_HHD -#define AQ_TimesyncPhyXsTransmitPathDataDelay_BiggestVersion AQ_TimesyncPhyXsTransmitPathDataDelay_HHD -#define AQ_TimesyncPmaCapability_BiggestVersion AQ_TimesyncPmaCapability_HHD -#define AQ_TimesyncPmaReceivePathDataDelay_BiggestVersion AQ_TimesyncPmaReceivePathDataDelay_HHD -#define AQ_TimesyncPmaTransmitPathDataDelay_BiggestVersion AQ_TimesyncPmaTransmitPathDataDelay_HHD -#define AQ_XenpakBasic_ApsLoading_BiggestVersion AQ_XenpakBasic_ApsLoading_HHD -#define AQ_XenpakBasic_ApsVoltage_BiggestVersion AQ_XenpakBasic_ApsVoltage_HHD -#define AQ_XenpakBasic_BitRate_BiggestVersion AQ_XenpakBasic_BitRate_HHD -#define AQ_XenpakBasic_Checksum_BiggestVersion AQ_XenpakBasic_Checksum_HHD -#define AQ_XenpakBasic_ConnectorType_BiggestVersion AQ_XenpakBasic_ConnectorType_HHD -#define AQ_XenpakBasic_DomCapability_BiggestVersion AQ_XenpakBasic_DomCapability_HHD -#define AQ_XenpakBasic_Encoding_BiggestVersion AQ_XenpakBasic_Encoding_HHD -#define AQ_XenpakBasic_Low_powerStartupCapability_BiggestVersion AQ_XenpakBasic_Low_powerStartupCapability_HHD -#define AQ_XenpakBasic_PackageIdentifier_BiggestVersion AQ_XenpakBasic_PackageIdentifier_HHD -#define AQ_XenpakBasic_Protocol_BiggestVersion AQ_XenpakBasic_Protocol_HHD -#define AQ_XenpakBasic_Reserved_0x11_BiggestVersion AQ_XenpakBasic_Reserved_0x11_HHD -#define AQ_XenpakBasic_Reserved_0x19_BiggestVersion AQ_XenpakBasic_Reserved_0x19_HHD -#define AQ_XenpakBasic_Reserved_0x7c_BiggestVersion AQ_XenpakBasic_Reserved_0x7c_HHD -#define AQ_XenpakBasic_StandardsComplianceCodes_BiggestVersion AQ_XenpakBasic_StandardsComplianceCodes_HHD -#define AQ_XenpakBasic_TransceiverType_BiggestVersion AQ_XenpakBasic_TransceiverType_HHD -#define AQ_XenpakBasic_VendorDateCode_BiggestVersion AQ_XenpakBasic_VendorDateCode_HHD -#define AQ_XenpakBasic_VendorIdentifier_BiggestVersion AQ_XenpakBasic_VendorIdentifier_HHD -#define AQ_XenpakBasic_VendorName_BiggestVersion AQ_XenpakBasic_VendorName_HHD -#define AQ_XenpakBasic_VendorPartNumber_BiggestVersion AQ_XenpakBasic_VendorPartNumber_HHD -#define AQ_XenpakBasic_VendorPartRevisionNumber_BiggestVersion AQ_XenpakBasic_VendorPartRevisionNumber_HHD -#define AQ_XenpakBasic_VendorSerialNumber_BiggestVersion AQ_XenpakBasic_VendorSerialNumber_HHD -#define AQ_XenpakBasic__3_3vLoading_BiggestVersion AQ_XenpakBasic__3_3vLoading_HHD -#define AQ_XenpakBasic__5vLoading_BiggestVersion AQ_XenpakBasic__5vLoading_HHD -#define AQ_XenpakControl_BiggestVersion AQ_XenpakControl_HHD -#define AQ_XenpakCustomer_Reserved_0x7e_BiggestVersion AQ_XenpakCustomer_Reserved_0x7e_HHD -#define AQ_XenpakDom_Alarms_BiggestVersion AQ_XenpakDom_Alarms_HHD -#define AQ_XenpakDom_Capability_BiggestVersion AQ_XenpakDom_Capability_HHD -#define AQ_XenpakDom_ControlAndStatus_BiggestVersion AQ_XenpakDom_ControlAndStatus_HHD -#define AQ_XenpakDom_HighTemperatureAlarmThresholdLSW_BiggestVersion AQ_XenpakDom_HighTemperatureAlarmThresholdLSW_HHD -#define AQ_XenpakDom_HighTemperatureAlarmThresholdMSW_BiggestVersion AQ_XenpakDom_HighTemperatureAlarmThresholdMSW_HHD -#define AQ_XenpakDom_HighTemperatureWarningThresholdLSW_BiggestVersion AQ_XenpakDom_HighTemperatureWarningThresholdLSW_HHD -#define AQ_XenpakDom_HighTemperatureWarningThresholdMSW_BiggestVersion AQ_XenpakDom_HighTemperatureWarningThresholdMSW_HHD -#define AQ_XenpakDom_LowTemperatureAlarmThresholdLSW_BiggestVersion AQ_XenpakDom_LowTemperatureAlarmThresholdLSW_HHD -#define AQ_XenpakDom_LowTemperatureAlarmThresholdMSW_BiggestVersion AQ_XenpakDom_LowTemperatureAlarmThresholdMSW_HHD -#define AQ_XenpakDom_LowTemperatureWarningThresholdLSW_BiggestVersion AQ_XenpakDom_LowTemperatureWarningThresholdLSW_HHD -#define AQ_XenpakDom_LowTemperatureWarningThresholdMSW_BiggestVersion AQ_XenpakDom_LowTemperatureWarningThresholdMSW_HHD -#define AQ_XenpakDom_Status_BiggestVersion AQ_XenpakDom_Status_HHD -#define AQ_XenpakDom_TemperatureLSW_BiggestVersion AQ_XenpakDom_TemperatureLSW_HHD -#define AQ_XenpakDom_TemperatureMSW_BiggestVersion AQ_XenpakDom_TemperatureMSW_HHD -#define AQ_XenpakDom_TxControl_BiggestVersion AQ_XenpakDom_TxControl_HHD -#define AQ_XenpakHeader_BasicMemoryStartAddress_BiggestVersion AQ_XenpakHeader_BasicMemoryStartAddress_HHD -#define AQ_XenpakHeader_CustomerMemoryOffset_BiggestVersion AQ_XenpakHeader_CustomerMemoryOffset_HHD -#define AQ_XenpakHeader_ExtendedVendorMemoryOffset_BiggestVersion AQ_XenpakHeader_ExtendedVendorMemoryOffset_HHD -#define AQ_XenpakHeader_MemoryUsed_BiggestVersion AQ_XenpakHeader_MemoryUsed_HHD -#define AQ_XenpakHeader_NvrSize_BiggestVersion AQ_XenpakHeader_NvrSize_HHD -#define AQ_XenpakHeader_VendorMemoryStartAddress_BiggestVersion AQ_XenpakHeader_VendorMemoryStartAddress_HHD -#define AQ_XenpakHeader_XenpakMsaVersionSupported_BiggestVersion AQ_XenpakHeader_XenpakMsaVersionSupported_HHD -#define AQ_XenpakLASI__Control_BiggestVersion AQ_XenpakLASI__Control_HHD -#define AQ_XenpakLASI__Status_BiggestVersion AQ_XenpakLASI__Status_HHD -#define AQ_XenpakRxAlarm_Control_BiggestVersion AQ_XenpakRxAlarm_Control_HHD -#define AQ_XenpakRxAlarm_Status_BiggestVersion AQ_XenpakRxAlarm_Status_HHD -#define AQ_XenpakTxAlarm_Control_BiggestVersion AQ_XenpakTxAlarm_Control_HHD -#define AQ_XenpakTxAlarm_Status_BiggestVersion AQ_XenpakTxAlarm_Status_HHD -#define AQ_XenpakVendor_Reserved_0xae_BiggestVersion AQ_XenpakVendor_Reserved_0xae_HHD - -#endif diff --git a/qca/aq-fw-download/src/include/registerMap/AQ_RegMaps.h b/qca/aq-fw-download/src/include/registerMap/AQ_RegMaps.h deleted file mode 100644 index 52a24e385..000000000 --- a/qca/aq-fw-download/src/include/registerMap/AQ_RegMaps.h +++ /dev/null @@ -1,69 +0,0 @@ -/*AQ_RegMaps.h*/ - -/************************************************************************************ -* Copyright (c) 2015, Aquantia -* -* Permission to use, copy, modify, and/or distribute this software for any -* purpose with or without fee is hereby granted, provided that the above -* copyright notice and this permission notice appear in all copies. -* -* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -* -* Description: -* -* This file contains includes all appropriate Aquantia PHY device-specific -* register map headers. -* -************************************************************************************/ - -/*! \file -* This file contains includes all appropriate Aquantia PHY device-specific -* register map headers. - */ - -#ifndef AQ_REGISTERMAPS_HEADER -#define AQ_REGISTERMAPS_HEADER - -#include "AQ_User.h" -#include "AQ_RegGroupMaxSizes.h" - - -#ifndef AQ_REVERSED_BITFIELD_ORDERING -/* - * Include non-reversed header files (bitfields ordered from LSbit to MSbit) - */ - -/* APPIA */ -#include "AQ_APPIA_Global_registers.h" - -#include "AQ_APPIA_Global_registers_Defines.h" - -/* HHD */ -#include "AQ_HHD_Global_registers.h" - -#include "AQ_HHD_Global_registers_Defines.h" - -#else -/* - * Include reversed header files (bitfields ordered from MSbit to LSbit) - */ - -/* APPIA */ -#include "AQ_APPIA_Global_registers_reversed.h" - -#include "AQ_APPIA_Global_registers_Defines.h" - -/* HHD */ -#include "AQ_HHD_Global_registers_reversed.h" - -#include "AQ_HHD_Global_registers_Defines.h" - -#endif - -#endif diff --git a/qca/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers.h b/qca/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers.h deleted file mode 100644 index e0a2fa27b..000000000 --- a/qca/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers.h +++ /dev/null @@ -1,12123 +0,0 @@ -/*! \file -* This file contains the data structures and doxygen comments -* for the Global Registers block. - */ - -/*! \addtogroup registerMap - @{ -*/ - -/*! \defgroup Global_registers Global Registers -* This module contains the data structures and doxygen comments -* for the Global Registers block. - */ -/*********************************************************************** -* Copyright (c) 2015, Aquantia -* -* Permission to use, copy, modify, and/or distribute this software for any -* purpose with or without fee is hereby granted, provided that the above -* copyright notice and this permission notice appear in all copies. -* -* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -* -* $Date: 2014/04/08 $ -* -* $Label: $ -* -* Description: -* -* This file contains the c header structures for the registers contained in the Global Registers block. -* -* The bit fields in this structure are from LSbit to MSbit -* -***********************************************************************/ - - -/*@{*/ -#ifndef AQ_HHD_GLOBAL_REGS_HEADER -#define AQ_HHD_GLOBAL_REGS_HEADER - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Standard Control 1: 1E.0000 */ -/* Global Standard Control 1: 1E.0000 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Standard Control 1 */ - union - { - struct - { - unsigned int reserved1 : 11; - /*! \brief 1E.0000.B R/WPD Low Power - AQ_GlobalStandardControl_1_HHD.u0.bits_0.lowPower - - Provisionable Default = 0x0 - - 1 = Low-power mode - 0 = Normal operation - - - Notes: - A one written to this register causes the chip to enter low-power mode. This bit puts the entire chip in low-power mode, with only the MDIO and microprocessor functioning, and turns off the analog front-end: i.e. places it in high-impedance mode. Setting this bit also sets all of the Low Power bits in the other MMDs. */ - unsigned int lowPower : 1; /* 1E.0000.B R/WPD Provisionable Default = 0x0 */ - /* 1 = Low-power mode - 0 = Normal operation - */ - unsigned int reserved0 : 3; - /*! \brief 1E.0000.F R/WSC Soft Reset - AQ_GlobalStandardControl_1_HHD.u0.bits_0.softReset - - Default = 0x1 - - 1 = Global soft reset - 0 = Normal operation - - - Notes: - Resets the entire PHY. - Setting this bit initiates a global soft reset on all of the digital logic not including the microprocessor (i.e. microprocessor is not reset). Upon completion of the reset sequence, this bit is set back to 0by the microprocessor. Note this bit is OR'ed with the individual MMD resets. This bit should be set to 0 before setting the individual MMD resets. */ - unsigned int softReset : 1; /* 1E.0000.F R/WSC Default = 0x1 */ - /* 1 = Global soft reset - 0 = Normal operation - */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalStandardControl_1_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Standard Device Identifier: 1E.0002 */ -/* Global Standard Device Identifier: 1E.0002 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Standard Device Identifier */ - union - { - struct - { - /*! \brief 1E.0002.F:0 RO Device ID MSW [1F:10] - AQ_GlobalStandardDeviceIdentifier_HHD.u0.bits_0.deviceIdMSW - - - - Bits 31 - 16 of Device ID - */ - unsigned int deviceIdMSW : 16; /* 1E.0002.F:0 RO */ - /* Bits 31 - 16 of Device ID */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Standard Device Identifier */ - union - { - struct - { - /*! \brief 1E.0003.F:0 RO Device ID LSW [F:0] - AQ_GlobalStandardDeviceIdentifier_HHD.u1.bits_1.deviceIdLSW - - - - Bits 15 - 0 of Device ID - */ - unsigned int deviceIdLSW : 16; /* 1E.0003.F:0 RO */ - /* Bits 15 - 0 of Device ID */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_GlobalStandardDeviceIdentifier_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Standard Devices in Package: 1E.0005 */ -/* Global Standard Devices in Package: 1E.0005 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Standard Devices in Package */ - union - { - struct - { - /*! \brief 1E.0005.0 ROS Clause 22 Registers Present - AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.clause_22RegistersPresent - - Default = 0x0 - - 1 = Clause 22 registers are present in package - 0 = Clause 22 registers are not present in package - - Notes: - This is always set to 0 in the PHY, as there are no Clause 22 registers in the device. */ - unsigned int clause_22RegistersPresent : 1; /* 1E.0005.0 ROS Default = 0x0 */ - /* 1 = Clause 22 registers are present in package - 0 = Clause 22 registers are not present in package */ - /*! \brief 1E.0005.1 ROS PMA Present - AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.pmaPresent - - Default = 0x1 - - 1 = PMA is present in package - 0 = PMA is not present - - Notes: - This is always set to 1 as there is PMA functionality in the PHY. */ - unsigned int pmaPresent : 1; /* 1E.0005.1 ROS Default = 0x1 */ - /* 1 = PMA is present in package - 0 = PMA is not present */ - /*! \brief 1E.0005.2 ROS WIS Present - AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.wisPresent - - Default = 0x0 - - 1 = WIS is present in package - 0 = WIS is not present in package - - Notes: - This is always set to 0, as there is no WIS functionality in the PHY. */ - unsigned int wisPresent : 1; /* 1E.0005.2 ROS Default = 0x0 */ - /* 1 = WIS is present in package - 0 = WIS is not present in package */ - /*! \brief 1E.0005.3 ROS PCS Present - AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.pcsPresent - - Default = 0x1 - - 1 = PCS is present in package - 0 = PCS is not present in package - - Notes: - This is always set to 1 as there is PCS functionality in the PHY. */ - unsigned int pcsPresent : 1; /* 1E.0005.3 ROS Default = 0x1 */ - /* 1 = PCS is present in package - 0 = PCS is not present in package */ - /*! \brief 1E.0005.4 ROS PHY XS Present - AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.phyXS_Present - - Default = 0x1 - - 1 = PHY XS is present in package - 0 = PHY XS is not present in package - - Notes: - This is always set to 1 as there is a PHY XS interface in the PHY. */ - unsigned int phyXS_Present : 1; /* 1E.0005.4 ROS Default = 0x1 */ - /* 1 = PHY XS is present in package - 0 = PHY XS is not present in package */ - /*! \brief 1E.0005.5 ROS DTE XS Present - AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.dteXsPresent - - Default = 0x0 - - 1 = DTE XS is present in package - 0 = DTE XS is not present in package - - - Notes: - This is always set to 0, as there is no DTE XAUI interface in the PHY. */ - unsigned int dteXsPresent : 1; /* 1E.0005.5 ROS Default = 0x0 */ - /* 1 = DTE XS is present in package - 0 = DTE XS is not present in package - */ - /*! \brief 1E.0005.6 ROS TC Present - AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.tcPresent - - Default = 0x0 - - 1 = TC is present in package - 0 = TC is not present in package - - Notes: - This is always set to 0, as there is no TC functionality in the PHY. */ - unsigned int tcPresent : 1; /* 1E.0005.6 ROS Default = 0x0 */ - /* 1 = TC is present in package - 0 = TC is not present in package */ - /*! \brief 1E.0005.7 ROS Autonegotiation Present - AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.autonegotiationPresent - - Default = 0x1 - - 1 = Autonegotiation is present in package - 0 = Autonegotiation is not present in package - - Notes: - This is always set to 1, as there is Autonegotiation in the PHY. */ - unsigned int autonegotiationPresent : 1; /* 1E.0005.7 ROS Default = 0x1 */ - /* 1 = Autonegotiation is present in package - 0 = Autonegotiation is not present in package */ - unsigned int reserved0 : 8; - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalStandardDevicesInPackage_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Standard Vendor Devices in Package: 1E.0006 */ -/* Global Standard Vendor Devices in Package: 1E.0006 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Standard Vendor Devices in Package */ - union - { - struct - { - unsigned int reserved0 : 13; - /*! \brief 1E.0006.D ROS Clause 22 Extension Present - AQ_GlobalStandardVendorDevicesInPackage_HHD.u0.bits_0.clause_22ExtensionPresent - - Default = 0x1 - - 1 = Clause 22 Extension is present in package - 0 = Clause 22 Extension is not present in package - - Notes: - This is always set to 1 as the PHY utilizes this device for the GbE registers. */ - unsigned int clause_22ExtensionPresent : 1; /* 1E.0006.D ROS Default = 0x1 */ - /* 1 = Clause 22 Extension is present in package - 0 = Clause 22 Extension is not present in package */ - /*! \brief 1E.0006.E ROS Vendor Specific Device #1 Present - AQ_GlobalStandardVendorDevicesInPackage_HHD.u0.bits_0.vendorSpecificDevice_1Present - - Default = 0x1 - - 1 = Device #1 is present in package - 0 = Device #1 is not present in package - - Notes: - This is always set to 1 as the PHY utilizes this device for the global control registers. */ - unsigned int vendorSpecificDevice_1Present : 1; /* 1E.0006.E ROS Default = 0x1 */ - /* 1 = Device #1 is present in package - 0 = Device #1 is not present in package */ - /*! \brief 1E.0006.F ROS Vendor Specific Device #2 Present - AQ_GlobalStandardVendorDevicesInPackage_HHD.u0.bits_0.vendorSpecificDevice_2Present - - Default = 0x1 - - 1 = Device #2 is present in package - 0 = Device #2 is not present in package - - Notes: - This is always set to 1 as the PHY utilizes this device for the DSP PMA registers. */ - unsigned int vendorSpecificDevice_2Present : 1; /* 1E.0006.F ROS Default = 0x1 */ - /* 1 = Device #2 is present in package - 0 = Device #2 is not present in package */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalStandardVendorDevicesInPackage_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Standard Status 2: 1E.0008 */ -/* Global Standard Status 2: 1E.0008 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Standard Status 2 */ - union - { - struct - { - unsigned int reserved0 : 14; - /*! \brief 1E.0008.F:E ROS Device Present [1:0] - AQ_GlobalStandardStatus_2_HHD.u0.bits_0.devicePresent - - Default = 0x2 - - [F:E] - 0x3 = No device at this address - 0x2 = Device present at this address - 0x1 = No device at this address - 0x0 = No device at this address - - Notes: - This field is always set to 0x2, as the Global MMD resides here in the PHY. */ - unsigned int devicePresent : 2; /* 1E.0008.F:E ROS Default = 0x2 */ - /* [F:E] - 0x3 = No device at this address - 0x2 = Device present at this address - 0x1 = No device at this address - 0x0 = No device at this address */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalStandardStatus_2_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Standard Package Identifier: 1E.000E */ -/* Global Standard Package Identifier: 1E.000E */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Standard Package Identifier */ - union - { - struct - { - /*! \brief 1E.000E.F:0 RO Package ID MSW [1F:10] - AQ_GlobalStandardPackageIdentifier_HHD.u0.bits_0.packageIdMSW - - - - Bits 31- 16 of Package ID - */ - unsigned int packageIdMSW : 16; /* 1E.000E.F:0 RO */ - /* Bits 31- 16 of Package ID */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Standard Package Identifier */ - union - { - struct - { - /*! \brief 1E.000F.F:0 RO Package ID LSW [F:0] - AQ_GlobalStandardPackageIdentifier_HHD.u1.bits_1.packageIdLSW - - - - Bits 15 - 0 of Package ID - */ - unsigned int packageIdLSW : 16; /* 1E.000F.F:0 RO */ - /* Bits 15 - 0 of Package ID */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_GlobalStandardPackageIdentifier_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Firmware ID: 1E.0020 */ -/* Global Firmware ID: 1E.0020 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Firmware ID */ - union - { - struct - { - /*! \brief 1E.0020.7:0 RO Firmware Minor Revision Number [7:0] - AQ_GlobalFirmwareID_HHD.u0.bits_0.firmwareMinorRevisionNumber - - - - [7:0] = Minor revision number - - Notes: - - - The lower six bits of major and minor firmware revision are exchanged in autonegotiation when the PHYID message is sent. */ - unsigned int firmwareMinorRevisionNumber : 8; /* 1E.0020.7:0 RO */ - /* [7:0] = Minor revision number */ - /*! \brief 1E.0020.F:8 RO Firmware Major Revision Number [7:0] - AQ_GlobalFirmwareID_HHD.u0.bits_0.firmwareMajorRevisionNumber - - - - [F:8] = Major revision number - - Notes: - - - The lower six bits of major and minor firmware revision are exchanged in autonegotiation when the PHYID message is sent. */ - unsigned int firmwareMajorRevisionNumber : 8; /* 1E.0020.F:8 RO */ - /* [F:8] = Major revision number */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalFirmwareID_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global NVR Interface: 1E.0100 */ -/* Global NVR Interface: 1E.0100 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global NVR Interface */ - union - { - struct - { - /*! \brief 1E.0100.7:0 R/W NVR Opcode [7:0] - AQ_GlobalNvrInterface_HHD.u0.bits_0.nvrOpcode - - Default = 0x03 - - NVR instruction opcode - - */ - unsigned int nvrOpcode : 8; /* 1E.0100.7:0 R/W Default = 0x03 */ - /* NVR instruction opcode - */ - /*! \brief 1E.0100.8 RO NVR Busy - AQ_GlobalNvrInterface_HHD.u0.bits_0.nvrBusy - - - - 1 = NVR is busy - 0 = NVR is ready - - - Notes: - When set to 1, the NVR is busy. A new NVR operation should not occur until this bit is 0. If the NVR clock is greater than 64/63 of the MDIO clock, this bit never needs to be polled when operating over the MDIO. */ - unsigned int nvrBusy : 1; /* 1E.0100.8 RO */ - /* 1 = NVR is busy - 0 = NVR is ready - */ - unsigned int reserved1 : 1; - /*! \brief 1E.0100.A R/W NVR Burst - AQ_GlobalNvrInterface_HHD.u0.bits_0.nvrBurst - - Default = 0x0 - - 0 = Single read or write operation of up to 4 bytes - 1 = Burst operation - - - Notes: - When this bit is set, the operation is a burst operation where more than 32-bits is read from the NVR or written to the NVR. This bit should be set to one until the last burst in the read or write operation, when it should be set to zero. It operates by gating the SPI clock, and not restarting it until new data is ready to be written, or the previous contents have been read. Each burst of data requires the NVR Execute Operation bit to be set to initiate the next phase. */ - unsigned int nvrBurst : 1; /* 1E.0100.A R/W Default = 0x0 */ - /* 0 = Single read or write operation of up to 4 bytes - 1 = Burst operation - */ - unsigned int reserved0 : 1; - /*! \brief 1E.0100.C R/WSC Reset NVR CRC - AQ_GlobalNvrInterface_HHD.u0.bits_0.resetNvrCrc - - Default = 0x0 - - 1 = Reset NVR Mailbox CRC calculation register - - - - Notes: - To prevent an erroneous answer, this bit should not be set at the same time the See NVR Operation Valid bit is set. */ - unsigned int resetNvrCrc : 1; /* 1E.0100.C R/WSC Default = 0x0 */ - /* 1 = Reset NVR Mailbox CRC calculation register - - */ - /*! \brief 1E.0100.D R/W Freeze NVR CRC - AQ_GlobalNvrInterface_HHD.u0.bits_0.freezeNvrCrc - - Default = 0x0 - - 1 = Freeze NVR Mailbox CRC calculation register - - - Notes: - To prevent an erroneous answer, this bit should not be set at the same time the See NVR Operation Valid bit is set. */ - unsigned int freezeNvrCrc : 1; /* 1E.0100.D R/W Default = 0x0 */ - /* 1 = Freeze NVR Mailbox CRC calculation register - */ - /*! \brief 1E.0100.E R/W NVR Write Mode - AQ_GlobalNvrInterface_HHD.u0.bits_0.nvrWriteMode - - Default = 0x0 - - 1 = Write to NVR - 0 = Read from NVR - - */ - unsigned int nvrWriteMode : 1; /* 1E.0100.E R/W Default = 0x0 */ - /* 1 = Write to NVR - 0 = Read from NVR - */ - /*! \brief 1E.0100.F R/WSC NVR Execute Operation - AQ_GlobalNvrInterface_HHD.u0.bits_0.nvrExecuteOperation - - Default = 0x0 - - 1 = Start NVR Operation - - - - Notes: - When set to 1, the NVR operation will begin. Ensure that the uP is stalled using the See MCP Run Stall bit to ensure no NVR contention. */ - unsigned int nvrExecuteOperation : 1; /* 1E.0100.F R/WSC Default = 0x0 */ - /* 1 = Start NVR Operation - - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global NVR Interface */ - union - { - struct - { - /*! \brief 1E.0101.F:0 RO NVR Mailbox CRC [F:0] - AQ_GlobalNvrInterface_HHD.u1.bits_1.nvrMailboxCrc - - - - The running CRC-16 of everything passing through the NVR interface - - - Notes: - The CRC-16 over all data written or read through the NVR interface. The CRC-16 is calculated by dividing the data by: - x^16 + x^12 + x^5 + 1 */ - unsigned int nvrMailboxCrc : 16; /* 1E.0101.F:0 RO */ - /* The running CRC-16 of everything passing through the NVR interface - */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global NVR Interface */ - union - { - struct - { - /*! \brief 1E.0102.7:0 R/W NVR Address MSW [17:10] - AQ_GlobalNvrInterface_HHD.u2.bits_2.nvrAddressMSW - - Default = 0x00 - - NVR address MSW bits [17:10] - - - Notes: - The address of where to read and write from in the NVR. This is self-incrementing and will automatically increment after each read or write operation. The increment amount is based on the data length (i.e. increments by 4 if the data length is 4 bytes) */ - unsigned int nvrAddressMSW : 8; /* 1E.0102.7:0 R/W Default = 0x00 */ - /* NVR address MSW bits [17:10] - */ - unsigned int reserved0 : 8; - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global NVR Interface */ - union - { - struct - { - /*! \brief 1E.0103.F:0 R/W NVR Address LSW [F:0] - AQ_GlobalNvrInterface_HHD.u3.bits_3.nvrAddressLSW - - Default = 0x0000 - - NVR address LSW bits [F:0] - - - Notes: - The address of where to read and write from in the NVR. This is self-incrementing and will automatically increment after each read or write operation. */ - unsigned int nvrAddressLSW : 16; /* 1E.0103.F:0 R/W Default = 0x0000 */ - /* NVR address LSW bits [F:0] - */ - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of Global NVR Interface */ - union - { - struct - { - /*! \brief 1E.0104.F:0 R/W NVR Data MSW [1F:10] - AQ_GlobalNvrInterface_HHD.u4.bits_4.nvrDataMSW - - Default = 0x0000 - - NVR data MSW bits [1F:10] - - - Notes: - Data is stored and read-out from these registers in little-endian format for operations such as FLASH device ID, and for programming the processor. - - For instance the 64K Atmel device code reads out as two bytes 0x651F into the LSW register, whereas the datasheet indicates that 1F is the first byte read, followed by 65 as the second byte. - - To burst read and write these 4 bytes in the correct order (where DD is written to address x), they should be stored as: - - AA BB in the MSW - CC DD in the LSW. */ - unsigned int nvrDataMSW : 16; /* 1E.0104.F:0 R/W Default = 0x0000 */ - /* NVR data MSW bits [1F:10] - */ - } bits_4; - uint16_t word_4; - } u4; - /*! \brief Union for bit and word level access of word 5 of Global NVR Interface */ - union - { - struct - { - /*! \brief 1E.0105.F:0 R/W NVR Data LSW [F:0] - AQ_GlobalNvrInterface_HHD.u5.bits_5.nvrDataLSW - - Default = 0x0000 - - NVR data LSW bits [F:0] - - - Notes: - Data is stored and read-out from these registers in little-endian format for operations such as FLASH device ID, and for programming the processor. - - For instance the 64K Atmel device code reads out as two bytes 0x651F into the LSW register, whereas the datasheet indicates that 1F is the first byte read, followed by 65 as the second byte. - To burst read and write these 4 bytes in the correct order (where DD is written to address x), they should be stored as: - - AA BB in the MSW - CC DD in the LSW. */ - unsigned int nvrDataLSW : 16; /* 1E.0105.F:0 R/W Default = 0x0000 */ - /* NVR data LSW bits [F:0] - */ - } bits_5; - uint16_t word_5; - } u5; -} AQ_GlobalNvrInterface_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Mailbox Interface: 1E.0200 */ -/* Global Mailbox Interface: 1E.0200 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Mailbox Interface */ - union - { - struct - { - unsigned int reserved2 : 8; - /*! \brief 1E.0200.8 RO uP Mailbox Busy - AQ_GlobalMailboxInterface_HHD.u0.bits_0.upMailboxBusy - - - - 1 = uP mailbox busy - 0 = uP mailbox ready - - - Notes: - In general the uP will respond within a few processor cycles to any PIF slave request, much faster than the MDIO. If the busy is asserted over multiple MDIO polling cycles, then a H/W error may have occurred and a Global S/W reset or uP reset is required. */ - unsigned int upMailboxBusy : 1; /* 1E.0200.8 RO */ - /* 1 = uP mailbox busy - 0 = uP mailbox ready - */ - unsigned int reserved1 : 3; - /*! \brief 1E.0200.C R/WSC Reset uP Mailbox CRC - AQ_GlobalMailboxInterface_HHD.u0.bits_0.resetUpMailboxCrc - - Default = 0x0 - - 1 = Reset uP mailbox CRC calculation register - - - */ - unsigned int resetUpMailboxCrc : 1; /* 1E.0200.C R/WSC Default = 0x0 */ - /* 1 = Reset uP mailbox CRC calculation register - - */ - unsigned int reserved0 : 1; - /*! \brief 1E.0200.E R/W uP Mailbox Write Mode - AQ_GlobalMailboxInterface_HHD.u0.bits_0.upMailboxWriteMode - - Default = 0x0 - - 1 = Write - 0 = Read - - - Notes: - Mailbox direction */ - unsigned int upMailboxWriteMode : 1; /* 1E.0200.E R/W Default = 0x0 */ - /* 1 = Write - 0 = Read - */ - /*! \brief 1E.0200.F R/WSC uP Mailbox Execute Operation - AQ_GlobalMailboxInterface_HHD.u0.bits_0.upMailboxExecuteOperation - - Default = 0x0 - - 1 = Start of mailbox Operation - - - - Notes: - Indicates mailbox is loaded and ready */ - unsigned int upMailboxExecuteOperation : 1; /* 1E.0200.F R/WSC Default = 0x0 */ - /* 1 = Start of mailbox Operation - - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Mailbox Interface */ - union - { - struct - { - /*! \brief 1E.0201.F:0 RO uP Mailbox CRC [F:0] - AQ_GlobalMailboxInterface_HHD.u1.bits_1.upMailboxCrc - - - - The running CRC-16 of everything passing through the mailbox interface - - */ - unsigned int upMailboxCrc : 16; /* 1E.0201.F:0 RO */ - /* The running CRC-16 of everything passing through the mailbox interface - */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global Mailbox Interface */ - union - { - struct - { - /*! \brief 1E.0202.F:0 R/W uP Mailbox Address MSW [1F:10] - AQ_GlobalMailboxInterface_HHD.u2.bits_2.upMailboxAddressMSW - - Default = 0x0000 - - uP Mailbox MSW address - - - Notes: - The address of where to read and write from in the Microcontroller Mailbox. This is self-incrementing and automatically increments after each read and write operation.PHY */ - unsigned int upMailboxAddressMSW : 16; /* 1E.0202.F:0 R/W Default = 0x0000 */ - /* uP Mailbox MSW address - */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global Mailbox Interface */ - union - { - struct - { - /*! \brief 1E.0203.1:0 RO uP Mailbox Address LSW Don't Care [1:0] - AQ_GlobalMailboxInterface_HHD.u3.bits_3.upMailboxAddressLSW_Don_tCare - - - - Least significant uP LSW Mailbox address bits [1:0] - - - Notes: - These bits are always set to 0 since each memory access is on a 4-byte boundary. */ - unsigned int upMailboxAddressLSW_Don_tCare : 2; /* 1E.0203.1:0 RO */ - /* Least significant uP LSW Mailbox address bits [1:0] - */ - /*! \brief 1E.0203.F:2 R/W uP Mailbox Address LSW [F:2] - AQ_GlobalMailboxInterface_HHD.u3.bits_3.upMailboxAddressLSW - - Default = 0x0000 - - uP LSW Mailbox address [F:2] - - - Notes: - The address of where to read and write from in the Microcontroller Mailbox. This is self-incrementing and automatically increments after each read and write operation.PHY */ - unsigned int upMailboxAddressLSW : 14; /* 1E.0203.F:2 R/W Default = 0x0000 */ - /* uP LSW Mailbox address [F:2] - */ - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of Global Mailbox Interface */ - union - { - struct - { - /*! \brief 1E.0204.F:0 R/W uP Mailbox Data MSW [1F:10] - AQ_GlobalMailboxInterface_HHD.u4.bits_4.upMailboxDataMSW - - Default = 0x0000 - - uP Mailbox data MSW - - */ - unsigned int upMailboxDataMSW : 16; /* 1E.0204.F:0 R/W Default = 0x0000 */ - /* uP Mailbox data MSW - */ - } bits_4; - uint16_t word_4; - } u4; - /*! \brief Union for bit and word level access of word 5 of Global Mailbox Interface */ - union - { - struct - { - /*! \brief 1E.0205.F:0 R/W uP Mailbox Data LSW [F:0] - AQ_GlobalMailboxInterface_HHD.u5.bits_5.upMailboxDataLSW - - Default = 0x0000 - - uP Mailbox data LSW - - */ - unsigned int upMailboxDataLSW : 16; /* 1E.0205.F:0 R/W Default = 0x0000 */ - /* uP Mailbox data LSW - */ - } bits_5; - uint16_t word_5; - } u5; - /*! \brief Union for bit and word level access of word 6 of Global Mailbox Interface */ - union - { - struct - { - unsigned int reserved1 : 1; - /*! \brief 1E.0206.1 R/W uP Mailbox CRC Read Enable - AQ_GlobalMailboxInterface_HHD.u6.bits_6.upMailboxCrcReadEnable - - Default = 0x0 - - 1 = Update uP mailbox CRC on read - - */ - unsigned int upMailboxCrcReadEnable : 1; /* 1E.0206.1 R/W Default = 0x0 */ - /* 1 = Update uP mailbox CRC on read - */ - unsigned int reserved0 : 14; - } bits_6; - uint16_t word_6; - } u6; -} AQ_GlobalMailboxInterface_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Microprocessor Scratch Pad: 1E.0300 */ -/* Global Microprocessor Scratch Pad: 1E.0300 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Microprocessor Scratch Pad */ - union - { - struct - { - /*! \brief 1E.0300.F:0 R/W Scratch Pad 1[F:0] - AQ_GlobalMicroprocessorScratchPad_HHD.u0.bits_0.scratchPad_1 - - Default = 0x0000 - - General Purpose Scratch Pad - */ - unsigned int scratchPad_1 : 16; /* 1E.0300.F:0 R/W Default = 0x0000 */ - /* General Purpose Scratch Pad */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Microprocessor Scratch Pad */ - union - { - struct - { - /*! \brief 1E.0301.F:0 R/W Scratch Pad 2 [F:0] - AQ_GlobalMicroprocessorScratchPad_HHD.u1.bits_1.scratchPad_2 - - Default = 0x0000 - - General Purpose Scratch Pad - */ - unsigned int scratchPad_2 : 16; /* 1E.0301.F:0 R/W Default = 0x0000 */ - /* General Purpose Scratch Pad */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_GlobalMicroprocessorScratchPad_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Egress Control Register: 1E.5002 */ -/* MSS Egress Control Register: 1E.5002 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Egress Control Register */ - union - { - struct - { - /*! \brief 1E.5002.0 R/W MSS Egress Soft Reset - AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressSoftReset - - Default = 0x0 - - 1 = Soft reset - - - Notes: - S/W reset */ - unsigned int mssEgressSoftReset : 1; /* 1E.5002.0 R/W Default = 0x0 */ - /* 1 = Soft reset - */ - /*! \brief 1E.5002.1 R/W MSS Egress Drop KAY Packet - AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressDropKayPacket - - Default = 0x0 - - 1 = Drop KAY packet - - - Notes: - Decides whether KAY packets have to be dropped */ - unsigned int mssEgressDropKayPacket : 1; /* 1E.5002.1 R/W Default = 0x0 */ - /* 1 = Drop KAY packet - */ - /*! \brief 1E.5002.2 R/W MSS Egress Drop EGPRC LUT Miss - AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressDropEgprcLutMiss - - Default = 0x0 - - 1 = Drop Egress Classification LUT miss packets - - - - Notes: - Decides whether Egress Pre-Security Classification (EGPRC) LUT miss packets are to be dropped */ - unsigned int mssEgressDropEgprcLutMiss : 1; /* 1E.5002.2 R/W Default = 0x0 */ - /* 1 = Drop Egress Classification LUT miss packets - - */ - /*! \brief 1E.5002.3 R/W MSS Egress GCM Start - AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressGcmStart - - Default = 0x0 - - 1 = Start GCM - - - - Notes: - Indicates GCM to start */ - unsigned int mssEgressGcmStart : 1; /* 1E.5002.3 R/W Default = 0x0 */ - /* 1 = Start GCM - - */ - /*! \brief 1E.5002.4 R/W MSS Egresss GCM Test Mode - AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgresssGcmTestMode - - Default = 0x0 - - 1 = Enable GCM test mode - - - - Notes: - Enables GCM test mode */ - unsigned int mssEgresssGcmTestMode : 1; /* 1E.5002.4 R/W Default = 0x0 */ - /* 1 = Enable GCM test mode - - */ - /*! \brief 1E.5002.5 R/W MSS Egress Unmatched Use SC 0 - AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressUnmatchedUseSc_0 - - Default = 0x0 - - 1 = Use SC 0 for unmatched packets - 0 = Unmatched packets are uncontrolled packets - - - - Notes: - Use SC-Index 0 as default SC for unmatched packets. Otherwise the packets are treated as uncontrolled packets. */ - unsigned int mssEgressUnmatchedUseSc_0 : 1; /* 1E.5002.5 R/W Default = 0x0 */ - /* 1 = Use SC 0 for unmatched packets - 0 = Unmatched packets are uncontrolled packets - - */ - /*! \brief 1E.5002.6 R/W MSS Egress Drop Invalid SA/SC Packets - AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressDropInvalidSa_scPackets - - Default = 0x0 - - 1 = Drop invalid SA/SC packets - - - - Notes: - Enables dropping of invalid SA/SC packets. */ - unsigned int mssEgressDropInvalidSa_scPackets : 1; /* 1E.5002.6 R/W Default = 0x0 */ - /* 1 = Drop invalid SA/SC packets - - */ - /*! \brief 1E.5002.7 R/W MSS Egress Explicit SECTag Report Short Length - AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressExplicitSectagReportShortLength - - Default = 0x0 - - Reserved - - - - Notes: - Unused. */ - unsigned int mssEgressExplicitSectagReportShortLength : 1; /* 1E.5002.7 R/W Default = 0x0 */ - /* Reserved - - */ - /*! \brief 1E.5002.8 R/W MSS Egress External Classification Enable - AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressExternalClassificationEnable - - Default = 0x0 - - 1 = Drop EGPRC miss packets - - - - Notes: - If set, internal classification is bypassed. Should always be set to 0. */ - unsigned int mssEgressExternalClassificationEnable : 1; /* 1E.5002.8 R/W Default = 0x0 */ - /* 1 = Drop EGPRC miss packets - - */ - /*! \brief 1E.5002.9 R/W MSS Egress ICV LSB 8 Bytes Enable - AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressIcvLsb_8BytesEnable - - Default = 0x0 - - 1 = Use LSB - 0 = Use MSB - - - - Notes: - This bit selects MSB or LSB 8 bytes selection in the case where the ICV is 8 bytes. - 0 = MSB is used. */ - unsigned int mssEgressIcvLsb_8BytesEnable : 1; /* 1E.5002.9 R/W Default = 0x0 */ - /* 1 = Use LSB - 0 = Use MSB - - */ - /*! \brief 1E.5002.A R/W MSS Egress High Priority - AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressHighPriority - - Default = 0x0 - - 1 = MIB counter clear on read enable - - - - Notes: - If this bit is set to 1, read is given high priority and the MIB count value becomes 0 after read. */ - unsigned int mssEgressHighPriority : 1; /* 1E.5002.A R/W Default = 0x0 */ - /* 1 = MIB counter clear on read enable - - */ - /*! \brief 1E.5002.B R/W MSS Egress Clear Counter - AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressClearCounter - - Default = 0x0 - - 1 = Clear all MIB counters - - - - Notes: - If this bit is set to 1, all MIB counters will be cleared. */ - unsigned int mssEgressClearCounter : 1; /* 1E.5002.B R/W Default = 0x0 */ - /* 1 = Clear all MIB counters - - */ - /*! \brief 1E.5002.C R/W MSS Egress Clear Global Time - AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressClearGlobalTime - - Default = 0x0 - - 1 = Clear global time - - - - Notes: - Clear global time. */ - unsigned int mssEgressClearGlobalTime : 1; /* 1E.5002.C R/W Default = 0x0 */ - /* 1 = Clear global time - - */ - /*! \brief 1E.5002.F:D R/W MSS Egress Ethertype Explicit SECTag LSB [2:0] - AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressEthertypeExplicitSectagLsb - - Default = 0x0 - - Ethertype for explicit SECTag bits 2:0. - - - Notes: - Ethertype for explicity SECTag. */ - unsigned int mssEgressEthertypeExplicitSectagLsb : 3; /* 1E.5002.F:D R/W Default = 0x0 */ - /* Ethertype for explicit SECTag bits 2:0. - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Egress Control Register */ - union - { - struct - { - /*! \brief 1E.5003.C:0 R/W MSS Egress Ethertype Explicit SECTag MSB [F:3] - AQ_MssEgressControlRegister_HHD.u1.bits_1.mssEgressEthertypeExplicitSectagMsb - - Default = 0x0000 - - Ethertype for explicit SECTag bits 15:3. - - - Notes: - Ethertype for explicity SECTag. */ - unsigned int mssEgressEthertypeExplicitSectagMsb : 13; /* 1E.5003.C:0 R/W Default = 0x0000 */ - /* Ethertype for explicit SECTag bits 15:3. - */ - unsigned int reserved0 : 3; - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssEgressControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Egress VLAN TPID 0 Register: 1E.5008 */ -/* MSS Egress VLAN TPID 0 Register: 1E.5008 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Egress VLAN TPID 0 Register */ - union - { - struct - { - /*! \brief 1E.5008.F:0 R/W MSS Egress VLAN STag TPID [F:0] - AQ_MssEgressVlanTpid_0Register_HHD.u0.bits_0.mssEgressVlanStagTpid - - Default = 0x0000 - - STag TPID - - - Notes: - Service Tag Protocol Identifier (TPID) values to identify a VLAN tag. The " See SEC Egress VLAN CP Tag Parse STag " bit must be set to 1 for the incoming packet's TPID to be parsed. */ - unsigned int mssEgressVlanStagTpid : 16; /* 1E.5008.F:0 R/W Default = 0x0000 */ - /* STag TPID - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Egress VLAN TPID 0 Register */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssEgressVlanTpid_0Register_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Egress VLAN TPID 1 Register: 1E.500A */ -/* MSS Egress VLAN TPID 1 Register: 1E.500A */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Egress VLAN TPID 1 Register */ - union - { - struct - { - /*! \brief 1E.500A.F:0 R/W MSS Egress VLAN QTag TPID [F:0] - AQ_MssEgressVlanTpid_1Register_HHD.u0.bits_0.mssEgressVlanQtagTpid - - Default = 0x0000 - - QTag TPID - - - Notes: - Customer Tag Protocol Identifier (TPID) values to identify a VLAN tag. The " See SEC Egress VLAN CP Tag Parse QTag " bit must be set to 1 for the incoming packet's TPID to be parsed. */ - unsigned int mssEgressVlanQtagTpid : 16; /* 1E.500A.F:0 R/W Default = 0x0000 */ - /* QTag TPID - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Egress VLAN TPID 1 Register */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssEgressVlanTpid_1Register_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Egress VLAN Control Register: 1E.500C */ -/* MSS Egress VLAN Control Register: 1E.500C */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Egress VLAN Control Register */ - union - { - struct - { - /*! \brief 1E.500C.F:0 R/W MSS Egress VLAN UP Map Table [F:0] - AQ_MssEgressVlanControlRegister_HHD.u0.bits_0.mssEgressVlanUpMapTable - - Default = 0x0000 - - UP Map table bits 15:0 - - - Notes: - If there is a customer TPID Tag match and no service TPID Tag match or the service TPID Tag match is disabled, the outer TAG's PCP is used to index into this map table to generate the packets user priority. - 2:0 : UP value for customer Tag PCP 0x0 - 5:3: UP value for customer Tag PCP 0x0 - 8:6 : UP value for customer Tag PCP 0x0 - 11:9 : UP value for customer Tag PCP 0x0 - 14:12 : UP value for customer Tag PCP 0x0 - 17:15 : UP value for customer Tag PCP 0x0 - 20:18 : UP value for customer Tag PCP 0x0 - 23:21 : UP value for customer Tag PCP 0x0 */ - unsigned int mssEgressVlanUpMapTable : 16; /* 1E.500C.F:0 R/W Default = 0x0000 */ - /* UP Map table bits 15:0 - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Egress VLAN Control Register */ - union - { - struct - { - /*! \brief 1E.500D.7:0 R/W MSS Egress VLAN UP Map Table MSW [17:10] - AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanUpMapTableMSW - - Default = 0x00 - - UP Map table bits 23:16 - - - Notes: - If there is a customer TPID Tag match and no service TPID Tag match or the service TPID Tag match is disabled, the outer TAG's PCP is used to index into this map table to generate the packets user priority. - 2:0 : UP value for customer Tag PCP 0x0 - 5:3: UP value for customer Tag PCP 0x0 - 8:6 : UP value for customer Tag PCP 0x0 - 11:9 : UP value for customer Tag PCP 0x0 - 14:12 : UP value for customer Tag PCP 0x0 - 17:15 : UP value for customer Tag PCP 0x0 - 20:18 : UP value for customer Tag PCP 0x0 - 23:21 : UP value for customer Tag PCP 0x0 */ - unsigned int mssEgressVlanUpMapTableMSW : 8; /* 1E.500D.7:0 R/W Default = 0x00 */ - /* UP Map table bits 23:16 - */ - /*! \brief 1E.500D.A:8 R/W MSS Egress VLAN UP Default [2:0] - AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanUpDefault - - Default = 0x0 - - UP default - - - Notes: - User priority default */ - unsigned int mssEgressVlanUpDefault : 3; /* 1E.500D.A:8 R/W Default = 0x0 */ - /* UP default - */ - /*! \brief 1E.500D.B R/W MSS Egress VLAN STag UP Parse Enable - AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanStagUpParseEnable - - Default = 0x0 - - VLAN CP Tag STag UP enable - - - Notes: - Enable controlled port service VLAN service Tag user priority field parsing. */ - unsigned int mssEgressVlanStagUpParseEnable : 1; /* 1E.500D.B R/W Default = 0x0 */ - /* VLAN CP Tag STag UP enable - */ - /*! \brief 1E.500D.C R/W MSS Egress VLAN QTag UP Parse Enable - AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanQtagUpParseEnable - - Default = 0x0 - - VLAN CP Tag QTag UP enable - - - Notes: - Enable controlled port customer VLAN customer Tag user priority field parsing. */ - unsigned int mssEgressVlanQtagUpParseEnable : 1; /* 1E.500D.C R/W Default = 0x0 */ - /* VLAN CP Tag QTag UP enable - */ - /*! \brief 1E.500D.D R/W MSS Egress VLAN QinQ Parse Enable - AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanQinqParseEnable - - Default = 0x0 - - VLAN CP Tag Parse QinQ - - - Notes: - Enable controlled port VLAN QinQ Tag parsing. When this bit is set to 1 both the outer and inner VLAN Tags will be parsed. */ - unsigned int mssEgressVlanQinqParseEnable : 1; /* 1E.500D.D R/W Default = 0x0 */ - /* VLAN CP Tag Parse QinQ - */ - /*! \brief 1E.500D.E R/W MSS Egress VLAN STag Parse Enable - AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanStagParseEnable - - Default = 0x0 - - 1 = Enable VLAN STag parsing - - - Notes: - Enable controlled port VLAN service Tag parsing. When this bit is set to 1, the incoming packets outer TPID will be compared with the configured " See SEC Egress TPID 0 [F:0] " for matching. If the " See SEC Egress VLAN CP Tag Parse QinQ " bit is set to1, this will also be used to compare the incoming packet's inner TPID. */ - unsigned int mssEgressVlanStagParseEnable : 1; /* 1E.500D.E R/W Default = 0x0 */ - /* 1 = Enable VLAN STag parsing - */ - /*! \brief 1E.500D.F R/W MSS Egress VLAN QTag Parse Enable - AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanQtagParseEnable - - Default = 0x0 - - 1 = Enable VLAN QTag parsing - - - Notes: - Enable controlled port VLAN customer Tag parsing. When this bit is set to 1, the incoming packet's outer TPID will be compared with the configured " See SEC Egress TPID 1 [F:0] " for matching. If the " See SEC Egress VLAN CP Tag Parse QinQ " bit is set to1, this will also be used to compare the incoming packet's inner TPID. */ - unsigned int mssEgressVlanQtagParseEnable : 1; /* 1E.500D.F R/W Default = 0x0 */ - /* 1 = Enable VLAN QTag parsing - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssEgressVlanControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Egress PN Control Register: 1E.500E */ -/* MSS Egress PN Control Register: 1E.500E */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Egress PN Control Register */ - union - { - struct - { - /*! \brief 1E.500E.F:0 R/W MSS Egress SA PN Threshold LSW [F:0] - AQ_MssEgressPnControlRegister_HHD.u0.bits_0.mssEgressSaPnThresholdLSW - - Default = 0x0000 - - PN threshold bits 15:0 - - - Notes: - Egress PN threshold to generate SA threshold interrupt. */ - unsigned int mssEgressSaPnThresholdLSW : 16; /* 1E.500E.F:0 R/W Default = 0x0000 */ - /* PN threshold bits 15:0 - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Egress PN Control Register */ - union - { - struct - { - /*! \brief 1E.500F.F:0 R/W MSS Egress SA PN Threshold MSW [1F:10] - AQ_MssEgressPnControlRegister_HHD.u1.bits_1.mssEgressSaPnThresholdMSW - - Default = 0x0000 - - PN threshold bits 31:16 - - - Notes: - Egress PN threshold to generate SA threshold interrupt. */ - unsigned int mssEgressSaPnThresholdMSW : 16; /* 1E.500F.F:0 R/W Default = 0x0000 */ - /* PN threshold bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssEgressPnControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Egress MTU Size Control Register: 1E.5010 */ -/* MSS Egress MTU Size Control Register: 1E.5010 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Egress MTU Size Control Register */ - union - { - struct - { - /*! \brief 1E.5010.F:0 R/W MSS Egress Controlled Packet MTU Size [F:0] - AQ_MssEgressMtuSizeControlRegister_HHD.u0.bits_0.mssEgressControlledPacketMtuSize - - Default = 0x05DC - - Maximum transmission unit for controlled packet - - - Notes: - Maximum transmission unit of controlled packet */ - unsigned int mssEgressControlledPacketMtuSize : 16; /* 1E.5010.F:0 R/W Default = 0x05DC */ - /* Maximum transmission unit for controlled packet - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Egress MTU Size Control Register */ - union - { - struct - { - /*! \brief 1E.5011.F:0 R/W MSS Egress Uncontrolled Packet MTU Size [F:0] - AQ_MssEgressMtuSizeControlRegister_HHD.u1.bits_1.mssEgressUncontrolledPacketMtuSize - - Default = 0x05DC - - Maximum transmission unit for uncontrolled packet - - - Notes: - Maximum transmission unit of uncontrolled packet */ - unsigned int mssEgressUncontrolledPacketMtuSize : 16; /* 1E.5011.F:0 R/W Default = 0x05DC */ - /* Maximum transmission unit for uncontrolled packet - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssEgressMtuSizeControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Egress Interrupt Status Register: 1E.505C */ -/* MSS Egress Interrupt Status Register: 1E.505C */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Egress Interrupt Status Register */ - union - { - struct - { - /*! \brief 1E.505C.0 COW MSS Egress Master Interrupt - AQ_MssEgressInterruptStatusRegister_HHD.u0.bits_0.mssEgressMasterInterrupt - - Default = 0x0 - - 1 = Interrupt - - - Notes: - Write to 1 to clear. This bit is set when any one of the above interrupt and the corresponding interrupt enable are both set. The interrupt enable for this bit must also be set for this bit to be set. */ - unsigned int mssEgressMasterInterrupt : 1; /* 1E.505C.0 COW Default = 0x0 */ - /* 1 = Interrupt - */ - /*! \brief 1E.505C.1 COW MSS Egress SA Expired Interrupt - AQ_MssEgressInterruptStatusRegister_HHD.u0.bits_0.mssEgressSaExpiredInterrupt - - Default = 0x0 - - 1 = Interrupt - - - Notes: - Write to 1 to clear. This bit is set when the SA PN reaches all ones saturation. */ - unsigned int mssEgressSaExpiredInterrupt : 1; /* 1E.505C.1 COW Default = 0x0 */ - /* 1 = Interrupt - */ - /*! \brief 1E.505C.2 COW MSS Egress SA Threshold Expired Interrupt - AQ_MssEgressInterruptStatusRegister_HHD.u0.bits_0.mssEgressSaThresholdExpiredInterrupt - - Default = 0x0 - - 1 = Interrupt - - - Notes: - Write to 1 to clear. This bit is set when the SA PN reaches the See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . */ - unsigned int mssEgressSaThresholdExpiredInterrupt : 1; /* 1E.505C.2 COW Default = 0x0 */ - /* 1 = Interrupt - */ - /*! \brief 1E.505C.3 COW MSS Egress MIB Saturation Interrupt - AQ_MssEgressInterruptStatusRegister_HHD.u0.bits_0.mssEgressMibSaturationInterrupt - - Default = 0x0 - - 1 = Interrupt - - - Notes: - Write to 1 to clear. This bit is set when the MIB counters reaches all ones saturation. */ - unsigned int mssEgressMibSaturationInterrupt : 1; /* 1E.505C.3 COW Default = 0x0 */ - /* 1 = Interrupt - */ - /*! \brief 1E.505C.4 COW MSS Egress ECC Error Interrupt - AQ_MssEgressInterruptStatusRegister_HHD.u0.bits_0.mssEgressEccErrorInterrupt - - Default = 0x0 - - 1 = Interrupt - - - Notes: - Write to 1 to clear. This bit is set when anyone of the memories detects an ECC error. */ - unsigned int mssEgressEccErrorInterrupt : 1; /* 1E.505C.4 COW Default = 0x0 */ - /* 1 = Interrupt - */ - unsigned int reserved0 : 11; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Egress Interrupt Status Register */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssEgressInterruptStatusRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Egress Interrupt Mask Register: 1E.505E */ -/* MSS Egress Interrupt Mask Register: 1E.505E */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Egress Interrupt Mask Register */ - union - { - struct - { - /*! \brief 1E.505E.0 COW MSS Egress Master Interrupt Enable - AQ_MssEgressInterruptMaskRegister_HHD.u0.bits_0.mssEgressMasterInterruptEnable - - Default = 0x0 - - 1 = Interrupt enabled - - - Notes: - Write to 1 to clear. */ - unsigned int mssEgressMasterInterruptEnable : 1; /* 1E.505E.0 COW Default = 0x0 */ - /* 1 = Interrupt enabled - */ - /*! \brief 1E.505E.1 COW MSS Egress SA Expired Interrupt Enable - AQ_MssEgressInterruptMaskRegister_HHD.u0.bits_0.mssEgressSaExpiredInterruptEnable - - Default = 0x0 - - 1 = Interrupt enabled - - - Notes: - Write to 1 to clear. This bit is set when the SA PN reaches all ones saturation. */ - unsigned int mssEgressSaExpiredInterruptEnable : 1; /* 1E.505E.1 COW Default = 0x0 */ - /* 1 = Interrupt enabled - */ - /*! \brief 1E.505E.2 COW MSS Egress SA Expired Threshold Interrupt Enable - AQ_MssEgressInterruptMaskRegister_HHD.u0.bits_0.mssEgressSaExpiredThresholdInterruptEnable - - Default = 0x0 - - 1 = Interrupt enabled - - - Notes: - Write to 1 to clear. This bit is set when the SA PN reaches the configured threshold See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . */ - unsigned int mssEgressSaExpiredThresholdInterruptEnable : 1; /* 1E.505E.2 COW Default = 0x0 */ - /* 1 = Interrupt enabled - */ - /*! \brief 1E.505E.3 COW MSS Egress MIB Saturation Interrupt Enable - AQ_MssEgressInterruptMaskRegister_HHD.u0.bits_0.mssEgressMibSaturationInterruptEnable - - Default = 0x0 - - 1 = Interrupt enabled - - - Notes: - Write to 1 to clear. This bit is set when the MIB counters reaches all ones saturation. */ - unsigned int mssEgressMibSaturationInterruptEnable : 1; /* 1E.505E.3 COW Default = 0x0 */ - /* 1 = Interrupt enabled - */ - /*! \brief 1E.505E.4 COW MSS Egress ECC Error Interrupt Enable - AQ_MssEgressInterruptMaskRegister_HHD.u0.bits_0.mssEgressEccErrorInterruptEnable - - Default = 0x0 - - 1 = Interrupt enabled - - - Notes: - Write to 1 to clear. This bit is set when anyone of the memories detects an ECC error. */ - unsigned int mssEgressEccErrorInterruptEnable : 1; /* 1E.505E.4 COW Default = 0x0 */ - /* 1 = Interrupt enabled - */ - unsigned int reserved0 : 11; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Egress Interrupt Mask Register */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssEgressInterruptMaskRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Egress SA Expired Status Register: 1E.5060 */ -/* MSS Egress SA Expired Status Register: 1E.5060 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Egress SA Expired Status Register */ - union - { - struct - { - /*! \brief 1E.5060.F:0 COW MSS Egress SA Expired LSW [F:0] - AQ_MssEgressSaExpiredStatusRegister_HHD.u0.bits_0.mssEgressSaExpiredLSW - - Default = 0x0000 - - SA expired bits 15:0 - - - Notes: - Write these bits to 1 to clear. - When set, these bits identify the SA that has expired when the SA PN reaches all-ones saturation. */ - unsigned int mssEgressSaExpiredLSW : 16; /* 1E.5060.F:0 COW Default = 0x0000 */ - /* SA expired bits 15:0 - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Egress SA Expired Status Register */ - union - { - struct - { - /*! \brief 1E.5061.F:0 COW MSS Egress SA Expired MSW [1F:10] - AQ_MssEgressSaExpiredStatusRegister_HHD.u1.bits_1.mssEgressSaExpiredMSW - - Default = 0x0000 - - SA expired bits 31:16 - - - Notes: - Write these bits to 1 to clear. - When set, these bits identify the SA that has expired when the SA PN reaches all-ones saturation. */ - unsigned int mssEgressSaExpiredMSW : 16; /* 1E.5061.F:0 COW Default = 0x0000 */ - /* SA expired bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssEgressSaExpiredStatusRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Egress SA Threshold Expired Status Register: 1E.5062 */ -/* MSS Egress SA Threshold Expired Status Register: 1E.5062 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Egress SA Threshold Expired Status Register */ - union - { - struct - { - /*! \brief 1E.5062.F:0 COW MSS Egress SA Threshold Expired LSW [F:0] - AQ_MssEgressSaThresholdExpiredStatusRegister_HHD.u0.bits_0.mssEgressSaThresholdExpiredLSW - - Default = 0x0000 - - SA threshold expired bits 15:0 - - - Notes: - Write these bits to 1 to clear. - When set, these bits identify the SA that has expired when the SA PN has reached the configured threshold See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . */ - unsigned int mssEgressSaThresholdExpiredLSW : 16; /* 1E.5062.F:0 COW Default = 0x0000 */ - /* SA threshold expired bits 15:0 - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Egress SA Threshold Expired Status Register */ - union - { - struct - { - /*! \brief 1E.5063.F:0 COW MSS Egress SA Threshold Expired MSW [1F:10] - AQ_MssEgressSaThresholdExpiredStatusRegister_HHD.u1.bits_1.mssEgressSaThresholdExpiredMSW - - Default = 0x0000 - - SA threshold expired bits 31:16 - - - Notes: - Write these bits to 1 to clear. - When set, these bits identify the SA that has expired when the SA PN has reached the configured threshold See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . */ - unsigned int mssEgressSaThresholdExpiredMSW : 16; /* 1E.5063.F:0 COW Default = 0x0000 */ - /* SA threshold expired bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssEgressSaThresholdExpiredStatusRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Egress ECC Interrupt Status Register: 1E.5064 */ -/* MSS Egress ECC Interrupt Status Register: 1E.5064 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Egress ECC Interrupt Status Register */ - union - { - struct - { - /*! \brief 1E.5064.F:0 COW MSS Egress SA ECC Error Interrupt LSW [F:0] - AQ_MssEgressEccInterruptStatusRegister_HHD.u0.bits_0.mssEgressSaEccErrorInterruptLSW - - Default = 0x0000 - - SA ECC error interrupt bits 15:0 - - - Notes: - Write these bits to 1 to clear. - When set to 1, indicates that an ECC error occured for the SA. */ - unsigned int mssEgressSaEccErrorInterruptLSW : 16; /* 1E.5064.F:0 COW Default = 0x0000 */ - /* SA ECC error interrupt bits 15:0 - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Egress ECC Interrupt Status Register */ - union - { - struct - { - /*! \brief 1E.5065.F:0 COW MSS Egress SA ECC Error Interrupt MSW [1F:10] - AQ_MssEgressEccInterruptStatusRegister_HHD.u1.bits_1.mssEgressSaEccErrorInterruptMSW - - Default = 0x0000 - - SA ECC error interrupt bits 31:16 - - - Notes: - Write these bits to 1 to clear. - When set to 1, indicates that an ECC error occured for the SA. */ - unsigned int mssEgressSaEccErrorInterruptMSW : 16; /* 1E.5065.F:0 COW Default = 0x0000 */ - /* SA ECC error interrupt bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssEgressEccInterruptStatusRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Egress LUT Address Control Register: 1E.5080 */ -/* MSS Egress LUT Address Control Register: 1E.5080 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Egress LUT Address Control Register */ - union - { - struct - { - /*! \brief 1E.5080.8:0 R/W MSS Egress LUT Address [8:0] - AQ_MssEgressLutAddressControlRegister_HHD.u0.bits_0.mssEgressLutAddress - - Default = 0x000 - - LUT address - - */ - unsigned int mssEgressLutAddress : 9; /* 1E.5080.8:0 R/W Default = 0x000 */ - /* LUT address - */ - unsigned int reserved0 : 3; - /*! \brief 1E.5080.F:C R/W MSS Egress LUT Select [3:0] - AQ_MssEgressLutAddressControlRegister_HHD.u0.bits_0.mssEgressLutSelect - - Default = 0x0 - - LUT select - - - Notes: - 0x0 : Egress MAC Control FIlter (CTLF) LUT - 0x1 : Egress Classification LUT - 0x2 : Egress SC/SA LUT - 0x3 : Egress SMIB */ - unsigned int mssEgressLutSelect : 4; /* 1E.5080.F:C R/W Default = 0x0 */ - /* LUT select - */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_MssEgressLutAddressControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Egress LUT Control Register: 1E.5081 */ -/* MSS Egress LUT Control Register: 1E.5081 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Egress LUT Control Register */ - union - { - struct - { - unsigned int reserved0 : 14; - /*! \brief 1E.5081.E R/W MSS Egress LUT Read - AQ_MssEgressLutControlRegister_HHD.u0.bits_0.mssEgressLutRead - - Default = 0x0 - - 1 = LUT read - - - Notes: - Setting this bit to 1, will read the LUT. This bit will automatically clear to 0. */ - unsigned int mssEgressLutRead : 1; /* 1E.5081.E R/W Default = 0x0 */ - /* 1 = LUT read - */ - /*! \brief 1E.5081.F R/W MSS Egress LUT Write - AQ_MssEgressLutControlRegister_HHD.u0.bits_0.mssEgressLutWrite - - Default = 0x0 - - 1 = LUT write - - - Notes: - Setting this bit to 1, will write the LUT. This bit will automatically clear to 0. */ - unsigned int mssEgressLutWrite : 1; /* 1E.5081.F R/W Default = 0x0 */ - /* 1 = LUT write - */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_MssEgressLutControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Egress LUT Data Control Register: 1E.50A0 */ -/* MSS Egress LUT Data Control Register: 1E.50A0 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50A0.F:0 R/W MSS Egress LUT Data 0 [F:0] - AQ_MssEgressLutDataControlRegister_HHD.u0.bits_0.mssEgressLutData_0 - - Default = 0x0000 - - LUT data bits 15:0 - - */ - unsigned int mssEgressLutData_0 : 16; /* 1E.50A0.F:0 R/W Default = 0x0000 */ - /* LUT data bits 15:0 - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50A1.F:0 R/W MSS Egress LUT Data 1 [1F:10] - AQ_MssEgressLutDataControlRegister_HHD.u1.bits_1.mssEgressLutData_1 - - Default = 0x0000 - - LUT data bits 31:16 - - */ - unsigned int mssEgressLutData_1 : 16; /* 1E.50A1.F:0 R/W Default = 0x0000 */ - /* LUT data bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50A2.F:0 R/W MSS Egress LUT Data 2 [2F:20] - AQ_MssEgressLutDataControlRegister_HHD.u2.bits_2.mssEgressLutData_2 - - Default = 0x0000 - - LUT data bits 47:32 - - */ - unsigned int mssEgressLutData_2 : 16; /* 1E.50A2.F:0 R/W Default = 0x0000 */ - /* LUT data bits 47:32 - */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50A3.F:0 R/W MSS Egress LUT Data 3 [3F:30] - AQ_MssEgressLutDataControlRegister_HHD.u3.bits_3.mssEgressLutData_3 - - Default = 0x0000 - - LUT data bits 63:48 - - */ - unsigned int mssEgressLutData_3 : 16; /* 1E.50A3.F:0 R/W Default = 0x0000 */ - /* LUT data bits 63:48 - */ - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50A4.F:0 R/W MSS Egress LUT Data 4 [4F:40] - AQ_MssEgressLutDataControlRegister_HHD.u4.bits_4.mssEgressLutData_4 - - Default = 0x0000 - - LUT data bits 79:64 - - */ - unsigned int mssEgressLutData_4 : 16; /* 1E.50A4.F:0 R/W Default = 0x0000 */ - /* LUT data bits 79:64 - */ - } bits_4; - uint16_t word_4; - } u4; - /*! \brief Union for bit and word level access of word 5 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50A5.F:0 R/W MSS Egress LUT Data 5 [5F:50] - AQ_MssEgressLutDataControlRegister_HHD.u5.bits_5.mssEgressLutData_5 - - Default = 0x0000 - - LUT data bits 95:80 - - */ - unsigned int mssEgressLutData_5 : 16; /* 1E.50A5.F:0 R/W Default = 0x0000 */ - /* LUT data bits 95:80 - */ - } bits_5; - uint16_t word_5; - } u5; - /*! \brief Union for bit and word level access of word 6 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50A6.F:0 R/W MSS Egress LUT Data 6 [6F:60] - AQ_MssEgressLutDataControlRegister_HHD.u6.bits_6.mssEgressLutData_6 - - Default = 0x0000 - - LUT data bits 111:96 - - */ - unsigned int mssEgressLutData_6 : 16; /* 1E.50A6.F:0 R/W Default = 0x0000 */ - /* LUT data bits 111:96 - */ - } bits_6; - uint16_t word_6; - } u6; - /*! \brief Union for bit and word level access of word 7 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50A7.F:0 R/W MSS Egress LUT Data 7 [7F:70] - AQ_MssEgressLutDataControlRegister_HHD.u7.bits_7.mssEgressLutData_7 - - Default = 0x0000 - - LUT data bits 127:112 - - */ - unsigned int mssEgressLutData_7 : 16; /* 1E.50A7.F:0 R/W Default = 0x0000 */ - /* LUT data bits 127:112 - */ - } bits_7; - uint16_t word_7; - } u7; - /*! \brief Union for bit and word level access of word 8 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50A8.F:0 R/W MSS Egress LUT Data 8 [8F:80] - AQ_MssEgressLutDataControlRegister_HHD.u8.bits_8.mssEgressLutData_8 - - Default = 0x0000 - - LUT data bits 143:128 - - */ - unsigned int mssEgressLutData_8 : 16; /* 1E.50A8.F:0 R/W Default = 0x0000 */ - /* LUT data bits 143:128 - */ - } bits_8; - uint16_t word_8; - } u8; - /*! \brief Union for bit and word level access of word 9 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50A9.F:0 R/W MSS Egress LUT Data 9 [9F:90] - AQ_MssEgressLutDataControlRegister_HHD.u9.bits_9.mssEgressLutData_9 - - Default = 0x0000 - - LUT data bits 159:144 - - */ - unsigned int mssEgressLutData_9 : 16; /* 1E.50A9.F:0 R/W Default = 0x0000 */ - /* LUT data bits 159:144 - */ - } bits_9; - uint16_t word_9; - } u9; - /*! \brief Union for bit and word level access of word 10 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50AA.F:0 R/W MSS Egress LUT Data 10 [AF:A0] - AQ_MssEgressLutDataControlRegister_HHD.u10.bits_10.mssEgressLutData_10 - - Default = 0x0000 - - LUT data bits 175:160 - - */ - unsigned int mssEgressLutData_10 : 16; /* 1E.50AA.F:0 R/W Default = 0x0000 */ - /* LUT data bits 175:160 - */ - } bits_10; - uint16_t word_10; - } u10; - /*! \brief Union for bit and word level access of word 11 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50AB.F:0 R/W MSS Egress LUT Data 11 [BF:B0] - AQ_MssEgressLutDataControlRegister_HHD.u11.bits_11.mssEgressLutData_11 - - Default = 0x0000 - - LUT data bits 191:176 - - */ - unsigned int mssEgressLutData_11 : 16; /* 1E.50AB.F:0 R/W Default = 0x0000 */ - /* LUT data bits 191:176 - */ - } bits_11; - uint16_t word_11; - } u11; - /*! \brief Union for bit and word level access of word 12 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50AC.F:0 R/W MSS Egress LUT Data 12 [CF:C0] - AQ_MssEgressLutDataControlRegister_HHD.u12.bits_12.mssEgressLutData_12 - - Default = 0x0000 - - LUT data bits 207:192 - - */ - unsigned int mssEgressLutData_12 : 16; /* 1E.50AC.F:0 R/W Default = 0x0000 */ - /* LUT data bits 207:192 - */ - } bits_12; - uint16_t word_12; - } u12; - /*! \brief Union for bit and word level access of word 13 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50AD.F:0 R/W MSS Egress LUT Data 13 [DF:D0] - AQ_MssEgressLutDataControlRegister_HHD.u13.bits_13.mssEgressLutData_13 - - Default = 0x0000 - - LUT data bits 223:208 - - */ - unsigned int mssEgressLutData_13 : 16; /* 1E.50AD.F:0 R/W Default = 0x0000 */ - /* LUT data bits 223:208 - */ - } bits_13; - uint16_t word_13; - } u13; - /*! \brief Union for bit and word level access of word 14 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50AE.F:0 R/W MSS Egress LUT Data 14 [EF:E0] - AQ_MssEgressLutDataControlRegister_HHD.u14.bits_14.mssEgressLutData_14 - - Default = 0x0000 - - LUT data bits 239:224 - - */ - unsigned int mssEgressLutData_14 : 16; /* 1E.50AE.F:0 R/W Default = 0x0000 */ - /* LUT data bits 239:224 - */ - } bits_14; - uint16_t word_14; - } u14; - /*! \brief Union for bit and word level access of word 15 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50AF.F:0 R/W MSS Egress LUT Data 15 [FF:F0] - AQ_MssEgressLutDataControlRegister_HHD.u15.bits_15.mssEgressLutData_15 - - Default = 0x0000 - - LUT data bits 255:240 - - */ - unsigned int mssEgressLutData_15 : 16; /* 1E.50AF.F:0 R/W Default = 0x0000 */ - /* LUT data bits 255:240 - */ - } bits_15; - uint16_t word_15; - } u15; - /*! \brief Union for bit and word level access of word 16 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50B0.F:0 R/W MSS Egress LUT Data 16 [10F:100] - AQ_MssEgressLutDataControlRegister_HHD.u16.bits_16.mssEgressLutData_16 - - Default = 0x0000 - - LUT data bits 271:256 - - */ - unsigned int mssEgressLutData_16 : 16; /* 1E.50B0.F:0 R/W Default = 0x0000 */ - /* LUT data bits 271:256 - */ - } bits_16; - uint16_t word_16; - } u16; - /*! \brief Union for bit and word level access of word 17 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50B1.F:0 R/W MSS Egress LUT Data 17 [11F:110] - AQ_MssEgressLutDataControlRegister_HHD.u17.bits_17.mssEgressLutData_17 - - Default = 0x0000 - - LUT data bits 287:272 - - */ - unsigned int mssEgressLutData_17 : 16; /* 1E.50B1.F:0 R/W Default = 0x0000 */ - /* LUT data bits 287:272 - */ - } bits_17; - uint16_t word_17; - } u17; - /*! \brief Union for bit and word level access of word 18 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50B2.F:0 R/W MSS Egress LUT Data 18 [12F:120] - AQ_MssEgressLutDataControlRegister_HHD.u18.bits_18.mssEgressLutData_18 - - Default = 0x0000 - - LUT data bits 303:288 - - */ - unsigned int mssEgressLutData_18 : 16; /* 1E.50B2.F:0 R/W Default = 0x0000 */ - /* LUT data bits 303:288 - */ - } bits_18; - uint16_t word_18; - } u18; - /*! \brief Union for bit and word level access of word 19 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50B3.F:0 R/W MSS Egress LUT Data 19 [13F:130] - AQ_MssEgressLutDataControlRegister_HHD.u19.bits_19.mssEgressLutData_19 - - Default = 0x0000 - - LUT data bits 319:304 - - */ - unsigned int mssEgressLutData_19 : 16; /* 1E.50B3.F:0 R/W Default = 0x0000 */ - /* LUT data bits 319:304 - */ - } bits_19; - uint16_t word_19; - } u19; - /*! \brief Union for bit and word level access of word 20 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50B4.F:0 R/W MSS Egress LUT Data 20 [14F:140] - AQ_MssEgressLutDataControlRegister_HHD.u20.bits_20.mssEgressLutData_20 - - Default = 0x0000 - - LUT data bits 335:320 - - */ - unsigned int mssEgressLutData_20 : 16; /* 1E.50B4.F:0 R/W Default = 0x0000 */ - /* LUT data bits 335:320 - */ - } bits_20; - uint16_t word_20; - } u20; - /*! \brief Union for bit and word level access of word 21 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50B5.F:0 R/W MSS Egress LUT Data 21 [15F:150] - AQ_MssEgressLutDataControlRegister_HHD.u21.bits_21.mssEgressLutData_21 - - Default = 0x0000 - - LUT data bits 351:336 - - */ - unsigned int mssEgressLutData_21 : 16; /* 1E.50B5.F:0 R/W Default = 0x0000 */ - /* LUT data bits 351:336 - */ - } bits_21; - uint16_t word_21; - } u21; - /*! \brief Union for bit and word level access of word 22 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50B6.F:0 R/W MSS Egress LUT Data 22 [16F:160] - AQ_MssEgressLutDataControlRegister_HHD.u22.bits_22.mssEgressLutData_22 - - Default = 0x0000 - - LUT data bits 367:352 - - */ - unsigned int mssEgressLutData_22 : 16; /* 1E.50B6.F:0 R/W Default = 0x0000 */ - /* LUT data bits 367:352 - */ - } bits_22; - uint16_t word_22; - } u22; - /*! \brief Union for bit and word level access of word 23 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50B7.F:0 R/W MSS Egress LUT Data 23 [17F:170] - AQ_MssEgressLutDataControlRegister_HHD.u23.bits_23.mssEgressLutData_23 - - Default = 0x0000 - - LUT data bits 383:368 - - */ - unsigned int mssEgressLutData_23 : 16; /* 1E.50B7.F:0 R/W Default = 0x0000 */ - /* LUT data bits 383:368 - */ - } bits_23; - uint16_t word_23; - } u23; - /*! \brief Union for bit and word level access of word 24 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50B8.F:0 R/W MSS Egress LUT Data 24 [18F:180] - AQ_MssEgressLutDataControlRegister_HHD.u24.bits_24.mssEgressLutData_24 - - Default = 0x0000 - - LUT data bits 399:384 - - */ - unsigned int mssEgressLutData_24 : 16; /* 1E.50B8.F:0 R/W Default = 0x0000 */ - /* LUT data bits 399:384 - */ - } bits_24; - uint16_t word_24; - } u24; - /*! \brief Union for bit and word level access of word 25 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50B9.F:0 R/W MSS Egress LUT Data 25 [19F:190] - AQ_MssEgressLutDataControlRegister_HHD.u25.bits_25.mssEgressLutData_25 - - Default = 0x0000 - - LUT data bits 415:400 - - */ - unsigned int mssEgressLutData_25 : 16; /* 1E.50B9.F:0 R/W Default = 0x0000 */ - /* LUT data bits 415:400 - */ - } bits_25; - uint16_t word_25; - } u25; - /*! \brief Union for bit and word level access of word 26 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50BA.F:0 R/W MSS Egress LUT Data 26 [1AF:1A0] - AQ_MssEgressLutDataControlRegister_HHD.u26.bits_26.mssEgressLutData_26 - - Default = 0x0000 - - LUT data bits 431:416 - - */ - unsigned int mssEgressLutData_26 : 16; /* 1E.50BA.F:0 R/W Default = 0x0000 */ - /* LUT data bits 431:416 - */ - } bits_26; - uint16_t word_26; - } u26; - /*! \brief Union for bit and word level access of word 27 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50BB.F:0 R/W MSS Egress LUT Data 27 [1BF:1B0] - AQ_MssEgressLutDataControlRegister_HHD.u27.bits_27.mssEgressLutData_27 - - Default = 0x0000 - - LUT data bits 447:432 - - */ - unsigned int mssEgressLutData_27 : 16; /* 1E.50BB.F:0 R/W Default = 0x0000 */ - /* LUT data bits 447:432 - */ - } bits_27; - uint16_t word_27; - } u27; -} AQ_MssEgressLutDataControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System General Control Register: 1E.6004 */ -/* MSM System General Control Register: 1E.6004 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System General Control Register */ - union - { - struct - { - /*! \brief 1E.6004.0 R/W MSM System Tx Enable - AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemTxEnable - - Default = 0x0 - - 1 = Tx enable - - Notes: - MAC Rx path enable. Should be set to 1 to enable the MAC Rx path. Should be set to 0 to disable the MAC Rx path. */ - unsigned int msmSystemTxEnable : 1; /* 1E.6004.0 R/W Default = 0x0 */ - /* 1 = Tx enable */ - /*! \brief 1E.6004.1 R/W MSM System Rx Enable - AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemRxEnable - - Default = 0x0 - - 1 = Rx enable - - Notes: - MAC Tx path enable. Should be set to 1 to enable the MAC Tx path. Should be set to 0 to disable the MAC Tx path. */ - unsigned int msmSystemRxEnable : 1; /* 1E.6004.1 R/W Default = 0x0 */ - /* 1 = Rx enable */ - unsigned int reserved0 : 1; - /*! \brief 1E.6004.3 R/W MSM System WAN Mode - AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemWanMode - - Default = 0x0 - - 1 = WAN mode - 0 = LAN mode - - - Notes: - WAN mode enable. Sets WAN mode when set to 1 and LAN mode when set to 0. Note: When changing the mode, verifiy correct setting of the Tx IPG. */ - unsigned int msmSystemWanMode : 1; /* 1E.6004.3 R/W Default = 0x0 */ - /* 1 = WAN mode - 0 = LAN mode - */ - /*! \brief 1E.6004.4 R/W MSM System Promiscuous Mode - AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemPromiscuousMode - - Default = 0x0 - - 1 = Promiscuous mode - - - Notes: - When set to 1, all frames are received without any MAC address filtering. */ - unsigned int msmSystemPromiscuousMode : 1; /* 1E.6004.4 R/W Default = 0x0 */ - /* 1 = Promiscuous mode - */ - /*! \brief 1E.6004.5 R/W MSM System PAD Enable - AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemPadEnable - - Default = 0x0 - - 1 = Enable frame padding removal on Rx - - - Notes: - When set to 1, enable frame padding removal on the Rx path. If enabled, padding is removed before the frame is transferred to the MAC client application. If disabled, no padding is removed on the Rx by the MAC. - Note : On Tx, the MAC always adds padding as required. */ - unsigned int msmSystemPadEnable : 1; /* 1E.6004.5 R/W Default = 0x0 */ - /* 1 = Enable frame padding removal on Rx - */ - /*! \brief 1E.6004.6 R/W MSM System CRC Forward - AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemCrcForward - - Default = 0x0 - - 1 = Enable CRC forwarding - - - Notes: - When set to 1, the CRC field of the received frames is forwarded with the frame to the user application. If disabled, the CRC field is stripped from the frame. - Note : If padding is enabled ( See MAC PAD Enable set to 1), this bit is ignored. */ - unsigned int msmSystemCrcForward : 1; /* 1E.6004.6 R/W Default = 0x0 */ - /* 1 = Enable CRC forwarding - */ - /*! \brief 1E.6004.7 R/W MSM System Pause Forward - AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemPauseForward - - Default = 0x0 - - 1 = Enable Pause forwarding - - - Notes: - Terminate or forward pause frames. If set to 1, pause frames are forwarded to the user application. In normal mode, when set to 0, pause frames are terminated and discarded within the MAC. */ - unsigned int msmSystemPauseForward : 1; /* 1E.6004.7 R/W Default = 0x0 */ - /* 1 = Enable Pause forwarding - */ - /*! \brief 1E.6004.8 R/W MSM System Pause Ignore - AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemPauseIgnore - - Default = 0x0 - - 1 = Ignore pause frames - - - Notes: - Ignore pause frame quanta. If set to 1, received pause frames are ignored by the MAC. When set to 0, the Tx is stopped for the amount of time specified in the pause quanta received within the pause frame. */ - unsigned int msmSystemPauseIgnore : 1; /* 1E.6004.8 R/W Default = 0x0 */ - /* 1 = Ignore pause frames - */ - /*! \brief 1E.6004.9 R/W MSM System Tx Address Insert Enable - AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemTxAddressInsertEnable - - Default = 0x0 - - 1 = Insert Tx MAC source address - - - Notes: - Set the source MAC address on transmit. If set to 1, the MAC overwrites the source MAC address with the MAC programmed address in all transmitted frames. When set to 0, the source MAC address is transmitted unmodified from the MAC Tx client application. */ - unsigned int msmSystemTxAddressInsertEnable : 1; /* 1E.6004.9 R/W Default = 0x0 */ - /* 1 = Insert Tx MAC source address - */ - /*! \brief 1E.6004.A R/W MSM System Tx CRC Append - AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemTxCrcAppend - - Default = 0x0 - - 1 = Append Tx CRC - - - Notes: - Permanently enable CRC append on transmit. If set to 1, the Tx will append a CRC to all transmitted frames. If set to 0, CRC append can be controlled on a per frame basis using the pin ff_tx_crc. - This configuration bit is OR'ed with the external ff_tx_crc pin to instruct the Tx to append a CRC to transmitted frames. The ff_tx_crc pin is tied to 0. */ - unsigned int msmSystemTxCrcAppend : 1; /* 1E.6004.A R/W Default = 0x0 */ - /* 1 = Append Tx CRC - */ - /*! \brief 1E.6004.B R/W MSM System Tx Pad Enable - AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemTxPadEnable - - Default = 0x1 - - 1 = Enable Tx padding - - - Notes: - When set to 1, enable padding of frames in the Tx direction. When set to 0, the MAC will not extend frames from the application to a minimum of 64 bytes, allowing to transmit short frames (violating the Ethernet mimimum size requirements). Must be set to 1 for normal operation. */ - unsigned int msmSystemTxPadEnable : 1; /* 1E.6004.B R/W Default = 0x1 */ - /* 1 = Enable Tx padding - */ - /*! \brief 1E.6004.C R/WSC MSM System Soft Reset - AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemSoftReset - - Default = 0x0 - - 1 = Soft reset - - - Notes: - Software reset. Self clearing bit. When set to 1, resets all statistic counters as well as the Tx and Rx FIFOs. It should be issued after all traffic has been stopped as a result of clearing the Rx/Tx enable bits ( See MAC Rx Enable set to 0 and See MAC Tx Enable set to 0). - Note : Can lead to an Rx interface (ff_rx_xxx) violations to the application if the reset is issued in the middle of a receive frame transfer. Then the end of packet (assertion of ff_rx_eop) is lost and the application should be prepeared to handle this exception. */ - unsigned int msmSystemSoftReset : 1; /* 1E.6004.C R/WSC Default = 0x0 */ - /* 1 = Soft reset - */ - /*! \brief 1E.6004.D R/W MSM System Control Frame Enable - AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemControlFrameEnable - - Default = 0x0 - - 1 = Control frame enabled - - - Notes: - MAC control frame enable. When set to 1, the MAC control frames with any Opcode other than 0x0001 are accepted and forwarded to the client interface. When set to 0, MAC control frames with any opcode other than 0x0001 are silently discarded. */ - unsigned int msmSystemControlFrameEnable : 1; /* 1E.6004.D R/W Default = 0x0 */ - /* 1 = Control frame enabled - */ - /*! \brief 1E.6004.E R/W MSM System Rx Error Discard - AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemRxErrorDiscard - - Default = 0x0 - - 1 = Enable discard of received errored frames - - - Notes: - Rx errored frame discard enable. When set to 1, any frame received with an error is discarded and not forwarded to the client interface. When set to 0, errored frames are forwarded to the client interface with ff_rx_err asserted. - Note : It is recommended to set this bit to 1 only when store and forward operation is enabled (RX_SECTION_FULL TBD). */ - unsigned int msmSystemRxErrorDiscard : 1; /* 1E.6004.E R/W Default = 0x0 */ - /* 1 = Enable discard of received errored frames - */ - /*! \brief 1E.6004.F R/W MSM System PHY Tx Enable - AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemPhyTxEnable - - Default = 0x0 - - 1 = Enable PHY Tx - - - Notes: - Directly controls the phy_tx_ena pin. */ - unsigned int msmSystemPhyTxEnable : 1; /* 1E.6004.F R/W Default = 0x0 */ - /* 1 = Enable PHY Tx - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System General Control Register */ - union - { - struct - { - /*! \brief 1E.6005.0 R/W MSM System Force Send IDLE - AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemForceSendIdle - - Default = 0x0 - - 1 = Force send idle - - Notes: - When set to 1, suppress any frame transmissions and forces IDLE n the Tx interface instead of frames. This control affects the MAC reconciliation layer (RS) which acts after all MAC datapath has processed the frame. - Note : Does not have an effect on fault handling (i.e. reception of local fault will still cause transmit of remote fault). - Must be 0 for normal operation. */ - unsigned int msmSystemForceSendIdle : 1; /* 1E.6005.0 R/W Default = 0x0 */ - /* 1 = Force send idle */ - /*! \brief 1E.6005.1 R/W MSM System Length Check Disable - AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemLengthCheckDisable - - Default = 0x0 - - 1 = Disable length check - - Notes: - Payload length check disable. When set to 0, the MAC checks the frames payload length with the frame length/type field. When set to 1, the payload length check is disabled. */ - unsigned int msmSystemLengthCheckDisable : 1; /* 1E.6005.1 R/W Default = 0x0 */ - /* 1 = Disable length check */ - /*! \brief 1E.6005.2 R/W MSM System IDLE Column Count Extend - AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemIdleColumnCountExtend - - Default = 0x0 - - 1 = Extend IDLE column count - - Notes: - When set to 1, extends the RS layer IDLE column counter by 2x. The IEEE 802.3ae defines the fault condition to be cleared after 128 columns of IDLE have been received. If the MAC operates together with a WAN mode PCS (WIS) it may may happen (depending on PCS) that this period is too short to bridge the IDLE stuffing occurring in this mode, leading to a toggling fault indication. In this case, extending the counter helps to aoivd toggling fault indications. */ - unsigned int msmSystemIdleColumnCountExtend : 1; /* 1E.6005.2 R/W Default = 0x0 */ - /* 1 = Extend IDLE column count */ - /*! \brief 1E.6005.3 R/W MSM System Priority Flow Control Enable - AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemPriorityFlowControlEnable - - Default = 0x0 - - 1 = Enable priority flow control - 0 = Enable link flow control - - - Notes: - Enable priority flow control (PFC) mode of operation. When set to 0, the MAC uses standard link pause frames. When set to 1, the MAC will transmit and accept PFC frames. */ - unsigned int msmSystemPriorityFlowControlEnable : 1; /* 1E.6005.3 R/W Default = 0x0 */ - /* 1 = Enable priority flow control - 0 = Enable link flow control - */ - unsigned int reserved2 : 1; - /*! \brief 1E.6005.5 R/W MSM System SFD Check Disable - AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemSfdCheckDisable - - Default = 0x0 - - 1 = Disable SFD check - - - Notes: - Disable check of SFD (0xD5) character at frame start. When set to 1, the frame is accepted even if the SFD byte following the preamble is not 0xD5. When set to 0, a frame is accepted only if the SFD byte is found with the value 0xD5. */ - unsigned int msmSystemSfdCheckDisable : 1; /* 1E.6005.5 R/W Default = 0x0 */ - /* 1 = Disable SFD check - */ - unsigned int reserved1 : 1; - /*! \brief 1E.6005.7 R/W MSM System Tx Low Power IDLE Enable - AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemTxLowPowerIdleEnable - - Default = 0x0 - - 1 = Transmit LPI enable - - - Notes: - Transmit low power IDLE enable. When set to 1, the MAC completes the transmission of the current frame and generates low power IDLE sequences (LPI) to the XGMII/SGMII. When set to 0, the MAC operates in normal mode. This bit is OR'ed with the reg_lowp_ena pin. */ - unsigned int msmSystemTxLowPowerIdleEnable : 1; /* 1E.6005.7 R/W Default = 0x0 */ - /* 1 = Transmit LPI enable - */ - unsigned int reserved0 : 8; - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemGeneralControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System FIFO Control Register: 1E.600E */ -/* MSM System FIFO Control Register: 1E.600E */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System FIFO Control Register */ - union - { - struct - { - /*! \brief 1E.600E.7:0 R/W MSM System Rx FIFO Full Threshold [7:0] - AQ_MsmSystemFifoControlRegister_HHD.u0.bits_0.msmSystemRxFifoFullThreshold - - Default = 0x08 - - Rx FIFO full threshold - - Notes: - All threshold values are in steps of FIFO words. */ - unsigned int msmSystemRxFifoFullThreshold : 8; /* 1E.600E.7:0 R/W Default = 0x08 */ - /* Rx FIFO full threshold */ - unsigned int reserved0 : 8; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System FIFO Control Register */ - union - { - struct - { - /*! \brief 1E.600F.7:0 R/W MSM System Rx FIFO Empty Threshold [7:0] - AQ_MsmSystemFifoControlRegister_HHD.u1.bits_1.msmSystemRxFifoEmptyThreshold - - Default = 0x00 - - Rx FIFO empty threshold - - Notes: - All threshold values are in steps of FIFO words. */ - unsigned int msmSystemRxFifoEmptyThreshold : 8; /* 1E.600F.7:0 R/W Default = 0x00 */ - /* Rx FIFO empty threshold */ - unsigned int reserved0 : 8; - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of MSM System FIFO Control Register */ - union - { - struct - { - /*! \brief 1E.6010.5:0 R/W MSM System Tx FIFO Full Threshold [5:0] - AQ_MsmSystemFifoControlRegister_HHD.u2.bits_2.msmSystemTxFifoFullThreshold - - Default = 0x08 - - Tx FIFO full threshold - - Notes: - All threshold values are in steps of FIFO words. */ - unsigned int msmSystemTxFifoFullThreshold : 6; /* 1E.6010.5:0 R/W Default = 0x08 */ - /* Tx FIFO full threshold */ - unsigned int reserved0 : 10; - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of MSM System FIFO Control Register */ - union - { - struct - { - /*! \brief 1E.6011.5:0 R/W MSM System Tx FIFO Empty Threshold [5:0] - AQ_MsmSystemFifoControlRegister_HHD.u3.bits_3.msmSystemTxFifoEmptyThreshold - - Default = 0x00 - - Tx FIFO empty threshold - - Notes: - All threshold values are in steps of FIFO words. */ - unsigned int msmSystemTxFifoEmptyThreshold : 6; /* 1E.6011.5:0 R/W Default = 0x00 */ - /* Tx FIFO empty threshold */ - unsigned int reserved0 : 10; - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of MSM System FIFO Control Register */ - union - { - struct - { - /*! \brief 1E.6012.7:0 ROS MSM System Rx FIFO Almost Full Threshold [7:0] - AQ_MsmSystemFifoControlRegister_HHD.u4.bits_4.msmSystemRxFifoAlmostFullThreshold - - Default = 0x00 - - Rx FIFO almost full threshold - - Notes: - Unused. */ - unsigned int msmSystemRxFifoAlmostFullThreshold : 8; /* 1E.6012.7:0 ROS Default = 0x00 */ - /* Rx FIFO almost full threshold */ - unsigned int reserved0 : 8; - } bits_4; - uint16_t word_4; - } u4; - /*! \brief Union for bit and word level access of word 5 of MSM System FIFO Control Register */ - union - { - struct - { - /*! \brief 1E.6013.7:0 ROS MSM System Rx FIFO Almost Empty Threshold [7:0] - AQ_MsmSystemFifoControlRegister_HHD.u5.bits_5.msmSystemRxFifoAlmostEmptyThreshold - - Default = 0x00 - - Rx FIFO almost empty threshold - - Notes: - Unused. */ - unsigned int msmSystemRxFifoAlmostEmptyThreshold : 8; /* 1E.6013.7:0 ROS Default = 0x00 */ - /* Rx FIFO almost empty threshold */ - unsigned int reserved0 : 8; - } bits_5; - uint16_t word_5; - } u5; - /*! \brief Union for bit and word level access of word 6 of MSM System FIFO Control Register */ - union - { - struct - { - /*! \brief 1E.6014.7:0 ROS MSM System Tx FIFO Almost Full Threshold [7:0] - AQ_MsmSystemFifoControlRegister_HHD.u6.bits_6.msmSystemTxFifoAlmostFullThreshold - - Default = 0x00 - - Tx FIFO almost full threshold - - Notes: - Unused. */ - unsigned int msmSystemTxFifoAlmostFullThreshold : 8; /* 1E.6014.7:0 ROS Default = 0x00 */ - /* Tx FIFO almost full threshold */ - unsigned int reserved0 : 8; - } bits_6; - uint16_t word_6; - } u6; - /*! \brief Union for bit and word level access of word 7 of MSM System FIFO Control Register */ - union - { - struct - { - /*! \brief 1E.6015.7:0 ROS MSM System Tx FIFO Almost Empty Threshold [7:0] - AQ_MsmSystemFifoControlRegister_HHD.u7.bits_7.msmSystemTxFifoAlmostEmptyThreshold - - Default = 0x00 - - Tx FIFO almost empty threshold - - Notes: - Unused. */ - unsigned int msmSystemTxFifoAlmostEmptyThreshold : 8; /* 1E.6015.7:0 ROS Default = 0x00 */ - /* Tx FIFO almost empty threshold */ - unsigned int reserved0 : 8; - } bits_7; - uint16_t word_7; - } u7; -} AQ_MsmSystemFifoControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System General Status Register: 1E.6020 */ -/* MSM System General Status Register: 1E.6020 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System General Status Register */ - union - { - struct - { - /*! \brief 1E.6020.0 BLH MSM System Rx Local Fault - AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemRxLocalFault - - - - Rx local fault detected - - Notes: - Latch high local fault status. Set to 1, whent he MAC detects Rx local fault sequences on the Rx interface. Reset to 0 after read and after reset. */ - unsigned int msmSystemRxLocalFault : 1; /* 1E.6020.0 BLH */ - /* Rx local fault detected */ - /*! \brief 1E.6020.1 BLH MSM System Rx Remote Fault - AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemRxRemoteFault - - - - Rx remote fault detected - - Notes: - Latch high local fault status. Set to 1, whent he MAC detects Rx local fault sequences on the Rx interface. Reset to 0 after read and after reset. */ - unsigned int msmSystemRxRemoteFault : 1; /* 1E.6020.1 BLH */ - /* Rx remote fault detected */ - /*! \brief 1E.6020.2 RO MSM System PHY Loss of Signal - AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemPhyLossOfSignal - - - - PHY loss of signal - - Notes: - PHY indicates loss of signal. This is the value of pin phy_los which is tied to 0. */ - unsigned int msmSystemPhyLossOfSignal : 1; /* 1E.6020.2 RO */ - /* PHY loss of signal */ - /*! \brief 1E.6020.3 R/W MSM System Timestamp Available - AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemTimestampAvailable - - Default = 0x0 - - Timestamp available - - Notes: - Transmit timestamp available. Indicates that the timestamp of the last transmitted event frame (which had ff_tx_ts_frm=1) is available in the register See MAC Time Stamp Status 0 [F:0] and See MAC Time Stamp Status 1 [F:0] . To clear this bit, the bit must be written with a 1. - */ - unsigned int msmSystemTimestampAvailable : 1; /* 1E.6020.3 R/W Default = 0x0 */ - /* Timestamp available */ - /*! \brief 1E.6020.4 RO MSM System Rx Low Power IDLE - AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemRxLowPowerIdle - - - - Rx LPI detected - - Notes: - Receive low power IDLE (LPI). Set to 1 when LPI is currently detected on the MAC Rx interface. Set to 0, when the MAC currently operates in normal mode. */ - unsigned int msmSystemRxLowPowerIdle : 1; /* 1E.6020.4 RO */ - /* Rx LPI detected */ - /*! \brief 1E.6020.5 RO MSM System Tx FIFO Empty - AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemTxFifoEmpty - - - - Tx FIFO empty - - Notes: - When set to 1, indicates the Tx FIFO is empty. When set to 0, Tx FIFO is non-empty. */ - unsigned int msmSystemTxFifoEmpty : 1; /* 1E.6020.5 RO */ - /* Tx FIFO empty */ - unsigned int reserved0 : 10; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System General Status Register */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemGeneralStatusRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Tx IPG Control Register: 1E.6022 */ -/* MSM System Tx IPG Control Register: 1E.6022 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Tx IPG Control Register */ - union - { - struct - { - /*! \brief 1E.6022.5:0 R/W MSM System Tx IPG Length [5:0] - AQ_MsmSystemTxIpgControlRegister_HHD.u0.bits_0.msmSystemTxIpgLength - - Default = 0x0C - - Tx IPG length - - Notes: - Tx inter-packet gap (IPG) value. Depending on LAN or WAN mode of operation. - LAN Mode : Number of octets in steps of 4. Valid values are 8, 12, 16,..., 100. DIC is supported for any setting > 8. A default of 12 must be set to conform to IEEE802.3ae. - WAN Mode : Stretch factor. Valid values are 4 ... 15. The stretch factor is calculated as (value+1)*8. A default of 12 must be set to conform to IEEE802.3ae (i.e. 13*8=104). A larger value shrinks the IPG (increasing bandwidth). - The reset value of 12 leads to IEEE802.3ae conformant behavior in both modes. - Note : WAN mode is only available in 10G mode of operation. */ - unsigned int msmSystemTxIpgLength : 6; /* 1E.6022.5:0 R/W Default = 0x0C */ - /* Tx IPG length */ - unsigned int reserved0 : 10; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Tx IPG Control Register */ - union - { - struct - { - /*! \brief 1E.6023.F:0 MSM System Tx IPG Reserved - AQ_MsmSystemTxIpgControlRegister_HHD.u1.bits_1.msmSystemTxIpgReserved - - - - Value always 0, writes ignored - */ - unsigned int msmSystemTxIpgReserved : 16; /* 1E.6023.F:0 */ - /* Value always 0, writes ignored */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemTxIpgControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Tx Good Frames Counter Register: 1E.6040 */ -/* MSM System Tx Good Frames Counter Register: 1E.6040 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Tx Good Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6040.F:0 ROS MSM System Tx Good Frames Counter 0 [F:0] - AQ_MsmSystemTxGoodFramesCounterRegister_HHD.u0.bits_0.msmSystemTxGoodFramesCounter_0 - - Default = 0x0000 - - Tx good frame counter bits 15:0 - - Notes: - Count of frames transmitted without error (Including pause frames). */ - unsigned int msmSystemTxGoodFramesCounter_0 : 16; /* 1E.6040.F:0 ROS Default = 0x0000 */ - /* Tx good frame counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Tx Good Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6041.F:0 ROS MSM System Tx Good Frames Counter 1 [F:0] - AQ_MsmSystemTxGoodFramesCounterRegister_HHD.u1.bits_1.msmSystemTxGoodFramesCounter_1 - - Default = 0x0000 - - Tx good frame counter bits 31:16 - - - Notes: - Count of frames transmitted without error (Including pause frames). */ - unsigned int msmSystemTxGoodFramesCounter_1 : 16; /* 1E.6041.F:0 ROS Default = 0x0000 */ - /* Tx good frame counter bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemTxGoodFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Rx Good Frames Counter Register: 1E.6044 */ -/* MSM System Rx Good Frames Counter Register: 1E.6044 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Rx Good Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6044.F:0 ROS MSM System Rx Good Frames Counter 0 [F:0] - AQ_MsmSystemRxGoodFramesCounterRegister_HHD.u0.bits_0.msmSystemRxGoodFramesCounter_0 - - Default = 0x0000 - - Rx good frame counter bits 15:0 - - Notes: - Count of frames received without error (Including pause frames). */ - unsigned int msmSystemRxGoodFramesCounter_0 : 16; /* 1E.6044.F:0 ROS Default = 0x0000 */ - /* Rx good frame counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Rx Good Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6045.F:0 ROS MSM System Rx Good Frames Counter 1 [F:0] - AQ_MsmSystemRxGoodFramesCounterRegister_HHD.u1.bits_1.msmSystemRxGoodFramesCounter_1 - - Default = 0x0000 - - Rx good frame counter bits 31:16 - - Notes: - Count of frames received without error (Including pause frames). */ - unsigned int msmSystemRxGoodFramesCounter_1 : 16; /* 1E.6045.F:0 ROS Default = 0x0000 */ - /* Rx good frame counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemRxGoodFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Rx FCS Errors Counter Register: 1E.6048 */ -/* MSM System Rx FCS Errors Counter Register: 1E.6048 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Rx FCS Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.6048.F:0 ROS MSM System FCS Error Counter 0 [F:0] - AQ_MsmSystemRxFcsErrorsCounterRegister_HHD.u0.bits_0.msmSystemFcsErrorCounter_0 - - Default = 0x0000 - - Frame check sequence error counter bits 15:0 - - Notes: - Count of frames for which a CRC-32 Error is detected but the frame is otherwise of correct length. */ - unsigned int msmSystemFcsErrorCounter_0 : 16; /* 1E.6048.F:0 ROS Default = 0x0000 */ - /* Frame check sequence error counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Rx FCS Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.6049.F:0 ROS MSM System FCS Error Counter 1 [F:0] - AQ_MsmSystemRxFcsErrorsCounterRegister_HHD.u1.bits_1.msmSystemFcsErrorCounter_1 - - Default = 0x0000 - - Frame check sequence error counter bits 31:16 - - Notes: - Count of frames for which a CRC-32 Error is detected but the frame is otherwise of correct length. */ - unsigned int msmSystemFcsErrorCounter_1 : 16; /* 1E.6049.F:0 ROS Default = 0x0000 */ - /* Frame check sequence error counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemRxFcsErrorsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Rx Alignment Errors Counter Register: 1E.604C */ -/* MSM System Rx Alignment Errors Counter Register: 1E.604C */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Rx Alignment Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.604C.F:0 ROS MSM System Alignment Error Counter 0 [F:0] - AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD.u0.bits_0.msmSystemAlignmentErrorCounter_0 - - Default = 0x0000 - - Alignment error counter bits 15:0 - - Notes: - Count of frames received with an alignment error. */ - unsigned int msmSystemAlignmentErrorCounter_0 : 16; /* 1E.604C.F:0 ROS Default = 0x0000 */ - /* Alignment error counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Rx Alignment Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.604D.F:0 ROS MSM System Alignment Error Counter 1 [F:0] - AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD.u1.bits_1.msmSystemAlignmentErrorCounter_1 - - Default = 0x0000 - - Alignment error counter bits 31:16 - - Notes: - Count of frames received with an alignment error. */ - unsigned int msmSystemAlignmentErrorCounter_1 : 16; /* 1E.604D.F:0 ROS Default = 0x0000 */ - /* Alignment error counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Tx Pause Frames Counter Register: 1E.6050 */ -/* MSM System Tx Pause Frames Counter Register: 1E.6050 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Tx Pause Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6050.F:0 ROS MSM System Tx Pause Frames Counter 0 [F:0] - AQ_MsmSystemTxPauseFramesCounterRegister_HHD.u0.bits_0.msmSystemTxPauseFramesCounter_0 - - Default = 0x0000 - - Tx pause frame counter bits 15:0 - - Notes: - Valid pause frames transmitted. */ - unsigned int msmSystemTxPauseFramesCounter_0 : 16; /* 1E.6050.F:0 ROS Default = 0x0000 */ - /* Tx pause frame counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Tx Pause Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6051.F:0 ROS MSM System Tx Pause Frames Counter 1 [F:0] - AQ_MsmSystemTxPauseFramesCounterRegister_HHD.u1.bits_1.msmSystemTxPauseFramesCounter_1 - - Default = 0x0000 - - Tx pause frame counter bits 31:16 - - - Notes: - Valid pause frames transmitted. */ - unsigned int msmSystemTxPauseFramesCounter_1 : 16; /* 1E.6051.F:0 ROS Default = 0x0000 */ - /* Tx pause frame counter bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemTxPauseFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Rx Pause Frames Counter Register: 1E.6054 */ -/* MSM System Rx Pause Frames Counter Register: 1E.6054 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Rx Pause Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6054.F:0 ROS MSM System Rx Pause Frames Counter 0 [F:0] - AQ_MsmSystemRxPauseFramesCounterRegister_HHD.u0.bits_0.msmSystemRxPauseFramesCounter_0 - - Default = 0x0000 - - Rx pause frame counter bits 15:0 - - Notes: - Valid pause frames received. */ - unsigned int msmSystemRxPauseFramesCounter_0 : 16; /* 1E.6054.F:0 ROS Default = 0x0000 */ - /* Rx pause frame counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Rx Pause Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6055.F:0 ROS MSM System Rx Pause Frames Counter 1 [F:0] - AQ_MsmSystemRxPauseFramesCounterRegister_HHD.u1.bits_1.msmSystemRxPauseFramesCounter_1 - - Default = 0x0000 - - Rx pause frame counter bits 31:16 - - Notes: - Valid pause frames received. */ - unsigned int msmSystemRxPauseFramesCounter_1 : 16; /* 1E.6055.F:0 ROS Default = 0x0000 */ - /* Rx pause frame counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemRxPauseFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Rx Too Long Errors Counter Register: 1E.6058 */ -/* MSM System Rx Too Long Errors Counter Register: 1E.6058 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Rx Too Long Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.6058.F:0 ROS MSM System Rx Too Long Errors Counter 0 [F:0] - AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD.u0.bits_0.msmSystemRxTooLongErrorsCounter_0 - - Default = 0x0000 - - Too-long errors counter bits 15:0 - - Notes: - Frame received exceeded the maximum length programmed with register FRM_LGTH. */ - unsigned int msmSystemRxTooLongErrorsCounter_0 : 16; /* 1E.6058.F:0 ROS Default = 0x0000 */ - /* Too-long errors counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Rx Too Long Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.6059.F:0 ROS MSM System Rx Too Long Errors Counter 1 [F:0] - AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD.u1.bits_1.msmSystemRxTooLongErrorsCounter_1 - - Default = 0x0000 - - Too-long errors counter bits 31:16 - - Notes: - Frame received exceeded the maximum length programmed with register FRM_LGTH. */ - unsigned int msmSystemRxTooLongErrorsCounter_1 : 16; /* 1E.6059.F:0 ROS Default = 0x0000 */ - /* Too-long errors counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Rx In Range Length Errors Counter Register: 1E.605C */ -/* MSM System Rx In Range Length Errors Counter Register: 1E.605C */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Rx In Range Length Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.605C.F:0 ROS MSM System Rx In Range Length Errors Counter 0 [F:0] - AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD.u0.bits_0.msmSystemRxInRangeLengthErrorsCounter_0 - - Default = 0x0000 - - In-range-length errors counter bits 15:0 - - Notes: - A count of frames with a length/type field value between 46 (VLAN: 42) and less than 0x0600, that does not match the number of payload data octets received. Should count also if length/type field is less than 46 (VLAN: 42) and the frame is longer than 64 bytes. */ - unsigned int msmSystemRxInRangeLengthErrorsCounter_0 : 16; /* 1E.605C.F:0 ROS Default = 0x0000 */ - /* In-range-length errors counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Rx In Range Length Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.605D.F:0 ROS MSM System Rx In Range Length Errors Counter 1 [F:0] - AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD.u1.bits_1.msmSystemRxInRangeLengthErrorsCounter_1 - - Default = 0x0000 - - In-range-length errors counter bits 31:16 - - Notes: - A count of frames with a length/type field value between 46 (VLAN: 42) and less than 0x0600, that does not match the number of payload data octets received. Should count also if length/type field is less than 46 (VLAN: 42) and the frame is longer than 64 bytes. */ - unsigned int msmSystemRxInRangeLengthErrorsCounter_1 : 16; /* 1E.605D.F:0 ROS Default = 0x0000 */ - /* In-range-length errors counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Tx VLAN Frames Counter Register: 1E.6060 */ -/* MSM System Tx VLAN Frames Counter Register: 1E.6060 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Tx VLAN Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6060.F:0 ROS MSM System Tx VLAN Frames Counter 0 [F:0] - AQ_MsmSystemTxVlanFramesCounterRegister_HHD.u0.bits_0.msmSystemTxVlanFramesCounter_0 - - Default = 0x0000 - - Tx VLAN frames counter bits 15:0 - - Notes: - Valid VLAN tagged frames transmitted. */ - unsigned int msmSystemTxVlanFramesCounter_0 : 16; /* 1E.6060.F:0 ROS Default = 0x0000 */ - /* Tx VLAN frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Tx VLAN Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6061.F:0 ROS MSM System Tx VLAN Frames Counter 1 [F:0] - AQ_MsmSystemTxVlanFramesCounterRegister_HHD.u1.bits_1.msmSystemTxVlanFramesCounter_1 - - Default = 0x0000 - - Tx VLAN frames counter bits 31:16 - - Notes: - Valid VLAN tagged frames transmitted. */ - unsigned int msmSystemTxVlanFramesCounter_1 : 16; /* 1E.6061.F:0 ROS Default = 0x0000 */ - /* Tx VLAN frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemTxVlanFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Rx VLAN Frames Counter Register: 1E.6064 */ -/* MSM System Rx VLAN Frames Counter Register: 1E.6064 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Rx VLAN Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6064.F:0 ROS MSM System Rx VLAN Frames Counter 0 [F:0] - AQ_MsmSystemRxVlanFramesCounterRegister_HHD.u0.bits_0.msmSystemRxVlanFramesCounter_0 - - Default = 0x0000 - - Rx VLAN frames counter bits 15:0 - - Notes: - Valid VLAN tagged frames received. */ - unsigned int msmSystemRxVlanFramesCounter_0 : 16; /* 1E.6064.F:0 ROS Default = 0x0000 */ - /* Rx VLAN frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Rx VLAN Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6065.F:0 ROS MSM System Rx VLAN Frames Counter 1 [F:0] - AQ_MsmSystemRxVlanFramesCounterRegister_HHD.u1.bits_1.msmSystemRxVlanFramesCounter_1 - - Default = 0x0000 - - Rx VLAN frames counter bits 31:16 - - Notes: - Valid VLAN tagged frames received. */ - unsigned int msmSystemRxVlanFramesCounter_1 : 16; /* 1E.6065.F:0 ROS Default = 0x0000 */ - /* Rx VLAN frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemRxVlanFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Tx Octets Counter Register: 1E.6068 */ -/* MSM System Tx Octets Counter Register: 1E.6068 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Tx Octets Counter Register */ - union - { - struct - { - /*! \brief 1E.6068.F:0 ROS MSM System Tx Octets Counter 0 [F:0] - AQ_MsmSystemTxOctetsCounterRegister_HHD.u0.bits_0.msmSystemTxOctetsCounter_0 - - Default = 0x0000 - - Tx octets counter bits 15:0 - - Notes: - All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ - unsigned int msmSystemTxOctetsCounter_0 : 16; /* 1E.6068.F:0 ROS Default = 0x0000 */ - /* Tx octets counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Tx Octets Counter Register */ - union - { - struct - { - /*! \brief 1E.6069.F:0 ROS MSM System Tx Octets Counter 1 [F:0] - AQ_MsmSystemTxOctetsCounterRegister_HHD.u1.bits_1.msmSystemTxOctetsCounter_1 - - Default = 0x0000 - - Tx octets counter bits 31:16 - - Notes: - All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ - unsigned int msmSystemTxOctetsCounter_1 : 16; /* 1E.6069.F:0 ROS Default = 0x0000 */ - /* Tx octets counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of MSM System Tx Octets Counter Register */ - union - { - struct - { - /*! \brief 1E.606A.F:0 ROS MSM System Tx Octets Counter 2 [F:0] - AQ_MsmSystemTxOctetsCounterRegister_HHD.u2.bits_2.msmSystemTxOctetsCounter_2 - - Default = 0x0000 - - Tx octets counter bits 47:32 - - Notes: - All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ - unsigned int msmSystemTxOctetsCounter_2 : 16; /* 1E.606A.F:0 ROS Default = 0x0000 */ - /* Tx octets counter bits 47:32 */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of MSM System Tx Octets Counter Register */ - union - { - struct - { - /*! \brief 1E.606B.F:0 ROS MSM System Tx Octets Counter 3 [F:0] - AQ_MsmSystemTxOctetsCounterRegister_HHD.u3.bits_3.msmSystemTxOctetsCounter_3 - - Default = 0x0000 - - Tx octets counter bits 63:48 - - Notes: - All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ - unsigned int msmSystemTxOctetsCounter_3 : 16; /* 1E.606B.F:0 ROS Default = 0x0000 */ - /* Tx octets counter bits 63:48 */ - } bits_3; - uint16_t word_3; - } u3; -} AQ_MsmSystemTxOctetsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Rx Octets Counter Register: 1E.606C */ -/* MSM System Rx Octets Counter Register: 1E.606C */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Rx Octets Counter Register */ - union - { - struct - { - /*! \brief 1E.606C.F:0 ROS MSM System Rx Octets Counter 0 [F:0] - AQ_MsmSystemRxOctetsCounterRegister_HHD.u0.bits_0.msmSystemRxOctetsCounter_0 - - Default = 0x0000 - - Rx octets counter bits 15:0 - - Notes: - All octets received except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames received. */ - unsigned int msmSystemRxOctetsCounter_0 : 16; /* 1E.606C.F:0 ROS Default = 0x0000 */ - /* Rx octets counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Rx Octets Counter Register */ - union - { - struct - { - /*! \brief 1E.606D.F:0 ROS MSM System Rx Octets Counter 1 [F:0] - AQ_MsmSystemRxOctetsCounterRegister_HHD.u1.bits_1.msmSystemRxOctetsCounter_1 - - Default = 0x0000 - - Rx octets counter bits 31:16 - - Notes: - All octets received except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames received. */ - unsigned int msmSystemRxOctetsCounter_1 : 16; /* 1E.606D.F:0 ROS Default = 0x0000 */ - /* Rx octets counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemRxOctetsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Rx Unicast Frames Counter Register: 1E.6070 */ -/* MSM System Rx Unicast Frames Counter Register: 1E.6070 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Rx Unicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6070.F:0 ROS MSM System Rx Unicast Frames Counter 0 [F:0] - AQ_MsmSystemRxUnicastFramesCounterRegister_HHD.u0.bits_0.msmSystemRxUnicastFramesCounter_0 - - Default = 0x0000 - - Rx unicast frames counter bits 15:0 - - Notes: - Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '0'. */ - unsigned int msmSystemRxUnicastFramesCounter_0 : 16; /* 1E.6070.F:0 ROS Default = 0x0000 */ - /* Rx unicast frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Rx Unicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6071.F:0 ROS MSM System Rx Unicast Frames Counter 1 [F:0] - AQ_MsmSystemRxUnicastFramesCounterRegister_HHD.u1.bits_1.msmSystemRxUnicastFramesCounter_1 - - Default = 0x0000 - - Rx unicast frames counter bits 31:16 - - Notes: - Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '0'. */ - unsigned int msmSystemRxUnicastFramesCounter_1 : 16; /* 1E.6071.F:0 ROS Default = 0x0000 */ - /* Rx unicast frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemRxUnicastFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Rx Multicast Frames Counter Register: 1E.6074 */ -/* MSM System Rx Multicast Frames Counter Register: 1E.6074 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Rx Multicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6074.F:0 ROS MSM System Rx Multicast Frames Counter 0 [F:0] - AQ_MsmSystemRxMulticastFramesCounterRegister_HHD.u0.bits_0.msmSystemRxMulticastFramesCounter_0 - - Default = 0x0000 - - Rx multicast frames counter bits 15:0 - - Notes: - Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '1' but not the broadcast address (all bits set '1' ). Pause frames are not counted. */ - unsigned int msmSystemRxMulticastFramesCounter_0 : 16; /* 1E.6074.F:0 ROS Default = 0x0000 */ - /* Rx multicast frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Rx Multicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6075.F:0 ROS MSM System Rx Multicast Frames Counter 1 [F:0] - AQ_MsmSystemRxMulticastFramesCounterRegister_HHD.u1.bits_1.msmSystemRxMulticastFramesCounter_1 - - Default = 0x0000 - - Rx multicast frames counter bits 31:16 - - Notes: - Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '1' but not the broadcast address (all bits set '1' ). Pause frames are not counted. */ - unsigned int msmSystemRxMulticastFramesCounter_1 : 16; /* 1E.6075.F:0 ROS Default = 0x0000 */ - /* Rx multicast frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemRxMulticastFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Rx Broadcast Frames Counter Register: 1E.6078 */ -/* MSM System Rx Broadcast Frames Counter Register: 1E.6078 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Rx Broadcast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6078.F:0 ROS MSM System Rx Broadcast Frames Counter 0 [F:0] - AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD.u0.bits_0.msmSystemRxBroadcastFramesCounter_0 - - Default = 0x0000 - - Rx broadcast frames counter bits 15:0 - - Notes: - Incremented with each valid frame received on the receive FIFO interface (FIFO) and all bits of the destination address were set '1'. */ - unsigned int msmSystemRxBroadcastFramesCounter_0 : 16; /* 1E.6078.F:0 ROS Default = 0x0000 */ - /* Rx broadcast frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Rx Broadcast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6079.F:0 ROS MSM System Rx Broadcast Frames Counter 1 [F:0] - AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD.u1.bits_1.msmSystemRxBroadcastFramesCounter_1 - - Default = 0x0000 - - Rx broadcast frames counter bits 31:16 - - Notes: - Incremented with each valid frame received on the receive FIFO interface (FIFO) and all bits of the destination address were set '1'. */ - unsigned int msmSystemRxBroadcastFramesCounter_1 : 16; /* 1E.6079.F:0 ROS Default = 0x0000 */ - /* Rx broadcast frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Tx Errors Counter Register: 1E.607C */ -/* MSM System Tx Errors Counter Register: 1E.607C */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Tx Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.607C.F:0 ROS MSM System Tx Errors Counter 0 [F:0] - AQ_MsmSystemTxErrorsCounterRegister_HHD.u0.bits_0.msmSystemTxErrorsCounter_0 - - Default = 0x0000 - - Rx errors counter bits 15:0 - - Notes: - Number of frames transmitted with error: - - FIFO Overflow Errors - - FIFO Underflow Errors */ - unsigned int msmSystemTxErrorsCounter_0 : 16; /* 1E.607C.F:0 ROS Default = 0x0000 */ - /* Rx errors counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Tx Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.607D.F:0 ROS MSM System Tx Errors Counter 1 [F:0] - AQ_MsmSystemTxErrorsCounterRegister_HHD.u1.bits_1.msmSystemTxErrorsCounter_1 - - Default = 0x0000 - - Tx errors counter bits 31:16 - - Notes: - Number of frames transmitted with error: - - FIFO Overflow Errors - - FIFO Underflow Errors */ - unsigned int msmSystemTxErrorsCounter_1 : 16; /* 1E.607D.F:0 ROS Default = 0x0000 */ - /* Tx errors counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemTxErrorsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Tx Unicast Frames Counter Register: 1E.6084 */ -/* MSM System Tx Unicast Frames Counter Register: 1E.6084 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Tx Unicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6084.F:0 ROS MSM System Tx Unicast Frames Counter 0 [F:0] - AQ_MsmSystemTxUnicastFramesCounterRegister_HHD.u0.bits_0.msmSystemTxUnicastFramesCounter_0 - - Default = 0x0000 - - Tx unicast frames counter bits 15:0 - - Notes: - Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '0'. */ - unsigned int msmSystemTxUnicastFramesCounter_0 : 16; /* 1E.6084.F:0 ROS Default = 0x0000 */ - /* Tx unicast frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Tx Unicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6085.F:0 ROS MSM System Tx Unicast Frames Counter 1 [F:0] - AQ_MsmSystemTxUnicastFramesCounterRegister_HHD.u1.bits_1.msmSystemTxUnicastFramesCounter_1 - - Default = 0x0000 - - Tx unicast frames counter bits 31:16 - - Notes: - Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '0'. */ - unsigned int msmSystemTxUnicastFramesCounter_1 : 16; /* 1E.6085.F:0 ROS Default = 0x0000 */ - /* Tx unicast frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemTxUnicastFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Tx Multicast Frames Counter Register: 1E.6088 */ -/* MSM System Tx Multicast Frames Counter Register: 1E.6088 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Tx Multicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6088.F:0 ROS MSM System Tx Multicast Frames Counter 0 [F:0] - AQ_MsmSystemTxMulticastFramesCounterRegister_HHD.u0.bits_0.msmSystemTxMulticastFramesCounter_0 - - Default = 0x0000 - - Tx multicast frames counter bits 15:0 - - Notes: - Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '1' but not the broadcast address (all bits '1'). */ - unsigned int msmSystemTxMulticastFramesCounter_0 : 16; /* 1E.6088.F:0 ROS Default = 0x0000 */ - /* Tx multicast frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Tx Multicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6089.F:0 ROS MSM System Tx Multicast Frames Counter 1 [F:0] - AQ_MsmSystemTxMulticastFramesCounterRegister_HHD.u1.bits_1.msmSystemTxMulticastFramesCounter_1 - - Default = 0x0000 - - Tx multicast frames counter bits 31:16 - - Notes: - Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '1' but not the broadcast address (all bits '1'). */ - unsigned int msmSystemTxMulticastFramesCounter_1 : 16; /* 1E.6089.F:0 ROS Default = 0x0000 */ - /* Tx multicast frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemTxMulticastFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Tx Broadcast Frames Counter Register: 1E.608C */ -/* MSM System Tx Broadcast Frames Counter Register: 1E.608C */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Tx Broadcast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.608C.F:0 ROS MSM System Tx Broadcast Frames Counter 0 [F:0] - AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD.u0.bits_0.msmSystemTxBroadcastFramesCounter_0 - - Default = 0x0000 - - Tx broadcast frames counter bits 15:0 - - Notes: - Incremented with each frame written to the FIFO interface and all bits of the destination address set to '1'. */ - unsigned int msmSystemTxBroadcastFramesCounter_0 : 16; /* 1E.608C.F:0 ROS Default = 0x0000 */ - /* Tx broadcast frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Tx Broadcast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.608D.F:0 ROS MSM System Tx Broadcast Frames Counter 1 [F:0] - AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD.u1.bits_1.msmSystemTxBroadcastFramesCounter_1 - - Default = 0x0000 - - Tx broadcast frames counter bits 31:16 - - Notes: - Incremented with each frame written to the FIFO interface and all bits of the destination address set to '1'. */ - unsigned int msmSystemTxBroadcastFramesCounter_1 : 16; /* 1E.608D.F:0 ROS Default = 0x0000 */ - /* Tx broadcast frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Rx Errors Counter Register: 1E.60C8 */ -/* MSM System Rx Errors Counter Register: 1E.60C8 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Rx Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.60C8.F:0 ROS MSM System Rx Errors Counter 0 [F:0] - AQ_MsmSystemRxErrorsCounterRegister_HHD.u0.bits_0.msmSystemRxErrorsCounter_0 - - Default = 0x0000 - - Rx errors counter bits 15:0 - - Notes: - Number of frames received with error: - - FIFO Overflow Errors - - CRC Errors - - Payload Length Errors - - Jabber and Oversized Errors - - Alignment Errors - - The dedicated Error Code (0xfe, not a code error) was received */ - unsigned int msmSystemRxErrorsCounter_0 : 16; /* 1E.60C8.F:0 ROS Default = 0x0000 */ - /* Rx errors counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Rx Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.60C9.F:0 ROS MSM System Rx Errors Counter 1 [F:0] - AQ_MsmSystemRxErrorsCounterRegister_HHD.u1.bits_1.msmSystemRxErrorsCounter_1 - - Default = 0x0000 - - Rx errors counter bits 31:16 - - Notes: - Number of frames received with error: - - FIFO Overflow Errors - - CRC Errors - - Payload Length Errors - - Jabber and Oversized Errors - - Alignment Errors - - The dedicated Error Code (0xfe, not a code error) was received */ - unsigned int msmSystemRxErrorsCounter_1 : 16; /* 1E.60C9.F:0 ROS Default = 0x0000 */ - /* Rx errors counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemRxErrorsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress VLAN TPID 0 Register: 1E.8006 */ -/* MSS Ingress VLAN TPID 0 Register: 1E.8006 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress VLAN TPID 0 Register */ - union - { - struct - { - /*! \brief 1E.8006.F:0 R/W MSS Ingress VLAN STag [F:0] - AQ_MssIngressVlanTpid_0Register_HHD.u0.bits_0.mssIngressVlanStag - - Default = 0x0000 - - STag TPID - - - Notes: - Service Tag Protocol Identifier (TPID) values to identify a VLAN tag. The " See SEC Egress VLAN CP Tag Parse STag " bit must be set to 1 for the incoming packet's TPID to be parsed. */ - unsigned int mssIngressVlanStag : 16; /* 1E.8006.F:0 R/W Default = 0x0000 */ - /* STag TPID - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Ingress VLAN TPID 0 Register */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssIngressVlanTpid_0Register_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress VLAN TPID 1 Register: 1E.8008 */ -/* MSS Ingress VLAN TPID 1 Register: 1E.8008 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress VLAN TPID 1 Register */ - union - { - struct - { - /*! \brief 1E.8008.F:0 R/W MSS Ingress VLAN QTag [F:0] - AQ_MssIngressVlanTpid_1Register_HHD.u0.bits_0.mssIngressVlanQtag - - Default = 0x0000 - - QTag TPID - - - Notes: - Customer Tag Protocol Identifier (TPID) values to identify a VLAN tag. The " See SEC Egress VLAN CP Tag Parse QTag " bit must be set to 1 for the incoming packet's TPID to be parsed. */ - unsigned int mssIngressVlanQtag : 16; /* 1E.8008.F:0 R/W Default = 0x0000 */ - /* QTag TPID - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Ingress VLAN TPID 1 Register */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssIngressVlanTpid_1Register_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress VLAN Control Register: 1E.800A */ -/* MSS Ingress VLAN Control Register: 1E.800A */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress VLAN Control Register */ - union - { - struct - { - /*! \brief 1E.800A.F:0 R/W MSS Ingress VLAN UP Map Table LSW [F:0] - AQ_MssIngressVlanControlRegister_HHD.u0.bits_0.mssIngressVlanUpMapTableLSW - - Default = 0x0000 - - Map table bits 15:0 - - - Notes: - If there is a customer TPID Tag match and no service TPID Tag match or the service TPID Tag match is disabled, the outer TAG's PCP is used to index into this map table to generate the packets user priority. - 2:0 : UP value for customer Tag PCP 0x0 - 5:3: UP value for customer Tag PCP 0x0 - 8:6 : UP value for customer Tag PCP 0x0 - 11:9 : UP value for customer Tag PCP 0x0 - 14:12 : UP value for customer Tag PCP 0x0 - 17:15 : UP value for customer Tag PCP 0x0 */ - unsigned int mssIngressVlanUpMapTableLSW : 16; /* 1E.800A.F:0 R/W Default = 0x0000 */ - /* Map table bits 15:0 - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Ingress VLAN Control Register */ - union - { - struct - { - /*! \brief 1E.800B.7:0 R/W MSS Ingress VLAN UP Map Table MSW [17:10] - AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanUpMapTableMSW - - Default = 0x00 - - UP Map table bits 23:16 - - - Notes: - If there is a customer TPID Tag match and no service TPID Tag match or the service TPID Tag match is disabled, the outer TAG's PCP is used to index into this map table to generate the packets user priority. - 2:0 : UP value for customer Tag PCP 0x0 - 5:3: UP value for customer Tag PCP 0x0 - 8:6 : UP value for customer Tag PCP 0x0 - 11:9 : UP value for customer Tag PCP 0x0 - 14:12 : UP value for customer Tag PCP 0x0 - 17:15 : UP value for customer Tag PCP 0x0 - 20:18 : UP value for customer Tag PCP 0x0 - 23:21 : UP value for customer Tag PCP 0x0 */ - unsigned int mssIngressVlanUpMapTableMSW : 8; /* 1E.800B.7:0 R/W Default = 0x00 */ - /* UP Map table bits 23:16 - */ - /*! \brief 1E.800B.A:8 R/W MSS Ingress VLAN UP Default [2:0] - AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanUpDefault - - Default = 0x0 - - UP default - - - Notes: - User priority default */ - unsigned int mssIngressVlanUpDefault : 3; /* 1E.800B.A:8 R/W Default = 0x0 */ - /* UP default - */ - /*! \brief 1E.800B.B R/W MSS Ingress VLAN STag UP Parse Enable - AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanStagUpParseEnable - - Default = 0x0 - - VLAN CP Tag STag UP enable - - - Notes: - Enable controlled port service VLAN service Tag user priority field parsing. */ - unsigned int mssIngressVlanStagUpParseEnable : 1; /* 1E.800B.B R/W Default = 0x0 */ - /* VLAN CP Tag STag UP enable - */ - /*! \brief 1E.800B.C R/W MSS Ingress VLAN QTag UP Parse Enable - AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanQtagUpParseEnable - - Default = 0x0 - - VLAN CP Tag QTag UP enable - - - Notes: - Enable controlled port customer VLAN customer Tag user priority field parsing. */ - unsigned int mssIngressVlanQtagUpParseEnable : 1; /* 1E.800B.C R/W Default = 0x0 */ - /* VLAN CP Tag QTag UP enable - */ - /*! \brief 1E.800B.D R/W MSS Ingress VLAN QinQ Parse Enable - AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanQinqParseEnable - - Default = 0x0 - - VLAN CP Tag Parse QinQ - - - Notes: - Enable controlled port VLAN QinQ Tag parsing. When this bit is set to 1 both the outer and inner VLAN Tags will be parsed. */ - unsigned int mssIngressVlanQinqParseEnable : 1; /* 1E.800B.D R/W Default = 0x0 */ - /* VLAN CP Tag Parse QinQ - */ - /*! \brief 1E.800B.E R/W MSS Ingress VLAN STag Parse Enable - AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanStagParseEnable - - Default = 0x0 - - 1 = Enable VLAN STag parsing - - - Notes: - Enable controlled port VLAN service Tag parsing. When this bit is set to 1, the incoming packets outer TPID will be compared with the configured " See MSS Ingress VLAN Stag [F:0] " for matching. If the " See SEC Egress VLAN CP Tag Parse QinQ " bit is set to1, this will also be used to compare the incoming packet's inner TPID. */ - unsigned int mssIngressVlanStagParseEnable : 1; /* 1E.800B.E R/W Default = 0x0 */ - /* 1 = Enable VLAN STag parsing - */ - /*! \brief 1E.800B.F R/W MSS Ingress VLAN QTag Parse Enable - AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanQtagParseEnable - - Default = 0x0 - - 1 = Enable VLAN QTag parsing - - - Notes: - Enable controlled port VLAN customer Tag parsing. When this bit is set to 1, the incoming packet's outer TPID will be compared with the configured " See MSS Ingress VLAN QTag [F:0] " for matching. If the " See SEC Egress VLAN CP Tag Parse QinQ " bit is set to1, this will also be used to compare the incoming packet's inner TPID. */ - unsigned int mssIngressVlanQtagParseEnable : 1; /* 1E.800B.F R/W Default = 0x0 */ - /* 1 = Enable VLAN QTag parsing - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssIngressVlanControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress MTU Size Control Register: 1E.800C */ -/* MSS Ingress MTU Size Control Register: 1E.800C */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress MTU Size Control Register */ - union - { - struct - { - /*! \brief 1E.800C.F:0 R/W MSS Ingress Controlled Packet MTU Size [F:0] - AQ_MssIngressMtuSizeControlRegister_HHD.u0.bits_0.mssIngressControlledPacketMtuSize - - Default = 0x05DC - - Maximum transmission unit for controlled packet - - - Notes: - Maximum transmission unit of controlled packet */ - unsigned int mssIngressControlledPacketMtuSize : 16; /* 1E.800C.F:0 R/W Default = 0x05DC */ - /* Maximum transmission unit for controlled packet - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Ingress MTU Size Control Register */ - union - { - struct - { - /*! \brief 1E.800D.F:0 R/W MSS Ingress Uncontrolled Packet MTU Size [F:0] - AQ_MssIngressMtuSizeControlRegister_HHD.u1.bits_1.mssIngressUncontrolledPacketMtuSize - - Default = 0x05DC - - Maximum transmission unit for uncontrolled packet - - - Notes: - Maximum transmission unit of uncontrolled packet */ - unsigned int mssIngressUncontrolledPacketMtuSize : 16; /* 1E.800D.F:0 R/W Default = 0x05DC */ - /* Maximum transmission unit for uncontrolled packet - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssIngressMtuSizeControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress Control Register: 1E.800E */ -/* MSS Ingress Control Register: 1E.800E */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress Control Register */ - union - { - struct - { - /*! \brief 1E.800E.0 R/W MSS Ingress Soft Reset - AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressSoftReset - - Default = 0x0 - - 1 = Soft reset - - - Notes: - S/W reset */ - unsigned int mssIngressSoftReset : 1; /* 1E.800E.0 R/W Default = 0x0 */ - /* 1 = Soft reset - */ - /*! \brief 1E.800E.1 R/W MSS Ingress Operation Point To Point - AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressOperationPointToPoint - - Default = 0x0 - - 1 = Enable the SCI for authorization default - - - Notes: - The default SCI for authorization is configured in See MSS Ingress SCI Default [F:0] See MSS Ingress SCI Default [1F:10] , See MSS Ingress SCI Default [2F:20] , and See MSS Ingress SCI Default [3F:30] . */ - unsigned int mssIngressOperationPointToPoint : 1; /* 1E.800E.1 R/W Default = 0x0 */ - /* 1 = Enable the SCI for authorization default - */ - /*! \brief 1E.800E.2 R/W MSS Ingress Create SCI - AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressCreateSci - - Default = 0x0 - - 0 = SCI from IGPRC LUT - - - Notes: - If the SCI is not in the packet and this bit is set to 0, the SCI will be taken from the IGPRC LUT. */ - unsigned int mssIngressCreateSci : 1; /* 1E.800E.2 R/W Default = 0x0 */ - /* 0 = SCI from IGPRC LUT - */ - /*! \brief 1E.800E.3 R/W MSS Ingress Mask Short Length Error - AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressMaskShortLengthError - - Default = 0x0 - - Unused - - - Notes: - Unused */ - unsigned int mssIngressMaskShortLengthError : 1; /* 1E.800E.3 R/W Default = 0x0 */ - /* Unused - */ - /*! \brief 1E.800E.4 R/W MSS Ingress Drop Kay Packet - AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressDropKayPacket - - Default = 0x0 - - 1 = Drop KaY packets - - - Notes: - Decides whether KaY packets have to be dropped */ - unsigned int mssIngressDropKayPacket : 1; /* 1E.800E.4 R/W Default = 0x0 */ - /* 1 = Drop KaY packets - */ - /*! \brief 1E.800E.5 R/W MSS Ingress Drop IGPRC Miss - AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressDropIgprcMiss - - Default = 0x0 - - 1 = Drop IGPRC miss packets - - - Notes: - Decides whether Ingress Pre-Security Classification (IGPRC) LUT miss packets are to be dropped */ - unsigned int mssIngressDropIgprcMiss : 1; /* 1E.800E.5 R/W Default = 0x0 */ - /* 1 = Drop IGPRC miss packets - */ - /*! \brief 1E.800E.6 R/W MSS Ingress Check ICV - AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressCheckIcv - - Default = 0x0 - - Unused - - - Notes: - Unused */ - unsigned int mssIngressCheckIcv : 1; /* 1E.800E.6 R/W Default = 0x0 */ - /* Unused - */ - /*! \brief 1E.800E.7 R/W MSS Ingress Clear Global Time - AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressClearGlobalTime - - Default = 0x0 - - 1 = Clear global time - - - Notes: - Clear global time */ - unsigned int mssIngressClearGlobalTime : 1; /* 1E.800E.7 R/W Default = 0x0 */ - /* 1 = Clear global time - */ - /*! \brief 1E.800E.8 R/W MSS Ingress Clear Count - AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressClearCount - - Default = 0x0 - - 1 = Clear all MIB counters - - - Notes: - If this bit is set to 1, all MIB counters will be cleared. */ - unsigned int mssIngressClearCount : 1; /* 1E.800E.8 R/W Default = 0x0 */ - /* 1 = Clear all MIB counters - */ - /*! \brief 1E.800E.9 R/W MSS Ingress High Priority - AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressHighPriority - - Default = 0x0 - - 1 = MIB counter clear on read enable - - - Notes: - If this bit is set to 1, read is given high priority and the MIB count value becomes 0 after read. */ - unsigned int mssIngressHighPriority : 1; /* 1E.800E.9 R/W Default = 0x0 */ - /* 1 = MIB counter clear on read enable - */ - /*! \brief 1E.800E.A R/W MSS Ingress Remove SECTag - AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressRemoveSectag - - Default = 0x0 - - 1 = Enable removal of SECTag - - - Notes: - If this bit is set and either of the following two conditions occurs, the SECTag will be removed. - Controlled packet and either the SA or SC is invalid. - IGPRC miss. */ - unsigned int mssIngressRemoveSectag : 1; /* 1E.800E.A R/W Default = 0x0 */ - /* 1 = Enable removal of SECTag - */ - /*! \brief 1E.800E.C:B R/W MSS Ingress Global Validate Frames [1:0] - AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressGlobalValidateFrames - - Default = 0x0 - - Default validate frames configuration - - - Notes: - If the SC is invalid or if an IGPRC miss packet condition occurs, this default will be used for the validate frames configuration instead of the validate frame entry in the Ingress SC Table (IGSCT). */ - unsigned int mssIngressGlobalValidateFrames : 2; /* 1E.800E.C:B R/W Default = 0x0 */ - /* Default validate frames configuration - */ - /*! \brief 1E.800E.D R/W MSS Ingress ICV LSB 8 Bytes Enable - AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressIcvLsb_8BytesEnable - - Default = 0x0 - - 1 = Use LSB - 0 = Use MSB - - - - Notes: - This bit selects MSB or LSB 8 bytes selection in the case where the ICV is 8 bytes. - 0 = MSB is used. */ - unsigned int mssIngressIcvLsb_8BytesEnable : 1; /* 1E.800E.D R/W Default = 0x0 */ - /* 1 = Use LSB - 0 = Use MSB - - */ - unsigned int reserved0 : 2; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Ingress Control Register */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssIngressControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress SA Control Register: 1E.8010 */ -/* MSS Ingress SA Control Register: 1E.8010 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress SA Control Register */ - union - { - struct - { - /*! \brief 1E.8010.F:0 R/W MSS Ingress SA Threshold LSW [F:0] - AQ_MssIngressSaControlRegister_HHD.u0.bits_0.mssIngressSaThresholdLSW - - Default = 0x0000 - - SA threshold bits 15:0 - - - Notes: - Ingress PN threshold to generate SA threshold interrupt. */ - unsigned int mssIngressSaThresholdLSW : 16; /* 1E.8010.F:0 R/W Default = 0x0000 */ - /* SA threshold bits 15:0 - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Ingress SA Control Register */ - union - { - struct - { - /*! \brief 1E.8011.F:0 R/W MSS Ingress SA Threshold MSW [1F:10] - AQ_MssIngressSaControlRegister_HHD.u1.bits_1.mssIngressSaThresholdMSW - - Default = 0x0000 - - SA threshold bits 31:16 - - - Notes: - Ingress PN threshold to generate SA threshold interrupt. */ - unsigned int mssIngressSaThresholdMSW : 16; /* 1E.8011.F:0 R/W Default = 0x0000 */ - /* SA threshold bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssIngressSaControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress Interrupt Status Register: 1E.802E */ -/* MSS Ingress Interrupt Status Register: 1E.802E */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress Interrupt Status Register */ - union - { - struct - { - /*! \brief 1E.802E.0 COW MSS Master Ingress Interrupt - AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssMasterIngressInterrupt - - Default = 0x0 - - 1 = Interrupt - - - Notes: - Write to 1 to clear. This bit is set when any one of the above interrupt and the corresponding interrupt enable are both set. The interrupt enable for this bit must also be set for this bit to be set. */ - unsigned int mssMasterIngressInterrupt : 1; /* 1E.802E.0 COW Default = 0x0 */ - /* 1 = Interrupt - */ - /*! \brief 1E.802E.1 COW MSS Ingress SA Expired Interrupt - AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressSaExpiredInterrupt - - Default = 0x0 - - 1 = Interrupt - - - Notes: - Write to 1 to clear. This bit is set when the SA PN reaches all ones saturation. */ - unsigned int mssIngressSaExpiredInterrupt : 1; /* 1E.802E.1 COW Default = 0x0 */ - /* 1 = Interrupt - */ - /*! \brief 1E.802E.2 COW MSS Ingress SA Threshold Expired Interrupt - AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressSaThresholdExpiredInterrupt - - Default = 0x0 - - 1 = Interrupt - - - Notes: - Write to 1 to clear. This bit is set when the SA PN reaches the See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . */ - unsigned int mssIngressSaThresholdExpiredInterrupt : 1; /* 1E.802E.2 COW Default = 0x0 */ - /* 1 = Interrupt - */ - /*! \brief 1E.802E.3 COW MSS Ingress ICV Error Interrupt - AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressIcvErrorInterrupt - - Default = 0x0 - - 1 = Interrupt - - - Notes: - Write to 1 to clear. */ - unsigned int mssIngressIcvErrorInterrupt : 1; /* 1E.802E.3 COW Default = 0x0 */ - /* 1 = Interrupt - */ - /*! \brief 1E.802E.4 COW MSS Ingress Replay Error Interrupt - AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressReplayErrorInterrupt - - Default = 0x0 - - 1 = Interrupt - - - Notes: - Write to 1 to clear. */ - unsigned int mssIngressReplayErrorInterrupt : 1; /* 1E.802E.4 COW Default = 0x0 */ - /* 1 = Interrupt - */ - /*! \brief 1E.802E.5 COW MSS Ingress MIB Saturation Interrupt - AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressMibSaturationInterrupt - - Default = 0x0 - - 1 = Interrupt - - - Notes: - Write to 1 to clear. This bit is set when the MIB counters reaches all ones saturation. */ - unsigned int mssIngressMibSaturationInterrupt : 1; /* 1E.802E.5 COW Default = 0x0 */ - /* 1 = Interrupt - */ - /*! \brief 1E.802E.6 COW MSS Ingress ECC Error Interrupt - AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressEccErrorInterrupt - - Default = 0x0 - - 1 = Interrupt - - - Notes: - Write to 1 to clear. */ - unsigned int mssIngressEccErrorInterrupt : 1; /* 1E.802E.6 COW Default = 0x0 */ - /* 1 = Interrupt - */ - /*! \brief 1E.802E.7 COW MSS Ingress TCI E/C Error Interrupt - AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressTciE_cErrorInterrupt - - Default = 0x0 - - 1 = Interrupt - - - Notes: - Write to 1 to clear. This error occurs when the TCI E bit is 1 and the TCI C bit is 0. The packet is not dropped, uncontrolled, or untagged. */ - unsigned int mssIngressTciE_cErrorInterrupt : 1; /* 1E.802E.7 COW Default = 0x0 */ - /* 1 = Interrupt - */ - /*! \brief 1E.802E.8 COW MSS Ingress IGPOC Miss Interrupt - AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressIgpocMissInterrupt - - Default = 0x0 - - 1 = Interrupt - - */ - unsigned int mssIngressIgpocMissInterrupt : 1; /* 1E.802E.8 COW Default = 0x0 */ - /* 1 = Interrupt - */ - unsigned int reserved0 : 7; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Ingress Interrupt Status Register */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssIngressInterruptStatusRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress Interrupt Mask Register: 1E.8030 */ -/* MSS Ingress Interrupt Mask Register: 1E.8030 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress Interrupt Mask Register */ - union - { - struct - { - /*! \brief 1E.8030.0 R/W MSS Ingress Master Interrupt Enable - AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressMasterInterruptEnable - - Default = 0x0 - - 1 = Interrupt enabled - - */ - unsigned int mssIngressMasterInterruptEnable : 1; /* 1E.8030.0 R/W Default = 0x0 */ - /* 1 = Interrupt enabled - */ - /*! \brief 1E.8030.1 R/W MSS Ingress SA Expired Interrupt Enable - AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressSaExpiredInterruptEnable - - Default = 0x0 - - 1 = Interrupt enabled - - */ - unsigned int mssIngressSaExpiredInterruptEnable : 1; /* 1E.8030.1 R/W Default = 0x0 */ - /* 1 = Interrupt enabled - */ - /*! \brief 1E.8030.2 R/W MSS Ingress SA Threshold Expired Interrupt Enable - AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressSaThresholdExpiredInterruptEnable - - Default = 0x0 - - 1 = Interrupt enabled - - */ - unsigned int mssIngressSaThresholdExpiredInterruptEnable : 1; /* 1E.8030.2 R/W Default = 0x0 */ - /* 1 = Interrupt enabled - */ - /*! \brief 1E.8030.3 R/W MSS Ingress ICV Error Interrupt Enable - AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressIcvErrorInterruptEnable - - Default = 0x0 - - 1 = Interrupt enabled - - */ - unsigned int mssIngressIcvErrorInterruptEnable : 1; /* 1E.8030.3 R/W Default = 0x0 */ - /* 1 = Interrupt enabled - */ - /*! \brief 1E.8030.4 R/W MSS Ingress Replay Error Interrupt Enable - AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressReplayErrorInterruptEnable - - Default = 0x0 - - 1 = Interrupt enabled - - */ - unsigned int mssIngressReplayErrorInterruptEnable : 1; /* 1E.8030.4 R/W Default = 0x0 */ - /* 1 = Interrupt enabled - */ - /*! \brief 1E.8030.5 R/W MSS Ingress MIB Saturation Interrupt Enable - AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressMibSaturationInterruptEnable - - Default = 0x0 - - 1 = Interrupt enabled - - */ - unsigned int mssIngressMibSaturationInterruptEnable : 1; /* 1E.8030.5 R/W Default = 0x0 */ - /* 1 = Interrupt enabled - */ - /*! \brief 1E.8030.6 R/W MSS Ingress ECC Error Interrupt Enable - AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressEccErrorInterruptEnable - - Default = 0x0 - - 1 = Interrupt enabled - - */ - unsigned int mssIngressEccErrorInterruptEnable : 1; /* 1E.8030.6 R/W Default = 0x0 */ - /* 1 = Interrupt enabled - */ - /*! \brief 1E.8030.7 R/W MSS Ingress TCI E/C Error Interrupt Enable - AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressTciE_cErrorInterruptEnable - - Default = 0x0 - - 1 = Interrupt enabled - - */ - unsigned int mssIngressTciE_cErrorInterruptEnable : 1; /* 1E.8030.7 R/W Default = 0x0 */ - /* 1 = Interrupt enabled - */ - /*! \brief 1E.8030.8 R/W MSS Ingress IGPOC Miss Interrupt Enable - AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressIgpocMissInterruptEnable - - Default = 0x0 - - 1 = Interrupt enabled - - */ - unsigned int mssIngressIgpocMissInterruptEnable : 1; /* 1E.8030.8 R/W Default = 0x0 */ - /* 1 = Interrupt enabled - */ - unsigned int reserved0 : 7; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Ingress Interrupt Mask Register */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssIngressInterruptMaskRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress SA ICV Error Status Register: 1E.8032 */ -/* MSS Ingress SA ICV Error Status Register: 1E.8032 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress SA ICV Error Status Register */ - union - { - struct - { - /*! \brief 1E.8032.F:0 COW MSS Ingress SA ICV Error LSW [F:0] - AQ_MssIngressSaIcvErrorStatusRegister_HHD.u0.bits_0.mssIngressSaIcvErrorLSW - - Default = 0x0000 - - SA ICV error bits 15:0 - - - Notes: - When set, these bits identify the SA that has an ICV error. Write these bits to 1 to clear. */ - unsigned int mssIngressSaIcvErrorLSW : 16; /* 1E.8032.F:0 COW Default = 0x0000 */ - /* SA ICV error bits 15:0 - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Ingress SA ICV Error Status Register */ - union - { - struct - { - /*! \brief 1E.8033.F:0 COW MSS Ingress SA ICV Error MSW [1F:10] - AQ_MssIngressSaIcvErrorStatusRegister_HHD.u1.bits_1.mssIngressSaIcvErrorMSW - - Default = 0x0000 - - SA ICV error bits 31:16 - - - Notes: - When set, these bits identify the SA that has an ICV error. Write these bits to 1 to clear. */ - unsigned int mssIngressSaIcvErrorMSW : 16; /* 1E.8033.F:0 COW Default = 0x0000 */ - /* SA ICV error bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssIngressSaIcvErrorStatusRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress SA Replay Error Status Register: 1E.8034 */ -/* MSS Ingress SA Replay Error Status Register: 1E.8034 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress SA Replay Error Status Register */ - union - { - struct - { - /*! \brief 1E.8034.F:0 COW MSS Ingress SA Replay Error LSW [F:0] - AQ_MssIngressSaReplayErrorStatusRegister_HHD.u0.bits_0.mssIngressSaReplayErrorLSW - - Default = 0x0000 - - SA replay error bits 15:0 - - - Notes: - When set, these bits identify the SA that has a replay error. Write these bits to 1 to clear. */ - unsigned int mssIngressSaReplayErrorLSW : 16; /* 1E.8034.F:0 COW Default = 0x0000 */ - /* SA replay error bits 15:0 - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Ingress SA Replay Error Status Register */ - union - { - struct - { - /*! \brief 1E.8035.F:0 COW MSS Ingress SA Replay Error MSW [1F:10] - AQ_MssIngressSaReplayErrorStatusRegister_HHD.u1.bits_1.mssIngressSaReplayErrorMSW - - Default = 0x0000 - - SA replay error bits 31:16 - - - Notes: - When set, these bits identify the SA that has a replay error. Write these bits to 1 to clear. */ - unsigned int mssIngressSaReplayErrorMSW : 16; /* 1E.8035.F:0 COW Default = 0x0000 */ - /* SA replay error bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssIngressSaReplayErrorStatusRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress SA Expired Status Register: 1E.8036 */ -/* MSS Ingress SA Expired Status Register: 1E.8036 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress SA Expired Status Register */ - union - { - struct - { - /*! \brief 1E.8036.F:0 ROS MSS Ingress SA Expired LSW [F:0] - AQ_MssIngressSaExpiredStatusRegister_HHD.u0.bits_0.mssIngressSaExpiredLSW - - Default = 0x0000 - - SA expired bits 15:0 - - - Notes: - When set, these bits identify the SA that has expired when the SA PN reaches all-ones saturation. Write these bits to 1 to clear. */ - unsigned int mssIngressSaExpiredLSW : 16; /* 1E.8036.F:0 ROS Default = 0x0000 */ - /* SA expired bits 15:0 - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Ingress SA Expired Status Register */ - union - { - struct - { - /*! \brief 1E.8037.F:0 ROS MSS Ingress SA Expired MSW [1F:10] - AQ_MssIngressSaExpiredStatusRegister_HHD.u1.bits_1.mssIngressSaExpiredMSW - - Default = 0x0000 - - SA expired bits 31:16 - - - Notes: - When set, these bits identify the SA that has expired when the SA PN reaches all-ones saturation. Write these bits to 1 to clear. */ - unsigned int mssIngressSaExpiredMSW : 16; /* 1E.8037.F:0 ROS Default = 0x0000 */ - /* SA expired bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssIngressSaExpiredStatusRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress SA Threshold Expired Status Register: 1E.8038 */ -/* MSS Ingress SA Threshold Expired Status Register: 1E.8038 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress SA Threshold Expired Status Register */ - union - { - struct - { - /*! \brief 1E.8038.F:0 ROS MSS Ingress SA Threshold Expired LSW [F:0] - AQ_MssIngressSaThresholdExpiredStatusRegister_HHD.u0.bits_0.mssIngressSaThresholdExpiredLSW - - Default = 0x0000 - - SA threshold expired bits 15:0 - - - Notes: - When set, these bits identify the SA that has expired when the SA PN has reached the configured threshold See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . Write these bits to 1 to clear. */ - unsigned int mssIngressSaThresholdExpiredLSW : 16; /* 1E.8038.F:0 ROS Default = 0x0000 */ - /* SA threshold expired bits 15:0 - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Ingress SA Threshold Expired Status Register */ - union - { - struct - { - /*! \brief 1E.8039.F:0 ROS MSS Ingress SA Threshold Expired MSW [1F:10] - AQ_MssIngressSaThresholdExpiredStatusRegister_HHD.u1.bits_1.mssIngressSaThresholdExpiredMSW - - Default = 0x0000 - - SA threshold expired bits 31:16 - - - Notes: - When set, these bits identify the SA that has expired when the SA PN has reached the configured threshold See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . Write these bits to 1 to clear. */ - unsigned int mssIngressSaThresholdExpiredMSW : 16; /* 1E.8039.F:0 ROS Default = 0x0000 */ - /* SA threshold expired bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssIngressSaThresholdExpiredStatusRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress ECC Interrupt Status Register: 1E.803A */ -/* MSS Ingress ECC Interrupt Status Register: 1E.803A */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress ECC Interrupt Status Register */ - union - { - struct - { - /*! \brief 1E.803A.F:0 R/W MSS Ingress SA ECC Error Interrupt LSW [F:0] - AQ_MssIngressEccInterruptStatusRegister_HHD.u0.bits_0.mssIngressSaEccErrorInterruptLSW - - Default = 0x0000 - - SA ECC error interrupt bits 15:0 - - - Notes: - When set to 1, indicates that an ECC error occured for the SA. */ - unsigned int mssIngressSaEccErrorInterruptLSW : 16; /* 1E.803A.F:0 R/W Default = 0x0000 */ - /* SA ECC error interrupt bits 15:0 - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Ingress ECC Interrupt Status Register */ - union - { - struct - { - /*! \brief 1E.803B.F:0 R/W MSS Ingress SA ECC Error Interrupt MSW [1F:10] - AQ_MssIngressEccInterruptStatusRegister_HHD.u1.bits_1.mssIngressSaEccErrorInterruptMSW - - Default = 0x0000 - - SA ECC error interrupt bits 31:16 - - - Notes: - When set to 1, indicates that an ECC error occured for the SA. */ - unsigned int mssIngressSaEccErrorInterruptMSW : 16; /* 1E.803B.F:0 R/W Default = 0x0000 */ - /* SA ECC error interrupt bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssIngressEccInterruptStatusRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress LUT Address Control Register: 1E.8080 */ -/* MSS Ingress LUT Address Control Register: 1E.8080 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress LUT Address Control Register */ - union - { - struct - { - /*! \brief 1E.8080.8:0 R/W MSS Ingress LUT Address [8:0] - AQ_MssIngressLutAddressControlRegister_HHD.u0.bits_0.mssIngressLutAddress - - Default = 0x000 - - LUT address - - */ - unsigned int mssIngressLutAddress : 9; /* 1E.8080.8:0 R/W Default = 0x000 */ - /* LUT address - */ - unsigned int reserved0 : 3; - /*! \brief 1E.8080.F:C R/W MSS Ingress LUT Select [3:0] - AQ_MssIngressLutAddressControlRegister_HHD.u0.bits_0.mssIngressLutSelect - - Default = 0x0 - - LUT select - - - Notes: - 0x0 : Ingress Pre-Security MAC Control FIlter (IGPRCTLF) LUT - 0x1 : Ingress Pre-Security Classification LUT (IGPRC) - 0x2 : Ingress Packet Format (IGPFMT) SAKey LUT - 0x3 : Ingress Packet Format (IGPFMT) SC/SA LUT - 0x4 : Ingress Post-Security Classification LUT (IGPOC) - 0x5 : Ingress Post-Security MAC Control Filter (IGPOCTLF) LUT - 0x6 : Ingress MIB (IGMIB) */ - unsigned int mssIngressLutSelect : 4; /* 1E.8080.F:C R/W Default = 0x0 */ - /* LUT select - */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_MssIngressLutAddressControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress LUT Control Register: 1E.8081 */ -/* MSS Ingress LUT Control Register: 1E.8081 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress LUT Control Register */ - union - { - struct - { - unsigned int reserved0 : 14; - /*! \brief 1E.8081.E R/W MSS Ingress LUT Read - AQ_MssIngressLutControlRegister_HHD.u0.bits_0.mssIngressLutRead - - Default = 0x0 - - 1 = LUT read - - - Notes: - Setting this bit to 1, will read the LUT. This bit will automatically clear to 0. */ - unsigned int mssIngressLutRead : 1; /* 1E.8081.E R/W Default = 0x0 */ - /* 1 = LUT read - */ - /*! \brief 1E.8081.F R/W MSS Ingress LUT Write - AQ_MssIngressLutControlRegister_HHD.u0.bits_0.mssIngressLutWrite - - Default = 0x0 - - 1 = LUT write - - - Notes: - Setting this bit to 1, will write the LUT. This bit will automatically clear to 0. */ - unsigned int mssIngressLutWrite : 1; /* 1E.8081.F R/W Default = 0x0 */ - /* 1 = LUT write - */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_MssIngressLutControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress LUT Data Control Register: 1E.80A0 */ -/* MSS Ingress LUT Data Control Register: 1E.80A0 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80A0.F:0 R/W MSS Ingress LUT Data 0 [F:0] - AQ_MssIngressLutDataControlRegister_HHD.u0.bits_0.mssIngressLutData_0 - - Default = 0x0000 - - LUT data bits 15:0 - - */ - unsigned int mssIngressLutData_0 : 16; /* 1E.80A0.F:0 R/W Default = 0x0000 */ - /* LUT data bits 15:0 - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80A1.F:0 R/W MSS Ingress LUT Data 1 [1F:10] - AQ_MssIngressLutDataControlRegister_HHD.u1.bits_1.mssIngressLutData_1 - - Default = 0x0000 - - LUT data bits 31:16 - - */ - unsigned int mssIngressLutData_1 : 16; /* 1E.80A1.F:0 R/W Default = 0x0000 */ - /* LUT data bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80A2.F:0 R/W MSS Ingress LUT Data 2 [2F:20] - AQ_MssIngressLutDataControlRegister_HHD.u2.bits_2.mssIngressLutData_2 - - Default = 0x0000 - - LUT data bits 47:32 - - */ - unsigned int mssIngressLutData_2 : 16; /* 1E.80A2.F:0 R/W Default = 0x0000 */ - /* LUT data bits 47:32 - */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80A3.F:0 R/W MSS Ingress LUT Data 3 [3F:30] - AQ_MssIngressLutDataControlRegister_HHD.u3.bits_3.mssIngressLutData_3 - - Default = 0x0000 - - LUT data bits 63:48 - - */ - unsigned int mssIngressLutData_3 : 16; /* 1E.80A3.F:0 R/W Default = 0x0000 */ - /* LUT data bits 63:48 - */ - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80A4.F:0 R/W MSS Ingress LUT Data 4 [4F:40] - AQ_MssIngressLutDataControlRegister_HHD.u4.bits_4.mssIngressLutData_4 - - Default = 0x0000 - - LUT data bits 79:64 - - */ - unsigned int mssIngressLutData_4 : 16; /* 1E.80A4.F:0 R/W Default = 0x0000 */ - /* LUT data bits 79:64 - */ - } bits_4; - uint16_t word_4; - } u4; - /*! \brief Union for bit and word level access of word 5 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80A5.F:0 R/W MSS Ingress LUT Data 5 [5F:50] - AQ_MssIngressLutDataControlRegister_HHD.u5.bits_5.mssIngressLutData_5 - - Default = 0x0000 - - LUT data bits 95:80 - - */ - unsigned int mssIngressLutData_5 : 16; /* 1E.80A5.F:0 R/W Default = 0x0000 */ - /* LUT data bits 95:80 - */ - } bits_5; - uint16_t word_5; - } u5; - /*! \brief Union for bit and word level access of word 6 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80A6.F:0 R/W MSS Ingress LUT Data 6 [6F:60] - AQ_MssIngressLutDataControlRegister_HHD.u6.bits_6.mssIngressLutData_6 - - Default = 0x0000 - - LUT data bits 111:96 - - */ - unsigned int mssIngressLutData_6 : 16; /* 1E.80A6.F:0 R/W Default = 0x0000 */ - /* LUT data bits 111:96 - */ - } bits_6; - uint16_t word_6; - } u6; - /*! \brief Union for bit and word level access of word 7 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80A7.F:0 R/W MSS Ingress LUT Data 7 [7F:70] - AQ_MssIngressLutDataControlRegister_HHD.u7.bits_7.mssIngressLutData_7 - - Default = 0x0000 - - LUT data bits 127:112 - - */ - unsigned int mssIngressLutData_7 : 16; /* 1E.80A7.F:0 R/W Default = 0x0000 */ - /* LUT data bits 127:112 - */ - } bits_7; - uint16_t word_7; - } u7; - /*! \brief Union for bit and word level access of word 8 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80A8.F:0 R/W MSS Ingress LUT Data 8 [8F:80] - AQ_MssIngressLutDataControlRegister_HHD.u8.bits_8.mssIngressLutData_8 - - Default = 0x0000 - - LUT data bits 143:128 - - */ - unsigned int mssIngressLutData_8 : 16; /* 1E.80A8.F:0 R/W Default = 0x0000 */ - /* LUT data bits 143:128 - */ - } bits_8; - uint16_t word_8; - } u8; - /*! \brief Union for bit and word level access of word 9 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80A9.F:0 R/W MSS Ingress LUT Data 9 [9F:90] - AQ_MssIngressLutDataControlRegister_HHD.u9.bits_9.mssIngressLutData_9 - - Default = 0x0000 - - LUT data bits 159:144 - - */ - unsigned int mssIngressLutData_9 : 16; /* 1E.80A9.F:0 R/W Default = 0x0000 */ - /* LUT data bits 159:144 - */ - } bits_9; - uint16_t word_9; - } u9; - /*! \brief Union for bit and word level access of word 10 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80AA.F:0 R/W MSS Ingress LUT Data 10 [AF:A0] - AQ_MssIngressLutDataControlRegister_HHD.u10.bits_10.mssIngressLutData_10 - - Default = 0x0000 - - LUT data bits 175:160 - - */ - unsigned int mssIngressLutData_10 : 16; /* 1E.80AA.F:0 R/W Default = 0x0000 */ - /* LUT data bits 175:160 - */ - } bits_10; - uint16_t word_10; - } u10; - /*! \brief Union for bit and word level access of word 11 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80AB.F:0 R/W MSS Ingress LUT Data 11 [BF:B0] - AQ_MssIngressLutDataControlRegister_HHD.u11.bits_11.mssIngressLutData_11 - - Default = 0x0000 - - LUT data bits 191:176 - - */ - unsigned int mssIngressLutData_11 : 16; /* 1E.80AB.F:0 R/W Default = 0x0000 */ - /* LUT data bits 191:176 - */ - } bits_11; - uint16_t word_11; - } u11; - /*! \brief Union for bit and word level access of word 12 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80AC.F:0 R/W MSS Ingress LUT Data 12 [CF:C0] - AQ_MssIngressLutDataControlRegister_HHD.u12.bits_12.mssIngressLutData_12 - - Default = 0x0000 - - LUT data bits 207:192 - - */ - unsigned int mssIngressLutData_12 : 16; /* 1E.80AC.F:0 R/W Default = 0x0000 */ - /* LUT data bits 207:192 - */ - } bits_12; - uint16_t word_12; - } u12; - /*! \brief Union for bit and word level access of word 13 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80AD.F:0 R/W MSS Ingress LUT Data 13 [DF:D0] - AQ_MssIngressLutDataControlRegister_HHD.u13.bits_13.mssIngressLutData_13 - - Default = 0x0000 - - LUT data bits 223:208 - - */ - unsigned int mssIngressLutData_13 : 16; /* 1E.80AD.F:0 R/W Default = 0x0000 */ - /* LUT data bits 223:208 - */ - } bits_13; - uint16_t word_13; - } u13; - /*! \brief Union for bit and word level access of word 14 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80AE.F:0 R/W MSS Ingress LUT Data 14 [EF:E0] - AQ_MssIngressLutDataControlRegister_HHD.u14.bits_14.mssIngressLutData_14 - - Default = 0x0000 - - LUT data bits 239:224 - - */ - unsigned int mssIngressLutData_14 : 16; /* 1E.80AE.F:0 R/W Default = 0x0000 */ - /* LUT data bits 239:224 - */ - } bits_14; - uint16_t word_14; - } u14; - /*! \brief Union for bit and word level access of word 15 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80AF.F:0 R/W MSS Ingress LUT Data 15 [FF:F0] - AQ_MssIngressLutDataControlRegister_HHD.u15.bits_15.mssIngressLutData_15 - - Default = 0x0000 - - LUT data bits 255:240 - - */ - unsigned int mssIngressLutData_15 : 16; /* 1E.80AF.F:0 R/W Default = 0x0000 */ - /* LUT data bits 255:240 - */ - } bits_15; - uint16_t word_15; - } u15; - /*! \brief Union for bit and word level access of word 16 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80B0.F:0 R/W MSS Ingress LUT Data 16 [10F:100] - AQ_MssIngressLutDataControlRegister_HHD.u16.bits_16.mssIngressLutData_16 - - Default = 0x0000 - - LUT data bits 271:256 - - */ - unsigned int mssIngressLutData_16 : 16; /* 1E.80B0.F:0 R/W Default = 0x0000 */ - /* LUT data bits 271:256 - */ - } bits_16; - uint16_t word_16; - } u16; - /*! \brief Union for bit and word level access of word 17 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80B1.F:0 R/W MSS Ingress LUT Data 17 [11F:110] - AQ_MssIngressLutDataControlRegister_HHD.u17.bits_17.mssIngressLutData_17 - - Default = 0x0000 - - LUT data bits 287:272 - - */ - unsigned int mssIngressLutData_17 : 16; /* 1E.80B1.F:0 R/W Default = 0x0000 */ - /* LUT data bits 287:272 - */ - } bits_17; - uint16_t word_17; - } u17; - /*! \brief Union for bit and word level access of word 18 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80B2.F:0 R/W MSS Ingress LUT Data 18 [12F:120] - AQ_MssIngressLutDataControlRegister_HHD.u18.bits_18.mssIngressLutData_18 - - Default = 0x0000 - - LUT data bits 303:288 - - */ - unsigned int mssIngressLutData_18 : 16; /* 1E.80B2.F:0 R/W Default = 0x0000 */ - /* LUT data bits 303:288 - */ - } bits_18; - uint16_t word_18; - } u18; - /*! \brief Union for bit and word level access of word 19 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80B3.F:0 R/W MSS Ingress LUT Data 19 [13F:130] - AQ_MssIngressLutDataControlRegister_HHD.u19.bits_19.mssIngressLutData_19 - - Default = 0x0000 - - LUT data bits 319:304 - - */ - unsigned int mssIngressLutData_19 : 16; /* 1E.80B3.F:0 R/W Default = 0x0000 */ - /* LUT data bits 319:304 - */ - } bits_19; - uint16_t word_19; - } u19; - /*! \brief Union for bit and word level access of word 20 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80B4.F:0 R/W MSS Ingress LUT Data 20 [14F:140] - AQ_MssIngressLutDataControlRegister_HHD.u20.bits_20.mssIngressLutData_20 - - Default = 0x0000 - - LUT data bits 335:320 - - */ - unsigned int mssIngressLutData_20 : 16; /* 1E.80B4.F:0 R/W Default = 0x0000 */ - /* LUT data bits 335:320 - */ - } bits_20; - uint16_t word_20; - } u20; - /*! \brief Union for bit and word level access of word 21 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80B5.F:0 R/W MSS Ingress LUT Data 21 [15F:150] - AQ_MssIngressLutDataControlRegister_HHD.u21.bits_21.mssIngressLutData_21 - - Default = 0x0000 - - LUT data bits 351:336 - - */ - unsigned int mssIngressLutData_21 : 16; /* 1E.80B5.F:0 R/W Default = 0x0000 */ - /* LUT data bits 351:336 - */ - } bits_21; - uint16_t word_21; - } u21; - /*! \brief Union for bit and word level access of word 22 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80B6.F:0 R/W MSS Ingress LUT Data 22 [16F:160] - AQ_MssIngressLutDataControlRegister_HHD.u22.bits_22.mssIngressLutData_22 - - Default = 0x0000 - - LUT data bits 367:352 - - */ - unsigned int mssIngressLutData_22 : 16; /* 1E.80B6.F:0 R/W Default = 0x0000 */ - /* LUT data bits 367:352 - */ - } bits_22; - uint16_t word_22; - } u22; - /*! \brief Union for bit and word level access of word 23 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80B7.F:0 R/W MSS Ingress LUT Data 23 [17F:170] - AQ_MssIngressLutDataControlRegister_HHD.u23.bits_23.mssIngressLutData_23 - - Default = 0x0000 - - LUT data bits 383:368 - - */ - unsigned int mssIngressLutData_23 : 16; /* 1E.80B7.F:0 R/W Default = 0x0000 */ - /* LUT data bits 383:368 - */ - } bits_23; - uint16_t word_23; - } u23; -} AQ_MssIngressLutDataControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line General Control Register: 1E.9004 */ -/* MSM Line General Control Register: 1E.9004 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line General Control Register */ - union - { - struct - { - /*! \brief 1E.9004.0 R/W MSM Line Tx Enable - AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineTxEnable - - Default = 0x0 - - 1 = Tx enable - - Notes: - MAC Rx path enable. Should be set to 1 to enable the MAC Rx path. Should be set to 0 to disable the MAC Rx path. */ - unsigned int msmLineTxEnable : 1; /* 1E.9004.0 R/W Default = 0x0 */ - /* 1 = Tx enable */ - /*! \brief 1E.9004.1 R/W MSM Line Rx Enable - AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineRxEnable - - Default = 0x0 - - 1 = Rx enable - - Notes: - MAC Tx path enable. Should be set to 1 to enable the MAC Tx path. Should be set to 0 to disable the MAC Tx path. */ - unsigned int msmLineRxEnable : 1; /* 1E.9004.1 R/W Default = 0x0 */ - /* 1 = Rx enable */ - unsigned int reserved0 : 1; - /*! \brief 1E.9004.3 R/W MSM Line WAN Mode - AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineWanMode - - Default = 0x0 - - 1 = WAN mode - 0 = LAN mode - - - Notes: - WAN mode enable. Sets WAN mode when set to 1 and LAN mode when set to 0. Note: When changing the mode, verifiy correct setting of the Tx IPG. */ - unsigned int msmLineWanMode : 1; /* 1E.9004.3 R/W Default = 0x0 */ - /* 1 = WAN mode - 0 = LAN mode - */ - /*! \brief 1E.9004.4 R/W MSM Line Promiscuous Mode - AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLinePromiscuousMode - - Default = 0x0 - - 1 = Promiscuous mode - - - Notes: - When set to 1, all frames are received without any MAC address filtering. */ - unsigned int msmLinePromiscuousMode : 1; /* 1E.9004.4 R/W Default = 0x0 */ - /* 1 = Promiscuous mode - */ - /*! \brief 1E.9004.5 R/W MSM Line PAD Enable - AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLinePadEnable - - Default = 0x0 - - 1 = Enable frame padding removal on Rx - - - Notes: - When set to 1, enable frame padding removal on the Rx path. If enabled, padding is removed before the frame is transferred to the MAC client application. If disabled, no padding is removed on the Rx by the MAC. - Note : On Tx, the MAC always adds padding as required. */ - unsigned int msmLinePadEnable : 1; /* 1E.9004.5 R/W Default = 0x0 */ - /* 1 = Enable frame padding removal on Rx - */ - /*! \brief 1E.9004.6 R/W MSM Line CRC Forward - AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineCrcForward - - Default = 0x0 - - 1 = Enable CRC forwarding - - - Notes: - When set to 1, the CRC field of the received frames is forwarded with the frame to the user application. If disabled, the CRC field is stripped from the frame. - Note : If padding is enabled ( See MAC PAD Enable set to 1), this bit is ignored. */ - unsigned int msmLineCrcForward : 1; /* 1E.9004.6 R/W Default = 0x0 */ - /* 1 = Enable CRC forwarding - */ - /*! \brief 1E.9004.7 R/W MSM Line Pause Forward - AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLinePauseForward - - Default = 0x0 - - 1 = Enable Pause forwarding - - - Notes: - Terminate or forward pause frames. If set to 1, pause frames are forwarded to the user application. In normal mode, when set to 0, pause frames are terminated and discarded within the MAC. */ - unsigned int msmLinePauseForward : 1; /* 1E.9004.7 R/W Default = 0x0 */ - /* 1 = Enable Pause forwarding - */ - /*! \brief 1E.9004.8 R/W MSM Line Pause Ignore - AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLinePauseIgnore - - Default = 0x0 - - 1 = Ignore pause frames - - - Notes: - Ignore pause frame quanta. If set to 1, received pause frames are ignored by the MAC. When set to 0, the Tx is stopped for the amount of time specified in the pause quanta received within the pause frame. */ - unsigned int msmLinePauseIgnore : 1; /* 1E.9004.8 R/W Default = 0x0 */ - /* 1 = Ignore pause frames - */ - /*! \brief 1E.9004.9 R/W MSM Line Tx Address Insert Enable - AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineTxAddressInsertEnable - - Default = 0x0 - - 1 = Insert Tx MAC source address - - - Notes: - Set the source MAC address on transmit. If set to 1, the MAC overwrites the source MAC address with the MAC programmed address in all transmitted frames. When set to 0, the source MAC address is transmitted unmodified from the MAC Tx client application. */ - unsigned int msmLineTxAddressInsertEnable : 1; /* 1E.9004.9 R/W Default = 0x0 */ - /* 1 = Insert Tx MAC source address - */ - /*! \brief 1E.9004.A R/W MSM Line Tx CRC Append - AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineTxCrcAppend - - Default = 0x0 - - 1 = Append Tx CRC - - - Notes: - Permanently enable CRC append on transmit. If set to 1, the Tx will append a CRC to all transmitted frames. If set to 0, CRC append can be controlled on a per frame basis using the pin ff_tx_crc. - This configuration bit is OR'ed with the external ff_tx_crc pin to instruct the Tx to append a CRC to transmitted frames. The ff_tx_crc pin is tied to 0. */ - unsigned int msmLineTxCrcAppend : 1; /* 1E.9004.A R/W Default = 0x0 */ - /* 1 = Append Tx CRC - */ - /*! \brief 1E.9004.B R/W MSM Line Tx Pad Enable - AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineTxPadEnable - - Default = 0x1 - - 1 = Enable Tx padding - - - Notes: - When set to 1, enable padding of frames in the Tx direction. When set to 0, the MAC will not extend frames from the application to a minimum of 64 bytes, allowing to transmit short frames (violating the Ethernet mimimum size requirements). Must be set to 1 for normal operation. */ - unsigned int msmLineTxPadEnable : 1; /* 1E.9004.B R/W Default = 0x1 */ - /* 1 = Enable Tx padding - */ - /*! \brief 1E.9004.C R/WSC MSM Line Soft Reset - AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineSoftReset - - Default = 0x0 - - 1 = Soft reset - - - Notes: - Software reset. Self clearing bit. When set to 1, resets all statistic counters as well as the Tx and Rx FIFOs. It should be issued after all traffic has been stopped as a result of clearing the Rx/Tx enable bits ( See MAC Rx Enable set to 0 and See MAC Tx Enable set to 0). - Note : Can lead to an Rx interface (ff_rx_xxx) violations to the application if the reset is issued in the middle of a receive frame transfer. Then the end of packet (assertion of ff_rx_eop) is lost and the application should be prepeared to handle this exception. */ - unsigned int msmLineSoftReset : 1; /* 1E.9004.C R/WSC Default = 0x0 */ - /* 1 = Soft reset - */ - /*! \brief 1E.9004.D R/W MSM Line Control Frame Enable - AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineControlFrameEnable - - Default = 0x0 - - 1 = Control frame enabled - - - Notes: - MAC control frame enable. When set to 1, the MAC control frames with any Opcode other than 0x0001 are accepted and forwarded to the client interface. When set to 0, MAC control frames with any opcode other than 0x0001 are silently discarded. */ - unsigned int msmLineControlFrameEnable : 1; /* 1E.9004.D R/W Default = 0x0 */ - /* 1 = Control frame enabled - */ - /*! \brief 1E.9004.E R/W MSM Line Rx Error Discard - AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineRxErrorDiscard - - Default = 0x0 - - 1 = Enable discard of received errored frames - - - Notes: - Rx errored frame discard enable. When set to 1, any frame received with an error is discarded and not forwarded to the client interface. When set to 0, errored frames are forwarded to the client interface with ff_rx_err asserted. - Note : It is recommended to set this bit to 1 only when store and forward operation is enabled (RX_SECTION_FULL TBD). */ - unsigned int msmLineRxErrorDiscard : 1; /* 1E.9004.E R/W Default = 0x0 */ - /* 1 = Enable discard of received errored frames - */ - /*! \brief 1E.9004.F R/W MSM Line PHY Tx Enable - AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLinePhyTxEnable - - Default = 0x0 - - 1 = Enable PHY Tx - - - Notes: - Directly controls the phy_tx_ena pin. */ - unsigned int msmLinePhyTxEnable : 1; /* 1E.9004.F R/W Default = 0x0 */ - /* 1 = Enable PHY Tx - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line General Control Register */ - union - { - struct - { - /*! \brief 1E.9005.0 R/W MSM Line Force Send IDLE - AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLineForceSendIdle - - Default = 0x0 - - 1 = Force send idle - - Notes: - When set to 1, suppress any frame transmissions and forces IDLE n the Tx interface instead of frames. This control affects the MAC reconciliation layer (RS) which acts after all MAC datapath has processed the frame. - Note : Does not have an effect on fault handling (i.e. reception of local fault will still cause transmit of remote fault). - Must be 0 for normal operation. */ - unsigned int msmLineForceSendIdle : 1; /* 1E.9005.0 R/W Default = 0x0 */ - /* 1 = Force send idle */ - /*! \brief 1E.9005.1 R/W MSM Line Length Check Disable - AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLineLengthCheckDisable - - Default = 0x0 - - 1 = Disable length check - - Notes: - Payload length check disable. When set to 0, the MAC checks the frames payload length with the frame length/type field. When set to 1, the payload length check is disabled. */ - unsigned int msmLineLengthCheckDisable : 1; /* 1E.9005.1 R/W Default = 0x0 */ - /* 1 = Disable length check */ - /*! \brief 1E.9005.2 R/W MSM Line IDLE Column Count Extend - AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLineIdleColumnCountExtend - - Default = 0x0 - - 1 = Extend IDLE column count - - Notes: - When set to 1, extends the RS layer IDLE column counter by 2x. The IEEE 802.3ae defines the fault condition to be cleared after 128 columns of IDLE have been received. If the MAC operates together with a WAN mode PCS (WIS) it may may happen (depending on PCS) that this period is too short to bridge the IDLE stuffing occurring in this mode, leading to a toggling fault indication. In this case, extending the counter helps to aoivd toggling fault indications. */ - unsigned int msmLineIdleColumnCountExtend : 1; /* 1E.9005.2 R/W Default = 0x0 */ - /* 1 = Extend IDLE column count */ - /*! \brief 1E.9005.3 R/W MSM Line Priority Flow Control Enable - AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLinePriorityFlowControlEnable - - Default = 0x0 - - 1 = Enable priority flow control - 0 = Enable link flow control - - - Notes: - Enable priority flow control (PFC) mode of operation. When set to 0, the MAC uses standard link pause frames. When set to 1, the MAC will transmit and accept PFC frames. */ - unsigned int msmLinePriorityFlowControlEnable : 1; /* 1E.9005.3 R/W Default = 0x0 */ - /* 1 = Enable priority flow control - 0 = Enable link flow control - */ - unsigned int reserved2 : 1; - /*! \brief 1E.9005.5 R/W MSM Line SFD Check Disable - AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLineSfdCheckDisable - - Default = 0x0 - - 1 = Disable SFD check - - - Notes: - Disable check of SFD (0xD5) character at frame start. When set to 1, the frame is accepted even if the SFD byte following the preamble is not 0xD5. When set to 0, a frame is accepted only if the SFD byte is found with the value 0xD5. */ - unsigned int msmLineSfdCheckDisable : 1; /* 1E.9005.5 R/W Default = 0x0 */ - /* 1 = Disable SFD check - */ - unsigned int reserved1 : 1; - /*! \brief 1E.9005.7 R/W MSM Line Tx Low Power IDLE Enable - AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLineTxLowPowerIdleEnable - - Default = 0x0 - - 1 = Transmit LPI enable - - - Notes: - Transmit low power IDLE enable. When set to 1, the MAC completes the transmission of the current frame and generates low power IDLE sequences (LPI) to the XGMII/SGMII. When set to 0, the MAC operates in normal mode. This bit is OR'ed with the reg_lowp_ena pin. */ - unsigned int msmLineTxLowPowerIdleEnable : 1; /* 1E.9005.7 R/W Default = 0x0 */ - /* 1 = Transmit LPI enable - */ - unsigned int reserved0 : 8; - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineGeneralControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line FIFO Control Register: 1E.900E */ -/* MSM Line FIFO Control Register: 1E.900E */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line FIFO Control Register */ - union - { - struct - { - /*! \brief 1E.900E.7:0 R/W MSM Line Rx FIFO Full Threshold [7:0] - AQ_MsmLineFifoControlRegister_HHD.u0.bits_0.msmLineRxFifoFullThreshold - - Default = 0x08 - - Rx FIFO full threshold - - Notes: - All threshold values are in steps of FIFO words. */ - unsigned int msmLineRxFifoFullThreshold : 8; /* 1E.900E.7:0 R/W Default = 0x08 */ - /* Rx FIFO full threshold */ - unsigned int reserved0 : 8; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line FIFO Control Register */ - union - { - struct - { - /*! \brief 1E.900F.7:0 R/W MSM Line Rx FIFO Empty Threshold [7:0] - AQ_MsmLineFifoControlRegister_HHD.u1.bits_1.msmLineRxFifoEmptyThreshold - - Default = 0x00 - - Rx FIFO empty threshold - - Notes: - All threshold values are in steps of FIFO words. */ - unsigned int msmLineRxFifoEmptyThreshold : 8; /* 1E.900F.7:0 R/W Default = 0x00 */ - /* Rx FIFO empty threshold */ - unsigned int reserved0 : 8; - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of MSM Line FIFO Control Register */ - union - { - struct - { - /*! \brief 1E.9010.5:0 R/W MSM Line Tx FIFO Full Threshold [5:0] - AQ_MsmLineFifoControlRegister_HHD.u2.bits_2.msmLineTxFifoFullThreshold - - Default = 0x08 - - Tx FIFO full threshold - - Notes: - All threshold values are in steps of FIFO words. */ - unsigned int msmLineTxFifoFullThreshold : 6; /* 1E.9010.5:0 R/W Default = 0x08 */ - /* Tx FIFO full threshold */ - unsigned int reserved0 : 10; - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of MSM Line FIFO Control Register */ - union - { - struct - { - /*! \brief 1E.9011.5:0 R/W MSM Line Tx FIFO Empty Threshold [5:0] - AQ_MsmLineFifoControlRegister_HHD.u3.bits_3.msmLineTxFifoEmptyThreshold - - Default = 0x00 - - Tx FIFO empty threshold - - Notes: - All threshold values are in steps of FIFO words. */ - unsigned int msmLineTxFifoEmptyThreshold : 6; /* 1E.9011.5:0 R/W Default = 0x00 */ - /* Tx FIFO empty threshold */ - unsigned int reserved0 : 10; - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of MSM Line FIFO Control Register */ - union - { - struct - { - /*! \brief 1E.9012.7:0 ROS MSM Line Rx FIFO Almost Full Threshold [7:0] - AQ_MsmLineFifoControlRegister_HHD.u4.bits_4.msmLineRxFifoAlmostFullThreshold - - Default = 0x00 - - Rx FIFO almost full threshold - - Notes: - Unused. */ - unsigned int msmLineRxFifoAlmostFullThreshold : 8; /* 1E.9012.7:0 ROS Default = 0x00 */ - /* Rx FIFO almost full threshold */ - unsigned int reserved0 : 8; - } bits_4; - uint16_t word_4; - } u4; - /*! \brief Union for bit and word level access of word 5 of MSM Line FIFO Control Register */ - union - { - struct - { - /*! \brief 1E.9013.7:0 ROS MSM Line Rx FIFO Almost Empty Threshold [7:0] - AQ_MsmLineFifoControlRegister_HHD.u5.bits_5.msmLineRxFifoAlmostEmptyThreshold - - Default = 0x00 - - Rx FIFO almost empty threshold - - Notes: - Unused. */ - unsigned int msmLineRxFifoAlmostEmptyThreshold : 8; /* 1E.9013.7:0 ROS Default = 0x00 */ - /* Rx FIFO almost empty threshold */ - unsigned int reserved0 : 8; - } bits_5; - uint16_t word_5; - } u5; - /*! \brief Union for bit and word level access of word 6 of MSM Line FIFO Control Register */ - union - { - struct - { - /*! \brief 1E.9014.7:0 ROS MSM Line Tx FIFO Almost Full Threshold [7:0] - AQ_MsmLineFifoControlRegister_HHD.u6.bits_6.msmLineTxFifoAlmostFullThreshold - - Default = 0x00 - - Tx FIFO almost full threshold - - Notes: - Unused. */ - unsigned int msmLineTxFifoAlmostFullThreshold : 8; /* 1E.9014.7:0 ROS Default = 0x00 */ - /* Tx FIFO almost full threshold */ - unsigned int reserved0 : 8; - } bits_6; - uint16_t word_6; - } u6; - /*! \brief Union for bit and word level access of word 7 of MSM Line FIFO Control Register */ - union - { - struct - { - /*! \brief 1E.9015.7:0 ROS MSM Line Tx FIFO Almost Empty Threshold [7:0] - AQ_MsmLineFifoControlRegister_HHD.u7.bits_7.msmLineTxFifoAlmostEmptyThreshold - - Default = 0x00 - - Tx FIFO almost empty threshold - - Notes: - Unused. */ - unsigned int msmLineTxFifoAlmostEmptyThreshold : 8; /* 1E.9015.7:0 ROS Default = 0x00 */ - /* Tx FIFO almost empty threshold */ - unsigned int reserved0 : 8; - } bits_7; - uint16_t word_7; - } u7; -} AQ_MsmLineFifoControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line General Status Register: 1E.9020 */ -/* MSM Line General Status Register: 1E.9020 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line General Status Register */ - union - { - struct - { - /*! \brief 1E.9020.0 BLH MSM Line Rx Local Fault - AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLineRxLocalFault - - - - Rx local fault detected - - Notes: - Latch high local fault status. Set to 1, whent he MAC detects Rx local fault sequences on the Rx interface. Reset to 0 after read and after reset. */ - unsigned int msmLineRxLocalFault : 1; /* 1E.9020.0 BLH */ - /* Rx local fault detected */ - /*! \brief 1E.9020.1 BLH MSM Line Rx Remote Fault - AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLineRxRemoteFault - - - - Rx remote fault detected - - Notes: - Latch high local fault status. Set to 1, whent he MAC detects Rx local fault sequences on the Rx interface. Reset to 0 after read and after reset. */ - unsigned int msmLineRxRemoteFault : 1; /* 1E.9020.1 BLH */ - /* Rx remote fault detected */ - /*! \brief 1E.9020.2 RO MSM Line PHY Loss of Signal - AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLinePhyLossOfSignal - - - - PHY loss of signal - - Notes: - PHY indicates loss of signal. This is the value of pin phy_los which is tied to 0. */ - unsigned int msmLinePhyLossOfSignal : 1; /* 1E.9020.2 RO */ - /* PHY loss of signal */ - /*! \brief 1E.9020.3 R/W MSM Line Timestamp Available - AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLineTimestampAvailable - - Default = 0x0 - - Timestamp available - - Notes: - Transmit timestamp available. Indicates that the timestamp of the last transmitted event frame (which had ff_tx_ts_frm=1) is available in the register See MAC Time Stamp Status 0 [F:0] and See MAC Time Stamp Status 1 [F:0] . To clear this bit, the bit must be written with a 1. - */ - unsigned int msmLineTimestampAvailable : 1; /* 1E.9020.3 R/W Default = 0x0 */ - /* Timestamp available */ - /*! \brief 1E.9020.4 RO MSM Line Rx Low Power IDLE - AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLineRxLowPowerIdle - - - - Rx LPI detected - - Notes: - Receive low power IDLE (LPI). Set to 1 when LPI is currently detected on the MAC Rx interface. Set to 0, when the MAC currently operates in normal mode. */ - unsigned int msmLineRxLowPowerIdle : 1; /* 1E.9020.4 RO */ - /* Rx LPI detected */ - /*! \brief 1E.9020.5 RO MSM Line Tx FIFO Empty - AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLineTxFifoEmpty - - - - Tx FIFO empty - - Notes: - When set to 1, indicates the Tx FIFO is empty. When set to 0, Tx FIFO is non-empty. */ - unsigned int msmLineTxFifoEmpty : 1; /* 1E.9020.5 RO */ - /* Tx FIFO empty */ - unsigned int reserved0 : 10; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line General Status Register */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineGeneralStatusRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Tx IPG Control Register: 1E.9022 */ -/* MSM Line Tx IPG Control Register: 1E.9022 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Tx IPG Control Register */ - union - { - struct - { - /*! \brief 1E.9022.5:0 R/W MSM Line Tx IPG Length [5:0] - AQ_MsmLineTxIpgControlRegister_HHD.u0.bits_0.msmLineTxIpgLength - - Default = 0x0C - - Tx IPG length - - Notes: - Tx inter-packet gap (IPG) value. Depending on LAN or WAN mode of operation. - LAN Mode : Number of octets in steps of 4. Valid values are 8, 12, 16,..., 100. DIC is supported for any setting > 8. A default of 12 must be set to conform to IEEE802.3ae. - WAN Mode : Stretch factor. Valid values are 4 ... 15. The stretch factor is calculated as (value+1)*8. A default of 12 must be set to conform to IEEE802.3ae (i.e. 13*8=104). A larger value shrinks the IPG (increasing bandwidth). - The reset value of 12 leads to IEEE802.3ae conformant behavior in both modes. - Note : WAN mode is only available in 10G mode of operation. */ - unsigned int msmLineTxIpgLength : 6; /* 1E.9022.5:0 R/W Default = 0x0C */ - /* Tx IPG length */ - unsigned int reserved0 : 10; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Tx IPG Control Register */ - union - { - struct - { - /*! \brief 1E.9023.F:0 MSM Line Tx IPG Reserved - AQ_MsmLineTxIpgControlRegister_HHD.u1.bits_1.msmLineTxIpgReserved - - - - Value always 0, writes ignored - */ - unsigned int msmLineTxIpgReserved : 16; /* 1E.9023.F:0 */ - /* Value always 0, writes ignored */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineTxIpgControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Tx Good Frames Counter Register: 1E.9040 */ -/* MSM Line Tx Good Frames Counter Register: 1E.9040 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Good Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9040.F:0 ROS MSM Line Tx Good Frames Counter 0 [F:0] - AQ_MsmLineTxGoodFramesCounterRegister_HHD.u0.bits_0.msmLineTxGoodFramesCounter_0 - - Default = 0x0000 - - Tx good frame counter bits 15:0 - - Notes: - Count of frames transmitted without error (Including pause frames). */ - unsigned int msmLineTxGoodFramesCounter_0 : 16; /* 1E.9040.F:0 ROS Default = 0x0000 */ - /* Tx good frame counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Good Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9041.F:0 ROS MSM Line Tx Good Frames Counter 1 [F:0] - AQ_MsmLineTxGoodFramesCounterRegister_HHD.u1.bits_1.msmLineTxGoodFramesCounter_1 - - Default = 0x0000 - - Tx good frame counter bits 31:16 - - - Notes: - Count of frames transmitted without error (Including pause frames). */ - unsigned int msmLineTxGoodFramesCounter_1 : 16; /* 1E.9041.F:0 ROS Default = 0x0000 */ - /* Tx good frame counter bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineTxGoodFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Rx Good Frames Counter Register: 1E.9044 */ -/* MSM Line Rx Good Frames Counter Register: 1E.9044 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Good Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9044.F:0 ROS MSM Line Rx Good Frames Counter 0 [F:0] - AQ_MsmLineRxGoodFramesCounterRegister_HHD.u0.bits_0.msmLineRxGoodFramesCounter_0 - - Default = 0x0000 - - Rx good frame counter bits 15:0 - - Notes: - Count of frames received without error (Including pause frames). */ - unsigned int msmLineRxGoodFramesCounter_0 : 16; /* 1E.9044.F:0 ROS Default = 0x0000 */ - /* Rx good frame counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Good Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9045.F:0 ROS MSM Line Rx Good Frames Counter 1 [F:0] - AQ_MsmLineRxGoodFramesCounterRegister_HHD.u1.bits_1.msmLineRxGoodFramesCounter_1 - - Default = 0x0000 - - Rx good frame counter bits 31:16 - - Notes: - Count of frames received without error (Including pause frames). */ - unsigned int msmLineRxGoodFramesCounter_1 : 16; /* 1E.9045.F:0 ROS Default = 0x0000 */ - /* Rx good frame counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineRxGoodFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Rx FCS Errors Counter Register: 1E.9048 */ -/* MSM Line Rx FCS Errors Counter Register: 1E.9048 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Rx FCS Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.9048.F:0 ROS MSM Line FCS Error Counter 0 [F:0] - AQ_MsmLineRxFcsErrorsCounterRegister_HHD.u0.bits_0.msmLineFcsErrorCounter_0 - - Default = 0x0000 - - Frame check sequence error counter bits 15:0 - - Notes: - Count of frames for which a CRC-32 Error is detected but the frame is otherwise of correct length. */ - unsigned int msmLineFcsErrorCounter_0 : 16; /* 1E.9048.F:0 ROS Default = 0x0000 */ - /* Frame check sequence error counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Rx FCS Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.9049.F:0 ROS MSM Line FCS Error Counter 1 [F:0] - AQ_MsmLineRxFcsErrorsCounterRegister_HHD.u1.bits_1.msmLineFcsErrorCounter_1 - - Default = 0x0000 - - Frame check sequence error counter bits 31:16 - - Notes: - Count of frames for which a CRC-32 Error is detected but the frame is otherwise of correct length. */ - unsigned int msmLineFcsErrorCounter_1 : 16; /* 1E.9049.F:0 ROS Default = 0x0000 */ - /* Frame check sequence error counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineRxFcsErrorsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Rx Alignment Errors Counter Register: 1E.904C */ -/* MSM Line Rx Alignment Errors Counter Register: 1E.904C */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Alignment Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.904C.F:0 ROS MSM Line Alignment Error Counter 0 [F:0] - AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD.u0.bits_0.msmLineAlignmentErrorCounter_0 - - Default = 0x0000 - - Alignment error counter bits 15:0 - - Notes: - Count of frames received with an alignment error. */ - unsigned int msmLineAlignmentErrorCounter_0 : 16; /* 1E.904C.F:0 ROS Default = 0x0000 */ - /* Alignment error counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Alignment Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.904D.F:0 ROS MSM Line Alignment Error Counter 1 [F:0] - AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD.u1.bits_1.msmLineAlignmentErrorCounter_1 - - Default = 0x0000 - - Alignment error counter bits 31:16 - - Notes: - Count of frames received with an alignment error. */ - unsigned int msmLineAlignmentErrorCounter_1 : 16; /* 1E.904D.F:0 ROS Default = 0x0000 */ - /* Alignment error counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Tx Pause Frames Counter Register: 1E.9050 */ -/* MSM Line Tx Pause Frames Counter Register: 1E.9050 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Pause Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9050.F:0 ROS MSM Line Tx Pause Frames Counter 0 [F:0] - AQ_MsmLineTxPauseFramesCounterRegister_HHD.u0.bits_0.msmLineTxPauseFramesCounter_0 - - Default = 0x0000 - - Tx pause frame counter bits 15:0 - - Notes: - Valid pause frames transmitted. */ - unsigned int msmLineTxPauseFramesCounter_0 : 16; /* 1E.9050.F:0 ROS Default = 0x0000 */ - /* Tx pause frame counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Pause Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9051.F:0 ROS MSM Line Tx Pause Frames Counter 1 [F:0] - AQ_MsmLineTxPauseFramesCounterRegister_HHD.u1.bits_1.msmLineTxPauseFramesCounter_1 - - Default = 0x0000 - - Tx pause frame counter bits 31:16 - - - Notes: - Valid pause frames transmitted. */ - unsigned int msmLineTxPauseFramesCounter_1 : 16; /* 1E.9051.F:0 ROS Default = 0x0000 */ - /* Tx pause frame counter bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineTxPauseFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Rx Pause Frames Counter Register: 1E.9054 */ -/* MSM Line Rx Pause Frames Counter Register: 1E.9054 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Pause Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9054.F:0 ROS MSM Line Rx Pause Frames Counter 0 [F:0] - AQ_MsmLineRxPauseFramesCounterRegister_HHD.u0.bits_0.msmLineRxPauseFramesCounter_0 - - Default = 0x0000 - - Rx pause frame counter bits 15:0 - - Notes: - Valid pause frames received. */ - unsigned int msmLineRxPauseFramesCounter_0 : 16; /* 1E.9054.F:0 ROS Default = 0x0000 */ - /* Rx pause frame counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Pause Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9055.F:0 ROS MSM Line Rx Pause Frames Counter 1 [F:0] - AQ_MsmLineRxPauseFramesCounterRegister_HHD.u1.bits_1.msmLineRxPauseFramesCounter_1 - - Default = 0x0000 - - Rx pause frame counter bits 31:16 - - Notes: - Valid pause frames received. */ - unsigned int msmLineRxPauseFramesCounter_1 : 16; /* 1E.9055.F:0 ROS Default = 0x0000 */ - /* Rx pause frame counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineRxPauseFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Rx Too Long Errors Counter Register: 1E.9058 */ -/* MSM Line Rx Too Long Errors Counter Register: 1E.9058 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Too Long Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.9058.F:0 ROS MSM Line Rx Too Long Errors Counter 0 [F:0] - AQ_MsmLineRxTooLongErrorsCounterRegister_HHD.u0.bits_0.msmLineRxTooLongErrorsCounter_0 - - Default = 0x0000 - - Too-long errors counter bits 15:0 - - Notes: - Frame received exceeded the maximum length programmed with register FRM_LGTH. */ - unsigned int msmLineRxTooLongErrorsCounter_0 : 16; /* 1E.9058.F:0 ROS Default = 0x0000 */ - /* Too-long errors counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Too Long Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.9059.F:0 ROS MSM Line Rx Too Long Errors Counter 1 [F:0] - AQ_MsmLineRxTooLongErrorsCounterRegister_HHD.u1.bits_1.msmLineRxTooLongErrorsCounter_1 - - Default = 0x0000 - - Too-long errors counter bits 31:16 - - Notes: - Frame received exceeded the maximum length programmed with register FRM_LGTH. */ - unsigned int msmLineRxTooLongErrorsCounter_1 : 16; /* 1E.9059.F:0 ROS Default = 0x0000 */ - /* Too-long errors counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineRxTooLongErrorsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Rx In Range Length Errors Counter Register: 1E.905C */ -/* MSM Line Rx In Range Length Errors Counter Register: 1E.905C */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Rx In Range Length Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.905C.F:0 ROS MSM Line Rx In Range Length Errors Counter 0 [F:0] - AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD.u0.bits_0.msmLineRxInRangeLengthErrorsCounter_0 - - Default = 0x0000 - - In-range-length errors counter bits 15:0 - - Notes: - A count of frames with a length/type field value between 46 (VLAN: 42) and less than 0x0600, that does not match the number of payload data octets received. Should count also if length/type field is less than 46 (VLAN: 42) and the frame is longer than 64 bytes. */ - unsigned int msmLineRxInRangeLengthErrorsCounter_0 : 16; /* 1E.905C.F:0 ROS Default = 0x0000 */ - /* In-range-length errors counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Rx In Range Length Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.905D.F:0 ROS MSM Line Rx In Range Length Errors Counter 1 [F:0] - AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD.u1.bits_1.msmLineRxInRangeLengthErrorsCounter_1 - - Default = 0x0000 - - In-range-length errors counter bits 31:16 - - Notes: - A count of frames with a length/type field value between 46 (VLAN: 42) and less than 0x0600, that does not match the number of payload data octets received. Should count also if length/type field is less than 46 (VLAN: 42) and the frame is longer than 64 bytes. */ - unsigned int msmLineRxInRangeLengthErrorsCounter_1 : 16; /* 1E.905D.F:0 ROS Default = 0x0000 */ - /* In-range-length errors counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Tx VLAN Frames Counter Register: 1E.9060 */ -/* MSM Line Tx VLAN Frames Counter Register: 1E.9060 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Tx VLAN Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9060.F:0 ROS MSM Line Tx VLAN Frames Counter 0 [F:0] - AQ_MsmLineTxVlanFramesCounterRegister_HHD.u0.bits_0.msmLineTxVlanFramesCounter_0 - - Default = 0x0000 - - Tx VLAN frames counter bits 15:0 - - Notes: - Valid VLAN tagged frames transmitted. */ - unsigned int msmLineTxVlanFramesCounter_0 : 16; /* 1E.9060.F:0 ROS Default = 0x0000 */ - /* Tx VLAN frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Tx VLAN Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9061.F:0 ROS MSM Line Tx VLAN Frames Counter 1 [F:0] - AQ_MsmLineTxVlanFramesCounterRegister_HHD.u1.bits_1.msmLineTxVlanFramesCounter_1 - - Default = 0x0000 - - Tx VLAN frames counter bits 31:16 - - Notes: - Valid VLAN tagged frames transmitted. */ - unsigned int msmLineTxVlanFramesCounter_1 : 16; /* 1E.9061.F:0 ROS Default = 0x0000 */ - /* Tx VLAN frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineTxVlanFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Rx VLAN Frames Counter Register: 1E.9064 */ -/* MSM Line Rx VLAN Frames Counter Register: 1E.9064 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Rx VLAN Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9064.F:0 ROS MSM Line Rx VLAN Frames Counter 0 [F:0] - AQ_MsmLineRxVlanFramesCounterRegister_HHD.u0.bits_0.msmLineRxVlanFramesCounter_0 - - Default = 0x0000 - - Rx VLAN frames counter bits 15:0 - - Notes: - Valid VLAN tagged frames received. */ - unsigned int msmLineRxVlanFramesCounter_0 : 16; /* 1E.9064.F:0 ROS Default = 0x0000 */ - /* Rx VLAN frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Rx VLAN Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9065.F:0 ROS MSM Line Rx VLAN Frames Counter 1 [F:0] - AQ_MsmLineRxVlanFramesCounterRegister_HHD.u1.bits_1.msmLineRxVlanFramesCounter_1 - - Default = 0x0000 - - Rx VLAN frames counter bits 31:16 - - Notes: - Valid VLAN tagged frames received. */ - unsigned int msmLineRxVlanFramesCounter_1 : 16; /* 1E.9065.F:0 ROS Default = 0x0000 */ - /* Rx VLAN frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineRxVlanFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Tx Octets Counter Register: 1E.9068 */ -/* MSM Line Tx Octets Counter Register: 1E.9068 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Octets Counter Register */ - union - { - struct - { - /*! \brief 1E.9068.F:0 ROS MSM Line Tx Octets Counter 0 [F:0] - AQ_MsmLineTxOctetsCounterRegister_HHD.u0.bits_0.msmLineTxOctetsCounter_0 - - Default = 0x0000 - - Tx octets counter bits 15:0 - - Notes: - All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ - unsigned int msmLineTxOctetsCounter_0 : 16; /* 1E.9068.F:0 ROS Default = 0x0000 */ - /* Tx octets counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Octets Counter Register */ - union - { - struct - { - /*! \brief 1E.9069.F:0 ROS MSM Line Tx Octets Counter 1 [F:0] - AQ_MsmLineTxOctetsCounterRegister_HHD.u1.bits_1.msmLineTxOctetsCounter_1 - - Default = 0x0000 - - Tx octets counter bits 31:16 - - Notes: - All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ - unsigned int msmLineTxOctetsCounter_1 : 16; /* 1E.9069.F:0 ROS Default = 0x0000 */ - /* Tx octets counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of MSM Line Tx Octets Counter Register */ - union - { - struct - { - /*! \brief 1E.906A.F:0 ROS MSM Line Tx Octets Counter 2 [F:0] - AQ_MsmLineTxOctetsCounterRegister_HHD.u2.bits_2.msmLineTxOctetsCounter_2 - - Default = 0x0000 - - Tx octets counter bits 47:32 - - Notes: - All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ - unsigned int msmLineTxOctetsCounter_2 : 16; /* 1E.906A.F:0 ROS Default = 0x0000 */ - /* Tx octets counter bits 47:32 */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of MSM Line Tx Octets Counter Register */ - union - { - struct - { - /*! \brief 1E.906B.F:0 ROS MSM Line Tx Octets Counter 3 [F:0] - AQ_MsmLineTxOctetsCounterRegister_HHD.u3.bits_3.msmLineTxOctetsCounter_3 - - Default = 0x0000 - - Tx octets counter bits 63:48 - - Notes: - All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ - unsigned int msmLineTxOctetsCounter_3 : 16; /* 1E.906B.F:0 ROS Default = 0x0000 */ - /* Tx octets counter bits 63:48 */ - } bits_3; - uint16_t word_3; - } u3; -} AQ_MsmLineTxOctetsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Rx Octets Counter Register: 1E.906C */ -/* MSM Line Rx Octets Counter Register: 1E.906C */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Octets Counter Register */ - union - { - struct - { - /*! \brief 1E.906C.F:0 ROS MSM Line Rx Octets Counter 0 [F:0] - AQ_MsmLineRxOctetsCounterRegister_HHD.u0.bits_0.msmLineRxOctetsCounter_0 - - Default = 0x0000 - - Rx octets counter bits 15:0 - - Notes: - All octets received except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames received. */ - unsigned int msmLineRxOctetsCounter_0 : 16; /* 1E.906C.F:0 ROS Default = 0x0000 */ - /* Rx octets counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Octets Counter Register */ - union - { - struct - { - /*! \brief 1E.906D.F:0 ROS MSM Line Rx Octets Counter 1 [F:0] - AQ_MsmLineRxOctetsCounterRegister_HHD.u1.bits_1.msmLineRxOctetsCounter_1 - - Default = 0x0000 - - Rx octets counter bits 31:16 - - Notes: - All octets received except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames received. */ - unsigned int msmLineRxOctetsCounter_1 : 16; /* 1E.906D.F:0 ROS Default = 0x0000 */ - /* Rx octets counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineRxOctetsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Rx Unicast Frames Counter Register: 1E.9070 */ -/* MSM Line Rx Unicast Frames Counter Register: 1E.9070 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Unicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9070.F:0 ROS MSM Line Rx Unicast Frames Counter 0 [F:0] - AQ_MsmLineRxUnicastFramesCounterRegister_HHD.u0.bits_0.msmLineRxUnicastFramesCounter_0 - - Default = 0x0000 - - Rx unicast frames counter bits 15:0 - - Notes: - Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '0'. */ - unsigned int msmLineRxUnicastFramesCounter_0 : 16; /* 1E.9070.F:0 ROS Default = 0x0000 */ - /* Rx unicast frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Unicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9071.F:0 ROS MSM Line Rx Unicast Frames Counter 1 [F:0] - AQ_MsmLineRxUnicastFramesCounterRegister_HHD.u1.bits_1.msmLineRxUnicastFramesCounter_1 - - Default = 0x0000 - - Rx unicast frames counter bits 31:16 - - Notes: - Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '0'. */ - unsigned int msmLineRxUnicastFramesCounter_1 : 16; /* 1E.9071.F:0 ROS Default = 0x0000 */ - /* Rx unicast frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineRxUnicastFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Rx Multicast Frames Counter Register: 1E.9074 */ -/* MSM Line Rx Multicast Frames Counter Register: 1E.9074 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Multicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9074.F:0 ROS MSM Line Rx Multicast Frames Counter 0 [F:0] - AQ_MsmLineRxMulticastFramesCounterRegister_HHD.u0.bits_0.msmLineRxMulticastFramesCounter_0 - - Default = 0x0000 - - Rx multicast frames counter bits 15:0 - - Notes: - Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '1' but not the broadcast address (all bits set '1' ). Pause frames are not counted. */ - unsigned int msmLineRxMulticastFramesCounter_0 : 16; /* 1E.9074.F:0 ROS Default = 0x0000 */ - /* Rx multicast frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Multicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9075.F:0 ROS MSM Line Rx Multicast Frames Counter 1 [F:0] - AQ_MsmLineRxMulticastFramesCounterRegister_HHD.u1.bits_1.msmLineRxMulticastFramesCounter_1 - - Default = 0x0000 - - Rx multicast frames counter bits 31:16 - - Notes: - Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '1' but not the broadcast address (all bits set '1' ). Pause frames are not counted. */ - unsigned int msmLineRxMulticastFramesCounter_1 : 16; /* 1E.9075.F:0 ROS Default = 0x0000 */ - /* Rx multicast frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineRxMulticastFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Rx Broadcast Frames Counter Register: 1E.9078 */ -/* MSM Line Rx Broadcast Frames Counter Register: 1E.9078 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Broadcast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9078.F:0 ROS MSM Line Rx Broadcast Frames Counter 0 [F:0] - AQ_MsmLineRxBroadcastFramesCounterRegister_HHD.u0.bits_0.msmLineRxBroadcastFramesCounter_0 - - Default = 0x0000 - - Rx broadcast frames counter bits 15:0 - - Notes: - Incremented with each valid frame received on the receive FIFO interface (FIFO) and all bits of the destination address were set '1'. */ - unsigned int msmLineRxBroadcastFramesCounter_0 : 16; /* 1E.9078.F:0 ROS Default = 0x0000 */ - /* Rx broadcast frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Broadcast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9079.F:0 ROS MSM Line Rx Broadcast Frames Counter 1 [F:0] - AQ_MsmLineRxBroadcastFramesCounterRegister_HHD.u1.bits_1.msmLineRxBroadcastFramesCounter_1 - - Default = 0x0000 - - Rx broadcast frames counter bits 31:16 - - Notes: - Incremented with each valid frame received on the receive FIFO interface (FIFO) and all bits of the destination address were set '1'. */ - unsigned int msmLineRxBroadcastFramesCounter_1 : 16; /* 1E.9079.F:0 ROS Default = 0x0000 */ - /* Rx broadcast frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineRxBroadcastFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Tx Errors Counter Register: 1E.907C */ -/* MSM Line Tx Errors Counter Register: 1E.907C */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.907C.F:0 ROS MSM Line Tx Errors Counter 0 [F:0] - AQ_MsmLineTxErrorsCounterRegister_HHD.u0.bits_0.msmLineTxErrorsCounter_0 - - Default = 0x0000 - - Rx errors counter bits 15:0 - - Notes: - Number of frames transmitted with error: - - FIFO Overflow Errors - - FIFO Underflow Errors */ - unsigned int msmLineTxErrorsCounter_0 : 16; /* 1E.907C.F:0 ROS Default = 0x0000 */ - /* Rx errors counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.907D.F:0 ROS MSM Line Tx Errors Counter 1 [F:0] - AQ_MsmLineTxErrorsCounterRegister_HHD.u1.bits_1.msmLineTxErrorsCounter_1 - - Default = 0x0000 - - Tx errors counter bits 31:16 - - Notes: - Number of frames transmitted with error: - - FIFO Overflow Errors - - FIFO Underflow Errors */ - unsigned int msmLineTxErrorsCounter_1 : 16; /* 1E.907D.F:0 ROS Default = 0x0000 */ - /* Tx errors counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineTxErrorsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Tx Unicast Frames Counter Register: 1E.9084 */ -/* MSM Line Tx Unicast Frames Counter Register: 1E.9084 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Unicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9084.F:0 ROS MSM Line Tx Unicast Frames Counter 0 [F:0] - AQ_MsmLineTxUnicastFramesCounterRegister_HHD.u0.bits_0.msmLineTxUnicastFramesCounter_0 - - Default = 0x0000 - - Tx unicast frames counter bits 15:0 - - Notes: - Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '0'. */ - unsigned int msmLineTxUnicastFramesCounter_0 : 16; /* 1E.9084.F:0 ROS Default = 0x0000 */ - /* Tx unicast frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Unicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9085.F:0 ROS MSM Line Tx Unicast Frames Counter 1 [F:0] - AQ_MsmLineTxUnicastFramesCounterRegister_HHD.u1.bits_1.msmLineTxUnicastFramesCounter_1 - - Default = 0x0000 - - Tx unicast frames counter bits 31:16 - - Notes: - Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '0'. */ - unsigned int msmLineTxUnicastFramesCounter_1 : 16; /* 1E.9085.F:0 ROS Default = 0x0000 */ - /* Tx unicast frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineTxUnicastFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Tx Multicast Frames Counter Register: 1E.9088 */ -/* MSM Line Tx Multicast Frames Counter Register: 1E.9088 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Multicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9088.F:0 ROS MSM Line Tx Multicast Frames Counter 0 [F:0] - AQ_MsmLineTxMulticastFramesCounterRegister_HHD.u0.bits_0.msmLineTxMulticastFramesCounter_0 - - Default = 0x0000 - - Tx multicast frames counter bits 15:0 - - Notes: - Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '1' but not the broadcast address (all bits '1'). */ - unsigned int msmLineTxMulticastFramesCounter_0 : 16; /* 1E.9088.F:0 ROS Default = 0x0000 */ - /* Tx multicast frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Multicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9089.F:0 ROS MSM Line Tx Multicast Frames Counter 1 [F:0] - AQ_MsmLineTxMulticastFramesCounterRegister_HHD.u1.bits_1.msmLineTxMulticastFramesCounter_1 - - Default = 0x0000 - - Tx multicast frames counter bits 31:16 - - Notes: - Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '1' but not the broadcast address (all bits '1'). */ - unsigned int msmLineTxMulticastFramesCounter_1 : 16; /* 1E.9089.F:0 ROS Default = 0x0000 */ - /* Tx multicast frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineTxMulticastFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Tx Broadcast Frames Counter Register: 1E.908C */ -/* MSM Line Tx Broadcast Frames Counter Register: 1E.908C */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Broadcast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.908C.F:0 ROS MSM Line Tx Broadcast Frames Counter 0 [F:0] - AQ_MsmLineTxBroadcastFramesCounterRegister_HHD.u0.bits_0.msmLineTxBroadcastFramesCounter_0 - - Default = 0x0000 - - Tx broadcast frames counter bits 15:0 - - Notes: - Incremented with each frame written to the FIFO interface and all bits of the destination address set to '1'. */ - unsigned int msmLineTxBroadcastFramesCounter_0 : 16; /* 1E.908C.F:0 ROS Default = 0x0000 */ - /* Tx broadcast frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Broadcast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.908D.F:0 ROS MSM Line Tx Broadcast Frames Counter 1 [F:0] - AQ_MsmLineTxBroadcastFramesCounterRegister_HHD.u1.bits_1.msmLineTxBroadcastFramesCounter_1 - - Default = 0x0000 - - Tx broadcast frames counter bits 31:16 - - Notes: - Incremented with each frame written to the FIFO interface and all bits of the destination address set to '1'. */ - unsigned int msmLineTxBroadcastFramesCounter_1 : 16; /* 1E.908D.F:0 ROS Default = 0x0000 */ - /* Tx broadcast frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineTxBroadcastFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Rx Errors Counter Register: 1E.90C8 */ -/* MSM Line Rx Errors Counter Register: 1E.90C8 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.90C8.F:0 ROS MSM Line Rx Errors Counter 0 [F:0] - AQ_MsmLineRxErrorsCounterRegister_HHD.u0.bits_0.msmLineRxErrorsCounter_0 - - Default = 0x0000 - - Rx errors counter bits 15:0 - - Notes: - Number of frames received with error: - - FIFO Overflow Errors - - CRC Errors - - Payload Length Errors - - Jabber and Oversized Errors - - Alignment Errors - - The dedicated Error Code (0xfe, not a code error) was received */ - unsigned int msmLineRxErrorsCounter_0 : 16; /* 1E.90C8.F:0 ROS Default = 0x0000 */ - /* Rx errors counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.90C9.F:0 ROS MSM Line Rx Errors Counter 1 [F:0] - AQ_MsmLineRxErrorsCounterRegister_HHD.u1.bits_1.msmLineRxErrorsCounter_1 - - Default = 0x0000 - - Rx errors counter bits 31:16 - - Notes: - Number of frames received with error: - - FIFO Overflow Errors - - CRC Errors - - Payload Length Errors - - Jabber and Oversized Errors - - Alignment Errors - - The dedicated Error Code (0xfe, not a code error) was received */ - unsigned int msmLineRxErrorsCounter_1 : 16; /* 1E.90C9.F:0 ROS Default = 0x0000 */ - /* Rx errors counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineRxErrorsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Control: 1E.C000 */ -/* Global Control: 1E.C000 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Control */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Control */ - union - { - struct - { - /*! \brief 1E.C001.0 R/W uP Run Stall - AQ_GlobalControl_HHD.u1.bits_1.upRunStall - - Default = 0x0 - - 1 = uP Run Stall - 0 = uP normal mode - - - Notes: - Deactivates the uP. */ - unsigned int upRunStall : 1; /* 1E.C001.0 R/W Default = 0x0 */ - /* 1 = uP Run Stall - 0 = uP normal mode - */ - unsigned int reserved1 : 5; - /*! \brief 1E.C001.6 R/W uP Run Stall Override - AQ_GlobalControl_HHD.u1.bits_1.upRunStallOverride - - Default = 0x0 - - 0 = uP Run Stall from "MDIO Boot Load" pin. - 1 = uP Run Stall from See MCP Run Stall bit - - - - Notes: - This bit selects the uP Run Stall from either the "MDIO Boot Load" pin or the See MCP Run Stall bit. Pin no longer brought out as deprecated. */ - unsigned int upRunStallOverride : 1; /* 1E.C001.6 R/W Default = 0x0 */ - /* 0 = uP Run Stall from "MDIO Boot Load" pin. - 1 = uP Run Stall from See MCP Run Stall bit - - */ - unsigned int reserved0 : 8; - /*! \brief 1E.C001.F R/W uP Reset - AQ_GlobalControl_HHD.u1.bits_1.upReset - - Default = 0x0 - - 1 = Reset - - - Notes: - Resets the uP and the PIF master and slave bus. Will be active for a minimum of 100 microseconds. */ - unsigned int upReset : 1; /* 1E.C001.F R/W Default = 0x0 */ - /* 1 = Reset - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_GlobalControl_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Reset Control: 1E.C006 */ -/* Global Reset Control: 1E.C006 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Reset Control */ - union - { - struct - { - unsigned int reserved1 : 14; - /*! \brief 1E.C006.E R/WPD Global MMD Reset Disable - AQ_GlobalResetControl_HHD.u0.bits_0.globalMMD_ResetDisable - - Provisionable Default = 0x0 - - 1 = Disable the S/W reset to the Global MMD registers - 0 = Enable the S/W reset to the Global MMD registers - - - Notes: - Setting this bit prevents a Global S/W reset or Global S/W reset from resetting the Global MMD registers */ - unsigned int globalMMD_ResetDisable : 1; /* 1E.C006.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Disable the S/W reset to the Global MMD registers - 0 = Enable the S/W reset to the Global MMD registers - */ - unsigned int reserved0 : 1; - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalResetControl_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Diagnostic Provisioning: 1E.C400 */ -/* Global Diagnostic Provisioning: 1E.C400 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Diagnostic Provisioning */ - union - { - struct - { - unsigned int reserved0 : 15; - /*! \brief 1E.C400.F R/WPD Enable Diagnostics - AQ_GlobalDiagnosticProvisioning_HHD.u0.bits_0.enableDiagnostics - - Provisionable Default = 0x1 - - 1 = Chip performs diagnostics on power-up - */ - unsigned int enableDiagnostics : 1; /* 1E.C400.F R/WPD Provisionable Default = 0x1 */ - /* 1 = Chip performs diagnostics on power-up */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalDiagnosticProvisioning_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Thermal Provisioning: 1E.C420 */ -/* Global Thermal Provisioning: 1E.C420 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Thermal Provisioning */ - union - { - struct - { - /*! \brief 1E.C420.F:0 R/WPD Reserved 0 [F:0] - AQ_GlobalThermalProvisioning_HHD.u0.bits_0.reserved_0 - - Provisionable Default = 0x0000 - - Internal reserved - do not modify - - */ - unsigned int reserved_0 : 16; /* 1E.C420.F:0 R/WPD Provisionable Default = 0x0000 */ - /* Internal reserved - do not modify - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Thermal Provisioning */ - union - { - struct - { - /*! \brief 1E.C421.F:0 R/WPD High Temp Failure Threshold [F:0] - AQ_GlobalThermalProvisioning_HHD.u1.bits_1.highTempFailureThreshold - - Provisionable Default = 0x4600 - - [F:0] of high temperature failure threshold - - Notes: - 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 70 degreesC. - - In XENPAK mode, F/W will use the XENPAK register 1.A000 - 1.A001: instead of this register. - - NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ - unsigned int highTempFailureThreshold : 16; /* 1E.C421.F:0 R/WPD Provisionable Default = 0x4600 */ - /* [F:0] of high temperature failure threshold */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global Thermal Provisioning */ - union - { - struct - { - /*! \brief 1E.C422.F:0 R/WPD Low Temp Failure Threshold [F:0] - AQ_GlobalThermalProvisioning_HHD.u2.bits_2.lowTempFailureThreshold - - Provisionable Default = 0x0000 - - [F:0] of low temperature failure threshold - - Notes: - 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 0 degreesC. - - In XENPAK mode, F/W will use the XENPAK register 1.A002 - 1.A003: instead of this register. - - NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ - unsigned int lowTempFailureThreshold : 16; /* 1E.C422.F:0 R/WPD Provisionable Default = 0x0000 */ - /* [F:0] of low temperature failure threshold */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global Thermal Provisioning */ - union - { - struct - { - /*! \brief 1E.C423.F:0 R/WPD High Temp Warning Threshold [F:0] - AQ_GlobalThermalProvisioning_HHD.u3.bits_3.highTempWarningThreshold - - Provisionable Default = 0x3C00 - - [F:0] of high temperature warning threshold - - Notes: - 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD008. Default is 60 degreesC. - - In XENPAK mode, F/W will use the XENPAK register 1.A004 - 1.A005: instead of this register. - - NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ - unsigned int highTempWarningThreshold : 16; /* 1E.C423.F:0 R/WPD Provisionable Default = 0x3C00 */ - /* [F:0] of high temperature warning threshold */ - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of Global Thermal Provisioning */ - union - { - struct - { - /*! \brief 1E.C424.F:0 R/WPD Low Temp Warning Threshold [F:0] - AQ_GlobalThermalProvisioning_HHD.u4.bits_4.lowTempWarningThreshold - - Provisionable Default = 0x0A00 - - [F:0] of low temperature warning threshold - - Notes: - 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 10 degreesC. - - In XENPAK mode, F/W will use the XENPAK register 1.A006 - 1.A007: instead of this register. - - NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ - unsigned int lowTempWarningThreshold : 16; /* 1E.C424.F:0 R/WPD Provisionable Default = 0x0A00 */ - /* [F:0] of low temperature warning threshold */ - } bits_4; - uint16_t word_4; - } u4; -} AQ_GlobalThermalProvisioning_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global LED Provisioning: 1E.C430 */ -/* Global LED Provisioning: 1E.C430 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global LED Provisioning */ - union - { - struct - { - /*! \brief 1E.C430.1:0 R/WPD LED #0 Activity Stretch [1:0] - AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0ActivityStretch - - Provisionable Default = 0x3 - - [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - - */ - unsigned int led_0ActivityStretch : 2; /* 1E.C430.1:0 R/WPD Provisionable Default = 0x3 */ - /* [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - */ - /*! \brief 1E.C430.2 R/WPD LED #0 Transmit Activity - AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0TransmitActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on transmit activity - - */ - unsigned int led_0TransmitActivity : 1; /* 1E.C430.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on transmit activity - */ - /*! \brief 1E.C430.3 R/WPD LED #0 Receive Activity - AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0ReceiveActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on receive activity - - */ - unsigned int led_0ReceiveActivity : 1; /* 1E.C430.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on receive activity - */ - /*! \brief 1E.C430.4 R/WPD LED #0 Connecting - AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0Connecting - - Provisionable Default = 0x0 - - 1 = LED is on when attempting to connect. - - */ - unsigned int led_0Connecting : 1; /* 1E.C430.4 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when attempting to connect. - */ - /*! \brief 1E.C430.5 R/WPD LED #0 100 Mb/s Link Established - AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0_100Mb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 100 Mb/s. - - */ - unsigned int led_0_100Mb_sLinkEstablished : 1; /* 1E.C430.5 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 100 Mb/s. - */ - /*! \brief 1E.C430.6 R/WPD LED #0 1 Gb/s Link Established - AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0_1Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 1 Gb/s - - */ - unsigned int led_0_1Gb_sLinkEstablished : 1; /* 1E.C430.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 1 Gb/s - */ - /*! \brief 1E.C430.7 R/WPD LED #0 10 Gb/s Link Established - AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0_10Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 10 Gb/s - - */ - unsigned int led_0_10Gb_sLinkEstablished : 1; /* 1E.C430.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 10 Gb/s - */ - /*! \brief 1E.C430.8 R/WPD LED #0 Manual Set - AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0ManualSet - - Provisionable Default = 0x0 - - 1 = LED On - - */ - unsigned int led_0ManualSet : 1; /* 1E.C430.8 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED On - */ - /*! \brief 1E.C430.D:9 R/WPD Reserved Provisioning C430 [4:0] - AQ_GlobalLedProvisioning_HHD.u0.bits_0.reservedProvisioningC430 - - Provisionable Default = 0x00 - - Reserved for future use - */ - unsigned int reservedProvisioningC430 : 5; /* 1E.C430.D:9 R/WPD Provisionable Default = 0x00 */ - /* Reserved for future use */ - unsigned int reserved0 : 2; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global LED Provisioning */ - union - { - struct - { - /*! \brief 1E.C431.1:0 R/WPD LED #1 Activity Stretch [1:0] - AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1ActivityStretch - - Provisionable Default = 0x3 - - [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - - */ - unsigned int led_1ActivityStretch : 2; /* 1E.C431.1:0 R/WPD Provisionable Default = 0x3 */ - /* [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - */ - /*! \brief 1E.C431.2 R/WPD LED #1 Transmit Activity - AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1TransmitActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on transmit activity - - */ - unsigned int led_1TransmitActivity : 1; /* 1E.C431.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on transmit activity - */ - /*! \brief 1E.C431.3 R/WPD LED #1 Receive Activity - AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1ReceiveActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on receive activity - - */ - unsigned int led_1ReceiveActivity : 1; /* 1E.C431.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on receive activity - */ - /*! \brief 1E.C431.4 R/WPD LED #1 Connecting - AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1Connecting - - Provisionable Default = 0x0 - - 1 = LED is on when attempting to connect. - - */ - unsigned int led_1Connecting : 1; /* 1E.C431.4 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when attempting to connect. - */ - /*! \brief 1E.C431.5 R/WPD LED #1 100 Mb/s Link Established - AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1_100Mb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 100 Mb/s. - - */ - unsigned int led_1_100Mb_sLinkEstablished : 1; /* 1E.C431.5 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 100 Mb/s. - */ - /*! \brief 1E.C431.6 R/WPD LED #1 1 Gb/s Link Established - AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1_1Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 1 Gb/s - - */ - unsigned int led_1_1Gb_sLinkEstablished : 1; /* 1E.C431.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 1 Gb/s - */ - /*! \brief 1E.C431.7 R/WPD LED #1 10 Gb/s Link Established - AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1_10Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 10 Gb/s - - */ - unsigned int led_1_10Gb_sLinkEstablished : 1; /* 1E.C431.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 10 Gb/s - */ - /*! \brief 1E.C431.8 R/WPD LED #1 Manual Set - AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1ManualSet - - Provisionable Default = 0x0 - - 1 = LED On - - */ - unsigned int led_1ManualSet : 1; /* 1E.C431.8 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED On - */ - /*! \brief 1E.C431.D:9 R/WPD Reserved Provisioning C431 [4:0] - AQ_GlobalLedProvisioning_HHD.u1.bits_1.reservedProvisioningC431 - - Provisionable Default = 0x00 - - Reserved for future use - */ - unsigned int reservedProvisioningC431 : 5; /* 1E.C431.D:9 R/WPD Provisionable Default = 0x00 */ - /* Reserved for future use */ - unsigned int reserved0 : 2; - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global LED Provisioning */ - union - { - struct - { - /*! \brief 1E.C432.1:0 R/WPD LED #2 Activity Stretch [1:0] - AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2ActivityStretch - - Provisionable Default = 0x3 - - [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - - */ - unsigned int led_2ActivityStretch : 2; /* 1E.C432.1:0 R/WPD Provisionable Default = 0x3 */ - /* [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - */ - /*! \brief 1E.C432.2 R/WPD LED #2 Transmit Activity - AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2TransmitActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on transmit activity - - */ - unsigned int led_2TransmitActivity : 1; /* 1E.C432.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on transmit activity - */ - /*! \brief 1E.C432.3 R/WPD LED #2 Receive Activity - AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2ReceiveActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on receive activity - - */ - unsigned int led_2ReceiveActivity : 1; /* 1E.C432.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on receive activity - */ - /*! \brief 1E.C432.4 R/WPD LED #2 Connecting - AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2Connecting - - Provisionable Default = 0x0 - - 1 = LED is on when attempting to connect. - - */ - unsigned int led_2Connecting : 1; /* 1E.C432.4 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when attempting to connect. - */ - /*! \brief 1E.C432.5 R/WPD LED #2 100 Mb/s Link Established - AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2_100Mb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 100 Mb/s. - */ - unsigned int led_2_100Mb_sLinkEstablished : 1; /* 1E.C432.5 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 100 Mb/s. */ - /*! \brief 1E.C432.6 R/WPD LED #2 1 Gb/s Link Established - AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2_1Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 1 Gb/s - - */ - unsigned int led_2_1Gb_sLinkEstablished : 1; /* 1E.C432.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 1 Gb/s - */ - /*! \brief 1E.C432.7 R/WPD LED #2 10 Gb/s Link Established - AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2_10Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 10 Gb/s - - */ - unsigned int led_2_10Gb_sLinkEstablished : 1; /* 1E.C432.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 10 Gb/s - */ - /*! \brief 1E.C432.8 R/WPD LED #2 Manual Set - AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2ManualSet - - Provisionable Default = 0x0 - - 1 = LED On - - */ - unsigned int led_2ManualSet : 1; /* 1E.C432.8 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED On - */ - /*! \brief 1E.C432.D:9 R/WPD Reserved Provisioning C432 [4:0] - AQ_GlobalLedProvisioning_HHD.u2.bits_2.reservedProvisioningC432 - - Provisionable Default = 0x00 - - Reserved for future use - */ - unsigned int reservedProvisioningC432 : 5; /* 1E.C432.D:9 R/WPD Provisionable Default = 0x00 */ - /* Reserved for future use */ - unsigned int reserved0 : 2; - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global LED Provisioning */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of Global LED Provisioning */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_4; - uint16_t word_4; - } u4; - /*! \brief Union for bit and word level access of word 5 of Global LED Provisioning */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_5; - uint16_t word_5; - } u5; - /*! \brief Union for bit and word level access of word 6 of Global LED Provisioning */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_6; - uint16_t word_6; - } u6; - /*! \brief Union for bit and word level access of word 7 of Global LED Provisioning */ - union - { - struct - { - /*! \brief 1E.C437.0 R/WPD LED Operation Mode - AQ_GlobalLedProvisioning_HHD.u7.bits_7.ledOperationMode - - Provisionable Default = 0x0 - - 1 = LED link activity in Mode #2 - 0 = LED link activity in Aquantia classic mode - - - Notes: - When set to 1, the LED blinking rate is based on Mode #2 algorithm. When set to 0, the LED blinking rate is based on the classic Aquantia algorithm. */ - unsigned int ledOperationMode : 1; /* 1E.C437.0 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED link activity in Mode #2 - 0 = LED link activity in Aquantia classic mode - */ - unsigned int reserved0 : 15; - } bits_7; - uint16_t word_7; - } u7; - /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ - union - { - struct - { - unsigned int reserved : 16; - } bits_8; - uint16_t word_8; - } u8; - /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ - union - { - struct - { - unsigned int reserved : 16; - } bits_9; - uint16_t word_9; - } u9; - /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ - union - { - struct - { - unsigned int reserved : 16; - } bits_10; - uint16_t word_10; - } u10; - /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ - union - { - struct - { - unsigned int reserved : 16; - } bits_11; - uint16_t word_11; - } u11; - /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ - union - { - struct - { - unsigned int reserved : 16; - } bits_12; - uint16_t word_12; - } u12; - /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ - union - { - struct - { - unsigned int reserved : 16; - } bits_13; - uint16_t word_13; - } u13; - /*! \brief Union for bit and word level access of word 14 of Global LED Provisioning */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_14; - uint16_t word_14; - } u14; -} AQ_GlobalLedProvisioning_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global General Provisioning: 1E.C440 */ -/* Global General Provisioning: 1E.C440 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global General Provisioning */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global General Provisioning */ - union - { - struct - { - unsigned int reserved3 : 2; - unsigned int reserved2 : 1; - /*! \brief 1E.C441.3 R/WPD MDIO Preamble Detection Disable - AQ_GlobalGeneralProvisioning_HHD.u1.bits_1.mdioPreambleDetectionDisable - - Provisionable Default = 0x0 - - 1 = Suppress preamble detection on MDIO - 0 = Enable preamble detection on MDIO - - */ - unsigned int mdioPreambleDetectionDisable : 1; /* 1E.C441.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = Suppress preamble detection on MDIO - 0 = Enable preamble detection on MDIO - */ - /*! \brief 1E.C441.4 R/WPD MDIO Drive Configuration - AQ_GlobalGeneralProvisioning_HHD.u1.bits_1.mdioDriveConfiguration - - Provisionable Default = 0x0 - - 0 = MDIO driver is in normal mode - 1 = MDIO driver is in open drain mode - - - Notes: - When the MDIO driver is in open drain mode during a read cycle, "0" data will be actively driven out of the MDIO, "1" data will set the MDIO driver in high impedance state and an external pullup will set the MDIO line to "1". The Turn-Around "0" will also be actively driven out of the MDIO, therefore in open drain mode, the Turn-Around is still "Z0". */ - unsigned int mdioDriveConfiguration : 1; /* 1E.C441.4 R/WPD Provisionable Default = 0x0 */ - /* 0 = MDIO driver is in normal mode - 1 = MDIO driver is in open drain mode - */ - unsigned int reserved1 : 8; - /*! \brief 1E.C441.D R/WPD MDIO Read MSW First Enable - AQ_GlobalGeneralProvisioning_HHD.u1.bits_1.mdioReadMSW_FirstEnable - - Provisionable Default = 0x0 - - 1 = MSW of counter must be read first - 0 = LSW of counter must be read first - - - Notes: - This bit configures whether the MSW or LSW must be read first for counters greater than 16 bits. */ - unsigned int mdioReadMSW_FirstEnable : 1; /* 1E.C441.D R/WPD Provisionable Default = 0x0 */ - /* 1 = MSW of counter must be read first - 0 = LSW of counter must be read first - */ - /*! \brief 1E.C441.E R/WPD MDIO Broadcast Mode Enable - AQ_GlobalGeneralProvisioning_HHD.u1.bits_1.mdioBroadcastModeEnable - - Provisionable Default = 0x0 - - 1 = Enable broadcast on address set in 1E.C446 - 0 = Disable broadcast on n address set in 1E.C446 - - - Notes: - When enabled, writes and load MMD address opcodes are supported. Read opcodes are ignored. */ - unsigned int mdioBroadcastModeEnable : 1; /* 1E.C441.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable broadcast on address set in 1E.C446 - 0 = Disable broadcast on n address set in 1E.C446 - */ - unsigned int reserved0 : 1; - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global General Provisioning */ - union - { - struct - { - /*! \brief 1E.C442.0 R/W Daisy Chain Reset - AQ_GlobalGeneralProvisioning_HHD.u2.bits_2.daisyChainReset - - Default = 0x0 - - 1 = Reset the daisy chain - - - Notes: - Toggling this bit from 0 to 1 will reload the IRAM and DRAM and reset the uP. The uP will be in uP run stall during the reload process. After the reload process, uP run stall will be de-asserted and the uP reset will be asserted. Note that before setting this bit, the See Soft Reset bit needs to be de-asserted. */ - unsigned int daisyChainReset : 1; /* 1E.C442.0 R/W Default = 0x0 */ - /* 1 = Reset the daisy chain - */ - unsigned int reserved0 : 15; - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global General Provisioning */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of Global General Provisioning */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_4; - uint16_t word_4; - } u4; - /*! \brief Union for bit and word level access of word 5 of Global General Provisioning */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_5; - uint16_t word_5; - } u5; - /*! \brief Union for bit and word level access of word 6 of Global General Provisioning */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_6; - uint16_t word_6; - } u6; - /*! \brief Union for bit and word level access of word 7 of Global General Provisioning */ - union - { - struct - { - /*! \brief 1E.C447.4:0 R/WPD MDIO Broadcast Address Configuration [4:0] - AQ_GlobalGeneralProvisioning_HHD.u7.bits_7.mdioBroadcastAddressConfiguration - - Provisionable Default = 0x1F - - Broadcast address - - - Notes: - Allows setting the broadcast address. By default this is set to 0x1F */ - unsigned int mdioBroadcastAddressConfiguration : 5; /* 1E.C447.4:0 R/WPD Provisionable Default = 0x1F */ - /* Broadcast address - */ - unsigned int reserved0 : 11; - } bits_7; - uint16_t word_7; - } u7; - /*! \brief Union for bit and word level access of word 8 of Global General Provisioning */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_8; - uint16_t word_8; - } u8; - /*! \brief Union for bit and word level access of word 9 of Global General Provisioning */ - union - { - struct - { - /*! \brief 1E.C449.6:0 R/W MDIO Preamble Length [6:0] - AQ_GlobalGeneralProvisioning_HHD.u9.bits_9.mdioPreambleLength - - Default = 0x02 - - MDIO Preamble Length - - */ - unsigned int mdioPreambleLength : 7; /* 1E.C449.6:0 R/W Default = 0x02 */ - /* MDIO Preamble Length - */ - unsigned int reserved0 : 9; - } bits_9; - uint16_t word_9; - } u9; -} AQ_GlobalGeneralProvisioning_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global NVR Provisioning: 1E.C450 */ -/* Global NVR Provisioning: 1E.C450 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global NVR Provisioning */ - union - { - struct - { - /*! \brief 1E.C450.1:0 R/WPD NVR Address Length [1:0] - AQ_GlobalNvrProvisioning_HHD.u0.bits_0.nvrAddressLength - - Provisionable Default = 0x2 - - NVR address length ranges from 0 bytes up to 3 bytes - - - Notes: - This sets the length of the address field used in read and write operations. Use of this field is enabled via Bit 8 of See Global NVR Provisioning 2: Address 1E.C451 . - */ - unsigned int nvrAddressLength : 2; /* 1E.C450.1:0 R/WPD Provisionable Default = 0x2 */ - /* NVR address length ranges from 0 bytes up to 3 bytes - */ - unsigned int reserved2 : 2; - /*! \brief 1E.C450.6:4 R/WPD NVR Dummy Length [2:0] - AQ_GlobalNvrProvisioning_HHD.u0.bits_0.nvrDummyLength - - Provisionable Default = 0x0 - - NVR dummy length ranges from 0 bytes to 4 bytes - - - Notes: - This sets the length of the dummy field used in some manufacturer's read status and write status operations. - */ - unsigned int nvrDummyLength : 3; /* 1E.C450.6:4 R/WPD Provisionable Default = 0x0 */ - /* NVR dummy length ranges from 0 bytes to 4 bytes - */ - unsigned int reserved1 : 1; - /*! \brief 1E.C450.A:8 R/WPD NVR Data Length [2:0] - AQ_GlobalNvrProvisioning_HHD.u0.bits_0.nvrDataLength - - Provisionable Default = 0x4 - - NVR data length ranges from 0 bytes to 4 bytes - - - Notes: - This sets the length of the data burst used in read and write operations. - */ - unsigned int nvrDataLength : 3; /* 1E.C450.A:8 R/WPD Provisionable Default = 0x4 */ - /* NVR data length ranges from 0 bytes to 4 bytes - */ - unsigned int reserved0 : 5; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global NVR Provisioning */ - union - { - struct - { - /*! \brief 1E.C451.7:0 R/WPD NVR Clock Divide [7:0] - AQ_GlobalNvrProvisioning_HHD.u1.bits_1.nvrClockDivide - - Provisionable Default = 0xA0 - - NVR clock divide. Clock frequency is divided by the NVR clock divide + 1 - - */ - unsigned int nvrClockDivide : 8; /* 1E.C451.7:0 R/WPD Provisionable Default = 0xA0 */ - /* NVR clock divide. Clock frequency is divided by the NVR clock divide + 1 - */ - /*! \brief 1E.C451.8 R/WPD NVR Address Length Override - AQ_GlobalNvrProvisioning_HHD.u1.bits_1.nvrAddressLengthOverride - - Provisionable Default = 0x0 - - 0 = NVR address length is based on the "NVR_SIZE" pin. - 1 = NVR address length is based on the See NVR Address Length [1:0] register - - - Notes: - When this bit = 0 and NVR_SIZE pin = 0, the NVR address length is 2 bytes. When this bit = 0 and the NVR_SIZE pin = 1, the NVR address length is 3 bytes. When this bit = 1 the NVR address length is from the See NVR Address Length [1:0] */ - unsigned int nvrAddressLengthOverride : 1; /* 1E.C451.8 R/WPD Provisionable Default = 0x0 */ - /* 0 = NVR address length is based on the "NVR_SIZE" pin. - 1 = NVR address length is based on the See NVR Address Length [1:0] register - */ - unsigned int reserved0 : 7; - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global NVR Provisioning */ - union - { - struct - { - /*! \brief 1E.C452.0 R/W NVR Daisy Chain Disable - AQ_GlobalNvrProvisioning_HHD.u2.bits_2.nvrDaisyChainDisable - - Default = 0x0 - - 1 = Disable the Daisy Chain - - - Notes: - When in daisy chain master mode, the daisy chain and MDIO can both access the SPI. Setting this bit to 1 will disable the daisy chain from accessing the SPI and force it into a reset state. */ - unsigned int nvrDaisyChainDisable : 1; /* 1E.C452.0 R/W Default = 0x0 */ - /* 1 = Disable the Daisy Chain - */ - /*! \brief 1E.C452.1 R/W NVR Daisy Chain Clock Divide Override - AQ_GlobalNvrProvisioning_HHD.u2.bits_2.nvrDaisyChainClockDivideOverride - - Default = 0x0 - - 1 = Override NVR clock divide when in daisy chain master mode - - - Notes: - When in daisy chain master mode, the clock divide configuration is received from the FLASH. This bit will override the clock divide configuration from the FLASH with the See NVR Clock Divide [7:0] . */ - unsigned int nvrDaisyChainClockDivideOverride : 1; /* 1E.C452.1 R/W Default = 0x0 */ - /* 1 = Override NVR clock divide when in daisy chain master mode - */ - unsigned int reserved0 : 14; - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global NVR Provisioning */ - union - { - struct - { - unsigned int reserved1 : 4; - /*! \brief 1E.C453.4 R/W NVR Reset - AQ_GlobalNvrProvisioning_HHD.u3.bits_3.nvrReset - - Default = 0x0 - - 1 = Reset SPI - - */ - unsigned int nvrReset : 1; /* 1E.C453.4 R/W Default = 0x0 */ - /* 1 = Reset SPI - */ - unsigned int reserved0 : 11; - } bits_3; - uint16_t word_3; - } u3; -} AQ_GlobalNvrProvisioning_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Reserved Provisioning: 1E.C470 */ -/* Global Reserved Provisioning: 1E.C470 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Reserved Provisioning */ - union - { - struct - { - unsigned int reserved2 : 4; - /*! \brief 1E.C470.4 R/WSC Initiate Cable Diagnostics - AQ_GlobalReservedProvisioning_HHD.u0.bits_0.initiateCableDiagnostics - - Default = 0x0 - - 1 = Perform cable diagnostics - - - Notes: - Perform cable diagnostics regardless of link state. If link is up, setting this bit will cause the link to drop while diagnostics are performed. This bit is self-clearing upon completion of the cable diagnostics. - - NOTE!! This is a processor intensive operation. Completion of this operation can also be monitored via 1E.C831.F */ - unsigned int initiateCableDiagnostics : 1; /* 1E.C470.4 R/WSC Default = 0x0 */ - /* 1 = Perform cable diagnostics - */ - unsigned int reserved1 : 3; - unsigned int reserved0 : 5; - /*! \brief 1E.C470.E:D R/WPD Extended MDI Diagnostics Select [1:0] - AQ_GlobalReservedProvisioning_HHD.u0.bits_0.extendedMdiDiagnosticsSelect - - Provisionable Default = 0x0 - - 0x0 = TDR Data - 0x1 = RFI Channel PSD - 0x2 = Noise PSD while the local Tx is Off - 0x3 = Noise PSD while the local Tx is On - - - Notes: - These bits select what sort of cable diagnostics to perform. For regular cable diagnostics, Bit F is set to zero, and the diagnostics are triggered by setting Bit 4. For extended diagnostics, Bit F is set to 1, and the desired extended diagnostics are selected by Bits E:D. The routine is then triggered by setting Bit 4. Each of the extended diagnostic routines present data for all for MDI pairs (A, B, C, D) consecutively, and after the data for each channel is gathered Bits F:D are reset. To get the data for the next pair, Bits F:D must be set back to the desired value (which must be the same as the initial channel). This continues until the data for all channels has been gathered. The address in memory where the data is stored is given in 1E.C802 and 1E.C804. - - For the case of PSD, the structure is as follows: - Int32 info - Int16 data[Len] - Info = Len << 16 | TxEnable << 8 | Pair (0 = A, etc.) - - For TDR: - Int32 info - Int16 tdr_A[Len] - Int16 tdr_B[Len] - Int16 tdr_C[Len] - Int16 tdr_D[Len] - - Info = Len << 16 | Channel - - TDR data is from the current pair to all other pairs. - - At the end of retrieving extended MDI diag data, the part will be reset. Conversely the only way to exit this routine once it starts is to issue a PMA reset. */ - unsigned int extendedMdiDiagnosticsSelect : 2; /* 1E.C470.E:D R/WPD Provisionable Default = 0x0 */ - /* 0x0 = TDR Data - 0x1 = RFI Channel PSD - 0x2 = Noise PSD while the local Tx is Off - 0x3 = Noise PSD while the local Tx is On - */ - /*! \brief 1E.C470.F R/WPD Diagnostics Select - AQ_GlobalReservedProvisioning_HHD.u0.bits_0.diagnosticsSelect - - Provisionable Default = 0x0 - - 1 = Provide Extended MDI Diagnostics Information. - 0 = Provide normal cable diagnostics - - - Notes: - These bits select what sort of cable diagnostics to perform. For regular cable diagnostics, Bit F is set to zero, and the diagnostics are triggered by setting Bit 4. For extended diagnostics, Bit F is set to 1, and the desired extended diagnostics are selected by Bits E:D. The routine is then triggered by setting Bit 4. Each of the extended diagnostic routines present data for all for MDI pairs (A, B, C, D) consecutively, and after the data for each channel is gathered Bits F:D are reset. To get the data for the next pair, Bits F:D must be set back to the desired value (which must be the same as the initial channel). This continues until the data for all channels has been gathered. The address in memory where the data is stored is given in 1E.C802 and 1E.C804. - - For the case of PSD, the structure is as follows: - Int32 info - Int16 data[Len] - Info = Len << 16 | TxEnable << 8 | Pair (0 = A, etc.) - - For TDR: - Int32 info - Int16 tdr_A[Len] - Int16 tdr_B[Len] - Int16 tdr_C[Len] - Int16 tdr_D[Len] - - Info = Len << 16 | Channel - - TDR data is from the current pair to all other pairs. - - At the end of retrieving extended MDI diag data, the part will be reset. Conversely the only way to exit this routine once it starts is to issue a PMA reset. */ - unsigned int diagnosticsSelect : 1; /* 1E.C470.F R/WPD Provisionable Default = 0x0 */ - /* 1 = Provide Extended MDI Diagnostics Information. - 0 = Provide normal cable diagnostics - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Reserved Provisioning */ - union - { - struct - { - /*! \brief 1E.C471.5:0 R/WuP Daisy-Chain Hop-Count Override Value [5:0] - AQ_GlobalReservedProvisioning_HHD.u1.bits_1.daisy_chainHop_countOverrideValue - - Default = 0x00 - - The value to use for the PHY's daisy-chain hop-count. Valid values are from 0 -> 47 - - - Notes: - Daisy-Chain Hop-Count Override should be used during MDIO boot-load operation, as the daisy-chain hop-count does not function when the daisy-chain is disabled (1E.C452.0). Setting this bit tells the processor where in the daisy-chain it is, so that the provisioning operation will function correctly. */ - unsigned int daisy_chainHop_countOverrideValue : 6; /* 1E.C471.5:0 R/WuP Default = 0x00 */ - /* The value to use for the PHY's daisy-chain hop-count. Valid values are from 0 -> 47 - */ - /*! \brief 1E.C471.6 R/WuP Enable Daisy-Chain Hop-Count Override - AQ_GlobalReservedProvisioning_HHD.u1.bits_1.enableDaisy_chainHop_countOverride - - Default = 0x0 - - 1 = Hop-count is set by Bits 5:0 - 0 = Hop-count is determined by the daisy-chain - - - Notes: - Daisy-Chain Hop-Count Override should be used during MDIO boot-load operation, as the daisy-chain hop-count does not function when the daisy-chain is disabled (1E.C452.0). Setting this bit tells the processor where in the daisy-chain it is, so that the provisioning operation will function correctly. */ - unsigned int enableDaisy_chainHop_countOverride : 1; /* 1E.C471.6 R/WuP Default = 0x0 */ - /* 1 = Hop-count is set by Bits 5:0 - 0 = Hop-count is determined by the daisy-chain - */ - unsigned int reserved0 : 9; - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global Reserved Provisioning */ - union - { - struct - { - /*! \brief 1E.C472.0 R/WPDuP Enable 5th Channel RFI Cancellation - AQ_GlobalReservedProvisioning_HHD.u2.bits_2.enable_5thChannelRfiCancellation - - Provisionable Default = 0x0 - - 1 = 5th channel and RFI cancellers operation enabled - 0 = 5th channel AFE is powered down, 5th channel digital is clock gated, RFI cancellers are disabled - - - Notes: - Note: The value of this bit at the time of Autonegotiation sets the local PHY behavior until the next time Autonegotiation occurs. */ - unsigned int enable_5thChannelRfiCancellation : 1; /* 1E.C472.0 R/WPDuP Provisionable Default = 0x0 */ - /* 1 = 5th channel and RFI cancellers operation enabled - 0 = 5th channel AFE is powered down, 5th channel digital is clock gated, RFI cancellers are disabled - */ - /*! \brief 1E.C472.1 R/WPDuP Enable XENPAK Register Space - AQ_GlobalReservedProvisioning_HHD.u2.bits_2.enableXenpakRegisterSpace - - Provisionable Default = 0x0 - - 1 = XENPAK register space enabled - 0 = XENPAK register space disabled - - */ - unsigned int enableXenpakRegisterSpace : 1; /* 1E.C472.1 R/WPDuP Provisionable Default = 0x0 */ - /* 1 = XENPAK register space enabled - 0 = XENPAK register space disabled - */ - /*! \brief 1E.C472.5:2 R/WPD External VDD Change Request [3:0] - AQ_GlobalReservedProvisioning_HHD.u2.bits_2.externalVddChangeRequest - - Provisionable Default = 0x0 - - The amount of VDD change requested by firmware, in mV (2's complement value). - - */ - unsigned int externalVddChangeRequest : 4; /* 1E.C472.5:2 R/WPD Provisionable Default = 0x0 */ - /* The amount of VDD change requested by firmware, in mV (2's complement value). - */ - /*! \brief 1E.C472.6 R/WPD Tunable External VDD Power Supply Present - AQ_GlobalReservedProvisioning_HHD.u2.bits_2.tunableExternalVddPowerSupplyPresent - - Provisionable Default = 0x0 - - 1 = Tunable external VDD power supply present - 0 = No tunable external VDD power supply present - - - Notes: - This bit must be set if tuning of external power supply is desired. */ - unsigned int tunableExternalVddPowerSupplyPresent : 1; /* 1E.C472.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = Tunable external VDD power supply present - 0 = No tunable external VDD power supply present - */ - unsigned int reserved1 : 7; - /*! \brief 1E.C472.E R/WPD Enable VDD Power Supply Tuning - AQ_GlobalReservedProvisioning_HHD.u2.bits_2.enableVddPowerSupplyTuning - - Provisionable Default = 0x0 - - 1 = Enable external VDD power supply tuning - 0 = Disable external VDD power supply tuning is disabled - - - Notes: - This bit controls whether the PHY attempts to tune the external VDD power supply via the SMBus. This bit is only operational if the external supply is present. (See 1E.C472.6) */ - unsigned int enableVddPowerSupplyTuning : 1; /* 1E.C472.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable external VDD power supply tuning - 0 = Disable external VDD power supply tuning is disabled - */ - unsigned int reserved0 : 1; - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global Reserved Provisioning */ - union - { - struct - { - /*! \brief 1E.C473.7:0 R/WPD Training SNR [7:0] - AQ_GlobalReservedProvisioning_HHD.u3.bits_3.trainingSNR - - Provisionable Default = 0x00 - - SNR during 10G training on the worst channel. SNR is in steps of 0.1dB - - - Notes: - The SNR margin that is enjoyed by the worst channel, over and above the minimum SNR required to operate at a BER of 10-12. It is reported with 0.1 dB of resolution to an accuracy of 0.5 dB within the range of -12.7 dB to 12.7 dB. The number is in offset binary, with 0.0 dB represented by 0x8000. */ - unsigned int trainingSNR : 8; /* 1E.C473.7:0 R/WPD Provisionable Default = 0x00 */ - /* SNR during 10G training on the worst channel. SNR is in steps of 0.1dB - */ - /*! \brief 1E.C473.A:8 R/WPD Rate Transition Request [2:0] - AQ_GlobalReservedProvisioning_HHD.u3.bits_3.rateTransitionRequest - - Provisionable Default = 0x0 - - 0 = No Transition - 1 = Reserved - 2 = Reserved - 3 = Retrain at 10G - 4 = Retrain at 5G - 5 = Retrain at 2.5G - 6 = Retrain at 1G - 7 = Reserved - - */ - unsigned int rateTransitionRequest : 3; /* 1E.C473.A:8 R/WPD Provisionable Default = 0x0 */ - /* 0 = No Transition - 1 = Reserved - 2 = Reserved - 3 = Retrain at 10G - 4 = Retrain at 5G - 5 = Retrain at 2.5G - 6 = Retrain at 1G - 7 = Reserved - */ - unsigned int reserved0 : 5; - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of Global Reserved Provisioning */ - union - { - struct - { - /*! \brief 1E.C474.0 R/W NVR Daisy Chain Kickstart - AQ_GlobalReservedProvisioning_HHD.u4.bits_4.nvrDaisyChainKickstart - - Default = 0x0 - - 1 = Kickstart the Daisy Chain - - - Notes: - When in daisy chain master mode, the PHY0 can kickstart the daisy chain. The kickstart will not reload the IRAM/DRAM or reset the uP for PHY0. It will just read the FLASH and transfer the FLASH data to the daisy chain. */ - unsigned int nvrDaisyChainKickstart : 1; /* 1E.C474.0 R/W Default = 0x0 */ - /* 1 = Kickstart the Daisy Chain - */ - /*! \brief 1E.C474.F:1 R/WPD Reserved Provisioning 5 [F:1] - AQ_GlobalReservedProvisioning_HHD.u4.bits_4.reservedProvisioning_5 - - Provisionable Default = 0x0000 - - Reserved for future use - - */ - unsigned int reservedProvisioning_5 : 15; /* 1E.C474.F:1 R/WPD Provisionable Default = 0x0000 */ - /* Reserved for future use - */ - } bits_4; - uint16_t word_4; - } u4; - /*! \brief Union for bit and word level access of word 5 of Global Reserved Provisioning */ - union - { - struct - { - unsigned int reserved1 : 2; - /*! \brief 1E.C475.2 R/WPD Smart Power-Down Enable - AQ_GlobalReservedProvisioning_HHD.u5.bits_5.smartPower_downEnable - - Provisionable Default = 0x0 - - 1 = Enable smart power down mode - 0 = Smart power-down mode disabled - - - Notes: - Smart power down (SPD) is the lowest power mode at which PHY is able to autonegotiate. SPD can be enabled with bit 1E.C475.2 */ - unsigned int smartPower_downEnable : 1; /* 1E.C475.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable smart power down mode - 0 = Smart power-down mode disabled - */ - /*! \brief 1E.C475.3 R/WPD Deadlock Avoidance Enable - AQ_GlobalReservedProvisioning_HHD.u5.bits_5.deadlockAvoidanceEnable - - Provisionable Default = 0x0 - - 1 = SPD with deadlock avoidance: PHY transmits autonegotiation pulses (FLPs) at a slower rate (~ 1 FLP/ 100ms) than specified by autonegotiation standard (~1 FLP / 8.25ms). Receiver is active and able to detect the pulses. - 0 = SPD without deadlock avoidance: PHY transmitter is shut down, no autonegotiation pulses are sent on the line but the receiver is active and able to detect the pulses - - */ - unsigned int deadlockAvoidanceEnable : 1; /* 1E.C475.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = SPD with deadlock avoidance: PHY transmits autonegotiation pulses (FLPs) at a slower rate (~ 1 FLP/ 100ms) than specified by autonegotiation standard (~1 FLP / 8.25ms). Receiver is active and able to detect the pulses. - 0 = SPD without deadlock avoidance: PHY transmitter is shut down, no autonegotiation pulses are sent on the line but the receiver is active and able to detect the pulses - */ - /*! \brief 1E.C475.4 R/WPD CFR Support - AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrSupport - - Provisionable Default = 0x0 - - 1 = Local PHY supports Cisco Fast Retrain - 0 = Local PHY does support Cisco Fast Retrain - - */ - unsigned int cfrSupport : 1; /* 1E.C475.4 R/WPD Provisionable Default = 0x0 */ - /* 1 = Local PHY supports Cisco Fast Retrain - 0 = Local PHY does support Cisco Fast Retrain - */ - /*! \brief 1E.C475.5 R/WPD CFR THP - AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrTHP - - Provisionable Default = 0x0 - - 1 = Local PHY requires local PHY to enable THP - 0 = Local PHY does not require local PHY to enable THP - - */ - unsigned int cfrTHP : 1; /* 1E.C475.5 R/WPD Provisionable Default = 0x0 */ - /* 1 = Local PHY requires local PHY to enable THP - 0 = Local PHY does not require local PHY to enable THP - */ - /*! \brief 1E.C475.6 R/WPD CFR Extended Maxwait - AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrExtendedMaxwait - - Provisionable Default = 0x0 - - 1 = Local PHY requires extended maxwait - 0 = Local PHY does not require extended maxwait - - */ - unsigned int cfrExtendedMaxwait : 1; /* 1E.C475.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = Local PHY requires extended maxwait - 0 = Local PHY does not require extended maxwait - */ - /*! \brief 1E.C475.7 R/WPD CFR Disable Timer - AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrDisableTimer - - Provisionable Default = 0x0 - - 1 = Local PHY requires cfr_disable timer - 0 = Local PHY does not require cfr_disable timer - - */ - unsigned int cfrDisableTimer : 1; /* 1E.C475.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = Local PHY requires cfr_disable timer - 0 = Local PHY does not require cfr_disable timer - */ - /*! \brief 1E.C475.8 R/WPD CFR LP Support - AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrLpSupport - - Provisionable Default = 0x0 - - 1 = Link partner supports Cisco Fast Retrain - 0 = Link partner does support Cisco Fast Retrain - - */ - unsigned int cfrLpSupport : 1; /* 1E.C475.8 R/WPD Provisionable Default = 0x0 */ - /* 1 = Link partner supports Cisco Fast Retrain - 0 = Link partner does support Cisco Fast Retrain - */ - /*! \brief 1E.C475.9 R/WPD CFR LP THP - AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrLpTHP - - Provisionable Default = 0x0 - - 1 = Link partner requires local PHY to enable THP - 0 = Link partner does not require local PHY to enable THP - - */ - unsigned int cfrLpTHP : 1; /* 1E.C475.9 R/WPD Provisionable Default = 0x0 */ - /* 1 = Link partner requires local PHY to enable THP - 0 = Link partner does not require local PHY to enable THP - */ - /*! \brief 1E.C475.A R/WPD CFR LP Extended Maxwait - AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrLpExtendedMaxwait - - Provisionable Default = 0x0 - - 1 = Link partner requires extended maxwait - 0 = Link partner does not require extended maxwait - - */ - unsigned int cfrLpExtendedMaxwait : 1; /* 1E.C475.A R/WPD Provisionable Default = 0x0 */ - /* 1 = Link partner requires extended maxwait - 0 = Link partner does not require extended maxwait - */ - /*! \brief 1E.C475.B R/WPD CFR LP Disable Timer - AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrLpDisableTimer - - Provisionable Default = 0x0 - - 1 = Link partner requires cfr_disable timer - 0 = Link partner does not require cfr_disable timer - - */ - unsigned int cfrLpDisableTimer : 1; /* 1E.C475.B R/WPD Provisionable Default = 0x0 */ - /* 1 = Link partner requires cfr_disable timer - 0 = Link partner does not require cfr_disable timer - */ - /*! \brief 1E.C475.C R/WPD Reserved Provisioning 6 - AQ_GlobalReservedProvisioning_HHD.u5.bits_5.reservedProvisioning_6 - - Provisionable Default = 0x0 - - Internal reserved - do not modify - - */ - unsigned int reservedProvisioning_6 : 1; /* 1E.C475.C R/WPD Provisionable Default = 0x0 */ - /* Internal reserved - do not modify - */ - /*! \brief 1E.C475.D R/WPD Smart Power-Down Status - AQ_GlobalReservedProvisioning_HHD.u5.bits_5.smartPower_downStatus - - Provisionable Default = 0x0 - - 1 = Smart Power-Down Active - 0 = Smart Power-Down Inactive - - */ - unsigned int smartPower_downStatus : 1; /* 1E.C475.D R/WPD Provisionable Default = 0x0 */ - /* 1 = Smart Power-Down Active - 0 = Smart Power-Down Inactive - */ - unsigned int reserved0 : 2; - } bits_5; - uint16_t word_5; - } u5; - /*! \brief Dummy union to fill space in the structure Global Reserved Provisioning */ - union - { - struct - { - unsigned int reserved : 16; - } bits_6; - uint16_t word_6; - } u6; - /*! \brief Dummy union to fill space in the structure Global Reserved Provisioning */ - union - { - struct - { - unsigned int reserved : 16; - } bits_7; - uint16_t word_7; - } u7; - /*! \brief Union for bit and word level access of word 8 of Global Reserved Provisioning */ - union - { - struct - { - /*! \brief 1E.C478.A:0 R/WPD Reserved Provisioning 9 [A:0] - AQ_GlobalReservedProvisioning_HHD.u8.bits_8.reservedProvisioning_9 - - Provisionable Default = 0x000 - - Reserved for future use - - */ - unsigned int reservedProvisioning_9 : 11; /* 1E.C478.A:0 R/WPD Provisionable Default = 0x000 */ - /* Reserved for future use - */ - /*! \brief 1E.C478.E:B R/WPD DTE Drop Reporting Timer [3:0] - AQ_GlobalReservedProvisioning_HHD.u8.bits_8.dteDropReportingTimer - - Provisionable Default = 0x0 - - Number of seconds between loss of link partner filter and assertion of no-power-needed state, in 5 second increments (e.g. 0x4 = 20 seconds). - - - Notes: - These bits are used to set how long the PHY waits after it no longer detects the link partner filter before declaring that power is not needed. */ - unsigned int dteDropReportingTimer : 4; /* 1E.C478.E:B R/WPD Provisionable Default = 0x0 */ - /* Number of seconds between loss of link partner filter and assertion of no-power-needed state, in 5 second increments (e.g. 0x4 = 20 seconds). - */ - /*! \brief 1E.C478.F R/WPD DTE Enable - AQ_GlobalReservedProvisioning_HHD.u8.bits_8.dteEnable - - Provisionable Default = 0x0 - - 1 = Enable DTE - 0 = Disable DTE - - */ - unsigned int dteEnable : 1; /* 1E.C478.F R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable DTE - 0 = Disable DTE - */ - } bits_8; - uint16_t word_8; - } u8; - /*! \brief Union for bit and word level access of word 9 of Global Reserved Provisioning */ - union - { - struct - { - /*! \brief 1E.C479.E:0 R/WPD Reserved Provisioning 10 [E:0] - AQ_GlobalReservedProvisioning_HHD.u9.bits_9.reservedProvisioning_10 - - Provisionable Default = 0x0000 - - Reserved for future use - - */ - unsigned int reservedProvisioning_10 : 15; /* 1E.C479.E:0 R/WPD Provisionable Default = 0x0000 */ - /* Reserved for future use - */ - /*! \brief 1E.C479.F R/WPD Power Up Stall - AQ_GlobalReservedProvisioning_HHD.u9.bits_9.powerUpStall - - Provisionable Default = 0x0 - - 1 = Stall FW at Power Up - 0 = Unstall the FW - - - Notes: - This bit needs to be provisioned in Power Up Init for firmware to stall. */ - unsigned int powerUpStall : 1; /* 1E.C479.F R/WPD Provisionable Default = 0x0 */ - /* 1 = Stall FW at Power Up - 0 = Unstall the FW - */ - } bits_9; - uint16_t word_9; - } u9; - /*! \brief Union for bit and word level access of word 10 of Global Reserved Provisioning */ - union - { - struct - { - /*! \brief 1E.C47A.1:0 R/WPD Rate [1:0] - AQ_GlobalReservedProvisioning_HHD.u10.bits_10.rate - - Provisionable Default = 0x0 - - 0x3 = 10G - 0x2 = 1G - 0x1 = 100M - 0x0 = reserved - - - Notes: - These bits select the rate for the loopback and packet generation. SERDES configuration, as well autonegotiation is controlled accordingly when a loopback is selected. For instance, if 100M system loopback on the network interface is selected, SGMII on the system interface is enabled to connect at 100M, and if passthrough is enabled 100BASE-TX will be the only advertised rate and will force a re-autonegotiation if not already connected at 100M. - - NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F - - The controls in this register are identical to, and mirrored with, the controls in 4.C444. */ - unsigned int rate : 2; /* 1E.C47A.1:0 R/WPD Provisionable Default = 0x0 */ - /* 0x3 = 10G - 0x2 = 1G - 0x1 = 100M - 0x0 = reserved - */ - /*! \brief 1E.C47A.2 R/WPD Reserved Provisioning 11a - AQ_GlobalReservedProvisioning_HHD.u10.bits_10.reservedProvisioning_11a - - Provisionable Default = 0x0 - - Reserved for future use - - */ - unsigned int reservedProvisioning_11a : 1; /* 1E.C47A.2 R/WPD Provisionable Default = 0x0 */ - /* Reserved for future use - */ - /*! \brief 1E.C47A.3 R/WPD System I/F Packet Generation - AQ_GlobalReservedProvisioning_HHD.u10.bits_10.systemI_fPacketGeneration - - Provisionable Default = 0x0 - - 1 = CRPAT packet generation out 10G system interface - 0 = No CRPAT packet generation out 10G system interface - - - Notes: - Selecting this mode of operation causes the CRPAT packet generator in the PHY to output CRPAT packets on the selected 10G system interface (4.C441.F:E) - - NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F - - The controls in this register are identical to, and mirrored with, the controls in 4.C444. */ - unsigned int systemI_fPacketGeneration : 1; /* 1E.C47A.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = CRPAT packet generation out 10G system interface - 0 = No CRPAT packet generation out 10G system interface - */ - /*! \brief 1E.C47A.4 R/WPD Look-Aside Port Packet Generation - AQ_GlobalReservedProvisioning_HHD.u10.bits_10.look_asidePortPacketGeneration - - Provisionable Default = 0x0 - - 1 = CRPAT packet generation out 10G look-aside interface (KR0) - 0 = No CRPAT packet generation out 10G look-aside interface (KR0) - - - Notes: - Selecting this mode of operation causes the CRPAT packet generator in the PHY to output on KR0. - - NOTE!! This only functions if KR1 (SERDES2) is selected as the system interface in (4.C441.F:E). - - NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F - - The controls in this register are identical to, and mirrored with, the controls in 4.C444. */ - unsigned int look_asidePortPacketGeneration : 1; /* 1E.C47A.4 R/WPD Provisionable Default = 0x0 */ - /* 1 = CRPAT packet generation out 10G look-aside interface (KR0) - 0 = No CRPAT packet generation out 10G look-aside interface (KR0) - */ - /*! \brief 1E.C47A.5 R/WPD MDI Packet Generation - AQ_GlobalReservedProvisioning_HHD.u10.bits_10.mdiPacketGeneration - - Provisionable Default = 0x0 - - 1 = CRPAT packet generation out MDI interface - 0 = No CRPAT packet generation out MDI interface - - - Notes: - Selecting this mode of operation causes the CRPAT packet generator in the PHY to output on the MDI interface at the selected rate. - - NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F - - The controls in this register are identical to, and mirrored with, the controls in 4.C444. */ - unsigned int mdiPacketGeneration : 1; /* 1E.C47A.5 R/WPD Provisionable Default = 0x0 */ - /* 1 = CRPAT packet generation out MDI interface - 0 = No CRPAT packet generation out MDI interface - */ - /*! \brief 1E.C47A.A:6 R/WPD Reserved Provisioning 11 [4:0] - AQ_GlobalReservedProvisioning_HHD.u10.bits_10.reservedProvisioning_11 - - Provisionable Default = 0x00 - - Reserved for future use - - */ - unsigned int reservedProvisioning_11 : 5; /* 1E.C47A.A:6 R/WPD Provisionable Default = 0x00 */ - /* Reserved for future use - */ - /*! \brief 1E.C47A.F:B R/WPD Loopback Control [4:0] - AQ_GlobalReservedProvisioning_HHD.u10.bits_10.loopbackControl - - Provisionable Default = 0x00 - - 0x00 = No loopback - 0x01 = System Interface - System Loopback - 0x02 = System Interface - System Loopback with Passthrough - 0x03 = System Interface - Network Loopback - 0x04 = System Interface - Network Loopback with Passthrough - 0x05 = System Interface - Network Loopback with Passthrough and Merge - 0x06 = System Interface - Peer-to-peer loopback - 0x07 - 0x08 = Reserved - 0x09 = Network Interface - System Loopback - 0x0A = Network Interface - System Loopback with Passthrough - 0x0B = Network Interface - Network Loopback - 0x0C = Network Interface - Network Loopback with Passthrough - 0x0D = Network Interface - Peer-to-peer loopback - 0x0E - 0x0F = Reserved - 0x10 = Cross-connect System Loopback - 0x11 = Cross-connect Network Loopback - 0x12 - 0x13 = Reserved - 0x14 = Network Interface - System Loopback via Loopback Plug - 0x15 - 0x1F = Reserved - - - Notes: - These bits, in conjunction with the chip configuration and the rate (Bits 1:0), select the loopback to configure for the chip. Setting one of these loopbacks provisions the chip for the specified loopback. Upon clearing the loopback, the chip returns to it's configuration prior to entering loopback (irregardless of whether other loopbacks were selected after the initial loopback). - - NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F. - - The controls in this register are identical to, and mirrored with, the controls in 4.C444. - */ - unsigned int loopbackControl : 5; /* 1E.C47A.F:B R/WPD Provisionable Default = 0x00 */ - /* 0x00 = No loopback - 0x01 = System Interface - System Loopback - 0x02 = System Interface - System Loopback with Passthrough - 0x03 = System Interface - Network Loopback - 0x04 = System Interface - Network Loopback with Passthrough - 0x05 = System Interface - Network Loopback with Passthrough and Merge - 0x06 = System Interface - Peer-to-peer loopback - 0x07 - 0x08 = Reserved - 0x09 = Network Interface - System Loopback - 0x0A = Network Interface - System Loopback with Passthrough - 0x0B = Network Interface - Network Loopback - 0x0C = Network Interface - Network Loopback with Passthrough - 0x0D = Network Interface - Peer-to-peer loopback - 0x0E - 0x0F = Reserved - 0x10 = Cross-connect System Loopback - 0x11 = Cross-connect Network Loopback - 0x12 - 0x13 = Reserved - 0x14 = Network Interface - System Loopback via Loopback Plug - 0x15 - 0x1F = Reserved - */ - } bits_10; - uint16_t word_10; - } u10; - /*! \brief Union for bit and word level access of word 11 of Global Reserved Provisioning */ - union - { - struct - { - /*! \brief 1E.C47B.0 R/WPD Enable PTP - AQ_GlobalReservedProvisioning_HHD.u11.bits_11.enablePtp - - Provisionable Default = 0x0 - - 1 = PTP functionality is enabled - 0 = PTP functionality is disabled - - - Notes: - If this bit is 1, the PTP/SEC block will be included in the data path, regardless of operating mode. */ - unsigned int enablePtp : 1; /* 1E.C47B.0 R/WPD Provisionable Default = 0x0 */ - /* 1 = PTP functionality is enabled - 0 = PTP functionality is disabled - */ - /*! \brief 1E.C47B.1 R/WPD Enable MACSec - AQ_GlobalReservedProvisioning_HHD.u11.bits_11.enableMacsec - - Provisionable Default = 0x0 - - 1 = MACSec functionality is enabled - 0 = MACSec functionality is disabled - - - Notes: - If this bit is 1, the PTP/SEC block will be included in the data path, regardless of operating mode. */ - unsigned int enableMacsec : 1; /* 1E.C47B.1 R/WPD Provisionable Default = 0x0 */ - /* 1 = MACSec functionality is enabled - 0 = MACSec functionality is disabled - */ - /*! \brief 1E.C47B.F:2 R/WPD Reserved Provisioning 12 [D:0] - AQ_GlobalReservedProvisioning_HHD.u11.bits_11.reservedProvisioning_12 - - Provisionable Default = 0x0000 - - Reserved for future use - - */ - unsigned int reservedProvisioning_12 : 14; /* 1E.C47B.F:2 R/WPD Provisionable Default = 0x0000 */ - /* Reserved for future use - */ - } bits_11; - uint16_t word_11; - } u11; -} AQ_GlobalReservedProvisioning_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief PIF Mailbox Control: 1E.C47C */ -/* PIF Mailbox Control: 1E.C47C */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of PIF Mailbox Control */ - union - { - struct - { - /*! \brief 1E.C47C.F:0 R/WPDuP PIF Mailbox Address [F:0] - AQ_PifMailboxControl_HHD.u0.bits_0.pifMailboxAddress - - Provisionable Default = 0x0000 - - The least 16 bits of the PIF address to read or write. - - */ - unsigned int pifMailboxAddress : 16; /* 1E.C47C.F:0 R/WPDuP Provisionable Default = 0x0000 */ - /* The least 16 bits of the PIF address to read or write. - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of PIF Mailbox Control */ - union - { - struct - { - /*! \brief 1E.C47D.F:0 R/WPDuP PIF Mailbox Data [F:0] - AQ_PifMailboxControl_HHD.u1.bits_1.pifMailboxData - - Provisionable Default = 0x0000 - - The data to be written, or that had been read. - - */ - unsigned int pifMailboxData : 16; /* 1E.C47D.F:0 R/WPDuP Provisionable Default = 0x0000 */ - /* The data to be written, or that had been read. - */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of PIF Mailbox Control */ - union - { - struct - { - /*! \brief 1E.C47E.7:0 R/WPDuP PIF Mailbox MMD [7:0] - AQ_PifMailboxControl_HHD.u2.bits_2.pifMailboxMMD - - Provisionable Default = 0x00 - - MMD (upper 8 bits) of the PID address to read or write. - - */ - unsigned int pifMailboxMMD : 8; /* 1E.C47E.7:0 R/WPDuP Provisionable Default = 0x00 */ - /* MMD (upper 8 bits) of the PID address to read or write. - */ - /*! \brief 1E.C47E.B:8 R/WPDuP PIF Mailbox Command Type [3:0] - AQ_PifMailboxControl_HHD.u2.bits_2.pifMailboxCommandType - - Provisionable Default = 0x0 - - 0 = No Action - 1 = Read - 2 = Write - - - Notes: - System SW writes non-zero value to start a PIF command. */ - unsigned int pifMailboxCommandType : 4; /* 1E.C47E.B:8 R/WPDuP Provisionable Default = 0x0 */ - /* 0 = No Action - 1 = Read - 2 = Write - */ - /*! \brief 1E.C47E.F:C R/WPD Reserved PIF Mailbox Control 3 [3:0] - AQ_PifMailboxControl_HHD.u2.bits_2.reservedPifMailboxControl_3 - - Provisionable Default = 0x0 - - Reserved for future use - - */ - unsigned int reservedPifMailboxControl_3 : 4; /* 1E.C47E.F:C R/WPD Provisionable Default = 0x0 */ - /* Reserved for future use - */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of PIF Mailbox Control */ - union - { - struct - { - /*! \brief 1E.C47F.3:0 R/WPDuP PIF Mailbox Command Status [3:0] - AQ_PifMailboxControl_HHD.u3.bits_3.pifMailboxCommandStatus - - Provisionable Default = 0x0 - - 0 = Idle - 1 = Command completed - 2 = Command did not complete - - - Notes: - System SW should write 0 before writing Command Type to clear completion status */ - unsigned int pifMailboxCommandStatus : 4; /* 1E.C47F.3:0 R/WPDuP Provisionable Default = 0x0 */ - /* 0 = Idle - 1 = Command completed - 2 = Command did not complete - */ - /*! \brief 1E.C47F.F:4 R/WPD Reserved PIF Mailbox Control 4 [B:0] - AQ_PifMailboxControl_HHD.u3.bits_3.reservedPifMailboxControl_4 - - Provisionable Default = 0x000 - - Reserved for future use - - */ - unsigned int reservedPifMailboxControl_4 : 12; /* 1E.C47F.F:4 R/WPD Provisionable Default = 0x000 */ - /* Reserved for future use - */ - } bits_3; - uint16_t word_3; - } u3; -} AQ_PifMailboxControl_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global SMBus 0 Provisioning: 1E.C485 */ -/* Global SMBus 0 Provisioning: 1E.C485 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global SMBus 0 Provisioning */ - union - { - struct - { - unsigned int reserved1 : 1; - /*! \brief 1E.C485.7:1 R/W SMB 0 Slave Address [7:1] - AQ_GlobalSmbus_0Provisioning_HHD.u0.bits_0.smb_0SlaveAddress - - Default = 0x00 - - SMB slave address configuration - - */ - unsigned int smb_0SlaveAddress : 7; /* 1E.C485.7:1 R/W Default = 0x00 */ - /* SMB slave address configuration - */ - unsigned int reserved0 : 8; - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalSmbus_0Provisioning_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global SMBus 1 Provisioning: 1E.C495 */ -/* Global SMBus 1 Provisioning: 1E.C495 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global SMBus 1 Provisioning */ - union - { - struct - { - unsigned int reserved1 : 1; - /*! \brief 1E.C495.7:1 R/W SMB 1 Slave Address [7:1] - AQ_GlobalSmbus_1Provisioning_HHD.u0.bits_0.smb_1SlaveAddress - - Default = 0x00 - - SMB slave address configuration - - */ - unsigned int smb_1SlaveAddress : 7; /* 1E.C495.7:1 R/W Default = 0x00 */ - /* SMB slave address configuration - */ - unsigned int reserved0 : 8; - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalSmbus_1Provisioning_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global EEE Provisioning: 1E.C4A0 */ -/* Global EEE Provisioning: 1E.C4A0 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global EEE Provisioning */ - union - { - struct - { - /*! \brief 1E.C4A0.0 R/WPD EEE Mode - AQ_GlobalEeeProvisioning_HHD.u0.bits_0.eeeMode - - Provisionable Default = 0x0 - - 1 = EEE mode of operation - - - Notes: - EEE mode of operation (0=disable, 1=enable, default:0) */ - unsigned int eeeMode : 1; /* 1E.C4A0.0 R/WPD Provisionable Default = 0x0 */ - /* 1 = EEE mode of operation - */ - unsigned int reserved0 : 15; - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalEeeProvisioning_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Cable Diagnostic Status: 1E.C800 */ -/* Global Cable Diagnostic Status: 1E.C800 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C800.2:0 RO Pair D Status [2:0] - AQ_GlobalCableDiagnosticStatus_HHD.u0.bits_0.pairDStatus - - - - [6:4] - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair C - 010= Connected to Pair B - 001= Connected to Pair A - 000= OK - - Notes: - This register summarizes the worst impairment on Pair D. */ - unsigned int pairDStatus : 3; /* 1E.C800.2:0 RO */ - /* [6:4] - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair C - 010= Connected to Pair B - 001= Connected to Pair A - 000= OK */ - unsigned int reserved3 : 1; - /*! \brief 1E.C800.6:4 RO Pair C Status [2:0] - AQ_GlobalCableDiagnosticStatus_HHD.u0.bits_0.pairCStatus - - - - [9:7] - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair B - 010= Connected to Pair A - 001= Connected to Pair D - 000= OK - - Notes: - This register summarizes the worst impairment on Pair C. */ - unsigned int pairCStatus : 3; /* 1E.C800.6:4 RO */ - /* [9:7] - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair B - 010= Connected to Pair A - 001= Connected to Pair D - 000= OK */ - unsigned int reserved2 : 1; - /*! \brief 1E.C800.A:8 RO Pair B Status [2:0] - AQ_GlobalCableDiagnosticStatus_HHD.u0.bits_0.pairBStatus - - - - [C:A] - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair A - 010= Connected to Pair D - 001= Connected to Pair C - 000= OK - - Notes: - This register summarizes the worst impairment on Pair B. */ - unsigned int pairBStatus : 3; /* 1E.C800.A:8 RO */ - /* [C:A] - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair A - 010= Connected to Pair D - 001= Connected to Pair C - 000= OK */ - unsigned int reserved1 : 1; - /*! \brief 1E.C800.E:C RO Pair A Status [2:0] - AQ_GlobalCableDiagnosticStatus_HHD.u0.bits_0.pairAStatus - - - - [F:D] - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair D - 010= Connected to Pair C - 001= Connected to Pair B - 000= OK - - Notes: - This register summarizes the worst impairment on Pair A. */ - unsigned int pairAStatus : 3; /* 1E.C800.E:C RO */ - /* [F:D] - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair D - 010= Connected to Pair C - 001= Connected to Pair B - 000= OK */ - unsigned int reserved0 : 1; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C801.7:0 RO Pair A Reflection #2 [7:0] - AQ_GlobalCableDiagnosticStatus_HHD.u1.bits_1.pairAReflection_2 - - - - The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair A - - Notes: - The distance to this reflection is given in See Global Reserved Status 1: Address 1E.C870 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairAReflection_2 : 8; /* 1E.C801.7:0 RO */ - /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair A */ - /*! \brief 1E.C801.F:8 RO Pair A Reflection #1 [7:0] - AQ_GlobalCableDiagnosticStatus_HHD.u1.bits_1.pairAReflection_1 - - - - The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair A - - Notes: - The distance to this reflection is given in See Global Reserved Status 1: Address 1E.C870 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairAReflection_1 : 8; /* 1E.C801.F:8 RO */ - /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair A */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C802.F:0 RO Impulse Response MSW [F:0] - AQ_GlobalCableDiagnosticStatus_HHD.u2.bits_2.impulseResponseMSW - - - - The MSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type in 1E.C470.E:D - - Notes: - See 1E.C470 for more information */ - unsigned int impulseResponseMSW : 16; /* 1E.C802.F:0 RO */ - /* The MSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type in 1E.C470.E:D */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C803.7:0 RO Pair B Reflection #2 [7:0] - AQ_GlobalCableDiagnosticStatus_HHD.u3.bits_3.pairBReflection_2 - - - - The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair B - - Notes: - The distance to this reflection is given in See Global Reserved Status 2: Address 1E.C871 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairBReflection_2 : 8; /* 1E.C803.7:0 RO */ - /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair B */ - /*! \brief 1E.C803.F:8 RO Pair B Reflection #1 [7:0] - AQ_GlobalCableDiagnosticStatus_HHD.u3.bits_3.pairBReflection_1 - - - - The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair B - - Notes: - The distance to this reflection is given in See Global Reserved Status 2: Address 1E.C871 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairBReflection_1 : 8; /* 1E.C803.F:8 RO */ - /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair B */ - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C804.F:0 RO Impulse Response LSW [F:0] - AQ_GlobalCableDiagnosticStatus_HHD.u4.bits_4.impulseResponseLSW - - - - The LSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type specified in 1E.C470.E:D - - Notes: - See 1E.C470 for more information */ - unsigned int impulseResponseLSW : 16; /* 1E.C804.F:0 RO */ - /* The LSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type specified in 1E.C470.E:D */ - } bits_4; - uint16_t word_4; - } u4; - /*! \brief Union for bit and word level access of word 5 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C805.7:0 RO Pair C Reflection #2 [7:0] - AQ_GlobalCableDiagnosticStatus_HHD.u5.bits_5.pairCReflection_2 - - - - The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair C - - Notes: - The distance to this reflection is given in See Global Reserved Status 3: Address 1E.C872 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairCReflection_2 : 8; /* 1E.C805.7:0 RO */ - /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair C */ - /*! \brief 1E.C805.F:8 RO Pair C Reflection #1 [7:0] - AQ_GlobalCableDiagnosticStatus_HHD.u5.bits_5.pairCReflection_1 - - - - The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair C - - Notes: - The distance to this reflection is given in See Global Reserved Status 3: Address 1E.C872 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairCReflection_1 : 8; /* 1E.C805.F:8 RO */ - /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair C */ - } bits_5; - uint16_t word_5; - } u5; - /*! \brief Union for bit and word level access of word 6 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C806.F:0 RO Reserved 1 [F:0] - AQ_GlobalCableDiagnosticStatus_HHD.u6.bits_6.reserved_1 - - - - Reserved for future use - */ - unsigned int reserved_1 : 16; /* 1E.C806.F:0 RO */ - /* Reserved for future use */ - } bits_6; - uint16_t word_6; - } u6; - /*! \brief Union for bit and word level access of word 7 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C807.7:0 RO Pair D Reflection #2 [7:0] - AQ_GlobalCableDiagnosticStatus_HHD.u7.bits_7.pairDReflection_2 - - - - The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair D - - Notes: - The distance to this reflection is given in See Global Reserved Status 4: Address 1E.C873 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairDReflection_2 : 8; /* 1E.C807.7:0 RO */ - /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair D */ - /*! \brief 1E.C807.F:8 RO Pair D Reflection #1 [7:0] - AQ_GlobalCableDiagnosticStatus_HHD.u7.bits_7.pairDReflection_1 - - - - The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair D - - Notes: - The distance to this reflection is given in See Global Reserved Status 4: Address 1E.C873 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairDReflection_1 : 8; /* 1E.C807.F:8 RO */ - /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair D */ - } bits_7; - uint16_t word_7; - } u7; -} AQ_GlobalCableDiagnosticStatus_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Thermal Status: 1E.C820 */ -/* Global Thermal Status: 1E.C820 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Thermal Status */ - union - { - struct - { - /*! \brief 1E.C820.F:0 RO Temperature [F:0] - AQ_GlobalThermalStatus_HHD.u0.bits_0.temperature - - - - [F:0] of temperature - - - Notes: - 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 70 degreesC. This is a mirror of the XENPAK register 1.A060 - 1.A061. The mirror is performed in H/W. */ - unsigned int temperature : 16; /* 1E.C820.F:0 RO */ - /* [F:0] of temperature - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Thermal Status */ - union - { - struct - { - /*! \brief 1E.C821.0 RO Temperature Ready - AQ_GlobalThermalStatus_HHD.u1.bits_1.temperatureReady - - - - 1 = Temperature measurement is valid - - - Notes: - This is a mirror of the XENPAK register 1.A06E. */ - unsigned int temperatureReady : 1; /* 1E.C821.0 RO */ - /* 1 = Temperature measurement is valid - */ - unsigned int reserved0 : 15; - } bits_1; - uint16_t word_1; - } u1; -} AQ_GlobalThermalStatus_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global General Status: 1E.C830 */ -/* Global General Status: 1E.C830 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global General Status */ - union - { - struct - { - unsigned int reserved1 : 11; - /*! \brief 1E.C830.B RO Low Temperature Warning State - AQ_GlobalGeneralStatus_HHD.u0.bits_0.lowTemperatureWarningState - - - - 1 = Low temperature warning threshold has been exceeded - - Notes: - In XENPAK mode, F/W will copy this register to the 1.A074.6 register. - - */ - unsigned int lowTemperatureWarningState : 1; /* 1E.C830.B RO */ - /* 1 = Low temperature warning threshold has been exceeded */ - /*! \brief 1E.C830.C RO High Temperature Warning State - AQ_GlobalGeneralStatus_HHD.u0.bits_0.highTemperatureWarningState - - - - 1 = High temperature warning threshold has been exceeded - - Notes: - In XENPAK mode, F/W will copy this register to the 1.A074.7 register. - - */ - unsigned int highTemperatureWarningState : 1; /* 1E.C830.C RO */ - /* 1 = High temperature warning threshold has been exceeded */ - /*! \brief 1E.C830.D RO Low Temperature Failure State - AQ_GlobalGeneralStatus_HHD.u0.bits_0.lowTemperatureFailureState - - - - 1 = Low temperature failure threshold has been exceeded - - Notes: - In XENPAK mode, F/W will copy this register to the 1.A070.6 register. - - */ - unsigned int lowTemperatureFailureState : 1; /* 1E.C830.D RO */ - /* 1 = Low temperature failure threshold has been exceeded */ - /*! \brief 1E.C830.E RO High Temperature Failure State - AQ_GlobalGeneralStatus_HHD.u0.bits_0.highTemperatureFailureState - - - - 1 = High temperature failure threshold has been exceeded - - Notes: - In XENPAK mode, F/W will copy this register to the 1.A070.7 register. - - */ - unsigned int highTemperatureFailureState : 1; /* 1E.C830.E RO */ - /* 1 = High temperature failure threshold has been exceeded */ - unsigned int reserved0 : 1; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global General Status */ - union - { - struct - { - unsigned int reserved0 : 15; - /*! \brief 1E.C831.F RO Processor Intensive MDIO Operation In- Progress - AQ_GlobalGeneralStatus_HHD.u1.bits_1.processorIntensiveMdioOperationIn_Progress - - - - 1 = PHY microprocessor is busy with a processor-intensive MDIO operation - 0 = Processor-intensive MDIO operation completed - - - Notes: - This bit should may be used with certain processor-intensive MDIO commands (such as Loopbacks, Test Modes, Low power modes, Tx-Disable, Restart autonegotiation, Cable Diagnostics, etc.) that take longer than an MDIO cycle to complete. Upon receiving an MDIO command that involves the PHY's microprocessor, this bit is set, and when the command is completed, this bit is cleared. - - NOTE!!! This bit should be checked only after 1 ms of issuing a processor-intensive MDIO operation. - - The list of operations that set this bit are as follows: - - 1.0.0, PMA Loopback - 1.0.B, Low power mode - 1.9.4:0, Tx Disable - 1.84, 10G Test modes - 1.8000.5, XENPAK Control - 1.9000, XENPAK Rx Fault Enable - 1.9002, XENPAK Alarm Enable - 1.E400.F, External loopback - 3.0.B, Low power mode - 3.0.E, System PCS loopback - 3.C471.5, PRBS Test - 3.C471.6, PRBS Test - 3.E471.5, PRBS Test - 3.E471.6, PRBS Test - 4.0.B, Low power mode - 4.0.E, PHY-XS network loopback - 4.C440, Output clock control, Load SERDES parameters - 4.F802.E, System loopback - 4.C444.F:B, Loopback Control - 4.C444.4:2, Packet generation - 4.C445.C, SERDES calibration - 7.0.9, Restart autonegotiation - 1D.C280, 1G/100M Network loopback - 1D.C500, 1G System loopback - 1D.C501, 1G / 100M Test modes - 1E.C470.4, Cable diagnostics - 1E.C47A.F:B, Loopback Control - 1E.C47A.4:2, Packet generation */ - unsigned int processorIntensiveMdioOperationIn_Progress : 1; /* 1E.C831.F RO */ - /* 1 = PHY microprocessor is busy with a processor-intensive MDIO operation - 0 = Processor-intensive MDIO operation completed - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_GlobalGeneralStatus_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Pin Status: 1E.C840 */ -/* Global Pin Status: 1E.C840 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Pin Status */ - union - { - struct - { - /*! \brief 1E.C840.5:0 RO LED Pullup State [5:0] - AQ_GlobalPinStatus_HHD.u0.bits_0.ledPullupState - - - - 1 = LED output pin is pulled high - 0 = LED output pin is pulled low - - */ - unsigned int ledPullupState : 6; /* 1E.C840.5:0 RO */ - /* 1 = LED output pin is pulled high - 0 = LED output pin is pulled low - */ - unsigned int reserved4 : 1; - /*! \brief 1E.C840.7 RO Tx Enable - AQ_GlobalPinStatus_HHD.u0.bits_0.txEnable - - - - Current Value of Tx Enable pin - - - Notes: - 0 = Disable Transmitter */ - unsigned int txEnable : 1; /* 1E.C840.7 RO */ - /* Current Value of Tx Enable pin - */ - unsigned int reserved3 : 1; - /*! \brief 1E.C840.9 RO Package Connectivity - AQ_GlobalPinStatus_HHD.u0.bits_0.packageConnectivity - - - - Value of the package connection pin - - */ - unsigned int packageConnectivity : 1; /* 1E.C840.9 RO */ - /* Value of the package connection pin - */ - unsigned int reserved2 : 3; - /*! \brief 1E.C840.D RO DC_MASTER_N - AQ_GlobalPinStatus_HHD.u0.bits_0.dcMasterN - - - - Value of DC_MASTER_N pin: - - 0x1 = PHY Slave Daisy Chain Boot - 0x0 = PHY Master Daisy Chain Boot from FLASH - */ - unsigned int dcMasterN : 1; /* 1E.C840.D RO */ - /* Value of DC_MASTER_N pin: - - 0x1 = PHY Slave Daisy Chain Boot - 0x0 = PHY Master Daisy Chain Boot from FLASH */ - unsigned int reserved1 : 1; - unsigned int reserved0 : 1; - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalPinStatus_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Daisy Chain Status: 1E.C842 */ -/* Global Daisy Chain Status: 1E.C842 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Daisy Chain Status */ - union - { - struct - { - /*! \brief 1E.C842.F:0 RO Rx Daisy Chain Calculated CRC [F:0] - AQ_GlobalDaisyChainStatus_HHD.u0.bits_0.rxDaisyChainCalculatedCrc - - - - Rx Daisy Chain Calculated CRC - - - Notes: - This is the calculated daisy chain CRC. */ - unsigned int rxDaisyChainCalculatedCrc : 16; /* 1E.C842.F:0 RO */ - /* Rx Daisy Chain Calculated CRC - */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalDaisyChainStatus_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Fault Message: 1E.C850 */ -/* Global Fault Message: 1E.C850 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Fault Message */ - union - { - struct - { - /*! \brief 1E.C850.F:0 RO Message [F:0] - AQ_GlobalFaultMessage_HHD.u0.bits_0.message - - - - Error code describing fault - - Notes: - Code 0x8001: Firmware not compatible with chip architecture. This fault occurs when firmware compiled for a different microprocessor core is loaded. - Code 0x8002: VCO calibration failed. This occurs when the main PLLs on chip fail to lock: this is not possible to trigger. - Code 0x8003: XAUI calibration failed. This occurs when the XAUI PLLs fail to lock: this is not possible to trigger. - Code 0x8005: Unexpected device ID. This occurs if the device ID programmed into the internal E-Fuse registers in not valid: this is not possible to trigger. - Code 0x8006: Computed checksum does not match expected checksum. This occurs when the FLASH checksum check performed at boot time fails. This only occurs when the system boots from FLASH. - Code 0x8007: Detected a bit error in static memory. To trigger, corrupt one of the static regions. - Code 0xC001: Illegal Instruction exception. This occurs when the processor attempts to execute an illegal instruction. To trigger this, write an illegal instruction to program memory. It's possible that the bit error check will trigger before the illegal instruction is executed. - Code 0xC002 Instruction Fetch Error. Internal physical address or a data error during instruction fetch: this is not possible to trigger. - Code 0xC003 Load Store Error. Internal physical address or data error during load store operation: this is not possible to trigger.. - Code 0xC004 Privileged Instruction. Attempt to execute a privileged operation without sufficient privilege: this is not possible to trigger. - Code 0xC005 Unaligned Load or Store. Attempt to load or store data at an address which cannot be handled due to alignment: this is not possible to trigger. - Code 0xC006 Instruction fetch from prohibited space: this is not possible to trigger. - Code 0xC007 Data load from prohibited space: this is not possible to trigger. - Code 0xC008 Data store into prohibited space: this is not possible to trigger. */ - unsigned int message : 16; /* 1E.C850.F:0 RO */ - /* Error code describing fault */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalFaultMessage_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Cable Diagnostic Impedance: 1E.C880 */ -/* Global Cable Diagnostic Impedance: 1E.C880 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Cable Diagnostic Impedance */ - union - { - struct - { - /*! \brief 1E.C880.2:0 RO Pair A Reflection #4 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.pairAReflection_4 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the fourth worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ - unsigned int pairAReflection_4 : 3; /* 1E.C880.2:0 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C880.3 RO Reserved 4 - AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.reserved_4 - - - - Reserved - - */ - unsigned int reserved_4 : 1; /* 1E.C880.3 RO */ - /* Reserved - */ - /*! \brief 1E.C880.6:4 RO Pair A Reflection #3 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.pairAReflection_3 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the third worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ - unsigned int pairAReflection_3 : 3; /* 1E.C880.6:4 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C880.7 RO Reserved 3 - AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.reserved_3 - - - - Reserved - - */ - unsigned int reserved_3 : 1; /* 1E.C880.7 RO */ - /* Reserved - */ - /*! \brief 1E.C880.A:8 RO Pair A Reflection #2 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.pairAReflection_2 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the second worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ - unsigned int pairAReflection_2 : 3; /* 1E.C880.A:8 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C880.B RO Reserved 2 - AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.reserved_2 - - - - Reserved - - */ - unsigned int reserved_2 : 1; /* 1E.C880.B RO */ - /* Reserved - */ - /*! \brief 1E.C880.E:C RO Pair A Reflection #1 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.pairAReflection_1 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the first worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ - unsigned int pairAReflection_1 : 3; /* 1E.C880.E:C RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C880.F RO Reserved 1 - AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.reserved_1 - - - - Reserved - - */ - unsigned int reserved_1 : 1; /* 1E.C880.F RO */ - /* Reserved - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Cable Diagnostic Impedance */ - union - { - struct - { - /*! \brief 1E.C881.2:0 RO Pair B Reflection #4 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.pairBReflection_4 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the fourth worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ - unsigned int pairBReflection_4 : 3; /* 1E.C881.2:0 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C881.3 RO Reserved 8 - AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.reserved_8 - - - - Reserved - - */ - unsigned int reserved_8 : 1; /* 1E.C881.3 RO */ - /* Reserved - */ - /*! \brief 1E.C881.6:4 RO Pair B Reflection #3 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.pairBReflection_3 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the third worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ - unsigned int pairBReflection_3 : 3; /* 1E.C881.6:4 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C881.7 RO Reserved 7 - AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.reserved_7 - - - - Reserved - - */ - unsigned int reserved_7 : 1; /* 1E.C881.7 RO */ - /* Reserved - */ - /*! \brief 1E.C881.A:8 RO Pair B Reflection #2 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.pairBReflection_2 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the second worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ - unsigned int pairBReflection_2 : 3; /* 1E.C881.A:8 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C881.B RO Reserved 6 - AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.reserved_6 - - - - Reserved - - */ - unsigned int reserved_6 : 1; /* 1E.C881.B RO */ - /* Reserved - */ - /*! \brief 1E.C881.E:C RO Pair B Reflection #1 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.pairBReflection_1 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the first worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ - unsigned int pairBReflection_1 : 3; /* 1E.C881.E:C RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C881.F RO Reserved 5 - AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.reserved_5 - - - - Reserved - - */ - unsigned int reserved_5 : 1; /* 1E.C881.F RO */ - /* Reserved - */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global Cable Diagnostic Impedance */ - union - { - struct - { - /*! \brief 1E.C882.2:0 RO Pair C Reflection #4 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.pairCReflection_4 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the fourth worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ - unsigned int pairCReflection_4 : 3; /* 1E.C882.2:0 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C882.3 RO Reserved 12 - AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.reserved_12 - - - - Reserved - - */ - unsigned int reserved_12 : 1; /* 1E.C882.3 RO */ - /* Reserved - */ - /*! \brief 1E.C882.6:4 RO Pair C Reflection #3 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.pairCReflection_3 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the third worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ - unsigned int pairCReflection_3 : 3; /* 1E.C882.6:4 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C882.7 RO Reserved 11 - AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.reserved_11 - - - - Reserved - - */ - unsigned int reserved_11 : 1; /* 1E.C882.7 RO */ - /* Reserved - */ - /*! \brief 1E.C882.A:8 RO Pair C Reflection #2 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.pairCReflection_2 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the second worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ - unsigned int pairCReflection_2 : 3; /* 1E.C882.A:8 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C882.B RO Reserved 10 - AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.reserved_10 - - - - Reserved - - */ - unsigned int reserved_10 : 1; /* 1E.C882.B RO */ - /* Reserved - */ - /*! \brief 1E.C882.E:C RO Pair C Reflection #1 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.pairCReflection_1 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the first worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ - unsigned int pairCReflection_1 : 3; /* 1E.C882.E:C RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C882.F RO Reserved 9 - AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.reserved_9 - - - - Reserved - - */ - unsigned int reserved_9 : 1; /* 1E.C882.F RO */ - /* Reserved - */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global Cable Diagnostic Impedance */ - union - { - struct - { - /*! \brief 1E.C883.2:0 RO Pair D Reflection #4 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.pairDReflection_4 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the fourth worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ - unsigned int pairDReflection_4 : 3; /* 1E.C883.2:0 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C883.3 RO Reserved 16 - AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.reserved_16 - - - - Reserved - - */ - unsigned int reserved_16 : 1; /* 1E.C883.3 RO */ - /* Reserved - */ - /*! \brief 1E.C883.6:4 RO Pair D Reflection #3 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.pairDReflection_3 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the third worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ - unsigned int pairDReflection_3 : 3; /* 1E.C883.6:4 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C883.7 RO Reserved 15 - AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.reserved_15 - - - - Reserved - - */ - unsigned int reserved_15 : 1; /* 1E.C883.7 RO */ - /* Reserved - */ - /*! \brief 1E.C883.A:8 RO Pair D Reflection #2 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.pairDReflection_2 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the second worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ - unsigned int pairDReflection_2 : 3; /* 1E.C883.A:8 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C883.B RO Reserved 14 - AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.reserved_14 - - - - Reserved - - */ - unsigned int reserved_14 : 1; /* 1E.C883.B RO */ - /* Reserved - */ - /*! \brief 1E.C883.E:C RO Pair D Reflection #1 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.pairDReflection_1 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the first worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ - unsigned int pairDReflection_1 : 3; /* 1E.C883.E:C RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C883.F RO Reserved 13 - AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.reserved_13 - - - - Reserved - - */ - unsigned int reserved_13 : 1; /* 1E.C883.F RO */ - /* Reserved - */ - } bits_3; - uint16_t word_3; - } u3; -} AQ_GlobalCableDiagnosticImpedance_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Status: 1E.C884 */ -/* Global Status: 1E.C884 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Status */ - union - { - struct - { - /*! \brief 1E.C884.7:0 RO Cable Length [7:0] - AQ_GlobalStatus_HHD.u0.bits_0.cableLength - - - - The estimated length of the cable in meters - - - Notes: - The length of the cable shown here is estimated from the cable diagnostic engine and should be accurate to +/-1m. */ - unsigned int cableLength : 8; /* 1E.C884.7:0 RO */ - /* The estimated length of the cable in meters - */ - /*! \brief 1E.C884.F:8 RO Reserved Status 0 [7:0] - AQ_GlobalStatus_HHD.u0.bits_0.reservedStatus_0 - - - - Reserved - - */ - unsigned int reservedStatus_0 : 8; /* 1E.C884.F:8 RO */ - /* Reserved - */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalStatus_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Reserved Status: 1E.C885 */ -/* Global Reserved Status: 1E.C885 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Reserved Status */ - union - { - struct - { - /*! \brief 1E.C885.3:0 ROSPD Provisioning ID [3:0] - AQ_GlobalReservedStatus_HHD.u0.bits_0.provisioningID - - Provisionable Default = 0x0 - - Provisioning ID - - - Notes: - Customers may receive multiple ROM images that differ only in their provisioning. This field is used to differentiate those images. This field is used in conjunction with the firmware major and minor revision numbers to uniquely identify ROM images. */ - unsigned int provisioningID : 4; /* 1E.C885.3:0 ROSPD Provisionable Default = 0x0 */ - /* Provisioning ID - */ - /*! \brief 1E.C885.7:4 ROSPD Firmware Build ID [3:0] - AQ_GlobalReservedStatus_HHD.u0.bits_0.firmwareBuildID - - Provisionable Default = 0x0 - - Firmware Build ID - - - Notes: - Customers may receive multiple ROM images that differ only in their provisioning. This field is used to differentiate those images. This field is used in conjunction with the firmware major and minor revision numbers to uniquely identify ROM images. */ - unsigned int firmwareBuildID : 4; /* 1E.C885.7:4 ROSPD Provisionable Default = 0x0 */ - /* Firmware Build ID - */ - /*! \brief 1E.C885.9:8 ROSPD XENPAK NVR Status [1:0] - AQ_GlobalReservedStatus_HHD.u0.bits_0.xenpakNvrStatus - - Provisionable Default = 0x0 - - Status of XENPAK NVR: - 0: NVR not enabled - 1: Last NVR operation succeeded - 2: Last NVR operation failed - 3: Reserved - - - Notes: - XENPAK register space is mirrored in NVR (SPI ROM). This register indicates the status of the last NVR operation. */ - unsigned int xenpakNvrStatus : 2; /* 1E.C885.9:8 ROSPD Provisionable Default = 0x0 */ - /* Status of XENPAK NVR: - 0: NVR not enabled - 1: Last NVR operation succeeded - 2: Last NVR operation failed - 3: Reserved - */ - /*! \brief 1E.C885.F:A RO Nearly Seconds MSW[5:0] - AQ_GlobalReservedStatus_HHD.u0.bits_0.nearlySecondsMSW - - - - Bits 16 to 21 of the 22 bit "Nearly Seconds" uptime counter. - - - Notes: - The "Nearly Seconds" counter is incremented every 1024 milliseconds. */ - unsigned int nearlySecondsMSW : 6; /* 1E.C885.F:A RO */ - /* Bits 16 to 21 of the 22 bit "Nearly Seconds" uptime counter. - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Reserved Status */ - union - { - struct - { - /*! \brief 1E.C886.F:0 RO Nearly Seconds LSW [F:0] - AQ_GlobalReservedStatus_HHD.u1.bits_1.nearlySecondsLSW - - - - Bits 0 to 15 of the 22 bit "Nearly Seconds" uptime counter - - - Notes: - The "Nearly Seconds" counter is incremented every 1024 milliseconds. */ - unsigned int nearlySecondsLSW : 16; /* 1E.C886.F:0 RO */ - /* Bits 0 to 15 of the 22 bit "Nearly Seconds" uptime counter - */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global Reserved Status */ - union - { - struct - { - /*! \brief 1E.C887.D:0 RO Reserved Status 3 [D:0] - AQ_GlobalReservedStatus_HHD.u2.bits_2.reservedStatus_3 - - - - Reserved for future use - - */ - unsigned int reservedStatus_3 : 14; /* 1E.C887.D:0 RO */ - /* Reserved for future use - */ - /*! \brief 1E.C887.E ROS Power Up Stall Status - AQ_GlobalReservedStatus_HHD.u2.bits_2.powerUpStallStatus - - Default = 0x0 - - 1 = FW is stalled at power up - 0 = Firmware is unstalled - - */ - unsigned int powerUpStallStatus : 1; /* 1E.C887.E ROS Default = 0x0 */ - /* 1 = FW is stalled at power up - 0 = Firmware is unstalled - */ - /*! \brief 1E.C887.F ROS DTE Status - AQ_GlobalReservedStatus_HHD.u2.bits_2.dteStatus - - Default = 0x0 - - 1 = Need power - 0 = Don't need power - - */ - unsigned int dteStatus : 1; /* 1E.C887.F ROS Default = 0x0 */ - /* 1 = Need power - 0 = Don't need power - */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global Reserved Status */ - union - { - struct - { - /*! \brief 1E.C888.1:0 RO Rate [1:0] - AQ_GlobalReservedStatus_HHD.u3.bits_3.rate - - Default = 0x0 - - 0x3 = 10G - 0x2 = 1G - 0x1 = 100M - 0x0 = invalid - - - Notes: - These bits report the selected rate for the loopback and packet generation. */ - unsigned int rate : 2; /* 1E.C888.1:0 RO Default = 0x0 */ - /* 0x3 = 10G - 0x2 = 1G - 0x1 = 100M - 0x0 = invalid - */ - /*! \brief 1E.C888.2 RO Reserved Status 4a - AQ_GlobalReservedStatus_HHD.u3.bits_3.reservedStatus_4a - - Default = 0x0 - - Reserved for future use - - */ - unsigned int reservedStatus_4a : 1; /* 1E.C888.2 RO Default = 0x0 */ - /* Reserved for future use - */ - /*! \brief 1E.C888.3 RO System I/F Packet Generation Status - AQ_GlobalReservedStatus_HHD.u3.bits_3.systemI_fPacketGenerationStatus - - Default = 0x0 - - 1 = CRPAT packet generation out 10G system interface - 0 = No CRPAT packet generation out 10G system interface - - - Notes: - Reports whether the CRPAT packet generator in the PHY outputs on the selected system interface at the selected rate. */ - unsigned int systemI_fPacketGenerationStatus : 1; /* 1E.C888.3 RO Default = 0x0 */ - /* 1 = CRPAT packet generation out 10G system interface - 0 = No CRPAT packet generation out 10G system interface - */ - /*! \brief 1E.C888.4 RO Look-Aside Port Packet Generation Status - AQ_GlobalReservedStatus_HHD.u3.bits_3.look_asidePortPacketGenerationStatus - - Default = 0x0 - - 1 = CRPAT packet generation out 10G look-aside interface (KR0) - 0 = No CRPAT packet generation out 10G look-aside interface (KR0) - - - Notes: - Reports whether the CRPAT packet generator in the PHY outputs on the KR0 interface at the selected rate. */ - unsigned int look_asidePortPacketGenerationStatus : 1; /* 1E.C888.4 RO Default = 0x0 */ - /* 1 = CRPAT packet generation out 10G look-aside interface (KR0) - 0 = No CRPAT packet generation out 10G look-aside interface (KR0) - */ - /*! \brief 1E.C888.5 RO MDI Packet Generation Status - AQ_GlobalReservedStatus_HHD.u3.bits_3.mdiPacketGenerationStatus - - Default = 0x0 - - 1 = CRPAT packet generation out MDI interface - 0 = No CRPAT packet generation out MDI interface - - - Notes: - Reports whether the CRPAT packet generator in the PHY outputs on the MDI interface at the selected rate. */ - unsigned int mdiPacketGenerationStatus : 1; /* 1E.C888.5 RO Default = 0x0 */ - /* 1 = CRPAT packet generation out MDI interface - 0 = No CRPAT packet generation out MDI interface - */ - /*! \brief 1E.C888.A:6 RO Reserved Status 4 [4:0] - AQ_GlobalReservedStatus_HHD.u3.bits_3.reservedStatus_4 - - Default = 0x00 - - Reserved for future use - - */ - unsigned int reservedStatus_4 : 5; /* 1E.C888.A:6 RO Default = 0x00 */ - /* Reserved for future use - */ - /*! \brief 1E.C888.F:B RO Loopback Status [4:0] - AQ_GlobalReservedStatus_HHD.u3.bits_3.loopbackStatus - - Default = 0x00 - - 0x00 = No loopback - 0x01 = System Interface - System Loopback - 0x02 = System Interface - System Loopback with Passthrough - 0x03 = System Interface - Network Loopback - 0x04 = System Interface - Network Loopback with Passthrough - 0x05 = System Interface - Network Loopback with Passthrough and Merge - 0x06 = System Interface - Peer-to-peer loopback - 0x07 - 0x08 = Reserved - 0x09 = Network Interface - System Loopback - 0x0A = Network Interface - System Loopback with Passthrough - 0x0B = Network Interface - Network Loopback - 0x0C = Network Interface - Network Loopback with Passthrough - 0x0D = Network Interface - Peer-to-peer loopback - 0x0E - 0x0F = Reserved - 0x10 = Cross-connect System Loopback - 0x11 = Cross-connect Network Loopback - 0x12 - 0x13 = Reserved - 0x14 = Network Interface - System Loopback via Loopback Plug - 0x15 - 0x1F = Reserved - - - Notes: - These bits, in conjunction with the chip configuration and the rate (Bits 1:0), report the selected loopback. - - */ - unsigned int loopbackStatus : 5; /* 1E.C888.F:B RO Default = 0x00 */ - /* 0x00 = No loopback - 0x01 = System Interface - System Loopback - 0x02 = System Interface - System Loopback with Passthrough - 0x03 = System Interface - Network Loopback - 0x04 = System Interface - Network Loopback with Passthrough - 0x05 = System Interface - Network Loopback with Passthrough and Merge - 0x06 = System Interface - Peer-to-peer loopback - 0x07 - 0x08 = Reserved - 0x09 = Network Interface - System Loopback - 0x0A = Network Interface - System Loopback with Passthrough - 0x0B = Network Interface - Network Loopback - 0x0C = Network Interface - Network Loopback with Passthrough - 0x0D = Network Interface - Peer-to-peer loopback - 0x0E - 0x0F = Reserved - 0x10 = Cross-connect System Loopback - 0x11 = Cross-connect Network Loopback - 0x12 - 0x13 = Reserved - 0x14 = Network Interface - System Loopback via Loopback Plug - 0x15 - 0x1F = Reserved - */ - } bits_3; - uint16_t word_3; - } u3; -} AQ_GlobalReservedStatus_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Alarms: 1E.CC00 */ -/* Global Alarms: 1E.CC00 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Alarms */ - union - { - struct - { - /*! \brief 1E.CC00.0 LH Reserved Alarm D - AQ_GlobalAlarms_HHD.u0.bits_0.reservedAlarmD - - - - Reserved for future use - - */ - unsigned int reservedAlarmD : 1; /* 1E.CC00.0 LH */ - /* Reserved for future use - */ - /*! \brief 1E.CC00.1 LH Reserved Alarm C - AQ_GlobalAlarms_HHD.u0.bits_0.reservedAlarmC - - - - Reserved for future use - - */ - unsigned int reservedAlarmC : 1; /* 1E.CC00.1 LH */ - /* Reserved for future use - */ - /*! \brief 1E.CC00.2 LH Reserved Alarm B - AQ_GlobalAlarms_HHD.u0.bits_0.reservedAlarmB - - - - Reserved for future use - - */ - unsigned int reservedAlarmB : 1; /* 1E.CC00.2 LH */ - /* Reserved for future use - */ - /*! \brief 1E.CC00.3 LH Reserved Alarm A - AQ_GlobalAlarms_HHD.u0.bits_0.reservedAlarmA - - - - Reserved for future use - - */ - unsigned int reservedAlarmA : 1; /* 1E.CC00.3 LH */ - /* Reserved for future use - */ - /*! \brief 1E.CC00.4 LH Device Fault - AQ_GlobalAlarms_HHD.u0.bits_0.deviceFault - - - - 1 = Fault - - Notes: - When set, a fault has been detected by the uP and the associated 16 bit error code is visible in See Global Configuration Fault Message: Address 1E.C850 */ - unsigned int deviceFault : 1; /* 1E.CC00.4 LH */ - /* 1 = Fault */ - unsigned int reserved2 : 1; - /*! \brief 1E.CC00.6 LH Reset completed - AQ_GlobalAlarms_HHD.u0.bits_0.resetCompleted - - - - 1 = Chip wide reset completed - - Notes: - This bit is set by the microprocessor when it has completed it's initialization sequence. This bit is mirrored in 1.CC02.0 */ - unsigned int resetCompleted : 1; /* 1E.CC00.6 LH */ - /* 1 = Chip wide reset completed */ - unsigned int reserved1 : 4; - /*! \brief 1E.CC00.B LH Low Temperature Warning - AQ_GlobalAlarms_HHD.u0.bits_0.lowTemperatureWarning - - - - 1 = Low temperature warning threshold has been exceeded - - - Notes: - - - - - These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ - unsigned int lowTemperatureWarning : 1; /* 1E.CC00.B LH */ - /* 1 = Low temperature warning threshold has been exceeded - */ - /*! \brief 1E.CC00.C LH High Temperature Warning - AQ_GlobalAlarms_HHD.u0.bits_0.highTemperatureWarning - - - - 1 = High temperature warning threshold has been exceeded - - - Notes: - - - - - These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ - unsigned int highTemperatureWarning : 1; /* 1E.CC00.C LH */ - /* 1 = High temperature warning threshold has been exceeded - */ - /*! \brief 1E.CC00.D LH Low Temperature Failure - AQ_GlobalAlarms_HHD.u0.bits_0.lowTemperatureFailure - - - - 1 = Low temperature failure threshold has been exceeded - - - Notes: - - - - - These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ - unsigned int lowTemperatureFailure : 1; /* 1E.CC00.D LH */ - /* 1 = Low temperature failure threshold has been exceeded - */ - /*! \brief 1E.CC00.E LH High Temperature Failure - AQ_GlobalAlarms_HHD.u0.bits_0.highTemperatureFailure - - - - 1 = High temperature failure threshold has been exceeded - - - Notes: - - - - - These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ - unsigned int highTemperatureFailure : 1; /* 1E.CC00.E LH */ - /* 1 = High temperature failure threshold has been exceeded - */ - unsigned int reserved0 : 1; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Alarms */ - union - { - struct - { - unsigned int reserved2 : 1; - unsigned int reserved1 : 6; - /*! \brief 1E.CC01.7 LH MDIO Command Handling Overflow - AQ_GlobalAlarms_HHD.u1.bits_1.mdioCommandHandlingOverflow - - - - 1 = PHY was issued more MDIO requests than it could service in it's request buffer - - - Notes: - Assertion of this bit means that more MDIO commands were issued than FW could handle. */ - unsigned int mdioCommandHandlingOverflow : 1; /* 1E.CC01.7 LH */ - /* 1 = PHY was issued more MDIO requests than it could service in it's request buffer - */ - /*! \brief 1E.CC01.A:8 LH Reserved Alarms [2:0] - AQ_GlobalAlarms_HHD.u1.bits_1.reservedAlarms - - - - Reserved - - - */ - unsigned int reservedAlarms : 3; /* 1E.CC01.A:8 LH */ - /* Reserved - - */ - /*! \brief 1E.CC01.B LH DTE Status Change - AQ_GlobalAlarms_HHD.u1.bits_1.dteStatusChange - - - - 1 = DTE status change - - - Notes: - Change in 1E.C887[F]. */ - unsigned int dteStatusChange : 1; /* 1E.CC01.B LH */ - /* 1 = DTE status change - */ - /*! \brief 1E.CC01.C LH IP Phone Detect - AQ_GlobalAlarms_HHD.u1.bits_1.ipPhoneDetect - - - - 1 = IP Phone Detect - - - Notes: - Assertion of this bit means that the presence of an IP Phone has been detected. */ - unsigned int ipPhoneDetect : 1; /* 1E.CC01.C LH */ - /* 1 = IP Phone Detect - */ - /*! \brief 1E.CC01.D RO XENPAK Alarm - AQ_GlobalAlarms_HHD.u1.bits_1.xenpakAlarm - - - - 1 = XENPAK Alarm - - */ - unsigned int xenpakAlarm : 1; /* 1E.CC01.D RO */ - /* 1 = XENPAK Alarm - */ - /*! \brief 1E.CC01.E LH Smart Power-Down Entered - AQ_GlobalAlarms_HHD.u1.bits_1.smartPower_downEntered - - - - 1 = Smart Power-Down State Entered - - - Notes: - When this bit is set, it indicates that the Smart Power-Down state was entered */ - unsigned int smartPower_downEntered : 1; /* 1E.CC01.E LH */ - /* 1 = Smart Power-Down State Entered - */ - unsigned int reserved0 : 1; - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global Alarms */ - union - { - struct - { - /*! \brief 1E.CC02.0 LH Watchdog Timer Alarm - AQ_GlobalAlarms_HHD.u2.bits_2.watchdogTimerAlarm - - - - 1 = Watchdog timer alarm - - */ - unsigned int watchdogTimerAlarm : 1; /* 1E.CC02.0 LH */ - /* 1 = Watchdog timer alarm - */ - /*! \brief 1E.CC02.1 LH MDIO Timeout Error - AQ_GlobalAlarms_HHD.u2.bits_2.mdioTimeoutError - - - - 1 = MDIO timeout detected - - */ - unsigned int mdioTimeoutError : 1; /* 1E.CC02.1 LH */ - /* 1 = MDIO timeout detected - */ - /*! \brief 1E.CC02.2 LH MDIO MMD Error - AQ_GlobalAlarms_HHD.u2.bits_2.mdioMMD_Error - - - - 1 = Invalid MMD address detected - - */ - unsigned int mdioMMD_Error : 1; /* 1E.CC02.2 LH */ - /* 1 = Invalid MMD address detected - */ - unsigned int reserved2 : 2; - /*! \brief 1E.CC02.5 LRF Tx Enable State Change - AQ_GlobalAlarms_HHD.u2.bits_2.txEnableStateChange - - - - 1 = TX_EN pin has changed state - - */ - unsigned int txEnableStateChange : 1; /* 1E.CC02.5 LRF */ - /* 1 = TX_EN pin has changed state - */ - unsigned int reserved1 : 2; - /*! \brief 1E.CC02.9:8 LH uP IRAM Parity Error [1:0] - AQ_GlobalAlarms_HHD.u2.bits_2.upIramParityError - - - - 1 = Parity error detected in the uP IRAM - - - Notes: - Bit 0 indicates a parity error was detected in the uP IRAM but was corrected. - Bit 1 indicates a multiple parity errors were detected in the uP IRAM and could not be corrected. - The uP IRAM is protected with ECC. */ - unsigned int upIramParityError : 2; /* 1E.CC02.9:8 LH */ - /* 1 = Parity error detected in the uP IRAM - */ - /*! \brief 1E.CC02.A LH uP DRAM Parity Error - AQ_GlobalAlarms_HHD.u2.bits_2.upDramParityError - - - - 1 = Parity error detected in the uP DRAM - - */ - unsigned int upDramParityError : 1; /* 1E.CC02.A LH */ - /* 1 = Parity error detected in the uP DRAM - */ - unsigned int reserved0 : 3; - /*! \brief 1E.CC02.E LH Mailbox Operation: Complete - AQ_GlobalAlarms_HHD.u2.bits_2.mailboxOperation_Complete - - - - 1 = Mailbox operation is complete - - - Notes: - Mailbox interface is ready interrupt for registers See Global Vendor Specific Control - Address 1E.C000 - See Global Vendor Specific Provisioning 5 - Address 1E.C404 */ - unsigned int mailboxOperation_Complete : 1; /* 1E.CC02.E LH */ - /* 1 = Mailbox operation is complete - */ - /*! \brief 1E.CC02.F LH NVR Operation Complete - AQ_GlobalAlarms_HHD.u2.bits_2.nvrOperationComplete - - - - 1 = NVR operation is complete - - - Notes: - NVR interface is ready interrupt for registers See Global NVR Interface 1: Address 1E.100 - See Global NVR Provisioning Data MSW - Address 1E.17 . */ - unsigned int nvrOperationComplete : 1; /* 1E.CC02.F LH */ - /* 1 = NVR operation is complete - */ - } bits_2; - uint16_t word_2; - } u2; -} AQ_GlobalAlarms_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Interrupt Mask: 1E.D400 */ -/* Global Interrupt Mask: 1E.D400 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Interrupt Mask */ - union - { - struct - { - /*! \brief 1E.D400.0 R/WPD Reserved Alarm D Mask - AQ_GlobalInterruptMask_HHD.u0.bits_0.reservedAlarmDMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int reservedAlarmDMask : 1; /* 1E.D400.0 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - /*! \brief 1E.D400.1 R/WPD Reserved Alarm C Mask - AQ_GlobalInterruptMask_HHD.u0.bits_0.reservedAlarmCMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int reservedAlarmCMask : 1; /* 1E.D400.1 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - /*! \brief 1E.D400.2 R/WPD Reserved Alarm B Mask - AQ_GlobalInterruptMask_HHD.u0.bits_0.reservedAlarmBMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int reservedAlarmBMask : 1; /* 1E.D400.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - /*! \brief 1E.D400.3 R/WPD Reserved Alarm A Mask - AQ_GlobalInterruptMask_HHD.u0.bits_0.reservedAlarmAMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int reservedAlarmAMask : 1; /* 1E.D400.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - /*! \brief 1E.D400.4 R/WPD Device Fault Mask - AQ_GlobalInterruptMask_HHD.u0.bits_0.deviceFaultMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int deviceFaultMask : 1; /* 1E.D400.4 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - unsigned int reserved2 : 1; - /*! \brief 1E.D400.6 R/WPD Reset completed Mask - AQ_GlobalInterruptMask_HHD.u0.bits_0.resetCompletedMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int resetCompletedMask : 1; /* 1E.D400.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - unsigned int reserved1 : 4; - /*! \brief 1E.D400.B R/WPD Low Temperature Warning Mask - AQ_GlobalInterruptMask_HHD.u0.bits_0.lowTemperatureWarningMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int lowTemperatureWarningMask : 1; /* 1E.D400.B R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.D400.C R/WPD High Temperature Warning Mask - AQ_GlobalInterruptMask_HHD.u0.bits_0.highTemperatureWarningMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int highTemperatureWarningMask : 1; /* 1E.D400.C R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.D400.D R/WPD Low Temperature Failure Mask - AQ_GlobalInterruptMask_HHD.u0.bits_0.lowTemperatureFailureMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int lowTemperatureFailureMask : 1; /* 1E.D400.D R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.D400.E R/WPD High Temperature Failure Mask - AQ_GlobalInterruptMask_HHD.u0.bits_0.highTemperatureFailureMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int highTemperatureFailureMask : 1; /* 1E.D400.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - unsigned int reserved0 : 1; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Interrupt Mask */ - union - { - struct - { - /*! \brief 1E.D401.0 R/WPD Diagnostic Alarm Mask - AQ_GlobalInterruptMask_HHD.u1.bits_1.diagnosticAlarmMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int diagnosticAlarmMask : 1; /* 1E.D401.0 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int reserved1 : 6; - /*! \brief 1E.D401.7 R/WPD MDIO Command Handling Overflow Mask - AQ_GlobalInterruptMask_HHD.u1.bits_1.mdioCommandHandlingOverflowMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int mdioCommandHandlingOverflowMask : 1; /* 1E.D401.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - /*! \brief 1E.D401.A:8 R/WPD Reserved Alarms Mask [2:0] - AQ_GlobalInterruptMask_HHD.u1.bits_1.reservedAlarmsMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int reservedAlarmsMask : 3; /* 1E.D401.A:8 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - /*! \brief 1E.D401.B R/WPD DTE Status Change Mask - AQ_GlobalInterruptMask_HHD.u1.bits_1.dteStatusChangeMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int dteStatusChangeMask : 1; /* 1E.D401.B R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - /*! \brief 1E.D401.C R/WPD IP Phone Detect Mask - AQ_GlobalInterruptMask_HHD.u1.bits_1.ipPhoneDetectMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int ipPhoneDetectMask : 1; /* 1E.D401.C R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - /*! \brief 1E.D401.D R/WPD XENPAK Alarm Mask - AQ_GlobalInterruptMask_HHD.u1.bits_1.xenpakAlarmMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int xenpakAlarmMask : 1; /* 1E.D401.D R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.D401.E R/WPD Smart Power-Down Entered Mask - AQ_GlobalInterruptMask_HHD.u1.bits_1.smartPower_downEnteredMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int smartPower_downEnteredMask : 1; /* 1E.D401.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int reserved0 : 1; - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global Interrupt Mask */ - union - { - struct - { - /*! \brief 1E.D402.0 R/WPD Watchdog Timer Alarm Mask - AQ_GlobalInterruptMask_HHD.u2.bits_2.watchdogTimerAlarmMask - - Provisionable Default = 0x1 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int watchdogTimerAlarmMask : 1; /* 1E.D402.0 R/WPD Provisionable Default = 0x1 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.D402.1 R/WPD MDIO Timeout Error Mask - AQ_GlobalInterruptMask_HHD.u2.bits_2.mdioTimeoutErrorMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int mdioTimeoutErrorMask : 1; /* 1E.D402.1 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.D402.2 R/WPD MDIO MMD Error Mask - AQ_GlobalInterruptMask_HHD.u2.bits_2.mdioMMD_ErrorMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int mdioMMD_ErrorMask : 1; /* 1E.D402.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - unsigned int reserved2 : 2; - /*! \brief 1E.D402.5 R/WPD Tx Enable State Change Mask - AQ_GlobalInterruptMask_HHD.u2.bits_2.txEnableStateChangeMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int txEnableStateChangeMask : 1; /* 1E.D402.5 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - unsigned int reserved1 : 2; - /*! \brief 1E.D402.9:8 R/WPD uP IRAM Parity Error Mask [1:0] - AQ_GlobalInterruptMask_HHD.u2.bits_2.upIramParityErrorMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int upIramParityErrorMask : 2; /* 1E.D402.9:8 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - /*! \brief 1E.D402.A R/WPD uP DRAM Parity Error Mask - AQ_GlobalInterruptMask_HHD.u2.bits_2.upDramParityErrorMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int upDramParityErrorMask : 1; /* 1E.D402.A R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int reserved0 : 3; - /*! \brief 1E.D402.E R/WPD Mailbox Operation Complete Mask - AQ_GlobalInterruptMask_HHD.u2.bits_2.mailboxOperationCompleteMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - Notes: - Mailbox interface is ready interrupt for registers See Global Vendor Specific Control - Address 1E.C000 - See Global Vendor Specific Provisioning 5 - Address 1E.C404 */ - unsigned int mailboxOperationCompleteMask : 1; /* 1E.D402.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.D402.F R/WPD NVR Operation Complete Mask - AQ_GlobalInterruptMask_HHD.u2.bits_2.nvrOperationCompleteMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - Notes: - NVR interface is ready interrupt for registers See Global NVR Interface 1: Address 1E.100 - See Global NVR Provisioning Data MSW - Address 1E.17 */ - unsigned int nvrOperationCompleteMask : 1; /* 1E.D402.F R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - } bits_2; - uint16_t word_2; - } u2; -} AQ_GlobalInterruptMask_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Chip-Wide Standard Interrupt Flags: 1E.FC00 */ -/* Global Chip-Wide Standard Interrupt Flags: 1E.FC00 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Chip-Wide Standard Interrupt Flags */ - union - { - struct - { - /*! \brief 1E.FC00.0 RO All Vendor Alarms Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.allVendorAlarmsInterrupt - - - - 1 = Interrupt in all vendor alarms - - - Notes: - An interrupt was generated from status register ( See Global Chip-Wide LASI Vendor Interrupt Flags: Address 1E.FC01 ) and the corresponding mask register. ( See Global Interrupt LASI Mask: Address 1E.FF01 ) */ - unsigned int allVendorAlarmsInterrupt : 1; /* 1E.FC00.0 RO */ - /* 1 = Interrupt in all vendor alarms - */ - unsigned int reserved0 : 5; - /*! \brief 1E.FC00.6 RO GbE Standard Alarms Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.gbeStandardAlarmsInterrupt - - - - 1 = Interrupt in GbE standard alarms - - - Notes: - An interrupt was generated from the TGE core. */ - unsigned int gbeStandardAlarmsInterrupt : 1; /* 1E.FC00.6 RO */ - /* 1 = Interrupt in GbE standard alarms - */ - /*! \brief 1E.FC00.7 RO Autonegotiation Standard Alarms 2 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.autonegotiationStandardAlarms_2Interrupt - - - - 1 = Interrupt in Autonegotiation standard alarms 2 - - - Notes: - An interrupt was generated from status register ( See Autonegotiation 10GBASE-T Status Register - Address 7.21 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ - unsigned int autonegotiationStandardAlarms_2Interrupt : 1; /* 1E.FC00.7 RO */ - /* 1 = Interrupt in Autonegotiation standard alarms 2 - */ - /*! \brief 1E.FC00.8 RO Autonegotiation Standard Alarms 1 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.autonegotiationStandardAlarms_1Interrupt - - - - 1 = Interrupt in Autonegotiation standard alarms 1 - - - Notes: - An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See Autonegotiation Standard LASI Interrupt Mask 1: Address 7.D000 ) */ - unsigned int autonegotiationStandardAlarms_1Interrupt : 1; /* 1E.FC00.8 RO */ - /* 1 = Interrupt in Autonegotiation standard alarms 1 - */ - /*! \brief 1E.FC00.9 RO PHY XS Standard Alarms 2 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.phyXS_StandardAlarms_2Interrupt - - - - 1 = Interrupt in PHY XS standard alarms 2 - - - Notes: - An interrupt was generated from the status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ - unsigned int phyXS_StandardAlarms_2Interrupt : 1; /* 1E.FC00.9 RO */ - /* 1 = Interrupt in PHY XS standard alarms 2 - */ - /*! \brief 1E.FC00.A RO PHY XS Standard Alarms 1 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.phyXS_StandardAlarms_1Interrupt - - - - 1 = Interrupt in PHY XS standard alarms 1 - - - Notes: - An interrupt was generated from the status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ - unsigned int phyXS_StandardAlarms_1Interrupt : 1; /* 1E.FC00.A RO */ - /* 1 = Interrupt in PHY XS standard alarms 1 - */ - /*! \brief 1E.FC00.B RO PCS Standard Alarm 3 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.pcsStandardAlarm_3Interrupt - - - - 1 = Interrupt in PCS standard alarms 3 - - - Notes: - An interrupt was generated from status register ( See PCS 10GBASE-T Status 2 - Address 3.21 ) and the corresponding mask register. ( See PCS Standard Interrupt Mask 1 - Address 3.E021 ) */ - unsigned int pcsStandardAlarm_3Interrupt : 1; /* 1E.FC00.B RO */ - /* 1 = Interrupt in PCS standard alarms 3 - */ - /*! \brief 1E.FC00.C RO PCS Standard Alarm 2 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.pcsStandardAlarm_2Interrupt - - - - 1 = Interrupt in PCS standard alarms 2 - - - Notes: - An interrupt was generated from status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ - unsigned int pcsStandardAlarm_2Interrupt : 1; /* 1E.FC00.C RO */ - /* 1 = Interrupt in PCS standard alarms 2 - */ - /*! \brief 1E.FC00.D RO PCS Standard Alarm 1 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.pcsStandardAlarm_1Interrupt - - - - 1 = Interrupt in PCS standard alarms 1 - - - Notes: - An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ - unsigned int pcsStandardAlarm_1Interrupt : 1; /* 1E.FC00.D RO */ - /* 1 = Interrupt in PCS standard alarms 1 - */ - /*! \brief 1E.FC00.E RO PMA Standard Alarm 2 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.pmaStandardAlarm_2Interrupt - - - - 1 = Interrupt in PMA standard alarms 2 - - - Notes: - An interrupt was generated from either bit 1.8.B or 1.8.A. - An interrupt was generated from status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ - unsigned int pmaStandardAlarm_2Interrupt : 1; /* 1E.FC00.E RO */ - /* 1 = Interrupt in PMA standard alarms 2 - */ - /*! \brief 1E.FC00.F RO PMA Standard Alarm 1 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.pmaStandardAlarm_1Interrupt - - - - 1 = Interrupt in PMA standard alarms 1 - - - Notes: - An interrupt was generated from bit 1.1.2. - An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ - unsigned int pmaStandardAlarm_1Interrupt : 1; /* 1E.FC00.F RO */ - /* 1 = Interrupt in PMA standard alarms 1 - */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalChip_wideStandardInterruptFlags_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Chip-Wide Vendor Interrupt Flags: 1E.FC01 */ -/* Global Chip-Wide Vendor Interrupt Flags: 1E.FC01 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Chip-Wide Vendor Interrupt Flags */ - union - { - struct - { - /*! \brief 1E.FC01.0 RO Global Alarms 3 Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.globalAlarms_3Interrupt - - - - 1 = Interrupt in Global alarms 3 - - - Notes: - An interrupt was generated from status register ( See Global Vendor Alarms 2: Address 1E.CC01 ) and the corresponding mask register. ( See Global LASI Interrupt Mask 2: Address 1E.D401 ) */ - unsigned int globalAlarms_3Interrupt : 1; /* 1E.FC01.0 RO */ - /* 1 = Interrupt in Global alarms 3 - */ - /*! \brief 1E.FC01.1 RO Global Alarms 2 Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.globalAlarms_2Interrupt - - - - 1 = Interrupt in Global alarms 2 - - - Notes: - An interrupt was generated from status register ( See Global Alarms 2: Address 1E.CC01 ) and the corresponding mask register. ( See Global LASI Interrupt Mask 2: Address 1E.D401 ) */ - unsigned int globalAlarms_2Interrupt : 1; /* 1E.FC01.1 RO */ - /* 1 = Interrupt in Global alarms 2 - */ - /*! \brief 1E.FC01.2 RO Global Alarms 1 Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.globalAlarms_1Interrupt - - - - 1 = Interrupt in Global alarms 1 - - - Notes: - An interrupt was generated from status register ( See Global Vendor Alarms 1 - Address 1E.CC00 ) and the corresponding mask register. ( See Global Vendor Interrupt Mask - Address 1E.D400 ) */ - unsigned int globalAlarms_1Interrupt : 1; /* 1E.FC01.2 RO */ - /* 1 = Interrupt in Global alarms 1 - */ - unsigned int reserved0 : 8; - /*! \brief 1E.FC01.B RO GbE Vendor Alarm Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.gbeVendorAlarmInterrupt - - - - 1 = Interrupt in GbE vendor specific alarm - - - Notes: - A GbE alarm was generated. ( See GbE PHY Vendor Global LASI Interrupt Flags 1: Address 1D.FC00 ) */ - unsigned int gbeVendorAlarmInterrupt : 1; /* 1E.FC01.B RO */ - /* 1 = Interrupt in GbE vendor specific alarm - */ - /*! \brief 1E.FC01.C RO Autonegotiation Vendor Alarm Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.autonegotiationVendorAlarmInterrupt - - - - 1 = Interrupt in Autonegotiation vendor specific alarm - - - Notes: - An Autonegotiation alarm was generated. ( See Autonegotiation Vendor Global LASI Interrupt Flags 1: Address 7.FC00 ) */ - unsigned int autonegotiationVendorAlarmInterrupt : 1; /* 1E.FC01.C RO */ - /* 1 = Interrupt in Autonegotiation vendor specific alarm - */ - /*! \brief 1E.FC01.D RO PHY XS Vendor Alarm Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.phyXS_VendorAlarmInterrupt - - - - 1 = Interrupt in PHY XS vendor specific alarm - - - Notes: - A PHY XS alarm was generated. ( See PHY XS Vendor Global LASI Interrupt Flags 1: Address 4.FC00 ) */ - unsigned int phyXS_VendorAlarmInterrupt : 1; /* 1E.FC01.D RO */ - /* 1 = Interrupt in PHY XS vendor specific alarm - */ - /*! \brief 1E.FC01.E RO PCS Vendor Alarm Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.pcsVendorAlarmInterrupt - - - - 1 = Interrupt in PCS vendor specific alarm - - - Notes: - A PCS alarm was generated. ( See PHY XS Vendor Global Interrupt Flags 1- Address 4.F800 ) */ - unsigned int pcsVendorAlarmInterrupt : 1; /* 1E.FC01.E RO */ - /* 1 = Interrupt in PCS vendor specific alarm - */ - /*! \brief 1E.FC01.F RO PMA Vendor Alarm Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.pmaVendorAlarmInterrupt - - - - 1 = Interrupt in PMA vendor specific alarm - - - Notes: - A PMA alarm was generated. ( See PHY XS Vendor Global Interrupt Flags 1- Address 4.F800 ) */ - unsigned int pmaVendorAlarmInterrupt : 1; /* 1E.FC01.F RO */ - /* 1 = Interrupt in PMA vendor specific alarm - */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalChip_wideVendorInterruptFlags_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Interrupt Chip-Wide Standard Mask: 1E.FF00 */ -/* Global Interrupt Chip-Wide Standard Mask: 1E.FF00 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Interrupt Chip-Wide Standard Mask */ - union - { - struct - { - /*! \brief 1E.FF00.0 R/WPD All Vendor Alarms Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.allVendorAlarmsInterruptMask - - Provisionable Default = 0x1 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int allVendorAlarmsInterruptMask : 1; /* 1E.FF00.0 R/WPD Provisionable Default = 0x1 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - unsigned int reserved0 : 5; - /*! \brief 1E.FF00.6 R/WPD Gbe Standard Alarms Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.gbeStandardAlarmsInterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int gbeStandardAlarmsInterruptMask : 1; /* 1E.FF00.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.7 R/WPD Autonegotiation Standard Alarms 2 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.autonegotiationStandardAlarms_2InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int autonegotiationStandardAlarms_2InterruptMask : 1; /* 1E.FF00.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.8 R/WPD Autonegotiation Standard Alarms 1 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.autonegotiationStandardAlarms_1InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int autonegotiationStandardAlarms_1InterruptMask : 1; /* 1E.FF00.8 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.9 R/WPD PHY XS Standard Alarms 2 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.phyXS_StandardAlarms_2InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int phyXS_StandardAlarms_2InterruptMask : 1; /* 1E.FF00.9 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.A R/WPD PHY XS Standard Alarms 1 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.phyXS_StandardAlarms_1InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int phyXS_StandardAlarms_1InterruptMask : 1; /* 1E.FF00.A R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.B R/WPD PCS Standard Alarm 3 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.pcsStandardAlarm_3InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int pcsStandardAlarm_3InterruptMask : 1; /* 1E.FF00.B R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.C R/WPD PCS Standard Alarm 2 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.pcsStandardAlarm_2InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int pcsStandardAlarm_2InterruptMask : 1; /* 1E.FF00.C R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.D R/WPD PCS Standard Alarm 1 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.pcsStandardAlarm_1InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int pcsStandardAlarm_1InterruptMask : 1; /* 1E.FF00.D R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.E R/WPD PMA Standard Alarm 2 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.pmaStandardAlarm_2InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int pmaStandardAlarm_2InterruptMask : 1; /* 1E.FF00.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.F R/WPD PMA Standard Alarm 1 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.pmaStandardAlarm_1InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int pmaStandardAlarm_1InterruptMask : 1; /* 1E.FF00.F R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalInterruptChip_wideStandardMask_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Interrupt Chip-Wide Vendor Mask: 1E.FF01 */ -/* Global Interrupt Chip-Wide Vendor Mask: 1E.FF01 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Interrupt Chip-Wide Vendor Mask */ - union - { - struct - { - /*! \brief 1E.FF01.0 R/WPD Global Alarms 3 Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.globalAlarms_3InterruptMask - - Provisionable Default = 0x1 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int globalAlarms_3InterruptMask : 1; /* 1E.FF01.0 R/WPD Provisionable Default = 0x1 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF01.1 R/WPD Global Alarms 2 Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.globalAlarms_2InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int globalAlarms_2InterruptMask : 1; /* 1E.FF01.1 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF01.2 R/WPD Global Alarms 1 Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.globalAlarms_1InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int globalAlarms_1InterruptMask : 1; /* 1E.FF01.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - unsigned int reserved0 : 8; - /*! \brief 1E.FF01.B R/WPD GbE Vendor Alarm Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.gbeVendorAlarmInterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int gbeVendorAlarmInterruptMask : 1; /* 1E.FF01.B R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF01.C R/WPD Autonegotiation Vendor Alarm Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.autonegotiationVendorAlarmInterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int autonegotiationVendorAlarmInterruptMask : 1; /* 1E.FF01.C R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF01.D R/WPD PHY XS Vendor Alarm Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.phyXS_VendorAlarmInterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int phyXS_VendorAlarmInterruptMask : 1; /* 1E.FF01.D R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF01.E R/WPD PCS Vendor Alarm Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.pcsVendorAlarmInterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int pcsVendorAlarmInterruptMask : 1; /* 1E.FF01.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF01.F R/WPD PMA Vendor Alarm Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.pmaVendorAlarmInterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int pmaVendorAlarmInterruptMask : 1; /* 1E.FF01.F R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalInterruptChip_wideVendorMask_HHD; - -#endif -/*@}*/ -/*@}*/ diff --git a/qca/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers_Defines.h b/qca/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers_Defines.h deleted file mode 100644 index d9a4429d5..000000000 --- a/qca/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers_Defines.h +++ /dev/null @@ -1,4413 +0,0 @@ -/*! \file -* This file contains the compiler assist macros and doxygen comments -* for the Global Registers block. -*/ - -/*! \defgroup Global_registers_Defines Global Registers Defines -* This module contains the compiler assist macros and doxygen comments -* for the Global Registers block. -*/ -/*********************************************************************** -* Copyright (c) 2015, Aquantia -* -* Permission to use, copy, modify, and/or distribute this software for any -* purpose with or without fee is hereby granted, provided that the above -* copyright notice and this permission notice appear in all copies. -* -* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -* -* $File: //depot/icm/proj/Dena/rev1.0/c/Systems/tools/windows/regMapParser/src/gencheaders.py $ -* -* $Revision: #10 $ -* -* $DateTime: 2014/04/08 16:55:58 $ -* -* $Author: joshd $ -* -* $Label: $ -* -* Description: -* -* This file contains the compiler assist macros for the registers contained in the Global Registers block. -* -* -***********************************************************************/ - - -/*@{*/ -#ifndef AQ_HHD_GLOBAL_REGS_DEFINES_HEADER -#define AQ_HHD_GLOBAL_REGS_DEFINES_HEADER - - -/*-----------------------------------------------------------------------------*/ -/*Access macro definitions */ -/*-----------------------------------------------------------------------------*/ -/*! \brief Base register address of structure AQ_GlobalStandardControl_1_HHD */ -#define AQ_GlobalStandardControl_1_HHD_baseRegisterAddress 0x0000 -/*! \brief MMD address of structure AQ_GlobalStandardControl_1_HHD */ -#define AQ_GlobalStandardControl_1_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure softReset in AQ_GlobalStandardControl_1_HHD */ -#define AQ_GlobalStandardControl_1_HHD_softReset 0 -/*! \brief Preprocessor variable to relate field to bit position in structure softReset in AQ_GlobalStandardControl_1_HHD */ -#define bits_AQ_GlobalStandardControl_1_HHD_softReset u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure softReset in AQ_GlobalStandardControl_1_HHD */ -#define word_AQ_GlobalStandardControl_1_HHD_softReset u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure lowPower in AQ_GlobalStandardControl_1_HHD */ -#define AQ_GlobalStandardControl_1_HHD_lowPower 0 -/*! \brief Preprocessor variable to relate field to bit position in structure lowPower in AQ_GlobalStandardControl_1_HHD */ -#define bits_AQ_GlobalStandardControl_1_HHD_lowPower u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure lowPower in AQ_GlobalStandardControl_1_HHD */ -#define word_AQ_GlobalStandardControl_1_HHD_lowPower u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalStandardDeviceIdentifier_HHD */ -#define AQ_GlobalStandardDeviceIdentifier_HHD_baseRegisterAddress 0x0002 -/*! \brief MMD address of structure AQ_GlobalStandardDeviceIdentifier_HHD */ -#define AQ_GlobalStandardDeviceIdentifier_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure deviceIdMSW in AQ_GlobalStandardDeviceIdentifier_HHD */ -#define AQ_GlobalStandardDeviceIdentifier_HHD_deviceIdMSW 0 -/*! \brief Preprocessor variable to relate field to bit position in structure deviceIdMSW in AQ_GlobalStandardDeviceIdentifier_HHD */ -#define bits_AQ_GlobalStandardDeviceIdentifier_HHD_deviceIdMSW u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure deviceIdMSW in AQ_GlobalStandardDeviceIdentifier_HHD */ -#define word_AQ_GlobalStandardDeviceIdentifier_HHD_deviceIdMSW u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure deviceIdLSW in AQ_GlobalStandardDeviceIdentifier_HHD */ -#define AQ_GlobalStandardDeviceIdentifier_HHD_deviceIdLSW 1 -/*! \brief Preprocessor variable to relate field to bit position in structure deviceIdLSW in AQ_GlobalStandardDeviceIdentifier_HHD */ -#define bits_AQ_GlobalStandardDeviceIdentifier_HHD_deviceIdLSW u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure deviceIdLSW in AQ_GlobalStandardDeviceIdentifier_HHD */ -#define word_AQ_GlobalStandardDeviceIdentifier_HHD_deviceIdLSW u1.word_1 - -/*! \brief Base register address of structure AQ_GlobalStandardDevicesInPackage_HHD */ -#define AQ_GlobalStandardDevicesInPackage_HHD_baseRegisterAddress 0x0005 -/*! \brief MMD address of structure AQ_GlobalStandardDevicesInPackage_HHD */ -#define AQ_GlobalStandardDevicesInPackage_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationPresent in AQ_GlobalStandardDevicesInPackage_HHD */ -#define AQ_GlobalStandardDevicesInPackage_HHD_autonegotiationPresent 0 -/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationPresent in AQ_GlobalStandardDevicesInPackage_HHD */ -#define bits_AQ_GlobalStandardDevicesInPackage_HHD_autonegotiationPresent u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationPresent in AQ_GlobalStandardDevicesInPackage_HHD */ -#define word_AQ_GlobalStandardDevicesInPackage_HHD_autonegotiationPresent u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure tcPresent in AQ_GlobalStandardDevicesInPackage_HHD */ -#define AQ_GlobalStandardDevicesInPackage_HHD_tcPresent 0 -/*! \brief Preprocessor variable to relate field to bit position in structure tcPresent in AQ_GlobalStandardDevicesInPackage_HHD */ -#define bits_AQ_GlobalStandardDevicesInPackage_HHD_tcPresent u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure tcPresent in AQ_GlobalStandardDevicesInPackage_HHD */ -#define word_AQ_GlobalStandardDevicesInPackage_HHD_tcPresent u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure dteXsPresent in AQ_GlobalStandardDevicesInPackage_HHD */ -#define AQ_GlobalStandardDevicesInPackage_HHD_dteXsPresent 0 -/*! \brief Preprocessor variable to relate field to bit position in structure dteXsPresent in AQ_GlobalStandardDevicesInPackage_HHD */ -#define bits_AQ_GlobalStandardDevicesInPackage_HHD_dteXsPresent u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure dteXsPresent in AQ_GlobalStandardDevicesInPackage_HHD */ -#define word_AQ_GlobalStandardDevicesInPackage_HHD_dteXsPresent u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure phyXS_Present in AQ_GlobalStandardDevicesInPackage_HHD */ -#define AQ_GlobalStandardDevicesInPackage_HHD_phyXS_Present 0 -/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_Present in AQ_GlobalStandardDevicesInPackage_HHD */ -#define bits_AQ_GlobalStandardDevicesInPackage_HHD_phyXS_Present u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure phyXS_Present in AQ_GlobalStandardDevicesInPackage_HHD */ -#define word_AQ_GlobalStandardDevicesInPackage_HHD_phyXS_Present u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pcsPresent in AQ_GlobalStandardDevicesInPackage_HHD */ -#define AQ_GlobalStandardDevicesInPackage_HHD_pcsPresent 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pcsPresent in AQ_GlobalStandardDevicesInPackage_HHD */ -#define bits_AQ_GlobalStandardDevicesInPackage_HHD_pcsPresent u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pcsPresent in AQ_GlobalStandardDevicesInPackage_HHD */ -#define word_AQ_GlobalStandardDevicesInPackage_HHD_pcsPresent u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure wisPresent in AQ_GlobalStandardDevicesInPackage_HHD */ -#define AQ_GlobalStandardDevicesInPackage_HHD_wisPresent 0 -/*! \brief Preprocessor variable to relate field to bit position in structure wisPresent in AQ_GlobalStandardDevicesInPackage_HHD */ -#define bits_AQ_GlobalStandardDevicesInPackage_HHD_wisPresent u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure wisPresent in AQ_GlobalStandardDevicesInPackage_HHD */ -#define word_AQ_GlobalStandardDevicesInPackage_HHD_wisPresent u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pmaPresent in AQ_GlobalStandardDevicesInPackage_HHD */ -#define AQ_GlobalStandardDevicesInPackage_HHD_pmaPresent 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pmaPresent in AQ_GlobalStandardDevicesInPackage_HHD */ -#define bits_AQ_GlobalStandardDevicesInPackage_HHD_pmaPresent u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pmaPresent in AQ_GlobalStandardDevicesInPackage_HHD */ -#define word_AQ_GlobalStandardDevicesInPackage_HHD_pmaPresent u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure clause_22RegistersPresent in AQ_GlobalStandardDevicesInPackage_HHD */ -#define AQ_GlobalStandardDevicesInPackage_HHD_clause_22RegistersPresent 0 -/*! \brief Preprocessor variable to relate field to bit position in structure clause_22RegistersPresent in AQ_GlobalStandardDevicesInPackage_HHD */ -#define bits_AQ_GlobalStandardDevicesInPackage_HHD_clause_22RegistersPresent u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure clause_22RegistersPresent in AQ_GlobalStandardDevicesInPackage_HHD */ -#define word_AQ_GlobalStandardDevicesInPackage_HHD_clause_22RegistersPresent u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalStandardVendorDevicesInPackage_HHD */ -#define AQ_GlobalStandardVendorDevicesInPackage_HHD_baseRegisterAddress 0x0006 -/*! \brief MMD address of structure AQ_GlobalStandardVendorDevicesInPackage_HHD */ -#define AQ_GlobalStandardVendorDevicesInPackage_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure vendorSpecificDevice_2Present in AQ_GlobalStandardVendorDevicesInPackage_HHD */ -#define AQ_GlobalStandardVendorDevicesInPackage_HHD_vendorSpecificDevice_2Present 0 -/*! \brief Preprocessor variable to relate field to bit position in structure vendorSpecificDevice_2Present in AQ_GlobalStandardVendorDevicesInPackage_HHD */ -#define bits_AQ_GlobalStandardVendorDevicesInPackage_HHD_vendorSpecificDevice_2Present u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure vendorSpecificDevice_2Present in AQ_GlobalStandardVendorDevicesInPackage_HHD */ -#define word_AQ_GlobalStandardVendorDevicesInPackage_HHD_vendorSpecificDevice_2Present u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure vendorSpecificDevice_1Present in AQ_GlobalStandardVendorDevicesInPackage_HHD */ -#define AQ_GlobalStandardVendorDevicesInPackage_HHD_vendorSpecificDevice_1Present 0 -/*! \brief Preprocessor variable to relate field to bit position in structure vendorSpecificDevice_1Present in AQ_GlobalStandardVendorDevicesInPackage_HHD */ -#define bits_AQ_GlobalStandardVendorDevicesInPackage_HHD_vendorSpecificDevice_1Present u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure vendorSpecificDevice_1Present in AQ_GlobalStandardVendorDevicesInPackage_HHD */ -#define word_AQ_GlobalStandardVendorDevicesInPackage_HHD_vendorSpecificDevice_1Present u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure clause_22ExtensionPresent in AQ_GlobalStandardVendorDevicesInPackage_HHD */ -#define AQ_GlobalStandardVendorDevicesInPackage_HHD_clause_22ExtensionPresent 0 -/*! \brief Preprocessor variable to relate field to bit position in structure clause_22ExtensionPresent in AQ_GlobalStandardVendorDevicesInPackage_HHD */ -#define bits_AQ_GlobalStandardVendorDevicesInPackage_HHD_clause_22ExtensionPresent u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure clause_22ExtensionPresent in AQ_GlobalStandardVendorDevicesInPackage_HHD */ -#define word_AQ_GlobalStandardVendorDevicesInPackage_HHD_clause_22ExtensionPresent u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalStandardStatus_2_HHD */ -#define AQ_GlobalStandardStatus_2_HHD_baseRegisterAddress 0x0008 -/*! \brief MMD address of structure AQ_GlobalStandardStatus_2_HHD */ -#define AQ_GlobalStandardStatus_2_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure devicePresent in AQ_GlobalStandardStatus_2_HHD */ -#define AQ_GlobalStandardStatus_2_HHD_devicePresent 0 -/*! \brief Preprocessor variable to relate field to bit position in structure devicePresent in AQ_GlobalStandardStatus_2_HHD */ -#define bits_AQ_GlobalStandardStatus_2_HHD_devicePresent u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure devicePresent in AQ_GlobalStandardStatus_2_HHD */ -#define word_AQ_GlobalStandardStatus_2_HHD_devicePresent u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalStandardPackageIdentifier_HHD */ -#define AQ_GlobalStandardPackageIdentifier_HHD_baseRegisterAddress 0x000E -/*! \brief MMD address of structure AQ_GlobalStandardPackageIdentifier_HHD */ -#define AQ_GlobalStandardPackageIdentifier_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure packageIdMSW in AQ_GlobalStandardPackageIdentifier_HHD */ -#define AQ_GlobalStandardPackageIdentifier_HHD_packageIdMSW 0 -/*! \brief Preprocessor variable to relate field to bit position in structure packageIdMSW in AQ_GlobalStandardPackageIdentifier_HHD */ -#define bits_AQ_GlobalStandardPackageIdentifier_HHD_packageIdMSW u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure packageIdMSW in AQ_GlobalStandardPackageIdentifier_HHD */ -#define word_AQ_GlobalStandardPackageIdentifier_HHD_packageIdMSW u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure packageIdLSW in AQ_GlobalStandardPackageIdentifier_HHD */ -#define AQ_GlobalStandardPackageIdentifier_HHD_packageIdLSW 1 -/*! \brief Preprocessor variable to relate field to bit position in structure packageIdLSW in AQ_GlobalStandardPackageIdentifier_HHD */ -#define bits_AQ_GlobalStandardPackageIdentifier_HHD_packageIdLSW u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure packageIdLSW in AQ_GlobalStandardPackageIdentifier_HHD */ -#define word_AQ_GlobalStandardPackageIdentifier_HHD_packageIdLSW u1.word_1 - -/*! \brief Base register address of structure AQ_GlobalFirmwareID_HHD */ -#define AQ_GlobalFirmwareID_HHD_baseRegisterAddress 0x0020 -/*! \brief MMD address of structure AQ_GlobalFirmwareID_HHD */ -#define AQ_GlobalFirmwareID_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure firmwareMajorRevisionNumber in AQ_GlobalFirmwareID_HHD */ -#define AQ_GlobalFirmwareID_HHD_firmwareMajorRevisionNumber 0 -/*! \brief Preprocessor variable to relate field to bit position in structure firmwareMajorRevisionNumber in AQ_GlobalFirmwareID_HHD */ -#define bits_AQ_GlobalFirmwareID_HHD_firmwareMajorRevisionNumber u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure firmwareMajorRevisionNumber in AQ_GlobalFirmwareID_HHD */ -#define word_AQ_GlobalFirmwareID_HHD_firmwareMajorRevisionNumber u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure firmwareMinorRevisionNumber in AQ_GlobalFirmwareID_HHD */ -#define AQ_GlobalFirmwareID_HHD_firmwareMinorRevisionNumber 0 -/*! \brief Preprocessor variable to relate field to bit position in structure firmwareMinorRevisionNumber in AQ_GlobalFirmwareID_HHD */ -#define bits_AQ_GlobalFirmwareID_HHD_firmwareMinorRevisionNumber u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure firmwareMinorRevisionNumber in AQ_GlobalFirmwareID_HHD */ -#define word_AQ_GlobalFirmwareID_HHD_firmwareMinorRevisionNumber u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalNvrInterface_HHD */ -#define AQ_GlobalNvrInterface_HHD_baseRegisterAddress 0x0100 -/*! \brief MMD address of structure AQ_GlobalNvrInterface_HHD */ -#define AQ_GlobalNvrInterface_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure nvrExecuteOperation in AQ_GlobalNvrInterface_HHD */ -#define AQ_GlobalNvrInterface_HHD_nvrExecuteOperation 0 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrExecuteOperation in AQ_GlobalNvrInterface_HHD */ -#define bits_AQ_GlobalNvrInterface_HHD_nvrExecuteOperation u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure nvrExecuteOperation in AQ_GlobalNvrInterface_HHD */ -#define word_AQ_GlobalNvrInterface_HHD_nvrExecuteOperation u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure nvrWriteMode in AQ_GlobalNvrInterface_HHD */ -#define AQ_GlobalNvrInterface_HHD_nvrWriteMode 0 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrWriteMode in AQ_GlobalNvrInterface_HHD */ -#define bits_AQ_GlobalNvrInterface_HHD_nvrWriteMode u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure nvrWriteMode in AQ_GlobalNvrInterface_HHD */ -#define word_AQ_GlobalNvrInterface_HHD_nvrWriteMode u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure freezeNvrCrc in AQ_GlobalNvrInterface_HHD */ -#define AQ_GlobalNvrInterface_HHD_freezeNvrCrc 0 -/*! \brief Preprocessor variable to relate field to bit position in structure freezeNvrCrc in AQ_GlobalNvrInterface_HHD */ -#define bits_AQ_GlobalNvrInterface_HHD_freezeNvrCrc u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure freezeNvrCrc in AQ_GlobalNvrInterface_HHD */ -#define word_AQ_GlobalNvrInterface_HHD_freezeNvrCrc u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure resetNvrCrc in AQ_GlobalNvrInterface_HHD */ -#define AQ_GlobalNvrInterface_HHD_resetNvrCrc 0 -/*! \brief Preprocessor variable to relate field to bit position in structure resetNvrCrc in AQ_GlobalNvrInterface_HHD */ -#define bits_AQ_GlobalNvrInterface_HHD_resetNvrCrc u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure resetNvrCrc in AQ_GlobalNvrInterface_HHD */ -#define word_AQ_GlobalNvrInterface_HHD_resetNvrCrc u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure nvrBurst in AQ_GlobalNvrInterface_HHD */ -#define AQ_GlobalNvrInterface_HHD_nvrBurst 0 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrBurst in AQ_GlobalNvrInterface_HHD */ -#define bits_AQ_GlobalNvrInterface_HHD_nvrBurst u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure nvrBurst in AQ_GlobalNvrInterface_HHD */ -#define word_AQ_GlobalNvrInterface_HHD_nvrBurst u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure nvrBusy in AQ_GlobalNvrInterface_HHD */ -#define AQ_GlobalNvrInterface_HHD_nvrBusy 0 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrBusy in AQ_GlobalNvrInterface_HHD */ -#define bits_AQ_GlobalNvrInterface_HHD_nvrBusy u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure nvrBusy in AQ_GlobalNvrInterface_HHD */ -#define word_AQ_GlobalNvrInterface_HHD_nvrBusy u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure nvrOpcode in AQ_GlobalNvrInterface_HHD */ -#define AQ_GlobalNvrInterface_HHD_nvrOpcode 0 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrOpcode in AQ_GlobalNvrInterface_HHD */ -#define bits_AQ_GlobalNvrInterface_HHD_nvrOpcode u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure nvrOpcode in AQ_GlobalNvrInterface_HHD */ -#define word_AQ_GlobalNvrInterface_HHD_nvrOpcode u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure nvrMailboxCrc in AQ_GlobalNvrInterface_HHD */ -#define AQ_GlobalNvrInterface_HHD_nvrMailboxCrc 1 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrMailboxCrc in AQ_GlobalNvrInterface_HHD */ -#define bits_AQ_GlobalNvrInterface_HHD_nvrMailboxCrc u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure nvrMailboxCrc in AQ_GlobalNvrInterface_HHD */ -#define word_AQ_GlobalNvrInterface_HHD_nvrMailboxCrc u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure nvrAddressMSW in AQ_GlobalNvrInterface_HHD */ -#define AQ_GlobalNvrInterface_HHD_nvrAddressMSW 2 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrAddressMSW in AQ_GlobalNvrInterface_HHD */ -#define bits_AQ_GlobalNvrInterface_HHD_nvrAddressMSW u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure nvrAddressMSW in AQ_GlobalNvrInterface_HHD */ -#define word_AQ_GlobalNvrInterface_HHD_nvrAddressMSW u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure nvrAddressLSW in AQ_GlobalNvrInterface_HHD */ -#define AQ_GlobalNvrInterface_HHD_nvrAddressLSW 3 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrAddressLSW in AQ_GlobalNvrInterface_HHD */ -#define bits_AQ_GlobalNvrInterface_HHD_nvrAddressLSW u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure nvrAddressLSW in AQ_GlobalNvrInterface_HHD */ -#define word_AQ_GlobalNvrInterface_HHD_nvrAddressLSW u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure nvrDataMSW in AQ_GlobalNvrInterface_HHD */ -#define AQ_GlobalNvrInterface_HHD_nvrDataMSW 4 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrDataMSW in AQ_GlobalNvrInterface_HHD */ -#define bits_AQ_GlobalNvrInterface_HHD_nvrDataMSW u4.bits_4 -/*! \brief Preprocessor variable to relate field to word position in structure nvrDataMSW in AQ_GlobalNvrInterface_HHD */ -#define word_AQ_GlobalNvrInterface_HHD_nvrDataMSW u4.word_4 -/*! \brief Preprocessor variable to relate field to word number in structure nvrDataLSW in AQ_GlobalNvrInterface_HHD */ -#define AQ_GlobalNvrInterface_HHD_nvrDataLSW 5 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrDataLSW in AQ_GlobalNvrInterface_HHD */ -#define bits_AQ_GlobalNvrInterface_HHD_nvrDataLSW u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure nvrDataLSW in AQ_GlobalNvrInterface_HHD */ -#define word_AQ_GlobalNvrInterface_HHD_nvrDataLSW u5.word_5 - -/*! \brief Base register address of structure AQ_GlobalMailboxInterface_HHD */ -#define AQ_GlobalMailboxInterface_HHD_baseRegisterAddress 0x0200 -/*! \brief MMD address of structure AQ_GlobalMailboxInterface_HHD */ -#define AQ_GlobalMailboxInterface_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure upMailboxExecuteOperation in AQ_GlobalMailboxInterface_HHD */ -#define AQ_GlobalMailboxInterface_HHD_upMailboxExecuteOperation 0 -/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxExecuteOperation in AQ_GlobalMailboxInterface_HHD */ -#define bits_AQ_GlobalMailboxInterface_HHD_upMailboxExecuteOperation u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure upMailboxExecuteOperation in AQ_GlobalMailboxInterface_HHD */ -#define word_AQ_GlobalMailboxInterface_HHD_upMailboxExecuteOperation u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure upMailboxWriteMode in AQ_GlobalMailboxInterface_HHD */ -#define AQ_GlobalMailboxInterface_HHD_upMailboxWriteMode 0 -/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxWriteMode in AQ_GlobalMailboxInterface_HHD */ -#define bits_AQ_GlobalMailboxInterface_HHD_upMailboxWriteMode u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure upMailboxWriteMode in AQ_GlobalMailboxInterface_HHD */ -#define word_AQ_GlobalMailboxInterface_HHD_upMailboxWriteMode u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure resetUpMailboxCrc in AQ_GlobalMailboxInterface_HHD */ -#define AQ_GlobalMailboxInterface_HHD_resetUpMailboxCrc 0 -/*! \brief Preprocessor variable to relate field to bit position in structure resetUpMailboxCrc in AQ_GlobalMailboxInterface_HHD */ -#define bits_AQ_GlobalMailboxInterface_HHD_resetUpMailboxCrc u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure resetUpMailboxCrc in AQ_GlobalMailboxInterface_HHD */ -#define word_AQ_GlobalMailboxInterface_HHD_resetUpMailboxCrc u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure upMailboxBusy in AQ_GlobalMailboxInterface_HHD */ -#define AQ_GlobalMailboxInterface_HHD_upMailboxBusy 0 -/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxBusy in AQ_GlobalMailboxInterface_HHD */ -#define bits_AQ_GlobalMailboxInterface_HHD_upMailboxBusy u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure upMailboxBusy in AQ_GlobalMailboxInterface_HHD */ -#define word_AQ_GlobalMailboxInterface_HHD_upMailboxBusy u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure upMailboxCrc in AQ_GlobalMailboxInterface_HHD */ -#define AQ_GlobalMailboxInterface_HHD_upMailboxCrc 1 -/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxCrc in AQ_GlobalMailboxInterface_HHD */ -#define bits_AQ_GlobalMailboxInterface_HHD_upMailboxCrc u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure upMailboxCrc in AQ_GlobalMailboxInterface_HHD */ -#define word_AQ_GlobalMailboxInterface_HHD_upMailboxCrc u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure upMailboxAddressMSW in AQ_GlobalMailboxInterface_HHD */ -#define AQ_GlobalMailboxInterface_HHD_upMailboxAddressMSW 2 -/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxAddressMSW in AQ_GlobalMailboxInterface_HHD */ -#define bits_AQ_GlobalMailboxInterface_HHD_upMailboxAddressMSW u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure upMailboxAddressMSW in AQ_GlobalMailboxInterface_HHD */ -#define word_AQ_GlobalMailboxInterface_HHD_upMailboxAddressMSW u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure upMailboxAddressLSW in AQ_GlobalMailboxInterface_HHD */ -#define AQ_GlobalMailboxInterface_HHD_upMailboxAddressLSW 3 -/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxAddressLSW in AQ_GlobalMailboxInterface_HHD */ -#define bits_AQ_GlobalMailboxInterface_HHD_upMailboxAddressLSW u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure upMailboxAddressLSW in AQ_GlobalMailboxInterface_HHD */ -#define word_AQ_GlobalMailboxInterface_HHD_upMailboxAddressLSW u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure upMailboxAddressLSW_Don_tCare in AQ_GlobalMailboxInterface_HHD */ -#define AQ_GlobalMailboxInterface_HHD_upMailboxAddressLSW_Don_tCare 3 -/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxAddressLSW_Don_tCare in AQ_GlobalMailboxInterface_HHD */ -#define bits_AQ_GlobalMailboxInterface_HHD_upMailboxAddressLSW_Don_tCare u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure upMailboxAddressLSW_Don_tCare in AQ_GlobalMailboxInterface_HHD */ -#define word_AQ_GlobalMailboxInterface_HHD_upMailboxAddressLSW_Don_tCare u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure upMailboxDataMSW in AQ_GlobalMailboxInterface_HHD */ -#define AQ_GlobalMailboxInterface_HHD_upMailboxDataMSW 4 -/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxDataMSW in AQ_GlobalMailboxInterface_HHD */ -#define bits_AQ_GlobalMailboxInterface_HHD_upMailboxDataMSW u4.bits_4 -/*! \brief Preprocessor variable to relate field to word position in structure upMailboxDataMSW in AQ_GlobalMailboxInterface_HHD */ -#define word_AQ_GlobalMailboxInterface_HHD_upMailboxDataMSW u4.word_4 -/*! \brief Preprocessor variable to relate field to word number in structure upMailboxDataLSW in AQ_GlobalMailboxInterface_HHD */ -#define AQ_GlobalMailboxInterface_HHD_upMailboxDataLSW 5 -/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxDataLSW in AQ_GlobalMailboxInterface_HHD */ -#define bits_AQ_GlobalMailboxInterface_HHD_upMailboxDataLSW u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure upMailboxDataLSW in AQ_GlobalMailboxInterface_HHD */ -#define word_AQ_GlobalMailboxInterface_HHD_upMailboxDataLSW u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure upMailboxCrcReadEnable in AQ_GlobalMailboxInterface_HHD */ -#define AQ_GlobalMailboxInterface_HHD_upMailboxCrcReadEnable 6 -/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxCrcReadEnable in AQ_GlobalMailboxInterface_HHD */ -#define bits_AQ_GlobalMailboxInterface_HHD_upMailboxCrcReadEnable u6.bits_6 -/*! \brief Preprocessor variable to relate field to word position in structure upMailboxCrcReadEnable in AQ_GlobalMailboxInterface_HHD */ -#define word_AQ_GlobalMailboxInterface_HHD_upMailboxCrcReadEnable u6.word_6 - -/*! \brief Base register address of structure AQ_GlobalMicroprocessorScratchPad_HHD */ -#define AQ_GlobalMicroprocessorScratchPad_HHD_baseRegisterAddress 0x0300 -/*! \brief MMD address of structure AQ_GlobalMicroprocessorScratchPad_HHD */ -#define AQ_GlobalMicroprocessorScratchPad_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure scratchPad_1 in AQ_GlobalMicroprocessorScratchPad_HHD */ -#define AQ_GlobalMicroprocessorScratchPad_HHD_scratchPad_1 0 -/*! \brief Preprocessor variable to relate field to bit position in structure scratchPad_1 in AQ_GlobalMicroprocessorScratchPad_HHD */ -#define bits_AQ_GlobalMicroprocessorScratchPad_HHD_scratchPad_1 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure scratchPad_1 in AQ_GlobalMicroprocessorScratchPad_HHD */ -#define word_AQ_GlobalMicroprocessorScratchPad_HHD_scratchPad_1 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure scratchPad_2 in AQ_GlobalMicroprocessorScratchPad_HHD */ -#define AQ_GlobalMicroprocessorScratchPad_HHD_scratchPad_2 1 -/*! \brief Preprocessor variable to relate field to bit position in structure scratchPad_2 in AQ_GlobalMicroprocessorScratchPad_HHD */ -#define bits_AQ_GlobalMicroprocessorScratchPad_HHD_scratchPad_2 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure scratchPad_2 in AQ_GlobalMicroprocessorScratchPad_HHD */ -#define word_AQ_GlobalMicroprocessorScratchPad_HHD_scratchPad_2 u1.word_1 - -/*! \brief Base register address of structure AQ_MssEgressControlRegister_HHD */ -#define AQ_MssEgressControlRegister_HHD_baseRegisterAddress 0x5002 -/*! \brief MMD address of structure AQ_MssEgressControlRegister_HHD */ -#define AQ_MssEgressControlRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressEthertypeExplicitSectagLsb in AQ_MssEgressControlRegister_HHD */ -#define AQ_MssEgressControlRegister_HHD_mssEgressEthertypeExplicitSectagLsb 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressEthertypeExplicitSectagLsb in AQ_MssEgressControlRegister_HHD */ -#define bits_AQ_MssEgressControlRegister_HHD_mssEgressEthertypeExplicitSectagLsb u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressEthertypeExplicitSectagLsb in AQ_MssEgressControlRegister_HHD */ -#define word_AQ_MssEgressControlRegister_HHD_mssEgressEthertypeExplicitSectagLsb u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressClearGlobalTime in AQ_MssEgressControlRegister_HHD */ -#define AQ_MssEgressControlRegister_HHD_mssEgressClearGlobalTime 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressClearGlobalTime in AQ_MssEgressControlRegister_HHD */ -#define bits_AQ_MssEgressControlRegister_HHD_mssEgressClearGlobalTime u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressClearGlobalTime in AQ_MssEgressControlRegister_HHD */ -#define word_AQ_MssEgressControlRegister_HHD_mssEgressClearGlobalTime u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressClearCounter in AQ_MssEgressControlRegister_HHD */ -#define AQ_MssEgressControlRegister_HHD_mssEgressClearCounter 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressClearCounter in AQ_MssEgressControlRegister_HHD */ -#define bits_AQ_MssEgressControlRegister_HHD_mssEgressClearCounter u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressClearCounter in AQ_MssEgressControlRegister_HHD */ -#define word_AQ_MssEgressControlRegister_HHD_mssEgressClearCounter u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressHighPriority in AQ_MssEgressControlRegister_HHD */ -#define AQ_MssEgressControlRegister_HHD_mssEgressHighPriority 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressHighPriority in AQ_MssEgressControlRegister_HHD */ -#define bits_AQ_MssEgressControlRegister_HHD_mssEgressHighPriority u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressHighPriority in AQ_MssEgressControlRegister_HHD */ -#define word_AQ_MssEgressControlRegister_HHD_mssEgressHighPriority u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressIcvLsb_8BytesEnable in AQ_MssEgressControlRegister_HHD */ -#define AQ_MssEgressControlRegister_HHD_mssEgressIcvLsb_8BytesEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressIcvLsb_8BytesEnable in AQ_MssEgressControlRegister_HHD */ -#define bits_AQ_MssEgressControlRegister_HHD_mssEgressIcvLsb_8BytesEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressIcvLsb_8BytesEnable in AQ_MssEgressControlRegister_HHD */ -#define word_AQ_MssEgressControlRegister_HHD_mssEgressIcvLsb_8BytesEnable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressExternalClassificationEnable in AQ_MssEgressControlRegister_HHD */ -#define AQ_MssEgressControlRegister_HHD_mssEgressExternalClassificationEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressExternalClassificationEnable in AQ_MssEgressControlRegister_HHD */ -#define bits_AQ_MssEgressControlRegister_HHD_mssEgressExternalClassificationEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressExternalClassificationEnable in AQ_MssEgressControlRegister_HHD */ -#define word_AQ_MssEgressControlRegister_HHD_mssEgressExternalClassificationEnable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressExplicitSectagReportShortLength in AQ_MssEgressControlRegister_HHD */ -#define AQ_MssEgressControlRegister_HHD_mssEgressExplicitSectagReportShortLength 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressExplicitSectagReportShortLength in AQ_MssEgressControlRegister_HHD */ -#define bits_AQ_MssEgressControlRegister_HHD_mssEgressExplicitSectagReportShortLength u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressExplicitSectagReportShortLength in AQ_MssEgressControlRegister_HHD */ -#define word_AQ_MssEgressControlRegister_HHD_mssEgressExplicitSectagReportShortLength u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressDropInvalidSa_scPackets in AQ_MssEgressControlRegister_HHD */ -#define AQ_MssEgressControlRegister_HHD_mssEgressDropInvalidSa_scPackets 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressDropInvalidSa_scPackets in AQ_MssEgressControlRegister_HHD */ -#define bits_AQ_MssEgressControlRegister_HHD_mssEgressDropInvalidSa_scPackets u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressDropInvalidSa_scPackets in AQ_MssEgressControlRegister_HHD */ -#define word_AQ_MssEgressControlRegister_HHD_mssEgressDropInvalidSa_scPackets u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressUnmatchedUseSc_0 in AQ_MssEgressControlRegister_HHD */ -#define AQ_MssEgressControlRegister_HHD_mssEgressUnmatchedUseSc_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressUnmatchedUseSc_0 in AQ_MssEgressControlRegister_HHD */ -#define bits_AQ_MssEgressControlRegister_HHD_mssEgressUnmatchedUseSc_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressUnmatchedUseSc_0 in AQ_MssEgressControlRegister_HHD */ -#define word_AQ_MssEgressControlRegister_HHD_mssEgressUnmatchedUseSc_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgresssGcmTestMode in AQ_MssEgressControlRegister_HHD */ -#define AQ_MssEgressControlRegister_HHD_mssEgresssGcmTestMode 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgresssGcmTestMode in AQ_MssEgressControlRegister_HHD */ -#define bits_AQ_MssEgressControlRegister_HHD_mssEgresssGcmTestMode u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgresssGcmTestMode in AQ_MssEgressControlRegister_HHD */ -#define word_AQ_MssEgressControlRegister_HHD_mssEgresssGcmTestMode u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressGcmStart in AQ_MssEgressControlRegister_HHD */ -#define AQ_MssEgressControlRegister_HHD_mssEgressGcmStart 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressGcmStart in AQ_MssEgressControlRegister_HHD */ -#define bits_AQ_MssEgressControlRegister_HHD_mssEgressGcmStart u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressGcmStart in AQ_MssEgressControlRegister_HHD */ -#define word_AQ_MssEgressControlRegister_HHD_mssEgressGcmStart u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressDropEgprcLutMiss in AQ_MssEgressControlRegister_HHD */ -#define AQ_MssEgressControlRegister_HHD_mssEgressDropEgprcLutMiss 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressDropEgprcLutMiss in AQ_MssEgressControlRegister_HHD */ -#define bits_AQ_MssEgressControlRegister_HHD_mssEgressDropEgprcLutMiss u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressDropEgprcLutMiss in AQ_MssEgressControlRegister_HHD */ -#define word_AQ_MssEgressControlRegister_HHD_mssEgressDropEgprcLutMiss u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressDropKayPacket in AQ_MssEgressControlRegister_HHD */ -#define AQ_MssEgressControlRegister_HHD_mssEgressDropKayPacket 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressDropKayPacket in AQ_MssEgressControlRegister_HHD */ -#define bits_AQ_MssEgressControlRegister_HHD_mssEgressDropKayPacket u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressDropKayPacket in AQ_MssEgressControlRegister_HHD */ -#define word_AQ_MssEgressControlRegister_HHD_mssEgressDropKayPacket u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSoftReset in AQ_MssEgressControlRegister_HHD */ -#define AQ_MssEgressControlRegister_HHD_mssEgressSoftReset 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSoftReset in AQ_MssEgressControlRegister_HHD */ -#define bits_AQ_MssEgressControlRegister_HHD_mssEgressSoftReset u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSoftReset in AQ_MssEgressControlRegister_HHD */ -#define word_AQ_MssEgressControlRegister_HHD_mssEgressSoftReset u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressEthertypeExplicitSectagMsb in AQ_MssEgressControlRegister_HHD */ -#define AQ_MssEgressControlRegister_HHD_mssEgressEthertypeExplicitSectagMsb 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressEthertypeExplicitSectagMsb in AQ_MssEgressControlRegister_HHD */ -#define bits_AQ_MssEgressControlRegister_HHD_mssEgressEthertypeExplicitSectagMsb u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressEthertypeExplicitSectagMsb in AQ_MssEgressControlRegister_HHD */ -#define word_AQ_MssEgressControlRegister_HHD_mssEgressEthertypeExplicitSectagMsb u1.word_1 - -/*! \brief Base register address of structure AQ_MssEgressVlanTpid_0Register_HHD */ -#define AQ_MssEgressVlanTpid_0Register_HHD_baseRegisterAddress 0x5008 -/*! \brief MMD address of structure AQ_MssEgressVlanTpid_0Register_HHD */ -#define AQ_MssEgressVlanTpid_0Register_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressVlanStagTpid in AQ_MssEgressVlanTpid_0Register_HHD */ -#define AQ_MssEgressVlanTpid_0Register_HHD_mssEgressVlanStagTpid 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressVlanStagTpid in AQ_MssEgressVlanTpid_0Register_HHD */ -#define bits_AQ_MssEgressVlanTpid_0Register_HHD_mssEgressVlanStagTpid u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressVlanStagTpid in AQ_MssEgressVlanTpid_0Register_HHD */ -#define word_AQ_MssEgressVlanTpid_0Register_HHD_mssEgressVlanStagTpid u0.word_0 - -/*! \brief Base register address of structure AQ_MssEgressVlanTpid_1Register_HHD */ -#define AQ_MssEgressVlanTpid_1Register_HHD_baseRegisterAddress 0x500A -/*! \brief MMD address of structure AQ_MssEgressVlanTpid_1Register_HHD */ -#define AQ_MssEgressVlanTpid_1Register_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressVlanQtagTpid in AQ_MssEgressVlanTpid_1Register_HHD */ -#define AQ_MssEgressVlanTpid_1Register_HHD_mssEgressVlanQtagTpid 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressVlanQtagTpid in AQ_MssEgressVlanTpid_1Register_HHD */ -#define bits_AQ_MssEgressVlanTpid_1Register_HHD_mssEgressVlanQtagTpid u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressVlanQtagTpid in AQ_MssEgressVlanTpid_1Register_HHD */ -#define word_AQ_MssEgressVlanTpid_1Register_HHD_mssEgressVlanQtagTpid u0.word_0 - -/*! \brief Base register address of structure AQ_MssEgressVlanControlRegister_HHD */ -#define AQ_MssEgressVlanControlRegister_HHD_baseRegisterAddress 0x500C -/*! \brief MMD address of structure AQ_MssEgressVlanControlRegister_HHD */ -#define AQ_MssEgressVlanControlRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressVlanUpMapTable in AQ_MssEgressVlanControlRegister_HHD */ -#define AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanUpMapTable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressVlanUpMapTable in AQ_MssEgressVlanControlRegister_HHD */ -#define bits_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanUpMapTable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressVlanUpMapTable in AQ_MssEgressVlanControlRegister_HHD */ -#define word_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanUpMapTable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressVlanQtagParseEnable in AQ_MssEgressVlanControlRegister_HHD */ -#define AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanQtagParseEnable 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressVlanQtagParseEnable in AQ_MssEgressVlanControlRegister_HHD */ -#define bits_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanQtagParseEnable u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressVlanQtagParseEnable in AQ_MssEgressVlanControlRegister_HHD */ -#define word_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanQtagParseEnable u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressVlanStagParseEnable in AQ_MssEgressVlanControlRegister_HHD */ -#define AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanStagParseEnable 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressVlanStagParseEnable in AQ_MssEgressVlanControlRegister_HHD */ -#define bits_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanStagParseEnable u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressVlanStagParseEnable in AQ_MssEgressVlanControlRegister_HHD */ -#define word_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanStagParseEnable u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressVlanQinqParseEnable in AQ_MssEgressVlanControlRegister_HHD */ -#define AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanQinqParseEnable 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressVlanQinqParseEnable in AQ_MssEgressVlanControlRegister_HHD */ -#define bits_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanQinqParseEnable u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressVlanQinqParseEnable in AQ_MssEgressVlanControlRegister_HHD */ -#define word_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanQinqParseEnable u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressVlanQtagUpParseEnable in AQ_MssEgressVlanControlRegister_HHD */ -#define AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanQtagUpParseEnable 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressVlanQtagUpParseEnable in AQ_MssEgressVlanControlRegister_HHD */ -#define bits_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanQtagUpParseEnable u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressVlanQtagUpParseEnable in AQ_MssEgressVlanControlRegister_HHD */ -#define word_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanQtagUpParseEnable u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressVlanStagUpParseEnable in AQ_MssEgressVlanControlRegister_HHD */ -#define AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanStagUpParseEnable 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressVlanStagUpParseEnable in AQ_MssEgressVlanControlRegister_HHD */ -#define bits_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanStagUpParseEnable u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressVlanStagUpParseEnable in AQ_MssEgressVlanControlRegister_HHD */ -#define word_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanStagUpParseEnable u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressVlanUpDefault in AQ_MssEgressVlanControlRegister_HHD */ -#define AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanUpDefault 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressVlanUpDefault in AQ_MssEgressVlanControlRegister_HHD */ -#define bits_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanUpDefault u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressVlanUpDefault in AQ_MssEgressVlanControlRegister_HHD */ -#define word_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanUpDefault u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressVlanUpMapTableMSW in AQ_MssEgressVlanControlRegister_HHD */ -#define AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanUpMapTableMSW 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressVlanUpMapTableMSW in AQ_MssEgressVlanControlRegister_HHD */ -#define bits_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanUpMapTableMSW u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressVlanUpMapTableMSW in AQ_MssEgressVlanControlRegister_HHD */ -#define word_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanUpMapTableMSW u1.word_1 - -/*! \brief Base register address of structure AQ_MssEgressPnControlRegister_HHD */ -#define AQ_MssEgressPnControlRegister_HHD_baseRegisterAddress 0x500E -/*! \brief MMD address of structure AQ_MssEgressPnControlRegister_HHD */ -#define AQ_MssEgressPnControlRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaPnThresholdLSW in AQ_MssEgressPnControlRegister_HHD */ -#define AQ_MssEgressPnControlRegister_HHD_mssEgressSaPnThresholdLSW 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaPnThresholdLSW in AQ_MssEgressPnControlRegister_HHD */ -#define bits_AQ_MssEgressPnControlRegister_HHD_mssEgressSaPnThresholdLSW u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaPnThresholdLSW in AQ_MssEgressPnControlRegister_HHD */ -#define word_AQ_MssEgressPnControlRegister_HHD_mssEgressSaPnThresholdLSW u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaPnThresholdMSW in AQ_MssEgressPnControlRegister_HHD */ -#define AQ_MssEgressPnControlRegister_HHD_mssEgressSaPnThresholdMSW 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaPnThresholdMSW in AQ_MssEgressPnControlRegister_HHD */ -#define bits_AQ_MssEgressPnControlRegister_HHD_mssEgressSaPnThresholdMSW u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaPnThresholdMSW in AQ_MssEgressPnControlRegister_HHD */ -#define word_AQ_MssEgressPnControlRegister_HHD_mssEgressSaPnThresholdMSW u1.word_1 - -/*! \brief Base register address of structure AQ_MssEgressMtuSizeControlRegister_HHD */ -#define AQ_MssEgressMtuSizeControlRegister_HHD_baseRegisterAddress 0x5010 -/*! \brief MMD address of structure AQ_MssEgressMtuSizeControlRegister_HHD */ -#define AQ_MssEgressMtuSizeControlRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressControlledPacketMtuSize in AQ_MssEgressMtuSizeControlRegister_HHD */ -#define AQ_MssEgressMtuSizeControlRegister_HHD_mssEgressControlledPacketMtuSize 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressControlledPacketMtuSize in AQ_MssEgressMtuSizeControlRegister_HHD */ -#define bits_AQ_MssEgressMtuSizeControlRegister_HHD_mssEgressControlledPacketMtuSize u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressControlledPacketMtuSize in AQ_MssEgressMtuSizeControlRegister_HHD */ -#define word_AQ_MssEgressMtuSizeControlRegister_HHD_mssEgressControlledPacketMtuSize u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressUncontrolledPacketMtuSize in AQ_MssEgressMtuSizeControlRegister_HHD */ -#define AQ_MssEgressMtuSizeControlRegister_HHD_mssEgressUncontrolledPacketMtuSize 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressUncontrolledPacketMtuSize in AQ_MssEgressMtuSizeControlRegister_HHD */ -#define bits_AQ_MssEgressMtuSizeControlRegister_HHD_mssEgressUncontrolledPacketMtuSize u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressUncontrolledPacketMtuSize in AQ_MssEgressMtuSizeControlRegister_HHD */ -#define word_AQ_MssEgressMtuSizeControlRegister_HHD_mssEgressUncontrolledPacketMtuSize u1.word_1 - -/*! \brief Base register address of structure AQ_MssEgressInterruptStatusRegister_HHD */ -#define AQ_MssEgressInterruptStatusRegister_HHD_baseRegisterAddress 0x505C -/*! \brief MMD address of structure AQ_MssEgressInterruptStatusRegister_HHD */ -#define AQ_MssEgressInterruptStatusRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressEccErrorInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ -#define AQ_MssEgressInterruptStatusRegister_HHD_mssEgressEccErrorInterrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressEccErrorInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ -#define bits_AQ_MssEgressInterruptStatusRegister_HHD_mssEgressEccErrorInterrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressEccErrorInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ -#define word_AQ_MssEgressInterruptStatusRegister_HHD_mssEgressEccErrorInterrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressMibSaturationInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ -#define AQ_MssEgressInterruptStatusRegister_HHD_mssEgressMibSaturationInterrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressMibSaturationInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ -#define bits_AQ_MssEgressInterruptStatusRegister_HHD_mssEgressMibSaturationInterrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressMibSaturationInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ -#define word_AQ_MssEgressInterruptStatusRegister_HHD_mssEgressMibSaturationInterrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaThresholdExpiredInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ -#define AQ_MssEgressInterruptStatusRegister_HHD_mssEgressSaThresholdExpiredInterrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaThresholdExpiredInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ -#define bits_AQ_MssEgressInterruptStatusRegister_HHD_mssEgressSaThresholdExpiredInterrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaThresholdExpiredInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ -#define word_AQ_MssEgressInterruptStatusRegister_HHD_mssEgressSaThresholdExpiredInterrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaExpiredInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ -#define AQ_MssEgressInterruptStatusRegister_HHD_mssEgressSaExpiredInterrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaExpiredInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ -#define bits_AQ_MssEgressInterruptStatusRegister_HHD_mssEgressSaExpiredInterrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaExpiredInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ -#define word_AQ_MssEgressInterruptStatusRegister_HHD_mssEgressSaExpiredInterrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressMasterInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ -#define AQ_MssEgressInterruptStatusRegister_HHD_mssEgressMasterInterrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressMasterInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ -#define bits_AQ_MssEgressInterruptStatusRegister_HHD_mssEgressMasterInterrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressMasterInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ -#define word_AQ_MssEgressInterruptStatusRegister_HHD_mssEgressMasterInterrupt u0.word_0 - -/*! \brief Base register address of structure AQ_MssEgressInterruptMaskRegister_HHD */ -#define AQ_MssEgressInterruptMaskRegister_HHD_baseRegisterAddress 0x505E -/*! \brief MMD address of structure AQ_MssEgressInterruptMaskRegister_HHD */ -#define AQ_MssEgressInterruptMaskRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressEccErrorInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ -#define AQ_MssEgressInterruptMaskRegister_HHD_mssEgressEccErrorInterruptEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressEccErrorInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ -#define bits_AQ_MssEgressInterruptMaskRegister_HHD_mssEgressEccErrorInterruptEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressEccErrorInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ -#define word_AQ_MssEgressInterruptMaskRegister_HHD_mssEgressEccErrorInterruptEnable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressMibSaturationInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ -#define AQ_MssEgressInterruptMaskRegister_HHD_mssEgressMibSaturationInterruptEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressMibSaturationInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ -#define bits_AQ_MssEgressInterruptMaskRegister_HHD_mssEgressMibSaturationInterruptEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressMibSaturationInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ -#define word_AQ_MssEgressInterruptMaskRegister_HHD_mssEgressMibSaturationInterruptEnable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaExpiredThresholdInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ -#define AQ_MssEgressInterruptMaskRegister_HHD_mssEgressSaExpiredThresholdInterruptEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaExpiredThresholdInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ -#define bits_AQ_MssEgressInterruptMaskRegister_HHD_mssEgressSaExpiredThresholdInterruptEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaExpiredThresholdInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ -#define word_AQ_MssEgressInterruptMaskRegister_HHD_mssEgressSaExpiredThresholdInterruptEnable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaExpiredInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ -#define AQ_MssEgressInterruptMaskRegister_HHD_mssEgressSaExpiredInterruptEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaExpiredInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ -#define bits_AQ_MssEgressInterruptMaskRegister_HHD_mssEgressSaExpiredInterruptEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaExpiredInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ -#define word_AQ_MssEgressInterruptMaskRegister_HHD_mssEgressSaExpiredInterruptEnable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressMasterInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ -#define AQ_MssEgressInterruptMaskRegister_HHD_mssEgressMasterInterruptEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressMasterInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ -#define bits_AQ_MssEgressInterruptMaskRegister_HHD_mssEgressMasterInterruptEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressMasterInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ -#define word_AQ_MssEgressInterruptMaskRegister_HHD_mssEgressMasterInterruptEnable u0.word_0 - -/*! \brief Base register address of structure AQ_MssEgressSaExpiredStatusRegister_HHD */ -#define AQ_MssEgressSaExpiredStatusRegister_HHD_baseRegisterAddress 0x5060 -/*! \brief MMD address of structure AQ_MssEgressSaExpiredStatusRegister_HHD */ -#define AQ_MssEgressSaExpiredStatusRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaExpiredLSW in AQ_MssEgressSaExpiredStatusRegister_HHD */ -#define AQ_MssEgressSaExpiredStatusRegister_HHD_mssEgressSaExpiredLSW 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaExpiredLSW in AQ_MssEgressSaExpiredStatusRegister_HHD */ -#define bits_AQ_MssEgressSaExpiredStatusRegister_HHD_mssEgressSaExpiredLSW u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaExpiredLSW in AQ_MssEgressSaExpiredStatusRegister_HHD */ -#define word_AQ_MssEgressSaExpiredStatusRegister_HHD_mssEgressSaExpiredLSW u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaExpiredMSW in AQ_MssEgressSaExpiredStatusRegister_HHD */ -#define AQ_MssEgressSaExpiredStatusRegister_HHD_mssEgressSaExpiredMSW 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaExpiredMSW in AQ_MssEgressSaExpiredStatusRegister_HHD */ -#define bits_AQ_MssEgressSaExpiredStatusRegister_HHD_mssEgressSaExpiredMSW u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaExpiredMSW in AQ_MssEgressSaExpiredStatusRegister_HHD */ -#define word_AQ_MssEgressSaExpiredStatusRegister_HHD_mssEgressSaExpiredMSW u1.word_1 - -/*! \brief Base register address of structure AQ_MssEgressSaThresholdExpiredStatusRegister_HHD */ -#define AQ_MssEgressSaThresholdExpiredStatusRegister_HHD_baseRegisterAddress 0x5062 -/*! \brief MMD address of structure AQ_MssEgressSaThresholdExpiredStatusRegister_HHD */ -#define AQ_MssEgressSaThresholdExpiredStatusRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaThresholdExpiredLSW in AQ_MssEgressSaThresholdExpiredStatusRegister_HHD */ -#define AQ_MssEgressSaThresholdExpiredStatusRegister_HHD_mssEgressSaThresholdExpiredLSW 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaThresholdExpiredLSW in AQ_MssEgressSaThresholdExpiredStatusRegister_HHD */ -#define bits_AQ_MssEgressSaThresholdExpiredStatusRegister_HHD_mssEgressSaThresholdExpiredLSW u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaThresholdExpiredLSW in AQ_MssEgressSaThresholdExpiredStatusRegister_HHD */ -#define word_AQ_MssEgressSaThresholdExpiredStatusRegister_HHD_mssEgressSaThresholdExpiredLSW u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaThresholdExpiredMSW in AQ_MssEgressSaThresholdExpiredStatusRegister_HHD */ -#define AQ_MssEgressSaThresholdExpiredStatusRegister_HHD_mssEgressSaThresholdExpiredMSW 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaThresholdExpiredMSW in AQ_MssEgressSaThresholdExpiredStatusRegister_HHD */ -#define bits_AQ_MssEgressSaThresholdExpiredStatusRegister_HHD_mssEgressSaThresholdExpiredMSW u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaThresholdExpiredMSW in AQ_MssEgressSaThresholdExpiredStatusRegister_HHD */ -#define word_AQ_MssEgressSaThresholdExpiredStatusRegister_HHD_mssEgressSaThresholdExpiredMSW u1.word_1 - -/*! \brief Base register address of structure AQ_MssEgressEccInterruptStatusRegister_HHD */ -#define AQ_MssEgressEccInterruptStatusRegister_HHD_baseRegisterAddress 0x5064 -/*! \brief MMD address of structure AQ_MssEgressEccInterruptStatusRegister_HHD */ -#define AQ_MssEgressEccInterruptStatusRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaEccErrorInterruptLSW in AQ_MssEgressEccInterruptStatusRegister_HHD */ -#define AQ_MssEgressEccInterruptStatusRegister_HHD_mssEgressSaEccErrorInterruptLSW 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaEccErrorInterruptLSW in AQ_MssEgressEccInterruptStatusRegister_HHD */ -#define bits_AQ_MssEgressEccInterruptStatusRegister_HHD_mssEgressSaEccErrorInterruptLSW u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaEccErrorInterruptLSW in AQ_MssEgressEccInterruptStatusRegister_HHD */ -#define word_AQ_MssEgressEccInterruptStatusRegister_HHD_mssEgressSaEccErrorInterruptLSW u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaEccErrorInterruptMSW in AQ_MssEgressEccInterruptStatusRegister_HHD */ -#define AQ_MssEgressEccInterruptStatusRegister_HHD_mssEgressSaEccErrorInterruptMSW 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaEccErrorInterruptMSW in AQ_MssEgressEccInterruptStatusRegister_HHD */ -#define bits_AQ_MssEgressEccInterruptStatusRegister_HHD_mssEgressSaEccErrorInterruptMSW u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaEccErrorInterruptMSW in AQ_MssEgressEccInterruptStatusRegister_HHD */ -#define word_AQ_MssEgressEccInterruptStatusRegister_HHD_mssEgressSaEccErrorInterruptMSW u1.word_1 - -/*! \brief Base register address of structure AQ_MssEgressLutAddressControlRegister_HHD */ -#define AQ_MssEgressLutAddressControlRegister_HHD_baseRegisterAddress 0x5080 -/*! \brief MMD address of structure AQ_MssEgressLutAddressControlRegister_HHD */ -#define AQ_MssEgressLutAddressControlRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutSelect in AQ_MssEgressLutAddressControlRegister_HHD */ -#define AQ_MssEgressLutAddressControlRegister_HHD_mssEgressLutSelect 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutSelect in AQ_MssEgressLutAddressControlRegister_HHD */ -#define bits_AQ_MssEgressLutAddressControlRegister_HHD_mssEgressLutSelect u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutSelect in AQ_MssEgressLutAddressControlRegister_HHD */ -#define word_AQ_MssEgressLutAddressControlRegister_HHD_mssEgressLutSelect u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutAddress in AQ_MssEgressLutAddressControlRegister_HHD */ -#define AQ_MssEgressLutAddressControlRegister_HHD_mssEgressLutAddress 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutAddress in AQ_MssEgressLutAddressControlRegister_HHD */ -#define bits_AQ_MssEgressLutAddressControlRegister_HHD_mssEgressLutAddress u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutAddress in AQ_MssEgressLutAddressControlRegister_HHD */ -#define word_AQ_MssEgressLutAddressControlRegister_HHD_mssEgressLutAddress u0.word_0 - -/*! \brief Base register address of structure AQ_MssEgressLutControlRegister_HHD */ -#define AQ_MssEgressLutControlRegister_HHD_baseRegisterAddress 0x5081 -/*! \brief MMD address of structure AQ_MssEgressLutControlRegister_HHD */ -#define AQ_MssEgressLutControlRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutWrite in AQ_MssEgressLutControlRegister_HHD */ -#define AQ_MssEgressLutControlRegister_HHD_mssEgressLutWrite 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutWrite in AQ_MssEgressLutControlRegister_HHD */ -#define bits_AQ_MssEgressLutControlRegister_HHD_mssEgressLutWrite u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutWrite in AQ_MssEgressLutControlRegister_HHD */ -#define word_AQ_MssEgressLutControlRegister_HHD_mssEgressLutWrite u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutRead in AQ_MssEgressLutControlRegister_HHD */ -#define AQ_MssEgressLutControlRegister_HHD_mssEgressLutRead 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutRead in AQ_MssEgressLutControlRegister_HHD */ -#define bits_AQ_MssEgressLutControlRegister_HHD_mssEgressLutRead u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutRead in AQ_MssEgressLutControlRegister_HHD */ -#define word_AQ_MssEgressLutControlRegister_HHD_mssEgressLutRead u0.word_0 - -/*! \brief Base register address of structure AQ_MssEgressLutDataControlRegister_HHD */ -#define AQ_MssEgressLutDataControlRegister_HHD_baseRegisterAddress 0x50A0 -/*! \brief MMD address of structure AQ_MssEgressLutDataControlRegister_HHD */ -#define AQ_MssEgressLutDataControlRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_0 in AQ_MssEgressLutDataControlRegister_HHD */ -#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_0 in AQ_MssEgressLutDataControlRegister_HHD */ -#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_0 in AQ_MssEgressLutDataControlRegister_HHD */ -#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_1 in AQ_MssEgressLutDataControlRegister_HHD */ -#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_1 in AQ_MssEgressLutDataControlRegister_HHD */ -#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_1 in AQ_MssEgressLutDataControlRegister_HHD */ -#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_1 u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_2 in AQ_MssEgressLutDataControlRegister_HHD */ -#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_2 2 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_2 in AQ_MssEgressLutDataControlRegister_HHD */ -#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_2 u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_2 in AQ_MssEgressLutDataControlRegister_HHD */ -#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_2 u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_3 in AQ_MssEgressLutDataControlRegister_HHD */ -#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_3 3 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_3 in AQ_MssEgressLutDataControlRegister_HHD */ -#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_3 u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_3 in AQ_MssEgressLutDataControlRegister_HHD */ -#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_3 u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_4 in AQ_MssEgressLutDataControlRegister_HHD */ -#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_4 4 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_4 in AQ_MssEgressLutDataControlRegister_HHD */ -#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_4 u4.bits_4 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_4 in AQ_MssEgressLutDataControlRegister_HHD */ -#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_4 u4.word_4 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_5 in AQ_MssEgressLutDataControlRegister_HHD */ -#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_5 5 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_5 in AQ_MssEgressLutDataControlRegister_HHD */ -#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_5 u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_5 in AQ_MssEgressLutDataControlRegister_HHD */ -#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_5 u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_6 in AQ_MssEgressLutDataControlRegister_HHD */ -#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_6 6 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_6 in AQ_MssEgressLutDataControlRegister_HHD */ -#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_6 u6.bits_6 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_6 in AQ_MssEgressLutDataControlRegister_HHD */ -#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_6 u6.word_6 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_7 in AQ_MssEgressLutDataControlRegister_HHD */ -#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_7 7 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_7 in AQ_MssEgressLutDataControlRegister_HHD */ -#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_7 u7.bits_7 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_7 in AQ_MssEgressLutDataControlRegister_HHD */ -#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_7 u7.word_7 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_8 in AQ_MssEgressLutDataControlRegister_HHD */ -#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_8 8 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_8 in AQ_MssEgressLutDataControlRegister_HHD */ -#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_8 u8.bits_8 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_8 in AQ_MssEgressLutDataControlRegister_HHD */ -#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_8 u8.word_8 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_9 in AQ_MssEgressLutDataControlRegister_HHD */ -#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_9 9 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_9 in AQ_MssEgressLutDataControlRegister_HHD */ -#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_9 u9.bits_9 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_9 in AQ_MssEgressLutDataControlRegister_HHD */ -#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_9 u9.word_9 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_10 in AQ_MssEgressLutDataControlRegister_HHD */ -#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_10 10 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_10 in AQ_MssEgressLutDataControlRegister_HHD */ -#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_10 u10.bits_10 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_10 in AQ_MssEgressLutDataControlRegister_HHD */ -#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_10 u10.word_10 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_11 in AQ_MssEgressLutDataControlRegister_HHD */ -#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_11 11 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_11 in AQ_MssEgressLutDataControlRegister_HHD */ -#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_11 u11.bits_11 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_11 in AQ_MssEgressLutDataControlRegister_HHD */ -#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_11 u11.word_11 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_12 in AQ_MssEgressLutDataControlRegister_HHD */ -#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_12 12 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_12 in AQ_MssEgressLutDataControlRegister_HHD */ -#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_12 u12.bits_12 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_12 in AQ_MssEgressLutDataControlRegister_HHD */ -#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_12 u12.word_12 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_13 in AQ_MssEgressLutDataControlRegister_HHD */ -#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_13 13 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_13 in AQ_MssEgressLutDataControlRegister_HHD */ -#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_13 u13.bits_13 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_13 in AQ_MssEgressLutDataControlRegister_HHD */ -#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_13 u13.word_13 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_14 in AQ_MssEgressLutDataControlRegister_HHD */ -#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_14 14 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_14 in AQ_MssEgressLutDataControlRegister_HHD */ -#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_14 u14.bits_14 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_14 in AQ_MssEgressLutDataControlRegister_HHD */ -#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_14 u14.word_14 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_15 in AQ_MssEgressLutDataControlRegister_HHD */ -#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_15 15 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_15 in AQ_MssEgressLutDataControlRegister_HHD */ -#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_15 u15.bits_15 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_15 in AQ_MssEgressLutDataControlRegister_HHD */ -#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_15 u15.word_15 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_16 in AQ_MssEgressLutDataControlRegister_HHD */ -#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_16 16 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_16 in AQ_MssEgressLutDataControlRegister_HHD */ -#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_16 u16.bits_16 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_16 in AQ_MssEgressLutDataControlRegister_HHD */ -#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_16 u16.word_16 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_17 in AQ_MssEgressLutDataControlRegister_HHD */ -#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_17 17 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_17 in AQ_MssEgressLutDataControlRegister_HHD */ -#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_17 u17.bits_17 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_17 in AQ_MssEgressLutDataControlRegister_HHD */ -#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_17 u17.word_17 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_18 in AQ_MssEgressLutDataControlRegister_HHD */ -#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_18 18 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_18 in AQ_MssEgressLutDataControlRegister_HHD */ -#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_18 u18.bits_18 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_18 in AQ_MssEgressLutDataControlRegister_HHD */ -#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_18 u18.word_18 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_19 in AQ_MssEgressLutDataControlRegister_HHD */ -#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_19 19 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_19 in AQ_MssEgressLutDataControlRegister_HHD */ -#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_19 u19.bits_19 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_19 in AQ_MssEgressLutDataControlRegister_HHD */ -#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_19 u19.word_19 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_20 in AQ_MssEgressLutDataControlRegister_HHD */ -#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_20 20 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_20 in AQ_MssEgressLutDataControlRegister_HHD */ -#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_20 u20.bits_20 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_20 in AQ_MssEgressLutDataControlRegister_HHD */ -#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_20 u20.word_20 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_21 in AQ_MssEgressLutDataControlRegister_HHD */ -#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_21 21 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_21 in AQ_MssEgressLutDataControlRegister_HHD */ -#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_21 u21.bits_21 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_21 in AQ_MssEgressLutDataControlRegister_HHD */ -#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_21 u21.word_21 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_22 in AQ_MssEgressLutDataControlRegister_HHD */ -#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_22 22 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_22 in AQ_MssEgressLutDataControlRegister_HHD */ -#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_22 u22.bits_22 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_22 in AQ_MssEgressLutDataControlRegister_HHD */ -#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_22 u22.word_22 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_23 in AQ_MssEgressLutDataControlRegister_HHD */ -#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_23 23 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_23 in AQ_MssEgressLutDataControlRegister_HHD */ -#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_23 u23.bits_23 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_23 in AQ_MssEgressLutDataControlRegister_HHD */ -#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_23 u23.word_23 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_24 in AQ_MssEgressLutDataControlRegister_HHD */ -#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_24 24 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_24 in AQ_MssEgressLutDataControlRegister_HHD */ -#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_24 u24.bits_24 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_24 in AQ_MssEgressLutDataControlRegister_HHD */ -#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_24 u24.word_24 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_25 in AQ_MssEgressLutDataControlRegister_HHD */ -#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_25 25 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_25 in AQ_MssEgressLutDataControlRegister_HHD */ -#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_25 u25.bits_25 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_25 in AQ_MssEgressLutDataControlRegister_HHD */ -#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_25 u25.word_25 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_26 in AQ_MssEgressLutDataControlRegister_HHD */ -#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_26 26 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_26 in AQ_MssEgressLutDataControlRegister_HHD */ -#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_26 u26.bits_26 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_26 in AQ_MssEgressLutDataControlRegister_HHD */ -#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_26 u26.word_26 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_27 in AQ_MssEgressLutDataControlRegister_HHD */ -#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_27 27 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_27 in AQ_MssEgressLutDataControlRegister_HHD */ -#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_27 u27.bits_27 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_27 in AQ_MssEgressLutDataControlRegister_HHD */ -#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_27 u27.word_27 - -/*! \brief Base register address of structure AQ_MsmSystemGeneralControlRegister_HHD */ -#define AQ_MsmSystemGeneralControlRegister_HHD_baseRegisterAddress 0x6004 -/*! \brief MMD address of structure AQ_MsmSystemGeneralControlRegister_HHD */ -#define AQ_MsmSystemGeneralControlRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemPhyTxEnable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPhyTxEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemPhyTxEnable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPhyTxEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemPhyTxEnable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPhyTxEnable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxErrorDiscard in AQ_MsmSystemGeneralControlRegister_HHD */ -#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemRxErrorDiscard 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxErrorDiscard in AQ_MsmSystemGeneralControlRegister_HHD */ -#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemRxErrorDiscard u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxErrorDiscard in AQ_MsmSystemGeneralControlRegister_HHD */ -#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemRxErrorDiscard u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemControlFrameEnable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemControlFrameEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemControlFrameEnable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemControlFrameEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemControlFrameEnable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemControlFrameEnable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemSoftReset in AQ_MsmSystemGeneralControlRegister_HHD */ -#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemSoftReset 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemSoftReset in AQ_MsmSystemGeneralControlRegister_HHD */ -#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemSoftReset u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemSoftReset in AQ_MsmSystemGeneralControlRegister_HHD */ -#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemSoftReset u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxPadEnable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxPadEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxPadEnable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxPadEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxPadEnable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxPadEnable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxCrcAppend in AQ_MsmSystemGeneralControlRegister_HHD */ -#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxCrcAppend 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxCrcAppend in AQ_MsmSystemGeneralControlRegister_HHD */ -#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxCrcAppend u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxCrcAppend in AQ_MsmSystemGeneralControlRegister_HHD */ -#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxCrcAppend u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxAddressInsertEnable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxAddressInsertEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxAddressInsertEnable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxAddressInsertEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxAddressInsertEnable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxAddressInsertEnable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemPauseIgnore in AQ_MsmSystemGeneralControlRegister_HHD */ -#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPauseIgnore 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemPauseIgnore in AQ_MsmSystemGeneralControlRegister_HHD */ -#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPauseIgnore u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemPauseIgnore in AQ_MsmSystemGeneralControlRegister_HHD */ -#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPauseIgnore u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemPauseForward in AQ_MsmSystemGeneralControlRegister_HHD */ -#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPauseForward 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemPauseForward in AQ_MsmSystemGeneralControlRegister_HHD */ -#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPauseForward u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemPauseForward in AQ_MsmSystemGeneralControlRegister_HHD */ -#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPauseForward u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemCrcForward in AQ_MsmSystemGeneralControlRegister_HHD */ -#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemCrcForward 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemCrcForward in AQ_MsmSystemGeneralControlRegister_HHD */ -#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemCrcForward u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemCrcForward in AQ_MsmSystemGeneralControlRegister_HHD */ -#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemCrcForward u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemPadEnable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPadEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemPadEnable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPadEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemPadEnable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPadEnable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemPromiscuousMode in AQ_MsmSystemGeneralControlRegister_HHD */ -#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPromiscuousMode 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemPromiscuousMode in AQ_MsmSystemGeneralControlRegister_HHD */ -#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPromiscuousMode u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemPromiscuousMode in AQ_MsmSystemGeneralControlRegister_HHD */ -#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPromiscuousMode u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemWanMode in AQ_MsmSystemGeneralControlRegister_HHD */ -#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemWanMode 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemWanMode in AQ_MsmSystemGeneralControlRegister_HHD */ -#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemWanMode u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemWanMode in AQ_MsmSystemGeneralControlRegister_HHD */ -#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemWanMode u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxEnable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemRxEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxEnable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemRxEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxEnable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemRxEnable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxEnable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxEnable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxEnable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxEnable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxLowPowerIdleEnable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxLowPowerIdleEnable 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxLowPowerIdleEnable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxLowPowerIdleEnable u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxLowPowerIdleEnable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxLowPowerIdleEnable u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemSfdCheckDisable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemSfdCheckDisable 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemSfdCheckDisable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemSfdCheckDisable u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemSfdCheckDisable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemSfdCheckDisable u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemPriorityFlowControlEnable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPriorityFlowControlEnable 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemPriorityFlowControlEnable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPriorityFlowControlEnable u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemPriorityFlowControlEnable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPriorityFlowControlEnable u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemIdleColumnCountExtend in AQ_MsmSystemGeneralControlRegister_HHD */ -#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemIdleColumnCountExtend 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemIdleColumnCountExtend in AQ_MsmSystemGeneralControlRegister_HHD */ -#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemIdleColumnCountExtend u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemIdleColumnCountExtend in AQ_MsmSystemGeneralControlRegister_HHD */ -#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemIdleColumnCountExtend u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemLengthCheckDisable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemLengthCheckDisable 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemLengthCheckDisable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemLengthCheckDisable u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemLengthCheckDisable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemLengthCheckDisable u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemForceSendIdle in AQ_MsmSystemGeneralControlRegister_HHD */ -#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemForceSendIdle 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemForceSendIdle in AQ_MsmSystemGeneralControlRegister_HHD */ -#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemForceSendIdle u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemForceSendIdle in AQ_MsmSystemGeneralControlRegister_HHD */ -#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemForceSendIdle u1.word_1 - -/*! \brief Base register address of structure AQ_MsmSystemFifoControlRegister_HHD */ -#define AQ_MsmSystemFifoControlRegister_HHD_baseRegisterAddress 0x600E -/*! \brief MMD address of structure AQ_MsmSystemFifoControlRegister_HHD */ -#define AQ_MsmSystemFifoControlRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxFifoFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ -#define AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoFullThreshold 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxFifoFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ -#define bits_AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoFullThreshold u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxFifoFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ -#define word_AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoFullThreshold u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxFifoEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ -#define AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoEmptyThreshold 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxFifoEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ -#define bits_AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoEmptyThreshold u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxFifoEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ -#define word_AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoEmptyThreshold u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxFifoFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ -#define AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoFullThreshold 2 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxFifoFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ -#define bits_AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoFullThreshold u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxFifoFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ -#define word_AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoFullThreshold u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxFifoEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ -#define AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoEmptyThreshold 3 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxFifoEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ -#define bits_AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoEmptyThreshold u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxFifoEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ -#define word_AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoEmptyThreshold u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxFifoAlmostFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ -#define AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoAlmostFullThreshold 4 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxFifoAlmostFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ -#define bits_AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoAlmostFullThreshold u4.bits_4 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxFifoAlmostFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ -#define word_AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoAlmostFullThreshold u4.word_4 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxFifoAlmostEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ -#define AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoAlmostEmptyThreshold 5 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxFifoAlmostEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ -#define bits_AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoAlmostEmptyThreshold u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxFifoAlmostEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ -#define word_AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoAlmostEmptyThreshold u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxFifoAlmostFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ -#define AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoAlmostFullThreshold 6 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxFifoAlmostFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ -#define bits_AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoAlmostFullThreshold u6.bits_6 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxFifoAlmostFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ -#define word_AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoAlmostFullThreshold u6.word_6 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxFifoAlmostEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ -#define AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoAlmostEmptyThreshold 7 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxFifoAlmostEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ -#define bits_AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoAlmostEmptyThreshold u7.bits_7 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxFifoAlmostEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ -#define word_AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoAlmostEmptyThreshold u7.word_7 - -/*! \brief Base register address of structure AQ_MsmSystemGeneralStatusRegister_HHD */ -#define AQ_MsmSystemGeneralStatusRegister_HHD_baseRegisterAddress 0x6020 -/*! \brief MMD address of structure AQ_MsmSystemGeneralStatusRegister_HHD */ -#define AQ_MsmSystemGeneralStatusRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxFifoEmpty in AQ_MsmSystemGeneralStatusRegister_HHD */ -#define AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemTxFifoEmpty 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxFifoEmpty in AQ_MsmSystemGeneralStatusRegister_HHD */ -#define bits_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemTxFifoEmpty u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxFifoEmpty in AQ_MsmSystemGeneralStatusRegister_HHD */ -#define word_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemTxFifoEmpty u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxLowPowerIdle in AQ_MsmSystemGeneralStatusRegister_HHD */ -#define AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemRxLowPowerIdle 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxLowPowerIdle in AQ_MsmSystemGeneralStatusRegister_HHD */ -#define bits_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemRxLowPowerIdle u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxLowPowerIdle in AQ_MsmSystemGeneralStatusRegister_HHD */ -#define word_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemRxLowPowerIdle u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTimestampAvailable in AQ_MsmSystemGeneralStatusRegister_HHD */ -#define AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemTimestampAvailable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTimestampAvailable in AQ_MsmSystemGeneralStatusRegister_HHD */ -#define bits_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemTimestampAvailable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTimestampAvailable in AQ_MsmSystemGeneralStatusRegister_HHD */ -#define word_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemTimestampAvailable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemPhyLossOfSignal in AQ_MsmSystemGeneralStatusRegister_HHD */ -#define AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemPhyLossOfSignal 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemPhyLossOfSignal in AQ_MsmSystemGeneralStatusRegister_HHD */ -#define bits_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemPhyLossOfSignal u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemPhyLossOfSignal in AQ_MsmSystemGeneralStatusRegister_HHD */ -#define word_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemPhyLossOfSignal u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxRemoteFault in AQ_MsmSystemGeneralStatusRegister_HHD */ -#define AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemRxRemoteFault 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxRemoteFault in AQ_MsmSystemGeneralStatusRegister_HHD */ -#define bits_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemRxRemoteFault u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxRemoteFault in AQ_MsmSystemGeneralStatusRegister_HHD */ -#define word_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemRxRemoteFault u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxLocalFault in AQ_MsmSystemGeneralStatusRegister_HHD */ -#define AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemRxLocalFault 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxLocalFault in AQ_MsmSystemGeneralStatusRegister_HHD */ -#define bits_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemRxLocalFault u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxLocalFault in AQ_MsmSystemGeneralStatusRegister_HHD */ -#define word_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemRxLocalFault u0.word_0 - -/*! \brief Base register address of structure AQ_MsmSystemTxIpgControlRegister_HHD */ -#define AQ_MsmSystemTxIpgControlRegister_HHD_baseRegisterAddress 0x6022 -/*! \brief MMD address of structure AQ_MsmSystemTxIpgControlRegister_HHD */ -#define AQ_MsmSystemTxIpgControlRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxIpgLength in AQ_MsmSystemTxIpgControlRegister_HHD */ -#define AQ_MsmSystemTxIpgControlRegister_HHD_msmSystemTxIpgLength 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxIpgLength in AQ_MsmSystemTxIpgControlRegister_HHD */ -#define bits_AQ_MsmSystemTxIpgControlRegister_HHD_msmSystemTxIpgLength u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxIpgLength in AQ_MsmSystemTxIpgControlRegister_HHD */ -#define word_AQ_MsmSystemTxIpgControlRegister_HHD_msmSystemTxIpgLength u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxIpgReserved in AQ_MsmSystemTxIpgControlRegister_HHD */ -#define AQ_MsmSystemTxIpgControlRegister_HHD_msmSystemTxIpgReserved 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxIpgReserved in AQ_MsmSystemTxIpgControlRegister_HHD */ -#define bits_AQ_MsmSystemTxIpgControlRegister_HHD_msmSystemTxIpgReserved u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxIpgReserved in AQ_MsmSystemTxIpgControlRegister_HHD */ -#define word_AQ_MsmSystemTxIpgControlRegister_HHD_msmSystemTxIpgReserved u1.word_1 - -/*! \brief Base register address of structure AQ_MsmSystemTxGoodFramesCounterRegister_HHD */ -#define AQ_MsmSystemTxGoodFramesCounterRegister_HHD_baseRegisterAddress 0x6040 -/*! \brief MMD address of structure AQ_MsmSystemTxGoodFramesCounterRegister_HHD */ -#define AQ_MsmSystemTxGoodFramesCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxGoodFramesCounter_0 in AQ_MsmSystemTxGoodFramesCounterRegister_HHD */ -#define AQ_MsmSystemTxGoodFramesCounterRegister_HHD_msmSystemTxGoodFramesCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxGoodFramesCounter_0 in AQ_MsmSystemTxGoodFramesCounterRegister_HHD */ -#define bits_AQ_MsmSystemTxGoodFramesCounterRegister_HHD_msmSystemTxGoodFramesCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxGoodFramesCounter_0 in AQ_MsmSystemTxGoodFramesCounterRegister_HHD */ -#define word_AQ_MsmSystemTxGoodFramesCounterRegister_HHD_msmSystemTxGoodFramesCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxGoodFramesCounter_1 in AQ_MsmSystemTxGoodFramesCounterRegister_HHD */ -#define AQ_MsmSystemTxGoodFramesCounterRegister_HHD_msmSystemTxGoodFramesCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxGoodFramesCounter_1 in AQ_MsmSystemTxGoodFramesCounterRegister_HHD */ -#define bits_AQ_MsmSystemTxGoodFramesCounterRegister_HHD_msmSystemTxGoodFramesCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxGoodFramesCounter_1 in AQ_MsmSystemTxGoodFramesCounterRegister_HHD */ -#define word_AQ_MsmSystemTxGoodFramesCounterRegister_HHD_msmSystemTxGoodFramesCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmSystemRxGoodFramesCounterRegister_HHD */ -#define AQ_MsmSystemRxGoodFramesCounterRegister_HHD_baseRegisterAddress 0x6044 -/*! \brief MMD address of structure AQ_MsmSystemRxGoodFramesCounterRegister_HHD */ -#define AQ_MsmSystemRxGoodFramesCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxGoodFramesCounter_0 in AQ_MsmSystemRxGoodFramesCounterRegister_HHD */ -#define AQ_MsmSystemRxGoodFramesCounterRegister_HHD_msmSystemRxGoodFramesCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxGoodFramesCounter_0 in AQ_MsmSystemRxGoodFramesCounterRegister_HHD */ -#define bits_AQ_MsmSystemRxGoodFramesCounterRegister_HHD_msmSystemRxGoodFramesCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxGoodFramesCounter_0 in AQ_MsmSystemRxGoodFramesCounterRegister_HHD */ -#define word_AQ_MsmSystemRxGoodFramesCounterRegister_HHD_msmSystemRxGoodFramesCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxGoodFramesCounter_1 in AQ_MsmSystemRxGoodFramesCounterRegister_HHD */ -#define AQ_MsmSystemRxGoodFramesCounterRegister_HHD_msmSystemRxGoodFramesCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxGoodFramesCounter_1 in AQ_MsmSystemRxGoodFramesCounterRegister_HHD */ -#define bits_AQ_MsmSystemRxGoodFramesCounterRegister_HHD_msmSystemRxGoodFramesCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxGoodFramesCounter_1 in AQ_MsmSystemRxGoodFramesCounterRegister_HHD */ -#define word_AQ_MsmSystemRxGoodFramesCounterRegister_HHD_msmSystemRxGoodFramesCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmSystemRxFcsErrorsCounterRegister_HHD */ -#define AQ_MsmSystemRxFcsErrorsCounterRegister_HHD_baseRegisterAddress 0x6048 -/*! \brief MMD address of structure AQ_MsmSystemRxFcsErrorsCounterRegister_HHD */ -#define AQ_MsmSystemRxFcsErrorsCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemFcsErrorCounter_0 in AQ_MsmSystemRxFcsErrorsCounterRegister_HHD */ -#define AQ_MsmSystemRxFcsErrorsCounterRegister_HHD_msmSystemFcsErrorCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemFcsErrorCounter_0 in AQ_MsmSystemRxFcsErrorsCounterRegister_HHD */ -#define bits_AQ_MsmSystemRxFcsErrorsCounterRegister_HHD_msmSystemFcsErrorCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemFcsErrorCounter_0 in AQ_MsmSystemRxFcsErrorsCounterRegister_HHD */ -#define word_AQ_MsmSystemRxFcsErrorsCounterRegister_HHD_msmSystemFcsErrorCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemFcsErrorCounter_1 in AQ_MsmSystemRxFcsErrorsCounterRegister_HHD */ -#define AQ_MsmSystemRxFcsErrorsCounterRegister_HHD_msmSystemFcsErrorCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemFcsErrorCounter_1 in AQ_MsmSystemRxFcsErrorsCounterRegister_HHD */ -#define bits_AQ_MsmSystemRxFcsErrorsCounterRegister_HHD_msmSystemFcsErrorCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemFcsErrorCounter_1 in AQ_MsmSystemRxFcsErrorsCounterRegister_HHD */ -#define word_AQ_MsmSystemRxFcsErrorsCounterRegister_HHD_msmSystemFcsErrorCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD */ -#define AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD_baseRegisterAddress 0x604C -/*! \brief MMD address of structure AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD */ -#define AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemAlignmentErrorCounter_0 in AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD */ -#define AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD_msmSystemAlignmentErrorCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemAlignmentErrorCounter_0 in AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD */ -#define bits_AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD_msmSystemAlignmentErrorCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemAlignmentErrorCounter_0 in AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD */ -#define word_AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD_msmSystemAlignmentErrorCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemAlignmentErrorCounter_1 in AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD */ -#define AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD_msmSystemAlignmentErrorCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemAlignmentErrorCounter_1 in AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD */ -#define bits_AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD_msmSystemAlignmentErrorCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemAlignmentErrorCounter_1 in AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD */ -#define word_AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD_msmSystemAlignmentErrorCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmSystemTxPauseFramesCounterRegister_HHD */ -#define AQ_MsmSystemTxPauseFramesCounterRegister_HHD_baseRegisterAddress 0x6050 -/*! \brief MMD address of structure AQ_MsmSystemTxPauseFramesCounterRegister_HHD */ -#define AQ_MsmSystemTxPauseFramesCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxPauseFramesCounter_0 in AQ_MsmSystemTxPauseFramesCounterRegister_HHD */ -#define AQ_MsmSystemTxPauseFramesCounterRegister_HHD_msmSystemTxPauseFramesCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxPauseFramesCounter_0 in AQ_MsmSystemTxPauseFramesCounterRegister_HHD */ -#define bits_AQ_MsmSystemTxPauseFramesCounterRegister_HHD_msmSystemTxPauseFramesCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxPauseFramesCounter_0 in AQ_MsmSystemTxPauseFramesCounterRegister_HHD */ -#define word_AQ_MsmSystemTxPauseFramesCounterRegister_HHD_msmSystemTxPauseFramesCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxPauseFramesCounter_1 in AQ_MsmSystemTxPauseFramesCounterRegister_HHD */ -#define AQ_MsmSystemTxPauseFramesCounterRegister_HHD_msmSystemTxPauseFramesCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxPauseFramesCounter_1 in AQ_MsmSystemTxPauseFramesCounterRegister_HHD */ -#define bits_AQ_MsmSystemTxPauseFramesCounterRegister_HHD_msmSystemTxPauseFramesCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxPauseFramesCounter_1 in AQ_MsmSystemTxPauseFramesCounterRegister_HHD */ -#define word_AQ_MsmSystemTxPauseFramesCounterRegister_HHD_msmSystemTxPauseFramesCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmSystemRxPauseFramesCounterRegister_HHD */ -#define AQ_MsmSystemRxPauseFramesCounterRegister_HHD_baseRegisterAddress 0x6054 -/*! \brief MMD address of structure AQ_MsmSystemRxPauseFramesCounterRegister_HHD */ -#define AQ_MsmSystemRxPauseFramesCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxPauseFramesCounter_0 in AQ_MsmSystemRxPauseFramesCounterRegister_HHD */ -#define AQ_MsmSystemRxPauseFramesCounterRegister_HHD_msmSystemRxPauseFramesCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxPauseFramesCounter_0 in AQ_MsmSystemRxPauseFramesCounterRegister_HHD */ -#define bits_AQ_MsmSystemRxPauseFramesCounterRegister_HHD_msmSystemRxPauseFramesCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxPauseFramesCounter_0 in AQ_MsmSystemRxPauseFramesCounterRegister_HHD */ -#define word_AQ_MsmSystemRxPauseFramesCounterRegister_HHD_msmSystemRxPauseFramesCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxPauseFramesCounter_1 in AQ_MsmSystemRxPauseFramesCounterRegister_HHD */ -#define AQ_MsmSystemRxPauseFramesCounterRegister_HHD_msmSystemRxPauseFramesCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxPauseFramesCounter_1 in AQ_MsmSystemRxPauseFramesCounterRegister_HHD */ -#define bits_AQ_MsmSystemRxPauseFramesCounterRegister_HHD_msmSystemRxPauseFramesCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxPauseFramesCounter_1 in AQ_MsmSystemRxPauseFramesCounterRegister_HHD */ -#define word_AQ_MsmSystemRxPauseFramesCounterRegister_HHD_msmSystemRxPauseFramesCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD */ -#define AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD_baseRegisterAddress 0x6058 -/*! \brief MMD address of structure AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD */ -#define AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxTooLongErrorsCounter_0 in AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD */ -#define AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD_msmSystemRxTooLongErrorsCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxTooLongErrorsCounter_0 in AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD */ -#define bits_AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD_msmSystemRxTooLongErrorsCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxTooLongErrorsCounter_0 in AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD */ -#define word_AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD_msmSystemRxTooLongErrorsCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxTooLongErrorsCounter_1 in AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD */ -#define AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD_msmSystemRxTooLongErrorsCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxTooLongErrorsCounter_1 in AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD */ -#define bits_AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD_msmSystemRxTooLongErrorsCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxTooLongErrorsCounter_1 in AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD */ -#define word_AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD_msmSystemRxTooLongErrorsCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD */ -#define AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD_baseRegisterAddress 0x605C -/*! \brief MMD address of structure AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD */ -#define AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxInRangeLengthErrorsCounter_0 in AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD */ -#define AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD_msmSystemRxInRangeLengthErrorsCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxInRangeLengthErrorsCounter_0 in AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD */ -#define bits_AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD_msmSystemRxInRangeLengthErrorsCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxInRangeLengthErrorsCounter_0 in AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD */ -#define word_AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD_msmSystemRxInRangeLengthErrorsCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxInRangeLengthErrorsCounter_1 in AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD */ -#define AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD_msmSystemRxInRangeLengthErrorsCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxInRangeLengthErrorsCounter_1 in AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD */ -#define bits_AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD_msmSystemRxInRangeLengthErrorsCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxInRangeLengthErrorsCounter_1 in AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD */ -#define word_AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD_msmSystemRxInRangeLengthErrorsCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmSystemTxVlanFramesCounterRegister_HHD */ -#define AQ_MsmSystemTxVlanFramesCounterRegister_HHD_baseRegisterAddress 0x6060 -/*! \brief MMD address of structure AQ_MsmSystemTxVlanFramesCounterRegister_HHD */ -#define AQ_MsmSystemTxVlanFramesCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxVlanFramesCounter_0 in AQ_MsmSystemTxVlanFramesCounterRegister_HHD */ -#define AQ_MsmSystemTxVlanFramesCounterRegister_HHD_msmSystemTxVlanFramesCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxVlanFramesCounter_0 in AQ_MsmSystemTxVlanFramesCounterRegister_HHD */ -#define bits_AQ_MsmSystemTxVlanFramesCounterRegister_HHD_msmSystemTxVlanFramesCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxVlanFramesCounter_0 in AQ_MsmSystemTxVlanFramesCounterRegister_HHD */ -#define word_AQ_MsmSystemTxVlanFramesCounterRegister_HHD_msmSystemTxVlanFramesCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxVlanFramesCounter_1 in AQ_MsmSystemTxVlanFramesCounterRegister_HHD */ -#define AQ_MsmSystemTxVlanFramesCounterRegister_HHD_msmSystemTxVlanFramesCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxVlanFramesCounter_1 in AQ_MsmSystemTxVlanFramesCounterRegister_HHD */ -#define bits_AQ_MsmSystemTxVlanFramesCounterRegister_HHD_msmSystemTxVlanFramesCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxVlanFramesCounter_1 in AQ_MsmSystemTxVlanFramesCounterRegister_HHD */ -#define word_AQ_MsmSystemTxVlanFramesCounterRegister_HHD_msmSystemTxVlanFramesCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmSystemRxVlanFramesCounterRegister_HHD */ -#define AQ_MsmSystemRxVlanFramesCounterRegister_HHD_baseRegisterAddress 0x6064 -/*! \brief MMD address of structure AQ_MsmSystemRxVlanFramesCounterRegister_HHD */ -#define AQ_MsmSystemRxVlanFramesCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxVlanFramesCounter_0 in AQ_MsmSystemRxVlanFramesCounterRegister_HHD */ -#define AQ_MsmSystemRxVlanFramesCounterRegister_HHD_msmSystemRxVlanFramesCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxVlanFramesCounter_0 in AQ_MsmSystemRxVlanFramesCounterRegister_HHD */ -#define bits_AQ_MsmSystemRxVlanFramesCounterRegister_HHD_msmSystemRxVlanFramesCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxVlanFramesCounter_0 in AQ_MsmSystemRxVlanFramesCounterRegister_HHD */ -#define word_AQ_MsmSystemRxVlanFramesCounterRegister_HHD_msmSystemRxVlanFramesCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxVlanFramesCounter_1 in AQ_MsmSystemRxVlanFramesCounterRegister_HHD */ -#define AQ_MsmSystemRxVlanFramesCounterRegister_HHD_msmSystemRxVlanFramesCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxVlanFramesCounter_1 in AQ_MsmSystemRxVlanFramesCounterRegister_HHD */ -#define bits_AQ_MsmSystemRxVlanFramesCounterRegister_HHD_msmSystemRxVlanFramesCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxVlanFramesCounter_1 in AQ_MsmSystemRxVlanFramesCounterRegister_HHD */ -#define word_AQ_MsmSystemRxVlanFramesCounterRegister_HHD_msmSystemRxVlanFramesCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmSystemTxOctetsCounterRegister_HHD */ -#define AQ_MsmSystemTxOctetsCounterRegister_HHD_baseRegisterAddress 0x6068 -/*! \brief MMD address of structure AQ_MsmSystemTxOctetsCounterRegister_HHD */ -#define AQ_MsmSystemTxOctetsCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxOctetsCounter_0 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ -#define AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxOctetsCounter_0 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ -#define bits_AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxOctetsCounter_0 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ -#define word_AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxOctetsCounter_1 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ -#define AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxOctetsCounter_1 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ -#define bits_AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxOctetsCounter_1 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ -#define word_AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_1 u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxOctetsCounter_2 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ -#define AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_2 2 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxOctetsCounter_2 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ -#define bits_AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_2 u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxOctetsCounter_2 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ -#define word_AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_2 u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxOctetsCounter_3 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ -#define AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_3 3 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxOctetsCounter_3 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ -#define bits_AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_3 u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxOctetsCounter_3 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ -#define word_AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_3 u3.word_3 - -/*! \brief Base register address of structure AQ_MsmSystemRxOctetsCounterRegister_HHD */ -#define AQ_MsmSystemRxOctetsCounterRegister_HHD_baseRegisterAddress 0x606C -/*! \brief MMD address of structure AQ_MsmSystemRxOctetsCounterRegister_HHD */ -#define AQ_MsmSystemRxOctetsCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxOctetsCounter_0 in AQ_MsmSystemRxOctetsCounterRegister_HHD */ -#define AQ_MsmSystemRxOctetsCounterRegister_HHD_msmSystemRxOctetsCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxOctetsCounter_0 in AQ_MsmSystemRxOctetsCounterRegister_HHD */ -#define bits_AQ_MsmSystemRxOctetsCounterRegister_HHD_msmSystemRxOctetsCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxOctetsCounter_0 in AQ_MsmSystemRxOctetsCounterRegister_HHD */ -#define word_AQ_MsmSystemRxOctetsCounterRegister_HHD_msmSystemRxOctetsCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxOctetsCounter_1 in AQ_MsmSystemRxOctetsCounterRegister_HHD */ -#define AQ_MsmSystemRxOctetsCounterRegister_HHD_msmSystemRxOctetsCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxOctetsCounter_1 in AQ_MsmSystemRxOctetsCounterRegister_HHD */ -#define bits_AQ_MsmSystemRxOctetsCounterRegister_HHD_msmSystemRxOctetsCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxOctetsCounter_1 in AQ_MsmSystemRxOctetsCounterRegister_HHD */ -#define word_AQ_MsmSystemRxOctetsCounterRegister_HHD_msmSystemRxOctetsCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmSystemRxUnicastFramesCounterRegister_HHD */ -#define AQ_MsmSystemRxUnicastFramesCounterRegister_HHD_baseRegisterAddress 0x6070 -/*! \brief MMD address of structure AQ_MsmSystemRxUnicastFramesCounterRegister_HHD */ -#define AQ_MsmSystemRxUnicastFramesCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxUnicastFramesCounter_0 in AQ_MsmSystemRxUnicastFramesCounterRegister_HHD */ -#define AQ_MsmSystemRxUnicastFramesCounterRegister_HHD_msmSystemRxUnicastFramesCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxUnicastFramesCounter_0 in AQ_MsmSystemRxUnicastFramesCounterRegister_HHD */ -#define bits_AQ_MsmSystemRxUnicastFramesCounterRegister_HHD_msmSystemRxUnicastFramesCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxUnicastFramesCounter_0 in AQ_MsmSystemRxUnicastFramesCounterRegister_HHD */ -#define word_AQ_MsmSystemRxUnicastFramesCounterRegister_HHD_msmSystemRxUnicastFramesCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxUnicastFramesCounter_1 in AQ_MsmSystemRxUnicastFramesCounterRegister_HHD */ -#define AQ_MsmSystemRxUnicastFramesCounterRegister_HHD_msmSystemRxUnicastFramesCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxUnicastFramesCounter_1 in AQ_MsmSystemRxUnicastFramesCounterRegister_HHD */ -#define bits_AQ_MsmSystemRxUnicastFramesCounterRegister_HHD_msmSystemRxUnicastFramesCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxUnicastFramesCounter_1 in AQ_MsmSystemRxUnicastFramesCounterRegister_HHD */ -#define word_AQ_MsmSystemRxUnicastFramesCounterRegister_HHD_msmSystemRxUnicastFramesCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmSystemRxMulticastFramesCounterRegister_HHD */ -#define AQ_MsmSystemRxMulticastFramesCounterRegister_HHD_baseRegisterAddress 0x6074 -/*! \brief MMD address of structure AQ_MsmSystemRxMulticastFramesCounterRegister_HHD */ -#define AQ_MsmSystemRxMulticastFramesCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxMulticastFramesCounter_0 in AQ_MsmSystemRxMulticastFramesCounterRegister_HHD */ -#define AQ_MsmSystemRxMulticastFramesCounterRegister_HHD_msmSystemRxMulticastFramesCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxMulticastFramesCounter_0 in AQ_MsmSystemRxMulticastFramesCounterRegister_HHD */ -#define bits_AQ_MsmSystemRxMulticastFramesCounterRegister_HHD_msmSystemRxMulticastFramesCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxMulticastFramesCounter_0 in AQ_MsmSystemRxMulticastFramesCounterRegister_HHD */ -#define word_AQ_MsmSystemRxMulticastFramesCounterRegister_HHD_msmSystemRxMulticastFramesCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxMulticastFramesCounter_1 in AQ_MsmSystemRxMulticastFramesCounterRegister_HHD */ -#define AQ_MsmSystemRxMulticastFramesCounterRegister_HHD_msmSystemRxMulticastFramesCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxMulticastFramesCounter_1 in AQ_MsmSystemRxMulticastFramesCounterRegister_HHD */ -#define bits_AQ_MsmSystemRxMulticastFramesCounterRegister_HHD_msmSystemRxMulticastFramesCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxMulticastFramesCounter_1 in AQ_MsmSystemRxMulticastFramesCounterRegister_HHD */ -#define word_AQ_MsmSystemRxMulticastFramesCounterRegister_HHD_msmSystemRxMulticastFramesCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD */ -#define AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD_baseRegisterAddress 0x6078 -/*! \brief MMD address of structure AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD */ -#define AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxBroadcastFramesCounter_0 in AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD */ -#define AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD_msmSystemRxBroadcastFramesCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxBroadcastFramesCounter_0 in AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD */ -#define bits_AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD_msmSystemRxBroadcastFramesCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxBroadcastFramesCounter_0 in AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD */ -#define word_AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD_msmSystemRxBroadcastFramesCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxBroadcastFramesCounter_1 in AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD */ -#define AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD_msmSystemRxBroadcastFramesCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxBroadcastFramesCounter_1 in AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD */ -#define bits_AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD_msmSystemRxBroadcastFramesCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxBroadcastFramesCounter_1 in AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD */ -#define word_AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD_msmSystemRxBroadcastFramesCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmSystemTxErrorsCounterRegister_HHD */ -#define AQ_MsmSystemTxErrorsCounterRegister_HHD_baseRegisterAddress 0x607C -/*! \brief MMD address of structure AQ_MsmSystemTxErrorsCounterRegister_HHD */ -#define AQ_MsmSystemTxErrorsCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxErrorsCounter_0 in AQ_MsmSystemTxErrorsCounterRegister_HHD */ -#define AQ_MsmSystemTxErrorsCounterRegister_HHD_msmSystemTxErrorsCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxErrorsCounter_0 in AQ_MsmSystemTxErrorsCounterRegister_HHD */ -#define bits_AQ_MsmSystemTxErrorsCounterRegister_HHD_msmSystemTxErrorsCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxErrorsCounter_0 in AQ_MsmSystemTxErrorsCounterRegister_HHD */ -#define word_AQ_MsmSystemTxErrorsCounterRegister_HHD_msmSystemTxErrorsCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxErrorsCounter_1 in AQ_MsmSystemTxErrorsCounterRegister_HHD */ -#define AQ_MsmSystemTxErrorsCounterRegister_HHD_msmSystemTxErrorsCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxErrorsCounter_1 in AQ_MsmSystemTxErrorsCounterRegister_HHD */ -#define bits_AQ_MsmSystemTxErrorsCounterRegister_HHD_msmSystemTxErrorsCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxErrorsCounter_1 in AQ_MsmSystemTxErrorsCounterRegister_HHD */ -#define word_AQ_MsmSystemTxErrorsCounterRegister_HHD_msmSystemTxErrorsCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmSystemTxUnicastFramesCounterRegister_HHD */ -#define AQ_MsmSystemTxUnicastFramesCounterRegister_HHD_baseRegisterAddress 0x6084 -/*! \brief MMD address of structure AQ_MsmSystemTxUnicastFramesCounterRegister_HHD */ -#define AQ_MsmSystemTxUnicastFramesCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxUnicastFramesCounter_0 in AQ_MsmSystemTxUnicastFramesCounterRegister_HHD */ -#define AQ_MsmSystemTxUnicastFramesCounterRegister_HHD_msmSystemTxUnicastFramesCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxUnicastFramesCounter_0 in AQ_MsmSystemTxUnicastFramesCounterRegister_HHD */ -#define bits_AQ_MsmSystemTxUnicastFramesCounterRegister_HHD_msmSystemTxUnicastFramesCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxUnicastFramesCounter_0 in AQ_MsmSystemTxUnicastFramesCounterRegister_HHD */ -#define word_AQ_MsmSystemTxUnicastFramesCounterRegister_HHD_msmSystemTxUnicastFramesCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxUnicastFramesCounter_1 in AQ_MsmSystemTxUnicastFramesCounterRegister_HHD */ -#define AQ_MsmSystemTxUnicastFramesCounterRegister_HHD_msmSystemTxUnicastFramesCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxUnicastFramesCounter_1 in AQ_MsmSystemTxUnicastFramesCounterRegister_HHD */ -#define bits_AQ_MsmSystemTxUnicastFramesCounterRegister_HHD_msmSystemTxUnicastFramesCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxUnicastFramesCounter_1 in AQ_MsmSystemTxUnicastFramesCounterRegister_HHD */ -#define word_AQ_MsmSystemTxUnicastFramesCounterRegister_HHD_msmSystemTxUnicastFramesCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmSystemTxMulticastFramesCounterRegister_HHD */ -#define AQ_MsmSystemTxMulticastFramesCounterRegister_HHD_baseRegisterAddress 0x6088 -/*! \brief MMD address of structure AQ_MsmSystemTxMulticastFramesCounterRegister_HHD */ -#define AQ_MsmSystemTxMulticastFramesCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxMulticastFramesCounter_0 in AQ_MsmSystemTxMulticastFramesCounterRegister_HHD */ -#define AQ_MsmSystemTxMulticastFramesCounterRegister_HHD_msmSystemTxMulticastFramesCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxMulticastFramesCounter_0 in AQ_MsmSystemTxMulticastFramesCounterRegister_HHD */ -#define bits_AQ_MsmSystemTxMulticastFramesCounterRegister_HHD_msmSystemTxMulticastFramesCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxMulticastFramesCounter_0 in AQ_MsmSystemTxMulticastFramesCounterRegister_HHD */ -#define word_AQ_MsmSystemTxMulticastFramesCounterRegister_HHD_msmSystemTxMulticastFramesCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxMulticastFramesCounter_1 in AQ_MsmSystemTxMulticastFramesCounterRegister_HHD */ -#define AQ_MsmSystemTxMulticastFramesCounterRegister_HHD_msmSystemTxMulticastFramesCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxMulticastFramesCounter_1 in AQ_MsmSystemTxMulticastFramesCounterRegister_HHD */ -#define bits_AQ_MsmSystemTxMulticastFramesCounterRegister_HHD_msmSystemTxMulticastFramesCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxMulticastFramesCounter_1 in AQ_MsmSystemTxMulticastFramesCounterRegister_HHD */ -#define word_AQ_MsmSystemTxMulticastFramesCounterRegister_HHD_msmSystemTxMulticastFramesCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD */ -#define AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD_baseRegisterAddress 0x608C -/*! \brief MMD address of structure AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD */ -#define AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxBroadcastFramesCounter_0 in AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD */ -#define AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD_msmSystemTxBroadcastFramesCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxBroadcastFramesCounter_0 in AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD */ -#define bits_AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD_msmSystemTxBroadcastFramesCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxBroadcastFramesCounter_0 in AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD */ -#define word_AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD_msmSystemTxBroadcastFramesCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxBroadcastFramesCounter_1 in AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD */ -#define AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD_msmSystemTxBroadcastFramesCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxBroadcastFramesCounter_1 in AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD */ -#define bits_AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD_msmSystemTxBroadcastFramesCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxBroadcastFramesCounter_1 in AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD */ -#define word_AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD_msmSystemTxBroadcastFramesCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmSystemRxErrorsCounterRegister_HHD */ -#define AQ_MsmSystemRxErrorsCounterRegister_HHD_baseRegisterAddress 0x60C8 -/*! \brief MMD address of structure AQ_MsmSystemRxErrorsCounterRegister_HHD */ -#define AQ_MsmSystemRxErrorsCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxErrorsCounter_0 in AQ_MsmSystemRxErrorsCounterRegister_HHD */ -#define AQ_MsmSystemRxErrorsCounterRegister_HHD_msmSystemRxErrorsCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxErrorsCounter_0 in AQ_MsmSystemRxErrorsCounterRegister_HHD */ -#define bits_AQ_MsmSystemRxErrorsCounterRegister_HHD_msmSystemRxErrorsCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxErrorsCounter_0 in AQ_MsmSystemRxErrorsCounterRegister_HHD */ -#define word_AQ_MsmSystemRxErrorsCounterRegister_HHD_msmSystemRxErrorsCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxErrorsCounter_1 in AQ_MsmSystemRxErrorsCounterRegister_HHD */ -#define AQ_MsmSystemRxErrorsCounterRegister_HHD_msmSystemRxErrorsCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxErrorsCounter_1 in AQ_MsmSystemRxErrorsCounterRegister_HHD */ -#define bits_AQ_MsmSystemRxErrorsCounterRegister_HHD_msmSystemRxErrorsCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxErrorsCounter_1 in AQ_MsmSystemRxErrorsCounterRegister_HHD */ -#define word_AQ_MsmSystemRxErrorsCounterRegister_HHD_msmSystemRxErrorsCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MssIngressVlanTpid_0Register_HHD */ -#define AQ_MssIngressVlanTpid_0Register_HHD_baseRegisterAddress 0x8006 -/*! \brief MMD address of structure AQ_MssIngressVlanTpid_0Register_HHD */ -#define AQ_MssIngressVlanTpid_0Register_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressVlanStag in AQ_MssIngressVlanTpid_0Register_HHD */ -#define AQ_MssIngressVlanTpid_0Register_HHD_mssIngressVlanStag 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressVlanStag in AQ_MssIngressVlanTpid_0Register_HHD */ -#define bits_AQ_MssIngressVlanTpid_0Register_HHD_mssIngressVlanStag u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressVlanStag in AQ_MssIngressVlanTpid_0Register_HHD */ -#define word_AQ_MssIngressVlanTpid_0Register_HHD_mssIngressVlanStag u0.word_0 - -/*! \brief Base register address of structure AQ_MssIngressVlanTpid_1Register_HHD */ -#define AQ_MssIngressVlanTpid_1Register_HHD_baseRegisterAddress 0x8008 -/*! \brief MMD address of structure AQ_MssIngressVlanTpid_1Register_HHD */ -#define AQ_MssIngressVlanTpid_1Register_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressVlanQtag in AQ_MssIngressVlanTpid_1Register_HHD */ -#define AQ_MssIngressVlanTpid_1Register_HHD_mssIngressVlanQtag 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressVlanQtag in AQ_MssIngressVlanTpid_1Register_HHD */ -#define bits_AQ_MssIngressVlanTpid_1Register_HHD_mssIngressVlanQtag u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressVlanQtag in AQ_MssIngressVlanTpid_1Register_HHD */ -#define word_AQ_MssIngressVlanTpid_1Register_HHD_mssIngressVlanQtag u0.word_0 - -/*! \brief Base register address of structure AQ_MssIngressVlanControlRegister_HHD */ -#define AQ_MssIngressVlanControlRegister_HHD_baseRegisterAddress 0x800A -/*! \brief MMD address of structure AQ_MssIngressVlanControlRegister_HHD */ -#define AQ_MssIngressVlanControlRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressVlanUpMapTableLSW in AQ_MssIngressVlanControlRegister_HHD */ -#define AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanUpMapTableLSW 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressVlanUpMapTableLSW in AQ_MssIngressVlanControlRegister_HHD */ -#define bits_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanUpMapTableLSW u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressVlanUpMapTableLSW in AQ_MssIngressVlanControlRegister_HHD */ -#define word_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanUpMapTableLSW u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressVlanQtagParseEnable in AQ_MssIngressVlanControlRegister_HHD */ -#define AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanQtagParseEnable 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressVlanQtagParseEnable in AQ_MssIngressVlanControlRegister_HHD */ -#define bits_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanQtagParseEnable u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressVlanQtagParseEnable in AQ_MssIngressVlanControlRegister_HHD */ -#define word_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanQtagParseEnable u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressVlanStagParseEnable in AQ_MssIngressVlanControlRegister_HHD */ -#define AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanStagParseEnable 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressVlanStagParseEnable in AQ_MssIngressVlanControlRegister_HHD */ -#define bits_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanStagParseEnable u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressVlanStagParseEnable in AQ_MssIngressVlanControlRegister_HHD */ -#define word_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanStagParseEnable u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressVlanQinqParseEnable in AQ_MssIngressVlanControlRegister_HHD */ -#define AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanQinqParseEnable 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressVlanQinqParseEnable in AQ_MssIngressVlanControlRegister_HHD */ -#define bits_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanQinqParseEnable u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressVlanQinqParseEnable in AQ_MssIngressVlanControlRegister_HHD */ -#define word_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanQinqParseEnable u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressVlanQtagUpParseEnable in AQ_MssIngressVlanControlRegister_HHD */ -#define AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanQtagUpParseEnable 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressVlanQtagUpParseEnable in AQ_MssIngressVlanControlRegister_HHD */ -#define bits_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanQtagUpParseEnable u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressVlanQtagUpParseEnable in AQ_MssIngressVlanControlRegister_HHD */ -#define word_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanQtagUpParseEnable u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressVlanStagUpParseEnable in AQ_MssIngressVlanControlRegister_HHD */ -#define AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanStagUpParseEnable 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressVlanStagUpParseEnable in AQ_MssIngressVlanControlRegister_HHD */ -#define bits_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanStagUpParseEnable u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressVlanStagUpParseEnable in AQ_MssIngressVlanControlRegister_HHD */ -#define word_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanStagUpParseEnable u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressVlanUpDefault in AQ_MssIngressVlanControlRegister_HHD */ -#define AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanUpDefault 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressVlanUpDefault in AQ_MssIngressVlanControlRegister_HHD */ -#define bits_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanUpDefault u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressVlanUpDefault in AQ_MssIngressVlanControlRegister_HHD */ -#define word_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanUpDefault u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressVlanUpMapTableMSW in AQ_MssIngressVlanControlRegister_HHD */ -#define AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanUpMapTableMSW 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressVlanUpMapTableMSW in AQ_MssIngressVlanControlRegister_HHD */ -#define bits_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanUpMapTableMSW u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressVlanUpMapTableMSW in AQ_MssIngressVlanControlRegister_HHD */ -#define word_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanUpMapTableMSW u1.word_1 - -/*! \brief Base register address of structure AQ_MssIngressMtuSizeControlRegister_HHD */ -#define AQ_MssIngressMtuSizeControlRegister_HHD_baseRegisterAddress 0x800C -/*! \brief MMD address of structure AQ_MssIngressMtuSizeControlRegister_HHD */ -#define AQ_MssIngressMtuSizeControlRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressControlledPacketMtuSize in AQ_MssIngressMtuSizeControlRegister_HHD */ -#define AQ_MssIngressMtuSizeControlRegister_HHD_mssIngressControlledPacketMtuSize 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressControlledPacketMtuSize in AQ_MssIngressMtuSizeControlRegister_HHD */ -#define bits_AQ_MssIngressMtuSizeControlRegister_HHD_mssIngressControlledPacketMtuSize u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressControlledPacketMtuSize in AQ_MssIngressMtuSizeControlRegister_HHD */ -#define word_AQ_MssIngressMtuSizeControlRegister_HHD_mssIngressControlledPacketMtuSize u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressUncontrolledPacketMtuSize in AQ_MssIngressMtuSizeControlRegister_HHD */ -#define AQ_MssIngressMtuSizeControlRegister_HHD_mssIngressUncontrolledPacketMtuSize 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressUncontrolledPacketMtuSize in AQ_MssIngressMtuSizeControlRegister_HHD */ -#define bits_AQ_MssIngressMtuSizeControlRegister_HHD_mssIngressUncontrolledPacketMtuSize u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressUncontrolledPacketMtuSize in AQ_MssIngressMtuSizeControlRegister_HHD */ -#define word_AQ_MssIngressMtuSizeControlRegister_HHD_mssIngressUncontrolledPacketMtuSize u1.word_1 - -/*! \brief Base register address of structure AQ_MssIngressControlRegister_HHD */ -#define AQ_MssIngressControlRegister_HHD_baseRegisterAddress 0x800E -/*! \brief MMD address of structure AQ_MssIngressControlRegister_HHD */ -#define AQ_MssIngressControlRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressIcvLsb_8BytesEnable in AQ_MssIngressControlRegister_HHD */ -#define AQ_MssIngressControlRegister_HHD_mssIngressIcvLsb_8BytesEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressIcvLsb_8BytesEnable in AQ_MssIngressControlRegister_HHD */ -#define bits_AQ_MssIngressControlRegister_HHD_mssIngressIcvLsb_8BytesEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressIcvLsb_8BytesEnable in AQ_MssIngressControlRegister_HHD */ -#define word_AQ_MssIngressControlRegister_HHD_mssIngressIcvLsb_8BytesEnable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressGlobalValidateFrames in AQ_MssIngressControlRegister_HHD */ -#define AQ_MssIngressControlRegister_HHD_mssIngressGlobalValidateFrames 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressGlobalValidateFrames in AQ_MssIngressControlRegister_HHD */ -#define bits_AQ_MssIngressControlRegister_HHD_mssIngressGlobalValidateFrames u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressGlobalValidateFrames in AQ_MssIngressControlRegister_HHD */ -#define word_AQ_MssIngressControlRegister_HHD_mssIngressGlobalValidateFrames u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressRemoveSectag in AQ_MssIngressControlRegister_HHD */ -#define AQ_MssIngressControlRegister_HHD_mssIngressRemoveSectag 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressRemoveSectag in AQ_MssIngressControlRegister_HHD */ -#define bits_AQ_MssIngressControlRegister_HHD_mssIngressRemoveSectag u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressRemoveSectag in AQ_MssIngressControlRegister_HHD */ -#define word_AQ_MssIngressControlRegister_HHD_mssIngressRemoveSectag u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressHighPriority in AQ_MssIngressControlRegister_HHD */ -#define AQ_MssIngressControlRegister_HHD_mssIngressHighPriority 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressHighPriority in AQ_MssIngressControlRegister_HHD */ -#define bits_AQ_MssIngressControlRegister_HHD_mssIngressHighPriority u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressHighPriority in AQ_MssIngressControlRegister_HHD */ -#define word_AQ_MssIngressControlRegister_HHD_mssIngressHighPriority u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressClearCount in AQ_MssIngressControlRegister_HHD */ -#define AQ_MssIngressControlRegister_HHD_mssIngressClearCount 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressClearCount in AQ_MssIngressControlRegister_HHD */ -#define bits_AQ_MssIngressControlRegister_HHD_mssIngressClearCount u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressClearCount in AQ_MssIngressControlRegister_HHD */ -#define word_AQ_MssIngressControlRegister_HHD_mssIngressClearCount u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressClearGlobalTime in AQ_MssIngressControlRegister_HHD */ -#define AQ_MssIngressControlRegister_HHD_mssIngressClearGlobalTime 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressClearGlobalTime in AQ_MssIngressControlRegister_HHD */ -#define bits_AQ_MssIngressControlRegister_HHD_mssIngressClearGlobalTime u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressClearGlobalTime in AQ_MssIngressControlRegister_HHD */ -#define word_AQ_MssIngressControlRegister_HHD_mssIngressClearGlobalTime u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressCheckIcv in AQ_MssIngressControlRegister_HHD */ -#define AQ_MssIngressControlRegister_HHD_mssIngressCheckIcv 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressCheckIcv in AQ_MssIngressControlRegister_HHD */ -#define bits_AQ_MssIngressControlRegister_HHD_mssIngressCheckIcv u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressCheckIcv in AQ_MssIngressControlRegister_HHD */ -#define word_AQ_MssIngressControlRegister_HHD_mssIngressCheckIcv u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressDropIgprcMiss in AQ_MssIngressControlRegister_HHD */ -#define AQ_MssIngressControlRegister_HHD_mssIngressDropIgprcMiss 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressDropIgprcMiss in AQ_MssIngressControlRegister_HHD */ -#define bits_AQ_MssIngressControlRegister_HHD_mssIngressDropIgprcMiss u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressDropIgprcMiss in AQ_MssIngressControlRegister_HHD */ -#define word_AQ_MssIngressControlRegister_HHD_mssIngressDropIgprcMiss u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressDropKayPacket in AQ_MssIngressControlRegister_HHD */ -#define AQ_MssIngressControlRegister_HHD_mssIngressDropKayPacket 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressDropKayPacket in AQ_MssIngressControlRegister_HHD */ -#define bits_AQ_MssIngressControlRegister_HHD_mssIngressDropKayPacket u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressDropKayPacket in AQ_MssIngressControlRegister_HHD */ -#define word_AQ_MssIngressControlRegister_HHD_mssIngressDropKayPacket u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressMaskShortLengthError in AQ_MssIngressControlRegister_HHD */ -#define AQ_MssIngressControlRegister_HHD_mssIngressMaskShortLengthError 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressMaskShortLengthError in AQ_MssIngressControlRegister_HHD */ -#define bits_AQ_MssIngressControlRegister_HHD_mssIngressMaskShortLengthError u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressMaskShortLengthError in AQ_MssIngressControlRegister_HHD */ -#define word_AQ_MssIngressControlRegister_HHD_mssIngressMaskShortLengthError u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressCreateSci in AQ_MssIngressControlRegister_HHD */ -#define AQ_MssIngressControlRegister_HHD_mssIngressCreateSci 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressCreateSci in AQ_MssIngressControlRegister_HHD */ -#define bits_AQ_MssIngressControlRegister_HHD_mssIngressCreateSci u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressCreateSci in AQ_MssIngressControlRegister_HHD */ -#define word_AQ_MssIngressControlRegister_HHD_mssIngressCreateSci u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressOperationPointToPoint in AQ_MssIngressControlRegister_HHD */ -#define AQ_MssIngressControlRegister_HHD_mssIngressOperationPointToPoint 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressOperationPointToPoint in AQ_MssIngressControlRegister_HHD */ -#define bits_AQ_MssIngressControlRegister_HHD_mssIngressOperationPointToPoint u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressOperationPointToPoint in AQ_MssIngressControlRegister_HHD */ -#define word_AQ_MssIngressControlRegister_HHD_mssIngressOperationPointToPoint u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSoftReset in AQ_MssIngressControlRegister_HHD */ -#define AQ_MssIngressControlRegister_HHD_mssIngressSoftReset 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSoftReset in AQ_MssIngressControlRegister_HHD */ -#define bits_AQ_MssIngressControlRegister_HHD_mssIngressSoftReset u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSoftReset in AQ_MssIngressControlRegister_HHD */ -#define word_AQ_MssIngressControlRegister_HHD_mssIngressSoftReset u0.word_0 - -/*! \brief Base register address of structure AQ_MssIngressSaControlRegister_HHD */ -#define AQ_MssIngressSaControlRegister_HHD_baseRegisterAddress 0x8010 -/*! \brief MMD address of structure AQ_MssIngressSaControlRegister_HHD */ -#define AQ_MssIngressSaControlRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaThresholdLSW in AQ_MssIngressSaControlRegister_HHD */ -#define AQ_MssIngressSaControlRegister_HHD_mssIngressSaThresholdLSW 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaThresholdLSW in AQ_MssIngressSaControlRegister_HHD */ -#define bits_AQ_MssIngressSaControlRegister_HHD_mssIngressSaThresholdLSW u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaThresholdLSW in AQ_MssIngressSaControlRegister_HHD */ -#define word_AQ_MssIngressSaControlRegister_HHD_mssIngressSaThresholdLSW u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaThresholdMSW in AQ_MssIngressSaControlRegister_HHD */ -#define AQ_MssIngressSaControlRegister_HHD_mssIngressSaThresholdMSW 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaThresholdMSW in AQ_MssIngressSaControlRegister_HHD */ -#define bits_AQ_MssIngressSaControlRegister_HHD_mssIngressSaThresholdMSW u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaThresholdMSW in AQ_MssIngressSaControlRegister_HHD */ -#define word_AQ_MssIngressSaControlRegister_HHD_mssIngressSaThresholdMSW u1.word_1 - -/*! \brief Base register address of structure AQ_MssIngressInterruptStatusRegister_HHD */ -#define AQ_MssIngressInterruptStatusRegister_HHD_baseRegisterAddress 0x802E -/*! \brief MMD address of structure AQ_MssIngressInterruptStatusRegister_HHD */ -#define AQ_MssIngressInterruptStatusRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressIgpocMissInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ -#define AQ_MssIngressInterruptStatusRegister_HHD_mssIngressIgpocMissInterrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressIgpocMissInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ -#define bits_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressIgpocMissInterrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressIgpocMissInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ -#define word_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressIgpocMissInterrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressTciE_cErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ -#define AQ_MssIngressInterruptStatusRegister_HHD_mssIngressTciE_cErrorInterrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressTciE_cErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ -#define bits_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressTciE_cErrorInterrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressTciE_cErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ -#define word_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressTciE_cErrorInterrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressEccErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ -#define AQ_MssIngressInterruptStatusRegister_HHD_mssIngressEccErrorInterrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressEccErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ -#define bits_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressEccErrorInterrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressEccErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ -#define word_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressEccErrorInterrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressMibSaturationInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ -#define AQ_MssIngressInterruptStatusRegister_HHD_mssIngressMibSaturationInterrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressMibSaturationInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ -#define bits_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressMibSaturationInterrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressMibSaturationInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ -#define word_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressMibSaturationInterrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressReplayErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ -#define AQ_MssIngressInterruptStatusRegister_HHD_mssIngressReplayErrorInterrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressReplayErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ -#define bits_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressReplayErrorInterrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressReplayErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ -#define word_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressReplayErrorInterrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressIcvErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ -#define AQ_MssIngressInterruptStatusRegister_HHD_mssIngressIcvErrorInterrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressIcvErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ -#define bits_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressIcvErrorInterrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressIcvErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ -#define word_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressIcvErrorInterrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaThresholdExpiredInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ -#define AQ_MssIngressInterruptStatusRegister_HHD_mssIngressSaThresholdExpiredInterrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaThresholdExpiredInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ -#define bits_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressSaThresholdExpiredInterrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaThresholdExpiredInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ -#define word_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressSaThresholdExpiredInterrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaExpiredInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ -#define AQ_MssIngressInterruptStatusRegister_HHD_mssIngressSaExpiredInterrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaExpiredInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ -#define bits_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressSaExpiredInterrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaExpiredInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ -#define word_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressSaExpiredInterrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssMasterIngressInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ -#define AQ_MssIngressInterruptStatusRegister_HHD_mssMasterIngressInterrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssMasterIngressInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ -#define bits_AQ_MssIngressInterruptStatusRegister_HHD_mssMasterIngressInterrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssMasterIngressInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ -#define word_AQ_MssIngressInterruptStatusRegister_HHD_mssMasterIngressInterrupt u0.word_0 - -/*! \brief Base register address of structure AQ_MssIngressInterruptMaskRegister_HHD */ -#define AQ_MssIngressInterruptMaskRegister_HHD_baseRegisterAddress 0x8030 -/*! \brief MMD address of structure AQ_MssIngressInterruptMaskRegister_HHD */ -#define AQ_MssIngressInterruptMaskRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressIgpocMissInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ -#define AQ_MssIngressInterruptMaskRegister_HHD_mssIngressIgpocMissInterruptEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressIgpocMissInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ -#define bits_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressIgpocMissInterruptEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressIgpocMissInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ -#define word_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressIgpocMissInterruptEnable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressTciE_cErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ -#define AQ_MssIngressInterruptMaskRegister_HHD_mssIngressTciE_cErrorInterruptEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressTciE_cErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ -#define bits_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressTciE_cErrorInterruptEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressTciE_cErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ -#define word_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressTciE_cErrorInterruptEnable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressEccErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ -#define AQ_MssIngressInterruptMaskRegister_HHD_mssIngressEccErrorInterruptEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressEccErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ -#define bits_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressEccErrorInterruptEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressEccErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ -#define word_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressEccErrorInterruptEnable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressMibSaturationInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ -#define AQ_MssIngressInterruptMaskRegister_HHD_mssIngressMibSaturationInterruptEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressMibSaturationInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ -#define bits_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressMibSaturationInterruptEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressMibSaturationInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ -#define word_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressMibSaturationInterruptEnable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressReplayErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ -#define AQ_MssIngressInterruptMaskRegister_HHD_mssIngressReplayErrorInterruptEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressReplayErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ -#define bits_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressReplayErrorInterruptEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressReplayErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ -#define word_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressReplayErrorInterruptEnable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressIcvErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ -#define AQ_MssIngressInterruptMaskRegister_HHD_mssIngressIcvErrorInterruptEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressIcvErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ -#define bits_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressIcvErrorInterruptEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressIcvErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ -#define word_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressIcvErrorInterruptEnable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaThresholdExpiredInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ -#define AQ_MssIngressInterruptMaskRegister_HHD_mssIngressSaThresholdExpiredInterruptEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaThresholdExpiredInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ -#define bits_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressSaThresholdExpiredInterruptEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaThresholdExpiredInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ -#define word_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressSaThresholdExpiredInterruptEnable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaExpiredInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ -#define AQ_MssIngressInterruptMaskRegister_HHD_mssIngressSaExpiredInterruptEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaExpiredInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ -#define bits_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressSaExpiredInterruptEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaExpiredInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ -#define word_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressSaExpiredInterruptEnable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressMasterInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ -#define AQ_MssIngressInterruptMaskRegister_HHD_mssIngressMasterInterruptEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressMasterInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ -#define bits_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressMasterInterruptEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressMasterInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ -#define word_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressMasterInterruptEnable u0.word_0 - -/*! \brief Base register address of structure AQ_MssIngressSaIcvErrorStatusRegister_HHD */ -#define AQ_MssIngressSaIcvErrorStatusRegister_HHD_baseRegisterAddress 0x8032 -/*! \brief MMD address of structure AQ_MssIngressSaIcvErrorStatusRegister_HHD */ -#define AQ_MssIngressSaIcvErrorStatusRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaIcvErrorLSW in AQ_MssIngressSaIcvErrorStatusRegister_HHD */ -#define AQ_MssIngressSaIcvErrorStatusRegister_HHD_mssIngressSaIcvErrorLSW 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaIcvErrorLSW in AQ_MssIngressSaIcvErrorStatusRegister_HHD */ -#define bits_AQ_MssIngressSaIcvErrorStatusRegister_HHD_mssIngressSaIcvErrorLSW u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaIcvErrorLSW in AQ_MssIngressSaIcvErrorStatusRegister_HHD */ -#define word_AQ_MssIngressSaIcvErrorStatusRegister_HHD_mssIngressSaIcvErrorLSW u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaIcvErrorMSW in AQ_MssIngressSaIcvErrorStatusRegister_HHD */ -#define AQ_MssIngressSaIcvErrorStatusRegister_HHD_mssIngressSaIcvErrorMSW 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaIcvErrorMSW in AQ_MssIngressSaIcvErrorStatusRegister_HHD */ -#define bits_AQ_MssIngressSaIcvErrorStatusRegister_HHD_mssIngressSaIcvErrorMSW u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaIcvErrorMSW in AQ_MssIngressSaIcvErrorStatusRegister_HHD */ -#define word_AQ_MssIngressSaIcvErrorStatusRegister_HHD_mssIngressSaIcvErrorMSW u1.word_1 - -/*! \brief Base register address of structure AQ_MssIngressSaReplayErrorStatusRegister_HHD */ -#define AQ_MssIngressSaReplayErrorStatusRegister_HHD_baseRegisterAddress 0x8034 -/*! \brief MMD address of structure AQ_MssIngressSaReplayErrorStatusRegister_HHD */ -#define AQ_MssIngressSaReplayErrorStatusRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaReplayErrorLSW in AQ_MssIngressSaReplayErrorStatusRegister_HHD */ -#define AQ_MssIngressSaReplayErrorStatusRegister_HHD_mssIngressSaReplayErrorLSW 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaReplayErrorLSW in AQ_MssIngressSaReplayErrorStatusRegister_HHD */ -#define bits_AQ_MssIngressSaReplayErrorStatusRegister_HHD_mssIngressSaReplayErrorLSW u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaReplayErrorLSW in AQ_MssIngressSaReplayErrorStatusRegister_HHD */ -#define word_AQ_MssIngressSaReplayErrorStatusRegister_HHD_mssIngressSaReplayErrorLSW u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaReplayErrorMSW in AQ_MssIngressSaReplayErrorStatusRegister_HHD */ -#define AQ_MssIngressSaReplayErrorStatusRegister_HHD_mssIngressSaReplayErrorMSW 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaReplayErrorMSW in AQ_MssIngressSaReplayErrorStatusRegister_HHD */ -#define bits_AQ_MssIngressSaReplayErrorStatusRegister_HHD_mssIngressSaReplayErrorMSW u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaReplayErrorMSW in AQ_MssIngressSaReplayErrorStatusRegister_HHD */ -#define word_AQ_MssIngressSaReplayErrorStatusRegister_HHD_mssIngressSaReplayErrorMSW u1.word_1 - -/*! \brief Base register address of structure AQ_MssIngressSaExpiredStatusRegister_HHD */ -#define AQ_MssIngressSaExpiredStatusRegister_HHD_baseRegisterAddress 0x8036 -/*! \brief MMD address of structure AQ_MssIngressSaExpiredStatusRegister_HHD */ -#define AQ_MssIngressSaExpiredStatusRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaExpiredLSW in AQ_MssIngressSaExpiredStatusRegister_HHD */ -#define AQ_MssIngressSaExpiredStatusRegister_HHD_mssIngressSaExpiredLSW 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaExpiredLSW in AQ_MssIngressSaExpiredStatusRegister_HHD */ -#define bits_AQ_MssIngressSaExpiredStatusRegister_HHD_mssIngressSaExpiredLSW u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaExpiredLSW in AQ_MssIngressSaExpiredStatusRegister_HHD */ -#define word_AQ_MssIngressSaExpiredStatusRegister_HHD_mssIngressSaExpiredLSW u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaExpiredMSW in AQ_MssIngressSaExpiredStatusRegister_HHD */ -#define AQ_MssIngressSaExpiredStatusRegister_HHD_mssIngressSaExpiredMSW 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaExpiredMSW in AQ_MssIngressSaExpiredStatusRegister_HHD */ -#define bits_AQ_MssIngressSaExpiredStatusRegister_HHD_mssIngressSaExpiredMSW u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaExpiredMSW in AQ_MssIngressSaExpiredStatusRegister_HHD */ -#define word_AQ_MssIngressSaExpiredStatusRegister_HHD_mssIngressSaExpiredMSW u1.word_1 - -/*! \brief Base register address of structure AQ_MssIngressSaThresholdExpiredStatusRegister_HHD */ -#define AQ_MssIngressSaThresholdExpiredStatusRegister_HHD_baseRegisterAddress 0x8038 -/*! \brief MMD address of structure AQ_MssIngressSaThresholdExpiredStatusRegister_HHD */ -#define AQ_MssIngressSaThresholdExpiredStatusRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaThresholdExpiredLSW in AQ_MssIngressSaThresholdExpiredStatusRegister_HHD */ -#define AQ_MssIngressSaThresholdExpiredStatusRegister_HHD_mssIngressSaThresholdExpiredLSW 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaThresholdExpiredLSW in AQ_MssIngressSaThresholdExpiredStatusRegister_HHD */ -#define bits_AQ_MssIngressSaThresholdExpiredStatusRegister_HHD_mssIngressSaThresholdExpiredLSW u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaThresholdExpiredLSW in AQ_MssIngressSaThresholdExpiredStatusRegister_HHD */ -#define word_AQ_MssIngressSaThresholdExpiredStatusRegister_HHD_mssIngressSaThresholdExpiredLSW u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaThresholdExpiredMSW in AQ_MssIngressSaThresholdExpiredStatusRegister_HHD */ -#define AQ_MssIngressSaThresholdExpiredStatusRegister_HHD_mssIngressSaThresholdExpiredMSW 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaThresholdExpiredMSW in AQ_MssIngressSaThresholdExpiredStatusRegister_HHD */ -#define bits_AQ_MssIngressSaThresholdExpiredStatusRegister_HHD_mssIngressSaThresholdExpiredMSW u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaThresholdExpiredMSW in AQ_MssIngressSaThresholdExpiredStatusRegister_HHD */ -#define word_AQ_MssIngressSaThresholdExpiredStatusRegister_HHD_mssIngressSaThresholdExpiredMSW u1.word_1 - -/*! \brief Base register address of structure AQ_MssIngressEccInterruptStatusRegister_HHD */ -#define AQ_MssIngressEccInterruptStatusRegister_HHD_baseRegisterAddress 0x803A -/*! \brief MMD address of structure AQ_MssIngressEccInterruptStatusRegister_HHD */ -#define AQ_MssIngressEccInterruptStatusRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaEccErrorInterruptLSW in AQ_MssIngressEccInterruptStatusRegister_HHD */ -#define AQ_MssIngressEccInterruptStatusRegister_HHD_mssIngressSaEccErrorInterruptLSW 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaEccErrorInterruptLSW in AQ_MssIngressEccInterruptStatusRegister_HHD */ -#define bits_AQ_MssIngressEccInterruptStatusRegister_HHD_mssIngressSaEccErrorInterruptLSW u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaEccErrorInterruptLSW in AQ_MssIngressEccInterruptStatusRegister_HHD */ -#define word_AQ_MssIngressEccInterruptStatusRegister_HHD_mssIngressSaEccErrorInterruptLSW u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaEccErrorInterruptMSW in AQ_MssIngressEccInterruptStatusRegister_HHD */ -#define AQ_MssIngressEccInterruptStatusRegister_HHD_mssIngressSaEccErrorInterruptMSW 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaEccErrorInterruptMSW in AQ_MssIngressEccInterruptStatusRegister_HHD */ -#define bits_AQ_MssIngressEccInterruptStatusRegister_HHD_mssIngressSaEccErrorInterruptMSW u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaEccErrorInterruptMSW in AQ_MssIngressEccInterruptStatusRegister_HHD */ -#define word_AQ_MssIngressEccInterruptStatusRegister_HHD_mssIngressSaEccErrorInterruptMSW u1.word_1 - -/*! \brief Base register address of structure AQ_MssIngressLutAddressControlRegister_HHD */ -#define AQ_MssIngressLutAddressControlRegister_HHD_baseRegisterAddress 0x8080 -/*! \brief MMD address of structure AQ_MssIngressLutAddressControlRegister_HHD */ -#define AQ_MssIngressLutAddressControlRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutSelect in AQ_MssIngressLutAddressControlRegister_HHD */ -#define AQ_MssIngressLutAddressControlRegister_HHD_mssIngressLutSelect 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutSelect in AQ_MssIngressLutAddressControlRegister_HHD */ -#define bits_AQ_MssIngressLutAddressControlRegister_HHD_mssIngressLutSelect u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutSelect in AQ_MssIngressLutAddressControlRegister_HHD */ -#define word_AQ_MssIngressLutAddressControlRegister_HHD_mssIngressLutSelect u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutAddress in AQ_MssIngressLutAddressControlRegister_HHD */ -#define AQ_MssIngressLutAddressControlRegister_HHD_mssIngressLutAddress 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutAddress in AQ_MssIngressLutAddressControlRegister_HHD */ -#define bits_AQ_MssIngressLutAddressControlRegister_HHD_mssIngressLutAddress u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutAddress in AQ_MssIngressLutAddressControlRegister_HHD */ -#define word_AQ_MssIngressLutAddressControlRegister_HHD_mssIngressLutAddress u0.word_0 - -/*! \brief Base register address of structure AQ_MssIngressLutControlRegister_HHD */ -#define AQ_MssIngressLutControlRegister_HHD_baseRegisterAddress 0x8081 -/*! \brief MMD address of structure AQ_MssIngressLutControlRegister_HHD */ -#define AQ_MssIngressLutControlRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutWrite in AQ_MssIngressLutControlRegister_HHD */ -#define AQ_MssIngressLutControlRegister_HHD_mssIngressLutWrite 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutWrite in AQ_MssIngressLutControlRegister_HHD */ -#define bits_AQ_MssIngressLutControlRegister_HHD_mssIngressLutWrite u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutWrite in AQ_MssIngressLutControlRegister_HHD */ -#define word_AQ_MssIngressLutControlRegister_HHD_mssIngressLutWrite u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutRead in AQ_MssIngressLutControlRegister_HHD */ -#define AQ_MssIngressLutControlRegister_HHD_mssIngressLutRead 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutRead in AQ_MssIngressLutControlRegister_HHD */ -#define bits_AQ_MssIngressLutControlRegister_HHD_mssIngressLutRead u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutRead in AQ_MssIngressLutControlRegister_HHD */ -#define word_AQ_MssIngressLutControlRegister_HHD_mssIngressLutRead u0.word_0 - -/*! \brief Base register address of structure AQ_MssIngressLutDataControlRegister_HHD */ -#define AQ_MssIngressLutDataControlRegister_HHD_baseRegisterAddress 0x80A0 -/*! \brief MMD address of structure AQ_MssIngressLutDataControlRegister_HHD */ -#define AQ_MssIngressLutDataControlRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_0 in AQ_MssIngressLutDataControlRegister_HHD */ -#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_0 in AQ_MssIngressLutDataControlRegister_HHD */ -#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_0 in AQ_MssIngressLutDataControlRegister_HHD */ -#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_1 in AQ_MssIngressLutDataControlRegister_HHD */ -#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_1 in AQ_MssIngressLutDataControlRegister_HHD */ -#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_1 in AQ_MssIngressLutDataControlRegister_HHD */ -#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_1 u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_2 in AQ_MssIngressLutDataControlRegister_HHD */ -#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_2 2 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_2 in AQ_MssIngressLutDataControlRegister_HHD */ -#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_2 u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_2 in AQ_MssIngressLutDataControlRegister_HHD */ -#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_2 u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_3 in AQ_MssIngressLutDataControlRegister_HHD */ -#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_3 3 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_3 in AQ_MssIngressLutDataControlRegister_HHD */ -#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_3 u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_3 in AQ_MssIngressLutDataControlRegister_HHD */ -#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_3 u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_4 in AQ_MssIngressLutDataControlRegister_HHD */ -#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_4 4 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_4 in AQ_MssIngressLutDataControlRegister_HHD */ -#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_4 u4.bits_4 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_4 in AQ_MssIngressLutDataControlRegister_HHD */ -#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_4 u4.word_4 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_5 in AQ_MssIngressLutDataControlRegister_HHD */ -#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_5 5 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_5 in AQ_MssIngressLutDataControlRegister_HHD */ -#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_5 u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_5 in AQ_MssIngressLutDataControlRegister_HHD */ -#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_5 u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_6 in AQ_MssIngressLutDataControlRegister_HHD */ -#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_6 6 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_6 in AQ_MssIngressLutDataControlRegister_HHD */ -#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_6 u6.bits_6 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_6 in AQ_MssIngressLutDataControlRegister_HHD */ -#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_6 u6.word_6 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_7 in AQ_MssIngressLutDataControlRegister_HHD */ -#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_7 7 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_7 in AQ_MssIngressLutDataControlRegister_HHD */ -#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_7 u7.bits_7 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_7 in AQ_MssIngressLutDataControlRegister_HHD */ -#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_7 u7.word_7 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_8 in AQ_MssIngressLutDataControlRegister_HHD */ -#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_8 8 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_8 in AQ_MssIngressLutDataControlRegister_HHD */ -#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_8 u8.bits_8 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_8 in AQ_MssIngressLutDataControlRegister_HHD */ -#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_8 u8.word_8 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_9 in AQ_MssIngressLutDataControlRegister_HHD */ -#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_9 9 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_9 in AQ_MssIngressLutDataControlRegister_HHD */ -#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_9 u9.bits_9 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_9 in AQ_MssIngressLutDataControlRegister_HHD */ -#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_9 u9.word_9 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_10 in AQ_MssIngressLutDataControlRegister_HHD */ -#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_10 10 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_10 in AQ_MssIngressLutDataControlRegister_HHD */ -#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_10 u10.bits_10 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_10 in AQ_MssIngressLutDataControlRegister_HHD */ -#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_10 u10.word_10 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_11 in AQ_MssIngressLutDataControlRegister_HHD */ -#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_11 11 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_11 in AQ_MssIngressLutDataControlRegister_HHD */ -#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_11 u11.bits_11 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_11 in AQ_MssIngressLutDataControlRegister_HHD */ -#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_11 u11.word_11 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_12 in AQ_MssIngressLutDataControlRegister_HHD */ -#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_12 12 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_12 in AQ_MssIngressLutDataControlRegister_HHD */ -#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_12 u12.bits_12 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_12 in AQ_MssIngressLutDataControlRegister_HHD */ -#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_12 u12.word_12 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_13 in AQ_MssIngressLutDataControlRegister_HHD */ -#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_13 13 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_13 in AQ_MssIngressLutDataControlRegister_HHD */ -#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_13 u13.bits_13 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_13 in AQ_MssIngressLutDataControlRegister_HHD */ -#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_13 u13.word_13 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_14 in AQ_MssIngressLutDataControlRegister_HHD */ -#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_14 14 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_14 in AQ_MssIngressLutDataControlRegister_HHD */ -#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_14 u14.bits_14 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_14 in AQ_MssIngressLutDataControlRegister_HHD */ -#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_14 u14.word_14 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_15 in AQ_MssIngressLutDataControlRegister_HHD */ -#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_15 15 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_15 in AQ_MssIngressLutDataControlRegister_HHD */ -#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_15 u15.bits_15 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_15 in AQ_MssIngressLutDataControlRegister_HHD */ -#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_15 u15.word_15 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_16 in AQ_MssIngressLutDataControlRegister_HHD */ -#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_16 16 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_16 in AQ_MssIngressLutDataControlRegister_HHD */ -#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_16 u16.bits_16 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_16 in AQ_MssIngressLutDataControlRegister_HHD */ -#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_16 u16.word_16 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_17 in AQ_MssIngressLutDataControlRegister_HHD */ -#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_17 17 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_17 in AQ_MssIngressLutDataControlRegister_HHD */ -#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_17 u17.bits_17 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_17 in AQ_MssIngressLutDataControlRegister_HHD */ -#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_17 u17.word_17 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_18 in AQ_MssIngressLutDataControlRegister_HHD */ -#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_18 18 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_18 in AQ_MssIngressLutDataControlRegister_HHD */ -#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_18 u18.bits_18 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_18 in AQ_MssIngressLutDataControlRegister_HHD */ -#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_18 u18.word_18 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_19 in AQ_MssIngressLutDataControlRegister_HHD */ -#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_19 19 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_19 in AQ_MssIngressLutDataControlRegister_HHD */ -#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_19 u19.bits_19 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_19 in AQ_MssIngressLutDataControlRegister_HHD */ -#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_19 u19.word_19 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_20 in AQ_MssIngressLutDataControlRegister_HHD */ -#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_20 20 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_20 in AQ_MssIngressLutDataControlRegister_HHD */ -#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_20 u20.bits_20 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_20 in AQ_MssIngressLutDataControlRegister_HHD */ -#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_20 u20.word_20 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_21 in AQ_MssIngressLutDataControlRegister_HHD */ -#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_21 21 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_21 in AQ_MssIngressLutDataControlRegister_HHD */ -#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_21 u21.bits_21 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_21 in AQ_MssIngressLutDataControlRegister_HHD */ -#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_21 u21.word_21 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_22 in AQ_MssIngressLutDataControlRegister_HHD */ -#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_22 22 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_22 in AQ_MssIngressLutDataControlRegister_HHD */ -#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_22 u22.bits_22 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_22 in AQ_MssIngressLutDataControlRegister_HHD */ -#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_22 u22.word_22 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_23 in AQ_MssIngressLutDataControlRegister_HHD */ -#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_23 23 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_23 in AQ_MssIngressLutDataControlRegister_HHD */ -#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_23 u23.bits_23 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_23 in AQ_MssIngressLutDataControlRegister_HHD */ -#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_23 u23.word_23 - -/*! \brief Base register address of structure AQ_MsmLineGeneralControlRegister_HHD */ -#define AQ_MsmLineGeneralControlRegister_HHD_baseRegisterAddress 0x9004 -/*! \brief MMD address of structure AQ_MsmLineGeneralControlRegister_HHD */ -#define AQ_MsmLineGeneralControlRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmLinePhyTxEnable in AQ_MsmLineGeneralControlRegister_HHD */ -#define AQ_MsmLineGeneralControlRegister_HHD_msmLinePhyTxEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLinePhyTxEnable in AQ_MsmLineGeneralControlRegister_HHD */ -#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLinePhyTxEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLinePhyTxEnable in AQ_MsmLineGeneralControlRegister_HHD */ -#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLinePhyTxEnable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxErrorDiscard in AQ_MsmLineGeneralControlRegister_HHD */ -#define AQ_MsmLineGeneralControlRegister_HHD_msmLineRxErrorDiscard 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxErrorDiscard in AQ_MsmLineGeneralControlRegister_HHD */ -#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineRxErrorDiscard u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxErrorDiscard in AQ_MsmLineGeneralControlRegister_HHD */ -#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineRxErrorDiscard u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineControlFrameEnable in AQ_MsmLineGeneralControlRegister_HHD */ -#define AQ_MsmLineGeneralControlRegister_HHD_msmLineControlFrameEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineControlFrameEnable in AQ_MsmLineGeneralControlRegister_HHD */ -#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineControlFrameEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineControlFrameEnable in AQ_MsmLineGeneralControlRegister_HHD */ -#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineControlFrameEnable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineSoftReset in AQ_MsmLineGeneralControlRegister_HHD */ -#define AQ_MsmLineGeneralControlRegister_HHD_msmLineSoftReset 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineSoftReset in AQ_MsmLineGeneralControlRegister_HHD */ -#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineSoftReset u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineSoftReset in AQ_MsmLineGeneralControlRegister_HHD */ -#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineSoftReset u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxPadEnable in AQ_MsmLineGeneralControlRegister_HHD */ -#define AQ_MsmLineGeneralControlRegister_HHD_msmLineTxPadEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxPadEnable in AQ_MsmLineGeneralControlRegister_HHD */ -#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineTxPadEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxPadEnable in AQ_MsmLineGeneralControlRegister_HHD */ -#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineTxPadEnable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxCrcAppend in AQ_MsmLineGeneralControlRegister_HHD */ -#define AQ_MsmLineGeneralControlRegister_HHD_msmLineTxCrcAppend 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxCrcAppend in AQ_MsmLineGeneralControlRegister_HHD */ -#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineTxCrcAppend u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxCrcAppend in AQ_MsmLineGeneralControlRegister_HHD */ -#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineTxCrcAppend u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxAddressInsertEnable in AQ_MsmLineGeneralControlRegister_HHD */ -#define AQ_MsmLineGeneralControlRegister_HHD_msmLineTxAddressInsertEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxAddressInsertEnable in AQ_MsmLineGeneralControlRegister_HHD */ -#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineTxAddressInsertEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxAddressInsertEnable in AQ_MsmLineGeneralControlRegister_HHD */ -#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineTxAddressInsertEnable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLinePauseIgnore in AQ_MsmLineGeneralControlRegister_HHD */ -#define AQ_MsmLineGeneralControlRegister_HHD_msmLinePauseIgnore 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLinePauseIgnore in AQ_MsmLineGeneralControlRegister_HHD */ -#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLinePauseIgnore u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLinePauseIgnore in AQ_MsmLineGeneralControlRegister_HHD */ -#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLinePauseIgnore u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLinePauseForward in AQ_MsmLineGeneralControlRegister_HHD */ -#define AQ_MsmLineGeneralControlRegister_HHD_msmLinePauseForward 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLinePauseForward in AQ_MsmLineGeneralControlRegister_HHD */ -#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLinePauseForward u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLinePauseForward in AQ_MsmLineGeneralControlRegister_HHD */ -#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLinePauseForward u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineCrcForward in AQ_MsmLineGeneralControlRegister_HHD */ -#define AQ_MsmLineGeneralControlRegister_HHD_msmLineCrcForward 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineCrcForward in AQ_MsmLineGeneralControlRegister_HHD */ -#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineCrcForward u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineCrcForward in AQ_MsmLineGeneralControlRegister_HHD */ -#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineCrcForward u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLinePadEnable in AQ_MsmLineGeneralControlRegister_HHD */ -#define AQ_MsmLineGeneralControlRegister_HHD_msmLinePadEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLinePadEnable in AQ_MsmLineGeneralControlRegister_HHD */ -#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLinePadEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLinePadEnable in AQ_MsmLineGeneralControlRegister_HHD */ -#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLinePadEnable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLinePromiscuousMode in AQ_MsmLineGeneralControlRegister_HHD */ -#define AQ_MsmLineGeneralControlRegister_HHD_msmLinePromiscuousMode 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLinePromiscuousMode in AQ_MsmLineGeneralControlRegister_HHD */ -#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLinePromiscuousMode u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLinePromiscuousMode in AQ_MsmLineGeneralControlRegister_HHD */ -#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLinePromiscuousMode u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineWanMode in AQ_MsmLineGeneralControlRegister_HHD */ -#define AQ_MsmLineGeneralControlRegister_HHD_msmLineWanMode 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineWanMode in AQ_MsmLineGeneralControlRegister_HHD */ -#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineWanMode u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineWanMode in AQ_MsmLineGeneralControlRegister_HHD */ -#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineWanMode u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxEnable in AQ_MsmLineGeneralControlRegister_HHD */ -#define AQ_MsmLineGeneralControlRegister_HHD_msmLineRxEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxEnable in AQ_MsmLineGeneralControlRegister_HHD */ -#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineRxEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxEnable in AQ_MsmLineGeneralControlRegister_HHD */ -#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineRxEnable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxEnable in AQ_MsmLineGeneralControlRegister_HHD */ -#define AQ_MsmLineGeneralControlRegister_HHD_msmLineTxEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxEnable in AQ_MsmLineGeneralControlRegister_HHD */ -#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineTxEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxEnable in AQ_MsmLineGeneralControlRegister_HHD */ -#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineTxEnable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxLowPowerIdleEnable in AQ_MsmLineGeneralControlRegister_HHD */ -#define AQ_MsmLineGeneralControlRegister_HHD_msmLineTxLowPowerIdleEnable 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxLowPowerIdleEnable in AQ_MsmLineGeneralControlRegister_HHD */ -#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineTxLowPowerIdleEnable u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxLowPowerIdleEnable in AQ_MsmLineGeneralControlRegister_HHD */ -#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineTxLowPowerIdleEnable u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineSfdCheckDisable in AQ_MsmLineGeneralControlRegister_HHD */ -#define AQ_MsmLineGeneralControlRegister_HHD_msmLineSfdCheckDisable 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineSfdCheckDisable in AQ_MsmLineGeneralControlRegister_HHD */ -#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineSfdCheckDisable u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineSfdCheckDisable in AQ_MsmLineGeneralControlRegister_HHD */ -#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineSfdCheckDisable u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure msmLinePriorityFlowControlEnable in AQ_MsmLineGeneralControlRegister_HHD */ -#define AQ_MsmLineGeneralControlRegister_HHD_msmLinePriorityFlowControlEnable 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLinePriorityFlowControlEnable in AQ_MsmLineGeneralControlRegister_HHD */ -#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLinePriorityFlowControlEnable u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmLinePriorityFlowControlEnable in AQ_MsmLineGeneralControlRegister_HHD */ -#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLinePriorityFlowControlEnable u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineIdleColumnCountExtend in AQ_MsmLineGeneralControlRegister_HHD */ -#define AQ_MsmLineGeneralControlRegister_HHD_msmLineIdleColumnCountExtend 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineIdleColumnCountExtend in AQ_MsmLineGeneralControlRegister_HHD */ -#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineIdleColumnCountExtend u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineIdleColumnCountExtend in AQ_MsmLineGeneralControlRegister_HHD */ -#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineIdleColumnCountExtend u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineLengthCheckDisable in AQ_MsmLineGeneralControlRegister_HHD */ -#define AQ_MsmLineGeneralControlRegister_HHD_msmLineLengthCheckDisable 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineLengthCheckDisable in AQ_MsmLineGeneralControlRegister_HHD */ -#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineLengthCheckDisable u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineLengthCheckDisable in AQ_MsmLineGeneralControlRegister_HHD */ -#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineLengthCheckDisable u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineForceSendIdle in AQ_MsmLineGeneralControlRegister_HHD */ -#define AQ_MsmLineGeneralControlRegister_HHD_msmLineForceSendIdle 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineForceSendIdle in AQ_MsmLineGeneralControlRegister_HHD */ -#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineForceSendIdle u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineForceSendIdle in AQ_MsmLineGeneralControlRegister_HHD */ -#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineForceSendIdle u1.word_1 - -/*! \brief Base register address of structure AQ_MsmLineFifoControlRegister_HHD */ -#define AQ_MsmLineFifoControlRegister_HHD_baseRegisterAddress 0x900E -/*! \brief MMD address of structure AQ_MsmLineFifoControlRegister_HHD */ -#define AQ_MsmLineFifoControlRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxFifoFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ -#define AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoFullThreshold 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxFifoFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ -#define bits_AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoFullThreshold u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxFifoFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ -#define word_AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoFullThreshold u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxFifoEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ -#define AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoEmptyThreshold 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxFifoEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ -#define bits_AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoEmptyThreshold u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxFifoEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ -#define word_AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoEmptyThreshold u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxFifoFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ -#define AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoFullThreshold 2 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxFifoFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ -#define bits_AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoFullThreshold u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxFifoFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ -#define word_AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoFullThreshold u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxFifoEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ -#define AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoEmptyThreshold 3 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxFifoEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ -#define bits_AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoEmptyThreshold u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxFifoEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ -#define word_AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoEmptyThreshold u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxFifoAlmostFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ -#define AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoAlmostFullThreshold 4 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxFifoAlmostFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ -#define bits_AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoAlmostFullThreshold u4.bits_4 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxFifoAlmostFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ -#define word_AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoAlmostFullThreshold u4.word_4 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxFifoAlmostEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ -#define AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoAlmostEmptyThreshold 5 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxFifoAlmostEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ -#define bits_AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoAlmostEmptyThreshold u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxFifoAlmostEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ -#define word_AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoAlmostEmptyThreshold u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxFifoAlmostFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ -#define AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoAlmostFullThreshold 6 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxFifoAlmostFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ -#define bits_AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoAlmostFullThreshold u6.bits_6 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxFifoAlmostFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ -#define word_AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoAlmostFullThreshold u6.word_6 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxFifoAlmostEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ -#define AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoAlmostEmptyThreshold 7 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxFifoAlmostEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ -#define bits_AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoAlmostEmptyThreshold u7.bits_7 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxFifoAlmostEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ -#define word_AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoAlmostEmptyThreshold u7.word_7 - -/*! \brief Base register address of structure AQ_MsmLineGeneralStatusRegister_HHD */ -#define AQ_MsmLineGeneralStatusRegister_HHD_baseRegisterAddress 0x9020 -/*! \brief MMD address of structure AQ_MsmLineGeneralStatusRegister_HHD */ -#define AQ_MsmLineGeneralStatusRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxFifoEmpty in AQ_MsmLineGeneralStatusRegister_HHD */ -#define AQ_MsmLineGeneralStatusRegister_HHD_msmLineTxFifoEmpty 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxFifoEmpty in AQ_MsmLineGeneralStatusRegister_HHD */ -#define bits_AQ_MsmLineGeneralStatusRegister_HHD_msmLineTxFifoEmpty u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxFifoEmpty in AQ_MsmLineGeneralStatusRegister_HHD */ -#define word_AQ_MsmLineGeneralStatusRegister_HHD_msmLineTxFifoEmpty u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxLowPowerIdle in AQ_MsmLineGeneralStatusRegister_HHD */ -#define AQ_MsmLineGeneralStatusRegister_HHD_msmLineRxLowPowerIdle 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxLowPowerIdle in AQ_MsmLineGeneralStatusRegister_HHD */ -#define bits_AQ_MsmLineGeneralStatusRegister_HHD_msmLineRxLowPowerIdle u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxLowPowerIdle in AQ_MsmLineGeneralStatusRegister_HHD */ -#define word_AQ_MsmLineGeneralStatusRegister_HHD_msmLineRxLowPowerIdle u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineTimestampAvailable in AQ_MsmLineGeneralStatusRegister_HHD */ -#define AQ_MsmLineGeneralStatusRegister_HHD_msmLineTimestampAvailable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTimestampAvailable in AQ_MsmLineGeneralStatusRegister_HHD */ -#define bits_AQ_MsmLineGeneralStatusRegister_HHD_msmLineTimestampAvailable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineTimestampAvailable in AQ_MsmLineGeneralStatusRegister_HHD */ -#define word_AQ_MsmLineGeneralStatusRegister_HHD_msmLineTimestampAvailable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLinePhyLossOfSignal in AQ_MsmLineGeneralStatusRegister_HHD */ -#define AQ_MsmLineGeneralStatusRegister_HHD_msmLinePhyLossOfSignal 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLinePhyLossOfSignal in AQ_MsmLineGeneralStatusRegister_HHD */ -#define bits_AQ_MsmLineGeneralStatusRegister_HHD_msmLinePhyLossOfSignal u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLinePhyLossOfSignal in AQ_MsmLineGeneralStatusRegister_HHD */ -#define word_AQ_MsmLineGeneralStatusRegister_HHD_msmLinePhyLossOfSignal u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxRemoteFault in AQ_MsmLineGeneralStatusRegister_HHD */ -#define AQ_MsmLineGeneralStatusRegister_HHD_msmLineRxRemoteFault 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxRemoteFault in AQ_MsmLineGeneralStatusRegister_HHD */ -#define bits_AQ_MsmLineGeneralStatusRegister_HHD_msmLineRxRemoteFault u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxRemoteFault in AQ_MsmLineGeneralStatusRegister_HHD */ -#define word_AQ_MsmLineGeneralStatusRegister_HHD_msmLineRxRemoteFault u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxLocalFault in AQ_MsmLineGeneralStatusRegister_HHD */ -#define AQ_MsmLineGeneralStatusRegister_HHD_msmLineRxLocalFault 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxLocalFault in AQ_MsmLineGeneralStatusRegister_HHD */ -#define bits_AQ_MsmLineGeneralStatusRegister_HHD_msmLineRxLocalFault u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxLocalFault in AQ_MsmLineGeneralStatusRegister_HHD */ -#define word_AQ_MsmLineGeneralStatusRegister_HHD_msmLineRxLocalFault u0.word_0 - -/*! \brief Base register address of structure AQ_MsmLineTxIpgControlRegister_HHD */ -#define AQ_MsmLineTxIpgControlRegister_HHD_baseRegisterAddress 0x9022 -/*! \brief MMD address of structure AQ_MsmLineTxIpgControlRegister_HHD */ -#define AQ_MsmLineTxIpgControlRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxIpgLength in AQ_MsmLineTxIpgControlRegister_HHD */ -#define AQ_MsmLineTxIpgControlRegister_HHD_msmLineTxIpgLength 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxIpgLength in AQ_MsmLineTxIpgControlRegister_HHD */ -#define bits_AQ_MsmLineTxIpgControlRegister_HHD_msmLineTxIpgLength u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxIpgLength in AQ_MsmLineTxIpgControlRegister_HHD */ -#define word_AQ_MsmLineTxIpgControlRegister_HHD_msmLineTxIpgLength u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxIpgReserved in AQ_MsmLineTxIpgControlRegister_HHD */ -#define AQ_MsmLineTxIpgControlRegister_HHD_msmLineTxIpgReserved 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxIpgReserved in AQ_MsmLineTxIpgControlRegister_HHD */ -#define bits_AQ_MsmLineTxIpgControlRegister_HHD_msmLineTxIpgReserved u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxIpgReserved in AQ_MsmLineTxIpgControlRegister_HHD */ -#define word_AQ_MsmLineTxIpgControlRegister_HHD_msmLineTxIpgReserved u1.word_1 - -/*! \brief Base register address of structure AQ_MsmLineTxGoodFramesCounterRegister_HHD */ -#define AQ_MsmLineTxGoodFramesCounterRegister_HHD_baseRegisterAddress 0x9040 -/*! \brief MMD address of structure AQ_MsmLineTxGoodFramesCounterRegister_HHD */ -#define AQ_MsmLineTxGoodFramesCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxGoodFramesCounter_0 in AQ_MsmLineTxGoodFramesCounterRegister_HHD */ -#define AQ_MsmLineTxGoodFramesCounterRegister_HHD_msmLineTxGoodFramesCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxGoodFramesCounter_0 in AQ_MsmLineTxGoodFramesCounterRegister_HHD */ -#define bits_AQ_MsmLineTxGoodFramesCounterRegister_HHD_msmLineTxGoodFramesCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxGoodFramesCounter_0 in AQ_MsmLineTxGoodFramesCounterRegister_HHD */ -#define word_AQ_MsmLineTxGoodFramesCounterRegister_HHD_msmLineTxGoodFramesCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxGoodFramesCounter_1 in AQ_MsmLineTxGoodFramesCounterRegister_HHD */ -#define AQ_MsmLineTxGoodFramesCounterRegister_HHD_msmLineTxGoodFramesCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxGoodFramesCounter_1 in AQ_MsmLineTxGoodFramesCounterRegister_HHD */ -#define bits_AQ_MsmLineTxGoodFramesCounterRegister_HHD_msmLineTxGoodFramesCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxGoodFramesCounter_1 in AQ_MsmLineTxGoodFramesCounterRegister_HHD */ -#define word_AQ_MsmLineTxGoodFramesCounterRegister_HHD_msmLineTxGoodFramesCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmLineRxGoodFramesCounterRegister_HHD */ -#define AQ_MsmLineRxGoodFramesCounterRegister_HHD_baseRegisterAddress 0x9044 -/*! \brief MMD address of structure AQ_MsmLineRxGoodFramesCounterRegister_HHD */ -#define AQ_MsmLineRxGoodFramesCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxGoodFramesCounter_0 in AQ_MsmLineRxGoodFramesCounterRegister_HHD */ -#define AQ_MsmLineRxGoodFramesCounterRegister_HHD_msmLineRxGoodFramesCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxGoodFramesCounter_0 in AQ_MsmLineRxGoodFramesCounterRegister_HHD */ -#define bits_AQ_MsmLineRxGoodFramesCounterRegister_HHD_msmLineRxGoodFramesCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxGoodFramesCounter_0 in AQ_MsmLineRxGoodFramesCounterRegister_HHD */ -#define word_AQ_MsmLineRxGoodFramesCounterRegister_HHD_msmLineRxGoodFramesCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxGoodFramesCounter_1 in AQ_MsmLineRxGoodFramesCounterRegister_HHD */ -#define AQ_MsmLineRxGoodFramesCounterRegister_HHD_msmLineRxGoodFramesCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxGoodFramesCounter_1 in AQ_MsmLineRxGoodFramesCounterRegister_HHD */ -#define bits_AQ_MsmLineRxGoodFramesCounterRegister_HHD_msmLineRxGoodFramesCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxGoodFramesCounter_1 in AQ_MsmLineRxGoodFramesCounterRegister_HHD */ -#define word_AQ_MsmLineRxGoodFramesCounterRegister_HHD_msmLineRxGoodFramesCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmLineRxFcsErrorsCounterRegister_HHD */ -#define AQ_MsmLineRxFcsErrorsCounterRegister_HHD_baseRegisterAddress 0x9048 -/*! \brief MMD address of structure AQ_MsmLineRxFcsErrorsCounterRegister_HHD */ -#define AQ_MsmLineRxFcsErrorsCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmLineFcsErrorCounter_0 in AQ_MsmLineRxFcsErrorsCounterRegister_HHD */ -#define AQ_MsmLineRxFcsErrorsCounterRegister_HHD_msmLineFcsErrorCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineFcsErrorCounter_0 in AQ_MsmLineRxFcsErrorsCounterRegister_HHD */ -#define bits_AQ_MsmLineRxFcsErrorsCounterRegister_HHD_msmLineFcsErrorCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineFcsErrorCounter_0 in AQ_MsmLineRxFcsErrorsCounterRegister_HHD */ -#define word_AQ_MsmLineRxFcsErrorsCounterRegister_HHD_msmLineFcsErrorCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineFcsErrorCounter_1 in AQ_MsmLineRxFcsErrorsCounterRegister_HHD */ -#define AQ_MsmLineRxFcsErrorsCounterRegister_HHD_msmLineFcsErrorCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineFcsErrorCounter_1 in AQ_MsmLineRxFcsErrorsCounterRegister_HHD */ -#define bits_AQ_MsmLineRxFcsErrorsCounterRegister_HHD_msmLineFcsErrorCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineFcsErrorCounter_1 in AQ_MsmLineRxFcsErrorsCounterRegister_HHD */ -#define word_AQ_MsmLineRxFcsErrorsCounterRegister_HHD_msmLineFcsErrorCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD */ -#define AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD_baseRegisterAddress 0x904C -/*! \brief MMD address of structure AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD */ -#define AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmLineAlignmentErrorCounter_0 in AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD */ -#define AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD_msmLineAlignmentErrorCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineAlignmentErrorCounter_0 in AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD */ -#define bits_AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD_msmLineAlignmentErrorCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineAlignmentErrorCounter_0 in AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD */ -#define word_AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD_msmLineAlignmentErrorCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineAlignmentErrorCounter_1 in AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD */ -#define AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD_msmLineAlignmentErrorCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineAlignmentErrorCounter_1 in AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD */ -#define bits_AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD_msmLineAlignmentErrorCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineAlignmentErrorCounter_1 in AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD */ -#define word_AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD_msmLineAlignmentErrorCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmLineTxPauseFramesCounterRegister_HHD */ -#define AQ_MsmLineTxPauseFramesCounterRegister_HHD_baseRegisterAddress 0x9050 -/*! \brief MMD address of structure AQ_MsmLineTxPauseFramesCounterRegister_HHD */ -#define AQ_MsmLineTxPauseFramesCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxPauseFramesCounter_0 in AQ_MsmLineTxPauseFramesCounterRegister_HHD */ -#define AQ_MsmLineTxPauseFramesCounterRegister_HHD_msmLineTxPauseFramesCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxPauseFramesCounter_0 in AQ_MsmLineTxPauseFramesCounterRegister_HHD */ -#define bits_AQ_MsmLineTxPauseFramesCounterRegister_HHD_msmLineTxPauseFramesCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxPauseFramesCounter_0 in AQ_MsmLineTxPauseFramesCounterRegister_HHD */ -#define word_AQ_MsmLineTxPauseFramesCounterRegister_HHD_msmLineTxPauseFramesCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxPauseFramesCounter_1 in AQ_MsmLineTxPauseFramesCounterRegister_HHD */ -#define AQ_MsmLineTxPauseFramesCounterRegister_HHD_msmLineTxPauseFramesCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxPauseFramesCounter_1 in AQ_MsmLineTxPauseFramesCounterRegister_HHD */ -#define bits_AQ_MsmLineTxPauseFramesCounterRegister_HHD_msmLineTxPauseFramesCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxPauseFramesCounter_1 in AQ_MsmLineTxPauseFramesCounterRegister_HHD */ -#define word_AQ_MsmLineTxPauseFramesCounterRegister_HHD_msmLineTxPauseFramesCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmLineRxPauseFramesCounterRegister_HHD */ -#define AQ_MsmLineRxPauseFramesCounterRegister_HHD_baseRegisterAddress 0x9054 -/*! \brief MMD address of structure AQ_MsmLineRxPauseFramesCounterRegister_HHD */ -#define AQ_MsmLineRxPauseFramesCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxPauseFramesCounter_0 in AQ_MsmLineRxPauseFramesCounterRegister_HHD */ -#define AQ_MsmLineRxPauseFramesCounterRegister_HHD_msmLineRxPauseFramesCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxPauseFramesCounter_0 in AQ_MsmLineRxPauseFramesCounterRegister_HHD */ -#define bits_AQ_MsmLineRxPauseFramesCounterRegister_HHD_msmLineRxPauseFramesCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxPauseFramesCounter_0 in AQ_MsmLineRxPauseFramesCounterRegister_HHD */ -#define word_AQ_MsmLineRxPauseFramesCounterRegister_HHD_msmLineRxPauseFramesCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxPauseFramesCounter_1 in AQ_MsmLineRxPauseFramesCounterRegister_HHD */ -#define AQ_MsmLineRxPauseFramesCounterRegister_HHD_msmLineRxPauseFramesCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxPauseFramesCounter_1 in AQ_MsmLineRxPauseFramesCounterRegister_HHD */ -#define bits_AQ_MsmLineRxPauseFramesCounterRegister_HHD_msmLineRxPauseFramesCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxPauseFramesCounter_1 in AQ_MsmLineRxPauseFramesCounterRegister_HHD */ -#define word_AQ_MsmLineRxPauseFramesCounterRegister_HHD_msmLineRxPauseFramesCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmLineRxTooLongErrorsCounterRegister_HHD */ -#define AQ_MsmLineRxTooLongErrorsCounterRegister_HHD_baseRegisterAddress 0x9058 -/*! \brief MMD address of structure AQ_MsmLineRxTooLongErrorsCounterRegister_HHD */ -#define AQ_MsmLineRxTooLongErrorsCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxTooLongErrorsCounter_0 in AQ_MsmLineRxTooLongErrorsCounterRegister_HHD */ -#define AQ_MsmLineRxTooLongErrorsCounterRegister_HHD_msmLineRxTooLongErrorsCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxTooLongErrorsCounter_0 in AQ_MsmLineRxTooLongErrorsCounterRegister_HHD */ -#define bits_AQ_MsmLineRxTooLongErrorsCounterRegister_HHD_msmLineRxTooLongErrorsCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxTooLongErrorsCounter_0 in AQ_MsmLineRxTooLongErrorsCounterRegister_HHD */ -#define word_AQ_MsmLineRxTooLongErrorsCounterRegister_HHD_msmLineRxTooLongErrorsCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxTooLongErrorsCounter_1 in AQ_MsmLineRxTooLongErrorsCounterRegister_HHD */ -#define AQ_MsmLineRxTooLongErrorsCounterRegister_HHD_msmLineRxTooLongErrorsCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxTooLongErrorsCounter_1 in AQ_MsmLineRxTooLongErrorsCounterRegister_HHD */ -#define bits_AQ_MsmLineRxTooLongErrorsCounterRegister_HHD_msmLineRxTooLongErrorsCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxTooLongErrorsCounter_1 in AQ_MsmLineRxTooLongErrorsCounterRegister_HHD */ -#define word_AQ_MsmLineRxTooLongErrorsCounterRegister_HHD_msmLineRxTooLongErrorsCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD */ -#define AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD_baseRegisterAddress 0x905C -/*! \brief MMD address of structure AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD */ -#define AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxInRangeLengthErrorsCounter_0 in AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD */ -#define AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD_msmLineRxInRangeLengthErrorsCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxInRangeLengthErrorsCounter_0 in AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD */ -#define bits_AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD_msmLineRxInRangeLengthErrorsCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxInRangeLengthErrorsCounter_0 in AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD */ -#define word_AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD_msmLineRxInRangeLengthErrorsCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxInRangeLengthErrorsCounter_1 in AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD */ -#define AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD_msmLineRxInRangeLengthErrorsCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxInRangeLengthErrorsCounter_1 in AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD */ -#define bits_AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD_msmLineRxInRangeLengthErrorsCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxInRangeLengthErrorsCounter_1 in AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD */ -#define word_AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD_msmLineRxInRangeLengthErrorsCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmLineTxVlanFramesCounterRegister_HHD */ -#define AQ_MsmLineTxVlanFramesCounterRegister_HHD_baseRegisterAddress 0x9060 -/*! \brief MMD address of structure AQ_MsmLineTxVlanFramesCounterRegister_HHD */ -#define AQ_MsmLineTxVlanFramesCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxVlanFramesCounter_0 in AQ_MsmLineTxVlanFramesCounterRegister_HHD */ -#define AQ_MsmLineTxVlanFramesCounterRegister_HHD_msmLineTxVlanFramesCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxVlanFramesCounter_0 in AQ_MsmLineTxVlanFramesCounterRegister_HHD */ -#define bits_AQ_MsmLineTxVlanFramesCounterRegister_HHD_msmLineTxVlanFramesCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxVlanFramesCounter_0 in AQ_MsmLineTxVlanFramesCounterRegister_HHD */ -#define word_AQ_MsmLineTxVlanFramesCounterRegister_HHD_msmLineTxVlanFramesCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxVlanFramesCounter_1 in AQ_MsmLineTxVlanFramesCounterRegister_HHD */ -#define AQ_MsmLineTxVlanFramesCounterRegister_HHD_msmLineTxVlanFramesCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxVlanFramesCounter_1 in AQ_MsmLineTxVlanFramesCounterRegister_HHD */ -#define bits_AQ_MsmLineTxVlanFramesCounterRegister_HHD_msmLineTxVlanFramesCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxVlanFramesCounter_1 in AQ_MsmLineTxVlanFramesCounterRegister_HHD */ -#define word_AQ_MsmLineTxVlanFramesCounterRegister_HHD_msmLineTxVlanFramesCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmLineRxVlanFramesCounterRegister_HHD */ -#define AQ_MsmLineRxVlanFramesCounterRegister_HHD_baseRegisterAddress 0x9064 -/*! \brief MMD address of structure AQ_MsmLineRxVlanFramesCounterRegister_HHD */ -#define AQ_MsmLineRxVlanFramesCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxVlanFramesCounter_0 in AQ_MsmLineRxVlanFramesCounterRegister_HHD */ -#define AQ_MsmLineRxVlanFramesCounterRegister_HHD_msmLineRxVlanFramesCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxVlanFramesCounter_0 in AQ_MsmLineRxVlanFramesCounterRegister_HHD */ -#define bits_AQ_MsmLineRxVlanFramesCounterRegister_HHD_msmLineRxVlanFramesCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxVlanFramesCounter_0 in AQ_MsmLineRxVlanFramesCounterRegister_HHD */ -#define word_AQ_MsmLineRxVlanFramesCounterRegister_HHD_msmLineRxVlanFramesCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxVlanFramesCounter_1 in AQ_MsmLineRxVlanFramesCounterRegister_HHD */ -#define AQ_MsmLineRxVlanFramesCounterRegister_HHD_msmLineRxVlanFramesCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxVlanFramesCounter_1 in AQ_MsmLineRxVlanFramesCounterRegister_HHD */ -#define bits_AQ_MsmLineRxVlanFramesCounterRegister_HHD_msmLineRxVlanFramesCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxVlanFramesCounter_1 in AQ_MsmLineRxVlanFramesCounterRegister_HHD */ -#define word_AQ_MsmLineRxVlanFramesCounterRegister_HHD_msmLineRxVlanFramesCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmLineTxOctetsCounterRegister_HHD */ -#define AQ_MsmLineTxOctetsCounterRegister_HHD_baseRegisterAddress 0x9068 -/*! \brief MMD address of structure AQ_MsmLineTxOctetsCounterRegister_HHD */ -#define AQ_MsmLineTxOctetsCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxOctetsCounter_0 in AQ_MsmLineTxOctetsCounterRegister_HHD */ -#define AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxOctetsCounter_0 in AQ_MsmLineTxOctetsCounterRegister_HHD */ -#define bits_AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxOctetsCounter_0 in AQ_MsmLineTxOctetsCounterRegister_HHD */ -#define word_AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxOctetsCounter_1 in AQ_MsmLineTxOctetsCounterRegister_HHD */ -#define AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxOctetsCounter_1 in AQ_MsmLineTxOctetsCounterRegister_HHD */ -#define bits_AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxOctetsCounter_1 in AQ_MsmLineTxOctetsCounterRegister_HHD */ -#define word_AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_1 u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxOctetsCounter_2 in AQ_MsmLineTxOctetsCounterRegister_HHD */ -#define AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_2 2 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxOctetsCounter_2 in AQ_MsmLineTxOctetsCounterRegister_HHD */ -#define bits_AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_2 u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxOctetsCounter_2 in AQ_MsmLineTxOctetsCounterRegister_HHD */ -#define word_AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_2 u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxOctetsCounter_3 in AQ_MsmLineTxOctetsCounterRegister_HHD */ -#define AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_3 3 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxOctetsCounter_3 in AQ_MsmLineTxOctetsCounterRegister_HHD */ -#define bits_AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_3 u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxOctetsCounter_3 in AQ_MsmLineTxOctetsCounterRegister_HHD */ -#define word_AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_3 u3.word_3 - -/*! \brief Base register address of structure AQ_MsmLineRxOctetsCounterRegister_HHD */ -#define AQ_MsmLineRxOctetsCounterRegister_HHD_baseRegisterAddress 0x906C -/*! \brief MMD address of structure AQ_MsmLineRxOctetsCounterRegister_HHD */ -#define AQ_MsmLineRxOctetsCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxOctetsCounter_0 in AQ_MsmLineRxOctetsCounterRegister_HHD */ -#define AQ_MsmLineRxOctetsCounterRegister_HHD_msmLineRxOctetsCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxOctetsCounter_0 in AQ_MsmLineRxOctetsCounterRegister_HHD */ -#define bits_AQ_MsmLineRxOctetsCounterRegister_HHD_msmLineRxOctetsCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxOctetsCounter_0 in AQ_MsmLineRxOctetsCounterRegister_HHD */ -#define word_AQ_MsmLineRxOctetsCounterRegister_HHD_msmLineRxOctetsCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxOctetsCounter_1 in AQ_MsmLineRxOctetsCounterRegister_HHD */ -#define AQ_MsmLineRxOctetsCounterRegister_HHD_msmLineRxOctetsCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxOctetsCounter_1 in AQ_MsmLineRxOctetsCounterRegister_HHD */ -#define bits_AQ_MsmLineRxOctetsCounterRegister_HHD_msmLineRxOctetsCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxOctetsCounter_1 in AQ_MsmLineRxOctetsCounterRegister_HHD */ -#define word_AQ_MsmLineRxOctetsCounterRegister_HHD_msmLineRxOctetsCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmLineRxUnicastFramesCounterRegister_HHD */ -#define AQ_MsmLineRxUnicastFramesCounterRegister_HHD_baseRegisterAddress 0x9070 -/*! \brief MMD address of structure AQ_MsmLineRxUnicastFramesCounterRegister_HHD */ -#define AQ_MsmLineRxUnicastFramesCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxUnicastFramesCounter_0 in AQ_MsmLineRxUnicastFramesCounterRegister_HHD */ -#define AQ_MsmLineRxUnicastFramesCounterRegister_HHD_msmLineRxUnicastFramesCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxUnicastFramesCounter_0 in AQ_MsmLineRxUnicastFramesCounterRegister_HHD */ -#define bits_AQ_MsmLineRxUnicastFramesCounterRegister_HHD_msmLineRxUnicastFramesCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxUnicastFramesCounter_0 in AQ_MsmLineRxUnicastFramesCounterRegister_HHD */ -#define word_AQ_MsmLineRxUnicastFramesCounterRegister_HHD_msmLineRxUnicastFramesCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxUnicastFramesCounter_1 in AQ_MsmLineRxUnicastFramesCounterRegister_HHD */ -#define AQ_MsmLineRxUnicastFramesCounterRegister_HHD_msmLineRxUnicastFramesCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxUnicastFramesCounter_1 in AQ_MsmLineRxUnicastFramesCounterRegister_HHD */ -#define bits_AQ_MsmLineRxUnicastFramesCounterRegister_HHD_msmLineRxUnicastFramesCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxUnicastFramesCounter_1 in AQ_MsmLineRxUnicastFramesCounterRegister_HHD */ -#define word_AQ_MsmLineRxUnicastFramesCounterRegister_HHD_msmLineRxUnicastFramesCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmLineRxMulticastFramesCounterRegister_HHD */ -#define AQ_MsmLineRxMulticastFramesCounterRegister_HHD_baseRegisterAddress 0x9074 -/*! \brief MMD address of structure AQ_MsmLineRxMulticastFramesCounterRegister_HHD */ -#define AQ_MsmLineRxMulticastFramesCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxMulticastFramesCounter_0 in AQ_MsmLineRxMulticastFramesCounterRegister_HHD */ -#define AQ_MsmLineRxMulticastFramesCounterRegister_HHD_msmLineRxMulticastFramesCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxMulticastFramesCounter_0 in AQ_MsmLineRxMulticastFramesCounterRegister_HHD */ -#define bits_AQ_MsmLineRxMulticastFramesCounterRegister_HHD_msmLineRxMulticastFramesCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxMulticastFramesCounter_0 in AQ_MsmLineRxMulticastFramesCounterRegister_HHD */ -#define word_AQ_MsmLineRxMulticastFramesCounterRegister_HHD_msmLineRxMulticastFramesCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxMulticastFramesCounter_1 in AQ_MsmLineRxMulticastFramesCounterRegister_HHD */ -#define AQ_MsmLineRxMulticastFramesCounterRegister_HHD_msmLineRxMulticastFramesCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxMulticastFramesCounter_1 in AQ_MsmLineRxMulticastFramesCounterRegister_HHD */ -#define bits_AQ_MsmLineRxMulticastFramesCounterRegister_HHD_msmLineRxMulticastFramesCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxMulticastFramesCounter_1 in AQ_MsmLineRxMulticastFramesCounterRegister_HHD */ -#define word_AQ_MsmLineRxMulticastFramesCounterRegister_HHD_msmLineRxMulticastFramesCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmLineRxBroadcastFramesCounterRegister_HHD */ -#define AQ_MsmLineRxBroadcastFramesCounterRegister_HHD_baseRegisterAddress 0x9078 -/*! \brief MMD address of structure AQ_MsmLineRxBroadcastFramesCounterRegister_HHD */ -#define AQ_MsmLineRxBroadcastFramesCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxBroadcastFramesCounter_0 in AQ_MsmLineRxBroadcastFramesCounterRegister_HHD */ -#define AQ_MsmLineRxBroadcastFramesCounterRegister_HHD_msmLineRxBroadcastFramesCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxBroadcastFramesCounter_0 in AQ_MsmLineRxBroadcastFramesCounterRegister_HHD */ -#define bits_AQ_MsmLineRxBroadcastFramesCounterRegister_HHD_msmLineRxBroadcastFramesCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxBroadcastFramesCounter_0 in AQ_MsmLineRxBroadcastFramesCounterRegister_HHD */ -#define word_AQ_MsmLineRxBroadcastFramesCounterRegister_HHD_msmLineRxBroadcastFramesCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxBroadcastFramesCounter_1 in AQ_MsmLineRxBroadcastFramesCounterRegister_HHD */ -#define AQ_MsmLineRxBroadcastFramesCounterRegister_HHD_msmLineRxBroadcastFramesCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxBroadcastFramesCounter_1 in AQ_MsmLineRxBroadcastFramesCounterRegister_HHD */ -#define bits_AQ_MsmLineRxBroadcastFramesCounterRegister_HHD_msmLineRxBroadcastFramesCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxBroadcastFramesCounter_1 in AQ_MsmLineRxBroadcastFramesCounterRegister_HHD */ -#define word_AQ_MsmLineRxBroadcastFramesCounterRegister_HHD_msmLineRxBroadcastFramesCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmLineTxErrorsCounterRegister_HHD */ -#define AQ_MsmLineTxErrorsCounterRegister_HHD_baseRegisterAddress 0x907C -/*! \brief MMD address of structure AQ_MsmLineTxErrorsCounterRegister_HHD */ -#define AQ_MsmLineTxErrorsCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxErrorsCounter_0 in AQ_MsmLineTxErrorsCounterRegister_HHD */ -#define AQ_MsmLineTxErrorsCounterRegister_HHD_msmLineTxErrorsCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxErrorsCounter_0 in AQ_MsmLineTxErrorsCounterRegister_HHD */ -#define bits_AQ_MsmLineTxErrorsCounterRegister_HHD_msmLineTxErrorsCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxErrorsCounter_0 in AQ_MsmLineTxErrorsCounterRegister_HHD */ -#define word_AQ_MsmLineTxErrorsCounterRegister_HHD_msmLineTxErrorsCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxErrorsCounter_1 in AQ_MsmLineTxErrorsCounterRegister_HHD */ -#define AQ_MsmLineTxErrorsCounterRegister_HHD_msmLineTxErrorsCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxErrorsCounter_1 in AQ_MsmLineTxErrorsCounterRegister_HHD */ -#define bits_AQ_MsmLineTxErrorsCounterRegister_HHD_msmLineTxErrorsCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxErrorsCounter_1 in AQ_MsmLineTxErrorsCounterRegister_HHD */ -#define word_AQ_MsmLineTxErrorsCounterRegister_HHD_msmLineTxErrorsCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmLineTxUnicastFramesCounterRegister_HHD */ -#define AQ_MsmLineTxUnicastFramesCounterRegister_HHD_baseRegisterAddress 0x9084 -/*! \brief MMD address of structure AQ_MsmLineTxUnicastFramesCounterRegister_HHD */ -#define AQ_MsmLineTxUnicastFramesCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxUnicastFramesCounter_0 in AQ_MsmLineTxUnicastFramesCounterRegister_HHD */ -#define AQ_MsmLineTxUnicastFramesCounterRegister_HHD_msmLineTxUnicastFramesCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxUnicastFramesCounter_0 in AQ_MsmLineTxUnicastFramesCounterRegister_HHD */ -#define bits_AQ_MsmLineTxUnicastFramesCounterRegister_HHD_msmLineTxUnicastFramesCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxUnicastFramesCounter_0 in AQ_MsmLineTxUnicastFramesCounterRegister_HHD */ -#define word_AQ_MsmLineTxUnicastFramesCounterRegister_HHD_msmLineTxUnicastFramesCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxUnicastFramesCounter_1 in AQ_MsmLineTxUnicastFramesCounterRegister_HHD */ -#define AQ_MsmLineTxUnicastFramesCounterRegister_HHD_msmLineTxUnicastFramesCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxUnicastFramesCounter_1 in AQ_MsmLineTxUnicastFramesCounterRegister_HHD */ -#define bits_AQ_MsmLineTxUnicastFramesCounterRegister_HHD_msmLineTxUnicastFramesCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxUnicastFramesCounter_1 in AQ_MsmLineTxUnicastFramesCounterRegister_HHD */ -#define word_AQ_MsmLineTxUnicastFramesCounterRegister_HHD_msmLineTxUnicastFramesCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmLineTxMulticastFramesCounterRegister_HHD */ -#define AQ_MsmLineTxMulticastFramesCounterRegister_HHD_baseRegisterAddress 0x9088 -/*! \brief MMD address of structure AQ_MsmLineTxMulticastFramesCounterRegister_HHD */ -#define AQ_MsmLineTxMulticastFramesCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxMulticastFramesCounter_0 in AQ_MsmLineTxMulticastFramesCounterRegister_HHD */ -#define AQ_MsmLineTxMulticastFramesCounterRegister_HHD_msmLineTxMulticastFramesCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxMulticastFramesCounter_0 in AQ_MsmLineTxMulticastFramesCounterRegister_HHD */ -#define bits_AQ_MsmLineTxMulticastFramesCounterRegister_HHD_msmLineTxMulticastFramesCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxMulticastFramesCounter_0 in AQ_MsmLineTxMulticastFramesCounterRegister_HHD */ -#define word_AQ_MsmLineTxMulticastFramesCounterRegister_HHD_msmLineTxMulticastFramesCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxMulticastFramesCounter_1 in AQ_MsmLineTxMulticastFramesCounterRegister_HHD */ -#define AQ_MsmLineTxMulticastFramesCounterRegister_HHD_msmLineTxMulticastFramesCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxMulticastFramesCounter_1 in AQ_MsmLineTxMulticastFramesCounterRegister_HHD */ -#define bits_AQ_MsmLineTxMulticastFramesCounterRegister_HHD_msmLineTxMulticastFramesCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxMulticastFramesCounter_1 in AQ_MsmLineTxMulticastFramesCounterRegister_HHD */ -#define word_AQ_MsmLineTxMulticastFramesCounterRegister_HHD_msmLineTxMulticastFramesCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmLineTxBroadcastFramesCounterRegister_HHD */ -#define AQ_MsmLineTxBroadcastFramesCounterRegister_HHD_baseRegisterAddress 0x908C -/*! \brief MMD address of structure AQ_MsmLineTxBroadcastFramesCounterRegister_HHD */ -#define AQ_MsmLineTxBroadcastFramesCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxBroadcastFramesCounter_0 in AQ_MsmLineTxBroadcastFramesCounterRegister_HHD */ -#define AQ_MsmLineTxBroadcastFramesCounterRegister_HHD_msmLineTxBroadcastFramesCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxBroadcastFramesCounter_0 in AQ_MsmLineTxBroadcastFramesCounterRegister_HHD */ -#define bits_AQ_MsmLineTxBroadcastFramesCounterRegister_HHD_msmLineTxBroadcastFramesCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxBroadcastFramesCounter_0 in AQ_MsmLineTxBroadcastFramesCounterRegister_HHD */ -#define word_AQ_MsmLineTxBroadcastFramesCounterRegister_HHD_msmLineTxBroadcastFramesCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxBroadcastFramesCounter_1 in AQ_MsmLineTxBroadcastFramesCounterRegister_HHD */ -#define AQ_MsmLineTxBroadcastFramesCounterRegister_HHD_msmLineTxBroadcastFramesCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxBroadcastFramesCounter_1 in AQ_MsmLineTxBroadcastFramesCounterRegister_HHD */ -#define bits_AQ_MsmLineTxBroadcastFramesCounterRegister_HHD_msmLineTxBroadcastFramesCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxBroadcastFramesCounter_1 in AQ_MsmLineTxBroadcastFramesCounterRegister_HHD */ -#define word_AQ_MsmLineTxBroadcastFramesCounterRegister_HHD_msmLineTxBroadcastFramesCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmLineRxErrorsCounterRegister_HHD */ -#define AQ_MsmLineRxErrorsCounterRegister_HHD_baseRegisterAddress 0x90C8 -/*! \brief MMD address of structure AQ_MsmLineRxErrorsCounterRegister_HHD */ -#define AQ_MsmLineRxErrorsCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxErrorsCounter_0 in AQ_MsmLineRxErrorsCounterRegister_HHD */ -#define AQ_MsmLineRxErrorsCounterRegister_HHD_msmLineRxErrorsCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxErrorsCounter_0 in AQ_MsmLineRxErrorsCounterRegister_HHD */ -#define bits_AQ_MsmLineRxErrorsCounterRegister_HHD_msmLineRxErrorsCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxErrorsCounter_0 in AQ_MsmLineRxErrorsCounterRegister_HHD */ -#define word_AQ_MsmLineRxErrorsCounterRegister_HHD_msmLineRxErrorsCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxErrorsCounter_1 in AQ_MsmLineRxErrorsCounterRegister_HHD */ -#define AQ_MsmLineRxErrorsCounterRegister_HHD_msmLineRxErrorsCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxErrorsCounter_1 in AQ_MsmLineRxErrorsCounterRegister_HHD */ -#define bits_AQ_MsmLineRxErrorsCounterRegister_HHD_msmLineRxErrorsCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxErrorsCounter_1 in AQ_MsmLineRxErrorsCounterRegister_HHD */ -#define word_AQ_MsmLineRxErrorsCounterRegister_HHD_msmLineRxErrorsCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_GlobalControl_HHD */ -#define AQ_GlobalControl_HHD_baseRegisterAddress 0xC000 -/*! \brief MMD address of structure AQ_GlobalControl_HHD */ -#define AQ_GlobalControl_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure upReset in AQ_GlobalControl_HHD */ -#define AQ_GlobalControl_HHD_upReset 1 -/*! \brief Preprocessor variable to relate field to bit position in structure upReset in AQ_GlobalControl_HHD */ -#define bits_AQ_GlobalControl_HHD_upReset u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure upReset in AQ_GlobalControl_HHD */ -#define word_AQ_GlobalControl_HHD_upReset u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure upRunStallOverride in AQ_GlobalControl_HHD */ -#define AQ_GlobalControl_HHD_upRunStallOverride 1 -/*! \brief Preprocessor variable to relate field to bit position in structure upRunStallOverride in AQ_GlobalControl_HHD */ -#define bits_AQ_GlobalControl_HHD_upRunStallOverride u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure upRunStallOverride in AQ_GlobalControl_HHD */ -#define word_AQ_GlobalControl_HHD_upRunStallOverride u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure upRunStall in AQ_GlobalControl_HHD */ -#define AQ_GlobalControl_HHD_upRunStall 1 -/*! \brief Preprocessor variable to relate field to bit position in structure upRunStall in AQ_GlobalControl_HHD */ -#define bits_AQ_GlobalControl_HHD_upRunStall u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure upRunStall in AQ_GlobalControl_HHD */ -#define word_AQ_GlobalControl_HHD_upRunStall u1.word_1 - -/*! \brief Base register address of structure AQ_GlobalResetControl_HHD */ -#define AQ_GlobalResetControl_HHD_baseRegisterAddress 0xC006 -/*! \brief MMD address of structure AQ_GlobalResetControl_HHD */ -#define AQ_GlobalResetControl_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure globalMMD_ResetDisable in AQ_GlobalResetControl_HHD */ -#define AQ_GlobalResetControl_HHD_globalMMD_ResetDisable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure globalMMD_ResetDisable in AQ_GlobalResetControl_HHD */ -#define bits_AQ_GlobalResetControl_HHD_globalMMD_ResetDisable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure globalMMD_ResetDisable in AQ_GlobalResetControl_HHD */ -#define word_AQ_GlobalResetControl_HHD_globalMMD_ResetDisable u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalDiagnosticProvisioning_HHD */ -#define AQ_GlobalDiagnosticProvisioning_HHD_baseRegisterAddress 0xC400 -/*! \brief MMD address of structure AQ_GlobalDiagnosticProvisioning_HHD */ -#define AQ_GlobalDiagnosticProvisioning_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure enableDiagnostics in AQ_GlobalDiagnosticProvisioning_HHD */ -#define AQ_GlobalDiagnosticProvisioning_HHD_enableDiagnostics 0 -/*! \brief Preprocessor variable to relate field to bit position in structure enableDiagnostics in AQ_GlobalDiagnosticProvisioning_HHD */ -#define bits_AQ_GlobalDiagnosticProvisioning_HHD_enableDiagnostics u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure enableDiagnostics in AQ_GlobalDiagnosticProvisioning_HHD */ -#define word_AQ_GlobalDiagnosticProvisioning_HHD_enableDiagnostics u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalThermalProvisioning_HHD */ -#define AQ_GlobalThermalProvisioning_HHD_baseRegisterAddress 0xC420 -/*! \brief MMD address of structure AQ_GlobalThermalProvisioning_HHD */ -#define AQ_GlobalThermalProvisioning_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure reserved_0 in AQ_GlobalThermalProvisioning_HHD */ -#define AQ_GlobalThermalProvisioning_HHD_reserved_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_0 in AQ_GlobalThermalProvisioning_HHD */ -#define bits_AQ_GlobalThermalProvisioning_HHD_reserved_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_0 in AQ_GlobalThermalProvisioning_HHD */ -#define word_AQ_GlobalThermalProvisioning_HHD_reserved_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure highTempFailureThreshold in AQ_GlobalThermalProvisioning_HHD */ -#define AQ_GlobalThermalProvisioning_HHD_highTempFailureThreshold 1 -/*! \brief Preprocessor variable to relate field to bit position in structure highTempFailureThreshold in AQ_GlobalThermalProvisioning_HHD */ -#define bits_AQ_GlobalThermalProvisioning_HHD_highTempFailureThreshold u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure highTempFailureThreshold in AQ_GlobalThermalProvisioning_HHD */ -#define word_AQ_GlobalThermalProvisioning_HHD_highTempFailureThreshold u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure lowTempFailureThreshold in AQ_GlobalThermalProvisioning_HHD */ -#define AQ_GlobalThermalProvisioning_HHD_lowTempFailureThreshold 2 -/*! \brief Preprocessor variable to relate field to bit position in structure lowTempFailureThreshold in AQ_GlobalThermalProvisioning_HHD */ -#define bits_AQ_GlobalThermalProvisioning_HHD_lowTempFailureThreshold u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure lowTempFailureThreshold in AQ_GlobalThermalProvisioning_HHD */ -#define word_AQ_GlobalThermalProvisioning_HHD_lowTempFailureThreshold u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure highTempWarningThreshold in AQ_GlobalThermalProvisioning_HHD */ -#define AQ_GlobalThermalProvisioning_HHD_highTempWarningThreshold 3 -/*! \brief Preprocessor variable to relate field to bit position in structure highTempWarningThreshold in AQ_GlobalThermalProvisioning_HHD */ -#define bits_AQ_GlobalThermalProvisioning_HHD_highTempWarningThreshold u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure highTempWarningThreshold in AQ_GlobalThermalProvisioning_HHD */ -#define word_AQ_GlobalThermalProvisioning_HHD_highTempWarningThreshold u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure lowTempWarningThreshold in AQ_GlobalThermalProvisioning_HHD */ -#define AQ_GlobalThermalProvisioning_HHD_lowTempWarningThreshold 4 -/*! \brief Preprocessor variable to relate field to bit position in structure lowTempWarningThreshold in AQ_GlobalThermalProvisioning_HHD */ -#define bits_AQ_GlobalThermalProvisioning_HHD_lowTempWarningThreshold u4.bits_4 -/*! \brief Preprocessor variable to relate field to word position in structure lowTempWarningThreshold in AQ_GlobalThermalProvisioning_HHD */ -#define word_AQ_GlobalThermalProvisioning_HHD_lowTempWarningThreshold u4.word_4 - -/*! \brief Base register address of structure AQ_GlobalLedProvisioning_HHD */ -#define AQ_GlobalLedProvisioning_HHD_baseRegisterAddress 0xC430 -/*! \brief MMD address of structure AQ_GlobalLedProvisioning_HHD */ -#define AQ_GlobalLedProvisioning_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioningC430 in AQ_GlobalLedProvisioning_HHD */ -#define AQ_GlobalLedProvisioning_HHD_reservedProvisioningC430 0 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioningC430 in AQ_GlobalLedProvisioning_HHD */ -#define bits_AQ_GlobalLedProvisioning_HHD_reservedProvisioningC430 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioningC430 in AQ_GlobalLedProvisioning_HHD */ -#define word_AQ_GlobalLedProvisioning_HHD_reservedProvisioningC430 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure led_0ManualSet in AQ_GlobalLedProvisioning_HHD */ -#define AQ_GlobalLedProvisioning_HHD_led_0ManualSet 0 -/*! \brief Preprocessor variable to relate field to bit position in structure led_0ManualSet in AQ_GlobalLedProvisioning_HHD */ -#define bits_AQ_GlobalLedProvisioning_HHD_led_0ManualSet u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure led_0ManualSet in AQ_GlobalLedProvisioning_HHD */ -#define word_AQ_GlobalLedProvisioning_HHD_led_0ManualSet u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure led_0_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ -#define AQ_GlobalLedProvisioning_HHD_led_0_10Gb_sLinkEstablished 0 -/*! \brief Preprocessor variable to relate field to bit position in structure led_0_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ -#define bits_AQ_GlobalLedProvisioning_HHD_led_0_10Gb_sLinkEstablished u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure led_0_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ -#define word_AQ_GlobalLedProvisioning_HHD_led_0_10Gb_sLinkEstablished u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure led_0_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ -#define AQ_GlobalLedProvisioning_HHD_led_0_1Gb_sLinkEstablished 0 -/*! \brief Preprocessor variable to relate field to bit position in structure led_0_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ -#define bits_AQ_GlobalLedProvisioning_HHD_led_0_1Gb_sLinkEstablished u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure led_0_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ -#define word_AQ_GlobalLedProvisioning_HHD_led_0_1Gb_sLinkEstablished u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure led_0_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ -#define AQ_GlobalLedProvisioning_HHD_led_0_100Mb_sLinkEstablished 0 -/*! \brief Preprocessor variable to relate field to bit position in structure led_0_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ -#define bits_AQ_GlobalLedProvisioning_HHD_led_0_100Mb_sLinkEstablished u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure led_0_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ -#define word_AQ_GlobalLedProvisioning_HHD_led_0_100Mb_sLinkEstablished u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure led_0Connecting in AQ_GlobalLedProvisioning_HHD */ -#define AQ_GlobalLedProvisioning_HHD_led_0Connecting 0 -/*! \brief Preprocessor variable to relate field to bit position in structure led_0Connecting in AQ_GlobalLedProvisioning_HHD */ -#define bits_AQ_GlobalLedProvisioning_HHD_led_0Connecting u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure led_0Connecting in AQ_GlobalLedProvisioning_HHD */ -#define word_AQ_GlobalLedProvisioning_HHD_led_0Connecting u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure led_0ReceiveActivity in AQ_GlobalLedProvisioning_HHD */ -#define AQ_GlobalLedProvisioning_HHD_led_0ReceiveActivity 0 -/*! \brief Preprocessor variable to relate field to bit position in structure led_0ReceiveActivity in AQ_GlobalLedProvisioning_HHD */ -#define bits_AQ_GlobalLedProvisioning_HHD_led_0ReceiveActivity u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure led_0ReceiveActivity in AQ_GlobalLedProvisioning_HHD */ -#define word_AQ_GlobalLedProvisioning_HHD_led_0ReceiveActivity u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure led_0TransmitActivity in AQ_GlobalLedProvisioning_HHD */ -#define AQ_GlobalLedProvisioning_HHD_led_0TransmitActivity 0 -/*! \brief Preprocessor variable to relate field to bit position in structure led_0TransmitActivity in AQ_GlobalLedProvisioning_HHD */ -#define bits_AQ_GlobalLedProvisioning_HHD_led_0TransmitActivity u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure led_0TransmitActivity in AQ_GlobalLedProvisioning_HHD */ -#define word_AQ_GlobalLedProvisioning_HHD_led_0TransmitActivity u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure led_0ActivityStretch in AQ_GlobalLedProvisioning_HHD */ -#define AQ_GlobalLedProvisioning_HHD_led_0ActivityStretch 0 -/*! \brief Preprocessor variable to relate field to bit position in structure led_0ActivityStretch in AQ_GlobalLedProvisioning_HHD */ -#define bits_AQ_GlobalLedProvisioning_HHD_led_0ActivityStretch u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure led_0ActivityStretch in AQ_GlobalLedProvisioning_HHD */ -#define word_AQ_GlobalLedProvisioning_HHD_led_0ActivityStretch u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioningC431 in AQ_GlobalLedProvisioning_HHD */ -#define AQ_GlobalLedProvisioning_HHD_reservedProvisioningC431 1 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioningC431 in AQ_GlobalLedProvisioning_HHD */ -#define bits_AQ_GlobalLedProvisioning_HHD_reservedProvisioningC431 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioningC431 in AQ_GlobalLedProvisioning_HHD */ -#define word_AQ_GlobalLedProvisioning_HHD_reservedProvisioningC431 u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure led_1ManualSet in AQ_GlobalLedProvisioning_HHD */ -#define AQ_GlobalLedProvisioning_HHD_led_1ManualSet 1 -/*! \brief Preprocessor variable to relate field to bit position in structure led_1ManualSet in AQ_GlobalLedProvisioning_HHD */ -#define bits_AQ_GlobalLedProvisioning_HHD_led_1ManualSet u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure led_1ManualSet in AQ_GlobalLedProvisioning_HHD */ -#define word_AQ_GlobalLedProvisioning_HHD_led_1ManualSet u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure led_1_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ -#define AQ_GlobalLedProvisioning_HHD_led_1_10Gb_sLinkEstablished 1 -/*! \brief Preprocessor variable to relate field to bit position in structure led_1_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ -#define bits_AQ_GlobalLedProvisioning_HHD_led_1_10Gb_sLinkEstablished u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure led_1_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ -#define word_AQ_GlobalLedProvisioning_HHD_led_1_10Gb_sLinkEstablished u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure led_1_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ -#define AQ_GlobalLedProvisioning_HHD_led_1_1Gb_sLinkEstablished 1 -/*! \brief Preprocessor variable to relate field to bit position in structure led_1_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ -#define bits_AQ_GlobalLedProvisioning_HHD_led_1_1Gb_sLinkEstablished u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure led_1_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ -#define word_AQ_GlobalLedProvisioning_HHD_led_1_1Gb_sLinkEstablished u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure led_1_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ -#define AQ_GlobalLedProvisioning_HHD_led_1_100Mb_sLinkEstablished 1 -/*! \brief Preprocessor variable to relate field to bit position in structure led_1_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ -#define bits_AQ_GlobalLedProvisioning_HHD_led_1_100Mb_sLinkEstablished u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure led_1_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ -#define word_AQ_GlobalLedProvisioning_HHD_led_1_100Mb_sLinkEstablished u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure led_1Connecting in AQ_GlobalLedProvisioning_HHD */ -#define AQ_GlobalLedProvisioning_HHD_led_1Connecting 1 -/*! \brief Preprocessor variable to relate field to bit position in structure led_1Connecting in AQ_GlobalLedProvisioning_HHD */ -#define bits_AQ_GlobalLedProvisioning_HHD_led_1Connecting u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure led_1Connecting in AQ_GlobalLedProvisioning_HHD */ -#define word_AQ_GlobalLedProvisioning_HHD_led_1Connecting u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure led_1ReceiveActivity in AQ_GlobalLedProvisioning_HHD */ -#define AQ_GlobalLedProvisioning_HHD_led_1ReceiveActivity 1 -/*! \brief Preprocessor variable to relate field to bit position in structure led_1ReceiveActivity in AQ_GlobalLedProvisioning_HHD */ -#define bits_AQ_GlobalLedProvisioning_HHD_led_1ReceiveActivity u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure led_1ReceiveActivity in AQ_GlobalLedProvisioning_HHD */ -#define word_AQ_GlobalLedProvisioning_HHD_led_1ReceiveActivity u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure led_1TransmitActivity in AQ_GlobalLedProvisioning_HHD */ -#define AQ_GlobalLedProvisioning_HHD_led_1TransmitActivity 1 -/*! \brief Preprocessor variable to relate field to bit position in structure led_1TransmitActivity in AQ_GlobalLedProvisioning_HHD */ -#define bits_AQ_GlobalLedProvisioning_HHD_led_1TransmitActivity u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure led_1TransmitActivity in AQ_GlobalLedProvisioning_HHD */ -#define word_AQ_GlobalLedProvisioning_HHD_led_1TransmitActivity u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure led_1ActivityStretch in AQ_GlobalLedProvisioning_HHD */ -#define AQ_GlobalLedProvisioning_HHD_led_1ActivityStretch 1 -/*! \brief Preprocessor variable to relate field to bit position in structure led_1ActivityStretch in AQ_GlobalLedProvisioning_HHD */ -#define bits_AQ_GlobalLedProvisioning_HHD_led_1ActivityStretch u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure led_1ActivityStretch in AQ_GlobalLedProvisioning_HHD */ -#define word_AQ_GlobalLedProvisioning_HHD_led_1ActivityStretch u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioningC432 in AQ_GlobalLedProvisioning_HHD */ -#define AQ_GlobalLedProvisioning_HHD_reservedProvisioningC432 2 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioningC432 in AQ_GlobalLedProvisioning_HHD */ -#define bits_AQ_GlobalLedProvisioning_HHD_reservedProvisioningC432 u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioningC432 in AQ_GlobalLedProvisioning_HHD */ -#define word_AQ_GlobalLedProvisioning_HHD_reservedProvisioningC432 u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure led_2ManualSet in AQ_GlobalLedProvisioning_HHD */ -#define AQ_GlobalLedProvisioning_HHD_led_2ManualSet 2 -/*! \brief Preprocessor variable to relate field to bit position in structure led_2ManualSet in AQ_GlobalLedProvisioning_HHD */ -#define bits_AQ_GlobalLedProvisioning_HHD_led_2ManualSet u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure led_2ManualSet in AQ_GlobalLedProvisioning_HHD */ -#define word_AQ_GlobalLedProvisioning_HHD_led_2ManualSet u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure led_2_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ -#define AQ_GlobalLedProvisioning_HHD_led_2_10Gb_sLinkEstablished 2 -/*! \brief Preprocessor variable to relate field to bit position in structure led_2_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ -#define bits_AQ_GlobalLedProvisioning_HHD_led_2_10Gb_sLinkEstablished u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure led_2_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ -#define word_AQ_GlobalLedProvisioning_HHD_led_2_10Gb_sLinkEstablished u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure led_2_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ -#define AQ_GlobalLedProvisioning_HHD_led_2_1Gb_sLinkEstablished 2 -/*! \brief Preprocessor variable to relate field to bit position in structure led_2_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ -#define bits_AQ_GlobalLedProvisioning_HHD_led_2_1Gb_sLinkEstablished u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure led_2_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ -#define word_AQ_GlobalLedProvisioning_HHD_led_2_1Gb_sLinkEstablished u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure led_2_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ -#define AQ_GlobalLedProvisioning_HHD_led_2_100Mb_sLinkEstablished 2 -/*! \brief Preprocessor variable to relate field to bit position in structure led_2_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ -#define bits_AQ_GlobalLedProvisioning_HHD_led_2_100Mb_sLinkEstablished u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure led_2_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ -#define word_AQ_GlobalLedProvisioning_HHD_led_2_100Mb_sLinkEstablished u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure led_2Connecting in AQ_GlobalLedProvisioning_HHD */ -#define AQ_GlobalLedProvisioning_HHD_led_2Connecting 2 -/*! \brief Preprocessor variable to relate field to bit position in structure led_2Connecting in AQ_GlobalLedProvisioning_HHD */ -#define bits_AQ_GlobalLedProvisioning_HHD_led_2Connecting u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure led_2Connecting in AQ_GlobalLedProvisioning_HHD */ -#define word_AQ_GlobalLedProvisioning_HHD_led_2Connecting u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure led_2ReceiveActivity in AQ_GlobalLedProvisioning_HHD */ -#define AQ_GlobalLedProvisioning_HHD_led_2ReceiveActivity 2 -/*! \brief Preprocessor variable to relate field to bit position in structure led_2ReceiveActivity in AQ_GlobalLedProvisioning_HHD */ -#define bits_AQ_GlobalLedProvisioning_HHD_led_2ReceiveActivity u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure led_2ReceiveActivity in AQ_GlobalLedProvisioning_HHD */ -#define word_AQ_GlobalLedProvisioning_HHD_led_2ReceiveActivity u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure led_2TransmitActivity in AQ_GlobalLedProvisioning_HHD */ -#define AQ_GlobalLedProvisioning_HHD_led_2TransmitActivity 2 -/*! \brief Preprocessor variable to relate field to bit position in structure led_2TransmitActivity in AQ_GlobalLedProvisioning_HHD */ -#define bits_AQ_GlobalLedProvisioning_HHD_led_2TransmitActivity u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure led_2TransmitActivity in AQ_GlobalLedProvisioning_HHD */ -#define word_AQ_GlobalLedProvisioning_HHD_led_2TransmitActivity u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure led_2ActivityStretch in AQ_GlobalLedProvisioning_HHD */ -#define AQ_GlobalLedProvisioning_HHD_led_2ActivityStretch 2 -/*! \brief Preprocessor variable to relate field to bit position in structure led_2ActivityStretch in AQ_GlobalLedProvisioning_HHD */ -#define bits_AQ_GlobalLedProvisioning_HHD_led_2ActivityStretch u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure led_2ActivityStretch in AQ_GlobalLedProvisioning_HHD */ -#define word_AQ_GlobalLedProvisioning_HHD_led_2ActivityStretch u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure ledOperationMode in AQ_GlobalLedProvisioning_HHD */ -#define AQ_GlobalLedProvisioning_HHD_ledOperationMode 7 -/*! \brief Preprocessor variable to relate field to bit position in structure ledOperationMode in AQ_GlobalLedProvisioning_HHD */ -#define bits_AQ_GlobalLedProvisioning_HHD_ledOperationMode u7.bits_7 -/*! \brief Preprocessor variable to relate field to word position in structure ledOperationMode in AQ_GlobalLedProvisioning_HHD */ -#define word_AQ_GlobalLedProvisioning_HHD_ledOperationMode u7.word_7 - -/*! \brief Base register address of structure AQ_GlobalGeneralProvisioning_HHD */ -#define AQ_GlobalGeneralProvisioning_HHD_baseRegisterAddress 0xC440 -/*! \brief MMD address of structure AQ_GlobalGeneralProvisioning_HHD */ -#define AQ_GlobalGeneralProvisioning_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mdioBroadcastModeEnable in AQ_GlobalGeneralProvisioning_HHD */ -#define AQ_GlobalGeneralProvisioning_HHD_mdioBroadcastModeEnable 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mdioBroadcastModeEnable in AQ_GlobalGeneralProvisioning_HHD */ -#define bits_AQ_GlobalGeneralProvisioning_HHD_mdioBroadcastModeEnable u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mdioBroadcastModeEnable in AQ_GlobalGeneralProvisioning_HHD */ -#define word_AQ_GlobalGeneralProvisioning_HHD_mdioBroadcastModeEnable u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure mdioReadMSW_FirstEnable in AQ_GlobalGeneralProvisioning_HHD */ -#define AQ_GlobalGeneralProvisioning_HHD_mdioReadMSW_FirstEnable 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mdioReadMSW_FirstEnable in AQ_GlobalGeneralProvisioning_HHD */ -#define bits_AQ_GlobalGeneralProvisioning_HHD_mdioReadMSW_FirstEnable u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mdioReadMSW_FirstEnable in AQ_GlobalGeneralProvisioning_HHD */ -#define word_AQ_GlobalGeneralProvisioning_HHD_mdioReadMSW_FirstEnable u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure mdioDriveConfiguration in AQ_GlobalGeneralProvisioning_HHD */ -#define AQ_GlobalGeneralProvisioning_HHD_mdioDriveConfiguration 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mdioDriveConfiguration in AQ_GlobalGeneralProvisioning_HHD */ -#define bits_AQ_GlobalGeneralProvisioning_HHD_mdioDriveConfiguration u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mdioDriveConfiguration in AQ_GlobalGeneralProvisioning_HHD */ -#define word_AQ_GlobalGeneralProvisioning_HHD_mdioDriveConfiguration u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure mdioPreambleDetectionDisable in AQ_GlobalGeneralProvisioning_HHD */ -#define AQ_GlobalGeneralProvisioning_HHD_mdioPreambleDetectionDisable 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mdioPreambleDetectionDisable in AQ_GlobalGeneralProvisioning_HHD */ -#define bits_AQ_GlobalGeneralProvisioning_HHD_mdioPreambleDetectionDisable u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mdioPreambleDetectionDisable in AQ_GlobalGeneralProvisioning_HHD */ -#define word_AQ_GlobalGeneralProvisioning_HHD_mdioPreambleDetectionDisable u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure daisyChainReset in AQ_GlobalGeneralProvisioning_HHD */ -#define AQ_GlobalGeneralProvisioning_HHD_daisyChainReset 2 -/*! \brief Preprocessor variable to relate field to bit position in structure daisyChainReset in AQ_GlobalGeneralProvisioning_HHD */ -#define bits_AQ_GlobalGeneralProvisioning_HHD_daisyChainReset u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure daisyChainReset in AQ_GlobalGeneralProvisioning_HHD */ -#define word_AQ_GlobalGeneralProvisioning_HHD_daisyChainReset u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure mdioBroadcastAddressConfiguration in AQ_GlobalGeneralProvisioning_HHD */ -#define AQ_GlobalGeneralProvisioning_HHD_mdioBroadcastAddressConfiguration 7 -/*! \brief Preprocessor variable to relate field to bit position in structure mdioBroadcastAddressConfiguration in AQ_GlobalGeneralProvisioning_HHD */ -#define bits_AQ_GlobalGeneralProvisioning_HHD_mdioBroadcastAddressConfiguration u7.bits_7 -/*! \brief Preprocessor variable to relate field to word position in structure mdioBroadcastAddressConfiguration in AQ_GlobalGeneralProvisioning_HHD */ -#define word_AQ_GlobalGeneralProvisioning_HHD_mdioBroadcastAddressConfiguration u7.word_7 -/*! \brief Preprocessor variable to relate field to word number in structure mdioPreambleLength in AQ_GlobalGeneralProvisioning_HHD */ -#define AQ_GlobalGeneralProvisioning_HHD_mdioPreambleLength 9 -/*! \brief Preprocessor variable to relate field to bit position in structure mdioPreambleLength in AQ_GlobalGeneralProvisioning_HHD */ -#define bits_AQ_GlobalGeneralProvisioning_HHD_mdioPreambleLength u9.bits_9 -/*! \brief Preprocessor variable to relate field to word position in structure mdioPreambleLength in AQ_GlobalGeneralProvisioning_HHD */ -#define word_AQ_GlobalGeneralProvisioning_HHD_mdioPreambleLength u9.word_9 - -/*! \brief Base register address of structure AQ_GlobalNvrProvisioning_HHD */ -#define AQ_GlobalNvrProvisioning_HHD_baseRegisterAddress 0xC450 -/*! \brief MMD address of structure AQ_GlobalNvrProvisioning_HHD */ -#define AQ_GlobalNvrProvisioning_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure nvrDataLength in AQ_GlobalNvrProvisioning_HHD */ -#define AQ_GlobalNvrProvisioning_HHD_nvrDataLength 0 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrDataLength in AQ_GlobalNvrProvisioning_HHD */ -#define bits_AQ_GlobalNvrProvisioning_HHD_nvrDataLength u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure nvrDataLength in AQ_GlobalNvrProvisioning_HHD */ -#define word_AQ_GlobalNvrProvisioning_HHD_nvrDataLength u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure nvrDummyLength in AQ_GlobalNvrProvisioning_HHD */ -#define AQ_GlobalNvrProvisioning_HHD_nvrDummyLength 0 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrDummyLength in AQ_GlobalNvrProvisioning_HHD */ -#define bits_AQ_GlobalNvrProvisioning_HHD_nvrDummyLength u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure nvrDummyLength in AQ_GlobalNvrProvisioning_HHD */ -#define word_AQ_GlobalNvrProvisioning_HHD_nvrDummyLength u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure nvrAddressLength in AQ_GlobalNvrProvisioning_HHD */ -#define AQ_GlobalNvrProvisioning_HHD_nvrAddressLength 0 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrAddressLength in AQ_GlobalNvrProvisioning_HHD */ -#define bits_AQ_GlobalNvrProvisioning_HHD_nvrAddressLength u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure nvrAddressLength in AQ_GlobalNvrProvisioning_HHD */ -#define word_AQ_GlobalNvrProvisioning_HHD_nvrAddressLength u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure nvrAddressLengthOverride in AQ_GlobalNvrProvisioning_HHD */ -#define AQ_GlobalNvrProvisioning_HHD_nvrAddressLengthOverride 1 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrAddressLengthOverride in AQ_GlobalNvrProvisioning_HHD */ -#define bits_AQ_GlobalNvrProvisioning_HHD_nvrAddressLengthOverride u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure nvrAddressLengthOverride in AQ_GlobalNvrProvisioning_HHD */ -#define word_AQ_GlobalNvrProvisioning_HHD_nvrAddressLengthOverride u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure nvrClockDivide in AQ_GlobalNvrProvisioning_HHD */ -#define AQ_GlobalNvrProvisioning_HHD_nvrClockDivide 1 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrClockDivide in AQ_GlobalNvrProvisioning_HHD */ -#define bits_AQ_GlobalNvrProvisioning_HHD_nvrClockDivide u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure nvrClockDivide in AQ_GlobalNvrProvisioning_HHD */ -#define word_AQ_GlobalNvrProvisioning_HHD_nvrClockDivide u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure nvrDaisyChainClockDivideOverride in AQ_GlobalNvrProvisioning_HHD */ -#define AQ_GlobalNvrProvisioning_HHD_nvrDaisyChainClockDivideOverride 2 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrDaisyChainClockDivideOverride in AQ_GlobalNvrProvisioning_HHD */ -#define bits_AQ_GlobalNvrProvisioning_HHD_nvrDaisyChainClockDivideOverride u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure nvrDaisyChainClockDivideOverride in AQ_GlobalNvrProvisioning_HHD */ -#define word_AQ_GlobalNvrProvisioning_HHD_nvrDaisyChainClockDivideOverride u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure nvrDaisyChainDisable in AQ_GlobalNvrProvisioning_HHD */ -#define AQ_GlobalNvrProvisioning_HHD_nvrDaisyChainDisable 2 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrDaisyChainDisable in AQ_GlobalNvrProvisioning_HHD */ -#define bits_AQ_GlobalNvrProvisioning_HHD_nvrDaisyChainDisable u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure nvrDaisyChainDisable in AQ_GlobalNvrProvisioning_HHD */ -#define word_AQ_GlobalNvrProvisioning_HHD_nvrDaisyChainDisable u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure nvrReset in AQ_GlobalNvrProvisioning_HHD */ -#define AQ_GlobalNvrProvisioning_HHD_nvrReset 3 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrReset in AQ_GlobalNvrProvisioning_HHD */ -#define bits_AQ_GlobalNvrProvisioning_HHD_nvrReset u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure nvrReset in AQ_GlobalNvrProvisioning_HHD */ -#define word_AQ_GlobalNvrProvisioning_HHD_nvrReset u3.word_3 - -/*! \brief Base register address of structure AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_baseRegisterAddress 0xC470 -/*! \brief MMD address of structure AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure diagnosticsSelect in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_diagnosticsSelect 0 -/*! \brief Preprocessor variable to relate field to bit position in structure diagnosticsSelect in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_diagnosticsSelect u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure diagnosticsSelect in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_diagnosticsSelect u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure extendedMdiDiagnosticsSelect in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_extendedMdiDiagnosticsSelect 0 -/*! \brief Preprocessor variable to relate field to bit position in structure extendedMdiDiagnosticsSelect in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_extendedMdiDiagnosticsSelect u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure extendedMdiDiagnosticsSelect in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_extendedMdiDiagnosticsSelect u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure initiateCableDiagnostics in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_initiateCableDiagnostics 0 -/*! \brief Preprocessor variable to relate field to bit position in structure initiateCableDiagnostics in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_initiateCableDiagnostics u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure initiateCableDiagnostics in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_initiateCableDiagnostics u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure enableDaisy_chainHop_countOverride in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_enableDaisy_chainHop_countOverride 1 -/*! \brief Preprocessor variable to relate field to bit position in structure enableDaisy_chainHop_countOverride in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_enableDaisy_chainHop_countOverride u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure enableDaisy_chainHop_countOverride in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_enableDaisy_chainHop_countOverride u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure daisy_chainHop_countOverrideValue in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_daisy_chainHop_countOverrideValue 1 -/*! \brief Preprocessor variable to relate field to bit position in structure daisy_chainHop_countOverrideValue in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_daisy_chainHop_countOverrideValue u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure daisy_chainHop_countOverrideValue in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_daisy_chainHop_countOverrideValue u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure enableVddPowerSupplyTuning in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_enableVddPowerSupplyTuning 2 -/*! \brief Preprocessor variable to relate field to bit position in structure enableVddPowerSupplyTuning in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_enableVddPowerSupplyTuning u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure enableVddPowerSupplyTuning in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_enableVddPowerSupplyTuning u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure tunableExternalVddPowerSupplyPresent in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_tunableExternalVddPowerSupplyPresent 2 -/*! \brief Preprocessor variable to relate field to bit position in structure tunableExternalVddPowerSupplyPresent in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_tunableExternalVddPowerSupplyPresent u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure tunableExternalVddPowerSupplyPresent in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_tunableExternalVddPowerSupplyPresent u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure externalVddChangeRequest in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_externalVddChangeRequest 2 -/*! \brief Preprocessor variable to relate field to bit position in structure externalVddChangeRequest in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_externalVddChangeRequest u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure externalVddChangeRequest in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_externalVddChangeRequest u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure enableXenpakRegisterSpace in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_enableXenpakRegisterSpace 2 -/*! \brief Preprocessor variable to relate field to bit position in structure enableXenpakRegisterSpace in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_enableXenpakRegisterSpace u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure enableXenpakRegisterSpace in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_enableXenpakRegisterSpace u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure enable_5thChannelRfiCancellation in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_enable_5thChannelRfiCancellation 2 -/*! \brief Preprocessor variable to relate field to bit position in structure enable_5thChannelRfiCancellation in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_enable_5thChannelRfiCancellation u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure enable_5thChannelRfiCancellation in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_enable_5thChannelRfiCancellation u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure rateTransitionRequest in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_rateTransitionRequest 3 -/*! \brief Preprocessor variable to relate field to bit position in structure rateTransitionRequest in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_rateTransitionRequest u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure rateTransitionRequest in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_rateTransitionRequest u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure trainingSNR in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_trainingSNR 3 -/*! \brief Preprocessor variable to relate field to bit position in structure trainingSNR in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_trainingSNR u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure trainingSNR in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_trainingSNR u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioning_5 in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_5 4 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioning_5 in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_5 u4.bits_4 -/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioning_5 in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_5 u4.word_4 -/*! \brief Preprocessor variable to relate field to word number in structure nvrDaisyChainKickstart in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_nvrDaisyChainKickstart 4 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrDaisyChainKickstart in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_nvrDaisyChainKickstart u4.bits_4 -/*! \brief Preprocessor variable to relate field to word position in structure nvrDaisyChainKickstart in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_nvrDaisyChainKickstart u4.word_4 -/*! \brief Preprocessor variable to relate field to word number in structure smartPower_downStatus in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_smartPower_downStatus 5 -/*! \brief Preprocessor variable to relate field to bit position in structure smartPower_downStatus in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_smartPower_downStatus u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure smartPower_downStatus in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_smartPower_downStatus u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioning_6 in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_6 5 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioning_6 in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_6 u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioning_6 in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_6 u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure cfrLpDisableTimer in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_cfrLpDisableTimer 5 -/*! \brief Preprocessor variable to relate field to bit position in structure cfrLpDisableTimer in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_cfrLpDisableTimer u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure cfrLpDisableTimer in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_cfrLpDisableTimer u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure cfrLpExtendedMaxwait in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_cfrLpExtendedMaxwait 5 -/*! \brief Preprocessor variable to relate field to bit position in structure cfrLpExtendedMaxwait in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_cfrLpExtendedMaxwait u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure cfrLpExtendedMaxwait in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_cfrLpExtendedMaxwait u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure cfrLpTHP in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_cfrLpTHP 5 -/*! \brief Preprocessor variable to relate field to bit position in structure cfrLpTHP in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_cfrLpTHP u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure cfrLpTHP in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_cfrLpTHP u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure cfrLpSupport in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_cfrLpSupport 5 -/*! \brief Preprocessor variable to relate field to bit position in structure cfrLpSupport in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_cfrLpSupport u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure cfrLpSupport in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_cfrLpSupport u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure cfrDisableTimer in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_cfrDisableTimer 5 -/*! \brief Preprocessor variable to relate field to bit position in structure cfrDisableTimer in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_cfrDisableTimer u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure cfrDisableTimer in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_cfrDisableTimer u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure cfrExtendedMaxwait in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_cfrExtendedMaxwait 5 -/*! \brief Preprocessor variable to relate field to bit position in structure cfrExtendedMaxwait in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_cfrExtendedMaxwait u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure cfrExtendedMaxwait in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_cfrExtendedMaxwait u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure cfrTHP in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_cfrTHP 5 -/*! \brief Preprocessor variable to relate field to bit position in structure cfrTHP in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_cfrTHP u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure cfrTHP in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_cfrTHP u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure cfrSupport in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_cfrSupport 5 -/*! \brief Preprocessor variable to relate field to bit position in structure cfrSupport in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_cfrSupport u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure cfrSupport in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_cfrSupport u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure deadlockAvoidanceEnable in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_deadlockAvoidanceEnable 5 -/*! \brief Preprocessor variable to relate field to bit position in structure deadlockAvoidanceEnable in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_deadlockAvoidanceEnable u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure deadlockAvoidanceEnable in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_deadlockAvoidanceEnable u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure smartPower_downEnable in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_smartPower_downEnable 5 -/*! \brief Preprocessor variable to relate field to bit position in structure smartPower_downEnable in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_smartPower_downEnable u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure smartPower_downEnable in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_smartPower_downEnable u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure dteEnable in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_dteEnable 8 -/*! \brief Preprocessor variable to relate field to bit position in structure dteEnable in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_dteEnable u8.bits_8 -/*! \brief Preprocessor variable to relate field to word position in structure dteEnable in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_dteEnable u8.word_8 -/*! \brief Preprocessor variable to relate field to word number in structure dteDropReportingTimer in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_dteDropReportingTimer 8 -/*! \brief Preprocessor variable to relate field to bit position in structure dteDropReportingTimer in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_dteDropReportingTimer u8.bits_8 -/*! \brief Preprocessor variable to relate field to word position in structure dteDropReportingTimer in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_dteDropReportingTimer u8.word_8 -/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioning_9 in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_9 8 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioning_9 in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_9 u8.bits_8 -/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioning_9 in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_9 u8.word_8 -/*! \brief Preprocessor variable to relate field to word number in structure powerUpStall in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_powerUpStall 9 -/*! \brief Preprocessor variable to relate field to bit position in structure powerUpStall in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_powerUpStall u9.bits_9 -/*! \brief Preprocessor variable to relate field to word position in structure powerUpStall in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_powerUpStall u9.word_9 -/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioning_10 in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_10 9 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioning_10 in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_10 u9.bits_9 -/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioning_10 in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_10 u9.word_9 -/*! \brief Preprocessor variable to relate field to word number in structure loopbackControl in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_loopbackControl 10 -/*! \brief Preprocessor variable to relate field to bit position in structure loopbackControl in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_loopbackControl u10.bits_10 -/*! \brief Preprocessor variable to relate field to word position in structure loopbackControl in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_loopbackControl u10.word_10 -/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioning_11 in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_11 10 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioning_11 in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_11 u10.bits_10 -/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioning_11 in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_11 u10.word_10 -/*! \brief Preprocessor variable to relate field to word number in structure mdiPacketGeneration in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_mdiPacketGeneration 10 -/*! \brief Preprocessor variable to relate field to bit position in structure mdiPacketGeneration in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_mdiPacketGeneration u10.bits_10 -/*! \brief Preprocessor variable to relate field to word position in structure mdiPacketGeneration in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_mdiPacketGeneration u10.word_10 -/*! \brief Preprocessor variable to relate field to word number in structure look_asidePortPacketGeneration in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_look_asidePortPacketGeneration 10 -/*! \brief Preprocessor variable to relate field to bit position in structure look_asidePortPacketGeneration in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_look_asidePortPacketGeneration u10.bits_10 -/*! \brief Preprocessor variable to relate field to word position in structure look_asidePortPacketGeneration in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_look_asidePortPacketGeneration u10.word_10 -/*! \brief Preprocessor variable to relate field to word number in structure systemI_fPacketGeneration in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_systemI_fPacketGeneration 10 -/*! \brief Preprocessor variable to relate field to bit position in structure systemI_fPacketGeneration in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_systemI_fPacketGeneration u10.bits_10 -/*! \brief Preprocessor variable to relate field to word position in structure systemI_fPacketGeneration in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_systemI_fPacketGeneration u10.word_10 -/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioning_11a in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_11a 10 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioning_11a in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_11a u10.bits_10 -/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioning_11a in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_11a u10.word_10 -/*! \brief Preprocessor variable to relate field to word number in structure rate in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_rate 10 -/*! \brief Preprocessor variable to relate field to bit position in structure rate in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_rate u10.bits_10 -/*! \brief Preprocessor variable to relate field to word position in structure rate in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_rate u10.word_10 -/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioning_12 in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_12 11 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioning_12 in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_12 u11.bits_11 -/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioning_12 in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_12 u11.word_11 -/*! \brief Preprocessor variable to relate field to word number in structure enableMacsec in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_enableMacsec 11 -/*! \brief Preprocessor variable to relate field to bit position in structure enableMacsec in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_enableMacsec u11.bits_11 -/*! \brief Preprocessor variable to relate field to word position in structure enableMacsec in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_enableMacsec u11.word_11 -/*! \brief Preprocessor variable to relate field to word number in structure enablePtp in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_enablePtp 11 -/*! \brief Preprocessor variable to relate field to bit position in structure enablePtp in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_enablePtp u11.bits_11 -/*! \brief Preprocessor variable to relate field to word position in structure enablePtp in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_enablePtp u11.word_11 - -/*! \brief Base register address of structure AQ_PifMailboxControl_HHD */ -#define AQ_PifMailboxControl_HHD_baseRegisterAddress 0xC47C -/*! \brief MMD address of structure AQ_PifMailboxControl_HHD */ -#define AQ_PifMailboxControl_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure pifMailboxAddress in AQ_PifMailboxControl_HHD */ -#define AQ_PifMailboxControl_HHD_pifMailboxAddress 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pifMailboxAddress in AQ_PifMailboxControl_HHD */ -#define bits_AQ_PifMailboxControl_HHD_pifMailboxAddress u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pifMailboxAddress in AQ_PifMailboxControl_HHD */ -#define word_AQ_PifMailboxControl_HHD_pifMailboxAddress u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pifMailboxData in AQ_PifMailboxControl_HHD */ -#define AQ_PifMailboxControl_HHD_pifMailboxData 1 -/*! \brief Preprocessor variable to relate field to bit position in structure pifMailboxData in AQ_PifMailboxControl_HHD */ -#define bits_AQ_PifMailboxControl_HHD_pifMailboxData u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure pifMailboxData in AQ_PifMailboxControl_HHD */ -#define word_AQ_PifMailboxControl_HHD_pifMailboxData u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure reservedPifMailboxControl_3 in AQ_PifMailboxControl_HHD */ -#define AQ_PifMailboxControl_HHD_reservedPifMailboxControl_3 2 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedPifMailboxControl_3 in AQ_PifMailboxControl_HHD */ -#define bits_AQ_PifMailboxControl_HHD_reservedPifMailboxControl_3 u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure reservedPifMailboxControl_3 in AQ_PifMailboxControl_HHD */ -#define word_AQ_PifMailboxControl_HHD_reservedPifMailboxControl_3 u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure pifMailboxCommandType in AQ_PifMailboxControl_HHD */ -#define AQ_PifMailboxControl_HHD_pifMailboxCommandType 2 -/*! \brief Preprocessor variable to relate field to bit position in structure pifMailboxCommandType in AQ_PifMailboxControl_HHD */ -#define bits_AQ_PifMailboxControl_HHD_pifMailboxCommandType u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure pifMailboxCommandType in AQ_PifMailboxControl_HHD */ -#define word_AQ_PifMailboxControl_HHD_pifMailboxCommandType u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure pifMailboxMMD in AQ_PifMailboxControl_HHD */ -#define AQ_PifMailboxControl_HHD_pifMailboxMMD 2 -/*! \brief Preprocessor variable to relate field to bit position in structure pifMailboxMMD in AQ_PifMailboxControl_HHD */ -#define bits_AQ_PifMailboxControl_HHD_pifMailboxMMD u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure pifMailboxMMD in AQ_PifMailboxControl_HHD */ -#define word_AQ_PifMailboxControl_HHD_pifMailboxMMD u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure reservedPifMailboxControl_4 in AQ_PifMailboxControl_HHD */ -#define AQ_PifMailboxControl_HHD_reservedPifMailboxControl_4 3 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedPifMailboxControl_4 in AQ_PifMailboxControl_HHD */ -#define bits_AQ_PifMailboxControl_HHD_reservedPifMailboxControl_4 u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure reservedPifMailboxControl_4 in AQ_PifMailboxControl_HHD */ -#define word_AQ_PifMailboxControl_HHD_reservedPifMailboxControl_4 u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure pifMailboxCommandStatus in AQ_PifMailboxControl_HHD */ -#define AQ_PifMailboxControl_HHD_pifMailboxCommandStatus 3 -/*! \brief Preprocessor variable to relate field to bit position in structure pifMailboxCommandStatus in AQ_PifMailboxControl_HHD */ -#define bits_AQ_PifMailboxControl_HHD_pifMailboxCommandStatus u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure pifMailboxCommandStatus in AQ_PifMailboxControl_HHD */ -#define word_AQ_PifMailboxControl_HHD_pifMailboxCommandStatus u3.word_3 - -/*! \brief Base register address of structure AQ_GlobalSmbus_0Provisioning_HHD */ -#define AQ_GlobalSmbus_0Provisioning_HHD_baseRegisterAddress 0xC485 -/*! \brief MMD address of structure AQ_GlobalSmbus_0Provisioning_HHD */ -#define AQ_GlobalSmbus_0Provisioning_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure smb_0SlaveAddress in AQ_GlobalSmbus_0Provisioning_HHD */ -#define AQ_GlobalSmbus_0Provisioning_HHD_smb_0SlaveAddress 0 -/*! \brief Preprocessor variable to relate field to bit position in structure smb_0SlaveAddress in AQ_GlobalSmbus_0Provisioning_HHD */ -#define bits_AQ_GlobalSmbus_0Provisioning_HHD_smb_0SlaveAddress u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure smb_0SlaveAddress in AQ_GlobalSmbus_0Provisioning_HHD */ -#define word_AQ_GlobalSmbus_0Provisioning_HHD_smb_0SlaveAddress u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalSmbus_1Provisioning_HHD */ -#define AQ_GlobalSmbus_1Provisioning_HHD_baseRegisterAddress 0xC495 -/*! \brief MMD address of structure AQ_GlobalSmbus_1Provisioning_HHD */ -#define AQ_GlobalSmbus_1Provisioning_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure smb_1SlaveAddress in AQ_GlobalSmbus_1Provisioning_HHD */ -#define AQ_GlobalSmbus_1Provisioning_HHD_smb_1SlaveAddress 0 -/*! \brief Preprocessor variable to relate field to bit position in structure smb_1SlaveAddress in AQ_GlobalSmbus_1Provisioning_HHD */ -#define bits_AQ_GlobalSmbus_1Provisioning_HHD_smb_1SlaveAddress u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure smb_1SlaveAddress in AQ_GlobalSmbus_1Provisioning_HHD */ -#define word_AQ_GlobalSmbus_1Provisioning_HHD_smb_1SlaveAddress u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalEeeProvisioning_HHD */ -#define AQ_GlobalEeeProvisioning_HHD_baseRegisterAddress 0xC4A0 -/*! \brief MMD address of structure AQ_GlobalEeeProvisioning_HHD */ -#define AQ_GlobalEeeProvisioning_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure eeeMode in AQ_GlobalEeeProvisioning_HHD */ -#define AQ_GlobalEeeProvisioning_HHD_eeeMode 0 -/*! \brief Preprocessor variable to relate field to bit position in structure eeeMode in AQ_GlobalEeeProvisioning_HHD */ -#define bits_AQ_GlobalEeeProvisioning_HHD_eeeMode u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure eeeMode in AQ_GlobalEeeProvisioning_HHD */ -#define word_AQ_GlobalEeeProvisioning_HHD_eeeMode u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalCableDiagnosticStatus_HHD */ -#define AQ_GlobalCableDiagnosticStatus_HHD_baseRegisterAddress 0xC800 -/*! \brief MMD address of structure AQ_GlobalCableDiagnosticStatus_HHD */ -#define AQ_GlobalCableDiagnosticStatus_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure pairAStatus in AQ_GlobalCableDiagnosticStatus_HHD */ -#define AQ_GlobalCableDiagnosticStatus_HHD_pairAStatus 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pairAStatus in AQ_GlobalCableDiagnosticStatus_HHD */ -#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairAStatus u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pairAStatus in AQ_GlobalCableDiagnosticStatus_HHD */ -#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairAStatus u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pairBStatus in AQ_GlobalCableDiagnosticStatus_HHD */ -#define AQ_GlobalCableDiagnosticStatus_HHD_pairBStatus 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pairBStatus in AQ_GlobalCableDiagnosticStatus_HHD */ -#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairBStatus u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pairBStatus in AQ_GlobalCableDiagnosticStatus_HHD */ -#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairBStatus u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pairCStatus in AQ_GlobalCableDiagnosticStatus_HHD */ -#define AQ_GlobalCableDiagnosticStatus_HHD_pairCStatus 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pairCStatus in AQ_GlobalCableDiagnosticStatus_HHD */ -#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairCStatus u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pairCStatus in AQ_GlobalCableDiagnosticStatus_HHD */ -#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairCStatus u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pairDStatus in AQ_GlobalCableDiagnosticStatus_HHD */ -#define AQ_GlobalCableDiagnosticStatus_HHD_pairDStatus 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pairDStatus in AQ_GlobalCableDiagnosticStatus_HHD */ -#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairDStatus u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pairDStatus in AQ_GlobalCableDiagnosticStatus_HHD */ -#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairDStatus u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ -#define AQ_GlobalCableDiagnosticStatus_HHD_pairAReflection_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ -#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairAReflection_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ -#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairAReflection_1 u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ -#define AQ_GlobalCableDiagnosticStatus_HHD_pairAReflection_2 1 -/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ -#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairAReflection_2 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ -#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairAReflection_2 u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure impulseResponseMSW in AQ_GlobalCableDiagnosticStatus_HHD */ -#define AQ_GlobalCableDiagnosticStatus_HHD_impulseResponseMSW 2 -/*! \brief Preprocessor variable to relate field to bit position in structure impulseResponseMSW in AQ_GlobalCableDiagnosticStatus_HHD */ -#define bits_AQ_GlobalCableDiagnosticStatus_HHD_impulseResponseMSW u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure impulseResponseMSW in AQ_GlobalCableDiagnosticStatus_HHD */ -#define word_AQ_GlobalCableDiagnosticStatus_HHD_impulseResponseMSW u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ -#define AQ_GlobalCableDiagnosticStatus_HHD_pairBReflection_1 3 -/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ -#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairBReflection_1 u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ -#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairBReflection_1 u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ -#define AQ_GlobalCableDiagnosticStatus_HHD_pairBReflection_2 3 -/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ -#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairBReflection_2 u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ -#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairBReflection_2 u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure impulseResponseLSW in AQ_GlobalCableDiagnosticStatus_HHD */ -#define AQ_GlobalCableDiagnosticStatus_HHD_impulseResponseLSW 4 -/*! \brief Preprocessor variable to relate field to bit position in structure impulseResponseLSW in AQ_GlobalCableDiagnosticStatus_HHD */ -#define bits_AQ_GlobalCableDiagnosticStatus_HHD_impulseResponseLSW u4.bits_4 -/*! \brief Preprocessor variable to relate field to word position in structure impulseResponseLSW in AQ_GlobalCableDiagnosticStatus_HHD */ -#define word_AQ_GlobalCableDiagnosticStatus_HHD_impulseResponseLSW u4.word_4 -/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ -#define AQ_GlobalCableDiagnosticStatus_HHD_pairCReflection_1 5 -/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ -#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairCReflection_1 u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ -#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairCReflection_1 u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ -#define AQ_GlobalCableDiagnosticStatus_HHD_pairCReflection_2 5 -/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ -#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairCReflection_2 u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ -#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairCReflection_2 u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_1 in AQ_GlobalCableDiagnosticStatus_HHD */ -#define AQ_GlobalCableDiagnosticStatus_HHD_reserved_1 6 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_1 in AQ_GlobalCableDiagnosticStatus_HHD */ -#define bits_AQ_GlobalCableDiagnosticStatus_HHD_reserved_1 u6.bits_6 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_1 in AQ_GlobalCableDiagnosticStatus_HHD */ -#define word_AQ_GlobalCableDiagnosticStatus_HHD_reserved_1 u6.word_6 -/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ -#define AQ_GlobalCableDiagnosticStatus_HHD_pairDReflection_1 7 -/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ -#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairDReflection_1 u7.bits_7 -/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ -#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairDReflection_1 u7.word_7 -/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ -#define AQ_GlobalCableDiagnosticStatus_HHD_pairDReflection_2 7 -/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ -#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairDReflection_2 u7.bits_7 -/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ -#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairDReflection_2 u7.word_7 - -/*! \brief Base register address of structure AQ_GlobalThermalStatus_HHD */ -#define AQ_GlobalThermalStatus_HHD_baseRegisterAddress 0xC820 -/*! \brief MMD address of structure AQ_GlobalThermalStatus_HHD */ -#define AQ_GlobalThermalStatus_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure temperature in AQ_GlobalThermalStatus_HHD */ -#define AQ_GlobalThermalStatus_HHD_temperature 0 -/*! \brief Preprocessor variable to relate field to bit position in structure temperature in AQ_GlobalThermalStatus_HHD */ -#define bits_AQ_GlobalThermalStatus_HHD_temperature u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure temperature in AQ_GlobalThermalStatus_HHD */ -#define word_AQ_GlobalThermalStatus_HHD_temperature u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure temperatureReady in AQ_GlobalThermalStatus_HHD */ -#define AQ_GlobalThermalStatus_HHD_temperatureReady 1 -/*! \brief Preprocessor variable to relate field to bit position in structure temperatureReady in AQ_GlobalThermalStatus_HHD */ -#define bits_AQ_GlobalThermalStatus_HHD_temperatureReady u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure temperatureReady in AQ_GlobalThermalStatus_HHD */ -#define word_AQ_GlobalThermalStatus_HHD_temperatureReady u1.word_1 - -/*! \brief Base register address of structure AQ_GlobalGeneralStatus_HHD */ -#define AQ_GlobalGeneralStatus_HHD_baseRegisterAddress 0xC830 -/*! \brief MMD address of structure AQ_GlobalGeneralStatus_HHD */ -#define AQ_GlobalGeneralStatus_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureFailureState in AQ_GlobalGeneralStatus_HHD */ -#define AQ_GlobalGeneralStatus_HHD_highTemperatureFailureState 0 -/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureFailureState in AQ_GlobalGeneralStatus_HHD */ -#define bits_AQ_GlobalGeneralStatus_HHD_highTemperatureFailureState u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureFailureState in AQ_GlobalGeneralStatus_HHD */ -#define word_AQ_GlobalGeneralStatus_HHD_highTemperatureFailureState u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureFailureState in AQ_GlobalGeneralStatus_HHD */ -#define AQ_GlobalGeneralStatus_HHD_lowTemperatureFailureState 0 -/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureFailureState in AQ_GlobalGeneralStatus_HHD */ -#define bits_AQ_GlobalGeneralStatus_HHD_lowTemperatureFailureState u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureFailureState in AQ_GlobalGeneralStatus_HHD */ -#define word_AQ_GlobalGeneralStatus_HHD_lowTemperatureFailureState u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureWarningState in AQ_GlobalGeneralStatus_HHD */ -#define AQ_GlobalGeneralStatus_HHD_highTemperatureWarningState 0 -/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureWarningState in AQ_GlobalGeneralStatus_HHD */ -#define bits_AQ_GlobalGeneralStatus_HHD_highTemperatureWarningState u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureWarningState in AQ_GlobalGeneralStatus_HHD */ -#define word_AQ_GlobalGeneralStatus_HHD_highTemperatureWarningState u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureWarningState in AQ_GlobalGeneralStatus_HHD */ -#define AQ_GlobalGeneralStatus_HHD_lowTemperatureWarningState 0 -/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureWarningState in AQ_GlobalGeneralStatus_HHD */ -#define bits_AQ_GlobalGeneralStatus_HHD_lowTemperatureWarningState u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureWarningState in AQ_GlobalGeneralStatus_HHD */ -#define word_AQ_GlobalGeneralStatus_HHD_lowTemperatureWarningState u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure processorIntensiveMdioOperationIn_Progress in AQ_GlobalGeneralStatus_HHD */ -#define AQ_GlobalGeneralStatus_HHD_processorIntensiveMdioOperationIn_Progress 1 -/*! \brief Preprocessor variable to relate field to bit position in structure processorIntensiveMdioOperationIn_Progress in AQ_GlobalGeneralStatus_HHD */ -#define bits_AQ_GlobalGeneralStatus_HHD_processorIntensiveMdioOperationIn_Progress u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure processorIntensiveMdioOperationIn_Progress in AQ_GlobalGeneralStatus_HHD */ -#define word_AQ_GlobalGeneralStatus_HHD_processorIntensiveMdioOperationIn_Progress u1.word_1 - -/*! \brief Base register address of structure AQ_GlobalPinStatus_HHD */ -#define AQ_GlobalPinStatus_HHD_baseRegisterAddress 0xC840 -/*! \brief MMD address of structure AQ_GlobalPinStatus_HHD */ -#define AQ_GlobalPinStatus_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure dcMasterN in AQ_GlobalPinStatus_HHD */ -#define AQ_GlobalPinStatus_HHD_dcMasterN 0 -/*! \brief Preprocessor variable to relate field to bit position in structure dcMasterN in AQ_GlobalPinStatus_HHD */ -#define bits_AQ_GlobalPinStatus_HHD_dcMasterN u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure dcMasterN in AQ_GlobalPinStatus_HHD */ -#define word_AQ_GlobalPinStatus_HHD_dcMasterN u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure packageConnectivity in AQ_GlobalPinStatus_HHD */ -#define AQ_GlobalPinStatus_HHD_packageConnectivity 0 -/*! \brief Preprocessor variable to relate field to bit position in structure packageConnectivity in AQ_GlobalPinStatus_HHD */ -#define bits_AQ_GlobalPinStatus_HHD_packageConnectivity u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure packageConnectivity in AQ_GlobalPinStatus_HHD */ -#define word_AQ_GlobalPinStatus_HHD_packageConnectivity u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure txEnable in AQ_GlobalPinStatus_HHD */ -#define AQ_GlobalPinStatus_HHD_txEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure txEnable in AQ_GlobalPinStatus_HHD */ -#define bits_AQ_GlobalPinStatus_HHD_txEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure txEnable in AQ_GlobalPinStatus_HHD */ -#define word_AQ_GlobalPinStatus_HHD_txEnable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure ledPullupState in AQ_GlobalPinStatus_HHD */ -#define AQ_GlobalPinStatus_HHD_ledPullupState 0 -/*! \brief Preprocessor variable to relate field to bit position in structure ledPullupState in AQ_GlobalPinStatus_HHD */ -#define bits_AQ_GlobalPinStatus_HHD_ledPullupState u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure ledPullupState in AQ_GlobalPinStatus_HHD */ -#define word_AQ_GlobalPinStatus_HHD_ledPullupState u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalDaisyChainStatus_HHD */ -#define AQ_GlobalDaisyChainStatus_HHD_baseRegisterAddress 0xC842 -/*! \brief MMD address of structure AQ_GlobalDaisyChainStatus_HHD */ -#define AQ_GlobalDaisyChainStatus_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure rxDaisyChainCalculatedCrc in AQ_GlobalDaisyChainStatus_HHD */ -#define AQ_GlobalDaisyChainStatus_HHD_rxDaisyChainCalculatedCrc 0 -/*! \brief Preprocessor variable to relate field to bit position in structure rxDaisyChainCalculatedCrc in AQ_GlobalDaisyChainStatus_HHD */ -#define bits_AQ_GlobalDaisyChainStatus_HHD_rxDaisyChainCalculatedCrc u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure rxDaisyChainCalculatedCrc in AQ_GlobalDaisyChainStatus_HHD */ -#define word_AQ_GlobalDaisyChainStatus_HHD_rxDaisyChainCalculatedCrc u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalFaultMessage_HHD */ -#define AQ_GlobalFaultMessage_HHD_baseRegisterAddress 0xC850 -/*! \brief MMD address of structure AQ_GlobalFaultMessage_HHD */ -#define AQ_GlobalFaultMessage_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure message in AQ_GlobalFaultMessage_HHD */ -#define AQ_GlobalFaultMessage_HHD_message 0 -/*! \brief Preprocessor variable to relate field to bit position in structure message in AQ_GlobalFaultMessage_HHD */ -#define bits_AQ_GlobalFaultMessage_HHD_message u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure message in AQ_GlobalFaultMessage_HHD */ -#define word_AQ_GlobalFaultMessage_HHD_message u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_baseRegisterAddress 0xC880 -/*! \brief MMD address of structure AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure reserved_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_1 0 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_1 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_1 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_1 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_1 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_1 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_2 0 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_2 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_2 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_2 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_2 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_2 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_3 0 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_3 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_3 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_3 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_3 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_3 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_4 0 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_4 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_4 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_4 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_4 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_4 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_5 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_5 1 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_5 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_5 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_5 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_5 u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_1 u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_6 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_6 1 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_6 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_6 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_6 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_6 u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_2 1 -/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_2 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_2 u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_7 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_7 1 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_7 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_7 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_7 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_7 u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_3 1 -/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_3 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_3 u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_8 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_8 1 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_8 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_8 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_8 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_8 u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_4 1 -/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_4 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_4 u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_9 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_9 2 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_9 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_9 u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_9 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_9 u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_1 2 -/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_1 u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_1 u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_10 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_10 2 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_10 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_10 u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_10 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_10 u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_2 2 -/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_2 u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_2 u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_11 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_11 2 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_11 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_11 u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_11 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_11 u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_3 2 -/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_3 u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_3 u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_12 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_12 2 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_12 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_12 u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_12 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_12 u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_4 2 -/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_4 u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_4 u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_13 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_13 3 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_13 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_13 u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_13 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_13 u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_1 3 -/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_1 u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_1 u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_14 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_14 3 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_14 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_14 u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_14 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_14 u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_2 3 -/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_2 u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_2 u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_15 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_15 3 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_15 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_15 u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_15 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_15 u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_3 3 -/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_3 u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_3 u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_16 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_16 3 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_16 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_16 u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_16 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_16 u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_4 3 -/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_4 u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_4 u3.word_3 - -/*! \brief Base register address of structure AQ_GlobalStatus_HHD */ -#define AQ_GlobalStatus_HHD_baseRegisterAddress 0xC884 -/*! \brief MMD address of structure AQ_GlobalStatus_HHD */ -#define AQ_GlobalStatus_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure reservedStatus_0 in AQ_GlobalStatus_HHD */ -#define AQ_GlobalStatus_HHD_reservedStatus_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedStatus_0 in AQ_GlobalStatus_HHD */ -#define bits_AQ_GlobalStatus_HHD_reservedStatus_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure reservedStatus_0 in AQ_GlobalStatus_HHD */ -#define word_AQ_GlobalStatus_HHD_reservedStatus_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure cableLength in AQ_GlobalStatus_HHD */ -#define AQ_GlobalStatus_HHD_cableLength 0 -/*! \brief Preprocessor variable to relate field to bit position in structure cableLength in AQ_GlobalStatus_HHD */ -#define bits_AQ_GlobalStatus_HHD_cableLength u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure cableLength in AQ_GlobalStatus_HHD */ -#define word_AQ_GlobalStatus_HHD_cableLength u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalReservedStatus_HHD */ -#define AQ_GlobalReservedStatus_HHD_baseRegisterAddress 0xC885 -/*! \brief MMD address of structure AQ_GlobalReservedStatus_HHD */ -#define AQ_GlobalReservedStatus_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure nearlySecondsMSW in AQ_GlobalReservedStatus_HHD */ -#define AQ_GlobalReservedStatus_HHD_nearlySecondsMSW 0 -/*! \brief Preprocessor variable to relate field to bit position in structure nearlySecondsMSW in AQ_GlobalReservedStatus_HHD */ -#define bits_AQ_GlobalReservedStatus_HHD_nearlySecondsMSW u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure nearlySecondsMSW in AQ_GlobalReservedStatus_HHD */ -#define word_AQ_GlobalReservedStatus_HHD_nearlySecondsMSW u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure xenpakNvrStatus in AQ_GlobalReservedStatus_HHD */ -#define AQ_GlobalReservedStatus_HHD_xenpakNvrStatus 0 -/*! \brief Preprocessor variable to relate field to bit position in structure xenpakNvrStatus in AQ_GlobalReservedStatus_HHD */ -#define bits_AQ_GlobalReservedStatus_HHD_xenpakNvrStatus u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure xenpakNvrStatus in AQ_GlobalReservedStatus_HHD */ -#define word_AQ_GlobalReservedStatus_HHD_xenpakNvrStatus u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure firmwareBuildID in AQ_GlobalReservedStatus_HHD */ -#define AQ_GlobalReservedStatus_HHD_firmwareBuildID 0 -/*! \brief Preprocessor variable to relate field to bit position in structure firmwareBuildID in AQ_GlobalReservedStatus_HHD */ -#define bits_AQ_GlobalReservedStatus_HHD_firmwareBuildID u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure firmwareBuildID in AQ_GlobalReservedStatus_HHD */ -#define word_AQ_GlobalReservedStatus_HHD_firmwareBuildID u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure provisioningID in AQ_GlobalReservedStatus_HHD */ -#define AQ_GlobalReservedStatus_HHD_provisioningID 0 -/*! \brief Preprocessor variable to relate field to bit position in structure provisioningID in AQ_GlobalReservedStatus_HHD */ -#define bits_AQ_GlobalReservedStatus_HHD_provisioningID u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure provisioningID in AQ_GlobalReservedStatus_HHD */ -#define word_AQ_GlobalReservedStatus_HHD_provisioningID u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure nearlySecondsLSW in AQ_GlobalReservedStatus_HHD */ -#define AQ_GlobalReservedStatus_HHD_nearlySecondsLSW 1 -/*! \brief Preprocessor variable to relate field to bit position in structure nearlySecondsLSW in AQ_GlobalReservedStatus_HHD */ -#define bits_AQ_GlobalReservedStatus_HHD_nearlySecondsLSW u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure nearlySecondsLSW in AQ_GlobalReservedStatus_HHD */ -#define word_AQ_GlobalReservedStatus_HHD_nearlySecondsLSW u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure dteStatus in AQ_GlobalReservedStatus_HHD */ -#define AQ_GlobalReservedStatus_HHD_dteStatus 2 -/*! \brief Preprocessor variable to relate field to bit position in structure dteStatus in AQ_GlobalReservedStatus_HHD */ -#define bits_AQ_GlobalReservedStatus_HHD_dteStatus u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure dteStatus in AQ_GlobalReservedStatus_HHD */ -#define word_AQ_GlobalReservedStatus_HHD_dteStatus u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure powerUpStallStatus in AQ_GlobalReservedStatus_HHD */ -#define AQ_GlobalReservedStatus_HHD_powerUpStallStatus 2 -/*! \brief Preprocessor variable to relate field to bit position in structure powerUpStallStatus in AQ_GlobalReservedStatus_HHD */ -#define bits_AQ_GlobalReservedStatus_HHD_powerUpStallStatus u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure powerUpStallStatus in AQ_GlobalReservedStatus_HHD */ -#define word_AQ_GlobalReservedStatus_HHD_powerUpStallStatus u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure reservedStatus_3 in AQ_GlobalReservedStatus_HHD */ -#define AQ_GlobalReservedStatus_HHD_reservedStatus_3 2 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedStatus_3 in AQ_GlobalReservedStatus_HHD */ -#define bits_AQ_GlobalReservedStatus_HHD_reservedStatus_3 u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure reservedStatus_3 in AQ_GlobalReservedStatus_HHD */ -#define word_AQ_GlobalReservedStatus_HHD_reservedStatus_3 u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure loopbackStatus in AQ_GlobalReservedStatus_HHD */ -#define AQ_GlobalReservedStatus_HHD_loopbackStatus 3 -/*! \brief Preprocessor variable to relate field to bit position in structure loopbackStatus in AQ_GlobalReservedStatus_HHD */ -#define bits_AQ_GlobalReservedStatus_HHD_loopbackStatus u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure loopbackStatus in AQ_GlobalReservedStatus_HHD */ -#define word_AQ_GlobalReservedStatus_HHD_loopbackStatus u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure reservedStatus_4 in AQ_GlobalReservedStatus_HHD */ -#define AQ_GlobalReservedStatus_HHD_reservedStatus_4 3 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedStatus_4 in AQ_GlobalReservedStatus_HHD */ -#define bits_AQ_GlobalReservedStatus_HHD_reservedStatus_4 u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure reservedStatus_4 in AQ_GlobalReservedStatus_HHD */ -#define word_AQ_GlobalReservedStatus_HHD_reservedStatus_4 u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure mdiPacketGenerationStatus in AQ_GlobalReservedStatus_HHD */ -#define AQ_GlobalReservedStatus_HHD_mdiPacketGenerationStatus 3 -/*! \brief Preprocessor variable to relate field to bit position in structure mdiPacketGenerationStatus in AQ_GlobalReservedStatus_HHD */ -#define bits_AQ_GlobalReservedStatus_HHD_mdiPacketGenerationStatus u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure mdiPacketGenerationStatus in AQ_GlobalReservedStatus_HHD */ -#define word_AQ_GlobalReservedStatus_HHD_mdiPacketGenerationStatus u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure look_asidePortPacketGenerationStatus in AQ_GlobalReservedStatus_HHD */ -#define AQ_GlobalReservedStatus_HHD_look_asidePortPacketGenerationStatus 3 -/*! \brief Preprocessor variable to relate field to bit position in structure look_asidePortPacketGenerationStatus in AQ_GlobalReservedStatus_HHD */ -#define bits_AQ_GlobalReservedStatus_HHD_look_asidePortPacketGenerationStatus u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure look_asidePortPacketGenerationStatus in AQ_GlobalReservedStatus_HHD */ -#define word_AQ_GlobalReservedStatus_HHD_look_asidePortPacketGenerationStatus u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure systemI_fPacketGenerationStatus in AQ_GlobalReservedStatus_HHD */ -#define AQ_GlobalReservedStatus_HHD_systemI_fPacketGenerationStatus 3 -/*! \brief Preprocessor variable to relate field to bit position in structure systemI_fPacketGenerationStatus in AQ_GlobalReservedStatus_HHD */ -#define bits_AQ_GlobalReservedStatus_HHD_systemI_fPacketGenerationStatus u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure systemI_fPacketGenerationStatus in AQ_GlobalReservedStatus_HHD */ -#define word_AQ_GlobalReservedStatus_HHD_systemI_fPacketGenerationStatus u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure reservedStatus_4a in AQ_GlobalReservedStatus_HHD */ -#define AQ_GlobalReservedStatus_HHD_reservedStatus_4a 3 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedStatus_4a in AQ_GlobalReservedStatus_HHD */ -#define bits_AQ_GlobalReservedStatus_HHD_reservedStatus_4a u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure reservedStatus_4a in AQ_GlobalReservedStatus_HHD */ -#define word_AQ_GlobalReservedStatus_HHD_reservedStatus_4a u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure rate in AQ_GlobalReservedStatus_HHD */ -#define AQ_GlobalReservedStatus_HHD_rate 3 -/*! \brief Preprocessor variable to relate field to bit position in structure rate in AQ_GlobalReservedStatus_HHD */ -#define bits_AQ_GlobalReservedStatus_HHD_rate u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure rate in AQ_GlobalReservedStatus_HHD */ -#define word_AQ_GlobalReservedStatus_HHD_rate u3.word_3 - -/*! \brief Base register address of structure AQ_GlobalAlarms_HHD */ -#define AQ_GlobalAlarms_HHD_baseRegisterAddress 0xCC00 -/*! \brief MMD address of structure AQ_GlobalAlarms_HHD */ -#define AQ_GlobalAlarms_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureFailure in AQ_GlobalAlarms_HHD */ -#define AQ_GlobalAlarms_HHD_highTemperatureFailure 0 -/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureFailure in AQ_GlobalAlarms_HHD */ -#define bits_AQ_GlobalAlarms_HHD_highTemperatureFailure u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureFailure in AQ_GlobalAlarms_HHD */ -#define word_AQ_GlobalAlarms_HHD_highTemperatureFailure u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureFailure in AQ_GlobalAlarms_HHD */ -#define AQ_GlobalAlarms_HHD_lowTemperatureFailure 0 -/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureFailure in AQ_GlobalAlarms_HHD */ -#define bits_AQ_GlobalAlarms_HHD_lowTemperatureFailure u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureFailure in AQ_GlobalAlarms_HHD */ -#define word_AQ_GlobalAlarms_HHD_lowTemperatureFailure u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureWarning in AQ_GlobalAlarms_HHD */ -#define AQ_GlobalAlarms_HHD_highTemperatureWarning 0 -/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureWarning in AQ_GlobalAlarms_HHD */ -#define bits_AQ_GlobalAlarms_HHD_highTemperatureWarning u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureWarning in AQ_GlobalAlarms_HHD */ -#define word_AQ_GlobalAlarms_HHD_highTemperatureWarning u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureWarning in AQ_GlobalAlarms_HHD */ -#define AQ_GlobalAlarms_HHD_lowTemperatureWarning 0 -/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureWarning in AQ_GlobalAlarms_HHD */ -#define bits_AQ_GlobalAlarms_HHD_lowTemperatureWarning u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureWarning in AQ_GlobalAlarms_HHD */ -#define word_AQ_GlobalAlarms_HHD_lowTemperatureWarning u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure resetCompleted in AQ_GlobalAlarms_HHD */ -#define AQ_GlobalAlarms_HHD_resetCompleted 0 -/*! \brief Preprocessor variable to relate field to bit position in structure resetCompleted in AQ_GlobalAlarms_HHD */ -#define bits_AQ_GlobalAlarms_HHD_resetCompleted u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure resetCompleted in AQ_GlobalAlarms_HHD */ -#define word_AQ_GlobalAlarms_HHD_resetCompleted u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure deviceFault in AQ_GlobalAlarms_HHD */ -#define AQ_GlobalAlarms_HHD_deviceFault 0 -/*! \brief Preprocessor variable to relate field to bit position in structure deviceFault in AQ_GlobalAlarms_HHD */ -#define bits_AQ_GlobalAlarms_HHD_deviceFault u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure deviceFault in AQ_GlobalAlarms_HHD */ -#define word_AQ_GlobalAlarms_HHD_deviceFault u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmA in AQ_GlobalAlarms_HHD */ -#define AQ_GlobalAlarms_HHD_reservedAlarmA 0 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmA in AQ_GlobalAlarms_HHD */ -#define bits_AQ_GlobalAlarms_HHD_reservedAlarmA u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmA in AQ_GlobalAlarms_HHD */ -#define word_AQ_GlobalAlarms_HHD_reservedAlarmA u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmB in AQ_GlobalAlarms_HHD */ -#define AQ_GlobalAlarms_HHD_reservedAlarmB 0 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmB in AQ_GlobalAlarms_HHD */ -#define bits_AQ_GlobalAlarms_HHD_reservedAlarmB u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmB in AQ_GlobalAlarms_HHD */ -#define word_AQ_GlobalAlarms_HHD_reservedAlarmB u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmC in AQ_GlobalAlarms_HHD */ -#define AQ_GlobalAlarms_HHD_reservedAlarmC 0 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmC in AQ_GlobalAlarms_HHD */ -#define bits_AQ_GlobalAlarms_HHD_reservedAlarmC u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmC in AQ_GlobalAlarms_HHD */ -#define word_AQ_GlobalAlarms_HHD_reservedAlarmC u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmD in AQ_GlobalAlarms_HHD */ -#define AQ_GlobalAlarms_HHD_reservedAlarmD 0 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmD in AQ_GlobalAlarms_HHD */ -#define bits_AQ_GlobalAlarms_HHD_reservedAlarmD u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmD in AQ_GlobalAlarms_HHD */ -#define word_AQ_GlobalAlarms_HHD_reservedAlarmD u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure smartPower_downEntered in AQ_GlobalAlarms_HHD */ -#define AQ_GlobalAlarms_HHD_smartPower_downEntered 1 -/*! \brief Preprocessor variable to relate field to bit position in structure smartPower_downEntered in AQ_GlobalAlarms_HHD */ -#define bits_AQ_GlobalAlarms_HHD_smartPower_downEntered u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure smartPower_downEntered in AQ_GlobalAlarms_HHD */ -#define word_AQ_GlobalAlarms_HHD_smartPower_downEntered u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure xenpakAlarm in AQ_GlobalAlarms_HHD */ -#define AQ_GlobalAlarms_HHD_xenpakAlarm 1 -/*! \brief Preprocessor variable to relate field to bit position in structure xenpakAlarm in AQ_GlobalAlarms_HHD */ -#define bits_AQ_GlobalAlarms_HHD_xenpakAlarm u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure xenpakAlarm in AQ_GlobalAlarms_HHD */ -#define word_AQ_GlobalAlarms_HHD_xenpakAlarm u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure ipPhoneDetect in AQ_GlobalAlarms_HHD */ -#define AQ_GlobalAlarms_HHD_ipPhoneDetect 1 -/*! \brief Preprocessor variable to relate field to bit position in structure ipPhoneDetect in AQ_GlobalAlarms_HHD */ -#define bits_AQ_GlobalAlarms_HHD_ipPhoneDetect u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure ipPhoneDetect in AQ_GlobalAlarms_HHD */ -#define word_AQ_GlobalAlarms_HHD_ipPhoneDetect u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure dteStatusChange in AQ_GlobalAlarms_HHD */ -#define AQ_GlobalAlarms_HHD_dteStatusChange 1 -/*! \brief Preprocessor variable to relate field to bit position in structure dteStatusChange in AQ_GlobalAlarms_HHD */ -#define bits_AQ_GlobalAlarms_HHD_dteStatusChange u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure dteStatusChange in AQ_GlobalAlarms_HHD */ -#define word_AQ_GlobalAlarms_HHD_dteStatusChange u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarms in AQ_GlobalAlarms_HHD */ -#define AQ_GlobalAlarms_HHD_reservedAlarms 1 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarms in AQ_GlobalAlarms_HHD */ -#define bits_AQ_GlobalAlarms_HHD_reservedAlarms u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarms in AQ_GlobalAlarms_HHD */ -#define word_AQ_GlobalAlarms_HHD_reservedAlarms u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure mdioCommandHandlingOverflow in AQ_GlobalAlarms_HHD */ -#define AQ_GlobalAlarms_HHD_mdioCommandHandlingOverflow 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mdioCommandHandlingOverflow in AQ_GlobalAlarms_HHD */ -#define bits_AQ_GlobalAlarms_HHD_mdioCommandHandlingOverflow u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mdioCommandHandlingOverflow in AQ_GlobalAlarms_HHD */ -#define word_AQ_GlobalAlarms_HHD_mdioCommandHandlingOverflow u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure nvrOperationComplete in AQ_GlobalAlarms_HHD */ -#define AQ_GlobalAlarms_HHD_nvrOperationComplete 2 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrOperationComplete in AQ_GlobalAlarms_HHD */ -#define bits_AQ_GlobalAlarms_HHD_nvrOperationComplete u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure nvrOperationComplete in AQ_GlobalAlarms_HHD */ -#define word_AQ_GlobalAlarms_HHD_nvrOperationComplete u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure mailboxOperation_Complete in AQ_GlobalAlarms_HHD */ -#define AQ_GlobalAlarms_HHD_mailboxOperation_Complete 2 -/*! \brief Preprocessor variable to relate field to bit position in structure mailboxOperation_Complete in AQ_GlobalAlarms_HHD */ -#define bits_AQ_GlobalAlarms_HHD_mailboxOperation_Complete u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure mailboxOperation_Complete in AQ_GlobalAlarms_HHD */ -#define word_AQ_GlobalAlarms_HHD_mailboxOperation_Complete u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure upDramParityError in AQ_GlobalAlarms_HHD */ -#define AQ_GlobalAlarms_HHD_upDramParityError 2 -/*! \brief Preprocessor variable to relate field to bit position in structure upDramParityError in AQ_GlobalAlarms_HHD */ -#define bits_AQ_GlobalAlarms_HHD_upDramParityError u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure upDramParityError in AQ_GlobalAlarms_HHD */ -#define word_AQ_GlobalAlarms_HHD_upDramParityError u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure upIramParityError in AQ_GlobalAlarms_HHD */ -#define AQ_GlobalAlarms_HHD_upIramParityError 2 -/*! \brief Preprocessor variable to relate field to bit position in structure upIramParityError in AQ_GlobalAlarms_HHD */ -#define bits_AQ_GlobalAlarms_HHD_upIramParityError u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure upIramParityError in AQ_GlobalAlarms_HHD */ -#define word_AQ_GlobalAlarms_HHD_upIramParityError u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure txEnableStateChange in AQ_GlobalAlarms_HHD */ -#define AQ_GlobalAlarms_HHD_txEnableStateChange 2 -/*! \brief Preprocessor variable to relate field to bit position in structure txEnableStateChange in AQ_GlobalAlarms_HHD */ -#define bits_AQ_GlobalAlarms_HHD_txEnableStateChange u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure txEnableStateChange in AQ_GlobalAlarms_HHD */ -#define word_AQ_GlobalAlarms_HHD_txEnableStateChange u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure mdioMMD_Error in AQ_GlobalAlarms_HHD */ -#define AQ_GlobalAlarms_HHD_mdioMMD_Error 2 -/*! \brief Preprocessor variable to relate field to bit position in structure mdioMMD_Error in AQ_GlobalAlarms_HHD */ -#define bits_AQ_GlobalAlarms_HHD_mdioMMD_Error u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure mdioMMD_Error in AQ_GlobalAlarms_HHD */ -#define word_AQ_GlobalAlarms_HHD_mdioMMD_Error u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure mdioTimeoutError in AQ_GlobalAlarms_HHD */ -#define AQ_GlobalAlarms_HHD_mdioTimeoutError 2 -/*! \brief Preprocessor variable to relate field to bit position in structure mdioTimeoutError in AQ_GlobalAlarms_HHD */ -#define bits_AQ_GlobalAlarms_HHD_mdioTimeoutError u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure mdioTimeoutError in AQ_GlobalAlarms_HHD */ -#define word_AQ_GlobalAlarms_HHD_mdioTimeoutError u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure watchdogTimerAlarm in AQ_GlobalAlarms_HHD */ -#define AQ_GlobalAlarms_HHD_watchdogTimerAlarm 2 -/*! \brief Preprocessor variable to relate field to bit position in structure watchdogTimerAlarm in AQ_GlobalAlarms_HHD */ -#define bits_AQ_GlobalAlarms_HHD_watchdogTimerAlarm u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure watchdogTimerAlarm in AQ_GlobalAlarms_HHD */ -#define word_AQ_GlobalAlarms_HHD_watchdogTimerAlarm u2.word_2 - -/*! \brief Base register address of structure AQ_GlobalInterruptMask_HHD */ -#define AQ_GlobalInterruptMask_HHD_baseRegisterAddress 0xD400 -/*! \brief MMD address of structure AQ_GlobalInterruptMask_HHD */ -#define AQ_GlobalInterruptMask_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureFailureMask in AQ_GlobalInterruptMask_HHD */ -#define AQ_GlobalInterruptMask_HHD_highTemperatureFailureMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureFailureMask in AQ_GlobalInterruptMask_HHD */ -#define bits_AQ_GlobalInterruptMask_HHD_highTemperatureFailureMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureFailureMask in AQ_GlobalInterruptMask_HHD */ -#define word_AQ_GlobalInterruptMask_HHD_highTemperatureFailureMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureFailureMask in AQ_GlobalInterruptMask_HHD */ -#define AQ_GlobalInterruptMask_HHD_lowTemperatureFailureMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureFailureMask in AQ_GlobalInterruptMask_HHD */ -#define bits_AQ_GlobalInterruptMask_HHD_lowTemperatureFailureMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureFailureMask in AQ_GlobalInterruptMask_HHD */ -#define word_AQ_GlobalInterruptMask_HHD_lowTemperatureFailureMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureWarningMask in AQ_GlobalInterruptMask_HHD */ -#define AQ_GlobalInterruptMask_HHD_highTemperatureWarningMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureWarningMask in AQ_GlobalInterruptMask_HHD */ -#define bits_AQ_GlobalInterruptMask_HHD_highTemperatureWarningMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureWarningMask in AQ_GlobalInterruptMask_HHD */ -#define word_AQ_GlobalInterruptMask_HHD_highTemperatureWarningMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureWarningMask in AQ_GlobalInterruptMask_HHD */ -#define AQ_GlobalInterruptMask_HHD_lowTemperatureWarningMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureWarningMask in AQ_GlobalInterruptMask_HHD */ -#define bits_AQ_GlobalInterruptMask_HHD_lowTemperatureWarningMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureWarningMask in AQ_GlobalInterruptMask_HHD */ -#define word_AQ_GlobalInterruptMask_HHD_lowTemperatureWarningMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure resetCompletedMask in AQ_GlobalInterruptMask_HHD */ -#define AQ_GlobalInterruptMask_HHD_resetCompletedMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure resetCompletedMask in AQ_GlobalInterruptMask_HHD */ -#define bits_AQ_GlobalInterruptMask_HHD_resetCompletedMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure resetCompletedMask in AQ_GlobalInterruptMask_HHD */ -#define word_AQ_GlobalInterruptMask_HHD_resetCompletedMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure deviceFaultMask in AQ_GlobalInterruptMask_HHD */ -#define AQ_GlobalInterruptMask_HHD_deviceFaultMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure deviceFaultMask in AQ_GlobalInterruptMask_HHD */ -#define bits_AQ_GlobalInterruptMask_HHD_deviceFaultMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure deviceFaultMask in AQ_GlobalInterruptMask_HHD */ -#define word_AQ_GlobalInterruptMask_HHD_deviceFaultMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmAMask in AQ_GlobalInterruptMask_HHD */ -#define AQ_GlobalInterruptMask_HHD_reservedAlarmAMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmAMask in AQ_GlobalInterruptMask_HHD */ -#define bits_AQ_GlobalInterruptMask_HHD_reservedAlarmAMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmAMask in AQ_GlobalInterruptMask_HHD */ -#define word_AQ_GlobalInterruptMask_HHD_reservedAlarmAMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmBMask in AQ_GlobalInterruptMask_HHD */ -#define AQ_GlobalInterruptMask_HHD_reservedAlarmBMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmBMask in AQ_GlobalInterruptMask_HHD */ -#define bits_AQ_GlobalInterruptMask_HHD_reservedAlarmBMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmBMask in AQ_GlobalInterruptMask_HHD */ -#define word_AQ_GlobalInterruptMask_HHD_reservedAlarmBMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmCMask in AQ_GlobalInterruptMask_HHD */ -#define AQ_GlobalInterruptMask_HHD_reservedAlarmCMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmCMask in AQ_GlobalInterruptMask_HHD */ -#define bits_AQ_GlobalInterruptMask_HHD_reservedAlarmCMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmCMask in AQ_GlobalInterruptMask_HHD */ -#define word_AQ_GlobalInterruptMask_HHD_reservedAlarmCMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmDMask in AQ_GlobalInterruptMask_HHD */ -#define AQ_GlobalInterruptMask_HHD_reservedAlarmDMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmDMask in AQ_GlobalInterruptMask_HHD */ -#define bits_AQ_GlobalInterruptMask_HHD_reservedAlarmDMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmDMask in AQ_GlobalInterruptMask_HHD */ -#define word_AQ_GlobalInterruptMask_HHD_reservedAlarmDMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure smartPower_downEnteredMask in AQ_GlobalInterruptMask_HHD */ -#define AQ_GlobalInterruptMask_HHD_smartPower_downEnteredMask 1 -/*! \brief Preprocessor variable to relate field to bit position in structure smartPower_downEnteredMask in AQ_GlobalInterruptMask_HHD */ -#define bits_AQ_GlobalInterruptMask_HHD_smartPower_downEnteredMask u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure smartPower_downEnteredMask in AQ_GlobalInterruptMask_HHD */ -#define word_AQ_GlobalInterruptMask_HHD_smartPower_downEnteredMask u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure xenpakAlarmMask in AQ_GlobalInterruptMask_HHD */ -#define AQ_GlobalInterruptMask_HHD_xenpakAlarmMask 1 -/*! \brief Preprocessor variable to relate field to bit position in structure xenpakAlarmMask in AQ_GlobalInterruptMask_HHD */ -#define bits_AQ_GlobalInterruptMask_HHD_xenpakAlarmMask u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure xenpakAlarmMask in AQ_GlobalInterruptMask_HHD */ -#define word_AQ_GlobalInterruptMask_HHD_xenpakAlarmMask u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure ipPhoneDetectMask in AQ_GlobalInterruptMask_HHD */ -#define AQ_GlobalInterruptMask_HHD_ipPhoneDetectMask 1 -/*! \brief Preprocessor variable to relate field to bit position in structure ipPhoneDetectMask in AQ_GlobalInterruptMask_HHD */ -#define bits_AQ_GlobalInterruptMask_HHD_ipPhoneDetectMask u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure ipPhoneDetectMask in AQ_GlobalInterruptMask_HHD */ -#define word_AQ_GlobalInterruptMask_HHD_ipPhoneDetectMask u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure dteStatusChangeMask in AQ_GlobalInterruptMask_HHD */ -#define AQ_GlobalInterruptMask_HHD_dteStatusChangeMask 1 -/*! \brief Preprocessor variable to relate field to bit position in structure dteStatusChangeMask in AQ_GlobalInterruptMask_HHD */ -#define bits_AQ_GlobalInterruptMask_HHD_dteStatusChangeMask u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure dteStatusChangeMask in AQ_GlobalInterruptMask_HHD */ -#define word_AQ_GlobalInterruptMask_HHD_dteStatusChangeMask u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmsMask in AQ_GlobalInterruptMask_HHD */ -#define AQ_GlobalInterruptMask_HHD_reservedAlarmsMask 1 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmsMask in AQ_GlobalInterruptMask_HHD */ -#define bits_AQ_GlobalInterruptMask_HHD_reservedAlarmsMask u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmsMask in AQ_GlobalInterruptMask_HHD */ -#define word_AQ_GlobalInterruptMask_HHD_reservedAlarmsMask u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure mdioCommandHandlingOverflowMask in AQ_GlobalInterruptMask_HHD */ -#define AQ_GlobalInterruptMask_HHD_mdioCommandHandlingOverflowMask 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mdioCommandHandlingOverflowMask in AQ_GlobalInterruptMask_HHD */ -#define bits_AQ_GlobalInterruptMask_HHD_mdioCommandHandlingOverflowMask u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mdioCommandHandlingOverflowMask in AQ_GlobalInterruptMask_HHD */ -#define word_AQ_GlobalInterruptMask_HHD_mdioCommandHandlingOverflowMask u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure diagnosticAlarmMask in AQ_GlobalInterruptMask_HHD */ -#define AQ_GlobalInterruptMask_HHD_diagnosticAlarmMask 1 -/*! \brief Preprocessor variable to relate field to bit position in structure diagnosticAlarmMask in AQ_GlobalInterruptMask_HHD */ -#define bits_AQ_GlobalInterruptMask_HHD_diagnosticAlarmMask u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure diagnosticAlarmMask in AQ_GlobalInterruptMask_HHD */ -#define word_AQ_GlobalInterruptMask_HHD_diagnosticAlarmMask u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure nvrOperationCompleteMask in AQ_GlobalInterruptMask_HHD */ -#define AQ_GlobalInterruptMask_HHD_nvrOperationCompleteMask 2 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrOperationCompleteMask in AQ_GlobalInterruptMask_HHD */ -#define bits_AQ_GlobalInterruptMask_HHD_nvrOperationCompleteMask u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure nvrOperationCompleteMask in AQ_GlobalInterruptMask_HHD */ -#define word_AQ_GlobalInterruptMask_HHD_nvrOperationCompleteMask u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure mailboxOperationCompleteMask in AQ_GlobalInterruptMask_HHD */ -#define AQ_GlobalInterruptMask_HHD_mailboxOperationCompleteMask 2 -/*! \brief Preprocessor variable to relate field to bit position in structure mailboxOperationCompleteMask in AQ_GlobalInterruptMask_HHD */ -#define bits_AQ_GlobalInterruptMask_HHD_mailboxOperationCompleteMask u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure mailboxOperationCompleteMask in AQ_GlobalInterruptMask_HHD */ -#define word_AQ_GlobalInterruptMask_HHD_mailboxOperationCompleteMask u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure upDramParityErrorMask in AQ_GlobalInterruptMask_HHD */ -#define AQ_GlobalInterruptMask_HHD_upDramParityErrorMask 2 -/*! \brief Preprocessor variable to relate field to bit position in structure upDramParityErrorMask in AQ_GlobalInterruptMask_HHD */ -#define bits_AQ_GlobalInterruptMask_HHD_upDramParityErrorMask u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure upDramParityErrorMask in AQ_GlobalInterruptMask_HHD */ -#define word_AQ_GlobalInterruptMask_HHD_upDramParityErrorMask u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure upIramParityErrorMask in AQ_GlobalInterruptMask_HHD */ -#define AQ_GlobalInterruptMask_HHD_upIramParityErrorMask 2 -/*! \brief Preprocessor variable to relate field to bit position in structure upIramParityErrorMask in AQ_GlobalInterruptMask_HHD */ -#define bits_AQ_GlobalInterruptMask_HHD_upIramParityErrorMask u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure upIramParityErrorMask in AQ_GlobalInterruptMask_HHD */ -#define word_AQ_GlobalInterruptMask_HHD_upIramParityErrorMask u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure txEnableStateChangeMask in AQ_GlobalInterruptMask_HHD */ -#define AQ_GlobalInterruptMask_HHD_txEnableStateChangeMask 2 -/*! \brief Preprocessor variable to relate field to bit position in structure txEnableStateChangeMask in AQ_GlobalInterruptMask_HHD */ -#define bits_AQ_GlobalInterruptMask_HHD_txEnableStateChangeMask u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure txEnableStateChangeMask in AQ_GlobalInterruptMask_HHD */ -#define word_AQ_GlobalInterruptMask_HHD_txEnableStateChangeMask u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure mdioMMD_ErrorMask in AQ_GlobalInterruptMask_HHD */ -#define AQ_GlobalInterruptMask_HHD_mdioMMD_ErrorMask 2 -/*! \brief Preprocessor variable to relate field to bit position in structure mdioMMD_ErrorMask in AQ_GlobalInterruptMask_HHD */ -#define bits_AQ_GlobalInterruptMask_HHD_mdioMMD_ErrorMask u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure mdioMMD_ErrorMask in AQ_GlobalInterruptMask_HHD */ -#define word_AQ_GlobalInterruptMask_HHD_mdioMMD_ErrorMask u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure mdioTimeoutErrorMask in AQ_GlobalInterruptMask_HHD */ -#define AQ_GlobalInterruptMask_HHD_mdioTimeoutErrorMask 2 -/*! \brief Preprocessor variable to relate field to bit position in structure mdioTimeoutErrorMask in AQ_GlobalInterruptMask_HHD */ -#define bits_AQ_GlobalInterruptMask_HHD_mdioTimeoutErrorMask u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure mdioTimeoutErrorMask in AQ_GlobalInterruptMask_HHD */ -#define word_AQ_GlobalInterruptMask_HHD_mdioTimeoutErrorMask u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure watchdogTimerAlarmMask in AQ_GlobalInterruptMask_HHD */ -#define AQ_GlobalInterruptMask_HHD_watchdogTimerAlarmMask 2 -/*! \brief Preprocessor variable to relate field to bit position in structure watchdogTimerAlarmMask in AQ_GlobalInterruptMask_HHD */ -#define bits_AQ_GlobalInterruptMask_HHD_watchdogTimerAlarmMask u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure watchdogTimerAlarmMask in AQ_GlobalInterruptMask_HHD */ -#define word_AQ_GlobalInterruptMask_HHD_watchdogTimerAlarmMask u2.word_2 - -/*! \brief Base register address of structure AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_baseRegisterAddress 0xFC00 -/*! \brief MMD address of structure AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure pmaStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_pmaStandardAlarm_1Interrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pmaStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_pmaStandardAlarm_1Interrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pmaStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_pmaStandardAlarm_1Interrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pmaStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_pmaStandardAlarm_2Interrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pmaStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_pmaStandardAlarm_2Interrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pmaStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_pmaStandardAlarm_2Interrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_pcsStandardAlarm_1Interrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_pcsStandardAlarm_1Interrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_pcsStandardAlarm_1Interrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_pcsStandardAlarm_2Interrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_pcsStandardAlarm_2Interrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_pcsStandardAlarm_2Interrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_3Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_pcsStandardAlarm_3Interrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_3Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_pcsStandardAlarm_3Interrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_3Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_pcsStandardAlarm_3Interrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure phyXS_StandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_phyXS_StandardAlarms_1Interrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_StandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_phyXS_StandardAlarms_1Interrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure phyXS_StandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_phyXS_StandardAlarms_1Interrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure phyXS_StandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_phyXS_StandardAlarms_2Interrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_StandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_phyXS_StandardAlarms_2Interrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure phyXS_StandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_phyXS_StandardAlarms_2Interrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationStandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_autonegotiationStandardAlarms_1Interrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationStandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_autonegotiationStandardAlarms_1Interrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationStandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_autonegotiationStandardAlarms_1Interrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationStandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_autonegotiationStandardAlarms_2Interrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationStandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_autonegotiationStandardAlarms_2Interrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationStandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_autonegotiationStandardAlarms_2Interrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure gbeStandardAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_gbeStandardAlarmsInterrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure gbeStandardAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_gbeStandardAlarmsInterrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure gbeStandardAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_gbeStandardAlarmsInterrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure allVendorAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_allVendorAlarmsInterrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure allVendorAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_allVendorAlarmsInterrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure allVendorAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_allVendorAlarmsInterrupt u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalChip_wideVendorInterruptFlags_HHD */ -#define AQ_GlobalChip_wideVendorInterruptFlags_HHD_baseRegisterAddress 0xFC01 -/*! \brief MMD address of structure AQ_GlobalChip_wideVendorInterruptFlags_HHD */ -#define AQ_GlobalChip_wideVendorInterruptFlags_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure pmaVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ -#define AQ_GlobalChip_wideVendorInterruptFlags_HHD_pmaVendorAlarmInterrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pmaVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ -#define bits_AQ_GlobalChip_wideVendorInterruptFlags_HHD_pmaVendorAlarmInterrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pmaVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ -#define word_AQ_GlobalChip_wideVendorInterruptFlags_HHD_pmaVendorAlarmInterrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pcsVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ -#define AQ_GlobalChip_wideVendorInterruptFlags_HHD_pcsVendorAlarmInterrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pcsVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ -#define bits_AQ_GlobalChip_wideVendorInterruptFlags_HHD_pcsVendorAlarmInterrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pcsVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ -#define word_AQ_GlobalChip_wideVendorInterruptFlags_HHD_pcsVendorAlarmInterrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure phyXS_VendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ -#define AQ_GlobalChip_wideVendorInterruptFlags_HHD_phyXS_VendorAlarmInterrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_VendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ -#define bits_AQ_GlobalChip_wideVendorInterruptFlags_HHD_phyXS_VendorAlarmInterrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure phyXS_VendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ -#define word_AQ_GlobalChip_wideVendorInterruptFlags_HHD_phyXS_VendorAlarmInterrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ -#define AQ_GlobalChip_wideVendorInterruptFlags_HHD_autonegotiationVendorAlarmInterrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ -#define bits_AQ_GlobalChip_wideVendorInterruptFlags_HHD_autonegotiationVendorAlarmInterrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ -#define word_AQ_GlobalChip_wideVendorInterruptFlags_HHD_autonegotiationVendorAlarmInterrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure gbeVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ -#define AQ_GlobalChip_wideVendorInterruptFlags_HHD_gbeVendorAlarmInterrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure gbeVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ -#define bits_AQ_GlobalChip_wideVendorInterruptFlags_HHD_gbeVendorAlarmInterrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure gbeVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ -#define word_AQ_GlobalChip_wideVendorInterruptFlags_HHD_gbeVendorAlarmInterrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_1Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ -#define AQ_GlobalChip_wideVendorInterruptFlags_HHD_globalAlarms_1Interrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_1Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ -#define bits_AQ_GlobalChip_wideVendorInterruptFlags_HHD_globalAlarms_1Interrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_1Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ -#define word_AQ_GlobalChip_wideVendorInterruptFlags_HHD_globalAlarms_1Interrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_2Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ -#define AQ_GlobalChip_wideVendorInterruptFlags_HHD_globalAlarms_2Interrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_2Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ -#define bits_AQ_GlobalChip_wideVendorInterruptFlags_HHD_globalAlarms_2Interrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_2Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ -#define word_AQ_GlobalChip_wideVendorInterruptFlags_HHD_globalAlarms_2Interrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_3Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ -#define AQ_GlobalChip_wideVendorInterruptFlags_HHD_globalAlarms_3Interrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_3Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ -#define bits_AQ_GlobalChip_wideVendorInterruptFlags_HHD_globalAlarms_3Interrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_3Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ -#define word_AQ_GlobalChip_wideVendorInterruptFlags_HHD_globalAlarms_3Interrupt u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define AQ_GlobalInterruptChip_wideStandardMask_HHD_baseRegisterAddress 0xFF00 -/*! \brief MMD address of structure AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define AQ_GlobalInterruptChip_wideStandardMask_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure pmaStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define AQ_GlobalInterruptChip_wideStandardMask_HHD_pmaStandardAlarm_1InterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pmaStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_pmaStandardAlarm_1InterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pmaStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_pmaStandardAlarm_1InterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pmaStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define AQ_GlobalInterruptChip_wideStandardMask_HHD_pmaStandardAlarm_2InterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pmaStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_pmaStandardAlarm_2InterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pmaStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_pmaStandardAlarm_2InterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define AQ_GlobalInterruptChip_wideStandardMask_HHD_pcsStandardAlarm_1InterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_pcsStandardAlarm_1InterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_pcsStandardAlarm_1InterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define AQ_GlobalInterruptChip_wideStandardMask_HHD_pcsStandardAlarm_2InterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_pcsStandardAlarm_2InterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_pcsStandardAlarm_2InterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_3InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define AQ_GlobalInterruptChip_wideStandardMask_HHD_pcsStandardAlarm_3InterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_3InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_pcsStandardAlarm_3InterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_3InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_pcsStandardAlarm_3InterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure phyXS_StandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define AQ_GlobalInterruptChip_wideStandardMask_HHD_phyXS_StandardAlarms_1InterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_StandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_phyXS_StandardAlarms_1InterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure phyXS_StandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_phyXS_StandardAlarms_1InterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure phyXS_StandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define AQ_GlobalInterruptChip_wideStandardMask_HHD_phyXS_StandardAlarms_2InterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_StandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_phyXS_StandardAlarms_2InterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure phyXS_StandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_phyXS_StandardAlarms_2InterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationStandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define AQ_GlobalInterruptChip_wideStandardMask_HHD_autonegotiationStandardAlarms_1InterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationStandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_autonegotiationStandardAlarms_1InterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationStandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_autonegotiationStandardAlarms_1InterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationStandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define AQ_GlobalInterruptChip_wideStandardMask_HHD_autonegotiationStandardAlarms_2InterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationStandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_autonegotiationStandardAlarms_2InterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationStandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_autonegotiationStandardAlarms_2InterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure gbeStandardAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define AQ_GlobalInterruptChip_wideStandardMask_HHD_gbeStandardAlarmsInterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure gbeStandardAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_gbeStandardAlarmsInterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure gbeStandardAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_gbeStandardAlarmsInterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure allVendorAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define AQ_GlobalInterruptChip_wideStandardMask_HHD_allVendorAlarmsInterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure allVendorAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_allVendorAlarmsInterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure allVendorAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_allVendorAlarmsInterruptMask u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalInterruptChip_wideVendorMask_HHD */ -#define AQ_GlobalInterruptChip_wideVendorMask_HHD_baseRegisterAddress 0xFF01 -/*! \brief MMD address of structure AQ_GlobalInterruptChip_wideVendorMask_HHD */ -#define AQ_GlobalInterruptChip_wideVendorMask_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure pmaVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ -#define AQ_GlobalInterruptChip_wideVendorMask_HHD_pmaVendorAlarmInterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pmaVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ -#define bits_AQ_GlobalInterruptChip_wideVendorMask_HHD_pmaVendorAlarmInterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pmaVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ -#define word_AQ_GlobalInterruptChip_wideVendorMask_HHD_pmaVendorAlarmInterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pcsVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ -#define AQ_GlobalInterruptChip_wideVendorMask_HHD_pcsVendorAlarmInterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pcsVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ -#define bits_AQ_GlobalInterruptChip_wideVendorMask_HHD_pcsVendorAlarmInterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pcsVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ -#define word_AQ_GlobalInterruptChip_wideVendorMask_HHD_pcsVendorAlarmInterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure phyXS_VendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ -#define AQ_GlobalInterruptChip_wideVendorMask_HHD_phyXS_VendorAlarmInterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_VendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ -#define bits_AQ_GlobalInterruptChip_wideVendorMask_HHD_phyXS_VendorAlarmInterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure phyXS_VendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ -#define word_AQ_GlobalInterruptChip_wideVendorMask_HHD_phyXS_VendorAlarmInterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ -#define AQ_GlobalInterruptChip_wideVendorMask_HHD_autonegotiationVendorAlarmInterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ -#define bits_AQ_GlobalInterruptChip_wideVendorMask_HHD_autonegotiationVendorAlarmInterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ -#define word_AQ_GlobalInterruptChip_wideVendorMask_HHD_autonegotiationVendorAlarmInterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure gbeVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ -#define AQ_GlobalInterruptChip_wideVendorMask_HHD_gbeVendorAlarmInterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure gbeVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ -#define bits_AQ_GlobalInterruptChip_wideVendorMask_HHD_gbeVendorAlarmInterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure gbeVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ -#define word_AQ_GlobalInterruptChip_wideVendorMask_HHD_gbeVendorAlarmInterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ -#define AQ_GlobalInterruptChip_wideVendorMask_HHD_globalAlarms_1InterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ -#define bits_AQ_GlobalInterruptChip_wideVendorMask_HHD_globalAlarms_1InterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ -#define word_AQ_GlobalInterruptChip_wideVendorMask_HHD_globalAlarms_1InterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ -#define AQ_GlobalInterruptChip_wideVendorMask_HHD_globalAlarms_2InterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ -#define bits_AQ_GlobalInterruptChip_wideVendorMask_HHD_globalAlarms_2InterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ -#define word_AQ_GlobalInterruptChip_wideVendorMask_HHD_globalAlarms_2InterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_3InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ -#define AQ_GlobalInterruptChip_wideVendorMask_HHD_globalAlarms_3InterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_3InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ -#define bits_AQ_GlobalInterruptChip_wideVendorMask_HHD_globalAlarms_3InterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_3InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ -#define word_AQ_GlobalInterruptChip_wideVendorMask_HHD_globalAlarms_3InterruptMask u0.word_0 -#endif -/*@}*/ -/*@}*/ diff --git a/qca/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers_reversed.h b/qca/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers_reversed.h deleted file mode 100644 index f6fe99831..000000000 --- a/qca/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers_reversed.h +++ /dev/null @@ -1,12123 +0,0 @@ -/*! \file -* This file contains the data structures and doxygen comments -* for the Global Registers block. - */ - -/*! \addtogroup registerMap - @{ -*/ - -/*! \defgroup Global_registers Global Registers -* This module contains the data structures and doxygen comments -* for the Global Registers block. - */ -/*********************************************************************** -* Copyright (c) 2015, Aquantia -* -* Permission to use, copy, modify, and/or distribute this software for any -* purpose with or without fee is hereby granted, provided that the above -* copyright notice and this permission notice appear in all copies. -* -* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -* -* $Date: 2014/04/08 $ -* -* $Label: $ -* -* Description: -* -* This file contains the c header structures for the registers contained in the Global Registers block. -* -* The bit fields in this structure are from MSbit to LSbit -* -***********************************************************************/ - - -/*@{*/ -#ifndef AQ_HHD_GLOBAL_REGS_HEADER -#define AQ_HHD_GLOBAL_REGS_HEADER - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Standard Control 1: 1E.0000 */ -/* Global Standard Control 1: 1E.0000 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Standard Control 1 */ - union - { - struct - { - /*! \brief 1E.0000.F R/WSC Soft Reset - AQ_GlobalStandardControl_1_HHD.u0.bits_0.softReset - - Default = 0x1 - - 1 = Global soft reset - 0 = Normal operation - - - Notes: - Resets the entire PHY. - Setting this bit initiates a global soft reset on all of the digital logic not including the microprocessor (i.e. microprocessor is not reset). Upon completion of the reset sequence, this bit is set back to 0by the microprocessor. Note this bit is OR'ed with the individual MMD resets. This bit should be set to 0 before setting the individual MMD resets. */ - unsigned int softReset : 1; /* 1E.0000.F R/WSC Default = 0x1 */ - /* 1 = Global soft reset - 0 = Normal operation - */ - unsigned int reserved0 : 3; - /*! \brief 1E.0000.B R/WPD Low Power - AQ_GlobalStandardControl_1_HHD.u0.bits_0.lowPower - - Provisionable Default = 0x0 - - 1 = Low-power mode - 0 = Normal operation - - - Notes: - A one written to this register causes the chip to enter low-power mode. This bit puts the entire chip in low-power mode, with only the MDIO and microprocessor functioning, and turns off the analog front-end: i.e. places it in high-impedance mode. Setting this bit also sets all of the Low Power bits in the other MMDs. */ - unsigned int lowPower : 1; /* 1E.0000.B R/WPD Provisionable Default = 0x0 */ - /* 1 = Low-power mode - 0 = Normal operation - */ - unsigned int reserved1 : 11; - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalStandardControl_1_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Standard Device Identifier: 1E.0002 */ -/* Global Standard Device Identifier: 1E.0002 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Standard Device Identifier */ - union - { - struct - { - /*! \brief 1E.0002.F:0 RO Device ID MSW [1F:10] - AQ_GlobalStandardDeviceIdentifier_HHD.u0.bits_0.deviceIdMSW - - - - Bits 31 - 16 of Device ID - */ - unsigned int deviceIdMSW : 16; /* 1E.0002.F:0 RO */ - /* Bits 31 - 16 of Device ID */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Standard Device Identifier */ - union - { - struct - { - /*! \brief 1E.0003.F:0 RO Device ID LSW [F:0] - AQ_GlobalStandardDeviceIdentifier_HHD.u1.bits_1.deviceIdLSW - - - - Bits 15 - 0 of Device ID - */ - unsigned int deviceIdLSW : 16; /* 1E.0003.F:0 RO */ - /* Bits 15 - 0 of Device ID */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_GlobalStandardDeviceIdentifier_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Standard Devices in Package: 1E.0005 */ -/* Global Standard Devices in Package: 1E.0005 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Standard Devices in Package */ - union - { - struct - { - unsigned int reserved0 : 8; - /*! \brief 1E.0005.7 ROS Autonegotiation Present - AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.autonegotiationPresent - - Default = 0x1 - - 1 = Autonegotiation is present in package - 0 = Autonegotiation is not present in package - - Notes: - This is always set to 1, as there is Autonegotiation in the PHY. */ - unsigned int autonegotiationPresent : 1; /* 1E.0005.7 ROS Default = 0x1 */ - /* 1 = Autonegotiation is present in package - 0 = Autonegotiation is not present in package */ - /*! \brief 1E.0005.6 ROS TC Present - AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.tcPresent - - Default = 0x0 - - 1 = TC is present in package - 0 = TC is not present in package - - Notes: - This is always set to 0, as there is no TC functionality in the PHY. */ - unsigned int tcPresent : 1; /* 1E.0005.6 ROS Default = 0x0 */ - /* 1 = TC is present in package - 0 = TC is not present in package */ - /*! \brief 1E.0005.5 ROS DTE XS Present - AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.dteXsPresent - - Default = 0x0 - - 1 = DTE XS is present in package - 0 = DTE XS is not present in package - - - Notes: - This is always set to 0, as there is no DTE XAUI interface in the PHY. */ - unsigned int dteXsPresent : 1; /* 1E.0005.5 ROS Default = 0x0 */ - /* 1 = DTE XS is present in package - 0 = DTE XS is not present in package - */ - /*! \brief 1E.0005.4 ROS PHY XS Present - AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.phyXS_Present - - Default = 0x1 - - 1 = PHY XS is present in package - 0 = PHY XS is not present in package - - Notes: - This is always set to 1 as there is a PHY XS interface in the PHY. */ - unsigned int phyXS_Present : 1; /* 1E.0005.4 ROS Default = 0x1 */ - /* 1 = PHY XS is present in package - 0 = PHY XS is not present in package */ - /*! \brief 1E.0005.3 ROS PCS Present - AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.pcsPresent - - Default = 0x1 - - 1 = PCS is present in package - 0 = PCS is not present in package - - Notes: - This is always set to 1 as there is PCS functionality in the PHY. */ - unsigned int pcsPresent : 1; /* 1E.0005.3 ROS Default = 0x1 */ - /* 1 = PCS is present in package - 0 = PCS is not present in package */ - /*! \brief 1E.0005.2 ROS WIS Present - AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.wisPresent - - Default = 0x0 - - 1 = WIS is present in package - 0 = WIS is not present in package - - Notes: - This is always set to 0, as there is no WIS functionality in the PHY. */ - unsigned int wisPresent : 1; /* 1E.0005.2 ROS Default = 0x0 */ - /* 1 = WIS is present in package - 0 = WIS is not present in package */ - /*! \brief 1E.0005.1 ROS PMA Present - AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.pmaPresent - - Default = 0x1 - - 1 = PMA is present in package - 0 = PMA is not present - - Notes: - This is always set to 1 as there is PMA functionality in the PHY. */ - unsigned int pmaPresent : 1; /* 1E.0005.1 ROS Default = 0x1 */ - /* 1 = PMA is present in package - 0 = PMA is not present */ - /*! \brief 1E.0005.0 ROS Clause 22 Registers Present - AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.clause_22RegistersPresent - - Default = 0x0 - - 1 = Clause 22 registers are present in package - 0 = Clause 22 registers are not present in package - - Notes: - This is always set to 0 in the PHY, as there are no Clause 22 registers in the device. */ - unsigned int clause_22RegistersPresent : 1; /* 1E.0005.0 ROS Default = 0x0 */ - /* 1 = Clause 22 registers are present in package - 0 = Clause 22 registers are not present in package */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalStandardDevicesInPackage_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Standard Vendor Devices in Package: 1E.0006 */ -/* Global Standard Vendor Devices in Package: 1E.0006 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Standard Vendor Devices in Package */ - union - { - struct - { - /*! \brief 1E.0006.F ROS Vendor Specific Device #2 Present - AQ_GlobalStandardVendorDevicesInPackage_HHD.u0.bits_0.vendorSpecificDevice_2Present - - Default = 0x1 - - 1 = Device #2 is present in package - 0 = Device #2 is not present in package - - Notes: - This is always set to 1 as the PHY utilizes this device for the DSP PMA registers. */ - unsigned int vendorSpecificDevice_2Present : 1; /* 1E.0006.F ROS Default = 0x1 */ - /* 1 = Device #2 is present in package - 0 = Device #2 is not present in package */ - /*! \brief 1E.0006.E ROS Vendor Specific Device #1 Present - AQ_GlobalStandardVendorDevicesInPackage_HHD.u0.bits_0.vendorSpecificDevice_1Present - - Default = 0x1 - - 1 = Device #1 is present in package - 0 = Device #1 is not present in package - - Notes: - This is always set to 1 as the PHY utilizes this device for the global control registers. */ - unsigned int vendorSpecificDevice_1Present : 1; /* 1E.0006.E ROS Default = 0x1 */ - /* 1 = Device #1 is present in package - 0 = Device #1 is not present in package */ - /*! \brief 1E.0006.D ROS Clause 22 Extension Present - AQ_GlobalStandardVendorDevicesInPackage_HHD.u0.bits_0.clause_22ExtensionPresent - - Default = 0x1 - - 1 = Clause 22 Extension is present in package - 0 = Clause 22 Extension is not present in package - - Notes: - This is always set to 1 as the PHY utilizes this device for the GbE registers. */ - unsigned int clause_22ExtensionPresent : 1; /* 1E.0006.D ROS Default = 0x1 */ - /* 1 = Clause 22 Extension is present in package - 0 = Clause 22 Extension is not present in package */ - unsigned int reserved0 : 13; - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalStandardVendorDevicesInPackage_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Standard Status 2: 1E.0008 */ -/* Global Standard Status 2: 1E.0008 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Standard Status 2 */ - union - { - struct - { - /*! \brief 1E.0008.F:E ROS Device Present [1:0] - AQ_GlobalStandardStatus_2_HHD.u0.bits_0.devicePresent - - Default = 0x2 - - [F:E] - 0x3 = No device at this address - 0x2 = Device present at this address - 0x1 = No device at this address - 0x0 = No device at this address - - Notes: - This field is always set to 0x2, as the Global MMD resides here in the PHY. */ - unsigned int devicePresent : 2; /* 1E.0008.F:E ROS Default = 0x2 */ - /* [F:E] - 0x3 = No device at this address - 0x2 = Device present at this address - 0x1 = No device at this address - 0x0 = No device at this address */ - unsigned int reserved0 : 14; - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalStandardStatus_2_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Standard Package Identifier: 1E.000E */ -/* Global Standard Package Identifier: 1E.000E */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Standard Package Identifier */ - union - { - struct - { - /*! \brief 1E.000E.F:0 RO Package ID MSW [1F:10] - AQ_GlobalStandardPackageIdentifier_HHD.u0.bits_0.packageIdMSW - - - - Bits 31- 16 of Package ID - */ - unsigned int packageIdMSW : 16; /* 1E.000E.F:0 RO */ - /* Bits 31- 16 of Package ID */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Standard Package Identifier */ - union - { - struct - { - /*! \brief 1E.000F.F:0 RO Package ID LSW [F:0] - AQ_GlobalStandardPackageIdentifier_HHD.u1.bits_1.packageIdLSW - - - - Bits 15 - 0 of Package ID - */ - unsigned int packageIdLSW : 16; /* 1E.000F.F:0 RO */ - /* Bits 15 - 0 of Package ID */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_GlobalStandardPackageIdentifier_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Firmware ID: 1E.0020 */ -/* Global Firmware ID: 1E.0020 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Firmware ID */ - union - { - struct - { - /*! \brief 1E.0020.F:8 RO Firmware Major Revision Number [7:0] - AQ_GlobalFirmwareID_HHD.u0.bits_0.firmwareMajorRevisionNumber - - - - [F:8] = Major revision number - - Notes: - - - The lower six bits of major and minor firmware revision are exchanged in autonegotiation when the PHYID message is sent. */ - unsigned int firmwareMajorRevisionNumber : 8; /* 1E.0020.F:8 RO */ - /* [F:8] = Major revision number */ - /*! \brief 1E.0020.7:0 RO Firmware Minor Revision Number [7:0] - AQ_GlobalFirmwareID_HHD.u0.bits_0.firmwareMinorRevisionNumber - - - - [7:0] = Minor revision number - - Notes: - - - The lower six bits of major and minor firmware revision are exchanged in autonegotiation when the PHYID message is sent. */ - unsigned int firmwareMinorRevisionNumber : 8; /* 1E.0020.7:0 RO */ - /* [7:0] = Minor revision number */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalFirmwareID_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global NVR Interface: 1E.0100 */ -/* Global NVR Interface: 1E.0100 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global NVR Interface */ - union - { - struct - { - /*! \brief 1E.0100.F R/WSC NVR Execute Operation - AQ_GlobalNvrInterface_HHD.u0.bits_0.nvrExecuteOperation - - Default = 0x0 - - 1 = Start NVR Operation - - - - Notes: - When set to 1, the NVR operation will begin. Ensure that the uP is stalled using the See MCP Run Stall bit to ensure no NVR contention. */ - unsigned int nvrExecuteOperation : 1; /* 1E.0100.F R/WSC Default = 0x0 */ - /* 1 = Start NVR Operation - - */ - /*! \brief 1E.0100.E R/W NVR Write Mode - AQ_GlobalNvrInterface_HHD.u0.bits_0.nvrWriteMode - - Default = 0x0 - - 1 = Write to NVR - 0 = Read from NVR - - */ - unsigned int nvrWriteMode : 1; /* 1E.0100.E R/W Default = 0x0 */ - /* 1 = Write to NVR - 0 = Read from NVR - */ - /*! \brief 1E.0100.D R/W Freeze NVR CRC - AQ_GlobalNvrInterface_HHD.u0.bits_0.freezeNvrCrc - - Default = 0x0 - - 1 = Freeze NVR Mailbox CRC calculation register - - - Notes: - To prevent an erroneous answer, this bit should not be set at the same time the See NVR Operation Valid bit is set. */ - unsigned int freezeNvrCrc : 1; /* 1E.0100.D R/W Default = 0x0 */ - /* 1 = Freeze NVR Mailbox CRC calculation register - */ - /*! \brief 1E.0100.C R/WSC Reset NVR CRC - AQ_GlobalNvrInterface_HHD.u0.bits_0.resetNvrCrc - - Default = 0x0 - - 1 = Reset NVR Mailbox CRC calculation register - - - - Notes: - To prevent an erroneous answer, this bit should not be set at the same time the See NVR Operation Valid bit is set. */ - unsigned int resetNvrCrc : 1; /* 1E.0100.C R/WSC Default = 0x0 */ - /* 1 = Reset NVR Mailbox CRC calculation register - - */ - unsigned int reserved0 : 1; - /*! \brief 1E.0100.A R/W NVR Burst - AQ_GlobalNvrInterface_HHD.u0.bits_0.nvrBurst - - Default = 0x0 - - 0 = Single read or write operation of up to 4 bytes - 1 = Burst operation - - - Notes: - When this bit is set, the operation is a burst operation where more than 32-bits is read from the NVR or written to the NVR. This bit should be set to one until the last burst in the read or write operation, when it should be set to zero. It operates by gating the SPI clock, and not restarting it until new data is ready to be written, or the previous contents have been read. Each burst of data requires the NVR Execute Operation bit to be set to initiate the next phase. */ - unsigned int nvrBurst : 1; /* 1E.0100.A R/W Default = 0x0 */ - /* 0 = Single read or write operation of up to 4 bytes - 1 = Burst operation - */ - unsigned int reserved1 : 1; - /*! \brief 1E.0100.8 RO NVR Busy - AQ_GlobalNvrInterface_HHD.u0.bits_0.nvrBusy - - - - 1 = NVR is busy - 0 = NVR is ready - - - Notes: - When set to 1, the NVR is busy. A new NVR operation should not occur until this bit is 0. If the NVR clock is greater than 64/63 of the MDIO clock, this bit never needs to be polled when operating over the MDIO. */ - unsigned int nvrBusy : 1; /* 1E.0100.8 RO */ - /* 1 = NVR is busy - 0 = NVR is ready - */ - /*! \brief 1E.0100.7:0 R/W NVR Opcode [7:0] - AQ_GlobalNvrInterface_HHD.u0.bits_0.nvrOpcode - - Default = 0x03 - - NVR instruction opcode - - */ - unsigned int nvrOpcode : 8; /* 1E.0100.7:0 R/W Default = 0x03 */ - /* NVR instruction opcode - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global NVR Interface */ - union - { - struct - { - /*! \brief 1E.0101.F:0 RO NVR Mailbox CRC [F:0] - AQ_GlobalNvrInterface_HHD.u1.bits_1.nvrMailboxCrc - - - - The running CRC-16 of everything passing through the NVR interface - - - Notes: - The CRC-16 over all data written or read through the NVR interface. The CRC-16 is calculated by dividing the data by: - x^16 + x^12 + x^5 + 1 */ - unsigned int nvrMailboxCrc : 16; /* 1E.0101.F:0 RO */ - /* The running CRC-16 of everything passing through the NVR interface - */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global NVR Interface */ - union - { - struct - { - unsigned int reserved0 : 8; - /*! \brief 1E.0102.7:0 R/W NVR Address MSW [17:10] - AQ_GlobalNvrInterface_HHD.u2.bits_2.nvrAddressMSW - - Default = 0x00 - - NVR address MSW bits [17:10] - - - Notes: - The address of where to read and write from in the NVR. This is self-incrementing and will automatically increment after each read or write operation. The increment amount is based on the data length (i.e. increments by 4 if the data length is 4 bytes) */ - unsigned int nvrAddressMSW : 8; /* 1E.0102.7:0 R/W Default = 0x00 */ - /* NVR address MSW bits [17:10] - */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global NVR Interface */ - union - { - struct - { - /*! \brief 1E.0103.F:0 R/W NVR Address LSW [F:0] - AQ_GlobalNvrInterface_HHD.u3.bits_3.nvrAddressLSW - - Default = 0x0000 - - NVR address LSW bits [F:0] - - - Notes: - The address of where to read and write from in the NVR. This is self-incrementing and will automatically increment after each read or write operation. */ - unsigned int nvrAddressLSW : 16; /* 1E.0103.F:0 R/W Default = 0x0000 */ - /* NVR address LSW bits [F:0] - */ - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of Global NVR Interface */ - union - { - struct - { - /*! \brief 1E.0104.F:0 R/W NVR Data MSW [1F:10] - AQ_GlobalNvrInterface_HHD.u4.bits_4.nvrDataMSW - - Default = 0x0000 - - NVR data MSW bits [1F:10] - - - Notes: - Data is stored and read-out from these registers in little-endian format for operations such as FLASH device ID, and for programming the processor. - - For instance the 64K Atmel device code reads out as two bytes 0x651F into the LSW register, whereas the datasheet indicates that 1F is the first byte read, followed by 65 as the second byte. - - To burst read and write these 4 bytes in the correct order (where DD is written to address x), they should be stored as: - - AA BB in the MSW - CC DD in the LSW. */ - unsigned int nvrDataMSW : 16; /* 1E.0104.F:0 R/W Default = 0x0000 */ - /* NVR data MSW bits [1F:10] - */ - } bits_4; - uint16_t word_4; - } u4; - /*! \brief Union for bit and word level access of word 5 of Global NVR Interface */ - union - { - struct - { - /*! \brief 1E.0105.F:0 R/W NVR Data LSW [F:0] - AQ_GlobalNvrInterface_HHD.u5.bits_5.nvrDataLSW - - Default = 0x0000 - - NVR data LSW bits [F:0] - - - Notes: - Data is stored and read-out from these registers in little-endian format for operations such as FLASH device ID, and for programming the processor. - - For instance the 64K Atmel device code reads out as two bytes 0x651F into the LSW register, whereas the datasheet indicates that 1F is the first byte read, followed by 65 as the second byte. - To burst read and write these 4 bytes in the correct order (where DD is written to address x), they should be stored as: - - AA BB in the MSW - CC DD in the LSW. */ - unsigned int nvrDataLSW : 16; /* 1E.0105.F:0 R/W Default = 0x0000 */ - /* NVR data LSW bits [F:0] - */ - } bits_5; - uint16_t word_5; - } u5; -} AQ_GlobalNvrInterface_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Mailbox Interface: 1E.0200 */ -/* Global Mailbox Interface: 1E.0200 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Mailbox Interface */ - union - { - struct - { - /*! \brief 1E.0200.F R/WSC uP Mailbox Execute Operation - AQ_GlobalMailboxInterface_HHD.u0.bits_0.upMailboxExecuteOperation - - Default = 0x0 - - 1 = Start of mailbox Operation - - - - Notes: - Indicates mailbox is loaded and ready */ - unsigned int upMailboxExecuteOperation : 1; /* 1E.0200.F R/WSC Default = 0x0 */ - /* 1 = Start of mailbox Operation - - */ - /*! \brief 1E.0200.E R/W uP Mailbox Write Mode - AQ_GlobalMailboxInterface_HHD.u0.bits_0.upMailboxWriteMode - - Default = 0x0 - - 1 = Write - 0 = Read - - - Notes: - Mailbox direction */ - unsigned int upMailboxWriteMode : 1; /* 1E.0200.E R/W Default = 0x0 */ - /* 1 = Write - 0 = Read - */ - unsigned int reserved0 : 1; - /*! \brief 1E.0200.C R/WSC Reset uP Mailbox CRC - AQ_GlobalMailboxInterface_HHD.u0.bits_0.resetUpMailboxCrc - - Default = 0x0 - - 1 = Reset uP mailbox CRC calculation register - - - */ - unsigned int resetUpMailboxCrc : 1; /* 1E.0200.C R/WSC Default = 0x0 */ - /* 1 = Reset uP mailbox CRC calculation register - - */ - unsigned int reserved1 : 3; - /*! \brief 1E.0200.8 RO uP Mailbox Busy - AQ_GlobalMailboxInterface_HHD.u0.bits_0.upMailboxBusy - - - - 1 = uP mailbox busy - 0 = uP mailbox ready - - - Notes: - In general the uP will respond within a few processor cycles to any PIF slave request, much faster than the MDIO. If the busy is asserted over multiple MDIO polling cycles, then a H/W error may have occurred and a Global S/W reset or uP reset is required. */ - unsigned int upMailboxBusy : 1; /* 1E.0200.8 RO */ - /* 1 = uP mailbox busy - 0 = uP mailbox ready - */ - unsigned int reserved2 : 8; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Mailbox Interface */ - union - { - struct - { - /*! \brief 1E.0201.F:0 RO uP Mailbox CRC [F:0] - AQ_GlobalMailboxInterface_HHD.u1.bits_1.upMailboxCrc - - - - The running CRC-16 of everything passing through the mailbox interface - - */ - unsigned int upMailboxCrc : 16; /* 1E.0201.F:0 RO */ - /* The running CRC-16 of everything passing through the mailbox interface - */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global Mailbox Interface */ - union - { - struct - { - /*! \brief 1E.0202.F:0 R/W uP Mailbox Address MSW [1F:10] - AQ_GlobalMailboxInterface_HHD.u2.bits_2.upMailboxAddressMSW - - Default = 0x0000 - - uP Mailbox MSW address - - - Notes: - The address of where to read and write from in the Microcontroller Mailbox. This is self-incrementing and automatically increments after each read and write operation.PHY */ - unsigned int upMailboxAddressMSW : 16; /* 1E.0202.F:0 R/W Default = 0x0000 */ - /* uP Mailbox MSW address - */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global Mailbox Interface */ - union - { - struct - { - /*! \brief 1E.0203.F:2 R/W uP Mailbox Address LSW [F:2] - AQ_GlobalMailboxInterface_HHD.u3.bits_3.upMailboxAddressLSW - - Default = 0x0000 - - uP LSW Mailbox address [F:2] - - - Notes: - The address of where to read and write from in the Microcontroller Mailbox. This is self-incrementing and automatically increments after each read and write operation.PHY */ - unsigned int upMailboxAddressLSW : 14; /* 1E.0203.F:2 R/W Default = 0x0000 */ - /* uP LSW Mailbox address [F:2] - */ - /*! \brief 1E.0203.1:0 RO uP Mailbox Address LSW Don't Care [1:0] - AQ_GlobalMailboxInterface_HHD.u3.bits_3.upMailboxAddressLSW_Don_tCare - - - - Least significant uP LSW Mailbox address bits [1:0] - - - Notes: - These bits are always set to 0 since each memory access is on a 4-byte boundary. */ - unsigned int upMailboxAddressLSW_Don_tCare : 2; /* 1E.0203.1:0 RO */ - /* Least significant uP LSW Mailbox address bits [1:0] - */ - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of Global Mailbox Interface */ - union - { - struct - { - /*! \brief 1E.0204.F:0 R/W uP Mailbox Data MSW [1F:10] - AQ_GlobalMailboxInterface_HHD.u4.bits_4.upMailboxDataMSW - - Default = 0x0000 - - uP Mailbox data MSW - - */ - unsigned int upMailboxDataMSW : 16; /* 1E.0204.F:0 R/W Default = 0x0000 */ - /* uP Mailbox data MSW - */ - } bits_4; - uint16_t word_4; - } u4; - /*! \brief Union for bit and word level access of word 5 of Global Mailbox Interface */ - union - { - struct - { - /*! \brief 1E.0205.F:0 R/W uP Mailbox Data LSW [F:0] - AQ_GlobalMailboxInterface_HHD.u5.bits_5.upMailboxDataLSW - - Default = 0x0000 - - uP Mailbox data LSW - - */ - unsigned int upMailboxDataLSW : 16; /* 1E.0205.F:0 R/W Default = 0x0000 */ - /* uP Mailbox data LSW - */ - } bits_5; - uint16_t word_5; - } u5; - /*! \brief Union for bit and word level access of word 6 of Global Mailbox Interface */ - union - { - struct - { - unsigned int reserved0 : 14; - /*! \brief 1E.0206.1 R/W uP Mailbox CRC Read Enable - AQ_GlobalMailboxInterface_HHD.u6.bits_6.upMailboxCrcReadEnable - - Default = 0x0 - - 1 = Update uP mailbox CRC on read - - */ - unsigned int upMailboxCrcReadEnable : 1; /* 1E.0206.1 R/W Default = 0x0 */ - /* 1 = Update uP mailbox CRC on read - */ - unsigned int reserved1 : 1; - } bits_6; - uint16_t word_6; - } u6; -} AQ_GlobalMailboxInterface_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Microprocessor Scratch Pad: 1E.0300 */ -/* Global Microprocessor Scratch Pad: 1E.0300 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Microprocessor Scratch Pad */ - union - { - struct - { - /*! \brief 1E.0300.F:0 R/W Scratch Pad 1[F:0] - AQ_GlobalMicroprocessorScratchPad_HHD.u0.bits_0.scratchPad_1 - - Default = 0x0000 - - General Purpose Scratch Pad - */ - unsigned int scratchPad_1 : 16; /* 1E.0300.F:0 R/W Default = 0x0000 */ - /* General Purpose Scratch Pad */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Microprocessor Scratch Pad */ - union - { - struct - { - /*! \brief 1E.0301.F:0 R/W Scratch Pad 2 [F:0] - AQ_GlobalMicroprocessorScratchPad_HHD.u1.bits_1.scratchPad_2 - - Default = 0x0000 - - General Purpose Scratch Pad - */ - unsigned int scratchPad_2 : 16; /* 1E.0301.F:0 R/W Default = 0x0000 */ - /* General Purpose Scratch Pad */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_GlobalMicroprocessorScratchPad_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Egress Control Register: 1E.5002 */ -/* MSS Egress Control Register: 1E.5002 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Egress Control Register */ - union - { - struct - { - /*! \brief 1E.5002.F:D R/W MSS Egress Ethertype Explicit SECTag LSB [2:0] - AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressEthertypeExplicitSectagLsb - - Default = 0x0 - - Ethertype for explicit SECTag bits 2:0. - - - Notes: - Ethertype for explicity SECTag. */ - unsigned int mssEgressEthertypeExplicitSectagLsb : 3; /* 1E.5002.F:D R/W Default = 0x0 */ - /* Ethertype for explicit SECTag bits 2:0. - */ - /*! \brief 1E.5002.C R/W MSS Egress Clear Global Time - AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressClearGlobalTime - - Default = 0x0 - - 1 = Clear global time - - - - Notes: - Clear global time. */ - unsigned int mssEgressClearGlobalTime : 1; /* 1E.5002.C R/W Default = 0x0 */ - /* 1 = Clear global time - - */ - /*! \brief 1E.5002.B R/W MSS Egress Clear Counter - AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressClearCounter - - Default = 0x0 - - 1 = Clear all MIB counters - - - - Notes: - If this bit is set to 1, all MIB counters will be cleared. */ - unsigned int mssEgressClearCounter : 1; /* 1E.5002.B R/W Default = 0x0 */ - /* 1 = Clear all MIB counters - - */ - /*! \brief 1E.5002.A R/W MSS Egress High Priority - AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressHighPriority - - Default = 0x0 - - 1 = MIB counter clear on read enable - - - - Notes: - If this bit is set to 1, read is given high priority and the MIB count value becomes 0 after read. */ - unsigned int mssEgressHighPriority : 1; /* 1E.5002.A R/W Default = 0x0 */ - /* 1 = MIB counter clear on read enable - - */ - /*! \brief 1E.5002.9 R/W MSS Egress ICV LSB 8 Bytes Enable - AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressIcvLsb_8BytesEnable - - Default = 0x0 - - 1 = Use LSB - 0 = Use MSB - - - - Notes: - This bit selects MSB or LSB 8 bytes selection in the case where the ICV is 8 bytes. - 0 = MSB is used. */ - unsigned int mssEgressIcvLsb_8BytesEnable : 1; /* 1E.5002.9 R/W Default = 0x0 */ - /* 1 = Use LSB - 0 = Use MSB - - */ - /*! \brief 1E.5002.8 R/W MSS Egress External Classification Enable - AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressExternalClassificationEnable - - Default = 0x0 - - 1 = Drop EGPRC miss packets - - - - Notes: - If set, internal classification is bypassed. Should always be set to 0. */ - unsigned int mssEgressExternalClassificationEnable : 1; /* 1E.5002.8 R/W Default = 0x0 */ - /* 1 = Drop EGPRC miss packets - - */ - /*! \brief 1E.5002.7 R/W MSS Egress Explicit SECTag Report Short Length - AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressExplicitSectagReportShortLength - - Default = 0x0 - - Reserved - - - - Notes: - Unused. */ - unsigned int mssEgressExplicitSectagReportShortLength : 1; /* 1E.5002.7 R/W Default = 0x0 */ - /* Reserved - - */ - /*! \brief 1E.5002.6 R/W MSS Egress Drop Invalid SA/SC Packets - AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressDropInvalidSa_scPackets - - Default = 0x0 - - 1 = Drop invalid SA/SC packets - - - - Notes: - Enables dropping of invalid SA/SC packets. */ - unsigned int mssEgressDropInvalidSa_scPackets : 1; /* 1E.5002.6 R/W Default = 0x0 */ - /* 1 = Drop invalid SA/SC packets - - */ - /*! \brief 1E.5002.5 R/W MSS Egress Unmatched Use SC 0 - AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressUnmatchedUseSc_0 - - Default = 0x0 - - 1 = Use SC 0 for unmatched packets - 0 = Unmatched packets are uncontrolled packets - - - - Notes: - Use SC-Index 0 as default SC for unmatched packets. Otherwise the packets are treated as uncontrolled packets. */ - unsigned int mssEgressUnmatchedUseSc_0 : 1; /* 1E.5002.5 R/W Default = 0x0 */ - /* 1 = Use SC 0 for unmatched packets - 0 = Unmatched packets are uncontrolled packets - - */ - /*! \brief 1E.5002.4 R/W MSS Egresss GCM Test Mode - AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgresssGcmTestMode - - Default = 0x0 - - 1 = Enable GCM test mode - - - - Notes: - Enables GCM test mode */ - unsigned int mssEgresssGcmTestMode : 1; /* 1E.5002.4 R/W Default = 0x0 */ - /* 1 = Enable GCM test mode - - */ - /*! \brief 1E.5002.3 R/W MSS Egress GCM Start - AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressGcmStart - - Default = 0x0 - - 1 = Start GCM - - - - Notes: - Indicates GCM to start */ - unsigned int mssEgressGcmStart : 1; /* 1E.5002.3 R/W Default = 0x0 */ - /* 1 = Start GCM - - */ - /*! \brief 1E.5002.2 R/W MSS Egress Drop EGPRC LUT Miss - AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressDropEgprcLutMiss - - Default = 0x0 - - 1 = Drop Egress Classification LUT miss packets - - - - Notes: - Decides whether Egress Pre-Security Classification (EGPRC) LUT miss packets are to be dropped */ - unsigned int mssEgressDropEgprcLutMiss : 1; /* 1E.5002.2 R/W Default = 0x0 */ - /* 1 = Drop Egress Classification LUT miss packets - - */ - /*! \brief 1E.5002.1 R/W MSS Egress Drop KAY Packet - AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressDropKayPacket - - Default = 0x0 - - 1 = Drop KAY packet - - - Notes: - Decides whether KAY packets have to be dropped */ - unsigned int mssEgressDropKayPacket : 1; /* 1E.5002.1 R/W Default = 0x0 */ - /* 1 = Drop KAY packet - */ - /*! \brief 1E.5002.0 R/W MSS Egress Soft Reset - AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressSoftReset - - Default = 0x0 - - 1 = Soft reset - - - Notes: - S/W reset */ - unsigned int mssEgressSoftReset : 1; /* 1E.5002.0 R/W Default = 0x0 */ - /* 1 = Soft reset - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Egress Control Register */ - union - { - struct - { - unsigned int reserved0 : 3; - /*! \brief 1E.5003.C:0 R/W MSS Egress Ethertype Explicit SECTag MSB [F:3] - AQ_MssEgressControlRegister_HHD.u1.bits_1.mssEgressEthertypeExplicitSectagMsb - - Default = 0x0000 - - Ethertype for explicit SECTag bits 15:3. - - - Notes: - Ethertype for explicity SECTag. */ - unsigned int mssEgressEthertypeExplicitSectagMsb : 13; /* 1E.5003.C:0 R/W Default = 0x0000 */ - /* Ethertype for explicit SECTag bits 15:3. - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssEgressControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Egress VLAN TPID 0 Register: 1E.5008 */ -/* MSS Egress VLAN TPID 0 Register: 1E.5008 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Egress VLAN TPID 0 Register */ - union - { - struct - { - /*! \brief 1E.5008.F:0 R/W MSS Egress VLAN STag TPID [F:0] - AQ_MssEgressVlanTpid_0Register_HHD.u0.bits_0.mssEgressVlanStagTpid - - Default = 0x0000 - - STag TPID - - - Notes: - Service Tag Protocol Identifier (TPID) values to identify a VLAN tag. The " See SEC Egress VLAN CP Tag Parse STag " bit must be set to 1 for the incoming packet's TPID to be parsed. */ - unsigned int mssEgressVlanStagTpid : 16; /* 1E.5008.F:0 R/W Default = 0x0000 */ - /* STag TPID - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Egress VLAN TPID 0 Register */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssEgressVlanTpid_0Register_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Egress VLAN TPID 1 Register: 1E.500A */ -/* MSS Egress VLAN TPID 1 Register: 1E.500A */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Egress VLAN TPID 1 Register */ - union - { - struct - { - /*! \brief 1E.500A.F:0 R/W MSS Egress VLAN QTag TPID [F:0] - AQ_MssEgressVlanTpid_1Register_HHD.u0.bits_0.mssEgressVlanQtagTpid - - Default = 0x0000 - - QTag TPID - - - Notes: - Customer Tag Protocol Identifier (TPID) values to identify a VLAN tag. The " See SEC Egress VLAN CP Tag Parse QTag " bit must be set to 1 for the incoming packet's TPID to be parsed. */ - unsigned int mssEgressVlanQtagTpid : 16; /* 1E.500A.F:0 R/W Default = 0x0000 */ - /* QTag TPID - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Egress VLAN TPID 1 Register */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssEgressVlanTpid_1Register_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Egress VLAN Control Register: 1E.500C */ -/* MSS Egress VLAN Control Register: 1E.500C */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Egress VLAN Control Register */ - union - { - struct - { - /*! \brief 1E.500C.F:0 R/W MSS Egress VLAN UP Map Table [F:0] - AQ_MssEgressVlanControlRegister_HHD.u0.bits_0.mssEgressVlanUpMapTable - - Default = 0x0000 - - UP Map table bits 15:0 - - - Notes: - If there is a customer TPID Tag match and no service TPID Tag match or the service TPID Tag match is disabled, the outer TAG's PCP is used to index into this map table to generate the packets user priority. - 2:0 : UP value for customer Tag PCP 0x0 - 5:3: UP value for customer Tag PCP 0x0 - 8:6 : UP value for customer Tag PCP 0x0 - 11:9 : UP value for customer Tag PCP 0x0 - 14:12 : UP value for customer Tag PCP 0x0 - 17:15 : UP value for customer Tag PCP 0x0 - 20:18 : UP value for customer Tag PCP 0x0 - 23:21 : UP value for customer Tag PCP 0x0 */ - unsigned int mssEgressVlanUpMapTable : 16; /* 1E.500C.F:0 R/W Default = 0x0000 */ - /* UP Map table bits 15:0 - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Egress VLAN Control Register */ - union - { - struct - { - /*! \brief 1E.500D.F R/W MSS Egress VLAN QTag Parse Enable - AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanQtagParseEnable - - Default = 0x0 - - 1 = Enable VLAN QTag parsing - - - Notes: - Enable controlled port VLAN customer Tag parsing. When this bit is set to 1, the incoming packet's outer TPID will be compared with the configured " See SEC Egress TPID 1 [F:0] " for matching. If the " See SEC Egress VLAN CP Tag Parse QinQ " bit is set to1, this will also be used to compare the incoming packet's inner TPID. */ - unsigned int mssEgressVlanQtagParseEnable : 1; /* 1E.500D.F R/W Default = 0x0 */ - /* 1 = Enable VLAN QTag parsing - */ - /*! \brief 1E.500D.E R/W MSS Egress VLAN STag Parse Enable - AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanStagParseEnable - - Default = 0x0 - - 1 = Enable VLAN STag parsing - - - Notes: - Enable controlled port VLAN service Tag parsing. When this bit is set to 1, the incoming packets outer TPID will be compared with the configured " See SEC Egress TPID 0 [F:0] " for matching. If the " See SEC Egress VLAN CP Tag Parse QinQ " bit is set to1, this will also be used to compare the incoming packet's inner TPID. */ - unsigned int mssEgressVlanStagParseEnable : 1; /* 1E.500D.E R/W Default = 0x0 */ - /* 1 = Enable VLAN STag parsing - */ - /*! \brief 1E.500D.D R/W MSS Egress VLAN QinQ Parse Enable - AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanQinqParseEnable - - Default = 0x0 - - VLAN CP Tag Parse QinQ - - - Notes: - Enable controlled port VLAN QinQ Tag parsing. When this bit is set to 1 both the outer and inner VLAN Tags will be parsed. */ - unsigned int mssEgressVlanQinqParseEnable : 1; /* 1E.500D.D R/W Default = 0x0 */ - /* VLAN CP Tag Parse QinQ - */ - /*! \brief 1E.500D.C R/W MSS Egress VLAN QTag UP Parse Enable - AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanQtagUpParseEnable - - Default = 0x0 - - VLAN CP Tag QTag UP enable - - - Notes: - Enable controlled port customer VLAN customer Tag user priority field parsing. */ - unsigned int mssEgressVlanQtagUpParseEnable : 1; /* 1E.500D.C R/W Default = 0x0 */ - /* VLAN CP Tag QTag UP enable - */ - /*! \brief 1E.500D.B R/W MSS Egress VLAN STag UP Parse Enable - AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanStagUpParseEnable - - Default = 0x0 - - VLAN CP Tag STag UP enable - - - Notes: - Enable controlled port service VLAN service Tag user priority field parsing. */ - unsigned int mssEgressVlanStagUpParseEnable : 1; /* 1E.500D.B R/W Default = 0x0 */ - /* VLAN CP Tag STag UP enable - */ - /*! \brief 1E.500D.A:8 R/W MSS Egress VLAN UP Default [2:0] - AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanUpDefault - - Default = 0x0 - - UP default - - - Notes: - User priority default */ - unsigned int mssEgressVlanUpDefault : 3; /* 1E.500D.A:8 R/W Default = 0x0 */ - /* UP default - */ - /*! \brief 1E.500D.7:0 R/W MSS Egress VLAN UP Map Table MSW [17:10] - AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanUpMapTableMSW - - Default = 0x00 - - UP Map table bits 23:16 - - - Notes: - If there is a customer TPID Tag match and no service TPID Tag match or the service TPID Tag match is disabled, the outer TAG's PCP is used to index into this map table to generate the packets user priority. - 2:0 : UP value for customer Tag PCP 0x0 - 5:3: UP value for customer Tag PCP 0x0 - 8:6 : UP value for customer Tag PCP 0x0 - 11:9 : UP value for customer Tag PCP 0x0 - 14:12 : UP value for customer Tag PCP 0x0 - 17:15 : UP value for customer Tag PCP 0x0 - 20:18 : UP value for customer Tag PCP 0x0 - 23:21 : UP value for customer Tag PCP 0x0 */ - unsigned int mssEgressVlanUpMapTableMSW : 8; /* 1E.500D.7:0 R/W Default = 0x00 */ - /* UP Map table bits 23:16 - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssEgressVlanControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Egress PN Control Register: 1E.500E */ -/* MSS Egress PN Control Register: 1E.500E */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Egress PN Control Register */ - union - { - struct - { - /*! \brief 1E.500E.F:0 R/W MSS Egress SA PN Threshold LSW [F:0] - AQ_MssEgressPnControlRegister_HHD.u0.bits_0.mssEgressSaPnThresholdLSW - - Default = 0x0000 - - PN threshold bits 15:0 - - - Notes: - Egress PN threshold to generate SA threshold interrupt. */ - unsigned int mssEgressSaPnThresholdLSW : 16; /* 1E.500E.F:0 R/W Default = 0x0000 */ - /* PN threshold bits 15:0 - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Egress PN Control Register */ - union - { - struct - { - /*! \brief 1E.500F.F:0 R/W MSS Egress SA PN Threshold MSW [1F:10] - AQ_MssEgressPnControlRegister_HHD.u1.bits_1.mssEgressSaPnThresholdMSW - - Default = 0x0000 - - PN threshold bits 31:16 - - - Notes: - Egress PN threshold to generate SA threshold interrupt. */ - unsigned int mssEgressSaPnThresholdMSW : 16; /* 1E.500F.F:0 R/W Default = 0x0000 */ - /* PN threshold bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssEgressPnControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Egress MTU Size Control Register: 1E.5010 */ -/* MSS Egress MTU Size Control Register: 1E.5010 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Egress MTU Size Control Register */ - union - { - struct - { - /*! \brief 1E.5010.F:0 R/W MSS Egress Controlled Packet MTU Size [F:0] - AQ_MssEgressMtuSizeControlRegister_HHD.u0.bits_0.mssEgressControlledPacketMtuSize - - Default = 0x05DC - - Maximum transmission unit for controlled packet - - - Notes: - Maximum transmission unit of controlled packet */ - unsigned int mssEgressControlledPacketMtuSize : 16; /* 1E.5010.F:0 R/W Default = 0x05DC */ - /* Maximum transmission unit for controlled packet - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Egress MTU Size Control Register */ - union - { - struct - { - /*! \brief 1E.5011.F:0 R/W MSS Egress Uncontrolled Packet MTU Size [F:0] - AQ_MssEgressMtuSizeControlRegister_HHD.u1.bits_1.mssEgressUncontrolledPacketMtuSize - - Default = 0x05DC - - Maximum transmission unit for uncontrolled packet - - - Notes: - Maximum transmission unit of uncontrolled packet */ - unsigned int mssEgressUncontrolledPacketMtuSize : 16; /* 1E.5011.F:0 R/W Default = 0x05DC */ - /* Maximum transmission unit for uncontrolled packet - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssEgressMtuSizeControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Egress Interrupt Status Register: 1E.505C */ -/* MSS Egress Interrupt Status Register: 1E.505C */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Egress Interrupt Status Register */ - union - { - struct - { - unsigned int reserved0 : 11; - /*! \brief 1E.505C.4 COW MSS Egress ECC Error Interrupt - AQ_MssEgressInterruptStatusRegister_HHD.u0.bits_0.mssEgressEccErrorInterrupt - - Default = 0x0 - - 1 = Interrupt - - - Notes: - Write to 1 to clear. This bit is set when anyone of the memories detects an ECC error. */ - unsigned int mssEgressEccErrorInterrupt : 1; /* 1E.505C.4 COW Default = 0x0 */ - /* 1 = Interrupt - */ - /*! \brief 1E.505C.3 COW MSS Egress MIB Saturation Interrupt - AQ_MssEgressInterruptStatusRegister_HHD.u0.bits_0.mssEgressMibSaturationInterrupt - - Default = 0x0 - - 1 = Interrupt - - - Notes: - Write to 1 to clear. This bit is set when the MIB counters reaches all ones saturation. */ - unsigned int mssEgressMibSaturationInterrupt : 1; /* 1E.505C.3 COW Default = 0x0 */ - /* 1 = Interrupt - */ - /*! \brief 1E.505C.2 COW MSS Egress SA Threshold Expired Interrupt - AQ_MssEgressInterruptStatusRegister_HHD.u0.bits_0.mssEgressSaThresholdExpiredInterrupt - - Default = 0x0 - - 1 = Interrupt - - - Notes: - Write to 1 to clear. This bit is set when the SA PN reaches the See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . */ - unsigned int mssEgressSaThresholdExpiredInterrupt : 1; /* 1E.505C.2 COW Default = 0x0 */ - /* 1 = Interrupt - */ - /*! \brief 1E.505C.1 COW MSS Egress SA Expired Interrupt - AQ_MssEgressInterruptStatusRegister_HHD.u0.bits_0.mssEgressSaExpiredInterrupt - - Default = 0x0 - - 1 = Interrupt - - - Notes: - Write to 1 to clear. This bit is set when the SA PN reaches all ones saturation. */ - unsigned int mssEgressSaExpiredInterrupt : 1; /* 1E.505C.1 COW Default = 0x0 */ - /* 1 = Interrupt - */ - /*! \brief 1E.505C.0 COW MSS Egress Master Interrupt - AQ_MssEgressInterruptStatusRegister_HHD.u0.bits_0.mssEgressMasterInterrupt - - Default = 0x0 - - 1 = Interrupt - - - Notes: - Write to 1 to clear. This bit is set when any one of the above interrupt and the corresponding interrupt enable are both set. The interrupt enable for this bit must also be set for this bit to be set. */ - unsigned int mssEgressMasterInterrupt : 1; /* 1E.505C.0 COW Default = 0x0 */ - /* 1 = Interrupt - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Egress Interrupt Status Register */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssEgressInterruptStatusRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Egress Interrupt Mask Register: 1E.505E */ -/* MSS Egress Interrupt Mask Register: 1E.505E */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Egress Interrupt Mask Register */ - union - { - struct - { - unsigned int reserved0 : 11; - /*! \brief 1E.505E.4 COW MSS Egress ECC Error Interrupt Enable - AQ_MssEgressInterruptMaskRegister_HHD.u0.bits_0.mssEgressEccErrorInterruptEnable - - Default = 0x0 - - 1 = Interrupt enabled - - - Notes: - Write to 1 to clear. This bit is set when anyone of the memories detects an ECC error. */ - unsigned int mssEgressEccErrorInterruptEnable : 1; /* 1E.505E.4 COW Default = 0x0 */ - /* 1 = Interrupt enabled - */ - /*! \brief 1E.505E.3 COW MSS Egress MIB Saturation Interrupt Enable - AQ_MssEgressInterruptMaskRegister_HHD.u0.bits_0.mssEgressMibSaturationInterruptEnable - - Default = 0x0 - - 1 = Interrupt enabled - - - Notes: - Write to 1 to clear. This bit is set when the MIB counters reaches all ones saturation. */ - unsigned int mssEgressMibSaturationInterruptEnable : 1; /* 1E.505E.3 COW Default = 0x0 */ - /* 1 = Interrupt enabled - */ - /*! \brief 1E.505E.2 COW MSS Egress SA Expired Threshold Interrupt Enable - AQ_MssEgressInterruptMaskRegister_HHD.u0.bits_0.mssEgressSaExpiredThresholdInterruptEnable - - Default = 0x0 - - 1 = Interrupt enabled - - - Notes: - Write to 1 to clear. This bit is set when the SA PN reaches the configured threshold See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . */ - unsigned int mssEgressSaExpiredThresholdInterruptEnable : 1; /* 1E.505E.2 COW Default = 0x0 */ - /* 1 = Interrupt enabled - */ - /*! \brief 1E.505E.1 COW MSS Egress SA Expired Interrupt Enable - AQ_MssEgressInterruptMaskRegister_HHD.u0.bits_0.mssEgressSaExpiredInterruptEnable - - Default = 0x0 - - 1 = Interrupt enabled - - - Notes: - Write to 1 to clear. This bit is set when the SA PN reaches all ones saturation. */ - unsigned int mssEgressSaExpiredInterruptEnable : 1; /* 1E.505E.1 COW Default = 0x0 */ - /* 1 = Interrupt enabled - */ - /*! \brief 1E.505E.0 COW MSS Egress Master Interrupt Enable - AQ_MssEgressInterruptMaskRegister_HHD.u0.bits_0.mssEgressMasterInterruptEnable - - Default = 0x0 - - 1 = Interrupt enabled - - - Notes: - Write to 1 to clear. */ - unsigned int mssEgressMasterInterruptEnable : 1; /* 1E.505E.0 COW Default = 0x0 */ - /* 1 = Interrupt enabled - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Egress Interrupt Mask Register */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssEgressInterruptMaskRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Egress SA Expired Status Register: 1E.5060 */ -/* MSS Egress SA Expired Status Register: 1E.5060 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Egress SA Expired Status Register */ - union - { - struct - { - /*! \brief 1E.5060.F:0 COW MSS Egress SA Expired LSW [F:0] - AQ_MssEgressSaExpiredStatusRegister_HHD.u0.bits_0.mssEgressSaExpiredLSW - - Default = 0x0000 - - SA expired bits 15:0 - - - Notes: - Write these bits to 1 to clear. - When set, these bits identify the SA that has expired when the SA PN reaches all-ones saturation. */ - unsigned int mssEgressSaExpiredLSW : 16; /* 1E.5060.F:0 COW Default = 0x0000 */ - /* SA expired bits 15:0 - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Egress SA Expired Status Register */ - union - { - struct - { - /*! \brief 1E.5061.F:0 COW MSS Egress SA Expired MSW [1F:10] - AQ_MssEgressSaExpiredStatusRegister_HHD.u1.bits_1.mssEgressSaExpiredMSW - - Default = 0x0000 - - SA expired bits 31:16 - - - Notes: - Write these bits to 1 to clear. - When set, these bits identify the SA that has expired when the SA PN reaches all-ones saturation. */ - unsigned int mssEgressSaExpiredMSW : 16; /* 1E.5061.F:0 COW Default = 0x0000 */ - /* SA expired bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssEgressSaExpiredStatusRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Egress SA Threshold Expired Status Register: 1E.5062 */ -/* MSS Egress SA Threshold Expired Status Register: 1E.5062 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Egress SA Threshold Expired Status Register */ - union - { - struct - { - /*! \brief 1E.5062.F:0 COW MSS Egress SA Threshold Expired LSW [F:0] - AQ_MssEgressSaThresholdExpiredStatusRegister_HHD.u0.bits_0.mssEgressSaThresholdExpiredLSW - - Default = 0x0000 - - SA threshold expired bits 15:0 - - - Notes: - Write these bits to 1 to clear. - When set, these bits identify the SA that has expired when the SA PN has reached the configured threshold See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . */ - unsigned int mssEgressSaThresholdExpiredLSW : 16; /* 1E.5062.F:0 COW Default = 0x0000 */ - /* SA threshold expired bits 15:0 - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Egress SA Threshold Expired Status Register */ - union - { - struct - { - /*! \brief 1E.5063.F:0 COW MSS Egress SA Threshold Expired MSW [1F:10] - AQ_MssEgressSaThresholdExpiredStatusRegister_HHD.u1.bits_1.mssEgressSaThresholdExpiredMSW - - Default = 0x0000 - - SA threshold expired bits 31:16 - - - Notes: - Write these bits to 1 to clear. - When set, these bits identify the SA that has expired when the SA PN has reached the configured threshold See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . */ - unsigned int mssEgressSaThresholdExpiredMSW : 16; /* 1E.5063.F:0 COW Default = 0x0000 */ - /* SA threshold expired bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssEgressSaThresholdExpiredStatusRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Egress ECC Interrupt Status Register: 1E.5064 */ -/* MSS Egress ECC Interrupt Status Register: 1E.5064 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Egress ECC Interrupt Status Register */ - union - { - struct - { - /*! \brief 1E.5064.F:0 COW MSS Egress SA ECC Error Interrupt LSW [F:0] - AQ_MssEgressEccInterruptStatusRegister_HHD.u0.bits_0.mssEgressSaEccErrorInterruptLSW - - Default = 0x0000 - - SA ECC error interrupt bits 15:0 - - - Notes: - Write these bits to 1 to clear. - When set to 1, indicates that an ECC error occured for the SA. */ - unsigned int mssEgressSaEccErrorInterruptLSW : 16; /* 1E.5064.F:0 COW Default = 0x0000 */ - /* SA ECC error interrupt bits 15:0 - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Egress ECC Interrupt Status Register */ - union - { - struct - { - /*! \brief 1E.5065.F:0 COW MSS Egress SA ECC Error Interrupt MSW [1F:10] - AQ_MssEgressEccInterruptStatusRegister_HHD.u1.bits_1.mssEgressSaEccErrorInterruptMSW - - Default = 0x0000 - - SA ECC error interrupt bits 31:16 - - - Notes: - Write these bits to 1 to clear. - When set to 1, indicates that an ECC error occured for the SA. */ - unsigned int mssEgressSaEccErrorInterruptMSW : 16; /* 1E.5065.F:0 COW Default = 0x0000 */ - /* SA ECC error interrupt bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssEgressEccInterruptStatusRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Egress LUT Address Control Register: 1E.5080 */ -/* MSS Egress LUT Address Control Register: 1E.5080 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Egress LUT Address Control Register */ - union - { - struct - { - /*! \brief 1E.5080.F:C R/W MSS Egress LUT Select [3:0] - AQ_MssEgressLutAddressControlRegister_HHD.u0.bits_0.mssEgressLutSelect - - Default = 0x0 - - LUT select - - - Notes: - 0x0 : Egress MAC Control FIlter (CTLF) LUT - 0x1 : Egress Classification LUT - 0x2 : Egress SC/SA LUT - 0x3 : Egress SMIB */ - unsigned int mssEgressLutSelect : 4; /* 1E.5080.F:C R/W Default = 0x0 */ - /* LUT select - */ - unsigned int reserved0 : 3; - /*! \brief 1E.5080.8:0 R/W MSS Egress LUT Address [8:0] - AQ_MssEgressLutAddressControlRegister_HHD.u0.bits_0.mssEgressLutAddress - - Default = 0x000 - - LUT address - - */ - unsigned int mssEgressLutAddress : 9; /* 1E.5080.8:0 R/W Default = 0x000 */ - /* LUT address - */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_MssEgressLutAddressControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Egress LUT Control Register: 1E.5081 */ -/* MSS Egress LUT Control Register: 1E.5081 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Egress LUT Control Register */ - union - { - struct - { - /*! \brief 1E.5081.F R/W MSS Egress LUT Write - AQ_MssEgressLutControlRegister_HHD.u0.bits_0.mssEgressLutWrite - - Default = 0x0 - - 1 = LUT write - - - Notes: - Setting this bit to 1, will write the LUT. This bit will automatically clear to 0. */ - unsigned int mssEgressLutWrite : 1; /* 1E.5081.F R/W Default = 0x0 */ - /* 1 = LUT write - */ - /*! \brief 1E.5081.E R/W MSS Egress LUT Read - AQ_MssEgressLutControlRegister_HHD.u0.bits_0.mssEgressLutRead - - Default = 0x0 - - 1 = LUT read - - - Notes: - Setting this bit to 1, will read the LUT. This bit will automatically clear to 0. */ - unsigned int mssEgressLutRead : 1; /* 1E.5081.E R/W Default = 0x0 */ - /* 1 = LUT read - */ - unsigned int reserved0 : 14; - } bits_0; - uint16_t word_0; - } u0; -} AQ_MssEgressLutControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Egress LUT Data Control Register: 1E.50A0 */ -/* MSS Egress LUT Data Control Register: 1E.50A0 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50A0.F:0 R/W MSS Egress LUT Data 0 [F:0] - AQ_MssEgressLutDataControlRegister_HHD.u0.bits_0.mssEgressLutData_0 - - Default = 0x0000 - - LUT data bits 15:0 - - */ - unsigned int mssEgressLutData_0 : 16; /* 1E.50A0.F:0 R/W Default = 0x0000 */ - /* LUT data bits 15:0 - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50A1.F:0 R/W MSS Egress LUT Data 1 [1F:10] - AQ_MssEgressLutDataControlRegister_HHD.u1.bits_1.mssEgressLutData_1 - - Default = 0x0000 - - LUT data bits 31:16 - - */ - unsigned int mssEgressLutData_1 : 16; /* 1E.50A1.F:0 R/W Default = 0x0000 */ - /* LUT data bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50A2.F:0 R/W MSS Egress LUT Data 2 [2F:20] - AQ_MssEgressLutDataControlRegister_HHD.u2.bits_2.mssEgressLutData_2 - - Default = 0x0000 - - LUT data bits 47:32 - - */ - unsigned int mssEgressLutData_2 : 16; /* 1E.50A2.F:0 R/W Default = 0x0000 */ - /* LUT data bits 47:32 - */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50A3.F:0 R/W MSS Egress LUT Data 3 [3F:30] - AQ_MssEgressLutDataControlRegister_HHD.u3.bits_3.mssEgressLutData_3 - - Default = 0x0000 - - LUT data bits 63:48 - - */ - unsigned int mssEgressLutData_3 : 16; /* 1E.50A3.F:0 R/W Default = 0x0000 */ - /* LUT data bits 63:48 - */ - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50A4.F:0 R/W MSS Egress LUT Data 4 [4F:40] - AQ_MssEgressLutDataControlRegister_HHD.u4.bits_4.mssEgressLutData_4 - - Default = 0x0000 - - LUT data bits 79:64 - - */ - unsigned int mssEgressLutData_4 : 16; /* 1E.50A4.F:0 R/W Default = 0x0000 */ - /* LUT data bits 79:64 - */ - } bits_4; - uint16_t word_4; - } u4; - /*! \brief Union for bit and word level access of word 5 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50A5.F:0 R/W MSS Egress LUT Data 5 [5F:50] - AQ_MssEgressLutDataControlRegister_HHD.u5.bits_5.mssEgressLutData_5 - - Default = 0x0000 - - LUT data bits 95:80 - - */ - unsigned int mssEgressLutData_5 : 16; /* 1E.50A5.F:0 R/W Default = 0x0000 */ - /* LUT data bits 95:80 - */ - } bits_5; - uint16_t word_5; - } u5; - /*! \brief Union for bit and word level access of word 6 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50A6.F:0 R/W MSS Egress LUT Data 6 [6F:60] - AQ_MssEgressLutDataControlRegister_HHD.u6.bits_6.mssEgressLutData_6 - - Default = 0x0000 - - LUT data bits 111:96 - - */ - unsigned int mssEgressLutData_6 : 16; /* 1E.50A6.F:0 R/W Default = 0x0000 */ - /* LUT data bits 111:96 - */ - } bits_6; - uint16_t word_6; - } u6; - /*! \brief Union for bit and word level access of word 7 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50A7.F:0 R/W MSS Egress LUT Data 7 [7F:70] - AQ_MssEgressLutDataControlRegister_HHD.u7.bits_7.mssEgressLutData_7 - - Default = 0x0000 - - LUT data bits 127:112 - - */ - unsigned int mssEgressLutData_7 : 16; /* 1E.50A7.F:0 R/W Default = 0x0000 */ - /* LUT data bits 127:112 - */ - } bits_7; - uint16_t word_7; - } u7; - /*! \brief Union for bit and word level access of word 8 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50A8.F:0 R/W MSS Egress LUT Data 8 [8F:80] - AQ_MssEgressLutDataControlRegister_HHD.u8.bits_8.mssEgressLutData_8 - - Default = 0x0000 - - LUT data bits 143:128 - - */ - unsigned int mssEgressLutData_8 : 16; /* 1E.50A8.F:0 R/W Default = 0x0000 */ - /* LUT data bits 143:128 - */ - } bits_8; - uint16_t word_8; - } u8; - /*! \brief Union for bit and word level access of word 9 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50A9.F:0 R/W MSS Egress LUT Data 9 [9F:90] - AQ_MssEgressLutDataControlRegister_HHD.u9.bits_9.mssEgressLutData_9 - - Default = 0x0000 - - LUT data bits 159:144 - - */ - unsigned int mssEgressLutData_9 : 16; /* 1E.50A9.F:0 R/W Default = 0x0000 */ - /* LUT data bits 159:144 - */ - } bits_9; - uint16_t word_9; - } u9; - /*! \brief Union for bit and word level access of word 10 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50AA.F:0 R/W MSS Egress LUT Data 10 [AF:A0] - AQ_MssEgressLutDataControlRegister_HHD.u10.bits_10.mssEgressLutData_10 - - Default = 0x0000 - - LUT data bits 175:160 - - */ - unsigned int mssEgressLutData_10 : 16; /* 1E.50AA.F:0 R/W Default = 0x0000 */ - /* LUT data bits 175:160 - */ - } bits_10; - uint16_t word_10; - } u10; - /*! \brief Union for bit and word level access of word 11 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50AB.F:0 R/W MSS Egress LUT Data 11 [BF:B0] - AQ_MssEgressLutDataControlRegister_HHD.u11.bits_11.mssEgressLutData_11 - - Default = 0x0000 - - LUT data bits 191:176 - - */ - unsigned int mssEgressLutData_11 : 16; /* 1E.50AB.F:0 R/W Default = 0x0000 */ - /* LUT data bits 191:176 - */ - } bits_11; - uint16_t word_11; - } u11; - /*! \brief Union for bit and word level access of word 12 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50AC.F:0 R/W MSS Egress LUT Data 12 [CF:C0] - AQ_MssEgressLutDataControlRegister_HHD.u12.bits_12.mssEgressLutData_12 - - Default = 0x0000 - - LUT data bits 207:192 - - */ - unsigned int mssEgressLutData_12 : 16; /* 1E.50AC.F:0 R/W Default = 0x0000 */ - /* LUT data bits 207:192 - */ - } bits_12; - uint16_t word_12; - } u12; - /*! \brief Union for bit and word level access of word 13 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50AD.F:0 R/W MSS Egress LUT Data 13 [DF:D0] - AQ_MssEgressLutDataControlRegister_HHD.u13.bits_13.mssEgressLutData_13 - - Default = 0x0000 - - LUT data bits 223:208 - - */ - unsigned int mssEgressLutData_13 : 16; /* 1E.50AD.F:0 R/W Default = 0x0000 */ - /* LUT data bits 223:208 - */ - } bits_13; - uint16_t word_13; - } u13; - /*! \brief Union for bit and word level access of word 14 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50AE.F:0 R/W MSS Egress LUT Data 14 [EF:E0] - AQ_MssEgressLutDataControlRegister_HHD.u14.bits_14.mssEgressLutData_14 - - Default = 0x0000 - - LUT data bits 239:224 - - */ - unsigned int mssEgressLutData_14 : 16; /* 1E.50AE.F:0 R/W Default = 0x0000 */ - /* LUT data bits 239:224 - */ - } bits_14; - uint16_t word_14; - } u14; - /*! \brief Union for bit and word level access of word 15 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50AF.F:0 R/W MSS Egress LUT Data 15 [FF:F0] - AQ_MssEgressLutDataControlRegister_HHD.u15.bits_15.mssEgressLutData_15 - - Default = 0x0000 - - LUT data bits 255:240 - - */ - unsigned int mssEgressLutData_15 : 16; /* 1E.50AF.F:0 R/W Default = 0x0000 */ - /* LUT data bits 255:240 - */ - } bits_15; - uint16_t word_15; - } u15; - /*! \brief Union for bit and word level access of word 16 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50B0.F:0 R/W MSS Egress LUT Data 16 [10F:100] - AQ_MssEgressLutDataControlRegister_HHD.u16.bits_16.mssEgressLutData_16 - - Default = 0x0000 - - LUT data bits 271:256 - - */ - unsigned int mssEgressLutData_16 : 16; /* 1E.50B0.F:0 R/W Default = 0x0000 */ - /* LUT data bits 271:256 - */ - } bits_16; - uint16_t word_16; - } u16; - /*! \brief Union for bit and word level access of word 17 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50B1.F:0 R/W MSS Egress LUT Data 17 [11F:110] - AQ_MssEgressLutDataControlRegister_HHD.u17.bits_17.mssEgressLutData_17 - - Default = 0x0000 - - LUT data bits 287:272 - - */ - unsigned int mssEgressLutData_17 : 16; /* 1E.50B1.F:0 R/W Default = 0x0000 */ - /* LUT data bits 287:272 - */ - } bits_17; - uint16_t word_17; - } u17; - /*! \brief Union for bit and word level access of word 18 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50B2.F:0 R/W MSS Egress LUT Data 18 [12F:120] - AQ_MssEgressLutDataControlRegister_HHD.u18.bits_18.mssEgressLutData_18 - - Default = 0x0000 - - LUT data bits 303:288 - - */ - unsigned int mssEgressLutData_18 : 16; /* 1E.50B2.F:0 R/W Default = 0x0000 */ - /* LUT data bits 303:288 - */ - } bits_18; - uint16_t word_18; - } u18; - /*! \brief Union for bit and word level access of word 19 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50B3.F:0 R/W MSS Egress LUT Data 19 [13F:130] - AQ_MssEgressLutDataControlRegister_HHD.u19.bits_19.mssEgressLutData_19 - - Default = 0x0000 - - LUT data bits 319:304 - - */ - unsigned int mssEgressLutData_19 : 16; /* 1E.50B3.F:0 R/W Default = 0x0000 */ - /* LUT data bits 319:304 - */ - } bits_19; - uint16_t word_19; - } u19; - /*! \brief Union for bit and word level access of word 20 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50B4.F:0 R/W MSS Egress LUT Data 20 [14F:140] - AQ_MssEgressLutDataControlRegister_HHD.u20.bits_20.mssEgressLutData_20 - - Default = 0x0000 - - LUT data bits 335:320 - - */ - unsigned int mssEgressLutData_20 : 16; /* 1E.50B4.F:0 R/W Default = 0x0000 */ - /* LUT data bits 335:320 - */ - } bits_20; - uint16_t word_20; - } u20; - /*! \brief Union for bit and word level access of word 21 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50B5.F:0 R/W MSS Egress LUT Data 21 [15F:150] - AQ_MssEgressLutDataControlRegister_HHD.u21.bits_21.mssEgressLutData_21 - - Default = 0x0000 - - LUT data bits 351:336 - - */ - unsigned int mssEgressLutData_21 : 16; /* 1E.50B5.F:0 R/W Default = 0x0000 */ - /* LUT data bits 351:336 - */ - } bits_21; - uint16_t word_21; - } u21; - /*! \brief Union for bit and word level access of word 22 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50B6.F:0 R/W MSS Egress LUT Data 22 [16F:160] - AQ_MssEgressLutDataControlRegister_HHD.u22.bits_22.mssEgressLutData_22 - - Default = 0x0000 - - LUT data bits 367:352 - - */ - unsigned int mssEgressLutData_22 : 16; /* 1E.50B6.F:0 R/W Default = 0x0000 */ - /* LUT data bits 367:352 - */ - } bits_22; - uint16_t word_22; - } u22; - /*! \brief Union for bit and word level access of word 23 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50B7.F:0 R/W MSS Egress LUT Data 23 [17F:170] - AQ_MssEgressLutDataControlRegister_HHD.u23.bits_23.mssEgressLutData_23 - - Default = 0x0000 - - LUT data bits 383:368 - - */ - unsigned int mssEgressLutData_23 : 16; /* 1E.50B7.F:0 R/W Default = 0x0000 */ - /* LUT data bits 383:368 - */ - } bits_23; - uint16_t word_23; - } u23; - /*! \brief Union for bit and word level access of word 24 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50B8.F:0 R/W MSS Egress LUT Data 24 [18F:180] - AQ_MssEgressLutDataControlRegister_HHD.u24.bits_24.mssEgressLutData_24 - - Default = 0x0000 - - LUT data bits 399:384 - - */ - unsigned int mssEgressLutData_24 : 16; /* 1E.50B8.F:0 R/W Default = 0x0000 */ - /* LUT data bits 399:384 - */ - } bits_24; - uint16_t word_24; - } u24; - /*! \brief Union for bit and word level access of word 25 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50B9.F:0 R/W MSS Egress LUT Data 25 [19F:190] - AQ_MssEgressLutDataControlRegister_HHD.u25.bits_25.mssEgressLutData_25 - - Default = 0x0000 - - LUT data bits 415:400 - - */ - unsigned int mssEgressLutData_25 : 16; /* 1E.50B9.F:0 R/W Default = 0x0000 */ - /* LUT data bits 415:400 - */ - } bits_25; - uint16_t word_25; - } u25; - /*! \brief Union for bit and word level access of word 26 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50BA.F:0 R/W MSS Egress LUT Data 26 [1AF:1A0] - AQ_MssEgressLutDataControlRegister_HHD.u26.bits_26.mssEgressLutData_26 - - Default = 0x0000 - - LUT data bits 431:416 - - */ - unsigned int mssEgressLutData_26 : 16; /* 1E.50BA.F:0 R/W Default = 0x0000 */ - /* LUT data bits 431:416 - */ - } bits_26; - uint16_t word_26; - } u26; - /*! \brief Union for bit and word level access of word 27 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50BB.F:0 R/W MSS Egress LUT Data 27 [1BF:1B0] - AQ_MssEgressLutDataControlRegister_HHD.u27.bits_27.mssEgressLutData_27 - - Default = 0x0000 - - LUT data bits 447:432 - - */ - unsigned int mssEgressLutData_27 : 16; /* 1E.50BB.F:0 R/W Default = 0x0000 */ - /* LUT data bits 447:432 - */ - } bits_27; - uint16_t word_27; - } u27; -} AQ_MssEgressLutDataControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System General Control Register: 1E.6004 */ -/* MSM System General Control Register: 1E.6004 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System General Control Register */ - union - { - struct - { - /*! \brief 1E.6004.F R/W MSM System PHY Tx Enable - AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemPhyTxEnable - - Default = 0x0 - - 1 = Enable PHY Tx - - - Notes: - Directly controls the phy_tx_ena pin. */ - unsigned int msmSystemPhyTxEnable : 1; /* 1E.6004.F R/W Default = 0x0 */ - /* 1 = Enable PHY Tx - */ - /*! \brief 1E.6004.E R/W MSM System Rx Error Discard - AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemRxErrorDiscard - - Default = 0x0 - - 1 = Enable discard of received errored frames - - - Notes: - Rx errored frame discard enable. When set to 1, any frame received with an error is discarded and not forwarded to the client interface. When set to 0, errored frames are forwarded to the client interface with ff_rx_err asserted. - Note : It is recommended to set this bit to 1 only when store and forward operation is enabled (RX_SECTION_FULL TBD). */ - unsigned int msmSystemRxErrorDiscard : 1; /* 1E.6004.E R/W Default = 0x0 */ - /* 1 = Enable discard of received errored frames - */ - /*! \brief 1E.6004.D R/W MSM System Control Frame Enable - AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemControlFrameEnable - - Default = 0x0 - - 1 = Control frame enabled - - - Notes: - MAC control frame enable. When set to 1, the MAC control frames with any Opcode other than 0x0001 are accepted and forwarded to the client interface. When set to 0, MAC control frames with any opcode other than 0x0001 are silently discarded. */ - unsigned int msmSystemControlFrameEnable : 1; /* 1E.6004.D R/W Default = 0x0 */ - /* 1 = Control frame enabled - */ - /*! \brief 1E.6004.C R/WSC MSM System Soft Reset - AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemSoftReset - - Default = 0x0 - - 1 = Soft reset - - - Notes: - Software reset. Self clearing bit. When set to 1, resets all statistic counters as well as the Tx and Rx FIFOs. It should be issued after all traffic has been stopped as a result of clearing the Rx/Tx enable bits ( See MAC Rx Enable set to 0 and See MAC Tx Enable set to 0). - Note : Can lead to an Rx interface (ff_rx_xxx) violations to the application if the reset is issued in the middle of a receive frame transfer. Then the end of packet (assertion of ff_rx_eop) is lost and the application should be prepeared to handle this exception. */ - unsigned int msmSystemSoftReset : 1; /* 1E.6004.C R/WSC Default = 0x0 */ - /* 1 = Soft reset - */ - /*! \brief 1E.6004.B R/W MSM System Tx Pad Enable - AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemTxPadEnable - - Default = 0x1 - - 1 = Enable Tx padding - - - Notes: - When set to 1, enable padding of frames in the Tx direction. When set to 0, the MAC will not extend frames from the application to a minimum of 64 bytes, allowing to transmit short frames (violating the Ethernet mimimum size requirements). Must be set to 1 for normal operation. */ - unsigned int msmSystemTxPadEnable : 1; /* 1E.6004.B R/W Default = 0x1 */ - /* 1 = Enable Tx padding - */ - /*! \brief 1E.6004.A R/W MSM System Tx CRC Append - AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemTxCrcAppend - - Default = 0x0 - - 1 = Append Tx CRC - - - Notes: - Permanently enable CRC append on transmit. If set to 1, the Tx will append a CRC to all transmitted frames. If set to 0, CRC append can be controlled on a per frame basis using the pin ff_tx_crc. - This configuration bit is OR'ed with the external ff_tx_crc pin to instruct the Tx to append a CRC to transmitted frames. The ff_tx_crc pin is tied to 0. */ - unsigned int msmSystemTxCrcAppend : 1; /* 1E.6004.A R/W Default = 0x0 */ - /* 1 = Append Tx CRC - */ - /*! \brief 1E.6004.9 R/W MSM System Tx Address Insert Enable - AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemTxAddressInsertEnable - - Default = 0x0 - - 1 = Insert Tx MAC source address - - - Notes: - Set the source MAC address on transmit. If set to 1, the MAC overwrites the source MAC address with the MAC programmed address in all transmitted frames. When set to 0, the source MAC address is transmitted unmodified from the MAC Tx client application. */ - unsigned int msmSystemTxAddressInsertEnable : 1; /* 1E.6004.9 R/W Default = 0x0 */ - /* 1 = Insert Tx MAC source address - */ - /*! \brief 1E.6004.8 R/W MSM System Pause Ignore - AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemPauseIgnore - - Default = 0x0 - - 1 = Ignore pause frames - - - Notes: - Ignore pause frame quanta. If set to 1, received pause frames are ignored by the MAC. When set to 0, the Tx is stopped for the amount of time specified in the pause quanta received within the pause frame. */ - unsigned int msmSystemPauseIgnore : 1; /* 1E.6004.8 R/W Default = 0x0 */ - /* 1 = Ignore pause frames - */ - /*! \brief 1E.6004.7 R/W MSM System Pause Forward - AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemPauseForward - - Default = 0x0 - - 1 = Enable Pause forwarding - - - Notes: - Terminate or forward pause frames. If set to 1, pause frames are forwarded to the user application. In normal mode, when set to 0, pause frames are terminated and discarded within the MAC. */ - unsigned int msmSystemPauseForward : 1; /* 1E.6004.7 R/W Default = 0x0 */ - /* 1 = Enable Pause forwarding - */ - /*! \brief 1E.6004.6 R/W MSM System CRC Forward - AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemCrcForward - - Default = 0x0 - - 1 = Enable CRC forwarding - - - Notes: - When set to 1, the CRC field of the received frames is forwarded with the frame to the user application. If disabled, the CRC field is stripped from the frame. - Note : If padding is enabled ( See MAC PAD Enable set to 1), this bit is ignored. */ - unsigned int msmSystemCrcForward : 1; /* 1E.6004.6 R/W Default = 0x0 */ - /* 1 = Enable CRC forwarding - */ - /*! \brief 1E.6004.5 R/W MSM System PAD Enable - AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemPadEnable - - Default = 0x0 - - 1 = Enable frame padding removal on Rx - - - Notes: - When set to 1, enable frame padding removal on the Rx path. If enabled, padding is removed before the frame is transferred to the MAC client application. If disabled, no padding is removed on the Rx by the MAC. - Note : On Tx, the MAC always adds padding as required. */ - unsigned int msmSystemPadEnable : 1; /* 1E.6004.5 R/W Default = 0x0 */ - /* 1 = Enable frame padding removal on Rx - */ - /*! \brief 1E.6004.4 R/W MSM System Promiscuous Mode - AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemPromiscuousMode - - Default = 0x0 - - 1 = Promiscuous mode - - - Notes: - When set to 1, all frames are received without any MAC address filtering. */ - unsigned int msmSystemPromiscuousMode : 1; /* 1E.6004.4 R/W Default = 0x0 */ - /* 1 = Promiscuous mode - */ - /*! \brief 1E.6004.3 R/W MSM System WAN Mode - AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemWanMode - - Default = 0x0 - - 1 = WAN mode - 0 = LAN mode - - - Notes: - WAN mode enable. Sets WAN mode when set to 1 and LAN mode when set to 0. Note: When changing the mode, verifiy correct setting of the Tx IPG. */ - unsigned int msmSystemWanMode : 1; /* 1E.6004.3 R/W Default = 0x0 */ - /* 1 = WAN mode - 0 = LAN mode - */ - unsigned int reserved0 : 1; - /*! \brief 1E.6004.1 R/W MSM System Rx Enable - AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemRxEnable - - Default = 0x0 - - 1 = Rx enable - - Notes: - MAC Tx path enable. Should be set to 1 to enable the MAC Tx path. Should be set to 0 to disable the MAC Tx path. */ - unsigned int msmSystemRxEnable : 1; /* 1E.6004.1 R/W Default = 0x0 */ - /* 1 = Rx enable */ - /*! \brief 1E.6004.0 R/W MSM System Tx Enable - AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemTxEnable - - Default = 0x0 - - 1 = Tx enable - - Notes: - MAC Rx path enable. Should be set to 1 to enable the MAC Rx path. Should be set to 0 to disable the MAC Rx path. */ - unsigned int msmSystemTxEnable : 1; /* 1E.6004.0 R/W Default = 0x0 */ - /* 1 = Tx enable */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System General Control Register */ - union - { - struct - { - unsigned int reserved0 : 8; - /*! \brief 1E.6005.7 R/W MSM System Tx Low Power IDLE Enable - AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemTxLowPowerIdleEnable - - Default = 0x0 - - 1 = Transmit LPI enable - - - Notes: - Transmit low power IDLE enable. When set to 1, the MAC completes the transmission of the current frame and generates low power IDLE sequences (LPI) to the XGMII/SGMII. When set to 0, the MAC operates in normal mode. This bit is OR'ed with the reg_lowp_ena pin. */ - unsigned int msmSystemTxLowPowerIdleEnable : 1; /* 1E.6005.7 R/W Default = 0x0 */ - /* 1 = Transmit LPI enable - */ - unsigned int reserved1 : 1; - /*! \brief 1E.6005.5 R/W MSM System SFD Check Disable - AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemSfdCheckDisable - - Default = 0x0 - - 1 = Disable SFD check - - - Notes: - Disable check of SFD (0xD5) character at frame start. When set to 1, the frame is accepted even if the SFD byte following the preamble is not 0xD5. When set to 0, a frame is accepted only if the SFD byte is found with the value 0xD5. */ - unsigned int msmSystemSfdCheckDisable : 1; /* 1E.6005.5 R/W Default = 0x0 */ - /* 1 = Disable SFD check - */ - unsigned int reserved2 : 1; - /*! \brief 1E.6005.3 R/W MSM System Priority Flow Control Enable - AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemPriorityFlowControlEnable - - Default = 0x0 - - 1 = Enable priority flow control - 0 = Enable link flow control - - - Notes: - Enable priority flow control (PFC) mode of operation. When set to 0, the MAC uses standard link pause frames. When set to 1, the MAC will transmit and accept PFC frames. */ - unsigned int msmSystemPriorityFlowControlEnable : 1; /* 1E.6005.3 R/W Default = 0x0 */ - /* 1 = Enable priority flow control - 0 = Enable link flow control - */ - /*! \brief 1E.6005.2 R/W MSM System IDLE Column Count Extend - AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemIdleColumnCountExtend - - Default = 0x0 - - 1 = Extend IDLE column count - - Notes: - When set to 1, extends the RS layer IDLE column counter by 2x. The IEEE 802.3ae defines the fault condition to be cleared after 128 columns of IDLE have been received. If the MAC operates together with a WAN mode PCS (WIS) it may may happen (depending on PCS) that this period is too short to bridge the IDLE stuffing occurring in this mode, leading to a toggling fault indication. In this case, extending the counter helps to aoivd toggling fault indications. */ - unsigned int msmSystemIdleColumnCountExtend : 1; /* 1E.6005.2 R/W Default = 0x0 */ - /* 1 = Extend IDLE column count */ - /*! \brief 1E.6005.1 R/W MSM System Length Check Disable - AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemLengthCheckDisable - - Default = 0x0 - - 1 = Disable length check - - Notes: - Payload length check disable. When set to 0, the MAC checks the frames payload length with the frame length/type field. When set to 1, the payload length check is disabled. */ - unsigned int msmSystemLengthCheckDisable : 1; /* 1E.6005.1 R/W Default = 0x0 */ - /* 1 = Disable length check */ - /*! \brief 1E.6005.0 R/W MSM System Force Send IDLE - AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemForceSendIdle - - Default = 0x0 - - 1 = Force send idle - - Notes: - When set to 1, suppress any frame transmissions and forces IDLE n the Tx interface instead of frames. This control affects the MAC reconciliation layer (RS) which acts after all MAC datapath has processed the frame. - Note : Does not have an effect on fault handling (i.e. reception of local fault will still cause transmit of remote fault). - Must be 0 for normal operation. */ - unsigned int msmSystemForceSendIdle : 1; /* 1E.6005.0 R/W Default = 0x0 */ - /* 1 = Force send idle */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemGeneralControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System FIFO Control Register: 1E.600E */ -/* MSM System FIFO Control Register: 1E.600E */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System FIFO Control Register */ - union - { - struct - { - unsigned int reserved0 : 8; - /*! \brief 1E.600E.7:0 R/W MSM System Rx FIFO Full Threshold [7:0] - AQ_MsmSystemFifoControlRegister_HHD.u0.bits_0.msmSystemRxFifoFullThreshold - - Default = 0x08 - - Rx FIFO full threshold - - Notes: - All threshold values are in steps of FIFO words. */ - unsigned int msmSystemRxFifoFullThreshold : 8; /* 1E.600E.7:0 R/W Default = 0x08 */ - /* Rx FIFO full threshold */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System FIFO Control Register */ - union - { - struct - { - unsigned int reserved0 : 8; - /*! \brief 1E.600F.7:0 R/W MSM System Rx FIFO Empty Threshold [7:0] - AQ_MsmSystemFifoControlRegister_HHD.u1.bits_1.msmSystemRxFifoEmptyThreshold - - Default = 0x00 - - Rx FIFO empty threshold - - Notes: - All threshold values are in steps of FIFO words. */ - unsigned int msmSystemRxFifoEmptyThreshold : 8; /* 1E.600F.7:0 R/W Default = 0x00 */ - /* Rx FIFO empty threshold */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of MSM System FIFO Control Register */ - union - { - struct - { - unsigned int reserved0 : 10; - /*! \brief 1E.6010.5:0 R/W MSM System Tx FIFO Full Threshold [5:0] - AQ_MsmSystemFifoControlRegister_HHD.u2.bits_2.msmSystemTxFifoFullThreshold - - Default = 0x08 - - Tx FIFO full threshold - - Notes: - All threshold values are in steps of FIFO words. */ - unsigned int msmSystemTxFifoFullThreshold : 6; /* 1E.6010.5:0 R/W Default = 0x08 */ - /* Tx FIFO full threshold */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of MSM System FIFO Control Register */ - union - { - struct - { - unsigned int reserved0 : 10; - /*! \brief 1E.6011.5:0 R/W MSM System Tx FIFO Empty Threshold [5:0] - AQ_MsmSystemFifoControlRegister_HHD.u3.bits_3.msmSystemTxFifoEmptyThreshold - - Default = 0x00 - - Tx FIFO empty threshold - - Notes: - All threshold values are in steps of FIFO words. */ - unsigned int msmSystemTxFifoEmptyThreshold : 6; /* 1E.6011.5:0 R/W Default = 0x00 */ - /* Tx FIFO empty threshold */ - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of MSM System FIFO Control Register */ - union - { - struct - { - unsigned int reserved0 : 8; - /*! \brief 1E.6012.7:0 ROS MSM System Rx FIFO Almost Full Threshold [7:0] - AQ_MsmSystemFifoControlRegister_HHD.u4.bits_4.msmSystemRxFifoAlmostFullThreshold - - Default = 0x00 - - Rx FIFO almost full threshold - - Notes: - Unused. */ - unsigned int msmSystemRxFifoAlmostFullThreshold : 8; /* 1E.6012.7:0 ROS Default = 0x00 */ - /* Rx FIFO almost full threshold */ - } bits_4; - uint16_t word_4; - } u4; - /*! \brief Union for bit and word level access of word 5 of MSM System FIFO Control Register */ - union - { - struct - { - unsigned int reserved0 : 8; - /*! \brief 1E.6013.7:0 ROS MSM System Rx FIFO Almost Empty Threshold [7:0] - AQ_MsmSystemFifoControlRegister_HHD.u5.bits_5.msmSystemRxFifoAlmostEmptyThreshold - - Default = 0x00 - - Rx FIFO almost empty threshold - - Notes: - Unused. */ - unsigned int msmSystemRxFifoAlmostEmptyThreshold : 8; /* 1E.6013.7:0 ROS Default = 0x00 */ - /* Rx FIFO almost empty threshold */ - } bits_5; - uint16_t word_5; - } u5; - /*! \brief Union for bit and word level access of word 6 of MSM System FIFO Control Register */ - union - { - struct - { - unsigned int reserved0 : 8; - /*! \brief 1E.6014.7:0 ROS MSM System Tx FIFO Almost Full Threshold [7:0] - AQ_MsmSystemFifoControlRegister_HHD.u6.bits_6.msmSystemTxFifoAlmostFullThreshold - - Default = 0x00 - - Tx FIFO almost full threshold - - Notes: - Unused. */ - unsigned int msmSystemTxFifoAlmostFullThreshold : 8; /* 1E.6014.7:0 ROS Default = 0x00 */ - /* Tx FIFO almost full threshold */ - } bits_6; - uint16_t word_6; - } u6; - /*! \brief Union for bit and word level access of word 7 of MSM System FIFO Control Register */ - union - { - struct - { - unsigned int reserved0 : 8; - /*! \brief 1E.6015.7:0 ROS MSM System Tx FIFO Almost Empty Threshold [7:0] - AQ_MsmSystemFifoControlRegister_HHD.u7.bits_7.msmSystemTxFifoAlmostEmptyThreshold - - Default = 0x00 - - Tx FIFO almost empty threshold - - Notes: - Unused. */ - unsigned int msmSystemTxFifoAlmostEmptyThreshold : 8; /* 1E.6015.7:0 ROS Default = 0x00 */ - /* Tx FIFO almost empty threshold */ - } bits_7; - uint16_t word_7; - } u7; -} AQ_MsmSystemFifoControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System General Status Register: 1E.6020 */ -/* MSM System General Status Register: 1E.6020 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System General Status Register */ - union - { - struct - { - unsigned int reserved0 : 10; - /*! \brief 1E.6020.5 RO MSM System Tx FIFO Empty - AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemTxFifoEmpty - - - - Tx FIFO empty - - Notes: - When set to 1, indicates the Tx FIFO is empty. When set to 0, Tx FIFO is non-empty. */ - unsigned int msmSystemTxFifoEmpty : 1; /* 1E.6020.5 RO */ - /* Tx FIFO empty */ - /*! \brief 1E.6020.4 RO MSM System Rx Low Power IDLE - AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemRxLowPowerIdle - - - - Rx LPI detected - - Notes: - Receive low power IDLE (LPI). Set to 1 when LPI is currently detected on the MAC Rx interface. Set to 0, when the MAC currently operates in normal mode. */ - unsigned int msmSystemRxLowPowerIdle : 1; /* 1E.6020.4 RO */ - /* Rx LPI detected */ - /*! \brief 1E.6020.3 R/W MSM System Timestamp Available - AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemTimestampAvailable - - Default = 0x0 - - Timestamp available - - Notes: - Transmit timestamp available. Indicates that the timestamp of the last transmitted event frame (which had ff_tx_ts_frm=1) is available in the register See MAC Time Stamp Status 0 [F:0] and See MAC Time Stamp Status 1 [F:0] . To clear this bit, the bit must be written with a 1. - */ - unsigned int msmSystemTimestampAvailable : 1; /* 1E.6020.3 R/W Default = 0x0 */ - /* Timestamp available */ - /*! \brief 1E.6020.2 RO MSM System PHY Loss of Signal - AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemPhyLossOfSignal - - - - PHY loss of signal - - Notes: - PHY indicates loss of signal. This is the value of pin phy_los which is tied to 0. */ - unsigned int msmSystemPhyLossOfSignal : 1; /* 1E.6020.2 RO */ - /* PHY loss of signal */ - /*! \brief 1E.6020.1 BLH MSM System Rx Remote Fault - AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemRxRemoteFault - - - - Rx remote fault detected - - Notes: - Latch high local fault status. Set to 1, whent he MAC detects Rx local fault sequences on the Rx interface. Reset to 0 after read and after reset. */ - unsigned int msmSystemRxRemoteFault : 1; /* 1E.6020.1 BLH */ - /* Rx remote fault detected */ - /*! \brief 1E.6020.0 BLH MSM System Rx Local Fault - AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemRxLocalFault - - - - Rx local fault detected - - Notes: - Latch high local fault status. Set to 1, whent he MAC detects Rx local fault sequences on the Rx interface. Reset to 0 after read and after reset. */ - unsigned int msmSystemRxLocalFault : 1; /* 1E.6020.0 BLH */ - /* Rx local fault detected */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System General Status Register */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemGeneralStatusRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Tx IPG Control Register: 1E.6022 */ -/* MSM System Tx IPG Control Register: 1E.6022 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Tx IPG Control Register */ - union - { - struct - { - unsigned int reserved0 : 10; - /*! \brief 1E.6022.5:0 R/W MSM System Tx IPG Length [5:0] - AQ_MsmSystemTxIpgControlRegister_HHD.u0.bits_0.msmSystemTxIpgLength - - Default = 0x0C - - Tx IPG length - - Notes: - Tx inter-packet gap (IPG) value. Depending on LAN or WAN mode of operation. - LAN Mode : Number of octets in steps of 4. Valid values are 8, 12, 16,..., 100. DIC is supported for any setting > 8. A default of 12 must be set to conform to IEEE802.3ae. - WAN Mode : Stretch factor. Valid values are 4 ... 15. The stretch factor is calculated as (value+1)*8. A default of 12 must be set to conform to IEEE802.3ae (i.e. 13*8=104). A larger value shrinks the IPG (increasing bandwidth). - The reset value of 12 leads to IEEE802.3ae conformant behavior in both modes. - Note : WAN mode is only available in 10G mode of operation. */ - unsigned int msmSystemTxIpgLength : 6; /* 1E.6022.5:0 R/W Default = 0x0C */ - /* Tx IPG length */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Tx IPG Control Register */ - union - { - struct - { - /*! \brief 1E.6023.F:0 MSM System Tx IPG Reserved - AQ_MsmSystemTxIpgControlRegister_HHD.u1.bits_1.msmSystemTxIpgReserved - - - - Value always 0, writes ignored - */ - unsigned int msmSystemTxIpgReserved : 16; /* 1E.6023.F:0 */ - /* Value always 0, writes ignored */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemTxIpgControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Tx Good Frames Counter Register: 1E.6040 */ -/* MSM System Tx Good Frames Counter Register: 1E.6040 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Tx Good Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6040.F:0 ROS MSM System Tx Good Frames Counter 0 [F:0] - AQ_MsmSystemTxGoodFramesCounterRegister_HHD.u0.bits_0.msmSystemTxGoodFramesCounter_0 - - Default = 0x0000 - - Tx good frame counter bits 15:0 - - Notes: - Count of frames transmitted without error (Including pause frames). */ - unsigned int msmSystemTxGoodFramesCounter_0 : 16; /* 1E.6040.F:0 ROS Default = 0x0000 */ - /* Tx good frame counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Tx Good Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6041.F:0 ROS MSM System Tx Good Frames Counter 1 [F:0] - AQ_MsmSystemTxGoodFramesCounterRegister_HHD.u1.bits_1.msmSystemTxGoodFramesCounter_1 - - Default = 0x0000 - - Tx good frame counter bits 31:16 - - - Notes: - Count of frames transmitted without error (Including pause frames). */ - unsigned int msmSystemTxGoodFramesCounter_1 : 16; /* 1E.6041.F:0 ROS Default = 0x0000 */ - /* Tx good frame counter bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemTxGoodFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Rx Good Frames Counter Register: 1E.6044 */ -/* MSM System Rx Good Frames Counter Register: 1E.6044 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Rx Good Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6044.F:0 ROS MSM System Rx Good Frames Counter 0 [F:0] - AQ_MsmSystemRxGoodFramesCounterRegister_HHD.u0.bits_0.msmSystemRxGoodFramesCounter_0 - - Default = 0x0000 - - Rx good frame counter bits 15:0 - - Notes: - Count of frames received without error (Including pause frames). */ - unsigned int msmSystemRxGoodFramesCounter_0 : 16; /* 1E.6044.F:0 ROS Default = 0x0000 */ - /* Rx good frame counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Rx Good Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6045.F:0 ROS MSM System Rx Good Frames Counter 1 [F:0] - AQ_MsmSystemRxGoodFramesCounterRegister_HHD.u1.bits_1.msmSystemRxGoodFramesCounter_1 - - Default = 0x0000 - - Rx good frame counter bits 31:16 - - Notes: - Count of frames received without error (Including pause frames). */ - unsigned int msmSystemRxGoodFramesCounter_1 : 16; /* 1E.6045.F:0 ROS Default = 0x0000 */ - /* Rx good frame counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemRxGoodFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Rx FCS Errors Counter Register: 1E.6048 */ -/* MSM System Rx FCS Errors Counter Register: 1E.6048 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Rx FCS Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.6048.F:0 ROS MSM System FCS Error Counter 0 [F:0] - AQ_MsmSystemRxFcsErrorsCounterRegister_HHD.u0.bits_0.msmSystemFcsErrorCounter_0 - - Default = 0x0000 - - Frame check sequence error counter bits 15:0 - - Notes: - Count of frames for which a CRC-32 Error is detected but the frame is otherwise of correct length. */ - unsigned int msmSystemFcsErrorCounter_0 : 16; /* 1E.6048.F:0 ROS Default = 0x0000 */ - /* Frame check sequence error counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Rx FCS Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.6049.F:0 ROS MSM System FCS Error Counter 1 [F:0] - AQ_MsmSystemRxFcsErrorsCounterRegister_HHD.u1.bits_1.msmSystemFcsErrorCounter_1 - - Default = 0x0000 - - Frame check sequence error counter bits 31:16 - - Notes: - Count of frames for which a CRC-32 Error is detected but the frame is otherwise of correct length. */ - unsigned int msmSystemFcsErrorCounter_1 : 16; /* 1E.6049.F:0 ROS Default = 0x0000 */ - /* Frame check sequence error counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemRxFcsErrorsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Rx Alignment Errors Counter Register: 1E.604C */ -/* MSM System Rx Alignment Errors Counter Register: 1E.604C */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Rx Alignment Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.604C.F:0 ROS MSM System Alignment Error Counter 0 [F:0] - AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD.u0.bits_0.msmSystemAlignmentErrorCounter_0 - - Default = 0x0000 - - Alignment error counter bits 15:0 - - Notes: - Count of frames received with an alignment error. */ - unsigned int msmSystemAlignmentErrorCounter_0 : 16; /* 1E.604C.F:0 ROS Default = 0x0000 */ - /* Alignment error counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Rx Alignment Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.604D.F:0 ROS MSM System Alignment Error Counter 1 [F:0] - AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD.u1.bits_1.msmSystemAlignmentErrorCounter_1 - - Default = 0x0000 - - Alignment error counter bits 31:16 - - Notes: - Count of frames received with an alignment error. */ - unsigned int msmSystemAlignmentErrorCounter_1 : 16; /* 1E.604D.F:0 ROS Default = 0x0000 */ - /* Alignment error counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Tx Pause Frames Counter Register: 1E.6050 */ -/* MSM System Tx Pause Frames Counter Register: 1E.6050 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Tx Pause Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6050.F:0 ROS MSM System Tx Pause Frames Counter 0 [F:0] - AQ_MsmSystemTxPauseFramesCounterRegister_HHD.u0.bits_0.msmSystemTxPauseFramesCounter_0 - - Default = 0x0000 - - Tx pause frame counter bits 15:0 - - Notes: - Valid pause frames transmitted. */ - unsigned int msmSystemTxPauseFramesCounter_0 : 16; /* 1E.6050.F:0 ROS Default = 0x0000 */ - /* Tx pause frame counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Tx Pause Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6051.F:0 ROS MSM System Tx Pause Frames Counter 1 [F:0] - AQ_MsmSystemTxPauseFramesCounterRegister_HHD.u1.bits_1.msmSystemTxPauseFramesCounter_1 - - Default = 0x0000 - - Tx pause frame counter bits 31:16 - - - Notes: - Valid pause frames transmitted. */ - unsigned int msmSystemTxPauseFramesCounter_1 : 16; /* 1E.6051.F:0 ROS Default = 0x0000 */ - /* Tx pause frame counter bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemTxPauseFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Rx Pause Frames Counter Register: 1E.6054 */ -/* MSM System Rx Pause Frames Counter Register: 1E.6054 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Rx Pause Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6054.F:0 ROS MSM System Rx Pause Frames Counter 0 [F:0] - AQ_MsmSystemRxPauseFramesCounterRegister_HHD.u0.bits_0.msmSystemRxPauseFramesCounter_0 - - Default = 0x0000 - - Rx pause frame counter bits 15:0 - - Notes: - Valid pause frames received. */ - unsigned int msmSystemRxPauseFramesCounter_0 : 16; /* 1E.6054.F:0 ROS Default = 0x0000 */ - /* Rx pause frame counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Rx Pause Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6055.F:0 ROS MSM System Rx Pause Frames Counter 1 [F:0] - AQ_MsmSystemRxPauseFramesCounterRegister_HHD.u1.bits_1.msmSystemRxPauseFramesCounter_1 - - Default = 0x0000 - - Rx pause frame counter bits 31:16 - - Notes: - Valid pause frames received. */ - unsigned int msmSystemRxPauseFramesCounter_1 : 16; /* 1E.6055.F:0 ROS Default = 0x0000 */ - /* Rx pause frame counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemRxPauseFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Rx Too Long Errors Counter Register: 1E.6058 */ -/* MSM System Rx Too Long Errors Counter Register: 1E.6058 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Rx Too Long Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.6058.F:0 ROS MSM System Rx Too Long Errors Counter 0 [F:0] - AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD.u0.bits_0.msmSystemRxTooLongErrorsCounter_0 - - Default = 0x0000 - - Too-long errors counter bits 15:0 - - Notes: - Frame received exceeded the maximum length programmed with register FRM_LGTH. */ - unsigned int msmSystemRxTooLongErrorsCounter_0 : 16; /* 1E.6058.F:0 ROS Default = 0x0000 */ - /* Too-long errors counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Rx Too Long Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.6059.F:0 ROS MSM System Rx Too Long Errors Counter 1 [F:0] - AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD.u1.bits_1.msmSystemRxTooLongErrorsCounter_1 - - Default = 0x0000 - - Too-long errors counter bits 31:16 - - Notes: - Frame received exceeded the maximum length programmed with register FRM_LGTH. */ - unsigned int msmSystemRxTooLongErrorsCounter_1 : 16; /* 1E.6059.F:0 ROS Default = 0x0000 */ - /* Too-long errors counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Rx In Range Length Errors Counter Register: 1E.605C */ -/* MSM System Rx In Range Length Errors Counter Register: 1E.605C */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Rx In Range Length Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.605C.F:0 ROS MSM System Rx In Range Length Errors Counter 0 [F:0] - AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD.u0.bits_0.msmSystemRxInRangeLengthErrorsCounter_0 - - Default = 0x0000 - - In-range-length errors counter bits 15:0 - - Notes: - A count of frames with a length/type field value between 46 (VLAN: 42) and less than 0x0600, that does not match the number of payload data octets received. Should count also if length/type field is less than 46 (VLAN: 42) and the frame is longer than 64 bytes. */ - unsigned int msmSystemRxInRangeLengthErrorsCounter_0 : 16; /* 1E.605C.F:0 ROS Default = 0x0000 */ - /* In-range-length errors counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Rx In Range Length Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.605D.F:0 ROS MSM System Rx In Range Length Errors Counter 1 [F:0] - AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD.u1.bits_1.msmSystemRxInRangeLengthErrorsCounter_1 - - Default = 0x0000 - - In-range-length errors counter bits 31:16 - - Notes: - A count of frames with a length/type field value between 46 (VLAN: 42) and less than 0x0600, that does not match the number of payload data octets received. Should count also if length/type field is less than 46 (VLAN: 42) and the frame is longer than 64 bytes. */ - unsigned int msmSystemRxInRangeLengthErrorsCounter_1 : 16; /* 1E.605D.F:0 ROS Default = 0x0000 */ - /* In-range-length errors counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Tx VLAN Frames Counter Register: 1E.6060 */ -/* MSM System Tx VLAN Frames Counter Register: 1E.6060 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Tx VLAN Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6060.F:0 ROS MSM System Tx VLAN Frames Counter 0 [F:0] - AQ_MsmSystemTxVlanFramesCounterRegister_HHD.u0.bits_0.msmSystemTxVlanFramesCounter_0 - - Default = 0x0000 - - Tx VLAN frames counter bits 15:0 - - Notes: - Valid VLAN tagged frames transmitted. */ - unsigned int msmSystemTxVlanFramesCounter_0 : 16; /* 1E.6060.F:0 ROS Default = 0x0000 */ - /* Tx VLAN frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Tx VLAN Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6061.F:0 ROS MSM System Tx VLAN Frames Counter 1 [F:0] - AQ_MsmSystemTxVlanFramesCounterRegister_HHD.u1.bits_1.msmSystemTxVlanFramesCounter_1 - - Default = 0x0000 - - Tx VLAN frames counter bits 31:16 - - Notes: - Valid VLAN tagged frames transmitted. */ - unsigned int msmSystemTxVlanFramesCounter_1 : 16; /* 1E.6061.F:0 ROS Default = 0x0000 */ - /* Tx VLAN frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemTxVlanFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Rx VLAN Frames Counter Register: 1E.6064 */ -/* MSM System Rx VLAN Frames Counter Register: 1E.6064 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Rx VLAN Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6064.F:0 ROS MSM System Rx VLAN Frames Counter 0 [F:0] - AQ_MsmSystemRxVlanFramesCounterRegister_HHD.u0.bits_0.msmSystemRxVlanFramesCounter_0 - - Default = 0x0000 - - Rx VLAN frames counter bits 15:0 - - Notes: - Valid VLAN tagged frames received. */ - unsigned int msmSystemRxVlanFramesCounter_0 : 16; /* 1E.6064.F:0 ROS Default = 0x0000 */ - /* Rx VLAN frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Rx VLAN Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6065.F:0 ROS MSM System Rx VLAN Frames Counter 1 [F:0] - AQ_MsmSystemRxVlanFramesCounterRegister_HHD.u1.bits_1.msmSystemRxVlanFramesCounter_1 - - Default = 0x0000 - - Rx VLAN frames counter bits 31:16 - - Notes: - Valid VLAN tagged frames received. */ - unsigned int msmSystemRxVlanFramesCounter_1 : 16; /* 1E.6065.F:0 ROS Default = 0x0000 */ - /* Rx VLAN frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemRxVlanFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Tx Octets Counter Register: 1E.6068 */ -/* MSM System Tx Octets Counter Register: 1E.6068 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Tx Octets Counter Register */ - union - { - struct - { - /*! \brief 1E.6068.F:0 ROS MSM System Tx Octets Counter 0 [F:0] - AQ_MsmSystemTxOctetsCounterRegister_HHD.u0.bits_0.msmSystemTxOctetsCounter_0 - - Default = 0x0000 - - Tx octets counter bits 15:0 - - Notes: - All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ - unsigned int msmSystemTxOctetsCounter_0 : 16; /* 1E.6068.F:0 ROS Default = 0x0000 */ - /* Tx octets counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Tx Octets Counter Register */ - union - { - struct - { - /*! \brief 1E.6069.F:0 ROS MSM System Tx Octets Counter 1 [F:0] - AQ_MsmSystemTxOctetsCounterRegister_HHD.u1.bits_1.msmSystemTxOctetsCounter_1 - - Default = 0x0000 - - Tx octets counter bits 31:16 - - Notes: - All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ - unsigned int msmSystemTxOctetsCounter_1 : 16; /* 1E.6069.F:0 ROS Default = 0x0000 */ - /* Tx octets counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of MSM System Tx Octets Counter Register */ - union - { - struct - { - /*! \brief 1E.606A.F:0 ROS MSM System Tx Octets Counter 2 [F:0] - AQ_MsmSystemTxOctetsCounterRegister_HHD.u2.bits_2.msmSystemTxOctetsCounter_2 - - Default = 0x0000 - - Tx octets counter bits 47:32 - - Notes: - All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ - unsigned int msmSystemTxOctetsCounter_2 : 16; /* 1E.606A.F:0 ROS Default = 0x0000 */ - /* Tx octets counter bits 47:32 */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of MSM System Tx Octets Counter Register */ - union - { - struct - { - /*! \brief 1E.606B.F:0 ROS MSM System Tx Octets Counter 3 [F:0] - AQ_MsmSystemTxOctetsCounterRegister_HHD.u3.bits_3.msmSystemTxOctetsCounter_3 - - Default = 0x0000 - - Tx octets counter bits 63:48 - - Notes: - All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ - unsigned int msmSystemTxOctetsCounter_3 : 16; /* 1E.606B.F:0 ROS Default = 0x0000 */ - /* Tx octets counter bits 63:48 */ - } bits_3; - uint16_t word_3; - } u3; -} AQ_MsmSystemTxOctetsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Rx Octets Counter Register: 1E.606C */ -/* MSM System Rx Octets Counter Register: 1E.606C */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Rx Octets Counter Register */ - union - { - struct - { - /*! \brief 1E.606C.F:0 ROS MSM System Rx Octets Counter 0 [F:0] - AQ_MsmSystemRxOctetsCounterRegister_HHD.u0.bits_0.msmSystemRxOctetsCounter_0 - - Default = 0x0000 - - Rx octets counter bits 15:0 - - Notes: - All octets received except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames received. */ - unsigned int msmSystemRxOctetsCounter_0 : 16; /* 1E.606C.F:0 ROS Default = 0x0000 */ - /* Rx octets counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Rx Octets Counter Register */ - union - { - struct - { - /*! \brief 1E.606D.F:0 ROS MSM System Rx Octets Counter 1 [F:0] - AQ_MsmSystemRxOctetsCounterRegister_HHD.u1.bits_1.msmSystemRxOctetsCounter_1 - - Default = 0x0000 - - Rx octets counter bits 31:16 - - Notes: - All octets received except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames received. */ - unsigned int msmSystemRxOctetsCounter_1 : 16; /* 1E.606D.F:0 ROS Default = 0x0000 */ - /* Rx octets counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemRxOctetsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Rx Unicast Frames Counter Register: 1E.6070 */ -/* MSM System Rx Unicast Frames Counter Register: 1E.6070 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Rx Unicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6070.F:0 ROS MSM System Rx Unicast Frames Counter 0 [F:0] - AQ_MsmSystemRxUnicastFramesCounterRegister_HHD.u0.bits_0.msmSystemRxUnicastFramesCounter_0 - - Default = 0x0000 - - Rx unicast frames counter bits 15:0 - - Notes: - Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '0'. */ - unsigned int msmSystemRxUnicastFramesCounter_0 : 16; /* 1E.6070.F:0 ROS Default = 0x0000 */ - /* Rx unicast frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Rx Unicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6071.F:0 ROS MSM System Rx Unicast Frames Counter 1 [F:0] - AQ_MsmSystemRxUnicastFramesCounterRegister_HHD.u1.bits_1.msmSystemRxUnicastFramesCounter_1 - - Default = 0x0000 - - Rx unicast frames counter bits 31:16 - - Notes: - Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '0'. */ - unsigned int msmSystemRxUnicastFramesCounter_1 : 16; /* 1E.6071.F:0 ROS Default = 0x0000 */ - /* Rx unicast frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemRxUnicastFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Rx Multicast Frames Counter Register: 1E.6074 */ -/* MSM System Rx Multicast Frames Counter Register: 1E.6074 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Rx Multicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6074.F:0 ROS MSM System Rx Multicast Frames Counter 0 [F:0] - AQ_MsmSystemRxMulticastFramesCounterRegister_HHD.u0.bits_0.msmSystemRxMulticastFramesCounter_0 - - Default = 0x0000 - - Rx multicast frames counter bits 15:0 - - Notes: - Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '1' but not the broadcast address (all bits set '1' ). Pause frames are not counted. */ - unsigned int msmSystemRxMulticastFramesCounter_0 : 16; /* 1E.6074.F:0 ROS Default = 0x0000 */ - /* Rx multicast frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Rx Multicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6075.F:0 ROS MSM System Rx Multicast Frames Counter 1 [F:0] - AQ_MsmSystemRxMulticastFramesCounterRegister_HHD.u1.bits_1.msmSystemRxMulticastFramesCounter_1 - - Default = 0x0000 - - Rx multicast frames counter bits 31:16 - - Notes: - Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '1' but not the broadcast address (all bits set '1' ). Pause frames are not counted. */ - unsigned int msmSystemRxMulticastFramesCounter_1 : 16; /* 1E.6075.F:0 ROS Default = 0x0000 */ - /* Rx multicast frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemRxMulticastFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Rx Broadcast Frames Counter Register: 1E.6078 */ -/* MSM System Rx Broadcast Frames Counter Register: 1E.6078 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Rx Broadcast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6078.F:0 ROS MSM System Rx Broadcast Frames Counter 0 [F:0] - AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD.u0.bits_0.msmSystemRxBroadcastFramesCounter_0 - - Default = 0x0000 - - Rx broadcast frames counter bits 15:0 - - Notes: - Incremented with each valid frame received on the receive FIFO interface (FIFO) and all bits of the destination address were set '1'. */ - unsigned int msmSystemRxBroadcastFramesCounter_0 : 16; /* 1E.6078.F:0 ROS Default = 0x0000 */ - /* Rx broadcast frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Rx Broadcast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6079.F:0 ROS MSM System Rx Broadcast Frames Counter 1 [F:0] - AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD.u1.bits_1.msmSystemRxBroadcastFramesCounter_1 - - Default = 0x0000 - - Rx broadcast frames counter bits 31:16 - - Notes: - Incremented with each valid frame received on the receive FIFO interface (FIFO) and all bits of the destination address were set '1'. */ - unsigned int msmSystemRxBroadcastFramesCounter_1 : 16; /* 1E.6079.F:0 ROS Default = 0x0000 */ - /* Rx broadcast frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Tx Errors Counter Register: 1E.607C */ -/* MSM System Tx Errors Counter Register: 1E.607C */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Tx Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.607C.F:0 ROS MSM System Tx Errors Counter 0 [F:0] - AQ_MsmSystemTxErrorsCounterRegister_HHD.u0.bits_0.msmSystemTxErrorsCounter_0 - - Default = 0x0000 - - Rx errors counter bits 15:0 - - Notes: - Number of frames transmitted with error: - - FIFO Overflow Errors - - FIFO Underflow Errors */ - unsigned int msmSystemTxErrorsCounter_0 : 16; /* 1E.607C.F:0 ROS Default = 0x0000 */ - /* Rx errors counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Tx Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.607D.F:0 ROS MSM System Tx Errors Counter 1 [F:0] - AQ_MsmSystemTxErrorsCounterRegister_HHD.u1.bits_1.msmSystemTxErrorsCounter_1 - - Default = 0x0000 - - Tx errors counter bits 31:16 - - Notes: - Number of frames transmitted with error: - - FIFO Overflow Errors - - FIFO Underflow Errors */ - unsigned int msmSystemTxErrorsCounter_1 : 16; /* 1E.607D.F:0 ROS Default = 0x0000 */ - /* Tx errors counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemTxErrorsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Tx Unicast Frames Counter Register: 1E.6084 */ -/* MSM System Tx Unicast Frames Counter Register: 1E.6084 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Tx Unicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6084.F:0 ROS MSM System Tx Unicast Frames Counter 0 [F:0] - AQ_MsmSystemTxUnicastFramesCounterRegister_HHD.u0.bits_0.msmSystemTxUnicastFramesCounter_0 - - Default = 0x0000 - - Tx unicast frames counter bits 15:0 - - Notes: - Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '0'. */ - unsigned int msmSystemTxUnicastFramesCounter_0 : 16; /* 1E.6084.F:0 ROS Default = 0x0000 */ - /* Tx unicast frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Tx Unicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6085.F:0 ROS MSM System Tx Unicast Frames Counter 1 [F:0] - AQ_MsmSystemTxUnicastFramesCounterRegister_HHD.u1.bits_1.msmSystemTxUnicastFramesCounter_1 - - Default = 0x0000 - - Tx unicast frames counter bits 31:16 - - Notes: - Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '0'. */ - unsigned int msmSystemTxUnicastFramesCounter_1 : 16; /* 1E.6085.F:0 ROS Default = 0x0000 */ - /* Tx unicast frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemTxUnicastFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Tx Multicast Frames Counter Register: 1E.6088 */ -/* MSM System Tx Multicast Frames Counter Register: 1E.6088 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Tx Multicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6088.F:0 ROS MSM System Tx Multicast Frames Counter 0 [F:0] - AQ_MsmSystemTxMulticastFramesCounterRegister_HHD.u0.bits_0.msmSystemTxMulticastFramesCounter_0 - - Default = 0x0000 - - Tx multicast frames counter bits 15:0 - - Notes: - Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '1' but not the broadcast address (all bits '1'). */ - unsigned int msmSystemTxMulticastFramesCounter_0 : 16; /* 1E.6088.F:0 ROS Default = 0x0000 */ - /* Tx multicast frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Tx Multicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6089.F:0 ROS MSM System Tx Multicast Frames Counter 1 [F:0] - AQ_MsmSystemTxMulticastFramesCounterRegister_HHD.u1.bits_1.msmSystemTxMulticastFramesCounter_1 - - Default = 0x0000 - - Tx multicast frames counter bits 31:16 - - Notes: - Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '1' but not the broadcast address (all bits '1'). */ - unsigned int msmSystemTxMulticastFramesCounter_1 : 16; /* 1E.6089.F:0 ROS Default = 0x0000 */ - /* Tx multicast frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemTxMulticastFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Tx Broadcast Frames Counter Register: 1E.608C */ -/* MSM System Tx Broadcast Frames Counter Register: 1E.608C */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Tx Broadcast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.608C.F:0 ROS MSM System Tx Broadcast Frames Counter 0 [F:0] - AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD.u0.bits_0.msmSystemTxBroadcastFramesCounter_0 - - Default = 0x0000 - - Tx broadcast frames counter bits 15:0 - - Notes: - Incremented with each frame written to the FIFO interface and all bits of the destination address set to '1'. */ - unsigned int msmSystemTxBroadcastFramesCounter_0 : 16; /* 1E.608C.F:0 ROS Default = 0x0000 */ - /* Tx broadcast frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Tx Broadcast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.608D.F:0 ROS MSM System Tx Broadcast Frames Counter 1 [F:0] - AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD.u1.bits_1.msmSystemTxBroadcastFramesCounter_1 - - Default = 0x0000 - - Tx broadcast frames counter bits 31:16 - - Notes: - Incremented with each frame written to the FIFO interface and all bits of the destination address set to '1'. */ - unsigned int msmSystemTxBroadcastFramesCounter_1 : 16; /* 1E.608D.F:0 ROS Default = 0x0000 */ - /* Tx broadcast frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Rx Errors Counter Register: 1E.60C8 */ -/* MSM System Rx Errors Counter Register: 1E.60C8 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Rx Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.60C8.F:0 ROS MSM System Rx Errors Counter 0 [F:0] - AQ_MsmSystemRxErrorsCounterRegister_HHD.u0.bits_0.msmSystemRxErrorsCounter_0 - - Default = 0x0000 - - Rx errors counter bits 15:0 - - Notes: - Number of frames received with error: - - FIFO Overflow Errors - - CRC Errors - - Payload Length Errors - - Jabber and Oversized Errors - - Alignment Errors - - The dedicated Error Code (0xfe, not a code error) was received */ - unsigned int msmSystemRxErrorsCounter_0 : 16; /* 1E.60C8.F:0 ROS Default = 0x0000 */ - /* Rx errors counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Rx Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.60C9.F:0 ROS MSM System Rx Errors Counter 1 [F:0] - AQ_MsmSystemRxErrorsCounterRegister_HHD.u1.bits_1.msmSystemRxErrorsCounter_1 - - Default = 0x0000 - - Rx errors counter bits 31:16 - - Notes: - Number of frames received with error: - - FIFO Overflow Errors - - CRC Errors - - Payload Length Errors - - Jabber and Oversized Errors - - Alignment Errors - - The dedicated Error Code (0xfe, not a code error) was received */ - unsigned int msmSystemRxErrorsCounter_1 : 16; /* 1E.60C9.F:0 ROS Default = 0x0000 */ - /* Rx errors counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemRxErrorsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress VLAN TPID 0 Register: 1E.8006 */ -/* MSS Ingress VLAN TPID 0 Register: 1E.8006 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress VLAN TPID 0 Register */ - union - { - struct - { - /*! \brief 1E.8006.F:0 R/W MSS Ingress VLAN STag [F:0] - AQ_MssIngressVlanTpid_0Register_HHD.u0.bits_0.mssIngressVlanStag - - Default = 0x0000 - - STag TPID - - - Notes: - Service Tag Protocol Identifier (TPID) values to identify a VLAN tag. The " See SEC Egress VLAN CP Tag Parse STag " bit must be set to 1 for the incoming packet's TPID to be parsed. */ - unsigned int mssIngressVlanStag : 16; /* 1E.8006.F:0 R/W Default = 0x0000 */ - /* STag TPID - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Ingress VLAN TPID 0 Register */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssIngressVlanTpid_0Register_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress VLAN TPID 1 Register: 1E.8008 */ -/* MSS Ingress VLAN TPID 1 Register: 1E.8008 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress VLAN TPID 1 Register */ - union - { - struct - { - /*! \brief 1E.8008.F:0 R/W MSS Ingress VLAN QTag [F:0] - AQ_MssIngressVlanTpid_1Register_HHD.u0.bits_0.mssIngressVlanQtag - - Default = 0x0000 - - QTag TPID - - - Notes: - Customer Tag Protocol Identifier (TPID) values to identify a VLAN tag. The " See SEC Egress VLAN CP Tag Parse QTag " bit must be set to 1 for the incoming packet's TPID to be parsed. */ - unsigned int mssIngressVlanQtag : 16; /* 1E.8008.F:0 R/W Default = 0x0000 */ - /* QTag TPID - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Ingress VLAN TPID 1 Register */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssIngressVlanTpid_1Register_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress VLAN Control Register: 1E.800A */ -/* MSS Ingress VLAN Control Register: 1E.800A */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress VLAN Control Register */ - union - { - struct - { - /*! \brief 1E.800A.F:0 R/W MSS Ingress VLAN UP Map Table LSW [F:0] - AQ_MssIngressVlanControlRegister_HHD.u0.bits_0.mssIngressVlanUpMapTableLSW - - Default = 0x0000 - - Map table bits 15:0 - - - Notes: - If there is a customer TPID Tag match and no service TPID Tag match or the service TPID Tag match is disabled, the outer TAG's PCP is used to index into this map table to generate the packets user priority. - 2:0 : UP value for customer Tag PCP 0x0 - 5:3: UP value for customer Tag PCP 0x0 - 8:6 : UP value for customer Tag PCP 0x0 - 11:9 : UP value for customer Tag PCP 0x0 - 14:12 : UP value for customer Tag PCP 0x0 - 17:15 : UP value for customer Tag PCP 0x0 */ - unsigned int mssIngressVlanUpMapTableLSW : 16; /* 1E.800A.F:0 R/W Default = 0x0000 */ - /* Map table bits 15:0 - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Ingress VLAN Control Register */ - union - { - struct - { - /*! \brief 1E.800B.F R/W MSS Ingress VLAN QTag Parse Enable - AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanQtagParseEnable - - Default = 0x0 - - 1 = Enable VLAN QTag parsing - - - Notes: - Enable controlled port VLAN customer Tag parsing. When this bit is set to 1, the incoming packet's outer TPID will be compared with the configured " See MSS Ingress VLAN QTag [F:0] " for matching. If the " See SEC Egress VLAN CP Tag Parse QinQ " bit is set to1, this will also be used to compare the incoming packet's inner TPID. */ - unsigned int mssIngressVlanQtagParseEnable : 1; /* 1E.800B.F R/W Default = 0x0 */ - /* 1 = Enable VLAN QTag parsing - */ - /*! \brief 1E.800B.E R/W MSS Ingress VLAN STag Parse Enable - AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanStagParseEnable - - Default = 0x0 - - 1 = Enable VLAN STag parsing - - - Notes: - Enable controlled port VLAN service Tag parsing. When this bit is set to 1, the incoming packets outer TPID will be compared with the configured " See MSS Ingress VLAN Stag [F:0] " for matching. If the " See SEC Egress VLAN CP Tag Parse QinQ " bit is set to1, this will also be used to compare the incoming packet's inner TPID. */ - unsigned int mssIngressVlanStagParseEnable : 1; /* 1E.800B.E R/W Default = 0x0 */ - /* 1 = Enable VLAN STag parsing - */ - /*! \brief 1E.800B.D R/W MSS Ingress VLAN QinQ Parse Enable - AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanQinqParseEnable - - Default = 0x0 - - VLAN CP Tag Parse QinQ - - - Notes: - Enable controlled port VLAN QinQ Tag parsing. When this bit is set to 1 both the outer and inner VLAN Tags will be parsed. */ - unsigned int mssIngressVlanQinqParseEnable : 1; /* 1E.800B.D R/W Default = 0x0 */ - /* VLAN CP Tag Parse QinQ - */ - /*! \brief 1E.800B.C R/W MSS Ingress VLAN QTag UP Parse Enable - AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanQtagUpParseEnable - - Default = 0x0 - - VLAN CP Tag QTag UP enable - - - Notes: - Enable controlled port customer VLAN customer Tag user priority field parsing. */ - unsigned int mssIngressVlanQtagUpParseEnable : 1; /* 1E.800B.C R/W Default = 0x0 */ - /* VLAN CP Tag QTag UP enable - */ - /*! \brief 1E.800B.B R/W MSS Ingress VLAN STag UP Parse Enable - AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanStagUpParseEnable - - Default = 0x0 - - VLAN CP Tag STag UP enable - - - Notes: - Enable controlled port service VLAN service Tag user priority field parsing. */ - unsigned int mssIngressVlanStagUpParseEnable : 1; /* 1E.800B.B R/W Default = 0x0 */ - /* VLAN CP Tag STag UP enable - */ - /*! \brief 1E.800B.A:8 R/W MSS Ingress VLAN UP Default [2:0] - AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanUpDefault - - Default = 0x0 - - UP default - - - Notes: - User priority default */ - unsigned int mssIngressVlanUpDefault : 3; /* 1E.800B.A:8 R/W Default = 0x0 */ - /* UP default - */ - /*! \brief 1E.800B.7:0 R/W MSS Ingress VLAN UP Map Table MSW [17:10] - AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanUpMapTableMSW - - Default = 0x00 - - UP Map table bits 23:16 - - - Notes: - If there is a customer TPID Tag match and no service TPID Tag match or the service TPID Tag match is disabled, the outer TAG's PCP is used to index into this map table to generate the packets user priority. - 2:0 : UP value for customer Tag PCP 0x0 - 5:3: UP value for customer Tag PCP 0x0 - 8:6 : UP value for customer Tag PCP 0x0 - 11:9 : UP value for customer Tag PCP 0x0 - 14:12 : UP value for customer Tag PCP 0x0 - 17:15 : UP value for customer Tag PCP 0x0 - 20:18 : UP value for customer Tag PCP 0x0 - 23:21 : UP value for customer Tag PCP 0x0 */ - unsigned int mssIngressVlanUpMapTableMSW : 8; /* 1E.800B.7:0 R/W Default = 0x00 */ - /* UP Map table bits 23:16 - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssIngressVlanControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress MTU Size Control Register: 1E.800C */ -/* MSS Ingress MTU Size Control Register: 1E.800C */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress MTU Size Control Register */ - union - { - struct - { - /*! \brief 1E.800C.F:0 R/W MSS Ingress Controlled Packet MTU Size [F:0] - AQ_MssIngressMtuSizeControlRegister_HHD.u0.bits_0.mssIngressControlledPacketMtuSize - - Default = 0x05DC - - Maximum transmission unit for controlled packet - - - Notes: - Maximum transmission unit of controlled packet */ - unsigned int mssIngressControlledPacketMtuSize : 16; /* 1E.800C.F:0 R/W Default = 0x05DC */ - /* Maximum transmission unit for controlled packet - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Ingress MTU Size Control Register */ - union - { - struct - { - /*! \brief 1E.800D.F:0 R/W MSS Ingress Uncontrolled Packet MTU Size [F:0] - AQ_MssIngressMtuSizeControlRegister_HHD.u1.bits_1.mssIngressUncontrolledPacketMtuSize - - Default = 0x05DC - - Maximum transmission unit for uncontrolled packet - - - Notes: - Maximum transmission unit of uncontrolled packet */ - unsigned int mssIngressUncontrolledPacketMtuSize : 16; /* 1E.800D.F:0 R/W Default = 0x05DC */ - /* Maximum transmission unit for uncontrolled packet - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssIngressMtuSizeControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress Control Register: 1E.800E */ -/* MSS Ingress Control Register: 1E.800E */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress Control Register */ - union - { - struct - { - unsigned int reserved0 : 2; - /*! \brief 1E.800E.D R/W MSS Ingress ICV LSB 8 Bytes Enable - AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressIcvLsb_8BytesEnable - - Default = 0x0 - - 1 = Use LSB - 0 = Use MSB - - - - Notes: - This bit selects MSB or LSB 8 bytes selection in the case where the ICV is 8 bytes. - 0 = MSB is used. */ - unsigned int mssIngressIcvLsb_8BytesEnable : 1; /* 1E.800E.D R/W Default = 0x0 */ - /* 1 = Use LSB - 0 = Use MSB - - */ - /*! \brief 1E.800E.C:B R/W MSS Ingress Global Validate Frames [1:0] - AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressGlobalValidateFrames - - Default = 0x0 - - Default validate frames configuration - - - Notes: - If the SC is invalid or if an IGPRC miss packet condition occurs, this default will be used for the validate frames configuration instead of the validate frame entry in the Ingress SC Table (IGSCT). */ - unsigned int mssIngressGlobalValidateFrames : 2; /* 1E.800E.C:B R/W Default = 0x0 */ - /* Default validate frames configuration - */ - /*! \brief 1E.800E.A R/W MSS Ingress Remove SECTag - AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressRemoveSectag - - Default = 0x0 - - 1 = Enable removal of SECTag - - - Notes: - If this bit is set and either of the following two conditions occurs, the SECTag will be removed. - Controlled packet and either the SA or SC is invalid. - IGPRC miss. */ - unsigned int mssIngressRemoveSectag : 1; /* 1E.800E.A R/W Default = 0x0 */ - /* 1 = Enable removal of SECTag - */ - /*! \brief 1E.800E.9 R/W MSS Ingress High Priority - AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressHighPriority - - Default = 0x0 - - 1 = MIB counter clear on read enable - - - Notes: - If this bit is set to 1, read is given high priority and the MIB count value becomes 0 after read. */ - unsigned int mssIngressHighPriority : 1; /* 1E.800E.9 R/W Default = 0x0 */ - /* 1 = MIB counter clear on read enable - */ - /*! \brief 1E.800E.8 R/W MSS Ingress Clear Count - AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressClearCount - - Default = 0x0 - - 1 = Clear all MIB counters - - - Notes: - If this bit is set to 1, all MIB counters will be cleared. */ - unsigned int mssIngressClearCount : 1; /* 1E.800E.8 R/W Default = 0x0 */ - /* 1 = Clear all MIB counters - */ - /*! \brief 1E.800E.7 R/W MSS Ingress Clear Global Time - AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressClearGlobalTime - - Default = 0x0 - - 1 = Clear global time - - - Notes: - Clear global time */ - unsigned int mssIngressClearGlobalTime : 1; /* 1E.800E.7 R/W Default = 0x0 */ - /* 1 = Clear global time - */ - /*! \brief 1E.800E.6 R/W MSS Ingress Check ICV - AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressCheckIcv - - Default = 0x0 - - Unused - - - Notes: - Unused */ - unsigned int mssIngressCheckIcv : 1; /* 1E.800E.6 R/W Default = 0x0 */ - /* Unused - */ - /*! \brief 1E.800E.5 R/W MSS Ingress Drop IGPRC Miss - AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressDropIgprcMiss - - Default = 0x0 - - 1 = Drop IGPRC miss packets - - - Notes: - Decides whether Ingress Pre-Security Classification (IGPRC) LUT miss packets are to be dropped */ - unsigned int mssIngressDropIgprcMiss : 1; /* 1E.800E.5 R/W Default = 0x0 */ - /* 1 = Drop IGPRC miss packets - */ - /*! \brief 1E.800E.4 R/W MSS Ingress Drop Kay Packet - AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressDropKayPacket - - Default = 0x0 - - 1 = Drop KaY packets - - - Notes: - Decides whether KaY packets have to be dropped */ - unsigned int mssIngressDropKayPacket : 1; /* 1E.800E.4 R/W Default = 0x0 */ - /* 1 = Drop KaY packets - */ - /*! \brief 1E.800E.3 R/W MSS Ingress Mask Short Length Error - AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressMaskShortLengthError - - Default = 0x0 - - Unused - - - Notes: - Unused */ - unsigned int mssIngressMaskShortLengthError : 1; /* 1E.800E.3 R/W Default = 0x0 */ - /* Unused - */ - /*! \brief 1E.800E.2 R/W MSS Ingress Create SCI - AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressCreateSci - - Default = 0x0 - - 0 = SCI from IGPRC LUT - - - Notes: - If the SCI is not in the packet and this bit is set to 0, the SCI will be taken from the IGPRC LUT. */ - unsigned int mssIngressCreateSci : 1; /* 1E.800E.2 R/W Default = 0x0 */ - /* 0 = SCI from IGPRC LUT - */ - /*! \brief 1E.800E.1 R/W MSS Ingress Operation Point To Point - AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressOperationPointToPoint - - Default = 0x0 - - 1 = Enable the SCI for authorization default - - - Notes: - The default SCI for authorization is configured in See MSS Ingress SCI Default [F:0] See MSS Ingress SCI Default [1F:10] , See MSS Ingress SCI Default [2F:20] , and See MSS Ingress SCI Default [3F:30] . */ - unsigned int mssIngressOperationPointToPoint : 1; /* 1E.800E.1 R/W Default = 0x0 */ - /* 1 = Enable the SCI for authorization default - */ - /*! \brief 1E.800E.0 R/W MSS Ingress Soft Reset - AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressSoftReset - - Default = 0x0 - - 1 = Soft reset - - - Notes: - S/W reset */ - unsigned int mssIngressSoftReset : 1; /* 1E.800E.0 R/W Default = 0x0 */ - /* 1 = Soft reset - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Ingress Control Register */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssIngressControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress SA Control Register: 1E.8010 */ -/* MSS Ingress SA Control Register: 1E.8010 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress SA Control Register */ - union - { - struct - { - /*! \brief 1E.8010.F:0 R/W MSS Ingress SA Threshold LSW [F:0] - AQ_MssIngressSaControlRegister_HHD.u0.bits_0.mssIngressSaThresholdLSW - - Default = 0x0000 - - SA threshold bits 15:0 - - - Notes: - Ingress PN threshold to generate SA threshold interrupt. */ - unsigned int mssIngressSaThresholdLSW : 16; /* 1E.8010.F:0 R/W Default = 0x0000 */ - /* SA threshold bits 15:0 - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Ingress SA Control Register */ - union - { - struct - { - /*! \brief 1E.8011.F:0 R/W MSS Ingress SA Threshold MSW [1F:10] - AQ_MssIngressSaControlRegister_HHD.u1.bits_1.mssIngressSaThresholdMSW - - Default = 0x0000 - - SA threshold bits 31:16 - - - Notes: - Ingress PN threshold to generate SA threshold interrupt. */ - unsigned int mssIngressSaThresholdMSW : 16; /* 1E.8011.F:0 R/W Default = 0x0000 */ - /* SA threshold bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssIngressSaControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress Interrupt Status Register: 1E.802E */ -/* MSS Ingress Interrupt Status Register: 1E.802E */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress Interrupt Status Register */ - union - { - struct - { - unsigned int reserved0 : 7; - /*! \brief 1E.802E.8 COW MSS Ingress IGPOC Miss Interrupt - AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressIgpocMissInterrupt - - Default = 0x0 - - 1 = Interrupt - - */ - unsigned int mssIngressIgpocMissInterrupt : 1; /* 1E.802E.8 COW Default = 0x0 */ - /* 1 = Interrupt - */ - /*! \brief 1E.802E.7 COW MSS Ingress TCI E/C Error Interrupt - AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressTciE_cErrorInterrupt - - Default = 0x0 - - 1 = Interrupt - - - Notes: - Write to 1 to clear. This error occurs when the TCI E bit is 1 and the TCI C bit is 0. The packet is not dropped, uncontrolled, or untagged. */ - unsigned int mssIngressTciE_cErrorInterrupt : 1; /* 1E.802E.7 COW Default = 0x0 */ - /* 1 = Interrupt - */ - /*! \brief 1E.802E.6 COW MSS Ingress ECC Error Interrupt - AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressEccErrorInterrupt - - Default = 0x0 - - 1 = Interrupt - - - Notes: - Write to 1 to clear. */ - unsigned int mssIngressEccErrorInterrupt : 1; /* 1E.802E.6 COW Default = 0x0 */ - /* 1 = Interrupt - */ - /*! \brief 1E.802E.5 COW MSS Ingress MIB Saturation Interrupt - AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressMibSaturationInterrupt - - Default = 0x0 - - 1 = Interrupt - - - Notes: - Write to 1 to clear. This bit is set when the MIB counters reaches all ones saturation. */ - unsigned int mssIngressMibSaturationInterrupt : 1; /* 1E.802E.5 COW Default = 0x0 */ - /* 1 = Interrupt - */ - /*! \brief 1E.802E.4 COW MSS Ingress Replay Error Interrupt - AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressReplayErrorInterrupt - - Default = 0x0 - - 1 = Interrupt - - - Notes: - Write to 1 to clear. */ - unsigned int mssIngressReplayErrorInterrupt : 1; /* 1E.802E.4 COW Default = 0x0 */ - /* 1 = Interrupt - */ - /*! \brief 1E.802E.3 COW MSS Ingress ICV Error Interrupt - AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressIcvErrorInterrupt - - Default = 0x0 - - 1 = Interrupt - - - Notes: - Write to 1 to clear. */ - unsigned int mssIngressIcvErrorInterrupt : 1; /* 1E.802E.3 COW Default = 0x0 */ - /* 1 = Interrupt - */ - /*! \brief 1E.802E.2 COW MSS Ingress SA Threshold Expired Interrupt - AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressSaThresholdExpiredInterrupt - - Default = 0x0 - - 1 = Interrupt - - - Notes: - Write to 1 to clear. This bit is set when the SA PN reaches the See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . */ - unsigned int mssIngressSaThresholdExpiredInterrupt : 1; /* 1E.802E.2 COW Default = 0x0 */ - /* 1 = Interrupt - */ - /*! \brief 1E.802E.1 COW MSS Ingress SA Expired Interrupt - AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressSaExpiredInterrupt - - Default = 0x0 - - 1 = Interrupt - - - Notes: - Write to 1 to clear. This bit is set when the SA PN reaches all ones saturation. */ - unsigned int mssIngressSaExpiredInterrupt : 1; /* 1E.802E.1 COW Default = 0x0 */ - /* 1 = Interrupt - */ - /*! \brief 1E.802E.0 COW MSS Master Ingress Interrupt - AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssMasterIngressInterrupt - - Default = 0x0 - - 1 = Interrupt - - - Notes: - Write to 1 to clear. This bit is set when any one of the above interrupt and the corresponding interrupt enable are both set. The interrupt enable for this bit must also be set for this bit to be set. */ - unsigned int mssMasterIngressInterrupt : 1; /* 1E.802E.0 COW Default = 0x0 */ - /* 1 = Interrupt - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Ingress Interrupt Status Register */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssIngressInterruptStatusRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress Interrupt Mask Register: 1E.8030 */ -/* MSS Ingress Interrupt Mask Register: 1E.8030 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress Interrupt Mask Register */ - union - { - struct - { - unsigned int reserved0 : 7; - /*! \brief 1E.8030.8 R/W MSS Ingress IGPOC Miss Interrupt Enable - AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressIgpocMissInterruptEnable - - Default = 0x0 - - 1 = Interrupt enabled - - */ - unsigned int mssIngressIgpocMissInterruptEnable : 1; /* 1E.8030.8 R/W Default = 0x0 */ - /* 1 = Interrupt enabled - */ - /*! \brief 1E.8030.7 R/W MSS Ingress TCI E/C Error Interrupt Enable - AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressTciE_cErrorInterruptEnable - - Default = 0x0 - - 1 = Interrupt enabled - - */ - unsigned int mssIngressTciE_cErrorInterruptEnable : 1; /* 1E.8030.7 R/W Default = 0x0 */ - /* 1 = Interrupt enabled - */ - /*! \brief 1E.8030.6 R/W MSS Ingress ECC Error Interrupt Enable - AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressEccErrorInterruptEnable - - Default = 0x0 - - 1 = Interrupt enabled - - */ - unsigned int mssIngressEccErrorInterruptEnable : 1; /* 1E.8030.6 R/W Default = 0x0 */ - /* 1 = Interrupt enabled - */ - /*! \brief 1E.8030.5 R/W MSS Ingress MIB Saturation Interrupt Enable - AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressMibSaturationInterruptEnable - - Default = 0x0 - - 1 = Interrupt enabled - - */ - unsigned int mssIngressMibSaturationInterruptEnable : 1; /* 1E.8030.5 R/W Default = 0x0 */ - /* 1 = Interrupt enabled - */ - /*! \brief 1E.8030.4 R/W MSS Ingress Replay Error Interrupt Enable - AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressReplayErrorInterruptEnable - - Default = 0x0 - - 1 = Interrupt enabled - - */ - unsigned int mssIngressReplayErrorInterruptEnable : 1; /* 1E.8030.4 R/W Default = 0x0 */ - /* 1 = Interrupt enabled - */ - /*! \brief 1E.8030.3 R/W MSS Ingress ICV Error Interrupt Enable - AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressIcvErrorInterruptEnable - - Default = 0x0 - - 1 = Interrupt enabled - - */ - unsigned int mssIngressIcvErrorInterruptEnable : 1; /* 1E.8030.3 R/W Default = 0x0 */ - /* 1 = Interrupt enabled - */ - /*! \brief 1E.8030.2 R/W MSS Ingress SA Threshold Expired Interrupt Enable - AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressSaThresholdExpiredInterruptEnable - - Default = 0x0 - - 1 = Interrupt enabled - - */ - unsigned int mssIngressSaThresholdExpiredInterruptEnable : 1; /* 1E.8030.2 R/W Default = 0x0 */ - /* 1 = Interrupt enabled - */ - /*! \brief 1E.8030.1 R/W MSS Ingress SA Expired Interrupt Enable - AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressSaExpiredInterruptEnable - - Default = 0x0 - - 1 = Interrupt enabled - - */ - unsigned int mssIngressSaExpiredInterruptEnable : 1; /* 1E.8030.1 R/W Default = 0x0 */ - /* 1 = Interrupt enabled - */ - /*! \brief 1E.8030.0 R/W MSS Ingress Master Interrupt Enable - AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressMasterInterruptEnable - - Default = 0x0 - - 1 = Interrupt enabled - - */ - unsigned int mssIngressMasterInterruptEnable : 1; /* 1E.8030.0 R/W Default = 0x0 */ - /* 1 = Interrupt enabled - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Ingress Interrupt Mask Register */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssIngressInterruptMaskRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress SA ICV Error Status Register: 1E.8032 */ -/* MSS Ingress SA ICV Error Status Register: 1E.8032 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress SA ICV Error Status Register */ - union - { - struct - { - /*! \brief 1E.8032.F:0 COW MSS Ingress SA ICV Error LSW [F:0] - AQ_MssIngressSaIcvErrorStatusRegister_HHD.u0.bits_0.mssIngressSaIcvErrorLSW - - Default = 0x0000 - - SA ICV error bits 15:0 - - - Notes: - When set, these bits identify the SA that has an ICV error. Write these bits to 1 to clear. */ - unsigned int mssIngressSaIcvErrorLSW : 16; /* 1E.8032.F:0 COW Default = 0x0000 */ - /* SA ICV error bits 15:0 - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Ingress SA ICV Error Status Register */ - union - { - struct - { - /*! \brief 1E.8033.F:0 COW MSS Ingress SA ICV Error MSW [1F:10] - AQ_MssIngressSaIcvErrorStatusRegister_HHD.u1.bits_1.mssIngressSaIcvErrorMSW - - Default = 0x0000 - - SA ICV error bits 31:16 - - - Notes: - When set, these bits identify the SA that has an ICV error. Write these bits to 1 to clear. */ - unsigned int mssIngressSaIcvErrorMSW : 16; /* 1E.8033.F:0 COW Default = 0x0000 */ - /* SA ICV error bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssIngressSaIcvErrorStatusRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress SA Replay Error Status Register: 1E.8034 */ -/* MSS Ingress SA Replay Error Status Register: 1E.8034 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress SA Replay Error Status Register */ - union - { - struct - { - /*! \brief 1E.8034.F:0 COW MSS Ingress SA Replay Error LSW [F:0] - AQ_MssIngressSaReplayErrorStatusRegister_HHD.u0.bits_0.mssIngressSaReplayErrorLSW - - Default = 0x0000 - - SA replay error bits 15:0 - - - Notes: - When set, these bits identify the SA that has a replay error. Write these bits to 1 to clear. */ - unsigned int mssIngressSaReplayErrorLSW : 16; /* 1E.8034.F:0 COW Default = 0x0000 */ - /* SA replay error bits 15:0 - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Ingress SA Replay Error Status Register */ - union - { - struct - { - /*! \brief 1E.8035.F:0 COW MSS Ingress SA Replay Error MSW [1F:10] - AQ_MssIngressSaReplayErrorStatusRegister_HHD.u1.bits_1.mssIngressSaReplayErrorMSW - - Default = 0x0000 - - SA replay error bits 31:16 - - - Notes: - When set, these bits identify the SA that has a replay error. Write these bits to 1 to clear. */ - unsigned int mssIngressSaReplayErrorMSW : 16; /* 1E.8035.F:0 COW Default = 0x0000 */ - /* SA replay error bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssIngressSaReplayErrorStatusRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress SA Expired Status Register: 1E.8036 */ -/* MSS Ingress SA Expired Status Register: 1E.8036 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress SA Expired Status Register */ - union - { - struct - { - /*! \brief 1E.8036.F:0 ROS MSS Ingress SA Expired LSW [F:0] - AQ_MssIngressSaExpiredStatusRegister_HHD.u0.bits_0.mssIngressSaExpiredLSW - - Default = 0x0000 - - SA expired bits 15:0 - - - Notes: - When set, these bits identify the SA that has expired when the SA PN reaches all-ones saturation. Write these bits to 1 to clear. */ - unsigned int mssIngressSaExpiredLSW : 16; /* 1E.8036.F:0 ROS Default = 0x0000 */ - /* SA expired bits 15:0 - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Ingress SA Expired Status Register */ - union - { - struct - { - /*! \brief 1E.8037.F:0 ROS MSS Ingress SA Expired MSW [1F:10] - AQ_MssIngressSaExpiredStatusRegister_HHD.u1.bits_1.mssIngressSaExpiredMSW - - Default = 0x0000 - - SA expired bits 31:16 - - - Notes: - When set, these bits identify the SA that has expired when the SA PN reaches all-ones saturation. Write these bits to 1 to clear. */ - unsigned int mssIngressSaExpiredMSW : 16; /* 1E.8037.F:0 ROS Default = 0x0000 */ - /* SA expired bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssIngressSaExpiredStatusRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress SA Threshold Expired Status Register: 1E.8038 */ -/* MSS Ingress SA Threshold Expired Status Register: 1E.8038 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress SA Threshold Expired Status Register */ - union - { - struct - { - /*! \brief 1E.8038.F:0 ROS MSS Ingress SA Threshold Expired LSW [F:0] - AQ_MssIngressSaThresholdExpiredStatusRegister_HHD.u0.bits_0.mssIngressSaThresholdExpiredLSW - - Default = 0x0000 - - SA threshold expired bits 15:0 - - - Notes: - When set, these bits identify the SA that has expired when the SA PN has reached the configured threshold See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . Write these bits to 1 to clear. */ - unsigned int mssIngressSaThresholdExpiredLSW : 16; /* 1E.8038.F:0 ROS Default = 0x0000 */ - /* SA threshold expired bits 15:0 - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Ingress SA Threshold Expired Status Register */ - union - { - struct - { - /*! \brief 1E.8039.F:0 ROS MSS Ingress SA Threshold Expired MSW [1F:10] - AQ_MssIngressSaThresholdExpiredStatusRegister_HHD.u1.bits_1.mssIngressSaThresholdExpiredMSW - - Default = 0x0000 - - SA threshold expired bits 31:16 - - - Notes: - When set, these bits identify the SA that has expired when the SA PN has reached the configured threshold See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . Write these bits to 1 to clear. */ - unsigned int mssIngressSaThresholdExpiredMSW : 16; /* 1E.8039.F:0 ROS Default = 0x0000 */ - /* SA threshold expired bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssIngressSaThresholdExpiredStatusRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress ECC Interrupt Status Register: 1E.803A */ -/* MSS Ingress ECC Interrupt Status Register: 1E.803A */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress ECC Interrupt Status Register */ - union - { - struct - { - /*! \brief 1E.803A.F:0 R/W MSS Ingress SA ECC Error Interrupt LSW [F:0] - AQ_MssIngressEccInterruptStatusRegister_HHD.u0.bits_0.mssIngressSaEccErrorInterruptLSW - - Default = 0x0000 - - SA ECC error interrupt bits 15:0 - - - Notes: - When set to 1, indicates that an ECC error occured for the SA. */ - unsigned int mssIngressSaEccErrorInterruptLSW : 16; /* 1E.803A.F:0 R/W Default = 0x0000 */ - /* SA ECC error interrupt bits 15:0 - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Ingress ECC Interrupt Status Register */ - union - { - struct - { - /*! \brief 1E.803B.F:0 R/W MSS Ingress SA ECC Error Interrupt MSW [1F:10] - AQ_MssIngressEccInterruptStatusRegister_HHD.u1.bits_1.mssIngressSaEccErrorInterruptMSW - - Default = 0x0000 - - SA ECC error interrupt bits 31:16 - - - Notes: - When set to 1, indicates that an ECC error occured for the SA. */ - unsigned int mssIngressSaEccErrorInterruptMSW : 16; /* 1E.803B.F:0 R/W Default = 0x0000 */ - /* SA ECC error interrupt bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssIngressEccInterruptStatusRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress LUT Address Control Register: 1E.8080 */ -/* MSS Ingress LUT Address Control Register: 1E.8080 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress LUT Address Control Register */ - union - { - struct - { - /*! \brief 1E.8080.F:C R/W MSS Ingress LUT Select [3:0] - AQ_MssIngressLutAddressControlRegister_HHD.u0.bits_0.mssIngressLutSelect - - Default = 0x0 - - LUT select - - - Notes: - 0x0 : Ingress Pre-Security MAC Control FIlter (IGPRCTLF) LUT - 0x1 : Ingress Pre-Security Classification LUT (IGPRC) - 0x2 : Ingress Packet Format (IGPFMT) SAKey LUT - 0x3 : Ingress Packet Format (IGPFMT) SC/SA LUT - 0x4 : Ingress Post-Security Classification LUT (IGPOC) - 0x5 : Ingress Post-Security MAC Control Filter (IGPOCTLF) LUT - 0x6 : Ingress MIB (IGMIB) */ - unsigned int mssIngressLutSelect : 4; /* 1E.8080.F:C R/W Default = 0x0 */ - /* LUT select - */ - unsigned int reserved0 : 3; - /*! \brief 1E.8080.8:0 R/W MSS Ingress LUT Address [8:0] - AQ_MssIngressLutAddressControlRegister_HHD.u0.bits_0.mssIngressLutAddress - - Default = 0x000 - - LUT address - - */ - unsigned int mssIngressLutAddress : 9; /* 1E.8080.8:0 R/W Default = 0x000 */ - /* LUT address - */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_MssIngressLutAddressControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress LUT Control Register: 1E.8081 */ -/* MSS Ingress LUT Control Register: 1E.8081 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress LUT Control Register */ - union - { - struct - { - /*! \brief 1E.8081.F R/W MSS Ingress LUT Write - AQ_MssIngressLutControlRegister_HHD.u0.bits_0.mssIngressLutWrite - - Default = 0x0 - - 1 = LUT write - - - Notes: - Setting this bit to 1, will write the LUT. This bit will automatically clear to 0. */ - unsigned int mssIngressLutWrite : 1; /* 1E.8081.F R/W Default = 0x0 */ - /* 1 = LUT write - */ - /*! \brief 1E.8081.E R/W MSS Ingress LUT Read - AQ_MssIngressLutControlRegister_HHD.u0.bits_0.mssIngressLutRead - - Default = 0x0 - - 1 = LUT read - - - Notes: - Setting this bit to 1, will read the LUT. This bit will automatically clear to 0. */ - unsigned int mssIngressLutRead : 1; /* 1E.8081.E R/W Default = 0x0 */ - /* 1 = LUT read - */ - unsigned int reserved0 : 14; - } bits_0; - uint16_t word_0; - } u0; -} AQ_MssIngressLutControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress LUT Data Control Register: 1E.80A0 */ -/* MSS Ingress LUT Data Control Register: 1E.80A0 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80A0.F:0 R/W MSS Ingress LUT Data 0 [F:0] - AQ_MssIngressLutDataControlRegister_HHD.u0.bits_0.mssIngressLutData_0 - - Default = 0x0000 - - LUT data bits 15:0 - - */ - unsigned int mssIngressLutData_0 : 16; /* 1E.80A0.F:0 R/W Default = 0x0000 */ - /* LUT data bits 15:0 - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80A1.F:0 R/W MSS Ingress LUT Data 1 [1F:10] - AQ_MssIngressLutDataControlRegister_HHD.u1.bits_1.mssIngressLutData_1 - - Default = 0x0000 - - LUT data bits 31:16 - - */ - unsigned int mssIngressLutData_1 : 16; /* 1E.80A1.F:0 R/W Default = 0x0000 */ - /* LUT data bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80A2.F:0 R/W MSS Ingress LUT Data 2 [2F:20] - AQ_MssIngressLutDataControlRegister_HHD.u2.bits_2.mssIngressLutData_2 - - Default = 0x0000 - - LUT data bits 47:32 - - */ - unsigned int mssIngressLutData_2 : 16; /* 1E.80A2.F:0 R/W Default = 0x0000 */ - /* LUT data bits 47:32 - */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80A3.F:0 R/W MSS Ingress LUT Data 3 [3F:30] - AQ_MssIngressLutDataControlRegister_HHD.u3.bits_3.mssIngressLutData_3 - - Default = 0x0000 - - LUT data bits 63:48 - - */ - unsigned int mssIngressLutData_3 : 16; /* 1E.80A3.F:0 R/W Default = 0x0000 */ - /* LUT data bits 63:48 - */ - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80A4.F:0 R/W MSS Ingress LUT Data 4 [4F:40] - AQ_MssIngressLutDataControlRegister_HHD.u4.bits_4.mssIngressLutData_4 - - Default = 0x0000 - - LUT data bits 79:64 - - */ - unsigned int mssIngressLutData_4 : 16; /* 1E.80A4.F:0 R/W Default = 0x0000 */ - /* LUT data bits 79:64 - */ - } bits_4; - uint16_t word_4; - } u4; - /*! \brief Union for bit and word level access of word 5 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80A5.F:0 R/W MSS Ingress LUT Data 5 [5F:50] - AQ_MssIngressLutDataControlRegister_HHD.u5.bits_5.mssIngressLutData_5 - - Default = 0x0000 - - LUT data bits 95:80 - - */ - unsigned int mssIngressLutData_5 : 16; /* 1E.80A5.F:0 R/W Default = 0x0000 */ - /* LUT data bits 95:80 - */ - } bits_5; - uint16_t word_5; - } u5; - /*! \brief Union for bit and word level access of word 6 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80A6.F:0 R/W MSS Ingress LUT Data 6 [6F:60] - AQ_MssIngressLutDataControlRegister_HHD.u6.bits_6.mssIngressLutData_6 - - Default = 0x0000 - - LUT data bits 111:96 - - */ - unsigned int mssIngressLutData_6 : 16; /* 1E.80A6.F:0 R/W Default = 0x0000 */ - /* LUT data bits 111:96 - */ - } bits_6; - uint16_t word_6; - } u6; - /*! \brief Union for bit and word level access of word 7 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80A7.F:0 R/W MSS Ingress LUT Data 7 [7F:70] - AQ_MssIngressLutDataControlRegister_HHD.u7.bits_7.mssIngressLutData_7 - - Default = 0x0000 - - LUT data bits 127:112 - - */ - unsigned int mssIngressLutData_7 : 16; /* 1E.80A7.F:0 R/W Default = 0x0000 */ - /* LUT data bits 127:112 - */ - } bits_7; - uint16_t word_7; - } u7; - /*! \brief Union for bit and word level access of word 8 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80A8.F:0 R/W MSS Ingress LUT Data 8 [8F:80] - AQ_MssIngressLutDataControlRegister_HHD.u8.bits_8.mssIngressLutData_8 - - Default = 0x0000 - - LUT data bits 143:128 - - */ - unsigned int mssIngressLutData_8 : 16; /* 1E.80A8.F:0 R/W Default = 0x0000 */ - /* LUT data bits 143:128 - */ - } bits_8; - uint16_t word_8; - } u8; - /*! \brief Union for bit and word level access of word 9 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80A9.F:0 R/W MSS Ingress LUT Data 9 [9F:90] - AQ_MssIngressLutDataControlRegister_HHD.u9.bits_9.mssIngressLutData_9 - - Default = 0x0000 - - LUT data bits 159:144 - - */ - unsigned int mssIngressLutData_9 : 16; /* 1E.80A9.F:0 R/W Default = 0x0000 */ - /* LUT data bits 159:144 - */ - } bits_9; - uint16_t word_9; - } u9; - /*! \brief Union for bit and word level access of word 10 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80AA.F:0 R/W MSS Ingress LUT Data 10 [AF:A0] - AQ_MssIngressLutDataControlRegister_HHD.u10.bits_10.mssIngressLutData_10 - - Default = 0x0000 - - LUT data bits 175:160 - - */ - unsigned int mssIngressLutData_10 : 16; /* 1E.80AA.F:0 R/W Default = 0x0000 */ - /* LUT data bits 175:160 - */ - } bits_10; - uint16_t word_10; - } u10; - /*! \brief Union for bit and word level access of word 11 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80AB.F:0 R/W MSS Ingress LUT Data 11 [BF:B0] - AQ_MssIngressLutDataControlRegister_HHD.u11.bits_11.mssIngressLutData_11 - - Default = 0x0000 - - LUT data bits 191:176 - - */ - unsigned int mssIngressLutData_11 : 16; /* 1E.80AB.F:0 R/W Default = 0x0000 */ - /* LUT data bits 191:176 - */ - } bits_11; - uint16_t word_11; - } u11; - /*! \brief Union for bit and word level access of word 12 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80AC.F:0 R/W MSS Ingress LUT Data 12 [CF:C0] - AQ_MssIngressLutDataControlRegister_HHD.u12.bits_12.mssIngressLutData_12 - - Default = 0x0000 - - LUT data bits 207:192 - - */ - unsigned int mssIngressLutData_12 : 16; /* 1E.80AC.F:0 R/W Default = 0x0000 */ - /* LUT data bits 207:192 - */ - } bits_12; - uint16_t word_12; - } u12; - /*! \brief Union for bit and word level access of word 13 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80AD.F:0 R/W MSS Ingress LUT Data 13 [DF:D0] - AQ_MssIngressLutDataControlRegister_HHD.u13.bits_13.mssIngressLutData_13 - - Default = 0x0000 - - LUT data bits 223:208 - - */ - unsigned int mssIngressLutData_13 : 16; /* 1E.80AD.F:0 R/W Default = 0x0000 */ - /* LUT data bits 223:208 - */ - } bits_13; - uint16_t word_13; - } u13; - /*! \brief Union for bit and word level access of word 14 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80AE.F:0 R/W MSS Ingress LUT Data 14 [EF:E0] - AQ_MssIngressLutDataControlRegister_HHD.u14.bits_14.mssIngressLutData_14 - - Default = 0x0000 - - LUT data bits 239:224 - - */ - unsigned int mssIngressLutData_14 : 16; /* 1E.80AE.F:0 R/W Default = 0x0000 */ - /* LUT data bits 239:224 - */ - } bits_14; - uint16_t word_14; - } u14; - /*! \brief Union for bit and word level access of word 15 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80AF.F:0 R/W MSS Ingress LUT Data 15 [FF:F0] - AQ_MssIngressLutDataControlRegister_HHD.u15.bits_15.mssIngressLutData_15 - - Default = 0x0000 - - LUT data bits 255:240 - - */ - unsigned int mssIngressLutData_15 : 16; /* 1E.80AF.F:0 R/W Default = 0x0000 */ - /* LUT data bits 255:240 - */ - } bits_15; - uint16_t word_15; - } u15; - /*! \brief Union for bit and word level access of word 16 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80B0.F:0 R/W MSS Ingress LUT Data 16 [10F:100] - AQ_MssIngressLutDataControlRegister_HHD.u16.bits_16.mssIngressLutData_16 - - Default = 0x0000 - - LUT data bits 271:256 - - */ - unsigned int mssIngressLutData_16 : 16; /* 1E.80B0.F:0 R/W Default = 0x0000 */ - /* LUT data bits 271:256 - */ - } bits_16; - uint16_t word_16; - } u16; - /*! \brief Union for bit and word level access of word 17 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80B1.F:0 R/W MSS Ingress LUT Data 17 [11F:110] - AQ_MssIngressLutDataControlRegister_HHD.u17.bits_17.mssIngressLutData_17 - - Default = 0x0000 - - LUT data bits 287:272 - - */ - unsigned int mssIngressLutData_17 : 16; /* 1E.80B1.F:0 R/W Default = 0x0000 */ - /* LUT data bits 287:272 - */ - } bits_17; - uint16_t word_17; - } u17; - /*! \brief Union for bit and word level access of word 18 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80B2.F:0 R/W MSS Ingress LUT Data 18 [12F:120] - AQ_MssIngressLutDataControlRegister_HHD.u18.bits_18.mssIngressLutData_18 - - Default = 0x0000 - - LUT data bits 303:288 - - */ - unsigned int mssIngressLutData_18 : 16; /* 1E.80B2.F:0 R/W Default = 0x0000 */ - /* LUT data bits 303:288 - */ - } bits_18; - uint16_t word_18; - } u18; - /*! \brief Union for bit and word level access of word 19 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80B3.F:0 R/W MSS Ingress LUT Data 19 [13F:130] - AQ_MssIngressLutDataControlRegister_HHD.u19.bits_19.mssIngressLutData_19 - - Default = 0x0000 - - LUT data bits 319:304 - - */ - unsigned int mssIngressLutData_19 : 16; /* 1E.80B3.F:0 R/W Default = 0x0000 */ - /* LUT data bits 319:304 - */ - } bits_19; - uint16_t word_19; - } u19; - /*! \brief Union for bit and word level access of word 20 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80B4.F:0 R/W MSS Ingress LUT Data 20 [14F:140] - AQ_MssIngressLutDataControlRegister_HHD.u20.bits_20.mssIngressLutData_20 - - Default = 0x0000 - - LUT data bits 335:320 - - */ - unsigned int mssIngressLutData_20 : 16; /* 1E.80B4.F:0 R/W Default = 0x0000 */ - /* LUT data bits 335:320 - */ - } bits_20; - uint16_t word_20; - } u20; - /*! \brief Union for bit and word level access of word 21 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80B5.F:0 R/W MSS Ingress LUT Data 21 [15F:150] - AQ_MssIngressLutDataControlRegister_HHD.u21.bits_21.mssIngressLutData_21 - - Default = 0x0000 - - LUT data bits 351:336 - - */ - unsigned int mssIngressLutData_21 : 16; /* 1E.80B5.F:0 R/W Default = 0x0000 */ - /* LUT data bits 351:336 - */ - } bits_21; - uint16_t word_21; - } u21; - /*! \brief Union for bit and word level access of word 22 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80B6.F:0 R/W MSS Ingress LUT Data 22 [16F:160] - AQ_MssIngressLutDataControlRegister_HHD.u22.bits_22.mssIngressLutData_22 - - Default = 0x0000 - - LUT data bits 367:352 - - */ - unsigned int mssIngressLutData_22 : 16; /* 1E.80B6.F:0 R/W Default = 0x0000 */ - /* LUT data bits 367:352 - */ - } bits_22; - uint16_t word_22; - } u22; - /*! \brief Union for bit and word level access of word 23 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80B7.F:0 R/W MSS Ingress LUT Data 23 [17F:170] - AQ_MssIngressLutDataControlRegister_HHD.u23.bits_23.mssIngressLutData_23 - - Default = 0x0000 - - LUT data bits 383:368 - - */ - unsigned int mssIngressLutData_23 : 16; /* 1E.80B7.F:0 R/W Default = 0x0000 */ - /* LUT data bits 383:368 - */ - } bits_23; - uint16_t word_23; - } u23; -} AQ_MssIngressLutDataControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line General Control Register: 1E.9004 */ -/* MSM Line General Control Register: 1E.9004 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line General Control Register */ - union - { - struct - { - /*! \brief 1E.9004.F R/W MSM Line PHY Tx Enable - AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLinePhyTxEnable - - Default = 0x0 - - 1 = Enable PHY Tx - - - Notes: - Directly controls the phy_tx_ena pin. */ - unsigned int msmLinePhyTxEnable : 1; /* 1E.9004.F R/W Default = 0x0 */ - /* 1 = Enable PHY Tx - */ - /*! \brief 1E.9004.E R/W MSM Line Rx Error Discard - AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineRxErrorDiscard - - Default = 0x0 - - 1 = Enable discard of received errored frames - - - Notes: - Rx errored frame discard enable. When set to 1, any frame received with an error is discarded and not forwarded to the client interface. When set to 0, errored frames are forwarded to the client interface with ff_rx_err asserted. - Note : It is recommended to set this bit to 1 only when store and forward operation is enabled (RX_SECTION_FULL TBD). */ - unsigned int msmLineRxErrorDiscard : 1; /* 1E.9004.E R/W Default = 0x0 */ - /* 1 = Enable discard of received errored frames - */ - /*! \brief 1E.9004.D R/W MSM Line Control Frame Enable - AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineControlFrameEnable - - Default = 0x0 - - 1 = Control frame enabled - - - Notes: - MAC control frame enable. When set to 1, the MAC control frames with any Opcode other than 0x0001 are accepted and forwarded to the client interface. When set to 0, MAC control frames with any opcode other than 0x0001 are silently discarded. */ - unsigned int msmLineControlFrameEnable : 1; /* 1E.9004.D R/W Default = 0x0 */ - /* 1 = Control frame enabled - */ - /*! \brief 1E.9004.C R/WSC MSM Line Soft Reset - AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineSoftReset - - Default = 0x0 - - 1 = Soft reset - - - Notes: - Software reset. Self clearing bit. When set to 1, resets all statistic counters as well as the Tx and Rx FIFOs. It should be issued after all traffic has been stopped as a result of clearing the Rx/Tx enable bits ( See MAC Rx Enable set to 0 and See MAC Tx Enable set to 0). - Note : Can lead to an Rx interface (ff_rx_xxx) violations to the application if the reset is issued in the middle of a receive frame transfer. Then the end of packet (assertion of ff_rx_eop) is lost and the application should be prepeared to handle this exception. */ - unsigned int msmLineSoftReset : 1; /* 1E.9004.C R/WSC Default = 0x0 */ - /* 1 = Soft reset - */ - /*! \brief 1E.9004.B R/W MSM Line Tx Pad Enable - AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineTxPadEnable - - Default = 0x1 - - 1 = Enable Tx padding - - - Notes: - When set to 1, enable padding of frames in the Tx direction. When set to 0, the MAC will not extend frames from the application to a minimum of 64 bytes, allowing to transmit short frames (violating the Ethernet mimimum size requirements). Must be set to 1 for normal operation. */ - unsigned int msmLineTxPadEnable : 1; /* 1E.9004.B R/W Default = 0x1 */ - /* 1 = Enable Tx padding - */ - /*! \brief 1E.9004.A R/W MSM Line Tx CRC Append - AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineTxCrcAppend - - Default = 0x0 - - 1 = Append Tx CRC - - - Notes: - Permanently enable CRC append on transmit. If set to 1, the Tx will append a CRC to all transmitted frames. If set to 0, CRC append can be controlled on a per frame basis using the pin ff_tx_crc. - This configuration bit is OR'ed with the external ff_tx_crc pin to instruct the Tx to append a CRC to transmitted frames. The ff_tx_crc pin is tied to 0. */ - unsigned int msmLineTxCrcAppend : 1; /* 1E.9004.A R/W Default = 0x0 */ - /* 1 = Append Tx CRC - */ - /*! \brief 1E.9004.9 R/W MSM Line Tx Address Insert Enable - AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineTxAddressInsertEnable - - Default = 0x0 - - 1 = Insert Tx MAC source address - - - Notes: - Set the source MAC address on transmit. If set to 1, the MAC overwrites the source MAC address with the MAC programmed address in all transmitted frames. When set to 0, the source MAC address is transmitted unmodified from the MAC Tx client application. */ - unsigned int msmLineTxAddressInsertEnable : 1; /* 1E.9004.9 R/W Default = 0x0 */ - /* 1 = Insert Tx MAC source address - */ - /*! \brief 1E.9004.8 R/W MSM Line Pause Ignore - AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLinePauseIgnore - - Default = 0x0 - - 1 = Ignore pause frames - - - Notes: - Ignore pause frame quanta. If set to 1, received pause frames are ignored by the MAC. When set to 0, the Tx is stopped for the amount of time specified in the pause quanta received within the pause frame. */ - unsigned int msmLinePauseIgnore : 1; /* 1E.9004.8 R/W Default = 0x0 */ - /* 1 = Ignore pause frames - */ - /*! \brief 1E.9004.7 R/W MSM Line Pause Forward - AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLinePauseForward - - Default = 0x0 - - 1 = Enable Pause forwarding - - - Notes: - Terminate or forward pause frames. If set to 1, pause frames are forwarded to the user application. In normal mode, when set to 0, pause frames are terminated and discarded within the MAC. */ - unsigned int msmLinePauseForward : 1; /* 1E.9004.7 R/W Default = 0x0 */ - /* 1 = Enable Pause forwarding - */ - /*! \brief 1E.9004.6 R/W MSM Line CRC Forward - AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineCrcForward - - Default = 0x0 - - 1 = Enable CRC forwarding - - - Notes: - When set to 1, the CRC field of the received frames is forwarded with the frame to the user application. If disabled, the CRC field is stripped from the frame. - Note : If padding is enabled ( See MAC PAD Enable set to 1), this bit is ignored. */ - unsigned int msmLineCrcForward : 1; /* 1E.9004.6 R/W Default = 0x0 */ - /* 1 = Enable CRC forwarding - */ - /*! \brief 1E.9004.5 R/W MSM Line PAD Enable - AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLinePadEnable - - Default = 0x0 - - 1 = Enable frame padding removal on Rx - - - Notes: - When set to 1, enable frame padding removal on the Rx path. If enabled, padding is removed before the frame is transferred to the MAC client application. If disabled, no padding is removed on the Rx by the MAC. - Note : On Tx, the MAC always adds padding as required. */ - unsigned int msmLinePadEnable : 1; /* 1E.9004.5 R/W Default = 0x0 */ - /* 1 = Enable frame padding removal on Rx - */ - /*! \brief 1E.9004.4 R/W MSM Line Promiscuous Mode - AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLinePromiscuousMode - - Default = 0x0 - - 1 = Promiscuous mode - - - Notes: - When set to 1, all frames are received without any MAC address filtering. */ - unsigned int msmLinePromiscuousMode : 1; /* 1E.9004.4 R/W Default = 0x0 */ - /* 1 = Promiscuous mode - */ - /*! \brief 1E.9004.3 R/W MSM Line WAN Mode - AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineWanMode - - Default = 0x0 - - 1 = WAN mode - 0 = LAN mode - - - Notes: - WAN mode enable. Sets WAN mode when set to 1 and LAN mode when set to 0. Note: When changing the mode, verifiy correct setting of the Tx IPG. */ - unsigned int msmLineWanMode : 1; /* 1E.9004.3 R/W Default = 0x0 */ - /* 1 = WAN mode - 0 = LAN mode - */ - unsigned int reserved0 : 1; - /*! \brief 1E.9004.1 R/W MSM Line Rx Enable - AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineRxEnable - - Default = 0x0 - - 1 = Rx enable - - Notes: - MAC Tx path enable. Should be set to 1 to enable the MAC Tx path. Should be set to 0 to disable the MAC Tx path. */ - unsigned int msmLineRxEnable : 1; /* 1E.9004.1 R/W Default = 0x0 */ - /* 1 = Rx enable */ - /*! \brief 1E.9004.0 R/W MSM Line Tx Enable - AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineTxEnable - - Default = 0x0 - - 1 = Tx enable - - Notes: - MAC Rx path enable. Should be set to 1 to enable the MAC Rx path. Should be set to 0 to disable the MAC Rx path. */ - unsigned int msmLineTxEnable : 1; /* 1E.9004.0 R/W Default = 0x0 */ - /* 1 = Tx enable */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line General Control Register */ - union - { - struct - { - unsigned int reserved0 : 8; - /*! \brief 1E.9005.7 R/W MSM Line Tx Low Power IDLE Enable - AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLineTxLowPowerIdleEnable - - Default = 0x0 - - 1 = Transmit LPI enable - - - Notes: - Transmit low power IDLE enable. When set to 1, the MAC completes the transmission of the current frame and generates low power IDLE sequences (LPI) to the XGMII/SGMII. When set to 0, the MAC operates in normal mode. This bit is OR'ed with the reg_lowp_ena pin. */ - unsigned int msmLineTxLowPowerIdleEnable : 1; /* 1E.9005.7 R/W Default = 0x0 */ - /* 1 = Transmit LPI enable - */ - unsigned int reserved1 : 1; - /*! \brief 1E.9005.5 R/W MSM Line SFD Check Disable - AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLineSfdCheckDisable - - Default = 0x0 - - 1 = Disable SFD check - - - Notes: - Disable check of SFD (0xD5) character at frame start. When set to 1, the frame is accepted even if the SFD byte following the preamble is not 0xD5. When set to 0, a frame is accepted only if the SFD byte is found with the value 0xD5. */ - unsigned int msmLineSfdCheckDisable : 1; /* 1E.9005.5 R/W Default = 0x0 */ - /* 1 = Disable SFD check - */ - unsigned int reserved2 : 1; - /*! \brief 1E.9005.3 R/W MSM Line Priority Flow Control Enable - AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLinePriorityFlowControlEnable - - Default = 0x0 - - 1 = Enable priority flow control - 0 = Enable link flow control - - - Notes: - Enable priority flow control (PFC) mode of operation. When set to 0, the MAC uses standard link pause frames. When set to 1, the MAC will transmit and accept PFC frames. */ - unsigned int msmLinePriorityFlowControlEnable : 1; /* 1E.9005.3 R/W Default = 0x0 */ - /* 1 = Enable priority flow control - 0 = Enable link flow control - */ - /*! \brief 1E.9005.2 R/W MSM Line IDLE Column Count Extend - AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLineIdleColumnCountExtend - - Default = 0x0 - - 1 = Extend IDLE column count - - Notes: - When set to 1, extends the RS layer IDLE column counter by 2x. The IEEE 802.3ae defines the fault condition to be cleared after 128 columns of IDLE have been received. If the MAC operates together with a WAN mode PCS (WIS) it may may happen (depending on PCS) that this period is too short to bridge the IDLE stuffing occurring in this mode, leading to a toggling fault indication. In this case, extending the counter helps to aoivd toggling fault indications. */ - unsigned int msmLineIdleColumnCountExtend : 1; /* 1E.9005.2 R/W Default = 0x0 */ - /* 1 = Extend IDLE column count */ - /*! \brief 1E.9005.1 R/W MSM Line Length Check Disable - AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLineLengthCheckDisable - - Default = 0x0 - - 1 = Disable length check - - Notes: - Payload length check disable. When set to 0, the MAC checks the frames payload length with the frame length/type field. When set to 1, the payload length check is disabled. */ - unsigned int msmLineLengthCheckDisable : 1; /* 1E.9005.1 R/W Default = 0x0 */ - /* 1 = Disable length check */ - /*! \brief 1E.9005.0 R/W MSM Line Force Send IDLE - AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLineForceSendIdle - - Default = 0x0 - - 1 = Force send idle - - Notes: - When set to 1, suppress any frame transmissions and forces IDLE n the Tx interface instead of frames. This control affects the MAC reconciliation layer (RS) which acts after all MAC datapath has processed the frame. - Note : Does not have an effect on fault handling (i.e. reception of local fault will still cause transmit of remote fault). - Must be 0 for normal operation. */ - unsigned int msmLineForceSendIdle : 1; /* 1E.9005.0 R/W Default = 0x0 */ - /* 1 = Force send idle */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineGeneralControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line FIFO Control Register: 1E.900E */ -/* MSM Line FIFO Control Register: 1E.900E */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line FIFO Control Register */ - union - { - struct - { - unsigned int reserved0 : 8; - /*! \brief 1E.900E.7:0 R/W MSM Line Rx FIFO Full Threshold [7:0] - AQ_MsmLineFifoControlRegister_HHD.u0.bits_0.msmLineRxFifoFullThreshold - - Default = 0x08 - - Rx FIFO full threshold - - Notes: - All threshold values are in steps of FIFO words. */ - unsigned int msmLineRxFifoFullThreshold : 8; /* 1E.900E.7:0 R/W Default = 0x08 */ - /* Rx FIFO full threshold */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line FIFO Control Register */ - union - { - struct - { - unsigned int reserved0 : 8; - /*! \brief 1E.900F.7:0 R/W MSM Line Rx FIFO Empty Threshold [7:0] - AQ_MsmLineFifoControlRegister_HHD.u1.bits_1.msmLineRxFifoEmptyThreshold - - Default = 0x00 - - Rx FIFO empty threshold - - Notes: - All threshold values are in steps of FIFO words. */ - unsigned int msmLineRxFifoEmptyThreshold : 8; /* 1E.900F.7:0 R/W Default = 0x00 */ - /* Rx FIFO empty threshold */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of MSM Line FIFO Control Register */ - union - { - struct - { - unsigned int reserved0 : 10; - /*! \brief 1E.9010.5:0 R/W MSM Line Tx FIFO Full Threshold [5:0] - AQ_MsmLineFifoControlRegister_HHD.u2.bits_2.msmLineTxFifoFullThreshold - - Default = 0x08 - - Tx FIFO full threshold - - Notes: - All threshold values are in steps of FIFO words. */ - unsigned int msmLineTxFifoFullThreshold : 6; /* 1E.9010.5:0 R/W Default = 0x08 */ - /* Tx FIFO full threshold */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of MSM Line FIFO Control Register */ - union - { - struct - { - unsigned int reserved0 : 10; - /*! \brief 1E.9011.5:0 R/W MSM Line Tx FIFO Empty Threshold [5:0] - AQ_MsmLineFifoControlRegister_HHD.u3.bits_3.msmLineTxFifoEmptyThreshold - - Default = 0x00 - - Tx FIFO empty threshold - - Notes: - All threshold values are in steps of FIFO words. */ - unsigned int msmLineTxFifoEmptyThreshold : 6; /* 1E.9011.5:0 R/W Default = 0x00 */ - /* Tx FIFO empty threshold */ - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of MSM Line FIFO Control Register */ - union - { - struct - { - unsigned int reserved0 : 8; - /*! \brief 1E.9012.7:0 ROS MSM Line Rx FIFO Almost Full Threshold [7:0] - AQ_MsmLineFifoControlRegister_HHD.u4.bits_4.msmLineRxFifoAlmostFullThreshold - - Default = 0x00 - - Rx FIFO almost full threshold - - Notes: - Unused. */ - unsigned int msmLineRxFifoAlmostFullThreshold : 8; /* 1E.9012.7:0 ROS Default = 0x00 */ - /* Rx FIFO almost full threshold */ - } bits_4; - uint16_t word_4; - } u4; - /*! \brief Union for bit and word level access of word 5 of MSM Line FIFO Control Register */ - union - { - struct - { - unsigned int reserved0 : 8; - /*! \brief 1E.9013.7:0 ROS MSM Line Rx FIFO Almost Empty Threshold [7:0] - AQ_MsmLineFifoControlRegister_HHD.u5.bits_5.msmLineRxFifoAlmostEmptyThreshold - - Default = 0x00 - - Rx FIFO almost empty threshold - - Notes: - Unused. */ - unsigned int msmLineRxFifoAlmostEmptyThreshold : 8; /* 1E.9013.7:0 ROS Default = 0x00 */ - /* Rx FIFO almost empty threshold */ - } bits_5; - uint16_t word_5; - } u5; - /*! \brief Union for bit and word level access of word 6 of MSM Line FIFO Control Register */ - union - { - struct - { - unsigned int reserved0 : 8; - /*! \brief 1E.9014.7:0 ROS MSM Line Tx FIFO Almost Full Threshold [7:0] - AQ_MsmLineFifoControlRegister_HHD.u6.bits_6.msmLineTxFifoAlmostFullThreshold - - Default = 0x00 - - Tx FIFO almost full threshold - - Notes: - Unused. */ - unsigned int msmLineTxFifoAlmostFullThreshold : 8; /* 1E.9014.7:0 ROS Default = 0x00 */ - /* Tx FIFO almost full threshold */ - } bits_6; - uint16_t word_6; - } u6; - /*! \brief Union for bit and word level access of word 7 of MSM Line FIFO Control Register */ - union - { - struct - { - unsigned int reserved0 : 8; - /*! \brief 1E.9015.7:0 ROS MSM Line Tx FIFO Almost Empty Threshold [7:0] - AQ_MsmLineFifoControlRegister_HHD.u7.bits_7.msmLineTxFifoAlmostEmptyThreshold - - Default = 0x00 - - Tx FIFO almost empty threshold - - Notes: - Unused. */ - unsigned int msmLineTxFifoAlmostEmptyThreshold : 8; /* 1E.9015.7:0 ROS Default = 0x00 */ - /* Tx FIFO almost empty threshold */ - } bits_7; - uint16_t word_7; - } u7; -} AQ_MsmLineFifoControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line General Status Register: 1E.9020 */ -/* MSM Line General Status Register: 1E.9020 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line General Status Register */ - union - { - struct - { - unsigned int reserved0 : 10; - /*! \brief 1E.9020.5 RO MSM Line Tx FIFO Empty - AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLineTxFifoEmpty - - - - Tx FIFO empty - - Notes: - When set to 1, indicates the Tx FIFO is empty. When set to 0, Tx FIFO is non-empty. */ - unsigned int msmLineTxFifoEmpty : 1; /* 1E.9020.5 RO */ - /* Tx FIFO empty */ - /*! \brief 1E.9020.4 RO MSM Line Rx Low Power IDLE - AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLineRxLowPowerIdle - - - - Rx LPI detected - - Notes: - Receive low power IDLE (LPI). Set to 1 when LPI is currently detected on the MAC Rx interface. Set to 0, when the MAC currently operates in normal mode. */ - unsigned int msmLineRxLowPowerIdle : 1; /* 1E.9020.4 RO */ - /* Rx LPI detected */ - /*! \brief 1E.9020.3 R/W MSM Line Timestamp Available - AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLineTimestampAvailable - - Default = 0x0 - - Timestamp available - - Notes: - Transmit timestamp available. Indicates that the timestamp of the last transmitted event frame (which had ff_tx_ts_frm=1) is available in the register See MAC Time Stamp Status 0 [F:0] and See MAC Time Stamp Status 1 [F:0] . To clear this bit, the bit must be written with a 1. - */ - unsigned int msmLineTimestampAvailable : 1; /* 1E.9020.3 R/W Default = 0x0 */ - /* Timestamp available */ - /*! \brief 1E.9020.2 RO MSM Line PHY Loss of Signal - AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLinePhyLossOfSignal - - - - PHY loss of signal - - Notes: - PHY indicates loss of signal. This is the value of pin phy_los which is tied to 0. */ - unsigned int msmLinePhyLossOfSignal : 1; /* 1E.9020.2 RO */ - /* PHY loss of signal */ - /*! \brief 1E.9020.1 BLH MSM Line Rx Remote Fault - AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLineRxRemoteFault - - - - Rx remote fault detected - - Notes: - Latch high local fault status. Set to 1, whent he MAC detects Rx local fault sequences on the Rx interface. Reset to 0 after read and after reset. */ - unsigned int msmLineRxRemoteFault : 1; /* 1E.9020.1 BLH */ - /* Rx remote fault detected */ - /*! \brief 1E.9020.0 BLH MSM Line Rx Local Fault - AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLineRxLocalFault - - - - Rx local fault detected - - Notes: - Latch high local fault status. Set to 1, whent he MAC detects Rx local fault sequences on the Rx interface. Reset to 0 after read and after reset. */ - unsigned int msmLineRxLocalFault : 1; /* 1E.9020.0 BLH */ - /* Rx local fault detected */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line General Status Register */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineGeneralStatusRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Tx IPG Control Register: 1E.9022 */ -/* MSM Line Tx IPG Control Register: 1E.9022 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Tx IPG Control Register */ - union - { - struct - { - unsigned int reserved0 : 10; - /*! \brief 1E.9022.5:0 R/W MSM Line Tx IPG Length [5:0] - AQ_MsmLineTxIpgControlRegister_HHD.u0.bits_0.msmLineTxIpgLength - - Default = 0x0C - - Tx IPG length - - Notes: - Tx inter-packet gap (IPG) value. Depending on LAN or WAN mode of operation. - LAN Mode : Number of octets in steps of 4. Valid values are 8, 12, 16,..., 100. DIC is supported for any setting > 8. A default of 12 must be set to conform to IEEE802.3ae. - WAN Mode : Stretch factor. Valid values are 4 ... 15. The stretch factor is calculated as (value+1)*8. A default of 12 must be set to conform to IEEE802.3ae (i.e. 13*8=104). A larger value shrinks the IPG (increasing bandwidth). - The reset value of 12 leads to IEEE802.3ae conformant behavior in both modes. - Note : WAN mode is only available in 10G mode of operation. */ - unsigned int msmLineTxIpgLength : 6; /* 1E.9022.5:0 R/W Default = 0x0C */ - /* Tx IPG length */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Tx IPG Control Register */ - union - { - struct - { - /*! \brief 1E.9023.F:0 MSM Line Tx IPG Reserved - AQ_MsmLineTxIpgControlRegister_HHD.u1.bits_1.msmLineTxIpgReserved - - - - Value always 0, writes ignored - */ - unsigned int msmLineTxIpgReserved : 16; /* 1E.9023.F:0 */ - /* Value always 0, writes ignored */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineTxIpgControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Tx Good Frames Counter Register: 1E.9040 */ -/* MSM Line Tx Good Frames Counter Register: 1E.9040 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Good Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9040.F:0 ROS MSM Line Tx Good Frames Counter 0 [F:0] - AQ_MsmLineTxGoodFramesCounterRegister_HHD.u0.bits_0.msmLineTxGoodFramesCounter_0 - - Default = 0x0000 - - Tx good frame counter bits 15:0 - - Notes: - Count of frames transmitted without error (Including pause frames). */ - unsigned int msmLineTxGoodFramesCounter_0 : 16; /* 1E.9040.F:0 ROS Default = 0x0000 */ - /* Tx good frame counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Good Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9041.F:0 ROS MSM Line Tx Good Frames Counter 1 [F:0] - AQ_MsmLineTxGoodFramesCounterRegister_HHD.u1.bits_1.msmLineTxGoodFramesCounter_1 - - Default = 0x0000 - - Tx good frame counter bits 31:16 - - - Notes: - Count of frames transmitted without error (Including pause frames). */ - unsigned int msmLineTxGoodFramesCounter_1 : 16; /* 1E.9041.F:0 ROS Default = 0x0000 */ - /* Tx good frame counter bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineTxGoodFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Rx Good Frames Counter Register: 1E.9044 */ -/* MSM Line Rx Good Frames Counter Register: 1E.9044 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Good Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9044.F:0 ROS MSM Line Rx Good Frames Counter 0 [F:0] - AQ_MsmLineRxGoodFramesCounterRegister_HHD.u0.bits_0.msmLineRxGoodFramesCounter_0 - - Default = 0x0000 - - Rx good frame counter bits 15:0 - - Notes: - Count of frames received without error (Including pause frames). */ - unsigned int msmLineRxGoodFramesCounter_0 : 16; /* 1E.9044.F:0 ROS Default = 0x0000 */ - /* Rx good frame counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Good Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9045.F:0 ROS MSM Line Rx Good Frames Counter 1 [F:0] - AQ_MsmLineRxGoodFramesCounterRegister_HHD.u1.bits_1.msmLineRxGoodFramesCounter_1 - - Default = 0x0000 - - Rx good frame counter bits 31:16 - - Notes: - Count of frames received without error (Including pause frames). */ - unsigned int msmLineRxGoodFramesCounter_1 : 16; /* 1E.9045.F:0 ROS Default = 0x0000 */ - /* Rx good frame counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineRxGoodFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Rx FCS Errors Counter Register: 1E.9048 */ -/* MSM Line Rx FCS Errors Counter Register: 1E.9048 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Rx FCS Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.9048.F:0 ROS MSM Line FCS Error Counter 0 [F:0] - AQ_MsmLineRxFcsErrorsCounterRegister_HHD.u0.bits_0.msmLineFcsErrorCounter_0 - - Default = 0x0000 - - Frame check sequence error counter bits 15:0 - - Notes: - Count of frames for which a CRC-32 Error is detected but the frame is otherwise of correct length. */ - unsigned int msmLineFcsErrorCounter_0 : 16; /* 1E.9048.F:0 ROS Default = 0x0000 */ - /* Frame check sequence error counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Rx FCS Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.9049.F:0 ROS MSM Line FCS Error Counter 1 [F:0] - AQ_MsmLineRxFcsErrorsCounterRegister_HHD.u1.bits_1.msmLineFcsErrorCounter_1 - - Default = 0x0000 - - Frame check sequence error counter bits 31:16 - - Notes: - Count of frames for which a CRC-32 Error is detected but the frame is otherwise of correct length. */ - unsigned int msmLineFcsErrorCounter_1 : 16; /* 1E.9049.F:0 ROS Default = 0x0000 */ - /* Frame check sequence error counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineRxFcsErrorsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Rx Alignment Errors Counter Register: 1E.904C */ -/* MSM Line Rx Alignment Errors Counter Register: 1E.904C */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Alignment Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.904C.F:0 ROS MSM Line Alignment Error Counter 0 [F:0] - AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD.u0.bits_0.msmLineAlignmentErrorCounter_0 - - Default = 0x0000 - - Alignment error counter bits 15:0 - - Notes: - Count of frames received with an alignment error. */ - unsigned int msmLineAlignmentErrorCounter_0 : 16; /* 1E.904C.F:0 ROS Default = 0x0000 */ - /* Alignment error counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Alignment Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.904D.F:0 ROS MSM Line Alignment Error Counter 1 [F:0] - AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD.u1.bits_1.msmLineAlignmentErrorCounter_1 - - Default = 0x0000 - - Alignment error counter bits 31:16 - - Notes: - Count of frames received with an alignment error. */ - unsigned int msmLineAlignmentErrorCounter_1 : 16; /* 1E.904D.F:0 ROS Default = 0x0000 */ - /* Alignment error counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Tx Pause Frames Counter Register: 1E.9050 */ -/* MSM Line Tx Pause Frames Counter Register: 1E.9050 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Pause Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9050.F:0 ROS MSM Line Tx Pause Frames Counter 0 [F:0] - AQ_MsmLineTxPauseFramesCounterRegister_HHD.u0.bits_0.msmLineTxPauseFramesCounter_0 - - Default = 0x0000 - - Tx pause frame counter bits 15:0 - - Notes: - Valid pause frames transmitted. */ - unsigned int msmLineTxPauseFramesCounter_0 : 16; /* 1E.9050.F:0 ROS Default = 0x0000 */ - /* Tx pause frame counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Pause Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9051.F:0 ROS MSM Line Tx Pause Frames Counter 1 [F:0] - AQ_MsmLineTxPauseFramesCounterRegister_HHD.u1.bits_1.msmLineTxPauseFramesCounter_1 - - Default = 0x0000 - - Tx pause frame counter bits 31:16 - - - Notes: - Valid pause frames transmitted. */ - unsigned int msmLineTxPauseFramesCounter_1 : 16; /* 1E.9051.F:0 ROS Default = 0x0000 */ - /* Tx pause frame counter bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineTxPauseFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Rx Pause Frames Counter Register: 1E.9054 */ -/* MSM Line Rx Pause Frames Counter Register: 1E.9054 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Pause Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9054.F:0 ROS MSM Line Rx Pause Frames Counter 0 [F:0] - AQ_MsmLineRxPauseFramesCounterRegister_HHD.u0.bits_0.msmLineRxPauseFramesCounter_0 - - Default = 0x0000 - - Rx pause frame counter bits 15:0 - - Notes: - Valid pause frames received. */ - unsigned int msmLineRxPauseFramesCounter_0 : 16; /* 1E.9054.F:0 ROS Default = 0x0000 */ - /* Rx pause frame counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Pause Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9055.F:0 ROS MSM Line Rx Pause Frames Counter 1 [F:0] - AQ_MsmLineRxPauseFramesCounterRegister_HHD.u1.bits_1.msmLineRxPauseFramesCounter_1 - - Default = 0x0000 - - Rx pause frame counter bits 31:16 - - Notes: - Valid pause frames received. */ - unsigned int msmLineRxPauseFramesCounter_1 : 16; /* 1E.9055.F:0 ROS Default = 0x0000 */ - /* Rx pause frame counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineRxPauseFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Rx Too Long Errors Counter Register: 1E.9058 */ -/* MSM Line Rx Too Long Errors Counter Register: 1E.9058 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Too Long Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.9058.F:0 ROS MSM Line Rx Too Long Errors Counter 0 [F:0] - AQ_MsmLineRxTooLongErrorsCounterRegister_HHD.u0.bits_0.msmLineRxTooLongErrorsCounter_0 - - Default = 0x0000 - - Too-long errors counter bits 15:0 - - Notes: - Frame received exceeded the maximum length programmed with register FRM_LGTH. */ - unsigned int msmLineRxTooLongErrorsCounter_0 : 16; /* 1E.9058.F:0 ROS Default = 0x0000 */ - /* Too-long errors counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Too Long Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.9059.F:0 ROS MSM Line Rx Too Long Errors Counter 1 [F:0] - AQ_MsmLineRxTooLongErrorsCounterRegister_HHD.u1.bits_1.msmLineRxTooLongErrorsCounter_1 - - Default = 0x0000 - - Too-long errors counter bits 31:16 - - Notes: - Frame received exceeded the maximum length programmed with register FRM_LGTH. */ - unsigned int msmLineRxTooLongErrorsCounter_1 : 16; /* 1E.9059.F:0 ROS Default = 0x0000 */ - /* Too-long errors counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineRxTooLongErrorsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Rx In Range Length Errors Counter Register: 1E.905C */ -/* MSM Line Rx In Range Length Errors Counter Register: 1E.905C */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Rx In Range Length Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.905C.F:0 ROS MSM Line Rx In Range Length Errors Counter 0 [F:0] - AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD.u0.bits_0.msmLineRxInRangeLengthErrorsCounter_0 - - Default = 0x0000 - - In-range-length errors counter bits 15:0 - - Notes: - A count of frames with a length/type field value between 46 (VLAN: 42) and less than 0x0600, that does not match the number of payload data octets received. Should count also if length/type field is less than 46 (VLAN: 42) and the frame is longer than 64 bytes. */ - unsigned int msmLineRxInRangeLengthErrorsCounter_0 : 16; /* 1E.905C.F:0 ROS Default = 0x0000 */ - /* In-range-length errors counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Rx In Range Length Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.905D.F:0 ROS MSM Line Rx In Range Length Errors Counter 1 [F:0] - AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD.u1.bits_1.msmLineRxInRangeLengthErrorsCounter_1 - - Default = 0x0000 - - In-range-length errors counter bits 31:16 - - Notes: - A count of frames with a length/type field value between 46 (VLAN: 42) and less than 0x0600, that does not match the number of payload data octets received. Should count also if length/type field is less than 46 (VLAN: 42) and the frame is longer than 64 bytes. */ - unsigned int msmLineRxInRangeLengthErrorsCounter_1 : 16; /* 1E.905D.F:0 ROS Default = 0x0000 */ - /* In-range-length errors counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Tx VLAN Frames Counter Register: 1E.9060 */ -/* MSM Line Tx VLAN Frames Counter Register: 1E.9060 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Tx VLAN Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9060.F:0 ROS MSM Line Tx VLAN Frames Counter 0 [F:0] - AQ_MsmLineTxVlanFramesCounterRegister_HHD.u0.bits_0.msmLineTxVlanFramesCounter_0 - - Default = 0x0000 - - Tx VLAN frames counter bits 15:0 - - Notes: - Valid VLAN tagged frames transmitted. */ - unsigned int msmLineTxVlanFramesCounter_0 : 16; /* 1E.9060.F:0 ROS Default = 0x0000 */ - /* Tx VLAN frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Tx VLAN Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9061.F:0 ROS MSM Line Tx VLAN Frames Counter 1 [F:0] - AQ_MsmLineTxVlanFramesCounterRegister_HHD.u1.bits_1.msmLineTxVlanFramesCounter_1 - - Default = 0x0000 - - Tx VLAN frames counter bits 31:16 - - Notes: - Valid VLAN tagged frames transmitted. */ - unsigned int msmLineTxVlanFramesCounter_1 : 16; /* 1E.9061.F:0 ROS Default = 0x0000 */ - /* Tx VLAN frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineTxVlanFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Rx VLAN Frames Counter Register: 1E.9064 */ -/* MSM Line Rx VLAN Frames Counter Register: 1E.9064 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Rx VLAN Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9064.F:0 ROS MSM Line Rx VLAN Frames Counter 0 [F:0] - AQ_MsmLineRxVlanFramesCounterRegister_HHD.u0.bits_0.msmLineRxVlanFramesCounter_0 - - Default = 0x0000 - - Rx VLAN frames counter bits 15:0 - - Notes: - Valid VLAN tagged frames received. */ - unsigned int msmLineRxVlanFramesCounter_0 : 16; /* 1E.9064.F:0 ROS Default = 0x0000 */ - /* Rx VLAN frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Rx VLAN Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9065.F:0 ROS MSM Line Rx VLAN Frames Counter 1 [F:0] - AQ_MsmLineRxVlanFramesCounterRegister_HHD.u1.bits_1.msmLineRxVlanFramesCounter_1 - - Default = 0x0000 - - Rx VLAN frames counter bits 31:16 - - Notes: - Valid VLAN tagged frames received. */ - unsigned int msmLineRxVlanFramesCounter_1 : 16; /* 1E.9065.F:0 ROS Default = 0x0000 */ - /* Rx VLAN frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineRxVlanFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Tx Octets Counter Register: 1E.9068 */ -/* MSM Line Tx Octets Counter Register: 1E.9068 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Octets Counter Register */ - union - { - struct - { - /*! \brief 1E.9068.F:0 ROS MSM Line Tx Octets Counter 0 [F:0] - AQ_MsmLineTxOctetsCounterRegister_HHD.u0.bits_0.msmLineTxOctetsCounter_0 - - Default = 0x0000 - - Tx octets counter bits 15:0 - - Notes: - All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ - unsigned int msmLineTxOctetsCounter_0 : 16; /* 1E.9068.F:0 ROS Default = 0x0000 */ - /* Tx octets counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Octets Counter Register */ - union - { - struct - { - /*! \brief 1E.9069.F:0 ROS MSM Line Tx Octets Counter 1 [F:0] - AQ_MsmLineTxOctetsCounterRegister_HHD.u1.bits_1.msmLineTxOctetsCounter_1 - - Default = 0x0000 - - Tx octets counter bits 31:16 - - Notes: - All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ - unsigned int msmLineTxOctetsCounter_1 : 16; /* 1E.9069.F:0 ROS Default = 0x0000 */ - /* Tx octets counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of MSM Line Tx Octets Counter Register */ - union - { - struct - { - /*! \brief 1E.906A.F:0 ROS MSM Line Tx Octets Counter 2 [F:0] - AQ_MsmLineTxOctetsCounterRegister_HHD.u2.bits_2.msmLineTxOctetsCounter_2 - - Default = 0x0000 - - Tx octets counter bits 47:32 - - Notes: - All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ - unsigned int msmLineTxOctetsCounter_2 : 16; /* 1E.906A.F:0 ROS Default = 0x0000 */ - /* Tx octets counter bits 47:32 */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of MSM Line Tx Octets Counter Register */ - union - { - struct - { - /*! \brief 1E.906B.F:0 ROS MSM Line Tx Octets Counter 3 [F:0] - AQ_MsmLineTxOctetsCounterRegister_HHD.u3.bits_3.msmLineTxOctetsCounter_3 - - Default = 0x0000 - - Tx octets counter bits 63:48 - - Notes: - All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ - unsigned int msmLineTxOctetsCounter_3 : 16; /* 1E.906B.F:0 ROS Default = 0x0000 */ - /* Tx octets counter bits 63:48 */ - } bits_3; - uint16_t word_3; - } u3; -} AQ_MsmLineTxOctetsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Rx Octets Counter Register: 1E.906C */ -/* MSM Line Rx Octets Counter Register: 1E.906C */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Octets Counter Register */ - union - { - struct - { - /*! \brief 1E.906C.F:0 ROS MSM Line Rx Octets Counter 0 [F:0] - AQ_MsmLineRxOctetsCounterRegister_HHD.u0.bits_0.msmLineRxOctetsCounter_0 - - Default = 0x0000 - - Rx octets counter bits 15:0 - - Notes: - All octets received except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames received. */ - unsigned int msmLineRxOctetsCounter_0 : 16; /* 1E.906C.F:0 ROS Default = 0x0000 */ - /* Rx octets counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Octets Counter Register */ - union - { - struct - { - /*! \brief 1E.906D.F:0 ROS MSM Line Rx Octets Counter 1 [F:0] - AQ_MsmLineRxOctetsCounterRegister_HHD.u1.bits_1.msmLineRxOctetsCounter_1 - - Default = 0x0000 - - Rx octets counter bits 31:16 - - Notes: - All octets received except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames received. */ - unsigned int msmLineRxOctetsCounter_1 : 16; /* 1E.906D.F:0 ROS Default = 0x0000 */ - /* Rx octets counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineRxOctetsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Rx Unicast Frames Counter Register: 1E.9070 */ -/* MSM Line Rx Unicast Frames Counter Register: 1E.9070 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Unicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9070.F:0 ROS MSM Line Rx Unicast Frames Counter 0 [F:0] - AQ_MsmLineRxUnicastFramesCounterRegister_HHD.u0.bits_0.msmLineRxUnicastFramesCounter_0 - - Default = 0x0000 - - Rx unicast frames counter bits 15:0 - - Notes: - Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '0'. */ - unsigned int msmLineRxUnicastFramesCounter_0 : 16; /* 1E.9070.F:0 ROS Default = 0x0000 */ - /* Rx unicast frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Unicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9071.F:0 ROS MSM Line Rx Unicast Frames Counter 1 [F:0] - AQ_MsmLineRxUnicastFramesCounterRegister_HHD.u1.bits_1.msmLineRxUnicastFramesCounter_1 - - Default = 0x0000 - - Rx unicast frames counter bits 31:16 - - Notes: - Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '0'. */ - unsigned int msmLineRxUnicastFramesCounter_1 : 16; /* 1E.9071.F:0 ROS Default = 0x0000 */ - /* Rx unicast frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineRxUnicastFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Rx Multicast Frames Counter Register: 1E.9074 */ -/* MSM Line Rx Multicast Frames Counter Register: 1E.9074 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Multicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9074.F:0 ROS MSM Line Rx Multicast Frames Counter 0 [F:0] - AQ_MsmLineRxMulticastFramesCounterRegister_HHD.u0.bits_0.msmLineRxMulticastFramesCounter_0 - - Default = 0x0000 - - Rx multicast frames counter bits 15:0 - - Notes: - Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '1' but not the broadcast address (all bits set '1' ). Pause frames are not counted. */ - unsigned int msmLineRxMulticastFramesCounter_0 : 16; /* 1E.9074.F:0 ROS Default = 0x0000 */ - /* Rx multicast frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Multicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9075.F:0 ROS MSM Line Rx Multicast Frames Counter 1 [F:0] - AQ_MsmLineRxMulticastFramesCounterRegister_HHD.u1.bits_1.msmLineRxMulticastFramesCounter_1 - - Default = 0x0000 - - Rx multicast frames counter bits 31:16 - - Notes: - Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '1' but not the broadcast address (all bits set '1' ). Pause frames are not counted. */ - unsigned int msmLineRxMulticastFramesCounter_1 : 16; /* 1E.9075.F:0 ROS Default = 0x0000 */ - /* Rx multicast frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineRxMulticastFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Rx Broadcast Frames Counter Register: 1E.9078 */ -/* MSM Line Rx Broadcast Frames Counter Register: 1E.9078 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Broadcast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9078.F:0 ROS MSM Line Rx Broadcast Frames Counter 0 [F:0] - AQ_MsmLineRxBroadcastFramesCounterRegister_HHD.u0.bits_0.msmLineRxBroadcastFramesCounter_0 - - Default = 0x0000 - - Rx broadcast frames counter bits 15:0 - - Notes: - Incremented with each valid frame received on the receive FIFO interface (FIFO) and all bits of the destination address were set '1'. */ - unsigned int msmLineRxBroadcastFramesCounter_0 : 16; /* 1E.9078.F:0 ROS Default = 0x0000 */ - /* Rx broadcast frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Broadcast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9079.F:0 ROS MSM Line Rx Broadcast Frames Counter 1 [F:0] - AQ_MsmLineRxBroadcastFramesCounterRegister_HHD.u1.bits_1.msmLineRxBroadcastFramesCounter_1 - - Default = 0x0000 - - Rx broadcast frames counter bits 31:16 - - Notes: - Incremented with each valid frame received on the receive FIFO interface (FIFO) and all bits of the destination address were set '1'. */ - unsigned int msmLineRxBroadcastFramesCounter_1 : 16; /* 1E.9079.F:0 ROS Default = 0x0000 */ - /* Rx broadcast frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineRxBroadcastFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Tx Errors Counter Register: 1E.907C */ -/* MSM Line Tx Errors Counter Register: 1E.907C */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.907C.F:0 ROS MSM Line Tx Errors Counter 0 [F:0] - AQ_MsmLineTxErrorsCounterRegister_HHD.u0.bits_0.msmLineTxErrorsCounter_0 - - Default = 0x0000 - - Rx errors counter bits 15:0 - - Notes: - Number of frames transmitted with error: - - FIFO Overflow Errors - - FIFO Underflow Errors */ - unsigned int msmLineTxErrorsCounter_0 : 16; /* 1E.907C.F:0 ROS Default = 0x0000 */ - /* Rx errors counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.907D.F:0 ROS MSM Line Tx Errors Counter 1 [F:0] - AQ_MsmLineTxErrorsCounterRegister_HHD.u1.bits_1.msmLineTxErrorsCounter_1 - - Default = 0x0000 - - Tx errors counter bits 31:16 - - Notes: - Number of frames transmitted with error: - - FIFO Overflow Errors - - FIFO Underflow Errors */ - unsigned int msmLineTxErrorsCounter_1 : 16; /* 1E.907D.F:0 ROS Default = 0x0000 */ - /* Tx errors counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineTxErrorsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Tx Unicast Frames Counter Register: 1E.9084 */ -/* MSM Line Tx Unicast Frames Counter Register: 1E.9084 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Unicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9084.F:0 ROS MSM Line Tx Unicast Frames Counter 0 [F:0] - AQ_MsmLineTxUnicastFramesCounterRegister_HHD.u0.bits_0.msmLineTxUnicastFramesCounter_0 - - Default = 0x0000 - - Tx unicast frames counter bits 15:0 - - Notes: - Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '0'. */ - unsigned int msmLineTxUnicastFramesCounter_0 : 16; /* 1E.9084.F:0 ROS Default = 0x0000 */ - /* Tx unicast frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Unicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9085.F:0 ROS MSM Line Tx Unicast Frames Counter 1 [F:0] - AQ_MsmLineTxUnicastFramesCounterRegister_HHD.u1.bits_1.msmLineTxUnicastFramesCounter_1 - - Default = 0x0000 - - Tx unicast frames counter bits 31:16 - - Notes: - Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '0'. */ - unsigned int msmLineTxUnicastFramesCounter_1 : 16; /* 1E.9085.F:0 ROS Default = 0x0000 */ - /* Tx unicast frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineTxUnicastFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Tx Multicast Frames Counter Register: 1E.9088 */ -/* MSM Line Tx Multicast Frames Counter Register: 1E.9088 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Multicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9088.F:0 ROS MSM Line Tx Multicast Frames Counter 0 [F:0] - AQ_MsmLineTxMulticastFramesCounterRegister_HHD.u0.bits_0.msmLineTxMulticastFramesCounter_0 - - Default = 0x0000 - - Tx multicast frames counter bits 15:0 - - Notes: - Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '1' but not the broadcast address (all bits '1'). */ - unsigned int msmLineTxMulticastFramesCounter_0 : 16; /* 1E.9088.F:0 ROS Default = 0x0000 */ - /* Tx multicast frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Multicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9089.F:0 ROS MSM Line Tx Multicast Frames Counter 1 [F:0] - AQ_MsmLineTxMulticastFramesCounterRegister_HHD.u1.bits_1.msmLineTxMulticastFramesCounter_1 - - Default = 0x0000 - - Tx multicast frames counter bits 31:16 - - Notes: - Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '1' but not the broadcast address (all bits '1'). */ - unsigned int msmLineTxMulticastFramesCounter_1 : 16; /* 1E.9089.F:0 ROS Default = 0x0000 */ - /* Tx multicast frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineTxMulticastFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Tx Broadcast Frames Counter Register: 1E.908C */ -/* MSM Line Tx Broadcast Frames Counter Register: 1E.908C */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Broadcast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.908C.F:0 ROS MSM Line Tx Broadcast Frames Counter 0 [F:0] - AQ_MsmLineTxBroadcastFramesCounterRegister_HHD.u0.bits_0.msmLineTxBroadcastFramesCounter_0 - - Default = 0x0000 - - Tx broadcast frames counter bits 15:0 - - Notes: - Incremented with each frame written to the FIFO interface and all bits of the destination address set to '1'. */ - unsigned int msmLineTxBroadcastFramesCounter_0 : 16; /* 1E.908C.F:0 ROS Default = 0x0000 */ - /* Tx broadcast frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Broadcast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.908D.F:0 ROS MSM Line Tx Broadcast Frames Counter 1 [F:0] - AQ_MsmLineTxBroadcastFramesCounterRegister_HHD.u1.bits_1.msmLineTxBroadcastFramesCounter_1 - - Default = 0x0000 - - Tx broadcast frames counter bits 31:16 - - Notes: - Incremented with each frame written to the FIFO interface and all bits of the destination address set to '1'. */ - unsigned int msmLineTxBroadcastFramesCounter_1 : 16; /* 1E.908D.F:0 ROS Default = 0x0000 */ - /* Tx broadcast frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineTxBroadcastFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Rx Errors Counter Register: 1E.90C8 */ -/* MSM Line Rx Errors Counter Register: 1E.90C8 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.90C8.F:0 ROS MSM Line Rx Errors Counter 0 [F:0] - AQ_MsmLineRxErrorsCounterRegister_HHD.u0.bits_0.msmLineRxErrorsCounter_0 - - Default = 0x0000 - - Rx errors counter bits 15:0 - - Notes: - Number of frames received with error: - - FIFO Overflow Errors - - CRC Errors - - Payload Length Errors - - Jabber and Oversized Errors - - Alignment Errors - - The dedicated Error Code (0xfe, not a code error) was received */ - unsigned int msmLineRxErrorsCounter_0 : 16; /* 1E.90C8.F:0 ROS Default = 0x0000 */ - /* Rx errors counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.90C9.F:0 ROS MSM Line Rx Errors Counter 1 [F:0] - AQ_MsmLineRxErrorsCounterRegister_HHD.u1.bits_1.msmLineRxErrorsCounter_1 - - Default = 0x0000 - - Rx errors counter bits 31:16 - - Notes: - Number of frames received with error: - - FIFO Overflow Errors - - CRC Errors - - Payload Length Errors - - Jabber and Oversized Errors - - Alignment Errors - - The dedicated Error Code (0xfe, not a code error) was received */ - unsigned int msmLineRxErrorsCounter_1 : 16; /* 1E.90C9.F:0 ROS Default = 0x0000 */ - /* Rx errors counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineRxErrorsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Control: 1E.C000 */ -/* Global Control: 1E.C000 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Control */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Control */ - union - { - struct - { - /*! \brief 1E.C001.F R/W uP Reset - AQ_GlobalControl_HHD.u1.bits_1.upReset - - Default = 0x0 - - 1 = Reset - - - Notes: - Resets the uP and the PIF master and slave bus. Will be active for a minimum of 100 microseconds. */ - unsigned int upReset : 1; /* 1E.C001.F R/W Default = 0x0 */ - /* 1 = Reset - */ - unsigned int reserved0 : 8; - /*! \brief 1E.C001.6 R/W uP Run Stall Override - AQ_GlobalControl_HHD.u1.bits_1.upRunStallOverride - - Default = 0x0 - - 0 = uP Run Stall from "MDIO Boot Load" pin. - 1 = uP Run Stall from See MCP Run Stall bit - - - - Notes: - This bit selects the uP Run Stall from either the "MDIO Boot Load" pin or the See MCP Run Stall bit. Pin no longer brought out as deprecated. */ - unsigned int upRunStallOverride : 1; /* 1E.C001.6 R/W Default = 0x0 */ - /* 0 = uP Run Stall from "MDIO Boot Load" pin. - 1 = uP Run Stall from See MCP Run Stall bit - - */ - unsigned int reserved1 : 5; - /*! \brief 1E.C001.0 R/W uP Run Stall - AQ_GlobalControl_HHD.u1.bits_1.upRunStall - - Default = 0x0 - - 1 = uP Run Stall - 0 = uP normal mode - - - Notes: - Deactivates the uP. */ - unsigned int upRunStall : 1; /* 1E.C001.0 R/W Default = 0x0 */ - /* 1 = uP Run Stall - 0 = uP normal mode - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_GlobalControl_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Reset Control: 1E.C006 */ -/* Global Reset Control: 1E.C006 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Reset Control */ - union - { - struct - { - unsigned int reserved0 : 1; - /*! \brief 1E.C006.E R/WPD Global MMD Reset Disable - AQ_GlobalResetControl_HHD.u0.bits_0.globalMMD_ResetDisable - - Provisionable Default = 0x0 - - 1 = Disable the S/W reset to the Global MMD registers - 0 = Enable the S/W reset to the Global MMD registers - - - Notes: - Setting this bit prevents a Global S/W reset or Global S/W reset from resetting the Global MMD registers */ - unsigned int globalMMD_ResetDisable : 1; /* 1E.C006.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Disable the S/W reset to the Global MMD registers - 0 = Enable the S/W reset to the Global MMD registers - */ - unsigned int reserved1 : 14; - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalResetControl_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Diagnostic Provisioning: 1E.C400 */ -/* Global Diagnostic Provisioning: 1E.C400 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Diagnostic Provisioning */ - union - { - struct - { - /*! \brief 1E.C400.F R/WPD Enable Diagnostics - AQ_GlobalDiagnosticProvisioning_HHD.u0.bits_0.enableDiagnostics - - Provisionable Default = 0x1 - - 1 = Chip performs diagnostics on power-up - */ - unsigned int enableDiagnostics : 1; /* 1E.C400.F R/WPD Provisionable Default = 0x1 */ - /* 1 = Chip performs diagnostics on power-up */ - unsigned int reserved0 : 15; - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalDiagnosticProvisioning_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Thermal Provisioning: 1E.C420 */ -/* Global Thermal Provisioning: 1E.C420 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Thermal Provisioning */ - union - { - struct - { - /*! \brief 1E.C420.F:0 R/WPD Reserved 0 [F:0] - AQ_GlobalThermalProvisioning_HHD.u0.bits_0.reserved_0 - - Provisionable Default = 0x0000 - - Internal reserved - do not modify - - */ - unsigned int reserved_0 : 16; /* 1E.C420.F:0 R/WPD Provisionable Default = 0x0000 */ - /* Internal reserved - do not modify - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Thermal Provisioning */ - union - { - struct - { - /*! \brief 1E.C421.F:0 R/WPD High Temp Failure Threshold [F:0] - AQ_GlobalThermalProvisioning_HHD.u1.bits_1.highTempFailureThreshold - - Provisionable Default = 0x4600 - - [F:0] of high temperature failure threshold - - Notes: - 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 70 degreesC. - - In XENPAK mode, F/W will use the XENPAK register 1.A000 - 1.A001: instead of this register. - - NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ - unsigned int highTempFailureThreshold : 16; /* 1E.C421.F:0 R/WPD Provisionable Default = 0x4600 */ - /* [F:0] of high temperature failure threshold */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global Thermal Provisioning */ - union - { - struct - { - /*! \brief 1E.C422.F:0 R/WPD Low Temp Failure Threshold [F:0] - AQ_GlobalThermalProvisioning_HHD.u2.bits_2.lowTempFailureThreshold - - Provisionable Default = 0x0000 - - [F:0] of low temperature failure threshold - - Notes: - 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 0 degreesC. - - In XENPAK mode, F/W will use the XENPAK register 1.A002 - 1.A003: instead of this register. - - NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ - unsigned int lowTempFailureThreshold : 16; /* 1E.C422.F:0 R/WPD Provisionable Default = 0x0000 */ - /* [F:0] of low temperature failure threshold */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global Thermal Provisioning */ - union - { - struct - { - /*! \brief 1E.C423.F:0 R/WPD High Temp Warning Threshold [F:0] - AQ_GlobalThermalProvisioning_HHD.u3.bits_3.highTempWarningThreshold - - Provisionable Default = 0x3C00 - - [F:0] of high temperature warning threshold - - Notes: - 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD008. Default is 60 degreesC. - - In XENPAK mode, F/W will use the XENPAK register 1.A004 - 1.A005: instead of this register. - - NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ - unsigned int highTempWarningThreshold : 16; /* 1E.C423.F:0 R/WPD Provisionable Default = 0x3C00 */ - /* [F:0] of high temperature warning threshold */ - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of Global Thermal Provisioning */ - union - { - struct - { - /*! \brief 1E.C424.F:0 R/WPD Low Temp Warning Threshold [F:0] - AQ_GlobalThermalProvisioning_HHD.u4.bits_4.lowTempWarningThreshold - - Provisionable Default = 0x0A00 - - [F:0] of low temperature warning threshold - - Notes: - 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 10 degreesC. - - In XENPAK mode, F/W will use the XENPAK register 1.A006 - 1.A007: instead of this register. - - NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ - unsigned int lowTempWarningThreshold : 16; /* 1E.C424.F:0 R/WPD Provisionable Default = 0x0A00 */ - /* [F:0] of low temperature warning threshold */ - } bits_4; - uint16_t word_4; - } u4; -} AQ_GlobalThermalProvisioning_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global LED Provisioning: 1E.C430 */ -/* Global LED Provisioning: 1E.C430 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global LED Provisioning */ - union - { - struct - { - unsigned int reserved0 : 2; - /*! \brief 1E.C430.D:9 R/WPD Reserved Provisioning C430 [4:0] - AQ_GlobalLedProvisioning_HHD.u0.bits_0.reservedProvisioningC430 - - Provisionable Default = 0x00 - - Reserved for future use - */ - unsigned int reservedProvisioningC430 : 5; /* 1E.C430.D:9 R/WPD Provisionable Default = 0x00 */ - /* Reserved for future use */ - /*! \brief 1E.C430.8 R/WPD LED #0 Manual Set - AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0ManualSet - - Provisionable Default = 0x0 - - 1 = LED On - - */ - unsigned int led_0ManualSet : 1; /* 1E.C430.8 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED On - */ - /*! \brief 1E.C430.7 R/WPD LED #0 10 Gb/s Link Established - AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0_10Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 10 Gb/s - - */ - unsigned int led_0_10Gb_sLinkEstablished : 1; /* 1E.C430.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 10 Gb/s - */ - /*! \brief 1E.C430.6 R/WPD LED #0 1 Gb/s Link Established - AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0_1Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 1 Gb/s - - */ - unsigned int led_0_1Gb_sLinkEstablished : 1; /* 1E.C430.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 1 Gb/s - */ - /*! \brief 1E.C430.5 R/WPD LED #0 100 Mb/s Link Established - AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0_100Mb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 100 Mb/s. - - */ - unsigned int led_0_100Mb_sLinkEstablished : 1; /* 1E.C430.5 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 100 Mb/s. - */ - /*! \brief 1E.C430.4 R/WPD LED #0 Connecting - AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0Connecting - - Provisionable Default = 0x0 - - 1 = LED is on when attempting to connect. - - */ - unsigned int led_0Connecting : 1; /* 1E.C430.4 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when attempting to connect. - */ - /*! \brief 1E.C430.3 R/WPD LED #0 Receive Activity - AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0ReceiveActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on receive activity - - */ - unsigned int led_0ReceiveActivity : 1; /* 1E.C430.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on receive activity - */ - /*! \brief 1E.C430.2 R/WPD LED #0 Transmit Activity - AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0TransmitActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on transmit activity - - */ - unsigned int led_0TransmitActivity : 1; /* 1E.C430.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on transmit activity - */ - /*! \brief 1E.C430.1:0 R/WPD LED #0 Activity Stretch [1:0] - AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0ActivityStretch - - Provisionable Default = 0x3 - - [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - - */ - unsigned int led_0ActivityStretch : 2; /* 1E.C430.1:0 R/WPD Provisionable Default = 0x3 */ - /* [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global LED Provisioning */ - union - { - struct - { - unsigned int reserved0 : 2; - /*! \brief 1E.C431.D:9 R/WPD Reserved Provisioning C431 [4:0] - AQ_GlobalLedProvisioning_HHD.u1.bits_1.reservedProvisioningC431 - - Provisionable Default = 0x00 - - Reserved for future use - */ - unsigned int reservedProvisioningC431 : 5; /* 1E.C431.D:9 R/WPD Provisionable Default = 0x00 */ - /* Reserved for future use */ - /*! \brief 1E.C431.8 R/WPD LED #1 Manual Set - AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1ManualSet - - Provisionable Default = 0x0 - - 1 = LED On - - */ - unsigned int led_1ManualSet : 1; /* 1E.C431.8 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED On - */ - /*! \brief 1E.C431.7 R/WPD LED #1 10 Gb/s Link Established - AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1_10Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 10 Gb/s - - */ - unsigned int led_1_10Gb_sLinkEstablished : 1; /* 1E.C431.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 10 Gb/s - */ - /*! \brief 1E.C431.6 R/WPD LED #1 1 Gb/s Link Established - AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1_1Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 1 Gb/s - - */ - unsigned int led_1_1Gb_sLinkEstablished : 1; /* 1E.C431.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 1 Gb/s - */ - /*! \brief 1E.C431.5 R/WPD LED #1 100 Mb/s Link Established - AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1_100Mb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 100 Mb/s. - - */ - unsigned int led_1_100Mb_sLinkEstablished : 1; /* 1E.C431.5 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 100 Mb/s. - */ - /*! \brief 1E.C431.4 R/WPD LED #1 Connecting - AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1Connecting - - Provisionable Default = 0x0 - - 1 = LED is on when attempting to connect. - - */ - unsigned int led_1Connecting : 1; /* 1E.C431.4 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when attempting to connect. - */ - /*! \brief 1E.C431.3 R/WPD LED #1 Receive Activity - AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1ReceiveActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on receive activity - - */ - unsigned int led_1ReceiveActivity : 1; /* 1E.C431.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on receive activity - */ - /*! \brief 1E.C431.2 R/WPD LED #1 Transmit Activity - AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1TransmitActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on transmit activity - - */ - unsigned int led_1TransmitActivity : 1; /* 1E.C431.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on transmit activity - */ - /*! \brief 1E.C431.1:0 R/WPD LED #1 Activity Stretch [1:0] - AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1ActivityStretch - - Provisionable Default = 0x3 - - [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - - */ - unsigned int led_1ActivityStretch : 2; /* 1E.C431.1:0 R/WPD Provisionable Default = 0x3 */ - /* [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global LED Provisioning */ - union - { - struct - { - unsigned int reserved0 : 2; - /*! \brief 1E.C432.D:9 R/WPD Reserved Provisioning C432 [4:0] - AQ_GlobalLedProvisioning_HHD.u2.bits_2.reservedProvisioningC432 - - Provisionable Default = 0x00 - - Reserved for future use - */ - unsigned int reservedProvisioningC432 : 5; /* 1E.C432.D:9 R/WPD Provisionable Default = 0x00 */ - /* Reserved for future use */ - /*! \brief 1E.C432.8 R/WPD LED #2 Manual Set - AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2ManualSet - - Provisionable Default = 0x0 - - 1 = LED On - - */ - unsigned int led_2ManualSet : 1; /* 1E.C432.8 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED On - */ - /*! \brief 1E.C432.7 R/WPD LED #2 10 Gb/s Link Established - AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2_10Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 10 Gb/s - - */ - unsigned int led_2_10Gb_sLinkEstablished : 1; /* 1E.C432.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 10 Gb/s - */ - /*! \brief 1E.C432.6 R/WPD LED #2 1 Gb/s Link Established - AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2_1Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 1 Gb/s - - */ - unsigned int led_2_1Gb_sLinkEstablished : 1; /* 1E.C432.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 1 Gb/s - */ - /*! \brief 1E.C432.5 R/WPD LED #2 100 Mb/s Link Established - AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2_100Mb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 100 Mb/s. - */ - unsigned int led_2_100Mb_sLinkEstablished : 1; /* 1E.C432.5 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 100 Mb/s. */ - /*! \brief 1E.C432.4 R/WPD LED #2 Connecting - AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2Connecting - - Provisionable Default = 0x0 - - 1 = LED is on when attempting to connect. - - */ - unsigned int led_2Connecting : 1; /* 1E.C432.4 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when attempting to connect. - */ - /*! \brief 1E.C432.3 R/WPD LED #2 Receive Activity - AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2ReceiveActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on receive activity - - */ - unsigned int led_2ReceiveActivity : 1; /* 1E.C432.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on receive activity - */ - /*! \brief 1E.C432.2 R/WPD LED #2 Transmit Activity - AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2TransmitActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on transmit activity - - */ - unsigned int led_2TransmitActivity : 1; /* 1E.C432.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on transmit activity - */ - /*! \brief 1E.C432.1:0 R/WPD LED #2 Activity Stretch [1:0] - AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2ActivityStretch - - Provisionable Default = 0x3 - - [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - - */ - unsigned int led_2ActivityStretch : 2; /* 1E.C432.1:0 R/WPD Provisionable Default = 0x3 */ - /* [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global LED Provisioning */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of Global LED Provisioning */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_4; - uint16_t word_4; - } u4; - /*! \brief Union for bit and word level access of word 5 of Global LED Provisioning */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_5; - uint16_t word_5; - } u5; - /*! \brief Union for bit and word level access of word 6 of Global LED Provisioning */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_6; - uint16_t word_6; - } u6; - /*! \brief Union for bit and word level access of word 7 of Global LED Provisioning */ - union - { - struct - { - unsigned int reserved0 : 15; - /*! \brief 1E.C437.0 R/WPD LED Operation Mode - AQ_GlobalLedProvisioning_HHD.u7.bits_7.ledOperationMode - - Provisionable Default = 0x0 - - 1 = LED link activity in Mode #2 - 0 = LED link activity in Aquantia classic mode - - - Notes: - When set to 1, the LED blinking rate is based on Mode #2 algorithm. When set to 0, the LED blinking rate is based on the classic Aquantia algorithm. */ - unsigned int ledOperationMode : 1; /* 1E.C437.0 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED link activity in Mode #2 - 0 = LED link activity in Aquantia classic mode - */ - } bits_7; - uint16_t word_7; - } u7; - /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ - union - { - struct - { - unsigned int reserved : 16; - } bits_8; - uint16_t word_8; - } u8; - /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ - union - { - struct - { - unsigned int reserved : 16; - } bits_9; - uint16_t word_9; - } u9; - /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ - union - { - struct - { - unsigned int reserved : 16; - } bits_10; - uint16_t word_10; - } u10; - /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ - union - { - struct - { - unsigned int reserved : 16; - } bits_11; - uint16_t word_11; - } u11; - /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ - union - { - struct - { - unsigned int reserved : 16; - } bits_12; - uint16_t word_12; - } u12; - /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ - union - { - struct - { - unsigned int reserved : 16; - } bits_13; - uint16_t word_13; - } u13; - /*! \brief Union for bit and word level access of word 14 of Global LED Provisioning */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_14; - uint16_t word_14; - } u14; -} AQ_GlobalLedProvisioning_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global General Provisioning: 1E.C440 */ -/* Global General Provisioning: 1E.C440 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global General Provisioning */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global General Provisioning */ - union - { - struct - { - unsigned int reserved0 : 1; - /*! \brief 1E.C441.E R/WPD MDIO Broadcast Mode Enable - AQ_GlobalGeneralProvisioning_HHD.u1.bits_1.mdioBroadcastModeEnable - - Provisionable Default = 0x0 - - 1 = Enable broadcast on address set in 1E.C446 - 0 = Disable broadcast on n address set in 1E.C446 - - - Notes: - When enabled, writes and load MMD address opcodes are supported. Read opcodes are ignored. */ - unsigned int mdioBroadcastModeEnable : 1; /* 1E.C441.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable broadcast on address set in 1E.C446 - 0 = Disable broadcast on n address set in 1E.C446 - */ - /*! \brief 1E.C441.D R/WPD MDIO Read MSW First Enable - AQ_GlobalGeneralProvisioning_HHD.u1.bits_1.mdioReadMSW_FirstEnable - - Provisionable Default = 0x0 - - 1 = MSW of counter must be read first - 0 = LSW of counter must be read first - - - Notes: - This bit configures whether the MSW or LSW must be read first for counters greater than 16 bits. */ - unsigned int mdioReadMSW_FirstEnable : 1; /* 1E.C441.D R/WPD Provisionable Default = 0x0 */ - /* 1 = MSW of counter must be read first - 0 = LSW of counter must be read first - */ - unsigned int reserved1 : 8; - /*! \brief 1E.C441.4 R/WPD MDIO Drive Configuration - AQ_GlobalGeneralProvisioning_HHD.u1.bits_1.mdioDriveConfiguration - - Provisionable Default = 0x0 - - 0 = MDIO driver is in normal mode - 1 = MDIO driver is in open drain mode - - - Notes: - When the MDIO driver is in open drain mode during a read cycle, "0" data will be actively driven out of the MDIO, "1" data will set the MDIO driver in high impedance state and an external pullup will set the MDIO line to "1". The Turn-Around "0" will also be actively driven out of the MDIO, therefore in open drain mode, the Turn-Around is still "Z0". */ - unsigned int mdioDriveConfiguration : 1; /* 1E.C441.4 R/WPD Provisionable Default = 0x0 */ - /* 0 = MDIO driver is in normal mode - 1 = MDIO driver is in open drain mode - */ - /*! \brief 1E.C441.3 R/WPD MDIO Preamble Detection Disable - AQ_GlobalGeneralProvisioning_HHD.u1.bits_1.mdioPreambleDetectionDisable - - Provisionable Default = 0x0 - - 1 = Suppress preamble detection on MDIO - 0 = Enable preamble detection on MDIO - - */ - unsigned int mdioPreambleDetectionDisable : 1; /* 1E.C441.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = Suppress preamble detection on MDIO - 0 = Enable preamble detection on MDIO - */ - unsigned int reserved2 : 1; - unsigned int reserved3 : 2; - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global General Provisioning */ - union - { - struct - { - unsigned int reserved0 : 15; - /*! \brief 1E.C442.0 R/W Daisy Chain Reset - AQ_GlobalGeneralProvisioning_HHD.u2.bits_2.daisyChainReset - - Default = 0x0 - - 1 = Reset the daisy chain - - - Notes: - Toggling this bit from 0 to 1 will reload the IRAM and DRAM and reset the uP. The uP will be in uP run stall during the reload process. After the reload process, uP run stall will be de-asserted and the uP reset will be asserted. Note that before setting this bit, the See Soft Reset bit needs to be de-asserted. */ - unsigned int daisyChainReset : 1; /* 1E.C442.0 R/W Default = 0x0 */ - /* 1 = Reset the daisy chain - */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global General Provisioning */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of Global General Provisioning */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_4; - uint16_t word_4; - } u4; - /*! \brief Union for bit and word level access of word 5 of Global General Provisioning */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_5; - uint16_t word_5; - } u5; - /*! \brief Union for bit and word level access of word 6 of Global General Provisioning */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_6; - uint16_t word_6; - } u6; - /*! \brief Union for bit and word level access of word 7 of Global General Provisioning */ - union - { - struct - { - unsigned int reserved0 : 11; - /*! \brief 1E.C447.4:0 R/WPD MDIO Broadcast Address Configuration [4:0] - AQ_GlobalGeneralProvisioning_HHD.u7.bits_7.mdioBroadcastAddressConfiguration - - Provisionable Default = 0x1F - - Broadcast address - - - Notes: - Allows setting the broadcast address. By default this is set to 0x1F */ - unsigned int mdioBroadcastAddressConfiguration : 5; /* 1E.C447.4:0 R/WPD Provisionable Default = 0x1F */ - /* Broadcast address - */ - } bits_7; - uint16_t word_7; - } u7; - /*! \brief Union for bit and word level access of word 8 of Global General Provisioning */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_8; - uint16_t word_8; - } u8; - /*! \brief Union for bit and word level access of word 9 of Global General Provisioning */ - union - { - struct - { - unsigned int reserved0 : 9; - /*! \brief 1E.C449.6:0 R/W MDIO Preamble Length [6:0] - AQ_GlobalGeneralProvisioning_HHD.u9.bits_9.mdioPreambleLength - - Default = 0x02 - - MDIO Preamble Length - - */ - unsigned int mdioPreambleLength : 7; /* 1E.C449.6:0 R/W Default = 0x02 */ - /* MDIO Preamble Length - */ - } bits_9; - uint16_t word_9; - } u9; -} AQ_GlobalGeneralProvisioning_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global NVR Provisioning: 1E.C450 */ -/* Global NVR Provisioning: 1E.C450 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global NVR Provisioning */ - union - { - struct - { - unsigned int reserved0 : 5; - /*! \brief 1E.C450.A:8 R/WPD NVR Data Length [2:0] - AQ_GlobalNvrProvisioning_HHD.u0.bits_0.nvrDataLength - - Provisionable Default = 0x4 - - NVR data length ranges from 0 bytes to 4 bytes - - - Notes: - This sets the length of the data burst used in read and write operations. - */ - unsigned int nvrDataLength : 3; /* 1E.C450.A:8 R/WPD Provisionable Default = 0x4 */ - /* NVR data length ranges from 0 bytes to 4 bytes - */ - unsigned int reserved1 : 1; - /*! \brief 1E.C450.6:4 R/WPD NVR Dummy Length [2:0] - AQ_GlobalNvrProvisioning_HHD.u0.bits_0.nvrDummyLength - - Provisionable Default = 0x0 - - NVR dummy length ranges from 0 bytes to 4 bytes - - - Notes: - This sets the length of the dummy field used in some manufacturer's read status and write status operations. - */ - unsigned int nvrDummyLength : 3; /* 1E.C450.6:4 R/WPD Provisionable Default = 0x0 */ - /* NVR dummy length ranges from 0 bytes to 4 bytes - */ - unsigned int reserved2 : 2; - /*! \brief 1E.C450.1:0 R/WPD NVR Address Length [1:0] - AQ_GlobalNvrProvisioning_HHD.u0.bits_0.nvrAddressLength - - Provisionable Default = 0x2 - - NVR address length ranges from 0 bytes up to 3 bytes - - - Notes: - This sets the length of the address field used in read and write operations. Use of this field is enabled via Bit 8 of See Global NVR Provisioning 2: Address 1E.C451 . - */ - unsigned int nvrAddressLength : 2; /* 1E.C450.1:0 R/WPD Provisionable Default = 0x2 */ - /* NVR address length ranges from 0 bytes up to 3 bytes - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global NVR Provisioning */ - union - { - struct - { - unsigned int reserved0 : 7; - /*! \brief 1E.C451.8 R/WPD NVR Address Length Override - AQ_GlobalNvrProvisioning_HHD.u1.bits_1.nvrAddressLengthOverride - - Provisionable Default = 0x0 - - 0 = NVR address length is based on the "NVR_SIZE" pin. - 1 = NVR address length is based on the See NVR Address Length [1:0] register - - - Notes: - When this bit = 0 and NVR_SIZE pin = 0, the NVR address length is 2 bytes. When this bit = 0 and the NVR_SIZE pin = 1, the NVR address length is 3 bytes. When this bit = 1 the NVR address length is from the See NVR Address Length [1:0] */ - unsigned int nvrAddressLengthOverride : 1; /* 1E.C451.8 R/WPD Provisionable Default = 0x0 */ - /* 0 = NVR address length is based on the "NVR_SIZE" pin. - 1 = NVR address length is based on the See NVR Address Length [1:0] register - */ - /*! \brief 1E.C451.7:0 R/WPD NVR Clock Divide [7:0] - AQ_GlobalNvrProvisioning_HHD.u1.bits_1.nvrClockDivide - - Provisionable Default = 0xA0 - - NVR clock divide. Clock frequency is divided by the NVR clock divide + 1 - - */ - unsigned int nvrClockDivide : 8; /* 1E.C451.7:0 R/WPD Provisionable Default = 0xA0 */ - /* NVR clock divide. Clock frequency is divided by the NVR clock divide + 1 - */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global NVR Provisioning */ - union - { - struct - { - unsigned int reserved0 : 14; - /*! \brief 1E.C452.1 R/W NVR Daisy Chain Clock Divide Override - AQ_GlobalNvrProvisioning_HHD.u2.bits_2.nvrDaisyChainClockDivideOverride - - Default = 0x0 - - 1 = Override NVR clock divide when in daisy chain master mode - - - Notes: - When in daisy chain master mode, the clock divide configuration is received from the FLASH. This bit will override the clock divide configuration from the FLASH with the See NVR Clock Divide [7:0] . */ - unsigned int nvrDaisyChainClockDivideOverride : 1; /* 1E.C452.1 R/W Default = 0x0 */ - /* 1 = Override NVR clock divide when in daisy chain master mode - */ - /*! \brief 1E.C452.0 R/W NVR Daisy Chain Disable - AQ_GlobalNvrProvisioning_HHD.u2.bits_2.nvrDaisyChainDisable - - Default = 0x0 - - 1 = Disable the Daisy Chain - - - Notes: - When in daisy chain master mode, the daisy chain and MDIO can both access the SPI. Setting this bit to 1 will disable the daisy chain from accessing the SPI and force it into a reset state. */ - unsigned int nvrDaisyChainDisable : 1; /* 1E.C452.0 R/W Default = 0x0 */ - /* 1 = Disable the Daisy Chain - */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global NVR Provisioning */ - union - { - struct - { - unsigned int reserved0 : 11; - /*! \brief 1E.C453.4 R/W NVR Reset - AQ_GlobalNvrProvisioning_HHD.u3.bits_3.nvrReset - - Default = 0x0 - - 1 = Reset SPI - - */ - unsigned int nvrReset : 1; /* 1E.C453.4 R/W Default = 0x0 */ - /* 1 = Reset SPI - */ - unsigned int reserved1 : 4; - } bits_3; - uint16_t word_3; - } u3; -} AQ_GlobalNvrProvisioning_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Reserved Provisioning: 1E.C470 */ -/* Global Reserved Provisioning: 1E.C470 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Reserved Provisioning */ - union - { - struct - { - /*! \brief 1E.C470.F R/WPD Diagnostics Select - AQ_GlobalReservedProvisioning_HHD.u0.bits_0.diagnosticsSelect - - Provisionable Default = 0x0 - - 1 = Provide Extended MDI Diagnostics Information. - 0 = Provide normal cable diagnostics - - - Notes: - These bits select what sort of cable diagnostics to perform. For regular cable diagnostics, Bit F is set to zero, and the diagnostics are triggered by setting Bit 4. For extended diagnostics, Bit F is set to 1, and the desired extended diagnostics are selected by Bits E:D. The routine is then triggered by setting Bit 4. Each of the extended diagnostic routines present data for all for MDI pairs (A, B, C, D) consecutively, and after the data for each channel is gathered Bits F:D are reset. To get the data for the next pair, Bits F:D must be set back to the desired value (which must be the same as the initial channel). This continues until the data for all channels has been gathered. The address in memory where the data is stored is given in 1E.C802 and 1E.C804. - - For the case of PSD, the structure is as follows: - Int32 info - Int16 data[Len] - Info = Len << 16 | TxEnable << 8 | Pair (0 = A, etc.) - - For TDR: - Int32 info - Int16 tdr_A[Len] - Int16 tdr_B[Len] - Int16 tdr_C[Len] - Int16 tdr_D[Len] - - Info = Len << 16 | Channel - - TDR data is from the current pair to all other pairs. - - At the end of retrieving extended MDI diag data, the part will be reset. Conversely the only way to exit this routine once it starts is to issue a PMA reset. */ - unsigned int diagnosticsSelect : 1; /* 1E.C470.F R/WPD Provisionable Default = 0x0 */ - /* 1 = Provide Extended MDI Diagnostics Information. - 0 = Provide normal cable diagnostics - */ - /*! \brief 1E.C470.E:D R/WPD Extended MDI Diagnostics Select [1:0] - AQ_GlobalReservedProvisioning_HHD.u0.bits_0.extendedMdiDiagnosticsSelect - - Provisionable Default = 0x0 - - 0x0 = TDR Data - 0x1 = RFI Channel PSD - 0x2 = Noise PSD while the local Tx is Off - 0x3 = Noise PSD while the local Tx is On - - - Notes: - These bits select what sort of cable diagnostics to perform. For regular cable diagnostics, Bit F is set to zero, and the diagnostics are triggered by setting Bit 4. For extended diagnostics, Bit F is set to 1, and the desired extended diagnostics are selected by Bits E:D. The routine is then triggered by setting Bit 4. Each of the extended diagnostic routines present data for all for MDI pairs (A, B, C, D) consecutively, and after the data for each channel is gathered Bits F:D are reset. To get the data for the next pair, Bits F:D must be set back to the desired value (which must be the same as the initial channel). This continues until the data for all channels has been gathered. The address in memory where the data is stored is given in 1E.C802 and 1E.C804. - - For the case of PSD, the structure is as follows: - Int32 info - Int16 data[Len] - Info = Len << 16 | TxEnable << 8 | Pair (0 = A, etc.) - - For TDR: - Int32 info - Int16 tdr_A[Len] - Int16 tdr_B[Len] - Int16 tdr_C[Len] - Int16 tdr_D[Len] - - Info = Len << 16 | Channel - - TDR data is from the current pair to all other pairs. - - At the end of retrieving extended MDI diag data, the part will be reset. Conversely the only way to exit this routine once it starts is to issue a PMA reset. */ - unsigned int extendedMdiDiagnosticsSelect : 2; /* 1E.C470.E:D R/WPD Provisionable Default = 0x0 */ - /* 0x0 = TDR Data - 0x1 = RFI Channel PSD - 0x2 = Noise PSD while the local Tx is Off - 0x3 = Noise PSD while the local Tx is On - */ - unsigned int reserved0 : 5; - unsigned int reserved1 : 3; - /*! \brief 1E.C470.4 R/WSC Initiate Cable Diagnostics - AQ_GlobalReservedProvisioning_HHD.u0.bits_0.initiateCableDiagnostics - - Default = 0x0 - - 1 = Perform cable diagnostics - - - Notes: - Perform cable diagnostics regardless of link state. If link is up, setting this bit will cause the link to drop while diagnostics are performed. This bit is self-clearing upon completion of the cable diagnostics. - - NOTE!! This is a processor intensive operation. Completion of this operation can also be monitored via 1E.C831.F */ - unsigned int initiateCableDiagnostics : 1; /* 1E.C470.4 R/WSC Default = 0x0 */ - /* 1 = Perform cable diagnostics - */ - unsigned int reserved2 : 4; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Reserved Provisioning */ - union - { - struct - { - unsigned int reserved0 : 9; - /*! \brief 1E.C471.6 R/WuP Enable Daisy-Chain Hop-Count Override - AQ_GlobalReservedProvisioning_HHD.u1.bits_1.enableDaisy_chainHop_countOverride - - Default = 0x0 - - 1 = Hop-count is set by Bits 5:0 - 0 = Hop-count is determined by the daisy-chain - - - Notes: - Daisy-Chain Hop-Count Override should be used during MDIO boot-load operation, as the daisy-chain hop-count does not function when the daisy-chain is disabled (1E.C452.0). Setting this bit tells the processor where in the daisy-chain it is, so that the provisioning operation will function correctly. */ - unsigned int enableDaisy_chainHop_countOverride : 1; /* 1E.C471.6 R/WuP Default = 0x0 */ - /* 1 = Hop-count is set by Bits 5:0 - 0 = Hop-count is determined by the daisy-chain - */ - /*! \brief 1E.C471.5:0 R/WuP Daisy-Chain Hop-Count Override Value [5:0] - AQ_GlobalReservedProvisioning_HHD.u1.bits_1.daisy_chainHop_countOverrideValue - - Default = 0x00 - - The value to use for the PHY's daisy-chain hop-count. Valid values are from 0 -> 47 - - - Notes: - Daisy-Chain Hop-Count Override should be used during MDIO boot-load operation, as the daisy-chain hop-count does not function when the daisy-chain is disabled (1E.C452.0). Setting this bit tells the processor where in the daisy-chain it is, so that the provisioning operation will function correctly. */ - unsigned int daisy_chainHop_countOverrideValue : 6; /* 1E.C471.5:0 R/WuP Default = 0x00 */ - /* The value to use for the PHY's daisy-chain hop-count. Valid values are from 0 -> 47 - */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global Reserved Provisioning */ - union - { - struct - { - unsigned int reserved0 : 1; - /*! \brief 1E.C472.E R/WPD Enable VDD Power Supply Tuning - AQ_GlobalReservedProvisioning_HHD.u2.bits_2.enableVddPowerSupplyTuning - - Provisionable Default = 0x0 - - 1 = Enable external VDD power supply tuning - 0 = Disable external VDD power supply tuning is disabled - - - Notes: - This bit controls whether the PHY attempts to tune the external VDD power supply via the SMBus. This bit is only operational if the external supply is present. (See 1E.C472.6) */ - unsigned int enableVddPowerSupplyTuning : 1; /* 1E.C472.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable external VDD power supply tuning - 0 = Disable external VDD power supply tuning is disabled - */ - unsigned int reserved1 : 7; - /*! \brief 1E.C472.6 R/WPD Tunable External VDD Power Supply Present - AQ_GlobalReservedProvisioning_HHD.u2.bits_2.tunableExternalVddPowerSupplyPresent - - Provisionable Default = 0x0 - - 1 = Tunable external VDD power supply present - 0 = No tunable external VDD power supply present - - - Notes: - This bit must be set if tuning of external power supply is desired. */ - unsigned int tunableExternalVddPowerSupplyPresent : 1; /* 1E.C472.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = Tunable external VDD power supply present - 0 = No tunable external VDD power supply present - */ - /*! \brief 1E.C472.5:2 R/WPD External VDD Change Request [3:0] - AQ_GlobalReservedProvisioning_HHD.u2.bits_2.externalVddChangeRequest - - Provisionable Default = 0x0 - - The amount of VDD change requested by firmware, in mV (2's complement value). - - */ - unsigned int externalVddChangeRequest : 4; /* 1E.C472.5:2 R/WPD Provisionable Default = 0x0 */ - /* The amount of VDD change requested by firmware, in mV (2's complement value). - */ - /*! \brief 1E.C472.1 R/WPDuP Enable XENPAK Register Space - AQ_GlobalReservedProvisioning_HHD.u2.bits_2.enableXenpakRegisterSpace - - Provisionable Default = 0x0 - - 1 = XENPAK register space enabled - 0 = XENPAK register space disabled - - */ - unsigned int enableXenpakRegisterSpace : 1; /* 1E.C472.1 R/WPDuP Provisionable Default = 0x0 */ - /* 1 = XENPAK register space enabled - 0 = XENPAK register space disabled - */ - /*! \brief 1E.C472.0 R/WPDuP Enable 5th Channel RFI Cancellation - AQ_GlobalReservedProvisioning_HHD.u2.bits_2.enable_5thChannelRfiCancellation - - Provisionable Default = 0x0 - - 1 = 5th channel and RFI cancellers operation enabled - 0 = 5th channel AFE is powered down, 5th channel digital is clock gated, RFI cancellers are disabled - - - Notes: - Note: The value of this bit at the time of Autonegotiation sets the local PHY behavior until the next time Autonegotiation occurs. */ - unsigned int enable_5thChannelRfiCancellation : 1; /* 1E.C472.0 R/WPDuP Provisionable Default = 0x0 */ - /* 1 = 5th channel and RFI cancellers operation enabled - 0 = 5th channel AFE is powered down, 5th channel digital is clock gated, RFI cancellers are disabled - */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global Reserved Provisioning */ - union - { - struct - { - unsigned int reserved0 : 5; - /*! \brief 1E.C473.A:8 R/WPD Rate Transition Request [2:0] - AQ_GlobalReservedProvisioning_HHD.u3.bits_3.rateTransitionRequest - - Provisionable Default = 0x0 - - 0 = No Transition - 1 = Reserved - 2 = Reserved - 3 = Retrain at 10G - 4 = Retrain at 5G - 5 = Retrain at 2.5G - 6 = Retrain at 1G - 7 = Reserved - - */ - unsigned int rateTransitionRequest : 3; /* 1E.C473.A:8 R/WPD Provisionable Default = 0x0 */ - /* 0 = No Transition - 1 = Reserved - 2 = Reserved - 3 = Retrain at 10G - 4 = Retrain at 5G - 5 = Retrain at 2.5G - 6 = Retrain at 1G - 7 = Reserved - */ - /*! \brief 1E.C473.7:0 R/WPD Training SNR [7:0] - AQ_GlobalReservedProvisioning_HHD.u3.bits_3.trainingSNR - - Provisionable Default = 0x00 - - SNR during 10G training on the worst channel. SNR is in steps of 0.1dB - - - Notes: - The SNR margin that is enjoyed by the worst channel, over and above the minimum SNR required to operate at a BER of 10-12. It is reported with 0.1 dB of resolution to an accuracy of 0.5 dB within the range of -12.7 dB to 12.7 dB. The number is in offset binary, with 0.0 dB represented by 0x8000. */ - unsigned int trainingSNR : 8; /* 1E.C473.7:0 R/WPD Provisionable Default = 0x00 */ - /* SNR during 10G training on the worst channel. SNR is in steps of 0.1dB - */ - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of Global Reserved Provisioning */ - union - { - struct - { - /*! \brief 1E.C474.F:1 R/WPD Reserved Provisioning 5 [F:1] - AQ_GlobalReservedProvisioning_HHD.u4.bits_4.reservedProvisioning_5 - - Provisionable Default = 0x0000 - - Reserved for future use - - */ - unsigned int reservedProvisioning_5 : 15; /* 1E.C474.F:1 R/WPD Provisionable Default = 0x0000 */ - /* Reserved for future use - */ - /*! \brief 1E.C474.0 R/W NVR Daisy Chain Kickstart - AQ_GlobalReservedProvisioning_HHD.u4.bits_4.nvrDaisyChainKickstart - - Default = 0x0 - - 1 = Kickstart the Daisy Chain - - - Notes: - When in daisy chain master mode, the PHY0 can kickstart the daisy chain. The kickstart will not reload the IRAM/DRAM or reset the uP for PHY0. It will just read the FLASH and transfer the FLASH data to the daisy chain. */ - unsigned int nvrDaisyChainKickstart : 1; /* 1E.C474.0 R/W Default = 0x0 */ - /* 1 = Kickstart the Daisy Chain - */ - } bits_4; - uint16_t word_4; - } u4; - /*! \brief Union for bit and word level access of word 5 of Global Reserved Provisioning */ - union - { - struct - { - unsigned int reserved0 : 2; - /*! \brief 1E.C475.D R/WPD Smart Power-Down Status - AQ_GlobalReservedProvisioning_HHD.u5.bits_5.smartPower_downStatus - - Provisionable Default = 0x0 - - 1 = Smart Power-Down Active - 0 = Smart Power-Down Inactive - - */ - unsigned int smartPower_downStatus : 1; /* 1E.C475.D R/WPD Provisionable Default = 0x0 */ - /* 1 = Smart Power-Down Active - 0 = Smart Power-Down Inactive - */ - /*! \brief 1E.C475.C R/WPD Reserved Provisioning 6 - AQ_GlobalReservedProvisioning_HHD.u5.bits_5.reservedProvisioning_6 - - Provisionable Default = 0x0 - - Internal reserved - do not modify - - */ - unsigned int reservedProvisioning_6 : 1; /* 1E.C475.C R/WPD Provisionable Default = 0x0 */ - /* Internal reserved - do not modify - */ - /*! \brief 1E.C475.B R/WPD CFR LP Disable Timer - AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrLpDisableTimer - - Provisionable Default = 0x0 - - 1 = Link partner requires cfr_disable timer - 0 = Link partner does not require cfr_disable timer - - */ - unsigned int cfrLpDisableTimer : 1; /* 1E.C475.B R/WPD Provisionable Default = 0x0 */ - /* 1 = Link partner requires cfr_disable timer - 0 = Link partner does not require cfr_disable timer - */ - /*! \brief 1E.C475.A R/WPD CFR LP Extended Maxwait - AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrLpExtendedMaxwait - - Provisionable Default = 0x0 - - 1 = Link partner requires extended maxwait - 0 = Link partner does not require extended maxwait - - */ - unsigned int cfrLpExtendedMaxwait : 1; /* 1E.C475.A R/WPD Provisionable Default = 0x0 */ - /* 1 = Link partner requires extended maxwait - 0 = Link partner does not require extended maxwait - */ - /*! \brief 1E.C475.9 R/WPD CFR LP THP - AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrLpTHP - - Provisionable Default = 0x0 - - 1 = Link partner requires local PHY to enable THP - 0 = Link partner does not require local PHY to enable THP - - */ - unsigned int cfrLpTHP : 1; /* 1E.C475.9 R/WPD Provisionable Default = 0x0 */ - /* 1 = Link partner requires local PHY to enable THP - 0 = Link partner does not require local PHY to enable THP - */ - /*! \brief 1E.C475.8 R/WPD CFR LP Support - AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrLpSupport - - Provisionable Default = 0x0 - - 1 = Link partner supports Cisco Fast Retrain - 0 = Link partner does support Cisco Fast Retrain - - */ - unsigned int cfrLpSupport : 1; /* 1E.C475.8 R/WPD Provisionable Default = 0x0 */ - /* 1 = Link partner supports Cisco Fast Retrain - 0 = Link partner does support Cisco Fast Retrain - */ - /*! \brief 1E.C475.7 R/WPD CFR Disable Timer - AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrDisableTimer - - Provisionable Default = 0x0 - - 1 = Local PHY requires cfr_disable timer - 0 = Local PHY does not require cfr_disable timer - - */ - unsigned int cfrDisableTimer : 1; /* 1E.C475.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = Local PHY requires cfr_disable timer - 0 = Local PHY does not require cfr_disable timer - */ - /*! \brief 1E.C475.6 R/WPD CFR Extended Maxwait - AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrExtendedMaxwait - - Provisionable Default = 0x0 - - 1 = Local PHY requires extended maxwait - 0 = Local PHY does not require extended maxwait - - */ - unsigned int cfrExtendedMaxwait : 1; /* 1E.C475.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = Local PHY requires extended maxwait - 0 = Local PHY does not require extended maxwait - */ - /*! \brief 1E.C475.5 R/WPD CFR THP - AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrTHP - - Provisionable Default = 0x0 - - 1 = Local PHY requires local PHY to enable THP - 0 = Local PHY does not require local PHY to enable THP - - */ - unsigned int cfrTHP : 1; /* 1E.C475.5 R/WPD Provisionable Default = 0x0 */ - /* 1 = Local PHY requires local PHY to enable THP - 0 = Local PHY does not require local PHY to enable THP - */ - /*! \brief 1E.C475.4 R/WPD CFR Support - AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrSupport - - Provisionable Default = 0x0 - - 1 = Local PHY supports Cisco Fast Retrain - 0 = Local PHY does support Cisco Fast Retrain - - */ - unsigned int cfrSupport : 1; /* 1E.C475.4 R/WPD Provisionable Default = 0x0 */ - /* 1 = Local PHY supports Cisco Fast Retrain - 0 = Local PHY does support Cisco Fast Retrain - */ - /*! \brief 1E.C475.3 R/WPD Deadlock Avoidance Enable - AQ_GlobalReservedProvisioning_HHD.u5.bits_5.deadlockAvoidanceEnable - - Provisionable Default = 0x0 - - 1 = SPD with deadlock avoidance: PHY transmits autonegotiation pulses (FLPs) at a slower rate (~ 1 FLP/ 100ms) than specified by autonegotiation standard (~1 FLP / 8.25ms). Receiver is active and able to detect the pulses. - 0 = SPD without deadlock avoidance: PHY transmitter is shut down, no autonegotiation pulses are sent on the line but the receiver is active and able to detect the pulses - - */ - unsigned int deadlockAvoidanceEnable : 1; /* 1E.C475.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = SPD with deadlock avoidance: PHY transmits autonegotiation pulses (FLPs) at a slower rate (~ 1 FLP/ 100ms) than specified by autonegotiation standard (~1 FLP / 8.25ms). Receiver is active and able to detect the pulses. - 0 = SPD without deadlock avoidance: PHY transmitter is shut down, no autonegotiation pulses are sent on the line but the receiver is active and able to detect the pulses - */ - /*! \brief 1E.C475.2 R/WPD Smart Power-Down Enable - AQ_GlobalReservedProvisioning_HHD.u5.bits_5.smartPower_downEnable - - Provisionable Default = 0x0 - - 1 = Enable smart power down mode - 0 = Smart power-down mode disabled - - - Notes: - Smart power down (SPD) is the lowest power mode at which PHY is able to autonegotiate. SPD can be enabled with bit 1E.C475.2 */ - unsigned int smartPower_downEnable : 1; /* 1E.C475.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable smart power down mode - 0 = Smart power-down mode disabled - */ - unsigned int reserved1 : 2; - } bits_5; - uint16_t word_5; - } u5; - /*! \brief Dummy union to fill space in the structure Global Reserved Provisioning */ - union - { - struct - { - unsigned int reserved : 16; - } bits_6; - uint16_t word_6; - } u6; - /*! \brief Dummy union to fill space in the structure Global Reserved Provisioning */ - union - { - struct - { - unsigned int reserved : 16; - } bits_7; - uint16_t word_7; - } u7; - /*! \brief Union for bit and word level access of word 8 of Global Reserved Provisioning */ - union - { - struct - { - /*! \brief 1E.C478.F R/WPD DTE Enable - AQ_GlobalReservedProvisioning_HHD.u8.bits_8.dteEnable - - Provisionable Default = 0x0 - - 1 = Enable DTE - 0 = Disable DTE - - */ - unsigned int dteEnable : 1; /* 1E.C478.F R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable DTE - 0 = Disable DTE - */ - /*! \brief 1E.C478.E:B R/WPD DTE Drop Reporting Timer [3:0] - AQ_GlobalReservedProvisioning_HHD.u8.bits_8.dteDropReportingTimer - - Provisionable Default = 0x0 - - Number of seconds between loss of link partner filter and assertion of no-power-needed state, in 5 second increments (e.g. 0x4 = 20 seconds). - - - Notes: - These bits are used to set how long the PHY waits after it no longer detects the link partner filter before declaring that power is not needed. */ - unsigned int dteDropReportingTimer : 4; /* 1E.C478.E:B R/WPD Provisionable Default = 0x0 */ - /* Number of seconds between loss of link partner filter and assertion of no-power-needed state, in 5 second increments (e.g. 0x4 = 20 seconds). - */ - /*! \brief 1E.C478.A:0 R/WPD Reserved Provisioning 9 [A:0] - AQ_GlobalReservedProvisioning_HHD.u8.bits_8.reservedProvisioning_9 - - Provisionable Default = 0x000 - - Reserved for future use - - */ - unsigned int reservedProvisioning_9 : 11; /* 1E.C478.A:0 R/WPD Provisionable Default = 0x000 */ - /* Reserved for future use - */ - } bits_8; - uint16_t word_8; - } u8; - /*! \brief Union for bit and word level access of word 9 of Global Reserved Provisioning */ - union - { - struct - { - /*! \brief 1E.C479.F R/WPD Power Up Stall - AQ_GlobalReservedProvisioning_HHD.u9.bits_9.powerUpStall - - Provisionable Default = 0x0 - - 1 = Stall FW at Power Up - 0 = Unstall the FW - - - Notes: - This bit needs to be provisioned in Power Up Init for firmware to stall. */ - unsigned int powerUpStall : 1; /* 1E.C479.F R/WPD Provisionable Default = 0x0 */ - /* 1 = Stall FW at Power Up - 0 = Unstall the FW - */ - /*! \brief 1E.C479.E:0 R/WPD Reserved Provisioning 10 [E:0] - AQ_GlobalReservedProvisioning_HHD.u9.bits_9.reservedProvisioning_10 - - Provisionable Default = 0x0000 - - Reserved for future use - - */ - unsigned int reservedProvisioning_10 : 15; /* 1E.C479.E:0 R/WPD Provisionable Default = 0x0000 */ - /* Reserved for future use - */ - } bits_9; - uint16_t word_9; - } u9; - /*! \brief Union for bit and word level access of word 10 of Global Reserved Provisioning */ - union - { - struct - { - /*! \brief 1E.C47A.F:B R/WPD Loopback Control [4:0] - AQ_GlobalReservedProvisioning_HHD.u10.bits_10.loopbackControl - - Provisionable Default = 0x00 - - 0x00 = No loopback - 0x01 = System Interface - System Loopback - 0x02 = System Interface - System Loopback with Passthrough - 0x03 = System Interface - Network Loopback - 0x04 = System Interface - Network Loopback with Passthrough - 0x05 = System Interface - Network Loopback with Passthrough and Merge - 0x06 = System Interface - Peer-to-peer loopback - 0x07 - 0x08 = Reserved - 0x09 = Network Interface - System Loopback - 0x0A = Network Interface - System Loopback with Passthrough - 0x0B = Network Interface - Network Loopback - 0x0C = Network Interface - Network Loopback with Passthrough - 0x0D = Network Interface - Peer-to-peer loopback - 0x0E - 0x0F = Reserved - 0x10 = Cross-connect System Loopback - 0x11 = Cross-connect Network Loopback - 0x12 - 0x13 = Reserved - 0x14 = Network Interface - System Loopback via Loopback Plug - 0x15 - 0x1F = Reserved - - - Notes: - These bits, in conjunction with the chip configuration and the rate (Bits 1:0), select the loopback to configure for the chip. Setting one of these loopbacks provisions the chip for the specified loopback. Upon clearing the loopback, the chip returns to it's configuration prior to entering loopback (irregardless of whether other loopbacks were selected after the initial loopback). - - NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F. - - The controls in this register are identical to, and mirrored with, the controls in 4.C444. - */ - unsigned int loopbackControl : 5; /* 1E.C47A.F:B R/WPD Provisionable Default = 0x00 */ - /* 0x00 = No loopback - 0x01 = System Interface - System Loopback - 0x02 = System Interface - System Loopback with Passthrough - 0x03 = System Interface - Network Loopback - 0x04 = System Interface - Network Loopback with Passthrough - 0x05 = System Interface - Network Loopback with Passthrough and Merge - 0x06 = System Interface - Peer-to-peer loopback - 0x07 - 0x08 = Reserved - 0x09 = Network Interface - System Loopback - 0x0A = Network Interface - System Loopback with Passthrough - 0x0B = Network Interface - Network Loopback - 0x0C = Network Interface - Network Loopback with Passthrough - 0x0D = Network Interface - Peer-to-peer loopback - 0x0E - 0x0F = Reserved - 0x10 = Cross-connect System Loopback - 0x11 = Cross-connect Network Loopback - 0x12 - 0x13 = Reserved - 0x14 = Network Interface - System Loopback via Loopback Plug - 0x15 - 0x1F = Reserved - */ - /*! \brief 1E.C47A.A:6 R/WPD Reserved Provisioning 11 [4:0] - AQ_GlobalReservedProvisioning_HHD.u10.bits_10.reservedProvisioning_11 - - Provisionable Default = 0x00 - - Reserved for future use - - */ - unsigned int reservedProvisioning_11 : 5; /* 1E.C47A.A:6 R/WPD Provisionable Default = 0x00 */ - /* Reserved for future use - */ - /*! \brief 1E.C47A.5 R/WPD MDI Packet Generation - AQ_GlobalReservedProvisioning_HHD.u10.bits_10.mdiPacketGeneration - - Provisionable Default = 0x0 - - 1 = CRPAT packet generation out MDI interface - 0 = No CRPAT packet generation out MDI interface - - - Notes: - Selecting this mode of operation causes the CRPAT packet generator in the PHY to output on the MDI interface at the selected rate. - - NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F - - The controls in this register are identical to, and mirrored with, the controls in 4.C444. */ - unsigned int mdiPacketGeneration : 1; /* 1E.C47A.5 R/WPD Provisionable Default = 0x0 */ - /* 1 = CRPAT packet generation out MDI interface - 0 = No CRPAT packet generation out MDI interface - */ - /*! \brief 1E.C47A.4 R/WPD Look-Aside Port Packet Generation - AQ_GlobalReservedProvisioning_HHD.u10.bits_10.look_asidePortPacketGeneration - - Provisionable Default = 0x0 - - 1 = CRPAT packet generation out 10G look-aside interface (KR0) - 0 = No CRPAT packet generation out 10G look-aside interface (KR0) - - - Notes: - Selecting this mode of operation causes the CRPAT packet generator in the PHY to output on KR0. - - NOTE!! This only functions if KR1 (SERDES2) is selected as the system interface in (4.C441.F:E). - - NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F - - The controls in this register are identical to, and mirrored with, the controls in 4.C444. */ - unsigned int look_asidePortPacketGeneration : 1; /* 1E.C47A.4 R/WPD Provisionable Default = 0x0 */ - /* 1 = CRPAT packet generation out 10G look-aside interface (KR0) - 0 = No CRPAT packet generation out 10G look-aside interface (KR0) - */ - /*! \brief 1E.C47A.3 R/WPD System I/F Packet Generation - AQ_GlobalReservedProvisioning_HHD.u10.bits_10.systemI_fPacketGeneration - - Provisionable Default = 0x0 - - 1 = CRPAT packet generation out 10G system interface - 0 = No CRPAT packet generation out 10G system interface - - - Notes: - Selecting this mode of operation causes the CRPAT packet generator in the PHY to output CRPAT packets on the selected 10G system interface (4.C441.F:E) - - NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F - - The controls in this register are identical to, and mirrored with, the controls in 4.C444. */ - unsigned int systemI_fPacketGeneration : 1; /* 1E.C47A.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = CRPAT packet generation out 10G system interface - 0 = No CRPAT packet generation out 10G system interface - */ - /*! \brief 1E.C47A.2 R/WPD Reserved Provisioning 11a - AQ_GlobalReservedProvisioning_HHD.u10.bits_10.reservedProvisioning_11a - - Provisionable Default = 0x0 - - Reserved for future use - - */ - unsigned int reservedProvisioning_11a : 1; /* 1E.C47A.2 R/WPD Provisionable Default = 0x0 */ - /* Reserved for future use - */ - /*! \brief 1E.C47A.1:0 R/WPD Rate [1:0] - AQ_GlobalReservedProvisioning_HHD.u10.bits_10.rate - - Provisionable Default = 0x0 - - 0x3 = 10G - 0x2 = 1G - 0x1 = 100M - 0x0 = reserved - - - Notes: - These bits select the rate for the loopback and packet generation. SERDES configuration, as well autonegotiation is controlled accordingly when a loopback is selected. For instance, if 100M system loopback on the network interface is selected, SGMII on the system interface is enabled to connect at 100M, and if passthrough is enabled 100BASE-TX will be the only advertised rate and will force a re-autonegotiation if not already connected at 100M. - - NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F - - The controls in this register are identical to, and mirrored with, the controls in 4.C444. */ - unsigned int rate : 2; /* 1E.C47A.1:0 R/WPD Provisionable Default = 0x0 */ - /* 0x3 = 10G - 0x2 = 1G - 0x1 = 100M - 0x0 = reserved - */ - } bits_10; - uint16_t word_10; - } u10; - /*! \brief Union for bit and word level access of word 11 of Global Reserved Provisioning */ - union - { - struct - { - /*! \brief 1E.C47B.F:2 R/WPD Reserved Provisioning 12 [D:0] - AQ_GlobalReservedProvisioning_HHD.u11.bits_11.reservedProvisioning_12 - - Provisionable Default = 0x0000 - - Reserved for future use - - */ - unsigned int reservedProvisioning_12 : 14; /* 1E.C47B.F:2 R/WPD Provisionable Default = 0x0000 */ - /* Reserved for future use - */ - /*! \brief 1E.C47B.1 R/WPD Enable MACSec - AQ_GlobalReservedProvisioning_HHD.u11.bits_11.enableMacsec - - Provisionable Default = 0x0 - - 1 = MACSec functionality is enabled - 0 = MACSec functionality is disabled - - - Notes: - If this bit is 1, the PTP/SEC block will be included in the data path, regardless of operating mode. */ - unsigned int enableMacsec : 1; /* 1E.C47B.1 R/WPD Provisionable Default = 0x0 */ - /* 1 = MACSec functionality is enabled - 0 = MACSec functionality is disabled - */ - /*! \brief 1E.C47B.0 R/WPD Enable PTP - AQ_GlobalReservedProvisioning_HHD.u11.bits_11.enablePtp - - Provisionable Default = 0x0 - - 1 = PTP functionality is enabled - 0 = PTP functionality is disabled - - - Notes: - If this bit is 1, the PTP/SEC block will be included in the data path, regardless of operating mode. */ - unsigned int enablePtp : 1; /* 1E.C47B.0 R/WPD Provisionable Default = 0x0 */ - /* 1 = PTP functionality is enabled - 0 = PTP functionality is disabled - */ - } bits_11; - uint16_t word_11; - } u11; -} AQ_GlobalReservedProvisioning_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief PIF Mailbox Control: 1E.C47C */ -/* PIF Mailbox Control: 1E.C47C */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of PIF Mailbox Control */ - union - { - struct - { - /*! \brief 1E.C47C.F:0 R/WPDuP PIF Mailbox Address [F:0] - AQ_PifMailboxControl_HHD.u0.bits_0.pifMailboxAddress - - Provisionable Default = 0x0000 - - The least 16 bits of the PIF address to read or write. - - */ - unsigned int pifMailboxAddress : 16; /* 1E.C47C.F:0 R/WPDuP Provisionable Default = 0x0000 */ - /* The least 16 bits of the PIF address to read or write. - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of PIF Mailbox Control */ - union - { - struct - { - /*! \brief 1E.C47D.F:0 R/WPDuP PIF Mailbox Data [F:0] - AQ_PifMailboxControl_HHD.u1.bits_1.pifMailboxData - - Provisionable Default = 0x0000 - - The data to be written, or that had been read. - - */ - unsigned int pifMailboxData : 16; /* 1E.C47D.F:0 R/WPDuP Provisionable Default = 0x0000 */ - /* The data to be written, or that had been read. - */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of PIF Mailbox Control */ - union - { - struct - { - /*! \brief 1E.C47E.F:C R/WPD Reserved PIF Mailbox Control 3 [3:0] - AQ_PifMailboxControl_HHD.u2.bits_2.reservedPifMailboxControl_3 - - Provisionable Default = 0x0 - - Reserved for future use - - */ - unsigned int reservedPifMailboxControl_3 : 4; /* 1E.C47E.F:C R/WPD Provisionable Default = 0x0 */ - /* Reserved for future use - */ - /*! \brief 1E.C47E.B:8 R/WPDuP PIF Mailbox Command Type [3:0] - AQ_PifMailboxControl_HHD.u2.bits_2.pifMailboxCommandType - - Provisionable Default = 0x0 - - 0 = No Action - 1 = Read - 2 = Write - - - Notes: - System SW writes non-zero value to start a PIF command. */ - unsigned int pifMailboxCommandType : 4; /* 1E.C47E.B:8 R/WPDuP Provisionable Default = 0x0 */ - /* 0 = No Action - 1 = Read - 2 = Write - */ - /*! \brief 1E.C47E.7:0 R/WPDuP PIF Mailbox MMD [7:0] - AQ_PifMailboxControl_HHD.u2.bits_2.pifMailboxMMD - - Provisionable Default = 0x00 - - MMD (upper 8 bits) of the PID address to read or write. - - */ - unsigned int pifMailboxMMD : 8; /* 1E.C47E.7:0 R/WPDuP Provisionable Default = 0x00 */ - /* MMD (upper 8 bits) of the PID address to read or write. - */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of PIF Mailbox Control */ - union - { - struct - { - /*! \brief 1E.C47F.F:4 R/WPD Reserved PIF Mailbox Control 4 [B:0] - AQ_PifMailboxControl_HHD.u3.bits_3.reservedPifMailboxControl_4 - - Provisionable Default = 0x000 - - Reserved for future use - - */ - unsigned int reservedPifMailboxControl_4 : 12; /* 1E.C47F.F:4 R/WPD Provisionable Default = 0x000 */ - /* Reserved for future use - */ - /*! \brief 1E.C47F.3:0 R/WPDuP PIF Mailbox Command Status [3:0] - AQ_PifMailboxControl_HHD.u3.bits_3.pifMailboxCommandStatus - - Provisionable Default = 0x0 - - 0 = Idle - 1 = Command completed - 2 = Command did not complete - - - Notes: - System SW should write 0 before writing Command Type to clear completion status */ - unsigned int pifMailboxCommandStatus : 4; /* 1E.C47F.3:0 R/WPDuP Provisionable Default = 0x0 */ - /* 0 = Idle - 1 = Command completed - 2 = Command did not complete - */ - } bits_3; - uint16_t word_3; - } u3; -} AQ_PifMailboxControl_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global SMBus 0 Provisioning: 1E.C485 */ -/* Global SMBus 0 Provisioning: 1E.C485 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global SMBus 0 Provisioning */ - union - { - struct - { - unsigned int reserved0 : 8; - /*! \brief 1E.C485.7:1 R/W SMB 0 Slave Address [7:1] - AQ_GlobalSmbus_0Provisioning_HHD.u0.bits_0.smb_0SlaveAddress - - Default = 0x00 - - SMB slave address configuration - - */ - unsigned int smb_0SlaveAddress : 7; /* 1E.C485.7:1 R/W Default = 0x00 */ - /* SMB slave address configuration - */ - unsigned int reserved1 : 1; - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalSmbus_0Provisioning_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global SMBus 1 Provisioning: 1E.C495 */ -/* Global SMBus 1 Provisioning: 1E.C495 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global SMBus 1 Provisioning */ - union - { - struct - { - unsigned int reserved0 : 8; - /*! \brief 1E.C495.7:1 R/W SMB 1 Slave Address [7:1] - AQ_GlobalSmbus_1Provisioning_HHD.u0.bits_0.smb_1SlaveAddress - - Default = 0x00 - - SMB slave address configuration - - */ - unsigned int smb_1SlaveAddress : 7; /* 1E.C495.7:1 R/W Default = 0x00 */ - /* SMB slave address configuration - */ - unsigned int reserved1 : 1; - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalSmbus_1Provisioning_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global EEE Provisioning: 1E.C4A0 */ -/* Global EEE Provisioning: 1E.C4A0 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global EEE Provisioning */ - union - { - struct - { - unsigned int reserved0 : 15; - /*! \brief 1E.C4A0.0 R/WPD EEE Mode - AQ_GlobalEeeProvisioning_HHD.u0.bits_0.eeeMode - - Provisionable Default = 0x0 - - 1 = EEE mode of operation - - - Notes: - EEE mode of operation (0=disable, 1=enable, default:0) */ - unsigned int eeeMode : 1; /* 1E.C4A0.0 R/WPD Provisionable Default = 0x0 */ - /* 1 = EEE mode of operation - */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalEeeProvisioning_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Cable Diagnostic Status: 1E.C800 */ -/* Global Cable Diagnostic Status: 1E.C800 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Cable Diagnostic Status */ - union - { - struct - { - unsigned int reserved0 : 1; - /*! \brief 1E.C800.E:C RO Pair A Status [2:0] - AQ_GlobalCableDiagnosticStatus_HHD.u0.bits_0.pairAStatus - - - - [F:D] - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair D - 010= Connected to Pair C - 001= Connected to Pair B - 000= OK - - Notes: - This register summarizes the worst impairment on Pair A. */ - unsigned int pairAStatus : 3; /* 1E.C800.E:C RO */ - /* [F:D] - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair D - 010= Connected to Pair C - 001= Connected to Pair B - 000= OK */ - unsigned int reserved1 : 1; - /*! \brief 1E.C800.A:8 RO Pair B Status [2:0] - AQ_GlobalCableDiagnosticStatus_HHD.u0.bits_0.pairBStatus - - - - [C:A] - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair A - 010= Connected to Pair D - 001= Connected to Pair C - 000= OK - - Notes: - This register summarizes the worst impairment on Pair B. */ - unsigned int pairBStatus : 3; /* 1E.C800.A:8 RO */ - /* [C:A] - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair A - 010= Connected to Pair D - 001= Connected to Pair C - 000= OK */ - unsigned int reserved2 : 1; - /*! \brief 1E.C800.6:4 RO Pair C Status [2:0] - AQ_GlobalCableDiagnosticStatus_HHD.u0.bits_0.pairCStatus - - - - [9:7] - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair B - 010= Connected to Pair A - 001= Connected to Pair D - 000= OK - - Notes: - This register summarizes the worst impairment on Pair C. */ - unsigned int pairCStatus : 3; /* 1E.C800.6:4 RO */ - /* [9:7] - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair B - 010= Connected to Pair A - 001= Connected to Pair D - 000= OK */ - unsigned int reserved3 : 1; - /*! \brief 1E.C800.2:0 RO Pair D Status [2:0] - AQ_GlobalCableDiagnosticStatus_HHD.u0.bits_0.pairDStatus - - - - [6:4] - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair C - 010= Connected to Pair B - 001= Connected to Pair A - 000= OK - - Notes: - This register summarizes the worst impairment on Pair D. */ - unsigned int pairDStatus : 3; /* 1E.C800.2:0 RO */ - /* [6:4] - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair C - 010= Connected to Pair B - 001= Connected to Pair A - 000= OK */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C801.F:8 RO Pair A Reflection #1 [7:0] - AQ_GlobalCableDiagnosticStatus_HHD.u1.bits_1.pairAReflection_1 - - - - The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair A - - Notes: - The distance to this reflection is given in See Global Reserved Status 1: Address 1E.C870 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairAReflection_1 : 8; /* 1E.C801.F:8 RO */ - /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair A */ - /*! \brief 1E.C801.7:0 RO Pair A Reflection #2 [7:0] - AQ_GlobalCableDiagnosticStatus_HHD.u1.bits_1.pairAReflection_2 - - - - The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair A - - Notes: - The distance to this reflection is given in See Global Reserved Status 1: Address 1E.C870 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairAReflection_2 : 8; /* 1E.C801.7:0 RO */ - /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair A */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C802.F:0 RO Impulse Response MSW [F:0] - AQ_GlobalCableDiagnosticStatus_HHD.u2.bits_2.impulseResponseMSW - - - - The MSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type in 1E.C470.E:D - - Notes: - See 1E.C470 for more information */ - unsigned int impulseResponseMSW : 16; /* 1E.C802.F:0 RO */ - /* The MSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type in 1E.C470.E:D */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C803.F:8 RO Pair B Reflection #1 [7:0] - AQ_GlobalCableDiagnosticStatus_HHD.u3.bits_3.pairBReflection_1 - - - - The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair B - - Notes: - The distance to this reflection is given in See Global Reserved Status 2: Address 1E.C871 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairBReflection_1 : 8; /* 1E.C803.F:8 RO */ - /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair B */ - /*! \brief 1E.C803.7:0 RO Pair B Reflection #2 [7:0] - AQ_GlobalCableDiagnosticStatus_HHD.u3.bits_3.pairBReflection_2 - - - - The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair B - - Notes: - The distance to this reflection is given in See Global Reserved Status 2: Address 1E.C871 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairBReflection_2 : 8; /* 1E.C803.7:0 RO */ - /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair B */ - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C804.F:0 RO Impulse Response LSW [F:0] - AQ_GlobalCableDiagnosticStatus_HHD.u4.bits_4.impulseResponseLSW - - - - The LSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type specified in 1E.C470.E:D - - Notes: - See 1E.C470 for more information */ - unsigned int impulseResponseLSW : 16; /* 1E.C804.F:0 RO */ - /* The LSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type specified in 1E.C470.E:D */ - } bits_4; - uint16_t word_4; - } u4; - /*! \brief Union for bit and word level access of word 5 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C805.F:8 RO Pair C Reflection #1 [7:0] - AQ_GlobalCableDiagnosticStatus_HHD.u5.bits_5.pairCReflection_1 - - - - The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair C - - Notes: - The distance to this reflection is given in See Global Reserved Status 3: Address 1E.C872 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairCReflection_1 : 8; /* 1E.C805.F:8 RO */ - /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair C */ - /*! \brief 1E.C805.7:0 RO Pair C Reflection #2 [7:0] - AQ_GlobalCableDiagnosticStatus_HHD.u5.bits_5.pairCReflection_2 - - - - The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair C - - Notes: - The distance to this reflection is given in See Global Reserved Status 3: Address 1E.C872 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairCReflection_2 : 8; /* 1E.C805.7:0 RO */ - /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair C */ - } bits_5; - uint16_t word_5; - } u5; - /*! \brief Union for bit and word level access of word 6 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C806.F:0 RO Reserved 1 [F:0] - AQ_GlobalCableDiagnosticStatus_HHD.u6.bits_6.reserved_1 - - - - Reserved for future use - */ - unsigned int reserved_1 : 16; /* 1E.C806.F:0 RO */ - /* Reserved for future use */ - } bits_6; - uint16_t word_6; - } u6; - /*! \brief Union for bit and word level access of word 7 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C807.F:8 RO Pair D Reflection #1 [7:0] - AQ_GlobalCableDiagnosticStatus_HHD.u7.bits_7.pairDReflection_1 - - - - The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair D - - Notes: - The distance to this reflection is given in See Global Reserved Status 4: Address 1E.C873 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairDReflection_1 : 8; /* 1E.C807.F:8 RO */ - /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair D */ - /*! \brief 1E.C807.7:0 RO Pair D Reflection #2 [7:0] - AQ_GlobalCableDiagnosticStatus_HHD.u7.bits_7.pairDReflection_2 - - - - The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair D - - Notes: - The distance to this reflection is given in See Global Reserved Status 4: Address 1E.C873 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairDReflection_2 : 8; /* 1E.C807.7:0 RO */ - /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair D */ - } bits_7; - uint16_t word_7; - } u7; -} AQ_GlobalCableDiagnosticStatus_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Thermal Status: 1E.C820 */ -/* Global Thermal Status: 1E.C820 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Thermal Status */ - union - { - struct - { - /*! \brief 1E.C820.F:0 RO Temperature [F:0] - AQ_GlobalThermalStatus_HHD.u0.bits_0.temperature - - - - [F:0] of temperature - - - Notes: - 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 70 degreesC. This is a mirror of the XENPAK register 1.A060 - 1.A061. The mirror is performed in H/W. */ - unsigned int temperature : 16; /* 1E.C820.F:0 RO */ - /* [F:0] of temperature - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Thermal Status */ - union - { - struct - { - unsigned int reserved0 : 15; - /*! \brief 1E.C821.0 RO Temperature Ready - AQ_GlobalThermalStatus_HHD.u1.bits_1.temperatureReady - - - - 1 = Temperature measurement is valid - - - Notes: - This is a mirror of the XENPAK register 1.A06E. */ - unsigned int temperatureReady : 1; /* 1E.C821.0 RO */ - /* 1 = Temperature measurement is valid - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_GlobalThermalStatus_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global General Status: 1E.C830 */ -/* Global General Status: 1E.C830 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global General Status */ - union - { - struct - { - unsigned int reserved0 : 1; - /*! \brief 1E.C830.E RO High Temperature Failure State - AQ_GlobalGeneralStatus_HHD.u0.bits_0.highTemperatureFailureState - - - - 1 = High temperature failure threshold has been exceeded - - Notes: - In XENPAK mode, F/W will copy this register to the 1.A070.7 register. - - */ - unsigned int highTemperatureFailureState : 1; /* 1E.C830.E RO */ - /* 1 = High temperature failure threshold has been exceeded */ - /*! \brief 1E.C830.D RO Low Temperature Failure State - AQ_GlobalGeneralStatus_HHD.u0.bits_0.lowTemperatureFailureState - - - - 1 = Low temperature failure threshold has been exceeded - - Notes: - In XENPAK mode, F/W will copy this register to the 1.A070.6 register. - - */ - unsigned int lowTemperatureFailureState : 1; /* 1E.C830.D RO */ - /* 1 = Low temperature failure threshold has been exceeded */ - /*! \brief 1E.C830.C RO High Temperature Warning State - AQ_GlobalGeneralStatus_HHD.u0.bits_0.highTemperatureWarningState - - - - 1 = High temperature warning threshold has been exceeded - - Notes: - In XENPAK mode, F/W will copy this register to the 1.A074.7 register. - - */ - unsigned int highTemperatureWarningState : 1; /* 1E.C830.C RO */ - /* 1 = High temperature warning threshold has been exceeded */ - /*! \brief 1E.C830.B RO Low Temperature Warning State - AQ_GlobalGeneralStatus_HHD.u0.bits_0.lowTemperatureWarningState - - - - 1 = Low temperature warning threshold has been exceeded - - Notes: - In XENPAK mode, F/W will copy this register to the 1.A074.6 register. - - */ - unsigned int lowTemperatureWarningState : 1; /* 1E.C830.B RO */ - /* 1 = Low temperature warning threshold has been exceeded */ - unsigned int reserved1 : 11; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global General Status */ - union - { - struct - { - /*! \brief 1E.C831.F RO Processor Intensive MDIO Operation In- Progress - AQ_GlobalGeneralStatus_HHD.u1.bits_1.processorIntensiveMdioOperationIn_Progress - - - - 1 = PHY microprocessor is busy with a processor-intensive MDIO operation - 0 = Processor-intensive MDIO operation completed - - - Notes: - This bit should may be used with certain processor-intensive MDIO commands (such as Loopbacks, Test Modes, Low power modes, Tx-Disable, Restart autonegotiation, Cable Diagnostics, etc.) that take longer than an MDIO cycle to complete. Upon receiving an MDIO command that involves the PHY's microprocessor, this bit is set, and when the command is completed, this bit is cleared. - - NOTE!!! This bit should be checked only after 1 ms of issuing a processor-intensive MDIO operation. - - The list of operations that set this bit are as follows: - - 1.0.0, PMA Loopback - 1.0.B, Low power mode - 1.9.4:0, Tx Disable - 1.84, 10G Test modes - 1.8000.5, XENPAK Control - 1.9000, XENPAK Rx Fault Enable - 1.9002, XENPAK Alarm Enable - 1.E400.F, External loopback - 3.0.B, Low power mode - 3.0.E, System PCS loopback - 3.C471.5, PRBS Test - 3.C471.6, PRBS Test - 3.E471.5, PRBS Test - 3.E471.6, PRBS Test - 4.0.B, Low power mode - 4.0.E, PHY-XS network loopback - 4.C440, Output clock control, Load SERDES parameters - 4.F802.E, System loopback - 4.C444.F:B, Loopback Control - 4.C444.4:2, Packet generation - 4.C445.C, SERDES calibration - 7.0.9, Restart autonegotiation - 1D.C280, 1G/100M Network loopback - 1D.C500, 1G System loopback - 1D.C501, 1G / 100M Test modes - 1E.C470.4, Cable diagnostics - 1E.C47A.F:B, Loopback Control - 1E.C47A.4:2, Packet generation */ - unsigned int processorIntensiveMdioOperationIn_Progress : 1; /* 1E.C831.F RO */ - /* 1 = PHY microprocessor is busy with a processor-intensive MDIO operation - 0 = Processor-intensive MDIO operation completed - */ - unsigned int reserved0 : 15; - } bits_1; - uint16_t word_1; - } u1; -} AQ_GlobalGeneralStatus_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Pin Status: 1E.C840 */ -/* Global Pin Status: 1E.C840 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Pin Status */ - union - { - struct - { - unsigned int reserved0 : 1; - unsigned int reserved1 : 1; - /*! \brief 1E.C840.D RO DC_MASTER_N - AQ_GlobalPinStatus_HHD.u0.bits_0.dcMasterN - - - - Value of DC_MASTER_N pin: - - 0x1 = PHY Slave Daisy Chain Boot - 0x0 = PHY Master Daisy Chain Boot from FLASH - */ - unsigned int dcMasterN : 1; /* 1E.C840.D RO */ - /* Value of DC_MASTER_N pin: - - 0x1 = PHY Slave Daisy Chain Boot - 0x0 = PHY Master Daisy Chain Boot from FLASH */ - unsigned int reserved2 : 3; - /*! \brief 1E.C840.9 RO Package Connectivity - AQ_GlobalPinStatus_HHD.u0.bits_0.packageConnectivity - - - - Value of the package connection pin - - */ - unsigned int packageConnectivity : 1; /* 1E.C840.9 RO */ - /* Value of the package connection pin - */ - unsigned int reserved3 : 1; - /*! \brief 1E.C840.7 RO Tx Enable - AQ_GlobalPinStatus_HHD.u0.bits_0.txEnable - - - - Current Value of Tx Enable pin - - - Notes: - 0 = Disable Transmitter */ - unsigned int txEnable : 1; /* 1E.C840.7 RO */ - /* Current Value of Tx Enable pin - */ - unsigned int reserved4 : 1; - /*! \brief 1E.C840.5:0 RO LED Pullup State [5:0] - AQ_GlobalPinStatus_HHD.u0.bits_0.ledPullupState - - - - 1 = LED output pin is pulled high - 0 = LED output pin is pulled low - - */ - unsigned int ledPullupState : 6; /* 1E.C840.5:0 RO */ - /* 1 = LED output pin is pulled high - 0 = LED output pin is pulled low - */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalPinStatus_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Daisy Chain Status: 1E.C842 */ -/* Global Daisy Chain Status: 1E.C842 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Daisy Chain Status */ - union - { - struct - { - /*! \brief 1E.C842.F:0 RO Rx Daisy Chain Calculated CRC [F:0] - AQ_GlobalDaisyChainStatus_HHD.u0.bits_0.rxDaisyChainCalculatedCrc - - - - Rx Daisy Chain Calculated CRC - - - Notes: - This is the calculated daisy chain CRC. */ - unsigned int rxDaisyChainCalculatedCrc : 16; /* 1E.C842.F:0 RO */ - /* Rx Daisy Chain Calculated CRC - */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalDaisyChainStatus_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Fault Message: 1E.C850 */ -/* Global Fault Message: 1E.C850 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Fault Message */ - union - { - struct - { - /*! \brief 1E.C850.F:0 RO Message [F:0] - AQ_GlobalFaultMessage_HHD.u0.bits_0.message - - - - Error code describing fault - - Notes: - Code 0x8001: Firmware not compatible with chip architecture. This fault occurs when firmware compiled for a different microprocessor core is loaded. - Code 0x8002: VCO calibration failed. This occurs when the main PLLs on chip fail to lock: this is not possible to trigger. - Code 0x8003: XAUI calibration failed. This occurs when the XAUI PLLs fail to lock: this is not possible to trigger. - Code 0x8005: Unexpected device ID. This occurs if the device ID programmed into the internal E-Fuse registers in not valid: this is not possible to trigger. - Code 0x8006: Computed checksum does not match expected checksum. This occurs when the FLASH checksum check performed at boot time fails. This only occurs when the system boots from FLASH. - Code 0x8007: Detected a bit error in static memory. To trigger, corrupt one of the static regions. - Code 0xC001: Illegal Instruction exception. This occurs when the processor attempts to execute an illegal instruction. To trigger this, write an illegal instruction to program memory. It's possible that the bit error check will trigger before the illegal instruction is executed. - Code 0xC002 Instruction Fetch Error. Internal physical address or a data error during instruction fetch: this is not possible to trigger. - Code 0xC003 Load Store Error. Internal physical address or data error during load store operation: this is not possible to trigger.. - Code 0xC004 Privileged Instruction. Attempt to execute a privileged operation without sufficient privilege: this is not possible to trigger. - Code 0xC005 Unaligned Load or Store. Attempt to load or store data at an address which cannot be handled due to alignment: this is not possible to trigger. - Code 0xC006 Instruction fetch from prohibited space: this is not possible to trigger. - Code 0xC007 Data load from prohibited space: this is not possible to trigger. - Code 0xC008 Data store into prohibited space: this is not possible to trigger. */ - unsigned int message : 16; /* 1E.C850.F:0 RO */ - /* Error code describing fault */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalFaultMessage_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Cable Diagnostic Impedance: 1E.C880 */ -/* Global Cable Diagnostic Impedance: 1E.C880 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Cable Diagnostic Impedance */ - union - { - struct - { - /*! \brief 1E.C880.F RO Reserved 1 - AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.reserved_1 - - - - Reserved - - */ - unsigned int reserved_1 : 1; /* 1E.C880.F RO */ - /* Reserved - */ - /*! \brief 1E.C880.E:C RO Pair A Reflection #1 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.pairAReflection_1 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the first worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ - unsigned int pairAReflection_1 : 3; /* 1E.C880.E:C RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C880.B RO Reserved 2 - AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.reserved_2 - - - - Reserved - - */ - unsigned int reserved_2 : 1; /* 1E.C880.B RO */ - /* Reserved - */ - /*! \brief 1E.C880.A:8 RO Pair A Reflection #2 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.pairAReflection_2 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the second worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ - unsigned int pairAReflection_2 : 3; /* 1E.C880.A:8 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C880.7 RO Reserved 3 - AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.reserved_3 - - - - Reserved - - */ - unsigned int reserved_3 : 1; /* 1E.C880.7 RO */ - /* Reserved - */ - /*! \brief 1E.C880.6:4 RO Pair A Reflection #3 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.pairAReflection_3 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the third worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ - unsigned int pairAReflection_3 : 3; /* 1E.C880.6:4 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C880.3 RO Reserved 4 - AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.reserved_4 - - - - Reserved - - */ - unsigned int reserved_4 : 1; /* 1E.C880.3 RO */ - /* Reserved - */ - /*! \brief 1E.C880.2:0 RO Pair A Reflection #4 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.pairAReflection_4 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the fourth worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ - unsigned int pairAReflection_4 : 3; /* 1E.C880.2:0 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Cable Diagnostic Impedance */ - union - { - struct - { - /*! \brief 1E.C881.F RO Reserved 5 - AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.reserved_5 - - - - Reserved - - */ - unsigned int reserved_5 : 1; /* 1E.C881.F RO */ - /* Reserved - */ - /*! \brief 1E.C881.E:C RO Pair B Reflection #1 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.pairBReflection_1 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the first worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ - unsigned int pairBReflection_1 : 3; /* 1E.C881.E:C RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C881.B RO Reserved 6 - AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.reserved_6 - - - - Reserved - - */ - unsigned int reserved_6 : 1; /* 1E.C881.B RO */ - /* Reserved - */ - /*! \brief 1E.C881.A:8 RO Pair B Reflection #2 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.pairBReflection_2 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the second worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ - unsigned int pairBReflection_2 : 3; /* 1E.C881.A:8 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C881.7 RO Reserved 7 - AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.reserved_7 - - - - Reserved - - */ - unsigned int reserved_7 : 1; /* 1E.C881.7 RO */ - /* Reserved - */ - /*! \brief 1E.C881.6:4 RO Pair B Reflection #3 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.pairBReflection_3 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the third worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ - unsigned int pairBReflection_3 : 3; /* 1E.C881.6:4 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C881.3 RO Reserved 8 - AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.reserved_8 - - - - Reserved - - */ - unsigned int reserved_8 : 1; /* 1E.C881.3 RO */ - /* Reserved - */ - /*! \brief 1E.C881.2:0 RO Pair B Reflection #4 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.pairBReflection_4 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the fourth worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ - unsigned int pairBReflection_4 : 3; /* 1E.C881.2:0 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global Cable Diagnostic Impedance */ - union - { - struct - { - /*! \brief 1E.C882.F RO Reserved 9 - AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.reserved_9 - - - - Reserved - - */ - unsigned int reserved_9 : 1; /* 1E.C882.F RO */ - /* Reserved - */ - /*! \brief 1E.C882.E:C RO Pair C Reflection #1 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.pairCReflection_1 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the first worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ - unsigned int pairCReflection_1 : 3; /* 1E.C882.E:C RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C882.B RO Reserved 10 - AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.reserved_10 - - - - Reserved - - */ - unsigned int reserved_10 : 1; /* 1E.C882.B RO */ - /* Reserved - */ - /*! \brief 1E.C882.A:8 RO Pair C Reflection #2 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.pairCReflection_2 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the second worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ - unsigned int pairCReflection_2 : 3; /* 1E.C882.A:8 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C882.7 RO Reserved 11 - AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.reserved_11 - - - - Reserved - - */ - unsigned int reserved_11 : 1; /* 1E.C882.7 RO */ - /* Reserved - */ - /*! \brief 1E.C882.6:4 RO Pair C Reflection #3 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.pairCReflection_3 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the third worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ - unsigned int pairCReflection_3 : 3; /* 1E.C882.6:4 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C882.3 RO Reserved 12 - AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.reserved_12 - - - - Reserved - - */ - unsigned int reserved_12 : 1; /* 1E.C882.3 RO */ - /* Reserved - */ - /*! \brief 1E.C882.2:0 RO Pair C Reflection #4 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.pairCReflection_4 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the fourth worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ - unsigned int pairCReflection_4 : 3; /* 1E.C882.2:0 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global Cable Diagnostic Impedance */ - union - { - struct - { - /*! \brief 1E.C883.F RO Reserved 13 - AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.reserved_13 - - - - Reserved - - */ - unsigned int reserved_13 : 1; /* 1E.C883.F RO */ - /* Reserved - */ - /*! \brief 1E.C883.E:C RO Pair D Reflection #1 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.pairDReflection_1 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the first worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ - unsigned int pairDReflection_1 : 3; /* 1E.C883.E:C RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C883.B RO Reserved 14 - AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.reserved_14 - - - - Reserved - - */ - unsigned int reserved_14 : 1; /* 1E.C883.B RO */ - /* Reserved - */ - /*! \brief 1E.C883.A:8 RO Pair D Reflection #2 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.pairDReflection_2 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the second worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ - unsigned int pairDReflection_2 : 3; /* 1E.C883.A:8 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C883.7 RO Reserved 15 - AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.reserved_15 - - - - Reserved - - */ - unsigned int reserved_15 : 1; /* 1E.C883.7 RO */ - /* Reserved - */ - /*! \brief 1E.C883.6:4 RO Pair D Reflection #3 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.pairDReflection_3 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the third worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ - unsigned int pairDReflection_3 : 3; /* 1E.C883.6:4 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C883.3 RO Reserved 16 - AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.reserved_16 - - - - Reserved - - */ - unsigned int reserved_16 : 1; /* 1E.C883.3 RO */ - /* Reserved - */ - /*! \brief 1E.C883.2:0 RO Pair D Reflection #4 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.pairDReflection_4 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the fourth worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ - unsigned int pairDReflection_4 : 3; /* 1E.C883.2:0 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - } bits_3; - uint16_t word_3; - } u3; -} AQ_GlobalCableDiagnosticImpedance_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Status: 1E.C884 */ -/* Global Status: 1E.C884 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Status */ - union - { - struct - { - /*! \brief 1E.C884.F:8 RO Reserved Status 0 [7:0] - AQ_GlobalStatus_HHD.u0.bits_0.reservedStatus_0 - - - - Reserved - - */ - unsigned int reservedStatus_0 : 8; /* 1E.C884.F:8 RO */ - /* Reserved - */ - /*! \brief 1E.C884.7:0 RO Cable Length [7:0] - AQ_GlobalStatus_HHD.u0.bits_0.cableLength - - - - The estimated length of the cable in meters - - - Notes: - The length of the cable shown here is estimated from the cable diagnostic engine and should be accurate to +/-1m. */ - unsigned int cableLength : 8; /* 1E.C884.7:0 RO */ - /* The estimated length of the cable in meters - */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalStatus_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Reserved Status: 1E.C885 */ -/* Global Reserved Status: 1E.C885 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Reserved Status */ - union - { - struct - { - /*! \brief 1E.C885.F:A RO Nearly Seconds MSW[5:0] - AQ_GlobalReservedStatus_HHD.u0.bits_0.nearlySecondsMSW - - - - Bits 16 to 21 of the 22 bit "Nearly Seconds" uptime counter. - - - Notes: - The "Nearly Seconds" counter is incremented every 1024 milliseconds. */ - unsigned int nearlySecondsMSW : 6; /* 1E.C885.F:A RO */ - /* Bits 16 to 21 of the 22 bit "Nearly Seconds" uptime counter. - */ - /*! \brief 1E.C885.9:8 ROSPD XENPAK NVR Status [1:0] - AQ_GlobalReservedStatus_HHD.u0.bits_0.xenpakNvrStatus - - Provisionable Default = 0x0 - - Status of XENPAK NVR: - 0: NVR not enabled - 1: Last NVR operation succeeded - 2: Last NVR operation failed - 3: Reserved - - - Notes: - XENPAK register space is mirrored in NVR (SPI ROM). This register indicates the status of the last NVR operation. */ - unsigned int xenpakNvrStatus : 2; /* 1E.C885.9:8 ROSPD Provisionable Default = 0x0 */ - /* Status of XENPAK NVR: - 0: NVR not enabled - 1: Last NVR operation succeeded - 2: Last NVR operation failed - 3: Reserved - */ - /*! \brief 1E.C885.7:4 ROSPD Firmware Build ID [3:0] - AQ_GlobalReservedStatus_HHD.u0.bits_0.firmwareBuildID - - Provisionable Default = 0x0 - - Firmware Build ID - - - Notes: - Customers may receive multiple ROM images that differ only in their provisioning. This field is used to differentiate those images. This field is used in conjunction with the firmware major and minor revision numbers to uniquely identify ROM images. */ - unsigned int firmwareBuildID : 4; /* 1E.C885.7:4 ROSPD Provisionable Default = 0x0 */ - /* Firmware Build ID - */ - /*! \brief 1E.C885.3:0 ROSPD Provisioning ID [3:0] - AQ_GlobalReservedStatus_HHD.u0.bits_0.provisioningID - - Provisionable Default = 0x0 - - Provisioning ID - - - Notes: - Customers may receive multiple ROM images that differ only in their provisioning. This field is used to differentiate those images. This field is used in conjunction with the firmware major and minor revision numbers to uniquely identify ROM images. */ - unsigned int provisioningID : 4; /* 1E.C885.3:0 ROSPD Provisionable Default = 0x0 */ - /* Provisioning ID - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Reserved Status */ - union - { - struct - { - /*! \brief 1E.C886.F:0 RO Nearly Seconds LSW [F:0] - AQ_GlobalReservedStatus_HHD.u1.bits_1.nearlySecondsLSW - - - - Bits 0 to 15 of the 22 bit "Nearly Seconds" uptime counter - - - Notes: - The "Nearly Seconds" counter is incremented every 1024 milliseconds. */ - unsigned int nearlySecondsLSW : 16; /* 1E.C886.F:0 RO */ - /* Bits 0 to 15 of the 22 bit "Nearly Seconds" uptime counter - */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global Reserved Status */ - union - { - struct - { - /*! \brief 1E.C887.F ROS DTE Status - AQ_GlobalReservedStatus_HHD.u2.bits_2.dteStatus - - Default = 0x0 - - 1 = Need power - 0 = Don't need power - - */ - unsigned int dteStatus : 1; /* 1E.C887.F ROS Default = 0x0 */ - /* 1 = Need power - 0 = Don't need power - */ - /*! \brief 1E.C887.E ROS Power Up Stall Status - AQ_GlobalReservedStatus_HHD.u2.bits_2.powerUpStallStatus - - Default = 0x0 - - 1 = FW is stalled at power up - 0 = Firmware is unstalled - - */ - unsigned int powerUpStallStatus : 1; /* 1E.C887.E ROS Default = 0x0 */ - /* 1 = FW is stalled at power up - 0 = Firmware is unstalled - */ - /*! \brief 1E.C887.D:0 RO Reserved Status 3 [D:0] - AQ_GlobalReservedStatus_HHD.u2.bits_2.reservedStatus_3 - - - - Reserved for future use - - */ - unsigned int reservedStatus_3 : 14; /* 1E.C887.D:0 RO */ - /* Reserved for future use - */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global Reserved Status */ - union - { - struct - { - /*! \brief 1E.C888.F:B RO Loopback Status [4:0] - AQ_GlobalReservedStatus_HHD.u3.bits_3.loopbackStatus - - Default = 0x00 - - 0x00 = No loopback - 0x01 = System Interface - System Loopback - 0x02 = System Interface - System Loopback with Passthrough - 0x03 = System Interface - Network Loopback - 0x04 = System Interface - Network Loopback with Passthrough - 0x05 = System Interface - Network Loopback with Passthrough and Merge - 0x06 = System Interface - Peer-to-peer loopback - 0x07 - 0x08 = Reserved - 0x09 = Network Interface - System Loopback - 0x0A = Network Interface - System Loopback with Passthrough - 0x0B = Network Interface - Network Loopback - 0x0C = Network Interface - Network Loopback with Passthrough - 0x0D = Network Interface - Peer-to-peer loopback - 0x0E - 0x0F = Reserved - 0x10 = Cross-connect System Loopback - 0x11 = Cross-connect Network Loopback - 0x12 - 0x13 = Reserved - 0x14 = Network Interface - System Loopback via Loopback Plug - 0x15 - 0x1F = Reserved - - - Notes: - These bits, in conjunction with the chip configuration and the rate (Bits 1:0), report the selected loopback. - - */ - unsigned int loopbackStatus : 5; /* 1E.C888.F:B RO Default = 0x00 */ - /* 0x00 = No loopback - 0x01 = System Interface - System Loopback - 0x02 = System Interface - System Loopback with Passthrough - 0x03 = System Interface - Network Loopback - 0x04 = System Interface - Network Loopback with Passthrough - 0x05 = System Interface - Network Loopback with Passthrough and Merge - 0x06 = System Interface - Peer-to-peer loopback - 0x07 - 0x08 = Reserved - 0x09 = Network Interface - System Loopback - 0x0A = Network Interface - System Loopback with Passthrough - 0x0B = Network Interface - Network Loopback - 0x0C = Network Interface - Network Loopback with Passthrough - 0x0D = Network Interface - Peer-to-peer loopback - 0x0E - 0x0F = Reserved - 0x10 = Cross-connect System Loopback - 0x11 = Cross-connect Network Loopback - 0x12 - 0x13 = Reserved - 0x14 = Network Interface - System Loopback via Loopback Plug - 0x15 - 0x1F = Reserved - */ - /*! \brief 1E.C888.A:6 RO Reserved Status 4 [4:0] - AQ_GlobalReservedStatus_HHD.u3.bits_3.reservedStatus_4 - - Default = 0x00 - - Reserved for future use - - */ - unsigned int reservedStatus_4 : 5; /* 1E.C888.A:6 RO Default = 0x00 */ - /* Reserved for future use - */ - /*! \brief 1E.C888.5 RO MDI Packet Generation Status - AQ_GlobalReservedStatus_HHD.u3.bits_3.mdiPacketGenerationStatus - - Default = 0x0 - - 1 = CRPAT packet generation out MDI interface - 0 = No CRPAT packet generation out MDI interface - - - Notes: - Reports whether the CRPAT packet generator in the PHY outputs on the MDI interface at the selected rate. */ - unsigned int mdiPacketGenerationStatus : 1; /* 1E.C888.5 RO Default = 0x0 */ - /* 1 = CRPAT packet generation out MDI interface - 0 = No CRPAT packet generation out MDI interface - */ - /*! \brief 1E.C888.4 RO Look-Aside Port Packet Generation Status - AQ_GlobalReservedStatus_HHD.u3.bits_3.look_asidePortPacketGenerationStatus - - Default = 0x0 - - 1 = CRPAT packet generation out 10G look-aside interface (KR0) - 0 = No CRPAT packet generation out 10G look-aside interface (KR0) - - - Notes: - Reports whether the CRPAT packet generator in the PHY outputs on the KR0 interface at the selected rate. */ - unsigned int look_asidePortPacketGenerationStatus : 1; /* 1E.C888.4 RO Default = 0x0 */ - /* 1 = CRPAT packet generation out 10G look-aside interface (KR0) - 0 = No CRPAT packet generation out 10G look-aside interface (KR0) - */ - /*! \brief 1E.C888.3 RO System I/F Packet Generation Status - AQ_GlobalReservedStatus_HHD.u3.bits_3.systemI_fPacketGenerationStatus - - Default = 0x0 - - 1 = CRPAT packet generation out 10G system interface - 0 = No CRPAT packet generation out 10G system interface - - - Notes: - Reports whether the CRPAT packet generator in the PHY outputs on the selected system interface at the selected rate. */ - unsigned int systemI_fPacketGenerationStatus : 1; /* 1E.C888.3 RO Default = 0x0 */ - /* 1 = CRPAT packet generation out 10G system interface - 0 = No CRPAT packet generation out 10G system interface - */ - /*! \brief 1E.C888.2 RO Reserved Status 4a - AQ_GlobalReservedStatus_HHD.u3.bits_3.reservedStatus_4a - - Default = 0x0 - - Reserved for future use - - */ - unsigned int reservedStatus_4a : 1; /* 1E.C888.2 RO Default = 0x0 */ - /* Reserved for future use - */ - /*! \brief 1E.C888.1:0 RO Rate [1:0] - AQ_GlobalReservedStatus_HHD.u3.bits_3.rate - - Default = 0x0 - - 0x3 = 10G - 0x2 = 1G - 0x1 = 100M - 0x0 = invalid - - - Notes: - These bits report the selected rate for the loopback and packet generation. */ - unsigned int rate : 2; /* 1E.C888.1:0 RO Default = 0x0 */ - /* 0x3 = 10G - 0x2 = 1G - 0x1 = 100M - 0x0 = invalid - */ - } bits_3; - uint16_t word_3; - } u3; -} AQ_GlobalReservedStatus_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Alarms: 1E.CC00 */ -/* Global Alarms: 1E.CC00 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Alarms */ - union - { - struct - { - unsigned int reserved0 : 1; - /*! \brief 1E.CC00.E LH High Temperature Failure - AQ_GlobalAlarms_HHD.u0.bits_0.highTemperatureFailure - - - - 1 = High temperature failure threshold has been exceeded - - - Notes: - - - - - These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ - unsigned int highTemperatureFailure : 1; /* 1E.CC00.E LH */ - /* 1 = High temperature failure threshold has been exceeded - */ - /*! \brief 1E.CC00.D LH Low Temperature Failure - AQ_GlobalAlarms_HHD.u0.bits_0.lowTemperatureFailure - - - - 1 = Low temperature failure threshold has been exceeded - - - Notes: - - - - - These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ - unsigned int lowTemperatureFailure : 1; /* 1E.CC00.D LH */ - /* 1 = Low temperature failure threshold has been exceeded - */ - /*! \brief 1E.CC00.C LH High Temperature Warning - AQ_GlobalAlarms_HHD.u0.bits_0.highTemperatureWarning - - - - 1 = High temperature warning threshold has been exceeded - - - Notes: - - - - - These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ - unsigned int highTemperatureWarning : 1; /* 1E.CC00.C LH */ - /* 1 = High temperature warning threshold has been exceeded - */ - /*! \brief 1E.CC00.B LH Low Temperature Warning - AQ_GlobalAlarms_HHD.u0.bits_0.lowTemperatureWarning - - - - 1 = Low temperature warning threshold has been exceeded - - - Notes: - - - - - These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ - unsigned int lowTemperatureWarning : 1; /* 1E.CC00.B LH */ - /* 1 = Low temperature warning threshold has been exceeded - */ - unsigned int reserved1 : 4; - /*! \brief 1E.CC00.6 LH Reset completed - AQ_GlobalAlarms_HHD.u0.bits_0.resetCompleted - - - - 1 = Chip wide reset completed - - Notes: - This bit is set by the microprocessor when it has completed it's initialization sequence. This bit is mirrored in 1.CC02.0 */ - unsigned int resetCompleted : 1; /* 1E.CC00.6 LH */ - /* 1 = Chip wide reset completed */ - unsigned int reserved2 : 1; - /*! \brief 1E.CC00.4 LH Device Fault - AQ_GlobalAlarms_HHD.u0.bits_0.deviceFault - - - - 1 = Fault - - Notes: - When set, a fault has been detected by the uP and the associated 16 bit error code is visible in See Global Configuration Fault Message: Address 1E.C850 */ - unsigned int deviceFault : 1; /* 1E.CC00.4 LH */ - /* 1 = Fault */ - /*! \brief 1E.CC00.3 LH Reserved Alarm A - AQ_GlobalAlarms_HHD.u0.bits_0.reservedAlarmA - - - - Reserved for future use - - */ - unsigned int reservedAlarmA : 1; /* 1E.CC00.3 LH */ - /* Reserved for future use - */ - /*! \brief 1E.CC00.2 LH Reserved Alarm B - AQ_GlobalAlarms_HHD.u0.bits_0.reservedAlarmB - - - - Reserved for future use - - */ - unsigned int reservedAlarmB : 1; /* 1E.CC00.2 LH */ - /* Reserved for future use - */ - /*! \brief 1E.CC00.1 LH Reserved Alarm C - AQ_GlobalAlarms_HHD.u0.bits_0.reservedAlarmC - - - - Reserved for future use - - */ - unsigned int reservedAlarmC : 1; /* 1E.CC00.1 LH */ - /* Reserved for future use - */ - /*! \brief 1E.CC00.0 LH Reserved Alarm D - AQ_GlobalAlarms_HHD.u0.bits_0.reservedAlarmD - - - - Reserved for future use - - */ - unsigned int reservedAlarmD : 1; /* 1E.CC00.0 LH */ - /* Reserved for future use - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Alarms */ - union - { - struct - { - unsigned int reserved0 : 1; - /*! \brief 1E.CC01.E LH Smart Power-Down Entered - AQ_GlobalAlarms_HHD.u1.bits_1.smartPower_downEntered - - - - 1 = Smart Power-Down State Entered - - - Notes: - When this bit is set, it indicates that the Smart Power-Down state was entered */ - unsigned int smartPower_downEntered : 1; /* 1E.CC01.E LH */ - /* 1 = Smart Power-Down State Entered - */ - /*! \brief 1E.CC01.D RO XENPAK Alarm - AQ_GlobalAlarms_HHD.u1.bits_1.xenpakAlarm - - - - 1 = XENPAK Alarm - - */ - unsigned int xenpakAlarm : 1; /* 1E.CC01.D RO */ - /* 1 = XENPAK Alarm - */ - /*! \brief 1E.CC01.C LH IP Phone Detect - AQ_GlobalAlarms_HHD.u1.bits_1.ipPhoneDetect - - - - 1 = IP Phone Detect - - - Notes: - Assertion of this bit means that the presence of an IP Phone has been detected. */ - unsigned int ipPhoneDetect : 1; /* 1E.CC01.C LH */ - /* 1 = IP Phone Detect - */ - /*! \brief 1E.CC01.B LH DTE Status Change - AQ_GlobalAlarms_HHD.u1.bits_1.dteStatusChange - - - - 1 = DTE status change - - - Notes: - Change in 1E.C887[F]. */ - unsigned int dteStatusChange : 1; /* 1E.CC01.B LH */ - /* 1 = DTE status change - */ - /*! \brief 1E.CC01.A:8 LH Reserved Alarms [2:0] - AQ_GlobalAlarms_HHD.u1.bits_1.reservedAlarms - - - - Reserved - - - */ - unsigned int reservedAlarms : 3; /* 1E.CC01.A:8 LH */ - /* Reserved - - */ - /*! \brief 1E.CC01.7 LH MDIO Command Handling Overflow - AQ_GlobalAlarms_HHD.u1.bits_1.mdioCommandHandlingOverflow - - - - 1 = PHY was issued more MDIO requests than it could service in it's request buffer - - - Notes: - Assertion of this bit means that more MDIO commands were issued than FW could handle. */ - unsigned int mdioCommandHandlingOverflow : 1; /* 1E.CC01.7 LH */ - /* 1 = PHY was issued more MDIO requests than it could service in it's request buffer - */ - unsigned int reserved1 : 6; - unsigned int reserved2 : 1; - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global Alarms */ - union - { - struct - { - /*! \brief 1E.CC02.F LH NVR Operation Complete - AQ_GlobalAlarms_HHD.u2.bits_2.nvrOperationComplete - - - - 1 = NVR operation is complete - - - Notes: - NVR interface is ready interrupt for registers See Global NVR Interface 1: Address 1E.100 - See Global NVR Provisioning Data MSW - Address 1E.17 . */ - unsigned int nvrOperationComplete : 1; /* 1E.CC02.F LH */ - /* 1 = NVR operation is complete - */ - /*! \brief 1E.CC02.E LH Mailbox Operation: Complete - AQ_GlobalAlarms_HHD.u2.bits_2.mailboxOperation_Complete - - - - 1 = Mailbox operation is complete - - - Notes: - Mailbox interface is ready interrupt for registers See Global Vendor Specific Control - Address 1E.C000 - See Global Vendor Specific Provisioning 5 - Address 1E.C404 */ - unsigned int mailboxOperation_Complete : 1; /* 1E.CC02.E LH */ - /* 1 = Mailbox operation is complete - */ - unsigned int reserved0 : 3; - /*! \brief 1E.CC02.A LH uP DRAM Parity Error - AQ_GlobalAlarms_HHD.u2.bits_2.upDramParityError - - - - 1 = Parity error detected in the uP DRAM - - */ - unsigned int upDramParityError : 1; /* 1E.CC02.A LH */ - /* 1 = Parity error detected in the uP DRAM - */ - /*! \brief 1E.CC02.9:8 LH uP IRAM Parity Error [1:0] - AQ_GlobalAlarms_HHD.u2.bits_2.upIramParityError - - - - 1 = Parity error detected in the uP IRAM - - - Notes: - Bit 0 indicates a parity error was detected in the uP IRAM but was corrected. - Bit 1 indicates a multiple parity errors were detected in the uP IRAM and could not be corrected. - The uP IRAM is protected with ECC. */ - unsigned int upIramParityError : 2; /* 1E.CC02.9:8 LH */ - /* 1 = Parity error detected in the uP IRAM - */ - unsigned int reserved1 : 2; - /*! \brief 1E.CC02.5 LRF Tx Enable State Change - AQ_GlobalAlarms_HHD.u2.bits_2.txEnableStateChange - - - - 1 = TX_EN pin has changed state - - */ - unsigned int txEnableStateChange : 1; /* 1E.CC02.5 LRF */ - /* 1 = TX_EN pin has changed state - */ - unsigned int reserved2 : 2; - /*! \brief 1E.CC02.2 LH MDIO MMD Error - AQ_GlobalAlarms_HHD.u2.bits_2.mdioMMD_Error - - - - 1 = Invalid MMD address detected - - */ - unsigned int mdioMMD_Error : 1; /* 1E.CC02.2 LH */ - /* 1 = Invalid MMD address detected - */ - /*! \brief 1E.CC02.1 LH MDIO Timeout Error - AQ_GlobalAlarms_HHD.u2.bits_2.mdioTimeoutError - - - - 1 = MDIO timeout detected - - */ - unsigned int mdioTimeoutError : 1; /* 1E.CC02.1 LH */ - /* 1 = MDIO timeout detected - */ - /*! \brief 1E.CC02.0 LH Watchdog Timer Alarm - AQ_GlobalAlarms_HHD.u2.bits_2.watchdogTimerAlarm - - - - 1 = Watchdog timer alarm - - */ - unsigned int watchdogTimerAlarm : 1; /* 1E.CC02.0 LH */ - /* 1 = Watchdog timer alarm - */ - } bits_2; - uint16_t word_2; - } u2; -} AQ_GlobalAlarms_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Interrupt Mask: 1E.D400 */ -/* Global Interrupt Mask: 1E.D400 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Interrupt Mask */ - union - { - struct - { - unsigned int reserved0 : 1; - /*! \brief 1E.D400.E R/WPD High Temperature Failure Mask - AQ_GlobalInterruptMask_HHD.u0.bits_0.highTemperatureFailureMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int highTemperatureFailureMask : 1; /* 1E.D400.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.D400.D R/WPD Low Temperature Failure Mask - AQ_GlobalInterruptMask_HHD.u0.bits_0.lowTemperatureFailureMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int lowTemperatureFailureMask : 1; /* 1E.D400.D R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.D400.C R/WPD High Temperature Warning Mask - AQ_GlobalInterruptMask_HHD.u0.bits_0.highTemperatureWarningMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int highTemperatureWarningMask : 1; /* 1E.D400.C R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.D400.B R/WPD Low Temperature Warning Mask - AQ_GlobalInterruptMask_HHD.u0.bits_0.lowTemperatureWarningMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int lowTemperatureWarningMask : 1; /* 1E.D400.B R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - unsigned int reserved1 : 4; - /*! \brief 1E.D400.6 R/WPD Reset completed Mask - AQ_GlobalInterruptMask_HHD.u0.bits_0.resetCompletedMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int resetCompletedMask : 1; /* 1E.D400.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - unsigned int reserved2 : 1; - /*! \brief 1E.D400.4 R/WPD Device Fault Mask - AQ_GlobalInterruptMask_HHD.u0.bits_0.deviceFaultMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int deviceFaultMask : 1; /* 1E.D400.4 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.D400.3 R/WPD Reserved Alarm A Mask - AQ_GlobalInterruptMask_HHD.u0.bits_0.reservedAlarmAMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int reservedAlarmAMask : 1; /* 1E.D400.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - /*! \brief 1E.D400.2 R/WPD Reserved Alarm B Mask - AQ_GlobalInterruptMask_HHD.u0.bits_0.reservedAlarmBMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int reservedAlarmBMask : 1; /* 1E.D400.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - /*! \brief 1E.D400.1 R/WPD Reserved Alarm C Mask - AQ_GlobalInterruptMask_HHD.u0.bits_0.reservedAlarmCMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int reservedAlarmCMask : 1; /* 1E.D400.1 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - /*! \brief 1E.D400.0 R/WPD Reserved Alarm D Mask - AQ_GlobalInterruptMask_HHD.u0.bits_0.reservedAlarmDMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int reservedAlarmDMask : 1; /* 1E.D400.0 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Interrupt Mask */ - union - { - struct - { - unsigned int reserved0 : 1; - /*! \brief 1E.D401.E R/WPD Smart Power-Down Entered Mask - AQ_GlobalInterruptMask_HHD.u1.bits_1.smartPower_downEnteredMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int smartPower_downEnteredMask : 1; /* 1E.D401.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - /*! \brief 1E.D401.D R/WPD XENPAK Alarm Mask - AQ_GlobalInterruptMask_HHD.u1.bits_1.xenpakAlarmMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int xenpakAlarmMask : 1; /* 1E.D401.D R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.D401.C R/WPD IP Phone Detect Mask - AQ_GlobalInterruptMask_HHD.u1.bits_1.ipPhoneDetectMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int ipPhoneDetectMask : 1; /* 1E.D401.C R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - /*! \brief 1E.D401.B R/WPD DTE Status Change Mask - AQ_GlobalInterruptMask_HHD.u1.bits_1.dteStatusChangeMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int dteStatusChangeMask : 1; /* 1E.D401.B R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - /*! \brief 1E.D401.A:8 R/WPD Reserved Alarms Mask [2:0] - AQ_GlobalInterruptMask_HHD.u1.bits_1.reservedAlarmsMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int reservedAlarmsMask : 3; /* 1E.D401.A:8 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - /*! \brief 1E.D401.7 R/WPD MDIO Command Handling Overflow Mask - AQ_GlobalInterruptMask_HHD.u1.bits_1.mdioCommandHandlingOverflowMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int mdioCommandHandlingOverflowMask : 1; /* 1E.D401.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int reserved1 : 6; - /*! \brief 1E.D401.0 R/WPD Diagnostic Alarm Mask - AQ_GlobalInterruptMask_HHD.u1.bits_1.diagnosticAlarmMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int diagnosticAlarmMask : 1; /* 1E.D401.0 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global Interrupt Mask */ - union - { - struct - { - /*! \brief 1E.D402.F R/WPD NVR Operation Complete Mask - AQ_GlobalInterruptMask_HHD.u2.bits_2.nvrOperationCompleteMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - Notes: - NVR interface is ready interrupt for registers See Global NVR Interface 1: Address 1E.100 - See Global NVR Provisioning Data MSW - Address 1E.17 */ - unsigned int nvrOperationCompleteMask : 1; /* 1E.D402.F R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.D402.E R/WPD Mailbox Operation Complete Mask - AQ_GlobalInterruptMask_HHD.u2.bits_2.mailboxOperationCompleteMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - Notes: - Mailbox interface is ready interrupt for registers See Global Vendor Specific Control - Address 1E.C000 - See Global Vendor Specific Provisioning 5 - Address 1E.C404 */ - unsigned int mailboxOperationCompleteMask : 1; /* 1E.D402.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - unsigned int reserved0 : 3; - /*! \brief 1E.D402.A R/WPD uP DRAM Parity Error Mask - AQ_GlobalInterruptMask_HHD.u2.bits_2.upDramParityErrorMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int upDramParityErrorMask : 1; /* 1E.D402.A R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - /*! \brief 1E.D402.9:8 R/WPD uP IRAM Parity Error Mask [1:0] - AQ_GlobalInterruptMask_HHD.u2.bits_2.upIramParityErrorMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int upIramParityErrorMask : 2; /* 1E.D402.9:8 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int reserved1 : 2; - /*! \brief 1E.D402.5 R/WPD Tx Enable State Change Mask - AQ_GlobalInterruptMask_HHD.u2.bits_2.txEnableStateChangeMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int txEnableStateChangeMask : 1; /* 1E.D402.5 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - unsigned int reserved2 : 2; - /*! \brief 1E.D402.2 R/WPD MDIO MMD Error Mask - AQ_GlobalInterruptMask_HHD.u2.bits_2.mdioMMD_ErrorMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int mdioMMD_ErrorMask : 1; /* 1E.D402.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.D402.1 R/WPD MDIO Timeout Error Mask - AQ_GlobalInterruptMask_HHD.u2.bits_2.mdioTimeoutErrorMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int mdioTimeoutErrorMask : 1; /* 1E.D402.1 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.D402.0 R/WPD Watchdog Timer Alarm Mask - AQ_GlobalInterruptMask_HHD.u2.bits_2.watchdogTimerAlarmMask - - Provisionable Default = 0x1 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int watchdogTimerAlarmMask : 1; /* 1E.D402.0 R/WPD Provisionable Default = 0x1 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - } bits_2; - uint16_t word_2; - } u2; -} AQ_GlobalInterruptMask_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Chip-Wide Standard Interrupt Flags: 1E.FC00 */ -/* Global Chip-Wide Standard Interrupt Flags: 1E.FC00 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Chip-Wide Standard Interrupt Flags */ - union - { - struct - { - /*! \brief 1E.FC00.F RO PMA Standard Alarm 1 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.pmaStandardAlarm_1Interrupt - - - - 1 = Interrupt in PMA standard alarms 1 - - - Notes: - An interrupt was generated from bit 1.1.2. - An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ - unsigned int pmaStandardAlarm_1Interrupt : 1; /* 1E.FC00.F RO */ - /* 1 = Interrupt in PMA standard alarms 1 - */ - /*! \brief 1E.FC00.E RO PMA Standard Alarm 2 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.pmaStandardAlarm_2Interrupt - - - - 1 = Interrupt in PMA standard alarms 2 - - - Notes: - An interrupt was generated from either bit 1.8.B or 1.8.A. - An interrupt was generated from status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ - unsigned int pmaStandardAlarm_2Interrupt : 1; /* 1E.FC00.E RO */ - /* 1 = Interrupt in PMA standard alarms 2 - */ - /*! \brief 1E.FC00.D RO PCS Standard Alarm 1 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.pcsStandardAlarm_1Interrupt - - - - 1 = Interrupt in PCS standard alarms 1 - - - Notes: - An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ - unsigned int pcsStandardAlarm_1Interrupt : 1; /* 1E.FC00.D RO */ - /* 1 = Interrupt in PCS standard alarms 1 - */ - /*! \brief 1E.FC00.C RO PCS Standard Alarm 2 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.pcsStandardAlarm_2Interrupt - - - - 1 = Interrupt in PCS standard alarms 2 - - - Notes: - An interrupt was generated from status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ - unsigned int pcsStandardAlarm_2Interrupt : 1; /* 1E.FC00.C RO */ - /* 1 = Interrupt in PCS standard alarms 2 - */ - /*! \brief 1E.FC00.B RO PCS Standard Alarm 3 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.pcsStandardAlarm_3Interrupt - - - - 1 = Interrupt in PCS standard alarms 3 - - - Notes: - An interrupt was generated from status register ( See PCS 10GBASE-T Status 2 - Address 3.21 ) and the corresponding mask register. ( See PCS Standard Interrupt Mask 1 - Address 3.E021 ) */ - unsigned int pcsStandardAlarm_3Interrupt : 1; /* 1E.FC00.B RO */ - /* 1 = Interrupt in PCS standard alarms 3 - */ - /*! \brief 1E.FC00.A RO PHY XS Standard Alarms 1 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.phyXS_StandardAlarms_1Interrupt - - - - 1 = Interrupt in PHY XS standard alarms 1 - - - Notes: - An interrupt was generated from the status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ - unsigned int phyXS_StandardAlarms_1Interrupt : 1; /* 1E.FC00.A RO */ - /* 1 = Interrupt in PHY XS standard alarms 1 - */ - /*! \brief 1E.FC00.9 RO PHY XS Standard Alarms 2 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.phyXS_StandardAlarms_2Interrupt - - - - 1 = Interrupt in PHY XS standard alarms 2 - - - Notes: - An interrupt was generated from the status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ - unsigned int phyXS_StandardAlarms_2Interrupt : 1; /* 1E.FC00.9 RO */ - /* 1 = Interrupt in PHY XS standard alarms 2 - */ - /*! \brief 1E.FC00.8 RO Autonegotiation Standard Alarms 1 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.autonegotiationStandardAlarms_1Interrupt - - - - 1 = Interrupt in Autonegotiation standard alarms 1 - - - Notes: - An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See Autonegotiation Standard LASI Interrupt Mask 1: Address 7.D000 ) */ - unsigned int autonegotiationStandardAlarms_1Interrupt : 1; /* 1E.FC00.8 RO */ - /* 1 = Interrupt in Autonegotiation standard alarms 1 - */ - /*! \brief 1E.FC00.7 RO Autonegotiation Standard Alarms 2 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.autonegotiationStandardAlarms_2Interrupt - - - - 1 = Interrupt in Autonegotiation standard alarms 2 - - - Notes: - An interrupt was generated from status register ( See Autonegotiation 10GBASE-T Status Register - Address 7.21 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ - unsigned int autonegotiationStandardAlarms_2Interrupt : 1; /* 1E.FC00.7 RO */ - /* 1 = Interrupt in Autonegotiation standard alarms 2 - */ - /*! \brief 1E.FC00.6 RO GbE Standard Alarms Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.gbeStandardAlarmsInterrupt - - - - 1 = Interrupt in GbE standard alarms - - - Notes: - An interrupt was generated from the TGE core. */ - unsigned int gbeStandardAlarmsInterrupt : 1; /* 1E.FC00.6 RO */ - /* 1 = Interrupt in GbE standard alarms - */ - unsigned int reserved0 : 5; - /*! \brief 1E.FC00.0 RO All Vendor Alarms Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.allVendorAlarmsInterrupt - - - - 1 = Interrupt in all vendor alarms - - - Notes: - An interrupt was generated from status register ( See Global Chip-Wide LASI Vendor Interrupt Flags: Address 1E.FC01 ) and the corresponding mask register. ( See Global Interrupt LASI Mask: Address 1E.FF01 ) */ - unsigned int allVendorAlarmsInterrupt : 1; /* 1E.FC00.0 RO */ - /* 1 = Interrupt in all vendor alarms - */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalChip_wideStandardInterruptFlags_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Chip-Wide Vendor Interrupt Flags: 1E.FC01 */ -/* Global Chip-Wide Vendor Interrupt Flags: 1E.FC01 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Chip-Wide Vendor Interrupt Flags */ - union - { - struct - { - /*! \brief 1E.FC01.F RO PMA Vendor Alarm Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.pmaVendorAlarmInterrupt - - - - 1 = Interrupt in PMA vendor specific alarm - - - Notes: - A PMA alarm was generated. ( See PHY XS Vendor Global Interrupt Flags 1- Address 4.F800 ) */ - unsigned int pmaVendorAlarmInterrupt : 1; /* 1E.FC01.F RO */ - /* 1 = Interrupt in PMA vendor specific alarm - */ - /*! \brief 1E.FC01.E RO PCS Vendor Alarm Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.pcsVendorAlarmInterrupt - - - - 1 = Interrupt in PCS vendor specific alarm - - - Notes: - A PCS alarm was generated. ( See PHY XS Vendor Global Interrupt Flags 1- Address 4.F800 ) */ - unsigned int pcsVendorAlarmInterrupt : 1; /* 1E.FC01.E RO */ - /* 1 = Interrupt in PCS vendor specific alarm - */ - /*! \brief 1E.FC01.D RO PHY XS Vendor Alarm Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.phyXS_VendorAlarmInterrupt - - - - 1 = Interrupt in PHY XS vendor specific alarm - - - Notes: - A PHY XS alarm was generated. ( See PHY XS Vendor Global LASI Interrupt Flags 1: Address 4.FC00 ) */ - unsigned int phyXS_VendorAlarmInterrupt : 1; /* 1E.FC01.D RO */ - /* 1 = Interrupt in PHY XS vendor specific alarm - */ - /*! \brief 1E.FC01.C RO Autonegotiation Vendor Alarm Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.autonegotiationVendorAlarmInterrupt - - - - 1 = Interrupt in Autonegotiation vendor specific alarm - - - Notes: - An Autonegotiation alarm was generated. ( See Autonegotiation Vendor Global LASI Interrupt Flags 1: Address 7.FC00 ) */ - unsigned int autonegotiationVendorAlarmInterrupt : 1; /* 1E.FC01.C RO */ - /* 1 = Interrupt in Autonegotiation vendor specific alarm - */ - /*! \brief 1E.FC01.B RO GbE Vendor Alarm Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.gbeVendorAlarmInterrupt - - - - 1 = Interrupt in GbE vendor specific alarm - - - Notes: - A GbE alarm was generated. ( See GbE PHY Vendor Global LASI Interrupt Flags 1: Address 1D.FC00 ) */ - unsigned int gbeVendorAlarmInterrupt : 1; /* 1E.FC01.B RO */ - /* 1 = Interrupt in GbE vendor specific alarm - */ - unsigned int reserved0 : 8; - /*! \brief 1E.FC01.2 RO Global Alarms 1 Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.globalAlarms_1Interrupt - - - - 1 = Interrupt in Global alarms 1 - - - Notes: - An interrupt was generated from status register ( See Global Vendor Alarms 1 - Address 1E.CC00 ) and the corresponding mask register. ( See Global Vendor Interrupt Mask - Address 1E.D400 ) */ - unsigned int globalAlarms_1Interrupt : 1; /* 1E.FC01.2 RO */ - /* 1 = Interrupt in Global alarms 1 - */ - /*! \brief 1E.FC01.1 RO Global Alarms 2 Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.globalAlarms_2Interrupt - - - - 1 = Interrupt in Global alarms 2 - - - Notes: - An interrupt was generated from status register ( See Global Alarms 2: Address 1E.CC01 ) and the corresponding mask register. ( See Global LASI Interrupt Mask 2: Address 1E.D401 ) */ - unsigned int globalAlarms_2Interrupt : 1; /* 1E.FC01.1 RO */ - /* 1 = Interrupt in Global alarms 2 - */ - /*! \brief 1E.FC01.0 RO Global Alarms 3 Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.globalAlarms_3Interrupt - - - - 1 = Interrupt in Global alarms 3 - - - Notes: - An interrupt was generated from status register ( See Global Vendor Alarms 2: Address 1E.CC01 ) and the corresponding mask register. ( See Global LASI Interrupt Mask 2: Address 1E.D401 ) */ - unsigned int globalAlarms_3Interrupt : 1; /* 1E.FC01.0 RO */ - /* 1 = Interrupt in Global alarms 3 - */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalChip_wideVendorInterruptFlags_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Interrupt Chip-Wide Standard Mask: 1E.FF00 */ -/* Global Interrupt Chip-Wide Standard Mask: 1E.FF00 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Interrupt Chip-Wide Standard Mask */ - union - { - struct - { - /*! \brief 1E.FF00.F R/WPD PMA Standard Alarm 1 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.pmaStandardAlarm_1InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int pmaStandardAlarm_1InterruptMask : 1; /* 1E.FF00.F R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.E R/WPD PMA Standard Alarm 2 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.pmaStandardAlarm_2InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int pmaStandardAlarm_2InterruptMask : 1; /* 1E.FF00.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.D R/WPD PCS Standard Alarm 1 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.pcsStandardAlarm_1InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int pcsStandardAlarm_1InterruptMask : 1; /* 1E.FF00.D R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.C R/WPD PCS Standard Alarm 2 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.pcsStandardAlarm_2InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int pcsStandardAlarm_2InterruptMask : 1; /* 1E.FF00.C R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.B R/WPD PCS Standard Alarm 3 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.pcsStandardAlarm_3InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int pcsStandardAlarm_3InterruptMask : 1; /* 1E.FF00.B R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.A R/WPD PHY XS Standard Alarms 1 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.phyXS_StandardAlarms_1InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int phyXS_StandardAlarms_1InterruptMask : 1; /* 1E.FF00.A R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.9 R/WPD PHY XS Standard Alarms 2 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.phyXS_StandardAlarms_2InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int phyXS_StandardAlarms_2InterruptMask : 1; /* 1E.FF00.9 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.8 R/WPD Autonegotiation Standard Alarms 1 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.autonegotiationStandardAlarms_1InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int autonegotiationStandardAlarms_1InterruptMask : 1; /* 1E.FF00.8 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.7 R/WPD Autonegotiation Standard Alarms 2 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.autonegotiationStandardAlarms_2InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int autonegotiationStandardAlarms_2InterruptMask : 1; /* 1E.FF00.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.6 R/WPD Gbe Standard Alarms Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.gbeStandardAlarmsInterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int gbeStandardAlarmsInterruptMask : 1; /* 1E.FF00.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - unsigned int reserved0 : 5; - /*! \brief 1E.FF00.0 R/WPD All Vendor Alarms Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.allVendorAlarmsInterruptMask - - Provisionable Default = 0x1 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int allVendorAlarmsInterruptMask : 1; /* 1E.FF00.0 R/WPD Provisionable Default = 0x1 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalInterruptChip_wideStandardMask_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Interrupt Chip-Wide Vendor Mask: 1E.FF01 */ -/* Global Interrupt Chip-Wide Vendor Mask: 1E.FF01 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Interrupt Chip-Wide Vendor Mask */ - union - { - struct - { - /*! \brief 1E.FF01.F R/WPD PMA Vendor Alarm Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.pmaVendorAlarmInterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int pmaVendorAlarmInterruptMask : 1; /* 1E.FF01.F R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF01.E R/WPD PCS Vendor Alarm Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.pcsVendorAlarmInterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int pcsVendorAlarmInterruptMask : 1; /* 1E.FF01.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF01.D R/WPD PHY XS Vendor Alarm Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.phyXS_VendorAlarmInterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int phyXS_VendorAlarmInterruptMask : 1; /* 1E.FF01.D R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF01.C R/WPD Autonegotiation Vendor Alarm Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.autonegotiationVendorAlarmInterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int autonegotiationVendorAlarmInterruptMask : 1; /* 1E.FF01.C R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF01.B R/WPD GbE Vendor Alarm Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.gbeVendorAlarmInterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int gbeVendorAlarmInterruptMask : 1; /* 1E.FF01.B R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - unsigned int reserved0 : 8; - /*! \brief 1E.FF01.2 R/WPD Global Alarms 1 Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.globalAlarms_1InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int globalAlarms_1InterruptMask : 1; /* 1E.FF01.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF01.1 R/WPD Global Alarms 2 Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.globalAlarms_2InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int globalAlarms_2InterruptMask : 1; /* 1E.FF01.1 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF01.0 R/WPD Global Alarms 3 Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.globalAlarms_3InterruptMask - - Provisionable Default = 0x1 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int globalAlarms_3InterruptMask : 1; /* 1E.FF01.0 R/WPD Provisionable Default = 0x1 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalInterruptChip_wideVendorMask_HHD; - -#endif -/*@}*/ -/*@}*/ diff --git a/qca/aq-fw-download/src/mdioBootLoadCLD.c b/qca/aq-fw-download/src/mdioBootLoadCLD.c deleted file mode 100644 index a8e09d8c9..000000000 --- a/qca/aq-fw-download/src/mdioBootLoadCLD.c +++ /dev/null @@ -1,193 +0,0 @@ -/* mdioBootLoadCLD.c */ - -/************************************************************************************ -* Copyright (c) 2015 Aquantia -* -* Permission to use, copy, modify, and/or distribute this software for any -* purpose with or without fee is hereby granted, provided that the above -* copyright notice and this permission notice appear in all copies. -* -* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -* -* $File: //depot/icm/proj/Dena/rev1.0/c/Systems/tools/windows/flashUtilities/src/mdioBootLoadCLD.c $ -* -* $Revision: #12 $ -* -* $DateTime: 2014/05/19 15:34:49 $ -* -* $Author: joshd $ -* -* $Label: $ -* -************************************************************************************/ - -/*! \file -This file contains the main (int, char**) file for the mdioBootLoadCLD program, which burns a flash image into a target -Aquantia PHY using the AQ_API. This program calls the API function:

    - - uint8_t AQ_API_WriteBootLoadImage (uint8_t PHY_ID, uint8_t *image, uint16_t *crc16)

    - -to boot load a cld flash image into an Aquantia PHY */ - -/*! \addtogroup mdioBootLoad -@{ -*/ - - - -/*! \def DEBUG -Uncomment this to compile in debug mode. This sets the source to an arbitrary file, defined by DEBUG_FILENAME, -and an arbitrary PHY_ID, defined by DEBUG_PHY_ID. */ -/* #define DEBUG */ - -/*! The debug source file name */ -#define DEBUG_FILENAME "HelloWorld.cld" - -/*! The debug PHY ID */ -#define DEBUG_PHY_ID 0 - - -#include -#include -#include -#include -#include -#include -#include -#include - -#include "AQ_API.h" -#include "AQ_PhyInterface.h" - -int sock; -char devname[7]; - -int sock_init() -{ - if ((sock = socket(AF_INET, SOCK_DGRAM, 0)) < 0) { - fprintf(stderr, "Error creating socket: %s\n", strerror(errno)); - return -1; - } - - return 0; -} - -int main ( int argc, char **argp) -{ - /* declare local variables */ - FILE *pFile; - uint8_t* image; - uint8_t byte; - unsigned int PHY_ID; - AQ_Retcode resultCode; - AQ_Retcode resultCodes[4]; - uint32_t i; - uint32_t imageSize; - char sourceFileName[1000]; - AQ_API_Port targetPort0; - AQ_API_Port* targetPorts[1]; - AQ_API_Port broadcastPort; - unsigned int provisioningAddresses[1] = {0}; - uint32_t reg1, reg2; - - targetPorts[0] = &targetPort0; - - if(argc < 4) { - fprintf (stderr, "enter file name/netdev name/phy address\n"); - return (101); - } - - /*Copy the file name from command line arg*/ - if (strlcpy (sourceFileName, argp[1], sizeof(sourceFileName)) >= sizeof(sourceFileName)) { - fprintf (stderr, "Filename: %s too long \n", argp[1]); - return (101); - } - /*Copy the interface name from command line arg*/ - strlcpy (devname, argp[2], sizeof(devname)); - /*Get PHY Address from command line arg*/ - PHY_ID = (unsigned int)strtoul(argp[3], NULL, 0); - - /* FIXME: set port and device type */ - targetPort0.device = AQ_DEVICE_HHD; - targetPort0.PHY_ID = PHY_ID; - - broadcastPort.device = AQ_DEVICE_HHD; - broadcastPort.PHY_ID = PHY_ID; - - /* open the source in binary read mode */ - pFile = fopen(sourceFileName, "rb"); - if (pFile == NULL) - { - fprintf (stderr, "Unable to open source file %s\n", sourceFileName); - return (101); - } - fseek (pFile, 0, SEEK_END); - imageSize = ftell (pFile); - - image = (uint8_t*) malloc (imageSize * sizeof(uint8_t)); - fseek (pFile, 0, SEEK_SET); - - /* load the file */ - for (i = 0; i < imageSize; i++) - { - byte = (uint8_t) fgetc (pFile); - image[i] = byte; - } - fclose(pFile); - - - if (sock_init() < 0) - { - fprintf (stderr, "Unable to initialize interface\n"); - return (200); - } - - /* Write in the Auantia phy scratch pad register, - * read back the same reg and match the values written. - */ - AQ_API_MDIO_Write(PHY_ID, 0x1e, 0x300, 0xdead); - AQ_API_MDIO_Write(PHY_ID, 0x1e, 0x301, 0xbeaf); - reg1 = AQ_API_MDIO_Read(PHY_ID, 0x1e, 0x300); - reg2 = AQ_API_MDIO_Read(PHY_ID, 0x1e, 0x301); - if(reg1 != 0xdead && reg2 != 0xbeaf) { - fprintf (stderr, "Scratchpad Read/Write test fail\n"); - return (101); - } - - /* call the boot-load function */ - resultCode = AQ_API_WriteBootLoadImage(targetPorts, 1, provisioningAddresses, resultCodes, &imageSize, image, PHY_ID, &broadcastPort); - - switch (resultCode) - { - case 0: - printf("Image load good - mailbox CRC-16 matches\n"); - free (image); - close(sock); - return 0; - - case 1: - fprintf (stderr, "CRC-16 on file is bad\n"); - free (image); - close(sock); - return 1; - - case 2: - fprintf (stderr, "CRC-16 check on image load failed (mailbox CRC-16 check)\n"); - free (image); - close(sock); - return 2; - - default: - fprintf (stderr, "Invalid return code\n"); - free (image); - close(sock); - } - return 12; -} -/*@}*/ diff --git a/qca/aq-fw-download/src/src/AQ_API.c b/qca/aq-fw-download/src/src/AQ_API.c deleted file mode 100644 index 89e73344f..000000000 --- a/qca/aq-fw-download/src/src/AQ_API.c +++ /dev/null @@ -1,1021 +0,0 @@ -/*AQ_API.c*/ - -/************************************************************************************ -* Copyright (c) 2015, Aquantia -* -* Permission to use, copy, modify, and/or distribute this software for any -* purpose with or without fee is hereby granted, provided that the above -* copyright notice and this permission notice appear in all copies. -* -* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -* -* Description: -* -* This file contains the code for all of the API functions defined in AQ_API.h -* -************************************************************************************/ - - -/*! \file -* This file contains the code for all of the API functions defined in AQ_API.h - */ - -#include -#include - -#include "AQ_API.h" -#include "AQ_User.h" -#include "AQ_RegMacro.h" -#include "AQ_PlatformRoutines.h" -#include "AQ_RegMaps.h" -#include "AQ_ReturnCodes.h" - -#ifdef AQ_VERBOSE - #include - #include -#endif - - -#ifndef AQ_TIME_T_EXISTS - #ifndef AQ_MDIO_READS_PER_SECOND - #error AQ_MDIO_READS_PER_SECOND in AQ_User.h must be defined, as AQ_TIME_T_EXISTS is currently undefined! - #endif -#endif - -#ifdef AQ_TIME_T_EXISTS - #include -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef AQ_ENABLE_UP_BUSY_CHECKS - #ifdef AQ_VERBOSE - #define AQ_API_UP_BUSY_PRINT_STATEMENT printf("uP-busy check timed out.\n"); - #else - #define AQ_API_UP_BUSY_PRINT_STATEMENT /* nothing */ - #endif - - #ifdef AQ_TIME_T_EXISTS - #define AQ_API_UP_BUSY_TIMEOUT (CLOCKS_PER_SEC / 10) - - #define AQ_API_DECLARE_UP_BUSY_VARS AQ_API_Variable(AQ_GlobalGeneralStatus) \ - uint16_t uPbusy; \ - clock_t startTime; \ - AQ_boolean uPBusyTimeoutOccurred = False; - - #define AQ_API_CHECK_UP_NOT_BUSY AQ_API_Wait(1, port); \ - startTime = clock(); \ - do \ - { \ - AQ_API_Get(port->PHY_ID, AQ_GlobalGeneralStatus, processorIntensiveMdioOperationIn_Progress, uPbusy); \ - if ((clock() - startTime) > AQ_API_UP_BUSY_TIMEOUT) \ - { \ - AQ_API_UP_BUSY_PRINT_STATEMENT \ - uPBusyTimeoutOccurred = True; \ - break; \ - } \ - } while (uPbusy != 0); - #else - #define AQ_API_UP_BUSY_MAX_CHECKS (AQ_MDIO_READS_PER_SECOND * 5) - - #define AQ_API_DECLARE_UP_BUSY_VARS AQ_API_Variable(AQ_GlobalGeneralStatus) \ - uint16_t uPbusy; \ - uint32_t numChecks; \ - AQ_boolean uPBusyTimeoutOccurred = False; - - #define AQ_API_CHECK_UP_NOT_BUSY AQ_API_Wait(1, port); \ - numChecks = 0; \ - do \ - { \ - AQ_API_Get(port->PHY_ID, AQ_GlobalGeneralStatus, processorIntensiveMdioOperationIn_Progress, uPbusy); \ - if (numChecks++ > AQ_API_UP_BUSY_MAX_CHECKS) \ - { \ - AQ_API_UP_BUSY_PRINT_STATEMENT \ - uPBusyTimeoutOccurred = True; \ - break; \ - } \ - } while (uPbusy != 0); - #endif - - /* If a uP busy timeout occurred, return the corresponding return code; otherwise, return - * retval. retval should be a return code defined in AQ_ReturnCodes. */ - #define AQ_API_RETURN_UP_BUSY(retval) return (uPBusyTimeoutOccurred ? AQ_RET_UP_BUSY_TIMEOUT : retval); - -#else - #define AQ_API_DECLARE_UP_BUSY_VARS /* nothing */ - #define AQ_API_CHECK_UP_NOT_BUSY /* nothing */ - #define AQ_API_RETURN_UP_BUSY(retval) return retval; -#endif - - -/*! FW image version string maximum length. */ -#define AQ_VERSION_STRING_SIZE 0x40 - -/*! The byte offset from top of DRAM to the FW image version string. */ -#define AQ_VERSION_STRING_BLOCK_OFFSET 0x0200 - -/*! The byte address, in processor memory, of the start of the IRAM segment. */ -#define AQ_IRAM_BASE_ADDRESS 0x40000000 - -/*! The byte address, in processor memory, of the start of the DRAM segment. */ -#define AQ_DRAM_BASE_ADDRESS 0x3FFE0000 - -/*! The byte offset from the top of the PHY image to the header content (HHD devices). */ -#define AQ_PHY_IMAGE_HEADER_CONTENT_OFFSET_HHD 0x300 - -/*! The byte offset from the top of the PHY image to the header content (APPIA devices). */ -#define AQ_PHY_IMAGE_HEADER_CONTENT_OFFSET_APPIA 0 - -/*! The offset, from the start of DRAM, where the provisioning block begins. */ -#define AQ_PHY_IMAGE_PROVTABLE_OFFSET 0x680 - -/*! The offset, from the start of DRAM, where the provisioning block's ending address is recorded. */ -#define AQ_PHY_IMAGE_PROVTABLE_TERM_OFFSET 0x028C - -/*! The size of the space alloted within the PHY image for the provisioning table. */ -#define AQ_PHY_IMAGE_PROVTABLE_MAXSIZE 0x800 - -/*! The maximum number of polling cycles ever required before the FLASH interface is ready. */ -#define AQ_FLASH_INTERFACE_MAX_POLL_COUNT 20 - -/*! The maximum number of ports that can be MDIO bootloaded at once. */ -#define AQ_MAX_NUM_PHY_IDS 48 - -/*! The maximum allowed number of times to poll for debug-trace-freeze acknowledgement. */ -#define AQ_MAX_FREEZE_CHECKS 2000 - -/*! The maximum size of the debug trace buffer. */ -#define AQ_MAX_TRACE_BUFFER_LENGTH 8192 - -/*! The maximum allowed number of times to poll for SERDES Rx eye measurement done. */ -#define AQ_SERDESEYE_MAX_DONE_CHECKS 50 - -/*! The maximum allowed number of times to poll for PIF mailbox status. */ -#define MAX_NUM_COMMAND_STATUS_POLLS 700 - -/* REGDOC_START */ - - -/********************************************************************************************************************** -* MDIO Boot Load -**********************************************************************************************************************/ - -const uint16_t AQ_CRC16Table[256] = {0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50a5, 0x60c6, 0x70e7, - 0x8108, 0x9129, 0xa14a, 0xb16b, 0xc18c, 0xd1ad, 0xe1ce, 0xf1ef, - 0x1231, 0x0210, 0x3273, 0x2252, 0x52b5, 0x4294, 0x72f7, 0x62d6, - 0x9339, 0x8318, 0xb37b, 0xa35a, 0xd3bd, 0xc39c, 0xf3ff, 0xe3de, - 0x2462, 0x3443, 0x0420, 0x1401, 0x64e6, 0x74c7, 0x44a4, 0x5485, - 0xa56a, 0xb54b, 0x8528, 0x9509, 0xe5ee, 0xf5cf, 0xc5ac, 0xd58d, - 0x3653, 0x2672, 0x1611, 0x0630, 0x76d7, 0x66f6, 0x5695, 0x46b4, - 0xb75b, 0xa77a, 0x9719, 0x8738, 0xf7df, 0xe7fe, 0xd79d, 0xc7bc, - 0x48c4, 0x58e5, 0x6886, 0x78a7, 0x0840, 0x1861, 0x2802, 0x3823, - 0xc9cc, 0xd9ed, 0xe98e, 0xf9af, 0x8948, 0x9969, 0xa90a, 0xb92b, - 0x5af5, 0x4ad4, 0x7ab7, 0x6a96, 0x1a71, 0x0a50, 0x3a33, 0x2a12, - 0xdbfd, 0xcbdc, 0xfbbf, 0xeb9e, 0x9b79, 0x8b58, 0xbb3b, 0xab1a, - 0x6ca6, 0x7c87, 0x4ce4, 0x5cc5, 0x2c22, 0x3c03, 0x0c60, 0x1c41, - 0xedae, 0xfd8f, 0xcdec, 0xddcd, 0xad2a, 0xbd0b, 0x8d68, 0x9d49, - 0x7e97, 0x6eb6, 0x5ed5, 0x4ef4, 0x3e13, 0x2e32, 0x1e51, 0x0e70, - 0xff9f, 0xefbe, 0xdfdd, 0xcffc, 0xbf1b, 0xaf3a, 0x9f59, 0x8f78, - 0x9188, 0x81a9, 0xb1ca, 0xa1eb, 0xd10c, 0xc12d, 0xf14e, 0xe16f, - 0x1080, 0x00a1, 0x30c2, 0x20e3, 0x5004, 0x4025, 0x7046, 0x6067, - 0x83b9, 0x9398, 0xa3fb, 0xb3da, 0xc33d, 0xd31c, 0xe37f, 0xf35e, - 0x02b1, 0x1290, 0x22f3, 0x32d2, 0x4235, 0x5214, 0x6277, 0x7256, - 0xb5ea, 0xa5cb, 0x95a8, 0x8589, 0xf56e, 0xe54f, 0xd52c, 0xc50d, - 0x34e2, 0x24c3, 0x14a0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405, - 0xa7db, 0xb7fa, 0x8799, 0x97b8, 0xe75f, 0xf77e, 0xc71d, 0xd73c, - 0x26d3, 0x36f2, 0x0691, 0x16b0, 0x6657, 0x7676, 0x4615, 0x5634, - 0xd94c, 0xc96d, 0xf90e, 0xe92f, 0x99c8, 0x89e9, 0xb98a, 0xa9ab, - 0x5844, 0x4865, 0x7806, 0x6827, 0x18c0, 0x08e1, 0x3882, 0x28a3, - 0xcb7d, 0xdb5c, 0xeb3f, 0xfb1e, 0x8bf9, 0x9bd8, 0xabbb, 0xbb9a, - 0x4a75, 0x5a54, 0x6a37, 0x7a16, 0x0af1, 0x1ad0, 0x2ab3, 0x3a92, - 0xfd2e, 0xed0f, 0xdd6c, 0xcd4d, 0xbdaa, 0xad8b, 0x9de8, 0x8dc9, - 0x7c26, 0x6c07, 0x5c64, 0x4c45, 0x3ca2, 0x2c83, 0x1ce0, 0x0cc1, - 0xef1f, 0xff3e, 0xcf5d, 0xdf7c, 0xaf9b, 0xbfba, 0x8fd9, 0x9ff8, - 0x6e17, 0x7e36, 0x4e55, 0x5e74, 0x2e93, 0x3eb2, 0x0ed1, 0x1ef0}; - -/*! \addtogroup writingImages - @{ -*/ - -/*! Prepare the specified port for MDIO bootloading. Disables the daisy-chain, - * and explicitly sets the port's provisioningAddress. */ -void AQ_API_EnableMDIO_BootLoadMode -( - /*! The target PHY port.*/ - AQ_API_Port* port, - /*! The provisioning address to use when the FW starts and applies the - * bootloaded image's provisioned values. */ - unsigned int provisioningAddress -) -{ - AQ_API_Variable(AQ_GlobalNvrProvisioning) - - AQ_API_DeclareLocalStruct(AQ_GlobalReservedProvisioning, globalReservedProvisioning) - - - /* disable the daisy-chain */ - /* REGDOC: Read-Modify-Write bitfield (HHD/APPIA: 1E.C452.0) */ - AQ_API_Set(port->PHY_ID, AQ_GlobalNvrProvisioning, nvrDaisyChainDisable, 1); - - /* override the hop-count */ - AQ_API_AssignWordOfLocalStruct(globalReservedProvisioning, 1, - /* REGDOC: Read register (HHD/APPIA: 1E.C470 + 1) */ - AQ_API_ReadRegister(port->PHY_ID, AQ_GlobalReservedProvisioning, 1)); - /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C471.5:0) */ - AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalReservedProvisioning, globalReservedProvisioning, - daisy_chainHop_countOverrideValue, provisioningAddress); - /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C471.6) */ - AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalReservedProvisioning, globalReservedProvisioning, - enableDaisy_chainHop_countOverride, 1); - /* REGDOC: Write register (HHD/APPIA: 1E.C470 + 1) */ - AQ_API_WriteRegister(port->PHY_ID, AQ_GlobalReservedProvisioning, 1, - AQ_API_WordOfLocalStruct(globalReservedProvisioning, 1)); - - return; -} - - -/*! Prepare the specified port for MDIO bootloading, and set the temporary MDIO - * address to be used during the bootload process. Disables the daisy-chain, - * and explicitly sets the port's provisioningAddress. */ -void AQ_API_EnableGangLoadMode -( - /*! The target PHY port.*/ - AQ_API_Port* port, - /*! The provisioning address to use when the FW starts and applies the - * bootloaded image's provisioned values. */ - unsigned int provisioningAddress, - /*! The PHY's MDIO address will be changed to this value during the - * bootload process. */ - unsigned int gangLoadAddress -) -{ - /*AQ_API_Variable_DeviceRestricted(APPIA, AQ_GlobalGeneralProvisioning)*/ - AQ_API_Variable(AQ_GlobalGeneralProvisioning) - - - /* Get ready for MDIO bootloading. */ - AQ_API_EnableMDIO_BootLoadMode(port, provisioningAddress); - - /* Enable gangload mode. After doing this, the PHY will be - * addressable at the MDIO address indicated by gangLoadAddress. - * Now that the PHY is in gangload mode, MDIO reads are prohibited - * until AQ_API_DisableGangLoadMode is called. */ - if (AQ_DEVICE_APPIA == port->device) - { - /* REGDOC: Read-Modify-Write bitfield (APPIA: 1E.C440.8:4) */ - AQ_API_Set_DeviceRestricted(APPIA, port->PHY_ID, AQ_GlobalGeneralProvisioning, - gangLoadMdioAddress, gangLoadAddress); - } - else if (AQ_DEVICE_HHD == port->device) - { - /* REGDOC: Read-Modify-Write bitfield (HHD: 1E.C447.4:0) */ - AQ_API_Set_DeviceRestricted(HHD, port->PHY_ID, AQ_GlobalGeneralProvisioning, - mdioBroadcastAddressConfiguration, gangLoadAddress); - /* REGDOC: Read-Modify-Write bitfield (HHD: 1E.C441.E) */ - AQ_API_Set_DeviceRestricted(HHD, port->PHY_ID, AQ_GlobalGeneralProvisioning, - mdioBroadcastModeEnable, 1); - } - - return; -} - - -/*! Restore the PHY's MDIO address to the pin-specified value. Should be - * called when MDIO bootloading is complete, to return to normal MDIO - * addressing. - * This is a gang-load function, hence write-only! */ -void AQ_API_DisableGangLoadMode -( - /*! The target PHY port.*/ - AQ_API_Port* port, - /*! The value to write to of AQ_GlobalGeneralProvisioning.u1.word_1. */ - uint16_t origVal_GGP1 -) -{ - AQ_API_DeclareLocalStruct(AQ_GlobalGeneralProvisioning, globalGeneralProvisioning) - - - /* Restore the original value of globalGeneralProvisioning.u1, and set - * the MDIO address reset bit. This will cause the MDIO address to be - * reset to the value indicated by the pins. */ - AQ_API_AssignWordOfLocalStruct(globalGeneralProvisioning, 1, origVal_GGP1); - if (AQ_DEVICE_APPIA == port->device) - { - /* REGDOC: Assign to local representation of bitfield (APPIA: 1E.C441.2) */ - AQ_API_AssignBitfieldOfLocalStruct_DeviceRestricted(APPIA, AQ_GlobalGeneralProvisioning, - globalGeneralProvisioning, mdioAddressReset, 1); - } - else if (AQ_DEVICE_HHD == port->device) - { - /* REGDOC: Assign to local representation of bitfield (HHD: 1E.C441.E) */ - AQ_API_AssignBitfieldOfLocalStruct_DeviceRestricted(HHD, AQ_GlobalGeneralProvisioning, - globalGeneralProvisioning, mdioBroadcastModeEnable, 0); - } - /* REGDOC: Write register (HHD/APPIA: 1E.C440 + 1) */ - AQ_API_WriteRegister(port->PHY_ID, AQ_GlobalGeneralProvisioning, 1, - AQ_API_WordOfLocalStruct(globalGeneralProvisioning, 1)); - - /* The PHY has now exited gang-load mode. */ - return; -} - - -AQ_Retcode AQ_API_WriteBootLoadImageWithProvTable -( - AQ_API_Port** ports, - unsigned int numPorts, - unsigned int* provisioningAddresses, - AQ_Retcode* resultCodes, - uint32_t* imageSizePointer, - uint8_t* image, - uint8_t gangload_MDIO_address, - AQ_API_Port* gangloadPort, - uint32_t* provTableSizePointer, - uint8_t* provTableImage -) -{ - /*------------------------------------- NOTE!!!!!!!!!! ----------------------------------------------------------*/ - /* This function uses word level writes here as in gang-load mode we cannot do a read in a read-modify-write */ - /* operation */ - /*---------------------------------------------------------------------------------------------------------------*/ - - AQ_API_Variable_DeviceRestricted(APPIA, AQ_GlobalPinStatus) - - AQ_API_DeclareLocalStruct(AQ_GlobalControl, globalControl) - AQ_API_DeclareLocalStruct(AQ_GlobalMailboxInterface, globalMailboxInterface) - - AQ_API_Port* port; - uint32_t primaryHeaderPtr = 0x00000000; - uint32_t primaryIramPtr = 0x00000000; - uint32_t primaryDramPtr = 0x00000000; - uint32_t primaryIramSize = 0x00000000; - uint32_t primaryDramSize = 0x00000000; - uint32_t terminatorPtr = 0x00000000; - uint32_t phyImageHeaderContentOffset; - uint32_t i; - uint32_t j; - uint32_t imageSize; - uint32_t provTableImageSize = 0; - uint32_t bytePointer; - uint32_t byteSize; - uint32_t dWordSize; -#ifdef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE - uint32_t countPendingOps; /* A count of block MDIO operation pending... necessary to keep a count - in order to ensure we don't exceed the maximum pending operations. */ -#endif - uint16_t msw; - uint16_t lsw; - uint16_t crc16Calculated; - uint16_t provTableCrc16Calculated; - uint16_t fileCRC; - uint16_t provTableFileCRC; - uint16_t mailboxCRC; - uint16_t mailboxWrite; - uint16_t bootLoadMode; - uint16_t recordedGGP1Values[AQ_MAX_NUM_PHY_IDS]; /* When entering/exiting gangload mode, we record and restore - the AQ_GlobalGeneralProvisioning.u1 register values. */ - - - /* store the CRC-16 for the image, which is the last two bytes */ - imageSize = *imageSizePointer; - fileCRC = image[imageSize-2] << 8 | image[imageSize-1]; - - /*------------------------------------- Check the image integrity ------------------------------------------------*/ - crc16Calculated = 0x0000; - for (i = 0; i < imageSize-2; i++) - { - crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ image[i]]; - } - - if (crc16Calculated != fileCRC) - { - #ifdef AQ_VERBOSE - printf ("CRC check failed on image file (expected 0x%X, found 0x%X)\n", - fileCRC, crc16Calculated); - #endif - for (j = 0; j < numPorts; j++) - { - /* Before returning, set ALL result codes to indicate "bad image". */ - resultCodes[j] = AQ_RET_FLASH_IMAGE_CORRUPT; - } - return AQ_RET_ERROR; - } -#ifdef AQ_VERBOSE - else - { - printf ("CRC check good on image file (0x%04X)\n", crc16Calculated); - } -#endif - - /*-------------------------------- Check the provisioning table image integrity ----------------------------------*/ - if (provTableSizePointer != NULL && provTableImage != NULL) - { - provTableImageSize = (*provTableSizePointer) - 2; - provTableFileCRC = provTableImage[provTableImageSize + 1] << 8 | - provTableImage[provTableImageSize]; - - provTableCrc16Calculated = 0x0000; - for (i = 0; i < provTableImageSize; i++) - { - provTableCrc16Calculated = ((provTableCrc16Calculated & 0xFF) << 8) ^ - AQ_CRC16Table[(provTableCrc16Calculated >> 8) ^ provTableImage[i]]; - } - - if (provTableCrc16Calculated != provTableFileCRC) - { - #ifdef AQ_VERBOSE - printf ("CRC check failed on provisioning table file (expected 0x%X, found 0x%X)\n", - provTableFileCRC, provTableCrc16Calculated); - #endif - for (j = 0; j < numPorts; j++) - { - /* Before returning, set ALL result codes to indicate "bad image". */ - resultCodes[j] = AQ_RET_FLASH_IMAGE_CORRUPT; - } - return AQ_RET_ERROR; - } - #ifdef AQ_VERBOSE - else - { - printf ("CRC check good on provisioning table file (0x%04X)\n", - provTableCrc16Calculated); - } - #endif - } - - /*------------------------ Check that all provisioning addresses are in the proper range. ------------------------*/ - for (j = 0; j < numPorts; j++) - { - if (provisioningAddresses[j] > 47) - { - #ifdef AQ_VERBOSE - printf ("Provisioning address out of range 0-47 (index %u: %d)\n", j, provisioningAddresses[j]); - #endif - for (j = 0; j < numPorts; j++) - { - /* Before returning, set ALL result codes to indicate "provisioning address out-of-range". */ - resultCodes[j] = AQ_RET_BOOTLOAD_PROVADDR_OOR; - } - return AQ_RET_ERROR; - } - } - - /*--------------------------- Store 1E.C441 values for later use. Enforce uniformity. ---------------------------*/ - for (j = 0; j < numPorts; j++) - { - /* Record the original value of AQ_GlobalGeneralProvisioning.u1.word_1, - * so that we can restore it later after exiting gangload mode. */ - port = ports[j]; - /* REGDOC: Read register (HHD/APPIA: 1E.C440 + 1) */ - recordedGGP1Values[j] = AQ_API_ReadRegister(port->PHY_ID, AQ_GlobalGeneralProvisioning, 1); - - /* If any of the PHYs' GGP1 values don't match the others, set the appropriate - * error code and return. */ - if (j > 0 && recordedGGP1Values[j] != recordedGGP1Values[0]) - { - #ifdef AQ_VERBOSE - printf ("Non-uniform value of 1E.C441 found (expected 0x%X, found 0x%X)\n", - recordedGGP1Values[0], recordedGGP1Values[j]); - #endif - for (j = 0; j < numPorts; j++) - { - /* Before returning, set ALL result codes to indicate "non-uniform GGP1 values". */ - resultCodes[j] = AQ_RET_BOOTLOAD_NONUNIFORM_REGVALS; - } - return AQ_RET_ERROR; - } - } - - /*--------------------------- Put each PHY into gangload mode at the specified address ---------------------------*/ - for (j = 0; j < numPorts; j++) - { - AQ_API_EnableGangLoadMode(ports[j], provisioningAddresses[j], gangload_MDIO_address); - } - /* Set up the port context for using device-restricted macros while in - * gangload mode. */ - port = gangloadPort; - - /*------------------------------------- Stall the uP ------------------------------------------------------------*/ - AQ_API_AssignWordOfLocalStruct(globalControl, 1, 0x0000); - /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.6) */ - AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upRunStallOverride, 1); - /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.0) */ - AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upRunStall, 1); - /* REGDOC: Write register (HHD/APPIA: 1E.C000 + 1) */ - AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalControl, 1, - AQ_API_WordOfLocalStruct(globalControl, 1)); - - /*------------------------------------- Initialize the mailbox write command -------------------------------------*/ - AQ_API_AssignWordOfLocalStruct(globalMailboxInterface, 0, 0x0000); - /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.0200.E) */ - AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalMailboxInterface, globalMailboxInterface, upMailboxWriteMode, 1); - /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.0200.F) */ - AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalMailboxInterface, globalMailboxInterface, upMailboxExecuteOperation, 1); - mailboxWrite = AQ_API_WordOfLocalStruct(globalMailboxInterface, 0); - - /*------------------------------------- Read the segment addresses and sizes -------------------------------------*/ - primaryHeaderPtr = (((image[0x9] & 0x0F) << 8) | image[0x8]) << 12; - - if (AQ_DEVICE_APPIA == port->device) - phyImageHeaderContentOffset = AQ_PHY_IMAGE_HEADER_CONTENT_OFFSET_APPIA; - else /* HHD */ - phyImageHeaderContentOffset = AQ_PHY_IMAGE_HEADER_CONTENT_OFFSET_HHD; - - primaryIramPtr = (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0x4 + 2] << 16) | - (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0x4 + 1] << 8) | - image[primaryHeaderPtr + phyImageHeaderContentOffset + 0x4]; - primaryIramSize = (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0x7 + 2] << 16) | - (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0x7 + 1] << 8) | - image[primaryHeaderPtr + phyImageHeaderContentOffset + 0x7]; - primaryDramPtr = (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0xA + 2] << 16) | - (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0xA + 1] << 8) | - image[primaryHeaderPtr + phyImageHeaderContentOffset + 0xA]; - primaryDramSize = (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0xD + 2] << 16) | - (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0xD + 1] << 8) | - image[primaryHeaderPtr + phyImageHeaderContentOffset + 0xD]; - - if (AQ_DEVICE_HHD == port->device) - { - primaryIramPtr += primaryHeaderPtr; - primaryDramPtr += primaryHeaderPtr; - } - -#ifdef AQ_VERBOSE - printf ("\nSegment Addresses and Sizes as read from the PHY ROM image header:\n\n"); - printf ("Primary Iram Address: 0x%x\n", primaryIramPtr); - printf ("Primary Iram Size: 0x%x\n", primaryIramSize); - printf ("Primary Dram Address: 0x%x\n", primaryDramPtr); - printf ("Primary Dram Size: 0x%x\n\n", primaryDramSize); -#endif - - /*----------------------------- Merge the provisioning table into the main image ---------------------------------*/ - if (provTableSizePointer != NULL && provTableImage != NULL) - { - /* Locate the terminator of the built-in provisioning table */ - terminatorPtr = primaryDramPtr + - ((image[primaryDramPtr + AQ_PHY_IMAGE_PROVTABLE_TERM_OFFSET + 1] << 8) | - image[primaryDramPtr + AQ_PHY_IMAGE_PROVTABLE_TERM_OFFSET]); - - #ifdef AQ_VERBOSE - printf("Supplied Provisioning Table At Address: 0x%x\n\n", terminatorPtr); - #endif - - /* Check that the supplied provisioning table will fit within the alloted - * space. */ - if (terminatorPtr - (primaryDramPtr + AQ_PHY_IMAGE_PROVTABLE_OFFSET) + - provTableImageSize > AQ_PHY_IMAGE_PROVTABLE_MAXSIZE) - { - for (j = 0; j < numPorts; j++) - { - /* Before returning, set ALL result codes to indicate "provisioning - * table too large". */ - resultCodes[j] = AQ_RET_BOOTLOAD_PROVTABLE_TOO_LARGE; - } - return AQ_RET_ERROR; - } - - /* Write the supplied provisioning table into the image, starting at the - * terminator address. */ - for (i = 0; i < provTableImageSize; i++) - { - image[terminatorPtr + i] = provTableImage[i]; - } - } - - /*------------------------------------- Load IRAM and DRAM -------------------------------------------------------*/ - /* clear the mailbox CRC */ - AQ_API_AssignWordOfLocalStruct(globalMailboxInterface, 0, 0x0000); - /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.0200.C) */ - AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalMailboxInterface, globalMailboxInterface, resetUpMailboxCrc, 1); - /* REGDOC: Write register (HHD/APPIA: 1E.0200) */ - AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, - AQ_API_WordOfLocalStruct(globalMailboxInterface, 0)); - /* REGDOC: Write register (HHD/APPIA: 1E.0200) */ - AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, 0x0000); - - crc16Calculated = 0; /* This is to calculate what was written through the mailbox */ - - /* load the IRAM */ -#ifdef AQ_VERBOSE - printf ("\nLoading IRAM:\n\n"); -#endif - - /* dWord align the address: note the image addressing is byte based, but is properly aligned on dWord - boundaries, so the 2 LSbits of the block start are always zero. */ - msw = (uint16_t) (AQ_IRAM_BASE_ADDRESS >> 16); - AQ_API_AssignWordOfLocalStruct(globalMailboxInterface, 3, 0x0000); - /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.0203.1:0) */ - AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalMailboxInterface, globalMailboxInterface, - upMailboxAddressLSW , (AQ_IRAM_BASE_ADDRESS & 0xFFFF) >> 2); - lsw = AQ_API_WordOfLocalStruct(globalMailboxInterface, 3); - /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 2) */ - AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 2, msw); /* MSW */ - /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 3) */ - AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 3, lsw); /* LSW */ - - - /* set block size so that there are from 0-3 bytes remaining */ - byteSize = primaryIramSize; - dWordSize = byteSize >> 2; - - bytePointer = primaryIramPtr; -#ifdef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE - countPendingOps = 0; -#endif - for (i = 0; i < dWordSize; i++) - { - /* write 4 bytes of data */ - lsw = (image[bytePointer+1] << 8) | image[bytePointer]; - bytePointer += 2; - msw = (image[bytePointer+1] << 8) | image[bytePointer]; - bytePointer += 2; - - #ifdef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE - AQ_API_BlockWriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 4, msw); - AQ_API_BlockWriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 5, lsw); - AQ_API_BlockWriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, mailboxWrite); - - countPendingOps += 3; - /* Check if we've filled our output buffer, and if so, flush. */ - if (countPendingOps >= AQ_API_MDIO_MaxBlockOperations() - 3 ) - { - AQ_API_MDIO_BlockOperationExecute (gangloadPort->PHY_ID); - countPendingOps = 0; - } - #else - /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 4) */ - AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 4, msw); - /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 5) */ - AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 5, lsw); - /* REGDOC: Write register (HHD/APPIA: 1E.0200) */ - AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, mailboxWrite); - #endif - - /* update the calculated CRC */ - crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (msw >> 8)]; - crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (msw & 0xFF)]; - crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (lsw >> 8)]; - crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (lsw & 0xFF)]; - - #ifdef AQ_VERBOSE - if (i && ((i % 512) == 0)) printf(" Byte: %X:\n", i << 2); - #endif - } - -#ifdef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE - /* flush the output buffer one last time. */ - AQ_API_MDIO_BlockOperationExecute(gangloadPort->PHY_ID); - countPendingOps = 0; -#endif - - /* Note: this final write right-justifies non-dWord data in the final dWord */ - switch (byteSize & 0x3) - { - case 0x1: - /* write 1 byte of data */ - lsw = image[bytePointer++]; - msw = 0x0000; - /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 4) */ - AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 4, msw); - /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 5) */ - AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 5, lsw); - - /* no polling */ - /* REGDOC: Write register (HHD/APPIA: 1E.0200) */ - AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, mailboxWrite); - break; - - case 0x2: - /* write 2 bytes of data */ - lsw = (image[bytePointer+1] << 8) | image[bytePointer]; - bytePointer += 2; - msw = 0x0000; - /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 4) */ - AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 4, msw); - /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 5) */ - AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 5, lsw); - - /* no polling */ - /* REGDOC: Write register (HHD/APPIA: 1E.0200) */ - AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, mailboxWrite); - break; - - case 0x3: - /* write 3 bytes of data */ - lsw = (image[bytePointer+1] << 8) | image[bytePointer]; - bytePointer += 2; - msw = image[bytePointer++]; - /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 4) */ - AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 4, msw); - /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 5) */ - AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 5, lsw); - - /* no polling */ - /* REGDOC: Write register (HHD/APPIA: 1E.0200) */ - AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, mailboxWrite); - break; - } - - if (byteSize & 0x3) - { - /* update the calculated CRC */ - crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (msw >> 8)]; - crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (msw & 0xFF)]; - crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (lsw >> 8)]; - crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (lsw & 0xFF)]; - } - - /* load the DRAM */ -#ifdef AQ_VERBOSE - printf ("\nCRC-16 after loading IRAM: 0x%X\n", crc16Calculated); - printf ("\nLoading DRAM:\n\n"); -#endif - - /* dWord align the address: note the image addressing is byte based, but is properly aligned on dWord - boundaries, so the 2 LSbits of the block start are always zero. */ - msw = (uint16_t) (AQ_DRAM_BASE_ADDRESS >> 16); - AQ_API_AssignWordOfLocalStruct(globalMailboxInterface, 3, 0x0000); - /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.0203.1:0) */ - AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalMailboxInterface, globalMailboxInterface, - upMailboxAddressLSW, (AQ_DRAM_BASE_ADDRESS & 0xFFFF) >> 2); - lsw = AQ_API_WordOfLocalStruct(globalMailboxInterface, 3); - /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 2) */ - AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 2, msw); /* MSW */ - /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 3) */ - AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 3, lsw); /* LSW */ - - - /* set block size so that there are from 0-3 bytes remaining */ - byteSize = primaryDramSize; - dWordSize = byteSize >> 2; - - bytePointer = primaryDramPtr; - for (i = 0; i < dWordSize; i++) - { - /* write 4 bytes of data */ - lsw = (image[bytePointer+1] << 8) | image[bytePointer]; - bytePointer += 2; - msw = (image[bytePointer+1] << 8) | image[bytePointer]; - bytePointer += 2; - - #ifdef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE - AQ_API_BlockWriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 4, msw); - AQ_API_BlockWriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 5, lsw); - AQ_API_BlockWriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, mailboxWrite); - - countPendingOps += 3; - /* Check if we've filled our output buffer, and if so, flush. */ - if (countPendingOps >= AQ_API_MDIO_MaxBlockOperations() - 3 ) - { - AQ_API_MDIO_BlockOperationExecute (gangloadPort->PHY_ID); - countPendingOps = 0; - } - #else - /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 4) */ - AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 4, msw); - /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 5) */ - AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 5, lsw); - /* REGDOC: Write register (HHD/APPIA: 1E.0200) */ - AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, mailboxWrite); - #endif - - /* update the calculated CRC */ - crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (msw >> 8)]; - crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (msw & 0xFF)]; - crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (lsw >> 8)]; - crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (lsw & 0xFF)]; - - #ifdef AQ_VERBOSE - if (i && ((i % 512) == 0)) printf(" Byte: %X:\n", i << 2); - #endif - } - -#ifdef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE - /* flush the output buffer one last time. */ - AQ_API_MDIO_BlockOperationExecute(gangloadPort->PHY_ID); - countPendingOps = 0; -#endif - - /* Note: this final write right-justifies non-dWord data in the final dWord */ - switch (byteSize & 0x3) - { - case 0x1: - /* write 1 byte of data */ - lsw = image[bytePointer++]; - msw = 0x0000; - /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 4) */ - AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 4, msw); - /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 5) */ - AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 5, lsw); - - /* no polling */ - /* REGDOC: Write register (HHD/APPIA: 1E.0200) */ - AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, mailboxWrite); - break; - - case 0x2: - /* write 2 bytes of data */ - lsw = (image[bytePointer+1] << 8) | image[bytePointer]; - bytePointer += 2; - msw = 0x0000; - /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 4) */ - AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 4, msw); - /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 5) */ - AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 5, lsw); - - /* no polling */ - /* REGDOC: Write register (HHD/APPIA: 1E.0200) */ - AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, mailboxWrite); - break; - - case 0x3: - /* write 3 bytes of data */ - lsw = (image[bytePointer+1] << 8) | image[bytePointer]; - bytePointer += 2; - msw = image[bytePointer++]; - /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 4) */ - AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 4, msw); - /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 5) */ - AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 5, lsw); - - /* no polling */ - /* REGDOC: Write register (HHD/APPIA: 1E.0200) */ - AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, mailboxWrite); - break; - } - - if (byteSize & 0x3) - { - /* update the calculated CRC */ - crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (msw >> 8)]; - crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (msw & 0xFF)]; - crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (lsw >> 8)]; - crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (lsw & 0xFF)]; - } - - /*------------------------------------- Exit gangload mode -------------------------------------------------------*/ - AQ_API_DisableGangLoadMode(gangloadPort, recordedGGP1Values[0]); - - /*------------------------------------- Check mailbox CRCs -------------------------------------------------------*/ - /* check to make sure the mailbox CRC matches the calculated CRC */ - /*foundMailboxCRCMismatch = False;*/ - for (j = 0; j < numPorts; j++) - { - /* REGDOC: Read register (HHD/APPIA: 1E.0200 + 1) */ - mailboxCRC = AQ_API_ReadRegister(ports[j]->PHY_ID,AQ_GlobalMailboxInterface, 1); - if (mailboxCRC != crc16Calculated) - { - #ifdef AQ_VERBOSE - printf("\n%uth port: Mailbox CRC-16 (0x%X) does not match calculated CRC-16 (0x%X)\n", - j, mailboxCRC, crc16Calculated); - #endif - /* Note that we can't just return here, because we still need to - * release the uPs for the other PHYs that might have been - * bootloaded successfully. */ - resultCodes[j] = AQ_RET_BOOTLOAD_CRC_MISMATCH; - } - #ifdef AQ_VERBOSE - else - { - printf("\n%uth port: Image load good - mailbox CRC-16 matches (0x%X)\n", - j, mailboxCRC); - resultCodes[j] = AQ_RET_OK; - } - #endif - } - - /*------------------------------------- Clear any resets ---------------------------------------------------------*/ - for (j = 0; j < numPorts; j++) - { - /* REGDOC: Write register (HHD/APPIA: 1E.0000) */ - AQ_API_WriteRegister(ports[j]->PHY_ID,AQ_GlobalStandardControl_1, 0, 0x0000); - } - - /*------------------------------------- Release the uP -----------------------------------------------------------*/ - AQ_API_AssignWordOfLocalStruct(globalControl, 1, 0x0000); - /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.6) */ - AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upRunStallOverride, 1); - /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.0) */ - AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upRunStall, 1); - for (j = 0; j < numPorts; j++) - { - /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.F) */ - AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upReset, 0); - /* REGDOC: Write register (HHD/APPIA: 1E.C000 + 1) */ - AQ_API_WriteRegister(ports[j]->PHY_ID,AQ_GlobalControl, 1, - AQ_API_WordOfLocalStruct(globalControl, 1)); - /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.F) */ - AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upReset, 1); - /* REGDOC: Write register (HHD/APPIA: 1E.C000 + 1) */ - AQ_API_WriteRegister(ports[j]->PHY_ID,AQ_GlobalControl, 1, - AQ_API_WordOfLocalStruct(globalControl, 1)); - } - - /* Need to wait at least 100us. */ - AQ_API_Wait(1, ports[0]); - - /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.F) */ - AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upReset, 0); - /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.0) */ - AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upRunStall, 0); - for (j = 0; j < numPorts; j++) - { - if (AQ_DEVICE_APPIA == port->device) - { - /* If the BOOT_LD pins are set to MDIO boot load mode, we can't clear the - * uP run stall override bit. If we did, the uP would stall. */ - /* REGDOC: Read bitfield (APPIA: 1E.C840.E:D) */ - AQ_API_Get_DeviceRestricted(APPIA, j, AQ_GlobalPinStatus, mdioBootLoad, bootLoadMode); - if (bootLoadMode == 0x1) - { - /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.6) */ - AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upRunStallOverride, 1); - } - else - { - /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.6) */ - AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upRunStallOverride, 0); - } - } - else - { - /* For post-APPIA devices, always set the uP stall override bit to - * smooth over any packaging differences WRT the boot load pin. */ - /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.6) */ - AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upRunStallOverride, 1); - } - - /* REGDOC: Write register (HHD/APPIA: 1E.C000 + 1) */ - AQ_API_WriteRegister(ports[j]->PHY_ID,AQ_GlobalControl, 1, - AQ_API_WordOfLocalStruct(globalControl, 1)); - } - - /* NOTE!!! We can't re-enable the daisy-chain here, as this will overwrite the IRAM and DRAM with the FLASH contents*/ - - /* If any of the ports was not bootloaded successfully, return AQ_RET_ERROR */ - for (j = 0; j < numPorts; j++) - { - if (resultCodes[j] != AQ_RET_OK) - return AQ_RET_ERROR; - } - - /* All ports were bootloaded successfully. */ - return AQ_RET_OK; -} - - -AQ_Retcode AQ_API_WriteBootLoadImage -( - AQ_API_Port** ports, - unsigned int numPorts, - unsigned int* provisioningAddresses, - AQ_Retcode* resultCodes, - uint32_t* imageSizePointer, - uint8_t* image, - uint8_t gangload_MDIO_address, - AQ_API_Port* gangloadPort -) -{ - return AQ_API_WriteBootLoadImageWithProvTable(ports, numPorts, - provisioningAddresses, resultCodes, imageSizePointer, image, - gangload_MDIO_address, gangloadPort, NULL, NULL); -} - - -AQ_Retcode AQ_API_EnableDaisyChain -( - /*! The target PHY port.*/ - AQ_API_Port* port -) -{ - - /* declare local variables */ - AQ_API_Variable(AQ_GlobalNvrProvisioning) - AQ_API_Variable(AQ_GlobalReservedProvisioning) - - /* disable the hop-count override */ - /* REGDOC: Read-Modify-Write bitfield (HHD/APPIA: 1E.C471.6) */ - AQ_API_Set(port->PHY_ID, AQ_GlobalReservedProvisioning, enableDaisy_chainHop_countOverride, 0); - - /* enable the daisy-chain */ - /* REGDOC: Read-Modify-Write bitfield (HHD/APPIA: 1E.C452.0) */ - AQ_API_Set(port->PHY_ID, AQ_GlobalNvrProvisioning, nvrDaisyChainDisable, 0); - - return AQ_RET_OK; -} - -/*@}*/ - - -#ifdef __cplusplus -} -#endif diff --git a/qca/aq-fw-download/src/src/AQ_PhyInterface.c b/qca/aq-fw-download/src/src/AQ_PhyInterface.c deleted file mode 100644 index 6a8fce125..000000000 --- a/qca/aq-fw-download/src/src/AQ_PhyInterface.c +++ /dev/null @@ -1,141 +0,0 @@ -/* AQ_PhyInterface.c */ - -/************************************************************************************ -* Copyright (c) 2015, Aquantia -* -* Permission to use, copy, modify, and/or distribute this software for any -* purpose with or without fee is hereby granted, provided that the above -* copyright notice and this permission notice appear in all copies. -* -* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -* -* $Revision: #12 $ -* -* $DateTime: 2015/02/25 15:34:49 $ -* -* $Label: $ -* -************************************************************************************/ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include - -#include "AQ_PhyInterface.h" -#include "AQ_PlatformRoutines.h" - -#define MII_ADDR_C45 (0x8000) - -extern int sock; -extern char devname[7]; - -static struct ifreq ifr; - -/*! Provides generic synchronous PHY register write functionality. It is the - * responsibility of the system designer to provide the specific MDIO address - * pointer updates, etc. in order to accomplish this write operation. - * It will be assumed that the write has been completed by the time this - * function returns.*/ -void AQ_API_MDIO_Write( - /*! Uniquely identifies the port within the system. AQ_Port must be - * defined to a whatever data type is suitable for the platform.*/ - AQ_Port PHY_ID, - /*! The address of the MMD within the target PHY. */ - unsigned int MMD, - /*! The 16-bit address of the PHY register being written. */ - unsigned int address, - /*! The 16-bits of data to write to the specified PHY register. */ - unsigned int data) -{ - struct mii_ioctl_data mii; - - /* - * Frame the control structures - * and send the ioctl to kernel. - */ - memset(&ifr, 0, sizeof(ifr)); - strlcpy(ifr.ifr_name, devname, sizeof(ifr.ifr_name)); - memset(&mii, 0, sizeof(mii)); - memcpy(&mii, &ifr.ifr_data, sizeof(mii)); - mii.phy_id = MII_ADDR_C45 | PHY_ID << 5 | MMD; - mii.reg_num = address; - mii.val_in = data; - memcpy(&ifr.ifr_data, &mii, sizeof(mii)); - - if (ioctl(sock, SIOCSMIIREG, &ifr) < 0) { - fprintf(stderr, "SIOCSMIIREG on %s failed: %s\n", ifr.ifr_name, - strerror(errno)); - } - - return; -} - -/*! Provides generic synchronous PHY register read functionality. It is the - * responsibility of the system designer to provide the specific MDIO address - * pointer updates, etc. in order to accomplish this read operation.*/ -unsigned int AQ_API_MDIO_Read -( - /*! Uniquely identifies the port within the system. AQ_Port must be - * defined to a whatever data type is suitable for the platform.*/ - AQ_Port PHY_ID, - /*! The address of the MMD within the target PHY. */ - unsigned int MMD, - /*! The 16-bit address of the PHY register being read. */ - unsigned int address) -{ - struct mii_ioctl_data mii; - - /* - * Frame the control structures - * and send the ioctl to kernel. - */ - memset(&ifr, 0, sizeof(ifr)); - strlcpy(ifr.ifr_name, devname, sizeof(ifr.ifr_name)); - memset(&mii, 0, sizeof(mii)); - memcpy(&mii, &ifr.ifr_data, sizeof(mii)); - mii.phy_id = MII_ADDR_C45 | PHY_ID << 5 | MMD; - mii.reg_num = address; - memcpy(&ifr.ifr_data, &mii, sizeof(mii)); - - if (ioctl(sock, SIOCGMIIREG, &ifr) < 0) { - fprintf(stderr, "SIOCGMIIREG on %s failed: %s\n", ifr.ifr_name, - strerror(errno)); - return -1; - } else { - memcpy(&mii, &ifr.ifr_data, sizeof(mii)); - } - - - return mii.val_out; -} - -/*! Returns after at least milliseconds have elapsed. This must be implemented - * * in a platform-approriate way. AQ_API functions will call this function to - * * block for the specified period of time. If necessary, PHY register reads - * * may be performed on port to busy-wait. */ -void AQ_API_Wait( - uint32_t milliseconds, /*!< The delay in milliseconds */ - AQ_API_Port* port /*!< The PHY to use if delay reads are necessary*/ ) -{ - unsigned long long mirco = milliseconds *1000; - usleep(mirco); -} diff --git a/qca/nss-eip-firmware/Makefile b/qca/nss-eip-firmware/Makefile deleted file mode 100644 index a20c9afd6..000000000 --- a/qca/nss-eip-firmware/Makefile +++ /dev/null @@ -1,34 +0,0 @@ -include $(TOPDIR)/rules.mk - -PKG_NAME:=nss-eip-firmware -PKG_VERSION=2.5.7 -PKG_RELEASE:=$(AUTORELEASE) - -PKG_MAINTAINER:=Robert Marko - -include $(INCLUDE_DIR)/package.mk - -define Package/nss-eip-firmware - SECTION:=firmware - CATEGORY:=Firmware - TITLE:=NSS EIP-197 firmware - DEPENDS:=@(TARGET_ipq807x||TARGET_ipq60xx) -endef - -define Build/Compile - -endef - -define Package/nss-eip-firmware/install - $(INSTALL_DIR) $(1)/lib/firmware/ - $(INSTALL_DATA) \ - $(PKG_BUILD_DIR)/ifpp.bin $(1)/lib/firmware/ifpp.bin - $(INSTALL_DATA) \ - $(PKG_BUILD_DIR)/ipue.bin $(1)/lib/firmware/ipue.bin - $(INSTALL_DATA) \ - $(PKG_BUILD_DIR)/ofpp.bin $(1)/lib/firmware/ofpp.bin - $(INSTALL_DATA) \ - $(PKG_BUILD_DIR)/opue.bin $(1)/lib/firmware/opue.bin -endef - -$(eval $(call BuildPackage,nss-eip-firmware)) diff --git a/qca/nss-eip-firmware/src/.gitkeep b/qca/nss-eip-firmware/src/.gitkeep deleted file mode 100644 index e69de29bb..000000000 diff --git a/qca/nss-firmware/Makefile b/qca/nss-firmware/Makefile deleted file mode 100644 index eff44a8fb..000000000 --- a/qca/nss-firmware/Makefile +++ /dev/null @@ -1,72 +0,0 @@ -# -# Copyright (C) 2021 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# - -include $(TOPDIR)/rules.mk - -PKG_NAME:=nss-firmware -PKG_SOURCE_DATE:=2022-05-16 -PKG_SOURCE_VERSION:=20c9a9b7e0ea2935b0a54f112104e433009312ca -PKG_MIRROR_HASH:=376b3605776f75bccb1da2b30dd522cc22d3f6b17dff6c954dd9b7222418d6c6 -PKG_RELEASE:=$(AUTORELEASE) - -PKG_SOURCE_PROTO:=git -PKG_SOURCE_URL:=https://github.com/quic/qca-sdk-nss-fw.git - -PKG_LICENSE_FILES:=LICENSE.md - -PKG_MAINTAINER:=Robert Marko - -include $(INCLUDE_DIR)/package.mk - -VERSION_PATH=$(PKG_BUILD_DIR)/QCA_Networking.SPF_11.5.0/CS - -define Package/nss-firmware-default - SECTION:=firmware - CATEGORY:=Firmware - URL:=$(PKG_SOURCE_URL) - DEPENDS:=@(TARGET_ipq807x||TARGET_ipq60xx) -endef - -define Package/nss-firmware-ipq6018 -$(Package/nss-firmware-default) - TITLE:=NSS firmware for IPQ6018 devices - NSS_ARCHIVE:=$(VERSION_PATH)/IPQ6018.ATH.11.4/BIN-NSS.CP.11.4.0.5-5-R.tar.bz2 -endef - -define Package/nss-firmware-ipq8074 -$(Package/nss-firmware-default) - TITLE:=NSS firmware for IPQ8074 devices - NSS_ARCHIVE:=$(VERSION_PATH)/IPQ8074.ATH.11.5.0/BIN-NSS.FW.12.0.r1-002-HK.R.tar.bz2 -endef - -define Build/Compile - -endef - -define Package/nss-firmware-ipq6018/install - mkdir -p $(PKG_BUILD_DIR)/IPQ6018 - $(TAR) -C $(PKG_BUILD_DIR)/IPQ6018 -xf $(NSS_ARCHIVE) --strip-components=1 - $(INSTALL_DIR) $(1)/lib/firmware/ - $(INSTALL_DATA) \ - $(PKG_BUILD_DIR)/IPQ6018/retail_router0.bin \ - $(1)/lib/firmware/qca-nss0-retail.bin -endef - -define Package/nss-firmware-ipq8074/install - mkdir -p $(PKG_BUILD_DIR)/IPQ8074 - $(TAR) -C $(PKG_BUILD_DIR)/IPQ8074 -xf $(NSS_ARCHIVE) --strip-components=1 - $(INSTALL_DIR) $(1)/lib/firmware/ - $(INSTALL_DATA) \ - $(PKG_BUILD_DIR)/IPQ8074/retail_router0.bin \ - $(1)/lib/firmware/qca-nss0-retail.bin - $(INSTALL_DATA) \ - $(PKG_BUILD_DIR)/IPQ8074/retail_router1.bin \ - $(1)/lib/firmware/qca-nss1-retail.bin -endef - -$(eval $(call BuildPackage,nss-firmware-ipq6018)) -$(eval $(call BuildPackage,nss-firmware-ipq8074)) diff --git a/qca/qca-nss-cfi/Makefile b/qca/qca-nss-cfi/Makefile deleted file mode 100644 index 64f7bd7ab..000000000 --- a/qca/qca-nss-cfi/Makefile +++ /dev/null @@ -1,71 +0,0 @@ -include $(TOPDIR)/rules.mk - -PKG_NAME:=qca-nss-cfi -PKG_RELEASE:=1 - -PKG_SOURCE_PROTO:=git -PKG_SOURCE_DATE:=2021-03-22 -PKG_SOURCE_URL:=https://source.codeaurora.org/quic/qsdk/oss/lklm/nss-cfi -PKG_SOURCE_VERSION:=73f2e5f5bf93cc244036ce5641faf9f859692cdf -PKG_MIRROR_HASH:=8c8edc9b8d8c68fdd14640152245013a93c123957b6b338c06f266f6c9db8cbd - -include $(INCLUDE_DIR)/kernel.mk -include $(INCLUDE_DIR)/package.mk - -# v1.0 is for Akronite -# v2.0 is for Hawkeye/Cypress/Maple -ifneq (, $(findstring $(BOARD), ipq50xx ipq60xx ipq807x)) - CFI_OCF_DIR:=ocf/v2.0 - CFI_CRYPTOAPI_DIR:=cryptoapi/v2.0 -else - CFI_CRYPTOAPI_DIR:=cryptoapi/v1.1 - CFI_OCF_DIR:=ocf/v1.0 - CFI_IPSEC_DIR:=ipsec/v1.0 -endif - -define KernelPackage/qca-nss-cfi-cryptoapi - SECTION:=kernel - CATEGORY:=Kernel modules - SUBMENU:=Network Devices - DEPENDS:=@TARGET_ipq60xx +kmod-crypto-authenc +kmod-qca-nss-crypto - TITLE:=Kernel driver for NSS cfi - FILES:=$(PKG_BUILD_DIR)/$(CFI_CRYPTOAPI_DIR)/qca-nss-cfi-cryptoapi.ko - AUTOLOAD:=$(call AutoLoad,59,qca-nss-cfi-cryptoapi) -endef - -define Build/InstallDev - $(INSTALL_DIR) $(1)/usr/include/qca-nss-cfi - $(CP) $(PKG_BUILD_DIR)/$(CFI_CRYPTOAPI_DIR)/../exports/* $(1)/usr/include/qca-nss-cfi - $(CP) $(PKG_BUILD_DIR)/include/* $(1)/usr/include/qca-nss-cfi -endef - -define KernelPackage/qca-nss-cfi/Description -This package contains a NSS cfi driver for QCA chipset -endef - -EXTRA_CFLAGS+= \ - -DCONFIG_NSS_DEBUG_LEVEL=4 \ - -I$(LINUX_DIR)/crypto/ocf \ - -I$(STAGING_DIR)/usr/include/qca-nss-crypto \ - -I$(STAGING_DIR)/usr/include/crypto \ - -I$(STAGING_DIR)/usr/include/qca-nss-drv - -ifneq (, $(findstring $(BOARD), ipq50xx ipq60xx ipq807x)) -EXTRA_CFLAGS+= -I$(STAGING_DIR)/usr/include/qca-nss-clients -endif - -define Build/Compile - $(MAKE) -C "$(LINUX_DIR)" \ - CROSS_COMPILE="$(TARGET_CROSS)" \ - EXTRA_CFLAGS="$(EXTRA_CFLAGS)" \ - CFI_CRYPTOAPI_DIR=$(CFI_CRYPTOAPI_DIR) \ - CFI_IPSEC_DIR=$(CFI_IPSEC_DIR) \ - CFI_OCF_DIR=$(CFI_OCF_DIR) \ - $(KERNEL_MAKE_FLAGS) \ - M="$(PKG_BUILD_DIR)" \ - SoC="$(BOARD)_64" \ - "cryptoapi=y" \ - modules -endef - -$(eval $(call KernelPackage,qca-nss-cfi-cryptoapi)) diff --git a/qca/qca-nss-cfi/patches/100-remove-noise-logs.patch b/qca/qca-nss-cfi/patches/100-remove-noise-logs.patch deleted file mode 100644 index 085aeaf24..000000000 --- a/qca/qca-nss-cfi/patches/100-remove-noise-logs.patch +++ /dev/null @@ -1,30 +0,0 @@ ---- a/cryptoapi/v2.0/nss_cryptoapi_ahash.c -+++ b/cryptoapi/v2.0/nss_cryptoapi_ahash.c -@@ -449,9 +449,12 @@ int nss_cryptoapi_ahash_digest(struct ahash_request *req) - int nss_cryptoapi_ahash_export(struct ahash_request *req, void *out) - { - struct nss_cryptoapi_ctx *ctx __attribute__((unused)) = crypto_tfm_ctx(req->base.tfm); -+ struct nss_cryptoapi_req_ctx *rctx = ahash_request_ctx(req); -+ struct nss_cryptoapi_req_ctx *state = out; -+ -+ *state = *rctx; - -- nss_cfi_warn("%px: ahash .export is not supported", ctx); -- return -ENOSYS; -+ return 0; - }; - - /* -@@ -464,7 +467,10 @@ int nss_cryptoapi_ahash_export(struct ahash_request *req, void *out) - int nss_cryptoapi_ahash_import(struct ahash_request *req, const void *in) - { - struct nss_cryptoapi_ctx *ctx __attribute__((unused)) = crypto_tfm_ctx(req->base.tfm); -+ struct nss_cryptoapi_req_ctx *rctx = ahash_request_ctx(req); -+ const struct nss_cryptoapi_req_ctx *state = in; -+ -+ *rctx = *state; - -- nss_cfi_warn("%px: ahash .import is not supported", ctx); -- return -ENOSYS; -+ return 0; - } diff --git a/qca/qca-nss-clients/Makefile b/qca/qca-nss-clients/Makefile deleted file mode 100644 index 274512780..000000000 --- a/qca/qca-nss-clients/Makefile +++ /dev/null @@ -1,102 +0,0 @@ -include $(TOPDIR)/rules.mk - -PKG_NAME:=qca-nss-clients -PKG_RELEASE:=$(AUTORELEASE) - -PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/nss-clients.git -PKG_SOURCE_PROTO:=git -PKG_SOURCE_DATE:=2021-07-23 -PKG_SOURCE_VERSION:=ec7a57bed8914adcbd5bf95de1f0b630296489c1 -PKG_MIRROR_HASH:=b7413c5b20a341d3d7ea49c1b86ff92b4a8795aa7c64986ca820ba18205e332d - -include $(INCLUDE_DIR)/kernel.mk -include $(INCLUDE_DIR)/package.mk - -define KernelPackage/qca-nss-drv-pppoe - SECTION:=kernel - CATEGORY:=Kernel modules - SUBMENU:=Network Devices - TITLE:=Kernel driver for NSS (connection manager) - PPPoE - DEPENDS:=@LINUX_5_10 @TARGET_ipq807x +kmod-qca-nss-drv +kmod-ppp +kmod-pppoe - FILES:=$(PKG_BUILD_DIR)/pppoe/qca-nss-pppoe.ko - AUTOLOAD:=$(call AutoLoad,51,qca-nss-pppoe) -endef - -define KernelPackage/qca-nss-drv-pppoe/Description -Kernel modules for NSS connection manager - Support for PPPoE -endef - -define KernelPackage/qca-nss-drv-bridge-mgr - SECTION:=kernel - CATEGORY:=Kernel modules - SUBMENU:=Network Devices - TITLE:=Kernel driver for NSS bridge manager - DEPENDS:=@LINUX_5_10 @TARGET_ipq807x +kmod-qca-nss-drv +kmod-qca-nss-drv-vlan-mgr - FILES:=$(PKG_BUILD_DIR)/bridge/qca-nss-bridge-mgr.ko - AUTOLOAD:=$(call AutoLoad,51,qca-nss-bridge-mgr) -endef - -define KernelPackage/qca-nss-drv-bridge-mgr/Description -Kernel modules for NSS bridge manager -endef - -define KernelPackage/qca-nss-drv-vlan-mgr - SECTION:=kernel - CATEGORY:=Kernel modules - SUBMENU:=Network Devices - TITLE:=Kernel driver for NSS vlan manager - DEPENDS:=@LINUX_5_10 @TARGET_ipq807x +kmod-qca-nss-drv - FILES:=$(PKG_BUILD_DIR)/vlan/qca-nss-vlan.ko - AUTOLOAD:=$(call AutoLoad,51,qca-nss-vlan) -endef - -define KernelPackage/qca-nss-drv-vlan-mgr/Description -Kernel modules for NSS vlan manager -endef - -EXTRA_CFLAGS+= \ - -I$(STAGING_DIR)/usr/include/qca-nss-drv \ - -I$(STAGING_DIR)/usr/include/qca-nss-crypto \ - -I$(STAGING_DIR)/usr/include/qca-nss-cfi \ - -I$(STAGING_DIR)/usr/include/qca-nss-gmac \ - -I$(STAGING_DIR)/usr/include/qca-ssdk \ - -I$(STAGING_DIR)/usr/include/qca-ssdk/fal \ - -I$(STAGING_DIR)/usr/include/nat46 - -ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-pppoe),) -NSS_CLIENTS_MAKE_OPTS+=pppoe=y -endif - -ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-bridge-mgr),) -NSS_CLIENTS_MAKE_OPTS+=bridge-mgr=y -#enable OVS bridge if ovsmgr is enabled -ifneq ($(CONFIG_PACKAGE_kmod-qca-ovsmgr),) -NSS_CLIENTS_MAKE_OPTS+= NSS_BRIDGE_MGR_OVS_ENABLE=y -EXTRA_CFLAGS+= -I$(STAGING_DIR)/usr/include/qca-ovsmgr -endif -endif - -ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-vlan-mgr),) -NSS_CLIENTS_MAKE_OPTS+=vlan-mgr=y -endif - -ifeq ($(CONFIG_TARGET_BOARD), "ipq807x") - SOC="ipq807x_64" -else ifeq ($(CONFIG_TARGET_BOARD), "ipq60xx") - SOC="ipq60xx_64" -endif - -define Build/Compile - $(MAKE) -C "$(LINUX_DIR)" $(strip $(NSS_CLIENTS_MAKE_OPTS)) \ - CROSS_COMPILE="$(TARGET_CROSS)" \ - ARCH="$(LINUX_KARCH)" \ - M="$(PKG_BUILD_DIR)" \ - EXTRA_CFLAGS="$(EXTRA_CFLAGS)" \ - SoC=$(SOC) \ - $(KERNEL_MAKE_FLAGS) \ - modules -endef - -$(eval $(call KernelPackage,qca-nss-drv-pppoe)) -$(eval $(call KernelPackage,qca-nss-drv-bridge-mgr)) -$(eval $(call KernelPackage,qca-nss-drv-vlan-mgr)) diff --git a/qca/qca-nss-clients/files/qca-nss-ipsec b/qca/qca-nss-clients/files/qca-nss-ipsec deleted file mode 100644 index 5f682c8e9..000000000 --- a/qca/qca-nss-clients/files/qca-nss-ipsec +++ /dev/null @@ -1,214 +0,0 @@ -#!/bin/sh /etc/rc.common -# -# Copyright (c) 2018-2019, 2021 The Linux Foundation. All rights reserved. -# -# Permission to use, copy, modify, and/or distribute this software for any -# purpose with or without fee is hereby granted, provided that the above -# copyright notice and this permission notice appear in all copies. -# -# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - -NSS_IPSEC_LOG_FILE=/tmp/.nss_ipsec_log -NSS_IPSEC_LOG_STR_ECM="ECM_Loaded" -NSS_IPSEC_OL_FILE=/tmp/qca_nss_ipsec_ol - -ecm_load () { - if [ ! -d /sys/module/ecm ]; then - /etc/init.d/qca-nss-ecm start - if [ -d /sys/module/ecm ]; then - echo ${NSS_IPSEC_LOG_STR_ECM} >> ${NSS_IPSEC_LOG_FILE} - fi - fi -} - -ecm_unload () { - if [ -f /tmp/.nss_ipsec_log ]; then - str=`grep ${NSS_IPSEC_LOG_STR_ECM} ${NSS_IPSEC_LOG_FILE}` - if [[ $str == ${NSS_IPSEC_LOG_STR_ECM} ]]; then - /etc/init.d/qca-nss-ecm stop - `sed 's/${NSS_IPSEC_LOG_STR_ECM}/ /g' $NSS_IPSEC_LOG_FILE > $NSS_IPSEC_LOG_FILE` - fi - fi -} - -ecm_disable() { - - if [ ! -d /sys/module/ecm ]; then - return; - fi - - echo 1 > /sys/kernel/debug/ecm/front_end_ipv4_stop - echo 1 > /sys/kernel/debug/ecm/front_end_ipv6_stop - echo 1 > /sys/kernel/debug/ecm/ecm_db/defunct_all - sleep 2 -} - -ecm_enable() { - if [ ! -d /sys/module/ecm ]; then - return; - fi - - echo 0 > /sys/kernel/debug/ecm/ecm_db/defunct_all - echo 0 > /sys/kernel/debug/ecm/front_end_ipv4_stop - echo 0 > /sys/kernel/debug/ecm/front_end_ipv6_stop -} - -kernel_version_check_5_4() { - major_ver=$(uname -r | awk -F '.' '{print $1}') - minor_ver=$(uname -r | awk -F '.' '{print $2}') - if [ $major_ver -lt 5 ] || ([ $major_ver -eq 5 ] && [ $minor_ver -lt 4 ] ) ; then - return 1 - else - return 0 - fi -} - -start_klips() { - if kernel_version_check_5_4 - then - echo "Kernel 5.4 doesn't support klips stack." - return $? - fi - - touch $NSS_IPSEC_OL_FILE - ecm_load - - local kernel_version=$(uname -r) - - insmod /lib/modules/${kernel_version}/qca-nss-ipsec-klips.ko - if [ "$?" -gt 0 ]; then - echo "Failed to load plugin. Please start ecm if not done already" - ecm_enable - rm $NSS_IPSEC_OL_FILE - return - fi - - /etc/init.d/ipsec start - sleep 2 - ipsec eroute - - ecm_enable -} - -stop_klips() { - if kernel_version_check_5_4 - then - echo "Kernel 5.4 doesn't support klips stack." - return $? - fi - - ecm_disable - - /etc/init.d/ipsec stop - rmmod qca-nss-ipsec-klips - rm $NSS_IPSEC_OL_FILE - - ecm_unload -} - -start_xfrm() { - touch $NSS_IPSEC_OL_FILE - ecm_load - - local kernel_version=$(uname -r) - - # load all NETKEY modules first. - for mod in xfrm_ipcomp ipcomp xfrm6_tunnel ipcomp6 xfrm6_mode_tunnel xfrm6_mode_beet xfrm6_mode_ro \ - xfrm6_mode_transport xfrm4_mode_transport xfrm4_mode_tunnel \ - xfrm4_tunnel xfrm4_mode_beet esp4 esp6 ah4 ah6 af_key - do - insmod $mod 2> /dev/null - done - - # Now load the xfrm plugin - insmod /lib/modules/${kernel_version}/qca-nss-ipsec-xfrm.ko - if [ "$?" -gt 0 ]; then - echo "Failed to load plugin. Please start ecm if not done already" - ecm_enable - rm $NSS_IPSEC_OL_FILE - return - fi - - /etc/init.d/ipsec start - sleep 2 - - ecm_enable -} - -stop_xfrm() { - ecm_disable - - #Shutdown Pluto first. Then only plugin can be removed. - plutopid=/var/run/pluto/pluto.pid - if [ -f $plutopid ]; then - pid=`cat $plutopid` - if [ ! -z "$pid" ]; then - ipsec whack --shutdown | grep -v "002"; - if [ -s $plutopid ]; then - echo "Attempt to shut Pluto down failed! Trying kill:" - kill $pid; - sleep 5; - fi - fi - rm -rf $plutopid - fi - ip xfrm state flush; - ip xfrm policy flush; - sleep 2 - - #Now we can remove the plugin - retries=5 - while [ -d /sys/module/qca_nss_ipsec_xfrm ] - do - rmmod qca-nss-ipsec-xfrm - if [ "$?" -eq 0 ]; then - rm $NSS_IPSEC_OL_FILE - break - fi - - if [ ${retries} -eq 0 ]; then - echo "Failed to unload qca-nss-ipsec-xfrm plugin!" - exit - fi - - echo "XFRM plugin unload failed; retrying ${retries} times" - sleep 1 - retries=`expr ${retries} - 1` - done - - /etc/init.d/ipsec stop - ecm_unload -} - -start() { - local protostack=`uci -q get ipsec.setup.protostack` - if [ "$protostack" = "klips" ]; then - start_klips - return $? - fi - - start_xfrm - return $? -} - -stop() { - local protostack=`uci -q get ipsec.setup.protostack` - if [ "$protostack" = "klips" ]; then - stop_klips - return $? - fi - - stop_xfrm - return $? -} - -restart() { - stop - start -} diff --git a/qca/qca-nss-clients/files/qca-nss-mirred.init b/qca/qca-nss-clients/files/qca-nss-mirred.init deleted file mode 100644 index 1f931f090..000000000 --- a/qca/qca-nss-clients/files/qca-nss-mirred.init +++ /dev/null @@ -1,28 +0,0 @@ -#!/bin/sh /etc/rc.common - -########################################################################### -# Copyright (c) 2019, The Linux Foundation. All rights reserved. -# Permission to use, copy, modify, and/or distribute this software for -# any purpose with or without fee is hereby granted, provided that the -# above copyright notice and this permission notice appear in all copies. -# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT -# OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -########################################################################### - -restart() { - rmmod act_nssmirred.ko - insmod act_nssmirred.ko -} - -start() { - insmod act_nssmirred.ko -} - -stop() { - rmmod act_nssmirred.ko -} diff --git a/qca/qca-nss-clients/files/qca-nss-ovpn.init b/qca/qca-nss-clients/files/qca-nss-ovpn.init deleted file mode 100644 index 622e295ee..000000000 --- a/qca/qca-nss-clients/files/qca-nss-ovpn.init +++ /dev/null @@ -1,69 +0,0 @@ -#!/bin/sh /etc/rc.common - -########################################################################### -# Copyright (c) 2019, The Linux Foundation. All rights reserved. -# Permission to use, copy, modify, and/or distribute this software for -# any purpose with or without fee is hereby granted, provided that the -# above copyright notice and this permission notice appear in all copies. -# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT -# OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -########################################################################### - -ecm_disable() { - if [ ! -d /sys/module/ecm ]; then - return - fi - - echo 1 > /sys/kernel/debug/ecm/front_end_ipv4_stop - echo 1 > /sys/kernel/debug/ecm/front_end_ipv6_stop - echo 1 > /sys/kernel/debug/ecm/ecm_db/defunct_all - sleep 2 -} - -ecm_enable() { - if [ ! -d /sys/module/ecm ]; then - return - fi - - echo 0 > /sys/kernel/debug/ecm/ecm_db/defunct_all - echo 0 > /sys/kernel/debug/ecm/front_end_ipv4_stop - echo 0 > /sys/kernel/debug/ecm/front_end_ipv6_stop -} - -restart() { - ecm_disable - - /etc/init.d/openvpn stop - rmmod qca-nss-ovpn-link - rmmod qca-nss-ovpn-mgr - - insmod qca-nss-ovpn-mgr - insmod qca-nss-ovpn-link - - if [ "$?" -gt 0 ]; then - echo "Failed to load plugin. Please start ecm if not done already" - ecm_enable - return - fi - - ecm_enable -} - -start() { - restart -} - -stop() { - ecm_disable - - /etc/init.d/openvpn stop - rmmod qca-nss-ovpn-link - rmmod qca-nss-ovpn-mgr - - ecm_enable -} diff --git a/qca/qca-nss-crypto/Makefile b/qca/qca-nss-crypto/Makefile deleted file mode 100644 index 5c1003b89..000000000 --- a/qca/qca-nss-crypto/Makefile +++ /dev/null @@ -1,72 +0,0 @@ -include $(TOPDIR)/rules.mk - -PKG_NAME:=qca-nss-crypto -PKG_RELEASE:=$(AUTORELEASE) - -PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/nss-crypto.git -PKG_SOURCE_PROTO:=git -PKG_SOURCE_DATE:=2021-03-20 -PKG_SOURCE_VERSION:=2271a3a66f7e8284d42a9e787ddec6f24a1d2e15 -PKG_MIRROR_HASH:=afd2b746779bf9abb72dfb58c755acf54d1cb51085b879013dd0edf9ba98d3c9 - -PKG_BUILD_PARALLEL:=1 - -include $(INCLUDE_DIR)/kernel.mk -include $(INCLUDE_DIR)/package.mk - -ifeq ($(CONFIG_TARGET_BOARD), "ipq807x") - SOC="ipq807x_64" -else ifeq ($(CONFIG_TARGET_BOARD), "ipq60xx") - SOC="ipq60xx_64" -endif - -# v1.0 is for Akronite -# v2.0 is for Hawkeye/Cypress/Maple -ifneq (, $(findstring $(CONFIG_TARGET_BOARD), "ipq807x" "ipq60xx")) -NSS_CRYPTO_DIR:=v2.0 -else -NSS_CRYPTO_DIR:=v1.0 -endif - -define KernelPackage/qca-nss-crypto - SECTION:=kernel - CATEGORY:=Kernel modules - SUBMENU:=Cryptographic API modules - DEPENDS:=@(TARGET_ipq807x||TARGET_ipq60xx) +kmod-qca-nss-drv +nss-eip-firmware - TITLE:=Kernel driver for NSS crypto driver - FILES:=$(PKG_BUILD_DIR)/$(NSS_CRYPTO_DIR)/src/qca-nss-crypto.ko \ - $(PKG_BUILD_DIR)/$(NSS_CRYPTO_DIR)/tool/qca-nss-crypto-tool.ko - AUTOLOAD:=$(call AutoLoad,52,qca-nss-crypto) -endef - -define KernelPackage/qca-nss-crypto/Description -This package contains a NSS crypto driver for QCA chipset -endef - -define Build/InstallDev - $(INSTALL_DIR) $(1)/usr/include/qca-nss-crypto - $(CP) $(PKG_BUILD_DIR)/$(NSS_CRYPTO_DIR)/include/* $(1)/usr/include/qca-nss-crypto -endef - -EXTRA_CFLAGS+= \ - -DCONFIG_NSS_DEBUG_LEVEL=4 \ - -I$(STAGING_DIR)/usr/include/qca-nss-crypto \ - -I$(STAGING_DIR)/usr/include/qca-nss-drv \ - -I$(PKG_BUILD_DIR)/$(NSS_CRYPTO_DIR)/include \ - -I$(PKG_BUILD_DIR)/$(NSS_CRYPTO_DIR)/src - -define Build/Compile - +$(MAKE) -C "$(LINUX_DIR)" \ - CC="$(TARGET_CC)" \ - CROSS_COMPILE="$(TARGET_CROSS)" \ - ARCH="$(LINUX_KARCH)" \ - M="$(PKG_BUILD_DIR)" \ - EXTRA_CFLAGS="$(EXTRA_CFLAGS)" \ - NSS_CRYPTO_DIR=$(NSS_CRYPTO_DIR) \ - SoC=$(SOC) \ - $(KERNEL_MAKE_FLAGS) \ - $(PKG_JOBS) \ - modules -endef - -$(eval $(call KernelPackage,qca-nss-crypto)) diff --git a/qca/qca-nss-crypto/patches/0001-nss-crypto-fix-SHA1-header-include.patch b/qca/qca-nss-crypto/patches/0001-nss-crypto-fix-SHA1-header-include.patch deleted file mode 100644 index 757b172ea..000000000 --- a/qca/qca-nss-crypto/patches/0001-nss-crypto-fix-SHA1-header-include.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 68b7776673aabc2f93bd75e73ef4b45a1ac561d9 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Sun, 13 Mar 2022 13:44:47 +0100 -Subject: [PATCH 1/3] nss-crypto: fix SHA1 header include - -SHA1 header has been merged to the generic SHA one, -and with that the cryptohash.h was dropped. - -So, fix include in kernels 5.8 and newer. - -Signed-off-by: Robert Marko ---- - v2.0/src/nss_crypto_hlos.h | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/v2.0/src/nss_crypto_hlos.h b/v2.0/src/nss_crypto_hlos.h -index 84740c2..e827f4f 100644 ---- a/v2.0/src/nss_crypto_hlos.h -+++ b/v2.0/src/nss_crypto_hlos.h -@@ -55,7 +55,9 @@ - #include - #include - #include -+#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 8, 0) - #include -+#endif - #include - #include - #include --- -2.35.1 - diff --git a/qca/qca-nss-crypto/patches/0002-nss-crypto-replace-ioremap_nocache-with-ioremap.patch b/qca/qca-nss-crypto/patches/0002-nss-crypto-replace-ioremap_nocache-with-ioremap.patch deleted file mode 100644 index 8c829c11e..000000000 --- a/qca/qca-nss-crypto/patches/0002-nss-crypto-replace-ioremap_nocache-with-ioremap.patch +++ /dev/null @@ -1,69 +0,0 @@ -From 80393ab565e26d572de56b7502b069b0a944bd40 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Tue, 8 Jun 2021 22:14:34 +0200 -Subject: [PATCH 2/3] nss-crypto: replace ioremap_nocache() with ioremap - -ioremap_nocache() was dropped in kernel 5.5 as regular -ioremap() was exactly the same. - -So, simply replace all of the ioremap_nocache() calls -with ioremap(). - -Signed-off-by: Robert Marko ---- - v2.0/src/hal/ipq50xx/nss_crypto_ce5.c | 4 ++-- - v2.0/src/hal/ipq60xx/nss_crypto_eip197.c | 2 +- - v2.0/src/hal/ipq807x/nss_crypto_eip197.c | 2 +- - 3 files changed, 4 insertions(+), 4 deletions(-) - -diff --git a/v2.0/src/hal/ipq50xx/nss_crypto_ce5.c b/v2.0/src/hal/ipq50xx/nss_crypto_ce5.c -index c89cd38..a7a46e0 100644 ---- a/v2.0/src/hal/ipq50xx/nss_crypto_ce5.c -+++ b/v2.0/src/hal/ipq50xx/nss_crypto_ce5.c -@@ -288,7 +288,7 @@ int nss_crypto_ce5_engine_init(struct platform_device *pdev, struct resource *cr - * remap the I/O addresses for crypto - */ - eng->crypto_paddr = crypto_res->start; -- eng->crypto_vaddr = ioremap_nocache(crypto_res->start, resource_size(crypto_res)); -+ eng->crypto_vaddr = ioremap(crypto_res->start, resource_size(crypto_res)); - if (!eng->crypto_vaddr) { - nss_crypto_warn("%px: unable to remap crypto_addr(0x%px)\n", node, (void *)eng->crypto_paddr); - nss_crypto_engine_free(eng); -@@ -299,7 +299,7 @@ int nss_crypto_ce5_engine_init(struct platform_device *pdev, struct resource *cr - * remap the I/O addresses for bam - */ - eng->dma_paddr = bam_res->start; -- eng->dma_vaddr = ioremap_nocache(bam_res->start, resource_size(bam_res)); -+ eng->dma_vaddr = ioremap(bam_res->start, resource_size(bam_res)); - if (!eng->dma_vaddr) { - iounmap(eng->crypto_vaddr); - nss_crypto_warn("%px: unable to remap dma_addr(0x%px)\n", node, (void *)eng->dma_paddr); -diff --git a/v2.0/src/hal/ipq60xx/nss_crypto_eip197.c b/v2.0/src/hal/ipq60xx/nss_crypto_eip197.c -index 8dfc35d..79649f9 100644 ---- a/v2.0/src/hal/ipq60xx/nss_crypto_eip197.c -+++ b/v2.0/src/hal/ipq60xx/nss_crypto_eip197.c -@@ -490,7 +490,7 @@ int nss_crypto_eip197_engine_init(struct platform_device *pdev, struct device_no - * remap the I/O addresses - */ - paddr = res->start + offset; -- vaddr = ioremap_nocache(paddr, resource_size(res)); -+ vaddr = ioremap(paddr, resource_size(res)); - if (!vaddr) { - nss_crypto_warn("%px: unable to remap crypto_addr(0x%px)\n", node, (void *)paddr); - return -EIO; -diff --git a/v2.0/src/hal/ipq807x/nss_crypto_eip197.c b/v2.0/src/hal/ipq807x/nss_crypto_eip197.c -index 632adca..5e2c146 100644 ---- a/v2.0/src/hal/ipq807x/nss_crypto_eip197.c -+++ b/v2.0/src/hal/ipq807x/nss_crypto_eip197.c -@@ -490,7 +490,7 @@ int nss_crypto_eip197_engine_init(struct platform_device *pdev, struct device_no - * remap the I/O addresses - */ - paddr = res->start + offset; -- vaddr = ioremap_nocache(paddr, resource_size(res)); -+ vaddr = ioremap(paddr, resource_size(res)); - if (!vaddr) { - nss_crypto_warn("%px: unable to remap crypto_addr(0x%px)\n", node, (void *)paddr); - return -EIO; --- -2.35.1 - diff --git a/qca/qca-nss-crypto/patches/0003-nss-crypto-fix-SHA-header-include-in-5.15.patch b/qca/qca-nss-crypto/patches/0003-nss-crypto-fix-SHA-header-include-in-5.15.patch deleted file mode 100644 index 311070d91..000000000 --- a/qca/qca-nss-crypto/patches/0003-nss-crypto-fix-SHA-header-include-in-5.15.patch +++ /dev/null @@ -1,51 +0,0 @@ -From 4c0cc66cde0c4a30aa049b586af311501304e9ce Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Sun, 13 Mar 2022 13:47:24 +0100 -Subject: [PATCH 3/3] nss-crypto: fix SHA header include in 5.15 - -SHA header was split into SHA-1 and SHA-2 headers in kernel 5.11, so -fix the include for newer kernels. - -Signed-off-by: Robert Marko ---- - v2.0/src/nss_crypto_ctrl.c | 6 ++++++ - v2.0/src/nss_crypto_hlos.h | 4 ++++ - 2 files changed, 10 insertions(+) - -diff --git a/v2.0/src/nss_crypto_ctrl.c b/v2.0/src/nss_crypto_ctrl.c -index 72d1602..a462705 100644 ---- a/v2.0/src/nss_crypto_ctrl.c -+++ b/v2.0/src/nss_crypto_ctrl.c -@@ -38,7 +38,13 @@ - #include - #include - #include -+#include -+#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 11, 0) - #include -+#else -+#include -+#include -+#endif - #include - #include - #include -diff --git a/v2.0/src/nss_crypto_hlos.h b/v2.0/src/nss_crypto_hlos.h -index e827f4f..5565472 100644 ---- a/v2.0/src/nss_crypto_hlos.h -+++ b/v2.0/src/nss_crypto_hlos.h -@@ -58,7 +58,11 @@ - #if LINUX_VERSION_CODE < KERNEL_VERSION(5, 8, 0) - #include - #endif -+#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 11, 0) - #include -+#else -+#include -+#endif - #include - #include - #include --- -2.35.1 - diff --git a/qca/qca-nss-dp/Makefile b/qca/qca-nss-dp/Makefile deleted file mode 100644 index 17627674a..000000000 --- a/qca/qca-nss-dp/Makefile +++ /dev/null @@ -1,56 +0,0 @@ -include $(TOPDIR)/rules.mk - -PKG_NAME:=qca-nss-dp -PKG_RELEASE:=$(AUTORELEASE) - -PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/nss-dp.git -PKG_SOURCE_PROTO:=git -PKG_SOURCE_DATE:=2022-04-30 -PKG_SOURCE_VERSION:=72e9ec4187414461cbcf6ccff100e8b5ebe5f40b -PKG_MIRROR_HASH:=805f16e59c75511132922f97740ebf6bf953845b0bbfd2089c4615456893bb37 - -PKG_BUILD_PARALLEL:=1 - -include $(INCLUDE_DIR)/kernel.mk -include $(INCLUDE_DIR)/package.mk - -define KernelPackage/qca-nss-dp - SECTION:=kernel - CATEGORY:=Kernel modules - SUBMENU:=Network Devices - DEPENDS:=@(TARGET_ipq807x||TARGET_ipq60xx) +kmod-qca-ssdk-nohnat - TITLE:=Kernel driver for NSS data plane - FILES:=$(PKG_BUILD_DIR)/qca-nss-dp.ko - AUTOLOAD:=$(call AutoLoad,31,qca-nss-dp,1) -endef - -define KernelPackage/qca-nss-dp/Description -This package contains a NSS data plane driver for QCA chipset -endef - -define Build/InstallDev - mkdir -p $(1)/usr/include/qca-nss-dp - $(CP) $(PKG_BUILD_DIR)/exports/* $(1)/usr/include/qca-nss-dp/ -endef - -EXTRA_CFLAGS+= \ - -I$(STAGING_DIR)/usr/include/qca-ssdk - -NSS_DP_HAL_DIR:=$(PKG_BUILD_DIR)/hal -define Build/Configure - $(LN) $(NSS_DP_HAL_DIR)/soc_ops/$(CONFIG_TARGET_BOARD)/nss_$(CONFIG_TARGET_BOARD).h \ - $(PKG_BUILD_DIR)/exports/nss_dp_arch.h -endef - -define Build/Compile - +$(MAKE) -C "$(LINUX_DIR)" \ - CROSS_COMPILE="$(TARGET_CROSS)" \ - ARCH="$(LINUX_KARCH)" \ - M="$(PKG_BUILD_DIR)" \ - EXTRA_CFLAGS="$(EXTRA_CFLAGS)" SoC="$(CONFIG_TARGET_BOARD)" \ - $(KERNEL_MAKE_FLAGS) \ - $(PKG_JOBS) \ - modules -endef - -$(eval $(call KernelPackage,qca-nss-dp)) diff --git a/qca/qca-nss-dp/patches/0001-edma_tx_rx-support-newer-kernels-time-stamping-API.patch b/qca/qca-nss-dp/patches/0001-edma_tx_rx-support-newer-kernels-time-stamping-API.patch deleted file mode 100644 index 1fed4ba8a..000000000 --- a/qca/qca-nss-dp/patches/0001-edma_tx_rx-support-newer-kernels-time-stamping-API.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 40979666b4371012405715ffa61ab5760fcdc6b3 Mon Sep 17 00:00:00 2001 -Message-Id: <40979666b4371012405715ffa61ab5760fcdc6b3.1620066716.git.baruch@tkos.co.il> -From: Baruch Siach -Date: Mon, 3 May 2021 20:07:36 +0300 -Subject: [PATCH 1/3] edma_tx_rx: support newer kernels time stamping API - ---- - hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c | 11 +++++++++++ - 1 file changed, 11 insertions(+) - ---- a/hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c -+++ b/hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c -@@ -227,10 +227,16 @@ void nss_phy_tstamp_rx_buf(__attribute__ - * set to the correct PTP class value by calling ptp_classify_raw - * in drv->rxtstamp function. - */ -+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 6, 0)) - if (ndev && ndev->phydev && ndev->phydev->drv && - ndev->phydev->drv->rxtstamp) - if(ndev->phydev->drv->rxtstamp(ndev->phydev, skb, 0)) - return; -+#else -+ if (ndev && phy_has_rxtstamp(ndev->phydev)) -+ if (phy_rxtstamp(ndev->phydev, skb, 0)) -+ return; -+#endif - - netif_receive_skb(skb); - } -@@ -248,9 +254,14 @@ void nss_phy_tstamp_tx_buf(struct net_de - * set to the correct PTP class value by calling ptp_classify_raw - * in the drv->txtstamp function. - */ -+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 6, 0)) - if (ndev && ndev->phydev && ndev->phydev->drv && - ndev->phydev->drv->txtstamp) - ndev->phydev->drv->txtstamp(ndev->phydev, skb, 0); -+#else -+ if (ndev && phy_has_txtstamp(ndev->phydev)) -+ phy_rxtstamp(ndev->phydev, skb, 0); -+#endif - } - EXPORT_SYMBOL(nss_phy_tstamp_tx_buf); - diff --git a/qca/qca-nss-dp/patches/0002-nss_dp_main-make-phy-mode-code-compatible-with-newer.patch b/qca/qca-nss-dp/patches/0002-nss_dp_main-make-phy-mode-code-compatible-with-newer.patch deleted file mode 100644 index 04adad86f..000000000 --- a/qca/qca-nss-dp/patches/0002-nss_dp_main-make-phy-mode-code-compatible-with-newer.patch +++ /dev/null @@ -1,48 +0,0 @@ -From cef7873a2d77df13ee702d902ed4e06b2248904b Mon Sep 17 00:00:00 2001 -Message-Id: -In-Reply-To: <40979666b4371012405715ffa61ab5760fcdc6b3.1620066716.git.baruch@tkos.co.il> -References: <40979666b4371012405715ffa61ab5760fcdc6b3.1620066716.git.baruch@tkos.co.il> -From: Baruch Siach -Date: Mon, 3 May 2021 20:17:22 +0300 -Subject: [PATCH 2/3] nss_dp_main: make phy mode code compatible with newer - kernels - ---- - include/nss_dp_dev.h | 4 ++-- - nss_dp_main.c | 4 ++++ - 2 files changed, 6 insertions(+), 2 deletions(-) - ---- a/include/nss_dp_dev.h -+++ b/include/nss_dp_dev.h -@@ -22,7 +22,7 @@ - #include - #include - #include --#include -+#include - #include - - #include "nss_dp_api_if.h" -@@ -99,7 +99,7 @@ struct nss_dp_dev { - /* Phy related stuff */ - struct phy_device *phydev; /* Phy device */ - struct mii_bus *miibus; /* MII bus */ -- uint32_t phy_mii_type; /* RGMII/SGMII/QSGMII */ -+ phy_interface_t phy_mii_type; /* RGMII/SGMII/QSGMII */ - uint32_t phy_mdio_addr; /* Mdio address */ - bool link_poll; /* Link polling enable? */ - uint32_t forced_speed; /* Forced speed? */ ---- a/nss_dp_main.c -+++ b/nss_dp_main.c -@@ -584,7 +584,11 @@ static int32_t nss_dp_of_get_pdata(struc - hal_pdata->netdev = netdev; - hal_pdata->macid = dp_priv->macid; - -+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 5, 0)) - dp_priv->phy_mii_type = of_get_phy_mode(np); -+#else -+ of_get_phy_mode(np, &dp_priv->phy_mii_type); -+#endif - dp_priv->link_poll = of_property_read_bool(np, "qcom,link-poll"); - if (of_property_read_u32(np, "qcom,phy-mdio-addr", - &dp_priv->phy_mdio_addr) && dp_priv->link_poll) { diff --git a/qca/qca-nss-dp/patches/0003-Drop-_nocache-variants-of-ioremap.patch b/qca/qca-nss-dp/patches/0003-Drop-_nocache-variants-of-ioremap.patch deleted file mode 100644 index 18bd85c8c..000000000 --- a/qca/qca-nss-dp/patches/0003-Drop-_nocache-variants-of-ioremap.patch +++ /dev/null @@ -1,48 +0,0 @@ -From c8c52512ff48bee578901c381a42f027e79eadf9 Mon Sep 17 00:00:00 2001 -Message-Id: -In-Reply-To: <40979666b4371012405715ffa61ab5760fcdc6b3.1620066716.git.baruch@tkos.co.il> -References: <40979666b4371012405715ffa61ab5760fcdc6b3.1620066716.git.baruch@tkos.co.il> -From: Baruch Siach -Date: Mon, 3 May 2021 20:20:29 +0300 -Subject: [PATCH 3/3] Drop _nocache variants of ioremap() - -Recent kernels removed them. ---- - hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c | 2 +- - hal/gmac_ops/qcom/qcom_if.c | 2 +- - hal/gmac_ops/syn/xgmac/syn_if.c | 2 +- - 3 files changed, 3 insertions(+), 3 deletions(-) - ---- a/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c -+++ b/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c -@@ -279,7 +279,7 @@ int edma_init(void) - /* - * Remap register resource - */ -- edma_hw.reg_base = ioremap_nocache((edma_hw.reg_resource)->start, -+ edma_hw.reg_base = ioremap((edma_hw.reg_resource)->start, - resource_size(edma_hw.reg_resource)); - if (!edma_hw.reg_base) { - pr_warn("Unable to remap EDMA register memory.\n"); ---- a/hal/gmac_ops/qcom/qcom_if.c -+++ b/hal/gmac_ops/qcom/qcom_if.c -@@ -418,7 +418,7 @@ static void *qcom_init(struct nss_gmac_h - qhd->nghd.mac_id = gmacpdata->macid; - - /* Populate the mac base addresses */ -- qhd->nghd.mac_base = devm_ioremap_nocache(&dp_priv->pdev->dev, -+ qhd->nghd.mac_base = devm_ioremap(&dp_priv->pdev->dev, - res->start, resource_size(res)); - if (!qhd->nghd.mac_base) { - netdev_dbg(ndev, "ioremap fail.\n"); ---- a/hal/gmac_ops/syn/xgmac/syn_if.c -+++ b/hal/gmac_ops/syn/xgmac/syn_if.c -@@ -432,7 +432,7 @@ static void *syn_init(struct nss_gmac_ha - - /* Populate the mac base addresses */ - shd->nghd.mac_base = -- devm_ioremap_nocache(&dp_priv->pdev->dev, res->start, -+ devm_ioremap(&dp_priv->pdev->dev, res->start, - resource_size(res)); - if (!shd->nghd.mac_base) { - netdev_dbg(ndev, "ioremap fail.\n"); diff --git a/qca/qca-nss-dp/patches/0004-EDMA-Fix-NAPI-packet-counting.patch b/qca/qca-nss-dp/patches/0004-EDMA-Fix-NAPI-packet-counting.patch deleted file mode 100644 index f7653729a..000000000 --- a/qca/qca-nss-dp/patches/0004-EDMA-Fix-NAPI-packet-counting.patch +++ /dev/null @@ -1,31 +0,0 @@ -From d74920e2a7c413ef40eed72f9cf287cf6fbd5fb8 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Thu, 20 May 2021 14:56:46 +0200 -Subject: [PATCH 1/2] EDMA: Fix NAPI packet counting - -There is a bug in the NAPI packet counting that will -cause NAPI over budget warnings. - -Signed-off-by: Baruch Siach -Signed-off-by: Robert Marko ---- - hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c -+++ b/hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c -@@ -459,12 +459,12 @@ int edma_napi(struct napi_struct *napi, - - for (i = 0; i < ehw->txcmpl_rings; i++) { - txcmpl_ring = &ehw->txcmpl_ring[i]; -- work_done += edma_clean_tx(ehw, txcmpl_ring); -+ edma_clean_tx(ehw, txcmpl_ring); - } - - for (i = 0; i < ehw->rxfill_rings; i++) { - rxfill_ring = &ehw->rxfill_ring[i]; -- work_done += edma_alloc_rx_buffer(ehw, rxfill_ring); -+ edma_alloc_rx_buffer(ehw, rxfill_ring); - } - - /* diff --git a/qca/qca-nss-dp/patches/0005-EDMA-Use-NAPI_POLL_WEIGHT-as-NAPI-weight.patch b/qca/qca-nss-dp/patches/0005-EDMA-Use-NAPI_POLL_WEIGHT-as-NAPI-weight.patch deleted file mode 100644 index 9c22fa790..000000000 --- a/qca/qca-nss-dp/patches/0005-EDMA-Use-NAPI_POLL_WEIGHT-as-NAPI-weight.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 44a30d94abcbb10aacc21db29be212518a6b1bf7 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Thu, 20 May 2021 14:57:46 +0200 -Subject: [PATCH] EDMA: Use NAPI_POLL_WEIGHT as NAPI weight - -Currently a weight of 100 is used by the EDMA, according -to upstream max of 64 should be used and that is used for -almost any driver. - -They also introduced NAPI_POLL_WEIGHT define which equals -to 64. - -So use NAPI_POLL_WEIGHT as the weight. - -Signed-off-by: Robert Marko ---- - hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c | 2 +- - hal/dp_ops/edma_dp/edma_v1/edma_data_plane.h | 1 - - 2 files changed, 1 insertion(+), 2 deletions(-) - ---- a/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c -+++ b/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c -@@ -837,7 +837,7 @@ static int edma_register_netdevice(struc - */ - if (!edma_hw.napi_added) { - netif_napi_add(netdev, &edma_hw.napi, edma_napi, -- EDMA_NAPI_WORK); -+ NAPI_POLL_WEIGHT); - /* - * Register the interrupt handlers and enable interrupts - */ ---- a/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.h -+++ b/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.h -@@ -26,7 +26,6 @@ - #define EDMA_RX_PREHDR_SIZE (sizeof(struct edma_rx_preheader)) - #define EDMA_TX_PREHDR_SIZE (sizeof(struct edma_tx_preheader)) - #define EDMA_RING_SIZE 128 --#define EDMA_NAPI_WORK 100 - #define EDMA_START_GMACS NSS_DP_HAL_START_IFNUM - #define EDMA_MAX_GMACS NSS_DP_HAL_MAX_PORTS - #define EDMA_TX_PKT_MIN_SIZE 33 /* IPQ807x EDMA needs a minimum packet size of 33 bytes */ diff --git a/qca/qca-nss-dp/patches/0006-NSS-DP-fix-of_get_mac_address.patch b/qca/qca-nss-dp/patches/0006-NSS-DP-fix-of_get_mac_address.patch deleted file mode 100644 index 1d7b49129..000000000 --- a/qca/qca-nss-dp/patches/0006-NSS-DP-fix-of_get_mac_address.patch +++ /dev/null @@ -1,46 +0,0 @@ -From cadeb62a42296563141d6954eec58e34ef86778d Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Fri, 13 Aug 2021 20:12:08 +0200 -Subject: [PATCH] NSS-DP: fix of_get_mac_address() - -Recently OpenWrt backported the updated of_get_mac_address() -function which returns and error code instead. - -So, patch the SSDK to use it and fix the compilation error. - -Signed-off-by: Robert Marko ---- - nss_dp_main.c | 13 ++++--------- - 1 file changed, 4 insertions(+), 9 deletions(-) - ---- a/nss_dp_main.c -+++ b/nss_dp_main.c -@@ -555,9 +555,10 @@ static int32_t nss_dp_of_get_pdata(struc - struct net_device *netdev, - struct nss_gmac_hal_platform_data *hal_pdata) - { -- uint8_t *maddr; -+ u8 maddr[ETH_ALEN]; - struct nss_dp_dev *dp_priv; - struct resource memres_devtree = {0}; -+ int ret; - - dp_priv = netdev_priv(netdev); - -@@ -600,14 +601,8 @@ static int32_t nss_dp_of_get_pdata(struc - of_property_read_u32(np, "qcom,forced-speed", &dp_priv->forced_speed); - of_property_read_u32(np, "qcom,forced-duplex", &dp_priv->forced_duplex); - -- maddr = (uint8_t *)of_get_mac_address(np); --#if (LINUX_VERSION_CODE > KERNEL_VERSION(5, 4, 0)) -- if (IS_ERR((void *)maddr)) { -- maddr = NULL; -- } --#endif -- -- if (maddr && is_valid_ether_addr(maddr)) { -+ ret = of_get_mac_address(np, maddr); -+ if (!ret && is_valid_ether_addr(maddr)) { - ether_addr_copy(netdev->dev_addr, maddr); - } else { - random_ether_addr(netdev->dev_addr); diff --git a/qca/qca-nss-dp/patches/0007-NSS-DP-implement-ethernet-IOCTL-s.patch b/qca/qca-nss-dp/patches/0007-NSS-DP-implement-ethernet-IOCTL-s.patch deleted file mode 100644 index 824f18634..000000000 --- a/qca/qca-nss-dp/patches/0007-NSS-DP-implement-ethernet-IOCTL-s.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 5da62ba19f554bf437752a44360fb5ae9f1a7f5e Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Tue, 8 Mar 2022 10:48:32 +0100 -Subject: [PATCH] NSS-DP: implement ethernet IOCTL-s - -Since kernel 5.15 ethernet/PHY related IOCTL-s have been split from the -generic IOCTL netdev op. -So, implement the new op instead of the generic one which is considered -for private IOCTL-s only now for 5.15+. - -Signed-off-by: Robert Marko ---- - nss_dp_main.c | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/nss_dp_main.c -+++ b/nss_dp_main.c -@@ -532,7 +532,11 @@ static const struct net_device_ops nss_d - .ndo_set_mac_address = nss_dp_set_mac_address, - .ndo_validate_addr = eth_validate_addr, - .ndo_change_mtu = nss_dp_change_mtu, -+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 15, 0)) - .ndo_do_ioctl = nss_dp_do_ioctl, -+#else -+ .ndo_eth_ioctl = nss_dp_do_ioctl, -+#endif - - #if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 5, 0)) - .ndo_bridge_setlink = switchdev_port_bridge_setlink, diff --git a/qca/qca-nss-dp/patches/0008-switchdev-remove-the-transaction-structure.patch b/qca/qca-nss-dp/patches/0008-switchdev-remove-the-transaction-structure.patch deleted file mode 100644 index 220be961a..000000000 --- a/qca/qca-nss-dp/patches/0008-switchdev-remove-the-transaction-structure.patch +++ /dev/null @@ -1,48 +0,0 @@ -From c9afdcdd2642485a6476906be9da2e811090fc7a Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Fri, 18 Mar 2022 18:06:03 +0100 -Subject: [PATCH] switchdev: remove the transaction structure - -Since 5.12 there is no transaction structure anymore, so drop it for -5.12 and newer. - -Signed-off-by: Robert Marko ---- - nss_dp_switchdev.c | 10 ++++++++++ - 1 file changed, 10 insertions(+) - ---- a/nss_dp_switchdev.c -+++ b/nss_dp_switchdev.c -@@ -279,13 +279,19 @@ void nss_dp_switchdev_setup(struct net_d - * Sets attributes - */ - static int nss_dp_port_attr_set(struct net_device *dev, -+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 12, 0)) - const struct switchdev_attr *attr, - struct switchdev_trans *trans) -+#else -+ const struct switchdev_attr *attr) -+#endif - { - struct nss_dp_dev *dp_priv = (struct nss_dp_dev *)netdev_priv(dev); - -+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 12, 0)) - if (switchdev_trans_ph_prepare(trans)) - return 0; -+#endif - - switch (attr->id) { - case SWITCHDEV_ATTR_ID_PORT_BRIDGE_FLAGS: -@@ -309,8 +315,12 @@ static int nss_dp_switchdev_port_attr_se - { - int err; - -+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 12, 0)) - err = nss_dp_port_attr_set(netdev, port_attr_info->attr, - port_attr_info->trans); -+#else -+ err = nss_dp_port_attr_set(netdev, port_attr_info->attr); -+#endif - - port_attr_info->handled = true; - return notifier_from_errno(err); diff --git a/qca/qca-nss-dp/patches/0009-switchdev-use-new-switchdev-flags.patch b/qca/qca-nss-dp/patches/0009-switchdev-use-new-switchdev-flags.patch deleted file mode 100644 index ecc84c174..000000000 --- a/qca/qca-nss-dp/patches/0009-switchdev-use-new-switchdev-flags.patch +++ /dev/null @@ -1,51 +0,0 @@ -From f95868d54301c0f54e968ec9d978c9caa02ee425 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Fri, 18 Mar 2022 18:24:18 +0100 -Subject: [PATCH] switchdev: use new switchdev flags - -Since kernel 5.12 switched utilizes a new way of setting the flags by -using a dedicated structure with flags and mask. - -So fix using kernels 5.12 and later. - -Signed-off-by: Robert Marko ---- - include/nss_dp_dev.h | 7 +++++++ - nss_dp_switchdev.c | 2 +- - 2 files changed, 8 insertions(+), 1 deletion(-) - ---- a/include/nss_dp_dev.h -+++ b/include/nss_dp_dev.h -@@ -24,6 +24,9 @@ - #include - #include - #include -+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 12, 0)) -+#include -+#endif - - #include "nss_dp_api_if.h" - #include "nss_dp_hal_if.h" -@@ -126,7 +129,11 @@ struct nss_dp_dev { - /* switchdev related attributes */ - #ifdef CONFIG_NET_SWITCHDEV - u8 stp_state; /* STP state of this physical port */ -+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 12, 0)) - unsigned long brport_flags; /* bridge port flags */ -+#else -+ struct switchdev_brport_flags brport_flags; /* bridge port flags */ -+#endif - #endif - uint32_t rx_page_mode; /* page mode for Rx processing */ - uint32_t rx_jumbo_mru; /* Jumbo mru value for Rx processing */ ---- a/nss_dp_switchdev.c -+++ b/nss_dp_switchdev.c -@@ -296,7 +296,7 @@ static int nss_dp_port_attr_set(struct n - switch (attr->id) { - case SWITCHDEV_ATTR_ID_PORT_BRIDGE_FLAGS: - dp_priv->brport_flags = attr->u.brport_flags; -- netdev_dbg(dev, "set brport_flags %lu\n", attr->u.brport_flags); -+ netdev_dbg(dev, "set brport_flags %lu\n", attr->u.brport_flags.val); - return 0; - case SWITCHDEV_ATTR_ID_PORT_STP_STATE: - return nss_dp_stp_state_set(dp_priv, attr->u.stp_state); diff --git a/qca/qca-nss-dp/patches/0010-switchdev-fix-FDB-roaming.patch b/qca/qca-nss-dp/patches/0010-switchdev-fix-FDB-roaming.patch deleted file mode 100644 index 19395ac42..000000000 --- a/qca/qca-nss-dp/patches/0010-switchdev-fix-FDB-roaming.patch +++ /dev/null @@ -1,110 +0,0 @@ -From d16102cad769f430144ca8094d928762b445e9b0 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Fri, 18 Mar 2022 22:02:01 +0100 -Subject: [PATCH] switchdev: fix FDB roaming - -Try and solve the roaming issue by trying to replicate what NSS bridge -module is doing, but by utilizing switchdev FDB notifiers instead of -adding new notifiers to the bridge code. - -We register a new non-blocking switchdev notifier and simply wait for -notification, and then process the SWITCHDEV_FDB_DEL_TO_DEVICE -notifications. - -Those tell us that a certain FDB entry should be removed, then a VSI ID -is fetched for the physical PPE port and using that VSI ID and the -notification provided MAC adress existing FDB entry gets removed. - -Signed-off-by: Robert Marko ---- - nss_dp_switchdev.c | 61 ++++++++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 61 insertions(+) - ---- a/nss_dp_switchdev.c -+++ b/nss_dp_switchdev.c -@@ -24,6 +24,8 @@ - #include "nss_dp_dev.h" - #include "fal/fal_stp.h" - #include "fal/fal_ctrlpkt.h" -+#include "fal/fal_fdb.h" -+#include "ref/ref_vsi.h" - - #define NSS_DP_SWITCH_ID 0 - #define NSS_DP_SW_ETHTYPE_PID 0 /* PPE ethtype profile ID for slow protocols */ -@@ -348,10 +350,64 @@ static int nss_dp_switchdev_event(struct - return NOTIFY_DONE; - } - -+static int nss_dp_switchdev_fdb_del_event(struct net_device *netdev, -+ struct switchdev_notifier_fdb_info *fdb_info) -+{ -+ struct nss_dp_dev *dp_priv = (struct nss_dp_dev *)netdev_priv(netdev); -+ fal_fdb_entry_t entry; -+ a_uint32_t vsi_id; -+ sw_error_t rv; -+ -+ netdev_dbg(netdev, "FDB DEL %pM port %d\n", fdb_info->addr, dp_priv->macid); -+ -+ rv = ppe_port_vsi_get(NSS_DP_SWITCH_ID, dp_priv->macid, &vsi_id); -+ if (rv) { -+ netdev_err(netdev, "cannot get VSI ID for port %d\n", dp_priv->macid); -+ return notifier_from_errno(rv); -+ } -+ -+ memset(&entry, 0, sizeof(entry)); -+ memcpy(&entry.addr, fdb_info->addr, ETH_ALEN); -+ entry.fid = vsi_id; -+ -+ rv = fal_fdb_entry_del_bymac(NSS_DP_SWITCH_ID, &entry); -+ if (rv) { -+ netdev_err(netdev, "FDB entry delete failed with MAC %pM and fid %d\n", -+ &entry.addr, entry.fid); -+ return notifier_from_errno(rv); -+ } -+ -+ return notifier_from_errno(rv); -+} -+ -+static int nss_dp_fdb_switchdev_event(struct notifier_block *nb, -+ unsigned long event, void *ptr) -+{ -+ struct net_device *dev = switchdev_notifier_info_to_dev(ptr); -+ -+ /* -+ * Handle switchdev event only for physical devices -+ */ -+ if (!nss_dp_is_phy_dev(dev)) { -+ return NOTIFY_DONE; -+ } -+ -+ switch (event) { -+ case SWITCHDEV_FDB_DEL_TO_DEVICE: -+ return nss_dp_switchdev_fdb_del_event(dev, ptr); -+ } -+ -+ return NOTIFY_DONE; -+} -+ - static struct notifier_block nss_dp_switchdev_notifier = { - .notifier_call = nss_dp_switchdev_event, - }; - -+static struct notifier_block nss_dp_switchdev_fdb_notifier = { -+ .notifier_call = nss_dp_fdb_switchdev_event, -+}; -+ - static bool switch_init_done; - - /* -@@ -366,6 +422,11 @@ void nss_dp_switchdev_setup(struct net_d - return; - } - -+ err = register_switchdev_notifier(&nss_dp_switchdev_fdb_notifier); -+ if (err) { -+ netdev_dbg(dev, "%px:Failed to register switchdev FDB notifier\n", dev); -+ } -+ - err = register_switchdev_blocking_notifier(&nss_dp_switchdev_notifier); - if (err) { - netdev_dbg(dev, "%px:Failed to register switchdev notifier\n", dev); diff --git a/qca/qca-nss-dp/patches/0011-treewide-fix-confusing-printing-of-registered-netdev.patch b/qca/qca-nss-dp/patches/0011-treewide-fix-confusing-printing-of-registered-netdev.patch deleted file mode 100644 index 63fea1982..000000000 --- a/qca/qca-nss-dp/patches/0011-treewide-fix-confusing-printing-of-registered-netdev.patch +++ /dev/null @@ -1,48 +0,0 @@ -From 7e4ae2d6285095794d73d2f2ce61404f61d4e633 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Tue, 17 May 2022 15:55:36 +0200 -Subject: [PATCH 11/11] treewide: fix confusing printing of registered netdev - -Net core implementation changed and now printing the netdev name cause -confusing printing if done before register_netdev. Move the old printing -to dbg and add an additional info log right after register_netdev to -give the user some info on correct nss-dp probe. - -Signed-off-by: Ansuel Smith ---- - hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c | 4 ++-- - nss_dp_main.c | 3 +++ - 2 files changed, 5 insertions(+), 2 deletions(-) - -diff --git a/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c b/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c -index 0af39c2..1d748db 100644 ---- a/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c -+++ b/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c -@@ -822,8 +822,8 @@ static int edma_register_netdevice(struct net_device *netdev, uint32_t macid) - return -EINVAL; - } - -- netdev_info(netdev, "nss_dp_edma: Registering netdev %s(qcom-id:%d) with EDMA\n", -- netdev->name, macid); -+ netdev_dbg(netdev, "nss_dp_edma: Registering netdev %s(qcom-id:%d) with EDMA\n", -+ netdev->name, macid); - - /* - * We expect 'macid' to correspond to ports numbers on -diff --git a/nss_dp_main.c b/nss_dp_main.c -index c0ae9d6..441c300 100644 ---- a/nss_dp_main.c -+++ b/nss_dp_main.c -@@ -875,6 +875,9 @@ static int32_t nss_dp_probe(struct platform_device *pdev) - goto phy_setup_fail; - } - -+ netdev_info(netdev, "Registered netdev %s(qcom-id:%d)\n", -+ netdev->name, port_id); -+ - dp_global_ctx.nss_dp[dp_priv->macid - 1] = dp_priv; - dp_global_ctx.slowproto_acl_bm = 0; - --- -2.34.1 - diff --git a/qca/qca-nss-dp/patches/0012-gmac-syn-xgmac-silence-debug-log-on-probe.patch b/qca/qca-nss-dp/patches/0012-gmac-syn-xgmac-silence-debug-log-on-probe.patch deleted file mode 100644 index 2bc576ccb..000000000 --- a/qca/qca-nss-dp/patches/0012-gmac-syn-xgmac-silence-debug-log-on-probe.patch +++ /dev/null @@ -1,28 +0,0 @@ -From fee52ef165e9fab2fca15492677082fd8e9e891f Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Thu, 19 May 2022 23:40:24 +0200 -Subject: [PATCH 12/12] gmac: syn: xgmac: silence debug log on probe - -Silence debug log set as info in xgmac port probe. - -Signed-off-by: Ansuel Smith ---- - hal/gmac_ops/syn/xgmac/syn_if.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/hal/gmac_ops/syn/xgmac/syn_if.c b/hal/gmac_ops/syn/xgmac/syn_if.c -index 1152f5c..bc2880d 100644 ---- a/hal/gmac_ops/syn/xgmac/syn_if.c -+++ b/hal/gmac_ops/syn/xgmac/syn_if.c -@@ -445,7 +445,7 @@ static void *syn_init(struct nss_gmac_hal_platform_data *gmacpdata) - - spin_lock_init(&shd->nghd.slock); - -- netdev_info(ndev, "ioremap OK.Size 0x%x Ndev base 0x%lx macbase 0x%px\n", -+ netdev_dbg(ndev, "ioremap OK.Size 0x%x Ndev base 0x%lx macbase 0x%px\n", - gmacpdata->reg_len, - ndev->base_addr, - shd->nghd.mac_base); --- -2.34.1 - diff --git a/qca/qca-nss-dp/patches/0013-nss_dp_main-Use-a-phy-handle-property-to-connect-to-.patch b/qca/qca-nss-dp/patches/0013-nss_dp_main-Use-a-phy-handle-property-to-connect-to-.patch deleted file mode 100644 index ea6993d75..000000000 --- a/qca/qca-nss-dp/patches/0013-nss_dp_main-Use-a-phy-handle-property-to-connect-to-.patch +++ /dev/null @@ -1,189 +0,0 @@ -From 8293a26ca56ee2e9a88e4efb5dcc7f647803cd8c Mon Sep 17 00:00:00 2001 -From: Alexandru Gagniuc -Date: Sun, 5 Jun 2022 21:45:09 -0500 -Subject: [PATCH] nss_dp_main: Use a 'phy-handle' property to connect to the - PHY - -The original method of connecting a PHY to the ethernet controller -requires the "qcom,link-poll", and "qcom,phy-mdio-addr" devicetree -properties. This is redundant. The PHY node already contains the MDIO -address, and attaching a PHY implies "link-poll". - -Allow using a "phy-handle" property. Remove the following properties, -as they are no longer used: - * "qcom,link-poll" - * "qcom,phy-mdio-addr" - * "mdio-bus" - * "qcom,forced-speed" - * "qcom,forced-duplex" - -Signed-off-by: Alexandru Gagniuc ---- - include/nss_dp_dev.h | 5 +-- - nss_dp_main.c | 91 +++++--------------------------------------- - 2 files changed, 10 insertions(+), 86 deletions(-) - -diff --git a/include/nss_dp_dev.h b/include/nss_dp_dev.h -index 19b3e78..63a857a 100644 ---- a/include/nss_dp_dev.h -+++ b/include/nss_dp_dev.h -@@ -100,13 +100,10 @@ struct nss_dp_dev { - unsigned long drv_flags; /* Driver specific feature flags */ - - /* Phy related stuff */ -+ struct device_node *phy_node; - struct phy_device *phydev; /* Phy device */ - struct mii_bus *miibus; /* MII bus */ - phy_interface_t phy_mii_type; /* RGMII/SGMII/QSGMII */ -- uint32_t phy_mdio_addr; /* Mdio address */ -- bool link_poll; /* Link polling enable? */ -- uint32_t forced_speed; /* Forced speed? */ -- uint32_t forced_duplex; /* Forced duplex? */ - uint32_t link_state; /* Current link state */ - uint32_t pause; /* Current flow control settings */ - -diff --git a/nss_dp_main.c b/nss_dp_main.c -index 441c300..a1e8627 100644 ---- a/nss_dp_main.c -+++ b/nss_dp_main.c -@@ -399,7 +399,7 @@ static int nss_dp_open(struct net_device *netdev) - - netif_start_queue(netdev); - -- if (!dp_priv->link_poll) { -+ if (!dp_priv->phydev) { - /* Notify data plane link is up */ - if (dp_priv->data_plane_ops->link_state(dp_priv->dpc, 1)) { - netdev_dbg(netdev, "Data plane set link failed\n"); -@@ -576,6 +576,8 @@ static int32_t nss_dp_of_get_pdata(struct device_node *np, - return -EFAULT; - } - -+ dp_priv->phy_node = of_parse_phandle(np, "phy-handle", 0); -+ - if (of_property_read_u32(np, "qcom,mactype", &hal_pdata->mactype)) { - pr_err("%s: error reading mactype\n", np->name); - return -EFAULT; -@@ -594,16 +596,6 @@ static int32_t nss_dp_of_get_pdata(struct device_node *np, - #else - of_get_phy_mode(np, &dp_priv->phy_mii_type); - #endif -- dp_priv->link_poll = of_property_read_bool(np, "qcom,link-poll"); -- if (of_property_read_u32(np, "qcom,phy-mdio-addr", -- &dp_priv->phy_mdio_addr) && dp_priv->link_poll) { -- pr_err("%s: mdio addr required if link polling is enabled\n", -- np->name); -- return -EFAULT; -- } -- -- of_property_read_u32(np, "qcom,forced-speed", &dp_priv->forced_speed); -- of_property_read_u32(np, "qcom,forced-duplex", &dp_priv->forced_duplex); - - ret = of_get_mac_address(np, maddr); - if (!ret && is_valid_ether_addr(maddr)) { -@@ -636,50 +628,6 @@ static int32_t nss_dp_of_get_pdata(struct device_node *np, - return 0; - } - --/* -- * nss_dp_mdio_attach() -- */ --static struct mii_bus *nss_dp_mdio_attach(struct platform_device *pdev) --{ -- struct device_node *mdio_node; -- struct platform_device *mdio_plat; -- struct ipq40xx_mdio_data *mdio_data; -- -- /* -- * Find mii_bus using "mdio-bus" handle. -- */ -- mdio_node = of_parse_phandle(pdev->dev.of_node, "mdio-bus", 0); -- if (mdio_node) { -- return of_mdio_find_bus(mdio_node); -- } -- -- mdio_node = of_find_compatible_node(NULL, NULL, "qcom,qca-mdio"); -- if (!mdio_node) { -- mdio_node = of_find_compatible_node(NULL, NULL, -- "qcom,ipq40xx-mdio"); -- if (!mdio_node) { -- dev_err(&pdev->dev, "cannot find mdio node by phandle\n"); -- return NULL; -- } -- } -- -- mdio_plat = of_find_device_by_node(mdio_node); -- if (!mdio_plat) { -- dev_err(&pdev->dev, "cannot find platform device from mdio node\n"); -- of_node_put(mdio_node); -- return NULL; -- } -- -- mdio_data = dev_get_drvdata(&mdio_plat->dev); -- if (!mdio_data) { -- dev_err(&pdev->dev, "cannot get mii bus reference from device data\n"); -- of_node_put(mdio_node); -- return NULL; -- } -- -- return mdio_data->mii_bus; --} -- - #ifdef CONFIG_NET_SWITCHDEV - /* - * nss_dp_is_phy_dev() -@@ -738,7 +686,6 @@ static int32_t nss_dp_probe(struct platform_device *pdev) - struct device_node *np = pdev->dev.of_node; - struct nss_gmac_hal_platform_data gmac_hal_pdata; - int32_t ret = 0; -- uint8_t phy_id[MII_BUS_ID_SIZE + 3]; - #if defined(NSS_DP_PPE_SUPPORT) - uint32_t vsi_id; - fal_port_t port_id; -@@ -813,37 +760,17 @@ static int32_t nss_dp_probe(struct platform_device *pdev) - - dp_priv->drv_flags |= NSS_DP_PRIV_FLAG(INIT_DONE); - -- if (dp_priv->link_poll) { -- dp_priv->miibus = nss_dp_mdio_attach(pdev); -- if (!dp_priv->miibus) { -- netdev_dbg(netdev, "failed to find miibus\n"); -- goto phy_setup_fail; -- } -- snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, -- dp_priv->miibus->id, dp_priv->phy_mdio_addr); -- -+ if (dp_priv->phy_node) { - SET_NETDEV_DEV(netdev, &pdev->dev); -- -- dp_priv->phydev = phy_connect(netdev, phy_id, -- &nss_dp_adjust_link, -- dp_priv->phy_mii_type); -+ dp_priv->phydev = of_phy_connect(netdev, dp_priv->phy_node, -+ &nss_dp_adjust_link, 0, -+ dp_priv->phy_mii_type); - if (IS_ERR(dp_priv->phydev)) { -- netdev_dbg(netdev, "failed to connect to phy device\n"); -+ dev_err(&pdev->dev, "Could not attach to PHY\n"); - goto phy_setup_fail; - } - --#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 5, 0)) -- dp_priv->phydev->advertising |= -- (ADVERTISED_Pause | ADVERTISED_Asym_Pause); -- dp_priv->phydev->supported |= -- (SUPPORTED_Pause | SUPPORTED_Asym_Pause); --#else -- linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, dp_priv->phydev->advertising); -- linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, dp_priv->phydev->advertising); -- -- linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, dp_priv->phydev->supported); -- linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, dp_priv->phydev->supported); --#endif -+ phy_attached_info(dp_priv->phydev); - } - - #if defined(NSS_DP_PPE_SUPPORT) --- -2.36.1 - diff --git a/qca/qca-nss-dp/patches/0014-nss-dp-edma-v1-switch-to-napi_gro_receive.patch b/qca/qca-nss-dp/patches/0014-nss-dp-edma-v1-switch-to-napi_gro_receive.patch deleted file mode 100644 index 3a437bd37..000000000 --- a/qca/qca-nss-dp/patches/0014-nss-dp-edma-v1-switch-to-napi_gro_receive.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 57b521e876986844dfe34457f39c62dc8100424d Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Thu, 23 Jun 2022 14:18:50 +0200 -Subject: [PATCH] nss-dp: edma-v1: switch to napi_gro_receive - -Utilize napi_gro_receive instead of plain netif_receive_skb on EDMA v1. -It provides significant performance improvements when testing with iperf3. - -Signed-off-by: Robert Marko ---- - Makefile | 2 +- - hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c | 4 ++++ - 2 files changed, 5 insertions(+), 1 deletion(-) - -diff --git a/Makefile b/Makefile -index 8e81317..dcfa8ca 100644 ---- a/Makefile -+++ b/Makefile -@@ -25,7 +25,7 @@ qca-nss-dp-objs += hal/dp_ops/edma_dp/edma_v1/edma_cfg.o \ - hal/gmac_ops/qcom/qcom_if.o \ - hal/gmac_ops/syn/xgmac/syn_if.o - NSS_DP_INCLUDE += -I$(obj)/hal/dp_ops/edma_dp/edma_v1/include --ccflags-y += -DNSS_DP_PPE_SUPPORT -+ccflags-y += -DNSS_DP_PPE_SUPPORT -DNSS_DP_ENABLE_NAPI_GRO - endif - - ifeq ($(SoC),$(filter $(SoC),ipq807x)) -diff --git a/hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c b/hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c -index 5780a30..6ee1451 100644 ---- a/hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c -+++ b/hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c -@@ -411,7 +411,11 @@ static uint32_t edma_clean_rx(struct edma_hw *ehw, - NSS_PTP_EVENT_SERVICE_CODE)) - nss_phy_tstamp_rx_buf(ndev, skb); - else -+#if defined(NSS_DP_ENABLE_NAPI_GRO) -+ napi_gro_receive(&ehw->napi, skb); -+#else - netif_receive_skb(skb); -+#endif - - next_rx_desc: - /* --- -2.36.1 - diff --git a/qca/qca-nss-drv/Makefile b/qca/qca-nss-drv/Makefile deleted file mode 100644 index 92616caaa..000000000 --- a/qca/qca-nss-drv/Makefile +++ /dev/null @@ -1,129 +0,0 @@ -include $(TOPDIR)/rules.mk - -PKG_NAME:=qca-nss-drv -PKG_RELEASE:=$(AUTORELEASE) - -PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/nss-drv.git -PKG_SOURCE_PROTO:=git -PKG_SOURCE_DATE:=2022-03-07 -PKG_SOURCE_VERSION:=397c88cf184e0eb011dd44ad82c2dfae60ece1b4 -PKG_MIRROR_HASH:=a3bea305d85fcec3d77f9b40d06a71b65ccf3d8b98018d9c8c23d6ad95e6aedc - -PKG_BUILD_PARALLEL:=1 - -include $(INCLUDE_DIR)/kernel.mk -include $(INCLUDE_DIR)/package.mk - -NSS_CLIENTS_DIR:=$(TOPDIR)/qca/src/qca-nss-clients - -define KernelPackage/qca-nss-drv - SECTION:=kernel - CATEGORY:=Kernel modules - SUBMENU:=Network Devices - DEPENDS:=@(TARGET_ipq807x||TARGET_ipq60xx) +kmod-qca-nss-dp - TITLE:=Kernel driver for NSS (core driver) - FILES:=$(PKG_BUILD_DIR)/qca-nss-drv.ko - AUTOLOAD:=$(call AutoLoad,32,qca-nss-drv) -endef - -define KernelPackage/qca-nss-drv/install - $(INSTALL_DIR) $(1)/lib/debug - $(INSTALL_DIR) $(1)/etc/init.d - $(INSTALL_DIR) $(1)/etc/sysctl.d - $(INSTALL_DIR) $(1)/etc/hotplug.d/firmware - $(INSTALL_DIR) $(1)/etc/config - - $(INSTALL_BIN) ./files/qca-nss-drv.debug $(1)/lib/debug/qca-nss-drv - $(INSTALL_BIN) ./files/qca-nss-drv.init $(1)/etc/init.d/qca-nss-drv - $(INSTALL_BIN) ./files/qca-nss-drv.sysctl $(1)/etc/sysctl.d/qca-nss-drv.conf - $(INSTALL_BIN) ./files/qca-nss-drv.hotplug $(1)/etc/hotplug.d/firmware/10-qca-nss-fw - $(INSTALL_BIN) ./files/qca-nss-drv.conf $(1)/etc/config/nss - -endef - -define KernelPackage/qca-nss-drv/Description -This package contains a NSS driver for QCA chipset -endef - -define Build/InstallDev - mkdir -p $(1)/usr/include/qca-nss-drv - $(CP) $(PKG_BUILD_DIR)/exports/* $(1)/usr/include/qca-nss-drv/ -endef - -EXTRA_CFLAGS+= -I$(STAGING_DIR)/usr/include/qca-nss-gmac \ - -I$(STAGING_DIR)/usr/include/qca-nss-dp \ - -I$(STAGING_DIR)/usr/include/qca-ssdk \ - -Wno-unused-variable - -ifneq (, $(findstring $(CONFIG_TARGET_BOARD), "ipq807x" "ipq60xx")) -EXTRA_CFLAGS+= -DNSS_MEM_PROFILE_MEDIUM -LOW_MEM_PROFILE_MAKE_OPTS=y -endif - -ifeq ($(CONFIG_KERNEL_SKB_FIXED_SIZE_2K),y) -EXTRA_CFLAGS+= -DNSS_SKB_FIXED_SIZE_2K -endif - -DRV_MAKE_OPTS:= -ifeq ($(LOW_MEM_PROFILE_MAKE_OPTS),y) -DRV_MAKE_OPTS+= \ - NSS_DRV_C2C_ENABLE=n \ - NSS_DRV_CAPWAP_ENABLE=n \ - NSS_DRV_CLMAP_ENABLE=n \ - NSS_DRV_CRYPTO_ENABLE=y \ - NSS_DRV_DTLS_ENABLE=n \ - NSS_DRV_GRE_ENABLE=n \ - NSS_DRV_GRE_REDIR_ENABLE=n \ - NSS_DRV_GRE_TUNNEL_ENABLE=n \ - NSS_DRV_IGS_ENABLE=n \ - NSS_DRV_IPSEC_ENABLE=n \ - NSS_DRV_LAG_ENABLE=n \ - NSS_DRV_L2TP_ENABLE=n \ - NSS_DRV_MAPT_ENABLE=n \ - NSS_DRV_OAM_ENABLE=n \ - NSS_DRV_PPTP_ENABLE=n \ - NSS_DRV_PORTID_ENABLE=n \ - NSS_DRV_PVXLAN_ENABLE=n \ - NSS_DRV_QRFS_ENABLE=n \ - NSS_DRV_QVPN_ENABLE=n \ - NSS_DRV_RMNET_ENABLE=n \ - NSS_DRV_SHAPER_ENABLE=n \ - NSS_DRV_SJACK_ENABLE=n \ - NSS_DRV_TLS_ENABLE=n \ - NSS_DRV_TRUSTSEC_ENABLE=n \ - NSS_DRV_TSTAMP_ENABLE=n \ - NSS_DRV_TUN6RD_ENABLE=n \ - NSS_DRV_TUNIPIP6_ENABLE=n \ - NSS_DRV_VXLAN_ENABLE=n \ - NSS_DRV_MATCH_ENABLE=n \ - NSS_DRV_MIRROR_ENABLE=n \ - NSS_DRV_PPPOE_ENABLE=n \ - NSS_DRV_VIRT_IF_ENABLE=n \ - NSS_DRV_VLAN_ENABLE=n \ - NSS_DRV_BRIDGE_ENABLE=n \ - NSS_DRV_WIFI_EXT_VDEV_ENABLE=n \ - NSS_DRV_WIFI_MESH_ENABLE=n -endif - -ifeq ($(CONFIG_TARGET_BOARD), "ipq807x") - SOC="ipq807x_64" -else ifeq ($(CONFIG_TARGET_BOARD), "ipq60xx") - SOC="ipq60xx_64" -endif - -define Build/Configure - $(LN) arch/nss_$(SOC).h $(PKG_BUILD_DIR)/exports/nss_arch.h -endef - -define Build/Compile - +$(MAKE) -C "$(LINUX_DIR)" $(strip $(DRV_MAKE_OPTS)) \ - CROSS_COMPILE="$(TARGET_CROSS)" \ - ARCH="$(LINUX_KARCH)" \ - M="$(PKG_BUILD_DIR)" \ - EXTRA_CFLAGS="$(EXTRA_CFLAGS)" SoC=$(SOC) \ - $(KERNEL_MAKE_FLAGS) \ - $(PKG_JOBS) \ - modules -endef - -$(eval $(call KernelPackage,qca-nss-drv)) diff --git a/qca/qca-nss-drv/files/qca-nss-drv.conf b/qca/qca-nss-drv/files/qca-nss-drv.conf deleted file mode 100644 index a8a1fbf40..000000000 --- a/qca/qca-nss-drv/files/qca-nss-drv.conf +++ /dev/null @@ -1,6 +0,0 @@ -config nss_firmware 'qca_nss_0' - -config nss_firmware 'qca_nss_1' - -config general - option enable_rps '1' diff --git a/qca/qca-nss-drv/files/qca-nss-drv.debug b/qca/qca-nss-drv/files/qca-nss-drv.debug deleted file mode 100644 index 5d435c3a7..000000000 --- a/qca/qca-nss-drv/files/qca-nss-drv.debug +++ /dev/null @@ -1,26 +0,0 @@ -#!/bin/sh /sbin/sysdebug -# -# Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. -# -# Permission to use, copy, modify, and/or distribute this software for any -# purpose with or without fee is hereby granted, provided that the above -# copyright notice and this permission notice appear in all copies. -# -# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -# - -log cat /sys/kernel/debug/qca-nss-drv/stats/pppoe -log cat /sys/kernel/debug/qca-nss-drv/stats/n2h -log cat /sys/kernel/debug/qca-nss-drv/stats/ipv6 -log cat /sys/kernel/debug/qca-nss-drv/stats/ipv4 -log cat /sys/kernel/debug/qca-nss-drv/stats/gmac -log cat /sys/kernel/debug/qca-nss-drv/stats/drv -log cat /sys/kernel/debug/qca-nss-drv/stats/wifi -log cat /sys/kernel/debug/qca-nss-drv/stats/wifi_if -log cat /sys/kernel/debug/qca-nss-drv/stats/eth_rx diff --git a/qca/qca-nss-drv/files/qca-nss-drv.hotplug b/qca/qca-nss-drv/files/qca-nss-drv.hotplug deleted file mode 100644 index 1e4813838..000000000 --- a/qca/qca-nss-drv/files/qca-nss-drv.hotplug +++ /dev/null @@ -1,70 +0,0 @@ -#!/bin/sh -# -# Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. -# -# Permission to use, copy, modify, and/or distribute this software for any -# purpose with or without fee is hereby granted, provided that the above -# copyright notice and this permission notice appear in all copies. -# -# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -# - -KERNEL=`uname -r` -case "${KERNEL}" in - 3.4*) - select_or_load=load_nss_fw - ;; - *) - select_or_load=select_nss_fw - ;; -esac - -load_nss_fw () { - ls -l $1 | awk ' { print $9,$5 } '> /dev/console - echo 1 > /sys/class/firmware/$DEVICENAME/loading - cat $1 > /sys/class/firmware/$DEVICENAME/data - echo 0 > /sys/class/firmware/$DEVICENAME/loading -} - -select_nss_fw () { - rm -f /lib/firmware/$DEVICENAME - ln -s $1 /lib/firmware/$DEVICENAME - ls -l /lib/firmware/$DEVICENAME | awk ' { print $9,$5 } '> /dev/console -} - -[ "$ACTION" != "add" ] && exit - -# dev name for UCI, since it doesn't let you use . or - -SDEVNAME=$(echo ${DEVICENAME} | sed s/[.-]/_/g) - -SELECTED_FW=$(uci get nss.${SDEVNAME}.firmware 2>/dev/null) -[ -e "${SELECTED_FW}" ] && { - $select_or_load ${SELECTED_FW} - exit -} - -case $DEVICENAME in - qca-nss0* | qca-nss.0*) - if [ -e /lib/firmware/qca-nss0-enterprise.bin ] ; then - $select_or_load /lib/firmware/qca-nss0-enterprise.bin - else - $select_or_load /lib/firmware/qca-nss0-retail.bin - fi - exit - ;; - qca-nss1* | qca-nss.1*) - if [ -e /lib/firmware/qca-nss1-enterprise.bin ] ; then - $select_or_load /lib/firmware/qca-nss1-enterprise.bin - else - $select_or_load /lib/firmware/qca-nss1-retail.bin - fi - exit - ;; -esac - diff --git a/qca/qca-nss-drv/files/qca-nss-drv.init b/qca/qca-nss-drv/files/qca-nss-drv.init deleted file mode 100644 index de12cb6d1..000000000 --- a/qca/qca-nss-drv/files/qca-nss-drv.init +++ /dev/null @@ -1,50 +0,0 @@ -#!/bin/sh /etc/rc.common -# -# Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. -# -# Permission to use, copy, modify, and/or distribute this software for any -# purpose with or without fee is hereby granted, provided that the above -# copyright notice and this permission notice appear in all copies. -# -# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -# - -START=70 - -enable_rps() { - irq_nss_rps=`grep nss_queue1 /proc/interrupts | cut -d ':' -f 1 | tr -d ' '` - for entry in $irq_nss_rps - do - echo 2 > /proc/irq/$entry/smp_affinity - done - - irq_nss_rps=`grep nss_queue2 /proc/interrupts | cut -d ':' -f 1 | tr -d ' '` - for entry in $irq_nss_rps - do - echo 4 > /proc/irq/$entry/smp_affinity - done - - irq_nss_rps=`grep nss_queue3 /proc/interrupts | cut -d ':' -f 1 | tr -d ' '` - for entry in $irq_nss_rps - do - echo 8 > /proc/irq/$entry/smp_affinity - done - - # Enable NSS RPS - sysctl -w dev.nss.rps.enable=1 >/dev/null 2>/dev/null - -} - - -start() { - local rps_enabled="$(uci_get nss @general[0] enable_rps)" - if [ "$rps_enabled" -eq 1 ]; then - enable_rps - fi -} diff --git a/qca/qca-nss-drv/files/qca-nss-drv.sysctl b/qca/qca-nss-drv/files/qca-nss-drv.sysctl deleted file mode 100644 index fc36c33eb..000000000 --- a/qca/qca-nss-drv/files/qca-nss-drv.sysctl +++ /dev/null @@ -1,4 +0,0 @@ -# Default Number of connection configuration -dev.nss.ipv4cfg.ipv4_conn=4096 -dev.nss.ipv6cfg.ipv6_conn=4096 - diff --git a/qca/qca-nss-drv/patches/0001-core-add-5.10-kernel-to-version-check.patch b/qca/qca-nss-drv/patches/0001-core-add-5.10-kernel-to-version-check.patch deleted file mode 100644 index 3fea9b5ce..000000000 --- a/qca/qca-nss-drv/patches/0001-core-add-5.10-kernel-to-version-check.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 3885c752e12f74cad6c97888b797e5903ad1930d Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Thu, 13 May 2021 23:22:38 +0200 -Subject: [PATCH] core: add 5.10 kernel to version check - -NSS DRV has a kernel version check, so simply add -5.10 as supported. - -Signed-off-by: Robert Marko ---- - nss_core.c | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - ---- a/nss_core.c -+++ b/nss_core.c -@@ -52,7 +52,8 @@ - (((LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0)))) || \ - (((LINUX_VERSION_CODE >= KERNEL_VERSION(3, 18, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 19, 0)))) || \ - (((LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(4, 5, 0)))) || \ --(((LINUX_VERSION_CODE >= KERNEL_VERSION(5, 4, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 5, 0)))))) -+(((LINUX_VERSION_CODE >= KERNEL_VERSION(5, 4, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 5, 0)))) || \ -+(((LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 11, 0)))))) - #error "Check skb recycle code in this file to match Linux version" - #endif - diff --git a/qca/qca-nss-drv/patches/0002-nss-drv-replace-ioremap_nocache-with-ioremap.patch b/qca/qca-nss-drv/patches/0002-nss-drv-replace-ioremap_nocache-with-ioremap.patch deleted file mode 100644 index 89d650be1..000000000 --- a/qca/qca-nss-drv/patches/0002-nss-drv-replace-ioremap_nocache-with-ioremap.patch +++ /dev/null @@ -1,181 +0,0 @@ -From 0cffa7bb366a4e0ff5665d6fc2fa33c1437cb397 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Thu, 13 May 2021 23:33:18 +0200 -Subject: [PATCH 2/8] nss-drv: replace ioremap_nocache() with ioremap() - -ioremap_nocache() does not exist anymore. - -Signed-off-by: Robert Marko ---- - nss_hal/ipq50xx/nss_hal_pvt.c | 6 +++--- - nss_hal/ipq60xx/nss_hal_pvt.c | 8 ++++---- - nss_hal/ipq806x/nss_hal_pvt.c | 4 ++-- - nss_hal/ipq807x/nss_hal_pvt.c | 6 +++--- - nss_hal/nss_hal.c | 4 ++-- - nss_meminfo.c | 2 +- - nss_ppe.c | 2 +- - 7 files changed, 16 insertions(+), 16 deletions(-) - -diff --git a/nss_hal/ipq50xx/nss_hal_pvt.c b/nss_hal/ipq50xx/nss_hal_pvt.c -index 3d6dfd0..e3e4bd2 100644 ---- a/nss_hal/ipq50xx/nss_hal_pvt.c -+++ b/nss_hal/ipq50xx/nss_hal_pvt.c -@@ -184,13 +184,13 @@ static struct nss_platform_data *__nss_hal_of_get_pdata(struct platform_device * - npd->nphys = res_nphys.start; - npd->qgic_phys = res_qgic_phys.start; - -- npd->nmap = ioremap_nocache(npd->nphys, resource_size(&res_nphys)); -+ npd->nmap = ioremap(npd->nphys, resource_size(&res_nphys)); - if (!npd->nmap) { - nss_info_always("%px: nss%d: ioremap() fail for nphys\n", nss_ctx, nss_ctx->id); - goto out; - } - -- npd->qgic_map = ioremap_nocache(npd->qgic_phys, resource_size(&res_qgic_phys)); -+ npd->qgic_map = ioremap(npd->qgic_phys, resource_size(&res_qgic_phys)); - if (!npd->qgic_map) { - nss_info_always("%px: nss%d: ioremap() fail for qgic map\n", nss_ctx, nss_ctx->id); - goto out; -@@ -348,7 +348,7 @@ static int __nss_hal_common_reset(struct platform_device *nss_dev) - - of_node_put(cmn); - -- nss_misc_reset = ioremap_nocache(res_nss_misc_reset.start, resource_size(&res_nss_misc_reset)); -+ nss_misc_reset = ioremap(res_nss_misc_reset.start, resource_size(&res_nss_misc_reset)); - if (!nss_misc_reset) { - pr_err("%px: ioremap fail for nss_misc_reset\n", nss_dev); - return -EFAULT; -diff --git a/nss_hal/ipq60xx/nss_hal_pvt.c b/nss_hal/ipq60xx/nss_hal_pvt.c -index 4c84cb9..e76ef6d 100644 ---- a/nss_hal/ipq60xx/nss_hal_pvt.c -+++ b/nss_hal/ipq60xx/nss_hal_pvt.c -@@ -207,13 +207,13 @@ static struct nss_platform_data *__nss_hal_of_get_pdata(struct platform_device * - npd->nphys = res_nphys.start; - npd->qgic_phys = res_qgic_phys.start; - -- npd->nmap = ioremap_nocache(npd->nphys, resource_size(&res_nphys)); -+ npd->nmap = ioremap(npd->nphys, resource_size(&res_nphys)); - if (!npd->nmap) { - nss_info_always("%px: nss%d: ioremap() fail for nphys\n", nss_ctx, nss_ctx->id); - goto out; - } - -- npd->qgic_map = ioremap_nocache(npd->qgic_phys, resource_size(&res_qgic_phys)); -+ npd->qgic_map = ioremap(npd->qgic_phys, resource_size(&res_qgic_phys)); - if (!npd->qgic_map) { - nss_info_always("%px: nss%d: ioremap() fail for qgic map\n", nss_ctx, nss_ctx->id); - goto out; -@@ -433,13 +433,13 @@ static int __nss_hal_common_reset(struct platform_device *nss_dev) - - of_node_put(cmn); - -- nss_misc_reset = ioremap_nocache(res_nss_misc_reset.start, resource_size(&res_nss_misc_reset)); -+ nss_misc_reset = ioremap(res_nss_misc_reset.start, resource_size(&res_nss_misc_reset)); - if (!nss_misc_reset) { - pr_err("%px: ioremap fail for nss_misc_reset\n", nss_dev); - return -EFAULT; - } - -- nss_misc_reset_flag = ioremap_nocache(res_nss_misc_reset_flag.start, resource_size(&res_nss_misc_reset_flag)); -+ nss_misc_reset_flag = ioremap(res_nss_misc_reset_flag.start, resource_size(&res_nss_misc_reset_flag)); - if (!nss_misc_reset_flag) { - pr_err("%px: ioremap fail for nss_misc_reset_flag\n", nss_dev); - return -EFAULT; -diff --git a/nss_hal/ipq806x/nss_hal_pvt.c b/nss_hal/ipq806x/nss_hal_pvt.c -index b8733e0..52d63b0 100644 ---- a/nss_hal/ipq806x/nss_hal_pvt.c -+++ b/nss_hal/ipq806x/nss_hal_pvt.c -@@ -458,7 +458,7 @@ static struct nss_platform_data *__nss_hal_of_get_pdata(struct platform_device * - npd->nphys = res_nphys.start; - npd->vphys = res_vphys.start; - -- npd->nmap = ioremap_nocache(npd->nphys, resource_size(&res_nphys)); -+ npd->nmap = ioremap(npd->nphys, resource_size(&res_nphys)); - if (!npd->nmap) { - nss_info_always("%px: nss%d: ioremap() fail for nphys\n", nss_ctx, nss_ctx->id); - goto out; -@@ -711,7 +711,7 @@ static int __nss_hal_common_reset(struct platform_device *nss_dev) - } - of_node_put(cmn); - -- fpb_base = ioremap_nocache(res_nss_fpb_base.start, resource_size(&res_nss_fpb_base)); -+ fpb_base = ioremap(res_nss_fpb_base.start, resource_size(&res_nss_fpb_base)); - if (!fpb_base) { - pr_err("%px: ioremap fail for nss_fpb_base\n", nss_dev); - return -EFAULT; -diff --git a/nss_hal/ipq807x/nss_hal_pvt.c b/nss_hal/ipq807x/nss_hal_pvt.c -index b95a23c..bb8f42f 100644 ---- a/nss_hal/ipq807x/nss_hal_pvt.c -+++ b/nss_hal/ipq807x/nss_hal_pvt.c -@@ -234,7 +234,7 @@ static struct nss_platform_data *__nss_hal_of_get_pdata(struct platform_device * - npd->vphys = res_vphys.start; - npd->qgic_phys = res_qgic_phys.start; - -- npd->nmap = ioremap_nocache(npd->nphys, resource_size(&res_nphys)); -+ npd->nmap = ioremap(npd->nphys, resource_size(&res_nphys)); - if (!npd->nmap) { - nss_info_always("%px: nss%d: ioremap() fail for nphys\n", nss_ctx, nss_ctx->id); - goto out; -@@ -247,7 +247,7 @@ static struct nss_platform_data *__nss_hal_of_get_pdata(struct platform_device * - goto out; - } - -- npd->qgic_map = ioremap_nocache(npd->qgic_phys, resource_size(&res_qgic_phys)); -+ npd->qgic_map = ioremap(npd->qgic_phys, resource_size(&res_qgic_phys)); - if (!npd->qgic_map) { - nss_info_always("%px: nss%d: ioremap() fail for qgic map\n", nss_ctx, nss_ctx->id); - goto out; -@@ -467,7 +467,7 @@ static int __nss_hal_common_reset(struct platform_device *nss_dev) - } - of_node_put(cmn); - -- nss_misc_reset = ioremap_nocache(res_nss_misc_reset.start, resource_size(&res_nss_misc_reset)); -+ nss_misc_reset = ioremap(res_nss_misc_reset.start, resource_size(&res_nss_misc_reset)); - if (!nss_misc_reset) { - pr_err("%px: ioremap fail for nss_misc_reset\n", nss_dev); - return -EFAULT; -diff --git a/nss_hal/nss_hal.c b/nss_hal/nss_hal.c -index d58bb57..57974c1 100644 ---- a/nss_hal/nss_hal.c -+++ b/nss_hal/nss_hal.c -@@ -78,9 +78,9 @@ int nss_hal_firmware_load(struct nss_ctx_instance *nss_ctx, struct platform_devi - return rc; - } - -- load_mem = ioremap_nocache(npd->load_addr, nss_fw->size); -+ load_mem = ioremap(npd->load_addr, nss_fw->size); - if (!load_mem) { -- nss_info_always("%px: ioremap_nocache failed: %x", nss_ctx, npd->load_addr); -+ nss_info_always("%px: ioremap failed: %x", nss_ctx, npd->load_addr); - release_firmware(nss_fw); - return rc; - } -diff --git a/nss_meminfo.c b/nss_meminfo.c -index e24e6be..2255eae 100644 ---- a/nss_meminfo.c -+++ b/nss_meminfo.c -@@ -728,7 +728,7 @@ bool nss_meminfo_init(struct nss_ctx_instance *nss_ctx) - /* - * meminfo_start is the label where the start address of meminfo map is stored. - */ -- meminfo_start = (uint32_t *)ioremap_nocache(nss_ctx->load + NSS_MEMINFO_MAP_START_OFFSET, -+ meminfo_start = (uint32_t *)ioremap(nss_ctx->load + NSS_MEMINFO_MAP_START_OFFSET, - NSS_MEMINFO_RESERVE_AREA_SIZE); - if (!meminfo_start) { - nss_info_always("%px: cannot remap meminfo start\n", nss_ctx); -diff --git a/nss_ppe.c b/nss_ppe.c -index 46ce217..644fc98 100644 ---- a/nss_ppe.c -+++ b/nss_ppe.c -@@ -357,7 +357,7 @@ void nss_ppe_init(void) - /* - * Get the PPE base address - */ -- ppe_pvt.ppe_base = ioremap_nocache(PPE_BASE_ADDR, PPE_REG_SIZE); -+ ppe_pvt.ppe_base = ioremap(PPE_BASE_ADDR, PPE_REG_SIZE); - if (!ppe_pvt.ppe_base) { - nss_warning("DRV can't get PPE base address\n"); - return; --- -2.34.1 - diff --git a/qca/qca-nss-drv/patches/0003-DMA-Fix-NULL-pointer-exceptions.patch b/qca/qca-nss-drv/patches/0003-DMA-Fix-NULL-pointer-exceptions.patch deleted file mode 100644 index 0c13a7887..000000000 --- a/qca/qca-nss-drv/patches/0003-DMA-Fix-NULL-pointer-exceptions.patch +++ /dev/null @@ -1,49 +0,0 @@ -From 62e457f262aaa0db7113ad3ccbcb7ae49d4d7ea8 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Tue, 8 Jun 2021 23:24:43 +0200 -Subject: [PATCH] DMA: Fix NULL pointer exceptions - -There are multiple instances that pass NULL instead -of device to DMA functions. -That is incorrect and will cause kernel NULL pointer -exceptions. - -So, simply pass the device structure pointers. - -Signed-off-by: Robert Marko ---- - nss_core.c | 2 +- - nss_coredump.c | 4 ++-- - 2 files changed, 3 insertions(+), 3 deletions(-) - ---- a/nss_core.c -+++ b/nss_core.c -@@ -1617,7 +1617,7 @@ static int32_t nss_core_handle_cause_que - * - */ - if (unlikely((buffer_type == N2H_BUFFER_CRYPTO_RESP))) { -- dma_unmap_single(NULL, (desc->buffer + desc->payload_offs), desc->payload_len, DMA_FROM_DEVICE); -+ dma_unmap_single(nss_ctx->dev, (desc->buffer + desc->payload_offs), desc->payload_len, DMA_FROM_DEVICE); - goto consume; - } - ---- a/nss_coredump.c -+++ b/nss_coredump.c -@@ -154,7 +154,7 @@ void nss_fw_coredump_notify(struct nss_c - dma_addr = nss_own->meminfo_ctx.logbuffer_dma; - } - -- dma_sync_single_for_cpu(NULL, dma_addr, sizeof(struct nss_log_descriptor), DMA_FROM_DEVICE); -+ dma_sync_single_for_cpu(nss_own->dev, dma_addr, sizeof(struct nss_log_descriptor), DMA_FROM_DEVICE); - - /* - * If the current entry is smaller than or equal to the number of NSS_LOG_COREDUMP_LINE_NUM, -@@ -181,7 +181,7 @@ void nss_fw_coredump_notify(struct nss_c - - offset = (index * sizeof(struct nss_log_entry)) - + offsetof(struct nss_log_descriptor, log_ring_buffer); -- dma_sync_single_for_cpu(NULL, dma_addr + offset, -+ dma_sync_single_for_cpu(nss_own->dev, dma_addr + offset, - sizeof(struct nss_log_entry), DMA_FROM_DEVICE); - nss_info_always("%px: %s\n", nss_own, nle_print->message); - nle_print++; diff --git a/qca/qca-nss-drv/patches/0004-nss-drv-rework-NSS_CORE_DMA_CACHE_MAINT-ops.patch b/qca/qca-nss-drv/patches/0004-nss-drv-rework-NSS_CORE_DMA_CACHE_MAINT-ops.patch deleted file mode 100644 index 6ef442aad..000000000 --- a/qca/qca-nss-drv/patches/0004-nss-drv-rework-NSS_CORE_DMA_CACHE_MAINT-ops.patch +++ /dev/null @@ -1,573 +0,0 @@ -From 12cf63f66bfe509da6d845e5c716efd99dadf01e Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Tue, 5 Apr 2022 15:38:18 +0200 -Subject: [PATCH 4/8] nss-drv: rework NSS_CORE_DMA_CACHE_MAINT ops - -Rework NSS_CORE_DMA_CACHE_MAINT ops to use standard dma sync ops instead -of using the direct arch function. This permit to skip any hack/patch -needed for nss-drv to correctly compile on upstream kernel. - -We drop any NSS_CORE_DMA_CACHE_MAINT use in nss_core and we correctly -use the dma_sync_single_for_device we correctly dma addr using the new -DMA helper. -We drop sync for IOREMAP addr and we just leave a memory block. -We hope the nss_profiler is correctly ported. -We finally drop the NSS_CORE_DMA_CACHE_MAINT jus in case someone wants -to use it. - -Signed-off-by: Ansuel Smith ---- - nss_core.c | 136 +++++++++++++++++++++++++--------- - nss_core.h | 41 +++++----- - nss_hal/ipq806x/nss_hal_pvt.c | 5 +- - nss_hal/ipq807x/nss_hal_pvt.c | 5 +- - nss_meminfo.c | 5 +- - nss_profiler.c | 3 +- - 6 files changed, 127 insertions(+), 68 deletions(-) - -diff --git a/nss_core.c b/nss_core.c -index 23dc155..f9e6014 100644 ---- a/nss_core.c -+++ b/nss_core.c -@@ -1429,6 +1429,8 @@ static inline void nss_core_handle_empty_buffers(struct nss_ctx_instance *nss_ct - uint32_t count, uint32_t hlos_index, - uint16_t mask) - { -+ struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; -+ - while (count) { - /* - * Since we only return the primary skb, we have no way to unmap -@@ -1482,7 +1484,9 @@ next: - n2h_desc_ring->hlos_index = hlos_index; - if_map->n2h_hlos_index[NSS_IF_N2H_EMPTY_BUFFER_RETURN_QUEUE] = hlos_index; - -- NSS_CORE_DMA_CACHE_MAINT((void *)&if_map->n2h_hlos_index[NSS_IF_N2H_EMPTY_BUFFER_RETURN_QUEUE], sizeof(uint32_t), DMA_TO_DEVICE); -+ dma_sync_single_for_device(nss_ctx->dev, -+ n2h_hlos_index_to_dma(mem_ctx->if_map_dma, NSS_IF_N2H_EMPTY_BUFFER_RETURN_QUEUE), -+ sizeof(uint32_t), DMA_TO_DEVICE); - NSS_CORE_DSB(); - } - -@@ -1504,6 +1508,7 @@ static int32_t nss_core_handle_cause_queue(struct int_ctx_instance *int_ctx, uin - struct nss_ctx_instance *nss_ctx = int_ctx->nss_ctx; - struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; - struct nss_if_mem_map *if_map = mem_ctx->if_map; -+ int dma_size; - - qid = nss_core_cause_to_queue(cause); - -@@ -1515,7 +1520,8 @@ static int32_t nss_core_handle_cause_queue(struct int_ctx_instance *int_ctx, uin - n2h_desc_ring = &nss_ctx->n2h_desc_ring[qid]; - desc_if = &n2h_desc_ring->desc_ring; - desc_ring = desc_if->desc; -- NSS_CORE_DMA_CACHE_MAINT((void *)&if_map->n2h_nss_index[qid], sizeof(uint32_t), DMA_FROM_DEVICE); -+ dma_sync_single_for_device(nss_ctx->dev, n2h_nss_index_to_dma(mem_ctx->if_map_dma, qid), -+ sizeof(uint32_t), DMA_FROM_DEVICE); - NSS_CORE_DSB(); - nss_index = if_map->n2h_nss_index[qid]; - -@@ -1544,13 +1550,23 @@ static int32_t nss_core_handle_cause_queue(struct int_ctx_instance *int_ctx, uin - start = hlos_index; - end = (hlos_index + count) & mask; - if (end > start) { -- dmac_inv_range((void *)&desc_ring[start], (void *)&desc_ring[end] + sizeof(struct n2h_descriptor)); -+ dma_size = sizeof(struct n2h_descriptor) * (end - start + 1); -+ -+ dma_sync_single_for_device(nss_ctx->dev, n2h_desc_index_to_dma(if_map, qid, start), -+ dma_size, DMA_FROM_DEVICE); - } else { - /* - * We have wrapped around - */ -- dmac_inv_range((void *)&desc_ring[start], (void *)&desc_ring[mask] + sizeof(struct n2h_descriptor)); -- dmac_inv_range((void *)&desc_ring[0], (void *)&desc_ring[end] + sizeof(struct n2h_descriptor)); -+ dma_size = sizeof(struct n2h_descriptor) * (mask - start + 1); -+ -+ dma_sync_single_for_device(nss_ctx->dev, n2h_desc_index_to_dma(if_map, qid, start), -+ dma_size, DMA_FROM_DEVICE); -+ -+ dma_size = sizeof(struct n2h_descriptor) * (end + 1); -+ -+ dma_sync_single_for_device(nss_ctx->dev, n2h_desc_index_to_dma(if_map, qid, 0), dma_size, -+ DMA_FROM_DEVICE); - } - - /* -@@ -1679,7 +1695,8 @@ next: - n2h_desc_ring->hlos_index = hlos_index; - if_map->n2h_hlos_index[qid] = hlos_index; - -- NSS_CORE_DMA_CACHE_MAINT((void *)&if_map->n2h_hlos_index[qid], sizeof(uint32_t), DMA_TO_DEVICE); -+ dma_sync_single_for_device(nss_ctx->dev, n2h_hlos_index_to_dma(mem_ctx->if_map_dma, qid), -+ sizeof(uint32_t), DMA_TO_DEVICE); - NSS_CORE_DSB(); - - return count; -@@ -1691,11 +1708,12 @@ next: - */ - static void nss_core_init_nss(struct nss_ctx_instance *nss_ctx, struct nss_if_mem_map *if_map) - { -+ struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; - struct nss_top_instance *nss_top; - int ret; - int i; - -- NSS_CORE_DMA_CACHE_MAINT((void *)if_map, sizeof(*if_map), DMA_FROM_DEVICE); -+ dma_sync_single_for_device(nss_ctx->dev, mem_ctx->if_map_dma, sizeof(*if_map), DMA_FROM_DEVICE); - NSS_CORE_DSB(); - - /* -@@ -1762,6 +1780,7 @@ static void nss_core_alloc_paged_buffers(struct nss_ctx_instance *nss_ctx, struc - uint16_t count, int16_t mask, int32_t hlos_index, uint32_t alloc_fail_count, - uint32_t buffer_type, uint32_t buffer_queue, uint32_t stats_index) - { -+ struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; - struct sk_buff *nbuf; - struct page *npage; - struct hlos_h2n_desc_rings *h2n_desc_ring = &nss_ctx->h2n_desc_rings[buffer_queue]; -@@ -1831,7 +1850,9 @@ static void nss_core_alloc_paged_buffers(struct nss_ctx_instance *nss_ctx, struc - /* - * Flush the descriptor - */ -- NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE); -+ dma_sync_single_for_device(nss_ctx->dev, -+ h2n_desc_index_to_dma(if_map, buffer_queue, hlos_index), -+ sizeof(*desc), DMA_TO_DEVICE); - - hlos_index = (hlos_index + 1) & (mask); - count--; -@@ -1845,7 +1866,8 @@ static void nss_core_alloc_paged_buffers(struct nss_ctx_instance *nss_ctx, struc - h2n_desc_ring->hlos_index = hlos_index; - if_map->h2n_hlos_index[buffer_queue] = hlos_index; - -- NSS_CORE_DMA_CACHE_MAINT(&if_map->h2n_hlos_index[buffer_queue], sizeof(uint32_t), DMA_TO_DEVICE); -+ dma_sync_single_for_device(nss_ctx->dev, h2n_hlos_index_to_dma(mem_ctx->if_map_dma, buffer_queue), -+ sizeof(uint32_t), DMA_TO_DEVICE); - NSS_CORE_DSB(); - - NSS_PKT_STATS_INC(&nss_top->stats_drv[stats_index]); -@@ -1858,7 +1880,7 @@ static void nss_core_alloc_paged_buffers(struct nss_ctx_instance *nss_ctx, struc - static void nss_core_alloc_jumbo_mru_buffers(struct nss_ctx_instance *nss_ctx, struct nss_if_mem_map *if_map, - int jumbo_mru, uint16_t count, int16_t mask, int32_t hlos_index) - { -- -+ struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; - struct sk_buff *nbuf; - struct hlos_h2n_desc_rings *h2n_desc_ring = &nss_ctx->h2n_desc_rings[NSS_IF_H2N_EMPTY_BUFFER_QUEUE]; - struct h2n_desc_if_instance *desc_if = &h2n_desc_ring->desc_ring; -@@ -1905,7 +1927,9 @@ static void nss_core_alloc_jumbo_mru_buffers(struct nss_ctx_instance *nss_ctx, s - /* - * Flush the descriptor - */ -- NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE); -+ dma_sync_single_for_device(nss_ctx->dev, -+ h2n_desc_index_to_dma(if_map, NSS_IF_H2N_EMPTY_BUFFER_QUEUE, hlos_index), -+ sizeof(*desc), DMA_TO_DEVICE); - - hlos_index = (hlos_index + 1) & (mask); - count--; -@@ -1919,7 +1943,8 @@ static void nss_core_alloc_jumbo_mru_buffers(struct nss_ctx_instance *nss_ctx, s - h2n_desc_ring->hlos_index = hlos_index; - if_map->h2n_hlos_index[NSS_IF_H2N_EMPTY_BUFFER_QUEUE] = hlos_index; - -- NSS_CORE_DMA_CACHE_MAINT(&if_map->h2n_hlos_index[NSS_IF_H2N_EMPTY_BUFFER_QUEUE], sizeof(uint32_t), DMA_TO_DEVICE); -+ dma_sync_single_for_device(nss_ctx->dev, h2n_hlos_index_to_dma(mem_ctx->if_map_dma, NSS_IF_H2N_EMPTY_BUFFER_QUEUE), -+ sizeof(uint32_t), DMA_TO_DEVICE); - NSS_CORE_DSB(); - - NSS_PKT_STATS_INC(&nss_top->stats_drv[NSS_DRV_STATS_TX_EMPTY]); -@@ -1932,6 +1957,7 @@ static void nss_core_alloc_jumbo_mru_buffers(struct nss_ctx_instance *nss_ctx, s - static void nss_core_alloc_max_avail_size_buffers(struct nss_ctx_instance *nss_ctx, struct nss_if_mem_map *if_map, - uint16_t max_buf_size, uint16_t count, int16_t mask, int32_t hlos_index) - { -+ struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; - struct hlos_h2n_desc_rings *h2n_desc_ring = &nss_ctx->h2n_desc_rings[NSS_IF_H2N_EMPTY_BUFFER_QUEUE]; - struct h2n_desc_if_instance *desc_if = &h2n_desc_ring->desc_ring; - struct h2n_descriptor *desc_ring = desc_if->desc; -@@ -1939,6 +1965,7 @@ static void nss_core_alloc_max_avail_size_buffers(struct nss_ctx_instance *nss_c - uint16_t payload_len = max_buf_size + NET_SKB_PAD; - uint16_t start = hlos_index; - uint16_t prev_hlos_index; -+ int dma_size; - - while (count) { - dma_addr_t buffer; -@@ -1991,13 +2018,26 @@ static void nss_core_alloc_max_avail_size_buffers(struct nss_ctx_instance *nss_c - * Flush the descriptors, including the descriptor at prev_hlos_index. - */ - if (prev_hlos_index > start) { -- dmac_clean_range((void *)&desc_ring[start], (void *)&desc_ring[prev_hlos_index] + sizeof(struct h2n_descriptor)); -+ dma_size = sizeof(struct h2n_descriptor) * (prev_hlos_index - start + 1); -+ -+ dma_sync_single_for_device(nss_ctx->dev, -+ h2n_desc_index_to_dma(if_map, NSS_IF_H2N_EMPTY_BUFFER_QUEUE, start), -+ dma_size, DMA_TO_DEVICE); - } else { - /* - * We have wrapped around - */ -- dmac_clean_range((void *)&desc_ring[start], (void *)&desc_ring[mask] + sizeof(struct h2n_descriptor)); -- dmac_clean_range((void *)&desc_ring[0], (void *)&desc_ring[prev_hlos_index] + sizeof(struct h2n_descriptor)); -+ dma_size = sizeof(struct h2n_descriptor) * (mask - start + 1); -+ -+ dma_sync_single_for_device(nss_ctx->dev, -+ h2n_desc_index_to_dma(if_map, NSS_IF_H2N_EMPTY_BUFFER_QUEUE, start), -+ dma_size, DMA_TO_DEVICE); -+ -+ dma_size = sizeof(struct h2n_descriptor) * (prev_hlos_index + 1); -+ -+ dma_sync_single_for_device(nss_ctx->dev, -+ h2n_desc_index_to_dma(if_map, NSS_IF_H2N_EMPTY_BUFFER_QUEUE, 0), -+ dma_size, DMA_TO_DEVICE); - } - - /* -@@ -2008,7 +2048,8 @@ static void nss_core_alloc_max_avail_size_buffers(struct nss_ctx_instance *nss_c - h2n_desc_ring->hlos_index = hlos_index; - if_map->h2n_hlos_index[NSS_IF_H2N_EMPTY_BUFFER_QUEUE] = hlos_index; - -- NSS_CORE_DMA_CACHE_MAINT(&if_map->h2n_hlos_index[NSS_IF_H2N_EMPTY_BUFFER_QUEUE], sizeof(uint32_t), DMA_TO_DEVICE); -+ dma_sync_single_for_device(nss_ctx->dev, h2n_hlos_index_to_dma(mem_ctx->if_map_dma, NSS_IF_H2N_EMPTY_BUFFER_QUEUE), -+ sizeof(uint32_t), DMA_TO_DEVICE); - NSS_CORE_DSB(); - - NSS_PKT_STATS_INC(&nss_top->stats_drv[NSS_DRV_STATS_TX_EMPTY]); -@@ -2021,6 +2062,7 @@ static void nss_core_alloc_max_avail_size_buffers(struct nss_ctx_instance *nss_c - static inline void nss_core_handle_empty_buffer_sos(struct nss_ctx_instance *nss_ctx, - struct nss_if_mem_map *if_map, uint16_t max_buf_size) - { -+ struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; - uint16_t count, size, mask; - int32_t nss_index, hlos_index; - struct hlos_h2n_desc_rings *h2n_desc_ring = &nss_ctx->h2n_desc_rings[NSS_IF_H2N_EMPTY_BUFFER_QUEUE]; -@@ -2031,7 +2073,8 @@ static inline void nss_core_handle_empty_buffer_sos(struct nss_ctx_instance *nss - /* - * Check how many empty buffers could be filled in queue - */ -- NSS_CORE_DMA_CACHE_MAINT(&if_map->h2n_nss_index[NSS_IF_H2N_EMPTY_BUFFER_QUEUE], sizeof(uint32_t), DMA_FROM_DEVICE); -+ dma_sync_single_for_device(nss_ctx->dev, h2n_nss_index_to_dma(mem_ctx->if_map_dma, NSS_IF_H2N_EMPTY_BUFFER_QUEUE), -+ sizeof(uint32_t), DMA_FROM_DEVICE); - NSS_CORE_DSB(); - nss_index = if_map->h2n_nss_index[NSS_IF_H2N_EMPTY_BUFFER_QUEUE]; - -@@ -2076,6 +2119,7 @@ static inline void nss_core_handle_empty_buffer_sos(struct nss_ctx_instance *nss - static inline void nss_core_handle_paged_empty_buffer_sos(struct nss_ctx_instance *nss_ctx, - struct nss_if_mem_map *if_map, uint16_t max_buf_size) - { -+ struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; - uint16_t count, size, mask; - int32_t nss_index, hlos_index; - struct hlos_h2n_desc_rings *h2n_desc_ring = &nss_ctx->h2n_desc_rings[NSS_IF_H2N_EMPTY_PAGED_BUFFER_QUEUE]; -@@ -2083,7 +2127,8 @@ static inline void nss_core_handle_paged_empty_buffer_sos(struct nss_ctx_instanc - /* - * Check how many empty buffers could be filled in queue - */ -- NSS_CORE_DMA_CACHE_MAINT((void *)&if_map->h2n_nss_index[NSS_IF_H2N_EMPTY_PAGED_BUFFER_QUEUE], sizeof(uint32_t), DMA_FROM_DEVICE); -+ dma_sync_single_for_device(nss_ctx->dev, h2n_nss_index_to_dma(mem_ctx->if_map_dma, NSS_IF_H2N_EMPTY_PAGED_BUFFER_QUEUE), -+ sizeof(uint32_t), DMA_FROM_DEVICE); - NSS_CORE_DSB(); - nss_index = if_map->h2n_nss_index[NSS_IF_H2N_EMPTY_PAGED_BUFFER_QUEUE]; - -@@ -2651,9 +2696,11 @@ void nss_skb_reuse(struct sk_buff *nbuf) - * Sends one skb to NSS FW - */ - static inline int32_t nss_core_send_buffer_simple_skb(struct nss_ctx_instance *nss_ctx, -- struct h2n_desc_if_instance *desc_if, uint32_t if_num, -- struct sk_buff *nbuf, uint16_t hlos_index, uint16_t flags, uint8_t buffer_type, uint16_t mss) -+ struct h2n_desc_if_instance *desc_if, uint32_t if_num, struct sk_buff *nbuf, -+ uint16_t qid, uint16_t hlos_index, uint16_t flags, uint8_t buffer_type, uint16_t mss) - { -+ struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; -+ struct nss_if_mem_map *if_map = mem_ctx->if_map; - struct h2n_descriptor *desc_ring = desc_if->desc; - struct h2n_descriptor *desc; - uint16_t bit_flags; -@@ -2707,7 +2754,8 @@ static inline int32_t nss_core_send_buffer_simple_skb(struct nss_ctx_instance *n - (nss_ptr_t)nbuf, (uint16_t)(nbuf->data - nbuf->head), nbuf->len, - sz, (uint32_t)nbuf->priority, mss, bit_flags); - -- NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE); -+ dma_sync_single_for_device(nss_ctx->dev, h2n_desc_index_to_dma(if_map, qid, hlos_index), -+ sizeof(*desc), DMA_TO_DEVICE); - - /* - * We are done using the skb fields and can reuse it now -@@ -2731,7 +2779,8 @@ no_reuse: - (nss_ptr_t)nbuf, (uint16_t)(nbuf->data - nbuf->head), nbuf->len, - (uint16_t)skb_end_offset(nbuf), (uint32_t)nbuf->priority, mss, bit_flags); - -- NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE); -+ dma_sync_single_for_device(nss_ctx->dev, h2n_desc_index_to_dma(if_map, qid, hlos_index), -+ sizeof(*desc), DMA_TO_DEVICE); - - NSS_PKT_STATS_INC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_TX_SIMPLE]); - return 1; -@@ -2745,9 +2794,11 @@ no_reuse: - * Used to differentiate from FRAGLIST - */ - static inline int32_t nss_core_send_buffer_nr_frags(struct nss_ctx_instance *nss_ctx, -- struct h2n_desc_if_instance *desc_if, uint32_t if_num, -- struct sk_buff *nbuf, uint16_t hlos_index, uint16_t flags, uint8_t buffer_type, uint16_t mss) -+ struct h2n_desc_if_instance *desc_if, uint32_t if_num, struct sk_buff *nbuf, -+ uint16_t qid, uint16_t hlos_index, uint16_t flags, uint8_t buffer_type, uint16_t mss) - { -+ struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; -+ struct nss_if_mem_map *if_map = mem_ctx->if_map; - struct h2n_descriptor *desc_ring = desc_if->desc; - struct h2n_descriptor *desc; - const skb_frag_t *frag; -@@ -2787,7 +2838,8 @@ static inline int32_t nss_core_send_buffer_nr_frags(struct nss_ctx_instance *nss - (nss_ptr_t)NULL, nbuf->data - nbuf->head, nbuf->len - nbuf->data_len, - skb_end_offset(nbuf), (uint32_t)nbuf->priority, mss, bit_flags | H2N_BIT_FLAG_FIRST_SEGMENT); - -- NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE); -+ dma_sync_single_for_device(nss_ctx->dev, h2n_desc_index_to_dma(if_map, qid, hlos_index), -+ sizeof(*desc), DMA_TO_DEVICE); - - /* - * Now handle rest of the fragments. -@@ -2811,7 +2863,8 @@ static inline int32_t nss_core_send_buffer_nr_frags(struct nss_ctx_instance *nss - (nss_ptr_t)NULL, 0, skb_frag_size(frag), skb_frag_size(frag), - nbuf->priority, mss, bit_flags); - -- NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE); -+ dma_sync_single_for_device(nss_ctx->dev, h2n_desc_index_to_dma(if_map, qid, hlos_index), -+ sizeof(*desc), DMA_TO_DEVICE); - } - - /* -@@ -2827,7 +2880,8 @@ static inline int32_t nss_core_send_buffer_nr_frags(struct nss_ctx_instance *nss - desc->bit_flags &= ~(H2N_BIT_FLAG_DISCARD); - desc->opaque = (nss_ptr_t)nbuf; - -- NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE); -+ dma_sync_single_for_device(nss_ctx->dev, h2n_desc_index_to_dma(if_map, qid, hlos_index), -+ sizeof(*desc), DMA_TO_DEVICE); - - NSS_PKT_STATS_INC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_TX_NR_FRAGS]); - return i+1; -@@ -2841,9 +2895,11 @@ static inline int32_t nss_core_send_buffer_nr_frags(struct nss_ctx_instance *nss - * Used to differentiate from FRAGS - */ - static inline int32_t nss_core_send_buffer_fraglist(struct nss_ctx_instance *nss_ctx, -- struct h2n_desc_if_instance *desc_if, uint32_t if_num, -- struct sk_buff *nbuf, uint16_t hlos_index, uint16_t flags, uint8_t buffer_type, uint16_t mss) -+ struct h2n_desc_if_instance *desc_if, uint32_t if_num, struct sk_buff *nbuf, -+ uint16_t qid, uint16_t hlos_index, uint16_t flags, uint8_t buffer_type, uint16_t mss) - { -+ struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; -+ struct nss_if_mem_map *if_map = mem_ctx->if_map; - struct h2n_descriptor *desc_ring = desc_if->desc; - struct h2n_descriptor *desc; - dma_addr_t buffer; -@@ -2882,7 +2938,8 @@ static inline int32_t nss_core_send_buffer_fraglist(struct nss_ctx_instance *nss - (nss_ptr_t)nbuf, nbuf->data - nbuf->head, nbuf->len - nbuf->data_len, - skb_end_offset(nbuf), (uint32_t)nbuf->priority, mss, bit_flags | H2N_BIT_FLAG_FIRST_SEGMENT); - -- NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE); -+ dma_sync_single_for_device(nss_ctx->dev, h2n_desc_index_to_dma(if_map, qid, hlos_index), -+ sizeof(*desc), DMA_TO_DEVICE); - - /* - * Walk the frag_list in nbuf -@@ -2935,7 +2992,8 @@ static inline int32_t nss_core_send_buffer_fraglist(struct nss_ctx_instance *nss - (nss_ptr_t)iter, iter->data - iter->head, iter->len - iter->data_len, - skb_end_offset(iter), iter->priority, mss, bit_flags); - -- NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE); -+ dma_sync_single_for_device(nss_ctx->dev, h2n_desc_index_to_dma(if_map, qid, hlos_index), -+ sizeof(*desc), DMA_TO_DEVICE); - - i++; - } -@@ -2954,7 +3012,8 @@ static inline int32_t nss_core_send_buffer_fraglist(struct nss_ctx_instance *nss - * Update bit flag for last descriptor. - */ - desc->bit_flags |= H2N_BIT_FLAG_LAST_SEGMENT; -- NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE); -+ dma_sync_single_for_device(nss_ctx->dev, h2n_desc_index_to_dma(if_map, qid, hlos_index), -+ sizeof(*desc), DMA_TO_DEVICE); - - NSS_PKT_STATS_INC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_TX_FRAGLIST]); - return i+1; -@@ -3025,8 +3084,10 @@ int32_t nss_core_send_buffer(struct nss_ctx_instance *nss_ctx, uint32_t if_num, - * We need to work out if there's sufficent space in our transmit descriptor - * ring to place all the segments of a nbuf. - */ -- NSS_CORE_DMA_CACHE_MAINT((void *)&if_map->h2n_nss_index[qid], sizeof(uint32_t), DMA_FROM_DEVICE); -+ dma_sync_single_for_device(nss_ctx->dev, h2n_nss_index_to_dma(mem_ctx->if_map_dma, qid), -+ sizeof(uint32_t), DMA_FROM_DEVICE); - NSS_CORE_DSB(); -+ - nss_index = if_map->h2n_nss_index[qid]; - h2n_desc_ring->nss_index_local = nss_index; - count = ((nss_index - hlos_index - 1) + size) & (mask); -@@ -3095,13 +3156,13 @@ int32_t nss_core_send_buffer(struct nss_ctx_instance *nss_ctx, uint32_t if_num, - count = 0; - if (likely((segments == 0) || is_bounce)) { - count = nss_core_send_buffer_simple_skb(nss_ctx, desc_if, if_num, -- nbuf, hlos_index, flags, buffer_type, mss); -+ nbuf, qid, hlos_index, flags, buffer_type, mss); - } else if (skb_has_frag_list(nbuf)) { - count = nss_core_send_buffer_fraglist(nss_ctx, desc_if, if_num, -- nbuf, hlos_index, flags, buffer_type, mss); -+ nbuf, qid, hlos_index, flags, buffer_type, mss); - } else { - count = nss_core_send_buffer_nr_frags(nss_ctx, desc_if, if_num, -- nbuf, hlos_index, flags, buffer_type, mss); -+ nbuf, qid, hlos_index, flags, buffer_type, mss); - } - - if (unlikely(count <= 0)) { -@@ -3125,7 +3186,8 @@ int32_t nss_core_send_buffer(struct nss_ctx_instance *nss_ctx, uint32_t if_num, - h2n_desc_ring->hlos_index = hlos_index; - if_map->h2n_hlos_index[qid] = hlos_index; - -- NSS_CORE_DMA_CACHE_MAINT(&if_map->h2n_hlos_index[qid], sizeof(uint32_t), DMA_TO_DEVICE); -+ dma_sync_single_for_device(nss_ctx->dev, h2n_hlos_index_to_dma(mem_ctx->if_map_dma, qid), -+ sizeof(uint32_t), DMA_TO_DEVICE); - NSS_CORE_DSB(); - - #ifdef CONFIG_DEBUG_KMEMLEAK -diff --git a/nss_core.h b/nss_core.h -index d7f62fe..7ddf6ce 100644 ---- a/nss_core.h -+++ b/nss_core.h -@@ -100,31 +100,30 @@ - #endif - - /* -- * Cache operation -+ * DMA Offset helper - */ --#define NSS_CORE_DSB() dsb(sy) --#define NSS_CORE_DMA_CACHE_MAINT(start, size, dir) nss_core_dma_cache_maint(start, size, dir) -+#define n2h_desc_index_offset(_index) sizeof(struct n2h_descriptor) * (_index) -+#define h2n_desc_index_offset(_index) sizeof(struct h2n_descriptor) * (_index) -+ -+#define n2h_desc_index_to_dma(_if_map_addr, _qid, _index) (_if_map_addr)->n2h_desc_if[(_qid)].desc_addr + n2h_desc_index_offset(_index) -+#define h2n_desc_index_to_dma(_if_map_addr, _qid, _index) (_if_map_addr)->h2n_desc_if[(_qid)].desc_addr + h2n_desc_index_offset(_index) -+ -+#define h2n_nss_index_offset offsetof(struct nss_if_mem_map, h2n_nss_index) -+#define n2h_nss_index_offset offsetof(struct nss_if_mem_map, n2h_nss_index) -+#define h2n_hlos_index_offset offsetof(struct nss_if_mem_map, h2n_hlos_index) -+#define n2h_hlos_index_offset offsetof(struct nss_if_mem_map, n2h_hlos_index) -+ -+#define h2n_nss_index_to_dma(_if_map_addr, _index) (_if_map_addr) + h2n_nss_index_offset + (sizeof(uint32_t) * (_index)) -+#define n2h_nss_index_to_dma(_if_map_addr, _index) (_if_map_addr) + n2h_nss_index_offset + (sizeof(uint32_t) * (_index)) -+#define h2n_hlos_index_to_dma(_if_map_addr, _index) (_if_map_addr) + h2n_hlos_index_offset + (sizeof(uint32_t) * (_index)) -+#define n2h_hlos_index_to_dma(_if_map_addr, _index) (_if_map_addr) + n2h_hlos_index_offset + (sizeof(uint32_t) * (_index)) - - /* -- * nss_core_dma_cache_maint() -- * Perform the appropriate cache op based on direction -+ * Cache operation - */ --static inline void nss_core_dma_cache_maint(void *start, uint32_t size, int direction) --{ -- switch (direction) { -- case DMA_FROM_DEVICE:/* invalidate only */ -- dmac_inv_range(start, start + size); -- break; -- case DMA_TO_DEVICE:/* writeback only */ -- dmac_clean_range(start, start + size); -- break; -- case DMA_BIDIRECTIONAL:/* writeback and invalidate */ -- dmac_flush_range(start, start + size); -- break; -- default: -- BUG(); -- } --} -+#define NSS_CORE_DSB() dsb(sy) -+#define NSS_CORE_DMA_CACHE_MAINT(dev, start, size, dir) BUILD_BUG_ON_MSG(1, \ -+ "NSS_CORE_DMA_CACHE_MAINT is deprecated. Fix the code to use correct dma_sync_* API") - - #define NSS_DEVICE_IF_START NSS_PHYSICAL_IF_START - -diff --git a/nss_hal/ipq806x/nss_hal_pvt.c b/nss_hal/ipq806x/nss_hal_pvt.c -index 52d63b0..5375087 100644 ---- a/nss_hal/ipq806x/nss_hal_pvt.c -+++ b/nss_hal/ipq806x/nss_hal_pvt.c -@@ -474,10 +474,9 @@ static struct nss_platform_data *__nss_hal_of_get_pdata(struct platform_device * - /* - * Clear TCM memory used by this core - */ -- for (i = 0; i < resource_size(&res_vphys) ; i += 4) { -+ for (i = 0; i < resource_size(&res_vphys) ; i += 4) - nss_write_32(npd->vmap, i, 0); -- NSS_CORE_DMA_CACHE_MAINT((npd->vmap + i), 4, DMA_TO_DEVICE); -- } -+ - NSS_CORE_DSB(); - - /* -diff --git a/nss_hal/ipq807x/nss_hal_pvt.c b/nss_hal/ipq807x/nss_hal_pvt.c -index bb8f42f..733d7f1 100644 ---- a/nss_hal/ipq807x/nss_hal_pvt.c -+++ b/nss_hal/ipq807x/nss_hal_pvt.c -@@ -256,10 +256,9 @@ static struct nss_platform_data *__nss_hal_of_get_pdata(struct platform_device * - /* - * Clear TCM memory used by this core - */ -- for (i = 0; i < resource_size(&res_vphys) ; i += 4) { -+ for (i = 0; i < resource_size(&res_vphys) ; i += 4) - nss_write_32(npd->vmap, i, 0); -- NSS_CORE_DMA_CACHE_MAINT((npd->vmap + i), 4, DMA_TO_DEVICE); -- } -+ - NSS_CORE_DSB(); - - /* -diff --git a/nss_meminfo.c b/nss_meminfo.c -index 2255eae..d804524 100644 ---- a/nss_meminfo.c -+++ b/nss_meminfo.c -@@ -414,7 +414,6 @@ static bool nss_meminfo_init_block_lists(struct nss_ctx_instance *nss_ctx) - /* - * Flush the updated meminfo request. - */ -- NSS_CORE_DMA_CACHE_MAINT(r, sizeof(struct nss_meminfo_request), DMA_TO_DEVICE); - NSS_CORE_DSB(); - - /* -@@ -538,7 +537,7 @@ static bool nss_meminfo_configure_n2h_h2n_rings(struct nss_ctx_instance *nss_ctx - * Bring a fresh copy of if_map from memory in order to read it correctly. - */ - if_map = mem_ctx->if_map; -- NSS_CORE_DMA_CACHE_MAINT((void *)if_map, sizeof(struct nss_if_mem_map), DMA_FROM_DEVICE); -+ dma_sync_single_for_device(nss_ctx->dev, mem_ctx->if_map_dma, sizeof(struct nss_if_mem_map), DMA_FROM_DEVICE); - NSS_CORE_DSB(); - - if_map->n2h_rings = NSS_N2H_RING_COUNT; -@@ -576,7 +575,7 @@ static bool nss_meminfo_configure_n2h_h2n_rings(struct nss_ctx_instance *nss_ctx - /* - * Flush the updated nss_if_mem_map. - */ -- NSS_CORE_DMA_CACHE_MAINT((void *)if_map, sizeof(struct nss_if_mem_map), DMA_TO_DEVICE); -+ dma_sync_single_for_device(nss_ctx->dev, mem_ctx->if_map_dma, sizeof(struct nss_if_mem_map), DMA_TO_DEVICE); - NSS_CORE_DSB(); - - return true; -diff --git a/nss_profiler.c b/nss_profiler.c -index 5717ac3..aadc7c9 100755 ---- a/nss_profiler.c -+++ b/nss_profiler.c -@@ -199,11 +199,12 @@ EXPORT_SYMBOL(nss_profile_dma_deregister_cb); - struct nss_profile_sdma_ctrl *nss_profile_dma_get_ctrl(struct nss_ctx_instance *nss_ctx) - { - struct nss_profile_sdma_ctrl *ctrl = nss_ctx->meminfo_ctx.sdma_ctrl; -+ int size = offsetof(struct nss_profile_sdma_ctrl, cidx); - if (!ctrl) { - return ctrl; - } - -- dmac_inv_range(ctrl, &ctrl->cidx); -+ dma_sync_single_for_device(nss_ctx->dev, (dma_addr_t) ctrl, size, DMA_FROM_DEVICE); - dsb(sy); - return ctrl; - } --- -2.34.1 - diff --git a/qca/qca-nss-drv/patches/0005-nss-drv-add-support-for-kernel-5.15.patch b/qca/qca-nss-drv/patches/0005-nss-drv-add-support-for-kernel-5.15.patch deleted file mode 100644 index 0995e2a07..000000000 --- a/qca/qca-nss-drv/patches/0005-nss-drv-add-support-for-kernel-5.15.patch +++ /dev/null @@ -1,70 +0,0 @@ -From 6e65f6daecb09463688eaea0a234018a728196b8 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Tue, 5 Apr 2022 18:10:57 +0200 -Subject: [PATCH 5/8] nss-drv: add support for kernel 5.15 - -- Fix coredump panic notifier include change. -- Fix skb ZEROCOPY flag. -- Add skb reuse support for 5.15 kernel version. - -Signed-off-by: Ansuel Smith ---- - nss_core.c | 5 +++-- - nss_coredump.c | 4 ++++ - nss_hal/nss_hal.c | 1 + - 3 files changed, 8 insertions(+), 2 deletions(-) - -diff --git a/nss_core.c b/nss_core.c -index f9e6014..8cd1d4b 100644 ---- a/nss_core.c -+++ b/nss_core.c -@@ -53,7 +53,8 @@ - (((LINUX_VERSION_CODE >= KERNEL_VERSION(3, 18, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 19, 0)))) || \ - (((LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(4, 5, 0)))) || \ - (((LINUX_VERSION_CODE >= KERNEL_VERSION(5, 4, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 5, 0)))) || \ --(((LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 11, 0)))))) -+(((LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 11, 0)))) || \ -+(((LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 16, 0)))))) - #error "Check skb recycle code in this file to match Linux version" - #endif - -@@ -2623,7 +2624,7 @@ static inline bool nss_core_skb_can_reuse(struct nss_ctx_instance *nss_ctx, - if (unlikely(irqs_disabled())) - return false; - -- if (unlikely(skb_shinfo(nbuf)->tx_flags & SKBTX_DEV_ZEROCOPY)) -+ if (unlikely(skb_shinfo(nbuf)->flags & SKBFL_ZEROCOPY_ENABLE)) - return false; - - if (unlikely(skb_is_nonlinear(nbuf))) -diff --git a/nss_coredump.c b/nss_coredump.c -index ecad659..3ecef7e 100644 ---- a/nss_coredump.c -+++ b/nss_coredump.c -@@ -23,7 +23,11 @@ - #include "nss_hal.h" - #include "nss_log.h" - #include -+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 14, 0)) - #include /* for panic_notifier_list */ -+#else -+#include -+#endif - #include /* for time */ - #include "nss_tx_rx_common.h" - -diff --git a/nss_hal/nss_hal.c b/nss_hal/nss_hal.c -index 57974c1..d8c703b 100644 ---- a/nss_hal/nss_hal.c -+++ b/nss_hal/nss_hal.c -@@ -24,6 +24,7 @@ - #include - #include - #include -+#include - - #include "nss_hal.h" - #include "nss_arch.h" --- -2.34.1 - diff --git a/qca/qca-nss-drv/patches/0005-nss-drv-use-standard-skb_skip_tc_classify-instead-of.patch b/qca/qca-nss-drv/patches/0005-nss-drv-use-standard-skb_skip_tc_classify-instead-of.patch deleted file mode 100644 index 6e8b4cdfd..000000000 --- a/qca/qca-nss-drv/patches/0005-nss-drv-use-standard-skb_skip_tc_classify-instead-of.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 4dd701916186803172a9f35e7e982a953613ad55 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Mon, 11 Apr 2022 21:32:41 +0200 -Subject: [PATCH 5/9] nss-drv: use standard skb_skip_tc_classify instead of - custom api - -Use skb_skip_tc_classify to skip classify for packet handled by nss -instead of custom api. - -Signed-off-by: Ansuel Smith ---- - nss_core.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/nss_core.c b/nss_core.c -index f9e6014..6ab8038 100644 ---- a/nss_core.c -+++ b/nss_core.c -@@ -1075,7 +1075,7 @@ static inline void nss_core_set_skb_classify(struct sk_buff *nbuf) - #if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0)) - nbuf->tc_verd = SET_TC_NCLS_NSS(nbuf->tc_verd); - #else -- skb_set_tc_classify_offload(nbuf); -+ skb_skip_tc_classify(nbuf); - #endif - #endif - } --- -2.34.1 - diff --git a/qca/qca-nss-drv/patches/0008-Makefile-modularize-driver-even-more.patch b/qca/qca-nss-drv/patches/0008-Makefile-modularize-driver-even-more.patch deleted file mode 100644 index eb7f27d06..000000000 --- a/qca/qca-nss-drv/patches/0008-Makefile-modularize-driver-even-more.patch +++ /dev/null @@ -1,172 +0,0 @@ -From 895de8e4119afe3cbad2aa81566b1ebcb2b39dcd Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Tue, 17 May 2022 20:23:19 +0200 -Subject: [PATCH] Makefile: modularize driver even more - -Permit to disable even more module. - -Signed-off-by: Ansuel Smith ---- - Makefile | 56 ++++++++++++++++++++++++++++++++--------------- - nss_hal/nss_hal.c | 6 +++++ - nss_init.c | 4 ++++ - 3 files changed, 48 insertions(+), 18 deletions(-) - -diff --git a/Makefile b/Makefile -index f5c4b90..0194dbd 100644 ---- a/Makefile -+++ b/Makefile -@@ -39,35 +39,55 @@ qca-nss-drv-objs := \ - nss_pm.o \ - nss_profiler.o \ - nss_project.o \ -- nss_pppoe.o \ -- nss_pppoe_log.o \ -- nss_pppoe_stats.o \ -- nss_pppoe_strings.o \ - nss_rps.o \ - nss_stats.o \ - nss_strings.o \ - nss_tx_msg_sync.o \ - nss_unaligned.o \ - nss_unaligned_log.o \ -- nss_unaligned_stats.o \ -- nss_virt_if.o \ -- nss_virt_if_stats.o \ -- nss_vlan.o \ -- nss_vlan_log.o \ -- nss_wifi.o \ -- nss_wifi_log.o \ -- nss_wifi_stats.o \ -- nss_wifi_vdev.o \ -- nss_wifili.o \ -- nss_wifili_log.o \ -- nss_wifili_stats.o \ -- nss_wifili_strings.o \ -- nss_wifi_mac_db.o -+ nss_unaligned_stats.o - - # Base NSS data plane/HAL support - qca-nss-drv-objs += nss_data_plane/nss_data_plane_common.o - qca-nss-drv-objs += nss_hal/nss_hal.o - -+ifneq "$(NSS_DRV_PPPOE_ENABLE)" "n" -+ccflags-y += -DNSS_DRV_PPPOE_ENABLE -+qca-nss-drv-objs += \ -+ nss_pppoe.o \ -+ nss_pppoe_log.o \ -+ nss_pppoe_stats.o \ -+ nss_pppoe_strings.o -+endif -+ -+ifneq "$(NSS_DRV_VIRT_IF_ENABLE)" "n" -+ccflags-y += -DNSS_DRV_VIRT_IF_ENABLE -+qca-nss-drv-objs += \ -+ nss_virt_if.o \ -+ nss_virt_if_stats.o -+endif -+ -+ifneq "$(NSS_DRV_VLAN_ENABLE)" "n" -+ccflags-y += -DNSS_DRV_VLAN_ENABLE -+qca-nss-drv-objs += \ -+ nss_vlan.o \ -+ nss_vlan_log.o -+endif -+ -+ifneq "$(NSS_DRV_WIFI_ENABLE)" "n" -+ccflags-y += -DNSS_DRV_WIFI_ENABLE -+qca-nss-drv-objs += \ -+ nss_wifi.o \ -+ nss_wifi_log.o \ -+ nss_wifi_stats.o \ -+ nss_wifi_vdev.o \ -+ nss_wifili.o \ -+ nss_wifili_log.o \ -+ nss_wifili_stats.o \ -+ nss_wifili_strings.o \ -+ nss_wifi_mac_db.o -+endif -+ - ifneq "$(NSS_DRV_BRIDGE_ENABLE)" "n" - ccflags-y += -DNSS_DRV_BRIDGE_ENABLE - qca-nss-drv-objs += \ -diff --git a/nss_hal/nss_hal.c b/nss_hal/nss_hal.c -index 7e9a044..c0051e4 100644 ---- a/nss_hal/nss_hal.c -+++ b/nss_hal/nss_hal.c -@@ -460,10 +460,12 @@ int nss_hal_probe(struct platform_device *nss_dev) - } - #endif - -+#ifdef NSS_DRV_PPPOE_ENABLE - if (npd->pppoe_enabled == NSS_FEATURE_ENABLED) { - nss_top->pppoe_handler_id = nss_dev->id; - nss_pppoe_register_handler(); - } -+#endif - - #ifdef NSS_DRV_PPE_ENABLE - if (npd->ppe_enabled == NSS_FEATURE_ENABLED) { -@@ -558,6 +560,7 @@ int nss_hal_probe(struct platform_device *nss_dev) - } - #endif - -+#ifdef NSS_DRV_WIFI_ENABLE - if (npd->wifioffload_enabled == NSS_FEATURE_ENABLED) { - nss_top->wifi_handler_id = nss_dev->id; - nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_VAP] = nss_dev->id; -@@ -585,6 +588,7 @@ int nss_hal_probe(struct platform_device *nss_dev) - */ - nss_wifili_thread_scheme_db_init(nss_dev->id); - } -+#endif - - #ifdef NSS_DRV_OAM_ENABLE - if (npd->oam_enabled == NSS_FEATURE_ENABLED) { -@@ -601,11 +605,13 @@ int nss_hal_probe(struct platform_device *nss_dev) - } - #endif - -+#ifdef NSS_DRV_VLAN_ENABLE - if (npd->vlan_enabled == NSS_FEATURE_ENABLED) { - nss_top->vlan_handler_id = nss_dev->id; - nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_VLAN] = nss_dev->id; - nss_vlan_register_handler(); - } -+#endif - - #ifdef NSS_DRV_QVPN_ENABLE - #if defined(NSS_HAL_IPQ807x_SUPPORT) || defined(NSS_HAL_IPQ60XX_SUPPORT) -diff --git a/nss_init.c b/nss_init.c -index ebd2a12..40e9351 100644 ---- a/nss_init.c -+++ b/nss_init.c -@@ -775,10 +775,12 @@ static int __init nss_init(void) - */ - nss_project_register_sysctl(); - -+#ifdef NSS_DRV_PPPOE_ENABLE - /* - * Registering sysctl for pppoe specific config. - */ - nss_pppoe_register_sysctl(); -+#endif - - /* - * Setup Runtime Sample values -@@ -913,10 +915,12 @@ static void __exit nss_cleanup(void) - nss_c2c_tx_unregister_sysctl(); - #endif - -+#ifdef NSS_DRV_PPPOE_ENABLE - /* - * Unregister pppoe specific sysctl - */ - nss_pppoe_unregister_sysctl(); -+#endif - - /* - * Unregister ipv4/6 specific sysctl and free allocated to connection tables --- -2.34.1 - diff --git a/qca/qca-nss-ecm/Makefile b/qca/qca-nss-ecm/Makefile deleted file mode 100644 index ceedc1988..000000000 --- a/qca/qca-nss-ecm/Makefile +++ /dev/null @@ -1,97 +0,0 @@ -include $(TOPDIR)/rules.mk - -PKG_NAME:=qca-nss-ecm -PKG_RELEASE:=$(AUTORELEASE) - -PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/qca-nss-ecm.git -PKG_SOURCE_PROTO:=git -PKG_SOURCE_DATE:=2021-06-15 -PKG_SOURCE_VERSION:=34267065855d32f33264dc3054efb0e8103d627b -PKG_MIRROR_HASH:=0917659d69c5f3e6067d6671b9393b4b2d6b6cd5a7bacf5e7d6cf842dc906eca - -PKG_BUILD_PARALLEL:=1 - -include $(INCLUDE_DIR)/kernel.mk -include $(INCLUDE_DIR)/package.mk - -define KernelPackage/qca-nss-ecm - SECTION:=kernel - CATEGORY:=Kernel modules - SUBMENU:=Network Support - DEPENDS:=@LINUX_5_10 @(TARGET_ipq807x||TARGET_ipq60xx) \ - +kmod-qca-nss-drv \ - +iptables-mod-extra \ - +kmod-ipt-conntrack \ - +kmod-ipt-physdev \ - +iptables-mod-physdev \ - +kmod-ppp \ - +kmod-pppoe - TITLE:=QCA NSS Enhanced Connection Manager (ECM) - FILES:=$(PKG_BUILD_DIR)/*.ko - KCONFIG:=CONFIG_BRIDGE_NETFILTER=y \ - CONFIG_NF_CONNTRACK_EVENTS=y \ - CONFIG_NF_CONNTRACK_CHAIN_EVENTS=n \ - CONFIG_NF_CONNTRACK_DSCPREMARK_EXT=n -endef - -define KernelPackage/qca-nss-ecm/Description -This package contains the QCA NSS Enhanced Connection Manager -endef - -define KernelPackage/qca-nss-ecm/install - $(INSTALL_DIR) $(1)/etc/firewall.d $(1)/etc/init.d $(1)/usr/bin $(1)/lib/netifd/offload $(1)/etc/config $(1)/etc/uci-defaults $(1)/etc/sysctl.d - $(INSTALL_DATA) ./files/qca-nss-ecm.firewall $(1)/etc/firewall.d/qca-nss-ecm - $(INSTALL_BIN) ./files/qca-nss-ecm.init $(1)/etc/init.d/qca-nss-ecm - $(INSTALL_BIN) ./files/ecm_dump.sh $(1)/usr/bin/ - $(INSTALL_BIN) ./files/on-demand-down $(1)/lib/netifd/offload/on-demand-down - $(INSTALL_DATA) ./files/qca-nss-ecm.uci $(1)/etc/config/ecm - $(INSTALL_DATA) ./files/qca-nss-ecm.defaults $(1)/etc/uci-defaults/99-qca-nss-ecm - $(INSTALL_BIN) ./files/qca-nss-ecm.sysctl $(1)/etc/sysctl.d/qca-nss-ecm.conf - echo 'net.netfilter.nf_conntrack_max=8192' >> $(1)/etc/sysctl.d/qca-nss-ecm.conf -endef - -EXTRA_CFLAGS+=-I$(STAGING_DIR)/usr/include/qca-nss-drv - -ifneq (, $(findstring $(CONFIG_TARGET_BOARD), "ipq807x" "ipq60xx")) -ECM_MAKE_OPTS+= ECM_FRONT_END_NSS_ENABLE=y \ - ECM_CLASSIFIER_HYFI_ENABLE=n \ - ECM_MULTICAST_ENABLE=n \ - ECM_INTERFACE_IPSEC_ENABLE=n \ - ECM_INTERFACE_PPTP_ENABLE=n \ - ECM_INTERFACE_L2TPV2_ENABLE=n \ - ECM_INTERFACE_GRE_TAP_ENABLE=n \ - ECM_INTERFACE_GRE_TUN_ENABLE=n \ - ECM_INTERFACE_SIT_ENABLE=n \ - ECM_INTERFACE_TUNIPIP6_ENABLE=n \ - ECM_INTERFACE_RAWIP_ENABLE=n \ - ECM_INTERFACE_VLAN_ENABLE=n \ - ECM_CLASSIFIER_MARK_ENABLE=n \ - ECM_CLASSIFIER_DSCP_ENABLE=n \ - ECM_CLASSIFIER_PCC_ENABLE=n \ - ECM_BAND_STEERING_ENABLE=n \ - ECM_INTERFACE_PPPOE_ENABLE=y -endif - -ifeq ($(CONFIG_TARGET_BOARD), "ipq807x") - SOC="ipq807x_64" -else ifeq ($(CONFIG_TARGET_BOARD), "ipq60xx") - SOC="ipq60xx_64" -endif - -define Build/InstallDev - mkdir -p $(1)/usr/include/qca-nss-ecm - $(CP) $(PKG_BUILD_DIR)/exports/* $(1)/usr/include/qca-nss-ecm -endef - -define Build/Compile - +$(MAKE) -C "$(LINUX_DIR)" $(strip $(ECM_MAKE_OPTS)) \ - CROSS_COMPILE="$(TARGET_CROSS)" \ - ARCH="$(LINUX_KARCH)" \ - M="$(PKG_BUILD_DIR)" \ - EXTRA_CFLAGS="$(EXTRA_CFLAGS)" SoC=$(SOC) \ - $(KERNEL_MAKE_FLAGS) \ - $(PKG_JOBS) \ - modules -endef - -$(eval $(call KernelPackage,qca-nss-ecm)) diff --git a/qca/qca-nss-ecm/files/ecm_dump.sh b/qca/qca-nss-ecm/files/ecm_dump.sh deleted file mode 100644 index dbf7de753..000000000 --- a/qca/qca-nss-ecm/files/ecm_dump.sh +++ /dev/null @@ -1,95 +0,0 @@ -#!/bin/sh -# -# Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. -# -# Permission to use, copy, modify, and/or distribute this software for any -# purpose with or without fee is hereby granted, provided that the above -# copyright notice and this permission notice appear in all copies. -# -# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -# - -ECM_MODULE=${1:-ecm_state} -MOUNT_ROOT=/dev/ecm - -# -# usage: ecm_dump.sh [module=ecm_db] -# -# with no parameters, ecm_dump.sh will attempt to mount the -# ecm_db state file and cat its contents. -# -# example with a parameter: ecm_dump.sh ecm_classifier_default -# -# this will cause ecm_dump to attempt to find and mount the state -# file for the ecm_classifier_default module, and if successful -# cat the contents. -# - -# this is one of the state files, which happens to be the -# last module started in ecm -ECM_STATE=/sys/kernel/debug/ecm/ecm_state/state_dev_major - -# tests to see if ECM is up and ready to receive commands. -# returns 0 if ECM is fully up and ready, else 1 -ecm_is_ready() { - if [ ! -e "${ECM_STATE}" ] - then - return 1 - fi - return 0 -} - -# -# module_state_mount(module_name) -# Mounts the state file of the module, if supported -# -module_state_mount() { - local module_name=$1 - local mount_dir=$2 - local state_file="/sys/kernel/debug/ecm/${module_name}/state_dev_major" - - if [ -e "${mount_dir}/${module_name}" ] - then - # already mounted - return 0 - fi - - #echo "Mount state file for $module_name ..." - if [ ! -e "$state_file" ] - then - #echo "... $module_name does not support state" - return 1 - fi - - local major="`cat $state_file`" - #echo "... Mounting state $state_file with major: $major" - mknod "${mount_dir}/${module_name}" c $major 0 -} - -# -# main -# -ecm_is_ready || { - #echo "ECM is not running" - exit 1 -} - -# all state files are mounted under MOUNT_ROOT, so make sure it exists -mkdir -p ${MOUNT_ROOT} - -# -# attempt to mount state files for the requested module and cat it -# if the mount succeeded -# -module_state_mount ${ECM_MODULE} ${MOUNT_ROOT} && { - cat ${MOUNT_ROOT}/${ECM_MODULE} - exit 0 -} - -exit 2 diff --git a/qca/qca-nss-ecm/files/on-demand-down b/qca/qca-nss-ecm/files/on-demand-down deleted file mode 100644 index 02d708e03..000000000 --- a/qca/qca-nss-ecm/files/on-demand-down +++ /dev/null @@ -1,6 +0,0 @@ -#!/bin/sh -# Copyright (c) 2016 The Linux Foundation. All rights reserved. - -[ -e "/sys/kernel/debug/ecm/ecm_db/defunct_all" ] && { - echo 1 > /sys/kernel/debug/ecm/ecm_db/defunct_all -} diff --git a/qca/qca-nss-ecm/files/qca-nss-ecm.defaults b/qca/qca-nss-ecm/files/qca-nss-ecm.defaults deleted file mode 100644 index 308e265c9..000000000 --- a/qca/qca-nss-ecm/files/qca-nss-ecm.defaults +++ /dev/null @@ -1,28 +0,0 @@ -#!/bin/sh -# -# Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. -# -# Permission to use, copy, modify, and/or distribute this software for any -# purpose with or without fee is hereby granted, provided that the above -# copyright notice and this permission notice appear in all copies. -# -# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -# - -uci -q batch << EOF - delete firewall.qcanssecm - set firewall.qcanssecm=include - set firewall.qcanssecm.type=script - set firewall.qcanssecm.path=/etc/firewall.d/qca-nss-ecm - set firewall.qcanssecm.family=any - set firewall.qcanssecm.reload=1 - commit firewall -EOF - -exit 0 diff --git a/qca/qca-nss-ecm/files/qca-nss-ecm.firewall b/qca/qca-nss-ecm/files/qca-nss-ecm.firewall deleted file mode 100644 index 24c64def2..000000000 --- a/qca/qca-nss-ecm/files/qca-nss-ecm.firewall +++ /dev/null @@ -1,18 +0,0 @@ -#!/bin/sh -# -# Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. -# -# Permission to use, copy, modify, and/or distribute this software for any -# purpose with or without fee is hereby granted, provided that the above -# copyright notice and this permission notice appear in all copies. -# -# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -# - -iptables -A FORWARD -m physdev --physdev-is-bridged -j ACCEPT diff --git a/qca/qca-nss-ecm/files/qca-nss-ecm.init b/qca/qca-nss-ecm/files/qca-nss-ecm.init deleted file mode 100644 index e64f077bb..000000000 --- a/qca/qca-nss-ecm/files/qca-nss-ecm.init +++ /dev/null @@ -1,142 +0,0 @@ -#!/bin/sh /etc/rc.common -# -# Copyright (c) 2014, 2019-2020 The Linux Foundation. All rights reserved. -# -# Permission to use, copy, modify, and/or distribute this software for any -# purpose with or without fee is hereby granted, provided that the above -# copyright notice and this permission notice appear in all copies. -# -# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - -# The shebang above has an extra space intentially to avoid having -# openwrt build scripts automatically enable this package starting -# at boot. - -START=19 - -get_front_end_mode() { - config_load "ecm" - config_get front_end global acceleration_engine "auto" - - case $front_end in - auto) - echo '0' - ;; - nss) - echo '1' - ;; - sfe) - echo '2' - ;; - *) - echo 'uci_option_acceleration_engine is invalid' - esac -} - -support_bridge() { - #NSS support bridge acceleration - [ -d /sys/kernel/debug/ecm/ecm_nss_ipv4 ] && return 0 - #SFE doesn't support bridge acceleration - [ -d /sys/kernel/debug/ecm/ecm_sfe_ipv4 ] && return 1 -} - -load_sfe() { - local kernel_version=$(uname -r) - - [ -e "/lib/modules/$kernel_version/shortcut-fe.ko" ] && { - [ -d /sys/module/shortcut_fe ] || insmod shortcut-fe - } - - [ -e "/lib/modules/$kernel_version/shortcut-fe-ipv6.ko" ] && { - [ -d /sys/module/shortcut_fe_ipv6 ] || insmod shortcut-fe-ipv6 - } - - [ -e "/lib/modules/$kernel_version/shortcut-fe-drv.ko" ] && { - [ -d /sys/module/shortcut_fe_drv ] || insmod shortcut-fe-drv - } -} - -load_ecm() { - [ -d /sys/module/ecm ] || { - [ ! -e /proc/device-tree/MP_256 ] && load_sfe - insmod ecm front_end_selection=$(get_front_end_mode) - } - - support_bridge && { - sysctl -w net.bridge.bridge-nf-call-ip6tables=1 - sysctl -w net.bridge.bridge-nf-call-iptables=1 - } -} - -unload_ecm() { - sysctl -w net.bridge.bridge-nf-call-ip6tables=0 - sysctl -w net.bridge.bridge-nf-call-iptables=0 - - if [ -d /sys/module/ecm ]; then - # - # Stop ECM frontends - # - echo 1 > /sys/kernel/debug/ecm/front_end_ipv4_stop - echo 1 > /sys/kernel/debug/ecm/front_end_ipv6_stop - - # - # Defunct the connections - # - echo 1 > /sys/kernel/debug/ecm/ecm_db/defunct_all - sleep 5; - - rmmod ecm - sleep 1 - fi -} - -start() { - # If SFE CM is loaded, return. - if [ -d /sys/module/shortcut_fe_cm ]; then - echo "shortcut_fe CM is loaded, unload it first" - echo "cmd: /etc/init.d/shortcut_fe stop" - return - fi - - load_ecm - - # If the acceleration engine is NSS, enable wifi redirect. - [ -d /sys/kernel/debug/ecm/ecm_nss_ipv4 ] && sysctl -w dev.nss.general.redirect=1 - - support_bridge && { - if ([ -z "$(grep "net.bridge.bridge-nf-call-ip6tables=1" /etc/sysctl.d/qca-nss-ecm.conf)" ] && [ -z "$(grep "net.bridge.bridge-nf-call-iptables=1" /etc/sysctl.d/qca-nss-ecm.conf)" ]); then - echo 'net.bridge.bridge-nf-call-ip6tables=1' >> /etc/sysctl.d/qca-nss-ecm.conf - echo 'net.bridge.bridge-nf-call-iptables=1' >> /etc/sysctl.d/qca-nss-ecm.conf - fi - } - - if [ -d /sys/module/qca_ovsmgr ]; then - insmod ecm_ovs - fi - -} - -stop() { - # If ECM is already not loaded, just return. - if [ ! -d /sys/module/ecm ]; then - return - fi - - # If the acceleration engine is NSS, disable wifi redirect. - [ -d /sys/kernel/debug/ecm/ecm_nss_ipv4 ] && sysctl -w dev.nss.general.redirect=0 - - sed '/net.bridge.bridge-nf-call-ip6tables=1/d' -i /etc/sysctl.d/qca-nss-ecm.conf - sed '/net.bridge.bridge-nf-call-iptables=1/d' -i /etc/sysctl.d/qca-nss-ecm.conf - - if [ -d /sys/module/ecm_ovs ]; then - rmmod ecm_ovs - fi - - unload_ecm -} diff --git a/qca/qca-nss-ecm/files/qca-nss-ecm.sysctl b/qca/qca-nss-ecm/files/qca-nss-ecm.sysctl deleted file mode 100644 index 1a3d76b18..000000000 --- a/qca/qca-nss-ecm/files/qca-nss-ecm.sysctl +++ /dev/null @@ -1,2 +0,0 @@ -# nf_conntrack_tcp_no_window_check is 0 by default, set it to 1 -net.netfilter.nf_conntrack_tcp_no_window_check=1 diff --git a/qca/qca-nss-ecm/files/qca-nss-ecm.uci b/qca/qca-nss-ecm/files/qca-nss-ecm.uci deleted file mode 100644 index 4f2de6877..000000000 --- a/qca/qca-nss-ecm/files/qca-nss-ecm.uci +++ /dev/null @@ -1,2 +0,0 @@ -config ecm 'global' - option acceleration_engine 'auto' diff --git a/qca/qca-nss-ecm/patches/001-treewide-componentize-the-module-even-more.patch b/qca/qca-nss-ecm/patches/001-treewide-componentize-the-module-even-more.patch deleted file mode 100644 index 4e7932c9d..000000000 --- a/qca/qca-nss-ecm/patches/001-treewide-componentize-the-module-even-more.patch +++ /dev/null @@ -1,335 +0,0 @@ -From 73345c87b28a473b35b57e673f8de963c3d73da1 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Wed, 19 May 2021 02:38:53 +0200 -Subject: [PATCH] treewide: componentize the module even more - -Signed-off-by: Ansuel Smith ---- - Makefile | 56 +++++++++++++++++++++++++------- - ecm_db/ecm_db_connection.c | 8 +++++ - ecm_db/ecm_db_node.c | 4 +++ - ecm_interface.c | 8 +++++ - frontends/ecm_front_end_common.c | 7 ++++ - 5 files changed, 72 insertions(+), 11 deletions(-) - ---- a/Makefile -+++ b/Makefile -@@ -82,10 +82,18 @@ ccflags-$(ECM_INTERFACE_BOND_ENABLE) += - # Define ECM_INTERFACE_PPPOE_ENABLE=y in order - # to enable support for PPPoE acceleration. - # ############################################################################# --ECM_INTERFACE_PPPOE_ENABLE=y -+ifndef $(ECM_INTERFACE_PPPOE_ENABLE) -+ ECM_INTERFACE_PPPOE_ENABLE=y -+endif - ccflags-$(ECM_INTERFACE_PPPOE_ENABLE) += -DECM_INTERFACE_PPPOE_ENABLE - - # ############################################################################# -+# Define ECM_INTERFACE_L2TPV2_PPTP_ENABLE=y in order -+# to enable support for l2tpv2 or PPTP detection. -+# ############################################################################# -+ccflags-$(ECM_INTERFACE_L2TPV2_PPTP_ENABLE) += -DECM_INTERFACE_L2TPV2_PPTP_ENABLE -+ -+# ############################################################################# - # Define ECM_INTERFACE_L2TPV2_ENABLE=y in order - # to enable support for l2tpv2 acceleration. - # ############################################################################# -@@ -118,6 +126,12 @@ ccflags-$(ECM_INTERFACE_PPP_ENABLE) += - - ccflags-$(ECM_INTERFACE_MAP_T_ENABLE) += -DECM_INTERFACE_MAP_T_ENABLE - - # ############################################################################# -+# Define ECM_INTERFACE_GRE_ENABLE=y in order -+# to enable support for GRE detection. -+# ############################################################################# -+ccflags-$(ECM_INTERFACE_GRE_ENABLE) += -DECM_INTERFACE_GRE_ENABLE -+ -+# ############################################################################# - # Define ECM_INTERFACE_GRE_TAP_ENABLE=y in order - # to enable support for GRE TAP interface. - # ############################################################################# -@@ -186,7 +200,9 @@ ccflags-$(ECM_INTERFACE_OVS_BRIDGE_ENABL - # ############################################################################# - # Define ECM_INTERFACE_VLAN_ENABLE=y in order to enable support for VLAN - # ############################################################################# --ECM_INTERFACE_VLAN_ENABLE=y -+ifndef $(ECM_INTERFACE_VLAN_ENABLE) -+ ECM_INTERFACE_VLAN_ENABLE=y -+endif - ccflags-$(ECM_INTERFACE_VLAN_ENABLE) += -DECM_INTERFACE_VLAN_ENABLE - - # ############################################################################# -@@ -228,7 +244,9 @@ ccflags-$(ECM_CLASSIFIER_OVS_ENABLE) += - # ############################################################################# - # Define ECM_CLASSIFIER_MARK_ENABLE=y in order to enable mark classifier. - # ############################################################################# --ECM_CLASSIFIER_MARK_ENABLE=y -+ifndef $(ECM_CLASSIFIER_MARK_ENABLE) -+ ECM_CLASSIFIER_MARK_ENABLE=y -+endif - ecm-$(ECM_CLASSIFIER_MARK_ENABLE) += ecm_classifier_mark.o - ccflags-$(ECM_CLASSIFIER_MARK_ENABLE) += -DECM_CLASSIFIER_MARK_ENABLE - -@@ -247,7 +265,9 @@ ccflags-$(ECM_CLASSIFIER_NL_ENABLE) += - - # ############################################################################# - # Define ECM_CLASSIFIER_DSCP_ENABLE=y in order to enable DSCP classifier. - # ############################################################################# --ECM_CLASSIFIER_DSCP_ENABLE=y -+ifndef $(ECM_CLASSIFIER_DSCP_ENABLE) -+ ECM_CLASSIFIER_DSCP_ENABLE=y -+endif - ecm-$(ECM_CLASSIFIER_DSCP_ENABLE) += ecm_classifier_dscp.o - ccflags-$(ECM_CLASSIFIER_DSCP_ENABLE) += -DECM_CLASSIFIER_DSCP_ENABLE - ccflags-$(ECM_CLASSIFIER_DSCP_IGS) += -DECM_CLASSIFIER_DSCP_IGS -@@ -274,7 +294,9 @@ endif - # the Parental Controls subsystem classifier in ECM. Currently disabled until - # customers require it / if they need to integrate their Parental Controls with it. - # ############################################################################# --ECM_CLASSIFIER_PCC_ENABLE=y -+ifndef $(ECM_CLASSIFIER_PCC_ENABLE) -+ ECM_CLASSIFIER_PCC_ENABLE=y -+endif - ecm-$(ECM_CLASSIFIER_PCC_ENABLE) += ecm_classifier_pcc.o - ccflags-$(ECM_CLASSIFIER_PCC_ENABLE) += -DECM_CLASSIFIER_PCC_ENABLE - -@@ -301,28 +323,36 @@ ccflags-$(ECM_NON_PORTED_SUPPORT_ENABLE) - # ############################################################################# - # Define ECM_STATE_OUTPUT_ENABLE=y to support XML state output - # ############################################################################# --ECM_STATE_OUTPUT_ENABLE=y -+ifndef $(ECM_STATE_OUTPUT_ENABLE) -+ ECM_STATE_OUTPUT_ENABLE=y -+endif - ecm-$(ECM_STATE_OUTPUT_ENABLE) += ecm_state.o - ccflags-$(ECM_STATE_OUTPUT_ENABLE) += -DECM_STATE_OUTPUT_ENABLE - - # ############################################################################# - # Define ECM_DB_ADVANCED_STATS_ENABLE to support XML state output - # ############################################################################# --ECM_DB_ADVANCED_STATS_ENABLE=y -+ifndef $(ECM_DB_ADVANCED_STATS_ENABLE) -+ ECM_DB_ADVANCED_STATS_ENABLE=y -+endif - ccflags-$(ECM_DB_ADVANCED_STATS_ENABLE) += -DECM_DB_ADVANCED_STATS_ENABLE - - # ############################################################################# - # Define ECM_DB_CONNECTION_CROSS_REFERENCING_ENABLE=y in order to enable - # the database to track relationships between objects. - # ############################################################################# --ECM_DB_CONNECTION_CROSS_REFERENCING_ENABLE=y -+ifndef $(ECM_DB_CONNECTION_CROSS_REFERENCING_ENABLE) -+ ECM_DB_CONNECTION_CROSS_REFERENCING_ENABLE=y -+endif - ccflags-$(ECM_DB_CONNECTION_CROSS_REFERENCING_ENABLE) += -DECM_DB_XREF_ENABLE - - # ############################################################################# - # Define ECM_TRACKER_DPI_SUPPORT_ENABLE=y in order to enable support for - # deep packet inspection and tracking of data with the trackers. - # ############################################################################# --ECM_TRACKER_DPI_SUPPORT_ENABLE=y -+ifndef $(ECM_TRACKER_DPI_SUPPORT_ENABLE) -+ ECM_TRACKER_DPI_SUPPORT_ENABLE=y -+endif - ccflags-$(ECM_TRACKER_DPI_SUPPORT_ENABLE) += -DECM_TRACKER_DPI_SUPPORT_ENABLE - - # ############################################################################# -@@ -330,14 +360,18 @@ ccflags-$(ECM_TRACKER_DPI_SUPPORT_ENABLE - # support for the database keeping lists of connections that are assigned - # on a per TYPE of classifier basis. - # ############################################################################# --ECM_DB_CLASSIFIER_TYPE_ASSIGNMENTS_TRACK_ENABLE=y -+ifndef $(ECM_DB_CLASSIFIER_TYPE_ASSIGNMENTS_TRACK_ENABLE) -+ ECM_DB_CLASSIFIER_TYPE_ASSIGNMENTS_TRACK_ENABLE=y -+endif - ccflags-$(ECM_DB_CLASSIFIER_TYPE_ASSIGNMENTS_TRACK_ENABLE) += -DECM_DB_CTA_TRACK_ENABLE - - # ############################################################################# - # Define ECM_BAND_STEERING_ENABLE=y in order to enable - # band steering feature. - # ############################################################################# --ECM_BAND_STEERING_ENABLE=y -+ifndef $(ECM_BAND_STEERING_ENABLE) -+ ECM_BAND_STEERING_ENABLE=y -+endif - ccflags-$(ECM_BAND_STEERING_ENABLE) += -DECM_BAND_STEERING_ENABLE - - # ############################################################################# ---- a/ecm_db/ecm_db_connection.c -+++ b/ecm_db/ecm_db_connection.c -@@ -430,7 +430,9 @@ EXPORT_SYMBOL(ecm_db_connection_make_def - */ - void ecm_db_connection_data_totals_update(struct ecm_db_connection_instance *ci, bool is_from, uint64_t size, uint64_t packets) - { -+#ifdef ECM_DB_ADVANCED_STATS_ENABLE - int32_t i; -+#endif - - DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed\n", ci); - -@@ -529,7 +531,9 @@ EXPORT_SYMBOL(ecm_db_connection_data_tot - */ - void ecm_db_connection_data_totals_update_dropped(struct ecm_db_connection_instance *ci, bool is_from, uint64_t size, uint64_t packets) - { -+#ifdef ECM_DB_ADVANCED_STATS_ENABLE - int32_t i; -+#endif - - DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed\n", ci); - -@@ -1508,6 +1512,7 @@ void ecm_db_connection_defunct_all(void) - } - EXPORT_SYMBOL(ecm_db_connection_defunct_all); - -+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE - /* - * ecm_db_connection_defunct_by_classifier() - * Make defunct based on masked fields -@@ -1667,6 +1672,7 @@ next_ci: - ECM_IP_ADDR_TO_OCTAL(dest_addr_mask), dest_port_mask, proto_mask, cnt); - } - } -+#endif - - /* - * ecm_db_connection_defunct_by_port() -@@ -1956,6 +1962,7 @@ struct ecm_db_node_instance *ecm_db_conn - } - EXPORT_SYMBOL(ecm_db_connection_node_get_and_ref); - -+#ifdef ECM_DB_XREF_ENABLE - /* - * ecm_db_connection_mapping_get_and_ref_next() - * Return reference to next connection in the mapping chain in the specified direction. -@@ -1997,6 +2004,7 @@ struct ecm_db_connection_instance *ecm_d - return nci; - } - EXPORT_SYMBOL(ecm_db_connection_iface_get_and_ref_next); -+#endif - - /* - * ecm_db_connection_mapping_get_and_ref() ---- a/ecm_db/ecm_db_node.c -+++ b/ecm_db/ecm_db_node.c -@@ -224,9 +224,11 @@ EXPORT_SYMBOL(ecm_db_node_get_and_ref_ne - */ - int ecm_db_node_deref(struct ecm_db_node_instance *ni) - { -+#ifdef ECM_DB_XREF_ENABLE - #if (DEBUG_LEVEL >= 1) - int dir; - #endif -+#endif - DEBUG_CHECK_MAGIC(ni, ECM_DB_NODE_INSTANCE_MAGIC, "%px: magic failed\n", ni); - - spin_lock_bh(&ecm_db_lock); -@@ -486,9 +488,11 @@ EXPORT_SYMBOL(ecm_db_node_iface_get_and_ - void ecm_db_node_add(struct ecm_db_node_instance *ni, struct ecm_db_iface_instance *ii, uint8_t *address, - ecm_db_node_final_callback_t final, void *arg) - { -+#ifdef ECM_DB_XREF_ENABLE - #if (DEBUG_LEVEL >= 1) - int dir; - #endif -+#endif - ecm_db_node_hash_t hash_index; - struct ecm_db_listener_instance *li; - ---- a/ecm_interface.c -+++ b/ecm_interface.c -@@ -1343,6 +1343,7 @@ struct neighbour *ecm_interface_ipv6_nei - */ - bool ecm_interface_is_pptp(struct sk_buff *skb, const struct net_device *out) - { -+#ifdef ECM_INTERFACE_PPTP_ENABLE - struct net_device *in; - - /* -@@ -1367,6 +1368,7 @@ bool ecm_interface_is_pptp(struct sk_buf - } - - dev_put(in); -+#endif - return false; - } - -@@ -1379,6 +1381,7 @@ bool ecm_interface_is_pptp(struct sk_buf - */ - bool ecm_interface_is_l2tp_packet_by_version(struct sk_buff *skb, const struct net_device *out, int ver) - { -+#ifdef ECM_INTERFACE_L2TPV2_PPTP_ENABLE - uint32_t flag = 0; - struct net_device *in; - -@@ -1411,6 +1414,7 @@ bool ecm_interface_is_l2tp_packet_by_ver - } - - dev_put(in); -+#endif - return false; - } - -@@ -1423,6 +1427,7 @@ bool ecm_interface_is_l2tp_packet_by_ver - */ - bool ecm_interface_is_l2tp_pptp(struct sk_buff *skb, const struct net_device *out) - { -+#ifdef ECM_INTERFACE_L2TPV2_PPTP_ENABLE - struct net_device *in; - - /* -@@ -1445,6 +1450,7 @@ bool ecm_interface_is_l2tp_pptp(struct s - } - - dev_put(in); -+#endif - return false; - } - -@@ -6630,6 +6636,7 @@ static void ecm_interface_regenerate_con - return; - } - -+#ifdef ECM_DB_XREF_ENABLE - for (dir = 0; dir < ECM_DB_OBJ_DIR_MAX; dir++) { - /* - * Re-generate all connections associated with this interface -@@ -6645,6 +6652,7 @@ static void ecm_interface_regenerate_con - ci[dir] = cin; - } - } -+#endif - - #ifdef ECM_MULTICAST_ENABLE - /* ---- a/frontends/ecm_front_end_common.c -+++ b/frontends/ecm_front_end_common.c -@@ -106,6 +106,7 @@ bool ecm_front_end_gre_proto_is_accel_al - struct nf_conntrack_tuple *tuple, - int ip_version) - { -+#ifdef ECM_INTERFACE_GRE_ENABLE - struct net_device *dev; - struct gre_base_hdr *greh; - -@@ -117,10 +118,12 @@ bool ecm_front_end_gre_proto_is_accel_al - /* - * Case 1: PPTP locally terminated - */ -+#ifdef ECM_INTERFACE_PPTP_ENABLE - if (ecm_interface_is_pptp(skb, outdev)) { - DEBUG_TRACE("%px: PPTP GRE locally terminated - allow acceleration\n", skb); - return true; - } -+#endif - - /* - * Case 2: PPTP pass through -@@ -223,6 +226,10 @@ bool ecm_front_end_gre_proto_is_accel_al - */ - DEBUG_TRACE("%px: GRE IPv%d pass through - allow acceleration\n", skb, ip_version); - return true; -+#else -+ DEBUG_TRACE("%px: GRE%d feature is disabled - do not allow acceleration\n", skb, ip_version); -+ return false; -+#endif - } - - #ifdef ECM_CLASSIFIER_DSCP_ENABLE diff --git a/qca/qca-nss-ecm/patches/100-kernel-5.10-support.patch b/qca/qca-nss-ecm/patches/100-kernel-5.10-support.patch deleted file mode 100644 index 3729dd3b9..000000000 --- a/qca/qca-nss-ecm/patches/100-kernel-5.10-support.patch +++ /dev/null @@ -1,831 +0,0 @@ -From e8b642c23af9146c973e828a7f4e0fb56cfc8d0b Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Sat, 15 May 2021 03:51:14 +0200 -Subject: [PATCH] add support for kernel 5.10 - -Signed-off-by: Ansuel Smith ---- - ecm_classifier_default.c | 24 +++--------- - ecm_classifier_dscp.c | 8 +--- - ecm_classifier_emesh.c | 16 ++------ - ecm_classifier_hyfi.c | 7 +--- - ecm_classifier_mark.c | 8 +--- - ecm_classifier_ovs.c | 8 +--- - ecm_classifier_pcc.c | 8 +--- - ecm_conntrack_notifier.c | 8 +--- - ecm_db/ecm_db_connection.c | 7 +--- - ecm_db/ecm_db_host.c | 7 +--- - ecm_db/ecm_db_iface.c | 7 +--- - ecm_db/ecm_db_mapping.c | 7 +--- - ecm_db/ecm_db_node.c | 7 +--- - ecm_interface.c | 4 +- - ecm_state.c | 14 ++----- - frontends/ecm_front_end_common.c | 4 +- - frontends/ecm_front_end_ipv4.c | 7 +--- - frontends/ecm_front_end_ipv6.c | 7 +--- - frontends/nss/ecm_nss_bond_notifier.c | 8 +--- - frontends/nss/ecm_nss_ipv4.c | 49 +++++++------------------ - frontends/nss/ecm_nss_ipv6.c | 49 +++++++------------------ - frontends/nss/ecm_nss_multicast_ipv4.c | 7 +--- - frontends/nss/ecm_nss_multicast_ipv6.c | 7 +--- - frontends/nss/ecm_nss_non_ported_ipv4.c | 7 +--- - frontends/nss/ecm_nss_non_ported_ipv6.c | 7 +--- - frontends/nss/ecm_nss_ported_ipv4.c | 8 +--- - frontends/nss/ecm_nss_ported_ipv6.c | 8 +--- - frontends/sfe/ecm_sfe_ipv4.c | 49 +++++++------------------ - frontends/sfe/ecm_sfe_ipv6.c | 49 +++++++------------------ - frontends/sfe/ecm_sfe_non_ported_ipv4.c | 7 +--- - frontends/sfe/ecm_sfe_non_ported_ipv6.c | 7 +--- - frontends/sfe/ecm_sfe_ported_ipv4.c | 8 +--- - frontends/sfe/ecm_sfe_ported_ipv6.c | 8 +--- - 33 files changed, 122 insertions(+), 314 deletions(-) - ---- a/ecm_classifier_default.c -+++ b/ecm_classifier_default.c -@@ -776,26 +776,14 @@ int ecm_classifier_default_init(struct d - return -1; - } - -- if (!debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_default_dentry, -- (u32 *)&ecm_classifier_default_enabled)) { -- DEBUG_ERROR("Failed to create ecm deafult classifier enabled file in debugfs\n"); -- debugfs_remove_recursive(ecm_classifier_default_dentry); -- return -1; -- } -+ debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_default_dentry, -+ (u32 *)&ecm_classifier_default_enabled); - -- if (!debugfs_create_u32("accel_mode", S_IRUGO | S_IWUSR, ecm_classifier_default_dentry, -- (u32 *)&ecm_classifier_default_accel_mode)) { -- DEBUG_ERROR("Failed to create ecm deafult classifier accel_mode file in debugfs\n"); -- debugfs_remove_recursive(ecm_classifier_default_dentry); -- return -1; -- } -+ debugfs_create_u32("accel_mode", S_IRUGO | S_IWUSR, ecm_classifier_default_dentry, -+ (u32 *)&ecm_classifier_default_accel_mode); - -- if (!debugfs_create_u32("accel_delay_pkts", S_IRUGO | S_IWUSR, ecm_classifier_default_dentry, -- (u32 *)&ecm_classifier_accel_delay_pkts)) { -- DEBUG_ERROR("Failed to create accel delay packet counts in debugfs\n"); -- debugfs_remove_recursive(ecm_classifier_default_dentry); -- return -1; -- } -+ debugfs_create_u32("accel_delay_pkts", S_IRUGO | S_IWUSR, ecm_classifier_default_dentry, -+ (u32 *)&ecm_classifier_accel_delay_pkts); - - return 0; - } ---- a/ecm_classifier_dscp.c -+++ b/ecm_classifier_dscp.c -@@ -747,12 +747,8 @@ int ecm_classifier_dscp_init(struct dent - return -1; - } - -- if (!debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_dscp_dentry, -- (u32 *)&ecm_classifier_dscp_enabled)) { -- DEBUG_ERROR("Failed to create dscp enabled file in debugfs\n"); -- debugfs_remove_recursive(ecm_classifier_dscp_dentry); -- return -1; -- } -+ debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_dscp_dentry, -+ (u32 *)&ecm_classifier_dscp_enabled); - - return 0; - } ---- a/ecm_classifier_emesh.c -+++ b/ecm_classifier_emesh.c -@@ -974,19 +974,11 @@ int ecm_classifier_emesh_init(struct den - return -1; - } - -- if (!debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_emesh_dentry, -- (u32 *)&ecm_classifier_emesh_enabled)) { -- DEBUG_ERROR("Failed to create ecm emesh classifier enabled file in debugfs\n"); -- debugfs_remove_recursive(ecm_classifier_emesh_dentry); -- return -1; -- } -+ debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_emesh_dentry, -+ (u32 *)&ecm_classifier_emesh_enabled); - -- if (!debugfs_create_u32("latency_config_enabled", S_IRUGO | S_IWUSR, ecm_classifier_emesh_dentry, -- (u32 *)&ecm_classifier_emesh_latency_config_enabled)) { -- DEBUG_ERROR("Failed to create ecm emesh classifier latency config enabled file in debugfs\n"); -- debugfs_remove_recursive(ecm_classifier_emesh_dentry); -- return -1; -- } -+ debugfs_create_u32("latency_config_enabled", S_IRUGO | S_IWUSR, ecm_classifier_emesh_dentry, -+ (u32 *)&ecm_classifier_emesh_latency_config_enabled); - - /* - * Register for service prioritization notification update. ---- a/ecm_classifier_hyfi.c -+++ b/ecm_classifier_hyfi.c -@@ -1099,11 +1099,8 @@ int ecm_classifier_hyfi_rules_init(struc - goto classifier_task_cleanup; - } - -- if (!debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_hyfi_dentry, -- (u32 *)&ecm_classifier_hyfi_enabled)) { -- DEBUG_ERROR("Failed to create ecm hyfi classifier enabled file in debugfs\n"); -- goto classifier_task_cleanup; -- } -+ debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_hyfi_dentry, -+ (u32 *)&ecm_classifier_hyfi_enabled); - - if (!debugfs_create_file("cmd", S_IWUSR, ecm_classifier_hyfi_dentry, - NULL, &ecm_classifier_hyfi_cmd_fops)) { ---- a/ecm_classifier_mark.c -+++ b/ecm_classifier_mark.c -@@ -753,12 +753,8 @@ int ecm_classifier_mark_init(struct dent - return -1; - } - -- if (!debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_mark_dentry, -- (u32 *)&ecm_classifier_mark_enabled)) { -- DEBUG_ERROR("Failed to create mark enabled file in debugfs\n"); -- debugfs_remove_recursive(ecm_classifier_mark_dentry); -- return -1; -- } -+ debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_mark_dentry, -+ (u32 *)&ecm_classifier_mark_enabled); - - return 0; - } ---- a/ecm_classifier_ovs.c -+++ b/ecm_classifier_ovs.c -@@ -2200,12 +2200,8 @@ int ecm_classifier_ovs_init(struct dentr - return -1; - } - -- if (!debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_ovs_dentry, -- (u32 *)&ecm_classifier_ovs_enabled)) { -- DEBUG_ERROR("Failed to create ovs enabled file in debugfs\n"); -- debugfs_remove_recursive(ecm_classifier_ovs_dentry); -- return -1; -- } -+ debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_ovs_dentry, -+ (u32 *)&ecm_classifier_ovs_enabled); - - return 0; - } ---- a/ecm_classifier_pcc.c -+++ b/ecm_classifier_pcc.c -@@ -1308,12 +1308,8 @@ int ecm_classifier_pcc_init(struct dentr - return -1; - } - -- if (!debugfs_create_u32("enabled", S_IRUGO, ecm_classifier_pcc_dentry, -- (u32 *)&ecm_classifier_pcc_enabled)) { -- DEBUG_ERROR("Failed to create pcc enabled file in debugfs\n"); -- debugfs_remove_recursive(ecm_classifier_pcc_dentry); -- return -1; -- } -+ debugfs_create_u32("enabled", S_IRUGO, ecm_classifier_pcc_dentry, -+ (u32 *)&ecm_classifier_pcc_enabled); - - return 0; - } ---- a/ecm_conntrack_notifier.c -+++ b/ecm_conntrack_notifier.c -@@ -414,12 +414,8 @@ int ecm_conntrack_notifier_init(struct d - return -1; - } - -- if (!debugfs_create_u32("stop", S_IRUGO | S_IWUSR, ecm_conntrack_notifier_dentry, -- (u32 *)&ecm_conntrack_notifier_stopped)) { -- DEBUG_ERROR("Failed to create ecm conntrack notifier stopped file in debugfs\n"); -- debugfs_remove_recursive(ecm_conntrack_notifier_dentry); -- return -1; -- } -+ debugfs_create_u32("stop", S_IRUGO | S_IWUSR, ecm_conntrack_notifier_dentry, -+ (u32 *)&ecm_conntrack_notifier_stopped); - - #ifdef CONFIG_NF_CONNTRACK_EVENTS - /* ---- a/ecm_db/ecm_db_connection.c -+++ b/ecm_db/ecm_db_connection.c -@@ -3642,11 +3642,8 @@ static struct file_operations ecm_db_con - */ - bool ecm_db_connection_init(struct dentry *dentry) - { -- if (!debugfs_create_u32("connection_count", S_IRUGO, dentry, -- (u32 *)&ecm_db_connection_count)) { -- DEBUG_ERROR("Failed to create ecm db connection count file in debugfs\n"); -- return false; -- } -+ debugfs_create_u32("connection_count", S_IRUGO, dentry, -+ (u32 *)&ecm_db_connection_count); - - if (!debugfs_create_file("connection_count_simple", S_IRUGO, dentry, - NULL, &ecm_db_connection_count_simple_fops)) { ---- a/ecm_db/ecm_db_host.c -+++ b/ecm_db/ecm_db_host.c -@@ -770,11 +770,8 @@ EXPORT_SYMBOL(ecm_db_host_alloc); - bool ecm_db_host_init(struct dentry *dentry) - { - -- if (!debugfs_create_u32("host_count", S_IRUGO, dentry, -- (u32 *)&ecm_db_host_count)) { -- DEBUG_ERROR("Failed to create ecm db host count file in debugfs\n"); -- return false;; -- } -+ debugfs_create_u32("host_count", S_IRUGO, dentry, -+ (u32 *)&ecm_db_host_count); - - ecm_db_host_table = vzalloc(sizeof(struct ecm_db_host_instance *) * ECM_DB_HOST_HASH_SLOTS); - if (!ecm_db_host_table) { ---- a/ecm_db/ecm_db_iface.c -+++ b/ecm_db/ecm_db_iface.c -@@ -3670,11 +3670,8 @@ EXPORT_SYMBOL(ecm_db_iface_alloc); - */ - bool ecm_db_iface_init(struct dentry *dentry) - { -- if (!debugfs_create_u32("iface_count", S_IRUGO, dentry, -- (u32 *)&ecm_db_iface_count)) { -- DEBUG_ERROR("Failed to create ecm db iface count file in debugfs\n"); -- return false; -- } -+ debugfs_create_u32("iface_count", S_IRUGO, dentry, -+ (u32 *)&ecm_db_iface_count); - - return true; - } ---- a/ecm_db/ecm_db_mapping.c -+++ b/ecm_db/ecm_db_mapping.c -@@ -806,11 +806,8 @@ EXPORT_SYMBOL(ecm_db_mapping_alloc); - */ - bool ecm_db_mapping_init(struct dentry *dentry) - { -- if (!debugfs_create_u32("mapping_count", S_IRUGO, dentry, -- (u32 *)&ecm_db_mapping_count)) { -- DEBUG_ERROR("Failed to create ecm db mapping count file in debugfs\n"); -- return false; -- } -+ debugfs_create_u32("mapping_count", S_IRUGO, dentry, -+ (u32 *)&ecm_db_mapping_count); - - ecm_db_mapping_table = vzalloc(sizeof(struct ecm_db_mapping_instance *) * ECM_DB_MAPPING_HASH_SLOTS); - if (!ecm_db_mapping_table) { ---- a/ecm_db/ecm_db_node.c -+++ b/ecm_db/ecm_db_node.c -@@ -1187,11 +1187,8 @@ keep_sni_conn: - */ - bool ecm_db_node_init(struct dentry *dentry) - { -- if (!debugfs_create_u32("node_count", S_IRUGO, dentry, -- (u32 *)&ecm_db_node_count)) { -- DEBUG_ERROR("Failed to create ecm db node count file in debugfs\n"); -- return false; -- } -+ debugfs_create_u32("node_count", S_IRUGO, dentry, -+ (u32 *)&ecm_db_node_count); - - ecm_db_node_table = vzalloc(sizeof(struct ecm_db_node_instance *) * ECM_DB_NODE_HASH_SLOTS); - if (!ecm_db_node_table) { ---- a/ecm_interface.c -+++ b/ecm_interface.c -@@ -332,7 +332,7 @@ static struct net_device *ecm_interface_ - struct net_device *dev; - - ECM_IP_ADDR_TO_NIN6_ADDR(addr6, addr); -- dev = (struct net_device *)ipv6_dev_find(&init_net, &addr6, 1); -+ dev = (struct net_device *)ipv6_dev_find_and_hold(&init_net, &addr6, 1); - return dev; - } - #endif -@@ -734,7 +734,7 @@ static bool ecm_interface_mac_addr_get_i - * Get the MAC address that corresponds to IP address given. - */ - ECM_IP_ADDR_TO_NIN6_ADDR(daddr, addr); -- local_dev = ipv6_dev_find(&init_net, &daddr, 1); -+ local_dev = ipv6_dev_find_and_hold(&init_net, &daddr, 1); - if (local_dev) { - DEBUG_TRACE("%pi6 is a local address\n", &daddr); - memcpy(mac_addr, dev->dev_addr, ETH_ALEN); ---- a/ecm_state.c -+++ b/ecm_state.c -@@ -899,17 +899,11 @@ int ecm_state_init(struct dentry *dentry - return -1; - } - -- if (!debugfs_create_u32("state_dev_major", S_IRUGO, ecm_state_dentry, -- (u32 *)&ecm_state_dev_major_id)) { -- DEBUG_ERROR("Failed to create ecm state dev major file in debugfs\n"); -- goto init_cleanup; -- } -+ debugfs_create_u32("state_dev_major", S_IRUGO, ecm_state_dentry, -+ (u32 *)&ecm_state_dev_major_id); - -- if (!debugfs_create_u32("state_file_output_mask", S_IRUGO | S_IWUSR, ecm_state_dentry, -- (u32 *)&ecm_state_file_output_mask)) { -- DEBUG_ERROR("Failed to create ecm state output mask file in debugfs\n"); -- goto init_cleanup; -- } -+ debugfs_create_u32("state_file_output_mask", S_IRUGO | S_IWUSR, ecm_state_dentry, -+ (u32 *)&ecm_state_file_output_mask); - - /* - * Register a char device that we will use to provide a dump of our state ---- a/frontends/ecm_front_end_common.c -+++ b/frontends/ecm_front_end_common.c -@@ -192,7 +192,7 @@ bool ecm_front_end_gre_proto_is_accel_al - return false; - } - } else { -- dev = ipv6_dev_find(&init_net, &(tuple->src.u3.in6), 1); -+ dev = ipv6_dev_find_and_hold(&init_net, &(tuple->src.u3.in6), 1); - if (dev) { - /* - * Source IP address is local -@@ -202,7 +202,7 @@ bool ecm_front_end_gre_proto_is_accel_al - return false; - } - -- dev = ipv6_dev_find(&init_net, &(tuple->dst.u3.in6), 1); -+ dev = ipv6_dev_find_and_hold(&init_net, &(tuple->dst.u3.in6), 1); - if (dev) { - /* - * Destination IP address is local ---- a/frontends/ecm_front_end_ipv4.c -+++ b/frontends/ecm_front_end_ipv4.c -@@ -376,11 +376,8 @@ void ecm_front_end_ipv4_stop(int num) - */ - int ecm_front_end_ipv4_init(struct dentry *dentry) - { -- if (!debugfs_create_u32("front_end_ipv4_stop", S_IRUGO | S_IWUSR, dentry, -- (u32 *)&ecm_front_end_ipv4_stopped)) { -- DEBUG_ERROR("Failed to create ecm front end ipv4 stop file in debugfs\n"); -- return -1; -- } -+ debugfs_create_u32("front_end_ipv4_stop", S_IRUGO | S_IWUSR, dentry, -+ (u32 *)&ecm_front_end_ipv4_stopped); - - switch (ecm_front_end_type_get()) { - case ECM_FRONT_END_TYPE_NSS: ---- a/frontends/ecm_front_end_ipv6.c -+++ b/frontends/ecm_front_end_ipv6.c -@@ -255,11 +255,8 @@ void ecm_front_end_ipv6_stop(int num) - */ - int ecm_front_end_ipv6_init(struct dentry *dentry) - { -- if (!debugfs_create_u32("front_end_ipv6_stop", S_IRUGO | S_IWUSR, dentry, -- (u32 *)&ecm_front_end_ipv6_stopped)) { -- DEBUG_ERROR("Failed to create ecm front end ipv6 stop file in debugfs\n"); -- return -1; -- } -+ debugfs_create_u32("front_end_ipv6_stop", S_IRUGO | S_IWUSR, dentry, -+ (u32 *)&ecm_front_end_ipv6_stopped); - - switch (ecm_front_end_type_get()) { - case ECM_FRONT_END_TYPE_NSS: ---- a/frontends/nss/ecm_nss_bond_notifier.c -+++ b/frontends/nss/ecm_nss_bond_notifier.c -@@ -240,12 +240,8 @@ int ecm_nss_bond_notifier_init(struct de - return -1; - } - -- if (!debugfs_create_u32("stop", S_IRUGO | S_IWUSR, ecm_nss_bond_notifier_dentry, -- (u32 *)&ecm_nss_bond_notifier_stopped)) { -- DEBUG_ERROR("Failed to create ecm bond notifier stopped file in debugfs\n"); -- debugfs_remove_recursive(ecm_nss_bond_notifier_dentry); -- return -1; -- } -+ debugfs_create_u32("stop", S_IRUGO | S_IWUSR, ecm_nss_bond_notifier_dentry, -+ (u32 *)&ecm_nss_bond_notifier_stopped); - - /* - * Register Link Aggregation callbacks with the bonding driver ---- a/frontends/nss/ecm_nss_ipv4.c -+++ b/frontends/nss/ecm_nss_ipv4.c -@@ -2802,41 +2802,23 @@ int ecm_nss_ipv4_init(struct dentry *den - return result; - } - -- if (!debugfs_create_u32("no_action_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, -- (u32 *)&ecm_nss_ipv4_no_action_limit_default)) { -- DEBUG_ERROR("Failed to create ecm nss ipv4 no_action_limit_default file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("no_action_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, -+ (u32 *)&ecm_nss_ipv4_no_action_limit_default); - -- if (!debugfs_create_u32("driver_fail_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, -- (u32 *)&ecm_nss_ipv4_driver_fail_limit_default)) { -- DEBUG_ERROR("Failed to create ecm nss ipv4 driver_fail_limit_default file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("driver_fail_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, -+ (u32 *)&ecm_nss_ipv4_driver_fail_limit_default); - -- if (!debugfs_create_u32("nack_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, -- (u32 *)&ecm_nss_ipv4_nack_limit_default)) { -- DEBUG_ERROR("Failed to create ecm nss ipv4 nack_limit_default file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("nack_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, -+ (u32 *)&ecm_nss_ipv4_nack_limit_default); - -- if (!debugfs_create_u32("accelerated_count", S_IRUGO, ecm_nss_ipv4_dentry, -- (u32 *)&ecm_nss_ipv4_accelerated_count)) { -- DEBUG_ERROR("Failed to create ecm nss ipv4 accelerated_count file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("accelerated_count", S_IRUGO, ecm_nss_ipv4_dentry, -+ (u32 *)&ecm_nss_ipv4_accelerated_count); - -- if (!debugfs_create_u32("pending_accel_count", S_IRUGO, ecm_nss_ipv4_dentry, -- (u32 *)&ecm_nss_ipv4_pending_accel_count)) { -- DEBUG_ERROR("Failed to create ecm nss ipv4 pending_accel_count file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("pending_accel_count", S_IRUGO, ecm_nss_ipv4_dentry, -+ (u32 *)&ecm_nss_ipv4_pending_accel_count); - -- if (!debugfs_create_u32("pending_decel_count", S_IRUGO, ecm_nss_ipv4_dentry, -- (u32 *)&ecm_nss_ipv4_pending_decel_count)) { -- DEBUG_ERROR("Failed to create ecm nss ipv4 pending_decel_count file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("pending_decel_count", S_IRUGO, ecm_nss_ipv4_dentry, -+ (u32 *)&ecm_nss_ipv4_pending_decel_count); - - if (!debugfs_create_file("accel_limit_mode", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, - NULL, &ecm_nss_ipv4_accel_limit_mode_fops)) { -@@ -2867,11 +2849,8 @@ int ecm_nss_ipv4_init(struct dentry *den - goto task_cleanup; - } - -- if (!debugfs_create_u32("vlan_passthrough_set", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, -- (u32 *)&ecm_nss_ipv4_vlan_passthrough_enable)) { -- DEBUG_ERROR("Failed to create ecm nss ipv4 vlan passthrough file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("vlan_passthrough_set", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, -+ (u32 *)&ecm_nss_ipv4_vlan_passthrough_enable); - - #ifdef ECM_NON_PORTED_SUPPORT_ENABLE - if (!ecm_nss_non_ported_ipv4_debugfs_init(ecm_nss_ipv4_dentry)) { ---- a/frontends/nss/ecm_nss_ipv6.c -+++ b/frontends/nss/ecm_nss_ipv6.c -@@ -2542,41 +2542,23 @@ int ecm_nss_ipv6_init(struct dentry *den - return result; - } - -- if (!debugfs_create_u32("no_action_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, -- (u32 *)&ecm_nss_ipv6_no_action_limit_default)) { -- DEBUG_ERROR("Failed to create ecm nss ipv6 no_action_limit_default file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("no_action_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, -+ (u32 *)&ecm_nss_ipv6_no_action_limit_default); - -- if (!debugfs_create_u32("driver_fail_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, -- (u32 *)&ecm_nss_ipv6_driver_fail_limit_default)) { -- DEBUG_ERROR("Failed to create ecm nss ipv6 driver_fail_limit_default file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("driver_fail_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, -+ (u32 *)&ecm_nss_ipv6_driver_fail_limit_default); - -- if (!debugfs_create_u32("nack_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, -- (u32 *)&ecm_nss_ipv6_nack_limit_default)) { -- DEBUG_ERROR("Failed to create ecm nss ipv6 nack_limit_default file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("nack_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, -+ (u32 *)&ecm_nss_ipv6_nack_limit_default); - -- if (!debugfs_create_u32("accelerated_count", S_IRUGO, ecm_nss_ipv6_dentry, -- (u32 *)&ecm_nss_ipv6_accelerated_count)) { -- DEBUG_ERROR("Failed to create ecm nss ipv6 accelerated_count file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("accelerated_count", S_IRUGO, ecm_nss_ipv6_dentry, -+ (u32 *)&ecm_nss_ipv6_accelerated_count); - -- if (!debugfs_create_u32("pending_accel_count", S_IRUGO, ecm_nss_ipv6_dentry, -- (u32 *)&ecm_nss_ipv6_pending_accel_count)) { -- DEBUG_ERROR("Failed to create ecm nss ipv6 pending_accel_count file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("pending_accel_count", S_IRUGO, ecm_nss_ipv6_dentry, -+ (u32 *)&ecm_nss_ipv6_pending_accel_count); - -- if (!debugfs_create_u32("pending_decel_count", S_IRUGO, ecm_nss_ipv6_dentry, -- (u32 *)&ecm_nss_ipv6_pending_decel_count)) { -- DEBUG_ERROR("Failed to create ecm nss ipv6 pending_decel_count file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("pending_decel_count", S_IRUGO, ecm_nss_ipv6_dentry, -+ (u32 *)&ecm_nss_ipv6_pending_decel_count); - - if (!debugfs_create_file("accel_limit_mode", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, - NULL, &ecm_nss_ipv6_accel_limit_mode_fops)) { -@@ -2607,11 +2589,8 @@ int ecm_nss_ipv6_init(struct dentry *den - goto task_cleanup; - } - -- if (!debugfs_create_u32("vlan_passthrough_set", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, -- (u32 *)&ecm_nss_ipv6_vlan_passthrough_enable)) { -- DEBUG_ERROR("Failed to create ecm nss ipv6 vlan passthrough file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("vlan_passthrough_set", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, -+ (u32 *)&ecm_nss_ipv6_vlan_passthrough_enable); - - #ifdef ECM_NON_PORTED_SUPPORT_ENABLE - if (!ecm_nss_non_ported_ipv6_debugfs_init(ecm_nss_ipv6_dentry)) { ---- a/frontends/nss/ecm_nss_multicast_ipv4.c -+++ b/frontends/nss/ecm_nss_multicast_ipv4.c -@@ -4139,11 +4139,8 @@ void ecm_nss_multicast_ipv4_stop(int num - */ - int ecm_nss_multicast_ipv4_init(struct dentry *dentry) - { -- if (!debugfs_create_u32("ecm_nss_multicast_ipv4_stop", S_IRUGO | S_IWUSR, dentry, -- (u32 *)&ecm_front_end_ipv4_mc_stopped)) { -- DEBUG_ERROR("Failed to create ecm front end ipv4 mc stop file in debugfs\n"); -- return -1; -- } -+ debugfs_create_u32("ecm_nss_multicast_ipv4_stop", S_IRUGO | S_IWUSR, dentry, -+ (u32 *)&ecm_front_end_ipv4_mc_stopped); - - /* - * Register multicast update callback to MCS snooper ---- a/frontends/nss/ecm_nss_multicast_ipv6.c -+++ b/frontends/nss/ecm_nss_multicast_ipv6.c -@@ -3939,11 +3939,8 @@ void ecm_nss_multicast_ipv6_stop(int num - */ - int ecm_nss_multicast_ipv6_init(struct dentry *dentry) - { -- if (!debugfs_create_u32("ecm_nss_multicast_ipv6_stop", S_IRUGO | S_IWUSR, dentry, -- (u32 *)&ecm_front_end_ipv6_mc_stopped)) { -- DEBUG_ERROR("Failed to create ecm front end ipv6 mc stop file in debugfs\n"); -- return -1; -- } -+ debugfs_create_u32("ecm_nss_multicast_ipv6_stop", S_IRUGO | S_IWUSR, dentry, -+ (u32 *)&ecm_front_end_ipv6_mc_stopped); - - /* - * Register multicast update callback to MCS snooper ---- a/frontends/nss/ecm_nss_non_ported_ipv4.c -+++ b/frontends/nss/ecm_nss_non_ported_ipv4.c -@@ -2615,11 +2615,8 @@ done: - */ - bool ecm_nss_non_ported_ipv4_debugfs_init(struct dentry *dentry) - { -- if (!debugfs_create_u32("non_ported_accelerated_count", S_IRUGO, dentry, -- (u32 *)&ecm_nss_non_ported_ipv4_accelerated_count)) { -- DEBUG_ERROR("Failed to create ecm nss ipv4 non_ported_accelerated_count file in debugfs\n"); -- return false; -- } -+ debugfs_create_u32("non_ported_accelerated_count", S_IRUGO, dentry, -+ (u32 *)&ecm_nss_non_ported_ipv4_accelerated_count); - - return true; - } ---- a/frontends/nss/ecm_nss_non_ported_ipv6.c -+++ b/frontends/nss/ecm_nss_non_ported_ipv6.c -@@ -2329,11 +2329,8 @@ done: - */ - bool ecm_nss_non_ported_ipv6_debugfs_init(struct dentry *dentry) - { -- if (!debugfs_create_u32("non_ported_accelerated_count", S_IRUGO, dentry, -- (u32 *)&ecm_nss_non_ported_ipv6_accelerated_count)) { -- DEBUG_ERROR("Failed to create ecm nss ipv6 non_ported_accelerated_count file in debugfs\n"); -- return false; -- } -+ debugfs_create_u32("non_ported_accelerated_count", S_IRUGO, dentry, -+ (u32 *)&ecm_nss_non_ported_ipv6_accelerated_count); - - return true; - } ---- a/frontends/nss/ecm_nss_ported_ipv4.c -+++ b/frontends/nss/ecm_nss_ported_ipv4.c -@@ -2944,12 +2944,8 @@ bool ecm_nss_ported_ipv4_debugfs_init(st - return false; - } - -- if (!debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, -- &ecm_nss_ported_ipv4_accelerated_count[ECM_NSS_PORTED_IPV4_PROTO_TCP])) { -- DEBUG_ERROR("Failed to create ecm nss ipv4 tcp_accelerated_count file in debugfs\n"); -- debugfs_remove(udp_dentry); -- return false; -- } -+ debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, -+ &ecm_nss_ported_ipv4_accelerated_count[ECM_NSS_PORTED_IPV4_PROTO_TCP]); - - return true; - } ---- a/frontends/nss/ecm_nss_ported_ipv6.c -+++ b/frontends/nss/ecm_nss_ported_ipv6.c -@@ -2732,12 +2732,8 @@ bool ecm_nss_ported_ipv6_debugfs_init(st - return false; - } - -- if (!debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, -- &ecm_nss_ported_ipv6_accelerated_count[ECM_NSS_PORTED_IPV6_PROTO_TCP])) { -- DEBUG_ERROR("Failed to create ecm nss ipv6 tcp_accelerated_count file in debugfs\n"); -- debugfs_remove(udp_dentry); -- return false; -- } -+ debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, -+ &ecm_nss_ported_ipv6_accelerated_count[ECM_NSS_PORTED_IPV6_PROTO_TCP]); - - return true; - } ---- a/frontends/sfe/ecm_sfe_ipv4.c -+++ b/frontends/sfe/ecm_sfe_ipv4.c -@@ -1808,48 +1808,27 @@ int ecm_sfe_ipv4_init(struct dentry *den - } - - #ifdef CONFIG_XFRM -- if (!debugfs_create_u32("reject_acceleration_for_ipsec", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, -- (u32 *)&ecm_sfe_ipv4_reject_acceleration_for_ipsec)) { -- DEBUG_ERROR("Failed to create ecm sfe ipv4 reject_acceleration_for_ipsec file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("reject_acceleration_for_ipsec", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, -+ (u32 *)&ecm_sfe_ipv4_reject_acceleration_for_ipsec); - #endif - -- if (!debugfs_create_u32("no_action_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, -- (u32 *)&ecm_sfe_ipv4_no_action_limit_default)) { -- DEBUG_ERROR("Failed to create ecm sfe ipv4 no_action_limit_default file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("no_action_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, -+ (u32 *)&ecm_sfe_ipv4_no_action_limit_default); - -- if (!debugfs_create_u32("driver_fail_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, -- (u32 *)&ecm_sfe_ipv4_driver_fail_limit_default)) { -- DEBUG_ERROR("Failed to create ecm sfe ipv4 driver_fail_limit_default file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("driver_fail_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, -+ (u32 *)&ecm_sfe_ipv4_driver_fail_limit_default); - -- if (!debugfs_create_u32("nack_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, -- (u32 *)&ecm_sfe_ipv4_nack_limit_default)) { -- DEBUG_ERROR("Failed to create ecm sfe ipv4 nack_limit_default file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("nack_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, -+ (u32 *)&ecm_sfe_ipv4_nack_limit_default); - -- if (!debugfs_create_u32("accelerated_count", S_IRUGO, ecm_sfe_ipv4_dentry, -- (u32 *)&ecm_sfe_ipv4_accelerated_count)) { -- DEBUG_ERROR("Failed to create ecm sfe ipv4 accelerated_count file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("accelerated_count", S_IRUGO, ecm_sfe_ipv4_dentry, -+ (u32 *)&ecm_sfe_ipv4_accelerated_count); - -- if (!debugfs_create_u32("pending_accel_count", S_IRUGO, ecm_sfe_ipv4_dentry, -- (u32 *)&ecm_sfe_ipv4_pending_accel_count)) { -- DEBUG_ERROR("Failed to create ecm sfe ipv4 pending_accel_count file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("pending_accel_count", S_IRUGO, ecm_sfe_ipv4_dentry, -+ (u32 *)&ecm_sfe_ipv4_pending_accel_count); - -- if (!debugfs_create_u32("pending_decel_count", S_IRUGO, ecm_sfe_ipv4_dentry, -- (u32 *)&ecm_sfe_ipv4_pending_decel_count)) { -- DEBUG_ERROR("Failed to create ecm sfe ipv4 pending_decel_count file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("pending_decel_count", S_IRUGO, ecm_sfe_ipv4_dentry, -+ (u32 *)&ecm_sfe_ipv4_pending_decel_count); - - if (!debugfs_create_file("accel_limit_mode", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, - NULL, &ecm_sfe_ipv4_accel_limit_mode_fops)) { ---- a/frontends/sfe/ecm_sfe_ipv6.c -+++ b/frontends/sfe/ecm_sfe_ipv6.c -@@ -1532,48 +1532,27 @@ int ecm_sfe_ipv6_init(struct dentry *den - } - - #ifdef CONFIG_XFRM -- if (!debugfs_create_u32("reject_acceleration_for_ipsec", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, -- (u32 *)&ecm_sfe_ipv6_reject_acceleration_for_ipsec)) { -- DEBUG_ERROR("Failed to create ecm sfe ipv6 reject_acceleration_for_ipsec file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("reject_acceleration_for_ipsec", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, -+ (u32 *)&ecm_sfe_ipv6_reject_acceleration_for_ipsec); - #endif - -- if (!debugfs_create_u32("no_action_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, -- (u32 *)&ecm_sfe_ipv6_no_action_limit_default)) { -- DEBUG_ERROR("Failed to create ecm sfe ipv6 no_action_limit_default file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("no_action_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, -+ (u32 *)&ecm_sfe_ipv6_no_action_limit_default); - -- if (!debugfs_create_u32("driver_fail_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, -- (u32 *)&ecm_sfe_ipv6_driver_fail_limit_default)) { -- DEBUG_ERROR("Failed to create ecm sfe ipv6 driver_fail_limit_default file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("driver_fail_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, -+ (u32 *)&ecm_sfe_ipv6_driver_fail_limit_default); - -- if (!debugfs_create_u32("nack_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, -- (u32 *)&ecm_sfe_ipv6_nack_limit_default)) { -- DEBUG_ERROR("Failed to create ecm sfe ipv6 nack_limit_default file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("nack_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, -+ (u32 *)&ecm_sfe_ipv6_nack_limit_default); - -- if (!debugfs_create_u32("accelerated_count", S_IRUGO, ecm_sfe_ipv6_dentry, -- (u32 *)&ecm_sfe_ipv6_accelerated_count)) { -- DEBUG_ERROR("Failed to create ecm sfe ipv6 accelerated_count file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("accelerated_count", S_IRUGO, ecm_sfe_ipv6_dentry, -+ (u32 *)&ecm_sfe_ipv6_accelerated_count); - -- if (!debugfs_create_u32("pending_accel_count", S_IRUGO, ecm_sfe_ipv6_dentry, -- (u32 *)&ecm_sfe_ipv6_pending_accel_count)) { -- DEBUG_ERROR("Failed to create ecm sfe ipv6 pending_accel_count file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("pending_accel_count", S_IRUGO, ecm_sfe_ipv6_dentry, -+ (u32 *)&ecm_sfe_ipv6_pending_accel_count); - -- if (!debugfs_create_u32("pending_decel_count", S_IRUGO, ecm_sfe_ipv6_dentry, -- (u32 *)&ecm_sfe_ipv6_pending_decel_count)) { -- DEBUG_ERROR("Failed to create ecm sfe ipv6 pending_decel_count file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("pending_decel_count", S_IRUGO, ecm_sfe_ipv6_dentry, -+ (u32 *)&ecm_sfe_ipv6_pending_decel_count); - - if (!debugfs_create_file("accel_limit_mode", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, - NULL, &ecm_sfe_ipv6_accel_limit_mode_fops)) { ---- a/frontends/sfe/ecm_sfe_non_ported_ipv4.c -+++ b/frontends/sfe/ecm_sfe_non_ported_ipv4.c -@@ -2284,11 +2284,8 @@ done: - */ - bool ecm_sfe_non_ported_ipv4_debugfs_init(struct dentry *dentry) - { -- if (!debugfs_create_u32("non_ported_accelerated_count", S_IRUGO, dentry, -- (u32 *)&ecm_sfe_non_ported_ipv4_accelerated_count)) { -- DEBUG_ERROR("Failed to create ecm sfe ipv4 non_ported_accelerated_count file in debugfs\n"); -- return false; -- } -+ debugfs_create_u32("non_ported_accelerated_count", S_IRUGO, dentry, -+ (u32 *)&ecm_sfe_non_ported_ipv4_accelerated_count); - - return true; - } ---- a/frontends/sfe/ecm_sfe_non_ported_ipv6.c -+++ b/frontends/sfe/ecm_sfe_non_ported_ipv6.c -@@ -2083,11 +2083,8 @@ done: - */ - bool ecm_sfe_non_ported_ipv6_debugfs_init(struct dentry *dentry) - { -- if (!debugfs_create_u32("non_ported_accelerated_count", S_IRUGO, dentry, -- (u32 *)&ecm_sfe_non_ported_ipv6_accelerated_count)) { -- DEBUG_ERROR("Failed to create ecm sfe ipv6 non_ported_accelerated_count file in debugfs\n"); -- return false; -- } -+ debugfs_create_u32("non_ported_accelerated_count", S_IRUGO, dentry, -+ (u32 *)&ecm_sfe_non_ported_ipv6_accelerated_count); - - return true; - } ---- a/frontends/sfe/ecm_sfe_ported_ipv4.c -+++ b/frontends/sfe/ecm_sfe_ported_ipv4.c -@@ -2528,12 +2528,8 @@ bool ecm_sfe_ported_ipv4_debugfs_init(st - return false; - } - -- if (!debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, -- &ecm_sfe_ported_ipv4_accelerated_count[ECM_SFE_PORTED_IPV4_PROTO_TCP])) { -- DEBUG_ERROR("Failed to create ecm sfe ipv4 tcp_accelerated_count file in debugfs\n"); -- debugfs_remove(udp_dentry); -- return false; -- } -+ debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, -+ &ecm_sfe_ported_ipv4_accelerated_count[ECM_SFE_PORTED_IPV4_PROTO_TCP]); - - return true; - } ---- a/frontends/sfe/ecm_sfe_ported_ipv6.c -+++ b/frontends/sfe/ecm_sfe_ported_ipv6.c -@@ -2374,12 +2374,8 @@ bool ecm_sfe_ported_ipv6_debugfs_init(st - return false; - } - -- if (!debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, -- &ecm_sfe_ported_ipv6_accelerated_count[ECM_SFE_PORTED_IPV6_PROTO_TCP])) { -- DEBUG_ERROR("Failed to create ecm sfe ipv6 tcp_accelerated_count file in debugfs\n"); -- debugfs_remove(udp_dentry); -- return false; -- } -+ debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, -+ &ecm_sfe_ported_ipv6_accelerated_count[ECM_SFE_PORTED_IPV6_PROTO_TCP]); - - return true; - } diff --git a/qca/qca-nss-ecm/patches/200-resolve-high-load.patch b/qca/qca-nss-ecm/patches/200-resolve-high-load.patch deleted file mode 100644 index 253b450a5..000000000 --- a/qca/qca-nss-ecm/patches/200-resolve-high-load.patch +++ /dev/null @@ -1,61 +0,0 @@ -From 6924b71ed809b37fffd74d6428a8ca83e5919746 Mon Sep 17 00:00:00 2001 -From: Dirk Buchwalder -Date: Sun, 27 Jun 2021 16:52:39 +0200 -Subject: [PATCH] qca-nss-ecm: resolve the cpu high load regarding ecm - -If using ECM, cpu load goes up (around 1.0) and stucks there. -This is due to using uninterruptible sleep function, -the patch changes this to interruptible sleep function. - -Signed-off-by: Dirk Buchwalder ---- - frontends/nss/ecm_nss_ipv4.c | 4 ++-- - frontends/nss/ecm_nss_ipv6.c | 4 ++-- - 2 files changed, 4 insertions(+), 4 deletions(-) - -diff --git a/frontends/nss/ecm_nss_ipv4.c b/frontends/nss/ecm_nss_ipv4.c -index e00553c..94b39cd 100644 ---- a/frontends/nss/ecm_nss_ipv4.c -+++ b/frontends/nss/ecm_nss_ipv4.c -@@ -2471,7 +2471,7 @@ static void ecm_nss_ipv4_stats_sync_req_work(struct work_struct *work) - } - spin_unlock_bh(&ecm_nss_ipv4_lock); - -- usleep_range(ECM_NSS_IPV4_STATS_SYNC_UDELAY - 100, ECM_NSS_IPV4_STATS_SYNC_UDELAY); -+ msleep_interruptible(ECM_NSS_IPV4_STATS_SYNC_UDELAY / 1000); - - /* - * If index is 0, we are starting a new round, but if we still have time remain -@@ -2485,7 +2485,7 @@ static void ecm_nss_ipv4_stats_sync_req_work(struct work_struct *work) - } - - if (time_after(ecm_nss_ipv4_next_req_time, current_jiffies)) { -- msleep(jiffies_to_msecs(ecm_nss_ipv4_next_req_time - current_jiffies)); -+ msleep_interruptible(jiffies_to_msecs(ecm_nss_ipv4_next_req_time - current_jiffies)); - } - ecm_nss_ipv4_roll_check_jiffies = jiffies; - ecm_nss_ipv4_next_req_time = ecm_nss_ipv4_roll_check_jiffies + ECM_NSS_IPV4_STATS_SYNC_PERIOD; -diff --git a/frontends/nss/ecm_nss_ipv6.c b/frontends/nss/ecm_nss_ipv6.c -index 82e739f..30af050 100644 ---- a/frontends/nss/ecm_nss_ipv6.c -+++ b/frontends/nss/ecm_nss_ipv6.c -@@ -2210,7 +2210,7 @@ static void ecm_nss_ipv6_stats_sync_req_work(struct work_struct *work) - } - spin_unlock_bh(&ecm_nss_ipv6_lock); - -- usleep_range(ECM_NSS_IPV6_STATS_SYNC_UDELAY - 100, ECM_NSS_IPV6_STATS_SYNC_UDELAY); -+ msleep_interruptible(ECM_NSS_IPV6_STATS_SYNC_UDELAY / 1000); - - /* - * If index is 0, we are starting a new round, but if we still have time remain -@@ -2224,7 +2224,7 @@ static void ecm_nss_ipv6_stats_sync_req_work(struct work_struct *work) - } - - if (time_after(ecm_nss_ipv6_next_req_time, current_jiffies)) { -- msleep(jiffies_to_msecs(ecm_nss_ipv6_next_req_time - current_jiffies)); -+ msleep_interruptible(jiffies_to_msecs(ecm_nss_ipv6_next_req_time - current_jiffies)); - } - ecm_nss_ipv6_roll_check_jiffies = jiffies; - ecm_nss_ipv6_next_req_time = ecm_nss_ipv6_roll_check_jiffies + ECM_NSS_IPV6_STATS_SYNC_PERIOD; --- -2.31.1 diff --git a/qca/qca-nss-ecm/patches/203-rework-nfct-notification.patch b/qca/qca-nss-ecm/patches/203-rework-nfct-notification.patch deleted file mode 100644 index 72005cd70..000000000 --- a/qca/qca-nss-ecm/patches/203-rework-nfct-notification.patch +++ /dev/null @@ -1,25 +0,0 @@ ---- a/ecm_conntrack_notifier.c -+++ b/ecm_conntrack_notifier.c -@@ -421,7 +421,11 @@ int ecm_conntrack_notifier_init(struct d - /* - * Eventing subsystem is available so we register a notifier hook to get fast notifications of expired connections - */ -+#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS -+ result = nf_conntrack_register_chain_notifier(&init_net, &ecm_conntrack_notifier); -+#else - result = nf_conntrack_register_notifier(&init_net, &ecm_conntrack_notifier); -+#endif - if (result < 0) { - DEBUG_ERROR("Can't register nf notifier hook.\n"); - debugfs_remove_recursive(ecm_conntrack_notifier_dentry); -@@ -439,7 +443,9 @@ EXPORT_SYMBOL(ecm_conntrack_notifier_ini - void ecm_conntrack_notifier_exit(void) - { - DEBUG_INFO("ECM Conntrack Notifier exit\n"); --#ifdef CONFIG_NF_CONNTRACK_EVENTS -+#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS -+ nf_conntrack_unregister_chain_notifier(&init_net, &ecm_conntrack_notifier); -+#else - nf_conntrack_unregister_notifier(&init_net, &ecm_conntrack_notifier); - #endif - /* diff --git a/qca/qca-nss-ecm/patches/204-More-compile-fixes.patch b/qca/qca-nss-ecm/patches/204-More-compile-fixes.patch deleted file mode 100644 index 63a83c193..000000000 --- a/qca/qca-nss-ecm/patches/204-More-compile-fixes.patch +++ /dev/null @@ -1,49 +0,0 @@ -From e6d701c0d454d841366c556b2ef07a5203ffb35d Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Fri, 21 May 2021 21:41:31 +0200 -Subject: [PATCH] More compile fixes - -More runtime compile fixes. - -Signed-off-by: Robert Marko ---- - frontends/nss/ecm_nss_ported_ipv4.c | 12 +++--------- - frontends/nss/ecm_nss_ported_ipv6.c | 12 +++--------- - 2 files changed, 6 insertions(+), 18 deletions(-) - ---- a/frontends/nss/ecm_nss_ported_ipv4.c -+++ b/frontends/nss/ecm_nss_ported_ipv4.c -@@ -2935,14 +2935,8 @@ done: - */ - bool ecm_nss_ported_ipv4_debugfs_init(struct dentry *dentry) - { -- struct dentry *udp_dentry; -- -- udp_dentry = debugfs_create_u32("udp_accelerated_count", S_IRUGO, dentry, -+ debugfs_create_u32("udp_accelerated_count", S_IRUGO, dentry, - &ecm_nss_ported_ipv4_accelerated_count[ECM_NSS_PORTED_IPV4_PROTO_UDP]); -- if (!udp_dentry) { -- DEBUG_ERROR("Failed to create ecm nss ipv4 udp_accelerated_count file in debugfs\n"); -- return false; -- } - - debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, - &ecm_nss_ported_ipv4_accelerated_count[ECM_NSS_PORTED_IPV4_PROTO_TCP]); ---- a/frontends/nss/ecm_nss_ported_ipv6.c -+++ b/frontends/nss/ecm_nss_ported_ipv6.c -@@ -2723,14 +2723,8 @@ done: - */ - bool ecm_nss_ported_ipv6_debugfs_init(struct dentry *dentry) - { -- struct dentry *udp_dentry; -- -- udp_dentry = debugfs_create_u32("udp_accelerated_count", S_IRUGO, dentry, -+ debugfs_create_u32("udp_accelerated_count", S_IRUGO, dentry, - &ecm_nss_ported_ipv6_accelerated_count[ECM_NSS_PORTED_IPV6_PROTO_UDP]); -- if (!udp_dentry) { -- DEBUG_ERROR("Failed to create ecm nss ipv6 udp_accelerated_count file in debugfs\n"); -- return false; -- } - - debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, - &ecm_nss_ported_ipv6_accelerated_count[ECM_NSS_PORTED_IPV6_PROTO_TCP]); diff --git a/qca/qca-nss-ecm/patches/205-resolve-high-load.patch b/qca/qca-nss-ecm/patches/205-resolve-high-load.patch deleted file mode 100644 index dd1ee13af..000000000 --- a/qca/qca-nss-ecm/patches/205-resolve-high-load.patch +++ /dev/null @@ -1,55 +0,0 @@ -From 6924b71ed809b37fffd74d6428a8ca83e5919746 Mon Sep 17 00:00:00 2001 -From: Dirk Buchwalder -Date: Sun, 27 Jun 2021 16:52:39 +0200 -Subject: [PATCH] qca-nss-ecm: resolve the cpu high load regarding ecm - -If using ECM, cpu load goes up (around 1.0) and stucks there. -This is due to using uninterruptible sleep function, -the patch changes this to interruptible sleep function. - -Signed-off-by: Dirk Buchwalder buchwalder@posteo.de ---- - frontends/nss/ecm_nss_ipv4.c | 4 ++-- - frontends/nss/ecm_nss_ipv6.c | 4 ++-- - 2 files changed, 4 insertions(+), 4 deletions(-) - ---- a/frontends/nss/ecm_nss_ipv4.c -+++ b/frontends/nss/ecm_nss_ipv4.c -@@ -2471,7 +2471,7 @@ static void ecm_nss_ipv4_stats_sync_req_ - } - spin_unlock_bh(&ecm_nss_ipv4_lock); - -- usleep_range(ECM_NSS_IPV4_STATS_SYNC_UDELAY - 100, ECM_NSS_IPV4_STATS_SYNC_UDELAY); -+ msleep_interruptible(ECM_NSS_IPV4_STATS_SYNC_UDELAY / 1000); - - /* - * If index is 0, we are starting a new round, but if we still have time remain -@@ -2485,7 +2485,7 @@ static void ecm_nss_ipv4_stats_sync_req_ - } - - if (time_after(ecm_nss_ipv4_next_req_time, current_jiffies)) { -- msleep(jiffies_to_msecs(ecm_nss_ipv4_next_req_time - current_jiffies)); -+ msleep_interruptible(jiffies_to_msecs(ecm_nss_ipv4_next_req_time - current_jiffies)); - } - ecm_nss_ipv4_roll_check_jiffies = jiffies; - ecm_nss_ipv4_next_req_time = ecm_nss_ipv4_roll_check_jiffies + ECM_NSS_IPV4_STATS_SYNC_PERIOD; ---- a/frontends/nss/ecm_nss_ipv6.c -+++ b/frontends/nss/ecm_nss_ipv6.c -@@ -2210,7 +2210,7 @@ static void ecm_nss_ipv6_stats_sync_req_ - } - spin_unlock_bh(&ecm_nss_ipv6_lock); - -- usleep_range(ECM_NSS_IPV6_STATS_SYNC_UDELAY - 100, ECM_NSS_IPV6_STATS_SYNC_UDELAY); -+ msleep_interruptible(ECM_NSS_IPV6_STATS_SYNC_UDELAY / 1000); - - /* - * If index is 0, we are starting a new round, but if we still have time remain -@@ -2224,7 +2224,7 @@ static void ecm_nss_ipv6_stats_sync_req_ - } - - if (time_after(ecm_nss_ipv6_next_req_time, current_jiffies)) { -- msleep(jiffies_to_msecs(ecm_nss_ipv6_next_req_time - current_jiffies)); -+ msleep_interruptible(jiffies_to_msecs(ecm_nss_ipv6_next_req_time - current_jiffies)); - } - ecm_nss_ipv6_roll_check_jiffies = jiffies; - ecm_nss_ipv6_next_req_time = ecm_nss_ipv6_roll_check_jiffies + ECM_NSS_IPV6_STATS_SYNC_PERIOD; diff --git a/qca/qca-ssdk-shell/Makefile b/qca/qca-ssdk-shell/Makefile deleted file mode 100644 index f872e431e..000000000 --- a/qca/qca-ssdk-shell/Makefile +++ /dev/null @@ -1,48 +0,0 @@ -include $(TOPDIR)/rules.mk - -PKG_NAME:=qca-ssdk-shell -PKG_RELEASE:=$(AUTORELEASE) - -PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/ssdk-shell.git -PKG_SOURCE_PROTO:=git -PKG_SOURCE_DATE:=2022-03-16 -PKG_SOURCE_VERSION:=72a7dc725ae9ccbe7d99f451a6518e7c0dde4740 -PKG_MIRROR_HASH:=a591875ad05d7a6779cf9da575d890bc470889308f239c89a14721924420ac2b - -include $(INCLUDE_DIR)/kernel.mk -include $(INCLUDE_DIR)/package.mk - -define Package/qca-ssdk-shell - SECTION:=QCA - CATEGORY:=Utilities - TITLE:=Shell application for QCA SSDK -endef - - -define Package/qca-ssdk-shell/Description - This package contains a qca-ssdk shell application for QCA chipset -endef - -ifndef CONFIG_TOOLCHAIN_BIN_PATH -CONFIG_TOOLCHAIN_BIN_PATH=$(TOOLCHAIN_DIR)/bin -endif - -QCASSDK_CONFIG_OPTS+= TOOL_PATH=$(CONFIG_TOOLCHAIN_BIN_PATH) \ - SYS_PATH=$(LINUX_DIR) \ - TOOLPREFIX=$(TARGET_CROSS) \ - KVER=$(LINUX_VERSION) \ - CFLAGS="$(TARGET_CFLAGS)" \ - LDFLAGS="$(TARGET_LDFLAGS)" \ - ARCH=$(LINUX_KARCH) - -define Build/Compile - $(MAKE) -C $(PKG_BUILD_DIR) $(strip $(QCASSDK_CONFIG_OPTS)) -endef - -define Package/qca-ssdk-shell/install - $(INSTALL_DIR) $(1)/usr/sbin - $(INSTALL_BIN) $(PKG_BUILD_DIR)/build/bin/ssdk_sh $(1)/usr/sbin/ -endef - - -$(eval $(call BuildPackage,qca-ssdk-shell)) diff --git a/qca/qca-ssdk/Makefile b/qca/qca-ssdk/Makefile deleted file mode 100644 index 5b1a7956f..000000000 --- a/qca/qca-ssdk/Makefile +++ /dev/null @@ -1,91 +0,0 @@ -include $(TOPDIR)/rules.mk - -PKG_NAME:=qca-ssdk -PKG_RELEASE:=$(AUTORELEASE) - -PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/qca-ssdk.git -PKG_SOURCE_PROTO:=git -PKG_SOURCE_DATE:=2022-04-07 -PKG_SOURCE_VERSION:=62955de3c838028d3f72313eef99c57fa4babb71 -PKG_MIRROR_HASH:=84c7de6d1ce82fb15acebea0e44158695a33ed6f18335da32ec9f248dcb4b285 - -include $(INCLUDE_DIR)/kernel.mk -include $(INCLUDE_DIR)/package.mk - -define KernelPackage/qca-ssdk-nohnat - SECTION:=kernel - CATEGORY:=Kernel modules - SUBMENU:=Network Devices - TITLE:=Kernel driver for QCA SSDK - DEPENDS:=@(TARGET_ipq807x) - FILES:=$(PKG_BUILD_DIR)/build/bin/qca-ssdk.ko - AUTOLOAD:=$(call AutoLoad,30,qca-ssdk) -endef - -define KernelPackage/qca-ssdk-nohnat/Description -This package contains a qca-ssdk driver for QCA chipset -endef - -GCC_VERSION=$(shell echo "$(CONFIG_GCC_VERSION)" | sed 's/[^0-9.]*\([0-9.]*\).*/\1/') - -ifdef CONFIG_TOOLCHAIN_BIN_PATH -TOOLCHAIN_BIN_PATH=$(CONFIG_TOOLCHAIN_BIN_PATH) -else -TOOLCHAIN_BIN_PATH=$(TOOLCHAIN_DIR)/bin -endif - -MAKE_FLAGS+= \ - TARGET_NAME=$(CONFIG_TARGET_NAME) \ - TOOL_PATH=$(TOOLCHAIN_BIN_PATH) \ - SYS_PATH=$(LINUX_DIR) \ - TOOLPREFIX=$(TARGET_CROSS) \ - KVER=$(LINUX_VERSION) \ - ARCH=$(LINUX_KARCH) \ - TARGET_SUFFIX=$(CONFIG_TARGET_SUFFIX) \ - GCC_VERSION=$(GCC_VERSION) \ - EXTRA_CFLAGS=-fno-stack-protector -I$(STAGING_DIR)/usr/include \ - $(KERNEL_MAKE_FLAGS) - -ifneq (, $(findstring $(CONFIG_TARGET_BOARD), "ipq60xx" "ipq807x")) - MAKE_FLAGS+= PTP_FEATURE=disable SWCONFIG_FEATURE=disable -endif - -ifeq ($(CONFIG_TARGET_BOARD), "ipq807x") - MAKE_FLAGS+= CHIP_TYPE=HPPE -else ifeq ($(CONFIG_TARGET_BOARD), "ipq60xx") - MAKE_FLAGS+= CHIP_TYPE=CPPE -endif - -define Build/InstallDev - $(INSTALL_DIR) $(1)/usr/include/qca-ssdk - $(INSTALL_DIR) $(1)/usr/include/qca-ssdk/api - $(INSTALL_DIR) $(1)/usr/include/qca-ssdk/ref - $(INSTALL_DIR) $(1)/usr/include/qca-ssdk/fal - $(INSTALL_DIR) $(1)/usr/include/qca-ssdk/sal - $(INSTALL_DIR) $(1)/usr/include/qca-ssdk/init - $(CP) -rf $(PKG_BUILD_DIR)/include/api/sw_ioctl.h $(1)/usr/include/qca-ssdk/api - if [ -f $(PKG_BUILD_DIR)/include/ref/ref_vsi.h ]; then \ - $(CP) -rf $(PKG_BUILD_DIR)/include/ref/ref_vsi.h $(1)/usr/include/qca-ssdk/ref/; \ - fi - if [ -f $(PKG_BUILD_DIR)/include/ref/ref_fdb.h ]; then \ - $(CP) -rf $(PKG_BUILD_DIR)/include/ref/ref_fdb.h $(1)/usr/include/qca-ssdk/ref/; \ - fi - if [ -f $(PKG_BUILD_DIR)/include/ref/ref_port_ctrl.h ]; then \ - $(CP) -rf $(PKG_BUILD_DIR)/include/ref/ref_port_ctrl.h $(1)/usr/include/qca-ssdk/ref/; \ - fi - if [ -f $(PKG_BUILD_DIR)/include/init/ssdk_init.h ]; then \ - $(CP) -rf $(PKG_BUILD_DIR)/include/init/ssdk_init.h $(1)/usr/include/qca-ssdk/init/; \ - fi - $(CP) -rf $(PKG_BUILD_DIR)/include/fal $(1)/usr/include/qca-ssdk - $(CP) -rf $(PKG_BUILD_DIR)/include/common/*.h $(1)/usr/include/qca-ssdk - $(CP) -rf $(PKG_BUILD_DIR)/include/sal/os/linux/*.h $(1)/usr/include/qca-ssdk - $(CP) -rf $(PKG_BUILD_DIR)/include/sal/os/*.h $(1)/usr/include/qca-ssdk - -endef - -define KernelPackage/qca-ssdk-nohnat/install - $(INSTALL_DIR) $(1)/etc/init.d - $(INSTALL_BIN) ./files/qca-ssdk $(1)/etc/init.d/qca-ssdk -endef - -$(eval $(call KernelPackage,qca-ssdk-nohnat)) diff --git a/qca/qca-ssdk/files/qca-ssdk b/qca/qca-ssdk/files/qca-ssdk deleted file mode 100644 index 389279c0c..000000000 --- a/qca/qca-ssdk/files/qca-ssdk +++ /dev/null @@ -1,206 +0,0 @@ -#!/bin/sh /etc/rc.common -# Copyright (c) 2018, The Linux Foundation. All rights reserved. -# -# Permission to use, copy, modify, and/or distribute this software for any -# purpose with or without fee is hereby granted, provided that the above -# copyright notice and this permission notice appear in all copies. -# -# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -# - -START=16 - -#!/bin/sh -ruletype="ip4 ip6" -side="wan lan" -qwan="1 3 2 0 5 7 6 4" -qlan="0 1 2 3 4 5 6 7" - -function create_war_acl_rules(){ - for lw in $side - do - #echo $lw - if [ "$lw" == "wan" ];then - listid=254 - queue=$qwan - portmap=0x20 - else - listid=255 - queue=$qlan - portmap=0x1e - fi - #echo $queue - #echo "creating list $listid" - ssdk_sh acl list create $listid 255 - ruleid=0 - for rt in $ruletype - do - for qid in $queue - do - cmd="ssdk_sh acl rule add $listid $ruleid 1 n 0 0" - #echo $cmd - if [ "$rt" == "ip4" ];then - cmd="$cmd ip4 n n n n n n n n n n n n n n n n n n n n n n n n n n n n n" - #echo $cmd - else - cmd="$cmd ip6 n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n" - #echo $cmd - fi - if [ $ruleid -le 3 ];then - #non-zero dscp - cmd="$cmd y 0x0 0xff" - elif [ $ruleid -le 7 ];then - #zero dscp - cmd="$cmd n" - elif [ $ruleid -le 11 ];then - #non-zero dscp - cmd="$cmd y 0x0 0xff" - else - #zero dscp - cmd="$cmd n" - fi - p=$((ruleid/2)) - cmd="$cmd y mask $((ruleid%2)) 0x1 y mask $((p%2)) 0x1 n n n n n n n n n n n n n n n y n n n n n n n y $qid n n 0 0 n n n n n n n n n n n n n n n n n n n n 0" - #echo $cmd - $cmd - ruleid=`expr $ruleid + 1` - done - done - ssdk_sh acl list bind $listid 0 1 $portmap - done -} - -function create_war_cosmap(){ - ssdk_sh cosmap pri2q set 0 0 - ssdk_sh cosmap pri2q set 1 0 - ssdk_sh cosmap pri2q set 2 0 - ssdk_sh cosmap pri2q set 3 0 - ssdk_sh cosmap pri2q set 4 1 - ssdk_sh cosmap pri2q set 5 1 - ssdk_sh cosmap pri2q set 6 1 - ssdk_sh cosmap pri2q set 7 1 - ssdk_sh cosmap pri2ehq set 0 0 - ssdk_sh cosmap pri2ehq set 1 0 - ssdk_sh cosmap pri2ehq set 2 0 - ssdk_sh cosmap pri2ehq set 3 0 - ssdk_sh cosmap pri2ehq set 4 1 - ssdk_sh cosmap pri2ehq set 5 1 - ssdk_sh cosmap pri2ehq set 6 1 - ssdk_sh cosmap pri2ehq set 7 1 -} - -function create_acl_byp_egstp_rules(){ - ssdk_sh debug module_func set servcode 0xf 0x0 0x0 - ssdk_sh servcode config set 1 n 0 0xfffefc7f 0xffbdff 0 0 0 0 0 0 - ssdk_sh debug module_func set servcode 0x0 0x0 0x0 - ssdk_sh acl list create 56 48 - ssdk_sh acl rule add 56 0 1 n 0 0 mac n n n n n y 01-80-c2-00-00-00 ff-ff-ff-ff-ff-ff n n n n n n n n n n n n n n n n n n n n n n n y n n n n n n n n n n 0 0 n n n n n n n n n n n n n y n n n n n n n n n n n n y n n n n n n n n n n n n 0 - ssdk_sh acl rule add 56 1 1 n 0 0 mac n n n n n n n yes 0x8809 0xffff n n n n n n n n n n n n n n n n n n n n n y n n n n n n n n n n 0 0 n n n n n n n n n n n n n y n n n n n n n n n n n n y n n n n n n n n n n n n 0 - ssdk_sh acl rule add 56 2 1 n 0 0 mac n n n n n n n yes 0x888e 0xffff n n n n n n n n n n n n n n n n n n n n n y n n n n n n n n n n 0 0 n n n n n n n n n n n n n y n n n n n n n n n n n n y n n n n n n n n n n n n 0 - ssdk_sh acl list bind 56 0 2 1 -} - -function delete_war_acl_rules(){ - for lw in $side - do - #echo $lw - if [ "$lw" == "wan" ];then - listid=254 - queue=$qwan - portmap=0x20 - else - listid=255 - queue=$qlan - portmap=0x1e - fi - ssdk_sh acl list unbind $listid 0 1 $portmap - for rt in $ruletype - do - for qid in $queue - do - cmd="ssdk_sh acl rule del $listid 0 1" - echo $cmd - $cmd - done - done - #echo "deleting list $listid" - ssdk_sh acl list destroy $listid - done -} - -function delete_war_cosmap(){ - ssdk_sh cosmap pri2q set 0 0 - ssdk_sh cosmap pri2q set 1 0 - ssdk_sh cosmap pri2q set 2 1 - ssdk_sh cosmap pri2q set 3 1 - ssdk_sh cosmap pri2q set 4 2 - ssdk_sh cosmap pri2q set 5 2 - ssdk_sh cosmap pri2q set 6 3 - ssdk_sh cosmap pri2q set 7 3 - ssdk_sh cosmap pri2ehq set 0 1 - ssdk_sh cosmap pri2ehq set 1 0 - ssdk_sh cosmap pri2ehq set 2 2 - ssdk_sh cosmap pri2ehq set 3 2 - ssdk_sh cosmap pri2ehq set 4 3 - ssdk_sh cosmap pri2ehq set 5 3 - ssdk_sh cosmap pri2ehq set 6 4 - ssdk_sh cosmap pri2ehq set 7 5 -} - -function delete_acl_byp_egstp_rules(){ - ssdk_sh debug module_func set servcode 0xf 0x0 0x0 - ssdk_sh servcode config set 1 n 0 0xfffefcff 0xffbfff 0 0 0 0 0 0 - ssdk_sh debug module_func set servcode 0x0 0x0 0x0 - ssdk_sh acl list unbind 56 0 2 1 - ssdk_sh acl rule del 56 0 1 - ssdk_sh acl rule del 56 1 1 - ssdk_sh acl rule del 56 2 1 - ssdk_sh acl list destroy 56 -} - -function edma_war_config_add(){ - create_war_cosmap - ssdk_sh acl status set enable - create_war_acl_rules -} - -function edma_war_config_del(){ - delete_war_acl_rules - delete_war_cosmap -} - -start() { - chip_ver=`ssdk_sh debug reg get 0 4 | grep Data | tr -d 'SSDK Init OK![Data]:'` - #The following commands should be uncommented to enable EDMA WAR - if [ "$chip_ver" = "0x1401" ]; then - #edma_war_config_add - echo '' - fi - #The following commands should be uncommented to add acl egress stp bypass rules - if [ "$chip_ver" = "0x1500" ] || [ "$chip_ver" = "0x1501" ]; then - #create_acl_byp_egstp_rules - echo '' - fi - echo starting -} - -stop() { - chip_ver=`ssdk_sh debug reg get 0 4 | grep Data | tr -d 'SSDK Init OK![Data]:'` - #The following commands should be uncommented to disable EDMA WAR - if [ "$chip_ver" = "0x1401" ]; then - #edma_war_config_del - echo '' - fi - #The following commands should be uncommented to delete acl egress stp bypass rules - if [ "$chip_ver" = "0x1500" ] || [ "$chip_ver" = "0x1501" ]; then - #delete_acl_byp_egstp_rules - echo '' - fi - echo stoping -} diff --git a/qca/qca-ssdk/patches/0001-SSDK-config-add-kernel-5.10.patch b/qca/qca-ssdk/patches/0001-SSDK-config-add-kernel-5.10.patch deleted file mode 100644 index 8ad541ebf..000000000 --- a/qca/qca-ssdk/patches/0001-SSDK-config-add-kernel-5.10.patch +++ /dev/null @@ -1,56 +0,0 @@ -From 472c0c8132784608312c80c4b02c03ea7c132235 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Wed, 12 May 2021 13:41:12 +0200 -Subject: [PATCH] SSDK: config: add kernel 5.10 - -This is purely to identify it and be able to set -flags correctly. - -Signed-off-by: Robert Marko ---- - config | 6 +++++- - make/linux_opt.mk | 4 ++-- - 2 files changed, 7 insertions(+), 3 deletions(-) - ---- a/config -+++ b/config -@@ -22,6 +22,10 @@ ifeq ($(KVER),$(filter 5.4%,$(KVER))) - OS_VER=5_4 - endif - -+ifeq ($(KVER),$(filter 5.10%,$(KVER))) -+OS_VER=5_10 -+endif -+ - ifeq ($(KVER), 3.4.0) - OS_VER=3_4 - endif -@@ -123,7 +127,7 @@ endif - endif - - ifeq ($(ARCH), arm64) -- ifeq ($(KVER),$(filter 4.1% 4.4% 4.9% 5.4%,$(KVER))) -+ ifeq ($(KVER),$(filter 4.1% 4.4% 4.9% 5.4% 5.10%,$(KVER))) - CPU_CFLAG= -DMODULE -Os -pipe -march=armv8-a -mcpu=cortex-a53+crypto -fno-caller-saves -fno-strict-aliasing -Werror -fno-common -Wno-format-security -Wno-pointer-sign -Wno-unused-but-set-variable -Wno-error=unused-result -mcmodel=large - endif - endif ---- a/make/linux_opt.mk -+++ b/make/linux_opt.mk -@@ -388,7 +388,7 @@ ifeq (KSLIB, $(MODULE_TYPE)) - KASAN_SHADOW_SCALE_SHIFT := 3 - endif - -- ifeq (5_4, $(OS_VER)) -+ ifeq ($(OS_VER),$(filter 5_4 5_10, $(OS_VER))) - ifeq ($(ARCH), arm64) - KASAN_OPTION += -DKASAN_SHADOW_SCALE_SHIFT=$(KASAN_SHADOW_SCALE_SHIFT) - endif -@@ -419,7 +419,7 @@ ifeq (KSLIB, $(MODULE_TYPE)) - - endif - -- ifeq ($(OS_VER),$(filter 4_4 5_4, $(OS_VER))) -+ ifeq ($(OS_VER),$(filter 4_4 5_4 5_10, $(OS_VER))) - MODULE_CFLAG += -DKVER34 - MODULE_CFLAG += -DKVER32 - MODULE_CFLAG += -DLNX26_22 diff --git a/qca/qca-ssdk/patches/0002-SSDK-replace-ioremap_nocache-with-ioremap.patch b/qca/qca-ssdk/patches/0002-SSDK-replace-ioremap_nocache-with-ioremap.patch deleted file mode 100644 index b293ad295..000000000 --- a/qca/qca-ssdk/patches/0002-SSDK-replace-ioremap_nocache-with-ioremap.patch +++ /dev/null @@ -1,102 +0,0 @@ -From 784f2cfdfaf3bdf44917924e157049230a0ef5f8 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Wed, 12 May 2021 13:45:45 +0200 -Subject: [PATCH] SSDK: replace ioremap_nocache with ioremap - -ioremap_nocache was dropped upstream, simply use the -generic variety. - -Signed-off-by: Robert Marko ---- - src/init/ssdk_clk.c | 10 +++++----- - src/init/ssdk_init.c | 2 +- - src/init/ssdk_plat.c | 6 +++--- - 3 files changed, 9 insertions(+), 9 deletions(-) - ---- a/src/init/ssdk_clk.c -+++ b/src/init/ssdk_clk.c -@@ -623,7 +623,7 @@ ssdk_mp_tcsr_get(a_uint32_t tcsr_offset, - { - void __iomem *tcsr_base = NULL; - -- tcsr_base = ioremap_nocache(TCSR_ETH_ADDR, TCSR_ETH_SIZE); -+ tcsr_base = ioremap(TCSR_ETH_ADDR, TCSR_ETH_SIZE); - if (!tcsr_base) - { - SSDK_ERROR("Failed to map tcsr eth address!\n"); -@@ -640,7 +640,7 @@ ssdk_mp_tcsr_set(a_uint32_t tcsr_offset, - { - void __iomem *tcsr_base = NULL; - -- tcsr_base = ioremap_nocache(TCSR_ETH_ADDR, TCSR_ETH_SIZE); -+ tcsr_base = ioremap(TCSR_ETH_ADDR, TCSR_ETH_SIZE); - if (!tcsr_base) - { - SSDK_ERROR("Failed to map tcsr eth address!\n"); -@@ -688,7 +688,7 @@ ssdk_mp_cmnblk_stable_check(void) - a_uint32_t reg_val; - int i, loops = 20; - -- pll_lock = ioremap_nocache(CMN_PLL_LOCKED_ADDR, CMN_PLL_LOCKED_SIZE); -+ pll_lock = ioremap(CMN_PLL_LOCKED_ADDR, CMN_PLL_LOCKED_SIZE); - if (!pll_lock) { - SSDK_ERROR("Failed to map CMN PLL LOCK register!\n"); - return A_FALSE; -@@ -745,7 +745,7 @@ static void ssdk_cmnblk_pll_src_set(enum - void __iomem *cmn_pll_src_base = NULL; - a_uint32_t reg_val; - -- cmn_pll_src_base = ioremap_nocache(CMN_BLK_PLL_SRC_ADDR, CMN_BLK_SIZE); -+ cmn_pll_src_base = ioremap(CMN_BLK_PLL_SRC_ADDR, CMN_BLK_SIZE); - if (!cmn_pll_src_base) { - SSDK_ERROR("Failed to map cmn pll source address!\n"); - return; -@@ -766,7 +766,7 @@ static void ssdk_cmnblk_init(enum cmnblk - void __iomem *gcc_pll_base = NULL; - a_uint32_t reg_val; - -- gcc_pll_base = ioremap_nocache(CMN_BLK_ADDR, CMN_BLK_SIZE); -+ gcc_pll_base = ioremap(CMN_BLK_ADDR, CMN_BLK_SIZE); - if (!gcc_pll_base) { - SSDK_ERROR("Failed to map gcc pll address!\n"); - return; ---- a/src/init/ssdk_init.c -+++ b/src/init/ssdk_init.c -@@ -2770,7 +2770,7 @@ static int ssdk_dess_mac_mode_init(a_uin - (a_uint8_t *)®_value, 4); - mdelay(10); - /*softreset psgmii, fixme*/ -- gcc_addr = ioremap_nocache(0x1812000, 0x200); -+ gcc_addr = ioremap(0x1812000, 0x200); - if (!gcc_addr) { - SSDK_ERROR("gcc map fail!\n"); - return 0; ---- a/src/init/ssdk_plat.c -+++ b/src/init/ssdk_plat.c -@@ -1312,7 +1312,7 @@ ssdk_plat_init(ssdk_init_cfg *cfg, a_uin - reg_mode = ssdk_uniphy_reg_access_mode_get(dev_id); - if(reg_mode == HSL_REG_LOCAL_BUS) { - ssdk_uniphy_reg_map_info_get(dev_id, &map); -- qca_phy_priv_global[dev_id]->uniphy_hw_addr = ioremap_nocache(map.base_addr, -+ qca_phy_priv_global[dev_id]->uniphy_hw_addr = ioremap(map.base_addr, - map.size); - if (!qca_phy_priv_global[dev_id]->uniphy_hw_addr) { - SSDK_ERROR("%s ioremap fail.", __func__); -@@ -1327,7 +1327,7 @@ ssdk_plat_init(ssdk_init_cfg *cfg, a_uin - reg_mode = ssdk_switch_reg_access_mode_get(dev_id); - if(reg_mode == HSL_REG_LOCAL_BUS) { - ssdk_switch_reg_map_info_get(dev_id, &map); -- qca_phy_priv_global[dev_id]->hw_addr = ioremap_nocache(map.base_addr, -+ qca_phy_priv_global[dev_id]->hw_addr = ioremap(map.base_addr, - map.size); - if (!qca_phy_priv_global[dev_id]->hw_addr) { - SSDK_ERROR("%s ioremap fail.", __func__); -@@ -1358,7 +1358,7 @@ ssdk_plat_init(ssdk_init_cfg *cfg, a_uin - return -1; - } - -- qca_phy_priv_global[dev_id]->psgmii_hw_addr = ioremap_nocache(map.base_addr, -+ qca_phy_priv_global[dev_id]->psgmii_hw_addr = ioremap(map.base_addr, - map.size); - if (!qca_phy_priv_global[dev_id]->psgmii_hw_addr) { - SSDK_ERROR("%s ioremap fail.", __func__); diff --git a/qca/qca-ssdk/patches/0004-platform-use-of_mdio_find_bus-to-get-MDIO-bus.patch b/qca/qca-ssdk/patches/0004-platform-use-of_mdio_find_bus-to-get-MDIO-bus.patch deleted file mode 100644 index 3bcbcccf6..000000000 --- a/qca/qca-ssdk/patches/0004-platform-use-of_mdio_find_bus-to-get-MDIO-bus.patch +++ /dev/null @@ -1,40 +0,0 @@ -From b6190ca46287d01a895c7cc14de30410c09ff1b8 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Wed, 12 May 2021 17:15:46 +0200 -Subject: [PATCH] SSDK: platform: use of_mdio_find_bus() to get MDIO bus - -Kernel has a generic of_mdio_find_bus() which can get the appropriate -MDIO bus based on the DT node. -So, drop the getting MDIO from platform data, which no longer works -in 5.4 and later and use of_mdio_find_bus(). - -Signed-off-by: Baruch Siach -Signed-off-by: Robert Marko ---- - src/init/ssdk_plat.c | 8 +------- - 1 file changed, 1 insertion(+), 7 deletions(-) - ---- a/src/init/ssdk_plat.c -+++ b/src/init/ssdk_plat.c -@@ -551,7 +551,6 @@ static int miibus_get(a_uint32_t dev_id) - struct device_node *mdio_node = NULL; - struct device_node *switch_node = NULL; - struct platform_device *mdio_plat = NULL; -- struct ipq40xx_mdio_data *mdio_data = NULL; - struct qca_phy_priv *priv; - hsl_reg_mode reg_mode = HSL_REG_LOCAL_BUS; - priv = qca_phy_priv_global[dev_id]; -@@ -584,12 +583,7 @@ static int miibus_get(a_uint32_t dev_id) - - if(reg_mode == HSL_REG_LOCAL_BUS) - { -- mdio_data = dev_get_drvdata(&mdio_plat->dev); -- if (!mdio_data) { -- SSDK_ERROR("cannot get mdio_data reference from device data\n"); -- return 1; -- } -- priv->miibus = mdio_data->mii_bus; -+ priv->miibus = of_mdio_find_bus(mdio_node); - } - else - priv->miibus = dev_get_drvdata(&mdio_plat->dev); diff --git a/qca/qca-ssdk/patches/0005-SSDK-dts-fix-of_get_mac_address.patch b/qca/qca-ssdk/patches/0005-SSDK-dts-fix-of_get_mac_address.patch deleted file mode 100644 index 29be93128..000000000 --- a/qca/qca-ssdk/patches/0005-SSDK-dts-fix-of_get_mac_address.patch +++ /dev/null @@ -1,42 +0,0 @@ -From f3a7b93137c1a6a1b8010b86296242178eed5d9e Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Fri, 13 Aug 2021 20:03:21 +0200 -Subject: [PATCH] SSDK: dts: fix of_get_mac_address() - -Recently OpenWrt backported the updated of_get_mac_address() -function which returns and error code instead. - -So, patch the SSDK to use it and fix the compilation error. - -Signed-off-by: Robert Marko ---- - src/init/ssdk_dts.c | 7 ++++--- - 1 file changed, 4 insertions(+), 3 deletions(-) - ---- a/src/init/ssdk_dts.c -+++ b/src/init/ssdk_dts.c -@@ -779,8 +779,9 @@ static void ssdk_dt_parse_intf_mac(void) - { - struct device_node *dp_node = NULL; - a_uint32_t dp = 0; -- a_uint8_t *maddr = NULL; -+ u8 maddr[ETH_ALEN]; - char dp_name[8] = {0}; -+ int ret; - - for (dp = 1; dp <= SSDK_MAX_NR_ETH; dp++) { - snprintf(dp_name, sizeof(dp_name), "dp%d", dp); -@@ -788,11 +789,11 @@ static void ssdk_dt_parse_intf_mac(void) - if (!dp_node) { - continue; - } -- maddr = (a_uint8_t *)of_get_mac_address(dp_node); -+ ret = of_get_mac_address(dp_node, maddr); - #if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0)) - if (maddr && is_valid_ether_addr(maddr)) { - #else -- if (!IS_ERR(maddr) && is_valid_ether_addr(maddr)) { -+ if (!ret && is_valid_ether_addr(maddr)) { - #endif - ssdk_dt_global.num_intf_mac++; - ether_addr_copy(ssdk_dt_global.intf_mac[dp-1].uc, maddr); diff --git a/qca/qca-ssdk/patches/0006-SSDK-config-add-kernel-5.15.patch b/qca/qca-ssdk/patches/0006-SSDK-config-add-kernel-5.15.patch deleted file mode 100644 index a4e1b2782..000000000 --- a/qca/qca-ssdk/patches/0006-SSDK-config-add-kernel-5.15.patch +++ /dev/null @@ -1,56 +0,0 @@ -From 599f19551dc8db3cb396e4c139a73bd72300ebf5 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Fri, 24 Dec 2021 19:39:02 +0100 -Subject: [PATCH] SSDK: config: add kernel 5.15 - -This is purely to identify it and be able to set -flags correctly. - -Signed-off-by: Robert Marko ---- - config | 6 +++++- - make/linux_opt.mk | 4 ++-- - 2 files changed, 7 insertions(+), 3 deletions(-) - ---- a/config -+++ b/config -@@ -26,6 +26,10 @@ ifeq ($(KVER),$(filter 5.10%,$(KVER))) - OS_VER=5_10 - endif - -+ifeq ($(KVER),$(filter 5.15%,$(KVER))) -+OS_VER=5_15 -+endif -+ - ifeq ($(KVER), 3.4.0) - OS_VER=3_4 - endif -@@ -127,7 +131,7 @@ endif - endif - - ifeq ($(ARCH), arm64) -- ifeq ($(KVER),$(filter 4.1% 4.4% 4.9% 5.4% 5.10%,$(KVER))) -+ ifeq ($(KVER),$(filter 4.1% 4.4% 4.9% 5.4% 5.10% 5.15%,$(KVER))) - CPU_CFLAG= -DMODULE -Os -pipe -march=armv8-a -mcpu=cortex-a53+crypto -fno-caller-saves -fno-strict-aliasing -Werror -fno-common -Wno-format-security -Wno-pointer-sign -Wno-unused-but-set-variable -Wno-error=unused-result -mcmodel=large - endif - endif ---- a/make/linux_opt.mk -+++ b/make/linux_opt.mk -@@ -388,7 +388,7 @@ ifeq (KSLIB, $(MODULE_TYPE)) - KASAN_SHADOW_SCALE_SHIFT := 3 - endif - -- ifeq ($(OS_VER),$(filter 5_4 5_10, $(OS_VER))) -+ ifeq ($(OS_VER),$(filter 5_4 5_10 5_15, $(OS_VER))) - ifeq ($(ARCH), arm64) - KASAN_OPTION += -DKASAN_SHADOW_SCALE_SHIFT=$(KASAN_SHADOW_SCALE_SHIFT) - endif -@@ -419,7 +419,7 @@ ifeq (KSLIB, $(MODULE_TYPE)) - - endif - -- ifeq ($(OS_VER),$(filter 4_4 5_4 5_10, $(OS_VER))) -+ ifeq ($(OS_VER),$(filter 4_4 5_4 5_10 5_15, $(OS_VER))) - MODULE_CFLAG += -DKVER34 - MODULE_CFLAG += -DKVER32 - MODULE_CFLAG += -DLNX26_22 diff --git a/qca/qca-ssdk/patches/0007-qca8081-convert-to-5.11-IRQ-model.patch b/qca/qca-ssdk/patches/0007-qca8081-convert-to-5.11-IRQ-model.patch deleted file mode 100644 index b0c272b17..000000000 --- a/qca/qca-ssdk/patches/0007-qca8081-convert-to-5.11-IRQ-model.patch +++ /dev/null @@ -1,83 +0,0 @@ -From 25ff0ae02accadd7b05f1dae788505f833d5c019 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Fri, 24 Dec 2021 20:02:32 +0100 -Subject: [PATCH] qca8081: convert to 5.11 IRQ model - -Kernel 5.11 introduced new IRQ handling model for PHY-s, -so provide those if 5.11 or later is used. - -Signed-off-by: Robert Marko ---- - src/hsl/phy/qca808x.c | 46 +++++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 46 insertions(+) - ---- a/src/hsl/phy/qca808x.c -+++ b/src/hsl/phy/qca808x.c -@@ -238,6 +238,7 @@ static int qca808x_config_intr(struct ph - return err; - } - -+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 11, 0)) - static int qca808x_ack_interrupt(struct phy_device *phydev) - { - int err; -@@ -257,6 +258,47 @@ static int qca808x_ack_interrupt(struct - - return (err < 0) ? err : 0; - } -+#endif -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(5, 11, 0)) -+static irqreturn_t qca808x_handle_interrupt(struct phy_device *phydev) -+{ -+ a_uint16_t irq_status, int_enabled; -+ a_uint32_t dev_id = 0, phy_id = 0; -+ qca808x_priv *priv = phydev->priv; -+ const struct qca808x_phy_info *pdata = priv->phy_info; -+ -+ if (!pdata) { -+ return SW_FAIL; -+ } -+ -+ dev_id = pdata->dev_id; -+ phy_id = pdata->phy_addr; -+ -+ irq_status = qca808x_phy_reg_read(dev_id, phy_id, -+ QCA808X_PHY_INTR_STATUS); -+ if (irq_status < 0) { -+ phy_error(phydev); -+ return IRQ_NONE; -+ } -+ -+ /* Read the current enabled interrupts */ -+ int_enabled = qca808x_phy_reg_read(dev_id, phy_id, -+ QCA808X_PHY_INTR_MASK); -+ if (int_enabled < 0) { -+ phy_error(phydev); -+ return IRQ_NONE; -+ } -+ -+ /* See if this was one of our enabled interrupts */ -+ if (!(irq_status & int_enabled)) -+ return IRQ_NONE; -+ -+ phy_trigger_machine(phydev); -+ -+ return IRQ_HANDLED; -+} -+#endif - - /* switch linux negtiation capability to fal avariable */ - #if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0)) -@@ -559,7 +601,11 @@ struct phy_driver qca808x_phy_driver = { - .config_intr = qca808x_config_intr, - .config_aneg = qca808x_config_aneg, - .aneg_done = qca808x_aneg_done, -+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 11, 0)) - .ack_interrupt = qca808x_ack_interrupt, -+#else -+ .handle_interrupt = qca808x_handle_interrupt, -+#endif - .read_status = qca808x_read_status, - .suspend = qca808x_suspend, - .resume = qca808x_resume, diff --git a/qca/qca-ssdk/patches/0008-qca807x-add-a-LED-quirk-for-Xiaomi-AX9000.patch b/qca/qca-ssdk/patches/0008-qca807x-add-a-LED-quirk-for-Xiaomi-AX9000.patch deleted file mode 100644 index 76f71be46..000000000 --- a/qca/qca-ssdk/patches/0008-qca807x-add-a-LED-quirk-for-Xiaomi-AX9000.patch +++ /dev/null @@ -1,74 +0,0 @@ -From 86624624c2b593c57999780a3838e6a9fe40b30c Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Tue, 11 Jan 2022 00:28:42 +0100 -Subject: [PATCH] qca807x: add a LED quirk for Xiaomi AX9000 - -Xiaomi AX9000 has a single LED for each of 4 gigabit ethernet ports that -are connected to QCA8075, and that LED is connected to the 100M LED pin. - -So, by default it will only work when in 10 or 100Mbit mode, this is quite -annoying and makes no sense(If they have connected it to the 1000Mbit LED -pin then it would have worked for 10/100 by default as well). - -So, to solve this add a check for system compatible as we cant parse if -from DTS in any other way and set the 100M LED to blink on 1000Base-T -as well. - -Signed-off-by: Robert Marko ---- - include/hsl/phy/malibu_phy.h | 2 ++ - src/hsl/phy/malibu_phy.c | 11 +++++++++++ - 2 files changed, 13 insertions(+) - -diff --git a/include/hsl/phy/malibu_phy.h b/include/hsl/phy/malibu_phy.h -index b7354041..ec7a0621 100755 ---- a/include/hsl/phy/malibu_phy.h -+++ b/include/hsl/phy/malibu_phy.h -@@ -94,6 +94,7 @@ extern "C" - #define MALIBU_DAC_CTRL_MASK 0x380 - #define MALIBU_DAC_CTRL_VALUE 0x280 - #define MALIBU_LED_1000_CTRL1_100_10_MASK 0x30 -+#define MALIBU_LED_100_CTRL1_1000_MASK 0x40 - - #define MALIBU_PHY_EEE_ADV_100M 0x0002 - #define MALIBU_PHY_EEE_ADV_1000M 0x0004 -@@ -118,6 +119,7 @@ extern "C" - #define MALIBU_PHY_MMD7_EGRESS_COUNTER_HIGH 0x802d - #define MALIBU_PHY_MMD7_EGRESS_COUNTER_LOW 0x802e - #define MALIBU_PHY_MMD7_EGRESS_ERROR_COUNTER 0x802f -+#define MALIBU_PHY_MMD7_LED_100_CTRL1 0x8074 - #define MALIBU_PHY_MMD7_LED_1000_CTRL1 0x8076 - - -diff --git a/src/hsl/phy/malibu_phy.c b/src/hsl/phy/malibu_phy.c -index 1f4dba15..2bef9fa3 100644 ---- a/src/hsl/phy/malibu_phy.c -+++ b/src/hsl/phy/malibu_phy.c -@@ -12,6 +12,8 @@ - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -+#include -+ - #include "sw.h" - #include "fal_port_ctrl.h" - #include "hsl_api.h" -@@ -2726,6 +2728,15 @@ malibu_phy_hw_init(a_uint32_t dev_id, a_uint32_t port_bmp) - led_status |= MALIBU_LED_1000_CTRL1_100_10_MASK; - malibu_phy_mmd_write(dev_id, phy_addr, MALIBU_PHY_MMD7_NUM, - MALIBU_PHY_MMD7_LED_1000_CTRL1, led_status); -+ if (of_machine_is_compatible("xiaomi,ax9000")) { -+ /* add 1000M link LED behavior for Xiaomi AX9000 */ -+ led_status = malibu_phy_mmd_read(dev_id, phy_addr, MALIBU_PHY_MMD7_NUM, -+ MALIBU_PHY_MMD7_LED_100_CTRL1); -+ led_status &= ~MALIBU_LED_100_CTRL1_1000_MASK; -+ led_status |= MALIBU_LED_100_CTRL1_1000_MASK; -+ malibu_phy_mmd_write(dev_id, phy_addr, MALIBU_PHY_MMD7_NUM, -+ MALIBU_PHY_MMD7_LED_100_CTRL1, led_status); -+ } - /*disable Extended next page*/ - phy_data = malibu_phy_reg_read(dev_id, phy_addr, MALIBU_AUTONEG_ADVERT); - phy_data &= ~MALIBU_EXTENDED_NEXT_PAGE_EN; --- -2.34.1 - diff --git a/qca/qca-ssdk/patches/0009-qca807x-add-a-LED-quirk-for-Xiaomi-AX3600.patch b/qca/qca-ssdk/patches/0009-qca807x-add-a-LED-quirk-for-Xiaomi-AX3600.patch deleted file mode 100644 index c31ea6da9..000000000 --- a/qca/qca-ssdk/patches/0009-qca807x-add-a-LED-quirk-for-Xiaomi-AX3600.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 913514b9177e77836f2c8d61fc498b54f54c6775 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Wed, 26 Jan 2022 14:47:33 +0100 -Subject: [PATCH] qca807x: add a LED quirk for Xiaomi AX3600 - -AX3600 requires the same LED quirk so that PHY LED-s will blink even -once Linux resets the PHY. - -So, just check for its compatible. - -Signed-off-by: Robert Marko ---- - src/hsl/phy/malibu_phy.c | 5 +++-- - 1 file changed, 3 insertions(+), 2 deletions(-) - ---- a/src/hsl/phy/malibu_phy.c -+++ b/src/hsl/phy/malibu_phy.c -@@ -2728,8 +2728,9 @@ malibu_phy_hw_init(a_uint32_t dev_id, a_ - led_status |= MALIBU_LED_1000_CTRL1_100_10_MASK; - malibu_phy_mmd_write(dev_id, phy_addr, MALIBU_PHY_MMD7_NUM, - MALIBU_PHY_MMD7_LED_1000_CTRL1, led_status); -- if (of_machine_is_compatible("xiaomi,ax9000")) { -- /* add 1000M link LED behavior for Xiaomi AX9000 */ -+ /* add 1000M link LED behavior for Xiaomi boards */ -+ if (of_machine_is_compatible("xiaomi,ax9000") || -+ of_machine_is_compatible("xiaomi,ax3600")) { - led_status = malibu_phy_mmd_read(dev_id, phy_addr, MALIBU_PHY_MMD7_NUM, - MALIBU_PHY_MMD7_LED_100_CTRL1); - led_status &= ~MALIBU_LED_100_CTRL1_1000_MASK; diff --git a/qca/qca-ssdk/patches/0012-include-fix-compilation-error-for-parse_uci_option.patch b/qca/qca-ssdk/patches/0012-include-fix-compilation-error-for-parse_uci_option.patch deleted file mode 100644 index 01b8deda9..000000000 --- a/qca/qca-ssdk/patches/0012-include-fix-compilation-error-for-parse_uci_option.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 8e3500df074625b3eb3a8ed4e8e0b1b116f13d0c Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Sat, 7 May 2022 19:03:55 +0200 -Subject: [PATCH] include: fix compilation error for parse_uci_option - -Fix missing include for parse_uci_option - -Signed-off-by: Ansuel Smith ---- - include/ref/ref_uci.h | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/include/ref/ref_uci.h b/include/ref/ref_uci.h -index a42ea153..0906c5ba 100755 ---- a/include/ref/ref_uci.h -+++ b/include/ref/ref_uci.h -@@ -19,6 +19,7 @@ - extern "C" { - #endif /* __cplusplus */ - -+#include - - #if defined(IN_SWCONFIG) - int --- -2.34.1 - From 8f04a5c8bfc9563d9f0f006c9b43a55a29163c87 Mon Sep 17 00:00:00 2001 From: suyuan <175338101@qq.com> Date: Tue, 13 Sep 2022 14:53:54 +0800 Subject: [PATCH 17/19] Revert "Revert "add qca"" This reverts commit a48d42f30470a2e1bebcf99d8ebaf8b9cd8b8173. --- qca/aq-fw-download/Makefile | 26 + qca/aq-fw-download/src/Makefile | 14 + qca/aq-fw-download/src/include/AQ_API.h | 246 + .../src/include/AQ_PhyInterface.h | 171 + .../src/include/AQ_PlatformRoutines.h | 71 + qca/aq-fw-download/src/include/AQ_RegMacro.h | 323 + .../src/include/AQ_ReturnCodes.h | 113 + qca/aq-fw-download/src/include/AQ_User.h | 97 + .../APPIA/AQ_APPIA_Global_registers.h | 5581 +++++++ .../APPIA/AQ_APPIA_Global_registers_Defines.h | 2134 +++ .../AQ_APPIA_Global_registers_reversed.h | 5581 +++++++ .../include/registerMap/AQ_RegGroupMaxSizes.h | 387 + .../src/include/registerMap/AQ_RegMaps.h | 69 + .../registerMap/HHD/AQ_HHD_Global_registers.h | 12123 ++++++++++++++++ .../HHD/AQ_HHD_Global_registers_Defines.h | 4413 ++++++ .../HHD/AQ_HHD_Global_registers_reversed.h | 12123 ++++++++++++++++ qca/aq-fw-download/src/mdioBootLoadCLD.c | 193 + qca/aq-fw-download/src/src/AQ_API.c | 1021 ++ qca/aq-fw-download/src/src/AQ_PhyInterface.c | 141 + qca/nss-eip-firmware/Makefile | 34 + qca/nss-eip-firmware/src/.gitkeep | 0 qca/nss-firmware/Makefile | 72 + qca/qca-nss-cfi/Makefile | 71 + .../patches/100-remove-noise-logs.patch | 30 + qca/qca-nss-clients/Makefile | 102 + qca/qca-nss-clients/files/qca-nss-ipsec | 214 + qca/qca-nss-clients/files/qca-nss-mirred.init | 28 + qca/qca-nss-clients/files/qca-nss-ovpn.init | 69 + qca/qca-nss-crypto/Makefile | 72 + ...1-nss-crypto-fix-SHA1-header-include.patch | 32 + ...replace-ioremap_nocache-with-ioremap.patch | 69 + ...rypto-fix-SHA-header-include-in-5.15.patch | 51 + qca/qca-nss-dp/Makefile | 56 + ...port-newer-kernels-time-stamping-API.patch | 44 + ...-phy-mode-code-compatible-with-newer.patch | 48 + ...03-Drop-_nocache-variants-of-ioremap.patch | 48 + .../0004-EDMA-Fix-NAPI-packet-counting.patch | 31 + ...-Use-NAPI_POLL_WEIGHT-as-NAPI-weight.patch | 41 + .../0006-NSS-DP-fix-of_get_mac_address.patch | 46 + ...07-NSS-DP-implement-ethernet-IOCTL-s.patch | 29 + ...dev-remove-the-transaction-structure.patch | 48 + ...09-switchdev-use-new-switchdev-flags.patch | 51 + .../0010-switchdev-fix-FDB-roaming.patch | 110 + ...fusing-printing-of-registered-netdev.patch | 48 + ...syn-xgmac-silence-debug-log-on-probe.patch | 28 + ...a-phy-handle-property-to-connect-to-.patch | 189 + ...p-edma-v1-switch-to-napi_gro_receive.patch | 46 + qca/qca-nss-drv/Makefile | 129 + qca/qca-nss-drv/files/qca-nss-drv.conf | 6 + qca/qca-nss-drv/files/qca-nss-drv.debug | 26 + qca/qca-nss-drv/files/qca-nss-drv.hotplug | 70 + qca/qca-nss-drv/files/qca-nss-drv.init | 50 + qca/qca-nss-drv/files/qca-nss-drv.sysctl | 4 + ...ore-add-5.10-kernel-to-version-check.patch | 25 + ...replace-ioremap_nocache-with-ioremap.patch | 181 + ...0003-DMA-Fix-NULL-pointer-exceptions.patch | 49 + ...-rework-NSS_CORE_DMA_CACHE_MAINT-ops.patch | 573 + ...-nss-drv-add-support-for-kernel-5.15.patch | 70 + ...dard-skb_skip_tc_classify-instead-of.patch | 30 + ...Makefile-modularize-driver-even-more.patch | 172 + qca/qca-nss-ecm/Makefile | 97 + qca/qca-nss-ecm/files/ecm_dump.sh | 95 + qca/qca-nss-ecm/files/on-demand-down | 6 + qca/qca-nss-ecm/files/qca-nss-ecm.defaults | 28 + qca/qca-nss-ecm/files/qca-nss-ecm.firewall | 18 + qca/qca-nss-ecm/files/qca-nss-ecm.init | 142 + qca/qca-nss-ecm/files/qca-nss-ecm.sysctl | 2 + qca/qca-nss-ecm/files/qca-nss-ecm.uci | 2 + ...de-componentize-the-module-even-more.patch | 335 + .../patches/100-kernel-5.10-support.patch | 831 ++ .../patches/200-resolve-high-load.patch | 61 + .../203-rework-nfct-notification.patch | 25 + .../patches/204-More-compile-fixes.patch | 49 + .../patches/205-resolve-high-load.patch | 55 + qca/qca-ssdk-shell/Makefile | 48 + qca/qca-ssdk/Makefile | 91 + qca/qca-ssdk/files/qca-ssdk | 206 + .../0001-SSDK-config-add-kernel-5.10.patch | 56 + ...replace-ioremap_nocache-with-ioremap.patch | 102 + ...use-of_mdio_find_bus-to-get-MDIO-bus.patch | 40 + ...0005-SSDK-dts-fix-of_get_mac_address.patch | 42 + .../0006-SSDK-config-add-kernel-5.15.patch | 56 + ...07-qca8081-convert-to-5.11-IRQ-model.patch | 83 + ...7x-add-a-LED-quirk-for-Xiaomi-AX9000.patch | 74 + ...7x-add-a-LED-quirk-for-Xiaomi-AX3600.patch | 29 + ...mpilation-error-for-parse_uci_option.patch | 27 + 86 files changed, 50519 insertions(+) create mode 100644 qca/aq-fw-download/Makefile create mode 100644 qca/aq-fw-download/src/Makefile create mode 100644 qca/aq-fw-download/src/include/AQ_API.h create mode 100644 qca/aq-fw-download/src/include/AQ_PhyInterface.h create mode 100644 qca/aq-fw-download/src/include/AQ_PlatformRoutines.h create mode 100644 qca/aq-fw-download/src/include/AQ_RegMacro.h create mode 100644 qca/aq-fw-download/src/include/AQ_ReturnCodes.h create mode 100644 qca/aq-fw-download/src/include/AQ_User.h create mode 100644 qca/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers.h create mode 100644 qca/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers_Defines.h create mode 100644 qca/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers_reversed.h create mode 100644 qca/aq-fw-download/src/include/registerMap/AQ_RegGroupMaxSizes.h create mode 100644 qca/aq-fw-download/src/include/registerMap/AQ_RegMaps.h create mode 100644 qca/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers.h create mode 100644 qca/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers_Defines.h create mode 100644 qca/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers_reversed.h create mode 100644 qca/aq-fw-download/src/mdioBootLoadCLD.c create mode 100644 qca/aq-fw-download/src/src/AQ_API.c create mode 100644 qca/aq-fw-download/src/src/AQ_PhyInterface.c create mode 100644 qca/nss-eip-firmware/Makefile create mode 100644 qca/nss-eip-firmware/src/.gitkeep create mode 100644 qca/nss-firmware/Makefile create mode 100644 qca/qca-nss-cfi/Makefile create mode 100644 qca/qca-nss-cfi/patches/100-remove-noise-logs.patch create mode 100644 qca/qca-nss-clients/Makefile create mode 100644 qca/qca-nss-clients/files/qca-nss-ipsec create mode 100644 qca/qca-nss-clients/files/qca-nss-mirred.init create mode 100644 qca/qca-nss-clients/files/qca-nss-ovpn.init create mode 100644 qca/qca-nss-crypto/Makefile create mode 100644 qca/qca-nss-crypto/patches/0001-nss-crypto-fix-SHA1-header-include.patch create mode 100644 qca/qca-nss-crypto/patches/0002-nss-crypto-replace-ioremap_nocache-with-ioremap.patch create mode 100644 qca/qca-nss-crypto/patches/0003-nss-crypto-fix-SHA-header-include-in-5.15.patch create mode 100644 qca/qca-nss-dp/Makefile create mode 100644 qca/qca-nss-dp/patches/0001-edma_tx_rx-support-newer-kernels-time-stamping-API.patch create mode 100644 qca/qca-nss-dp/patches/0002-nss_dp_main-make-phy-mode-code-compatible-with-newer.patch create mode 100644 qca/qca-nss-dp/patches/0003-Drop-_nocache-variants-of-ioremap.patch create mode 100644 qca/qca-nss-dp/patches/0004-EDMA-Fix-NAPI-packet-counting.patch create mode 100644 qca/qca-nss-dp/patches/0005-EDMA-Use-NAPI_POLL_WEIGHT-as-NAPI-weight.patch create mode 100644 qca/qca-nss-dp/patches/0006-NSS-DP-fix-of_get_mac_address.patch create mode 100644 qca/qca-nss-dp/patches/0007-NSS-DP-implement-ethernet-IOCTL-s.patch create mode 100644 qca/qca-nss-dp/patches/0008-switchdev-remove-the-transaction-structure.patch create mode 100644 qca/qca-nss-dp/patches/0009-switchdev-use-new-switchdev-flags.patch create mode 100644 qca/qca-nss-dp/patches/0010-switchdev-fix-FDB-roaming.patch create mode 100644 qca/qca-nss-dp/patches/0011-treewide-fix-confusing-printing-of-registered-netdev.patch create mode 100644 qca/qca-nss-dp/patches/0012-gmac-syn-xgmac-silence-debug-log-on-probe.patch create mode 100644 qca/qca-nss-dp/patches/0013-nss_dp_main-Use-a-phy-handle-property-to-connect-to-.patch create mode 100644 qca/qca-nss-dp/patches/0014-nss-dp-edma-v1-switch-to-napi_gro_receive.patch create mode 100644 qca/qca-nss-drv/Makefile create mode 100644 qca/qca-nss-drv/files/qca-nss-drv.conf create mode 100644 qca/qca-nss-drv/files/qca-nss-drv.debug create mode 100644 qca/qca-nss-drv/files/qca-nss-drv.hotplug create mode 100644 qca/qca-nss-drv/files/qca-nss-drv.init create mode 100644 qca/qca-nss-drv/files/qca-nss-drv.sysctl create mode 100644 qca/qca-nss-drv/patches/0001-core-add-5.10-kernel-to-version-check.patch create mode 100644 qca/qca-nss-drv/patches/0002-nss-drv-replace-ioremap_nocache-with-ioremap.patch create mode 100644 qca/qca-nss-drv/patches/0003-DMA-Fix-NULL-pointer-exceptions.patch create mode 100644 qca/qca-nss-drv/patches/0004-nss-drv-rework-NSS_CORE_DMA_CACHE_MAINT-ops.patch create mode 100644 qca/qca-nss-drv/patches/0005-nss-drv-add-support-for-kernel-5.15.patch create mode 100644 qca/qca-nss-drv/patches/0005-nss-drv-use-standard-skb_skip_tc_classify-instead-of.patch create mode 100644 qca/qca-nss-drv/patches/0008-Makefile-modularize-driver-even-more.patch create mode 100644 qca/qca-nss-ecm/Makefile create mode 100644 qca/qca-nss-ecm/files/ecm_dump.sh create mode 100644 qca/qca-nss-ecm/files/on-demand-down create mode 100644 qca/qca-nss-ecm/files/qca-nss-ecm.defaults create mode 100644 qca/qca-nss-ecm/files/qca-nss-ecm.firewall create mode 100644 qca/qca-nss-ecm/files/qca-nss-ecm.init create mode 100644 qca/qca-nss-ecm/files/qca-nss-ecm.sysctl create mode 100644 qca/qca-nss-ecm/files/qca-nss-ecm.uci create mode 100644 qca/qca-nss-ecm/patches/001-treewide-componentize-the-module-even-more.patch create mode 100644 qca/qca-nss-ecm/patches/100-kernel-5.10-support.patch create mode 100644 qca/qca-nss-ecm/patches/200-resolve-high-load.patch create mode 100644 qca/qca-nss-ecm/patches/203-rework-nfct-notification.patch create mode 100644 qca/qca-nss-ecm/patches/204-More-compile-fixes.patch create mode 100644 qca/qca-nss-ecm/patches/205-resolve-high-load.patch create mode 100644 qca/qca-ssdk-shell/Makefile create mode 100644 qca/qca-ssdk/Makefile create mode 100644 qca/qca-ssdk/files/qca-ssdk create mode 100644 qca/qca-ssdk/patches/0001-SSDK-config-add-kernel-5.10.patch create mode 100644 qca/qca-ssdk/patches/0002-SSDK-replace-ioremap_nocache-with-ioremap.patch create mode 100644 qca/qca-ssdk/patches/0004-platform-use-of_mdio_find_bus-to-get-MDIO-bus.patch create mode 100644 qca/qca-ssdk/patches/0005-SSDK-dts-fix-of_get_mac_address.patch create mode 100644 qca/qca-ssdk/patches/0006-SSDK-config-add-kernel-5.15.patch create mode 100644 qca/qca-ssdk/patches/0007-qca8081-convert-to-5.11-IRQ-model.patch create mode 100644 qca/qca-ssdk/patches/0008-qca807x-add-a-LED-quirk-for-Xiaomi-AX9000.patch create mode 100644 qca/qca-ssdk/patches/0009-qca807x-add-a-LED-quirk-for-Xiaomi-AX3600.patch create mode 100644 qca/qca-ssdk/patches/0012-include-fix-compilation-error-for-parse_uci_option.patch diff --git a/qca/aq-fw-download/Makefile b/qca/aq-fw-download/Makefile new file mode 100644 index 000000000..97270688b --- /dev/null +++ b/qca/aq-fw-download/Makefile @@ -0,0 +1,26 @@ +include $(TOPDIR)/rules.mk + +PKG_NAME:=aq-fw-download +PKG_RELEASE:=$(AUTORELEASE) + +PKG_FLAGS:=nonshared + +include $(INCLUDE_DIR)/package.mk + +define Package/aq-fw-download + SECTION:=firmware + CATEGORY:=Firmware + DEPENDS:=@TARGET_ipq807x + TITLE:=Aquantia FW downloader utitlity +endef + +define Package/aq-fw-download/description + Aquantia FW downloader utitlity +endef + +define Package/aq-fw-download/install + $(INSTALL_DIR) $(1)/sbin + $(INSTALL_BIN) $(PKG_BUILD_DIR)/aq-fw-download $(1)/sbin/aq-fw-download +endef + +$(eval $(call BuildPackage,aq-fw-download)) diff --git a/qca/aq-fw-download/src/Makefile b/qca/aq-fw-download/src/Makefile new file mode 100644 index 000000000..dc141be0e --- /dev/null +++ b/qca/aq-fw-download/src/Makefile @@ -0,0 +1,14 @@ +ifndef CFLAGS +CFLAGS = -O2 -g +endif +INCLUDES=-Iinclude -Iinclude/registerMap \ + -Iinclude/registerMap/APPIA \ + -Iinclude/registerMap/HHD + +all: aq-fw-download + +%.o: %.c + $(CC) $(INCLUDES) $(CFLAGS) -c -o $@ $^ + +aq-fw-download: mdioBootLoadCLD.o src/AQ_PhyInterface.o src/AQ_API.o + $(CC) $(LDFLAGS) -o $@ $^ $(LIBS) diff --git a/qca/aq-fw-download/src/include/AQ_API.h b/qca/aq-fw-download/src/include/AQ_API.h new file mode 100644 index 000000000..9a0b4c20a --- /dev/null +++ b/qca/aq-fw-download/src/include/AQ_API.h @@ -0,0 +1,246 @@ +/* +* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +*/ + +/*! \file + This file contains the AQ_API function and datatype declarations. */ + + +#ifndef AQ_API_TOKEN +#define AQ_API_TOKEN + +#include + +#include "AQ_User.h" +#include "AQ_ReturnCodes.h" + +/******************************************************************* + General +*******************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/*! This typedef defines the bool datatype which takes the values +true and false.*/ +typedef enum {False = 0, True = 1} AQ_boolean; + + +/*@}*/ + + +/******************************************************************* + Device Identity +*******************************************************************/ + +/*! \defgroup deviceIdentity Device Identity +All AQ_API functions accept a parameter identifying the target PHY that +should be acted upon. */ +/*@{*/ + + +/*! This enumeration is used to describe the different types of + Aquantia PHY.*/ +typedef enum +{ + /*! 1/2/4-port package, 40nm architechture.*/ + AQ_DEVICE_APPIA, + /*! 1/2/4-port package, 28nm architechture.*/ + AQ_DEVICE_HHD +} AQ_API_Device; + +/*! This structure is used to specify a particular Aquantia PHY port + within the system.*/ +typedef struct +{ + /*! The type of Aquantia PHY*/ + AQ_API_Device device; + /*! Uniquely identifies the port within the system. AQ_Port must be + defined to whatever data type is suitable for the platform. + AQ_API functions will never do anything with PHY_ID other than + pass it down to the platform's PHY register read/write + functions.*/ + AQ_Port PHY_ID; +} AQ_API_Port; + +/*@}*/ + + +/*! This function boot-loads the instruction and data memory (IRAM and + DRAM) of a set of Aquantia PHYs from a .cld format image file (the + same image file used to burn the FLASH). During boot-load of each + Aquantia PHY, the processor is halted, and after programming is + complete the processor is released. Note that calling this + function leaves the daisy-chain disabled to prevent RAM over- + write. To exit MDIO boot-load mode, use the function + AQ_API_EnableDaisyChain. + Unlike most of the other functions in this API, this function can + operate on a group of PHYs simultaneously. This is referred to as + gang-loading. To facilitate this, this function takes as + parameters 3 parallel arrays: PHY_IDs, provisioningAddresses, and + resultCodes. The length of these arrays must be identical, and is + specified by the num_PHY_IDs parameter. + In order to check the integrity of the boot-load operation, a + CRC-16 value is calculated over the IRAM and DRAM. After the image + has been loaded, this value is directly compared against each + PHY's Mailbox CRC-16 in 1E.0201. + The value of register 1E.C441 must be the same for all the boot- + loaded PHYs. This will be checked before the boot-load is + performed, and if a non-uniform value is read from any of the + PHYs, the function will fail before any writes are performed. + A separate result code is returned for each of the boot-loaded + PHYs, in the OUT parameter, resultCodes. + Individual Port Return codes: + AQ_RET_BOOTLOAD_PROVADDR_OOR: The specified provisioning address + was outside of the permitted range. + AQ_RET_BOOTLOAD_NONUNIFORM_REGVALS: The values of the register(s) + that must be uniform across the ports being bootloaded were not + uniform. + AQ_RET_BOOTLOAD_CRC_MISMATCH: The image was completely loaded into + memory, but the after the port exited bootload the running + checksum that was read from the uP memory mailbox was not the + expected value. This indicates that the memory has potentially + been corrupted, and the PHY should be reset before trying the + bootload again. + Overall Return codes (the return value from the function call): + AQ_RET_OK: all ports were successfully bootloaded. + AQ_RET_ERROR: One or more ports were not successfully bootloaded. + */ +AQ_Retcode AQ_API_WriteBootLoadImage +( + /*! An array identifying the target PHY ports.*/ + AQ_API_Port** ports, + /*! The length of the arrays ports, provisioningAddresses, and + resultCodes. These are parallel arrays, and must all be of the + same length.*/ + unsigned int numPorts, + /*! The provisioning addresses of each of the PHYs specified in + ports. This can range from 0 through 47, and is also known as + the daisy-chain address or the hop-count. If the PHYs are + connected to a FLASH using the daisy-chain, this is the distance + from the PHY to the FLASH, and is used to identify customized + provisioning for each PHY from the provisioning data within the + image. Otherwise, it is an arbitrary number. The length of this + array must match the length of ports.*/ + unsigned int* provisioningAddresses, + /*! OUT: The result code indicating success or failure of boot- + loading each of the PHYs specified in ports.*/ + AQ_Retcode* resultCodes, + /*! A pointer to the size of the image (in bytes) that is being + loaded into the Aquantia PHY.*/ + uint32_t* imageSizePointer, + /*! The image being loaded into the Aquantia PHY. This is the same + regardless of whether the target is internal RAM or FLASH.*/ + uint8_t* image, + /*! The 5-bit address to be used during the gang-loading operation. + During the boot-loading process, each of the PHYs specified in + ports will be changed such that they are addressed on the MDIO + bus at gangloadAddress. This allows all the PHYs to be loaded + simultaneously. Before returning, each PHY will be moved back to + its original MDIO address. If ports contains only a single + element, callers will probably want to use the PHY's original + MDIO address for this parameter.*/ + uint8_t gangload_MDIO_address, + /*! The address of the PHYs while in gangload mode. This is + ultimately some combination of the system address and the + gangload MDIO address, specified by gangload_MDIO_address. For + most platforms, gangload_MDIO_address and gangload_PHY_ID should + have the same value.*/ + AQ_API_Port* gangloadPort +); + +/*! This function boot-loads the instruction and data memory (IRAM and + DRAM) of a set of Aquantia PHYs from a .cld format image file (the + same image file used to burn the FLASH), as well as a separately + provided provisioning table image file.The provisioning table + image allows additional provisioning to be provided, beyond what + is built in to the .cld image. If provTableSizePointer or + provTableImage are NULL, this function behaves like + AQ_API_WriteBootLoadImage. + Aside from the additional provisioing table, this function behaves + exactly the same as AQ_API_WriteBootLoadImage. For additional + documentation and information on return codes, refer to + AQ_API_WriteBootLoadImage. + Individual Port Return codes (same as AQ_API_WriteBootLoadImage, + plus): + AQ_RET_BOOTLOAD_PROVTABLE_TOO_LARGE: The supplied provisioning + table image does not fit within the alloted space.*/ +AQ_Retcode AQ_API_WriteBootLoadImageWithProvTable +( + /*! An array identifying the target PHY ports.*/ + AQ_API_Port** ports, + /*! The length of the arrays ports, provisioningAddresses, and + resultCodes. These are parallel arrays, and must all be of the + same length.*/ + unsigned int numPorts, + /*! The provisioning addresses of each of the PHYs specified in + ports. This can range from 0 through 47, and is also known as + the daisy-chain address or the hop-count. If the PHYs are + connected to a FLASH using the daisy-chain, this is the distance + from the PHY to the FLASH, and is used to identify customized + provisioning for each PHY from the provisioning data within the + image. Otherwise, it is an arbitrary number. The length of this + array must match the length of ports.*/ + unsigned int* provisioningAddresses, + /*! OUT: The result code indicating success or failure of boot- + loading each of the PHYs specified in ports.*/ + AQ_Retcode* resultCodes, + /*! A pointer to the size of the image (in bytes) that is being + loaded into the Aquantia PHY.*/ + uint32_t* imageSizePointer, + /*! The image being loaded into the Aquantia PHY. This is the same + regardless of whether the target is internal RAM or FLASH.*/ + uint8_t* image, + /*! The 5-bit address to be used during the gang-loading operation. + During the boot-loading process, each of the PHYs specified in + ports will be changed such that they are addressed on the MDIO + bus at gangloadAddress. This allows all the PHYs to be loaded + simultaneously. Before returning, each PHY will be moved back to + its original MDIO address. If ports contains only a single + element, callers will probably want to use the PHY's original + MDIO address for this parameter.*/ + uint8_t gangload_MDIO_address, + /*! The address of the PHYs while in gangload mode. This is + ultimately some combination of the system address and the + gangload MDIO address, specified by gangload_MDIO_address. For + most platforms, gangload_MDIO_address and gangload_PHY_ID should + have the same value.*/ + AQ_API_Port* gangloadPort, + /*! A pointer to the size of the provTableImage (in bytes) that is + being loaded into the Aquantia PHY.*/ + uint32_t* provTableSizePointer, + /*! The additional provisioning table image being loaded into the + Aquantia PHY.*/ + uint8_t* provTableImage +); + +/*! Calling this function disables boot-loading and enables the daisy- + chain. This would typically be called after using MDIO boot- + loading on a daisy-chain enabled PHY. Re-enabling the daisy-chain + after performing an MDIO bootload will cause the PHY to reboot + from FLASH.*/ +AQ_Retcode AQ_API_EnableDaisyChain +( + /*! The target PHY port.*/ + AQ_API_Port* port +); + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/qca/aq-fw-download/src/include/AQ_PhyInterface.h b/qca/aq-fw-download/src/include/AQ_PhyInterface.h new file mode 100644 index 000000000..66eb817be --- /dev/null +++ b/qca/aq-fw-download/src/include/AQ_PhyInterface.h @@ -0,0 +1,171 @@ +/* AQ_PhyInterface.h */ + +/*********************************************************************** +* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +* +* Description: +* +* Declares the base PHY register read and write functions that are +* called by the API functions. The platform integrator must provide +* the implementation of these routines. +* +***********************************************************************/ + + +/*! \file + * Declares the base PHY register read and write functions that are + * called by the API functions. The platform integrator must provide + * the implementation of these routines. */ + + +#ifndef AQ_PHY_INTERFACE_TOKEN +#define AQ_PHY_INTERFACE_TOKEN + + +#include "AQ_API.h" +#include "AQ_User.h" + + +#ifdef __cplusplus +extern "C" { +#endif + + +/******************************************************************* + MDIO Access Functions +*******************************************************************/ + +/*! \defgroup mdioAccessFunctions MDIO Access Functions +The MDIO access functions are required by the API to access the register space +of each Aquantia PHY deployed in a system. The body of these functions needs to +be written by the system designer, as the method of accessing the PHY will +be unique to the target system. They are designed to be generic read and +write access functions, as the MDIO addressing scheme relies on each +MMD to maintain a 16 bit address pointer that determines the register where +the next read or write is coming from. Consequently, various levels of +optimization of the MDIO interface are possible: from re-writing the MMD +address pointer on every transaction, to storing shadow copies of the MMD +address pointers and only updating the MMD address pointer as necessary. +Thus these functions leave the MDIO optimization to the system engineer. + */ +/*@{*/ + + +/*! Provides generic synchronous PHY register write functionality. It is the + * responsibility of the system designer to provide the specific MDIO address + * pointer updates, etc. in order to accomplish this write operation. + * It will be assumed that the write has been completed by the time this + * function returns.*/ +void AQ_API_MDIO_Write +( + /*! Uniquely identifies the port within the system. AQ_Port must be + * defined to a whatever data type is suitable for the platform.*/ + AQ_Port PHY_ID, + /*! The address of the MMD within the target PHY. */ + unsigned int MMD, + /*! The 16-bit address of the PHY register being written. */ + unsigned int address, + /*! The 16-bits of data to write to the specified PHY register. */ + unsigned int data +); + +/*! Provides generic synchronous PHY register read functionality. It is the + * responsibility of the system designer to provide the specific MDIO address + * pointer updates, etc. in order to accomplish this read operation.*/ +unsigned int AQ_API_MDIO_Read +( + /*! Uniquely identifies the port within the system. AQ_Port must be + * defined to a whatever data type is suitable for the platform.*/ + AQ_Port PHY_ID, + /*! The address of the MMD within the target PHY. */ + unsigned int MMD, + /*! The 16-bit address of the PHY register being read. */ + unsigned int address +); + +#ifdef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE + +/*! Provides generic asynchronous/buffered PHY register write functionality. + * It is the responsibility of the system designer to provide the specific + * MDIO address pointer updates, etc. in order to accomplish this write + * operation. The write need not necessarily have been completed by the time + * this function returns. All register reads and writes to a particular PHY_ID + * that are requested by calling AQ_API_MDIO_BlockWrite or AQ_API_MDIO_BlockRead + * MUST be performed in the order that the calls are made. */ +void AQ_API_MDIO_BlockWrite +( + /*! Uniquely identifies the port within the system. AQ_Port must be + * defined to a whatever data type is suitable for the platform.*/ + AQ_Port PHY_ID, + /*! The address of the MMD within the target PHY. */ + unsigned int MMD, + /*! The 16-bit address of the PHY register being written. */ + unsigned int address, + /*! The 16-bits of data to write to the specified PHY register. */ + unsigned int data +); + +/*! Provides generic asynchronous/buffered PHY register read functionality. + * It is the responsibility of the system designer to provide the specific + * MDIO address pointer updates, etc. in order to accomplish this read + * operation. All register reads and writes to a particular PHY_ID that + * are requested by calling AQ_API_MDIO_BlockWrite or AQ_API_MDIO_BlockRead + * MUST be performed in the order that the calls are made. The register value + * may subsequently be fetched by calling AQ_API_MDIO_BlockOperationExecute.*/ +void AQ_API_MDIO_BlockRead +( + /*! Uniquely identifies the port within the system. AQ_Port must be + * defined to a whatever data type is suitable for the platform.*/ + AQ_Port PHY_ID, + /*! The address of the MMD within the target PHY. */ + unsigned int MMD, + /*! The 16-bit address of the PHY register being read. */ + unsigned int address +); + +/* Retrieve the results of all PHY register reads to PHY_ID previously + * requested via calls to AQ_API_MDIO_BlockRead. The read and write + * operations previously performed by calls to AQ_API_MDIO_BlockRead and + * AQ_API_MDIO_BlockRead must have all been completed by the time this + * function returns, in the order that the calls were performed. The + * return value is an array representing the fetched results of all + * pending calls to AQ_API_MDIO_BlockRead, in the order that the calls + * were performed. Callers should track the number of pending block + * reads to determine the size of the returned array. */ +unsigned int * AQ_API_MDIO_BlockOperationExecute +( + /*! Uniquely identifies the port within the system. AQ_Port must be + * defined to a whatever data type is suitable for the platform.*/ + AQ_Port PHY_ID +); + +/* Returns the maximum number of asynchronous/buffered PHY register + * read/write operations. Callers will call AQ_API_MDIO_BlockOperationExecute + * before issuing additional calls to AQ_API_MDIO_BlockWrite or + * AQ_API_MDIO_BlockRead to avoid a buffer overflow. */ +unsigned int AQ_API_MDIO_MaxBlockOperations +( +); + +#endif + +/*@}*/ + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/qca/aq-fw-download/src/include/AQ_PlatformRoutines.h b/qca/aq-fw-download/src/include/AQ_PlatformRoutines.h new file mode 100644 index 000000000..9a16d6408 --- /dev/null +++ b/qca/aq-fw-download/src/include/AQ_PlatformRoutines.h @@ -0,0 +1,71 @@ +/*AQ_PlatformRoutines.h*/ + +/************************************************************************************ +* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +* +* Description: +* +* Declares the platform interface functions that will be called by AQ_API +* functions. The platform integrator must provide the implementation of +* these functions. +* +************************************************************************************/ + +/*! \file + * Declares the platform interface functions that will be called by AQ_API + * functions. The platform integrator must provide the implementation of + * these functions. */ + + +#ifndef AQ_PHY_PLATFORMROUTINES_TOKEN +#define AQ_PHY_PLATFORMROUTINES_TOKEN + +#include + +#include "AQ_API.h" +#include "AQ_User.h" +#include "AQ_ReturnCodes.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/******************************************************************* + Time Delay +*******************************************************************/ + +/*! \defgroup delay Time Delay + @{ +*/ + +/*! Returns after at least milliseconds have elapsed. This must be implemented + * in a platform-approriate way. AQ_API functions will call this function to + * block for the specified period of time. If necessary, PHY register reads + * may be performed on port to busy-wait. */ +void AQ_API_Wait +( + uint32_t milliseconds, /*!< The delay in milliseconds */ + AQ_API_Port* port /*!< The PHY to use if delay reads are necessary*/ +); + +/*@}*/ + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/qca/aq-fw-download/src/include/AQ_RegMacro.h b/qca/aq-fw-download/src/include/AQ_RegMacro.h new file mode 100644 index 000000000..8dcca522b --- /dev/null +++ b/qca/aq-fw-download/src/include/AQ_RegMacro.h @@ -0,0 +1,323 @@ +/* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +*/ +/*! \file + This file contains macros for accessing the AQ PHYs' registers + using the device-specific register map data structures and definitions. +*/ + +#ifndef AQ_REG_MACRO_TOKEN +#define AQ_REG_MACRO_TOKEN + +#include "AQ_PhyInterface.h" + + +#define AQ_API_ReadRegister(id,reg,wd) AQ_API_ReadRegister_DeviceRestricted(APPIA_HHD,id,reg,wd) + +#define AQ_API_ReadRegister_DeviceRestricted(devices,id,reg,wd) AQ_API_ReadRegister_Devs_ ## devices(id,reg,wd) + +#define AQ_API_ReadRegister_Devs_APPIA(id,reg,wd) \ + ((port->device == AQ_DEVICE_APPIA) ? AQ_API_MDIO_Read (id,reg ## _APPIA_mmdAddress,(reg ## _APPIA_baseRegisterAddress + wd)) : \ + (0)) + +#define AQ_API_ReadRegister_Devs_HHD(id,reg,wd) \ + ((port->device == AQ_DEVICE_HHD) ? AQ_API_MDIO_Read (id,reg ## _HHD_mmdAddress,(reg ## _HHD_baseRegisterAddress + wd)) : \ + (0)) + +#define AQ_API_ReadRegister_Devs_APPIA_HHD(id,reg,wd) \ + ((port->device == AQ_DEVICE_HHD) ? AQ_API_MDIO_Read (id,reg ## _HHD_mmdAddress,(reg ## _HHD_baseRegisterAddress + wd)) : \ + ((port->device == AQ_DEVICE_APPIA) ? AQ_API_MDIO_Read (id,reg ## _APPIA_mmdAddress,(reg ## _APPIA_baseRegisterAddress + wd)) : \ + (0))) + +#define AQ_API_ReadRegister_Devs_HHD_APPIA(id,reg,wd) AQ_API_ReadRegister_Devs_APPIA_HHD(id,reg,wd) + + +#define AQ_API_WriteRegister(id,reg,wd,value) AQ_API_WriteRegister_DeviceRestricted(APPIA_HHD,id,reg,wd,value) + +#define AQ_API_WriteRegister_DeviceRestricted(devices,id,reg,wd,value) AQ_API_WriteRegister_Devs_ ## devices(id,reg,wd,value) + +#define AQ_API_WriteRegister_Devs_APPIA(id,reg,wd,value) \ + ((port->device == AQ_DEVICE_APPIA) ? AQ_API_MDIO_Write (id,reg ## _APPIA_mmdAddress,(reg ## _APPIA_baseRegisterAddress + wd),value) : \ + ((void)0)) + +#define AQ_API_WriteRegister_Devs_HHD(id,reg,wd,value) \ + ((port->device == AQ_DEVICE_HHD) ? AQ_API_MDIO_Write (id,reg ## _HHD_mmdAddress,(reg ## _HHD_baseRegisterAddress + wd),value) : \ + ((void)0)) + +#define AQ_API_WriteRegister_Devs_APPIA_HHD(id,reg,wd,value) \ + ((port->device == AQ_DEVICE_HHD) ? AQ_API_MDIO_Write (id,reg ## _HHD_mmdAddress,(reg ## _HHD_baseRegisterAddress + wd),value) : \ + ((port->device == AQ_DEVICE_APPIA) ? AQ_API_MDIO_Write (id,reg ## _APPIA_mmdAddress,(reg ## _APPIA_baseRegisterAddress + wd),value) : \ + ((void)0))) + +#define AQ_API_WriteRegister_Devs_HHD_APPIA(id,reg,wd,value) AQ_API_WriteRegister_Devs_APPIA_HHD(id,reg,wd,value) + + +#ifdef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE + +#define AQ_API_BlockReadRegister(id,reg,wd) AQ_API_BlockReadRegister_DeviceRestricted(APPIA_HHD,id,reg,wd) + +#define AQ_API_BlockReadRegister_DeviceRestricted(devices,id,reg,wd) AQ_API_BlockReadRegister_Devs_ ## devices(id,reg,wd) + +#define AQ_API_BlockReadRegister_Devs_APPIA(id,reg,wd) \ + ((port->device == AQ_DEVICE_APPIA) ? AQ_API_MDIO_BlockRead (id,reg ## _APPIA_mmdAddress,(reg ## _APPIA_baseRegisterAddress + wd)) : \ + ((void)0)) + +#define AQ_API_BlockReadRegister_Devs_HHD(id,reg,wd) \ + ((port->device == AQ_DEVICE_HHD) ? AQ_API_MDIO_BlockRead (id,reg ## _HHD_mmdAddress,(reg ## _HHD_baseRegisterAddress + wd)) : \ + ((void)0)) + +#define AQ_API_BlockReadRegister_Devs_APPIA_HHD(id,reg,wd) \ + ((port->device == AQ_DEVICE_HHD) ? AQ_API_MDIO_BlockRead (id,reg ## _HHD_mmdAddress,(reg ## _HHD_baseRegisterAddress + wd)) : \ + ((port->device == AQ_DEVICE_APPIA) ? AQ_API_MDIO_BlockRead (id,reg ## _APPIA_mmdAddress,(reg ## _APPIA_baseRegisterAddress + wd)) : \ + ((void)0))) + +#define AQ_API_BlockReadRegister_Devs_HHD_APPIA(id,reg,wd) AQ_API_BlockReadRegister_Devs_APPIA_HHD(id,reg,wd) + + +#define AQ_API_BlockWriteRegister(id,reg,wd,value) AQ_API_BlockWriteRegister_DeviceRestricted(APPIA_HHD,id,reg,wd,value) + +#define AQ_API_BlockWriteRegister_DeviceRestricted(devices,id,reg,wd,value) AQ_API_BlockWriteRegister_Devs_ ## devices(id,reg,wd,value) + +#define AQ_API_BlockWriteRegister_Devs_APPIA(id,reg,wd,value) \ + ((port->device == AQ_DEVICE_APPIA) ? AQ_API_MDIO_BlockWrite (id,reg ## _APPIA_mmdAddress,(reg ## _APPIA_baseRegisterAddress + wd),value) : \ + ((void)0)) + +#define AQ_API_BlockWriteRegister_Devs_HHD(id,reg,wd,value) \ + ((port->device == AQ_DEVICE_HHD) ? AQ_API_MDIO_BlockWrite (id,reg ## _HHD_mmdAddress,(reg ## _HHD_baseRegisterAddress + wd),value) : \ + ((void)0)) + +#define AQ_API_BlockWriteRegister_Devs_APPIA_HHD(id,reg,wd,value) \ + ((port->device == AQ_DEVICE_HHD) ? AQ_API_MDIO_BlockWrite (id,reg ## _HHD_mmdAddress,(reg ## _HHD_baseRegisterAddress + wd),value) : \ + ((port->device == AQ_DEVICE_APPIA) ? AQ_API_MDIO_BlockWrite (id,reg ## _APPIA_mmdAddress,(reg ## _APPIA_baseRegisterAddress + wd),value) : \ + ((void)0))) + +#define AQ_API_BlockWriteRegister_Devs_HHD_APPIA(id,reg,wd,value) AQ_API_BlockWriteRegister_Devs_APPIA_HHD(id,reg,wd,value) + + +#endif + +#define AQ_API_Variable(reg) AQ_API_Variable_DeviceRestricted(APPIA_HHD,reg) + +#define AQ_API_Variable_DeviceRestricted(devices,reg) AQ_API_Variable_Devs_ ## devices(reg) + +#define AQ_API_Variable_Devs_APPIA(reg) uint8_t _local ## reg ## _space[ sizeof(reg ## _BiggestVersion) ];\ + reg ## _APPIA* _local ## reg ## _APPIA = (reg ## _APPIA*) _local ## reg ## _space; \ + +#define AQ_API_Variable_Devs_HHD(reg) uint8_t _local ## reg ## _space[ sizeof(reg ## _BiggestVersion) ];\ + reg ## _HHD* _local ## reg ## _HHD = (reg ## _HHD*) _local ## reg ## _space; \ + +#define AQ_API_Variable_Devs_APPIA_HHD(reg) uint8_t _local ## reg ## _space[ sizeof(reg ## _BiggestVersion) ];\ + reg ## _APPIA* _local ## reg ## _APPIA = (reg ## _APPIA*) _local ## reg ## _space; \ + reg ## _HHD* _local ## reg ## _HHD = (reg ## _HHD*) _local ## reg ## _space; \ + +#define AQ_API_Variable_Devs_HHD_APPIA(reg) AQ_API_Variable_Devs_APPIA_HHD(reg) + + +#define AQ_API_DeclareLocalStruct(reg,localvar) AQ_API_DeclareLocalStruct_DeviceRestricted(APPIA_HHD,reg,localvar) + +#define AQ_API_DeclareLocalStruct_DeviceRestricted(devices,reg,localvar) AQ_API_DeclareLocalStruct_Devs_ ## devices(reg,localvar) + +#define AQ_API_DeclareLocalStruct_Devs_APPIA(reg,localvar) uint8_t localvar ## _space[ sizeof(reg ## _BiggestVersion) ];\ + reg ## _APPIA* localvar ## _APPIA = (reg ## _APPIA*) localvar ## _space; \ + +#define AQ_API_DeclareLocalStruct_Devs_HHD(reg,localvar) uint8_t localvar ## _space[ sizeof(reg ## _BiggestVersion) ];\ + reg ## _HHD* localvar ## _HHD = (reg ## _HHD*) localvar ## _space; \ + +#define AQ_API_DeclareLocalStruct_Devs_APPIA_HHD(reg,localvar) uint8_t localvar ## _space[ sizeof(reg ## _BiggestVersion) ];\ + reg ## _APPIA* localvar ## _APPIA = (reg ## _APPIA*) localvar ## _space; \ + reg ## _HHD* localvar ## _HHD = (reg ## _HHD*) localvar ## _space; \ + +#define AQ_API_DeclareLocalStruct_Devs_HHD_APPIA(reg,localvar) AQ_API_DeclareLocalStruct_Devs_APPIA_HHD(reg,localvar) + + +#define AQ_API_Set(id,reg,field,value) AQ_API_Set_DeviceRestricted(APPIA_HHD,id,reg,field,value) + +#define AQ_API_Set_DeviceRestricted(devices,id,reg,field,value) AQ_API_Set_Devs_ ## devices(id,reg,field,value) + +#define AQ_API_Set_Devs_APPIA(id,reg,field,value) { \ + switch (port->device) { \ + case AQ_DEVICE_APPIA: \ + _local ## reg ## _APPIA->word_ ## reg ## _APPIA_ ## field = AQ_API_ReadRegister_Devs_APPIA(id,reg,reg ## _APPIA_ ## field); \ + if (_local ## reg ## _APPIA->bits_ ## reg ## _APPIA_ ## field.field != value) \ + { \ + _local ## reg ## _APPIA->bits_ ## reg ## _APPIA_ ## field.field = value; \ + AQ_API_WriteRegister_Devs_APPIA(id,reg,reg ## _APPIA_ ## field,_local ## reg ## _APPIA->word_ ## reg ## _APPIA_ ## field); \ + } \ + break; \ + default: break; \ + } \ +} + +#define AQ_API_Set_Devs_HHD(id,reg,field,value) { \ + switch (port->device) { \ + case AQ_DEVICE_HHD: \ + _local ## reg ## _HHD->word_ ## reg ## _HHD_ ## field = AQ_API_ReadRegister_Devs_HHD(id,reg,reg ## _HHD_ ## field); \ + if (_local ## reg ## _HHD->bits_ ## reg ## _HHD_ ## field.field != value) \ + { \ + _local ## reg ## _HHD->bits_ ## reg ## _HHD_ ## field.field = value; \ + AQ_API_WriteRegister_Devs_HHD(id,reg,reg ## _HHD_ ## field,_local ## reg ## _HHD->word_ ## reg ## _HHD_ ## field); \ + } \ + break; \ + default: break; \ + } \ +} + +#define AQ_API_Set_Devs_APPIA_HHD(id,reg,field,value) { \ + switch (port->device) { \ + case AQ_DEVICE_APPIA: \ + _local ## reg ## _APPIA->word_ ## reg ## _APPIA_ ## field = AQ_API_ReadRegister_Devs_APPIA_HHD(id,reg,reg ## _APPIA_ ## field); \ + if (_local ## reg ## _APPIA->bits_ ## reg ## _APPIA_ ## field.field != value) \ + { \ + _local ## reg ## _APPIA->bits_ ## reg ## _APPIA_ ## field.field = value; \ + AQ_API_WriteRegister_Devs_APPIA_HHD(id,reg,reg ## _APPIA_ ## field,_local ## reg ## _APPIA->word_ ## reg ## _APPIA_ ## field); \ + } \ + break; \ + case AQ_DEVICE_HHD: \ + _local ## reg ## _HHD->word_ ## reg ## _HHD_ ## field = AQ_API_ReadRegister_Devs_APPIA_HHD(id,reg,reg ## _HHD_ ## field); \ + if (_local ## reg ## _HHD->bits_ ## reg ## _HHD_ ## field.field != value) \ + { \ + _local ## reg ## _HHD->bits_ ## reg ## _HHD_ ## field.field = value; \ + AQ_API_WriteRegister_Devs_APPIA_HHD(id,reg,reg ## _HHD_ ## field,_local ## reg ## _HHD->word_ ## reg ## _HHD_ ## field); \ + } \ + break; \ + default: break; \ + } \ +} + +#define AQ_API_Set_Devs_HHD_APPIA(id,reg,field,value) AQ_API_Set_Devs_APPIA_HHD(id,reg,field,value) + + +#define AQ_API_Get(id,reg,field,value) AQ_API_Get_DeviceRestricted(APPIA_HHD,id,reg,field,value) + +#define AQ_API_Get_DeviceRestricted(devices,id,reg,field,value) AQ_API_Get_Devs_ ## devices(id,reg,field,value) + +#define AQ_API_Get_Devs_APPIA(id,reg,field,value) { \ + switch (port->device) { \ + case AQ_DEVICE_APPIA: \ + _local ## reg ## _APPIA->word_ ## reg ## _APPIA_ ## field = AQ_API_ReadRegister_Devs_APPIA(id,reg,reg ## _APPIA_ ## field); \ + value = _local ## reg ## _APPIA->bits_ ## reg ## _APPIA_ ## field.field; \ + break; \ + default: value = 0; break; \ + } \ +} + +#define AQ_API_Get_Devs_HHD(id,reg,field,value) { \ + switch (port->device) { \ + case AQ_DEVICE_HHD: \ + _local ## reg ## _HHD->word_ ## reg ## _HHD_ ## field = AQ_API_ReadRegister_Devs_HHD(id,reg,reg ## _HHD_ ## field); \ + value = _local ## reg ## _HHD->bits_ ## reg ## _HHD_ ## field.field; \ + break; \ + default: value = 0; break; \ + } \ +} + +#define AQ_API_Get_Devs_APPIA_HHD(id,reg,field,value) { \ + switch (port->device) { \ + case AQ_DEVICE_APPIA: \ + _local ## reg ## _APPIA->word_ ## reg ## _APPIA_ ## field = AQ_API_ReadRegister_Devs_APPIA_HHD(id,reg,reg ## _APPIA_ ## field); \ + value = _local ## reg ## _APPIA->bits_ ## reg ## _APPIA_ ## field.field; \ + break; \ + case AQ_DEVICE_HHD: \ + _local ## reg ## _HHD->word_ ## reg ## _HHD_ ## field = AQ_API_ReadRegister_Devs_APPIA_HHD(id,reg,reg ## _HHD_ ## field); \ + value = _local ## reg ## _HHD->bits_ ## reg ## _HHD_ ## field.field; \ + break; \ + default: value = 0; break; \ + } \ +} + +#define AQ_API_Get_Devs_HHD_APPIA(id,reg,field,value) AQ_API_Get_Devs_APPIA_HHD(id,reg,field,value) + + +#define AQ_API_BitfieldOfLocalStruct(reg,localvar,field) AQ_API_BitfieldOfLocalStruct_DeviceRestricted(APPIA_HHD,reg,localvar,field) + +#define AQ_API_BitfieldOfLocalStruct_DeviceRestricted(devices,reg,localvar,field) AQ_API_BitfieldOfLocalStruct_Devs_ ## devices(reg,localvar,field) + +#define AQ_API_BitfieldOfLocalStruct_Devs_APPIA(reg,localvar,field) \ + ((port->device == AQ_DEVICE_APPIA) ? ((localvar ## _APPIA)->bits_ ## reg ## _APPIA ## _ ## field.field) : \ + (0)) + +#define AQ_API_BitfieldOfLocalStruct_Devs_HHD(reg,localvar,field) \ + ((port->device == AQ_DEVICE_HHD) ? ((localvar ## _HHD)->bits_ ## reg ## _HHD ## _ ## field.field) : \ + (0)) + +#define AQ_API_BitfieldOfLocalStruct_Devs_APPIA_HHD(reg,localvar,field) \ + ((port->device == AQ_DEVICE_HHD) ? ((localvar ## _HHD)->bits_ ## reg ## _HHD ## _ ## field.field) : \ + ((port->device == AQ_DEVICE_APPIA) ? ((localvar ## _APPIA)->bits_ ## reg ## _APPIA ## _ ## field.field) : \ + (0))) + +#define AQ_API_BitfieldOfLocalStruct_Devs_HHD_APPIA(reg,localvar,field) AQ_API_BitfieldOfLocalStruct_Devs_APPIA_HHD(reg,localvar,field) + + +#define AQ_API_AssignBitfieldOfLocalStruct(reg,localvar,field,value) AQ_API_AssignBitfieldOfLocalStruct_DeviceRestricted(APPIA_HHD,reg,localvar,field,value) + +#define AQ_API_AssignBitfieldOfLocalStruct_DeviceRestricted(devices,reg,localvar,field,value) AQ_API_AssignBitfieldOfLocalStruct_Devs_ ## devices(reg,localvar,field,value) + +#define AQ_API_AssignBitfieldOfLocalStruct_Devs_APPIA(reg,localvar,field,value) \ + ((port->device == AQ_DEVICE_APPIA) ? ((localvar ## _APPIA)->bits_ ## reg ## _APPIA ## _ ## field.field = value) : \ + (0)) + +#define AQ_API_AssignBitfieldOfLocalStruct_Devs_HHD(reg,localvar,field,value) \ + ((port->device == AQ_DEVICE_HHD) ? ((localvar ## _HHD)->bits_ ## reg ## _HHD ## _ ## field.field = value) : \ + (0)) + +#define AQ_API_AssignBitfieldOfLocalStruct_Devs_APPIA_HHD(reg,localvar,field,value) \ + ((port->device == AQ_DEVICE_HHD) ? ((localvar ## _HHD)->bits_ ## reg ## _HHD ## _ ## field.field = value) : \ + ((port->device == AQ_DEVICE_APPIA) ? ((localvar ## _APPIA)->bits_ ## reg ## _APPIA ## _ ## field.field = value) : \ + (0))) + +#define AQ_API_AssignBitfieldOfLocalStruct_Devs_HHD_APPIA(reg,localvar,field,value) AQ_API_AssignBitfieldOfLocalStruct_Devs_APPIA_HHD(reg,localvar,field,value) + + +#define AQ_API_WordOfLocalStruct(localvar,wd) AQ_API_WordOfLocalStruct_DeviceRestricted(APPIA_HHD,localvar,wd) + +#define AQ_API_WordOfLocalStruct_DeviceRestricted(devices,localvar,wd) AQ_API_WordOfLocalStruct_Devs_ ## devices(localvar,wd) + +#define AQ_API_WordOfLocalStruct_Devs_APPIA(localvar,wd) \ + ((port->device == AQ_DEVICE_APPIA) ? ((localvar ## _APPIA)->u ## wd.word_ ## wd) : \ + (0)) + +#define AQ_API_WordOfLocalStruct_Devs_HHD(localvar,wd) \ + ((port->device == AQ_DEVICE_HHD) ? ((localvar ## _HHD)->u ## wd.word_ ## wd) : \ + (0)) + +#define AQ_API_WordOfLocalStruct_Devs_APPIA_HHD(localvar,wd) \ + ((port->device == AQ_DEVICE_HHD) ? ((localvar ## _HHD)->u ## wd.word_ ## wd) : \ + ((port->device == AQ_DEVICE_APPIA) ? ((localvar ## _APPIA)->u ## wd.word_ ## wd) : \ + (0))) + +#define AQ_API_WordOfLocalStruct_Devs_HHD_APPIA(localvar,wd) AQ_API_WordOfLocalStruct_Devs_APPIA_HHD(localvar,wd) + + +#define AQ_API_AssignWordOfLocalStruct(localvar,wd,value) AQ_API_AssignWordOfLocalStruct_DeviceRestricted(APPIA_HHD,localvar,wd,value) + +#define AQ_API_AssignWordOfLocalStruct_DeviceRestricted(devices,localvar,wd,value) AQ_API_AssignWordOfLocalStruct_Devs_ ## devices(localvar,wd,value) + +#define AQ_API_AssignWordOfLocalStruct_Devs_APPIA(localvar,wd,value) \ + ((port->device == AQ_DEVICE_APPIA) ? ((localvar ## _APPIA)->u ## wd.word_ ## wd = value) : \ + (0)) + +#define AQ_API_AssignWordOfLocalStruct_Devs_HHD(localvar,wd,value) \ + ((port->device == AQ_DEVICE_HHD) ? ((localvar ## _HHD)->u ## wd.word_ ## wd = value) : \ + (0)) + +#define AQ_API_AssignWordOfLocalStruct_Devs_APPIA_HHD(localvar,wd,value) \ + ((port->device == AQ_DEVICE_HHD) ? ((localvar ## _HHD)->u ## wd.word_ ## wd = value) : \ + ((port->device == AQ_DEVICE_APPIA) ? ((localvar ## _APPIA)->u ## wd.word_ ## wd = value) : \ + (0))) + +#define AQ_API_AssignWordOfLocalStruct_Devs_HHD_APPIA(localvar,wd,value) AQ_API_AssignWordOfLocalStruct_Devs_APPIA_HHD(localvar,wd,value) + + +#endif + diff --git a/qca/aq-fw-download/src/include/AQ_ReturnCodes.h b/qca/aq-fw-download/src/include/AQ_ReturnCodes.h new file mode 100644 index 000000000..bff083b03 --- /dev/null +++ b/qca/aq-fw-download/src/include/AQ_ReturnCodes.h @@ -0,0 +1,113 @@ +/* AQ_ReturnCodes.h */ + +/************************************************************************************ +* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +* +* Description: +* +* This file defines the AQ_API functions' integral return codes. +* +* +************************************************************************************/ + +/*! \file + This file defines the AQ_API functions' integral return codes. +*/ + +#ifndef AQ_RETURNCODES_TOKEN +#define AQ_RETURNCODES_TOKEN + + +/*! \defgroup ReturnCodes + @{ +*/ + +/*! Most AQ_API functions return AQ_Retcode to report success or failure. + * The values used are defined as preprocessor symbols in AQ_ReturnCodes.h. + * Callers should prefer to test the return values by equivalence to these + * symbols, rather than using the integer values directly, as these may + * not be stable across releases. The set of possible return codes that may + * be returned by a particular API function can be found in the function's + * documentation, as well as information on how to interpret each of the + * possible return codes. */ +typedef unsigned int AQ_Retcode; + +/*! \defgroup Success + @{ */ +#define AQ_RET_OK 0 +/*@}*/ + + +/*! \defgroup GeneralErrors + @{ */ +#define AQ_RET_ERROR 100 +#define AQ_RET_UP_BUSY_TIMEOUT 101 +/*@}*/ + +/*! \defgroup FunctionSpecificResults + @{ */ +#define AQ_RET_FLASH_READY 200 +#define AQ_RET_FLASH_READINESS_TIMEOUT 204 + +#define AQ_RET_FLASHINTF_READY 201 +#define AQ_RET_FLASHINTF_NOTREADY 202 +#define AQ_RET_FLASHINTF_READINESS_TIMEOUT 203 + +#define AQ_RET_FLASH_TYPE_UNKNOWN 205 +#define AQ_RET_FLASH_TYPE_BAD 206 + +#define AQ_RET_FLASH_IMAGE_CORRUPT 207 +#define AQ_RET_FLASH_IMAGE_TOO_LARGE 208 +#define AQ_RET_FLASH_IMAGE_MISMATCH 209 + +#define AQ_RET_FLASH_PAGE_SIZE_CHANGED 210 + +#define AQ_RET_BOOTLOAD_PROVADDR_OOR 211 +#define AQ_RET_BOOTLOAD_NONUNIFORM_REGVALS 212 +#define AQ_RET_BOOTLOAD_CRC_MISMATCH 213 +#define AQ_RET_BOOTLOAD_PROVTABLE_TOO_LARGE 228 + +#define AQ_RET_LOOPBACK_BAD_ENTRY_STATE 214 + +#define AQ_RET_DEBUGTRACE_FREEZE_TIMEOUT 215 +#define AQ_RET_DEBUGTRACE_UNFREEZE_TIMEOUT 216 + +#define AQ_RET_CABLEDIAG_ALREADY_RUNNING 217 +#define AQ_RET_CABLEDIAG_STILL_RUNNING 218 +#define AQ_RET_CABLEDIAG_BAD_PAIRSTATUS 219 +#define AQ_RET_CABLEDIAG_RESULTS_ALREDY_COLLECTED 220 +#define AQ_RET_CABLEDIAG_BAD_NUM_SAMPLES 221 +#define AQ_RET_CABLEDIAG_REPORTEDPAIR_MISMATCH 222 +#define AQ_RET_CABLEDIAG_REPORTEDPAIR_OOR 223 +#define AQ_RET_CABLEDIAG_STARTED_PAIR_B 224 +#define AQ_RET_CABLEDIAG_STARTED_PAIR_C 225 +#define AQ_RET_CABLEDIAG_STARTED_PAIR_D 226 +#define AQ_RET_CABLEDIAG_TXENABLE_MISMATCH 227 + +#define AQ_RET_SERDESEYE_BAD_SERDES_MODE 229 +#define AQ_RET_SERDESEYE_BAD_MEAS_COUNT 230 +#define AQ_RET_SERDESEYE_MEAS_TIMEOUT 231 +#define AQ_RET_SERDESEYE_LANE_OOR 232 +#define AQ_RET_SERDESEYE_COORD_OOR 233 + +#define AQ_RET_PIFMAILBOX_ERROR 234 +#define AQ_RET_PIFMAILBOX_TIMEOUT 235 + +#define AQ_RET_SEC_TABLE_INDEX_OOR 236 +/*@}*/ + +/*@}*/ + +#endif diff --git a/qca/aq-fw-download/src/include/AQ_User.h b/qca/aq-fw-download/src/include/AQ_User.h new file mode 100644 index 000000000..c7526a7cb --- /dev/null +++ b/qca/aq-fw-download/src/include/AQ_User.h @@ -0,0 +1,97 @@ +/*AQ_User.h*/ + +/************************************************************************************ +* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +* +* Description: +* +* This file contains preprocessor symbol definitions and type definitions +* for the platform-integrator controlled compile-time AQ_API options. +* +************************************************************************************/ + +/*! \file + This file contains preprocessor symbol definitions and type definitions + for the platform-integrator controlled compile-time AQ_API options. +*/ + +#ifndef AQ_USER_TOKEN +#define AQ_USER_TOKEN + +/*! \defgroup User User Definitions +This module contains the definitions used to configure AQ_API behavior as desired. */ +/*@{*/ + + +/*! Specify the proper data type for AQ_Port. This will depend on the + * platform-specific implementation of the PHY register read/write functions.*/ +typedef unsigned int AQ_Port; + + +/*! If defined, AQ_API functions will print various error and info messages + * to stdout. If not, nothing will be printed and AQ_API.c will NOT include + * stdio.h. */ +#define AQ_VERBOSE + + +/*! If defined, the PHY interface supports block (asynchronous) read/write + * operation. If AQ_PHY_SUPPORTS_BLOCK_READ_WRITE is defined, then + * the API will call the block-operation functions and so implementations + * for each must be provided. If AQ_PHY_SUPPORTS_BLOCK_READ_WRITE is not + * defined, they will not be called, and need not be implemented. */ +#undef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE + + +/*! If defined, time.h exists, and so the associated functions wil be used to + * compute the elapsed time spent in a polling loop, to ensure that the + * maximum time-out period will not be exceeded. If not defined, then + * AQ_MDIO_READS_PER_SECOND will be used to calculate the minimum possible + * elapsed time. */ +#define AQ_TIME_T_EXISTS + + +/*! The maximum number of synchronous PHY register reads that can be performed + * per second. A worst case number can be derived as follows: + * + * AQ_MDIO_READS_PER_SECOND = MDIO Clock Frequency / 64 + * + * If using MDIO preamble suppression, multiply this number by 2 + * + * For instance, if a 5MHz MDIO clock is being used without preamble supression + * AQ_MDIO_READS_PER_SECOND = 78125 + * + * If AQ_TIME_T_EXISTS is defined, this will be ignored and need not be + * defined. If AQ_TIME_T_EXISTS is not defined, this must be defined. */ +#define AQ_MDIO_READS_PER_SECOND 78125 + + +/*! If defined, after writing to one of the registers that can trigger a + * processor-intensive MDIO operation, AQ_API functions will poll the + * the "processor intensive MDIO operation in progress" bit and wait for it + * to be zero before proceeding. */ +#define AQ_ENABLE_UP_BUSY_CHECKS + + +/*! If defined, the register map header files containing reverse-packed + * structs will be included. If not, the register map header files containing + * non-reverse-packed structs will be included. The proper choice is typically + * a function of the endianness of the platform; on big-endian systems the + * reverse-packed structs should be used, and on little-endian systems the + * non-reverse-packed structs should be used. */ +/*#define AQ_REVERSED_BITFIELD_ORDERING*/ + +/*@}*/ +#endif + diff --git a/qca/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers.h b/qca/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers.h new file mode 100644 index 000000000..a9485f5a4 --- /dev/null +++ b/qca/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers.h @@ -0,0 +1,5581 @@ +/*! \file +* This file contains the data structures and doxygen comments +* for the Global Registers block. + */ + +/*! \addtogroup registerMap + @{ +*/ + +/*! \defgroup Global_registers Global Registers +* This module contains the data structures and doxygen comments +* for the Global Registers block. + */ +/*********************************************************************** +* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +* +* $Date: 2014/04/08 $ +* +* $Label: $ +* +* Description: +* +* This file contains the c header structures for the registers contained in the Global Registers block. +* +* The bit fields in this structure are from LSbit to MSbit +* +***********************************************************************/ + + +/*@{*/ +#ifndef AQ_APPIA_GLOBAL_REGS_HEADER +#define AQ_APPIA_GLOBAL_REGS_HEADER + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Control 1: 1E.0000 */ +/* Global Standard Control 1: 1E.0000 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Control 1 */ + union + { + struct + { + unsigned int reserved1 : 11; + /*! \brief 1E.0000.B R/WPD Low Power + AQ_GlobalStandardControl_1_APPIA.u0.bits_0.lowPower + + Provisionable Default = 0x0 + + 1 = Low-power mode + 0 = Normal operation + + + Notes: + A one written to this register causes the chip to enter low-power mode. This bit puts the entire chip in low-power mode, with only the MDIO and microprocessor functioning, and turns off the analog front-end: i.e. places it in high-impedance mode. Setting this bit also sets all of the Low Power bits in the other MMDs. */ + unsigned int lowPower : 1; /* 1E.0000.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Low-power mode + 0 = Normal operation + */ + unsigned int reserved0 : 2; + /*! \brief 1E.0000.E R/WSC Hard Reset + AQ_GlobalStandardControl_1_APPIA.u0.bits_0.hardReset + + Default = 0x0 + + 1 = Global hard reset + 0 = Normal operation + + + Notes: + Setting this bit initiates a global hard reset, equivalent to pulling the reset pin low. This is a level sensitive pin that connects into the power-on reset generation circuitry to initiate a complete power-on reset. */ + unsigned int hardReset : 1; /* 1E.0000.E R/WSC Default = 0x0 */ + /* 1 = Global hard reset + 0 = Normal operation + */ + /*! \brief 1E.0000.F R/WSC Soft Reset + AQ_GlobalStandardControl_1_APPIA.u0.bits_0.softReset + + Default = 0x1 + + 1 = Global soft reset + 0 = Normal operation + + + Notes: + Setting this bit initiates a global soft reset on all of the digital logic, including the microprocessor. Upon completion of the reset sequence, this bit is set back to 0. */ + unsigned int softReset : 1; /* 1E.0000.F R/WSC Default = 0x1 */ + /* 1 = Global soft reset + 0 = Normal operation + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardControl_1_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Device Identifier: 1E.0002 */ +/* Global Standard Device Identifier: 1E.0002 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Device Identifier */ + union + { + struct + { + /*! \brief 1E.0002.F:0 RO Device ID MSW [1F:10] + AQ_GlobalStandardDeviceIdentifier_APPIA.u0.bits_0.deviceIdMSW + + + + Bits 31 - 16 of Device ID + */ + unsigned int deviceIdMSW : 16; /* 1E.0002.F:0 RO */ + /* Bits 31 - 16 of Device ID */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Standard Device Identifier */ + union + { + struct + { + /*! \brief 1E.0003.F:0 RO Device ID LSW [F:0] + AQ_GlobalStandardDeviceIdentifier_APPIA.u1.bits_1.deviceIdLSW + + + + Bits 15 - 0 of Device ID + */ + unsigned int deviceIdLSW : 16; /* 1E.0003.F:0 RO */ + /* Bits 15 - 0 of Device ID */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalStandardDeviceIdentifier_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Devices in Package: 1E.0005 */ +/* Global Standard Devices in Package: 1E.0005 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Devices in Package */ + union + { + struct + { + /*! \brief 1E.0005.0 ROS Clause 22 Registers Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.clause_22RegistersPresent + + Default = 0x0 + + 1 = Clause 22 registers are present in package + 0 = Clause 22 registers are not present in package + + Notes: + This is always set to 0 in the PHY, as there are no Clause 22 registers in the device. */ + unsigned int clause_22RegistersPresent : 1; /* 1E.0005.0 ROS Default = 0x0 */ + /* 1 = Clause 22 registers are present in package + 0 = Clause 22 registers are not present in package */ + /*! \brief 1E.0005.1 ROS PMA Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.pmaPresent + + Default = 0x1 + + 1 = PMA is present in package + 0 = PMA is not present + + Notes: + This is always set to 1 as there is PMA functionality in the PHY. */ + unsigned int pmaPresent : 1; /* 1E.0005.1 ROS Default = 0x1 */ + /* 1 = PMA is present in package + 0 = PMA is not present */ + /*! \brief 1E.0005.2 ROS WIS Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.wisPresent + + Default = 0x0 + + 1 = WIS is present in package + 0 = WIS is not present in package + + Notes: + This is always set to 0, as there is no WIS functionality in the PHY. */ + unsigned int wisPresent : 1; /* 1E.0005.2 ROS Default = 0x0 */ + /* 1 = WIS is present in package + 0 = WIS is not present in package */ + /*! \brief 1E.0005.3 ROS PCS Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.pcsPresent + + Default = 0x1 + + 1 = PCS is present in package + 0 = PCS is not present in package + + Notes: + This is always set to 1 as there is PCS functionality in the PHY. */ + unsigned int pcsPresent : 1; /* 1E.0005.3 ROS Default = 0x1 */ + /* 1 = PCS is present in package + 0 = PCS is not present in package */ + /*! \brief 1E.0005.4 ROS PHY XS Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.phyXS_Present + + Default = 0x1 + + 1 = PHY XS is present in package + 0 = PHY XS is not present in package + + Notes: + This is always set to 1 as there is a PHY XS interface in the PHY. */ + unsigned int phyXS_Present : 1; /* 1E.0005.4 ROS Default = 0x1 */ + /* 1 = PHY XS is present in package + 0 = PHY XS is not present in package */ + /*! \brief 1E.0005.5 ROS DTE XS Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.dteXsPresent + + Default = 0x0 + + 1 = DTE XS is present in package + 0 = DTE XS is not present in package + + + Notes: + This is always set to 0, as there is no DTE XAUI interface in the PHY. */ + unsigned int dteXsPresent : 1; /* 1E.0005.5 ROS Default = 0x0 */ + /* 1 = DTE XS is present in package + 0 = DTE XS is not present in package + */ + /*! \brief 1E.0005.6 ROS TC Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.tcPresent + + Default = 0x0 + + 1 = TC is present in package + 0 = TC is not present in package + + Notes: + This is always set to 0, as there is no TC functionality in the PHY. */ + unsigned int tcPresent : 1; /* 1E.0005.6 ROS Default = 0x0 */ + /* 1 = TC is present in package + 0 = TC is not present in package */ + /*! \brief 1E.0005.7 ROS Autonegotiation Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.autonegotiationPresent + + Default = 0x1 + + 1 = Autonegotiation is present in package + 0 = Autonegotiation is not present in package + + Notes: + This is always set to 1, as there is Autonegotiation in the PHY. */ + unsigned int autonegotiationPresent : 1; /* 1E.0005.7 ROS Default = 0x1 */ + /* 1 = Autonegotiation is present in package + 0 = Autonegotiation is not present in package */ + unsigned int reserved0 : 8; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardDevicesInPackage_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Vendor Devices in Package: 1E.0006 */ +/* Global Standard Vendor Devices in Package: 1E.0006 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Vendor Devices in Package */ + union + { + struct + { + unsigned int reserved0 : 13; + /*! \brief 1E.0006.D ROS Clause 22 Extension Present + AQ_GlobalStandardVendorDevicesInPackage_APPIA.u0.bits_0.clause_22ExtensionPresent + + Default = 0x1 + + 1 = Clause 22 Extension is present in package + 0 = Clause 22 Extension is not present in package + + Notes: + This is always set to 1 as the PHY utilizes this device for the GbE registers. */ + unsigned int clause_22ExtensionPresent : 1; /* 1E.0006.D ROS Default = 0x1 */ + /* 1 = Clause 22 Extension is present in package + 0 = Clause 22 Extension is not present in package */ + /*! \brief 1E.0006.E ROS Vendor Specific Device #1 Present + AQ_GlobalStandardVendorDevicesInPackage_APPIA.u0.bits_0.vendorSpecificDevice_1Present + + Default = 0x1 + + 1 = Device #1 is present in package + 0 = Device #1 is not present in package + + Notes: + This is always set to 1 as the PHY utilizes this device for the global control registers. */ + unsigned int vendorSpecificDevice_1Present : 1; /* 1E.0006.E ROS Default = 0x1 */ + /* 1 = Device #1 is present in package + 0 = Device #1 is not present in package */ + /*! \brief 1E.0006.F ROS Vendor Specific Device #2 Present + AQ_GlobalStandardVendorDevicesInPackage_APPIA.u0.bits_0.vendorSpecificDevice_2Present + + Default = 0x1 + + 1 = Device #2 is present in package + 0 = Device #2 is not present in package + + Notes: + This is always set to 1 as the PHY utilizes this device for the DSP PMA registers. */ + unsigned int vendorSpecificDevice_2Present : 1; /* 1E.0006.F ROS Default = 0x1 */ + /* 1 = Device #2 is present in package + 0 = Device #2 is not present in package */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardVendorDevicesInPackage_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Status 2: 1E.0008 */ +/* Global Standard Status 2: 1E.0008 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Status 2 */ + union + { + struct + { + unsigned int reserved0 : 14; + /*! \brief 1E.0008.F:E ROS Device Present [1:0] + AQ_GlobalStandardStatus_2_APPIA.u0.bits_0.devicePresent + + Default = 0x2 + + [F:E] + 0x3 = No device at this address + 0x2 = Device present at this address + 0x1 = No device at this address + 0x0 = No device at this address + + Notes: + This field is always set to 0x2, as the Global MMD resides here in the PHY. */ + unsigned int devicePresent : 2; /* 1E.0008.F:E ROS Default = 0x2 */ + /* [F:E] + 0x3 = No device at this address + 0x2 = Device present at this address + 0x1 = No device at this address + 0x0 = No device at this address */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardStatus_2_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Package Identifier: 1E.000E */ +/* Global Standard Package Identifier: 1E.000E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Package Identifier */ + union + { + struct + { + /*! \brief 1E.000E.F:0 RO Package ID MSW [1F:10] + AQ_GlobalStandardPackageIdentifier_APPIA.u0.bits_0.packageIdMSW + + + + Bits 31- 16 of Package ID + */ + unsigned int packageIdMSW : 16; /* 1E.000E.F:0 RO */ + /* Bits 31- 16 of Package ID */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Standard Package Identifier */ + union + { + struct + { + /*! \brief 1E.000F.F:0 RO Package ID LSW [F:0] + AQ_GlobalStandardPackageIdentifier_APPIA.u1.bits_1.packageIdLSW + + + + Bits 15 - 0 of Package ID + */ + unsigned int packageIdLSW : 16; /* 1E.000F.F:0 RO */ + /* Bits 15 - 0 of Package ID */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalStandardPackageIdentifier_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Firmware ID: 1E.0020 */ +/* Global Firmware ID: 1E.0020 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Firmware ID */ + union + { + struct + { + /*! \brief 1E.0020.7:0 RO Firmware Minor Revision Number [7:0] + AQ_GlobalFirmwareID_APPIA.u0.bits_0.firmwareMinorRevisionNumber + + + + [7:0] = Minor revision number + + Notes: + + + The lower six bits of major and minor firmware revision are exchanged in autonegotiation when the PHYID message is sent. */ + unsigned int firmwareMinorRevisionNumber : 8; /* 1E.0020.7:0 RO */ + /* [7:0] = Minor revision number */ + /*! \brief 1E.0020.F:8 RO Firmware Major Revision Number [7:0] + AQ_GlobalFirmwareID_APPIA.u0.bits_0.firmwareMajorRevisionNumber + + + + [F:8] = Major revision number + + Notes: + + + The lower six bits of major and minor firmware revision are exchanged in autonegotiation when the PHYID message is sent. */ + unsigned int firmwareMajorRevisionNumber : 8; /* 1E.0020.F:8 RO */ + /* [F:8] = Major revision number */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalFirmwareID_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Chip Identification: 1E.0021 */ +/* Global Chip Identification: 1E.0021 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Chip Identification */ + union + { + struct + { + /*! \brief 1E.0021.F:0 RO Chip Identification [F:0] + AQ_GlobalChipIdentification_APPIA.u0.bits_0.chipIdentification + + + + Hardware Chip ID + + Notes: + This value is a hard-coded chip ID */ + unsigned int chipIdentification : 16; /* 1E.0021.F:0 RO */ + /* Hardware Chip ID */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalChipIdentification_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Chip Revision: 1E.0022 */ +/* Global Chip Revision: 1E.0022 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Chip Revision */ + union + { + struct + { + /*! \brief 1E.0022.F:0 RO Chip Revision [F:0] + AQ_GlobalChipRevision_APPIA.u0.bits_0.chipRevision + + + + Hardware Chip Revision + + Notes: + This value is a hard-coded chip revision */ + unsigned int chipRevision : 16; /* 1E.0022.F:0 RO */ + /* Hardware Chip Revision */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalChipRevision_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global NVR Interface: 1E.0100 */ +/* Global NVR Interface: 1E.0100 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0100.7:0 R/W NVR Opcode [7:0] + AQ_GlobalNvrInterface_APPIA.u0.bits_0.nvrOpcode + + Default = 0x03 + + NVR instruction opcode + + */ + unsigned int nvrOpcode : 8; /* 1E.0100.7:0 R/W Default = 0x03 */ + /* NVR instruction opcode + */ + /*! \brief 1E.0100.8 RO NVR Busy + AQ_GlobalNvrInterface_APPIA.u0.bits_0.nvrBusy + + + + 1 = NVR is busy + 0 = NVR is ready + + + Notes: + When set to 1, the NVR is busy. A new NVR operation should not occur until this bit is 0. If the NVR clock is greater than 64/63 of the MDIO clock, this bit never needs to be polled when operating over the MDIO. */ + unsigned int nvrBusy : 1; /* 1E.0100.8 RO */ + /* 1 = NVR is busy + 0 = NVR is ready + */ + unsigned int reserved1 : 1; + /*! \brief 1E.0100.A R/W NVR Burst + AQ_GlobalNvrInterface_APPIA.u0.bits_0.nvrBurst + + Default = 0x0 + + 0 = Single read or write operation of up to 4 bytes + 1 = Burst operation + + + Notes: + When this bit is set, the operation is a burst operation where more than 32-bits is read from the NVR or written to the NVR. This bit should be set to one until the last burst in the read or write operation, when it should be set to zero. It operates by gating the SPI clock, and not restarting it until new data is ready to be written, or the previous contents have been read. Each burst of data requires the NVR Execute Operation bit to be set to initiate the next phase. */ + unsigned int nvrBurst : 1; /* 1E.0100.A R/W Default = 0x0 */ + /* 0 = Single read or write operation of up to 4 bytes + 1 = Burst operation + */ + unsigned int reserved0 : 1; + /*! \brief 1E.0100.C R/WSC Reset NVR CRC + AQ_GlobalNvrInterface_APPIA.u0.bits_0.resetNvrCrc + + Default = 0x0 + + 1 = Reset NVR Mailbox CRC calculation register + + + Notes: + To prevent an erroneous answer, this bit should not be set at the same time the See NVR Operation Valid bit is set. */ + unsigned int resetNvrCrc : 1; /* 1E.0100.C R/WSC Default = 0x0 */ + /* 1 = Reset NVR Mailbox CRC calculation register + */ + /*! \brief 1E.0100.D R/W Freeze NVR CRC + AQ_GlobalNvrInterface_APPIA.u0.bits_0.freezeNvrCrc + + Default = 0x0 + + 1 = Freeze NVR Mailbox CRC calculation register + + + Notes: + To prevent an erroneous answer, this bit should not be set at the same time the See NVR Operation Valid bit is set. */ + unsigned int freezeNvrCrc : 1; /* 1E.0100.D R/W Default = 0x0 */ + /* 1 = Freeze NVR Mailbox CRC calculation register + */ + /*! \brief 1E.0100.E R/W NVR Write Mode + AQ_GlobalNvrInterface_APPIA.u0.bits_0.nvrWriteMode + + Default = 0x0 + + 1 = Write to NVR + 0 = Read from NVR + + */ + unsigned int nvrWriteMode : 1; /* 1E.0100.E R/W Default = 0x0 */ + /* 1 = Write to NVR + 0 = Read from NVR + */ + /*! \brief 1E.0100.F R/WSC NVR Execute Operation + AQ_GlobalNvrInterface_APPIA.u0.bits_0.nvrExecuteOperation + + Default = 0x0 + + 1 = Start NVR Operation + + + Notes: + When set to 1, the NVR operation will begin. Ensure that the uP is stalled using the See MCP Run Stall bit to ensure no NVR contention. */ + unsigned int nvrExecuteOperation : 1; /* 1E.0100.F R/WSC Default = 0x0 */ + /* 1 = Start NVR Operation + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0101.F:0 RO NVR Mailbox CRC [F:0] + AQ_GlobalNvrInterface_APPIA.u1.bits_1.nvrMailboxCrc + + + + The running CRC-16 of everything passing through the NVR interface + + + Notes: + The CRC-16 over all data written or read through the NVR interface. The CRC-16 is calculated by dividing the data by: + x^16 + x^12 + x^5 + 1 */ + unsigned int nvrMailboxCrc : 16; /* 1E.0101.F:0 RO */ + /* The running CRC-16 of everything passing through the NVR interface + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0102.7:0 R/W NVR Address MSW [17:10] + AQ_GlobalNvrInterface_APPIA.u2.bits_2.nvrAddressMSW + + Default = 0x00 + + NVR address MSW bits [17:10] + + + Notes: + The address of where to read and write from in the NVR. This is self-incrementing and will automatically increment after each read or write operation. The increment amount is based on the data length (i.e. increments by 4 if the data length is 4 bytes) */ + unsigned int nvrAddressMSW : 8; /* 1E.0102.7:0 R/W Default = 0x00 */ + /* NVR address MSW bits [17:10] + */ + unsigned int reserved0 : 8; + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0103.F:0 R/W NVR Address LSW [F:0] + AQ_GlobalNvrInterface_APPIA.u3.bits_3.nvrAddressLSW + + Default = 0x0000 + + NVR address LSW bits [F:0] + + + Notes: + The address of where to read and write from in the NVR. This is self-incrementing and will automatically increment after each read or write operation. */ + unsigned int nvrAddressLSW : 16; /* 1E.0103.F:0 R/W Default = 0x0000 */ + /* NVR address LSW bits [F:0] + */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0104.F:0 R/W NVR Data MSW [1F:10] + AQ_GlobalNvrInterface_APPIA.u4.bits_4.nvrDataMSW + + Default = 0x0000 + + NVR data MSW bits [1F:10] + + + Notes: + Data is stored and read-out from these registers in little-endian format for operations such as FLASH device ID, and for programming the processor. + + For instance the 64K Atmel device code reads out as two bytes 0x651F into the LSW register, whereas the datasheet indicates that 1F is the first byte read, followed by 65 as the second byte. + + To burst read and write these 4 bytes in the correct order (where DD is written to address x), they should be stored as: + + AA BB in the MSW + CC DD in the LSW. */ + unsigned int nvrDataMSW : 16; /* 1E.0104.F:0 R/W Default = 0x0000 */ + /* NVR data MSW bits [1F:10] + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0105.F:0 R/W NVR Data LSW [F:0] + AQ_GlobalNvrInterface_APPIA.u5.bits_5.nvrDataLSW + + Default = 0x0000 + + NVR data LSW bits [F:0] + + + Notes: + Data is stored and read-out from these registers in little-endian format for operations such as FLASH device ID, and for programming the processor. + + For instance the 64K Atmel device code reads out as two bytes 0x651F into the LSW register, whereas the datasheet indicates that 1F is the first byte read, followed by 65 as the second byte. + To burst read and write these 4 bytes in the correct order (where DD is written to address x), they should be stored as: + + AA BB in the MSW + CC DD in the LSW. */ + unsigned int nvrDataLSW : 16; /* 1E.0105.F:0 R/W Default = 0x0000 */ + /* NVR data LSW bits [F:0] + */ + } bits_5; + uint16_t word_5; + } u5; +} AQ_GlobalNvrInterface_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Mailbox Interface: 1E.0200 */ +/* Global Mailbox Interface: 1E.0200 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Mailbox Interface */ + union + { + struct + { + unsigned int reserved2 : 8; + /*! \brief 1E.0200.8 RO uP Mailbox Busy + AQ_GlobalMailboxInterface_APPIA.u0.bits_0.upMailboxBusy + + + + 1 = uP mailbox busy + 0 = uP mailbox ready + + + Notes: + In general the uP will respond within a few processor cycles to any PIF slave request, much faster than the MDIO. If the busy is asserted over multiple MDIO polling cycles, then a H/W error may have occured and a Global S/W reset or uP reset is required. */ + unsigned int upMailboxBusy : 1; /* 1E.0200.8 RO */ + /* 1 = uP mailbox busy + 0 = uP mailbox ready + */ + unsigned int reserved1 : 3; + /*! \brief 1E.0200.C R/WSC Reset uP Mailbox CRC + AQ_GlobalMailboxInterface_APPIA.u0.bits_0.resetUpMailboxCrc + + Default = 0x0 + + 1 = Reset uP mailbox CRC calculation register + + */ + unsigned int resetUpMailboxCrc : 1; /* 1E.0200.C R/WSC Default = 0x0 */ + /* 1 = Reset uP mailbox CRC calculation register + */ + unsigned int reserved0 : 1; + /*! \brief 1E.0200.E R/W uP Mailbox Write Mode + AQ_GlobalMailboxInterface_APPIA.u0.bits_0.upMailboxWriteMode + + Default = 0x0 + + 1 = Write + 0 = Read + + + Notes: + Mailbox direction */ + unsigned int upMailboxWriteMode : 1; /* 1E.0200.E R/W Default = 0x0 */ + /* 1 = Write + 0 = Read + */ + /*! \brief 1E.0200.F R/WSC uP Mailbox Execute Operation + AQ_GlobalMailboxInterface_APPIA.u0.bits_0.upMailboxExecuteOperation + + Default = 0x0 + + 1 = Start of mailbox Operation + + + Notes: + Indicates mailbox is loaded and ready */ + unsigned int upMailboxExecuteOperation : 1; /* 1E.0200.F R/WSC Default = 0x0 */ + /* 1 = Start of mailbox Operation + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0201.F:0 RO uP Mailbox CRC [F:0] + AQ_GlobalMailboxInterface_APPIA.u1.bits_1.upMailboxCrc + + + + The running CRC-16 of everything passing through the mailbox interface + + */ + unsigned int upMailboxCrc : 16; /* 1E.0201.F:0 RO */ + /* The running CRC-16 of everything passing through the mailbox interface + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0202.F:0 R/W uP Mailbox Address MSW [1F:10] + AQ_GlobalMailboxInterface_APPIA.u2.bits_2.upMailboxAddressMSW + + Default = 0x0000 + + uP Mailbox MSW address + + + Notes: + The address of where to read and write from in the Microcontroller Mailbox. This is self-incrementing and automatically increments after each read and write operation.PHY */ + unsigned int upMailboxAddressMSW : 16; /* 1E.0202.F:0 R/W Default = 0x0000 */ + /* uP Mailbox MSW address + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0203.1:0 RO uP Mailbox Address LSW Don't Care [1:0] + AQ_GlobalMailboxInterface_APPIA.u3.bits_3.upMailboxAddressLSW_Don_tCare + + + + Least significant uP LSW Mailbox address bits [1:0] + + + Notes: + These bits are always set to 0 since each memory access is on a 4-byte boundary. */ + unsigned int upMailboxAddressLSW_Don_tCare : 2; /* 1E.0203.1:0 RO */ + /* Least significant uP LSW Mailbox address bits [1:0] + */ + /*! \brief 1E.0203.F:2 R/W uP Mailbox Address LSW [F:2] + AQ_GlobalMailboxInterface_APPIA.u3.bits_3.upMailboxAddressLSW + + Default = 0x0000 + + uP LSW Mailbox address [F:2] + + + Notes: + The address of where to read and write from in the Microcontroller Mailbox. This is self-incrementing and automatically increments after each read and write operation.PHY */ + unsigned int upMailboxAddressLSW : 14; /* 1E.0203.F:2 R/W Default = 0x0000 */ + /* uP LSW Mailbox address [F:2] + */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0204.F:0 R/W uP Mailbox Data MSW [1F:10] + AQ_GlobalMailboxInterface_APPIA.u4.bits_4.upMailboxDataMSW + + Default = 0x0000 + + uP Mailbox data MSW + + */ + unsigned int upMailboxDataMSW : 16; /* 1E.0204.F:0 R/W Default = 0x0000 */ + /* uP Mailbox data MSW + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0205.F:0 R/W uP Mailbox Data LSW [F:0] + AQ_GlobalMailboxInterface_APPIA.u5.bits_5.upMailboxDataLSW + + Default = 0x0000 + + uP Mailbox data LSW + + */ + unsigned int upMailboxDataLSW : 16; /* 1E.0205.F:0 R/W Default = 0x0000 */ + /* uP Mailbox data LSW + */ + } bits_5; + uint16_t word_5; + } u5; +} AQ_GlobalMailboxInterface_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Microprocessor Scratch Pad: 1E.0300 */ +/* Global Microprocessor Scratch Pad: 1E.0300 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Microprocessor Scratch Pad */ + union + { + struct + { + /*! \brief 1E.0300.F:0 R/W Scratch Pad 1[F:0] + AQ_GlobalMicroprocessorScratchPad_APPIA.u0.bits_0.scratchPad_1 + + Default = 0x0000 + + General Purpose Scratch Pad1 + */ + unsigned int scratchPad_1 : 16; /* 1E.0300.F:0 R/W Default = 0x0000 */ + /* General Purpose Scratch Pad1 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Microprocessor Scratch Pad */ + union + { + struct + { + /*! \brief 1E.0301.F:0 R/W Scratch Pad 2 [F:0] + AQ_GlobalMicroprocessorScratchPad_APPIA.u1.bits_1.scratchPad_2 + + Default = 0x0000 + + General Purpose Scratch P + */ + unsigned int scratchPad_2 : 16; /* 1E.0301.F:0 R/W Default = 0x0000 */ + /* General Purpose Scratch P */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalMicroprocessorScratchPad_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Control: 1E.C000 */ +/* Global Control: 1E.C000 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Control */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Control */ + union + { + struct + { + /*! \brief 1E.C001.0 R/W uP Run Stall + AQ_GlobalControl_APPIA.u1.bits_1.upRunStall + + Default = 0x0 + + 1 = uP Run Stall + 0 = uP normal mode + + + Notes: + Deactivates the uP. The PIF slave bus for inbound requests will still be active. This bit is muliplexed with the "MDIO Boot Load" pin with the See uP Run Stall Override bit as the select. When the "MDIO Boot Load" pin is asserted, the uP will be in Run Stall mode after reset. */ + unsigned int upRunStall : 1; /* 1E.C001.0 R/W Default = 0x0 */ + /* 1 = uP Run Stall + 0 = uP normal mode + */ + unsigned int reserved1 : 5; + /*! \brief 1E.C001.6 R/W uP Run Stall Override + AQ_GlobalControl_APPIA.u1.bits_1.upRunStallOverride + + Default = 0x0 + + 0 = uP Run Stall from "MDIO Boot Load" pin. + 1 = uP Run Stall from See MCP Run Stall bit + + + Notes: + This bit selects the uP Run Stall from either the "MDIO Boot Load" pin or the See MCP Run Stall bit. */ + unsigned int upRunStallOverride : 1; /* 1E.C001.6 R/W Default = 0x0 */ + /* 0 = uP Run Stall from "MDIO Boot Load" pin. + 1 = uP Run Stall from See MCP Run Stall bit + */ + unsigned int reserved0 : 8; + /*! \brief 1E.C001.F R/W uP Reset + AQ_GlobalControl_APPIA.u1.bits_1.upReset + + Default = 0x0 + + 1 = Reset + + + Notes: + Resets the uP and the PIF master and slave bus. Will be active for a minimum of 100 microseconds. */ + unsigned int upReset : 1; /* 1E.C001.F R/W Default = 0x0 */ + /* 1 = Reset + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalControl_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Reset Control: 1E.C006 */ +/* Global Reset Control: 1E.C006 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Reset Control */ + union + { + struct + { + unsigned int reserved1 : 14; + /*! \brief 1E.C006.E R/WPD Global MMD Reset Disable + AQ_GlobalResetControl_APPIA.u0.bits_0.globalMMD_ResetDisable + + Provisionable Default = 0x0 + + 1 = Disable the S/W reset to the Global MMD registers + 0 = Enable the S/W reset to the Global MMD registers + + + Notes: + Setting this bit prevents a Global S/W reset or Global S/W reset from resetting the Global MMD registers */ + unsigned int globalMMD_ResetDisable : 1; /* 1E.C006.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Disable the S/W reset to the Global MMD registers + 0 = Enable the S/W reset to the Global MMD registers + */ + unsigned int reserved0 : 1; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalResetControl_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Diagnostic Provisioning: 1E.C400 */ +/* Global Diagnostic Provisioning: 1E.C400 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Diagnostic Provisioning */ + union + { + struct + { + unsigned int reserved0 : 15; + /*! \brief 1E.C400.F R/WPD Enable Diagnostics + AQ_GlobalDiagnosticProvisioning_APPIA.u0.bits_0.enableDiagnostics + + Provisionable Default = 0x1 + + 1 = Chip performs diagnostics on power-up + */ + unsigned int enableDiagnostics : 1; /* 1E.C400.F R/WPD Provisionable Default = 0x1 */ + /* 1 = Chip performs diagnostics on power-up */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalDiagnosticProvisioning_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Thermal Provisioning: 1E.C420 */ +/* Global Thermal Provisioning: 1E.C420 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C420.F:0 R/WPD Reserved 0 [F:0] + AQ_GlobalThermalProvisioning_APPIA.u0.bits_0.reserved_0 + + Provisionable Default = 0x0000 + + Internal reserved - do not modify + + */ + unsigned int reserved_0 : 16; /* 1E.C420.F:0 R/WPD Provisionable Default = 0x0000 */ + /* Internal reserved - do not modify + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C421.F:0 R/WPD High Temp Failure Threshold [F:0] + AQ_GlobalThermalProvisioning_APPIA.u1.bits_1.highTempFailureThreshold + + Provisionable Default = 0x4600 + + [F:0] of high temperature failure threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 70 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A000 - 1.A001: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. - High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int highTempFailureThreshold : 16; /* 1E.C421.F:0 R/WPD Provisionable Default = 0x4600 */ + /* [F:0] of high temperature failure threshold */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C422.F:0 R/WPD Low Temp Failure Threshold [F:0] + AQ_GlobalThermalProvisioning_APPIA.u2.bits_2.lowTempFailureThreshold + + Provisionable Default = 0x0000 + + [F:0] of low temperature failure threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 0 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A002 - 1.A003: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. - High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int lowTempFailureThreshold : 16; /* 1E.C422.F:0 R/WPD Provisionable Default = 0x0000 */ + /* [F:0] of low temperature failure threshold */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C423.F:0 R/WPD High Temp Warning Threshold [F:0] + AQ_GlobalThermalProvisioning_APPIA.u3.bits_3.highTempWarningThreshold + + Provisionable Default = 0x3C00 + + [F:0] of high temperature warning threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD008. Default is 60 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A004 - 1.A005: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. - High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int highTempWarningThreshold : 16; /* 1E.C423.F:0 R/WPD Provisionable Default = 0x3C00 */ + /* [F:0] of high temperature warning threshold */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C424.F:0 R/WPD Low Temp Warning Threshold [F:0] + AQ_GlobalThermalProvisioning_APPIA.u4.bits_4.lowTempWarningThreshold + + Provisionable Default = 0x0A00 + + [F:0] of low temperature warning threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 10 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A006 - 1.A007: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. - High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int lowTempWarningThreshold : 16; /* 1E.C424.F:0 R/WPD Provisionable Default = 0x0A00 */ + /* [F:0] of low temperature warning threshold */ + } bits_4; + uint16_t word_4; + } u4; +} AQ_GlobalThermalProvisioning_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global LED Provisioning: 1E.C430 */ +/* Global LED Provisioning: 1E.C430 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C430.1:0 R/WPD LED #0 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_0ActivityStretch : 2; /* 1E.C430.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + /*! \brief 1E.C430.2 R/WPD LED #0 Transmit Activity + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_0TransmitActivity : 1; /* 1E.C430.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C430.3 R/WPD LED #0 Receive Activity + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_0ReceiveActivity : 1; /* 1E.C430.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C430.4 R/WPD LED #0 Connecting + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_0Connecting : 1; /* 1E.C430.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C430.5 R/WPD LED #0 100 Mb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s + + */ + unsigned int led_0_100Mb_sLinkEstablished : 1; /* 1E.C430.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s + */ + /*! \brief 1E.C430.6 R/WPD LED #0 1 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_0_1Gb_sLinkEstablished : 1; /* 1E.C430.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C430.7 R/WPD LED #0 10 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_0_10Gb_sLinkEstablished : 1; /* 1E.C430.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C430.8 R/WPD LED #0 Manual Set + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_0ManualSet : 1; /* 1E.C430.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + unsigned int reserved0 : 7; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C431.1:0 R/WPD LED #1 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_1ActivityStretch : 2; /* 1E.C431.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + /*! \brief 1E.C431.2 R/WPD LED #1 Transmit Activity + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_1TransmitActivity : 1; /* 1E.C431.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C431.3 R/WPD LED #1 Receive Activity + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_1ReceiveActivity : 1; /* 1E.C431.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C431.4 R/WPD LED #1 Connecting + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_1Connecting : 1; /* 1E.C431.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C431.5 R/WPD LED #1 100 Mb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s + + */ + unsigned int led_1_100Mb_sLinkEstablished : 1; /* 1E.C431.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s + */ + /*! \brief 1E.C431.6 R/WPD LED #1 1 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_1_1Gb_sLinkEstablished : 1; /* 1E.C431.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C431.7 R/WPD LED #1 10 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_1_10Gb_sLinkEstablished : 1; /* 1E.C431.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C431.8 R/WPD LED #1 Manual Set + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_1ManualSet : 1; /* 1E.C431.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + unsigned int reserved0 : 7; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C432.1:0 R/WPD LED #2 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_2ActivityStretch : 2; /* 1E.C432.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + /*! \brief 1E.C432.2 R/WPD LED #2 Transmit Activity + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_2TransmitActivity : 1; /* 1E.C432.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C432.3 R/WPD LED #2 Receive Activity + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_2ReceiveActivity : 1; /* 1E.C432.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C432.4 R/WPD LED #2 Connecting + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_2Connecting : 1; /* 1E.C432.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C432.5 R/WPD LED #2 100 Mb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s + + */ + unsigned int led_2_100Mb_sLinkEstablished : 1; /* 1E.C432.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s + */ + /*! \brief 1E.C432.6 R/WPD LED #2 1 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_2_1Gb_sLinkEstablished : 1; /* 1E.C432.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C432.7 R/WPD LED #2 10 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_2_10Gb_sLinkEstablished : 1; /* 1E.C432.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C432.8 R/WPD LED #2 Manual Set + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_2ManualSet : 1; /* 1E.C432.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + unsigned int reserved0 : 7; + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C433.1:0 R/WPD LED #3 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_3ActivityStretch : 2; /* 1E.C433.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + /*! \brief 1E.C433.2 R/WPD LED #3 Transmit Activity + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_3TransmitActivity : 1; /* 1E.C433.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C433.3 R/WPD LED #3 Receive Activity + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_3ReceiveActivity : 1; /* 1E.C433.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C433.4 R/WPD LED #3 Connecting + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_3Connecting : 1; /* 1E.C433.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C433.5 R/WPD LED #3 100 Mb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s + + */ + unsigned int led_3_100Mb_sLinkEstablished : 1; /* 1E.C433.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s + */ + /*! \brief 1E.C433.6 R/WPD LED #3 1 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_3_1Gb_sLinkEstablished : 1; /* 1E.C433.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C433.7 R/WPD LED #3 10 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_3_10Gb_sLinkEstablished : 1; /* 1E.C433.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C433.8 R/WPD LED #3 Manual Set + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_3ManualSet : 1; /* 1E.C433.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + unsigned int reserved0 : 7; + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C434.1:0 R/WPD LED #4 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_4ActivityStretch : 2; /* 1E.C434.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + /*! \brief 1E.C434.2 R/WPD LED #4 Transmit Activity + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_4TransmitActivity : 1; /* 1E.C434.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C434.3 R/WPD LED #4 Receive Activity + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_4ReceiveActivity : 1; /* 1E.C434.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C434.4 R/WPD LED #4 Connecting + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_4Connecting : 1; /* 1E.C434.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C434.5 R/WPD LED #4 100 Mb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s + + */ + unsigned int led_4_100Mb_sLinkEstablished : 1; /* 1E.C434.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s + */ + /*! \brief 1E.C434.6 R/WPD LED #4 1 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_4_1Gb_sLinkEstablished : 1; /* 1E.C434.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C434.7 R/WPD LED #4 10 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_4_10Gb_sLinkEstablished : 1; /* 1E.C434.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C434.8 R/WPD LED #4 Manual Set + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_4ManualSet : 1; /* 1E.C434.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + unsigned int reserved0 : 7; + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C435.1:0 R/WPD LED #5 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_5ActivityStretch : 2; /* 1E.C435.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + /*! \brief 1E.C435.2 R/WPD LED #5 Transmit Activity + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_5TransmitActivity : 1; /* 1E.C435.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C435.3 R/WPD LED #5 Receive Activity + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_5ReceiveActivity : 1; /* 1E.C435.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C435.4 R/WPD LED #5 Connecting + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_5Connecting : 1; /* 1E.C435.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C435.5 R/WPD LED #5 100 Mb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s + + */ + unsigned int led_5_100Mb_sLinkEstablished : 1; /* 1E.C435.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s + */ + /*! \brief 1E.C435.6 R/WPD LED #5 1 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_5_1Gb_sLinkEstablished : 1; /* 1E.C435.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C435.7 R/WPD LED #5 10 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_5_10Gb_sLinkEstablished : 1; /* 1E.C435.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C435.8 R/WPD LED #5 Manual Set + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_5ManualSet : 1; /* 1E.C435.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + unsigned int reserved0 : 7; + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C437.0 R/WPD LED Operation Mode + AQ_GlobalLedProvisioning_APPIA.u7.bits_7.ledOperationMode + + Provisionable Default = 0x0 + + 1 = LED link activity in Mode #2 + 0 = LED link activity in classic mode + + + Notes: + When set to 1, the LED blinking rate is based on Mode #2 algorithm. When set to 0, the LED blinking rate is based on the classic algorithm. */ + unsigned int ledOperationMode : 1; /* 1E.C437.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED link activity in Mode #2 + 0 = LED link activity in classic mode + */ + unsigned int reserved0 : 15; + } bits_7; + uint16_t word_7; + } u7; + /*! \brief Union for bit and word level access of word 8 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C438.0 R/WPD LED #0 Manual Active Select + AQ_GlobalLedProvisioning_APPIA.u8.bits_8.led_0ManualActiveSelect + + Provisionable Default = 0x0 + + 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + + */ + unsigned int led_0ManualActiveSelect : 1; /* 1E.C438.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + */ + /*! \brief 1E.C438.1 R/WPD LED #0 Active High Select + AQ_GlobalLedProvisioning_APPIA.u8.bits_8.led_0ActiveHighSelect + + Provisionable Default = 0x0 + + 1 = LED active high + 0 = LED active low + + + Notes: + The See LED #0 Manual Active Select bit must be 1 for this bit to take affect. */ + unsigned int led_0ActiveHighSelect : 1; /* 1E.C438.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED active high + 0 = LED active low + */ + /*! \brief 1E.C438.2 R/WPD LED #0 Drive Three State Select + AQ_GlobalLedProvisioning_APPIA.u8.bits_8.led_0DriveThreeStateSelect + + Provisionable Default = 0x0 + + 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + + */ + unsigned int led_0DriveThreeStateSelect : 1; /* 1E.C438.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + */ + unsigned int reserved0 : 13; + } bits_8; + uint16_t word_8; + } u8; + /*! \brief Union for bit and word level access of word 9 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C439.0 R/WPD LED #1 Manual Active Select + AQ_GlobalLedProvisioning_APPIA.u9.bits_9.led_1ManualActiveSelect + + Provisionable Default = 0x0 + + 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + + */ + unsigned int led_1ManualActiveSelect : 1; /* 1E.C439.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + */ + /*! \brief 1E.C439.1 R/WPD LED #1 Active High Select + AQ_GlobalLedProvisioning_APPIA.u9.bits_9.led_1ActiveHighSelect + + Provisionable Default = 0x0 + + 1 = LED active high + 0 = LED active low + + + Notes: + The See LED #1 Manual Active Select bit must be 1 for this bit to take affect. */ + unsigned int led_1ActiveHighSelect : 1; /* 1E.C439.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED active high + 0 = LED active low + */ + /*! \brief 1E.C439.2 R/WPD LED #1 Drive Three State Select + AQ_GlobalLedProvisioning_APPIA.u9.bits_9.led_1DriveThreeStateSelect + + Provisionable Default = 0x0 + + 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + + */ + unsigned int led_1DriveThreeStateSelect : 1; /* 1E.C439.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + */ + unsigned int reserved0 : 13; + } bits_9; + uint16_t word_9; + } u9; + /*! \brief Union for bit and word level access of word 10 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C43A.0 R/WPD LED #2 Manual Active Select + AQ_GlobalLedProvisioning_APPIA.u10.bits_10.led_2ManualActiveSelect + + Provisionable Default = 0x0 + + 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + + */ + unsigned int led_2ManualActiveSelect : 1; /* 1E.C43A.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + */ + /*! \brief 1E.C43A.1 R/WPD LED #2 Active High Select + AQ_GlobalLedProvisioning_APPIA.u10.bits_10.led_2ActiveHighSelect + + Provisionable Default = 0x0 + + 1 = LED active high + 0 = LED active low + + + Notes: + The See LED #2 Manual Active Select bit must be 1 for this bit to take affect. */ + unsigned int led_2ActiveHighSelect : 1; /* 1E.C43A.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED active high + 0 = LED active low + */ + /*! \brief 1E.C43A.2 R/WPD LED #2 Drive Three State Select + AQ_GlobalLedProvisioning_APPIA.u10.bits_10.led_2DriveThreeStateSelect + + Provisionable Default = 0x0 + + 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + + */ + unsigned int led_2DriveThreeStateSelect : 1; /* 1E.C43A.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + */ + unsigned int reserved0 : 13; + } bits_10; + uint16_t word_10; + } u10; + /*! \brief Union for bit and word level access of word 11 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C43B.0 R/WPD LED #3 Manual Active Select + AQ_GlobalLedProvisioning_APPIA.u11.bits_11.led_3ManualActiveSelect + + Provisionable Default = 0x0 + + 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + + */ + unsigned int led_3ManualActiveSelect : 1; /* 1E.C43B.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + */ + /*! \brief 1E.C43B.1 R/WPD LED #3 Active High Select + AQ_GlobalLedProvisioning_APPIA.u11.bits_11.led_3ActiveHighSelect + + Provisionable Default = 0x0 + + 1 = LED active high + 0 = LED active low + + + Notes: + The See LED #3 Manual Active Select bit must be 1 for this bit to take affect. */ + unsigned int led_3ActiveHighSelect : 1; /* 1E.C43B.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED active high + 0 = LED active low + */ + /*! \brief 1E.C43B.2 R/WPD LED #3 Drive Three State Select + AQ_GlobalLedProvisioning_APPIA.u11.bits_11.led_3DriveThreeStateSelect + + Provisionable Default = 0x0 + + 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + + */ + unsigned int led_3DriveThreeStateSelect : 1; /* 1E.C43B.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + */ + unsigned int reserved0 : 13; + } bits_11; + uint16_t word_11; + } u11; + /*! \brief Union for bit and word level access of word 12 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C43C.0 R/WPD LED #4 Manual Active Select + AQ_GlobalLedProvisioning_APPIA.u12.bits_12.led_4ManualActiveSelect + + Provisionable Default = 0x0 + + 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + + */ + unsigned int led_4ManualActiveSelect : 1; /* 1E.C43C.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + */ + /*! \brief 1E.C43C.1 R/WPD LED #4 Active High Select + AQ_GlobalLedProvisioning_APPIA.u12.bits_12.led_4ActiveHighSelect + + Provisionable Default = 0x0 + + 1 = LED active high + 0 = LED active low + + + Notes: + The See LED #4 Manual Active Select bit must be 1 for this bit to take affect. */ + unsigned int led_4ActiveHighSelect : 1; /* 1E.C43C.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED active high + 0 = LED active low + */ + /*! \brief 1E.C43C.2 R/WPD LED #4 Drive Three State Select + AQ_GlobalLedProvisioning_APPIA.u12.bits_12.led_4DriveThreeStateSelect + + Provisionable Default = 0x0 + + 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + + */ + unsigned int led_4DriveThreeStateSelect : 1; /* 1E.C43C.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + */ + unsigned int reserved0 : 13; + } bits_12; + uint16_t word_12; + } u12; + /*! \brief Union for bit and word level access of word 13 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C43D.0 R/WPD LED #5 Manual Active Select + AQ_GlobalLedProvisioning_APPIA.u13.bits_13.led_5ManualActiveSelect + + Provisionable Default = 0x0 + + 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + + */ + unsigned int led_5ManualActiveSelect : 1; /* 1E.C43D.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + */ + /*! \brief 1E.C43D.1 R/WPD LED #5 Active High Select + AQ_GlobalLedProvisioning_APPIA.u13.bits_13.led_5ActiveHighSelect + + Provisionable Default = 0x0 + + 1 = LED active high + 0 = LED active low + + + Notes: + The See LED #5 Manual Active Select bit must be 1 for this bit to take affect. */ + unsigned int led_5ActiveHighSelect : 1; /* 1E.C43D.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED active high + 0 = LED active low + */ + /*! \brief 1E.C43D.2 R/WPD LED #5 Drive Three State Select + AQ_GlobalLedProvisioning_APPIA.u13.bits_13.led_5DriveThreeStateSelect + + Provisionable Default = 0x0 + + 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + + */ + unsigned int led_5DriveThreeStateSelect : 1; /* 1E.C43D.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + */ + unsigned int reserved0 : 13; + } bits_13; + uint16_t word_13; + } u13; +} AQ_GlobalLedProvisioning_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global General Provisioning: 1E.C440 */ +/* Global General Provisioning: 1E.C440 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global General Provisioning */ + union + { + struct + { + /*! \brief 1E.C440.0 RO Gang Load MDIO Write Only + AQ_GlobalGeneralProvisioning_APPIA.u0.bits_0.gangLoadMdioWriteOnly + + + + 1 = MDIO gang load enable + + + Notes: + This bit enables gang load operation with the address specified in Bits 8:4. */ + unsigned int gangLoadMdioWriteOnly : 1; /* 1E.C440.0 RO */ + /* 1 = MDIO gang load enable + */ + unsigned int reserved1 : 3; + /*! \brief 1E.C440.8:4 R/WPD Gang Load MDIO Address [4:0] + AQ_GlobalGeneralProvisioning_APPIA.u0.bits_0.gangLoadMdioAddress + + Provisionable Default = 0x00 + + MDIO Address to be used during gang load operation + + + Notes: + Gang load operation is used to load data into multiple PHYs all connected to the same MDIO bus. The address for gang load operation is provided by these bits (8:4), and enabling is done by writing Bit 0. Disabling of gang load mode is done by writing the See MDIO Address Reset (1E.C441.2) bit. These will revert the PHY's MDIO address back to the address provided by the MDIO Address pins. During gang load operation, MDIO reads are disabled to prevent bus contention. */ + unsigned int gangLoadMdioAddress : 5; /* 1E.C440.8:4 R/WPD Provisionable Default = 0x00 */ + /* MDIO Address to be used during gang load operation + */ + unsigned int reserved0 : 7; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved2 : 2; + /*! \brief 1E.C441.2 R/WSC MDIO Address Reset + AQ_GlobalGeneralProvisioning_APPIA.u1.bits_1.mdioAddressReset + + Default = 0x0 + + 1 = Load MDIO Address with the address on the MDIO address pins + + + Notes: + Used to reset the address after gang load and enable MDIO reads again. */ + unsigned int mdioAddressReset : 1; /* 1E.C441.2 R/WSC Default = 0x0 */ + /* 1 = Load MDIO Address with the address on the MDIO address pins + */ + /*! \brief 1E.C441.3 R/WPD MDIO Preamble Detection Disable + AQ_GlobalGeneralProvisioning_APPIA.u1.bits_1.mdioPreambleDetectionDisable + + Provisionable Default = 0x0 + + 1 = Suppress preamble detection on MDIO + 0 = Enable preamble detection on MDIO + + */ + unsigned int mdioPreambleDetectionDisable : 1; /* 1E.C441.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = Suppress preamble detection on MDIO + 0 = Enable preamble detection on MDIO + */ + /*! \brief 1E.C441.4 R/WPD MDIO Drive Configuration + AQ_GlobalGeneralProvisioning_APPIA.u1.bits_1.mdioDriveConfiguration + + Provisionable Default = 0x0 + + 0 = MDIO driver is in normal mode + 1 = MDIO driver is in open drain mode + + + Notes: + When the MDIO driver is in open drain mode during a read cycle, "0" data will be actively driven out of the MDIO, "1" data will set the MDIO driver in high impedance state and an external pullup will set the MDIO line to "1". The Turn-Around "0" will also be actively driven out of the MDIO, therefore in open drain mode, the Turn-Around is still "Z0". */ + unsigned int mdioDriveConfiguration : 1; /* 1E.C441.4 R/WPD Provisionable Default = 0x0 */ + /* 0 = MDIO driver is in normal mode + 1 = MDIO driver is in open drain mode + */ + unsigned int reserved1 : 8; + /*! \brief 1E.C441.D R/WPD MDIO Read MSW First Enable + AQ_GlobalGeneralProvisioning_APPIA.u1.bits_1.mdioReadMSW_FirstEnable + + Provisionable Default = 0x0 + + 1 = MSW of counter must be read first + 0 = LSW of counter must be read first + + + Notes: + This bit configures whether the MSW or LSW must be read first for counters greater than 16 bits. */ + unsigned int mdioReadMSW_FirstEnable : 1; /* 1E.C441.D R/WPD Provisionable Default = 0x0 */ + /* 1 = MSW of counter must be read first + 0 = LSW of counter must be read first + */ + /*! \brief 1E.C441.E R/WPD MDIO Broadcast Mode Enable + AQ_GlobalGeneralProvisioning_APPIA.u1.bits_1.mdioBroadcastModeEnable + + Provisionable Default = 0x0 + + 1 = Enable broadcast on Address 0 + 0 = Disable broadcast on Address 0 + + + Notes: + When set, this bit enables gang-load operation on address zero, simultaneous with normal MDIO operation. Obviously, this requires that no PHY use address 0 as its normal operating address. As well, reads on MDIO Address 0 are disabled to prevent bus contention. */ + unsigned int mdioBroadcastModeEnable : 1; /* 1E.C441.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable broadcast on Address 0 + 0 = Disable broadcast on Address 0 + */ + unsigned int reserved0 : 1; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global General Provisioning */ + union + { + struct + { + /*! \brief 1E.C442.0 R/W Daisy Chain Reset + AQ_GlobalGeneralProvisioning_APPIA.u2.bits_2.daisyChainReset + + Default = 0x0 + + 1 = Reset the daisy chain + + + Notes: + Toggling this bit from 0 to 1 will reload the IRAM and DRAM and reset the uP. The uP will be in uP run stall during the reload process. After the reload process, uP run stall will be de-asserted adn the uP reset will be asserted. Note that before setting this bit, the See Soft Reset bit needs to be de-asserted. */ + unsigned int daisyChainReset : 1; /* 1E.C442.0 R/W Default = 0x0 */ + /* 1 = Reset the daisy chain + */ + unsigned int reserved0 : 15; + } bits_2; + uint16_t word_2; + } u2; +} AQ_GlobalGeneralProvisioning_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global NVR Provisioning: 1E.C450 */ +/* Global NVR Provisioning: 1E.C450 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global NVR Provisioning */ + union + { + struct + { + /*! \brief 1E.C450.1:0 R/WPD NVR Address Length [1:0] + AQ_GlobalNvrProvisioning_APPIA.u0.bits_0.nvrAddressLength + + Provisionable Default = 0x2 + + NVR address length ranges from 0 bytes up to 3 bytes. + + + Notes: + This sets the length of the address field used in read and write operations. Use of this field is enabled via Bit 8 of See Global NVR Provisioning 2: Address 1E.C451 . + */ + unsigned int nvrAddressLength : 2; /* 1E.C450.1:0 R/WPD Provisionable Default = 0x2 */ + /* NVR address length ranges from 0 bytes up to 3 bytes. + */ + unsigned int reserved2 : 2; + /*! \brief 1E.C450.6:4 R/WPD NVR Dummy Length [2:0] + AQ_GlobalNvrProvisioning_APPIA.u0.bits_0.nvrDummyLength + + Provisionable Default = 0x0 + + NVR dummy length ranges from 0 bytes to 4 bytes. + + + Notes: + This sets the length of the dummy field used in some maunfacturer's read status and write status operations. + */ + unsigned int nvrDummyLength : 3; /* 1E.C450.6:4 R/WPD Provisionable Default = 0x0 */ + /* NVR dummy length ranges from 0 bytes to 4 bytes. + */ + unsigned int reserved1 : 1; + /*! \brief 1E.C450.A:8 R/WPD NVR Data Length [2:0] + AQ_GlobalNvrProvisioning_APPIA.u0.bits_0.nvrDataLength + + Provisionable Default = 0x4 + + NVR data length ranges from 0 bytes to 4 bytes + + + Notes: + This sets the length of the data burst used in read and write operations. + */ + unsigned int nvrDataLength : 3; /* 1E.C450.A:8 R/WPD Provisionable Default = 0x4 */ + /* NVR data length ranges from 0 bytes to 4 bytes + */ + unsigned int reserved0 : 5; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global NVR Provisioning */ + union + { + struct + { + /*! \brief 1E.C451.7:0 R/WPD NVR Clock Divide [7:0] + AQ_GlobalNvrProvisioning_APPIA.u1.bits_1.nvrClockDivide + + Provisionable Default = 0xA0 + + NVR clock divide. Clock frequency is divided by the NVR clock divide + 1 + + */ + unsigned int nvrClockDivide : 8; /* 1E.C451.7:0 R/WPD Provisionable Default = 0xA0 */ + /* NVR clock divide. Clock frequency is divided by the NVR clock divide + 1 + */ + /*! \brief 1E.C451.8 R/WPD NVR Address Length Override + AQ_GlobalNvrProvisioning_APPIA.u1.bits_1.nvrAddressLengthOverride + + Provisionable Default = 0x0 + + 0 = NVR address length is based on the "NVR_SIZE" pin. + 1 = NVR address length is based on the See NVR Address Length [1:0] register. + + + Notes: + When the this bit = 0 and NVR_SIZE pin = 0, the NVR address length is 2 bytes. When this bit = 0 and the NVR_SIZE pin = 1, the NVR address length is 3 bytes. When this bit = 1 the NVR address length is from the See NVR Address Length [1:0] */ + unsigned int nvrAddressLengthOverride : 1; /* 1E.C451.8 R/WPD Provisionable Default = 0x0 */ + /* 0 = NVR address length is based on the "NVR_SIZE" pin. + 1 = NVR address length is based on the See NVR Address Length [1:0] register. + */ + unsigned int reserved0 : 7; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global NVR Provisioning */ + union + { + struct + { + /*! \brief 1E.C452.0 R/W NVR Daisy Chain Disable + AQ_GlobalNvrProvisioning_APPIA.u2.bits_2.nvrDaisyChainDisable + + Default = 0x0 + + 1 = Disable the Daisy Chain + + + Notes: + When in daisy chain master mode, the daisy chain and MDIO can both access the SPI. Setting this bit to 1 will disable the dasiy chain from accessing the SPI and force it into a reset state. */ + unsigned int nvrDaisyChainDisable : 1; /* 1E.C452.0 R/W Default = 0x0 */ + /* 1 = Disable the Daisy Chain + */ + /*! \brief 1E.C452.1 R/W NVR Daisy Chain Clock Divide Override + AQ_GlobalNvrProvisioning_APPIA.u2.bits_2.nvrDaisyChainClockDivideOverride + + Default = 0x0 + + 1 = Override NVR clock divide when in daisy chain master mode + + + + Notes: + When in daisy chain master mode, the clock divide configuration is received from the flash. This bit will override the clock divide configuration from the flash with the See NVR Clock Divide [7:0] . */ + unsigned int nvrDaisyChainClockDivideOverride : 1; /* 1E.C452.1 R/W Default = 0x0 */ + /* 1 = Override NVR clock divide when in daisy chain master mode + + */ + unsigned int reserved0 : 14; + } bits_2; + uint16_t word_2; + } u2; +} AQ_GlobalNvrProvisioning_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Reserved Provisioning: 1E.C470 */ +/* Global Reserved Provisioning: 1E.C470 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved2 : 4; + /*! \brief 1E.C470.4 R/WSC Initiate Cable Diagnostics + AQ_GlobalReservedProvisioning_APPIA.u0.bits_0.initiateCableDiagnostics + + Default = 0x0 + + 1 = Perform cable diagnostics + + + Notes: + Perform cable diagnostics regardless of link state. If link is up, setting this bit will cause the link to drop while diagnostics are performed. This bit is self-clearing upon completion of the cable diagnostics. Further MDIO writes should be avoided until this bit has self-cleared, indicating completion of the diagnostic routine. */ + unsigned int initiateCableDiagnostics : 1; /* 1E.C470.4 R/WSC Default = 0x0 */ + /* 1 = Perform cable diagnostics + */ + /*! \brief 1E.C470.5 R/WSC Initiate Component Diagnostics + AQ_GlobalReservedProvisioning_APPIA.u0.bits_0.initiateComponentDiagnostics + + Default = 0x0 + + 1 = Perform component diagnostics + + + Notes: + Perform component diagnostics regardless of link state. If link is up, setting this bit will cause the link to drop while diagnostics are performed. This bit is self-clearing upon completion of the component diagnostics. Further MDIO writes should be avoided until this bit has self-cleared, indicating completion of the diagnostic routine. */ + unsigned int initiateComponentDiagnostics : 1; /* 1E.C470.5 R/WSC Default = 0x0 */ + /* 1 = Perform component diagnostics + */ + unsigned int reserved1 : 2; + unsigned int reserved0 : 5; + /*! \brief 1E.C470.E:D R/WPD Extended MDI Diagnostics Select [1:0] + AQ_GlobalReservedProvisioning_APPIA.u0.bits_0.extendedMdiDiagnosticsSelect + + Provisionable Default = 0x0 + + 0x0 = TDR Data + 0x1 = RFI Channel PSD + 0x2 = Noise PSD while the local Tx is Off + 0x3 = Noise PSD while the local Tx is On + + + Notes: + These bits select what sort of cable diagnostics to perform. For regular cable diagnostics, Bit F is set to zero, and the diagnostics are triggered by setting Bit 4. For extended diagnostics, Bit F is set to 1, and the desired extended diagnostics are selected by Bits E:D. The routine is then triggered by setting Bit 4. Each of the extended diagnostic routines present data for all for MDI pairs (A, B, C, D) consecutively, and after the data for each channel is gathered Bits F:D are reset. To get the data for the next pair, Bits F:D must be set back to the desired value (which must be the same as the initial channel). This continues until the data for all channels has been gathered. The address in memory where the data is stored is given in 1E.C802 and 1E.C804. + + For the case of PSD, the structure is as follows: + Int32 info + Int16 data[Len] + Info = Len << 16 | TxEnable << 8 | Pair (0 = A, etc.) + + For TDR: + Int32 info + Int16 tdr_A[Len] + Int16 tdr_B[Len] + Int16 tdr_C[Len] + Int16 tdr_D[Len] + + Info = Len << 16 | Channel + + TDR data is from the current pair to all other pairs. + + At the end of retrieving extended MDI diag data, the part will be reset. Conversly the only way to exit this routine once it starts is to issue a PMA reset. */ + unsigned int extendedMdiDiagnosticsSelect : 2; /* 1E.C470.E:D R/WPD Provisionable Default = 0x0 */ + /* 0x0 = TDR Data + 0x1 = RFI Channel PSD + 0x2 = Noise PSD while the local Tx is Off + 0x3 = Noise PSD while the local Tx is On + */ + /*! \brief 1E.C470.F R/WPD Diagnostics Select + AQ_GlobalReservedProvisioning_APPIA.u0.bits_0.diagnosticsSelect + + Provisionable Default = 0x0 + + 1 = Provide Extended MDI Diagnostics Information. + 0 = Provide normal cable diagnostics + + + Notes: + These bits select what sort of cable diagnostics to perform. For regular cable diagnostics, Bit F is set to zero, and the diagnostics are triggered by setting Bit 4. For extended diagnostics, Bit F is set to 1, and the desired extended diagnostics are selected by Bits E:D. The routine is then triggered by setting Bit 4. Each of the extended diagnostic routines present data for all for MDI pairs (A, B, C, D) consecutively, and after the data for each channel is gathered Bits F:D are reset. To get the data for the next pair, Bits F:D must be set back to the desired value (which must be the same as the initial channel). This continues until the data for all channels has been gathered. The address in memory where the data is stored is given in 1E.C802 and 1E.C804. + + For the case of PSD, the structure is as follows: + Int32 info + Int16 data[Len] + Info = Len << 16 | TxEnable << 8 | Pair (0 = A, etc.) + + For TDR: + Int32 info + Int16 tdr_A[Len] + Int16 tdr_B[Len] + Int16 tdr_C[Len] + Int16 tdr_D[Len] + + Info = Len << 16 | Channel + + TDR data is from the current pair to all other pairs. + + At the end of retrieving extended MDI diag data, the part will be reset. Conversly the only way to exit this routine once it starts is to issue a PMA reset. */ + unsigned int diagnosticsSelect : 1; /* 1E.C470.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Provide Extended MDI Diagnostics Information. + 0 = Provide normal cable diagnostics + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C471.5:0 R/WuP Daisy-Chain Hop-Count Override Value [5:0] + AQ_GlobalReservedProvisioning_APPIA.u1.bits_1.daisy_chainHop_countOverrideValue + + Default = 0x00 + + The value to use for the PHY's daisy-chain hop-count. Valid values are from 0 -> 47 + + + Notes: + Daisy-Chain Hop-Count Override should be used during MDIO boot-load operation, as the daisy-chain hop-count does not function when the daisy-chain is disabled (1E.C452.0). Setting this bit tells the processor where in the diasy-chain it is, so that the provisioning operation will function correctly. */ + unsigned int daisy_chainHop_countOverrideValue : 6; /* 1E.C471.5:0 R/WuP Default = 0x00 */ + /* The value to use for the PHY's daisy-chain hop-count. Valid values are from 0 -> 47 + */ + /*! \brief 1E.C471.6 R/WuP Enable Daisy-Chain Hop-Count Override + AQ_GlobalReservedProvisioning_APPIA.u1.bits_1.enableDaisy_chainHop_countOverride + + Default = 0x0 + + 1 = Hop-count is set by Bits 5:0 + 0 = Hop-count is determined by the daisy-chain + + + Notes: + Daisy-Chain Hop-Count Override should be used during MDIO boot-load operation, as the daisy-chain hop-count does not function when the daisy-chain is disabled (1E.C452.0). Setting this bit tells the processor where in the diasy-chain it is, so that the provisioning operation will function correctly. */ + unsigned int enableDaisy_chainHop_countOverride : 1; /* 1E.C471.6 R/WuP Default = 0x0 */ + /* 1 = Hop-count is set by Bits 5:0 + 0 = Hop-count is determined by the daisy-chain + */ + /*! \brief 1E.C471.F:7 R/WPD Reserved Provisioning 2 [8:0] + AQ_GlobalReservedProvisioning_APPIA.u1.bits_1.reservedProvisioning_2 + + Provisionable Default = 0x000 + + Reserved for future use + + */ + unsigned int reservedProvisioning_2 : 9; /* 1E.C471.F:7 R/WPD Provisionable Default = 0x000 */ + /* Reserved for future use + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C472.0 R/WPDuP Enable 5th Channel RFI Cancellation + AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.enable_5thChannelRfiCancellation + + Provisionable Default = 0x0 + + 1 = 5th channel and RFI cancellers operation enabled + 0 = 5th channel AFE is powered down, 5th channel digital is clock gated, RFI cancellers are disabled + + + Notes: + Note: The value of this bit at the time of Autonegotiation sets the local PHY behavior until the next time Autonegotiation occurs. */ + unsigned int enable_5thChannelRfiCancellation : 1; /* 1E.C472.0 R/WPDuP Provisionable Default = 0x0 */ + /* 1 = 5th channel and RFI cancellers operation enabled + 0 = 5th channel AFE is powered down, 5th channel digital is clock gated, RFI cancellers are disabled + */ + /*! \brief 1E.C472.1 R/WPDuP Enable XENPAK Register Space + AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.enableXenpakRegisterSpace + + Provisionable Default = 0x0 + + 1 = XENPAK register space enabled + 0 = XENPAK register space disabled + + */ + unsigned int enableXenpakRegisterSpace : 1; /* 1E.C472.1 R/WPDuP Provisionable Default = 0x0 */ + /* 1 = XENPAK register space enabled + 0 = XENPAK register space disabled + */ + unsigned int reserved1 : 4; + /*! \brief 1E.C472.6 R/WPD Tunable External VDD Power Supply Present + AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.tunableExternalVddPowerSupplyPresent + + Provisionable Default = 0x0 + + 1 = Tunable external VDD power supply present + 0 = No tunable external VDD power supply present + + + Notes: + + + + These bits must be set if tuning of external power supplies is desired (see Bits 7:6) */ + unsigned int tunableExternalVddPowerSupplyPresent : 1; /* 1E.C472.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Tunable external VDD power supply present + 0 = No tunable external VDD power supply present + */ + /*! \brief 1E.C472.7 R/WPD Tunable External LVDD Power Supply Present + AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.tunableExternalLvddPowerSupplyPresent + + Provisionable Default = 0x0 + + 1 = Tunable external LVDD power supply present + 0 = No tunable external LVDD power supply present + + + Notes: + + + + These bits must be set if tuning of external power supplies is desired (see Bits 7:6) */ + unsigned int tunableExternalLvddPowerSupplyPresent : 1; /* 1E.C472.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = Tunable external LVDD power supply present + 0 = No tunable external LVDD power supply present + */ + unsigned int reserved0 : 6; + /*! \brief 1E.C472.E R/WPD Enable VDD Power Supply Tuning + AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.enableVddPowerSupplyTuning + + Provisionable Default = 0x0 + + 1 = Enable external VDD power supply tuning + 0 = Disable external VDD power supply tuning is disabled + + + Notes: + + + + These bits control whether the PHY attempts to tune the external VDD and LVDD power supplies via the PMBus. These bits are only operational if the external supplies are present (see Bits 7:6) */ + unsigned int enableVddPowerSupplyTuning : 1; /* 1E.C472.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable external VDD power supply tuning + 0 = Disable external VDD power supply tuning is disabled + */ + /*! \brief 1E.C472.F R/WPD Enable LVDD Power Supply Tuning + AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.enableLvddPowerSupplyTuning + + Provisionable Default = 0x0 + + 1 = Enable external LVDD power supply tuning + 0 = Disable external LVDD power supply tuning is disabled + + + Notes: + + + + These bits control whether the PHY attempts to tune the external VDD and LVDD power supplies via the PMBus. These bits are only operational if the external supplies are present (see Bits 7:6) */ + unsigned int enableLvddPowerSupplyTuning : 1; /* 1E.C472.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable external LVDD power supply tuning + 0 = Disable external LVDD power supply tuning is disabled + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C474.7:0 R/WPD Training SNR [7:0] + AQ_GlobalReservedProvisioning_APPIA.u4.bits_4.trainingSNR + + Provisionable Default = 0x00 + + SNR during 10G training on the worst channel. SNR is in steps of 0.1dB + + + Notes: + The SNR margin that is enjoyed by the worst channel, over and above the minimum SNR required to operate at a BER of 10-12. It is reported with 0.1 dB of resolution to an accuracy of 0.5 dB within the range of -12.7 dB to 12.7 dB. The number is in offset binary, with 0.0 dB represented by 0x8000. + */ + unsigned int trainingSNR : 8; /* 1E.C474.7:0 R/WPD Provisionable Default = 0x00 */ + /* SNR during 10G training on the worst channel. SNR is in steps of 0.1dB + */ + unsigned int reserved0 : 8; + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved1 : 2; + /*! \brief 1E.C475.2 R/WPD Smart Power-Down Enable + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.smartPower_downEnable + + Provisionable Default = 0x0 + + 1 = Enable smart power down mode + 0 = Smart power-down mode disabled + + + Notes: + Smart power down (SPD) is the lowest power mode at which PHY is able to autonegotiate. SPD can be enabled with bit 1E.C475.2 */ + unsigned int smartPower_downEnable : 1; /* 1E.C475.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable smart power down mode + 0 = Smart power-down mode disabled + */ + /*! \brief 1E.C475.3 R/WPD Deadlock Avoidance Enable + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.deadlockAvoidanceEnable + + Provisionable Default = 0x0 + + 1 = SPD with deadlock avoidance: PHY transmits autonegotiation pulses (FLPs) at a slower rate (~ 1 FLP/ 100ms) than specified by autonegotiation standard (~1 FLP / 8.25ms). Receiver is active and able to detect the pulses. + 0 = SPD without deadlock avoidance: PHY transmitter is shut down, no autonegotiation pulses are sent on the line but the receiver is active and able to detect the pulses + + */ + unsigned int deadlockAvoidanceEnable : 1; /* 1E.C475.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = SPD with deadlock avoidance: PHY transmits autonegotiation pulses (FLPs) at a slower rate (~ 1 FLP/ 100ms) than specified by autonegotiation standard (~1 FLP / 8.25ms). Receiver is active and able to detect the pulses. + 0 = SPD without deadlock avoidance: PHY transmitter is shut down, no autonegotiation pulses are sent on the line but the receiver is active and able to detect the pulses + */ + /*! \brief 1E.C475.4 R/WPD CFR Support + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrSupport + + Provisionable Default = 0x0 + + 1 = Local PHY supports Cisco Fast Retrain + 0 = Local PHY does support Cisco Fast Retrain + + */ + unsigned int cfrSupport : 1; /* 1E.C475.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY supports Cisco Fast Retrain + 0 = Local PHY does support Cisco Fast Retrain + */ + /*! \brief 1E.C475.5 R/WPD CFR THP + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrTHP + + Provisionable Default = 0x0 + + 1 = Local PHY requires local PHY to enable THP + 0 = Local PHY does not require local PHY to enable THP + + */ + unsigned int cfrTHP : 1; /* 1E.C475.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY requires local PHY to enable THP + 0 = Local PHY does not require local PHY to enable THP + */ + /*! \brief 1E.C475.6 R/WPD CFR Extended Maxwait + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrExtendedMaxwait + + Provisionable Default = 0x0 + + 1 = Local PHY requires extended maxwait + 0 = Local PHY does not require extended maxwait + + */ + unsigned int cfrExtendedMaxwait : 1; /* 1E.C475.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY requires extended maxwait + 0 = Local PHY does not require extended maxwait + */ + /*! \brief 1E.C475.7 R/WPD CFR Disable Timer + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrDisableTimer + + Provisionable Default = 0x0 + + 1 = Local PHY requires cfr_disable timer + 0 = Local PHY does not require cfr_disable timer + + */ + unsigned int cfrDisableTimer : 1; /* 1E.C475.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY requires cfr_disable timer + 0 = Local PHY does not require cfr_disable timer + */ + /*! \brief 1E.C475.8 R/WPD CFR LP Support + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrLpSupport + + Provisionable Default = 0x0 + + 1 = Link partner supports Cisco Fast Retrain + 0 = Link partner does support Cisco Fast Retrain + + */ + unsigned int cfrLpSupport : 1; /* 1E.C475.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner supports Cisco Fast Retrain + 0 = Link partner does support Cisco Fast Retrain + */ + /*! \brief 1E.C475.9 R/WPD CFR LP THP + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrLpTHP + + Provisionable Default = 0x0 + + 1 = Link partner requires local PHY to enable THP + 0 = Link partner does not require local PHY to enable THP + + */ + unsigned int cfrLpTHP : 1; /* 1E.C475.9 R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner requires local PHY to enable THP + 0 = Link partner does not require local PHY to enable THP + */ + /*! \brief 1E.C475.A R/WPD CFR LP Extended Maxwait + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrLpExtendedMaxwait + + Provisionable Default = 0x0 + + 1 = Link partner requires extended maxwait + 0 = Link partner does not require extended maxwait + + */ + unsigned int cfrLpExtendedMaxwait : 1; /* 1E.C475.A R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner requires extended maxwait + 0 = Link partner does not require extended maxwait + */ + /*! \brief 1E.C475.B R/WPD CFR LP Disable Timer + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrLpDisableTimer + + Provisionable Default = 0x0 + + 1 = Link partner requires cfr_disable timer + 0 = Link partner does not require cfr_disable timer + + */ + unsigned int cfrLpDisableTimer : 1; /* 1E.C475.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner requires cfr_disable timer + 0 = Link partner does not require cfr_disable timer + */ + /*! \brief 1E.C475.C R/WPD Reserved Provisioning 6 + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.reservedProvisioning_6 + + Provisionable Default = 0x0 + + Reserved for future use + + */ + unsigned int reservedProvisioning_6 : 1; /* 1E.C475.C R/WPD Provisionable Default = 0x0 */ + /* Reserved for future use + */ + /*! \brief 1E.C475.D R/WPD Smart Power-Down Status + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.smartPower_downStatus + + Provisionable Default = 0x0 + + 1 = Smart Power-Down Active + 0 = Smart Power-Down Inactive + + */ + unsigned int smartPower_downStatus : 1; /* 1E.C475.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Smart Power-Down Active + 0 = Smart Power-Down Inactive + */ + unsigned int reserved0 : 2; + } bits_5; + uint16_t word_5; + } u5; +} AQ_GlobalReservedProvisioning_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Cable Diagnostic Status: 1E.C800 */ +/* Global Cable Diagnostic Status: 1E.C800 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C800.2:0 RO Pair D Status [2:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u0.bits_0.pairDStatus + + + + (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair C + 010= Connected to Pair B + 001= Connected to Pair A + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK + + Notes: + This bitfield reports the result, for pair D, of running either cable diagnostics or component diagnostics. */ + unsigned int pairDStatus : 3; /* 1E.C800.2:0 RO */ + /* (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair C + 010= Connected to Pair B + 001= Connected to Pair A + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK */ + unsigned int reserved3 : 1; + /*! \brief 1E.C800.6:4 RO Pair C Status [2:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u0.bits_0.pairCStatus + + + + (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair B + 010= Connected to Pair A + 001= Connected to Pair D + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK + + Notes: + This bitfield reports the result, for pair C, of running either cable diagnostics or component diagnostics. */ + unsigned int pairCStatus : 3; /* 1E.C800.6:4 RO */ + /* (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair B + 010= Connected to Pair A + 001= Connected to Pair D + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK */ + unsigned int reserved2 : 1; + /*! \brief 1E.C800.A:8 RO Pair B Status [2:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u0.bits_0.pairBStatus + + + + (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair A + 010= Connected to Pair D + 001= Connected to Pair C + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK + + Notes: + This bitfield reports the result, for pair B, of running either cable diagnostics or component diagnostics. */ + unsigned int pairBStatus : 3; /* 1E.C800.A:8 RO */ + /* (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair A + 010= Connected to Pair D + 001= Connected to Pair C + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK */ + unsigned int reserved1 : 1; + /*! \brief 1E.C800.E:C RO Pair A Status [2:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u0.bits_0.pairAStatus + + + + (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair D + 010= Connected to Pair C + 001= Connected to Pair B + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK + + Notes: + This bitfield reports the result, for pair A, of running either cable diagnostics or component diagnostics. */ + unsigned int pairAStatus : 3; /* 1E.C800.E:C RO */ + /* (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair D + 010= Connected to Pair C + 001= Connected to Pair B + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK */ + unsigned int reserved0 : 1; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C801.7:0 RO Pair A Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u1.bits_1.pairAReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair A + + Notes: + The distance to this reflection is given in See Global Reserved Status 1: Address 1E.C870 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairAReflection_2 : 8; /* 1E.C801.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair A */ + /*! \brief 1E.C801.F:8 RO Pair A Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u1.bits_1.pairAReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair A + + Notes: + The distance to this reflection is given in See Global Reserved Status 1: Address 1E.C870 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairAReflection_1 : 8; /* 1E.C801.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair A */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C802.F:0 RO Impulse Response MSW [F:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u2.bits_2.impulseResponseMSW + + + + The MSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type in 1E.C470.E:D + + + Notes: + See 1E.C470 for more information */ + unsigned int impulseResponseMSW : 16; /* 1E.C802.F:0 RO */ + /* The MSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type in 1E.C470.E:D + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C803.7:0 RO Pair B Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u3.bits_3.pairBReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair B + + Notes: + The distance to this reflection is given in See Global Reserved Status 2: Address 1E.C871 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairBReflection_2 : 8; /* 1E.C803.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair B */ + /*! \brief 1E.C803.F:8 RO Pair B Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u3.bits_3.pairBReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair B + + Notes: + The distance to this reflection is given in See Global Reserved Status 2: Address 1E.C871 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairBReflection_1 : 8; /* 1E.C803.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair B */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C804.F:0 RO Impulse Response LSW [F:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u4.bits_4.impulseResponseLSW + + + + The LSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type specified in 1E.C470.E:D + + + Notes: + See 1E.C470 for more information */ + unsigned int impulseResponseLSW : 16; /* 1E.C804.F:0 RO */ + /* The LSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type specified in 1E.C470.E:D + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C805.7:0 RO Pair C Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u5.bits_5.pairCReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair C + + Notes: + The distance to this reflection is given in See Global Reserved Status 3: Address 1E.C872 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairCReflection_2 : 8; /* 1E.C805.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair C */ + /*! \brief 1E.C805.F:8 RO Pair C Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u5.bits_5.pairCReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair C + + Notes: + The distance to this reflection is given in See Global Reserved Status 3: Address 1E.C872 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairCReflection_1 : 8; /* 1E.C805.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair C */ + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C806.F:0 RO Reserved 1 [F:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u6.bits_6.reserved_1 + + + + Reserved for future use + + */ + unsigned int reserved_1 : 16; /* 1E.C806.F:0 RO */ + /* Reserved for future use + */ + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C807.7:0 RO Pair D Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u7.bits_7.pairDReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair D + + Notes: + The distance to this reflection is given in See Global Reserved Status 4: Address 1E.C873 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairDReflection_2 : 8; /* 1E.C807.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair D */ + /*! \brief 1E.C807.F:8 RO Pair D Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u7.bits_7.pairDReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair D + + Notes: + The distance to this reflection is given in See Global Reserved Status 4: Address 1E.C873 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairDReflection_1 : 8; /* 1E.C807.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair D */ + } bits_7; + uint16_t word_7; + } u7; + /*! \brief Union for bit and word level access of word 8 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C808.F:0 RO Reserved 2[F:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u8.bits_8.reserved_2 + + + + Reserved for future use + + */ + unsigned int reserved_2 : 16; /* 1E.C808.F:0 RO */ + /* Reserved for future use + */ + } bits_8; + uint16_t word_8; + } u8; +} AQ_GlobalCableDiagnosticStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Thermal Status: 1E.C820 */ +/* Global Thermal Status: 1E.C820 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Thermal Status */ + union + { + struct + { + /*! \brief 1E.C820.F:0 RO Temperature [F:0] + AQ_GlobalThermalStatus_APPIA.u0.bits_0.temperature + + + + [F:0] of temperature + + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 70 degreesC. This is a mirror of the XENPAK register 1.A060 - 1.A061. The mirror is performed in H/W. */ + unsigned int temperature : 16; /* 1E.C820.F:0 RO */ + /* [F:0] of temperature + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Thermal Status */ + union + { + struct + { + /*! \brief 1E.C821.0 RO Temperature Ready + AQ_GlobalThermalStatus_APPIA.u1.bits_1.temperatureReady + + + + 1 = Temperature measurement is valid + + + Notes: + This is a mirror of the XENPAK register 1.A06E. */ + unsigned int temperatureReady : 1; /* 1E.C821.0 RO */ + /* 1 = Temperature measurement is valid + */ + unsigned int reserved0 : 15; + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalThermalStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global General Status: 1E.C830 */ +/* Global General Status: 1E.C830 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global General Status */ + union + { + struct + { + unsigned int reserved1 : 11; + /*! \brief 1E.C830.B RO Low Temperature Warning State + AQ_GlobalGeneralStatus_APPIA.u0.bits_0.lowTemperatureWarningState + + + + 1 = Low temperature warning threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A074.6 register. + + */ + unsigned int lowTemperatureWarningState : 1; /* 1E.C830.B RO */ + /* 1 = Low temperature warning threshold has been exceeded */ + /*! \brief 1E.C830.C RO High Temperature Warning State + AQ_GlobalGeneralStatus_APPIA.u0.bits_0.highTemperatureWarningState + + + + 1 = High temperature warning threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A074.7 register. + + */ + unsigned int highTemperatureWarningState : 1; /* 1E.C830.C RO */ + /* 1 = High temperature warning threshold has been exceeded */ + /*! \brief 1E.C830.D RO Low Temperature Failure State + AQ_GlobalGeneralStatus_APPIA.u0.bits_0.lowTemperatureFailureState + + + + 1 = Low temperature failure threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A070.6 register. + + */ + unsigned int lowTemperatureFailureState : 1; /* 1E.C830.D RO */ + /* 1 = Low temperature failure threshold has been exceeded */ + /*! \brief 1E.C830.E RO High Temperature Failure State + AQ_GlobalGeneralStatus_APPIA.u0.bits_0.highTemperatureFailureState + + + + 1 = High temperature failure threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A070.7 register. + + */ + unsigned int highTemperatureFailureState : 1; /* 1E.C830.E RO */ + /* 1 = High temperature failure threshold has been exceeded */ + unsigned int reserved0 : 1; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global General Status */ + union + { + struct + { + unsigned int reserved0 : 15; + /*! \brief 1E.C831.F RO Processor Intensive MDIO Operation In- Progress + AQ_GlobalGeneralStatus_APPIA.u1.bits_1.processorIntensiveMdioOperationIn_Progress + + + + 1 = PHY microprocessor is busy with a processor-intensive MDIO operation + 0 = Processor-intensive MDIO operation completed + + + Notes: + This bit should may be used with certain processor-intensive MDIO commands (such as Loopbacks, Test Modes, Low power modes, Tx-Disable, Restart autoneg, Cable Diagnostics, etc.) that take longer than an MDIO cycle to complete. Upon receiving an MDIO command that involves the PHY's microprocessor, this bit is set, and when the command is completed, this bit is cleared. + + NOTE!!! This bit should be checked only after 1 ms of issuing a processor-intensive MDIO operation. + + The list of operations that set this bit are as follows: + + 1.0.0, PMA Loopback + 1.0.B, Low power mode + 1.9.4:0, Tx Disable + 1.84, 10G Test modes + 1.8000.5, XENPAK Control + 1.9000, XENPAK Rx Fault Enable + 1.9002, XENPAK Alarm Enable + 1.E400.F, External loopback + 3.0.B, Low power mode + 3.0.E, System PCS loopback + 3.C471.5, PRBS Test + 3.C471.6, PRBS Test + 3.E471.5, PRBS Test + 3.E471.6, PRBS Test + 4.0.B, Low power mode + 4.0.E, PHY-XS network loopback + 4.C440, Output clock control, Load SERDES parameters + 4.F802.E, System loopback + 4.C444.F:B, Loopback Control + 4.C444.4:2, Packet generation + 4.C445.C, SERDES calibration + 7.0.9, Restart autonegotiation + 1D.C280, 1G/100M Network loopback + 1D.C500, 1G System loopback + 1D.C501, 1G / 100M Test modes */ + unsigned int processorIntensiveMdioOperationIn_Progress : 1; /* 1E.C831.F RO */ + /* 1 = PHY microprocessor is busy with a processor-intensive MDIO operation + 0 = Processor-intensive MDIO operation completed + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalGeneralStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Pin Status: 1E.C840 */ +/* Global Pin Status: 1E.C840 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Pin Status */ + union + { + struct + { + /*! \brief 1E.C840.5:0 RO LED Pullup State [5:0] + AQ_GlobalPinStatus_APPIA.u0.bits_0.ledPullupState + + + + 1 = LED output pin is pulled high + 0 = LED output pin is pulled low + + */ + unsigned int ledPullupState : 6; /* 1E.C840.5:0 RO */ + /* 1 = LED output pin is pulled high + 0 = LED output pin is pulled low + */ + unsigned int reserved3 : 1; + /*! \brief 1E.C840.7 RO Tx Enable + AQ_GlobalPinStatus_APPIA.u0.bits_0.txEnable + + + + Current Value of Tx Enable pin + + + Notes: + 0 = Disable Transmitter */ + unsigned int txEnable : 1; /* 1E.C840.7 RO */ + /* Current Value of Tx Enable pin + */ + unsigned int reserved2 : 1; + /*! \brief 1E.C840.9 RO Package Connectivity + AQ_GlobalPinStatus_APPIA.u0.bits_0.packageConnectivity + + + + Value of the package connection pin + + */ + unsigned int packageConnectivity : 1; /* 1E.C840.9 RO */ + /* Value of the package connection pin + */ + unsigned int reserved1 : 3; + /*! \brief 1E.C840.E:D RO MDIO Boot Load [1:0] + AQ_GlobalPinStatus_APPIA.u0.bits_0.mdioBootLoad + + + + Value of MDIO Boot Load pins + + 0x3 = PHY #0 Slave Daisy Chain Boot + 0x2 = PHY #0 Master Daisy Chain Boot from Flash + 0x1 = MDIO Boot Load + 0x0 = Boot from Flash (PHY #0 only) + + + Notes: + NOTES: + + PHY #0 is the primary PHY, and PHY #1 is the secondary PHY + + PHY #1 is always in Slave Daisy Chain Boot from Flash when set to 0x2 or 0x3. */ + unsigned int mdioBootLoad : 2; /* 1E.C840.E:D RO */ + /* Value of MDIO Boot Load pins + + 0x3 = PHY #0 Slave Daisy Chain Boot + 0x2 = PHY #0 Master Daisy Chain Boot from Flash + 0x1 = MDIO Boot Load + 0x0 = Boot from Flash (PHY #0 only) + */ + unsigned int reserved0 : 1; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalPinStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Daisy Chain Status: 1E.C842 */ +/* Global Daisy Chain Status: 1E.C842 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Daisy Chain Status */ + union + { + struct + { + /*! \brief 1E.C842.F:0 RO Rx Daisy Chain Calculated CRC [F:0] + AQ_GlobalDaisyChainStatus_APPIA.u0.bits_0.rxDaisyChainCalculatedCrc + + + + Rx Daisy Chain Calculated CRC + + + Notes: + This is the calculated daisy chain CRC. */ + unsigned int rxDaisyChainCalculatedCrc : 16; /* 1E.C842.F:0 RO */ + /* Rx Daisy Chain Calculated CRC + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalDaisyChainStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Fault Message: 1E.C850 */ +/* Global Fault Message: 1E.C850 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Fault Message */ + union + { + struct + { + /*! \brief 1E.C850.F:0 RO Message [F:0] + AQ_GlobalFaultMessage_APPIA.u0.bits_0.message + + + + Error code describing fault + + Notes: + Code 0x8001: Firmware not compatible with chip architecture. This fault occurs when firmware compiled for a different Tensilica core is loaded. + Code 0x8002: VCO calibration failed. This occurs when the main PLLs on chip fail to lock: this is not possible to trigger. + Code 0x8003: XAUI calibration failed. This occurs when the XAUI PLLs fail to lock: this is not possible to trigger. + Code 0x8004: Failed to set operating voltages via PMBus. This only occurs when the processor has control over power supply voltage via an attached PMBus device and there is a protocol error on the I2C bus: this is not possible to trigger. + Code 0x8005: Unexpected device ID. This occurs if the device ID programmed into the internal E-Fuse registers in not valid: this is not possible to trigger. + Code 0x8006: Computed checksum does not match expected checksum. This occurs when the FLASH checksum check performed at boot time fails. This only occurs when the system boots from FLASH. + Code 0x8007: Detected a bit error in static memory. To trigger, corrupt one of the static regions. + Code 0xC001: Illegal Instruction exception. This occurs when the processor attempts to execute an illegal instruction. To trigger this, write an illegal instruction to program memory. It's possible that the bit error check will trigger before the illegal instruction is executed. + Code 0xC002 Instruction Fetch Error. Internal physical address or a data error during instruction fetch: this is not possible to trigger. + Code 0xC003 Load Store Error. Internal physical address or data error during load store operation: this is not possible to trigger.. + Code 0xC004 Privileged Instruction. Attempt to execute a privileged operation without sufficient privilege: this is not possible to trigger. + Code 0xC005 Unaligned Load or Store. Attempt to load or store data at an address which cannot be handled due to alignment: this is not possible to trigger. + Code 0xC006 Instruction fetch from prohibited space: this is not possible to trigger. + Code 0xC007 Data load from prohibited space: this is not possible to trigger. + Code 0xC008 Data store into prohibited space: this is not possible to trigger. */ + unsigned int message : 16; /* 1E.C850.F:0 RO */ + /* Error code describing fault */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalFaultMessage_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Primary Status: 1E.C851 */ +/* Global Primary Status: 1E.C851 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Primary Status */ + union + { + struct + { + /*! \brief 1E.C851.0 RO Primary Status + AQ_GlobalPrimaryStatus_APPIA.u0.bits_0.primaryStatus + + + + 1 = PHY is the primary PHY + 0 = PHY is is secondary PHY + + */ + unsigned int primaryStatus : 1; /* 1E.C851.0 RO */ + /* 1 = PHY is the primary PHY + 0 = PHY is is secondary PHY + */ + unsigned int reserved0 : 15; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalPrimaryStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Cable Diagnostic Impedance: 1E.C880 */ +/* Global Cable Diagnostic Impedance: 1E.C880 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C880.2:0 RO Pair A Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.pairAReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_4 : 3; /* 1E.C880.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C880.3 RO Reserved 4 + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.reserved_4 + + + + Reserved for future use + + */ + unsigned int reserved_4 : 1; /* 1E.C880.3 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C880.6:4 RO Pair A Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.pairAReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_3 : 3; /* 1E.C880.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C880.7 RO Reserved 3 + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.reserved_3 + + + + Reserved for future use + + */ + unsigned int reserved_3 : 1; /* 1E.C880.7 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C880.A:8 RO Pair A Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.pairAReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_2 : 3; /* 1E.C880.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C880.B RO Reserved 2 + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.reserved_2 + + + + Reserved for future use + + */ + unsigned int reserved_2 : 1; /* 1E.C880.B RO */ + /* Reserved for future use + */ + /*! \brief 1E.C880.E:C RO Pair A Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.pairAReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_1 : 3; /* 1E.C880.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C880.F RO Reserved 1 + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.reserved_1 + + + + Reserved for future use + + */ + unsigned int reserved_1 : 1; /* 1E.C880.F RO */ + /* Reserved for future use + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C881.2:0 RO Pair B Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.pairBReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_4 : 3; /* 1E.C881.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C881.3 RO Reserved 8 + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.reserved_8 + + + + Reserved for future use + + */ + unsigned int reserved_8 : 1; /* 1E.C881.3 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C881.6:4 RO Pair B Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.pairBReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_3 : 3; /* 1E.C881.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C881.7 RO Reserved 7 + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.reserved_7 + + + + Reserved for future use + + */ + unsigned int reserved_7 : 1; /* 1E.C881.7 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C881.A:8 RO Pair B Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.pairBReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_2 : 3; /* 1E.C881.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C881.B RO Reserved 6 + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.reserved_6 + + + + Reserved for future use + + */ + unsigned int reserved_6 : 1; /* 1E.C881.B RO */ + /* Reserved for future use + */ + /*! \brief 1E.C881.E:C RO Pair B Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.pairBReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_1 : 3; /* 1E.C881.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C881.F RO Reserved 5 + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.reserved_5 + + + + Reserved for future use + + */ + unsigned int reserved_5 : 1; /* 1E.C881.F RO */ + /* Reserved for future use + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C882.2:0 RO Pair C Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.pairCReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_4 : 3; /* 1E.C882.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C882.3 RO Reserved 12 + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.reserved_12 + + + + Reserved for future use + + */ + unsigned int reserved_12 : 1; /* 1E.C882.3 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C882.6:4 RO Pair C Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.pairCReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_3 : 3; /* 1E.C882.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C882.7 RO Reserved 11 + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.reserved_11 + + + + Reserved for future use + + */ + unsigned int reserved_11 : 1; /* 1E.C882.7 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C882.A:8 RO Pair C Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.pairCReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_2 : 3; /* 1E.C882.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C882.B RO Reserved 10 + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.reserved_10 + + + + Reserved for future use + + */ + unsigned int reserved_10 : 1; /* 1E.C882.B RO */ + /* Reserved for future use + */ + /*! \brief 1E.C882.E:C RO Pair C Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.pairCReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_1 : 3; /* 1E.C882.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C882.F RO Reserved 9 + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.reserved_9 + + + + Reserved for future use + + */ + unsigned int reserved_9 : 1; /* 1E.C882.F RO */ + /* Reserved for future use + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C883.2:0 RO Pair D Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.pairDReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_4 : 3; /* 1E.C883.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C883.3 RO Reserved 16 + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.reserved_16 + + + + Reserved for future use + + */ + unsigned int reserved_16 : 1; /* 1E.C883.3 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C883.6:4 RO Pair D Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.pairDReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_3 : 3; /* 1E.C883.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C883.7 RO Reserved 15 + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.reserved_15 + + + + Reserved for future use + + */ + unsigned int reserved_15 : 1; /* 1E.C883.7 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C883.A:8 RO Pair D Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.pairDReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_2 : 3; /* 1E.C883.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C883.B RO Reserved 14 + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.reserved_14 + + + + Reserved for future use + + */ + unsigned int reserved_14 : 1; /* 1E.C883.B RO */ + /* Reserved for future use + */ + /*! \brief 1E.C883.E:C RO Pair D Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.pairDReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_1 : 3; /* 1E.C883.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C883.F RO Reserved 13 + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.reserved_13 + + + + Reserved for future use + + */ + unsigned int reserved_13 : 1; /* 1E.C883.F RO */ + /* Reserved for future use + */ + } bits_3; + uint16_t word_3; + } u3; +} AQ_GlobalCableDiagnosticImpedance_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Status: 1E.C884 */ +/* Global Status: 1E.C884 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Status */ + union + { + struct + { + /*! \brief 1E.C884.7:0 RO Cable Length [7:0] + AQ_GlobalStatus_APPIA.u0.bits_0.cableLength + + + + The estimated length of the cable in meters + + + Notes: + The length of the cable shown here is estimated from the cable diagnostic engine and should be accurate to +/-1m. */ + unsigned int cableLength : 8; /* 1E.C884.7:0 RO */ + /* The estimated length of the cable in meters + */ + /*! \brief 1E.C884.F:8 RO Reserved Status 0 [7:0] + AQ_GlobalStatus_APPIA.u0.bits_0.reservedStatus_0 + + + + Reserved for future use + + */ + unsigned int reservedStatus_0 : 8; /* 1E.C884.F:8 RO */ + /* Reserved for future use + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Reserved Status: 1E.C885 */ +/* Global Reserved Status: 1E.C885 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Reserved Status */ + union + { + struct + { + /*! \brief 1E.C885.7:0 ROSPD ROM Revision [7:0] + AQ_GlobalReservedStatus_APPIA.u0.bits_0.romRevision + + Provisionable Default = 0x00 + + ROM Revision Number + + + Notes: + Customers may receive multiple ROM images that differ only in their provisioning. This field is used to differentiate those images. This field is used in conjunction with the firmware major and minor revision numbers to uniquely identify ROM images. */ + unsigned int romRevision : 8; /* 1E.C885.7:0 ROSPD Provisionable Default = 0x00 */ + /* ROM Revision Number + */ + /*! \brief 1E.C885.9:8 ROSPD XENPAK NVR Status [1:0] + AQ_GlobalReservedStatus_APPIA.u0.bits_0.xenpakNvrStatus + + Provisionable Default = 0x0 + + Status of XENPAK NVR: + 0: NVR not enabled + 1: Last NVR operation succeeded + 2: Last NVR operation failed + 3: Reserved + + + Notes: + XENPAK register space is mirrored in NVR (SPI ROM). This register indicates the status of the last NVR operation. */ + unsigned int xenpakNvrStatus : 2; /* 1E.C885.9:8 ROSPD Provisionable Default = 0x0 */ + /* Status of XENPAK NVR: + 0: NVR not enabled + 1: Last NVR operation succeeded + 2: Last NVR operation failed + 3: Reserved + */ + /*! \brief 1E.C885.F:A RO Nearly Seconds MSW[5:0] + AQ_GlobalReservedStatus_APPIA.u0.bits_0.nearlySecondsMSW + + + + Bits 16 to 21 of the 22 bit "Nearly Seconds" uptime counter. + + + Notes: + The "Nearly Seconds" counter is incremented every 1024 milliseconds. */ + unsigned int nearlySecondsMSW : 6; /* 1E.C885.F:A RO */ + /* Bits 16 to 21 of the 22 bit "Nearly Seconds" uptime counter. + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Reserved Status */ + union + { + struct + { + /*! \brief 1E.C886.F:0 RO Nearly Seconds LSW[F:0] + AQ_GlobalReservedStatus_APPIA.u1.bits_1.nearlySecondsLSW + + + + Bits 0 to 15 of the 22 bit "Nearly Seconds" uptime counter. + + + Notes: + The "Nearly Seconds" counter is incremented every 1024 milliseconds. */ + unsigned int nearlySecondsLSW : 16; /* 1E.C886.F:0 RO */ + /* Bits 0 to 15 of the 22 bit "Nearly Seconds" uptime counter. + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalReservedStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Alarms: 1E.CC00 */ +/* Global Alarms: 1E.CC00 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Alarms */ + union + { + struct + { + /*! \brief 1E.CC00.0 LH Reserved Alarm D + AQ_GlobalAlarms_APPIA.u0.bits_0.reservedAlarmD + + + + Reserved for future use + + */ + unsigned int reservedAlarmD : 1; /* 1E.CC00.0 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC00.1 LH Reserved Alarm C + AQ_GlobalAlarms_APPIA.u0.bits_0.reservedAlarmC + + + + Reserved for future use + + */ + unsigned int reservedAlarmC : 1; /* 1E.CC00.1 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC00.2 LH Reserved Alarm B + AQ_GlobalAlarms_APPIA.u0.bits_0.reservedAlarmB + + + + Reserved for future use + + */ + unsigned int reservedAlarmB : 1; /* 1E.CC00.2 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC00.3 LH Reserved Alarm A + AQ_GlobalAlarms_APPIA.u0.bits_0.reservedAlarmA + + + + Reserved for future use + + */ + unsigned int reservedAlarmA : 1; /* 1E.CC00.3 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC00.4 LH Device Fault + AQ_GlobalAlarms_APPIA.u0.bits_0.deviceFault + + + + 1 = Fault + + Notes: + When set, a fault has been detected by the uP and the associated 16 bit error code is visible in See Global Configuration Fault Message: Address 1E.C850 */ + unsigned int deviceFault : 1; /* 1E.CC00.4 LH */ + /* 1 = Fault */ + unsigned int reserved2 : 1; + /*! \brief 1E.CC00.6 LH Reset completed + AQ_GlobalAlarms_APPIA.u0.bits_0.resetCompleted + + + + 1 = Chip wide reset completed + + Notes: + This bit is set by the microprocessor when it has completed it's initialization sequence. This bit is mirrored in 1.CC02.0 */ + unsigned int resetCompleted : 1; /* 1E.CC00.6 LH */ + /* 1 = Chip wide reset completed */ + unsigned int reserved1 : 4; + /*! \brief 1E.CC00.B LH Low Temperature Warning + AQ_GlobalAlarms_APPIA.u0.bits_0.lowTemperatureWarning + + + + 1 = Low temperature warning threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int lowTemperatureWarning : 1; /* 1E.CC00.B LH */ + /* 1 = Low temperature warning threshold has been exceeded + */ + /*! \brief 1E.CC00.C LH High Temperature Warning + AQ_GlobalAlarms_APPIA.u0.bits_0.highTemperatureWarning + + + + 1 = High temperature warning threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int highTemperatureWarning : 1; /* 1E.CC00.C LH */ + /* 1 = High temperature warning threshold has been exceeded + */ + /*! \brief 1E.CC00.D LH Low Temperature Failure + AQ_GlobalAlarms_APPIA.u0.bits_0.lowTemperatureFailure + + + + 1 = Low temperature failure threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int lowTemperatureFailure : 1; /* 1E.CC00.D LH */ + /* 1 = Low temperature failure threshold has been exceeded + */ + /*! \brief 1E.CC00.E LH High Temperature Failure + AQ_GlobalAlarms_APPIA.u0.bits_0.highTemperatureFailure + + + + 1 = High temperature failure threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int highTemperatureFailure : 1; /* 1E.CC00.E LH */ + /* 1 = High temperature failure threshold has been exceeded + */ + unsigned int reserved0 : 1; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Alarms */ + union + { + struct + { + /*! \brief 1E.CC01.0 LH Diagnostic Alarm + AQ_GlobalAlarms_APPIA.u1.bits_1.diagnosticAlarm + + + + 1 = Alarm triggered by a write to 1E.C470.7 + + + Notes: + A diagnostic alarm use to test system alarm circuitry */ + unsigned int diagnosticAlarm : 1; /* 1E.CC01.0 LH */ + /* 1 = Alarm triggered by a write to 1E.C470.7 + */ + unsigned int reserved1 : 6; + /*! \brief 1E.CC01.7 LH MDIO Command Handling Overflow + AQ_GlobalAlarms_APPIA.u1.bits_1.mdioCommandHandlingOverflow + + + + 1 = PHY was issued more MDIO requests than it could service in it's request buffer + + + Notes: + Assertion of this bit means that more MDIO commands were issued than FW could handle. */ + unsigned int mdioCommandHandlingOverflow : 1; /* 1E.CC01.7 LH */ + /* 1 = PHY was issued more MDIO requests than it could service in it's request buffer + */ + /*! \brief 1E.CC01.C:8 LH Reserved Alarms [4:0] + AQ_GlobalAlarms_APPIA.u1.bits_1.reservedAlarms + + + + Reserved for future use + + */ + unsigned int reservedAlarms : 5; /* 1E.CC01.C:8 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC01.D RO XENPAK Alarm + AQ_GlobalAlarms_APPIA.u1.bits_1.xenpakAlarm + + + + 1 = XENPAK Alarm + + + Notes: + This alarm is performed by H/W. */ + unsigned int xenpakAlarm : 1; /* 1E.CC01.D RO */ + /* 1 = XENPAK Alarm + */ + /*! \brief 1E.CC01.E LH Smart Power-Down Entered + AQ_GlobalAlarms_APPIA.u1.bits_1.smartPower_downEntered + + + + 1 = Smart Power-Down State Entered + + + Notes: + When this bit is set, it indicates that the Smart Power-Down state was entered */ + unsigned int smartPower_downEntered : 1; /* 1E.CC01.E LH */ + /* 1 = Smart Power-Down State Entered + */ + unsigned int reserved0 : 1; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Alarms */ + union + { + struct + { + /*! \brief 1E.CC02.0 LH Watchdog Timer Alarm + AQ_GlobalAlarms_APPIA.u2.bits_2.watchdogTimerAlarm + + + + 1 = Watchdog timer alarm + + */ + unsigned int watchdogTimerAlarm : 1; /* 1E.CC02.0 LH */ + /* 1 = Watchdog timer alarm + */ + /*! \brief 1E.CC02.1 LH MDIO Timeout Error + AQ_GlobalAlarms_APPIA.u2.bits_2.mdioTimeoutError + + + + 1 = MDIO timeout detected + + */ + unsigned int mdioTimeoutError : 1; /* 1E.CC02.1 LH */ + /* 1 = MDIO timeout detected + */ + /*! \brief 1E.CC02.2 LH MDIO MMD Error + AQ_GlobalAlarms_APPIA.u2.bits_2.mdioMMD_Error + + + + 1 = Invalid MMD address detected + + */ + unsigned int mdioMMD_Error : 1; /* 1E.CC02.2 LH */ + /* 1 = Invalid MMD address detected + */ + unsigned int reserved2 : 2; + /*! \brief 1E.CC02.5 LRF Tx Enable State Change + AQ_GlobalAlarms_APPIA.u2.bits_2.txEnableStateChange + + + + 1 = TX_EN pin has changed state + + */ + unsigned int txEnableStateChange : 1; /* 1E.CC02.5 LRF */ + /* 1 = TX_EN pin has changed state + */ + unsigned int reserved1 : 2; + /*! \brief 1E.CC02.9:8 LH uP IRAM Parity Error [1:0] + AQ_GlobalAlarms_APPIA.u2.bits_2.upIramParityError + + + + 1 = Parity error detected in the uP IRAM + + + Notes: + Bit 0 indicates a parity error was detected in the uP IRAM but was corrected. + Bit 1 indicates a multiple parity errors were detected in the uP IRAM and could not be corrected. + The uP IRAM is protected with ECC. */ + unsigned int upIramParityError : 2; /* 1E.CC02.9:8 LH */ + /* 1 = Parity error detected in the uP IRAM + */ + /*! \brief 1E.CC02.A LH uP DRAM Parity Error + AQ_GlobalAlarms_APPIA.u2.bits_2.upDramParityError + + + + 1 = Parity error detected in the uP DRAM + + */ + unsigned int upDramParityError : 1; /* 1E.CC02.A LH */ + /* 1 = Parity error detected in the uP DRAM + */ + unsigned int reserved0 : 3; + /*! \brief 1E.CC02.E LH Mailbox Operation: Complete + AQ_GlobalAlarms_APPIA.u2.bits_2.mailboxOperation_Complete + + + + 1 = Mailbox operation is complete + + + Notes: + Mailbox interface is ready interrupt for registers See Global Vendor Specific Control - Address 1E.C000 - See Global Vendor Specific Provisioning 5 - Address 1E.C404 */ + unsigned int mailboxOperation_Complete : 1; /* 1E.CC02.E LH */ + /* 1 = Mailbox operation is complete + */ + /*! \brief 1E.CC02.F LH NVR Operation Complete + AQ_GlobalAlarms_APPIA.u2.bits_2.nvrOperationComplete + + + + 1 = NVR operation is complete + + + Notes: + NVR interface is ready interrupt for registers See Global NVR Interface 1: Address 1E.100 - See Global NVR Provisioning Data MSW - Address 1E.17 . */ + unsigned int nvrOperationComplete : 1; /* 1E.CC02.F LH */ + /* 1 = NVR operation is complete + */ + } bits_2; + uint16_t word_2; + } u2; +} AQ_GlobalAlarms_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Interrupt Mask: 1E.D400 */ +/* Global Interrupt Mask: 1E.D400 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Interrupt Mask */ + union + { + struct + { + /*! \brief 1E.D400.0 R/WPD Reserved Alarm D Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.reservedAlarmDMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmDMask : 1; /* 1E.D400.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D400.1 R/WPD Reserved Alarm C Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.reservedAlarmCMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmCMask : 1; /* 1E.D400.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D400.2 R/WPD Reserved Alarm B Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.reservedAlarmBMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmBMask : 1; /* 1E.D400.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D400.3 R/WPD Reserved Alarm A Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.reservedAlarmAMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmAMask : 1; /* 1E.D400.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D400.4 R/WPD Device Fault Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.deviceFaultMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int deviceFaultMask : 1; /* 1E.D400.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved2 : 1; + /*! \brief 1E.D400.6 R/WPD Reset completed Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.resetCompletedMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int resetCompletedMask : 1; /* 1E.D400.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved1 : 4; + /*! \brief 1E.D400.B R/WPD Low Temperature Warning Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.lowTemperatureWarningMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int lowTemperatureWarningMask : 1; /* 1E.D400.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D400.C R/WPD High Temperature Warning Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.highTemperatureWarningMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int highTemperatureWarningMask : 1; /* 1E.D400.C R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D400.D R/WPD Low Temperature Failure Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.lowTemperatureFailureMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int lowTemperatureFailureMask : 1; /* 1E.D400.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D400.E R/WPD High Temperature Failure Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.highTemperatureFailureMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int highTemperatureFailureMask : 1; /* 1E.D400.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved0 : 1; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Interrupt Mask */ + union + { + struct + { + /*! \brief 1E.D401.0 R/WPD Diagnostic Alarm Mask + AQ_GlobalInterruptMask_APPIA.u1.bits_1.diagnosticAlarmMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int diagnosticAlarmMask : 1; /* 1E.D401.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int reserved1 : 6; + /*! \brief 1E.D401.7 R/WPD MDIO Command Handling Overflow Mask + AQ_GlobalInterruptMask_APPIA.u1.bits_1.mdioCommandHandlingOverflowMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int mdioCommandHandlingOverflowMask : 1; /* 1E.D401.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D401.C:8 R/WPD Reserved Alarms Mask [4:0] + AQ_GlobalInterruptMask_APPIA.u1.bits_1.reservedAlarmsMask + + Provisionable Default = 0x00 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmsMask : 5; /* 1E.D401.C:8 R/WPD Provisionable Default = 0x00 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D401.D R/WPD XENPAK Alarm Mask + AQ_GlobalInterruptMask_APPIA.u1.bits_1.xenpakAlarmMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int xenpakAlarmMask : 1; /* 1E.D401.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D401.E R/WPD Smart Power-Down Entered Mask + AQ_GlobalInterruptMask_APPIA.u1.bits_1.smartPower_downEnteredMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int smartPower_downEnteredMask : 1; /* 1E.D401.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int reserved0 : 1; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Interrupt Mask */ + union + { + struct + { + /*! \brief 1E.D402.0 R/WPD Watchdog Timer Alarm Mask + AQ_GlobalInterruptMask_APPIA.u2.bits_2.watchdogTimerAlarmMask + + Provisionable Default = 0x1 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int watchdogTimerAlarmMask : 1; /* 1E.D402.0 R/WPD Provisionable Default = 0x1 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D402.1 R/WPD MDIO Timeout Error Mask + AQ_GlobalInterruptMask_APPIA.u2.bits_2.mdioTimeoutErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int mdioTimeoutErrorMask : 1; /* 1E.D402.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D402.2 R/WPD MDIO MMD Error Mask + AQ_GlobalInterruptMask_APPIA.u2.bits_2.mdioMMD_ErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int mdioMMD_ErrorMask : 1; /* 1E.D402.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved2 : 2; + /*! \brief 1E.D402.5 R/WPD Tx Enable State Change Mask + AQ_GlobalInterruptMask_APPIA.u2.bits_2.txEnableStateChangeMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int txEnableStateChangeMask : 1; /* 1E.D402.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved1 : 2; + /*! \brief 1E.D402.9:8 R/WPD uP IRAM Parity Error Mask [1:0] + AQ_GlobalInterruptMask_APPIA.u2.bits_2.upIramParityErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int upIramParityErrorMask : 2; /* 1E.D402.9:8 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D402.A R/WPD uP DRAM Parity Error Mask + AQ_GlobalInterruptMask_APPIA.u2.bits_2.upDramParityErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int upDramParityErrorMask : 1; /* 1E.D402.A R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int reserved0 : 3; + /*! \brief 1E.D402.E R/WPD Mailbox Operation Complete Mask + AQ_GlobalInterruptMask_APPIA.u2.bits_2.mailboxOperationCompleteMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + Notes: + Mailbox interface is ready interrupt for registers See Global Vendor Specific Control - Address 1E.C000 - See Global Vendor Specific Provisioning 5 - Address 1E.C404 */ + unsigned int mailboxOperationCompleteMask : 1; /* 1E.D402.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D402.F R/WPD NVR Operation Complete Mask + AQ_GlobalInterruptMask_APPIA.u2.bits_2.nvrOperationCompleteMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + Notes: + NVR interface is ready interrupt for registers See Global NVR Interface 1: Address 1E.100 - See Global NVR Provisioning Data MSW - Address 1E.17 */ + unsigned int nvrOperationCompleteMask : 1; /* 1E.D402.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + } bits_2; + uint16_t word_2; + } u2; +} AQ_GlobalInterruptMask_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Chip-Wide Standard Interrupt Flags: 1E.FC00 */ +/* Global Chip-Wide Standard Interrupt Flags: 1E.FC00 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Chip-Wide Standard Interrupt Flags */ + union + { + struct + { + /*! \brief 1E.FC00.0 RO All Vendor Alarms Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.allVendorAlarmsInterrupt + + + + 1 = Interrupt in all vendor alarms + + + Notes: + An interrupt was generated from status register ( See Global Chip-Wide LASI Vendor Interrupt Flags: Address 1E.FC01 ) and the corresponding mask register. ( See Global Interrupt LASI Mask: Address 1E.FF01 ) */ + unsigned int allVendorAlarmsInterrupt : 1; /* 1E.FC00.0 RO */ + /* 1 = Interrupt in all vendor alarms + */ + unsigned int reserved0 : 5; + /*! \brief 1E.FC00.6 RO GbE Standard Alarms Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.gbeStandardAlarmsInterrupt + + + + 1 = Interrupt in GbE standard alarms + + + Notes: + An interrupt was generated from the TGE core. */ + unsigned int gbeStandardAlarmsInterrupt : 1; /* 1E.FC00.6 RO */ + /* 1 = Interrupt in GbE standard alarms + */ + /*! \brief 1E.FC00.7 RO Autonegotiation Standard Alarms 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.autonegotiationStandardAlarms_2Interrupt + + + + 1 = Interrupt in Autonegotiation standard alarms 2 + + + Notes: + An interrupt was generated from status register ( See Autonegotiation 10GBASE-T Status Register - Address 7.21 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int autonegotiationStandardAlarms_2Interrupt : 1; /* 1E.FC00.7 RO */ + /* 1 = Interrupt in Autonegotiation standard alarms 2 + */ + /*! \brief 1E.FC00.8 RO Autonegotiation Standard Alarms 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.autonegotiationStandardAlarms_1Interrupt + + + + 1 = Interrupt in Autonegotiation standard alarms 1 + + + Notes: + An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See Autonegotiation Standard LASI Interrupt Mask 1: Address 7.D000 ) */ + unsigned int autonegotiationStandardAlarms_1Interrupt : 1; /* 1E.FC00.8 RO */ + /* 1 = Interrupt in Autonegotiation standard alarms 1 + */ + /*! \brief 1E.FC00.9 RO PHY XS Standard Alarms 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.phyXS_StandardAlarms_2Interrupt + + + + 1 = Interrupt in PHY XS standard alarms 2 + + + Notes: + An interrupt was generated from the status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int phyXS_StandardAlarms_2Interrupt : 1; /* 1E.FC00.9 RO */ + /* 1 = Interrupt in PHY XS standard alarms 2 + */ + /*! \brief 1E.FC00.A RO PHY XS Standard Alarms 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.phyXS_StandardAlarms_1Interrupt + + + + 1 = Interrupt in PHY XS standard alarms 1 + + + Notes: + An interrupt was generated from the status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ + unsigned int phyXS_StandardAlarms_1Interrupt : 1; /* 1E.FC00.A RO */ + /* 1 = Interrupt in PHY XS standard alarms 1 + */ + /*! \brief 1E.FC00.B RO PCS Standard Alarm 3 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.pcsStandardAlarm_3Interrupt + + + + 1 = Interrupt in PCS standard alarms 3 + + + Notes: + An interrupt was generated from status register ( See PCS 10GBASE-T Status 2 - Address 3.21 ) and the corresponding mask register. ( See PCS Standard Interrupt Mask 1 - Address 3.E021 ) */ + unsigned int pcsStandardAlarm_3Interrupt : 1; /* 1E.FC00.B RO */ + /* 1 = Interrupt in PCS standard alarms 3 + */ + /*! \brief 1E.FC00.C RO PCS Standard Alarm 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.pcsStandardAlarm_2Interrupt + + + + 1 = Interrupt in PCS standard alarms 2 + + + Notes: + An interrupt was generated from status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int pcsStandardAlarm_2Interrupt : 1; /* 1E.FC00.C RO */ + /* 1 = Interrupt in PCS standard alarms 2 + */ + /*! \brief 1E.FC00.D RO PCS Standard Alarm 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.pcsStandardAlarm_1Interrupt + + + + 1 = Interrupt in PCS standard alarms 1 + + + Notes: + An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ + unsigned int pcsStandardAlarm_1Interrupt : 1; /* 1E.FC00.D RO */ + /* 1 = Interrupt in PCS standard alarms 1 + */ + /*! \brief 1E.FC00.E RO PMA Standard Alarm 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.pmaStandardAlarm_2Interrupt + + + + 1 = Interrupt in PMA standard alarms 2 + + + Notes: + An interrupt was generated from either bit 1.8.B or 1.8.A. + An interrupt was generated from status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int pmaStandardAlarm_2Interrupt : 1; /* 1E.FC00.E RO */ + /* 1 = Interrupt in PMA standard alarms 2 + */ + /*! \brief 1E.FC00.F RO PMA Standard Alarm 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.pmaStandardAlarm_1Interrupt + + + + 1 = Interrupt in PMA standard alarms 1 + + + Notes: + An interrupt was generated from bit 1.1.2. + An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ + unsigned int pmaStandardAlarm_1Interrupt : 1; /* 1E.FC00.F RO */ + /* 1 = Interrupt in PMA standard alarms 1 + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalChip_wideStandardInterruptFlags_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Chip-Wide Vendor Interrupt Flags: 1E.FC01 */ +/* Global Chip-Wide Vendor Interrupt Flags: 1E.FC01 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Chip-Wide Vendor Interrupt Flags */ + union + { + struct + { + /*! \brief 1E.FC01.0 RO Global Alarms 3 Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.globalAlarms_3Interrupt + + + + 1 = Interrupt in Global alarms 3 + + + Notes: + An interrupt was generated from status register ( See Global Vendor Alarms 2: Address 1E.CC01 ) and the corresponding mask register. ( See Global LASI Interrupt Mask 2: Address 1E.D401 ) */ + unsigned int globalAlarms_3Interrupt : 1; /* 1E.FC01.0 RO */ + /* 1 = Interrupt in Global alarms 3 + */ + /*! \brief 1E.FC01.1 RO Global Alarms 2 Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.globalAlarms_2Interrupt + + + + 1 = Interrupt in Global alarms 2 + + + Notes: + An interrupt was generated from status register ( See Global Alarms 2: Address 1E.CC01 ) and the corresponding mask register. ( See Global LASI Interrupt Mask 2: Address 1E.D401 ) */ + unsigned int globalAlarms_2Interrupt : 1; /* 1E.FC01.1 RO */ + /* 1 = Interrupt in Global alarms 2 + */ + /*! \brief 1E.FC01.2 RO Global Alarms 1 Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.globalAlarms_1Interrupt + + + + 1 = Interrupt in Global alarms 1 + + + Notes: + An interrupt was generated from status register ( See Global Vendor Alarms 1 - Address 1E.CC00 ) and the corresponding mask register. ( See Global Vendor Interrupt Mask - Address 1E.D400 ) */ + unsigned int globalAlarms_1Interrupt : 1; /* 1E.FC01.2 RO */ + /* 1 = Interrupt in Global alarms 1 + */ + unsigned int reserved0 : 8; + /*! \brief 1E.FC01.B RO GbE Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.gbeVendorAlarmInterrupt + + + + 1 = Interrupt in GbE vendor specific alarm + + + Notes: + A GbE alarm was generated. ( See GbE PHY Vendor Global LASI Interrupt Flags 1: Address 1D.FC00 ) */ + unsigned int gbeVendorAlarmInterrupt : 1; /* 1E.FC01.B RO */ + /* 1 = Interrupt in GbE vendor specific alarm + */ + /*! \brief 1E.FC01.C RO Autonegotiation Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.autonegotiationVendorAlarmInterrupt + + + + 1 = Interrupt in Autonegotiation vendor specific alarm + + + Notes: + An Autonegotiation alarm was generated. ( See Autonegotiation Vendor Global LASI Interrupt Flags 1: Address 7.FC00 ) */ + unsigned int autonegotiationVendorAlarmInterrupt : 1; /* 1E.FC01.C RO */ + /* 1 = Interrupt in Autonegotiation vendor specific alarm + */ + /*! \brief 1E.FC01.D RO PHY XS Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.phyXS_VendorAlarmInterrupt + + + + 1 = Interrupt in PHY XS vendor specific alarm + + + Notes: + A PHY XS alarm was generated. ( See PHY XS Vendor Global LASI Interrupt Flags 1: Address 4.FC00 ) */ + unsigned int phyXS_VendorAlarmInterrupt : 1; /* 1E.FC01.D RO */ + /* 1 = Interrupt in PHY XS vendor specific alarm + */ + /*! \brief 1E.FC01.E RO PCS Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.pcsVendorAlarmInterrupt + + + + 1 = Interrupt in PCS vendor specific alarm + + + Notes: + A PCS alarm was generated. ( See PHY XS Vendor Global Interrupt Flags 1- Address 4.F800 ) */ + unsigned int pcsVendorAlarmInterrupt : 1; /* 1E.FC01.E RO */ + /* 1 = Interrupt in PCS vendor specific alarm + */ + /*! \brief 1E.FC01.F RO PMA Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.pmaVendorAlarmInterrupt + + + + 1 = Interrupt in PMA vendor specific alarm + + + Notes: + A PMA alarm was generated. ( See PHY XS Vendor Global Interrupt Flags 1- Address 4.F800 ) */ + unsigned int pmaVendorAlarmInterrupt : 1; /* 1E.FC01.F RO */ + /* 1 = Interrupt in PMA vendor specific alarm + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalChip_wideVendorInterruptFlags_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Interrupt Chip-Wide Standard Mask: 1E.FF00 */ +/* Global Interrupt Chip-Wide Standard Mask: 1E.FF00 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Interrupt Chip-Wide Standard Mask */ + union + { + struct + { + /*! \brief 1E.FF00.0 R/WPD All Vendor Alarms Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.allVendorAlarmsInterruptMask + + Provisionable Default = 0x1 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int allVendorAlarmsInterruptMask : 1; /* 1E.FF00.0 R/WPD Provisionable Default = 0x1 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved0 : 5; + /*! \brief 1E.FF00.6 R/WPD Gbe Standard Alarms Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.gbeStandardAlarmsInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int gbeStandardAlarmsInterruptMask : 1; /* 1E.FF00.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.7 R/WPD Autonegotiation Standard Alarms 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.autonegotiationStandardAlarms_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int autonegotiationStandardAlarms_2InterruptMask : 1; /* 1E.FF00.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.8 R/WPD Autonegotiation Standard Alarms 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.autonegotiationStandardAlarms_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int autonegotiationStandardAlarms_1InterruptMask : 1; /* 1E.FF00.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.9 R/WPD PHY XS Standard Alarms 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.phyXS_StandardAlarms_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int phyXS_StandardAlarms_2InterruptMask : 1; /* 1E.FF00.9 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.A R/WPD PHY XS Standard Alarms 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.phyXS_StandardAlarms_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int phyXS_StandardAlarms_1InterruptMask : 1; /* 1E.FF00.A R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.B R/WPD PCS Standard Alarm 3 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.pcsStandardAlarm_3InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsStandardAlarm_3InterruptMask : 1; /* 1E.FF00.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.C R/WPD PCS Standard Alarm 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.pcsStandardAlarm_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsStandardAlarm_2InterruptMask : 1; /* 1E.FF00.C R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.D R/WPD PCS Standard Alarm 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.pcsStandardAlarm_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsStandardAlarm_1InterruptMask : 1; /* 1E.FF00.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.E R/WPD PMA Standard Alarm 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.pmaStandardAlarm_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pmaStandardAlarm_2InterruptMask : 1; /* 1E.FF00.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.F R/WPD PMA Standard Alarm 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.pmaStandardAlarm_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pmaStandardAlarm_1InterruptMask : 1; /* 1E.FF00.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalInterruptChip_wideStandardMask_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Interrupt Chip-Wide Vendor Mask: 1E.FF01 */ +/* Global Interrupt Chip-Wide Vendor Mask: 1E.FF01 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Interrupt Chip-Wide Vendor Mask */ + union + { + struct + { + /*! \brief 1E.FF01.0 R/WPD Global Alarms 3 Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.globalAlarms_3InterruptMask + + Provisionable Default = 0x1 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int globalAlarms_3InterruptMask : 1; /* 1E.FF01.0 R/WPD Provisionable Default = 0x1 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.1 R/WPD Global Alarms 2 Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.globalAlarms_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int globalAlarms_2InterruptMask : 1; /* 1E.FF01.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.2 R/WPD Global Alarms 1 Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.globalAlarms_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int globalAlarms_1InterruptMask : 1; /* 1E.FF01.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved0 : 8; + /*! \brief 1E.FF01.B R/WPD GbE Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.gbeVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int gbeVendorAlarmInterruptMask : 1; /* 1E.FF01.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.C R/WPD Autonegotiation Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.autonegotiationVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int autonegotiationVendorAlarmInterruptMask : 1; /* 1E.FF01.C R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.D R/WPD PHY XS Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.phyXS_VendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int phyXS_VendorAlarmInterruptMask : 1; /* 1E.FF01.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.E R/WPD PCS Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.pcsVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsVendorAlarmInterruptMask : 1; /* 1E.FF01.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.F R/WPD PMA Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.pmaVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pmaVendorAlarmInterruptMask : 1; /* 1E.FF01.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalInterruptChip_wideVendorMask_APPIA; + +#endif +/*@}*/ +/*@}*/ diff --git a/qca/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers_Defines.h b/qca/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers_Defines.h new file mode 100644 index 000000000..9c7bb5cb5 --- /dev/null +++ b/qca/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers_Defines.h @@ -0,0 +1,2134 @@ +/*! \file +* This file contains the compiler assist macros and doxygen comments +* for the Global Registers block. +*/ + +/*! \defgroup Global_registers_Defines Global Registers Defines +* This module contains the compiler assist macros and doxygen comments +* for the Global Registers block. +*/ +/*********************************************************************** +* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +* +* $File: //depot/icm/proj/Dena/rev1.0/c/Systems/tools/windows/regMapParser/src/gencheaders.py $ +* +* $Revision: #10 $ +* +* $DateTime: 2014/04/08 16:55:58 $ +* +* $Author: joshd $ +* +* $Label: $ +* +* Description: +* +* This file contains the compiler assist macros for the registers contained in the Global Registers block. +* +* +***********************************************************************/ + + +/*@{*/ +#ifndef AQ_APPIA_GLOBAL_REGS_DEFINES_HEADER +#define AQ_APPIA_GLOBAL_REGS_DEFINES_HEADER + + +/*-----------------------------------------------------------------------------*/ +/*Access macro definitions */ +/*-----------------------------------------------------------------------------*/ +/*! \brief Base register address of structure AQ_GlobalStandardControl_1_APPIA */ +#define AQ_GlobalStandardControl_1_APPIA_baseRegisterAddress 0x0000 +/*! \brief MMD address of structure AQ_GlobalStandardControl_1_APPIA */ +#define AQ_GlobalStandardControl_1_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure softReset in AQ_GlobalStandardControl_1_APPIA */ +#define AQ_GlobalStandardControl_1_APPIA_softReset 0 +/*! \brief Preprocessor variable to relate field to bit position in structure softReset in AQ_GlobalStandardControl_1_APPIA */ +#define bits_AQ_GlobalStandardControl_1_APPIA_softReset u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure softReset in AQ_GlobalStandardControl_1_APPIA */ +#define word_AQ_GlobalStandardControl_1_APPIA_softReset u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure hardReset in AQ_GlobalStandardControl_1_APPIA */ +#define AQ_GlobalStandardControl_1_APPIA_hardReset 0 +/*! \brief Preprocessor variable to relate field to bit position in structure hardReset in AQ_GlobalStandardControl_1_APPIA */ +#define bits_AQ_GlobalStandardControl_1_APPIA_hardReset u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure hardReset in AQ_GlobalStandardControl_1_APPIA */ +#define word_AQ_GlobalStandardControl_1_APPIA_hardReset u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure lowPower in AQ_GlobalStandardControl_1_APPIA */ +#define AQ_GlobalStandardControl_1_APPIA_lowPower 0 +/*! \brief Preprocessor variable to relate field to bit position in structure lowPower in AQ_GlobalStandardControl_1_APPIA */ +#define bits_AQ_GlobalStandardControl_1_APPIA_lowPower u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure lowPower in AQ_GlobalStandardControl_1_APPIA */ +#define word_AQ_GlobalStandardControl_1_APPIA_lowPower u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalStandardDeviceIdentifier_APPIA */ +#define AQ_GlobalStandardDeviceIdentifier_APPIA_baseRegisterAddress 0x0002 +/*! \brief MMD address of structure AQ_GlobalStandardDeviceIdentifier_APPIA */ +#define AQ_GlobalStandardDeviceIdentifier_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure deviceIdMSW in AQ_GlobalStandardDeviceIdentifier_APPIA */ +#define AQ_GlobalStandardDeviceIdentifier_APPIA_deviceIdMSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure deviceIdMSW in AQ_GlobalStandardDeviceIdentifier_APPIA */ +#define bits_AQ_GlobalStandardDeviceIdentifier_APPIA_deviceIdMSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure deviceIdMSW in AQ_GlobalStandardDeviceIdentifier_APPIA */ +#define word_AQ_GlobalStandardDeviceIdentifier_APPIA_deviceIdMSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure deviceIdLSW in AQ_GlobalStandardDeviceIdentifier_APPIA */ +#define AQ_GlobalStandardDeviceIdentifier_APPIA_deviceIdLSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure deviceIdLSW in AQ_GlobalStandardDeviceIdentifier_APPIA */ +#define bits_AQ_GlobalStandardDeviceIdentifier_APPIA_deviceIdLSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure deviceIdLSW in AQ_GlobalStandardDeviceIdentifier_APPIA */ +#define word_AQ_GlobalStandardDeviceIdentifier_APPIA_deviceIdLSW u1.word_1 + +/*! \brief Base register address of structure AQ_GlobalStandardDevicesInPackage_APPIA */ +#define AQ_GlobalStandardDevicesInPackage_APPIA_baseRegisterAddress 0x0005 +/*! \brief MMD address of structure AQ_GlobalStandardDevicesInPackage_APPIA */ +#define AQ_GlobalStandardDevicesInPackage_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define AQ_GlobalStandardDevicesInPackage_APPIA_autonegotiationPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define bits_AQ_GlobalStandardDevicesInPackage_APPIA_autonegotiationPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define word_AQ_GlobalStandardDevicesInPackage_APPIA_autonegotiationPresent u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure tcPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define AQ_GlobalStandardDevicesInPackage_APPIA_tcPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure tcPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define bits_AQ_GlobalStandardDevicesInPackage_APPIA_tcPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure tcPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define word_AQ_GlobalStandardDevicesInPackage_APPIA_tcPresent u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure dteXsPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define AQ_GlobalStandardDevicesInPackage_APPIA_dteXsPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure dteXsPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define bits_AQ_GlobalStandardDevicesInPackage_APPIA_dteXsPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure dteXsPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define word_AQ_GlobalStandardDevicesInPackage_APPIA_dteXsPresent u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure phyXS_Present in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define AQ_GlobalStandardDevicesInPackage_APPIA_phyXS_Present 0 +/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_Present in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define bits_AQ_GlobalStandardDevicesInPackage_APPIA_phyXS_Present u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure phyXS_Present in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define word_AQ_GlobalStandardDevicesInPackage_APPIA_phyXS_Present u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define AQ_GlobalStandardDevicesInPackage_APPIA_pcsPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define bits_AQ_GlobalStandardDevicesInPackage_APPIA_pcsPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define word_AQ_GlobalStandardDevicesInPackage_APPIA_pcsPresent u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure wisPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define AQ_GlobalStandardDevicesInPackage_APPIA_wisPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure wisPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define bits_AQ_GlobalStandardDevicesInPackage_APPIA_wisPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure wisPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define word_AQ_GlobalStandardDevicesInPackage_APPIA_wisPresent u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pmaPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define AQ_GlobalStandardDevicesInPackage_APPIA_pmaPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pmaPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define bits_AQ_GlobalStandardDevicesInPackage_APPIA_pmaPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pmaPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define word_AQ_GlobalStandardDevicesInPackage_APPIA_pmaPresent u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure clause_22RegistersPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define AQ_GlobalStandardDevicesInPackage_APPIA_clause_22RegistersPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure clause_22RegistersPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define bits_AQ_GlobalStandardDevicesInPackage_APPIA_clause_22RegistersPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure clause_22RegistersPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ +#define word_AQ_GlobalStandardDevicesInPackage_APPIA_clause_22RegistersPresent u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalStandardVendorDevicesInPackage_APPIA */ +#define AQ_GlobalStandardVendorDevicesInPackage_APPIA_baseRegisterAddress 0x0006 +/*! \brief MMD address of structure AQ_GlobalStandardVendorDevicesInPackage_APPIA */ +#define AQ_GlobalStandardVendorDevicesInPackage_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure vendorSpecificDevice_2Present in AQ_GlobalStandardVendorDevicesInPackage_APPIA */ +#define AQ_GlobalStandardVendorDevicesInPackage_APPIA_vendorSpecificDevice_2Present 0 +/*! \brief Preprocessor variable to relate field to bit position in structure vendorSpecificDevice_2Present in AQ_GlobalStandardVendorDevicesInPackage_APPIA */ +#define bits_AQ_GlobalStandardVendorDevicesInPackage_APPIA_vendorSpecificDevice_2Present u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure vendorSpecificDevice_2Present in AQ_GlobalStandardVendorDevicesInPackage_APPIA */ +#define word_AQ_GlobalStandardVendorDevicesInPackage_APPIA_vendorSpecificDevice_2Present u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure vendorSpecificDevice_1Present in AQ_GlobalStandardVendorDevicesInPackage_APPIA */ +#define AQ_GlobalStandardVendorDevicesInPackage_APPIA_vendorSpecificDevice_1Present 0 +/*! \brief Preprocessor variable to relate field to bit position in structure vendorSpecificDevice_1Present in AQ_GlobalStandardVendorDevicesInPackage_APPIA */ +#define bits_AQ_GlobalStandardVendorDevicesInPackage_APPIA_vendorSpecificDevice_1Present u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure vendorSpecificDevice_1Present in AQ_GlobalStandardVendorDevicesInPackage_APPIA */ +#define word_AQ_GlobalStandardVendorDevicesInPackage_APPIA_vendorSpecificDevice_1Present u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure clause_22ExtensionPresent in AQ_GlobalStandardVendorDevicesInPackage_APPIA */ +#define AQ_GlobalStandardVendorDevicesInPackage_APPIA_clause_22ExtensionPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure clause_22ExtensionPresent in AQ_GlobalStandardVendorDevicesInPackage_APPIA */ +#define bits_AQ_GlobalStandardVendorDevicesInPackage_APPIA_clause_22ExtensionPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure clause_22ExtensionPresent in AQ_GlobalStandardVendorDevicesInPackage_APPIA */ +#define word_AQ_GlobalStandardVendorDevicesInPackage_APPIA_clause_22ExtensionPresent u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalStandardStatus_2_APPIA */ +#define AQ_GlobalStandardStatus_2_APPIA_baseRegisterAddress 0x0008 +/*! \brief MMD address of structure AQ_GlobalStandardStatus_2_APPIA */ +#define AQ_GlobalStandardStatus_2_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure devicePresent in AQ_GlobalStandardStatus_2_APPIA */ +#define AQ_GlobalStandardStatus_2_APPIA_devicePresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure devicePresent in AQ_GlobalStandardStatus_2_APPIA */ +#define bits_AQ_GlobalStandardStatus_2_APPIA_devicePresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure devicePresent in AQ_GlobalStandardStatus_2_APPIA */ +#define word_AQ_GlobalStandardStatus_2_APPIA_devicePresent u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalStandardPackageIdentifier_APPIA */ +#define AQ_GlobalStandardPackageIdentifier_APPIA_baseRegisterAddress 0x000E +/*! \brief MMD address of structure AQ_GlobalStandardPackageIdentifier_APPIA */ +#define AQ_GlobalStandardPackageIdentifier_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure packageIdMSW in AQ_GlobalStandardPackageIdentifier_APPIA */ +#define AQ_GlobalStandardPackageIdentifier_APPIA_packageIdMSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure packageIdMSW in AQ_GlobalStandardPackageIdentifier_APPIA */ +#define bits_AQ_GlobalStandardPackageIdentifier_APPIA_packageIdMSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure packageIdMSW in AQ_GlobalStandardPackageIdentifier_APPIA */ +#define word_AQ_GlobalStandardPackageIdentifier_APPIA_packageIdMSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure packageIdLSW in AQ_GlobalStandardPackageIdentifier_APPIA */ +#define AQ_GlobalStandardPackageIdentifier_APPIA_packageIdLSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure packageIdLSW in AQ_GlobalStandardPackageIdentifier_APPIA */ +#define bits_AQ_GlobalStandardPackageIdentifier_APPIA_packageIdLSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure packageIdLSW in AQ_GlobalStandardPackageIdentifier_APPIA */ +#define word_AQ_GlobalStandardPackageIdentifier_APPIA_packageIdLSW u1.word_1 + +/*! \brief Base register address of structure AQ_GlobalFirmwareID_APPIA */ +#define AQ_GlobalFirmwareID_APPIA_baseRegisterAddress 0x0020 +/*! \brief MMD address of structure AQ_GlobalFirmwareID_APPIA */ +#define AQ_GlobalFirmwareID_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure firmwareMajorRevisionNumber in AQ_GlobalFirmwareID_APPIA */ +#define AQ_GlobalFirmwareID_APPIA_firmwareMajorRevisionNumber 0 +/*! \brief Preprocessor variable to relate field to bit position in structure firmwareMajorRevisionNumber in AQ_GlobalFirmwareID_APPIA */ +#define bits_AQ_GlobalFirmwareID_APPIA_firmwareMajorRevisionNumber u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure firmwareMajorRevisionNumber in AQ_GlobalFirmwareID_APPIA */ +#define word_AQ_GlobalFirmwareID_APPIA_firmwareMajorRevisionNumber u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure firmwareMinorRevisionNumber in AQ_GlobalFirmwareID_APPIA */ +#define AQ_GlobalFirmwareID_APPIA_firmwareMinorRevisionNumber 0 +/*! \brief Preprocessor variable to relate field to bit position in structure firmwareMinorRevisionNumber in AQ_GlobalFirmwareID_APPIA */ +#define bits_AQ_GlobalFirmwareID_APPIA_firmwareMinorRevisionNumber u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure firmwareMinorRevisionNumber in AQ_GlobalFirmwareID_APPIA */ +#define word_AQ_GlobalFirmwareID_APPIA_firmwareMinorRevisionNumber u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalChipIdentification_APPIA */ +#define AQ_GlobalChipIdentification_APPIA_baseRegisterAddress 0x0021 +/*! \brief MMD address of structure AQ_GlobalChipIdentification_APPIA */ +#define AQ_GlobalChipIdentification_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure chipIdentification in AQ_GlobalChipIdentification_APPIA */ +#define AQ_GlobalChipIdentification_APPIA_chipIdentification 0 +/*! \brief Preprocessor variable to relate field to bit position in structure chipIdentification in AQ_GlobalChipIdentification_APPIA */ +#define bits_AQ_GlobalChipIdentification_APPIA_chipIdentification u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure chipIdentification in AQ_GlobalChipIdentification_APPIA */ +#define word_AQ_GlobalChipIdentification_APPIA_chipIdentification u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalChipRevision_APPIA */ +#define AQ_GlobalChipRevision_APPIA_baseRegisterAddress 0x0022 +/*! \brief MMD address of structure AQ_GlobalChipRevision_APPIA */ +#define AQ_GlobalChipRevision_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure chipRevision in AQ_GlobalChipRevision_APPIA */ +#define AQ_GlobalChipRevision_APPIA_chipRevision 0 +/*! \brief Preprocessor variable to relate field to bit position in structure chipRevision in AQ_GlobalChipRevision_APPIA */ +#define bits_AQ_GlobalChipRevision_APPIA_chipRevision u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure chipRevision in AQ_GlobalChipRevision_APPIA */ +#define word_AQ_GlobalChipRevision_APPIA_chipRevision u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalNvrInterface_APPIA */ +#define AQ_GlobalNvrInterface_APPIA_baseRegisterAddress 0x0100 +/*! \brief MMD address of structure AQ_GlobalNvrInterface_APPIA */ +#define AQ_GlobalNvrInterface_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure nvrExecuteOperation in AQ_GlobalNvrInterface_APPIA */ +#define AQ_GlobalNvrInterface_APPIA_nvrExecuteOperation 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrExecuteOperation in AQ_GlobalNvrInterface_APPIA */ +#define bits_AQ_GlobalNvrInterface_APPIA_nvrExecuteOperation u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrExecuteOperation in AQ_GlobalNvrInterface_APPIA */ +#define word_AQ_GlobalNvrInterface_APPIA_nvrExecuteOperation u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrWriteMode in AQ_GlobalNvrInterface_APPIA */ +#define AQ_GlobalNvrInterface_APPIA_nvrWriteMode 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrWriteMode in AQ_GlobalNvrInterface_APPIA */ +#define bits_AQ_GlobalNvrInterface_APPIA_nvrWriteMode u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrWriteMode in AQ_GlobalNvrInterface_APPIA */ +#define word_AQ_GlobalNvrInterface_APPIA_nvrWriteMode u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure freezeNvrCrc in AQ_GlobalNvrInterface_APPIA */ +#define AQ_GlobalNvrInterface_APPIA_freezeNvrCrc 0 +/*! \brief Preprocessor variable to relate field to bit position in structure freezeNvrCrc in AQ_GlobalNvrInterface_APPIA */ +#define bits_AQ_GlobalNvrInterface_APPIA_freezeNvrCrc u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure freezeNvrCrc in AQ_GlobalNvrInterface_APPIA */ +#define word_AQ_GlobalNvrInterface_APPIA_freezeNvrCrc u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure resetNvrCrc in AQ_GlobalNvrInterface_APPIA */ +#define AQ_GlobalNvrInterface_APPIA_resetNvrCrc 0 +/*! \brief Preprocessor variable to relate field to bit position in structure resetNvrCrc in AQ_GlobalNvrInterface_APPIA */ +#define bits_AQ_GlobalNvrInterface_APPIA_resetNvrCrc u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure resetNvrCrc in AQ_GlobalNvrInterface_APPIA */ +#define word_AQ_GlobalNvrInterface_APPIA_resetNvrCrc u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrBurst in AQ_GlobalNvrInterface_APPIA */ +#define AQ_GlobalNvrInterface_APPIA_nvrBurst 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrBurst in AQ_GlobalNvrInterface_APPIA */ +#define bits_AQ_GlobalNvrInterface_APPIA_nvrBurst u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrBurst in AQ_GlobalNvrInterface_APPIA */ +#define word_AQ_GlobalNvrInterface_APPIA_nvrBurst u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrBusy in AQ_GlobalNvrInterface_APPIA */ +#define AQ_GlobalNvrInterface_APPIA_nvrBusy 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrBusy in AQ_GlobalNvrInterface_APPIA */ +#define bits_AQ_GlobalNvrInterface_APPIA_nvrBusy u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrBusy in AQ_GlobalNvrInterface_APPIA */ +#define word_AQ_GlobalNvrInterface_APPIA_nvrBusy u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrOpcode in AQ_GlobalNvrInterface_APPIA */ +#define AQ_GlobalNvrInterface_APPIA_nvrOpcode 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrOpcode in AQ_GlobalNvrInterface_APPIA */ +#define bits_AQ_GlobalNvrInterface_APPIA_nvrOpcode u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrOpcode in AQ_GlobalNvrInterface_APPIA */ +#define word_AQ_GlobalNvrInterface_APPIA_nvrOpcode u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrMailboxCrc in AQ_GlobalNvrInterface_APPIA */ +#define AQ_GlobalNvrInterface_APPIA_nvrMailboxCrc 1 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrMailboxCrc in AQ_GlobalNvrInterface_APPIA */ +#define bits_AQ_GlobalNvrInterface_APPIA_nvrMailboxCrc u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure nvrMailboxCrc in AQ_GlobalNvrInterface_APPIA */ +#define word_AQ_GlobalNvrInterface_APPIA_nvrMailboxCrc u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure nvrAddressMSW in AQ_GlobalNvrInterface_APPIA */ +#define AQ_GlobalNvrInterface_APPIA_nvrAddressMSW 2 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrAddressMSW in AQ_GlobalNvrInterface_APPIA */ +#define bits_AQ_GlobalNvrInterface_APPIA_nvrAddressMSW u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure nvrAddressMSW in AQ_GlobalNvrInterface_APPIA */ +#define word_AQ_GlobalNvrInterface_APPIA_nvrAddressMSW u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure nvrAddressLSW in AQ_GlobalNvrInterface_APPIA */ +#define AQ_GlobalNvrInterface_APPIA_nvrAddressLSW 3 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrAddressLSW in AQ_GlobalNvrInterface_APPIA */ +#define bits_AQ_GlobalNvrInterface_APPIA_nvrAddressLSW u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure nvrAddressLSW in AQ_GlobalNvrInterface_APPIA */ +#define word_AQ_GlobalNvrInterface_APPIA_nvrAddressLSW u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure nvrDataMSW in AQ_GlobalNvrInterface_APPIA */ +#define AQ_GlobalNvrInterface_APPIA_nvrDataMSW 4 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrDataMSW in AQ_GlobalNvrInterface_APPIA */ +#define bits_AQ_GlobalNvrInterface_APPIA_nvrDataMSW u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure nvrDataMSW in AQ_GlobalNvrInterface_APPIA */ +#define word_AQ_GlobalNvrInterface_APPIA_nvrDataMSW u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure nvrDataLSW in AQ_GlobalNvrInterface_APPIA */ +#define AQ_GlobalNvrInterface_APPIA_nvrDataLSW 5 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrDataLSW in AQ_GlobalNvrInterface_APPIA */ +#define bits_AQ_GlobalNvrInterface_APPIA_nvrDataLSW u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure nvrDataLSW in AQ_GlobalNvrInterface_APPIA */ +#define word_AQ_GlobalNvrInterface_APPIA_nvrDataLSW u5.word_5 + +/*! \brief Base register address of structure AQ_GlobalMailboxInterface_APPIA */ +#define AQ_GlobalMailboxInterface_APPIA_baseRegisterAddress 0x0200 +/*! \brief MMD address of structure AQ_GlobalMailboxInterface_APPIA */ +#define AQ_GlobalMailboxInterface_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxExecuteOperation in AQ_GlobalMailboxInterface_APPIA */ +#define AQ_GlobalMailboxInterface_APPIA_upMailboxExecuteOperation 0 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxExecuteOperation in AQ_GlobalMailboxInterface_APPIA */ +#define bits_AQ_GlobalMailboxInterface_APPIA_upMailboxExecuteOperation u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxExecuteOperation in AQ_GlobalMailboxInterface_APPIA */ +#define word_AQ_GlobalMailboxInterface_APPIA_upMailboxExecuteOperation u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxWriteMode in AQ_GlobalMailboxInterface_APPIA */ +#define AQ_GlobalMailboxInterface_APPIA_upMailboxWriteMode 0 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxWriteMode in AQ_GlobalMailboxInterface_APPIA */ +#define bits_AQ_GlobalMailboxInterface_APPIA_upMailboxWriteMode u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxWriteMode in AQ_GlobalMailboxInterface_APPIA */ +#define word_AQ_GlobalMailboxInterface_APPIA_upMailboxWriteMode u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure resetUpMailboxCrc in AQ_GlobalMailboxInterface_APPIA */ +#define AQ_GlobalMailboxInterface_APPIA_resetUpMailboxCrc 0 +/*! \brief Preprocessor variable to relate field to bit position in structure resetUpMailboxCrc in AQ_GlobalMailboxInterface_APPIA */ +#define bits_AQ_GlobalMailboxInterface_APPIA_resetUpMailboxCrc u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure resetUpMailboxCrc in AQ_GlobalMailboxInterface_APPIA */ +#define word_AQ_GlobalMailboxInterface_APPIA_resetUpMailboxCrc u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxBusy in AQ_GlobalMailboxInterface_APPIA */ +#define AQ_GlobalMailboxInterface_APPIA_upMailboxBusy 0 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxBusy in AQ_GlobalMailboxInterface_APPIA */ +#define bits_AQ_GlobalMailboxInterface_APPIA_upMailboxBusy u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxBusy in AQ_GlobalMailboxInterface_APPIA */ +#define word_AQ_GlobalMailboxInterface_APPIA_upMailboxBusy u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxCrc in AQ_GlobalMailboxInterface_APPIA */ +#define AQ_GlobalMailboxInterface_APPIA_upMailboxCrc 1 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxCrc in AQ_GlobalMailboxInterface_APPIA */ +#define bits_AQ_GlobalMailboxInterface_APPIA_upMailboxCrc u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxCrc in AQ_GlobalMailboxInterface_APPIA */ +#define word_AQ_GlobalMailboxInterface_APPIA_upMailboxCrc u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxAddressMSW in AQ_GlobalMailboxInterface_APPIA */ +#define AQ_GlobalMailboxInterface_APPIA_upMailboxAddressMSW 2 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxAddressMSW in AQ_GlobalMailboxInterface_APPIA */ +#define bits_AQ_GlobalMailboxInterface_APPIA_upMailboxAddressMSW u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxAddressMSW in AQ_GlobalMailboxInterface_APPIA */ +#define word_AQ_GlobalMailboxInterface_APPIA_upMailboxAddressMSW u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxAddressLSW in AQ_GlobalMailboxInterface_APPIA */ +#define AQ_GlobalMailboxInterface_APPIA_upMailboxAddressLSW 3 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxAddressLSW in AQ_GlobalMailboxInterface_APPIA */ +#define bits_AQ_GlobalMailboxInterface_APPIA_upMailboxAddressLSW u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxAddressLSW in AQ_GlobalMailboxInterface_APPIA */ +#define word_AQ_GlobalMailboxInterface_APPIA_upMailboxAddressLSW u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxAddressLSW_Don_tCare in AQ_GlobalMailboxInterface_APPIA */ +#define AQ_GlobalMailboxInterface_APPIA_upMailboxAddressLSW_Don_tCare 3 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxAddressLSW_Don_tCare in AQ_GlobalMailboxInterface_APPIA */ +#define bits_AQ_GlobalMailboxInterface_APPIA_upMailboxAddressLSW_Don_tCare u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxAddressLSW_Don_tCare in AQ_GlobalMailboxInterface_APPIA */ +#define word_AQ_GlobalMailboxInterface_APPIA_upMailboxAddressLSW_Don_tCare u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxDataMSW in AQ_GlobalMailboxInterface_APPIA */ +#define AQ_GlobalMailboxInterface_APPIA_upMailboxDataMSW 4 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxDataMSW in AQ_GlobalMailboxInterface_APPIA */ +#define bits_AQ_GlobalMailboxInterface_APPIA_upMailboxDataMSW u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxDataMSW in AQ_GlobalMailboxInterface_APPIA */ +#define word_AQ_GlobalMailboxInterface_APPIA_upMailboxDataMSW u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxDataLSW in AQ_GlobalMailboxInterface_APPIA */ +#define AQ_GlobalMailboxInterface_APPIA_upMailboxDataLSW 5 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxDataLSW in AQ_GlobalMailboxInterface_APPIA */ +#define bits_AQ_GlobalMailboxInterface_APPIA_upMailboxDataLSW u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxDataLSW in AQ_GlobalMailboxInterface_APPIA */ +#define word_AQ_GlobalMailboxInterface_APPIA_upMailboxDataLSW u5.word_5 + +/*! \brief Base register address of structure AQ_GlobalMicroprocessorScratchPad_APPIA */ +#define AQ_GlobalMicroprocessorScratchPad_APPIA_baseRegisterAddress 0x0300 +/*! \brief MMD address of structure AQ_GlobalMicroprocessorScratchPad_APPIA */ +#define AQ_GlobalMicroprocessorScratchPad_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure scratchPad_1 in AQ_GlobalMicroprocessorScratchPad_APPIA */ +#define AQ_GlobalMicroprocessorScratchPad_APPIA_scratchPad_1 0 +/*! \brief Preprocessor variable to relate field to bit position in structure scratchPad_1 in AQ_GlobalMicroprocessorScratchPad_APPIA */ +#define bits_AQ_GlobalMicroprocessorScratchPad_APPIA_scratchPad_1 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure scratchPad_1 in AQ_GlobalMicroprocessorScratchPad_APPIA */ +#define word_AQ_GlobalMicroprocessorScratchPad_APPIA_scratchPad_1 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure scratchPad_2 in AQ_GlobalMicroprocessorScratchPad_APPIA */ +#define AQ_GlobalMicroprocessorScratchPad_APPIA_scratchPad_2 1 +/*! \brief Preprocessor variable to relate field to bit position in structure scratchPad_2 in AQ_GlobalMicroprocessorScratchPad_APPIA */ +#define bits_AQ_GlobalMicroprocessorScratchPad_APPIA_scratchPad_2 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure scratchPad_2 in AQ_GlobalMicroprocessorScratchPad_APPIA */ +#define word_AQ_GlobalMicroprocessorScratchPad_APPIA_scratchPad_2 u1.word_1 + +/*! \brief Base register address of structure AQ_GlobalControl_APPIA */ +#define AQ_GlobalControl_APPIA_baseRegisterAddress 0xC000 +/*! \brief MMD address of structure AQ_GlobalControl_APPIA */ +#define AQ_GlobalControl_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure upReset in AQ_GlobalControl_APPIA */ +#define AQ_GlobalControl_APPIA_upReset 1 +/*! \brief Preprocessor variable to relate field to bit position in structure upReset in AQ_GlobalControl_APPIA */ +#define bits_AQ_GlobalControl_APPIA_upReset u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure upReset in AQ_GlobalControl_APPIA */ +#define word_AQ_GlobalControl_APPIA_upReset u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure upRunStallOverride in AQ_GlobalControl_APPIA */ +#define AQ_GlobalControl_APPIA_upRunStallOverride 1 +/*! \brief Preprocessor variable to relate field to bit position in structure upRunStallOverride in AQ_GlobalControl_APPIA */ +#define bits_AQ_GlobalControl_APPIA_upRunStallOverride u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure upRunStallOverride in AQ_GlobalControl_APPIA */ +#define word_AQ_GlobalControl_APPIA_upRunStallOverride u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure upRunStall in AQ_GlobalControl_APPIA */ +#define AQ_GlobalControl_APPIA_upRunStall 1 +/*! \brief Preprocessor variable to relate field to bit position in structure upRunStall in AQ_GlobalControl_APPIA */ +#define bits_AQ_GlobalControl_APPIA_upRunStall u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure upRunStall in AQ_GlobalControl_APPIA */ +#define word_AQ_GlobalControl_APPIA_upRunStall u1.word_1 + +/*! \brief Base register address of structure AQ_GlobalResetControl_APPIA */ +#define AQ_GlobalResetControl_APPIA_baseRegisterAddress 0xC006 +/*! \brief MMD address of structure AQ_GlobalResetControl_APPIA */ +#define AQ_GlobalResetControl_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure globalMMD_ResetDisable in AQ_GlobalResetControl_APPIA */ +#define AQ_GlobalResetControl_APPIA_globalMMD_ResetDisable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure globalMMD_ResetDisable in AQ_GlobalResetControl_APPIA */ +#define bits_AQ_GlobalResetControl_APPIA_globalMMD_ResetDisable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure globalMMD_ResetDisable in AQ_GlobalResetControl_APPIA */ +#define word_AQ_GlobalResetControl_APPIA_globalMMD_ResetDisable u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalDiagnosticProvisioning_APPIA */ +#define AQ_GlobalDiagnosticProvisioning_APPIA_baseRegisterAddress 0xC400 +/*! \brief MMD address of structure AQ_GlobalDiagnosticProvisioning_APPIA */ +#define AQ_GlobalDiagnosticProvisioning_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure enableDiagnostics in AQ_GlobalDiagnosticProvisioning_APPIA */ +#define AQ_GlobalDiagnosticProvisioning_APPIA_enableDiagnostics 0 +/*! \brief Preprocessor variable to relate field to bit position in structure enableDiagnostics in AQ_GlobalDiagnosticProvisioning_APPIA */ +#define bits_AQ_GlobalDiagnosticProvisioning_APPIA_enableDiagnostics u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure enableDiagnostics in AQ_GlobalDiagnosticProvisioning_APPIA */ +#define word_AQ_GlobalDiagnosticProvisioning_APPIA_enableDiagnostics u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalThermalProvisioning_APPIA */ +#define AQ_GlobalThermalProvisioning_APPIA_baseRegisterAddress 0xC420 +/*! \brief MMD address of structure AQ_GlobalThermalProvisioning_APPIA */ +#define AQ_GlobalThermalProvisioning_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure reserved_0 in AQ_GlobalThermalProvisioning_APPIA */ +#define AQ_GlobalThermalProvisioning_APPIA_reserved_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_0 in AQ_GlobalThermalProvisioning_APPIA */ +#define bits_AQ_GlobalThermalProvisioning_APPIA_reserved_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_0 in AQ_GlobalThermalProvisioning_APPIA */ +#define word_AQ_GlobalThermalProvisioning_APPIA_reserved_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure highTempFailureThreshold in AQ_GlobalThermalProvisioning_APPIA */ +#define AQ_GlobalThermalProvisioning_APPIA_highTempFailureThreshold 1 +/*! \brief Preprocessor variable to relate field to bit position in structure highTempFailureThreshold in AQ_GlobalThermalProvisioning_APPIA */ +#define bits_AQ_GlobalThermalProvisioning_APPIA_highTempFailureThreshold u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure highTempFailureThreshold in AQ_GlobalThermalProvisioning_APPIA */ +#define word_AQ_GlobalThermalProvisioning_APPIA_highTempFailureThreshold u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure lowTempFailureThreshold in AQ_GlobalThermalProvisioning_APPIA */ +#define AQ_GlobalThermalProvisioning_APPIA_lowTempFailureThreshold 2 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTempFailureThreshold in AQ_GlobalThermalProvisioning_APPIA */ +#define bits_AQ_GlobalThermalProvisioning_APPIA_lowTempFailureThreshold u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure lowTempFailureThreshold in AQ_GlobalThermalProvisioning_APPIA */ +#define word_AQ_GlobalThermalProvisioning_APPIA_lowTempFailureThreshold u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure highTempWarningThreshold in AQ_GlobalThermalProvisioning_APPIA */ +#define AQ_GlobalThermalProvisioning_APPIA_highTempWarningThreshold 3 +/*! \brief Preprocessor variable to relate field to bit position in structure highTempWarningThreshold in AQ_GlobalThermalProvisioning_APPIA */ +#define bits_AQ_GlobalThermalProvisioning_APPIA_highTempWarningThreshold u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure highTempWarningThreshold in AQ_GlobalThermalProvisioning_APPIA */ +#define word_AQ_GlobalThermalProvisioning_APPIA_highTempWarningThreshold u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure lowTempWarningThreshold in AQ_GlobalThermalProvisioning_APPIA */ +#define AQ_GlobalThermalProvisioning_APPIA_lowTempWarningThreshold 4 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTempWarningThreshold in AQ_GlobalThermalProvisioning_APPIA */ +#define bits_AQ_GlobalThermalProvisioning_APPIA_lowTempWarningThreshold u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure lowTempWarningThreshold in AQ_GlobalThermalProvisioning_APPIA */ +#define word_AQ_GlobalThermalProvisioning_APPIA_lowTempWarningThreshold u4.word_4 + +/*! \brief Base register address of structure AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_baseRegisterAddress 0xC430 +/*! \brief MMD address of structure AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure led_0ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_0ManualSet 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_0ManualSet u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_0ManualSet u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_0_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_0_10Gb_sLinkEstablished 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_0_10Gb_sLinkEstablished u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_0_10Gb_sLinkEstablished u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_0_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_0_1Gb_sLinkEstablished 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_0_1Gb_sLinkEstablished u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_0_1Gb_sLinkEstablished u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_0_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_0_100Mb_sLinkEstablished 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_0_100Mb_sLinkEstablished u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_0_100Mb_sLinkEstablished u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_0Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_0Connecting 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_0Connecting u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_0Connecting u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_0ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_0ReceiveActivity 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_0ReceiveActivity u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_0ReceiveActivity u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_0TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_0TransmitActivity 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_0TransmitActivity u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_0TransmitActivity u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_0ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_0ActivityStretch 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_0ActivityStretch u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_0ActivityStretch u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_1ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_1ManualSet 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_1ManualSet u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_1ManualSet u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_1_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_1_10Gb_sLinkEstablished 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_1_10Gb_sLinkEstablished u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_1_10Gb_sLinkEstablished u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_1_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_1_1Gb_sLinkEstablished 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_1_1Gb_sLinkEstablished u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_1_1Gb_sLinkEstablished u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_1_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_1_100Mb_sLinkEstablished 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_1_100Mb_sLinkEstablished u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_1_100Mb_sLinkEstablished u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_1Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_1Connecting 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_1Connecting u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_1Connecting u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_1ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_1ReceiveActivity 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_1ReceiveActivity u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_1ReceiveActivity u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_1TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_1TransmitActivity 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_1TransmitActivity u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_1TransmitActivity u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_1ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_1ActivityStretch 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_1ActivityStretch u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_1ActivityStretch u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_2ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_2ManualSet 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_2ManualSet u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_2ManualSet u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_2_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_2_10Gb_sLinkEstablished 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_2_10Gb_sLinkEstablished u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_2_10Gb_sLinkEstablished u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_2_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_2_1Gb_sLinkEstablished 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_2_1Gb_sLinkEstablished u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_2_1Gb_sLinkEstablished u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_2_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_2_100Mb_sLinkEstablished 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_2_100Mb_sLinkEstablished u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_2_100Mb_sLinkEstablished u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_2Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_2Connecting 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_2Connecting u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_2Connecting u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_2ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_2ReceiveActivity 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_2ReceiveActivity u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_2ReceiveActivity u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_2TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_2TransmitActivity 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_2TransmitActivity u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_2TransmitActivity u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_2ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_2ActivityStretch 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_2ActivityStretch u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_2ActivityStretch u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_3ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_3ManualSet 3 +/*! \brief Preprocessor variable to relate field to bit position in structure led_3ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_3ManualSet u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure led_3ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_3ManualSet u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure led_3_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_3_10Gb_sLinkEstablished 3 +/*! \brief Preprocessor variable to relate field to bit position in structure led_3_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_3_10Gb_sLinkEstablished u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure led_3_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_3_10Gb_sLinkEstablished u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure led_3_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_3_1Gb_sLinkEstablished 3 +/*! \brief Preprocessor variable to relate field to bit position in structure led_3_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_3_1Gb_sLinkEstablished u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure led_3_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_3_1Gb_sLinkEstablished u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure led_3_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_3_100Mb_sLinkEstablished 3 +/*! \brief Preprocessor variable to relate field to bit position in structure led_3_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_3_100Mb_sLinkEstablished u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure led_3_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_3_100Mb_sLinkEstablished u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure led_3Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_3Connecting 3 +/*! \brief Preprocessor variable to relate field to bit position in structure led_3Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_3Connecting u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure led_3Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_3Connecting u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure led_3ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_3ReceiveActivity 3 +/*! \brief Preprocessor variable to relate field to bit position in structure led_3ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_3ReceiveActivity u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure led_3ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_3ReceiveActivity u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure led_3TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_3TransmitActivity 3 +/*! \brief Preprocessor variable to relate field to bit position in structure led_3TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_3TransmitActivity u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure led_3TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_3TransmitActivity u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure led_3ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_3ActivityStretch 3 +/*! \brief Preprocessor variable to relate field to bit position in structure led_3ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_3ActivityStretch u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure led_3ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_3ActivityStretch u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure led_4ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_4ManualSet 4 +/*! \brief Preprocessor variable to relate field to bit position in structure led_4ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_4ManualSet u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure led_4ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_4ManualSet u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure led_4_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_4_10Gb_sLinkEstablished 4 +/*! \brief Preprocessor variable to relate field to bit position in structure led_4_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_4_10Gb_sLinkEstablished u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure led_4_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_4_10Gb_sLinkEstablished u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure led_4_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_4_1Gb_sLinkEstablished 4 +/*! \brief Preprocessor variable to relate field to bit position in structure led_4_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_4_1Gb_sLinkEstablished u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure led_4_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_4_1Gb_sLinkEstablished u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure led_4_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_4_100Mb_sLinkEstablished 4 +/*! \brief Preprocessor variable to relate field to bit position in structure led_4_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_4_100Mb_sLinkEstablished u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure led_4_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_4_100Mb_sLinkEstablished u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure led_4Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_4Connecting 4 +/*! \brief Preprocessor variable to relate field to bit position in structure led_4Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_4Connecting u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure led_4Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_4Connecting u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure led_4ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_4ReceiveActivity 4 +/*! \brief Preprocessor variable to relate field to bit position in structure led_4ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_4ReceiveActivity u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure led_4ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_4ReceiveActivity u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure led_4TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_4TransmitActivity 4 +/*! \brief Preprocessor variable to relate field to bit position in structure led_4TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_4TransmitActivity u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure led_4TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_4TransmitActivity u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure led_4ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_4ActivityStretch 4 +/*! \brief Preprocessor variable to relate field to bit position in structure led_4ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_4ActivityStretch u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure led_4ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_4ActivityStretch u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure led_5ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_5ManualSet 5 +/*! \brief Preprocessor variable to relate field to bit position in structure led_5ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_5ManualSet u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure led_5ManualSet in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_5ManualSet u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure led_5_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_5_10Gb_sLinkEstablished 5 +/*! \brief Preprocessor variable to relate field to bit position in structure led_5_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_5_10Gb_sLinkEstablished u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure led_5_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_5_10Gb_sLinkEstablished u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure led_5_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_5_1Gb_sLinkEstablished 5 +/*! \brief Preprocessor variable to relate field to bit position in structure led_5_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_5_1Gb_sLinkEstablished u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure led_5_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_5_1Gb_sLinkEstablished u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure led_5_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_5_100Mb_sLinkEstablished 5 +/*! \brief Preprocessor variable to relate field to bit position in structure led_5_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_5_100Mb_sLinkEstablished u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure led_5_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_5_100Mb_sLinkEstablished u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure led_5Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_5Connecting 5 +/*! \brief Preprocessor variable to relate field to bit position in structure led_5Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_5Connecting u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure led_5Connecting in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_5Connecting u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure led_5ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_5ReceiveActivity 5 +/*! \brief Preprocessor variable to relate field to bit position in structure led_5ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_5ReceiveActivity u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure led_5ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_5ReceiveActivity u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure led_5TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_5TransmitActivity 5 +/*! \brief Preprocessor variable to relate field to bit position in structure led_5TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_5TransmitActivity u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure led_5TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_5TransmitActivity u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure led_5ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_5ActivityStretch 5 +/*! \brief Preprocessor variable to relate field to bit position in structure led_5ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_5ActivityStretch u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure led_5ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_5ActivityStretch u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure ledOperationMode in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_ledOperationMode 7 +/*! \brief Preprocessor variable to relate field to bit position in structure ledOperationMode in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_ledOperationMode u7.bits_7 +/*! \brief Preprocessor variable to relate field to word position in structure ledOperationMode in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_ledOperationMode u7.word_7 +/*! \brief Preprocessor variable to relate field to word number in structure led_0DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_0DriveThreeStateSelect 8 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_0DriveThreeStateSelect u8.bits_8 +/*! \brief Preprocessor variable to relate field to word position in structure led_0DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_0DriveThreeStateSelect u8.word_8 +/*! \brief Preprocessor variable to relate field to word number in structure led_0ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_0ActiveHighSelect 8 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_0ActiveHighSelect u8.bits_8 +/*! \brief Preprocessor variable to relate field to word position in structure led_0ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_0ActiveHighSelect u8.word_8 +/*! \brief Preprocessor variable to relate field to word number in structure led_0ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_0ManualActiveSelect 8 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_0ManualActiveSelect u8.bits_8 +/*! \brief Preprocessor variable to relate field to word position in structure led_0ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_0ManualActiveSelect u8.word_8 +/*! \brief Preprocessor variable to relate field to word number in structure led_1DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_1DriveThreeStateSelect 9 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_1DriveThreeStateSelect u9.bits_9 +/*! \brief Preprocessor variable to relate field to word position in structure led_1DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_1DriveThreeStateSelect u9.word_9 +/*! \brief Preprocessor variable to relate field to word number in structure led_1ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_1ActiveHighSelect 9 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_1ActiveHighSelect u9.bits_9 +/*! \brief Preprocessor variable to relate field to word position in structure led_1ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_1ActiveHighSelect u9.word_9 +/*! \brief Preprocessor variable to relate field to word number in structure led_1ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_1ManualActiveSelect 9 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_1ManualActiveSelect u9.bits_9 +/*! \brief Preprocessor variable to relate field to word position in structure led_1ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_1ManualActiveSelect u9.word_9 +/*! \brief Preprocessor variable to relate field to word number in structure led_2DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_2DriveThreeStateSelect 10 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_2DriveThreeStateSelect u10.bits_10 +/*! \brief Preprocessor variable to relate field to word position in structure led_2DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_2DriveThreeStateSelect u10.word_10 +/*! \brief Preprocessor variable to relate field to word number in structure led_2ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_2ActiveHighSelect 10 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_2ActiveHighSelect u10.bits_10 +/*! \brief Preprocessor variable to relate field to word position in structure led_2ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_2ActiveHighSelect u10.word_10 +/*! \brief Preprocessor variable to relate field to word number in structure led_2ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_2ManualActiveSelect 10 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_2ManualActiveSelect u10.bits_10 +/*! \brief Preprocessor variable to relate field to word position in structure led_2ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_2ManualActiveSelect u10.word_10 +/*! \brief Preprocessor variable to relate field to word number in structure led_3DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_3DriveThreeStateSelect 11 +/*! \brief Preprocessor variable to relate field to bit position in structure led_3DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_3DriveThreeStateSelect u11.bits_11 +/*! \brief Preprocessor variable to relate field to word position in structure led_3DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_3DriveThreeStateSelect u11.word_11 +/*! \brief Preprocessor variable to relate field to word number in structure led_3ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_3ActiveHighSelect 11 +/*! \brief Preprocessor variable to relate field to bit position in structure led_3ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_3ActiveHighSelect u11.bits_11 +/*! \brief Preprocessor variable to relate field to word position in structure led_3ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_3ActiveHighSelect u11.word_11 +/*! \brief Preprocessor variable to relate field to word number in structure led_3ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_3ManualActiveSelect 11 +/*! \brief Preprocessor variable to relate field to bit position in structure led_3ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_3ManualActiveSelect u11.bits_11 +/*! \brief Preprocessor variable to relate field to word position in structure led_3ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_3ManualActiveSelect u11.word_11 +/*! \brief Preprocessor variable to relate field to word number in structure led_4DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_4DriveThreeStateSelect 12 +/*! \brief Preprocessor variable to relate field to bit position in structure led_4DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_4DriveThreeStateSelect u12.bits_12 +/*! \brief Preprocessor variable to relate field to word position in structure led_4DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_4DriveThreeStateSelect u12.word_12 +/*! \brief Preprocessor variable to relate field to word number in structure led_4ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_4ActiveHighSelect 12 +/*! \brief Preprocessor variable to relate field to bit position in structure led_4ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_4ActiveHighSelect u12.bits_12 +/*! \brief Preprocessor variable to relate field to word position in structure led_4ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_4ActiveHighSelect u12.word_12 +/*! \brief Preprocessor variable to relate field to word number in structure led_4ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_4ManualActiveSelect 12 +/*! \brief Preprocessor variable to relate field to bit position in structure led_4ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_4ManualActiveSelect u12.bits_12 +/*! \brief Preprocessor variable to relate field to word position in structure led_4ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_4ManualActiveSelect u12.word_12 +/*! \brief Preprocessor variable to relate field to word number in structure led_5DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_5DriveThreeStateSelect 13 +/*! \brief Preprocessor variable to relate field to bit position in structure led_5DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_5DriveThreeStateSelect u13.bits_13 +/*! \brief Preprocessor variable to relate field to word position in structure led_5DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_5DriveThreeStateSelect u13.word_13 +/*! \brief Preprocessor variable to relate field to word number in structure led_5ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_5ActiveHighSelect 13 +/*! \brief Preprocessor variable to relate field to bit position in structure led_5ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_5ActiveHighSelect u13.bits_13 +/*! \brief Preprocessor variable to relate field to word position in structure led_5ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_5ActiveHighSelect u13.word_13 +/*! \brief Preprocessor variable to relate field to word number in structure led_5ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define AQ_GlobalLedProvisioning_APPIA_led_5ManualActiveSelect 13 +/*! \brief Preprocessor variable to relate field to bit position in structure led_5ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define bits_AQ_GlobalLedProvisioning_APPIA_led_5ManualActiveSelect u13.bits_13 +/*! \brief Preprocessor variable to relate field to word position in structure led_5ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ +#define word_AQ_GlobalLedProvisioning_APPIA_led_5ManualActiveSelect u13.word_13 + +/*! \brief Base register address of structure AQ_GlobalGeneralProvisioning_APPIA */ +#define AQ_GlobalGeneralProvisioning_APPIA_baseRegisterAddress 0xC440 +/*! \brief MMD address of structure AQ_GlobalGeneralProvisioning_APPIA */ +#define AQ_GlobalGeneralProvisioning_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure gangLoadMdioAddress in AQ_GlobalGeneralProvisioning_APPIA */ +#define AQ_GlobalGeneralProvisioning_APPIA_gangLoadMdioAddress 0 +/*! \brief Preprocessor variable to relate field to bit position in structure gangLoadMdioAddress in AQ_GlobalGeneralProvisioning_APPIA */ +#define bits_AQ_GlobalGeneralProvisioning_APPIA_gangLoadMdioAddress u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure gangLoadMdioAddress in AQ_GlobalGeneralProvisioning_APPIA */ +#define word_AQ_GlobalGeneralProvisioning_APPIA_gangLoadMdioAddress u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure gangLoadMdioWriteOnly in AQ_GlobalGeneralProvisioning_APPIA */ +#define AQ_GlobalGeneralProvisioning_APPIA_gangLoadMdioWriteOnly 0 +/*! \brief Preprocessor variable to relate field to bit position in structure gangLoadMdioWriteOnly in AQ_GlobalGeneralProvisioning_APPIA */ +#define bits_AQ_GlobalGeneralProvisioning_APPIA_gangLoadMdioWriteOnly u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure gangLoadMdioWriteOnly in AQ_GlobalGeneralProvisioning_APPIA */ +#define word_AQ_GlobalGeneralProvisioning_APPIA_gangLoadMdioWriteOnly u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mdioBroadcastModeEnable in AQ_GlobalGeneralProvisioning_APPIA */ +#define AQ_GlobalGeneralProvisioning_APPIA_mdioBroadcastModeEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioBroadcastModeEnable in AQ_GlobalGeneralProvisioning_APPIA */ +#define bits_AQ_GlobalGeneralProvisioning_APPIA_mdioBroadcastModeEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mdioBroadcastModeEnable in AQ_GlobalGeneralProvisioning_APPIA */ +#define word_AQ_GlobalGeneralProvisioning_APPIA_mdioBroadcastModeEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mdioReadMSW_FirstEnable in AQ_GlobalGeneralProvisioning_APPIA */ +#define AQ_GlobalGeneralProvisioning_APPIA_mdioReadMSW_FirstEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioReadMSW_FirstEnable in AQ_GlobalGeneralProvisioning_APPIA */ +#define bits_AQ_GlobalGeneralProvisioning_APPIA_mdioReadMSW_FirstEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mdioReadMSW_FirstEnable in AQ_GlobalGeneralProvisioning_APPIA */ +#define word_AQ_GlobalGeneralProvisioning_APPIA_mdioReadMSW_FirstEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mdioDriveConfiguration in AQ_GlobalGeneralProvisioning_APPIA */ +#define AQ_GlobalGeneralProvisioning_APPIA_mdioDriveConfiguration 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioDriveConfiguration in AQ_GlobalGeneralProvisioning_APPIA */ +#define bits_AQ_GlobalGeneralProvisioning_APPIA_mdioDriveConfiguration u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mdioDriveConfiguration in AQ_GlobalGeneralProvisioning_APPIA */ +#define word_AQ_GlobalGeneralProvisioning_APPIA_mdioDriveConfiguration u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mdioPreambleDetectionDisable in AQ_GlobalGeneralProvisioning_APPIA */ +#define AQ_GlobalGeneralProvisioning_APPIA_mdioPreambleDetectionDisable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioPreambleDetectionDisable in AQ_GlobalGeneralProvisioning_APPIA */ +#define bits_AQ_GlobalGeneralProvisioning_APPIA_mdioPreambleDetectionDisable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mdioPreambleDetectionDisable in AQ_GlobalGeneralProvisioning_APPIA */ +#define word_AQ_GlobalGeneralProvisioning_APPIA_mdioPreambleDetectionDisable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mdioAddressReset in AQ_GlobalGeneralProvisioning_APPIA */ +#define AQ_GlobalGeneralProvisioning_APPIA_mdioAddressReset 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioAddressReset in AQ_GlobalGeneralProvisioning_APPIA */ +#define bits_AQ_GlobalGeneralProvisioning_APPIA_mdioAddressReset u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mdioAddressReset in AQ_GlobalGeneralProvisioning_APPIA */ +#define word_AQ_GlobalGeneralProvisioning_APPIA_mdioAddressReset u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure daisyChainReset in AQ_GlobalGeneralProvisioning_APPIA */ +#define AQ_GlobalGeneralProvisioning_APPIA_daisyChainReset 2 +/*! \brief Preprocessor variable to relate field to bit position in structure daisyChainReset in AQ_GlobalGeneralProvisioning_APPIA */ +#define bits_AQ_GlobalGeneralProvisioning_APPIA_daisyChainReset u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure daisyChainReset in AQ_GlobalGeneralProvisioning_APPIA */ +#define word_AQ_GlobalGeneralProvisioning_APPIA_daisyChainReset u2.word_2 + +/*! \brief Base register address of structure AQ_GlobalNvrProvisioning_APPIA */ +#define AQ_GlobalNvrProvisioning_APPIA_baseRegisterAddress 0xC450 +/*! \brief MMD address of structure AQ_GlobalNvrProvisioning_APPIA */ +#define AQ_GlobalNvrProvisioning_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure nvrDataLength in AQ_GlobalNvrProvisioning_APPIA */ +#define AQ_GlobalNvrProvisioning_APPIA_nvrDataLength 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrDataLength in AQ_GlobalNvrProvisioning_APPIA */ +#define bits_AQ_GlobalNvrProvisioning_APPIA_nvrDataLength u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrDataLength in AQ_GlobalNvrProvisioning_APPIA */ +#define word_AQ_GlobalNvrProvisioning_APPIA_nvrDataLength u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrDummyLength in AQ_GlobalNvrProvisioning_APPIA */ +#define AQ_GlobalNvrProvisioning_APPIA_nvrDummyLength 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrDummyLength in AQ_GlobalNvrProvisioning_APPIA */ +#define bits_AQ_GlobalNvrProvisioning_APPIA_nvrDummyLength u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrDummyLength in AQ_GlobalNvrProvisioning_APPIA */ +#define word_AQ_GlobalNvrProvisioning_APPIA_nvrDummyLength u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrAddressLength in AQ_GlobalNvrProvisioning_APPIA */ +#define AQ_GlobalNvrProvisioning_APPIA_nvrAddressLength 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrAddressLength in AQ_GlobalNvrProvisioning_APPIA */ +#define bits_AQ_GlobalNvrProvisioning_APPIA_nvrAddressLength u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrAddressLength in AQ_GlobalNvrProvisioning_APPIA */ +#define word_AQ_GlobalNvrProvisioning_APPIA_nvrAddressLength u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrAddressLengthOverride in AQ_GlobalNvrProvisioning_APPIA */ +#define AQ_GlobalNvrProvisioning_APPIA_nvrAddressLengthOverride 1 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrAddressLengthOverride in AQ_GlobalNvrProvisioning_APPIA */ +#define bits_AQ_GlobalNvrProvisioning_APPIA_nvrAddressLengthOverride u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure nvrAddressLengthOverride in AQ_GlobalNvrProvisioning_APPIA */ +#define word_AQ_GlobalNvrProvisioning_APPIA_nvrAddressLengthOverride u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure nvrClockDivide in AQ_GlobalNvrProvisioning_APPIA */ +#define AQ_GlobalNvrProvisioning_APPIA_nvrClockDivide 1 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrClockDivide in AQ_GlobalNvrProvisioning_APPIA */ +#define bits_AQ_GlobalNvrProvisioning_APPIA_nvrClockDivide u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure nvrClockDivide in AQ_GlobalNvrProvisioning_APPIA */ +#define word_AQ_GlobalNvrProvisioning_APPIA_nvrClockDivide u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure nvrDaisyChainClockDivideOverride in AQ_GlobalNvrProvisioning_APPIA */ +#define AQ_GlobalNvrProvisioning_APPIA_nvrDaisyChainClockDivideOverride 2 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrDaisyChainClockDivideOverride in AQ_GlobalNvrProvisioning_APPIA */ +#define bits_AQ_GlobalNvrProvisioning_APPIA_nvrDaisyChainClockDivideOverride u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure nvrDaisyChainClockDivideOverride in AQ_GlobalNvrProvisioning_APPIA */ +#define word_AQ_GlobalNvrProvisioning_APPIA_nvrDaisyChainClockDivideOverride u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure nvrDaisyChainDisable in AQ_GlobalNvrProvisioning_APPIA */ +#define AQ_GlobalNvrProvisioning_APPIA_nvrDaisyChainDisable 2 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrDaisyChainDisable in AQ_GlobalNvrProvisioning_APPIA */ +#define bits_AQ_GlobalNvrProvisioning_APPIA_nvrDaisyChainDisable u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure nvrDaisyChainDisable in AQ_GlobalNvrProvisioning_APPIA */ +#define word_AQ_GlobalNvrProvisioning_APPIA_nvrDaisyChainDisable u2.word_2 + +/*! \brief Base register address of structure AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_baseRegisterAddress 0xC470 +/*! \brief MMD address of structure AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure diagnosticsSelect in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_diagnosticsSelect 0 +/*! \brief Preprocessor variable to relate field to bit position in structure diagnosticsSelect in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_diagnosticsSelect u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure diagnosticsSelect in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_diagnosticsSelect u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure extendedMdiDiagnosticsSelect in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_extendedMdiDiagnosticsSelect 0 +/*! \brief Preprocessor variable to relate field to bit position in structure extendedMdiDiagnosticsSelect in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_extendedMdiDiagnosticsSelect u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure extendedMdiDiagnosticsSelect in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_extendedMdiDiagnosticsSelect u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure initiateComponentDiagnostics in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_initiateComponentDiagnostics 0 +/*! \brief Preprocessor variable to relate field to bit position in structure initiateComponentDiagnostics in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_initiateComponentDiagnostics u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure initiateComponentDiagnostics in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_initiateComponentDiagnostics u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure initiateCableDiagnostics in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_initiateCableDiagnostics 0 +/*! \brief Preprocessor variable to relate field to bit position in structure initiateCableDiagnostics in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_initiateCableDiagnostics u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure initiateCableDiagnostics in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_initiateCableDiagnostics u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioning_2 in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_reservedProvisioning_2 1 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioning_2 in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_reservedProvisioning_2 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioning_2 in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_reservedProvisioning_2 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure enableDaisy_chainHop_countOverride in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_enableDaisy_chainHop_countOverride 1 +/*! \brief Preprocessor variable to relate field to bit position in structure enableDaisy_chainHop_countOverride in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_enableDaisy_chainHop_countOverride u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure enableDaisy_chainHop_countOverride in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_enableDaisy_chainHop_countOverride u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure daisy_chainHop_countOverrideValue in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_daisy_chainHop_countOverrideValue 1 +/*! \brief Preprocessor variable to relate field to bit position in structure daisy_chainHop_countOverrideValue in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_daisy_chainHop_countOverrideValue u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure daisy_chainHop_countOverrideValue in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_daisy_chainHop_countOverrideValue u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure enableLvddPowerSupplyTuning in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_enableLvddPowerSupplyTuning 2 +/*! \brief Preprocessor variable to relate field to bit position in structure enableLvddPowerSupplyTuning in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_enableLvddPowerSupplyTuning u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure enableLvddPowerSupplyTuning in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_enableLvddPowerSupplyTuning u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure enableVddPowerSupplyTuning in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_enableVddPowerSupplyTuning 2 +/*! \brief Preprocessor variable to relate field to bit position in structure enableVddPowerSupplyTuning in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_enableVddPowerSupplyTuning u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure enableVddPowerSupplyTuning in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_enableVddPowerSupplyTuning u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure tunableExternalLvddPowerSupplyPresent in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_tunableExternalLvddPowerSupplyPresent 2 +/*! \brief Preprocessor variable to relate field to bit position in structure tunableExternalLvddPowerSupplyPresent in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_tunableExternalLvddPowerSupplyPresent u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure tunableExternalLvddPowerSupplyPresent in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_tunableExternalLvddPowerSupplyPresent u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure tunableExternalVddPowerSupplyPresent in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_tunableExternalVddPowerSupplyPresent 2 +/*! \brief Preprocessor variable to relate field to bit position in structure tunableExternalVddPowerSupplyPresent in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_tunableExternalVddPowerSupplyPresent u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure tunableExternalVddPowerSupplyPresent in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_tunableExternalVddPowerSupplyPresent u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure enableXenpakRegisterSpace in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_enableXenpakRegisterSpace 2 +/*! \brief Preprocessor variable to relate field to bit position in structure enableXenpakRegisterSpace in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_enableXenpakRegisterSpace u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure enableXenpakRegisterSpace in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_enableXenpakRegisterSpace u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure enable_5thChannelRfiCancellation in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_enable_5thChannelRfiCancellation 2 +/*! \brief Preprocessor variable to relate field to bit position in structure enable_5thChannelRfiCancellation in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_enable_5thChannelRfiCancellation u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure enable_5thChannelRfiCancellation in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_enable_5thChannelRfiCancellation u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure trainingSNR in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_trainingSNR 4 +/*! \brief Preprocessor variable to relate field to bit position in structure trainingSNR in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_trainingSNR u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure trainingSNR in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_trainingSNR u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure smartPower_downStatus in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_smartPower_downStatus 5 +/*! \brief Preprocessor variable to relate field to bit position in structure smartPower_downStatus in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_smartPower_downStatus u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure smartPower_downStatus in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_smartPower_downStatus u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioning_6 in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_reservedProvisioning_6 5 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioning_6 in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_reservedProvisioning_6 u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioning_6 in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_reservedProvisioning_6 u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrLpDisableTimer in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_cfrLpDisableTimer 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrLpDisableTimer in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_cfrLpDisableTimer u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrLpDisableTimer in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_cfrLpDisableTimer u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrLpExtendedMaxwait in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_cfrLpExtendedMaxwait 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrLpExtendedMaxwait in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_cfrLpExtendedMaxwait u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrLpExtendedMaxwait in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_cfrLpExtendedMaxwait u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrLpTHP in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_cfrLpTHP 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrLpTHP in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_cfrLpTHP u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrLpTHP in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_cfrLpTHP u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrLpSupport in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_cfrLpSupport 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrLpSupport in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_cfrLpSupport u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrLpSupport in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_cfrLpSupport u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrDisableTimer in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_cfrDisableTimer 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrDisableTimer in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_cfrDisableTimer u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrDisableTimer in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_cfrDisableTimer u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrExtendedMaxwait in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_cfrExtendedMaxwait 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrExtendedMaxwait in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_cfrExtendedMaxwait u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrExtendedMaxwait in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_cfrExtendedMaxwait u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrTHP in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_cfrTHP 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrTHP in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_cfrTHP u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrTHP in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_cfrTHP u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrSupport in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_cfrSupport 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrSupport in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_cfrSupport u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrSupport in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_cfrSupport u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure deadlockAvoidanceEnable in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_deadlockAvoidanceEnable 5 +/*! \brief Preprocessor variable to relate field to bit position in structure deadlockAvoidanceEnable in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_deadlockAvoidanceEnable u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure deadlockAvoidanceEnable in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_deadlockAvoidanceEnable u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure smartPower_downEnable in AQ_GlobalReservedProvisioning_APPIA */ +#define AQ_GlobalReservedProvisioning_APPIA_smartPower_downEnable 5 +/*! \brief Preprocessor variable to relate field to bit position in structure smartPower_downEnable in AQ_GlobalReservedProvisioning_APPIA */ +#define bits_AQ_GlobalReservedProvisioning_APPIA_smartPower_downEnable u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure smartPower_downEnable in AQ_GlobalReservedProvisioning_APPIA */ +#define word_AQ_GlobalReservedProvisioning_APPIA_smartPower_downEnable u5.word_5 + +/*! \brief Base register address of structure AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_baseRegisterAddress 0xC800 +/*! \brief MMD address of structure AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure pairAStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_pairAStatus 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairAStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairAStatus u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairAStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairAStatus u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairBStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_pairBStatus 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairBStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairBStatus u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairBStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairBStatus u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairCStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_pairCStatus 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairCStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairCStatus u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairCStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairCStatus u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairDStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_pairDStatus 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairDStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairDStatus u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairDStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairDStatus u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_pairAReflection_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairAReflection_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairAReflection_1 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_pairAReflection_2 1 +/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairAReflection_2 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairAReflection_2 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure impulseResponseMSW in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_impulseResponseMSW 2 +/*! \brief Preprocessor variable to relate field to bit position in structure impulseResponseMSW in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_impulseResponseMSW u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure impulseResponseMSW in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_impulseResponseMSW u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_pairBReflection_1 3 +/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairBReflection_1 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairBReflection_1 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_pairBReflection_2 3 +/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairBReflection_2 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairBReflection_2 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure impulseResponseLSW in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_impulseResponseLSW 4 +/*! \brief Preprocessor variable to relate field to bit position in structure impulseResponseLSW in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_impulseResponseLSW u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure impulseResponseLSW in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_impulseResponseLSW u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_pairCReflection_1 5 +/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairCReflection_1 u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairCReflection_1 u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_pairCReflection_2 5 +/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairCReflection_2 u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairCReflection_2 u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_reserved_1 6 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_reserved_1 u6.bits_6 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_reserved_1 u6.word_6 +/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_pairDReflection_1 7 +/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairDReflection_1 u7.bits_7 +/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairDReflection_1 u7.word_7 +/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_pairDReflection_2 7 +/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairDReflection_2 u7.bits_7 +/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairDReflection_2 u7.word_7 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define AQ_GlobalCableDiagnosticStatus_APPIA_reserved_2 8 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_reserved_2 u8.bits_8 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ +#define word_AQ_GlobalCableDiagnosticStatus_APPIA_reserved_2 u8.word_8 + +/*! \brief Base register address of structure AQ_GlobalThermalStatus_APPIA */ +#define AQ_GlobalThermalStatus_APPIA_baseRegisterAddress 0xC820 +/*! \brief MMD address of structure AQ_GlobalThermalStatus_APPIA */ +#define AQ_GlobalThermalStatus_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure temperature in AQ_GlobalThermalStatus_APPIA */ +#define AQ_GlobalThermalStatus_APPIA_temperature 0 +/*! \brief Preprocessor variable to relate field to bit position in structure temperature in AQ_GlobalThermalStatus_APPIA */ +#define bits_AQ_GlobalThermalStatus_APPIA_temperature u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure temperature in AQ_GlobalThermalStatus_APPIA */ +#define word_AQ_GlobalThermalStatus_APPIA_temperature u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure temperatureReady in AQ_GlobalThermalStatus_APPIA */ +#define AQ_GlobalThermalStatus_APPIA_temperatureReady 1 +/*! \brief Preprocessor variable to relate field to bit position in structure temperatureReady in AQ_GlobalThermalStatus_APPIA */ +#define bits_AQ_GlobalThermalStatus_APPIA_temperatureReady u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure temperatureReady in AQ_GlobalThermalStatus_APPIA */ +#define word_AQ_GlobalThermalStatus_APPIA_temperatureReady u1.word_1 + +/*! \brief Base register address of structure AQ_GlobalGeneralStatus_APPIA */ +#define AQ_GlobalGeneralStatus_APPIA_baseRegisterAddress 0xC830 +/*! \brief MMD address of structure AQ_GlobalGeneralStatus_APPIA */ +#define AQ_GlobalGeneralStatus_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureFailureState in AQ_GlobalGeneralStatus_APPIA */ +#define AQ_GlobalGeneralStatus_APPIA_highTemperatureFailureState 0 +/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureFailureState in AQ_GlobalGeneralStatus_APPIA */ +#define bits_AQ_GlobalGeneralStatus_APPIA_highTemperatureFailureState u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureFailureState in AQ_GlobalGeneralStatus_APPIA */ +#define word_AQ_GlobalGeneralStatus_APPIA_highTemperatureFailureState u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureFailureState in AQ_GlobalGeneralStatus_APPIA */ +#define AQ_GlobalGeneralStatus_APPIA_lowTemperatureFailureState 0 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureFailureState in AQ_GlobalGeneralStatus_APPIA */ +#define bits_AQ_GlobalGeneralStatus_APPIA_lowTemperatureFailureState u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureFailureState in AQ_GlobalGeneralStatus_APPIA */ +#define word_AQ_GlobalGeneralStatus_APPIA_lowTemperatureFailureState u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureWarningState in AQ_GlobalGeneralStatus_APPIA */ +#define AQ_GlobalGeneralStatus_APPIA_highTemperatureWarningState 0 +/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureWarningState in AQ_GlobalGeneralStatus_APPIA */ +#define bits_AQ_GlobalGeneralStatus_APPIA_highTemperatureWarningState u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureWarningState in AQ_GlobalGeneralStatus_APPIA */ +#define word_AQ_GlobalGeneralStatus_APPIA_highTemperatureWarningState u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureWarningState in AQ_GlobalGeneralStatus_APPIA */ +#define AQ_GlobalGeneralStatus_APPIA_lowTemperatureWarningState 0 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureWarningState in AQ_GlobalGeneralStatus_APPIA */ +#define bits_AQ_GlobalGeneralStatus_APPIA_lowTemperatureWarningState u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureWarningState in AQ_GlobalGeneralStatus_APPIA */ +#define word_AQ_GlobalGeneralStatus_APPIA_lowTemperatureWarningState u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure processorIntensiveMdioOperationIn_Progress in AQ_GlobalGeneralStatus_APPIA */ +#define AQ_GlobalGeneralStatus_APPIA_processorIntensiveMdioOperationIn_Progress 1 +/*! \brief Preprocessor variable to relate field to bit position in structure processorIntensiveMdioOperationIn_Progress in AQ_GlobalGeneralStatus_APPIA */ +#define bits_AQ_GlobalGeneralStatus_APPIA_processorIntensiveMdioOperationIn_Progress u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure processorIntensiveMdioOperationIn_Progress in AQ_GlobalGeneralStatus_APPIA */ +#define word_AQ_GlobalGeneralStatus_APPIA_processorIntensiveMdioOperationIn_Progress u1.word_1 + +/*! \brief Base register address of structure AQ_GlobalPinStatus_APPIA */ +#define AQ_GlobalPinStatus_APPIA_baseRegisterAddress 0xC840 +/*! \brief MMD address of structure AQ_GlobalPinStatus_APPIA */ +#define AQ_GlobalPinStatus_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mdioBootLoad in AQ_GlobalPinStatus_APPIA */ +#define AQ_GlobalPinStatus_APPIA_mdioBootLoad 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioBootLoad in AQ_GlobalPinStatus_APPIA */ +#define bits_AQ_GlobalPinStatus_APPIA_mdioBootLoad u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mdioBootLoad in AQ_GlobalPinStatus_APPIA */ +#define word_AQ_GlobalPinStatus_APPIA_mdioBootLoad u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure packageConnectivity in AQ_GlobalPinStatus_APPIA */ +#define AQ_GlobalPinStatus_APPIA_packageConnectivity 0 +/*! \brief Preprocessor variable to relate field to bit position in structure packageConnectivity in AQ_GlobalPinStatus_APPIA */ +#define bits_AQ_GlobalPinStatus_APPIA_packageConnectivity u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure packageConnectivity in AQ_GlobalPinStatus_APPIA */ +#define word_AQ_GlobalPinStatus_APPIA_packageConnectivity u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure txEnable in AQ_GlobalPinStatus_APPIA */ +#define AQ_GlobalPinStatus_APPIA_txEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure txEnable in AQ_GlobalPinStatus_APPIA */ +#define bits_AQ_GlobalPinStatus_APPIA_txEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure txEnable in AQ_GlobalPinStatus_APPIA */ +#define word_AQ_GlobalPinStatus_APPIA_txEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure ledPullupState in AQ_GlobalPinStatus_APPIA */ +#define AQ_GlobalPinStatus_APPIA_ledPullupState 0 +/*! \brief Preprocessor variable to relate field to bit position in structure ledPullupState in AQ_GlobalPinStatus_APPIA */ +#define bits_AQ_GlobalPinStatus_APPIA_ledPullupState u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure ledPullupState in AQ_GlobalPinStatus_APPIA */ +#define word_AQ_GlobalPinStatus_APPIA_ledPullupState u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalDaisyChainStatus_APPIA */ +#define AQ_GlobalDaisyChainStatus_APPIA_baseRegisterAddress 0xC842 +/*! \brief MMD address of structure AQ_GlobalDaisyChainStatus_APPIA */ +#define AQ_GlobalDaisyChainStatus_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure rxDaisyChainCalculatedCrc in AQ_GlobalDaisyChainStatus_APPIA */ +#define AQ_GlobalDaisyChainStatus_APPIA_rxDaisyChainCalculatedCrc 0 +/*! \brief Preprocessor variable to relate field to bit position in structure rxDaisyChainCalculatedCrc in AQ_GlobalDaisyChainStatus_APPIA */ +#define bits_AQ_GlobalDaisyChainStatus_APPIA_rxDaisyChainCalculatedCrc u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure rxDaisyChainCalculatedCrc in AQ_GlobalDaisyChainStatus_APPIA */ +#define word_AQ_GlobalDaisyChainStatus_APPIA_rxDaisyChainCalculatedCrc u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalFaultMessage_APPIA */ +#define AQ_GlobalFaultMessage_APPIA_baseRegisterAddress 0xC850 +/*! \brief MMD address of structure AQ_GlobalFaultMessage_APPIA */ +#define AQ_GlobalFaultMessage_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure message in AQ_GlobalFaultMessage_APPIA */ +#define AQ_GlobalFaultMessage_APPIA_message 0 +/*! \brief Preprocessor variable to relate field to bit position in structure message in AQ_GlobalFaultMessage_APPIA */ +#define bits_AQ_GlobalFaultMessage_APPIA_message u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure message in AQ_GlobalFaultMessage_APPIA */ +#define word_AQ_GlobalFaultMessage_APPIA_message u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalPrimaryStatus_APPIA */ +#define AQ_GlobalPrimaryStatus_APPIA_baseRegisterAddress 0xC851 +/*! \brief MMD address of structure AQ_GlobalPrimaryStatus_APPIA */ +#define AQ_GlobalPrimaryStatus_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure primaryStatus in AQ_GlobalPrimaryStatus_APPIA */ +#define AQ_GlobalPrimaryStatus_APPIA_primaryStatus 0 +/*! \brief Preprocessor variable to relate field to bit position in structure primaryStatus in AQ_GlobalPrimaryStatus_APPIA */ +#define bits_AQ_GlobalPrimaryStatus_APPIA_primaryStatus u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure primaryStatus in AQ_GlobalPrimaryStatus_APPIA */ +#define word_AQ_GlobalPrimaryStatus_APPIA_primaryStatus u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_baseRegisterAddress 0xC880 +/*! \brief MMD address of structure AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure reserved_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_1 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_1 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_1 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_1 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_1 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_1 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_2 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_2 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_2 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_2 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_2 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_2 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_3 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_3 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_3 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_3 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_3 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_3 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_4 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_4 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_4 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_4 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_4 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_4 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_5 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_5 1 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_5 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_5 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_5 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_5 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_1 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_6 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_6 1 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_6 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_6 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_6 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_6 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_2 1 +/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_2 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_2 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_7 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_7 1 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_7 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_7 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_7 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_7 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_3 1 +/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_3 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_3 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_8 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_8 1 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_8 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_8 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_8 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_8 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_4 1 +/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_4 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_4 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_9 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_9 2 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_9 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_9 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_9 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_9 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_1 2 +/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_1 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_1 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_10 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_10 2 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_10 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_10 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_10 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_10 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_2 2 +/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_2 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_2 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_11 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_11 2 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_11 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_11 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_11 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_11 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_3 2 +/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_3 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_3 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_12 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_12 2 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_12 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_12 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_12 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_12 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_4 2 +/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_4 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_4 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_13 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_13 3 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_13 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_13 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_13 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_13 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_1 3 +/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_1 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_1 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_14 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_14 3 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_14 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_14 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_14 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_14 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_2 3 +/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_2 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_2 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_15 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_15 3 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_15 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_15 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_15 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_15 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_3 3 +/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_3 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_3 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_16 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_16 3 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_16 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_16 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_16 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_16 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_4 3 +/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_4 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ +#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_4 u3.word_3 + +/*! \brief Base register address of structure AQ_GlobalStatus_APPIA */ +#define AQ_GlobalStatus_APPIA_baseRegisterAddress 0xC884 +/*! \brief MMD address of structure AQ_GlobalStatus_APPIA */ +#define AQ_GlobalStatus_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure reservedStatus_0 in AQ_GlobalStatus_APPIA */ +#define AQ_GlobalStatus_APPIA_reservedStatus_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedStatus_0 in AQ_GlobalStatus_APPIA */ +#define bits_AQ_GlobalStatus_APPIA_reservedStatus_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedStatus_0 in AQ_GlobalStatus_APPIA */ +#define word_AQ_GlobalStatus_APPIA_reservedStatus_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure cableLength in AQ_GlobalStatus_APPIA */ +#define AQ_GlobalStatus_APPIA_cableLength 0 +/*! \brief Preprocessor variable to relate field to bit position in structure cableLength in AQ_GlobalStatus_APPIA */ +#define bits_AQ_GlobalStatus_APPIA_cableLength u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure cableLength in AQ_GlobalStatus_APPIA */ +#define word_AQ_GlobalStatus_APPIA_cableLength u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalReservedStatus_APPIA */ +#define AQ_GlobalReservedStatus_APPIA_baseRegisterAddress 0xC885 +/*! \brief MMD address of structure AQ_GlobalReservedStatus_APPIA */ +#define AQ_GlobalReservedStatus_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure nearlySecondsMSW in AQ_GlobalReservedStatus_APPIA */ +#define AQ_GlobalReservedStatus_APPIA_nearlySecondsMSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nearlySecondsMSW in AQ_GlobalReservedStatus_APPIA */ +#define bits_AQ_GlobalReservedStatus_APPIA_nearlySecondsMSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nearlySecondsMSW in AQ_GlobalReservedStatus_APPIA */ +#define word_AQ_GlobalReservedStatus_APPIA_nearlySecondsMSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure xenpakNvrStatus in AQ_GlobalReservedStatus_APPIA */ +#define AQ_GlobalReservedStatus_APPIA_xenpakNvrStatus 0 +/*! \brief Preprocessor variable to relate field to bit position in structure xenpakNvrStatus in AQ_GlobalReservedStatus_APPIA */ +#define bits_AQ_GlobalReservedStatus_APPIA_xenpakNvrStatus u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure xenpakNvrStatus in AQ_GlobalReservedStatus_APPIA */ +#define word_AQ_GlobalReservedStatus_APPIA_xenpakNvrStatus u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure romRevision in AQ_GlobalReservedStatus_APPIA */ +#define AQ_GlobalReservedStatus_APPIA_romRevision 0 +/*! \brief Preprocessor variable to relate field to bit position in structure romRevision in AQ_GlobalReservedStatus_APPIA */ +#define bits_AQ_GlobalReservedStatus_APPIA_romRevision u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure romRevision in AQ_GlobalReservedStatus_APPIA */ +#define word_AQ_GlobalReservedStatus_APPIA_romRevision u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nearlySecondsLSW in AQ_GlobalReservedStatus_APPIA */ +#define AQ_GlobalReservedStatus_APPIA_nearlySecondsLSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure nearlySecondsLSW in AQ_GlobalReservedStatus_APPIA */ +#define bits_AQ_GlobalReservedStatus_APPIA_nearlySecondsLSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure nearlySecondsLSW in AQ_GlobalReservedStatus_APPIA */ +#define word_AQ_GlobalReservedStatus_APPIA_nearlySecondsLSW u1.word_1 + +/*! \brief Base register address of structure AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_baseRegisterAddress 0xCC00 +/*! \brief MMD address of structure AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureFailure in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_highTemperatureFailure 0 +/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureFailure in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_highTemperatureFailure u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureFailure in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_highTemperatureFailure u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureFailure in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_lowTemperatureFailure 0 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureFailure in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_lowTemperatureFailure u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureFailure in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_lowTemperatureFailure u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureWarning in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_highTemperatureWarning 0 +/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureWarning in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_highTemperatureWarning u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureWarning in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_highTemperatureWarning u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureWarning in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_lowTemperatureWarning 0 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureWarning in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_lowTemperatureWarning u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureWarning in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_lowTemperatureWarning u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure resetCompleted in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_resetCompleted 0 +/*! \brief Preprocessor variable to relate field to bit position in structure resetCompleted in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_resetCompleted u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure resetCompleted in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_resetCompleted u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure deviceFault in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_deviceFault 0 +/*! \brief Preprocessor variable to relate field to bit position in structure deviceFault in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_deviceFault u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure deviceFault in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_deviceFault u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmA in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_reservedAlarmA 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmA in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_reservedAlarmA u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmA in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_reservedAlarmA u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmB in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_reservedAlarmB 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmB in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_reservedAlarmB u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmB in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_reservedAlarmB u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmC in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_reservedAlarmC 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmC in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_reservedAlarmC u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmC in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_reservedAlarmC u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmD in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_reservedAlarmD 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmD in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_reservedAlarmD u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmD in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_reservedAlarmD u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure smartPower_downEntered in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_smartPower_downEntered 1 +/*! \brief Preprocessor variable to relate field to bit position in structure smartPower_downEntered in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_smartPower_downEntered u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure smartPower_downEntered in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_smartPower_downEntered u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure xenpakAlarm in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_xenpakAlarm 1 +/*! \brief Preprocessor variable to relate field to bit position in structure xenpakAlarm in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_xenpakAlarm u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure xenpakAlarm in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_xenpakAlarm u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarms in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_reservedAlarms 1 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarms in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_reservedAlarms u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarms in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_reservedAlarms u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mdioCommandHandlingOverflow in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_mdioCommandHandlingOverflow 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioCommandHandlingOverflow in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_mdioCommandHandlingOverflow u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mdioCommandHandlingOverflow in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_mdioCommandHandlingOverflow u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure diagnosticAlarm in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_diagnosticAlarm 1 +/*! \brief Preprocessor variable to relate field to bit position in structure diagnosticAlarm in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_diagnosticAlarm u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure diagnosticAlarm in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_diagnosticAlarm u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure nvrOperationComplete in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_nvrOperationComplete 2 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrOperationComplete in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_nvrOperationComplete u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure nvrOperationComplete in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_nvrOperationComplete u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure mailboxOperation_Complete in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_mailboxOperation_Complete 2 +/*! \brief Preprocessor variable to relate field to bit position in structure mailboxOperation_Complete in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_mailboxOperation_Complete u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure mailboxOperation_Complete in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_mailboxOperation_Complete u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure upDramParityError in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_upDramParityError 2 +/*! \brief Preprocessor variable to relate field to bit position in structure upDramParityError in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_upDramParityError u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure upDramParityError in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_upDramParityError u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure upIramParityError in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_upIramParityError 2 +/*! \brief Preprocessor variable to relate field to bit position in structure upIramParityError in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_upIramParityError u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure upIramParityError in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_upIramParityError u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure txEnableStateChange in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_txEnableStateChange 2 +/*! \brief Preprocessor variable to relate field to bit position in structure txEnableStateChange in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_txEnableStateChange u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure txEnableStateChange in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_txEnableStateChange u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure mdioMMD_Error in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_mdioMMD_Error 2 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioMMD_Error in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_mdioMMD_Error u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure mdioMMD_Error in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_mdioMMD_Error u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure mdioTimeoutError in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_mdioTimeoutError 2 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioTimeoutError in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_mdioTimeoutError u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure mdioTimeoutError in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_mdioTimeoutError u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure watchdogTimerAlarm in AQ_GlobalAlarms_APPIA */ +#define AQ_GlobalAlarms_APPIA_watchdogTimerAlarm 2 +/*! \brief Preprocessor variable to relate field to bit position in structure watchdogTimerAlarm in AQ_GlobalAlarms_APPIA */ +#define bits_AQ_GlobalAlarms_APPIA_watchdogTimerAlarm u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure watchdogTimerAlarm in AQ_GlobalAlarms_APPIA */ +#define word_AQ_GlobalAlarms_APPIA_watchdogTimerAlarm u2.word_2 + +/*! \brief Base register address of structure AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_baseRegisterAddress 0xD400 +/*! \brief MMD address of structure AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureFailureMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_highTemperatureFailureMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureFailureMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_highTemperatureFailureMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureFailureMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_highTemperatureFailureMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureFailureMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_lowTemperatureFailureMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureFailureMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_lowTemperatureFailureMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureFailureMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_lowTemperatureFailureMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureWarningMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_highTemperatureWarningMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureWarningMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_highTemperatureWarningMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureWarningMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_highTemperatureWarningMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureWarningMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_lowTemperatureWarningMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureWarningMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_lowTemperatureWarningMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureWarningMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_lowTemperatureWarningMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure resetCompletedMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_resetCompletedMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure resetCompletedMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_resetCompletedMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure resetCompletedMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_resetCompletedMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure deviceFaultMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_deviceFaultMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure deviceFaultMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_deviceFaultMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure deviceFaultMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_deviceFaultMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmAMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_reservedAlarmAMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmAMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_reservedAlarmAMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmAMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_reservedAlarmAMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmBMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_reservedAlarmBMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmBMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_reservedAlarmBMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmBMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_reservedAlarmBMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmCMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_reservedAlarmCMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmCMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_reservedAlarmCMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmCMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_reservedAlarmCMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmDMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_reservedAlarmDMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmDMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_reservedAlarmDMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmDMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_reservedAlarmDMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure smartPower_downEnteredMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_smartPower_downEnteredMask 1 +/*! \brief Preprocessor variable to relate field to bit position in structure smartPower_downEnteredMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_smartPower_downEnteredMask u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure smartPower_downEnteredMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_smartPower_downEnteredMask u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure xenpakAlarmMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_xenpakAlarmMask 1 +/*! \brief Preprocessor variable to relate field to bit position in structure xenpakAlarmMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_xenpakAlarmMask u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure xenpakAlarmMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_xenpakAlarmMask u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmsMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_reservedAlarmsMask 1 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmsMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_reservedAlarmsMask u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmsMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_reservedAlarmsMask u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mdioCommandHandlingOverflowMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_mdioCommandHandlingOverflowMask 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioCommandHandlingOverflowMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_mdioCommandHandlingOverflowMask u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mdioCommandHandlingOverflowMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_mdioCommandHandlingOverflowMask u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure diagnosticAlarmMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_diagnosticAlarmMask 1 +/*! \brief Preprocessor variable to relate field to bit position in structure diagnosticAlarmMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_diagnosticAlarmMask u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure diagnosticAlarmMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_diagnosticAlarmMask u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure nvrOperationCompleteMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_nvrOperationCompleteMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrOperationCompleteMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_nvrOperationCompleteMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure nvrOperationCompleteMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_nvrOperationCompleteMask u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure mailboxOperationCompleteMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_mailboxOperationCompleteMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure mailboxOperationCompleteMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_mailboxOperationCompleteMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure mailboxOperationCompleteMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_mailboxOperationCompleteMask u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure upDramParityErrorMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_upDramParityErrorMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure upDramParityErrorMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_upDramParityErrorMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure upDramParityErrorMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_upDramParityErrorMask u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure upIramParityErrorMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_upIramParityErrorMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure upIramParityErrorMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_upIramParityErrorMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure upIramParityErrorMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_upIramParityErrorMask u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure txEnableStateChangeMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_txEnableStateChangeMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure txEnableStateChangeMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_txEnableStateChangeMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure txEnableStateChangeMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_txEnableStateChangeMask u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure mdioMMD_ErrorMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_mdioMMD_ErrorMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioMMD_ErrorMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_mdioMMD_ErrorMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure mdioMMD_ErrorMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_mdioMMD_ErrorMask u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure mdioTimeoutErrorMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_mdioTimeoutErrorMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioTimeoutErrorMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_mdioTimeoutErrorMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure mdioTimeoutErrorMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_mdioTimeoutErrorMask u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure watchdogTimerAlarmMask in AQ_GlobalInterruptMask_APPIA */ +#define AQ_GlobalInterruptMask_APPIA_watchdogTimerAlarmMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure watchdogTimerAlarmMask in AQ_GlobalInterruptMask_APPIA */ +#define bits_AQ_GlobalInterruptMask_APPIA_watchdogTimerAlarmMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure watchdogTimerAlarmMask in AQ_GlobalInterruptMask_APPIA */ +#define word_AQ_GlobalInterruptMask_APPIA_watchdogTimerAlarmMask u2.word_2 + +/*! \brief Base register address of structure AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_baseRegisterAddress 0xFC00 +/*! \brief MMD address of structure AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure pmaStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pmaStandardAlarm_1Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pmaStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pmaStandardAlarm_1Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pmaStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pmaStandardAlarm_1Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pmaStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pmaStandardAlarm_2Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pmaStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pmaStandardAlarm_2Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pmaStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pmaStandardAlarm_2Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pcsStandardAlarm_1Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pcsStandardAlarm_1Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pcsStandardAlarm_1Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pcsStandardAlarm_2Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pcsStandardAlarm_2Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pcsStandardAlarm_2Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_3Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pcsStandardAlarm_3Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_3Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pcsStandardAlarm_3Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_3Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pcsStandardAlarm_3Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure phyXS_StandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_phyXS_StandardAlarms_1Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_StandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_phyXS_StandardAlarms_1Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure phyXS_StandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_phyXS_StandardAlarms_1Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure phyXS_StandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_phyXS_StandardAlarms_2Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_StandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_phyXS_StandardAlarms_2Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure phyXS_StandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_phyXS_StandardAlarms_2Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationStandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_autonegotiationStandardAlarms_1Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationStandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_autonegotiationStandardAlarms_1Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationStandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_autonegotiationStandardAlarms_1Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationStandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_autonegotiationStandardAlarms_2Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationStandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_autonegotiationStandardAlarms_2Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationStandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_autonegotiationStandardAlarms_2Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure gbeStandardAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_gbeStandardAlarmsInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure gbeStandardAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_gbeStandardAlarmsInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure gbeStandardAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_gbeStandardAlarmsInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure allVendorAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_allVendorAlarmsInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure allVendorAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_allVendorAlarmsInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure allVendorAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_allVendorAlarmsInterrupt u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideVendorInterruptFlags_APPIA_baseRegisterAddress 0xFC01 +/*! \brief MMD address of structure AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideVendorInterruptFlags_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure pmaVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideVendorInterruptFlags_APPIA_pmaVendorAlarmInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pmaVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_pmaVendorAlarmInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pmaVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_pmaVendorAlarmInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideVendorInterruptFlags_APPIA_pcsVendorAlarmInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_pcsVendorAlarmInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_pcsVendorAlarmInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure phyXS_VendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideVendorInterruptFlags_APPIA_phyXS_VendorAlarmInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_VendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_phyXS_VendorAlarmInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure phyXS_VendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_phyXS_VendorAlarmInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideVendorInterruptFlags_APPIA_autonegotiationVendorAlarmInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_autonegotiationVendorAlarmInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_autonegotiationVendorAlarmInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure gbeVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideVendorInterruptFlags_APPIA_gbeVendorAlarmInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure gbeVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_gbeVendorAlarmInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure gbeVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_gbeVendorAlarmInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_1Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideVendorInterruptFlags_APPIA_globalAlarms_1Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_1Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_globalAlarms_1Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_1Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_globalAlarms_1Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_2Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideVendorInterruptFlags_APPIA_globalAlarms_2Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_2Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_globalAlarms_2Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_2Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_globalAlarms_2Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_3Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define AQ_GlobalChip_wideVendorInterruptFlags_APPIA_globalAlarms_3Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_3Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_globalAlarms_3Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_3Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_globalAlarms_3Interrupt u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_baseRegisterAddress 0xFF00 +/*! \brief MMD address of structure AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure pmaStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_pmaStandardAlarm_1InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pmaStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_pmaStandardAlarm_1InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pmaStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_pmaStandardAlarm_1InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pmaStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_pmaStandardAlarm_2InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pmaStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_pmaStandardAlarm_2InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pmaStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_pmaStandardAlarm_2InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_pcsStandardAlarm_1InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_pcsStandardAlarm_1InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_pcsStandardAlarm_1InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_pcsStandardAlarm_2InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_pcsStandardAlarm_2InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_pcsStandardAlarm_2InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_3InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_pcsStandardAlarm_3InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_3InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_pcsStandardAlarm_3InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_3InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_pcsStandardAlarm_3InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure phyXS_StandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_phyXS_StandardAlarms_1InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_StandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_phyXS_StandardAlarms_1InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure phyXS_StandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_phyXS_StandardAlarms_1InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure phyXS_StandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_phyXS_StandardAlarms_2InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_StandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_phyXS_StandardAlarms_2InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure phyXS_StandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_phyXS_StandardAlarms_2InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationStandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_autonegotiationStandardAlarms_1InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationStandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_autonegotiationStandardAlarms_1InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationStandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_autonegotiationStandardAlarms_1InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationStandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_autonegotiationStandardAlarms_2InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationStandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_autonegotiationStandardAlarms_2InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationStandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_autonegotiationStandardAlarms_2InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure gbeStandardAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_gbeStandardAlarmsInterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure gbeStandardAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_gbeStandardAlarmsInterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure gbeStandardAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_gbeStandardAlarmsInterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure allVendorAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_allVendorAlarmsInterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure allVendorAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_allVendorAlarmsInterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure allVendorAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_allVendorAlarmsInterruptMask u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define AQ_GlobalInterruptChip_wideVendorMask_APPIA_baseRegisterAddress 0xFF01 +/*! \brief MMD address of structure AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define AQ_GlobalInterruptChip_wideVendorMask_APPIA_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure pmaVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define AQ_GlobalInterruptChip_wideVendorMask_APPIA_pmaVendorAlarmInterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pmaVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_APPIA_pmaVendorAlarmInterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pmaVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_APPIA_pmaVendorAlarmInterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define AQ_GlobalInterruptChip_wideVendorMask_APPIA_pcsVendorAlarmInterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_APPIA_pcsVendorAlarmInterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_APPIA_pcsVendorAlarmInterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure phyXS_VendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define AQ_GlobalInterruptChip_wideVendorMask_APPIA_phyXS_VendorAlarmInterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_VendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_APPIA_phyXS_VendorAlarmInterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure phyXS_VendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_APPIA_phyXS_VendorAlarmInterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define AQ_GlobalInterruptChip_wideVendorMask_APPIA_autonegotiationVendorAlarmInterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_APPIA_autonegotiationVendorAlarmInterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_APPIA_autonegotiationVendorAlarmInterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure gbeVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define AQ_GlobalInterruptChip_wideVendorMask_APPIA_gbeVendorAlarmInterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure gbeVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_APPIA_gbeVendorAlarmInterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure gbeVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_APPIA_gbeVendorAlarmInterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define AQ_GlobalInterruptChip_wideVendorMask_APPIA_globalAlarms_1InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_APPIA_globalAlarms_1InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_APPIA_globalAlarms_1InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define AQ_GlobalInterruptChip_wideVendorMask_APPIA_globalAlarms_2InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_APPIA_globalAlarms_2InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_APPIA_globalAlarms_2InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_3InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define AQ_GlobalInterruptChip_wideVendorMask_APPIA_globalAlarms_3InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_3InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_APPIA_globalAlarms_3InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_3InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_APPIA_globalAlarms_3InterruptMask u0.word_0 +#endif +/*@}*/ +/*@}*/ diff --git a/qca/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers_reversed.h b/qca/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers_reversed.h new file mode 100644 index 000000000..89e02c325 --- /dev/null +++ b/qca/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers_reversed.h @@ -0,0 +1,5581 @@ +/*! \file +* This file contains the data structures and doxygen comments +* for the Global Registers block. + */ + +/*! \addtogroup registerMap + @{ +*/ + +/*! \defgroup Global_registers Global Registers +* This module contains the data structures and doxygen comments +* for the Global Registers block. + */ +/*********************************************************************** +* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +* +* $Date: 2014/04/08 $ +* +* $Label: $ +* +* Description: +* +* This file contains the c header structures for the registers contained in the Global Registers block. +* +* The bit fields in this structure are from MSbit to LSbit +* +***********************************************************************/ + + +/*@{*/ +#ifndef AQ_APPIA_GLOBAL_REGS_HEADER +#define AQ_APPIA_GLOBAL_REGS_HEADER + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Control 1: 1E.0000 */ +/* Global Standard Control 1: 1E.0000 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Control 1 */ + union + { + struct + { + /*! \brief 1E.0000.F R/WSC Soft Reset + AQ_GlobalStandardControl_1_APPIA.u0.bits_0.softReset + + Default = 0x1 + + 1 = Global soft reset + 0 = Normal operation + + + Notes: + Setting this bit initiates a global soft reset on all of the digital logic, including the microprocessor. Upon completion of the reset sequence, this bit is set back to 0. */ + unsigned int softReset : 1; /* 1E.0000.F R/WSC Default = 0x1 */ + /* 1 = Global soft reset + 0 = Normal operation + */ + /*! \brief 1E.0000.E R/WSC Hard Reset + AQ_GlobalStandardControl_1_APPIA.u0.bits_0.hardReset + + Default = 0x0 + + 1 = Global hard reset + 0 = Normal operation + + + Notes: + Setting this bit initiates a global hard reset, equivalent to pulling the reset pin low. This is a level sensitive pin that connects into the power-on reset generation circuitry to initiate a complete power-on reset. */ + unsigned int hardReset : 1; /* 1E.0000.E R/WSC Default = 0x0 */ + /* 1 = Global hard reset + 0 = Normal operation + */ + unsigned int reserved0 : 2; + /*! \brief 1E.0000.B R/WPD Low Power + AQ_GlobalStandardControl_1_APPIA.u0.bits_0.lowPower + + Provisionable Default = 0x0 + + 1 = Low-power mode + 0 = Normal operation + + + Notes: + A one written to this register causes the chip to enter low-power mode. This bit puts the entire chip in low-power mode, with only the MDIO and microprocessor functioning, and turns off the analog front-end: i.e. places it in high-impedance mode. Setting this bit also sets all of the Low Power bits in the other MMDs. */ + unsigned int lowPower : 1; /* 1E.0000.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Low-power mode + 0 = Normal operation + */ + unsigned int reserved1 : 11; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardControl_1_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Device Identifier: 1E.0002 */ +/* Global Standard Device Identifier: 1E.0002 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Device Identifier */ + union + { + struct + { + /*! \brief 1E.0002.F:0 RO Device ID MSW [1F:10] + AQ_GlobalStandardDeviceIdentifier_APPIA.u0.bits_0.deviceIdMSW + + + + Bits 31 - 16 of Device ID + */ + unsigned int deviceIdMSW : 16; /* 1E.0002.F:0 RO */ + /* Bits 31 - 16 of Device ID */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Standard Device Identifier */ + union + { + struct + { + /*! \brief 1E.0003.F:0 RO Device ID LSW [F:0] + AQ_GlobalStandardDeviceIdentifier_APPIA.u1.bits_1.deviceIdLSW + + + + Bits 15 - 0 of Device ID + */ + unsigned int deviceIdLSW : 16; /* 1E.0003.F:0 RO */ + /* Bits 15 - 0 of Device ID */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalStandardDeviceIdentifier_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Devices in Package: 1E.0005 */ +/* Global Standard Devices in Package: 1E.0005 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Devices in Package */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.0005.7 ROS Autonegotiation Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.autonegotiationPresent + + Default = 0x1 + + 1 = Autonegotiation is present in package + 0 = Autonegotiation is not present in package + + Notes: + This is always set to 1, as there is Autonegotiation in the PHY. */ + unsigned int autonegotiationPresent : 1; /* 1E.0005.7 ROS Default = 0x1 */ + /* 1 = Autonegotiation is present in package + 0 = Autonegotiation is not present in package */ + /*! \brief 1E.0005.6 ROS TC Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.tcPresent + + Default = 0x0 + + 1 = TC is present in package + 0 = TC is not present in package + + Notes: + This is always set to 0, as there is no TC functionality in the PHY. */ + unsigned int tcPresent : 1; /* 1E.0005.6 ROS Default = 0x0 */ + /* 1 = TC is present in package + 0 = TC is not present in package */ + /*! \brief 1E.0005.5 ROS DTE XS Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.dteXsPresent + + Default = 0x0 + + 1 = DTE XS is present in package + 0 = DTE XS is not present in package + + + Notes: + This is always set to 0, as there is no DTE XAUI interface in the PHY. */ + unsigned int dteXsPresent : 1; /* 1E.0005.5 ROS Default = 0x0 */ + /* 1 = DTE XS is present in package + 0 = DTE XS is not present in package + */ + /*! \brief 1E.0005.4 ROS PHY XS Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.phyXS_Present + + Default = 0x1 + + 1 = PHY XS is present in package + 0 = PHY XS is not present in package + + Notes: + This is always set to 1 as there is a PHY XS interface in the PHY. */ + unsigned int phyXS_Present : 1; /* 1E.0005.4 ROS Default = 0x1 */ + /* 1 = PHY XS is present in package + 0 = PHY XS is not present in package */ + /*! \brief 1E.0005.3 ROS PCS Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.pcsPresent + + Default = 0x1 + + 1 = PCS is present in package + 0 = PCS is not present in package + + Notes: + This is always set to 1 as there is PCS functionality in the PHY. */ + unsigned int pcsPresent : 1; /* 1E.0005.3 ROS Default = 0x1 */ + /* 1 = PCS is present in package + 0 = PCS is not present in package */ + /*! \brief 1E.0005.2 ROS WIS Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.wisPresent + + Default = 0x0 + + 1 = WIS is present in package + 0 = WIS is not present in package + + Notes: + This is always set to 0, as there is no WIS functionality in the PHY. */ + unsigned int wisPresent : 1; /* 1E.0005.2 ROS Default = 0x0 */ + /* 1 = WIS is present in package + 0 = WIS is not present in package */ + /*! \brief 1E.0005.1 ROS PMA Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.pmaPresent + + Default = 0x1 + + 1 = PMA is present in package + 0 = PMA is not present + + Notes: + This is always set to 1 as there is PMA functionality in the PHY. */ + unsigned int pmaPresent : 1; /* 1E.0005.1 ROS Default = 0x1 */ + /* 1 = PMA is present in package + 0 = PMA is not present */ + /*! \brief 1E.0005.0 ROS Clause 22 Registers Present + AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.clause_22RegistersPresent + + Default = 0x0 + + 1 = Clause 22 registers are present in package + 0 = Clause 22 registers are not present in package + + Notes: + This is always set to 0 in the PHY, as there are no Clause 22 registers in the device. */ + unsigned int clause_22RegistersPresent : 1; /* 1E.0005.0 ROS Default = 0x0 */ + /* 1 = Clause 22 registers are present in package + 0 = Clause 22 registers are not present in package */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardDevicesInPackage_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Vendor Devices in Package: 1E.0006 */ +/* Global Standard Vendor Devices in Package: 1E.0006 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Vendor Devices in Package */ + union + { + struct + { + /*! \brief 1E.0006.F ROS Vendor Specific Device #2 Present + AQ_GlobalStandardVendorDevicesInPackage_APPIA.u0.bits_0.vendorSpecificDevice_2Present + + Default = 0x1 + + 1 = Device #2 is present in package + 0 = Device #2 is not present in package + + Notes: + This is always set to 1 as the PHY utilizes this device for the DSP PMA registers. */ + unsigned int vendorSpecificDevice_2Present : 1; /* 1E.0006.F ROS Default = 0x1 */ + /* 1 = Device #2 is present in package + 0 = Device #2 is not present in package */ + /*! \brief 1E.0006.E ROS Vendor Specific Device #1 Present + AQ_GlobalStandardVendorDevicesInPackage_APPIA.u0.bits_0.vendorSpecificDevice_1Present + + Default = 0x1 + + 1 = Device #1 is present in package + 0 = Device #1 is not present in package + + Notes: + This is always set to 1 as the PHY utilizes this device for the global control registers. */ + unsigned int vendorSpecificDevice_1Present : 1; /* 1E.0006.E ROS Default = 0x1 */ + /* 1 = Device #1 is present in package + 0 = Device #1 is not present in package */ + /*! \brief 1E.0006.D ROS Clause 22 Extension Present + AQ_GlobalStandardVendorDevicesInPackage_APPIA.u0.bits_0.clause_22ExtensionPresent + + Default = 0x1 + + 1 = Clause 22 Extension is present in package + 0 = Clause 22 Extension is not present in package + + Notes: + This is always set to 1 as the PHY utilizes this device for the GbE registers. */ + unsigned int clause_22ExtensionPresent : 1; /* 1E.0006.D ROS Default = 0x1 */ + /* 1 = Clause 22 Extension is present in package + 0 = Clause 22 Extension is not present in package */ + unsigned int reserved0 : 13; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardVendorDevicesInPackage_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Status 2: 1E.0008 */ +/* Global Standard Status 2: 1E.0008 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Status 2 */ + union + { + struct + { + /*! \brief 1E.0008.F:E ROS Device Present [1:0] + AQ_GlobalStandardStatus_2_APPIA.u0.bits_0.devicePresent + + Default = 0x2 + + [F:E] + 0x3 = No device at this address + 0x2 = Device present at this address + 0x1 = No device at this address + 0x0 = No device at this address + + Notes: + This field is always set to 0x2, as the Global MMD resides here in the PHY. */ + unsigned int devicePresent : 2; /* 1E.0008.F:E ROS Default = 0x2 */ + /* [F:E] + 0x3 = No device at this address + 0x2 = Device present at this address + 0x1 = No device at this address + 0x0 = No device at this address */ + unsigned int reserved0 : 14; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardStatus_2_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Package Identifier: 1E.000E */ +/* Global Standard Package Identifier: 1E.000E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Package Identifier */ + union + { + struct + { + /*! \brief 1E.000E.F:0 RO Package ID MSW [1F:10] + AQ_GlobalStandardPackageIdentifier_APPIA.u0.bits_0.packageIdMSW + + + + Bits 31- 16 of Package ID + */ + unsigned int packageIdMSW : 16; /* 1E.000E.F:0 RO */ + /* Bits 31- 16 of Package ID */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Standard Package Identifier */ + union + { + struct + { + /*! \brief 1E.000F.F:0 RO Package ID LSW [F:0] + AQ_GlobalStandardPackageIdentifier_APPIA.u1.bits_1.packageIdLSW + + + + Bits 15 - 0 of Package ID + */ + unsigned int packageIdLSW : 16; /* 1E.000F.F:0 RO */ + /* Bits 15 - 0 of Package ID */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalStandardPackageIdentifier_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Firmware ID: 1E.0020 */ +/* Global Firmware ID: 1E.0020 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Firmware ID */ + union + { + struct + { + /*! \brief 1E.0020.F:8 RO Firmware Major Revision Number [7:0] + AQ_GlobalFirmwareID_APPIA.u0.bits_0.firmwareMajorRevisionNumber + + + + [F:8] = Major revision number + + Notes: + + + The lower six bits of major and minor firmware revision are exchanged in autonegotiation when the PHYID message is sent. */ + unsigned int firmwareMajorRevisionNumber : 8; /* 1E.0020.F:8 RO */ + /* [F:8] = Major revision number */ + /*! \brief 1E.0020.7:0 RO Firmware Minor Revision Number [7:0] + AQ_GlobalFirmwareID_APPIA.u0.bits_0.firmwareMinorRevisionNumber + + + + [7:0] = Minor revision number + + Notes: + + + The lower six bits of major and minor firmware revision are exchanged in autonegotiation when the PHYID message is sent. */ + unsigned int firmwareMinorRevisionNumber : 8; /* 1E.0020.7:0 RO */ + /* [7:0] = Minor revision number */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalFirmwareID_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Chip Identification: 1E.0021 */ +/* Global Chip Identification: 1E.0021 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Chip Identification */ + union + { + struct + { + /*! \brief 1E.0021.F:0 RO Chip Identification [F:0] + AQ_GlobalChipIdentification_APPIA.u0.bits_0.chipIdentification + + + + Hardware Chip ID + + Notes: + This value is a hard-coded chip ID */ + unsigned int chipIdentification : 16; /* 1E.0021.F:0 RO */ + /* Hardware Chip ID */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalChipIdentification_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Chip Revision: 1E.0022 */ +/* Global Chip Revision: 1E.0022 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Chip Revision */ + union + { + struct + { + /*! \brief 1E.0022.F:0 RO Chip Revision [F:0] + AQ_GlobalChipRevision_APPIA.u0.bits_0.chipRevision + + + + Hardware Chip Revision + + Notes: + This value is a hard-coded chip revision */ + unsigned int chipRevision : 16; /* 1E.0022.F:0 RO */ + /* Hardware Chip Revision */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalChipRevision_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global NVR Interface: 1E.0100 */ +/* Global NVR Interface: 1E.0100 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0100.F R/WSC NVR Execute Operation + AQ_GlobalNvrInterface_APPIA.u0.bits_0.nvrExecuteOperation + + Default = 0x0 + + 1 = Start NVR Operation + + + Notes: + When set to 1, the NVR operation will begin. Ensure that the uP is stalled using the See MCP Run Stall bit to ensure no NVR contention. */ + unsigned int nvrExecuteOperation : 1; /* 1E.0100.F R/WSC Default = 0x0 */ + /* 1 = Start NVR Operation + */ + /*! \brief 1E.0100.E R/W NVR Write Mode + AQ_GlobalNvrInterface_APPIA.u0.bits_0.nvrWriteMode + + Default = 0x0 + + 1 = Write to NVR + 0 = Read from NVR + + */ + unsigned int nvrWriteMode : 1; /* 1E.0100.E R/W Default = 0x0 */ + /* 1 = Write to NVR + 0 = Read from NVR + */ + /*! \brief 1E.0100.D R/W Freeze NVR CRC + AQ_GlobalNvrInterface_APPIA.u0.bits_0.freezeNvrCrc + + Default = 0x0 + + 1 = Freeze NVR Mailbox CRC calculation register + + + Notes: + To prevent an erroneous answer, this bit should not be set at the same time the See NVR Operation Valid bit is set. */ + unsigned int freezeNvrCrc : 1; /* 1E.0100.D R/W Default = 0x0 */ + /* 1 = Freeze NVR Mailbox CRC calculation register + */ + /*! \brief 1E.0100.C R/WSC Reset NVR CRC + AQ_GlobalNvrInterface_APPIA.u0.bits_0.resetNvrCrc + + Default = 0x0 + + 1 = Reset NVR Mailbox CRC calculation register + + + Notes: + To prevent an erroneous answer, this bit should not be set at the same time the See NVR Operation Valid bit is set. */ + unsigned int resetNvrCrc : 1; /* 1E.0100.C R/WSC Default = 0x0 */ + /* 1 = Reset NVR Mailbox CRC calculation register + */ + unsigned int reserved0 : 1; + /*! \brief 1E.0100.A R/W NVR Burst + AQ_GlobalNvrInterface_APPIA.u0.bits_0.nvrBurst + + Default = 0x0 + + 0 = Single read or write operation of up to 4 bytes + 1 = Burst operation + + + Notes: + When this bit is set, the operation is a burst operation where more than 32-bits is read from the NVR or written to the NVR. This bit should be set to one until the last burst in the read or write operation, when it should be set to zero. It operates by gating the SPI clock, and not restarting it until new data is ready to be written, or the previous contents have been read. Each burst of data requires the NVR Execute Operation bit to be set to initiate the next phase. */ + unsigned int nvrBurst : 1; /* 1E.0100.A R/W Default = 0x0 */ + /* 0 = Single read or write operation of up to 4 bytes + 1 = Burst operation + */ + unsigned int reserved1 : 1; + /*! \brief 1E.0100.8 RO NVR Busy + AQ_GlobalNvrInterface_APPIA.u0.bits_0.nvrBusy + + + + 1 = NVR is busy + 0 = NVR is ready + + + Notes: + When set to 1, the NVR is busy. A new NVR operation should not occur until this bit is 0. If the NVR clock is greater than 64/63 of the MDIO clock, this bit never needs to be polled when operating over the MDIO. */ + unsigned int nvrBusy : 1; /* 1E.0100.8 RO */ + /* 1 = NVR is busy + 0 = NVR is ready + */ + /*! \brief 1E.0100.7:0 R/W NVR Opcode [7:0] + AQ_GlobalNvrInterface_APPIA.u0.bits_0.nvrOpcode + + Default = 0x03 + + NVR instruction opcode + + */ + unsigned int nvrOpcode : 8; /* 1E.0100.7:0 R/W Default = 0x03 */ + /* NVR instruction opcode + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0101.F:0 RO NVR Mailbox CRC [F:0] + AQ_GlobalNvrInterface_APPIA.u1.bits_1.nvrMailboxCrc + + + + The running CRC-16 of everything passing through the NVR interface + + + Notes: + The CRC-16 over all data written or read through the NVR interface. The CRC-16 is calculated by dividing the data by: + x^16 + x^12 + x^5 + 1 */ + unsigned int nvrMailboxCrc : 16; /* 1E.0101.F:0 RO */ + /* The running CRC-16 of everything passing through the NVR interface + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global NVR Interface */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.0102.7:0 R/W NVR Address MSW [17:10] + AQ_GlobalNvrInterface_APPIA.u2.bits_2.nvrAddressMSW + + Default = 0x00 + + NVR address MSW bits [17:10] + + + Notes: + The address of where to read and write from in the NVR. This is self-incrementing and will automatically increment after each read or write operation. The increment amount is based on the data length (i.e. increments by 4 if the data length is 4 bytes) */ + unsigned int nvrAddressMSW : 8; /* 1E.0102.7:0 R/W Default = 0x00 */ + /* NVR address MSW bits [17:10] + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0103.F:0 R/W NVR Address LSW [F:0] + AQ_GlobalNvrInterface_APPIA.u3.bits_3.nvrAddressLSW + + Default = 0x0000 + + NVR address LSW bits [F:0] + + + Notes: + The address of where to read and write from in the NVR. This is self-incrementing and will automatically increment after each read or write operation. */ + unsigned int nvrAddressLSW : 16; /* 1E.0103.F:0 R/W Default = 0x0000 */ + /* NVR address LSW bits [F:0] + */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0104.F:0 R/W NVR Data MSW [1F:10] + AQ_GlobalNvrInterface_APPIA.u4.bits_4.nvrDataMSW + + Default = 0x0000 + + NVR data MSW bits [1F:10] + + + Notes: + Data is stored and read-out from these registers in little-endian format for operations such as FLASH device ID, and for programming the processor. + + For instance the 64K Atmel device code reads out as two bytes 0x651F into the LSW register, whereas the datasheet indicates that 1F is the first byte read, followed by 65 as the second byte. + + To burst read and write these 4 bytes in the correct order (where DD is written to address x), they should be stored as: + + AA BB in the MSW + CC DD in the LSW. */ + unsigned int nvrDataMSW : 16; /* 1E.0104.F:0 R/W Default = 0x0000 */ + /* NVR data MSW bits [1F:10] + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0105.F:0 R/W NVR Data LSW [F:0] + AQ_GlobalNvrInterface_APPIA.u5.bits_5.nvrDataLSW + + Default = 0x0000 + + NVR data LSW bits [F:0] + + + Notes: + Data is stored and read-out from these registers in little-endian format for operations such as FLASH device ID, and for programming the processor. + + For instance the 64K Atmel device code reads out as two bytes 0x651F into the LSW register, whereas the datasheet indicates that 1F is the first byte read, followed by 65 as the second byte. + To burst read and write these 4 bytes in the correct order (where DD is written to address x), they should be stored as: + + AA BB in the MSW + CC DD in the LSW. */ + unsigned int nvrDataLSW : 16; /* 1E.0105.F:0 R/W Default = 0x0000 */ + /* NVR data LSW bits [F:0] + */ + } bits_5; + uint16_t word_5; + } u5; +} AQ_GlobalNvrInterface_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Mailbox Interface: 1E.0200 */ +/* Global Mailbox Interface: 1E.0200 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0200.F R/WSC uP Mailbox Execute Operation + AQ_GlobalMailboxInterface_APPIA.u0.bits_0.upMailboxExecuteOperation + + Default = 0x0 + + 1 = Start of mailbox Operation + + + Notes: + Indicates mailbox is loaded and ready */ + unsigned int upMailboxExecuteOperation : 1; /* 1E.0200.F R/WSC Default = 0x0 */ + /* 1 = Start of mailbox Operation + */ + /*! \brief 1E.0200.E R/W uP Mailbox Write Mode + AQ_GlobalMailboxInterface_APPIA.u0.bits_0.upMailboxWriteMode + + Default = 0x0 + + 1 = Write + 0 = Read + + + Notes: + Mailbox direction */ + unsigned int upMailboxWriteMode : 1; /* 1E.0200.E R/W Default = 0x0 */ + /* 1 = Write + 0 = Read + */ + unsigned int reserved0 : 1; + /*! \brief 1E.0200.C R/WSC Reset uP Mailbox CRC + AQ_GlobalMailboxInterface_APPIA.u0.bits_0.resetUpMailboxCrc + + Default = 0x0 + + 1 = Reset uP mailbox CRC calculation register + + */ + unsigned int resetUpMailboxCrc : 1; /* 1E.0200.C R/WSC Default = 0x0 */ + /* 1 = Reset uP mailbox CRC calculation register + */ + unsigned int reserved1 : 3; + /*! \brief 1E.0200.8 RO uP Mailbox Busy + AQ_GlobalMailboxInterface_APPIA.u0.bits_0.upMailboxBusy + + + + 1 = uP mailbox busy + 0 = uP mailbox ready + + + Notes: + In general the uP will respond within a few processor cycles to any PIF slave request, much faster than the MDIO. If the busy is asserted over multiple MDIO polling cycles, then a H/W error may have occured and a Global S/W reset or uP reset is required. */ + unsigned int upMailboxBusy : 1; /* 1E.0200.8 RO */ + /* 1 = uP mailbox busy + 0 = uP mailbox ready + */ + unsigned int reserved2 : 8; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0201.F:0 RO uP Mailbox CRC [F:0] + AQ_GlobalMailboxInterface_APPIA.u1.bits_1.upMailboxCrc + + + + The running CRC-16 of everything passing through the mailbox interface + + */ + unsigned int upMailboxCrc : 16; /* 1E.0201.F:0 RO */ + /* The running CRC-16 of everything passing through the mailbox interface + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0202.F:0 R/W uP Mailbox Address MSW [1F:10] + AQ_GlobalMailboxInterface_APPIA.u2.bits_2.upMailboxAddressMSW + + Default = 0x0000 + + uP Mailbox MSW address + + + Notes: + The address of where to read and write from in the Microcontroller Mailbox. This is self-incrementing and automatically increments after each read and write operation.PHY */ + unsigned int upMailboxAddressMSW : 16; /* 1E.0202.F:0 R/W Default = 0x0000 */ + /* uP Mailbox MSW address + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0203.F:2 R/W uP Mailbox Address LSW [F:2] + AQ_GlobalMailboxInterface_APPIA.u3.bits_3.upMailboxAddressLSW + + Default = 0x0000 + + uP LSW Mailbox address [F:2] + + + Notes: + The address of where to read and write from in the Microcontroller Mailbox. This is self-incrementing and automatically increments after each read and write operation.PHY */ + unsigned int upMailboxAddressLSW : 14; /* 1E.0203.F:2 R/W Default = 0x0000 */ + /* uP LSW Mailbox address [F:2] + */ + /*! \brief 1E.0203.1:0 RO uP Mailbox Address LSW Don't Care [1:0] + AQ_GlobalMailboxInterface_APPIA.u3.bits_3.upMailboxAddressLSW_Don_tCare + + + + Least significant uP LSW Mailbox address bits [1:0] + + + Notes: + These bits are always set to 0 since each memory access is on a 4-byte boundary. */ + unsigned int upMailboxAddressLSW_Don_tCare : 2; /* 1E.0203.1:0 RO */ + /* Least significant uP LSW Mailbox address bits [1:0] + */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0204.F:0 R/W uP Mailbox Data MSW [1F:10] + AQ_GlobalMailboxInterface_APPIA.u4.bits_4.upMailboxDataMSW + + Default = 0x0000 + + uP Mailbox data MSW + + */ + unsigned int upMailboxDataMSW : 16; /* 1E.0204.F:0 R/W Default = 0x0000 */ + /* uP Mailbox data MSW + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0205.F:0 R/W uP Mailbox Data LSW [F:0] + AQ_GlobalMailboxInterface_APPIA.u5.bits_5.upMailboxDataLSW + + Default = 0x0000 + + uP Mailbox data LSW + + */ + unsigned int upMailboxDataLSW : 16; /* 1E.0205.F:0 R/W Default = 0x0000 */ + /* uP Mailbox data LSW + */ + } bits_5; + uint16_t word_5; + } u5; +} AQ_GlobalMailboxInterface_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Microprocessor Scratch Pad: 1E.0300 */ +/* Global Microprocessor Scratch Pad: 1E.0300 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Microprocessor Scratch Pad */ + union + { + struct + { + /*! \brief 1E.0300.F:0 R/W Scratch Pad 1[F:0] + AQ_GlobalMicroprocessorScratchPad_APPIA.u0.bits_0.scratchPad_1 + + Default = 0x0000 + + General Purpose Scratch Pad1 + */ + unsigned int scratchPad_1 : 16; /* 1E.0300.F:0 R/W Default = 0x0000 */ + /* General Purpose Scratch Pad1 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Microprocessor Scratch Pad */ + union + { + struct + { + /*! \brief 1E.0301.F:0 R/W Scratch Pad 2 [F:0] + AQ_GlobalMicroprocessorScratchPad_APPIA.u1.bits_1.scratchPad_2 + + Default = 0x0000 + + General Purpose Scratch P + */ + unsigned int scratchPad_2 : 16; /* 1E.0301.F:0 R/W Default = 0x0000 */ + /* General Purpose Scratch P */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalMicroprocessorScratchPad_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Control: 1E.C000 */ +/* Global Control: 1E.C000 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Control */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Control */ + union + { + struct + { + /*! \brief 1E.C001.F R/W uP Reset + AQ_GlobalControl_APPIA.u1.bits_1.upReset + + Default = 0x0 + + 1 = Reset + + + Notes: + Resets the uP and the PIF master and slave bus. Will be active for a minimum of 100 microseconds. */ + unsigned int upReset : 1; /* 1E.C001.F R/W Default = 0x0 */ + /* 1 = Reset + */ + unsigned int reserved0 : 8; + /*! \brief 1E.C001.6 R/W uP Run Stall Override + AQ_GlobalControl_APPIA.u1.bits_1.upRunStallOverride + + Default = 0x0 + + 0 = uP Run Stall from "MDIO Boot Load" pin. + 1 = uP Run Stall from See MCP Run Stall bit + + + Notes: + This bit selects the uP Run Stall from either the "MDIO Boot Load" pin or the See MCP Run Stall bit. */ + unsigned int upRunStallOverride : 1; /* 1E.C001.6 R/W Default = 0x0 */ + /* 0 = uP Run Stall from "MDIO Boot Load" pin. + 1 = uP Run Stall from See MCP Run Stall bit + */ + unsigned int reserved1 : 5; + /*! \brief 1E.C001.0 R/W uP Run Stall + AQ_GlobalControl_APPIA.u1.bits_1.upRunStall + + Default = 0x0 + + 1 = uP Run Stall + 0 = uP normal mode + + + Notes: + Deactivates the uP. The PIF slave bus for inbound requests will still be active. This bit is muliplexed with the "MDIO Boot Load" pin with the See uP Run Stall Override bit as the select. When the "MDIO Boot Load" pin is asserted, the uP will be in Run Stall mode after reset. */ + unsigned int upRunStall : 1; /* 1E.C001.0 R/W Default = 0x0 */ + /* 1 = uP Run Stall + 0 = uP normal mode + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalControl_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Reset Control: 1E.C006 */ +/* Global Reset Control: 1E.C006 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Reset Control */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.C006.E R/WPD Global MMD Reset Disable + AQ_GlobalResetControl_APPIA.u0.bits_0.globalMMD_ResetDisable + + Provisionable Default = 0x0 + + 1 = Disable the S/W reset to the Global MMD registers + 0 = Enable the S/W reset to the Global MMD registers + + + Notes: + Setting this bit prevents a Global S/W reset or Global S/W reset from resetting the Global MMD registers */ + unsigned int globalMMD_ResetDisable : 1; /* 1E.C006.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Disable the S/W reset to the Global MMD registers + 0 = Enable the S/W reset to the Global MMD registers + */ + unsigned int reserved1 : 14; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalResetControl_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Diagnostic Provisioning: 1E.C400 */ +/* Global Diagnostic Provisioning: 1E.C400 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Diagnostic Provisioning */ + union + { + struct + { + /*! \brief 1E.C400.F R/WPD Enable Diagnostics + AQ_GlobalDiagnosticProvisioning_APPIA.u0.bits_0.enableDiagnostics + + Provisionable Default = 0x1 + + 1 = Chip performs diagnostics on power-up + */ + unsigned int enableDiagnostics : 1; /* 1E.C400.F R/WPD Provisionable Default = 0x1 */ + /* 1 = Chip performs diagnostics on power-up */ + unsigned int reserved0 : 15; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalDiagnosticProvisioning_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Thermal Provisioning: 1E.C420 */ +/* Global Thermal Provisioning: 1E.C420 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C420.F:0 R/WPD Reserved 0 [F:0] + AQ_GlobalThermalProvisioning_APPIA.u0.bits_0.reserved_0 + + Provisionable Default = 0x0000 + + Internal reserved - do not modify + + */ + unsigned int reserved_0 : 16; /* 1E.C420.F:0 R/WPD Provisionable Default = 0x0000 */ + /* Internal reserved - do not modify + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C421.F:0 R/WPD High Temp Failure Threshold [F:0] + AQ_GlobalThermalProvisioning_APPIA.u1.bits_1.highTempFailureThreshold + + Provisionable Default = 0x4600 + + [F:0] of high temperature failure threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 70 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A000 - 1.A001: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. - High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int highTempFailureThreshold : 16; /* 1E.C421.F:0 R/WPD Provisionable Default = 0x4600 */ + /* [F:0] of high temperature failure threshold */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C422.F:0 R/WPD Low Temp Failure Threshold [F:0] + AQ_GlobalThermalProvisioning_APPIA.u2.bits_2.lowTempFailureThreshold + + Provisionable Default = 0x0000 + + [F:0] of low temperature failure threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 0 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A002 - 1.A003: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. - High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int lowTempFailureThreshold : 16; /* 1E.C422.F:0 R/WPD Provisionable Default = 0x0000 */ + /* [F:0] of low temperature failure threshold */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C423.F:0 R/WPD High Temp Warning Threshold [F:0] + AQ_GlobalThermalProvisioning_APPIA.u3.bits_3.highTempWarningThreshold + + Provisionable Default = 0x3C00 + + [F:0] of high temperature warning threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD008. Default is 60 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A004 - 1.A005: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. - High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int highTempWarningThreshold : 16; /* 1E.C423.F:0 R/WPD Provisionable Default = 0x3C00 */ + /* [F:0] of high temperature warning threshold */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C424.F:0 R/WPD Low Temp Warning Threshold [F:0] + AQ_GlobalThermalProvisioning_APPIA.u4.bits_4.lowTempWarningThreshold + + Provisionable Default = 0x0A00 + + [F:0] of low temperature warning threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 10 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A006 - 1.A007: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. - High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int lowTempWarningThreshold : 16; /* 1E.C424.F:0 R/WPD Provisionable Default = 0x0A00 */ + /* [F:0] of low temperature warning threshold */ + } bits_4; + uint16_t word_4; + } u4; +} AQ_GlobalThermalProvisioning_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global LED Provisioning: 1E.C430 */ +/* Global LED Provisioning: 1E.C430 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 7; + /*! \brief 1E.C430.8 R/WPD LED #0 Manual Set + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_0ManualSet : 1; /* 1E.C430.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + /*! \brief 1E.C430.7 R/WPD LED #0 10 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_0_10Gb_sLinkEstablished : 1; /* 1E.C430.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C430.6 R/WPD LED #0 1 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_0_1Gb_sLinkEstablished : 1; /* 1E.C430.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C430.5 R/WPD LED #0 100 Mb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s + + */ + unsigned int led_0_100Mb_sLinkEstablished : 1; /* 1E.C430.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s + */ + /*! \brief 1E.C430.4 R/WPD LED #0 Connecting + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_0Connecting : 1; /* 1E.C430.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C430.3 R/WPD LED #0 Receive Activity + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_0ReceiveActivity : 1; /* 1E.C430.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C430.2 R/WPD LED #0 Transmit Activity + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_0TransmitActivity : 1; /* 1E.C430.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C430.1:0 R/WPD LED #0 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_0ActivityStretch : 2; /* 1E.C430.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 7; + /*! \brief 1E.C431.8 R/WPD LED #1 Manual Set + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_1ManualSet : 1; /* 1E.C431.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + /*! \brief 1E.C431.7 R/WPD LED #1 10 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_1_10Gb_sLinkEstablished : 1; /* 1E.C431.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C431.6 R/WPD LED #1 1 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_1_1Gb_sLinkEstablished : 1; /* 1E.C431.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C431.5 R/WPD LED #1 100 Mb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s + + */ + unsigned int led_1_100Mb_sLinkEstablished : 1; /* 1E.C431.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s + */ + /*! \brief 1E.C431.4 R/WPD LED #1 Connecting + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_1Connecting : 1; /* 1E.C431.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C431.3 R/WPD LED #1 Receive Activity + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_1ReceiveActivity : 1; /* 1E.C431.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C431.2 R/WPD LED #1 Transmit Activity + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_1TransmitActivity : 1; /* 1E.C431.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C431.1:0 R/WPD LED #1 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_1ActivityStretch : 2; /* 1E.C431.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 7; + /*! \brief 1E.C432.8 R/WPD LED #2 Manual Set + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_2ManualSet : 1; /* 1E.C432.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + /*! \brief 1E.C432.7 R/WPD LED #2 10 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_2_10Gb_sLinkEstablished : 1; /* 1E.C432.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C432.6 R/WPD LED #2 1 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_2_1Gb_sLinkEstablished : 1; /* 1E.C432.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C432.5 R/WPD LED #2 100 Mb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s + + */ + unsigned int led_2_100Mb_sLinkEstablished : 1; /* 1E.C432.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s + */ + /*! \brief 1E.C432.4 R/WPD LED #2 Connecting + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_2Connecting : 1; /* 1E.C432.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C432.3 R/WPD LED #2 Receive Activity + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_2ReceiveActivity : 1; /* 1E.C432.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C432.2 R/WPD LED #2 Transmit Activity + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_2TransmitActivity : 1; /* 1E.C432.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C432.1:0 R/WPD LED #2 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_2ActivityStretch : 2; /* 1E.C432.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 7; + /*! \brief 1E.C433.8 R/WPD LED #3 Manual Set + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_3ManualSet : 1; /* 1E.C433.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + /*! \brief 1E.C433.7 R/WPD LED #3 10 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_3_10Gb_sLinkEstablished : 1; /* 1E.C433.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C433.6 R/WPD LED #3 1 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_3_1Gb_sLinkEstablished : 1; /* 1E.C433.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C433.5 R/WPD LED #3 100 Mb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s + + */ + unsigned int led_3_100Mb_sLinkEstablished : 1; /* 1E.C433.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s + */ + /*! \brief 1E.C433.4 R/WPD LED #3 Connecting + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_3Connecting : 1; /* 1E.C433.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C433.3 R/WPD LED #3 Receive Activity + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_3ReceiveActivity : 1; /* 1E.C433.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C433.2 R/WPD LED #3 Transmit Activity + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_3TransmitActivity : 1; /* 1E.C433.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C433.1:0 R/WPD LED #3 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_3ActivityStretch : 2; /* 1E.C433.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 7; + /*! \brief 1E.C434.8 R/WPD LED #4 Manual Set + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_4ManualSet : 1; /* 1E.C434.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + /*! \brief 1E.C434.7 R/WPD LED #4 10 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_4_10Gb_sLinkEstablished : 1; /* 1E.C434.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C434.6 R/WPD LED #4 1 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_4_1Gb_sLinkEstablished : 1; /* 1E.C434.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C434.5 R/WPD LED #4 100 Mb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s + + */ + unsigned int led_4_100Mb_sLinkEstablished : 1; /* 1E.C434.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s + */ + /*! \brief 1E.C434.4 R/WPD LED #4 Connecting + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_4Connecting : 1; /* 1E.C434.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C434.3 R/WPD LED #4 Receive Activity + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_4ReceiveActivity : 1; /* 1E.C434.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C434.2 R/WPD LED #4 Transmit Activity + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_4TransmitActivity : 1; /* 1E.C434.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C434.1:0 R/WPD LED #4 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_4ActivityStretch : 2; /* 1E.C434.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 7; + /*! \brief 1E.C435.8 R/WPD LED #5 Manual Set + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_5ManualSet : 1; /* 1E.C435.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + /*! \brief 1E.C435.7 R/WPD LED #5 10 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_5_10Gb_sLinkEstablished : 1; /* 1E.C435.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C435.6 R/WPD LED #5 1 Gb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_5_1Gb_sLinkEstablished : 1; /* 1E.C435.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C435.5 R/WPD LED #5 100 Mb/s Link Established + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s + + */ + unsigned int led_5_100Mb_sLinkEstablished : 1; /* 1E.C435.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s + */ + /*! \brief 1E.C435.4 R/WPD LED #5 Connecting + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_5Connecting : 1; /* 1E.C435.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C435.3 R/WPD LED #5 Receive Activity + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_5ReceiveActivity : 1; /* 1E.C435.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C435.2 R/WPD LED #5 Transmit Activity + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_5TransmitActivity : 1; /* 1E.C435.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C435.1:0 R/WPD LED #5 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_5ActivityStretch : 2; /* 1E.C435.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 15; + /*! \brief 1E.C437.0 R/WPD LED Operation Mode + AQ_GlobalLedProvisioning_APPIA.u7.bits_7.ledOperationMode + + Provisionable Default = 0x0 + + 1 = LED link activity in Mode #2 + 0 = LED link activity in classic mode + + + Notes: + When set to 1, the LED blinking rate is based on Mode #2 algorithm. When set to 0, the LED blinking rate is based on the classic algorithm. */ + unsigned int ledOperationMode : 1; /* 1E.C437.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED link activity in Mode #2 + 0 = LED link activity in classic mode + */ + } bits_7; + uint16_t word_7; + } u7; + /*! \brief Union for bit and word level access of word 8 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 13; + /*! \brief 1E.C438.2 R/WPD LED #0 Drive Three State Select + AQ_GlobalLedProvisioning_APPIA.u8.bits_8.led_0DriveThreeStateSelect + + Provisionable Default = 0x0 + + 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + + */ + unsigned int led_0DriveThreeStateSelect : 1; /* 1E.C438.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + */ + /*! \brief 1E.C438.1 R/WPD LED #0 Active High Select + AQ_GlobalLedProvisioning_APPIA.u8.bits_8.led_0ActiveHighSelect + + Provisionable Default = 0x0 + + 1 = LED active high + 0 = LED active low + + + Notes: + The See LED #0 Manual Active Select bit must be 1 for this bit to take affect. */ + unsigned int led_0ActiveHighSelect : 1; /* 1E.C438.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED active high + 0 = LED active low + */ + /*! \brief 1E.C438.0 R/WPD LED #0 Manual Active Select + AQ_GlobalLedProvisioning_APPIA.u8.bits_8.led_0ManualActiveSelect + + Provisionable Default = 0x0 + + 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + + */ + unsigned int led_0ManualActiveSelect : 1; /* 1E.C438.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + */ + } bits_8; + uint16_t word_8; + } u8; + /*! \brief Union for bit and word level access of word 9 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 13; + /*! \brief 1E.C439.2 R/WPD LED #1 Drive Three State Select + AQ_GlobalLedProvisioning_APPIA.u9.bits_9.led_1DriveThreeStateSelect + + Provisionable Default = 0x0 + + 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + + */ + unsigned int led_1DriveThreeStateSelect : 1; /* 1E.C439.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + */ + /*! \brief 1E.C439.1 R/WPD LED #1 Active High Select + AQ_GlobalLedProvisioning_APPIA.u9.bits_9.led_1ActiveHighSelect + + Provisionable Default = 0x0 + + 1 = LED active high + 0 = LED active low + + + Notes: + The See LED #1 Manual Active Select bit must be 1 for this bit to take affect. */ + unsigned int led_1ActiveHighSelect : 1; /* 1E.C439.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED active high + 0 = LED active low + */ + /*! \brief 1E.C439.0 R/WPD LED #1 Manual Active Select + AQ_GlobalLedProvisioning_APPIA.u9.bits_9.led_1ManualActiveSelect + + Provisionable Default = 0x0 + + 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + + */ + unsigned int led_1ManualActiveSelect : 1; /* 1E.C439.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + */ + } bits_9; + uint16_t word_9; + } u9; + /*! \brief Union for bit and word level access of word 10 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 13; + /*! \brief 1E.C43A.2 R/WPD LED #2 Drive Three State Select + AQ_GlobalLedProvisioning_APPIA.u10.bits_10.led_2DriveThreeStateSelect + + Provisionable Default = 0x0 + + 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + + */ + unsigned int led_2DriveThreeStateSelect : 1; /* 1E.C43A.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + */ + /*! \brief 1E.C43A.1 R/WPD LED #2 Active High Select + AQ_GlobalLedProvisioning_APPIA.u10.bits_10.led_2ActiveHighSelect + + Provisionable Default = 0x0 + + 1 = LED active high + 0 = LED active low + + + Notes: + The See LED #2 Manual Active Select bit must be 1 for this bit to take affect. */ + unsigned int led_2ActiveHighSelect : 1; /* 1E.C43A.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED active high + 0 = LED active low + */ + /*! \brief 1E.C43A.0 R/WPD LED #2 Manual Active Select + AQ_GlobalLedProvisioning_APPIA.u10.bits_10.led_2ManualActiveSelect + + Provisionable Default = 0x0 + + 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + + */ + unsigned int led_2ManualActiveSelect : 1; /* 1E.C43A.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + */ + } bits_10; + uint16_t word_10; + } u10; + /*! \brief Union for bit and word level access of word 11 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 13; + /*! \brief 1E.C43B.2 R/WPD LED #3 Drive Three State Select + AQ_GlobalLedProvisioning_APPIA.u11.bits_11.led_3DriveThreeStateSelect + + Provisionable Default = 0x0 + + 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + + */ + unsigned int led_3DriveThreeStateSelect : 1; /* 1E.C43B.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + */ + /*! \brief 1E.C43B.1 R/WPD LED #3 Active High Select + AQ_GlobalLedProvisioning_APPIA.u11.bits_11.led_3ActiveHighSelect + + Provisionable Default = 0x0 + + 1 = LED active high + 0 = LED active low + + + Notes: + The See LED #3 Manual Active Select bit must be 1 for this bit to take affect. */ + unsigned int led_3ActiveHighSelect : 1; /* 1E.C43B.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED active high + 0 = LED active low + */ + /*! \brief 1E.C43B.0 R/WPD LED #3 Manual Active Select + AQ_GlobalLedProvisioning_APPIA.u11.bits_11.led_3ManualActiveSelect + + Provisionable Default = 0x0 + + 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + + */ + unsigned int led_3ManualActiveSelect : 1; /* 1E.C43B.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + */ + } bits_11; + uint16_t word_11; + } u11; + /*! \brief Union for bit and word level access of word 12 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 13; + /*! \brief 1E.C43C.2 R/WPD LED #4 Drive Three State Select + AQ_GlobalLedProvisioning_APPIA.u12.bits_12.led_4DriveThreeStateSelect + + Provisionable Default = 0x0 + + 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + + */ + unsigned int led_4DriveThreeStateSelect : 1; /* 1E.C43C.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + */ + /*! \brief 1E.C43C.1 R/WPD LED #4 Active High Select + AQ_GlobalLedProvisioning_APPIA.u12.bits_12.led_4ActiveHighSelect + + Provisionable Default = 0x0 + + 1 = LED active high + 0 = LED active low + + + Notes: + The See LED #4 Manual Active Select bit must be 1 for this bit to take affect. */ + unsigned int led_4ActiveHighSelect : 1; /* 1E.C43C.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED active high + 0 = LED active low + */ + /*! \brief 1E.C43C.0 R/WPD LED #4 Manual Active Select + AQ_GlobalLedProvisioning_APPIA.u12.bits_12.led_4ManualActiveSelect + + Provisionable Default = 0x0 + + 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + + */ + unsigned int led_4ManualActiveSelect : 1; /* 1E.C43C.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + */ + } bits_12; + uint16_t word_12; + } u12; + /*! \brief Union for bit and word level access of word 13 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 13; + /*! \brief 1E.C43D.2 R/WPD LED #5 Drive Three State Select + AQ_GlobalLedProvisioning_APPIA.u13.bits_13.led_5DriveThreeStateSelect + + Provisionable Default = 0x0 + + 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + + */ + unsigned int led_5DriveThreeStateSelect : 1; /* 1E.C43D.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Drive LED tri-state when not active + 0 = Drive LED opposite of active level when not active + */ + /*! \brief 1E.C43D.1 R/WPD LED #5 Active High Select + AQ_GlobalLedProvisioning_APPIA.u13.bits_13.led_5ActiveHighSelect + + Provisionable Default = 0x0 + + 1 = LED active high + 0 = LED active low + + + Notes: + The See LED #5 Manual Active Select bit must be 1 for this bit to take affect. */ + unsigned int led_5ActiveHighSelect : 1; /* 1E.C43D.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED active high + 0 = LED active low + */ + /*! \brief 1E.C43D.0 R/WPD LED #5 Manual Active Select + AQ_GlobalLedProvisioning_APPIA.u13.bits_13.led_5ManualActiveSelect + + Provisionable Default = 0x0 + + 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + + */ + unsigned int led_5ManualActiveSelect : 1; /* 1E.C43D.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Manual selection of LED active high or low + 0 = Determine the active high or low based on the external pull-up or pull-down + */ + } bits_13; + uint16_t word_13; + } u13; +} AQ_GlobalLedProvisioning_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global General Provisioning: 1E.C440 */ +/* Global General Provisioning: 1E.C440 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 7; + /*! \brief 1E.C440.8:4 R/WPD Gang Load MDIO Address [4:0] + AQ_GlobalGeneralProvisioning_APPIA.u0.bits_0.gangLoadMdioAddress + + Provisionable Default = 0x00 + + MDIO Address to be used during gang load operation + + + Notes: + Gang load operation is used to load data into multiple PHYs all connected to the same MDIO bus. The address for gang load operation is provided by these bits (8:4), and enabling is done by writing Bit 0. Disabling of gang load mode is done by writing the See MDIO Address Reset (1E.C441.2) bit. These will revert the PHY's MDIO address back to the address provided by the MDIO Address pins. During gang load operation, MDIO reads are disabled to prevent bus contention. */ + unsigned int gangLoadMdioAddress : 5; /* 1E.C440.8:4 R/WPD Provisionable Default = 0x00 */ + /* MDIO Address to be used during gang load operation + */ + unsigned int reserved1 : 3; + /*! \brief 1E.C440.0 RO Gang Load MDIO Write Only + AQ_GlobalGeneralProvisioning_APPIA.u0.bits_0.gangLoadMdioWriteOnly + + + + 1 = MDIO gang load enable + + + Notes: + This bit enables gang load operation with the address specified in Bits 8:4. */ + unsigned int gangLoadMdioWriteOnly : 1; /* 1E.C440.0 RO */ + /* 1 = MDIO gang load enable + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.C441.E R/WPD MDIO Broadcast Mode Enable + AQ_GlobalGeneralProvisioning_APPIA.u1.bits_1.mdioBroadcastModeEnable + + Provisionable Default = 0x0 + + 1 = Enable broadcast on Address 0 + 0 = Disable broadcast on Address 0 + + + Notes: + When set, this bit enables gang-load operation on address zero, simultaneous with normal MDIO operation. Obviously, this requires that no PHY use address 0 as its normal operating address. As well, reads on MDIO Address 0 are disabled to prevent bus contention. */ + unsigned int mdioBroadcastModeEnable : 1; /* 1E.C441.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable broadcast on Address 0 + 0 = Disable broadcast on Address 0 + */ + /*! \brief 1E.C441.D R/WPD MDIO Read MSW First Enable + AQ_GlobalGeneralProvisioning_APPIA.u1.bits_1.mdioReadMSW_FirstEnable + + Provisionable Default = 0x0 + + 1 = MSW of counter must be read first + 0 = LSW of counter must be read first + + + Notes: + This bit configures whether the MSW or LSW must be read first for counters greater than 16 bits. */ + unsigned int mdioReadMSW_FirstEnable : 1; /* 1E.C441.D R/WPD Provisionable Default = 0x0 */ + /* 1 = MSW of counter must be read first + 0 = LSW of counter must be read first + */ + unsigned int reserved1 : 8; + /*! \brief 1E.C441.4 R/WPD MDIO Drive Configuration + AQ_GlobalGeneralProvisioning_APPIA.u1.bits_1.mdioDriveConfiguration + + Provisionable Default = 0x0 + + 0 = MDIO driver is in normal mode + 1 = MDIO driver is in open drain mode + + + Notes: + When the MDIO driver is in open drain mode during a read cycle, "0" data will be actively driven out of the MDIO, "1" data will set the MDIO driver in high impedance state and an external pullup will set the MDIO line to "1". The Turn-Around "0" will also be actively driven out of the MDIO, therefore in open drain mode, the Turn-Around is still "Z0". */ + unsigned int mdioDriveConfiguration : 1; /* 1E.C441.4 R/WPD Provisionable Default = 0x0 */ + /* 0 = MDIO driver is in normal mode + 1 = MDIO driver is in open drain mode + */ + /*! \brief 1E.C441.3 R/WPD MDIO Preamble Detection Disable + AQ_GlobalGeneralProvisioning_APPIA.u1.bits_1.mdioPreambleDetectionDisable + + Provisionable Default = 0x0 + + 1 = Suppress preamble detection on MDIO + 0 = Enable preamble detection on MDIO + + */ + unsigned int mdioPreambleDetectionDisable : 1; /* 1E.C441.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = Suppress preamble detection on MDIO + 0 = Enable preamble detection on MDIO + */ + /*! \brief 1E.C441.2 R/WSC MDIO Address Reset + AQ_GlobalGeneralProvisioning_APPIA.u1.bits_1.mdioAddressReset + + Default = 0x0 + + 1 = Load MDIO Address with the address on the MDIO address pins + + + Notes: + Used to reset the address after gang load and enable MDIO reads again. */ + unsigned int mdioAddressReset : 1; /* 1E.C441.2 R/WSC Default = 0x0 */ + /* 1 = Load MDIO Address with the address on the MDIO address pins + */ + unsigned int reserved2 : 2; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 15; + /*! \brief 1E.C442.0 R/W Daisy Chain Reset + AQ_GlobalGeneralProvisioning_APPIA.u2.bits_2.daisyChainReset + + Default = 0x0 + + 1 = Reset the daisy chain + + + Notes: + Toggling this bit from 0 to 1 will reload the IRAM and DRAM and reset the uP. The uP will be in uP run stall during the reload process. After the reload process, uP run stall will be de-asserted adn the uP reset will be asserted. Note that before setting this bit, the See Soft Reset bit needs to be de-asserted. */ + unsigned int daisyChainReset : 1; /* 1E.C442.0 R/W Default = 0x0 */ + /* 1 = Reset the daisy chain + */ + } bits_2; + uint16_t word_2; + } u2; +} AQ_GlobalGeneralProvisioning_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global NVR Provisioning: 1E.C450 */ +/* Global NVR Provisioning: 1E.C450 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global NVR Provisioning */ + union + { + struct + { + unsigned int reserved0 : 5; + /*! \brief 1E.C450.A:8 R/WPD NVR Data Length [2:0] + AQ_GlobalNvrProvisioning_APPIA.u0.bits_0.nvrDataLength + + Provisionable Default = 0x4 + + NVR data length ranges from 0 bytes to 4 bytes + + + Notes: + This sets the length of the data burst used in read and write operations. + */ + unsigned int nvrDataLength : 3; /* 1E.C450.A:8 R/WPD Provisionable Default = 0x4 */ + /* NVR data length ranges from 0 bytes to 4 bytes + */ + unsigned int reserved1 : 1; + /*! \brief 1E.C450.6:4 R/WPD NVR Dummy Length [2:0] + AQ_GlobalNvrProvisioning_APPIA.u0.bits_0.nvrDummyLength + + Provisionable Default = 0x0 + + NVR dummy length ranges from 0 bytes to 4 bytes. + + + Notes: + This sets the length of the dummy field used in some maunfacturer's read status and write status operations. + */ + unsigned int nvrDummyLength : 3; /* 1E.C450.6:4 R/WPD Provisionable Default = 0x0 */ + /* NVR dummy length ranges from 0 bytes to 4 bytes. + */ + unsigned int reserved2 : 2; + /*! \brief 1E.C450.1:0 R/WPD NVR Address Length [1:0] + AQ_GlobalNvrProvisioning_APPIA.u0.bits_0.nvrAddressLength + + Provisionable Default = 0x2 + + NVR address length ranges from 0 bytes up to 3 bytes. + + + Notes: + This sets the length of the address field used in read and write operations. Use of this field is enabled via Bit 8 of See Global NVR Provisioning 2: Address 1E.C451 . + */ + unsigned int nvrAddressLength : 2; /* 1E.C450.1:0 R/WPD Provisionable Default = 0x2 */ + /* NVR address length ranges from 0 bytes up to 3 bytes. + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global NVR Provisioning */ + union + { + struct + { + unsigned int reserved0 : 7; + /*! \brief 1E.C451.8 R/WPD NVR Address Length Override + AQ_GlobalNvrProvisioning_APPIA.u1.bits_1.nvrAddressLengthOverride + + Provisionable Default = 0x0 + + 0 = NVR address length is based on the "NVR_SIZE" pin. + 1 = NVR address length is based on the See NVR Address Length [1:0] register. + + + Notes: + When the this bit = 0 and NVR_SIZE pin = 0, the NVR address length is 2 bytes. When this bit = 0 and the NVR_SIZE pin = 1, the NVR address length is 3 bytes. When this bit = 1 the NVR address length is from the See NVR Address Length [1:0] */ + unsigned int nvrAddressLengthOverride : 1; /* 1E.C451.8 R/WPD Provisionable Default = 0x0 */ + /* 0 = NVR address length is based on the "NVR_SIZE" pin. + 1 = NVR address length is based on the See NVR Address Length [1:0] register. + */ + /*! \brief 1E.C451.7:0 R/WPD NVR Clock Divide [7:0] + AQ_GlobalNvrProvisioning_APPIA.u1.bits_1.nvrClockDivide + + Provisionable Default = 0xA0 + + NVR clock divide. Clock frequency is divided by the NVR clock divide + 1 + + */ + unsigned int nvrClockDivide : 8; /* 1E.C451.7:0 R/WPD Provisionable Default = 0xA0 */ + /* NVR clock divide. Clock frequency is divided by the NVR clock divide + 1 + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global NVR Provisioning */ + union + { + struct + { + unsigned int reserved0 : 14; + /*! \brief 1E.C452.1 R/W NVR Daisy Chain Clock Divide Override + AQ_GlobalNvrProvisioning_APPIA.u2.bits_2.nvrDaisyChainClockDivideOverride + + Default = 0x0 + + 1 = Override NVR clock divide when in daisy chain master mode + + + + Notes: + When in daisy chain master mode, the clock divide configuration is received from the flash. This bit will override the clock divide configuration from the flash with the See NVR Clock Divide [7:0] . */ + unsigned int nvrDaisyChainClockDivideOverride : 1; /* 1E.C452.1 R/W Default = 0x0 */ + /* 1 = Override NVR clock divide when in daisy chain master mode + + */ + /*! \brief 1E.C452.0 R/W NVR Daisy Chain Disable + AQ_GlobalNvrProvisioning_APPIA.u2.bits_2.nvrDaisyChainDisable + + Default = 0x0 + + 1 = Disable the Daisy Chain + + + Notes: + When in daisy chain master mode, the daisy chain and MDIO can both access the SPI. Setting this bit to 1 will disable the dasiy chain from accessing the SPI and force it into a reset state. */ + unsigned int nvrDaisyChainDisable : 1; /* 1E.C452.0 R/W Default = 0x0 */ + /* 1 = Disable the Daisy Chain + */ + } bits_2; + uint16_t word_2; + } u2; +} AQ_GlobalNvrProvisioning_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Reserved Provisioning: 1E.C470 */ +/* Global Reserved Provisioning: 1E.C470 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C470.F R/WPD Diagnostics Select + AQ_GlobalReservedProvisioning_APPIA.u0.bits_0.diagnosticsSelect + + Provisionable Default = 0x0 + + 1 = Provide Extended MDI Diagnostics Information. + 0 = Provide normal cable diagnostics + + + Notes: + These bits select what sort of cable diagnostics to perform. For regular cable diagnostics, Bit F is set to zero, and the diagnostics are triggered by setting Bit 4. For extended diagnostics, Bit F is set to 1, and the desired extended diagnostics are selected by Bits E:D. The routine is then triggered by setting Bit 4. Each of the extended diagnostic routines present data for all for MDI pairs (A, B, C, D) consecutively, and after the data for each channel is gathered Bits F:D are reset. To get the data for the next pair, Bits F:D must be set back to the desired value (which must be the same as the initial channel). This continues until the data for all channels has been gathered. The address in memory where the data is stored is given in 1E.C802 and 1E.C804. + + For the case of PSD, the structure is as follows: + Int32 info + Int16 data[Len] + Info = Len << 16 | TxEnable << 8 | Pair (0 = A, etc.) + + For TDR: + Int32 info + Int16 tdr_A[Len] + Int16 tdr_B[Len] + Int16 tdr_C[Len] + Int16 tdr_D[Len] + + Info = Len << 16 | Channel + + TDR data is from the current pair to all other pairs. + + At the end of retrieving extended MDI diag data, the part will be reset. Conversly the only way to exit this routine once it starts is to issue a PMA reset. */ + unsigned int diagnosticsSelect : 1; /* 1E.C470.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Provide Extended MDI Diagnostics Information. + 0 = Provide normal cable diagnostics + */ + /*! \brief 1E.C470.E:D R/WPD Extended MDI Diagnostics Select [1:0] + AQ_GlobalReservedProvisioning_APPIA.u0.bits_0.extendedMdiDiagnosticsSelect + + Provisionable Default = 0x0 + + 0x0 = TDR Data + 0x1 = RFI Channel PSD + 0x2 = Noise PSD while the local Tx is Off + 0x3 = Noise PSD while the local Tx is On + + + Notes: + These bits select what sort of cable diagnostics to perform. For regular cable diagnostics, Bit F is set to zero, and the diagnostics are triggered by setting Bit 4. For extended diagnostics, Bit F is set to 1, and the desired extended diagnostics are selected by Bits E:D. The routine is then triggered by setting Bit 4. Each of the extended diagnostic routines present data for all for MDI pairs (A, B, C, D) consecutively, and after the data for each channel is gathered Bits F:D are reset. To get the data for the next pair, Bits F:D must be set back to the desired value (which must be the same as the initial channel). This continues until the data for all channels has been gathered. The address in memory where the data is stored is given in 1E.C802 and 1E.C804. + + For the case of PSD, the structure is as follows: + Int32 info + Int16 data[Len] + Info = Len << 16 | TxEnable << 8 | Pair (0 = A, etc.) + + For TDR: + Int32 info + Int16 tdr_A[Len] + Int16 tdr_B[Len] + Int16 tdr_C[Len] + Int16 tdr_D[Len] + + Info = Len << 16 | Channel + + TDR data is from the current pair to all other pairs. + + At the end of retrieving extended MDI diag data, the part will be reset. Conversly the only way to exit this routine once it starts is to issue a PMA reset. */ + unsigned int extendedMdiDiagnosticsSelect : 2; /* 1E.C470.E:D R/WPD Provisionable Default = 0x0 */ + /* 0x0 = TDR Data + 0x1 = RFI Channel PSD + 0x2 = Noise PSD while the local Tx is Off + 0x3 = Noise PSD while the local Tx is On + */ + unsigned int reserved0 : 5; + unsigned int reserved1 : 2; + /*! \brief 1E.C470.5 R/WSC Initiate Component Diagnostics + AQ_GlobalReservedProvisioning_APPIA.u0.bits_0.initiateComponentDiagnostics + + Default = 0x0 + + 1 = Perform component diagnostics + + + Notes: + Perform component diagnostics regardless of link state. If link is up, setting this bit will cause the link to drop while diagnostics are performed. This bit is self-clearing upon completion of the component diagnostics. Further MDIO writes should be avoided until this bit has self-cleared, indicating completion of the diagnostic routine. */ + unsigned int initiateComponentDiagnostics : 1; /* 1E.C470.5 R/WSC Default = 0x0 */ + /* 1 = Perform component diagnostics + */ + /*! \brief 1E.C470.4 R/WSC Initiate Cable Diagnostics + AQ_GlobalReservedProvisioning_APPIA.u0.bits_0.initiateCableDiagnostics + + Default = 0x0 + + 1 = Perform cable diagnostics + + + Notes: + Perform cable diagnostics regardless of link state. If link is up, setting this bit will cause the link to drop while diagnostics are performed. This bit is self-clearing upon completion of the cable diagnostics. Further MDIO writes should be avoided until this bit has self-cleared, indicating completion of the diagnostic routine. */ + unsigned int initiateCableDiagnostics : 1; /* 1E.C470.4 R/WSC Default = 0x0 */ + /* 1 = Perform cable diagnostics + */ + unsigned int reserved2 : 4; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C471.F:7 R/WPD Reserved Provisioning 2 [8:0] + AQ_GlobalReservedProvisioning_APPIA.u1.bits_1.reservedProvisioning_2 + + Provisionable Default = 0x000 + + Reserved for future use + + */ + unsigned int reservedProvisioning_2 : 9; /* 1E.C471.F:7 R/WPD Provisionable Default = 0x000 */ + /* Reserved for future use + */ + /*! \brief 1E.C471.6 R/WuP Enable Daisy-Chain Hop-Count Override + AQ_GlobalReservedProvisioning_APPIA.u1.bits_1.enableDaisy_chainHop_countOverride + + Default = 0x0 + + 1 = Hop-count is set by Bits 5:0 + 0 = Hop-count is determined by the daisy-chain + + + Notes: + Daisy-Chain Hop-Count Override should be used during MDIO boot-load operation, as the daisy-chain hop-count does not function when the daisy-chain is disabled (1E.C452.0). Setting this bit tells the processor where in the diasy-chain it is, so that the provisioning operation will function correctly. */ + unsigned int enableDaisy_chainHop_countOverride : 1; /* 1E.C471.6 R/WuP Default = 0x0 */ + /* 1 = Hop-count is set by Bits 5:0 + 0 = Hop-count is determined by the daisy-chain + */ + /*! \brief 1E.C471.5:0 R/WuP Daisy-Chain Hop-Count Override Value [5:0] + AQ_GlobalReservedProvisioning_APPIA.u1.bits_1.daisy_chainHop_countOverrideValue + + Default = 0x00 + + The value to use for the PHY's daisy-chain hop-count. Valid values are from 0 -> 47 + + + Notes: + Daisy-Chain Hop-Count Override should be used during MDIO boot-load operation, as the daisy-chain hop-count does not function when the daisy-chain is disabled (1E.C452.0). Setting this bit tells the processor where in the diasy-chain it is, so that the provisioning operation will function correctly. */ + unsigned int daisy_chainHop_countOverrideValue : 6; /* 1E.C471.5:0 R/WuP Default = 0x00 */ + /* The value to use for the PHY's daisy-chain hop-count. Valid values are from 0 -> 47 + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C472.F R/WPD Enable LVDD Power Supply Tuning + AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.enableLvddPowerSupplyTuning + + Provisionable Default = 0x0 + + 1 = Enable external LVDD power supply tuning + 0 = Disable external LVDD power supply tuning is disabled + + + Notes: + + + + These bits control whether the PHY attempts to tune the external VDD and LVDD power supplies via the PMBus. These bits are only operational if the external supplies are present (see Bits 7:6) */ + unsigned int enableLvddPowerSupplyTuning : 1; /* 1E.C472.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable external LVDD power supply tuning + 0 = Disable external LVDD power supply tuning is disabled + */ + /*! \brief 1E.C472.E R/WPD Enable VDD Power Supply Tuning + AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.enableVddPowerSupplyTuning + + Provisionable Default = 0x0 + + 1 = Enable external VDD power supply tuning + 0 = Disable external VDD power supply tuning is disabled + + + Notes: + + + + These bits control whether the PHY attempts to tune the external VDD and LVDD power supplies via the PMBus. These bits are only operational if the external supplies are present (see Bits 7:6) */ + unsigned int enableVddPowerSupplyTuning : 1; /* 1E.C472.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable external VDD power supply tuning + 0 = Disable external VDD power supply tuning is disabled + */ + unsigned int reserved0 : 6; + /*! \brief 1E.C472.7 R/WPD Tunable External LVDD Power Supply Present + AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.tunableExternalLvddPowerSupplyPresent + + Provisionable Default = 0x0 + + 1 = Tunable external LVDD power supply present + 0 = No tunable external LVDD power supply present + + + Notes: + + + + These bits must be set if tuning of external power supplies is desired (see Bits 7:6) */ + unsigned int tunableExternalLvddPowerSupplyPresent : 1; /* 1E.C472.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = Tunable external LVDD power supply present + 0 = No tunable external LVDD power supply present + */ + /*! \brief 1E.C472.6 R/WPD Tunable External VDD Power Supply Present + AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.tunableExternalVddPowerSupplyPresent + + Provisionable Default = 0x0 + + 1 = Tunable external VDD power supply present + 0 = No tunable external VDD power supply present + + + Notes: + + + + These bits must be set if tuning of external power supplies is desired (see Bits 7:6) */ + unsigned int tunableExternalVddPowerSupplyPresent : 1; /* 1E.C472.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Tunable external VDD power supply present + 0 = No tunable external VDD power supply present + */ + unsigned int reserved1 : 4; + /*! \brief 1E.C472.1 R/WPDuP Enable XENPAK Register Space + AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.enableXenpakRegisterSpace + + Provisionable Default = 0x0 + + 1 = XENPAK register space enabled + 0 = XENPAK register space disabled + + */ + unsigned int enableXenpakRegisterSpace : 1; /* 1E.C472.1 R/WPDuP Provisionable Default = 0x0 */ + /* 1 = XENPAK register space enabled + 0 = XENPAK register space disabled + */ + /*! \brief 1E.C472.0 R/WPDuP Enable 5th Channel RFI Cancellation + AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.enable_5thChannelRfiCancellation + + Provisionable Default = 0x0 + + 1 = 5th channel and RFI cancellers operation enabled + 0 = 5th channel AFE is powered down, 5th channel digital is clock gated, RFI cancellers are disabled + + + Notes: + Note: The value of this bit at the time of Autonegotiation sets the local PHY behavior until the next time Autonegotiation occurs. */ + unsigned int enable_5thChannelRfiCancellation : 1; /* 1E.C472.0 R/WPDuP Provisionable Default = 0x0 */ + /* 1 = 5th channel and RFI cancellers operation enabled + 0 = 5th channel AFE is powered down, 5th channel digital is clock gated, RFI cancellers are disabled + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.C474.7:0 R/WPD Training SNR [7:0] + AQ_GlobalReservedProvisioning_APPIA.u4.bits_4.trainingSNR + + Provisionable Default = 0x00 + + SNR during 10G training on the worst channel. SNR is in steps of 0.1dB + + + Notes: + The SNR margin that is enjoyed by the worst channel, over and above the minimum SNR required to operate at a BER of 10-12. It is reported with 0.1 dB of resolution to an accuracy of 0.5 dB within the range of -12.7 dB to 12.7 dB. The number is in offset binary, with 0.0 dB represented by 0x8000. + */ + unsigned int trainingSNR : 8; /* 1E.C474.7:0 R/WPD Provisionable Default = 0x00 */ + /* SNR during 10G training on the worst channel. SNR is in steps of 0.1dB + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved0 : 2; + /*! \brief 1E.C475.D R/WPD Smart Power-Down Status + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.smartPower_downStatus + + Provisionable Default = 0x0 + + 1 = Smart Power-Down Active + 0 = Smart Power-Down Inactive + + */ + unsigned int smartPower_downStatus : 1; /* 1E.C475.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Smart Power-Down Active + 0 = Smart Power-Down Inactive + */ + /*! \brief 1E.C475.C R/WPD Reserved Provisioning 6 + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.reservedProvisioning_6 + + Provisionable Default = 0x0 + + Reserved for future use + + */ + unsigned int reservedProvisioning_6 : 1; /* 1E.C475.C R/WPD Provisionable Default = 0x0 */ + /* Reserved for future use + */ + /*! \brief 1E.C475.B R/WPD CFR LP Disable Timer + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrLpDisableTimer + + Provisionable Default = 0x0 + + 1 = Link partner requires cfr_disable timer + 0 = Link partner does not require cfr_disable timer + + */ + unsigned int cfrLpDisableTimer : 1; /* 1E.C475.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner requires cfr_disable timer + 0 = Link partner does not require cfr_disable timer + */ + /*! \brief 1E.C475.A R/WPD CFR LP Extended Maxwait + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrLpExtendedMaxwait + + Provisionable Default = 0x0 + + 1 = Link partner requires extended maxwait + 0 = Link partner does not require extended maxwait + + */ + unsigned int cfrLpExtendedMaxwait : 1; /* 1E.C475.A R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner requires extended maxwait + 0 = Link partner does not require extended maxwait + */ + /*! \brief 1E.C475.9 R/WPD CFR LP THP + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrLpTHP + + Provisionable Default = 0x0 + + 1 = Link partner requires local PHY to enable THP + 0 = Link partner does not require local PHY to enable THP + + */ + unsigned int cfrLpTHP : 1; /* 1E.C475.9 R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner requires local PHY to enable THP + 0 = Link partner does not require local PHY to enable THP + */ + /*! \brief 1E.C475.8 R/WPD CFR LP Support + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrLpSupport + + Provisionable Default = 0x0 + + 1 = Link partner supports Cisco Fast Retrain + 0 = Link partner does support Cisco Fast Retrain + + */ + unsigned int cfrLpSupport : 1; /* 1E.C475.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner supports Cisco Fast Retrain + 0 = Link partner does support Cisco Fast Retrain + */ + /*! \brief 1E.C475.7 R/WPD CFR Disable Timer + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrDisableTimer + + Provisionable Default = 0x0 + + 1 = Local PHY requires cfr_disable timer + 0 = Local PHY does not require cfr_disable timer + + */ + unsigned int cfrDisableTimer : 1; /* 1E.C475.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY requires cfr_disable timer + 0 = Local PHY does not require cfr_disable timer + */ + /*! \brief 1E.C475.6 R/WPD CFR Extended Maxwait + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrExtendedMaxwait + + Provisionable Default = 0x0 + + 1 = Local PHY requires extended maxwait + 0 = Local PHY does not require extended maxwait + + */ + unsigned int cfrExtendedMaxwait : 1; /* 1E.C475.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY requires extended maxwait + 0 = Local PHY does not require extended maxwait + */ + /*! \brief 1E.C475.5 R/WPD CFR THP + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrTHP + + Provisionable Default = 0x0 + + 1 = Local PHY requires local PHY to enable THP + 0 = Local PHY does not require local PHY to enable THP + + */ + unsigned int cfrTHP : 1; /* 1E.C475.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY requires local PHY to enable THP + 0 = Local PHY does not require local PHY to enable THP + */ + /*! \brief 1E.C475.4 R/WPD CFR Support + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrSupport + + Provisionable Default = 0x0 + + 1 = Local PHY supports Cisco Fast Retrain + 0 = Local PHY does support Cisco Fast Retrain + + */ + unsigned int cfrSupport : 1; /* 1E.C475.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY supports Cisco Fast Retrain + 0 = Local PHY does support Cisco Fast Retrain + */ + /*! \brief 1E.C475.3 R/WPD Deadlock Avoidance Enable + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.deadlockAvoidanceEnable + + Provisionable Default = 0x0 + + 1 = SPD with deadlock avoidance: PHY transmits autonegotiation pulses (FLPs) at a slower rate (~ 1 FLP/ 100ms) than specified by autonegotiation standard (~1 FLP / 8.25ms). Receiver is active and able to detect the pulses. + 0 = SPD without deadlock avoidance: PHY transmitter is shut down, no autonegotiation pulses are sent on the line but the receiver is active and able to detect the pulses + + */ + unsigned int deadlockAvoidanceEnable : 1; /* 1E.C475.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = SPD with deadlock avoidance: PHY transmits autonegotiation pulses (FLPs) at a slower rate (~ 1 FLP/ 100ms) than specified by autonegotiation standard (~1 FLP / 8.25ms). Receiver is active and able to detect the pulses. + 0 = SPD without deadlock avoidance: PHY transmitter is shut down, no autonegotiation pulses are sent on the line but the receiver is active and able to detect the pulses + */ + /*! \brief 1E.C475.2 R/WPD Smart Power-Down Enable + AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.smartPower_downEnable + + Provisionable Default = 0x0 + + 1 = Enable smart power down mode + 0 = Smart power-down mode disabled + + + Notes: + Smart power down (SPD) is the lowest power mode at which PHY is able to autonegotiate. SPD can be enabled with bit 1E.C475.2 */ + unsigned int smartPower_downEnable : 1; /* 1E.C475.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable smart power down mode + 0 = Smart power-down mode disabled + */ + unsigned int reserved1 : 2; + } bits_5; + uint16_t word_5; + } u5; +} AQ_GlobalReservedProvisioning_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Cable Diagnostic Status: 1E.C800 */ +/* Global Cable Diagnostic Status: 1E.C800 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Cable Diagnostic Status */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.C800.E:C RO Pair A Status [2:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u0.bits_0.pairAStatus + + + + (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair D + 010= Connected to Pair C + 001= Connected to Pair B + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK + + Notes: + This bitfield reports the result, for pair A, of running either cable diagnostics or component diagnostics. */ + unsigned int pairAStatus : 3; /* 1E.C800.E:C RO */ + /* (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair D + 010= Connected to Pair C + 001= Connected to Pair B + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK */ + unsigned int reserved1 : 1; + /*! \brief 1E.C800.A:8 RO Pair B Status [2:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u0.bits_0.pairBStatus + + + + (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair A + 010= Connected to Pair D + 001= Connected to Pair C + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK + + Notes: + This bitfield reports the result, for pair B, of running either cable diagnostics or component diagnostics. */ + unsigned int pairBStatus : 3; /* 1E.C800.A:8 RO */ + /* (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair A + 010= Connected to Pair D + 001= Connected to Pair C + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK */ + unsigned int reserved2 : 1; + /*! \brief 1E.C800.6:4 RO Pair C Status [2:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u0.bits_0.pairCStatus + + + + (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair B + 010= Connected to Pair A + 001= Connected to Pair D + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK + + Notes: + This bitfield reports the result, for pair C, of running either cable diagnostics or component diagnostics. */ + unsigned int pairCStatus : 3; /* 1E.C800.6:4 RO */ + /* (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair B + 010= Connected to Pair A + 001= Connected to Pair D + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK */ + unsigned int reserved3 : 1; + /*! \brief 1E.C800.2:0 RO Pair D Status [2:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u0.bits_0.pairDStatus + + + + (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair C + 010= Connected to Pair B + 001= Connected to Pair A + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK + + Notes: + This bitfield reports the result, for pair D, of running either cable diagnostics or component diagnostics. */ + unsigned int pairDStatus : 3; /* 1E.C800.2:0 RO */ + /* (after running cable diags) + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair C + 010= Connected to Pair B + 001= Connected to Pair A + 000= OK + + OR: + + (after running component diags) + 100 = TX pin open + 011= TX bias open + 010= Capacitor short + 001= Inductor open + 000= OK */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C801.F:8 RO Pair A Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u1.bits_1.pairAReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair A + + Notes: + The distance to this reflection is given in See Global Reserved Status 1: Address 1E.C870 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairAReflection_1 : 8; /* 1E.C801.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair A */ + /*! \brief 1E.C801.7:0 RO Pair A Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u1.bits_1.pairAReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair A + + Notes: + The distance to this reflection is given in See Global Reserved Status 1: Address 1E.C870 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairAReflection_2 : 8; /* 1E.C801.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair A */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C802.F:0 RO Impulse Response MSW [F:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u2.bits_2.impulseResponseMSW + + + + The MSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type in 1E.C470.E:D + + + Notes: + See 1E.C470 for more information */ + unsigned int impulseResponseMSW : 16; /* 1E.C802.F:0 RO */ + /* The MSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type in 1E.C470.E:D + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C803.F:8 RO Pair B Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u3.bits_3.pairBReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair B + + Notes: + The distance to this reflection is given in See Global Reserved Status 2: Address 1E.C871 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairBReflection_1 : 8; /* 1E.C803.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair B */ + /*! \brief 1E.C803.7:0 RO Pair B Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u3.bits_3.pairBReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair B + + Notes: + The distance to this reflection is given in See Global Reserved Status 2: Address 1E.C871 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairBReflection_2 : 8; /* 1E.C803.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair B */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C804.F:0 RO Impulse Response LSW [F:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u4.bits_4.impulseResponseLSW + + + + The LSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type specified in 1E.C470.E:D + + + Notes: + See 1E.C470 for more information */ + unsigned int impulseResponseLSW : 16; /* 1E.C804.F:0 RO */ + /* The LSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type specified in 1E.C470.E:D + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C805.F:8 RO Pair C Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u5.bits_5.pairCReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair C + + Notes: + The distance to this reflection is given in See Global Reserved Status 3: Address 1E.C872 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairCReflection_1 : 8; /* 1E.C805.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair C */ + /*! \brief 1E.C805.7:0 RO Pair C Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u5.bits_5.pairCReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair C + + Notes: + The distance to this reflection is given in See Global Reserved Status 3: Address 1E.C872 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairCReflection_2 : 8; /* 1E.C805.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair C */ + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C806.F:0 RO Reserved 1 [F:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u6.bits_6.reserved_1 + + + + Reserved for future use + + */ + unsigned int reserved_1 : 16; /* 1E.C806.F:0 RO */ + /* Reserved for future use + */ + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C807.F:8 RO Pair D Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u7.bits_7.pairDReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair D + + Notes: + The distance to this reflection is given in See Global Reserved Status 4: Address 1E.C873 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairDReflection_1 : 8; /* 1E.C807.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair D */ + /*! \brief 1E.C807.7:0 RO Pair D Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u7.bits_7.pairDReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair D + + Notes: + The distance to this reflection is given in See Global Reserved Status 4: Address 1E.C873 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairDReflection_2 : 8; /* 1E.C807.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair D */ + } bits_7; + uint16_t word_7; + } u7; + /*! \brief Union for bit and word level access of word 8 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C808.F:0 RO Reserved 2[F:0] + AQ_GlobalCableDiagnosticStatus_APPIA.u8.bits_8.reserved_2 + + + + Reserved for future use + + */ + unsigned int reserved_2 : 16; /* 1E.C808.F:0 RO */ + /* Reserved for future use + */ + } bits_8; + uint16_t word_8; + } u8; +} AQ_GlobalCableDiagnosticStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Thermal Status: 1E.C820 */ +/* Global Thermal Status: 1E.C820 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Thermal Status */ + union + { + struct + { + /*! \brief 1E.C820.F:0 RO Temperature [F:0] + AQ_GlobalThermalStatus_APPIA.u0.bits_0.temperature + + + + [F:0] of temperature + + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 70 degreesC. This is a mirror of the XENPAK register 1.A060 - 1.A061. The mirror is performed in H/W. */ + unsigned int temperature : 16; /* 1E.C820.F:0 RO */ + /* [F:0] of temperature + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Thermal Status */ + union + { + struct + { + unsigned int reserved0 : 15; + /*! \brief 1E.C821.0 RO Temperature Ready + AQ_GlobalThermalStatus_APPIA.u1.bits_1.temperatureReady + + + + 1 = Temperature measurement is valid + + + Notes: + This is a mirror of the XENPAK register 1.A06E. */ + unsigned int temperatureReady : 1; /* 1E.C821.0 RO */ + /* 1 = Temperature measurement is valid + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalThermalStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global General Status: 1E.C830 */ +/* Global General Status: 1E.C830 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global General Status */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.C830.E RO High Temperature Failure State + AQ_GlobalGeneralStatus_APPIA.u0.bits_0.highTemperatureFailureState + + + + 1 = High temperature failure threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A070.7 register. + + */ + unsigned int highTemperatureFailureState : 1; /* 1E.C830.E RO */ + /* 1 = High temperature failure threshold has been exceeded */ + /*! \brief 1E.C830.D RO Low Temperature Failure State + AQ_GlobalGeneralStatus_APPIA.u0.bits_0.lowTemperatureFailureState + + + + 1 = Low temperature failure threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A070.6 register. + + */ + unsigned int lowTemperatureFailureState : 1; /* 1E.C830.D RO */ + /* 1 = Low temperature failure threshold has been exceeded */ + /*! \brief 1E.C830.C RO High Temperature Warning State + AQ_GlobalGeneralStatus_APPIA.u0.bits_0.highTemperatureWarningState + + + + 1 = High temperature warning threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A074.7 register. + + */ + unsigned int highTemperatureWarningState : 1; /* 1E.C830.C RO */ + /* 1 = High temperature warning threshold has been exceeded */ + /*! \brief 1E.C830.B RO Low Temperature Warning State + AQ_GlobalGeneralStatus_APPIA.u0.bits_0.lowTemperatureWarningState + + + + 1 = Low temperature warning threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A074.6 register. + + */ + unsigned int lowTemperatureWarningState : 1; /* 1E.C830.B RO */ + /* 1 = Low temperature warning threshold has been exceeded */ + unsigned int reserved1 : 11; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global General Status */ + union + { + struct + { + /*! \brief 1E.C831.F RO Processor Intensive MDIO Operation In- Progress + AQ_GlobalGeneralStatus_APPIA.u1.bits_1.processorIntensiveMdioOperationIn_Progress + + + + 1 = PHY microprocessor is busy with a processor-intensive MDIO operation + 0 = Processor-intensive MDIO operation completed + + + Notes: + This bit should may be used with certain processor-intensive MDIO commands (such as Loopbacks, Test Modes, Low power modes, Tx-Disable, Restart autoneg, Cable Diagnostics, etc.) that take longer than an MDIO cycle to complete. Upon receiving an MDIO command that involves the PHY's microprocessor, this bit is set, and when the command is completed, this bit is cleared. + + NOTE!!! This bit should be checked only after 1 ms of issuing a processor-intensive MDIO operation. + + The list of operations that set this bit are as follows: + + 1.0.0, PMA Loopback + 1.0.B, Low power mode + 1.9.4:0, Tx Disable + 1.84, 10G Test modes + 1.8000.5, XENPAK Control + 1.9000, XENPAK Rx Fault Enable + 1.9002, XENPAK Alarm Enable + 1.E400.F, External loopback + 3.0.B, Low power mode + 3.0.E, System PCS loopback + 3.C471.5, PRBS Test + 3.C471.6, PRBS Test + 3.E471.5, PRBS Test + 3.E471.6, PRBS Test + 4.0.B, Low power mode + 4.0.E, PHY-XS network loopback + 4.C440, Output clock control, Load SERDES parameters + 4.F802.E, System loopback + 4.C444.F:B, Loopback Control + 4.C444.4:2, Packet generation + 4.C445.C, SERDES calibration + 7.0.9, Restart autonegotiation + 1D.C280, 1G/100M Network loopback + 1D.C500, 1G System loopback + 1D.C501, 1G / 100M Test modes */ + unsigned int processorIntensiveMdioOperationIn_Progress : 1; /* 1E.C831.F RO */ + /* 1 = PHY microprocessor is busy with a processor-intensive MDIO operation + 0 = Processor-intensive MDIO operation completed + */ + unsigned int reserved0 : 15; + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalGeneralStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Pin Status: 1E.C840 */ +/* Global Pin Status: 1E.C840 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Pin Status */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.C840.E:D RO MDIO Boot Load [1:0] + AQ_GlobalPinStatus_APPIA.u0.bits_0.mdioBootLoad + + + + Value of MDIO Boot Load pins + + 0x3 = PHY #0 Slave Daisy Chain Boot + 0x2 = PHY #0 Master Daisy Chain Boot from Flash + 0x1 = MDIO Boot Load + 0x0 = Boot from Flash (PHY #0 only) + + + Notes: + NOTES: + + PHY #0 is the primary PHY, and PHY #1 is the secondary PHY + + PHY #1 is always in Slave Daisy Chain Boot from Flash when set to 0x2 or 0x3. */ + unsigned int mdioBootLoad : 2; /* 1E.C840.E:D RO */ + /* Value of MDIO Boot Load pins + + 0x3 = PHY #0 Slave Daisy Chain Boot + 0x2 = PHY #0 Master Daisy Chain Boot from Flash + 0x1 = MDIO Boot Load + 0x0 = Boot from Flash (PHY #0 only) + */ + unsigned int reserved1 : 3; + /*! \brief 1E.C840.9 RO Package Connectivity + AQ_GlobalPinStatus_APPIA.u0.bits_0.packageConnectivity + + + + Value of the package connection pin + + */ + unsigned int packageConnectivity : 1; /* 1E.C840.9 RO */ + /* Value of the package connection pin + */ + unsigned int reserved2 : 1; + /*! \brief 1E.C840.7 RO Tx Enable + AQ_GlobalPinStatus_APPIA.u0.bits_0.txEnable + + + + Current Value of Tx Enable pin + + + Notes: + 0 = Disable Transmitter */ + unsigned int txEnable : 1; /* 1E.C840.7 RO */ + /* Current Value of Tx Enable pin + */ + unsigned int reserved3 : 1; + /*! \brief 1E.C840.5:0 RO LED Pullup State [5:0] + AQ_GlobalPinStatus_APPIA.u0.bits_0.ledPullupState + + + + 1 = LED output pin is pulled high + 0 = LED output pin is pulled low + + */ + unsigned int ledPullupState : 6; /* 1E.C840.5:0 RO */ + /* 1 = LED output pin is pulled high + 0 = LED output pin is pulled low + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalPinStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Daisy Chain Status: 1E.C842 */ +/* Global Daisy Chain Status: 1E.C842 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Daisy Chain Status */ + union + { + struct + { + /*! \brief 1E.C842.F:0 RO Rx Daisy Chain Calculated CRC [F:0] + AQ_GlobalDaisyChainStatus_APPIA.u0.bits_0.rxDaisyChainCalculatedCrc + + + + Rx Daisy Chain Calculated CRC + + + Notes: + This is the calculated daisy chain CRC. */ + unsigned int rxDaisyChainCalculatedCrc : 16; /* 1E.C842.F:0 RO */ + /* Rx Daisy Chain Calculated CRC + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalDaisyChainStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Fault Message: 1E.C850 */ +/* Global Fault Message: 1E.C850 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Fault Message */ + union + { + struct + { + /*! \brief 1E.C850.F:0 RO Message [F:0] + AQ_GlobalFaultMessage_APPIA.u0.bits_0.message + + + + Error code describing fault + + Notes: + Code 0x8001: Firmware not compatible with chip architecture. This fault occurs when firmware compiled for a different Tensilica core is loaded. + Code 0x8002: VCO calibration failed. This occurs when the main PLLs on chip fail to lock: this is not possible to trigger. + Code 0x8003: XAUI calibration failed. This occurs when the XAUI PLLs fail to lock: this is not possible to trigger. + Code 0x8004: Failed to set operating voltages via PMBus. This only occurs when the processor has control over power supply voltage via an attached PMBus device and there is a protocol error on the I2C bus: this is not possible to trigger. + Code 0x8005: Unexpected device ID. This occurs if the device ID programmed into the internal E-Fuse registers in not valid: this is not possible to trigger. + Code 0x8006: Computed checksum does not match expected checksum. This occurs when the FLASH checksum check performed at boot time fails. This only occurs when the system boots from FLASH. + Code 0x8007: Detected a bit error in static memory. To trigger, corrupt one of the static regions. + Code 0xC001: Illegal Instruction exception. This occurs when the processor attempts to execute an illegal instruction. To trigger this, write an illegal instruction to program memory. It's possible that the bit error check will trigger before the illegal instruction is executed. + Code 0xC002 Instruction Fetch Error. Internal physical address or a data error during instruction fetch: this is not possible to trigger. + Code 0xC003 Load Store Error. Internal physical address or data error during load store operation: this is not possible to trigger.. + Code 0xC004 Privileged Instruction. Attempt to execute a privileged operation without sufficient privilege: this is not possible to trigger. + Code 0xC005 Unaligned Load or Store. Attempt to load or store data at an address which cannot be handled due to alignment: this is not possible to trigger. + Code 0xC006 Instruction fetch from prohibited space: this is not possible to trigger. + Code 0xC007 Data load from prohibited space: this is not possible to trigger. + Code 0xC008 Data store into prohibited space: this is not possible to trigger. */ + unsigned int message : 16; /* 1E.C850.F:0 RO */ + /* Error code describing fault */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalFaultMessage_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Primary Status: 1E.C851 */ +/* Global Primary Status: 1E.C851 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Primary Status */ + union + { + struct + { + unsigned int reserved0 : 15; + /*! \brief 1E.C851.0 RO Primary Status + AQ_GlobalPrimaryStatus_APPIA.u0.bits_0.primaryStatus + + + + 1 = PHY is the primary PHY + 0 = PHY is is secondary PHY + + */ + unsigned int primaryStatus : 1; /* 1E.C851.0 RO */ + /* 1 = PHY is the primary PHY + 0 = PHY is is secondary PHY + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalPrimaryStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Cable Diagnostic Impedance: 1E.C880 */ +/* Global Cable Diagnostic Impedance: 1E.C880 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C880.F RO Reserved 1 + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.reserved_1 + + + + Reserved for future use + + */ + unsigned int reserved_1 : 1; /* 1E.C880.F RO */ + /* Reserved for future use + */ + /*! \brief 1E.C880.E:C RO Pair A Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.pairAReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_1 : 3; /* 1E.C880.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C880.B RO Reserved 2 + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.reserved_2 + + + + Reserved for future use + + */ + unsigned int reserved_2 : 1; /* 1E.C880.B RO */ + /* Reserved for future use + */ + /*! \brief 1E.C880.A:8 RO Pair A Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.pairAReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_2 : 3; /* 1E.C880.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C880.7 RO Reserved 3 + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.reserved_3 + + + + Reserved for future use + + */ + unsigned int reserved_3 : 1; /* 1E.C880.7 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C880.6:4 RO Pair A Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.pairAReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_3 : 3; /* 1E.C880.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C880.3 RO Reserved 4 + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.reserved_4 + + + + Reserved for future use + + */ + unsigned int reserved_4 : 1; /* 1E.C880.3 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C880.2:0 RO Pair A Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.pairAReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_4 : 3; /* 1E.C880.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C881.F RO Reserved 5 + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.reserved_5 + + + + Reserved for future use + + */ + unsigned int reserved_5 : 1; /* 1E.C881.F RO */ + /* Reserved for future use + */ + /*! \brief 1E.C881.E:C RO Pair B Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.pairBReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_1 : 3; /* 1E.C881.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C881.B RO Reserved 6 + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.reserved_6 + + + + Reserved for future use + + */ + unsigned int reserved_6 : 1; /* 1E.C881.B RO */ + /* Reserved for future use + */ + /*! \brief 1E.C881.A:8 RO Pair B Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.pairBReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_2 : 3; /* 1E.C881.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C881.7 RO Reserved 7 + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.reserved_7 + + + + Reserved for future use + + */ + unsigned int reserved_7 : 1; /* 1E.C881.7 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C881.6:4 RO Pair B Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.pairBReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_3 : 3; /* 1E.C881.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C881.3 RO Reserved 8 + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.reserved_8 + + + + Reserved for future use + + */ + unsigned int reserved_8 : 1; /* 1E.C881.3 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C881.2:0 RO Pair B Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.pairBReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_4 : 3; /* 1E.C881.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C882.F RO Reserved 9 + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.reserved_9 + + + + Reserved for future use + + */ + unsigned int reserved_9 : 1; /* 1E.C882.F RO */ + /* Reserved for future use + */ + /*! \brief 1E.C882.E:C RO Pair C Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.pairCReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_1 : 3; /* 1E.C882.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C882.B RO Reserved 10 + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.reserved_10 + + + + Reserved for future use + + */ + unsigned int reserved_10 : 1; /* 1E.C882.B RO */ + /* Reserved for future use + */ + /*! \brief 1E.C882.A:8 RO Pair C Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.pairCReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_2 : 3; /* 1E.C882.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C882.7 RO Reserved 11 + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.reserved_11 + + + + Reserved for future use + + */ + unsigned int reserved_11 : 1; /* 1E.C882.7 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C882.6:4 RO Pair C Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.pairCReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_3 : 3; /* 1E.C882.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C882.3 RO Reserved 12 + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.reserved_12 + + + + Reserved for future use + + */ + unsigned int reserved_12 : 1; /* 1E.C882.3 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C882.2:0 RO Pair C Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.pairCReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_4 : 3; /* 1E.C882.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C883.F RO Reserved 13 + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.reserved_13 + + + + Reserved for future use + + */ + unsigned int reserved_13 : 1; /* 1E.C883.F RO */ + /* Reserved for future use + */ + /*! \brief 1E.C883.E:C RO Pair D Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.pairDReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_1 : 3; /* 1E.C883.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C883.B RO Reserved 14 + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.reserved_14 + + + + Reserved for future use + + */ + unsigned int reserved_14 : 1; /* 1E.C883.B RO */ + /* Reserved for future use + */ + /*! \brief 1E.C883.A:8 RO Pair D Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.pairDReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_2 : 3; /* 1E.C883.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C883.7 RO Reserved 15 + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.reserved_15 + + + + Reserved for future use + + */ + unsigned int reserved_15 : 1; /* 1E.C883.7 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C883.6:4 RO Pair D Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.pairDReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_3 : 3; /* 1E.C883.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C883.3 RO Reserved 16 + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.reserved_16 + + + + Reserved for future use + + */ + unsigned int reserved_16 : 1; /* 1E.C883.3 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C883.2:0 RO Pair D Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.pairDReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_4 : 3; /* 1E.C883.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + } bits_3; + uint16_t word_3; + } u3; +} AQ_GlobalCableDiagnosticImpedance_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Status: 1E.C884 */ +/* Global Status: 1E.C884 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Status */ + union + { + struct + { + /*! \brief 1E.C884.F:8 RO Reserved Status 0 [7:0] + AQ_GlobalStatus_APPIA.u0.bits_0.reservedStatus_0 + + + + Reserved for future use + + */ + unsigned int reservedStatus_0 : 8; /* 1E.C884.F:8 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C884.7:0 RO Cable Length [7:0] + AQ_GlobalStatus_APPIA.u0.bits_0.cableLength + + + + The estimated length of the cable in meters + + + Notes: + The length of the cable shown here is estimated from the cable diagnostic engine and should be accurate to +/-1m. */ + unsigned int cableLength : 8; /* 1E.C884.7:0 RO */ + /* The estimated length of the cable in meters + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Reserved Status: 1E.C885 */ +/* Global Reserved Status: 1E.C885 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Reserved Status */ + union + { + struct + { + /*! \brief 1E.C885.F:A RO Nearly Seconds MSW[5:0] + AQ_GlobalReservedStatus_APPIA.u0.bits_0.nearlySecondsMSW + + + + Bits 16 to 21 of the 22 bit "Nearly Seconds" uptime counter. + + + Notes: + The "Nearly Seconds" counter is incremented every 1024 milliseconds. */ + unsigned int nearlySecondsMSW : 6; /* 1E.C885.F:A RO */ + /* Bits 16 to 21 of the 22 bit "Nearly Seconds" uptime counter. + */ + /*! \brief 1E.C885.9:8 ROSPD XENPAK NVR Status [1:0] + AQ_GlobalReservedStatus_APPIA.u0.bits_0.xenpakNvrStatus + + Provisionable Default = 0x0 + + Status of XENPAK NVR: + 0: NVR not enabled + 1: Last NVR operation succeeded + 2: Last NVR operation failed + 3: Reserved + + + Notes: + XENPAK register space is mirrored in NVR (SPI ROM). This register indicates the status of the last NVR operation. */ + unsigned int xenpakNvrStatus : 2; /* 1E.C885.9:8 ROSPD Provisionable Default = 0x0 */ + /* Status of XENPAK NVR: + 0: NVR not enabled + 1: Last NVR operation succeeded + 2: Last NVR operation failed + 3: Reserved + */ + /*! \brief 1E.C885.7:0 ROSPD ROM Revision [7:0] + AQ_GlobalReservedStatus_APPIA.u0.bits_0.romRevision + + Provisionable Default = 0x00 + + ROM Revision Number + + + Notes: + Customers may receive multiple ROM images that differ only in their provisioning. This field is used to differentiate those images. This field is used in conjunction with the firmware major and minor revision numbers to uniquely identify ROM images. */ + unsigned int romRevision : 8; /* 1E.C885.7:0 ROSPD Provisionable Default = 0x00 */ + /* ROM Revision Number + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Reserved Status */ + union + { + struct + { + /*! \brief 1E.C886.F:0 RO Nearly Seconds LSW[F:0] + AQ_GlobalReservedStatus_APPIA.u1.bits_1.nearlySecondsLSW + + + + Bits 0 to 15 of the 22 bit "Nearly Seconds" uptime counter. + + + Notes: + The "Nearly Seconds" counter is incremented every 1024 milliseconds. */ + unsigned int nearlySecondsLSW : 16; /* 1E.C886.F:0 RO */ + /* Bits 0 to 15 of the 22 bit "Nearly Seconds" uptime counter. + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalReservedStatus_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Alarms: 1E.CC00 */ +/* Global Alarms: 1E.CC00 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Alarms */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.CC00.E LH High Temperature Failure + AQ_GlobalAlarms_APPIA.u0.bits_0.highTemperatureFailure + + + + 1 = High temperature failure threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int highTemperatureFailure : 1; /* 1E.CC00.E LH */ + /* 1 = High temperature failure threshold has been exceeded + */ + /*! \brief 1E.CC00.D LH Low Temperature Failure + AQ_GlobalAlarms_APPIA.u0.bits_0.lowTemperatureFailure + + + + 1 = Low temperature failure threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int lowTemperatureFailure : 1; /* 1E.CC00.D LH */ + /* 1 = Low temperature failure threshold has been exceeded + */ + /*! \brief 1E.CC00.C LH High Temperature Warning + AQ_GlobalAlarms_APPIA.u0.bits_0.highTemperatureWarning + + + + 1 = High temperature warning threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int highTemperatureWarning : 1; /* 1E.CC00.C LH */ + /* 1 = High temperature warning threshold has been exceeded + */ + /*! \brief 1E.CC00.B LH Low Temperature Warning + AQ_GlobalAlarms_APPIA.u0.bits_0.lowTemperatureWarning + + + + 1 = Low temperature warning threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int lowTemperatureWarning : 1; /* 1E.CC00.B LH */ + /* 1 = Low temperature warning threshold has been exceeded + */ + unsigned int reserved1 : 4; + /*! \brief 1E.CC00.6 LH Reset completed + AQ_GlobalAlarms_APPIA.u0.bits_0.resetCompleted + + + + 1 = Chip wide reset completed + + Notes: + This bit is set by the microprocessor when it has completed it's initialization sequence. This bit is mirrored in 1.CC02.0 */ + unsigned int resetCompleted : 1; /* 1E.CC00.6 LH */ + /* 1 = Chip wide reset completed */ + unsigned int reserved2 : 1; + /*! \brief 1E.CC00.4 LH Device Fault + AQ_GlobalAlarms_APPIA.u0.bits_0.deviceFault + + + + 1 = Fault + + Notes: + When set, a fault has been detected by the uP and the associated 16 bit error code is visible in See Global Configuration Fault Message: Address 1E.C850 */ + unsigned int deviceFault : 1; /* 1E.CC00.4 LH */ + /* 1 = Fault */ + /*! \brief 1E.CC00.3 LH Reserved Alarm A + AQ_GlobalAlarms_APPIA.u0.bits_0.reservedAlarmA + + + + Reserved for future use + + */ + unsigned int reservedAlarmA : 1; /* 1E.CC00.3 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC00.2 LH Reserved Alarm B + AQ_GlobalAlarms_APPIA.u0.bits_0.reservedAlarmB + + + + Reserved for future use + + */ + unsigned int reservedAlarmB : 1; /* 1E.CC00.2 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC00.1 LH Reserved Alarm C + AQ_GlobalAlarms_APPIA.u0.bits_0.reservedAlarmC + + + + Reserved for future use + + */ + unsigned int reservedAlarmC : 1; /* 1E.CC00.1 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC00.0 LH Reserved Alarm D + AQ_GlobalAlarms_APPIA.u0.bits_0.reservedAlarmD + + + + Reserved for future use + + */ + unsigned int reservedAlarmD : 1; /* 1E.CC00.0 LH */ + /* Reserved for future use + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Alarms */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.CC01.E LH Smart Power-Down Entered + AQ_GlobalAlarms_APPIA.u1.bits_1.smartPower_downEntered + + + + 1 = Smart Power-Down State Entered + + + Notes: + When this bit is set, it indicates that the Smart Power-Down state was entered */ + unsigned int smartPower_downEntered : 1; /* 1E.CC01.E LH */ + /* 1 = Smart Power-Down State Entered + */ + /*! \brief 1E.CC01.D RO XENPAK Alarm + AQ_GlobalAlarms_APPIA.u1.bits_1.xenpakAlarm + + + + 1 = XENPAK Alarm + + + Notes: + This alarm is performed by H/W. */ + unsigned int xenpakAlarm : 1; /* 1E.CC01.D RO */ + /* 1 = XENPAK Alarm + */ + /*! \brief 1E.CC01.C:8 LH Reserved Alarms [4:0] + AQ_GlobalAlarms_APPIA.u1.bits_1.reservedAlarms + + + + Reserved for future use + + */ + unsigned int reservedAlarms : 5; /* 1E.CC01.C:8 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC01.7 LH MDIO Command Handling Overflow + AQ_GlobalAlarms_APPIA.u1.bits_1.mdioCommandHandlingOverflow + + + + 1 = PHY was issued more MDIO requests than it could service in it's request buffer + + + Notes: + Assertion of this bit means that more MDIO commands were issued than FW could handle. */ + unsigned int mdioCommandHandlingOverflow : 1; /* 1E.CC01.7 LH */ + /* 1 = PHY was issued more MDIO requests than it could service in it's request buffer + */ + unsigned int reserved1 : 6; + /*! \brief 1E.CC01.0 LH Diagnostic Alarm + AQ_GlobalAlarms_APPIA.u1.bits_1.diagnosticAlarm + + + + 1 = Alarm triggered by a write to 1E.C470.7 + + + Notes: + A diagnostic alarm use to test system alarm circuitry */ + unsigned int diagnosticAlarm : 1; /* 1E.CC01.0 LH */ + /* 1 = Alarm triggered by a write to 1E.C470.7 + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Alarms */ + union + { + struct + { + /*! \brief 1E.CC02.F LH NVR Operation Complete + AQ_GlobalAlarms_APPIA.u2.bits_2.nvrOperationComplete + + + + 1 = NVR operation is complete + + + Notes: + NVR interface is ready interrupt for registers See Global NVR Interface 1: Address 1E.100 - See Global NVR Provisioning Data MSW - Address 1E.17 . */ + unsigned int nvrOperationComplete : 1; /* 1E.CC02.F LH */ + /* 1 = NVR operation is complete + */ + /*! \brief 1E.CC02.E LH Mailbox Operation: Complete + AQ_GlobalAlarms_APPIA.u2.bits_2.mailboxOperation_Complete + + + + 1 = Mailbox operation is complete + + + Notes: + Mailbox interface is ready interrupt for registers See Global Vendor Specific Control - Address 1E.C000 - See Global Vendor Specific Provisioning 5 - Address 1E.C404 */ + unsigned int mailboxOperation_Complete : 1; /* 1E.CC02.E LH */ + /* 1 = Mailbox operation is complete + */ + unsigned int reserved0 : 3; + /*! \brief 1E.CC02.A LH uP DRAM Parity Error + AQ_GlobalAlarms_APPIA.u2.bits_2.upDramParityError + + + + 1 = Parity error detected in the uP DRAM + + */ + unsigned int upDramParityError : 1; /* 1E.CC02.A LH */ + /* 1 = Parity error detected in the uP DRAM + */ + /*! \brief 1E.CC02.9:8 LH uP IRAM Parity Error [1:0] + AQ_GlobalAlarms_APPIA.u2.bits_2.upIramParityError + + + + 1 = Parity error detected in the uP IRAM + + + Notes: + Bit 0 indicates a parity error was detected in the uP IRAM but was corrected. + Bit 1 indicates a multiple parity errors were detected in the uP IRAM and could not be corrected. + The uP IRAM is protected with ECC. */ + unsigned int upIramParityError : 2; /* 1E.CC02.9:8 LH */ + /* 1 = Parity error detected in the uP IRAM + */ + unsigned int reserved1 : 2; + /*! \brief 1E.CC02.5 LRF Tx Enable State Change + AQ_GlobalAlarms_APPIA.u2.bits_2.txEnableStateChange + + + + 1 = TX_EN pin has changed state + + */ + unsigned int txEnableStateChange : 1; /* 1E.CC02.5 LRF */ + /* 1 = TX_EN pin has changed state + */ + unsigned int reserved2 : 2; + /*! \brief 1E.CC02.2 LH MDIO MMD Error + AQ_GlobalAlarms_APPIA.u2.bits_2.mdioMMD_Error + + + + 1 = Invalid MMD address detected + + */ + unsigned int mdioMMD_Error : 1; /* 1E.CC02.2 LH */ + /* 1 = Invalid MMD address detected + */ + /*! \brief 1E.CC02.1 LH MDIO Timeout Error + AQ_GlobalAlarms_APPIA.u2.bits_2.mdioTimeoutError + + + + 1 = MDIO timeout detected + + */ + unsigned int mdioTimeoutError : 1; /* 1E.CC02.1 LH */ + /* 1 = MDIO timeout detected + */ + /*! \brief 1E.CC02.0 LH Watchdog Timer Alarm + AQ_GlobalAlarms_APPIA.u2.bits_2.watchdogTimerAlarm + + + + 1 = Watchdog timer alarm + + */ + unsigned int watchdogTimerAlarm : 1; /* 1E.CC02.0 LH */ + /* 1 = Watchdog timer alarm + */ + } bits_2; + uint16_t word_2; + } u2; +} AQ_GlobalAlarms_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Interrupt Mask: 1E.D400 */ +/* Global Interrupt Mask: 1E.D400 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Interrupt Mask */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.D400.E R/WPD High Temperature Failure Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.highTemperatureFailureMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int highTemperatureFailureMask : 1; /* 1E.D400.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D400.D R/WPD Low Temperature Failure Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.lowTemperatureFailureMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int lowTemperatureFailureMask : 1; /* 1E.D400.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D400.C R/WPD High Temperature Warning Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.highTemperatureWarningMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int highTemperatureWarningMask : 1; /* 1E.D400.C R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D400.B R/WPD Low Temperature Warning Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.lowTemperatureWarningMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int lowTemperatureWarningMask : 1; /* 1E.D400.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved1 : 4; + /*! \brief 1E.D400.6 R/WPD Reset completed Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.resetCompletedMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int resetCompletedMask : 1; /* 1E.D400.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved2 : 1; + /*! \brief 1E.D400.4 R/WPD Device Fault Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.deviceFaultMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int deviceFaultMask : 1; /* 1E.D400.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D400.3 R/WPD Reserved Alarm A Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.reservedAlarmAMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmAMask : 1; /* 1E.D400.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D400.2 R/WPD Reserved Alarm B Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.reservedAlarmBMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmBMask : 1; /* 1E.D400.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D400.1 R/WPD Reserved Alarm C Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.reservedAlarmCMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmCMask : 1; /* 1E.D400.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D400.0 R/WPD Reserved Alarm D Mask + AQ_GlobalInterruptMask_APPIA.u0.bits_0.reservedAlarmDMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmDMask : 1; /* 1E.D400.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Interrupt Mask */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.D401.E R/WPD Smart Power-Down Entered Mask + AQ_GlobalInterruptMask_APPIA.u1.bits_1.smartPower_downEnteredMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int smartPower_downEnteredMask : 1; /* 1E.D401.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D401.D R/WPD XENPAK Alarm Mask + AQ_GlobalInterruptMask_APPIA.u1.bits_1.xenpakAlarmMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int xenpakAlarmMask : 1; /* 1E.D401.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D401.C:8 R/WPD Reserved Alarms Mask [4:0] + AQ_GlobalInterruptMask_APPIA.u1.bits_1.reservedAlarmsMask + + Provisionable Default = 0x00 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmsMask : 5; /* 1E.D401.C:8 R/WPD Provisionable Default = 0x00 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D401.7 R/WPD MDIO Command Handling Overflow Mask + AQ_GlobalInterruptMask_APPIA.u1.bits_1.mdioCommandHandlingOverflowMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int mdioCommandHandlingOverflowMask : 1; /* 1E.D401.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int reserved1 : 6; + /*! \brief 1E.D401.0 R/WPD Diagnostic Alarm Mask + AQ_GlobalInterruptMask_APPIA.u1.bits_1.diagnosticAlarmMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int diagnosticAlarmMask : 1; /* 1E.D401.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Interrupt Mask */ + union + { + struct + { + /*! \brief 1E.D402.F R/WPD NVR Operation Complete Mask + AQ_GlobalInterruptMask_APPIA.u2.bits_2.nvrOperationCompleteMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + Notes: + NVR interface is ready interrupt for registers See Global NVR Interface 1: Address 1E.100 - See Global NVR Provisioning Data MSW - Address 1E.17 */ + unsigned int nvrOperationCompleteMask : 1; /* 1E.D402.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D402.E R/WPD Mailbox Operation Complete Mask + AQ_GlobalInterruptMask_APPIA.u2.bits_2.mailboxOperationCompleteMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + Notes: + Mailbox interface is ready interrupt for registers See Global Vendor Specific Control - Address 1E.C000 - See Global Vendor Specific Provisioning 5 - Address 1E.C404 */ + unsigned int mailboxOperationCompleteMask : 1; /* 1E.D402.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved0 : 3; + /*! \brief 1E.D402.A R/WPD uP DRAM Parity Error Mask + AQ_GlobalInterruptMask_APPIA.u2.bits_2.upDramParityErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int upDramParityErrorMask : 1; /* 1E.D402.A R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D402.9:8 R/WPD uP IRAM Parity Error Mask [1:0] + AQ_GlobalInterruptMask_APPIA.u2.bits_2.upIramParityErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int upIramParityErrorMask : 2; /* 1E.D402.9:8 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int reserved1 : 2; + /*! \brief 1E.D402.5 R/WPD Tx Enable State Change Mask + AQ_GlobalInterruptMask_APPIA.u2.bits_2.txEnableStateChangeMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int txEnableStateChangeMask : 1; /* 1E.D402.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved2 : 2; + /*! \brief 1E.D402.2 R/WPD MDIO MMD Error Mask + AQ_GlobalInterruptMask_APPIA.u2.bits_2.mdioMMD_ErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int mdioMMD_ErrorMask : 1; /* 1E.D402.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D402.1 R/WPD MDIO Timeout Error Mask + AQ_GlobalInterruptMask_APPIA.u2.bits_2.mdioTimeoutErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int mdioTimeoutErrorMask : 1; /* 1E.D402.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D402.0 R/WPD Watchdog Timer Alarm Mask + AQ_GlobalInterruptMask_APPIA.u2.bits_2.watchdogTimerAlarmMask + + Provisionable Default = 0x1 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int watchdogTimerAlarmMask : 1; /* 1E.D402.0 R/WPD Provisionable Default = 0x1 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + } bits_2; + uint16_t word_2; + } u2; +} AQ_GlobalInterruptMask_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Chip-Wide Standard Interrupt Flags: 1E.FC00 */ +/* Global Chip-Wide Standard Interrupt Flags: 1E.FC00 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Chip-Wide Standard Interrupt Flags */ + union + { + struct + { + /*! \brief 1E.FC00.F RO PMA Standard Alarm 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.pmaStandardAlarm_1Interrupt + + + + 1 = Interrupt in PMA standard alarms 1 + + + Notes: + An interrupt was generated from bit 1.1.2. + An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ + unsigned int pmaStandardAlarm_1Interrupt : 1; /* 1E.FC00.F RO */ + /* 1 = Interrupt in PMA standard alarms 1 + */ + /*! \brief 1E.FC00.E RO PMA Standard Alarm 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.pmaStandardAlarm_2Interrupt + + + + 1 = Interrupt in PMA standard alarms 2 + + + Notes: + An interrupt was generated from either bit 1.8.B or 1.8.A. + An interrupt was generated from status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int pmaStandardAlarm_2Interrupt : 1; /* 1E.FC00.E RO */ + /* 1 = Interrupt in PMA standard alarms 2 + */ + /*! \brief 1E.FC00.D RO PCS Standard Alarm 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.pcsStandardAlarm_1Interrupt + + + + 1 = Interrupt in PCS standard alarms 1 + + + Notes: + An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ + unsigned int pcsStandardAlarm_1Interrupt : 1; /* 1E.FC00.D RO */ + /* 1 = Interrupt in PCS standard alarms 1 + */ + /*! \brief 1E.FC00.C RO PCS Standard Alarm 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.pcsStandardAlarm_2Interrupt + + + + 1 = Interrupt in PCS standard alarms 2 + + + Notes: + An interrupt was generated from status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int pcsStandardAlarm_2Interrupt : 1; /* 1E.FC00.C RO */ + /* 1 = Interrupt in PCS standard alarms 2 + */ + /*! \brief 1E.FC00.B RO PCS Standard Alarm 3 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.pcsStandardAlarm_3Interrupt + + + + 1 = Interrupt in PCS standard alarms 3 + + + Notes: + An interrupt was generated from status register ( See PCS 10GBASE-T Status 2 - Address 3.21 ) and the corresponding mask register. ( See PCS Standard Interrupt Mask 1 - Address 3.E021 ) */ + unsigned int pcsStandardAlarm_3Interrupt : 1; /* 1E.FC00.B RO */ + /* 1 = Interrupt in PCS standard alarms 3 + */ + /*! \brief 1E.FC00.A RO PHY XS Standard Alarms 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.phyXS_StandardAlarms_1Interrupt + + + + 1 = Interrupt in PHY XS standard alarms 1 + + + Notes: + An interrupt was generated from the status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ + unsigned int phyXS_StandardAlarms_1Interrupt : 1; /* 1E.FC00.A RO */ + /* 1 = Interrupt in PHY XS standard alarms 1 + */ + /*! \brief 1E.FC00.9 RO PHY XS Standard Alarms 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.phyXS_StandardAlarms_2Interrupt + + + + 1 = Interrupt in PHY XS standard alarms 2 + + + Notes: + An interrupt was generated from the status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int phyXS_StandardAlarms_2Interrupt : 1; /* 1E.FC00.9 RO */ + /* 1 = Interrupt in PHY XS standard alarms 2 + */ + /*! \brief 1E.FC00.8 RO Autonegotiation Standard Alarms 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.autonegotiationStandardAlarms_1Interrupt + + + + 1 = Interrupt in Autonegotiation standard alarms 1 + + + Notes: + An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See Autonegotiation Standard LASI Interrupt Mask 1: Address 7.D000 ) */ + unsigned int autonegotiationStandardAlarms_1Interrupt : 1; /* 1E.FC00.8 RO */ + /* 1 = Interrupt in Autonegotiation standard alarms 1 + */ + /*! \brief 1E.FC00.7 RO Autonegotiation Standard Alarms 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.autonegotiationStandardAlarms_2Interrupt + + + + 1 = Interrupt in Autonegotiation standard alarms 2 + + + Notes: + An interrupt was generated from status register ( See Autonegotiation 10GBASE-T Status Register - Address 7.21 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int autonegotiationStandardAlarms_2Interrupt : 1; /* 1E.FC00.7 RO */ + /* 1 = Interrupt in Autonegotiation standard alarms 2 + */ + /*! \brief 1E.FC00.6 RO GbE Standard Alarms Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.gbeStandardAlarmsInterrupt + + + + 1 = Interrupt in GbE standard alarms + + + Notes: + An interrupt was generated from the TGE core. */ + unsigned int gbeStandardAlarmsInterrupt : 1; /* 1E.FC00.6 RO */ + /* 1 = Interrupt in GbE standard alarms + */ + unsigned int reserved0 : 5; + /*! \brief 1E.FC00.0 RO All Vendor Alarms Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.allVendorAlarmsInterrupt + + + + 1 = Interrupt in all vendor alarms + + + Notes: + An interrupt was generated from status register ( See Global Chip-Wide LASI Vendor Interrupt Flags: Address 1E.FC01 ) and the corresponding mask register. ( See Global Interrupt LASI Mask: Address 1E.FF01 ) */ + unsigned int allVendorAlarmsInterrupt : 1; /* 1E.FC00.0 RO */ + /* 1 = Interrupt in all vendor alarms + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalChip_wideStandardInterruptFlags_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Chip-Wide Vendor Interrupt Flags: 1E.FC01 */ +/* Global Chip-Wide Vendor Interrupt Flags: 1E.FC01 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Chip-Wide Vendor Interrupt Flags */ + union + { + struct + { + /*! \brief 1E.FC01.F RO PMA Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.pmaVendorAlarmInterrupt + + + + 1 = Interrupt in PMA vendor specific alarm + + + Notes: + A PMA alarm was generated. ( See PHY XS Vendor Global Interrupt Flags 1- Address 4.F800 ) */ + unsigned int pmaVendorAlarmInterrupt : 1; /* 1E.FC01.F RO */ + /* 1 = Interrupt in PMA vendor specific alarm + */ + /*! \brief 1E.FC01.E RO PCS Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.pcsVendorAlarmInterrupt + + + + 1 = Interrupt in PCS vendor specific alarm + + + Notes: + A PCS alarm was generated. ( See PHY XS Vendor Global Interrupt Flags 1- Address 4.F800 ) */ + unsigned int pcsVendorAlarmInterrupt : 1; /* 1E.FC01.E RO */ + /* 1 = Interrupt in PCS vendor specific alarm + */ + /*! \brief 1E.FC01.D RO PHY XS Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.phyXS_VendorAlarmInterrupt + + + + 1 = Interrupt in PHY XS vendor specific alarm + + + Notes: + A PHY XS alarm was generated. ( See PHY XS Vendor Global LASI Interrupt Flags 1: Address 4.FC00 ) */ + unsigned int phyXS_VendorAlarmInterrupt : 1; /* 1E.FC01.D RO */ + /* 1 = Interrupt in PHY XS vendor specific alarm + */ + /*! \brief 1E.FC01.C RO Autonegotiation Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.autonegotiationVendorAlarmInterrupt + + + + 1 = Interrupt in Autonegotiation vendor specific alarm + + + Notes: + An Autonegotiation alarm was generated. ( See Autonegotiation Vendor Global LASI Interrupt Flags 1: Address 7.FC00 ) */ + unsigned int autonegotiationVendorAlarmInterrupt : 1; /* 1E.FC01.C RO */ + /* 1 = Interrupt in Autonegotiation vendor specific alarm + */ + /*! \brief 1E.FC01.B RO GbE Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.gbeVendorAlarmInterrupt + + + + 1 = Interrupt in GbE vendor specific alarm + + + Notes: + A GbE alarm was generated. ( See GbE PHY Vendor Global LASI Interrupt Flags 1: Address 1D.FC00 ) */ + unsigned int gbeVendorAlarmInterrupt : 1; /* 1E.FC01.B RO */ + /* 1 = Interrupt in GbE vendor specific alarm + */ + unsigned int reserved0 : 8; + /*! \brief 1E.FC01.2 RO Global Alarms 1 Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.globalAlarms_1Interrupt + + + + 1 = Interrupt in Global alarms 1 + + + Notes: + An interrupt was generated from status register ( See Global Vendor Alarms 1 - Address 1E.CC00 ) and the corresponding mask register. ( See Global Vendor Interrupt Mask - Address 1E.D400 ) */ + unsigned int globalAlarms_1Interrupt : 1; /* 1E.FC01.2 RO */ + /* 1 = Interrupt in Global alarms 1 + */ + /*! \brief 1E.FC01.1 RO Global Alarms 2 Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.globalAlarms_2Interrupt + + + + 1 = Interrupt in Global alarms 2 + + + Notes: + An interrupt was generated from status register ( See Global Alarms 2: Address 1E.CC01 ) and the corresponding mask register. ( See Global LASI Interrupt Mask 2: Address 1E.D401 ) */ + unsigned int globalAlarms_2Interrupt : 1; /* 1E.FC01.1 RO */ + /* 1 = Interrupt in Global alarms 2 + */ + /*! \brief 1E.FC01.0 RO Global Alarms 3 Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.globalAlarms_3Interrupt + + + + 1 = Interrupt in Global alarms 3 + + + Notes: + An interrupt was generated from status register ( See Global Vendor Alarms 2: Address 1E.CC01 ) and the corresponding mask register. ( See Global LASI Interrupt Mask 2: Address 1E.D401 ) */ + unsigned int globalAlarms_3Interrupt : 1; /* 1E.FC01.0 RO */ + /* 1 = Interrupt in Global alarms 3 + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalChip_wideVendorInterruptFlags_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Interrupt Chip-Wide Standard Mask: 1E.FF00 */ +/* Global Interrupt Chip-Wide Standard Mask: 1E.FF00 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Interrupt Chip-Wide Standard Mask */ + union + { + struct + { + /*! \brief 1E.FF00.F R/WPD PMA Standard Alarm 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.pmaStandardAlarm_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pmaStandardAlarm_1InterruptMask : 1; /* 1E.FF00.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.E R/WPD PMA Standard Alarm 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.pmaStandardAlarm_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pmaStandardAlarm_2InterruptMask : 1; /* 1E.FF00.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.D R/WPD PCS Standard Alarm 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.pcsStandardAlarm_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsStandardAlarm_1InterruptMask : 1; /* 1E.FF00.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.C R/WPD PCS Standard Alarm 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.pcsStandardAlarm_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsStandardAlarm_2InterruptMask : 1; /* 1E.FF00.C R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.B R/WPD PCS Standard Alarm 3 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.pcsStandardAlarm_3InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsStandardAlarm_3InterruptMask : 1; /* 1E.FF00.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.A R/WPD PHY XS Standard Alarms 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.phyXS_StandardAlarms_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int phyXS_StandardAlarms_1InterruptMask : 1; /* 1E.FF00.A R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.9 R/WPD PHY XS Standard Alarms 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.phyXS_StandardAlarms_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int phyXS_StandardAlarms_2InterruptMask : 1; /* 1E.FF00.9 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.8 R/WPD Autonegotiation Standard Alarms 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.autonegotiationStandardAlarms_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int autonegotiationStandardAlarms_1InterruptMask : 1; /* 1E.FF00.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.7 R/WPD Autonegotiation Standard Alarms 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.autonegotiationStandardAlarms_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int autonegotiationStandardAlarms_2InterruptMask : 1; /* 1E.FF00.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.6 R/WPD Gbe Standard Alarms Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.gbeStandardAlarmsInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int gbeStandardAlarmsInterruptMask : 1; /* 1E.FF00.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved0 : 5; + /*! \brief 1E.FF00.0 R/WPD All Vendor Alarms Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.allVendorAlarmsInterruptMask + + Provisionable Default = 0x1 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int allVendorAlarmsInterruptMask : 1; /* 1E.FF00.0 R/WPD Provisionable Default = 0x1 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalInterruptChip_wideStandardMask_APPIA; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Interrupt Chip-Wide Vendor Mask: 1E.FF01 */ +/* Global Interrupt Chip-Wide Vendor Mask: 1E.FF01 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Interrupt Chip-Wide Vendor Mask */ + union + { + struct + { + /*! \brief 1E.FF01.F R/WPD PMA Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.pmaVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pmaVendorAlarmInterruptMask : 1; /* 1E.FF01.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.E R/WPD PCS Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.pcsVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsVendorAlarmInterruptMask : 1; /* 1E.FF01.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.D R/WPD PHY XS Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.phyXS_VendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int phyXS_VendorAlarmInterruptMask : 1; /* 1E.FF01.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.C R/WPD Autonegotiation Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.autonegotiationVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int autonegotiationVendorAlarmInterruptMask : 1; /* 1E.FF01.C R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.B R/WPD GbE Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.gbeVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int gbeVendorAlarmInterruptMask : 1; /* 1E.FF01.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved0 : 8; + /*! \brief 1E.FF01.2 R/WPD Global Alarms 1 Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.globalAlarms_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int globalAlarms_1InterruptMask : 1; /* 1E.FF01.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.1 R/WPD Global Alarms 2 Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.globalAlarms_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int globalAlarms_2InterruptMask : 1; /* 1E.FF01.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.0 R/WPD Global Alarms 3 Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.globalAlarms_3InterruptMask + + Provisionable Default = 0x1 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int globalAlarms_3InterruptMask : 1; /* 1E.FF01.0 R/WPD Provisionable Default = 0x1 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalInterruptChip_wideVendorMask_APPIA; + +#endif +/*@}*/ +/*@}*/ diff --git a/qca/aq-fw-download/src/include/registerMap/AQ_RegGroupMaxSizes.h b/qca/aq-fw-download/src/include/registerMap/AQ_RegGroupMaxSizes.h new file mode 100644 index 000000000..08e255860 --- /dev/null +++ b/qca/aq-fw-download/src/include/registerMap/AQ_RegGroupMaxSizes.h @@ -0,0 +1,387 @@ +/* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +*/ +#ifndef AQ_REG_GROUP_MAX_SIZES +#define AQ_REG_GROUP_MAX_SIZES + +#define AQ_Autonegotiation10GBaseT_ControlRegister_BiggestVersion AQ_Autonegotiation10GBaseT_ControlRegister_HHD +#define AQ_Autonegotiation10GBaseT_StatusRegister_BiggestVersion AQ_Autonegotiation10GBaseT_StatusRegister_HHD +#define AQ_AutonegotiationAdvertisementRegister_BiggestVersion AQ_AutonegotiationAdvertisementRegister_HHD +#define AQ_AutonegotiationEeeAdvertisementRegister_BiggestVersion AQ_AutonegotiationEeeAdvertisementRegister_HHD +#define AQ_AutonegotiationEeeLinkPartnerAbilityRegister_BiggestVersion AQ_AutonegotiationEeeLinkPartnerAbilityRegister_HHD +#define AQ_AutonegotiationExtendedNextPageTransmitRegister_BiggestVersion AQ_AutonegotiationExtendedNextPageTransmitRegister_HHD +#define AQ_AutonegotiationExtendedNextPageUnformattedCodeRegister_BiggestVersion AQ_AutonegotiationExtendedNextPageUnformattedCodeRegister_HHD +#define AQ_AutonegotiationLinkPartnerBasePageAbilityRegister_BiggestVersion AQ_AutonegotiationLinkPartnerBasePageAbilityRegister_HHD +#define AQ_AutonegotiationLinkPartnerExtendedNextPageAbilityRegister_BiggestVersion AQ_AutonegotiationLinkPartnerExtendedNextPageAbilityRegister_HHD +#define AQ_AutonegotiationLinkPartnerExtendedNextPageUnformattedCodeRegister_BiggestVersion AQ_AutonegotiationLinkPartnerExtendedNextPageUnformattedCodeRegister_HHD +#define AQ_AutonegotiationReceiveLinkPartnerStatus_BiggestVersion AQ_AutonegotiationReceiveLinkPartnerStatus_HHD +#define AQ_AutonegotiationReceiveReservedVendorProvisioning_BiggestVersion AQ_AutonegotiationReceiveReservedVendorProvisioning_APPIA +#define AQ_AutonegotiationReceiveReservedVendorStatus_BiggestVersion AQ_AutonegotiationReceiveReservedVendorStatus_HHD +#define AQ_AutonegotiationReceiveVendorAlarms_BiggestVersion AQ_AutonegotiationReceiveVendorAlarms_HHD +#define AQ_AutonegotiationReceiveVendorInterruptMask_BiggestVersion AQ_AutonegotiationReceiveVendorInterruptMask_HHD +#define AQ_AutonegotiationReservedVendorProvisioning_BiggestVersion AQ_AutonegotiationReservedVendorProvisioning_HHD +#define AQ_AutonegotiationReservedVendorStatus_BiggestVersion AQ_AutonegotiationReservedVendorStatus_HHD +#define AQ_AutonegotiationStandardControl_1_BiggestVersion AQ_AutonegotiationStandardControl_1_HHD +#define AQ_AutonegotiationStandardDeviceIdentifier_BiggestVersion AQ_AutonegotiationStandardDeviceIdentifier_HHD +#define AQ_AutonegotiationStandardDevicesInPackage_BiggestVersion AQ_AutonegotiationStandardDevicesInPackage_HHD +#define AQ_AutonegotiationStandardInterruptMask_BiggestVersion AQ_AutonegotiationStandardInterruptMask_HHD +#define AQ_AutonegotiationStandardPackageIdentifier_BiggestVersion AQ_AutonegotiationStandardPackageIdentifier_HHD +#define AQ_AutonegotiationStandardStatus_1_BiggestVersion AQ_AutonegotiationStandardStatus_1_HHD +#define AQ_AutonegotiationStandardStatus_2_BiggestVersion AQ_AutonegotiationStandardStatus_2_HHD +#define AQ_AutonegotiationTransmitVendorAlarms_BiggestVersion AQ_AutonegotiationTransmitVendorAlarms_APPIA +#define AQ_AutonegotiationTransmitVendorInterruptMask_BiggestVersion AQ_AutonegotiationTransmitVendorInterruptMask_HHD +#define AQ_AutonegotiationVendorGlobalInterruptFlags_BiggestVersion AQ_AutonegotiationVendorGlobalInterruptFlags_HHD +#define AQ_AutonegotiationVendorProvisioning_BiggestVersion AQ_AutonegotiationVendorProvisioning_HHD +#define AQ_AutonegotiationVendorStatus_BiggestVersion AQ_AutonegotiationVendorStatus_HHD +#define AQ_GbePhyExtendedWolControl_BiggestVersion AQ_GbePhyExtendedWolControl_HHD +#define AQ_GbePhySgmii0RxStatus_BiggestVersion AQ_GbePhySgmii0RxStatus_HHD +#define AQ_GbePhySgmii0TxStatus_BiggestVersion AQ_GbePhySgmii0TxStatus_HHD +#define AQ_GbePhySgmii1RxStatus_BiggestVersion AQ_GbePhySgmii1RxStatus_HHD +#define AQ_GbePhySgmii1TxStatus_BiggestVersion AQ_GbePhySgmii1TxStatus_HHD +#define AQ_GbePhySgmii1WolStatus_BiggestVersion AQ_GbePhySgmii1WolStatus_HHD +#define AQ_GbePhySgmiiRxAlarms_BiggestVersion AQ_GbePhySgmiiRxAlarms_HHD +#define AQ_GbePhySgmiiRxInterruptMask_BiggestVersion AQ_GbePhySgmiiRxInterruptMask_HHD +#define AQ_GbePhySgmiiTestControl_BiggestVersion AQ_GbePhySgmiiTestControl_HHD +#define AQ_GbePhySgmiiTxAlarms_BiggestVersion AQ_GbePhySgmiiTxAlarms_HHD +#define AQ_GbePhySgmiiTxInterruptMask_BiggestVersion AQ_GbePhySgmiiTxInterruptMask_HHD +#define AQ_GbePhySgmiiWolStatus_BiggestVersion AQ_GbePhySgmiiWolStatus_HHD +#define AQ_GbePhyVendorGlobalInterruptFlags_BiggestVersion AQ_GbePhyVendorGlobalInterruptFlags_HHD +#define AQ_GbePhyWolControl_BiggestVersion AQ_GbePhyWolControl_HHD +#define AQ_GbePhysgmii1WolStatus_BiggestVersion AQ_GbePhysgmii1WolStatus_APPIA +#define AQ_GbeReservedProvisioning_BiggestVersion AQ_GbeReservedProvisioning_HHD +#define AQ_GbeStandardDeviceIdentifier_BiggestVersion AQ_GbeStandardDeviceIdentifier_HHD +#define AQ_GbeStandardDevicesInPackage_BiggestVersion AQ_GbeStandardDevicesInPackage_HHD +#define AQ_GbeStandardPackageIdentifier_BiggestVersion AQ_GbeStandardPackageIdentifier_HHD +#define AQ_GbeStandardStatus_2_BiggestVersion AQ_GbeStandardStatus_2_HHD +#define AQ_GbeStandardVendorDevicesInPackage_BiggestVersion AQ_GbeStandardVendorDevicesInPackage_HHD +#define AQ_GlobalAlarms_BiggestVersion AQ_GlobalAlarms_HHD +#define AQ_GlobalCableDiagnosticImpedance_BiggestVersion AQ_GlobalCableDiagnosticImpedance_HHD +#define AQ_GlobalCableDiagnosticStatus_BiggestVersion AQ_GlobalCableDiagnosticStatus_APPIA +#define AQ_GlobalChipIdentification_BiggestVersion AQ_GlobalChipIdentification_APPIA +#define AQ_GlobalChipRevision_BiggestVersion AQ_GlobalChipRevision_APPIA +#define AQ_GlobalChip_wideStandardInterruptFlags_BiggestVersion AQ_GlobalChip_wideStandardInterruptFlags_HHD +#define AQ_GlobalChip_wideVendorInterruptFlags_BiggestVersion AQ_GlobalChip_wideVendorInterruptFlags_HHD +#define AQ_GlobalControl_BiggestVersion AQ_GlobalControl_HHD +#define AQ_GlobalDaisyChainStatus_BiggestVersion AQ_GlobalDaisyChainStatus_HHD +#define AQ_GlobalDiagnosticProvisioning_BiggestVersion AQ_GlobalDiagnosticProvisioning_HHD +#define AQ_GlobalEeeProvisioning_BiggestVersion AQ_GlobalEeeProvisioning_HHD +#define AQ_GlobalFaultMessage_BiggestVersion AQ_GlobalFaultMessage_HHD +#define AQ_GlobalFirmwareID_BiggestVersion AQ_GlobalFirmwareID_HHD +#define AQ_GlobalGeneralProvisioning_BiggestVersion AQ_GlobalGeneralProvisioning_HHD +#define AQ_GlobalGeneralStatus_BiggestVersion AQ_GlobalGeneralStatus_HHD +#define AQ_GlobalInterruptChip_wideStandardMask_BiggestVersion AQ_GlobalInterruptChip_wideStandardMask_HHD +#define AQ_GlobalInterruptChip_wideVendorMask_BiggestVersion AQ_GlobalInterruptChip_wideVendorMask_HHD +#define AQ_GlobalInterruptMask_BiggestVersion AQ_GlobalInterruptMask_HHD +#define AQ_GlobalLedProvisioning_BiggestVersion AQ_GlobalLedProvisioning_HHD +#define AQ_GlobalMailboxInterface_BiggestVersion AQ_GlobalMailboxInterface_HHD +#define AQ_GlobalMicroprocessorScratchPad_BiggestVersion AQ_GlobalMicroprocessorScratchPad_HHD +#define AQ_GlobalNvrInterface_BiggestVersion AQ_GlobalNvrInterface_HHD +#define AQ_GlobalNvrProvisioning_BiggestVersion AQ_GlobalNvrProvisioning_HHD +#define AQ_GlobalPinStatus_BiggestVersion AQ_GlobalPinStatus_HHD +#define AQ_GlobalPrimaryStatus_BiggestVersion AQ_GlobalPrimaryStatus_APPIA +#define AQ_GlobalReservedProvisioning_BiggestVersion AQ_GlobalReservedProvisioning_HHD +#define AQ_GlobalReservedStatus_BiggestVersion AQ_GlobalReservedStatus_HHD +#define AQ_GlobalResetControl_BiggestVersion AQ_GlobalResetControl_HHD +#define AQ_GlobalSmbus_0Provisioning_BiggestVersion AQ_GlobalSmbus_0Provisioning_HHD +#define AQ_GlobalSmbus_1Provisioning_BiggestVersion AQ_GlobalSmbus_1Provisioning_HHD +#define AQ_GlobalStandardControl_1_BiggestVersion AQ_GlobalStandardControl_1_HHD +#define AQ_GlobalStandardDeviceIdentifier_BiggestVersion AQ_GlobalStandardDeviceIdentifier_HHD +#define AQ_GlobalStandardDevicesInPackage_BiggestVersion AQ_GlobalStandardDevicesInPackage_HHD +#define AQ_GlobalStandardPackageIdentifier_BiggestVersion AQ_GlobalStandardPackageIdentifier_HHD +#define AQ_GlobalStandardStatus_2_BiggestVersion AQ_GlobalStandardStatus_2_HHD +#define AQ_GlobalStandardVendorDevicesInPackage_BiggestVersion AQ_GlobalStandardVendorDevicesInPackage_HHD +#define AQ_GlobalStatus_BiggestVersion AQ_GlobalStatus_HHD +#define AQ_GlobalThermalProvisioning_BiggestVersion AQ_GlobalThermalProvisioning_HHD +#define AQ_GlobalThermalStatus_BiggestVersion AQ_GlobalThermalStatus_HHD +#define AQ_Kr0AutonegotiationAdvertisementWord_BiggestVersion AQ_Kr0AutonegotiationAdvertisementWord_HHD +#define AQ_Kr0AutonegotiationControl_BiggestVersion AQ_Kr0AutonegotiationControl_HHD +#define AQ_Kr0AutonegotiationExtendedNextPageAdvertisementWord_BiggestVersion AQ_Kr0AutonegotiationExtendedNextPageAdvertisementWord_HHD +#define AQ_Kr0AutonegotiationStatus_BiggestVersion AQ_Kr0AutonegotiationStatus_HHD +#define AQ_Kr0LinkPartnerAutonegotiationAdvertisementWord_BiggestVersion AQ_Kr0LinkPartnerAutonegotiationAdvertisementWord_HHD +#define AQ_Kr0LinkPartnerAutonegotiationExtendedNextPageAdvertisementWord_BiggestVersion AQ_Kr0LinkPartnerAutonegotiationExtendedNextPageAdvertisementWord_HHD +#define AQ_Kr1AutonegotiationAdvertisementWord_BiggestVersion AQ_Kr1AutonegotiationAdvertisementWord_HHD +#define AQ_Kr1AutonegotiationControl_BiggestVersion AQ_Kr1AutonegotiationControl_HHD +#define AQ_Kr1AutonegotiationExtendedNextPageAdvertisementWord_BiggestVersion AQ_Kr1AutonegotiationExtendedNextPageAdvertisementWord_HHD +#define AQ_Kr1AutonegotiationStatus_BiggestVersion AQ_Kr1AutonegotiationStatus_HHD +#define AQ_Kr1LinkPartnerAutonegotiationAdvertisementWord_BiggestVersion AQ_Kr1LinkPartnerAutonegotiationAdvertisementWord_HHD +#define AQ_Kr1LinkPartnerAutonegotiationExtendedNextPageAdvertisementWord_BiggestVersion AQ_Kr1LinkPartnerAutonegotiationExtendedNextPageAdvertisementWord_HHD +#define AQ_MsmLineFifoControlRegister_BiggestVersion AQ_MsmLineFifoControlRegister_HHD +#define AQ_MsmLineGeneralControlRegister_BiggestVersion AQ_MsmLineGeneralControlRegister_HHD +#define AQ_MsmLineGeneralStatusRegister_BiggestVersion AQ_MsmLineGeneralStatusRegister_HHD +#define AQ_MsmLineRxAlignmentErrorsCounterRegister_BiggestVersion AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD +#define AQ_MsmLineRxBroadcastFramesCounterRegister_BiggestVersion AQ_MsmLineRxBroadcastFramesCounterRegister_HHD +#define AQ_MsmLineRxErrorsCounterRegister_BiggestVersion AQ_MsmLineRxErrorsCounterRegister_HHD +#define AQ_MsmLineRxFcsErrorsCounterRegister_BiggestVersion AQ_MsmLineRxFcsErrorsCounterRegister_HHD +#define AQ_MsmLineRxGoodFramesCounterRegister_BiggestVersion AQ_MsmLineRxGoodFramesCounterRegister_HHD +#define AQ_MsmLineRxInRangeLengthErrorsCounterRegister_BiggestVersion AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD +#define AQ_MsmLineRxMulticastFramesCounterRegister_BiggestVersion AQ_MsmLineRxMulticastFramesCounterRegister_HHD +#define AQ_MsmLineRxOctetsCounterRegister_BiggestVersion AQ_MsmLineRxOctetsCounterRegister_HHD +#define AQ_MsmLineRxPauseFramesCounterRegister_BiggestVersion AQ_MsmLineRxPauseFramesCounterRegister_HHD +#define AQ_MsmLineRxTooLongErrorsCounterRegister_BiggestVersion AQ_MsmLineRxTooLongErrorsCounterRegister_HHD +#define AQ_MsmLineRxUnicastFramesCounterRegister_BiggestVersion AQ_MsmLineRxUnicastFramesCounterRegister_HHD +#define AQ_MsmLineRxVlanFramesCounterRegister_BiggestVersion AQ_MsmLineRxVlanFramesCounterRegister_HHD +#define AQ_MsmLineTxBroadcastFramesCounterRegister_BiggestVersion AQ_MsmLineTxBroadcastFramesCounterRegister_HHD +#define AQ_MsmLineTxErrorsCounterRegister_BiggestVersion AQ_MsmLineTxErrorsCounterRegister_HHD +#define AQ_MsmLineTxGoodFramesCounterRegister_BiggestVersion AQ_MsmLineTxGoodFramesCounterRegister_HHD +#define AQ_MsmLineTxIpgControlRegister_BiggestVersion AQ_MsmLineTxIpgControlRegister_HHD +#define AQ_MsmLineTxMulticastFramesCounterRegister_BiggestVersion AQ_MsmLineTxMulticastFramesCounterRegister_HHD +#define AQ_MsmLineTxOctetsCounterRegister_BiggestVersion AQ_MsmLineTxOctetsCounterRegister_HHD +#define AQ_MsmLineTxPauseFramesCounterRegister_BiggestVersion AQ_MsmLineTxPauseFramesCounterRegister_HHD +#define AQ_MsmLineTxUnicastFramesCounterRegister_BiggestVersion AQ_MsmLineTxUnicastFramesCounterRegister_HHD +#define AQ_MsmLineTxVlanFramesCounterRegister_BiggestVersion AQ_MsmLineTxVlanFramesCounterRegister_HHD +#define AQ_MsmSystemFifoControlRegister_BiggestVersion AQ_MsmSystemFifoControlRegister_HHD +#define AQ_MsmSystemGeneralControlRegister_BiggestVersion AQ_MsmSystemGeneralControlRegister_HHD +#define AQ_MsmSystemGeneralStatusRegister_BiggestVersion AQ_MsmSystemGeneralStatusRegister_HHD +#define AQ_MsmSystemRxAlignmentErrorsCounterRegister_BiggestVersion AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD +#define AQ_MsmSystemRxBroadcastFramesCounterRegister_BiggestVersion AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD +#define AQ_MsmSystemRxErrorsCounterRegister_BiggestVersion AQ_MsmSystemRxErrorsCounterRegister_HHD +#define AQ_MsmSystemRxFcsErrorsCounterRegister_BiggestVersion AQ_MsmSystemRxFcsErrorsCounterRegister_HHD +#define AQ_MsmSystemRxGoodFramesCounterRegister_BiggestVersion AQ_MsmSystemRxGoodFramesCounterRegister_HHD +#define AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_BiggestVersion AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD +#define AQ_MsmSystemRxMulticastFramesCounterRegister_BiggestVersion AQ_MsmSystemRxMulticastFramesCounterRegister_HHD +#define AQ_MsmSystemRxOctetsCounterRegister_BiggestVersion AQ_MsmSystemRxOctetsCounterRegister_HHD +#define AQ_MsmSystemRxPauseFramesCounterRegister_BiggestVersion AQ_MsmSystemRxPauseFramesCounterRegister_HHD +#define AQ_MsmSystemRxTooLongErrorsCounterRegister_BiggestVersion AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD +#define AQ_MsmSystemRxUnicastFramesCounterRegister_BiggestVersion AQ_MsmSystemRxUnicastFramesCounterRegister_HHD +#define AQ_MsmSystemRxVlanFramesCounterRegister_BiggestVersion AQ_MsmSystemRxVlanFramesCounterRegister_HHD +#define AQ_MsmSystemTxBroadcastFramesCounterRegister_BiggestVersion AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD +#define AQ_MsmSystemTxErrorsCounterRegister_BiggestVersion AQ_MsmSystemTxErrorsCounterRegister_HHD +#define AQ_MsmSystemTxGoodFramesCounterRegister_BiggestVersion AQ_MsmSystemTxGoodFramesCounterRegister_HHD +#define AQ_MsmSystemTxIpgControlRegister_BiggestVersion AQ_MsmSystemTxIpgControlRegister_HHD +#define AQ_MsmSystemTxMulticastFramesCounterRegister_BiggestVersion AQ_MsmSystemTxMulticastFramesCounterRegister_HHD +#define AQ_MsmSystemTxOctetsCounterRegister_BiggestVersion AQ_MsmSystemTxOctetsCounterRegister_HHD +#define AQ_MsmSystemTxPauseFramesCounterRegister_BiggestVersion AQ_MsmSystemTxPauseFramesCounterRegister_HHD +#define AQ_MsmSystemTxUnicastFramesCounterRegister_BiggestVersion AQ_MsmSystemTxUnicastFramesCounterRegister_HHD +#define AQ_MsmSystemTxVlanFramesCounterRegister_BiggestVersion AQ_MsmSystemTxVlanFramesCounterRegister_HHD +#define AQ_MssEgressControlRegister_BiggestVersion AQ_MssEgressControlRegister_HHD +#define AQ_MssEgressEccInterruptStatusRegister_BiggestVersion AQ_MssEgressEccInterruptStatusRegister_HHD +#define AQ_MssEgressInterruptMaskRegister_BiggestVersion AQ_MssEgressInterruptMaskRegister_HHD +#define AQ_MssEgressInterruptStatusRegister_BiggestVersion AQ_MssEgressInterruptStatusRegister_HHD +#define AQ_MssEgressLutAddressControlRegister_BiggestVersion AQ_MssEgressLutAddressControlRegister_HHD +#define AQ_MssEgressLutControlRegister_BiggestVersion AQ_MssEgressLutControlRegister_HHD +#define AQ_MssEgressLutDataControlRegister_BiggestVersion AQ_MssEgressLutDataControlRegister_HHD +#define AQ_MssEgressMtuSizeControlRegister_BiggestVersion AQ_MssEgressMtuSizeControlRegister_HHD +#define AQ_MssEgressPnControlRegister_BiggestVersion AQ_MssEgressPnControlRegister_HHD +#define AQ_MssEgressSaExpiredStatusRegister_BiggestVersion AQ_MssEgressSaExpiredStatusRegister_HHD +#define AQ_MssEgressSaThresholdExpiredStatusRegister_BiggestVersion AQ_MssEgressSaThresholdExpiredStatusRegister_HHD +#define AQ_MssEgressVlanControlRegister_BiggestVersion AQ_MssEgressVlanControlRegister_HHD +#define AQ_MssEgressVlanTpid_0Register_BiggestVersion AQ_MssEgressVlanTpid_0Register_HHD +#define AQ_MssEgressVlanTpid_1Register_BiggestVersion AQ_MssEgressVlanTpid_1Register_HHD +#define AQ_MssIngressControlRegister_BiggestVersion AQ_MssIngressControlRegister_HHD +#define AQ_MssIngressEccInterruptStatusRegister_BiggestVersion AQ_MssIngressEccInterruptStatusRegister_HHD +#define AQ_MssIngressInterruptMaskRegister_BiggestVersion AQ_MssIngressInterruptMaskRegister_HHD +#define AQ_MssIngressInterruptStatusRegister_BiggestVersion AQ_MssIngressInterruptStatusRegister_HHD +#define AQ_MssIngressLutAddressControlRegister_BiggestVersion AQ_MssIngressLutAddressControlRegister_HHD +#define AQ_MssIngressLutControlRegister_BiggestVersion AQ_MssIngressLutControlRegister_HHD +#define AQ_MssIngressLutDataControlRegister_BiggestVersion AQ_MssIngressLutDataControlRegister_HHD +#define AQ_MssIngressMtuSizeControlRegister_BiggestVersion AQ_MssIngressMtuSizeControlRegister_HHD +#define AQ_MssIngressSaControlRegister_BiggestVersion AQ_MssIngressSaControlRegister_HHD +#define AQ_MssIngressSaExpiredStatusRegister_BiggestVersion AQ_MssIngressSaExpiredStatusRegister_HHD +#define AQ_MssIngressSaIcvErrorStatusRegister_BiggestVersion AQ_MssIngressSaIcvErrorStatusRegister_HHD +#define AQ_MssIngressSaReplayErrorStatusRegister_BiggestVersion AQ_MssIngressSaReplayErrorStatusRegister_HHD +#define AQ_MssIngressSaThresholdExpiredStatusRegister_BiggestVersion AQ_MssIngressSaThresholdExpiredStatusRegister_HHD +#define AQ_MssIngressVlanControlRegister_BiggestVersion AQ_MssIngressVlanControlRegister_HHD +#define AQ_MssIngressVlanTpid_0Register_BiggestVersion AQ_MssIngressVlanTpid_0Register_HHD +#define AQ_MssIngressVlanTpid_1Register_BiggestVersion AQ_MssIngressVlanTpid_1Register_HHD +#define AQ_Pcs10GBaseT_Status_BiggestVersion AQ_Pcs10GBaseT_Status_APPIA +#define AQ_Pcs10G_Status_BiggestVersion AQ_Pcs10G_Status_HHD +#define AQ_Pcs10G_base_rPcsTest_patternControl_BiggestVersion AQ_Pcs10G_base_rPcsTest_patternControl_HHD +#define AQ_Pcs10G_base_rPcsTest_patternErrorCounter_BiggestVersion AQ_Pcs10G_base_rPcsTest_patternErrorCounter_HHD +#define AQ_Pcs10G_base_rTestPatternSeedA_BiggestVersion AQ_Pcs10G_base_rTestPatternSeedA_HHD +#define AQ_Pcs10G_base_rTestPatternSeedB_BiggestVersion AQ_Pcs10G_base_rTestPatternSeedB_HHD +#define AQ_PcsEeeCapabilityRegister_BiggestVersion AQ_PcsEeeCapabilityRegister_HHD +#define AQ_PcsEeeWakeErrorCounter_BiggestVersion AQ_PcsEeeWakeErrorCounter_HHD +#define AQ_PcsReceiveStandardInterruptMask_BiggestVersion AQ_PcsReceiveStandardInterruptMask_APPIA +#define AQ_PcsReceiveVendorAlarms_BiggestVersion AQ_PcsReceiveVendorAlarms_HHD +#define AQ_PcsReceiveVendorCorrectedFrame_1IterationCounter_BiggestVersion AQ_PcsReceiveVendorCorrectedFrame_1IterationCounter_HHD +#define AQ_PcsReceiveVendorCorrectedFrame_2IterationCounter_BiggestVersion AQ_PcsReceiveVendorCorrectedFrame_2IterationCounter_HHD +#define AQ_PcsReceiveVendorCorrectedFrame_3IterationCounter_BiggestVersion AQ_PcsReceiveVendorCorrectedFrame_3IterationCounter_HHD +#define AQ_PcsReceiveVendorCorrectedFrame_4IterationCounter_BiggestVersion AQ_PcsReceiveVendorCorrectedFrame_4IterationCounter_HHD +#define AQ_PcsReceiveVendorCorrectedFrame_5IterationCounter_BiggestVersion AQ_PcsReceiveVendorCorrectedFrame_5IterationCounter_HHD +#define AQ_PcsReceiveVendorCorrectedFrame_6IterationCounter_BiggestVersion AQ_PcsReceiveVendorCorrectedFrame_6IterationCounter_HHD +#define AQ_PcsReceiveVendorCorrectedFrame_7IterationCounter_BiggestVersion AQ_PcsReceiveVendorCorrectedFrame_7IterationCounter_HHD +#define AQ_PcsReceiveVendorCorrectedFrame_8IterationCounter_BiggestVersion AQ_PcsReceiveVendorCorrectedFrame_8IterationCounter_HHD +#define AQ_PcsReceiveVendorCrc_8ErrorCounter_BiggestVersion AQ_PcsReceiveVendorCrc_8ErrorCounter_HHD +#define AQ_PcsReceiveVendorDebug_BiggestVersion AQ_PcsReceiveVendorDebug_HHD +#define AQ_PcsReceiveVendorFcsErrorFrameCounter_BiggestVersion AQ_PcsReceiveVendorFcsErrorFrameCounter_HHD +#define AQ_PcsReceiveVendorFcsNoErrorFrameCounter_BiggestVersion AQ_PcsReceiveVendorFcsNoErrorFrameCounter_HHD +#define AQ_PcsReceiveVendorInterruptMask_BiggestVersion AQ_PcsReceiveVendorInterruptMask_HHD +#define AQ_PcsReceiveVendorProvisioning_BiggestVersion AQ_PcsReceiveVendorProvisioning_HHD +#define AQ_PcsReceiveVendorState_BiggestVersion AQ_PcsReceiveVendorState_HHD +#define AQ_PcsReceiveVendorUncorrectedFrameCounter_BiggestVersion AQ_PcsReceiveVendorUncorrectedFrameCounter_HHD +#define AQ_PcsReceiveXfi0Provisioning_BiggestVersion AQ_PcsReceiveXfi0Provisioning_HHD +#define AQ_PcsReceiveXfi0VendorState_BiggestVersion AQ_PcsReceiveXfi0VendorState_HHD +#define AQ_PcsReceiveXfi1Provisioning_BiggestVersion AQ_PcsReceiveXfi1Provisioning_HHD +#define AQ_PcsReceiveXfi1VendorState_BiggestVersion AQ_PcsReceiveXfi1VendorState_HHD +#define AQ_PcsSerdesMuxSwapTxrxRegister_BiggestVersion AQ_PcsSerdesMuxSwapTxrxRegister_HHD +#define AQ_PcsStandardControl_1_BiggestVersion AQ_PcsStandardControl_1_HHD +#define AQ_PcsStandardControl_2_BiggestVersion AQ_PcsStandardControl_2_HHD +#define AQ_PcsStandardDeviceIdentifier_BiggestVersion AQ_PcsStandardDeviceIdentifier_HHD +#define AQ_PcsStandardDevicesInPackage_BiggestVersion AQ_PcsStandardDevicesInPackage_HHD +#define AQ_PcsStandardInterruptMask_BiggestVersion AQ_PcsStandardInterruptMask_HHD +#define AQ_PcsStandardPackageIdentifier_BiggestVersion AQ_PcsStandardPackageIdentifier_HHD +#define AQ_PcsStandardSpeedAbility_BiggestVersion AQ_PcsStandardSpeedAbility_HHD +#define AQ_PcsStandardStatus_1_BiggestVersion AQ_PcsStandardStatus_1_HHD +#define AQ_PcsStandardStatus_2_BiggestVersion AQ_PcsStandardStatus_2_HHD +#define AQ_PcsTransmitReservedVendorProvisioning_BiggestVersion AQ_PcsTransmitReservedVendorProvisioning_HHD +#define AQ_PcsTransmitVendorAlarms_BiggestVersion AQ_PcsTransmitVendorAlarms_APPIA +#define AQ_PcsTransmitVendorDebug_BiggestVersion AQ_PcsTransmitVendorDebug_HHD +#define AQ_PcsTransmitVendorFcsErrorFrameCounter_BiggestVersion AQ_PcsTransmitVendorFcsErrorFrameCounter_HHD +#define AQ_PcsTransmitVendorFcsNoErrorFrameCounter_BiggestVersion AQ_PcsTransmitVendorFcsNoErrorFrameCounter_HHD +#define AQ_PcsTransmitVendorInterruptMask_BiggestVersion AQ_PcsTransmitVendorInterruptMask_APPIA +#define AQ_PcsTransmitVendorProvisioning_BiggestVersion AQ_PcsTransmitVendorProvisioning_HHD +#define AQ_PcsTransmitXfi0VendorProvisioning_BiggestVersion AQ_PcsTransmitXfi0VendorProvisioning_HHD +#define AQ_PcsTransmitXfi0VendorState_BiggestVersion AQ_PcsTransmitXfi0VendorState_HHD +#define AQ_PcsTransmitXfi1VendorProvisioning_BiggestVersion AQ_PcsTransmitXfi1VendorProvisioning_HHD +#define AQ_PcsTransmitXfi1VendorState_BiggestVersion AQ_PcsTransmitXfi1VendorState_HHD +#define AQ_PcsTransmitXfiVendorProvisioning_BiggestVersion AQ_PcsTransmitXfiVendorProvisioning_HHD +#define AQ_PcsTransmitXgsVendorState_BiggestVersion AQ_PcsTransmitXgsVendorState_HHD +#define AQ_PcsVendorGlobalInterruptFlags_BiggestVersion AQ_PcsVendorGlobalInterruptFlags_HHD +#define AQ_PhyXS_EeeCapabilityRegister_BiggestVersion AQ_PhyXS_EeeCapabilityRegister_HHD +#define AQ_PhyXS_EeeWakeErrorCounter_BiggestVersion AQ_PhyXS_EeeWakeErrorCounter_HHD +#define AQ_PhyXS_Receive_xauiTx_PcsStatus_BiggestVersion AQ_PhyXS_Receive_xauiTx_PcsStatus_HHD +#define AQ_PhyXS_Receive_xauiTx_ReservedVendorProvisioning_BiggestVersion AQ_PhyXS_Receive_xauiTx_ReservedVendorProvisioning_HHD +#define AQ_PhyXS_Receive_xauiTx_VendorAlarms_BiggestVersion AQ_PhyXS_Receive_xauiTx_VendorAlarms_HHD +#define AQ_PhyXS_Receive_xauiTx_VendorDebug_BiggestVersion AQ_PhyXS_Receive_xauiTx_VendorDebug_HHD +#define AQ_PhyXS_Receive_xauiTx_VendorInterruptMask_BiggestVersion AQ_PhyXS_Receive_xauiTx_VendorInterruptMask_HHD +#define AQ_PhyXS_SerdesConfiguration_BiggestVersion AQ_PhyXS_SerdesConfiguration_HHD +#define AQ_PhyXS_SerdesLane_0Configuration_BiggestVersion AQ_PhyXS_SerdesLane_0Configuration_HHD +#define AQ_PhyXS_SerdesLane_1Configuration_BiggestVersion AQ_PhyXS_SerdesLane_1Configuration_HHD +#define AQ_PhyXS_SerdesLane_2Configuration_BiggestVersion AQ_PhyXS_SerdesLane_2Configuration_HHD +#define AQ_PhyXS_SerdesLane_3Configuration_BiggestVersion AQ_PhyXS_SerdesLane_3Configuration_HHD +#define AQ_PhyXS_SerdesLut_BiggestVersion AQ_PhyXS_SerdesLut_HHD +#define AQ_PhyXS_StandardControl_1_BiggestVersion AQ_PhyXS_StandardControl_1_HHD +#define AQ_PhyXS_StandardDeviceIdentifier_BiggestVersion AQ_PhyXS_StandardDeviceIdentifier_HHD +#define AQ_PhyXS_StandardDevicesInPackage_BiggestVersion AQ_PhyXS_StandardDevicesInPackage_HHD +#define AQ_PhyXS_StandardPackageIdentifier_BiggestVersion AQ_PhyXS_StandardPackageIdentifier_HHD +#define AQ_PhyXS_StandardSpeedAbility_BiggestVersion AQ_PhyXS_StandardSpeedAbility_HHD +#define AQ_PhyXS_StandardStatus_1_BiggestVersion AQ_PhyXS_StandardStatus_1_HHD +#define AQ_PhyXS_StandardStatus_2_BiggestVersion AQ_PhyXS_StandardStatus_2_HHD +#define AQ_PhyXS_StandardXGXS_LaneStatus_BiggestVersion AQ_PhyXS_StandardXGXS_LaneStatus_HHD +#define AQ_PhyXS_StandardXGXS_TestControl_BiggestVersion AQ_PhyXS_StandardXGXS_TestControl_HHD +#define AQ_PhyXS_SystemInterfaceConnectionStatus_BiggestVersion AQ_PhyXS_SystemInterfaceConnectionStatus_HHD +#define AQ_PhyXS_Transmit_xauiRx_PcsStatus_BiggestVersion AQ_PhyXS_Transmit_xauiRx_PcsStatus_HHD +#define AQ_PhyXS_Transmit_xauiRx_ReservedVendorProvisioning_BiggestVersion AQ_PhyXS_Transmit_xauiRx_ReservedVendorProvisioning_HHD +#define AQ_PhyXS_Transmit_xauiRx_ReservedVendorState_BiggestVersion AQ_PhyXS_Transmit_xauiRx_ReservedVendorState_HHD +#define AQ_PhyXS_Transmit_xauiRx_StandardInterruptMask_BiggestVersion AQ_PhyXS_Transmit_xauiRx_StandardInterruptMask_HHD +#define AQ_PhyXS_Transmit_xauiRx_TestPatternErrorCounter_BiggestVersion AQ_PhyXS_Transmit_xauiRx_TestPatternErrorCounter_HHD +#define AQ_PhyXS_Transmit_xauiRx_VendorAlarms_BiggestVersion AQ_PhyXS_Transmit_xauiRx_VendorAlarms_HHD +#define AQ_PhyXS_Transmit_xauiRx_VendorDebug_BiggestVersion AQ_PhyXS_Transmit_xauiRx_VendorDebug_HHD +#define AQ_PhyXS_Transmit_xauiRx_VendorInterruptMask_BiggestVersion AQ_PhyXS_Transmit_xauiRx_VendorInterruptMask_HHD +#define AQ_PhyXS_VendorGlobalInterruptFlags_BiggestVersion AQ_PhyXS_VendorGlobalInterruptFlags_HHD +#define AQ_PifMailboxControl_BiggestVersion AQ_PifMailboxControl_HHD +#define AQ_Pma10GBaseT_FastRetrainStatusAndControl_BiggestVersion AQ_Pma10GBaseT_FastRetrainStatusAndControl_HHD +#define AQ_Pma10GBaseT_PairSwapAndPolarityStatus_BiggestVersion AQ_Pma10GBaseT_PairSwapAndPolarityStatus_HHD +#define AQ_Pma10GBaseT_ReceiveSignalPowerChannelA_BiggestVersion AQ_Pma10GBaseT_ReceiveSignalPowerChannelA_HHD +#define AQ_Pma10GBaseT_ReceiveSignalPowerChannelB_BiggestVersion AQ_Pma10GBaseT_ReceiveSignalPowerChannelB_HHD +#define AQ_Pma10GBaseT_ReceiveSignalPowerChannelC_BiggestVersion AQ_Pma10GBaseT_ReceiveSignalPowerChannelC_HHD +#define AQ_Pma10GBaseT_ReceiveSignalPowerChannelD_BiggestVersion AQ_Pma10GBaseT_ReceiveSignalPowerChannelD_HHD +#define AQ_Pma10GBaseT_SNR_MinimumOperatingMarginChannelA_BiggestVersion AQ_Pma10GBaseT_SNR_MinimumOperatingMarginChannelA_HHD +#define AQ_Pma10GBaseT_SNR_MinimumOperatingMarginChannelB_BiggestVersion AQ_Pma10GBaseT_SNR_MinimumOperatingMarginChannelB_HHD +#define AQ_Pma10GBaseT_SNR_MinimumOperatingMarginChannelC_BiggestVersion AQ_Pma10GBaseT_SNR_MinimumOperatingMarginChannelC_HHD +#define AQ_Pma10GBaseT_SNR_MinimumOperatingMarginChannelD_BiggestVersion AQ_Pma10GBaseT_SNR_MinimumOperatingMarginChannelD_HHD +#define AQ_Pma10GBaseT_SNR_OperatingMarginChannelA_BiggestVersion AQ_Pma10GBaseT_SNR_OperatingMarginChannelA_HHD +#define AQ_Pma10GBaseT_SNR_OperatingMarginChannelB_BiggestVersion AQ_Pma10GBaseT_SNR_OperatingMarginChannelB_HHD +#define AQ_Pma10GBaseT_SNR_OperatingMarginChannelC_BiggestVersion AQ_Pma10GBaseT_SNR_OperatingMarginChannelC_HHD +#define AQ_Pma10GBaseT_SNR_OperatingMarginChannelD_BiggestVersion AQ_Pma10GBaseT_SNR_OperatingMarginChannelD_HHD +#define AQ_Pma10GBaseT_SkewDelay_BiggestVersion AQ_Pma10GBaseT_SkewDelay_HHD +#define AQ_Pma10GBaseT_Status_BiggestVersion AQ_Pma10GBaseT_Status_HHD +#define AQ_Pma10GBaseT_TestModes_BiggestVersion AQ_Pma10GBaseT_TestModes_HHD +#define AQ_Pma10GBaseT_TxPowerBackoffAndShortReachSetting_BiggestVersion AQ_Pma10GBaseT_TxPowerBackoffAndShortReachSetting_HHD +#define AQ_PmaReceiveReservedVendorProvisioning_BiggestVersion AQ_PmaReceiveReservedVendorProvisioning_HHD +#define AQ_PmaReceiveReservedVendorState_BiggestVersion AQ_PmaReceiveReservedVendorState_HHD +#define AQ_PmaReceiveVendorState_BiggestVersion AQ_PmaReceiveVendorState_HHD +#define AQ_PmaStandardControl_1_BiggestVersion AQ_PmaStandardControl_1_HHD +#define AQ_PmaStandardControl_2_BiggestVersion AQ_PmaStandardControl_2_HHD +#define AQ_PmaStandardDeviceIdentifier_BiggestVersion AQ_PmaStandardDeviceIdentifier_HHD +#define AQ_PmaStandardDevicesInPackage_BiggestVersion AQ_PmaStandardDevicesInPackage_HHD +#define AQ_PmaStandardPackageIdentifier_BiggestVersion AQ_PmaStandardPackageIdentifier_HHD +#define AQ_PmaStandardSpeedAbility_BiggestVersion AQ_PmaStandardSpeedAbility_HHD +#define AQ_PmaStandardStatus_1_BiggestVersion AQ_PmaStandardStatus_1_HHD +#define AQ_PmaStandardStatus_2_BiggestVersion AQ_PmaStandardStatus_2_HHD +#define AQ_PmaTransmitReservedVendorProvisioning_BiggestVersion AQ_PmaTransmitReservedVendorProvisioning_HHD +#define AQ_PmaTransmitStandardInterruptMask_BiggestVersion AQ_PmaTransmitStandardInterruptMask_HHD +#define AQ_PmaTransmitVendorAlarms_BiggestVersion AQ_PmaTransmitVendorAlarms_HHD +#define AQ_PmaTransmitVendorDebug_BiggestVersion AQ_PmaTransmitVendorDebug_HHD +#define AQ_PmaTransmitVendorLASI_InterruptMask_BiggestVersion AQ_PmaTransmitVendorLASI_InterruptMask_HHD +#define AQ_PmaVendorGlobalInterruptFlags_BiggestVersion AQ_PmaVendorGlobalInterruptFlags_HHD +#define AQ_PmdStandard10G_ExtendedAbilityRegister_BiggestVersion AQ_PmdStandard10G_ExtendedAbilityRegister_HHD +#define AQ_PmdStandardSignalDetect_BiggestVersion AQ_PmdStandardSignalDetect_HHD +#define AQ_PmdStandardTransmitDisableControl_BiggestVersion AQ_PmdStandardTransmitDisableControl_HHD +#define AQ_Sgmii0WolStatus_BiggestVersion AQ_Sgmii0WolStatus_HHD +#define AQ_TimesyncPcsCapability_BiggestVersion AQ_TimesyncPcsCapability_HHD +#define AQ_TimesyncPcsReceivePathDataDelay_BiggestVersion AQ_TimesyncPcsReceivePathDataDelay_HHD +#define AQ_TimesyncPcsTransmitPathDataDelay_BiggestVersion AQ_TimesyncPcsTransmitPathDataDelay_HHD +#define AQ_TimesyncPhyXsCapability_BiggestVersion AQ_TimesyncPhyXsCapability_HHD +#define AQ_TimesyncPhyXsReceivePathDataDelay_BiggestVersion AQ_TimesyncPhyXsReceivePathDataDelay_HHD +#define AQ_TimesyncPhyXsTransmitPathDataDelay_BiggestVersion AQ_TimesyncPhyXsTransmitPathDataDelay_HHD +#define AQ_TimesyncPmaCapability_BiggestVersion AQ_TimesyncPmaCapability_HHD +#define AQ_TimesyncPmaReceivePathDataDelay_BiggestVersion AQ_TimesyncPmaReceivePathDataDelay_HHD +#define AQ_TimesyncPmaTransmitPathDataDelay_BiggestVersion AQ_TimesyncPmaTransmitPathDataDelay_HHD +#define AQ_XenpakBasic_ApsLoading_BiggestVersion AQ_XenpakBasic_ApsLoading_HHD +#define AQ_XenpakBasic_ApsVoltage_BiggestVersion AQ_XenpakBasic_ApsVoltage_HHD +#define AQ_XenpakBasic_BitRate_BiggestVersion AQ_XenpakBasic_BitRate_HHD +#define AQ_XenpakBasic_Checksum_BiggestVersion AQ_XenpakBasic_Checksum_HHD +#define AQ_XenpakBasic_ConnectorType_BiggestVersion AQ_XenpakBasic_ConnectorType_HHD +#define AQ_XenpakBasic_DomCapability_BiggestVersion AQ_XenpakBasic_DomCapability_HHD +#define AQ_XenpakBasic_Encoding_BiggestVersion AQ_XenpakBasic_Encoding_HHD +#define AQ_XenpakBasic_Low_powerStartupCapability_BiggestVersion AQ_XenpakBasic_Low_powerStartupCapability_HHD +#define AQ_XenpakBasic_PackageIdentifier_BiggestVersion AQ_XenpakBasic_PackageIdentifier_HHD +#define AQ_XenpakBasic_Protocol_BiggestVersion AQ_XenpakBasic_Protocol_HHD +#define AQ_XenpakBasic_Reserved_0x11_BiggestVersion AQ_XenpakBasic_Reserved_0x11_HHD +#define AQ_XenpakBasic_Reserved_0x19_BiggestVersion AQ_XenpakBasic_Reserved_0x19_HHD +#define AQ_XenpakBasic_Reserved_0x7c_BiggestVersion AQ_XenpakBasic_Reserved_0x7c_HHD +#define AQ_XenpakBasic_StandardsComplianceCodes_BiggestVersion AQ_XenpakBasic_StandardsComplianceCodes_HHD +#define AQ_XenpakBasic_TransceiverType_BiggestVersion AQ_XenpakBasic_TransceiverType_HHD +#define AQ_XenpakBasic_VendorDateCode_BiggestVersion AQ_XenpakBasic_VendorDateCode_HHD +#define AQ_XenpakBasic_VendorIdentifier_BiggestVersion AQ_XenpakBasic_VendorIdentifier_HHD +#define AQ_XenpakBasic_VendorName_BiggestVersion AQ_XenpakBasic_VendorName_HHD +#define AQ_XenpakBasic_VendorPartNumber_BiggestVersion AQ_XenpakBasic_VendorPartNumber_HHD +#define AQ_XenpakBasic_VendorPartRevisionNumber_BiggestVersion AQ_XenpakBasic_VendorPartRevisionNumber_HHD +#define AQ_XenpakBasic_VendorSerialNumber_BiggestVersion AQ_XenpakBasic_VendorSerialNumber_HHD +#define AQ_XenpakBasic__3_3vLoading_BiggestVersion AQ_XenpakBasic__3_3vLoading_HHD +#define AQ_XenpakBasic__5vLoading_BiggestVersion AQ_XenpakBasic__5vLoading_HHD +#define AQ_XenpakControl_BiggestVersion AQ_XenpakControl_HHD +#define AQ_XenpakCustomer_Reserved_0x7e_BiggestVersion AQ_XenpakCustomer_Reserved_0x7e_HHD +#define AQ_XenpakDom_Alarms_BiggestVersion AQ_XenpakDom_Alarms_HHD +#define AQ_XenpakDom_Capability_BiggestVersion AQ_XenpakDom_Capability_HHD +#define AQ_XenpakDom_ControlAndStatus_BiggestVersion AQ_XenpakDom_ControlAndStatus_HHD +#define AQ_XenpakDom_HighTemperatureAlarmThresholdLSW_BiggestVersion AQ_XenpakDom_HighTemperatureAlarmThresholdLSW_HHD +#define AQ_XenpakDom_HighTemperatureAlarmThresholdMSW_BiggestVersion AQ_XenpakDom_HighTemperatureAlarmThresholdMSW_HHD +#define AQ_XenpakDom_HighTemperatureWarningThresholdLSW_BiggestVersion AQ_XenpakDom_HighTemperatureWarningThresholdLSW_HHD +#define AQ_XenpakDom_HighTemperatureWarningThresholdMSW_BiggestVersion AQ_XenpakDom_HighTemperatureWarningThresholdMSW_HHD +#define AQ_XenpakDom_LowTemperatureAlarmThresholdLSW_BiggestVersion AQ_XenpakDom_LowTemperatureAlarmThresholdLSW_HHD +#define AQ_XenpakDom_LowTemperatureAlarmThresholdMSW_BiggestVersion AQ_XenpakDom_LowTemperatureAlarmThresholdMSW_HHD +#define AQ_XenpakDom_LowTemperatureWarningThresholdLSW_BiggestVersion AQ_XenpakDom_LowTemperatureWarningThresholdLSW_HHD +#define AQ_XenpakDom_LowTemperatureWarningThresholdMSW_BiggestVersion AQ_XenpakDom_LowTemperatureWarningThresholdMSW_HHD +#define AQ_XenpakDom_Status_BiggestVersion AQ_XenpakDom_Status_HHD +#define AQ_XenpakDom_TemperatureLSW_BiggestVersion AQ_XenpakDom_TemperatureLSW_HHD +#define AQ_XenpakDom_TemperatureMSW_BiggestVersion AQ_XenpakDom_TemperatureMSW_HHD +#define AQ_XenpakDom_TxControl_BiggestVersion AQ_XenpakDom_TxControl_HHD +#define AQ_XenpakHeader_BasicMemoryStartAddress_BiggestVersion AQ_XenpakHeader_BasicMemoryStartAddress_HHD +#define AQ_XenpakHeader_CustomerMemoryOffset_BiggestVersion AQ_XenpakHeader_CustomerMemoryOffset_HHD +#define AQ_XenpakHeader_ExtendedVendorMemoryOffset_BiggestVersion AQ_XenpakHeader_ExtendedVendorMemoryOffset_HHD +#define AQ_XenpakHeader_MemoryUsed_BiggestVersion AQ_XenpakHeader_MemoryUsed_HHD +#define AQ_XenpakHeader_NvrSize_BiggestVersion AQ_XenpakHeader_NvrSize_HHD +#define AQ_XenpakHeader_VendorMemoryStartAddress_BiggestVersion AQ_XenpakHeader_VendorMemoryStartAddress_HHD +#define AQ_XenpakHeader_XenpakMsaVersionSupported_BiggestVersion AQ_XenpakHeader_XenpakMsaVersionSupported_HHD +#define AQ_XenpakLASI__Control_BiggestVersion AQ_XenpakLASI__Control_HHD +#define AQ_XenpakLASI__Status_BiggestVersion AQ_XenpakLASI__Status_HHD +#define AQ_XenpakRxAlarm_Control_BiggestVersion AQ_XenpakRxAlarm_Control_HHD +#define AQ_XenpakRxAlarm_Status_BiggestVersion AQ_XenpakRxAlarm_Status_HHD +#define AQ_XenpakTxAlarm_Control_BiggestVersion AQ_XenpakTxAlarm_Control_HHD +#define AQ_XenpakTxAlarm_Status_BiggestVersion AQ_XenpakTxAlarm_Status_HHD +#define AQ_XenpakVendor_Reserved_0xae_BiggestVersion AQ_XenpakVendor_Reserved_0xae_HHD + +#endif diff --git a/qca/aq-fw-download/src/include/registerMap/AQ_RegMaps.h b/qca/aq-fw-download/src/include/registerMap/AQ_RegMaps.h new file mode 100644 index 000000000..52a24e385 --- /dev/null +++ b/qca/aq-fw-download/src/include/registerMap/AQ_RegMaps.h @@ -0,0 +1,69 @@ +/*AQ_RegMaps.h*/ + +/************************************************************************************ +* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +* +* Description: +* +* This file contains includes all appropriate Aquantia PHY device-specific +* register map headers. +* +************************************************************************************/ + +/*! \file +* This file contains includes all appropriate Aquantia PHY device-specific +* register map headers. + */ + +#ifndef AQ_REGISTERMAPS_HEADER +#define AQ_REGISTERMAPS_HEADER + +#include "AQ_User.h" +#include "AQ_RegGroupMaxSizes.h" + + +#ifndef AQ_REVERSED_BITFIELD_ORDERING +/* + * Include non-reversed header files (bitfields ordered from LSbit to MSbit) + */ + +/* APPIA */ +#include "AQ_APPIA_Global_registers.h" + +#include "AQ_APPIA_Global_registers_Defines.h" + +/* HHD */ +#include "AQ_HHD_Global_registers.h" + +#include "AQ_HHD_Global_registers_Defines.h" + +#else +/* + * Include reversed header files (bitfields ordered from MSbit to LSbit) + */ + +/* APPIA */ +#include "AQ_APPIA_Global_registers_reversed.h" + +#include "AQ_APPIA_Global_registers_Defines.h" + +/* HHD */ +#include "AQ_HHD_Global_registers_reversed.h" + +#include "AQ_HHD_Global_registers_Defines.h" + +#endif + +#endif diff --git a/qca/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers.h b/qca/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers.h new file mode 100644 index 000000000..e0a2fa27b --- /dev/null +++ b/qca/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers.h @@ -0,0 +1,12123 @@ +/*! \file +* This file contains the data structures and doxygen comments +* for the Global Registers block. + */ + +/*! \addtogroup registerMap + @{ +*/ + +/*! \defgroup Global_registers Global Registers +* This module contains the data structures and doxygen comments +* for the Global Registers block. + */ +/*********************************************************************** +* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +* +* $Date: 2014/04/08 $ +* +* $Label: $ +* +* Description: +* +* This file contains the c header structures for the registers contained in the Global Registers block. +* +* The bit fields in this structure are from LSbit to MSbit +* +***********************************************************************/ + + +/*@{*/ +#ifndef AQ_HHD_GLOBAL_REGS_HEADER +#define AQ_HHD_GLOBAL_REGS_HEADER + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Control 1: 1E.0000 */ +/* Global Standard Control 1: 1E.0000 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Control 1 */ + union + { + struct + { + unsigned int reserved1 : 11; + /*! \brief 1E.0000.B R/WPD Low Power + AQ_GlobalStandardControl_1_HHD.u0.bits_0.lowPower + + Provisionable Default = 0x0 + + 1 = Low-power mode + 0 = Normal operation + + + Notes: + A one written to this register causes the chip to enter low-power mode. This bit puts the entire chip in low-power mode, with only the MDIO and microprocessor functioning, and turns off the analog front-end: i.e. places it in high-impedance mode. Setting this bit also sets all of the Low Power bits in the other MMDs. */ + unsigned int lowPower : 1; /* 1E.0000.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Low-power mode + 0 = Normal operation + */ + unsigned int reserved0 : 3; + /*! \brief 1E.0000.F R/WSC Soft Reset + AQ_GlobalStandardControl_1_HHD.u0.bits_0.softReset + + Default = 0x1 + + 1 = Global soft reset + 0 = Normal operation + + + Notes: + Resets the entire PHY. + Setting this bit initiates a global soft reset on all of the digital logic not including the microprocessor (i.e. microprocessor is not reset). Upon completion of the reset sequence, this bit is set back to 0by the microprocessor. Note this bit is OR'ed with the individual MMD resets. This bit should be set to 0 before setting the individual MMD resets. */ + unsigned int softReset : 1; /* 1E.0000.F R/WSC Default = 0x1 */ + /* 1 = Global soft reset + 0 = Normal operation + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardControl_1_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Device Identifier: 1E.0002 */ +/* Global Standard Device Identifier: 1E.0002 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Device Identifier */ + union + { + struct + { + /*! \brief 1E.0002.F:0 RO Device ID MSW [1F:10] + AQ_GlobalStandardDeviceIdentifier_HHD.u0.bits_0.deviceIdMSW + + + + Bits 31 - 16 of Device ID + */ + unsigned int deviceIdMSW : 16; /* 1E.0002.F:0 RO */ + /* Bits 31 - 16 of Device ID */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Standard Device Identifier */ + union + { + struct + { + /*! \brief 1E.0003.F:0 RO Device ID LSW [F:0] + AQ_GlobalStandardDeviceIdentifier_HHD.u1.bits_1.deviceIdLSW + + + + Bits 15 - 0 of Device ID + */ + unsigned int deviceIdLSW : 16; /* 1E.0003.F:0 RO */ + /* Bits 15 - 0 of Device ID */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalStandardDeviceIdentifier_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Devices in Package: 1E.0005 */ +/* Global Standard Devices in Package: 1E.0005 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Devices in Package */ + union + { + struct + { + /*! \brief 1E.0005.0 ROS Clause 22 Registers Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.clause_22RegistersPresent + + Default = 0x0 + + 1 = Clause 22 registers are present in package + 0 = Clause 22 registers are not present in package + + Notes: + This is always set to 0 in the PHY, as there are no Clause 22 registers in the device. */ + unsigned int clause_22RegistersPresent : 1; /* 1E.0005.0 ROS Default = 0x0 */ + /* 1 = Clause 22 registers are present in package + 0 = Clause 22 registers are not present in package */ + /*! \brief 1E.0005.1 ROS PMA Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.pmaPresent + + Default = 0x1 + + 1 = PMA is present in package + 0 = PMA is not present + + Notes: + This is always set to 1 as there is PMA functionality in the PHY. */ + unsigned int pmaPresent : 1; /* 1E.0005.1 ROS Default = 0x1 */ + /* 1 = PMA is present in package + 0 = PMA is not present */ + /*! \brief 1E.0005.2 ROS WIS Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.wisPresent + + Default = 0x0 + + 1 = WIS is present in package + 0 = WIS is not present in package + + Notes: + This is always set to 0, as there is no WIS functionality in the PHY. */ + unsigned int wisPresent : 1; /* 1E.0005.2 ROS Default = 0x0 */ + /* 1 = WIS is present in package + 0 = WIS is not present in package */ + /*! \brief 1E.0005.3 ROS PCS Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.pcsPresent + + Default = 0x1 + + 1 = PCS is present in package + 0 = PCS is not present in package + + Notes: + This is always set to 1 as there is PCS functionality in the PHY. */ + unsigned int pcsPresent : 1; /* 1E.0005.3 ROS Default = 0x1 */ + /* 1 = PCS is present in package + 0 = PCS is not present in package */ + /*! \brief 1E.0005.4 ROS PHY XS Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.phyXS_Present + + Default = 0x1 + + 1 = PHY XS is present in package + 0 = PHY XS is not present in package + + Notes: + This is always set to 1 as there is a PHY XS interface in the PHY. */ + unsigned int phyXS_Present : 1; /* 1E.0005.4 ROS Default = 0x1 */ + /* 1 = PHY XS is present in package + 0 = PHY XS is not present in package */ + /*! \brief 1E.0005.5 ROS DTE XS Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.dteXsPresent + + Default = 0x0 + + 1 = DTE XS is present in package + 0 = DTE XS is not present in package + + + Notes: + This is always set to 0, as there is no DTE XAUI interface in the PHY. */ + unsigned int dteXsPresent : 1; /* 1E.0005.5 ROS Default = 0x0 */ + /* 1 = DTE XS is present in package + 0 = DTE XS is not present in package + */ + /*! \brief 1E.0005.6 ROS TC Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.tcPresent + + Default = 0x0 + + 1 = TC is present in package + 0 = TC is not present in package + + Notes: + This is always set to 0, as there is no TC functionality in the PHY. */ + unsigned int tcPresent : 1; /* 1E.0005.6 ROS Default = 0x0 */ + /* 1 = TC is present in package + 0 = TC is not present in package */ + /*! \brief 1E.0005.7 ROS Autonegotiation Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.autonegotiationPresent + + Default = 0x1 + + 1 = Autonegotiation is present in package + 0 = Autonegotiation is not present in package + + Notes: + This is always set to 1, as there is Autonegotiation in the PHY. */ + unsigned int autonegotiationPresent : 1; /* 1E.0005.7 ROS Default = 0x1 */ + /* 1 = Autonegotiation is present in package + 0 = Autonegotiation is not present in package */ + unsigned int reserved0 : 8; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardDevicesInPackage_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Vendor Devices in Package: 1E.0006 */ +/* Global Standard Vendor Devices in Package: 1E.0006 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Vendor Devices in Package */ + union + { + struct + { + unsigned int reserved0 : 13; + /*! \brief 1E.0006.D ROS Clause 22 Extension Present + AQ_GlobalStandardVendorDevicesInPackage_HHD.u0.bits_0.clause_22ExtensionPresent + + Default = 0x1 + + 1 = Clause 22 Extension is present in package + 0 = Clause 22 Extension is not present in package + + Notes: + This is always set to 1 as the PHY utilizes this device for the GbE registers. */ + unsigned int clause_22ExtensionPresent : 1; /* 1E.0006.D ROS Default = 0x1 */ + /* 1 = Clause 22 Extension is present in package + 0 = Clause 22 Extension is not present in package */ + /*! \brief 1E.0006.E ROS Vendor Specific Device #1 Present + AQ_GlobalStandardVendorDevicesInPackage_HHD.u0.bits_0.vendorSpecificDevice_1Present + + Default = 0x1 + + 1 = Device #1 is present in package + 0 = Device #1 is not present in package + + Notes: + This is always set to 1 as the PHY utilizes this device for the global control registers. */ + unsigned int vendorSpecificDevice_1Present : 1; /* 1E.0006.E ROS Default = 0x1 */ + /* 1 = Device #1 is present in package + 0 = Device #1 is not present in package */ + /*! \brief 1E.0006.F ROS Vendor Specific Device #2 Present + AQ_GlobalStandardVendorDevicesInPackage_HHD.u0.bits_0.vendorSpecificDevice_2Present + + Default = 0x1 + + 1 = Device #2 is present in package + 0 = Device #2 is not present in package + + Notes: + This is always set to 1 as the PHY utilizes this device for the DSP PMA registers. */ + unsigned int vendorSpecificDevice_2Present : 1; /* 1E.0006.F ROS Default = 0x1 */ + /* 1 = Device #2 is present in package + 0 = Device #2 is not present in package */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardVendorDevicesInPackage_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Status 2: 1E.0008 */ +/* Global Standard Status 2: 1E.0008 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Status 2 */ + union + { + struct + { + unsigned int reserved0 : 14; + /*! \brief 1E.0008.F:E ROS Device Present [1:0] + AQ_GlobalStandardStatus_2_HHD.u0.bits_0.devicePresent + + Default = 0x2 + + [F:E] + 0x3 = No device at this address + 0x2 = Device present at this address + 0x1 = No device at this address + 0x0 = No device at this address + + Notes: + This field is always set to 0x2, as the Global MMD resides here in the PHY. */ + unsigned int devicePresent : 2; /* 1E.0008.F:E ROS Default = 0x2 */ + /* [F:E] + 0x3 = No device at this address + 0x2 = Device present at this address + 0x1 = No device at this address + 0x0 = No device at this address */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardStatus_2_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Package Identifier: 1E.000E */ +/* Global Standard Package Identifier: 1E.000E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Package Identifier */ + union + { + struct + { + /*! \brief 1E.000E.F:0 RO Package ID MSW [1F:10] + AQ_GlobalStandardPackageIdentifier_HHD.u0.bits_0.packageIdMSW + + + + Bits 31- 16 of Package ID + */ + unsigned int packageIdMSW : 16; /* 1E.000E.F:0 RO */ + /* Bits 31- 16 of Package ID */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Standard Package Identifier */ + union + { + struct + { + /*! \brief 1E.000F.F:0 RO Package ID LSW [F:0] + AQ_GlobalStandardPackageIdentifier_HHD.u1.bits_1.packageIdLSW + + + + Bits 15 - 0 of Package ID + */ + unsigned int packageIdLSW : 16; /* 1E.000F.F:0 RO */ + /* Bits 15 - 0 of Package ID */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalStandardPackageIdentifier_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Firmware ID: 1E.0020 */ +/* Global Firmware ID: 1E.0020 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Firmware ID */ + union + { + struct + { + /*! \brief 1E.0020.7:0 RO Firmware Minor Revision Number [7:0] + AQ_GlobalFirmwareID_HHD.u0.bits_0.firmwareMinorRevisionNumber + + + + [7:0] = Minor revision number + + Notes: + + + The lower six bits of major and minor firmware revision are exchanged in autonegotiation when the PHYID message is sent. */ + unsigned int firmwareMinorRevisionNumber : 8; /* 1E.0020.7:0 RO */ + /* [7:0] = Minor revision number */ + /*! \brief 1E.0020.F:8 RO Firmware Major Revision Number [7:0] + AQ_GlobalFirmwareID_HHD.u0.bits_0.firmwareMajorRevisionNumber + + + + [F:8] = Major revision number + + Notes: + + + The lower six bits of major and minor firmware revision are exchanged in autonegotiation when the PHYID message is sent. */ + unsigned int firmwareMajorRevisionNumber : 8; /* 1E.0020.F:8 RO */ + /* [F:8] = Major revision number */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalFirmwareID_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global NVR Interface: 1E.0100 */ +/* Global NVR Interface: 1E.0100 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0100.7:0 R/W NVR Opcode [7:0] + AQ_GlobalNvrInterface_HHD.u0.bits_0.nvrOpcode + + Default = 0x03 + + NVR instruction opcode + + */ + unsigned int nvrOpcode : 8; /* 1E.0100.7:0 R/W Default = 0x03 */ + /* NVR instruction opcode + */ + /*! \brief 1E.0100.8 RO NVR Busy + AQ_GlobalNvrInterface_HHD.u0.bits_0.nvrBusy + + + + 1 = NVR is busy + 0 = NVR is ready + + + Notes: + When set to 1, the NVR is busy. A new NVR operation should not occur until this bit is 0. If the NVR clock is greater than 64/63 of the MDIO clock, this bit never needs to be polled when operating over the MDIO. */ + unsigned int nvrBusy : 1; /* 1E.0100.8 RO */ + /* 1 = NVR is busy + 0 = NVR is ready + */ + unsigned int reserved1 : 1; + /*! \brief 1E.0100.A R/W NVR Burst + AQ_GlobalNvrInterface_HHD.u0.bits_0.nvrBurst + + Default = 0x0 + + 0 = Single read or write operation of up to 4 bytes + 1 = Burst operation + + + Notes: + When this bit is set, the operation is a burst operation where more than 32-bits is read from the NVR or written to the NVR. This bit should be set to one until the last burst in the read or write operation, when it should be set to zero. It operates by gating the SPI clock, and not restarting it until new data is ready to be written, or the previous contents have been read. Each burst of data requires the NVR Execute Operation bit to be set to initiate the next phase. */ + unsigned int nvrBurst : 1; /* 1E.0100.A R/W Default = 0x0 */ + /* 0 = Single read or write operation of up to 4 bytes + 1 = Burst operation + */ + unsigned int reserved0 : 1; + /*! \brief 1E.0100.C R/WSC Reset NVR CRC + AQ_GlobalNvrInterface_HHD.u0.bits_0.resetNvrCrc + + Default = 0x0 + + 1 = Reset NVR Mailbox CRC calculation register + + + + Notes: + To prevent an erroneous answer, this bit should not be set at the same time the See NVR Operation Valid bit is set. */ + unsigned int resetNvrCrc : 1; /* 1E.0100.C R/WSC Default = 0x0 */ + /* 1 = Reset NVR Mailbox CRC calculation register + + */ + /*! \brief 1E.0100.D R/W Freeze NVR CRC + AQ_GlobalNvrInterface_HHD.u0.bits_0.freezeNvrCrc + + Default = 0x0 + + 1 = Freeze NVR Mailbox CRC calculation register + + + Notes: + To prevent an erroneous answer, this bit should not be set at the same time the See NVR Operation Valid bit is set. */ + unsigned int freezeNvrCrc : 1; /* 1E.0100.D R/W Default = 0x0 */ + /* 1 = Freeze NVR Mailbox CRC calculation register + */ + /*! \brief 1E.0100.E R/W NVR Write Mode + AQ_GlobalNvrInterface_HHD.u0.bits_0.nvrWriteMode + + Default = 0x0 + + 1 = Write to NVR + 0 = Read from NVR + + */ + unsigned int nvrWriteMode : 1; /* 1E.0100.E R/W Default = 0x0 */ + /* 1 = Write to NVR + 0 = Read from NVR + */ + /*! \brief 1E.0100.F R/WSC NVR Execute Operation + AQ_GlobalNvrInterface_HHD.u0.bits_0.nvrExecuteOperation + + Default = 0x0 + + 1 = Start NVR Operation + + + + Notes: + When set to 1, the NVR operation will begin. Ensure that the uP is stalled using the See MCP Run Stall bit to ensure no NVR contention. */ + unsigned int nvrExecuteOperation : 1; /* 1E.0100.F R/WSC Default = 0x0 */ + /* 1 = Start NVR Operation + + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0101.F:0 RO NVR Mailbox CRC [F:0] + AQ_GlobalNvrInterface_HHD.u1.bits_1.nvrMailboxCrc + + + + The running CRC-16 of everything passing through the NVR interface + + + Notes: + The CRC-16 over all data written or read through the NVR interface. The CRC-16 is calculated by dividing the data by: + x^16 + x^12 + x^5 + 1 */ + unsigned int nvrMailboxCrc : 16; /* 1E.0101.F:0 RO */ + /* The running CRC-16 of everything passing through the NVR interface + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0102.7:0 R/W NVR Address MSW [17:10] + AQ_GlobalNvrInterface_HHD.u2.bits_2.nvrAddressMSW + + Default = 0x00 + + NVR address MSW bits [17:10] + + + Notes: + The address of where to read and write from in the NVR. This is self-incrementing and will automatically increment after each read or write operation. The increment amount is based on the data length (i.e. increments by 4 if the data length is 4 bytes) */ + unsigned int nvrAddressMSW : 8; /* 1E.0102.7:0 R/W Default = 0x00 */ + /* NVR address MSW bits [17:10] + */ + unsigned int reserved0 : 8; + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0103.F:0 R/W NVR Address LSW [F:0] + AQ_GlobalNvrInterface_HHD.u3.bits_3.nvrAddressLSW + + Default = 0x0000 + + NVR address LSW bits [F:0] + + + Notes: + The address of where to read and write from in the NVR. This is self-incrementing and will automatically increment after each read or write operation. */ + unsigned int nvrAddressLSW : 16; /* 1E.0103.F:0 R/W Default = 0x0000 */ + /* NVR address LSW bits [F:0] + */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0104.F:0 R/W NVR Data MSW [1F:10] + AQ_GlobalNvrInterface_HHD.u4.bits_4.nvrDataMSW + + Default = 0x0000 + + NVR data MSW bits [1F:10] + + + Notes: + Data is stored and read-out from these registers in little-endian format for operations such as FLASH device ID, and for programming the processor. + + For instance the 64K Atmel device code reads out as two bytes 0x651F into the LSW register, whereas the datasheet indicates that 1F is the first byte read, followed by 65 as the second byte. + + To burst read and write these 4 bytes in the correct order (where DD is written to address x), they should be stored as: + + AA BB in the MSW + CC DD in the LSW. */ + unsigned int nvrDataMSW : 16; /* 1E.0104.F:0 R/W Default = 0x0000 */ + /* NVR data MSW bits [1F:10] + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0105.F:0 R/W NVR Data LSW [F:0] + AQ_GlobalNvrInterface_HHD.u5.bits_5.nvrDataLSW + + Default = 0x0000 + + NVR data LSW bits [F:0] + + + Notes: + Data is stored and read-out from these registers in little-endian format for operations such as FLASH device ID, and for programming the processor. + + For instance the 64K Atmel device code reads out as two bytes 0x651F into the LSW register, whereas the datasheet indicates that 1F is the first byte read, followed by 65 as the second byte. + To burst read and write these 4 bytes in the correct order (where DD is written to address x), they should be stored as: + + AA BB in the MSW + CC DD in the LSW. */ + unsigned int nvrDataLSW : 16; /* 1E.0105.F:0 R/W Default = 0x0000 */ + /* NVR data LSW bits [F:0] + */ + } bits_5; + uint16_t word_5; + } u5; +} AQ_GlobalNvrInterface_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Mailbox Interface: 1E.0200 */ +/* Global Mailbox Interface: 1E.0200 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Mailbox Interface */ + union + { + struct + { + unsigned int reserved2 : 8; + /*! \brief 1E.0200.8 RO uP Mailbox Busy + AQ_GlobalMailboxInterface_HHD.u0.bits_0.upMailboxBusy + + + + 1 = uP mailbox busy + 0 = uP mailbox ready + + + Notes: + In general the uP will respond within a few processor cycles to any PIF slave request, much faster than the MDIO. If the busy is asserted over multiple MDIO polling cycles, then a H/W error may have occurred and a Global S/W reset or uP reset is required. */ + unsigned int upMailboxBusy : 1; /* 1E.0200.8 RO */ + /* 1 = uP mailbox busy + 0 = uP mailbox ready + */ + unsigned int reserved1 : 3; + /*! \brief 1E.0200.C R/WSC Reset uP Mailbox CRC + AQ_GlobalMailboxInterface_HHD.u0.bits_0.resetUpMailboxCrc + + Default = 0x0 + + 1 = Reset uP mailbox CRC calculation register + + + */ + unsigned int resetUpMailboxCrc : 1; /* 1E.0200.C R/WSC Default = 0x0 */ + /* 1 = Reset uP mailbox CRC calculation register + + */ + unsigned int reserved0 : 1; + /*! \brief 1E.0200.E R/W uP Mailbox Write Mode + AQ_GlobalMailboxInterface_HHD.u0.bits_0.upMailboxWriteMode + + Default = 0x0 + + 1 = Write + 0 = Read + + + Notes: + Mailbox direction */ + unsigned int upMailboxWriteMode : 1; /* 1E.0200.E R/W Default = 0x0 */ + /* 1 = Write + 0 = Read + */ + /*! \brief 1E.0200.F R/WSC uP Mailbox Execute Operation + AQ_GlobalMailboxInterface_HHD.u0.bits_0.upMailboxExecuteOperation + + Default = 0x0 + + 1 = Start of mailbox Operation + + + + Notes: + Indicates mailbox is loaded and ready */ + unsigned int upMailboxExecuteOperation : 1; /* 1E.0200.F R/WSC Default = 0x0 */ + /* 1 = Start of mailbox Operation + + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0201.F:0 RO uP Mailbox CRC [F:0] + AQ_GlobalMailboxInterface_HHD.u1.bits_1.upMailboxCrc + + + + The running CRC-16 of everything passing through the mailbox interface + + */ + unsigned int upMailboxCrc : 16; /* 1E.0201.F:0 RO */ + /* The running CRC-16 of everything passing through the mailbox interface + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0202.F:0 R/W uP Mailbox Address MSW [1F:10] + AQ_GlobalMailboxInterface_HHD.u2.bits_2.upMailboxAddressMSW + + Default = 0x0000 + + uP Mailbox MSW address + + + Notes: + The address of where to read and write from in the Microcontroller Mailbox. This is self-incrementing and automatically increments after each read and write operation.PHY */ + unsigned int upMailboxAddressMSW : 16; /* 1E.0202.F:0 R/W Default = 0x0000 */ + /* uP Mailbox MSW address + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0203.1:0 RO uP Mailbox Address LSW Don't Care [1:0] + AQ_GlobalMailboxInterface_HHD.u3.bits_3.upMailboxAddressLSW_Don_tCare + + + + Least significant uP LSW Mailbox address bits [1:0] + + + Notes: + These bits are always set to 0 since each memory access is on a 4-byte boundary. */ + unsigned int upMailboxAddressLSW_Don_tCare : 2; /* 1E.0203.1:0 RO */ + /* Least significant uP LSW Mailbox address bits [1:0] + */ + /*! \brief 1E.0203.F:2 R/W uP Mailbox Address LSW [F:2] + AQ_GlobalMailboxInterface_HHD.u3.bits_3.upMailboxAddressLSW + + Default = 0x0000 + + uP LSW Mailbox address [F:2] + + + Notes: + The address of where to read and write from in the Microcontroller Mailbox. This is self-incrementing and automatically increments after each read and write operation.PHY */ + unsigned int upMailboxAddressLSW : 14; /* 1E.0203.F:2 R/W Default = 0x0000 */ + /* uP LSW Mailbox address [F:2] + */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0204.F:0 R/W uP Mailbox Data MSW [1F:10] + AQ_GlobalMailboxInterface_HHD.u4.bits_4.upMailboxDataMSW + + Default = 0x0000 + + uP Mailbox data MSW + + */ + unsigned int upMailboxDataMSW : 16; /* 1E.0204.F:0 R/W Default = 0x0000 */ + /* uP Mailbox data MSW + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0205.F:0 R/W uP Mailbox Data LSW [F:0] + AQ_GlobalMailboxInterface_HHD.u5.bits_5.upMailboxDataLSW + + Default = 0x0000 + + uP Mailbox data LSW + + */ + unsigned int upMailboxDataLSW : 16; /* 1E.0205.F:0 R/W Default = 0x0000 */ + /* uP Mailbox data LSW + */ + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of Global Mailbox Interface */ + union + { + struct + { + unsigned int reserved1 : 1; + /*! \brief 1E.0206.1 R/W uP Mailbox CRC Read Enable + AQ_GlobalMailboxInterface_HHD.u6.bits_6.upMailboxCrcReadEnable + + Default = 0x0 + + 1 = Update uP mailbox CRC on read + + */ + unsigned int upMailboxCrcReadEnable : 1; /* 1E.0206.1 R/W Default = 0x0 */ + /* 1 = Update uP mailbox CRC on read + */ + unsigned int reserved0 : 14; + } bits_6; + uint16_t word_6; + } u6; +} AQ_GlobalMailboxInterface_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Microprocessor Scratch Pad: 1E.0300 */ +/* Global Microprocessor Scratch Pad: 1E.0300 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Microprocessor Scratch Pad */ + union + { + struct + { + /*! \brief 1E.0300.F:0 R/W Scratch Pad 1[F:0] + AQ_GlobalMicroprocessorScratchPad_HHD.u0.bits_0.scratchPad_1 + + Default = 0x0000 + + General Purpose Scratch Pad + */ + unsigned int scratchPad_1 : 16; /* 1E.0300.F:0 R/W Default = 0x0000 */ + /* General Purpose Scratch Pad */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Microprocessor Scratch Pad */ + union + { + struct + { + /*! \brief 1E.0301.F:0 R/W Scratch Pad 2 [F:0] + AQ_GlobalMicroprocessorScratchPad_HHD.u1.bits_1.scratchPad_2 + + Default = 0x0000 + + General Purpose Scratch Pad + */ + unsigned int scratchPad_2 : 16; /* 1E.0301.F:0 R/W Default = 0x0000 */ + /* General Purpose Scratch Pad */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalMicroprocessorScratchPad_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress Control Register: 1E.5002 */ +/* MSS Egress Control Register: 1E.5002 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress Control Register */ + union + { + struct + { + /*! \brief 1E.5002.0 R/W MSS Egress Soft Reset + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressSoftReset + + Default = 0x0 + + 1 = Soft reset + + + Notes: + S/W reset */ + unsigned int mssEgressSoftReset : 1; /* 1E.5002.0 R/W Default = 0x0 */ + /* 1 = Soft reset + */ + /*! \brief 1E.5002.1 R/W MSS Egress Drop KAY Packet + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressDropKayPacket + + Default = 0x0 + + 1 = Drop KAY packet + + + Notes: + Decides whether KAY packets have to be dropped */ + unsigned int mssEgressDropKayPacket : 1; /* 1E.5002.1 R/W Default = 0x0 */ + /* 1 = Drop KAY packet + */ + /*! \brief 1E.5002.2 R/W MSS Egress Drop EGPRC LUT Miss + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressDropEgprcLutMiss + + Default = 0x0 + + 1 = Drop Egress Classification LUT miss packets + + + + Notes: + Decides whether Egress Pre-Security Classification (EGPRC) LUT miss packets are to be dropped */ + unsigned int mssEgressDropEgprcLutMiss : 1; /* 1E.5002.2 R/W Default = 0x0 */ + /* 1 = Drop Egress Classification LUT miss packets + + */ + /*! \brief 1E.5002.3 R/W MSS Egress GCM Start + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressGcmStart + + Default = 0x0 + + 1 = Start GCM + + + + Notes: + Indicates GCM to start */ + unsigned int mssEgressGcmStart : 1; /* 1E.5002.3 R/W Default = 0x0 */ + /* 1 = Start GCM + + */ + /*! \brief 1E.5002.4 R/W MSS Egresss GCM Test Mode + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgresssGcmTestMode + + Default = 0x0 + + 1 = Enable GCM test mode + + + + Notes: + Enables GCM test mode */ + unsigned int mssEgresssGcmTestMode : 1; /* 1E.5002.4 R/W Default = 0x0 */ + /* 1 = Enable GCM test mode + + */ + /*! \brief 1E.5002.5 R/W MSS Egress Unmatched Use SC 0 + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressUnmatchedUseSc_0 + + Default = 0x0 + + 1 = Use SC 0 for unmatched packets + 0 = Unmatched packets are uncontrolled packets + + + + Notes: + Use SC-Index 0 as default SC for unmatched packets. Otherwise the packets are treated as uncontrolled packets. */ + unsigned int mssEgressUnmatchedUseSc_0 : 1; /* 1E.5002.5 R/W Default = 0x0 */ + /* 1 = Use SC 0 for unmatched packets + 0 = Unmatched packets are uncontrolled packets + + */ + /*! \brief 1E.5002.6 R/W MSS Egress Drop Invalid SA/SC Packets + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressDropInvalidSa_scPackets + + Default = 0x0 + + 1 = Drop invalid SA/SC packets + + + + Notes: + Enables dropping of invalid SA/SC packets. */ + unsigned int mssEgressDropInvalidSa_scPackets : 1; /* 1E.5002.6 R/W Default = 0x0 */ + /* 1 = Drop invalid SA/SC packets + + */ + /*! \brief 1E.5002.7 R/W MSS Egress Explicit SECTag Report Short Length + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressExplicitSectagReportShortLength + + Default = 0x0 + + Reserved + + + + Notes: + Unused. */ + unsigned int mssEgressExplicitSectagReportShortLength : 1; /* 1E.5002.7 R/W Default = 0x0 */ + /* Reserved + + */ + /*! \brief 1E.5002.8 R/W MSS Egress External Classification Enable + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressExternalClassificationEnable + + Default = 0x0 + + 1 = Drop EGPRC miss packets + + + + Notes: + If set, internal classification is bypassed. Should always be set to 0. */ + unsigned int mssEgressExternalClassificationEnable : 1; /* 1E.5002.8 R/W Default = 0x0 */ + /* 1 = Drop EGPRC miss packets + + */ + /*! \brief 1E.5002.9 R/W MSS Egress ICV LSB 8 Bytes Enable + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressIcvLsb_8BytesEnable + + Default = 0x0 + + 1 = Use LSB + 0 = Use MSB + + + + Notes: + This bit selects MSB or LSB 8 bytes selection in the case where the ICV is 8 bytes. + 0 = MSB is used. */ + unsigned int mssEgressIcvLsb_8BytesEnable : 1; /* 1E.5002.9 R/W Default = 0x0 */ + /* 1 = Use LSB + 0 = Use MSB + + */ + /*! \brief 1E.5002.A R/W MSS Egress High Priority + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressHighPriority + + Default = 0x0 + + 1 = MIB counter clear on read enable + + + + Notes: + If this bit is set to 1, read is given high priority and the MIB count value becomes 0 after read. */ + unsigned int mssEgressHighPriority : 1; /* 1E.5002.A R/W Default = 0x0 */ + /* 1 = MIB counter clear on read enable + + */ + /*! \brief 1E.5002.B R/W MSS Egress Clear Counter + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressClearCounter + + Default = 0x0 + + 1 = Clear all MIB counters + + + + Notes: + If this bit is set to 1, all MIB counters will be cleared. */ + unsigned int mssEgressClearCounter : 1; /* 1E.5002.B R/W Default = 0x0 */ + /* 1 = Clear all MIB counters + + */ + /*! \brief 1E.5002.C R/W MSS Egress Clear Global Time + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressClearGlobalTime + + Default = 0x0 + + 1 = Clear global time + + + + Notes: + Clear global time. */ + unsigned int mssEgressClearGlobalTime : 1; /* 1E.5002.C R/W Default = 0x0 */ + /* 1 = Clear global time + + */ + /*! \brief 1E.5002.F:D R/W MSS Egress Ethertype Explicit SECTag LSB [2:0] + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressEthertypeExplicitSectagLsb + + Default = 0x0 + + Ethertype for explicit SECTag bits 2:0. + + + Notes: + Ethertype for explicity SECTag. */ + unsigned int mssEgressEthertypeExplicitSectagLsb : 3; /* 1E.5002.F:D R/W Default = 0x0 */ + /* Ethertype for explicit SECTag bits 2:0. + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress Control Register */ + union + { + struct + { + /*! \brief 1E.5003.C:0 R/W MSS Egress Ethertype Explicit SECTag MSB [F:3] + AQ_MssEgressControlRegister_HHD.u1.bits_1.mssEgressEthertypeExplicitSectagMsb + + Default = 0x0000 + + Ethertype for explicit SECTag bits 15:3. + + + Notes: + Ethertype for explicity SECTag. */ + unsigned int mssEgressEthertypeExplicitSectagMsb : 13; /* 1E.5003.C:0 R/W Default = 0x0000 */ + /* Ethertype for explicit SECTag bits 15:3. + */ + unsigned int reserved0 : 3; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress VLAN TPID 0 Register: 1E.5008 */ +/* MSS Egress VLAN TPID 0 Register: 1E.5008 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress VLAN TPID 0 Register */ + union + { + struct + { + /*! \brief 1E.5008.F:0 R/W MSS Egress VLAN STag TPID [F:0] + AQ_MssEgressVlanTpid_0Register_HHD.u0.bits_0.mssEgressVlanStagTpid + + Default = 0x0000 + + STag TPID + + + Notes: + Service Tag Protocol Identifier (TPID) values to identify a VLAN tag. The " See SEC Egress VLAN CP Tag Parse STag " bit must be set to 1 for the incoming packet's TPID to be parsed. */ + unsigned int mssEgressVlanStagTpid : 16; /* 1E.5008.F:0 R/W Default = 0x0000 */ + /* STag TPID + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress VLAN TPID 0 Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressVlanTpid_0Register_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress VLAN TPID 1 Register: 1E.500A */ +/* MSS Egress VLAN TPID 1 Register: 1E.500A */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress VLAN TPID 1 Register */ + union + { + struct + { + /*! \brief 1E.500A.F:0 R/W MSS Egress VLAN QTag TPID [F:0] + AQ_MssEgressVlanTpid_1Register_HHD.u0.bits_0.mssEgressVlanQtagTpid + + Default = 0x0000 + + QTag TPID + + + Notes: + Customer Tag Protocol Identifier (TPID) values to identify a VLAN tag. The " See SEC Egress VLAN CP Tag Parse QTag " bit must be set to 1 for the incoming packet's TPID to be parsed. */ + unsigned int mssEgressVlanQtagTpid : 16; /* 1E.500A.F:0 R/W Default = 0x0000 */ + /* QTag TPID + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress VLAN TPID 1 Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressVlanTpid_1Register_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress VLAN Control Register: 1E.500C */ +/* MSS Egress VLAN Control Register: 1E.500C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress VLAN Control Register */ + union + { + struct + { + /*! \brief 1E.500C.F:0 R/W MSS Egress VLAN UP Map Table [F:0] + AQ_MssEgressVlanControlRegister_HHD.u0.bits_0.mssEgressVlanUpMapTable + + Default = 0x0000 + + UP Map table bits 15:0 + + + Notes: + If there is a customer TPID Tag match and no service TPID Tag match or the service TPID Tag match is disabled, the outer TAG's PCP is used to index into this map table to generate the packets user priority. + 2:0 : UP value for customer Tag PCP 0x0 + 5:3: UP value for customer Tag PCP 0x0 + 8:6 : UP value for customer Tag PCP 0x0 + 11:9 : UP value for customer Tag PCP 0x0 + 14:12 : UP value for customer Tag PCP 0x0 + 17:15 : UP value for customer Tag PCP 0x0 + 20:18 : UP value for customer Tag PCP 0x0 + 23:21 : UP value for customer Tag PCP 0x0 */ + unsigned int mssEgressVlanUpMapTable : 16; /* 1E.500C.F:0 R/W Default = 0x0000 */ + /* UP Map table bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress VLAN Control Register */ + union + { + struct + { + /*! \brief 1E.500D.7:0 R/W MSS Egress VLAN UP Map Table MSW [17:10] + AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanUpMapTableMSW + + Default = 0x00 + + UP Map table bits 23:16 + + + Notes: + If there is a customer TPID Tag match and no service TPID Tag match or the service TPID Tag match is disabled, the outer TAG's PCP is used to index into this map table to generate the packets user priority. + 2:0 : UP value for customer Tag PCP 0x0 + 5:3: UP value for customer Tag PCP 0x0 + 8:6 : UP value for customer Tag PCP 0x0 + 11:9 : UP value for customer Tag PCP 0x0 + 14:12 : UP value for customer Tag PCP 0x0 + 17:15 : UP value for customer Tag PCP 0x0 + 20:18 : UP value for customer Tag PCP 0x0 + 23:21 : UP value for customer Tag PCP 0x0 */ + unsigned int mssEgressVlanUpMapTableMSW : 8; /* 1E.500D.7:0 R/W Default = 0x00 */ + /* UP Map table bits 23:16 + */ + /*! \brief 1E.500D.A:8 R/W MSS Egress VLAN UP Default [2:0] + AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanUpDefault + + Default = 0x0 + + UP default + + + Notes: + User priority default */ + unsigned int mssEgressVlanUpDefault : 3; /* 1E.500D.A:8 R/W Default = 0x0 */ + /* UP default + */ + /*! \brief 1E.500D.B R/W MSS Egress VLAN STag UP Parse Enable + AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanStagUpParseEnable + + Default = 0x0 + + VLAN CP Tag STag UP enable + + + Notes: + Enable controlled port service VLAN service Tag user priority field parsing. */ + unsigned int mssEgressVlanStagUpParseEnable : 1; /* 1E.500D.B R/W Default = 0x0 */ + /* VLAN CP Tag STag UP enable + */ + /*! \brief 1E.500D.C R/W MSS Egress VLAN QTag UP Parse Enable + AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanQtagUpParseEnable + + Default = 0x0 + + VLAN CP Tag QTag UP enable + + + Notes: + Enable controlled port customer VLAN customer Tag user priority field parsing. */ + unsigned int mssEgressVlanQtagUpParseEnable : 1; /* 1E.500D.C R/W Default = 0x0 */ + /* VLAN CP Tag QTag UP enable + */ + /*! \brief 1E.500D.D R/W MSS Egress VLAN QinQ Parse Enable + AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanQinqParseEnable + + Default = 0x0 + + VLAN CP Tag Parse QinQ + + + Notes: + Enable controlled port VLAN QinQ Tag parsing. When this bit is set to 1 both the outer and inner VLAN Tags will be parsed. */ + unsigned int mssEgressVlanQinqParseEnable : 1; /* 1E.500D.D R/W Default = 0x0 */ + /* VLAN CP Tag Parse QinQ + */ + /*! \brief 1E.500D.E R/W MSS Egress VLAN STag Parse Enable + AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanStagParseEnable + + Default = 0x0 + + 1 = Enable VLAN STag parsing + + + Notes: + Enable controlled port VLAN service Tag parsing. When this bit is set to 1, the incoming packets outer TPID will be compared with the configured " See SEC Egress TPID 0 [F:0] " for matching. If the " See SEC Egress VLAN CP Tag Parse QinQ " bit is set to1, this will also be used to compare the incoming packet's inner TPID. */ + unsigned int mssEgressVlanStagParseEnable : 1; /* 1E.500D.E R/W Default = 0x0 */ + /* 1 = Enable VLAN STag parsing + */ + /*! \brief 1E.500D.F R/W MSS Egress VLAN QTag Parse Enable + AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanQtagParseEnable + + Default = 0x0 + + 1 = Enable VLAN QTag parsing + + + Notes: + Enable controlled port VLAN customer Tag parsing. When this bit is set to 1, the incoming packet's outer TPID will be compared with the configured " See SEC Egress TPID 1 [F:0] " for matching. If the " See SEC Egress VLAN CP Tag Parse QinQ " bit is set to1, this will also be used to compare the incoming packet's inner TPID. */ + unsigned int mssEgressVlanQtagParseEnable : 1; /* 1E.500D.F R/W Default = 0x0 */ + /* 1 = Enable VLAN QTag parsing + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressVlanControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress PN Control Register: 1E.500E */ +/* MSS Egress PN Control Register: 1E.500E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress PN Control Register */ + union + { + struct + { + /*! \brief 1E.500E.F:0 R/W MSS Egress SA PN Threshold LSW [F:0] + AQ_MssEgressPnControlRegister_HHD.u0.bits_0.mssEgressSaPnThresholdLSW + + Default = 0x0000 + + PN threshold bits 15:0 + + + Notes: + Egress PN threshold to generate SA threshold interrupt. */ + unsigned int mssEgressSaPnThresholdLSW : 16; /* 1E.500E.F:0 R/W Default = 0x0000 */ + /* PN threshold bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress PN Control Register */ + union + { + struct + { + /*! \brief 1E.500F.F:0 R/W MSS Egress SA PN Threshold MSW [1F:10] + AQ_MssEgressPnControlRegister_HHD.u1.bits_1.mssEgressSaPnThresholdMSW + + Default = 0x0000 + + PN threshold bits 31:16 + + + Notes: + Egress PN threshold to generate SA threshold interrupt. */ + unsigned int mssEgressSaPnThresholdMSW : 16; /* 1E.500F.F:0 R/W Default = 0x0000 */ + /* PN threshold bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressPnControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress MTU Size Control Register: 1E.5010 */ +/* MSS Egress MTU Size Control Register: 1E.5010 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress MTU Size Control Register */ + union + { + struct + { + /*! \brief 1E.5010.F:0 R/W MSS Egress Controlled Packet MTU Size [F:0] + AQ_MssEgressMtuSizeControlRegister_HHD.u0.bits_0.mssEgressControlledPacketMtuSize + + Default = 0x05DC + + Maximum transmission unit for controlled packet + + + Notes: + Maximum transmission unit of controlled packet */ + unsigned int mssEgressControlledPacketMtuSize : 16; /* 1E.5010.F:0 R/W Default = 0x05DC */ + /* Maximum transmission unit for controlled packet + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress MTU Size Control Register */ + union + { + struct + { + /*! \brief 1E.5011.F:0 R/W MSS Egress Uncontrolled Packet MTU Size [F:0] + AQ_MssEgressMtuSizeControlRegister_HHD.u1.bits_1.mssEgressUncontrolledPacketMtuSize + + Default = 0x05DC + + Maximum transmission unit for uncontrolled packet + + + Notes: + Maximum transmission unit of uncontrolled packet */ + unsigned int mssEgressUncontrolledPacketMtuSize : 16; /* 1E.5011.F:0 R/W Default = 0x05DC */ + /* Maximum transmission unit for uncontrolled packet + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressMtuSizeControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress Interrupt Status Register: 1E.505C */ +/* MSS Egress Interrupt Status Register: 1E.505C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress Interrupt Status Register */ + union + { + struct + { + /*! \brief 1E.505C.0 COW MSS Egress Master Interrupt + AQ_MssEgressInterruptStatusRegister_HHD.u0.bits_0.mssEgressMasterInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when any one of the above interrupt and the corresponding interrupt enable are both set. The interrupt enable for this bit must also be set for this bit to be set. */ + unsigned int mssEgressMasterInterrupt : 1; /* 1E.505C.0 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.505C.1 COW MSS Egress SA Expired Interrupt + AQ_MssEgressInterruptStatusRegister_HHD.u0.bits_0.mssEgressSaExpiredInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when the SA PN reaches all ones saturation. */ + unsigned int mssEgressSaExpiredInterrupt : 1; /* 1E.505C.1 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.505C.2 COW MSS Egress SA Threshold Expired Interrupt + AQ_MssEgressInterruptStatusRegister_HHD.u0.bits_0.mssEgressSaThresholdExpiredInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when the SA PN reaches the See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . */ + unsigned int mssEgressSaThresholdExpiredInterrupt : 1; /* 1E.505C.2 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.505C.3 COW MSS Egress MIB Saturation Interrupt + AQ_MssEgressInterruptStatusRegister_HHD.u0.bits_0.mssEgressMibSaturationInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when the MIB counters reaches all ones saturation. */ + unsigned int mssEgressMibSaturationInterrupt : 1; /* 1E.505C.3 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.505C.4 COW MSS Egress ECC Error Interrupt + AQ_MssEgressInterruptStatusRegister_HHD.u0.bits_0.mssEgressEccErrorInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when anyone of the memories detects an ECC error. */ + unsigned int mssEgressEccErrorInterrupt : 1; /* 1E.505C.4 COW Default = 0x0 */ + /* 1 = Interrupt + */ + unsigned int reserved0 : 11; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress Interrupt Status Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressInterruptStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress Interrupt Mask Register: 1E.505E */ +/* MSS Egress Interrupt Mask Register: 1E.505E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress Interrupt Mask Register */ + union + { + struct + { + /*! \brief 1E.505E.0 COW MSS Egress Master Interrupt Enable + AQ_MssEgressInterruptMaskRegister_HHD.u0.bits_0.mssEgressMasterInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + + Notes: + Write to 1 to clear. */ + unsigned int mssEgressMasterInterruptEnable : 1; /* 1E.505E.0 COW Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.505E.1 COW MSS Egress SA Expired Interrupt Enable + AQ_MssEgressInterruptMaskRegister_HHD.u0.bits_0.mssEgressSaExpiredInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + + Notes: + Write to 1 to clear. This bit is set when the SA PN reaches all ones saturation. */ + unsigned int mssEgressSaExpiredInterruptEnable : 1; /* 1E.505E.1 COW Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.505E.2 COW MSS Egress SA Expired Threshold Interrupt Enable + AQ_MssEgressInterruptMaskRegister_HHD.u0.bits_0.mssEgressSaExpiredThresholdInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + + Notes: + Write to 1 to clear. This bit is set when the SA PN reaches the configured threshold See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . */ + unsigned int mssEgressSaExpiredThresholdInterruptEnable : 1; /* 1E.505E.2 COW Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.505E.3 COW MSS Egress MIB Saturation Interrupt Enable + AQ_MssEgressInterruptMaskRegister_HHD.u0.bits_0.mssEgressMibSaturationInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + + Notes: + Write to 1 to clear. This bit is set when the MIB counters reaches all ones saturation. */ + unsigned int mssEgressMibSaturationInterruptEnable : 1; /* 1E.505E.3 COW Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.505E.4 COW MSS Egress ECC Error Interrupt Enable + AQ_MssEgressInterruptMaskRegister_HHD.u0.bits_0.mssEgressEccErrorInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + + Notes: + Write to 1 to clear. This bit is set when anyone of the memories detects an ECC error. */ + unsigned int mssEgressEccErrorInterruptEnable : 1; /* 1E.505E.4 COW Default = 0x0 */ + /* 1 = Interrupt enabled + */ + unsigned int reserved0 : 11; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress Interrupt Mask Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressInterruptMaskRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress SA Expired Status Register: 1E.5060 */ +/* MSS Egress SA Expired Status Register: 1E.5060 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress SA Expired Status Register */ + union + { + struct + { + /*! \brief 1E.5060.F:0 COW MSS Egress SA Expired LSW [F:0] + AQ_MssEgressSaExpiredStatusRegister_HHD.u0.bits_0.mssEgressSaExpiredLSW + + Default = 0x0000 + + SA expired bits 15:0 + + + Notes: + Write these bits to 1 to clear. + When set, these bits identify the SA that has expired when the SA PN reaches all-ones saturation. */ + unsigned int mssEgressSaExpiredLSW : 16; /* 1E.5060.F:0 COW Default = 0x0000 */ + /* SA expired bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress SA Expired Status Register */ + union + { + struct + { + /*! \brief 1E.5061.F:0 COW MSS Egress SA Expired MSW [1F:10] + AQ_MssEgressSaExpiredStatusRegister_HHD.u1.bits_1.mssEgressSaExpiredMSW + + Default = 0x0000 + + SA expired bits 31:16 + + + Notes: + Write these bits to 1 to clear. + When set, these bits identify the SA that has expired when the SA PN reaches all-ones saturation. */ + unsigned int mssEgressSaExpiredMSW : 16; /* 1E.5061.F:0 COW Default = 0x0000 */ + /* SA expired bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressSaExpiredStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress SA Threshold Expired Status Register: 1E.5062 */ +/* MSS Egress SA Threshold Expired Status Register: 1E.5062 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress SA Threshold Expired Status Register */ + union + { + struct + { + /*! \brief 1E.5062.F:0 COW MSS Egress SA Threshold Expired LSW [F:0] + AQ_MssEgressSaThresholdExpiredStatusRegister_HHD.u0.bits_0.mssEgressSaThresholdExpiredLSW + + Default = 0x0000 + + SA threshold expired bits 15:0 + + + Notes: + Write these bits to 1 to clear. + When set, these bits identify the SA that has expired when the SA PN has reached the configured threshold See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . */ + unsigned int mssEgressSaThresholdExpiredLSW : 16; /* 1E.5062.F:0 COW Default = 0x0000 */ + /* SA threshold expired bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress SA Threshold Expired Status Register */ + union + { + struct + { + /*! \brief 1E.5063.F:0 COW MSS Egress SA Threshold Expired MSW [1F:10] + AQ_MssEgressSaThresholdExpiredStatusRegister_HHD.u1.bits_1.mssEgressSaThresholdExpiredMSW + + Default = 0x0000 + + SA threshold expired bits 31:16 + + + Notes: + Write these bits to 1 to clear. + When set, these bits identify the SA that has expired when the SA PN has reached the configured threshold See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . */ + unsigned int mssEgressSaThresholdExpiredMSW : 16; /* 1E.5063.F:0 COW Default = 0x0000 */ + /* SA threshold expired bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressSaThresholdExpiredStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress ECC Interrupt Status Register: 1E.5064 */ +/* MSS Egress ECC Interrupt Status Register: 1E.5064 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress ECC Interrupt Status Register */ + union + { + struct + { + /*! \brief 1E.5064.F:0 COW MSS Egress SA ECC Error Interrupt LSW [F:0] + AQ_MssEgressEccInterruptStatusRegister_HHD.u0.bits_0.mssEgressSaEccErrorInterruptLSW + + Default = 0x0000 + + SA ECC error interrupt bits 15:0 + + + Notes: + Write these bits to 1 to clear. + When set to 1, indicates that an ECC error occured for the SA. */ + unsigned int mssEgressSaEccErrorInterruptLSW : 16; /* 1E.5064.F:0 COW Default = 0x0000 */ + /* SA ECC error interrupt bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress ECC Interrupt Status Register */ + union + { + struct + { + /*! \brief 1E.5065.F:0 COW MSS Egress SA ECC Error Interrupt MSW [1F:10] + AQ_MssEgressEccInterruptStatusRegister_HHD.u1.bits_1.mssEgressSaEccErrorInterruptMSW + + Default = 0x0000 + + SA ECC error interrupt bits 31:16 + + + Notes: + Write these bits to 1 to clear. + When set to 1, indicates that an ECC error occured for the SA. */ + unsigned int mssEgressSaEccErrorInterruptMSW : 16; /* 1E.5065.F:0 COW Default = 0x0000 */ + /* SA ECC error interrupt bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressEccInterruptStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress LUT Address Control Register: 1E.5080 */ +/* MSS Egress LUT Address Control Register: 1E.5080 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress LUT Address Control Register */ + union + { + struct + { + /*! \brief 1E.5080.8:0 R/W MSS Egress LUT Address [8:0] + AQ_MssEgressLutAddressControlRegister_HHD.u0.bits_0.mssEgressLutAddress + + Default = 0x000 + + LUT address + + */ + unsigned int mssEgressLutAddress : 9; /* 1E.5080.8:0 R/W Default = 0x000 */ + /* LUT address + */ + unsigned int reserved0 : 3; + /*! \brief 1E.5080.F:C R/W MSS Egress LUT Select [3:0] + AQ_MssEgressLutAddressControlRegister_HHD.u0.bits_0.mssEgressLutSelect + + Default = 0x0 + + LUT select + + + Notes: + 0x0 : Egress MAC Control FIlter (CTLF) LUT + 0x1 : Egress Classification LUT + 0x2 : Egress SC/SA LUT + 0x3 : Egress SMIB */ + unsigned int mssEgressLutSelect : 4; /* 1E.5080.F:C R/W Default = 0x0 */ + /* LUT select + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_MssEgressLutAddressControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress LUT Control Register: 1E.5081 */ +/* MSS Egress LUT Control Register: 1E.5081 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress LUT Control Register */ + union + { + struct + { + unsigned int reserved0 : 14; + /*! \brief 1E.5081.E R/W MSS Egress LUT Read + AQ_MssEgressLutControlRegister_HHD.u0.bits_0.mssEgressLutRead + + Default = 0x0 + + 1 = LUT read + + + Notes: + Setting this bit to 1, will read the LUT. This bit will automatically clear to 0. */ + unsigned int mssEgressLutRead : 1; /* 1E.5081.E R/W Default = 0x0 */ + /* 1 = LUT read + */ + /*! \brief 1E.5081.F R/W MSS Egress LUT Write + AQ_MssEgressLutControlRegister_HHD.u0.bits_0.mssEgressLutWrite + + Default = 0x0 + + 1 = LUT write + + + Notes: + Setting this bit to 1, will write the LUT. This bit will automatically clear to 0. */ + unsigned int mssEgressLutWrite : 1; /* 1E.5081.F R/W Default = 0x0 */ + /* 1 = LUT write + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_MssEgressLutControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress LUT Data Control Register: 1E.50A0 */ +/* MSS Egress LUT Data Control Register: 1E.50A0 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A0.F:0 R/W MSS Egress LUT Data 0 [F:0] + AQ_MssEgressLutDataControlRegister_HHD.u0.bits_0.mssEgressLutData_0 + + Default = 0x0000 + + LUT data bits 15:0 + + */ + unsigned int mssEgressLutData_0 : 16; /* 1E.50A0.F:0 R/W Default = 0x0000 */ + /* LUT data bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A1.F:0 R/W MSS Egress LUT Data 1 [1F:10] + AQ_MssEgressLutDataControlRegister_HHD.u1.bits_1.mssEgressLutData_1 + + Default = 0x0000 + + LUT data bits 31:16 + + */ + unsigned int mssEgressLutData_1 : 16; /* 1E.50A1.F:0 R/W Default = 0x0000 */ + /* LUT data bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A2.F:0 R/W MSS Egress LUT Data 2 [2F:20] + AQ_MssEgressLutDataControlRegister_HHD.u2.bits_2.mssEgressLutData_2 + + Default = 0x0000 + + LUT data bits 47:32 + + */ + unsigned int mssEgressLutData_2 : 16; /* 1E.50A2.F:0 R/W Default = 0x0000 */ + /* LUT data bits 47:32 + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A3.F:0 R/W MSS Egress LUT Data 3 [3F:30] + AQ_MssEgressLutDataControlRegister_HHD.u3.bits_3.mssEgressLutData_3 + + Default = 0x0000 + + LUT data bits 63:48 + + */ + unsigned int mssEgressLutData_3 : 16; /* 1E.50A3.F:0 R/W Default = 0x0000 */ + /* LUT data bits 63:48 + */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A4.F:0 R/W MSS Egress LUT Data 4 [4F:40] + AQ_MssEgressLutDataControlRegister_HHD.u4.bits_4.mssEgressLutData_4 + + Default = 0x0000 + + LUT data bits 79:64 + + */ + unsigned int mssEgressLutData_4 : 16; /* 1E.50A4.F:0 R/W Default = 0x0000 */ + /* LUT data bits 79:64 + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A5.F:0 R/W MSS Egress LUT Data 5 [5F:50] + AQ_MssEgressLutDataControlRegister_HHD.u5.bits_5.mssEgressLutData_5 + + Default = 0x0000 + + LUT data bits 95:80 + + */ + unsigned int mssEgressLutData_5 : 16; /* 1E.50A5.F:0 R/W Default = 0x0000 */ + /* LUT data bits 95:80 + */ + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A6.F:0 R/W MSS Egress LUT Data 6 [6F:60] + AQ_MssEgressLutDataControlRegister_HHD.u6.bits_6.mssEgressLutData_6 + + Default = 0x0000 + + LUT data bits 111:96 + + */ + unsigned int mssEgressLutData_6 : 16; /* 1E.50A6.F:0 R/W Default = 0x0000 */ + /* LUT data bits 111:96 + */ + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A7.F:0 R/W MSS Egress LUT Data 7 [7F:70] + AQ_MssEgressLutDataControlRegister_HHD.u7.bits_7.mssEgressLutData_7 + + Default = 0x0000 + + LUT data bits 127:112 + + */ + unsigned int mssEgressLutData_7 : 16; /* 1E.50A7.F:0 R/W Default = 0x0000 */ + /* LUT data bits 127:112 + */ + } bits_7; + uint16_t word_7; + } u7; + /*! \brief Union for bit and word level access of word 8 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A8.F:0 R/W MSS Egress LUT Data 8 [8F:80] + AQ_MssEgressLutDataControlRegister_HHD.u8.bits_8.mssEgressLutData_8 + + Default = 0x0000 + + LUT data bits 143:128 + + */ + unsigned int mssEgressLutData_8 : 16; /* 1E.50A8.F:0 R/W Default = 0x0000 */ + /* LUT data bits 143:128 + */ + } bits_8; + uint16_t word_8; + } u8; + /*! \brief Union for bit and word level access of word 9 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A9.F:0 R/W MSS Egress LUT Data 9 [9F:90] + AQ_MssEgressLutDataControlRegister_HHD.u9.bits_9.mssEgressLutData_9 + + Default = 0x0000 + + LUT data bits 159:144 + + */ + unsigned int mssEgressLutData_9 : 16; /* 1E.50A9.F:0 R/W Default = 0x0000 */ + /* LUT data bits 159:144 + */ + } bits_9; + uint16_t word_9; + } u9; + /*! \brief Union for bit and word level access of word 10 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50AA.F:0 R/W MSS Egress LUT Data 10 [AF:A0] + AQ_MssEgressLutDataControlRegister_HHD.u10.bits_10.mssEgressLutData_10 + + Default = 0x0000 + + LUT data bits 175:160 + + */ + unsigned int mssEgressLutData_10 : 16; /* 1E.50AA.F:0 R/W Default = 0x0000 */ + /* LUT data bits 175:160 + */ + } bits_10; + uint16_t word_10; + } u10; + /*! \brief Union for bit and word level access of word 11 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50AB.F:0 R/W MSS Egress LUT Data 11 [BF:B0] + AQ_MssEgressLutDataControlRegister_HHD.u11.bits_11.mssEgressLutData_11 + + Default = 0x0000 + + LUT data bits 191:176 + + */ + unsigned int mssEgressLutData_11 : 16; /* 1E.50AB.F:0 R/W Default = 0x0000 */ + /* LUT data bits 191:176 + */ + } bits_11; + uint16_t word_11; + } u11; + /*! \brief Union for bit and word level access of word 12 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50AC.F:0 R/W MSS Egress LUT Data 12 [CF:C0] + AQ_MssEgressLutDataControlRegister_HHD.u12.bits_12.mssEgressLutData_12 + + Default = 0x0000 + + LUT data bits 207:192 + + */ + unsigned int mssEgressLutData_12 : 16; /* 1E.50AC.F:0 R/W Default = 0x0000 */ + /* LUT data bits 207:192 + */ + } bits_12; + uint16_t word_12; + } u12; + /*! \brief Union for bit and word level access of word 13 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50AD.F:0 R/W MSS Egress LUT Data 13 [DF:D0] + AQ_MssEgressLutDataControlRegister_HHD.u13.bits_13.mssEgressLutData_13 + + Default = 0x0000 + + LUT data bits 223:208 + + */ + unsigned int mssEgressLutData_13 : 16; /* 1E.50AD.F:0 R/W Default = 0x0000 */ + /* LUT data bits 223:208 + */ + } bits_13; + uint16_t word_13; + } u13; + /*! \brief Union for bit and word level access of word 14 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50AE.F:0 R/W MSS Egress LUT Data 14 [EF:E0] + AQ_MssEgressLutDataControlRegister_HHD.u14.bits_14.mssEgressLutData_14 + + Default = 0x0000 + + LUT data bits 239:224 + + */ + unsigned int mssEgressLutData_14 : 16; /* 1E.50AE.F:0 R/W Default = 0x0000 */ + /* LUT data bits 239:224 + */ + } bits_14; + uint16_t word_14; + } u14; + /*! \brief Union for bit and word level access of word 15 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50AF.F:0 R/W MSS Egress LUT Data 15 [FF:F0] + AQ_MssEgressLutDataControlRegister_HHD.u15.bits_15.mssEgressLutData_15 + + Default = 0x0000 + + LUT data bits 255:240 + + */ + unsigned int mssEgressLutData_15 : 16; /* 1E.50AF.F:0 R/W Default = 0x0000 */ + /* LUT data bits 255:240 + */ + } bits_15; + uint16_t word_15; + } u15; + /*! \brief Union for bit and word level access of word 16 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B0.F:0 R/W MSS Egress LUT Data 16 [10F:100] + AQ_MssEgressLutDataControlRegister_HHD.u16.bits_16.mssEgressLutData_16 + + Default = 0x0000 + + LUT data bits 271:256 + + */ + unsigned int mssEgressLutData_16 : 16; /* 1E.50B0.F:0 R/W Default = 0x0000 */ + /* LUT data bits 271:256 + */ + } bits_16; + uint16_t word_16; + } u16; + /*! \brief Union for bit and word level access of word 17 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B1.F:0 R/W MSS Egress LUT Data 17 [11F:110] + AQ_MssEgressLutDataControlRegister_HHD.u17.bits_17.mssEgressLutData_17 + + Default = 0x0000 + + LUT data bits 287:272 + + */ + unsigned int mssEgressLutData_17 : 16; /* 1E.50B1.F:0 R/W Default = 0x0000 */ + /* LUT data bits 287:272 + */ + } bits_17; + uint16_t word_17; + } u17; + /*! \brief Union for bit and word level access of word 18 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B2.F:0 R/W MSS Egress LUT Data 18 [12F:120] + AQ_MssEgressLutDataControlRegister_HHD.u18.bits_18.mssEgressLutData_18 + + Default = 0x0000 + + LUT data bits 303:288 + + */ + unsigned int mssEgressLutData_18 : 16; /* 1E.50B2.F:0 R/W Default = 0x0000 */ + /* LUT data bits 303:288 + */ + } bits_18; + uint16_t word_18; + } u18; + /*! \brief Union for bit and word level access of word 19 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B3.F:0 R/W MSS Egress LUT Data 19 [13F:130] + AQ_MssEgressLutDataControlRegister_HHD.u19.bits_19.mssEgressLutData_19 + + Default = 0x0000 + + LUT data bits 319:304 + + */ + unsigned int mssEgressLutData_19 : 16; /* 1E.50B3.F:0 R/W Default = 0x0000 */ + /* LUT data bits 319:304 + */ + } bits_19; + uint16_t word_19; + } u19; + /*! \brief Union for bit and word level access of word 20 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B4.F:0 R/W MSS Egress LUT Data 20 [14F:140] + AQ_MssEgressLutDataControlRegister_HHD.u20.bits_20.mssEgressLutData_20 + + Default = 0x0000 + + LUT data bits 335:320 + + */ + unsigned int mssEgressLutData_20 : 16; /* 1E.50B4.F:0 R/W Default = 0x0000 */ + /* LUT data bits 335:320 + */ + } bits_20; + uint16_t word_20; + } u20; + /*! \brief Union for bit and word level access of word 21 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B5.F:0 R/W MSS Egress LUT Data 21 [15F:150] + AQ_MssEgressLutDataControlRegister_HHD.u21.bits_21.mssEgressLutData_21 + + Default = 0x0000 + + LUT data bits 351:336 + + */ + unsigned int mssEgressLutData_21 : 16; /* 1E.50B5.F:0 R/W Default = 0x0000 */ + /* LUT data bits 351:336 + */ + } bits_21; + uint16_t word_21; + } u21; + /*! \brief Union for bit and word level access of word 22 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B6.F:0 R/W MSS Egress LUT Data 22 [16F:160] + AQ_MssEgressLutDataControlRegister_HHD.u22.bits_22.mssEgressLutData_22 + + Default = 0x0000 + + LUT data bits 367:352 + + */ + unsigned int mssEgressLutData_22 : 16; /* 1E.50B6.F:0 R/W Default = 0x0000 */ + /* LUT data bits 367:352 + */ + } bits_22; + uint16_t word_22; + } u22; + /*! \brief Union for bit and word level access of word 23 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B7.F:0 R/W MSS Egress LUT Data 23 [17F:170] + AQ_MssEgressLutDataControlRegister_HHD.u23.bits_23.mssEgressLutData_23 + + Default = 0x0000 + + LUT data bits 383:368 + + */ + unsigned int mssEgressLutData_23 : 16; /* 1E.50B7.F:0 R/W Default = 0x0000 */ + /* LUT data bits 383:368 + */ + } bits_23; + uint16_t word_23; + } u23; + /*! \brief Union for bit and word level access of word 24 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B8.F:0 R/W MSS Egress LUT Data 24 [18F:180] + AQ_MssEgressLutDataControlRegister_HHD.u24.bits_24.mssEgressLutData_24 + + Default = 0x0000 + + LUT data bits 399:384 + + */ + unsigned int mssEgressLutData_24 : 16; /* 1E.50B8.F:0 R/W Default = 0x0000 */ + /* LUT data bits 399:384 + */ + } bits_24; + uint16_t word_24; + } u24; + /*! \brief Union for bit and word level access of word 25 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B9.F:0 R/W MSS Egress LUT Data 25 [19F:190] + AQ_MssEgressLutDataControlRegister_HHD.u25.bits_25.mssEgressLutData_25 + + Default = 0x0000 + + LUT data bits 415:400 + + */ + unsigned int mssEgressLutData_25 : 16; /* 1E.50B9.F:0 R/W Default = 0x0000 */ + /* LUT data bits 415:400 + */ + } bits_25; + uint16_t word_25; + } u25; + /*! \brief Union for bit and word level access of word 26 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50BA.F:0 R/W MSS Egress LUT Data 26 [1AF:1A0] + AQ_MssEgressLutDataControlRegister_HHD.u26.bits_26.mssEgressLutData_26 + + Default = 0x0000 + + LUT data bits 431:416 + + */ + unsigned int mssEgressLutData_26 : 16; /* 1E.50BA.F:0 R/W Default = 0x0000 */ + /* LUT data bits 431:416 + */ + } bits_26; + uint16_t word_26; + } u26; + /*! \brief Union for bit and word level access of word 27 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50BB.F:0 R/W MSS Egress LUT Data 27 [1BF:1B0] + AQ_MssEgressLutDataControlRegister_HHD.u27.bits_27.mssEgressLutData_27 + + Default = 0x0000 + + LUT data bits 447:432 + + */ + unsigned int mssEgressLutData_27 : 16; /* 1E.50BB.F:0 R/W Default = 0x0000 */ + /* LUT data bits 447:432 + */ + } bits_27; + uint16_t word_27; + } u27; +} AQ_MssEgressLutDataControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System General Control Register: 1E.6004 */ +/* MSM System General Control Register: 1E.6004 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System General Control Register */ + union + { + struct + { + /*! \brief 1E.6004.0 R/W MSM System Tx Enable + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemTxEnable + + Default = 0x0 + + 1 = Tx enable + + Notes: + MAC Rx path enable. Should be set to 1 to enable the MAC Rx path. Should be set to 0 to disable the MAC Rx path. */ + unsigned int msmSystemTxEnable : 1; /* 1E.6004.0 R/W Default = 0x0 */ + /* 1 = Tx enable */ + /*! \brief 1E.6004.1 R/W MSM System Rx Enable + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemRxEnable + + Default = 0x0 + + 1 = Rx enable + + Notes: + MAC Tx path enable. Should be set to 1 to enable the MAC Tx path. Should be set to 0 to disable the MAC Tx path. */ + unsigned int msmSystemRxEnable : 1; /* 1E.6004.1 R/W Default = 0x0 */ + /* 1 = Rx enable */ + unsigned int reserved0 : 1; + /*! \brief 1E.6004.3 R/W MSM System WAN Mode + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemWanMode + + Default = 0x0 + + 1 = WAN mode + 0 = LAN mode + + + Notes: + WAN mode enable. Sets WAN mode when set to 1 and LAN mode when set to 0. Note: When changing the mode, verifiy correct setting of the Tx IPG. */ + unsigned int msmSystemWanMode : 1; /* 1E.6004.3 R/W Default = 0x0 */ + /* 1 = WAN mode + 0 = LAN mode + */ + /*! \brief 1E.6004.4 R/W MSM System Promiscuous Mode + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemPromiscuousMode + + Default = 0x0 + + 1 = Promiscuous mode + + + Notes: + When set to 1, all frames are received without any MAC address filtering. */ + unsigned int msmSystemPromiscuousMode : 1; /* 1E.6004.4 R/W Default = 0x0 */ + /* 1 = Promiscuous mode + */ + /*! \brief 1E.6004.5 R/W MSM System PAD Enable + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemPadEnable + + Default = 0x0 + + 1 = Enable frame padding removal on Rx + + + Notes: + When set to 1, enable frame padding removal on the Rx path. If enabled, padding is removed before the frame is transferred to the MAC client application. If disabled, no padding is removed on the Rx by the MAC. + Note : On Tx, the MAC always adds padding as required. */ + unsigned int msmSystemPadEnable : 1; /* 1E.6004.5 R/W Default = 0x0 */ + /* 1 = Enable frame padding removal on Rx + */ + /*! \brief 1E.6004.6 R/W MSM System CRC Forward + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemCrcForward + + Default = 0x0 + + 1 = Enable CRC forwarding + + + Notes: + When set to 1, the CRC field of the received frames is forwarded with the frame to the user application. If disabled, the CRC field is stripped from the frame. + Note : If padding is enabled ( See MAC PAD Enable set to 1), this bit is ignored. */ + unsigned int msmSystemCrcForward : 1; /* 1E.6004.6 R/W Default = 0x0 */ + /* 1 = Enable CRC forwarding + */ + /*! \brief 1E.6004.7 R/W MSM System Pause Forward + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemPauseForward + + Default = 0x0 + + 1 = Enable Pause forwarding + + + Notes: + Terminate or forward pause frames. If set to 1, pause frames are forwarded to the user application. In normal mode, when set to 0, pause frames are terminated and discarded within the MAC. */ + unsigned int msmSystemPauseForward : 1; /* 1E.6004.7 R/W Default = 0x0 */ + /* 1 = Enable Pause forwarding + */ + /*! \brief 1E.6004.8 R/W MSM System Pause Ignore + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemPauseIgnore + + Default = 0x0 + + 1 = Ignore pause frames + + + Notes: + Ignore pause frame quanta. If set to 1, received pause frames are ignored by the MAC. When set to 0, the Tx is stopped for the amount of time specified in the pause quanta received within the pause frame. */ + unsigned int msmSystemPauseIgnore : 1; /* 1E.6004.8 R/W Default = 0x0 */ + /* 1 = Ignore pause frames + */ + /*! \brief 1E.6004.9 R/W MSM System Tx Address Insert Enable + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemTxAddressInsertEnable + + Default = 0x0 + + 1 = Insert Tx MAC source address + + + Notes: + Set the source MAC address on transmit. If set to 1, the MAC overwrites the source MAC address with the MAC programmed address in all transmitted frames. When set to 0, the source MAC address is transmitted unmodified from the MAC Tx client application. */ + unsigned int msmSystemTxAddressInsertEnable : 1; /* 1E.6004.9 R/W Default = 0x0 */ + /* 1 = Insert Tx MAC source address + */ + /*! \brief 1E.6004.A R/W MSM System Tx CRC Append + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemTxCrcAppend + + Default = 0x0 + + 1 = Append Tx CRC + + + Notes: + Permanently enable CRC append on transmit. If set to 1, the Tx will append a CRC to all transmitted frames. If set to 0, CRC append can be controlled on a per frame basis using the pin ff_tx_crc. + This configuration bit is OR'ed with the external ff_tx_crc pin to instruct the Tx to append a CRC to transmitted frames. The ff_tx_crc pin is tied to 0. */ + unsigned int msmSystemTxCrcAppend : 1; /* 1E.6004.A R/W Default = 0x0 */ + /* 1 = Append Tx CRC + */ + /*! \brief 1E.6004.B R/W MSM System Tx Pad Enable + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemTxPadEnable + + Default = 0x1 + + 1 = Enable Tx padding + + + Notes: + When set to 1, enable padding of frames in the Tx direction. When set to 0, the MAC will not extend frames from the application to a minimum of 64 bytes, allowing to transmit short frames (violating the Ethernet mimimum size requirements). Must be set to 1 for normal operation. */ + unsigned int msmSystemTxPadEnable : 1; /* 1E.6004.B R/W Default = 0x1 */ + /* 1 = Enable Tx padding + */ + /*! \brief 1E.6004.C R/WSC MSM System Soft Reset + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemSoftReset + + Default = 0x0 + + 1 = Soft reset + + + Notes: + Software reset. Self clearing bit. When set to 1, resets all statistic counters as well as the Tx and Rx FIFOs. It should be issued after all traffic has been stopped as a result of clearing the Rx/Tx enable bits ( See MAC Rx Enable set to 0 and See MAC Tx Enable set to 0). + Note : Can lead to an Rx interface (ff_rx_xxx) violations to the application if the reset is issued in the middle of a receive frame transfer. Then the end of packet (assertion of ff_rx_eop) is lost and the application should be prepeared to handle this exception. */ + unsigned int msmSystemSoftReset : 1; /* 1E.6004.C R/WSC Default = 0x0 */ + /* 1 = Soft reset + */ + /*! \brief 1E.6004.D R/W MSM System Control Frame Enable + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemControlFrameEnable + + Default = 0x0 + + 1 = Control frame enabled + + + Notes: + MAC control frame enable. When set to 1, the MAC control frames with any Opcode other than 0x0001 are accepted and forwarded to the client interface. When set to 0, MAC control frames with any opcode other than 0x0001 are silently discarded. */ + unsigned int msmSystemControlFrameEnable : 1; /* 1E.6004.D R/W Default = 0x0 */ + /* 1 = Control frame enabled + */ + /*! \brief 1E.6004.E R/W MSM System Rx Error Discard + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemRxErrorDiscard + + Default = 0x0 + + 1 = Enable discard of received errored frames + + + Notes: + Rx errored frame discard enable. When set to 1, any frame received with an error is discarded and not forwarded to the client interface. When set to 0, errored frames are forwarded to the client interface with ff_rx_err asserted. + Note : It is recommended to set this bit to 1 only when store and forward operation is enabled (RX_SECTION_FULL TBD). */ + unsigned int msmSystemRxErrorDiscard : 1; /* 1E.6004.E R/W Default = 0x0 */ + /* 1 = Enable discard of received errored frames + */ + /*! \brief 1E.6004.F R/W MSM System PHY Tx Enable + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemPhyTxEnable + + Default = 0x0 + + 1 = Enable PHY Tx + + + Notes: + Directly controls the phy_tx_ena pin. */ + unsigned int msmSystemPhyTxEnable : 1; /* 1E.6004.F R/W Default = 0x0 */ + /* 1 = Enable PHY Tx + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System General Control Register */ + union + { + struct + { + /*! \brief 1E.6005.0 R/W MSM System Force Send IDLE + AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemForceSendIdle + + Default = 0x0 + + 1 = Force send idle + + Notes: + When set to 1, suppress any frame transmissions and forces IDLE n the Tx interface instead of frames. This control affects the MAC reconciliation layer (RS) which acts after all MAC datapath has processed the frame. + Note : Does not have an effect on fault handling (i.e. reception of local fault will still cause transmit of remote fault). + Must be 0 for normal operation. */ + unsigned int msmSystemForceSendIdle : 1; /* 1E.6005.0 R/W Default = 0x0 */ + /* 1 = Force send idle */ + /*! \brief 1E.6005.1 R/W MSM System Length Check Disable + AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemLengthCheckDisable + + Default = 0x0 + + 1 = Disable length check + + Notes: + Payload length check disable. When set to 0, the MAC checks the frames payload length with the frame length/type field. When set to 1, the payload length check is disabled. */ + unsigned int msmSystemLengthCheckDisable : 1; /* 1E.6005.1 R/W Default = 0x0 */ + /* 1 = Disable length check */ + /*! \brief 1E.6005.2 R/W MSM System IDLE Column Count Extend + AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemIdleColumnCountExtend + + Default = 0x0 + + 1 = Extend IDLE column count + + Notes: + When set to 1, extends the RS layer IDLE column counter by 2x. The IEEE 802.3ae defines the fault condition to be cleared after 128 columns of IDLE have been received. If the MAC operates together with a WAN mode PCS (WIS) it may may happen (depending on PCS) that this period is too short to bridge the IDLE stuffing occurring in this mode, leading to a toggling fault indication. In this case, extending the counter helps to aoivd toggling fault indications. */ + unsigned int msmSystemIdleColumnCountExtend : 1; /* 1E.6005.2 R/W Default = 0x0 */ + /* 1 = Extend IDLE column count */ + /*! \brief 1E.6005.3 R/W MSM System Priority Flow Control Enable + AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemPriorityFlowControlEnable + + Default = 0x0 + + 1 = Enable priority flow control + 0 = Enable link flow control + + + Notes: + Enable priority flow control (PFC) mode of operation. When set to 0, the MAC uses standard link pause frames. When set to 1, the MAC will transmit and accept PFC frames. */ + unsigned int msmSystemPriorityFlowControlEnable : 1; /* 1E.6005.3 R/W Default = 0x0 */ + /* 1 = Enable priority flow control + 0 = Enable link flow control + */ + unsigned int reserved2 : 1; + /*! \brief 1E.6005.5 R/W MSM System SFD Check Disable + AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemSfdCheckDisable + + Default = 0x0 + + 1 = Disable SFD check + + + Notes: + Disable check of SFD (0xD5) character at frame start. When set to 1, the frame is accepted even if the SFD byte following the preamble is not 0xD5. When set to 0, a frame is accepted only if the SFD byte is found with the value 0xD5. */ + unsigned int msmSystemSfdCheckDisable : 1; /* 1E.6005.5 R/W Default = 0x0 */ + /* 1 = Disable SFD check + */ + unsigned int reserved1 : 1; + /*! \brief 1E.6005.7 R/W MSM System Tx Low Power IDLE Enable + AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemTxLowPowerIdleEnable + + Default = 0x0 + + 1 = Transmit LPI enable + + + Notes: + Transmit low power IDLE enable. When set to 1, the MAC completes the transmission of the current frame and generates low power IDLE sequences (LPI) to the XGMII/SGMII. When set to 0, the MAC operates in normal mode. This bit is OR'ed with the reg_lowp_ena pin. */ + unsigned int msmSystemTxLowPowerIdleEnable : 1; /* 1E.6005.7 R/W Default = 0x0 */ + /* 1 = Transmit LPI enable + */ + unsigned int reserved0 : 8; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemGeneralControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System FIFO Control Register: 1E.600E */ +/* MSM System FIFO Control Register: 1E.600E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.600E.7:0 R/W MSM System Rx FIFO Full Threshold [7:0] + AQ_MsmSystemFifoControlRegister_HHD.u0.bits_0.msmSystemRxFifoFullThreshold + + Default = 0x08 + + Rx FIFO full threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmSystemRxFifoFullThreshold : 8; /* 1E.600E.7:0 R/W Default = 0x08 */ + /* Rx FIFO full threshold */ + unsigned int reserved0 : 8; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.600F.7:0 R/W MSM System Rx FIFO Empty Threshold [7:0] + AQ_MsmSystemFifoControlRegister_HHD.u1.bits_1.msmSystemRxFifoEmptyThreshold + + Default = 0x00 + + Rx FIFO empty threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmSystemRxFifoEmptyThreshold : 8; /* 1E.600F.7:0 R/W Default = 0x00 */ + /* Rx FIFO empty threshold */ + unsigned int reserved0 : 8; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of MSM System FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.6010.5:0 R/W MSM System Tx FIFO Full Threshold [5:0] + AQ_MsmSystemFifoControlRegister_HHD.u2.bits_2.msmSystemTxFifoFullThreshold + + Default = 0x08 + + Tx FIFO full threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmSystemTxFifoFullThreshold : 6; /* 1E.6010.5:0 R/W Default = 0x08 */ + /* Tx FIFO full threshold */ + unsigned int reserved0 : 10; + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of MSM System FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.6011.5:0 R/W MSM System Tx FIFO Empty Threshold [5:0] + AQ_MsmSystemFifoControlRegister_HHD.u3.bits_3.msmSystemTxFifoEmptyThreshold + + Default = 0x00 + + Tx FIFO empty threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmSystemTxFifoEmptyThreshold : 6; /* 1E.6011.5:0 R/W Default = 0x00 */ + /* Tx FIFO empty threshold */ + unsigned int reserved0 : 10; + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of MSM System FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.6012.7:0 ROS MSM System Rx FIFO Almost Full Threshold [7:0] + AQ_MsmSystemFifoControlRegister_HHD.u4.bits_4.msmSystemRxFifoAlmostFullThreshold + + Default = 0x00 + + Rx FIFO almost full threshold + + Notes: + Unused. */ + unsigned int msmSystemRxFifoAlmostFullThreshold : 8; /* 1E.6012.7:0 ROS Default = 0x00 */ + /* Rx FIFO almost full threshold */ + unsigned int reserved0 : 8; + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of MSM System FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.6013.7:0 ROS MSM System Rx FIFO Almost Empty Threshold [7:0] + AQ_MsmSystemFifoControlRegister_HHD.u5.bits_5.msmSystemRxFifoAlmostEmptyThreshold + + Default = 0x00 + + Rx FIFO almost empty threshold + + Notes: + Unused. */ + unsigned int msmSystemRxFifoAlmostEmptyThreshold : 8; /* 1E.6013.7:0 ROS Default = 0x00 */ + /* Rx FIFO almost empty threshold */ + unsigned int reserved0 : 8; + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of MSM System FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.6014.7:0 ROS MSM System Tx FIFO Almost Full Threshold [7:0] + AQ_MsmSystemFifoControlRegister_HHD.u6.bits_6.msmSystemTxFifoAlmostFullThreshold + + Default = 0x00 + + Tx FIFO almost full threshold + + Notes: + Unused. */ + unsigned int msmSystemTxFifoAlmostFullThreshold : 8; /* 1E.6014.7:0 ROS Default = 0x00 */ + /* Tx FIFO almost full threshold */ + unsigned int reserved0 : 8; + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of MSM System FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.6015.7:0 ROS MSM System Tx FIFO Almost Empty Threshold [7:0] + AQ_MsmSystemFifoControlRegister_HHD.u7.bits_7.msmSystemTxFifoAlmostEmptyThreshold + + Default = 0x00 + + Tx FIFO almost empty threshold + + Notes: + Unused. */ + unsigned int msmSystemTxFifoAlmostEmptyThreshold : 8; /* 1E.6015.7:0 ROS Default = 0x00 */ + /* Tx FIFO almost empty threshold */ + unsigned int reserved0 : 8; + } bits_7; + uint16_t word_7; + } u7; +} AQ_MsmSystemFifoControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System General Status Register: 1E.6020 */ +/* MSM System General Status Register: 1E.6020 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System General Status Register */ + union + { + struct + { + /*! \brief 1E.6020.0 BLH MSM System Rx Local Fault + AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemRxLocalFault + + + + Rx local fault detected + + Notes: + Latch high local fault status. Set to 1, whent he MAC detects Rx local fault sequences on the Rx interface. Reset to 0 after read and after reset. */ + unsigned int msmSystemRxLocalFault : 1; /* 1E.6020.0 BLH */ + /* Rx local fault detected */ + /*! \brief 1E.6020.1 BLH MSM System Rx Remote Fault + AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemRxRemoteFault + + + + Rx remote fault detected + + Notes: + Latch high local fault status. Set to 1, whent he MAC detects Rx local fault sequences on the Rx interface. Reset to 0 after read and after reset. */ + unsigned int msmSystemRxRemoteFault : 1; /* 1E.6020.1 BLH */ + /* Rx remote fault detected */ + /*! \brief 1E.6020.2 RO MSM System PHY Loss of Signal + AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemPhyLossOfSignal + + + + PHY loss of signal + + Notes: + PHY indicates loss of signal. This is the value of pin phy_los which is tied to 0. */ + unsigned int msmSystemPhyLossOfSignal : 1; /* 1E.6020.2 RO */ + /* PHY loss of signal */ + /*! \brief 1E.6020.3 R/W MSM System Timestamp Available + AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemTimestampAvailable + + Default = 0x0 + + Timestamp available + + Notes: + Transmit timestamp available. Indicates that the timestamp of the last transmitted event frame (which had ff_tx_ts_frm=1) is available in the register See MAC Time Stamp Status 0 [F:0] and See MAC Time Stamp Status 1 [F:0] . To clear this bit, the bit must be written with a 1. + */ + unsigned int msmSystemTimestampAvailable : 1; /* 1E.6020.3 R/W Default = 0x0 */ + /* Timestamp available */ + /*! \brief 1E.6020.4 RO MSM System Rx Low Power IDLE + AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemRxLowPowerIdle + + + + Rx LPI detected + + Notes: + Receive low power IDLE (LPI). Set to 1 when LPI is currently detected on the MAC Rx interface. Set to 0, when the MAC currently operates in normal mode. */ + unsigned int msmSystemRxLowPowerIdle : 1; /* 1E.6020.4 RO */ + /* Rx LPI detected */ + /*! \brief 1E.6020.5 RO MSM System Tx FIFO Empty + AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemTxFifoEmpty + + + + Tx FIFO empty + + Notes: + When set to 1, indicates the Tx FIFO is empty. When set to 0, Tx FIFO is non-empty. */ + unsigned int msmSystemTxFifoEmpty : 1; /* 1E.6020.5 RO */ + /* Tx FIFO empty */ + unsigned int reserved0 : 10; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System General Status Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemGeneralStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx IPG Control Register: 1E.6022 */ +/* MSM System Tx IPG Control Register: 1E.6022 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx IPG Control Register */ + union + { + struct + { + /*! \brief 1E.6022.5:0 R/W MSM System Tx IPG Length [5:0] + AQ_MsmSystemTxIpgControlRegister_HHD.u0.bits_0.msmSystemTxIpgLength + + Default = 0x0C + + Tx IPG length + + Notes: + Tx inter-packet gap (IPG) value. Depending on LAN or WAN mode of operation. + LAN Mode : Number of octets in steps of 4. Valid values are 8, 12, 16,..., 100. DIC is supported for any setting > 8. A default of 12 must be set to conform to IEEE802.3ae. + WAN Mode : Stretch factor. Valid values are 4 ... 15. The stretch factor is calculated as (value+1)*8. A default of 12 must be set to conform to IEEE802.3ae (i.e. 13*8=104). A larger value shrinks the IPG (increasing bandwidth). + The reset value of 12 leads to IEEE802.3ae conformant behavior in both modes. + Note : WAN mode is only available in 10G mode of operation. */ + unsigned int msmSystemTxIpgLength : 6; /* 1E.6022.5:0 R/W Default = 0x0C */ + /* Tx IPG length */ + unsigned int reserved0 : 10; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx IPG Control Register */ + union + { + struct + { + /*! \brief 1E.6023.F:0 MSM System Tx IPG Reserved + AQ_MsmSystemTxIpgControlRegister_HHD.u1.bits_1.msmSystemTxIpgReserved + + + + Value always 0, writes ignored + */ + unsigned int msmSystemTxIpgReserved : 16; /* 1E.6023.F:0 */ + /* Value always 0, writes ignored */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxIpgControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx Good Frames Counter Register: 1E.6040 */ +/* MSM System Tx Good Frames Counter Register: 1E.6040 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6040.F:0 ROS MSM System Tx Good Frames Counter 0 [F:0] + AQ_MsmSystemTxGoodFramesCounterRegister_HHD.u0.bits_0.msmSystemTxGoodFramesCounter_0 + + Default = 0x0000 + + Tx good frame counter bits 15:0 + + Notes: + Count of frames transmitted without error (Including pause frames). */ + unsigned int msmSystemTxGoodFramesCounter_0 : 16; /* 1E.6040.F:0 ROS Default = 0x0000 */ + /* Tx good frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6041.F:0 ROS MSM System Tx Good Frames Counter 1 [F:0] + AQ_MsmSystemTxGoodFramesCounterRegister_HHD.u1.bits_1.msmSystemTxGoodFramesCounter_1 + + Default = 0x0000 + + Tx good frame counter bits 31:16 + + + Notes: + Count of frames transmitted without error (Including pause frames). */ + unsigned int msmSystemTxGoodFramesCounter_1 : 16; /* 1E.6041.F:0 ROS Default = 0x0000 */ + /* Tx good frame counter bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxGoodFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Good Frames Counter Register: 1E.6044 */ +/* MSM System Rx Good Frames Counter Register: 1E.6044 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6044.F:0 ROS MSM System Rx Good Frames Counter 0 [F:0] + AQ_MsmSystemRxGoodFramesCounterRegister_HHD.u0.bits_0.msmSystemRxGoodFramesCounter_0 + + Default = 0x0000 + + Rx good frame counter bits 15:0 + + Notes: + Count of frames received without error (Including pause frames). */ + unsigned int msmSystemRxGoodFramesCounter_0 : 16; /* 1E.6044.F:0 ROS Default = 0x0000 */ + /* Rx good frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6045.F:0 ROS MSM System Rx Good Frames Counter 1 [F:0] + AQ_MsmSystemRxGoodFramesCounterRegister_HHD.u1.bits_1.msmSystemRxGoodFramesCounter_1 + + Default = 0x0000 + + Rx good frame counter bits 31:16 + + Notes: + Count of frames received without error (Including pause frames). */ + unsigned int msmSystemRxGoodFramesCounter_1 : 16; /* 1E.6045.F:0 ROS Default = 0x0000 */ + /* Rx good frame counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxGoodFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx FCS Errors Counter Register: 1E.6048 */ +/* MSM System Rx FCS Errors Counter Register: 1E.6048 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx FCS Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.6048.F:0 ROS MSM System FCS Error Counter 0 [F:0] + AQ_MsmSystemRxFcsErrorsCounterRegister_HHD.u0.bits_0.msmSystemFcsErrorCounter_0 + + Default = 0x0000 + + Frame check sequence error counter bits 15:0 + + Notes: + Count of frames for which a CRC-32 Error is detected but the frame is otherwise of correct length. */ + unsigned int msmSystemFcsErrorCounter_0 : 16; /* 1E.6048.F:0 ROS Default = 0x0000 */ + /* Frame check sequence error counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx FCS Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.6049.F:0 ROS MSM System FCS Error Counter 1 [F:0] + AQ_MsmSystemRxFcsErrorsCounterRegister_HHD.u1.bits_1.msmSystemFcsErrorCounter_1 + + Default = 0x0000 + + Frame check sequence error counter bits 31:16 + + Notes: + Count of frames for which a CRC-32 Error is detected but the frame is otherwise of correct length. */ + unsigned int msmSystemFcsErrorCounter_1 : 16; /* 1E.6049.F:0 ROS Default = 0x0000 */ + /* Frame check sequence error counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxFcsErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Alignment Errors Counter Register: 1E.604C */ +/* MSM System Rx Alignment Errors Counter Register: 1E.604C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Alignment Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.604C.F:0 ROS MSM System Alignment Error Counter 0 [F:0] + AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD.u0.bits_0.msmSystemAlignmentErrorCounter_0 + + Default = 0x0000 + + Alignment error counter bits 15:0 + + Notes: + Count of frames received with an alignment error. */ + unsigned int msmSystemAlignmentErrorCounter_0 : 16; /* 1E.604C.F:0 ROS Default = 0x0000 */ + /* Alignment error counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Alignment Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.604D.F:0 ROS MSM System Alignment Error Counter 1 [F:0] + AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD.u1.bits_1.msmSystemAlignmentErrorCounter_1 + + Default = 0x0000 + + Alignment error counter bits 31:16 + + Notes: + Count of frames received with an alignment error. */ + unsigned int msmSystemAlignmentErrorCounter_1 : 16; /* 1E.604D.F:0 ROS Default = 0x0000 */ + /* Alignment error counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx Pause Frames Counter Register: 1E.6050 */ +/* MSM System Tx Pause Frames Counter Register: 1E.6050 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6050.F:0 ROS MSM System Tx Pause Frames Counter 0 [F:0] + AQ_MsmSystemTxPauseFramesCounterRegister_HHD.u0.bits_0.msmSystemTxPauseFramesCounter_0 + + Default = 0x0000 + + Tx pause frame counter bits 15:0 + + Notes: + Valid pause frames transmitted. */ + unsigned int msmSystemTxPauseFramesCounter_0 : 16; /* 1E.6050.F:0 ROS Default = 0x0000 */ + /* Tx pause frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6051.F:0 ROS MSM System Tx Pause Frames Counter 1 [F:0] + AQ_MsmSystemTxPauseFramesCounterRegister_HHD.u1.bits_1.msmSystemTxPauseFramesCounter_1 + + Default = 0x0000 + + Tx pause frame counter bits 31:16 + + + Notes: + Valid pause frames transmitted. */ + unsigned int msmSystemTxPauseFramesCounter_1 : 16; /* 1E.6051.F:0 ROS Default = 0x0000 */ + /* Tx pause frame counter bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxPauseFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Pause Frames Counter Register: 1E.6054 */ +/* MSM System Rx Pause Frames Counter Register: 1E.6054 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6054.F:0 ROS MSM System Rx Pause Frames Counter 0 [F:0] + AQ_MsmSystemRxPauseFramesCounterRegister_HHD.u0.bits_0.msmSystemRxPauseFramesCounter_0 + + Default = 0x0000 + + Rx pause frame counter bits 15:0 + + Notes: + Valid pause frames received. */ + unsigned int msmSystemRxPauseFramesCounter_0 : 16; /* 1E.6054.F:0 ROS Default = 0x0000 */ + /* Rx pause frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6055.F:0 ROS MSM System Rx Pause Frames Counter 1 [F:0] + AQ_MsmSystemRxPauseFramesCounterRegister_HHD.u1.bits_1.msmSystemRxPauseFramesCounter_1 + + Default = 0x0000 + + Rx pause frame counter bits 31:16 + + Notes: + Valid pause frames received. */ + unsigned int msmSystemRxPauseFramesCounter_1 : 16; /* 1E.6055.F:0 ROS Default = 0x0000 */ + /* Rx pause frame counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxPauseFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Too Long Errors Counter Register: 1E.6058 */ +/* MSM System Rx Too Long Errors Counter Register: 1E.6058 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Too Long Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.6058.F:0 ROS MSM System Rx Too Long Errors Counter 0 [F:0] + AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD.u0.bits_0.msmSystemRxTooLongErrorsCounter_0 + + Default = 0x0000 + + Too-long errors counter bits 15:0 + + Notes: + Frame received exceeded the maximum length programmed with register FRM_LGTH. */ + unsigned int msmSystemRxTooLongErrorsCounter_0 : 16; /* 1E.6058.F:0 ROS Default = 0x0000 */ + /* Too-long errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Too Long Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.6059.F:0 ROS MSM System Rx Too Long Errors Counter 1 [F:0] + AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD.u1.bits_1.msmSystemRxTooLongErrorsCounter_1 + + Default = 0x0000 + + Too-long errors counter bits 31:16 + + Notes: + Frame received exceeded the maximum length programmed with register FRM_LGTH. */ + unsigned int msmSystemRxTooLongErrorsCounter_1 : 16; /* 1E.6059.F:0 ROS Default = 0x0000 */ + /* Too-long errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx In Range Length Errors Counter Register: 1E.605C */ +/* MSM System Rx In Range Length Errors Counter Register: 1E.605C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx In Range Length Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.605C.F:0 ROS MSM System Rx In Range Length Errors Counter 0 [F:0] + AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD.u0.bits_0.msmSystemRxInRangeLengthErrorsCounter_0 + + Default = 0x0000 + + In-range-length errors counter bits 15:0 + + Notes: + A count of frames with a length/type field value between 46 (VLAN: 42) and less than 0x0600, that does not match the number of payload data octets received. Should count also if length/type field is less than 46 (VLAN: 42) and the frame is longer than 64 bytes. */ + unsigned int msmSystemRxInRangeLengthErrorsCounter_0 : 16; /* 1E.605C.F:0 ROS Default = 0x0000 */ + /* In-range-length errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx In Range Length Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.605D.F:0 ROS MSM System Rx In Range Length Errors Counter 1 [F:0] + AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD.u1.bits_1.msmSystemRxInRangeLengthErrorsCounter_1 + + Default = 0x0000 + + In-range-length errors counter bits 31:16 + + Notes: + A count of frames with a length/type field value between 46 (VLAN: 42) and less than 0x0600, that does not match the number of payload data octets received. Should count also if length/type field is less than 46 (VLAN: 42) and the frame is longer than 64 bytes. */ + unsigned int msmSystemRxInRangeLengthErrorsCounter_1 : 16; /* 1E.605D.F:0 ROS Default = 0x0000 */ + /* In-range-length errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx VLAN Frames Counter Register: 1E.6060 */ +/* MSM System Tx VLAN Frames Counter Register: 1E.6060 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6060.F:0 ROS MSM System Tx VLAN Frames Counter 0 [F:0] + AQ_MsmSystemTxVlanFramesCounterRegister_HHD.u0.bits_0.msmSystemTxVlanFramesCounter_0 + + Default = 0x0000 + + Tx VLAN frames counter bits 15:0 + + Notes: + Valid VLAN tagged frames transmitted. */ + unsigned int msmSystemTxVlanFramesCounter_0 : 16; /* 1E.6060.F:0 ROS Default = 0x0000 */ + /* Tx VLAN frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6061.F:0 ROS MSM System Tx VLAN Frames Counter 1 [F:0] + AQ_MsmSystemTxVlanFramesCounterRegister_HHD.u1.bits_1.msmSystemTxVlanFramesCounter_1 + + Default = 0x0000 + + Tx VLAN frames counter bits 31:16 + + Notes: + Valid VLAN tagged frames transmitted. */ + unsigned int msmSystemTxVlanFramesCounter_1 : 16; /* 1E.6061.F:0 ROS Default = 0x0000 */ + /* Tx VLAN frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxVlanFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx VLAN Frames Counter Register: 1E.6064 */ +/* MSM System Rx VLAN Frames Counter Register: 1E.6064 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6064.F:0 ROS MSM System Rx VLAN Frames Counter 0 [F:0] + AQ_MsmSystemRxVlanFramesCounterRegister_HHD.u0.bits_0.msmSystemRxVlanFramesCounter_0 + + Default = 0x0000 + + Rx VLAN frames counter bits 15:0 + + Notes: + Valid VLAN tagged frames received. */ + unsigned int msmSystemRxVlanFramesCounter_0 : 16; /* 1E.6064.F:0 ROS Default = 0x0000 */ + /* Rx VLAN frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6065.F:0 ROS MSM System Rx VLAN Frames Counter 1 [F:0] + AQ_MsmSystemRxVlanFramesCounterRegister_HHD.u1.bits_1.msmSystemRxVlanFramesCounter_1 + + Default = 0x0000 + + Rx VLAN frames counter bits 31:16 + + Notes: + Valid VLAN tagged frames received. */ + unsigned int msmSystemRxVlanFramesCounter_1 : 16; /* 1E.6065.F:0 ROS Default = 0x0000 */ + /* Rx VLAN frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxVlanFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx Octets Counter Register: 1E.6068 */ +/* MSM System Tx Octets Counter Register: 1E.6068 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.6068.F:0 ROS MSM System Tx Octets Counter 0 [F:0] + AQ_MsmSystemTxOctetsCounterRegister_HHD.u0.bits_0.msmSystemTxOctetsCounter_0 + + Default = 0x0000 + + Tx octets counter bits 15:0 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmSystemTxOctetsCounter_0 : 16; /* 1E.6068.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.6069.F:0 ROS MSM System Tx Octets Counter 1 [F:0] + AQ_MsmSystemTxOctetsCounterRegister_HHD.u1.bits_1.msmSystemTxOctetsCounter_1 + + Default = 0x0000 + + Tx octets counter bits 31:16 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmSystemTxOctetsCounter_1 : 16; /* 1E.6069.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of MSM System Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.606A.F:0 ROS MSM System Tx Octets Counter 2 [F:0] + AQ_MsmSystemTxOctetsCounterRegister_HHD.u2.bits_2.msmSystemTxOctetsCounter_2 + + Default = 0x0000 + + Tx octets counter bits 47:32 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmSystemTxOctetsCounter_2 : 16; /* 1E.606A.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 47:32 */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of MSM System Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.606B.F:0 ROS MSM System Tx Octets Counter 3 [F:0] + AQ_MsmSystemTxOctetsCounterRegister_HHD.u3.bits_3.msmSystemTxOctetsCounter_3 + + Default = 0x0000 + + Tx octets counter bits 63:48 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmSystemTxOctetsCounter_3 : 16; /* 1E.606B.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 63:48 */ + } bits_3; + uint16_t word_3; + } u3; +} AQ_MsmSystemTxOctetsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Octets Counter Register: 1E.606C */ +/* MSM System Rx Octets Counter Register: 1E.606C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.606C.F:0 ROS MSM System Rx Octets Counter 0 [F:0] + AQ_MsmSystemRxOctetsCounterRegister_HHD.u0.bits_0.msmSystemRxOctetsCounter_0 + + Default = 0x0000 + + Rx octets counter bits 15:0 + + Notes: + All octets received except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames received. */ + unsigned int msmSystemRxOctetsCounter_0 : 16; /* 1E.606C.F:0 ROS Default = 0x0000 */ + /* Rx octets counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.606D.F:0 ROS MSM System Rx Octets Counter 1 [F:0] + AQ_MsmSystemRxOctetsCounterRegister_HHD.u1.bits_1.msmSystemRxOctetsCounter_1 + + Default = 0x0000 + + Rx octets counter bits 31:16 + + Notes: + All octets received except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames received. */ + unsigned int msmSystemRxOctetsCounter_1 : 16; /* 1E.606D.F:0 ROS Default = 0x0000 */ + /* Rx octets counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxOctetsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Unicast Frames Counter Register: 1E.6070 */ +/* MSM System Rx Unicast Frames Counter Register: 1E.6070 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6070.F:0 ROS MSM System Rx Unicast Frames Counter 0 [F:0] + AQ_MsmSystemRxUnicastFramesCounterRegister_HHD.u0.bits_0.msmSystemRxUnicastFramesCounter_0 + + Default = 0x0000 + + Rx unicast frames counter bits 15:0 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '0'. */ + unsigned int msmSystemRxUnicastFramesCounter_0 : 16; /* 1E.6070.F:0 ROS Default = 0x0000 */ + /* Rx unicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6071.F:0 ROS MSM System Rx Unicast Frames Counter 1 [F:0] + AQ_MsmSystemRxUnicastFramesCounterRegister_HHD.u1.bits_1.msmSystemRxUnicastFramesCounter_1 + + Default = 0x0000 + + Rx unicast frames counter bits 31:16 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '0'. */ + unsigned int msmSystemRxUnicastFramesCounter_1 : 16; /* 1E.6071.F:0 ROS Default = 0x0000 */ + /* Rx unicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxUnicastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Multicast Frames Counter Register: 1E.6074 */ +/* MSM System Rx Multicast Frames Counter Register: 1E.6074 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6074.F:0 ROS MSM System Rx Multicast Frames Counter 0 [F:0] + AQ_MsmSystemRxMulticastFramesCounterRegister_HHD.u0.bits_0.msmSystemRxMulticastFramesCounter_0 + + Default = 0x0000 + + Rx multicast frames counter bits 15:0 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '1' but not the broadcast address (all bits set '1' ). Pause frames are not counted. */ + unsigned int msmSystemRxMulticastFramesCounter_0 : 16; /* 1E.6074.F:0 ROS Default = 0x0000 */ + /* Rx multicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6075.F:0 ROS MSM System Rx Multicast Frames Counter 1 [F:0] + AQ_MsmSystemRxMulticastFramesCounterRegister_HHD.u1.bits_1.msmSystemRxMulticastFramesCounter_1 + + Default = 0x0000 + + Rx multicast frames counter bits 31:16 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '1' but not the broadcast address (all bits set '1' ). Pause frames are not counted. */ + unsigned int msmSystemRxMulticastFramesCounter_1 : 16; /* 1E.6075.F:0 ROS Default = 0x0000 */ + /* Rx multicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxMulticastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Broadcast Frames Counter Register: 1E.6078 */ +/* MSM System Rx Broadcast Frames Counter Register: 1E.6078 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6078.F:0 ROS MSM System Rx Broadcast Frames Counter 0 [F:0] + AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD.u0.bits_0.msmSystemRxBroadcastFramesCounter_0 + + Default = 0x0000 + + Rx broadcast frames counter bits 15:0 + + Notes: + Incremented with each valid frame received on the receive FIFO interface (FIFO) and all bits of the destination address were set '1'. */ + unsigned int msmSystemRxBroadcastFramesCounter_0 : 16; /* 1E.6078.F:0 ROS Default = 0x0000 */ + /* Rx broadcast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6079.F:0 ROS MSM System Rx Broadcast Frames Counter 1 [F:0] + AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD.u1.bits_1.msmSystemRxBroadcastFramesCounter_1 + + Default = 0x0000 + + Rx broadcast frames counter bits 31:16 + + Notes: + Incremented with each valid frame received on the receive FIFO interface (FIFO) and all bits of the destination address were set '1'. */ + unsigned int msmSystemRxBroadcastFramesCounter_1 : 16; /* 1E.6079.F:0 ROS Default = 0x0000 */ + /* Rx broadcast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx Errors Counter Register: 1E.607C */ +/* MSM System Tx Errors Counter Register: 1E.607C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.607C.F:0 ROS MSM System Tx Errors Counter 0 [F:0] + AQ_MsmSystemTxErrorsCounterRegister_HHD.u0.bits_0.msmSystemTxErrorsCounter_0 + + Default = 0x0000 + + Rx errors counter bits 15:0 + + Notes: + Number of frames transmitted with error: + - FIFO Overflow Errors + - FIFO Underflow Errors */ + unsigned int msmSystemTxErrorsCounter_0 : 16; /* 1E.607C.F:0 ROS Default = 0x0000 */ + /* Rx errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.607D.F:0 ROS MSM System Tx Errors Counter 1 [F:0] + AQ_MsmSystemTxErrorsCounterRegister_HHD.u1.bits_1.msmSystemTxErrorsCounter_1 + + Default = 0x0000 + + Tx errors counter bits 31:16 + + Notes: + Number of frames transmitted with error: + - FIFO Overflow Errors + - FIFO Underflow Errors */ + unsigned int msmSystemTxErrorsCounter_1 : 16; /* 1E.607D.F:0 ROS Default = 0x0000 */ + /* Tx errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx Unicast Frames Counter Register: 1E.6084 */ +/* MSM System Tx Unicast Frames Counter Register: 1E.6084 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6084.F:0 ROS MSM System Tx Unicast Frames Counter 0 [F:0] + AQ_MsmSystemTxUnicastFramesCounterRegister_HHD.u0.bits_0.msmSystemTxUnicastFramesCounter_0 + + Default = 0x0000 + + Tx unicast frames counter bits 15:0 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '0'. */ + unsigned int msmSystemTxUnicastFramesCounter_0 : 16; /* 1E.6084.F:0 ROS Default = 0x0000 */ + /* Tx unicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6085.F:0 ROS MSM System Tx Unicast Frames Counter 1 [F:0] + AQ_MsmSystemTxUnicastFramesCounterRegister_HHD.u1.bits_1.msmSystemTxUnicastFramesCounter_1 + + Default = 0x0000 + + Tx unicast frames counter bits 31:16 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '0'. */ + unsigned int msmSystemTxUnicastFramesCounter_1 : 16; /* 1E.6085.F:0 ROS Default = 0x0000 */ + /* Tx unicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxUnicastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx Multicast Frames Counter Register: 1E.6088 */ +/* MSM System Tx Multicast Frames Counter Register: 1E.6088 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6088.F:0 ROS MSM System Tx Multicast Frames Counter 0 [F:0] + AQ_MsmSystemTxMulticastFramesCounterRegister_HHD.u0.bits_0.msmSystemTxMulticastFramesCounter_0 + + Default = 0x0000 + + Tx multicast frames counter bits 15:0 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '1' but not the broadcast address (all bits '1'). */ + unsigned int msmSystemTxMulticastFramesCounter_0 : 16; /* 1E.6088.F:0 ROS Default = 0x0000 */ + /* Tx multicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6089.F:0 ROS MSM System Tx Multicast Frames Counter 1 [F:0] + AQ_MsmSystemTxMulticastFramesCounterRegister_HHD.u1.bits_1.msmSystemTxMulticastFramesCounter_1 + + Default = 0x0000 + + Tx multicast frames counter bits 31:16 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '1' but not the broadcast address (all bits '1'). */ + unsigned int msmSystemTxMulticastFramesCounter_1 : 16; /* 1E.6089.F:0 ROS Default = 0x0000 */ + /* Tx multicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxMulticastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx Broadcast Frames Counter Register: 1E.608C */ +/* MSM System Tx Broadcast Frames Counter Register: 1E.608C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.608C.F:0 ROS MSM System Tx Broadcast Frames Counter 0 [F:0] + AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD.u0.bits_0.msmSystemTxBroadcastFramesCounter_0 + + Default = 0x0000 + + Tx broadcast frames counter bits 15:0 + + Notes: + Incremented with each frame written to the FIFO interface and all bits of the destination address set to '1'. */ + unsigned int msmSystemTxBroadcastFramesCounter_0 : 16; /* 1E.608C.F:0 ROS Default = 0x0000 */ + /* Tx broadcast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.608D.F:0 ROS MSM System Tx Broadcast Frames Counter 1 [F:0] + AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD.u1.bits_1.msmSystemTxBroadcastFramesCounter_1 + + Default = 0x0000 + + Tx broadcast frames counter bits 31:16 + + Notes: + Incremented with each frame written to the FIFO interface and all bits of the destination address set to '1'. */ + unsigned int msmSystemTxBroadcastFramesCounter_1 : 16; /* 1E.608D.F:0 ROS Default = 0x0000 */ + /* Tx broadcast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Errors Counter Register: 1E.60C8 */ +/* MSM System Rx Errors Counter Register: 1E.60C8 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.60C8.F:0 ROS MSM System Rx Errors Counter 0 [F:0] + AQ_MsmSystemRxErrorsCounterRegister_HHD.u0.bits_0.msmSystemRxErrorsCounter_0 + + Default = 0x0000 + + Rx errors counter bits 15:0 + + Notes: + Number of frames received with error: + - FIFO Overflow Errors + - CRC Errors + - Payload Length Errors + - Jabber and Oversized Errors + - Alignment Errors + - The dedicated Error Code (0xfe, not a code error) was received */ + unsigned int msmSystemRxErrorsCounter_0 : 16; /* 1E.60C8.F:0 ROS Default = 0x0000 */ + /* Rx errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.60C9.F:0 ROS MSM System Rx Errors Counter 1 [F:0] + AQ_MsmSystemRxErrorsCounterRegister_HHD.u1.bits_1.msmSystemRxErrorsCounter_1 + + Default = 0x0000 + + Rx errors counter bits 31:16 + + Notes: + Number of frames received with error: + - FIFO Overflow Errors + - CRC Errors + - Payload Length Errors + - Jabber and Oversized Errors + - Alignment Errors + - The dedicated Error Code (0xfe, not a code error) was received */ + unsigned int msmSystemRxErrorsCounter_1 : 16; /* 1E.60C9.F:0 ROS Default = 0x0000 */ + /* Rx errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress VLAN TPID 0 Register: 1E.8006 */ +/* MSS Ingress VLAN TPID 0 Register: 1E.8006 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress VLAN TPID 0 Register */ + union + { + struct + { + /*! \brief 1E.8006.F:0 R/W MSS Ingress VLAN STag [F:0] + AQ_MssIngressVlanTpid_0Register_HHD.u0.bits_0.mssIngressVlanStag + + Default = 0x0000 + + STag TPID + + + Notes: + Service Tag Protocol Identifier (TPID) values to identify a VLAN tag. The " See SEC Egress VLAN CP Tag Parse STag " bit must be set to 1 for the incoming packet's TPID to be parsed. */ + unsigned int mssIngressVlanStag : 16; /* 1E.8006.F:0 R/W Default = 0x0000 */ + /* STag TPID + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress VLAN TPID 0 Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressVlanTpid_0Register_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress VLAN TPID 1 Register: 1E.8008 */ +/* MSS Ingress VLAN TPID 1 Register: 1E.8008 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress VLAN TPID 1 Register */ + union + { + struct + { + /*! \brief 1E.8008.F:0 R/W MSS Ingress VLAN QTag [F:0] + AQ_MssIngressVlanTpid_1Register_HHD.u0.bits_0.mssIngressVlanQtag + + Default = 0x0000 + + QTag TPID + + + Notes: + Customer Tag Protocol Identifier (TPID) values to identify a VLAN tag. The " See SEC Egress VLAN CP Tag Parse QTag " bit must be set to 1 for the incoming packet's TPID to be parsed. */ + unsigned int mssIngressVlanQtag : 16; /* 1E.8008.F:0 R/W Default = 0x0000 */ + /* QTag TPID + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress VLAN TPID 1 Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressVlanTpid_1Register_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress VLAN Control Register: 1E.800A */ +/* MSS Ingress VLAN Control Register: 1E.800A */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress VLAN Control Register */ + union + { + struct + { + /*! \brief 1E.800A.F:0 R/W MSS Ingress VLAN UP Map Table LSW [F:0] + AQ_MssIngressVlanControlRegister_HHD.u0.bits_0.mssIngressVlanUpMapTableLSW + + Default = 0x0000 + + Map table bits 15:0 + + + Notes: + If there is a customer TPID Tag match and no service TPID Tag match or the service TPID Tag match is disabled, the outer TAG's PCP is used to index into this map table to generate the packets user priority. + 2:0 : UP value for customer Tag PCP 0x0 + 5:3: UP value for customer Tag PCP 0x0 + 8:6 : UP value for customer Tag PCP 0x0 + 11:9 : UP value for customer Tag PCP 0x0 + 14:12 : UP value for customer Tag PCP 0x0 + 17:15 : UP value for customer Tag PCP 0x0 */ + unsigned int mssIngressVlanUpMapTableLSW : 16; /* 1E.800A.F:0 R/W Default = 0x0000 */ + /* Map table bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress VLAN Control Register */ + union + { + struct + { + /*! \brief 1E.800B.7:0 R/W MSS Ingress VLAN UP Map Table MSW [17:10] + AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanUpMapTableMSW + + Default = 0x00 + + UP Map table bits 23:16 + + + Notes: + If there is a customer TPID Tag match and no service TPID Tag match or the service TPID Tag match is disabled, the outer TAG's PCP is used to index into this map table to generate the packets user priority. + 2:0 : UP value for customer Tag PCP 0x0 + 5:3: UP value for customer Tag PCP 0x0 + 8:6 : UP value for customer Tag PCP 0x0 + 11:9 : UP value for customer Tag PCP 0x0 + 14:12 : UP value for customer Tag PCP 0x0 + 17:15 : UP value for customer Tag PCP 0x0 + 20:18 : UP value for customer Tag PCP 0x0 + 23:21 : UP value for customer Tag PCP 0x0 */ + unsigned int mssIngressVlanUpMapTableMSW : 8; /* 1E.800B.7:0 R/W Default = 0x00 */ + /* UP Map table bits 23:16 + */ + /*! \brief 1E.800B.A:8 R/W MSS Ingress VLAN UP Default [2:0] + AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanUpDefault + + Default = 0x0 + + UP default + + + Notes: + User priority default */ + unsigned int mssIngressVlanUpDefault : 3; /* 1E.800B.A:8 R/W Default = 0x0 */ + /* UP default + */ + /*! \brief 1E.800B.B R/W MSS Ingress VLAN STag UP Parse Enable + AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanStagUpParseEnable + + Default = 0x0 + + VLAN CP Tag STag UP enable + + + Notes: + Enable controlled port service VLAN service Tag user priority field parsing. */ + unsigned int mssIngressVlanStagUpParseEnable : 1; /* 1E.800B.B R/W Default = 0x0 */ + /* VLAN CP Tag STag UP enable + */ + /*! \brief 1E.800B.C R/W MSS Ingress VLAN QTag UP Parse Enable + AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanQtagUpParseEnable + + Default = 0x0 + + VLAN CP Tag QTag UP enable + + + Notes: + Enable controlled port customer VLAN customer Tag user priority field parsing. */ + unsigned int mssIngressVlanQtagUpParseEnable : 1; /* 1E.800B.C R/W Default = 0x0 */ + /* VLAN CP Tag QTag UP enable + */ + /*! \brief 1E.800B.D R/W MSS Ingress VLAN QinQ Parse Enable + AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanQinqParseEnable + + Default = 0x0 + + VLAN CP Tag Parse QinQ + + + Notes: + Enable controlled port VLAN QinQ Tag parsing. When this bit is set to 1 both the outer and inner VLAN Tags will be parsed. */ + unsigned int mssIngressVlanQinqParseEnable : 1; /* 1E.800B.D R/W Default = 0x0 */ + /* VLAN CP Tag Parse QinQ + */ + /*! \brief 1E.800B.E R/W MSS Ingress VLAN STag Parse Enable + AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanStagParseEnable + + Default = 0x0 + + 1 = Enable VLAN STag parsing + + + Notes: + Enable controlled port VLAN service Tag parsing. When this bit is set to 1, the incoming packets outer TPID will be compared with the configured " See MSS Ingress VLAN Stag [F:0] " for matching. If the " See SEC Egress VLAN CP Tag Parse QinQ " bit is set to1, this will also be used to compare the incoming packet's inner TPID. */ + unsigned int mssIngressVlanStagParseEnable : 1; /* 1E.800B.E R/W Default = 0x0 */ + /* 1 = Enable VLAN STag parsing + */ + /*! \brief 1E.800B.F R/W MSS Ingress VLAN QTag Parse Enable + AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanQtagParseEnable + + Default = 0x0 + + 1 = Enable VLAN QTag parsing + + + Notes: + Enable controlled port VLAN customer Tag parsing. When this bit is set to 1, the incoming packet's outer TPID will be compared with the configured " See MSS Ingress VLAN QTag [F:0] " for matching. If the " See SEC Egress VLAN CP Tag Parse QinQ " bit is set to1, this will also be used to compare the incoming packet's inner TPID. */ + unsigned int mssIngressVlanQtagParseEnable : 1; /* 1E.800B.F R/W Default = 0x0 */ + /* 1 = Enable VLAN QTag parsing + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressVlanControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress MTU Size Control Register: 1E.800C */ +/* MSS Ingress MTU Size Control Register: 1E.800C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress MTU Size Control Register */ + union + { + struct + { + /*! \brief 1E.800C.F:0 R/W MSS Ingress Controlled Packet MTU Size [F:0] + AQ_MssIngressMtuSizeControlRegister_HHD.u0.bits_0.mssIngressControlledPacketMtuSize + + Default = 0x05DC + + Maximum transmission unit for controlled packet + + + Notes: + Maximum transmission unit of controlled packet */ + unsigned int mssIngressControlledPacketMtuSize : 16; /* 1E.800C.F:0 R/W Default = 0x05DC */ + /* Maximum transmission unit for controlled packet + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress MTU Size Control Register */ + union + { + struct + { + /*! \brief 1E.800D.F:0 R/W MSS Ingress Uncontrolled Packet MTU Size [F:0] + AQ_MssIngressMtuSizeControlRegister_HHD.u1.bits_1.mssIngressUncontrolledPacketMtuSize + + Default = 0x05DC + + Maximum transmission unit for uncontrolled packet + + + Notes: + Maximum transmission unit of uncontrolled packet */ + unsigned int mssIngressUncontrolledPacketMtuSize : 16; /* 1E.800D.F:0 R/W Default = 0x05DC */ + /* Maximum transmission unit for uncontrolled packet + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressMtuSizeControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress Control Register: 1E.800E */ +/* MSS Ingress Control Register: 1E.800E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress Control Register */ + union + { + struct + { + /*! \brief 1E.800E.0 R/W MSS Ingress Soft Reset + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressSoftReset + + Default = 0x0 + + 1 = Soft reset + + + Notes: + S/W reset */ + unsigned int mssIngressSoftReset : 1; /* 1E.800E.0 R/W Default = 0x0 */ + /* 1 = Soft reset + */ + /*! \brief 1E.800E.1 R/W MSS Ingress Operation Point To Point + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressOperationPointToPoint + + Default = 0x0 + + 1 = Enable the SCI for authorization default + + + Notes: + The default SCI for authorization is configured in See MSS Ingress SCI Default [F:0] See MSS Ingress SCI Default [1F:10] , See MSS Ingress SCI Default [2F:20] , and See MSS Ingress SCI Default [3F:30] . */ + unsigned int mssIngressOperationPointToPoint : 1; /* 1E.800E.1 R/W Default = 0x0 */ + /* 1 = Enable the SCI for authorization default + */ + /*! \brief 1E.800E.2 R/W MSS Ingress Create SCI + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressCreateSci + + Default = 0x0 + + 0 = SCI from IGPRC LUT + + + Notes: + If the SCI is not in the packet and this bit is set to 0, the SCI will be taken from the IGPRC LUT. */ + unsigned int mssIngressCreateSci : 1; /* 1E.800E.2 R/W Default = 0x0 */ + /* 0 = SCI from IGPRC LUT + */ + /*! \brief 1E.800E.3 R/W MSS Ingress Mask Short Length Error + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressMaskShortLengthError + + Default = 0x0 + + Unused + + + Notes: + Unused */ + unsigned int mssIngressMaskShortLengthError : 1; /* 1E.800E.3 R/W Default = 0x0 */ + /* Unused + */ + /*! \brief 1E.800E.4 R/W MSS Ingress Drop Kay Packet + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressDropKayPacket + + Default = 0x0 + + 1 = Drop KaY packets + + + Notes: + Decides whether KaY packets have to be dropped */ + unsigned int mssIngressDropKayPacket : 1; /* 1E.800E.4 R/W Default = 0x0 */ + /* 1 = Drop KaY packets + */ + /*! \brief 1E.800E.5 R/W MSS Ingress Drop IGPRC Miss + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressDropIgprcMiss + + Default = 0x0 + + 1 = Drop IGPRC miss packets + + + Notes: + Decides whether Ingress Pre-Security Classification (IGPRC) LUT miss packets are to be dropped */ + unsigned int mssIngressDropIgprcMiss : 1; /* 1E.800E.5 R/W Default = 0x0 */ + /* 1 = Drop IGPRC miss packets + */ + /*! \brief 1E.800E.6 R/W MSS Ingress Check ICV + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressCheckIcv + + Default = 0x0 + + Unused + + + Notes: + Unused */ + unsigned int mssIngressCheckIcv : 1; /* 1E.800E.6 R/W Default = 0x0 */ + /* Unused + */ + /*! \brief 1E.800E.7 R/W MSS Ingress Clear Global Time + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressClearGlobalTime + + Default = 0x0 + + 1 = Clear global time + + + Notes: + Clear global time */ + unsigned int mssIngressClearGlobalTime : 1; /* 1E.800E.7 R/W Default = 0x0 */ + /* 1 = Clear global time + */ + /*! \brief 1E.800E.8 R/W MSS Ingress Clear Count + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressClearCount + + Default = 0x0 + + 1 = Clear all MIB counters + + + Notes: + If this bit is set to 1, all MIB counters will be cleared. */ + unsigned int mssIngressClearCount : 1; /* 1E.800E.8 R/W Default = 0x0 */ + /* 1 = Clear all MIB counters + */ + /*! \brief 1E.800E.9 R/W MSS Ingress High Priority + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressHighPriority + + Default = 0x0 + + 1 = MIB counter clear on read enable + + + Notes: + If this bit is set to 1, read is given high priority and the MIB count value becomes 0 after read. */ + unsigned int mssIngressHighPriority : 1; /* 1E.800E.9 R/W Default = 0x0 */ + /* 1 = MIB counter clear on read enable + */ + /*! \brief 1E.800E.A R/W MSS Ingress Remove SECTag + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressRemoveSectag + + Default = 0x0 + + 1 = Enable removal of SECTag + + + Notes: + If this bit is set and either of the following two conditions occurs, the SECTag will be removed. + Controlled packet and either the SA or SC is invalid. + IGPRC miss. */ + unsigned int mssIngressRemoveSectag : 1; /* 1E.800E.A R/W Default = 0x0 */ + /* 1 = Enable removal of SECTag + */ + /*! \brief 1E.800E.C:B R/W MSS Ingress Global Validate Frames [1:0] + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressGlobalValidateFrames + + Default = 0x0 + + Default validate frames configuration + + + Notes: + If the SC is invalid or if an IGPRC miss packet condition occurs, this default will be used for the validate frames configuration instead of the validate frame entry in the Ingress SC Table (IGSCT). */ + unsigned int mssIngressGlobalValidateFrames : 2; /* 1E.800E.C:B R/W Default = 0x0 */ + /* Default validate frames configuration + */ + /*! \brief 1E.800E.D R/W MSS Ingress ICV LSB 8 Bytes Enable + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressIcvLsb_8BytesEnable + + Default = 0x0 + + 1 = Use LSB + 0 = Use MSB + + + + Notes: + This bit selects MSB or LSB 8 bytes selection in the case where the ICV is 8 bytes. + 0 = MSB is used. */ + unsigned int mssIngressIcvLsb_8BytesEnable : 1; /* 1E.800E.D R/W Default = 0x0 */ + /* 1 = Use LSB + 0 = Use MSB + + */ + unsigned int reserved0 : 2; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress Control Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress SA Control Register: 1E.8010 */ +/* MSS Ingress SA Control Register: 1E.8010 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress SA Control Register */ + union + { + struct + { + /*! \brief 1E.8010.F:0 R/W MSS Ingress SA Threshold LSW [F:0] + AQ_MssIngressSaControlRegister_HHD.u0.bits_0.mssIngressSaThresholdLSW + + Default = 0x0000 + + SA threshold bits 15:0 + + + Notes: + Ingress PN threshold to generate SA threshold interrupt. */ + unsigned int mssIngressSaThresholdLSW : 16; /* 1E.8010.F:0 R/W Default = 0x0000 */ + /* SA threshold bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress SA Control Register */ + union + { + struct + { + /*! \brief 1E.8011.F:0 R/W MSS Ingress SA Threshold MSW [1F:10] + AQ_MssIngressSaControlRegister_HHD.u1.bits_1.mssIngressSaThresholdMSW + + Default = 0x0000 + + SA threshold bits 31:16 + + + Notes: + Ingress PN threshold to generate SA threshold interrupt. */ + unsigned int mssIngressSaThresholdMSW : 16; /* 1E.8011.F:0 R/W Default = 0x0000 */ + /* SA threshold bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressSaControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress Interrupt Status Register: 1E.802E */ +/* MSS Ingress Interrupt Status Register: 1E.802E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress Interrupt Status Register */ + union + { + struct + { + /*! \brief 1E.802E.0 COW MSS Master Ingress Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssMasterIngressInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when any one of the above interrupt and the corresponding interrupt enable are both set. The interrupt enable for this bit must also be set for this bit to be set. */ + unsigned int mssMasterIngressInterrupt : 1; /* 1E.802E.0 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.1 COW MSS Ingress SA Expired Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressSaExpiredInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when the SA PN reaches all ones saturation. */ + unsigned int mssIngressSaExpiredInterrupt : 1; /* 1E.802E.1 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.2 COW MSS Ingress SA Threshold Expired Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressSaThresholdExpiredInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when the SA PN reaches the See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . */ + unsigned int mssIngressSaThresholdExpiredInterrupt : 1; /* 1E.802E.2 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.3 COW MSS Ingress ICV Error Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressIcvErrorInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. */ + unsigned int mssIngressIcvErrorInterrupt : 1; /* 1E.802E.3 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.4 COW MSS Ingress Replay Error Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressReplayErrorInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. */ + unsigned int mssIngressReplayErrorInterrupt : 1; /* 1E.802E.4 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.5 COW MSS Ingress MIB Saturation Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressMibSaturationInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when the MIB counters reaches all ones saturation. */ + unsigned int mssIngressMibSaturationInterrupt : 1; /* 1E.802E.5 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.6 COW MSS Ingress ECC Error Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressEccErrorInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. */ + unsigned int mssIngressEccErrorInterrupt : 1; /* 1E.802E.6 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.7 COW MSS Ingress TCI E/C Error Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressTciE_cErrorInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This error occurs when the TCI E bit is 1 and the TCI C bit is 0. The packet is not dropped, uncontrolled, or untagged. */ + unsigned int mssIngressTciE_cErrorInterrupt : 1; /* 1E.802E.7 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.8 COW MSS Ingress IGPOC Miss Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressIgpocMissInterrupt + + Default = 0x0 + + 1 = Interrupt + + */ + unsigned int mssIngressIgpocMissInterrupt : 1; /* 1E.802E.8 COW Default = 0x0 */ + /* 1 = Interrupt + */ + unsigned int reserved0 : 7; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress Interrupt Status Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressInterruptStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress Interrupt Mask Register: 1E.8030 */ +/* MSS Ingress Interrupt Mask Register: 1E.8030 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress Interrupt Mask Register */ + union + { + struct + { + /*! \brief 1E.8030.0 R/W MSS Ingress Master Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressMasterInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressMasterInterruptEnable : 1; /* 1E.8030.0 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.1 R/W MSS Ingress SA Expired Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressSaExpiredInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressSaExpiredInterruptEnable : 1; /* 1E.8030.1 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.2 R/W MSS Ingress SA Threshold Expired Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressSaThresholdExpiredInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressSaThresholdExpiredInterruptEnable : 1; /* 1E.8030.2 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.3 R/W MSS Ingress ICV Error Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressIcvErrorInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressIcvErrorInterruptEnable : 1; /* 1E.8030.3 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.4 R/W MSS Ingress Replay Error Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressReplayErrorInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressReplayErrorInterruptEnable : 1; /* 1E.8030.4 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.5 R/W MSS Ingress MIB Saturation Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressMibSaturationInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressMibSaturationInterruptEnable : 1; /* 1E.8030.5 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.6 R/W MSS Ingress ECC Error Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressEccErrorInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressEccErrorInterruptEnable : 1; /* 1E.8030.6 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.7 R/W MSS Ingress TCI E/C Error Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressTciE_cErrorInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressTciE_cErrorInterruptEnable : 1; /* 1E.8030.7 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.8 R/W MSS Ingress IGPOC Miss Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressIgpocMissInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressIgpocMissInterruptEnable : 1; /* 1E.8030.8 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + unsigned int reserved0 : 7; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress Interrupt Mask Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressInterruptMaskRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress SA ICV Error Status Register: 1E.8032 */ +/* MSS Ingress SA ICV Error Status Register: 1E.8032 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress SA ICV Error Status Register */ + union + { + struct + { + /*! \brief 1E.8032.F:0 COW MSS Ingress SA ICV Error LSW [F:0] + AQ_MssIngressSaIcvErrorStatusRegister_HHD.u0.bits_0.mssIngressSaIcvErrorLSW + + Default = 0x0000 + + SA ICV error bits 15:0 + + + Notes: + When set, these bits identify the SA that has an ICV error. Write these bits to 1 to clear. */ + unsigned int mssIngressSaIcvErrorLSW : 16; /* 1E.8032.F:0 COW Default = 0x0000 */ + /* SA ICV error bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress SA ICV Error Status Register */ + union + { + struct + { + /*! \brief 1E.8033.F:0 COW MSS Ingress SA ICV Error MSW [1F:10] + AQ_MssIngressSaIcvErrorStatusRegister_HHD.u1.bits_1.mssIngressSaIcvErrorMSW + + Default = 0x0000 + + SA ICV error bits 31:16 + + + Notes: + When set, these bits identify the SA that has an ICV error. Write these bits to 1 to clear. */ + unsigned int mssIngressSaIcvErrorMSW : 16; /* 1E.8033.F:0 COW Default = 0x0000 */ + /* SA ICV error bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressSaIcvErrorStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress SA Replay Error Status Register: 1E.8034 */ +/* MSS Ingress SA Replay Error Status Register: 1E.8034 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress SA Replay Error Status Register */ + union + { + struct + { + /*! \brief 1E.8034.F:0 COW MSS Ingress SA Replay Error LSW [F:0] + AQ_MssIngressSaReplayErrorStatusRegister_HHD.u0.bits_0.mssIngressSaReplayErrorLSW + + Default = 0x0000 + + SA replay error bits 15:0 + + + Notes: + When set, these bits identify the SA that has a replay error. Write these bits to 1 to clear. */ + unsigned int mssIngressSaReplayErrorLSW : 16; /* 1E.8034.F:0 COW Default = 0x0000 */ + /* SA replay error bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress SA Replay Error Status Register */ + union + { + struct + { + /*! \brief 1E.8035.F:0 COW MSS Ingress SA Replay Error MSW [1F:10] + AQ_MssIngressSaReplayErrorStatusRegister_HHD.u1.bits_1.mssIngressSaReplayErrorMSW + + Default = 0x0000 + + SA replay error bits 31:16 + + + Notes: + When set, these bits identify the SA that has a replay error. Write these bits to 1 to clear. */ + unsigned int mssIngressSaReplayErrorMSW : 16; /* 1E.8035.F:0 COW Default = 0x0000 */ + /* SA replay error bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressSaReplayErrorStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress SA Expired Status Register: 1E.8036 */ +/* MSS Ingress SA Expired Status Register: 1E.8036 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress SA Expired Status Register */ + union + { + struct + { + /*! \brief 1E.8036.F:0 ROS MSS Ingress SA Expired LSW [F:0] + AQ_MssIngressSaExpiredStatusRegister_HHD.u0.bits_0.mssIngressSaExpiredLSW + + Default = 0x0000 + + SA expired bits 15:0 + + + Notes: + When set, these bits identify the SA that has expired when the SA PN reaches all-ones saturation. Write these bits to 1 to clear. */ + unsigned int mssIngressSaExpiredLSW : 16; /* 1E.8036.F:0 ROS Default = 0x0000 */ + /* SA expired bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress SA Expired Status Register */ + union + { + struct + { + /*! \brief 1E.8037.F:0 ROS MSS Ingress SA Expired MSW [1F:10] + AQ_MssIngressSaExpiredStatusRegister_HHD.u1.bits_1.mssIngressSaExpiredMSW + + Default = 0x0000 + + SA expired bits 31:16 + + + Notes: + When set, these bits identify the SA that has expired when the SA PN reaches all-ones saturation. Write these bits to 1 to clear. */ + unsigned int mssIngressSaExpiredMSW : 16; /* 1E.8037.F:0 ROS Default = 0x0000 */ + /* SA expired bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressSaExpiredStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress SA Threshold Expired Status Register: 1E.8038 */ +/* MSS Ingress SA Threshold Expired Status Register: 1E.8038 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress SA Threshold Expired Status Register */ + union + { + struct + { + /*! \brief 1E.8038.F:0 ROS MSS Ingress SA Threshold Expired LSW [F:0] + AQ_MssIngressSaThresholdExpiredStatusRegister_HHD.u0.bits_0.mssIngressSaThresholdExpiredLSW + + Default = 0x0000 + + SA threshold expired bits 15:0 + + + Notes: + When set, these bits identify the SA that has expired when the SA PN has reached the configured threshold See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . Write these bits to 1 to clear. */ + unsigned int mssIngressSaThresholdExpiredLSW : 16; /* 1E.8038.F:0 ROS Default = 0x0000 */ + /* SA threshold expired bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress SA Threshold Expired Status Register */ + union + { + struct + { + /*! \brief 1E.8039.F:0 ROS MSS Ingress SA Threshold Expired MSW [1F:10] + AQ_MssIngressSaThresholdExpiredStatusRegister_HHD.u1.bits_1.mssIngressSaThresholdExpiredMSW + + Default = 0x0000 + + SA threshold expired bits 31:16 + + + Notes: + When set, these bits identify the SA that has expired when the SA PN has reached the configured threshold See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . Write these bits to 1 to clear. */ + unsigned int mssIngressSaThresholdExpiredMSW : 16; /* 1E.8039.F:0 ROS Default = 0x0000 */ + /* SA threshold expired bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressSaThresholdExpiredStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress ECC Interrupt Status Register: 1E.803A */ +/* MSS Ingress ECC Interrupt Status Register: 1E.803A */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress ECC Interrupt Status Register */ + union + { + struct + { + /*! \brief 1E.803A.F:0 R/W MSS Ingress SA ECC Error Interrupt LSW [F:0] + AQ_MssIngressEccInterruptStatusRegister_HHD.u0.bits_0.mssIngressSaEccErrorInterruptLSW + + Default = 0x0000 + + SA ECC error interrupt bits 15:0 + + + Notes: + When set to 1, indicates that an ECC error occured for the SA. */ + unsigned int mssIngressSaEccErrorInterruptLSW : 16; /* 1E.803A.F:0 R/W Default = 0x0000 */ + /* SA ECC error interrupt bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress ECC Interrupt Status Register */ + union + { + struct + { + /*! \brief 1E.803B.F:0 R/W MSS Ingress SA ECC Error Interrupt MSW [1F:10] + AQ_MssIngressEccInterruptStatusRegister_HHD.u1.bits_1.mssIngressSaEccErrorInterruptMSW + + Default = 0x0000 + + SA ECC error interrupt bits 31:16 + + + Notes: + When set to 1, indicates that an ECC error occured for the SA. */ + unsigned int mssIngressSaEccErrorInterruptMSW : 16; /* 1E.803B.F:0 R/W Default = 0x0000 */ + /* SA ECC error interrupt bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressEccInterruptStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress LUT Address Control Register: 1E.8080 */ +/* MSS Ingress LUT Address Control Register: 1E.8080 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress LUT Address Control Register */ + union + { + struct + { + /*! \brief 1E.8080.8:0 R/W MSS Ingress LUT Address [8:0] + AQ_MssIngressLutAddressControlRegister_HHD.u0.bits_0.mssIngressLutAddress + + Default = 0x000 + + LUT address + + */ + unsigned int mssIngressLutAddress : 9; /* 1E.8080.8:0 R/W Default = 0x000 */ + /* LUT address + */ + unsigned int reserved0 : 3; + /*! \brief 1E.8080.F:C R/W MSS Ingress LUT Select [3:0] + AQ_MssIngressLutAddressControlRegister_HHD.u0.bits_0.mssIngressLutSelect + + Default = 0x0 + + LUT select + + + Notes: + 0x0 : Ingress Pre-Security MAC Control FIlter (IGPRCTLF) LUT + 0x1 : Ingress Pre-Security Classification LUT (IGPRC) + 0x2 : Ingress Packet Format (IGPFMT) SAKey LUT + 0x3 : Ingress Packet Format (IGPFMT) SC/SA LUT + 0x4 : Ingress Post-Security Classification LUT (IGPOC) + 0x5 : Ingress Post-Security MAC Control Filter (IGPOCTLF) LUT + 0x6 : Ingress MIB (IGMIB) */ + unsigned int mssIngressLutSelect : 4; /* 1E.8080.F:C R/W Default = 0x0 */ + /* LUT select + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_MssIngressLutAddressControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress LUT Control Register: 1E.8081 */ +/* MSS Ingress LUT Control Register: 1E.8081 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress LUT Control Register */ + union + { + struct + { + unsigned int reserved0 : 14; + /*! \brief 1E.8081.E R/W MSS Ingress LUT Read + AQ_MssIngressLutControlRegister_HHD.u0.bits_0.mssIngressLutRead + + Default = 0x0 + + 1 = LUT read + + + Notes: + Setting this bit to 1, will read the LUT. This bit will automatically clear to 0. */ + unsigned int mssIngressLutRead : 1; /* 1E.8081.E R/W Default = 0x0 */ + /* 1 = LUT read + */ + /*! \brief 1E.8081.F R/W MSS Ingress LUT Write + AQ_MssIngressLutControlRegister_HHD.u0.bits_0.mssIngressLutWrite + + Default = 0x0 + + 1 = LUT write + + + Notes: + Setting this bit to 1, will write the LUT. This bit will automatically clear to 0. */ + unsigned int mssIngressLutWrite : 1; /* 1E.8081.F R/W Default = 0x0 */ + /* 1 = LUT write + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_MssIngressLutControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress LUT Data Control Register: 1E.80A0 */ +/* MSS Ingress LUT Data Control Register: 1E.80A0 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A0.F:0 R/W MSS Ingress LUT Data 0 [F:0] + AQ_MssIngressLutDataControlRegister_HHD.u0.bits_0.mssIngressLutData_0 + + Default = 0x0000 + + LUT data bits 15:0 + + */ + unsigned int mssIngressLutData_0 : 16; /* 1E.80A0.F:0 R/W Default = 0x0000 */ + /* LUT data bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A1.F:0 R/W MSS Ingress LUT Data 1 [1F:10] + AQ_MssIngressLutDataControlRegister_HHD.u1.bits_1.mssIngressLutData_1 + + Default = 0x0000 + + LUT data bits 31:16 + + */ + unsigned int mssIngressLutData_1 : 16; /* 1E.80A1.F:0 R/W Default = 0x0000 */ + /* LUT data bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A2.F:0 R/W MSS Ingress LUT Data 2 [2F:20] + AQ_MssIngressLutDataControlRegister_HHD.u2.bits_2.mssIngressLutData_2 + + Default = 0x0000 + + LUT data bits 47:32 + + */ + unsigned int mssIngressLutData_2 : 16; /* 1E.80A2.F:0 R/W Default = 0x0000 */ + /* LUT data bits 47:32 + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A3.F:0 R/W MSS Ingress LUT Data 3 [3F:30] + AQ_MssIngressLutDataControlRegister_HHD.u3.bits_3.mssIngressLutData_3 + + Default = 0x0000 + + LUT data bits 63:48 + + */ + unsigned int mssIngressLutData_3 : 16; /* 1E.80A3.F:0 R/W Default = 0x0000 */ + /* LUT data bits 63:48 + */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A4.F:0 R/W MSS Ingress LUT Data 4 [4F:40] + AQ_MssIngressLutDataControlRegister_HHD.u4.bits_4.mssIngressLutData_4 + + Default = 0x0000 + + LUT data bits 79:64 + + */ + unsigned int mssIngressLutData_4 : 16; /* 1E.80A4.F:0 R/W Default = 0x0000 */ + /* LUT data bits 79:64 + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A5.F:0 R/W MSS Ingress LUT Data 5 [5F:50] + AQ_MssIngressLutDataControlRegister_HHD.u5.bits_5.mssIngressLutData_5 + + Default = 0x0000 + + LUT data bits 95:80 + + */ + unsigned int mssIngressLutData_5 : 16; /* 1E.80A5.F:0 R/W Default = 0x0000 */ + /* LUT data bits 95:80 + */ + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A6.F:0 R/W MSS Ingress LUT Data 6 [6F:60] + AQ_MssIngressLutDataControlRegister_HHD.u6.bits_6.mssIngressLutData_6 + + Default = 0x0000 + + LUT data bits 111:96 + + */ + unsigned int mssIngressLutData_6 : 16; /* 1E.80A6.F:0 R/W Default = 0x0000 */ + /* LUT data bits 111:96 + */ + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A7.F:0 R/W MSS Ingress LUT Data 7 [7F:70] + AQ_MssIngressLutDataControlRegister_HHD.u7.bits_7.mssIngressLutData_7 + + Default = 0x0000 + + LUT data bits 127:112 + + */ + unsigned int mssIngressLutData_7 : 16; /* 1E.80A7.F:0 R/W Default = 0x0000 */ + /* LUT data bits 127:112 + */ + } bits_7; + uint16_t word_7; + } u7; + /*! \brief Union for bit and word level access of word 8 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A8.F:0 R/W MSS Ingress LUT Data 8 [8F:80] + AQ_MssIngressLutDataControlRegister_HHD.u8.bits_8.mssIngressLutData_8 + + Default = 0x0000 + + LUT data bits 143:128 + + */ + unsigned int mssIngressLutData_8 : 16; /* 1E.80A8.F:0 R/W Default = 0x0000 */ + /* LUT data bits 143:128 + */ + } bits_8; + uint16_t word_8; + } u8; + /*! \brief Union for bit and word level access of word 9 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A9.F:0 R/W MSS Ingress LUT Data 9 [9F:90] + AQ_MssIngressLutDataControlRegister_HHD.u9.bits_9.mssIngressLutData_9 + + Default = 0x0000 + + LUT data bits 159:144 + + */ + unsigned int mssIngressLutData_9 : 16; /* 1E.80A9.F:0 R/W Default = 0x0000 */ + /* LUT data bits 159:144 + */ + } bits_9; + uint16_t word_9; + } u9; + /*! \brief Union for bit and word level access of word 10 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80AA.F:0 R/W MSS Ingress LUT Data 10 [AF:A0] + AQ_MssIngressLutDataControlRegister_HHD.u10.bits_10.mssIngressLutData_10 + + Default = 0x0000 + + LUT data bits 175:160 + + */ + unsigned int mssIngressLutData_10 : 16; /* 1E.80AA.F:0 R/W Default = 0x0000 */ + /* LUT data bits 175:160 + */ + } bits_10; + uint16_t word_10; + } u10; + /*! \brief Union for bit and word level access of word 11 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80AB.F:0 R/W MSS Ingress LUT Data 11 [BF:B0] + AQ_MssIngressLutDataControlRegister_HHD.u11.bits_11.mssIngressLutData_11 + + Default = 0x0000 + + LUT data bits 191:176 + + */ + unsigned int mssIngressLutData_11 : 16; /* 1E.80AB.F:0 R/W Default = 0x0000 */ + /* LUT data bits 191:176 + */ + } bits_11; + uint16_t word_11; + } u11; + /*! \brief Union for bit and word level access of word 12 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80AC.F:0 R/W MSS Ingress LUT Data 12 [CF:C0] + AQ_MssIngressLutDataControlRegister_HHD.u12.bits_12.mssIngressLutData_12 + + Default = 0x0000 + + LUT data bits 207:192 + + */ + unsigned int mssIngressLutData_12 : 16; /* 1E.80AC.F:0 R/W Default = 0x0000 */ + /* LUT data bits 207:192 + */ + } bits_12; + uint16_t word_12; + } u12; + /*! \brief Union for bit and word level access of word 13 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80AD.F:0 R/W MSS Ingress LUT Data 13 [DF:D0] + AQ_MssIngressLutDataControlRegister_HHD.u13.bits_13.mssIngressLutData_13 + + Default = 0x0000 + + LUT data bits 223:208 + + */ + unsigned int mssIngressLutData_13 : 16; /* 1E.80AD.F:0 R/W Default = 0x0000 */ + /* LUT data bits 223:208 + */ + } bits_13; + uint16_t word_13; + } u13; + /*! \brief Union for bit and word level access of word 14 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80AE.F:0 R/W MSS Ingress LUT Data 14 [EF:E0] + AQ_MssIngressLutDataControlRegister_HHD.u14.bits_14.mssIngressLutData_14 + + Default = 0x0000 + + LUT data bits 239:224 + + */ + unsigned int mssIngressLutData_14 : 16; /* 1E.80AE.F:0 R/W Default = 0x0000 */ + /* LUT data bits 239:224 + */ + } bits_14; + uint16_t word_14; + } u14; + /*! \brief Union for bit and word level access of word 15 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80AF.F:0 R/W MSS Ingress LUT Data 15 [FF:F0] + AQ_MssIngressLutDataControlRegister_HHD.u15.bits_15.mssIngressLutData_15 + + Default = 0x0000 + + LUT data bits 255:240 + + */ + unsigned int mssIngressLutData_15 : 16; /* 1E.80AF.F:0 R/W Default = 0x0000 */ + /* LUT data bits 255:240 + */ + } bits_15; + uint16_t word_15; + } u15; + /*! \brief Union for bit and word level access of word 16 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B0.F:0 R/W MSS Ingress LUT Data 16 [10F:100] + AQ_MssIngressLutDataControlRegister_HHD.u16.bits_16.mssIngressLutData_16 + + Default = 0x0000 + + LUT data bits 271:256 + + */ + unsigned int mssIngressLutData_16 : 16; /* 1E.80B0.F:0 R/W Default = 0x0000 */ + /* LUT data bits 271:256 + */ + } bits_16; + uint16_t word_16; + } u16; + /*! \brief Union for bit and word level access of word 17 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B1.F:0 R/W MSS Ingress LUT Data 17 [11F:110] + AQ_MssIngressLutDataControlRegister_HHD.u17.bits_17.mssIngressLutData_17 + + Default = 0x0000 + + LUT data bits 287:272 + + */ + unsigned int mssIngressLutData_17 : 16; /* 1E.80B1.F:0 R/W Default = 0x0000 */ + /* LUT data bits 287:272 + */ + } bits_17; + uint16_t word_17; + } u17; + /*! \brief Union for bit and word level access of word 18 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B2.F:0 R/W MSS Ingress LUT Data 18 [12F:120] + AQ_MssIngressLutDataControlRegister_HHD.u18.bits_18.mssIngressLutData_18 + + Default = 0x0000 + + LUT data bits 303:288 + + */ + unsigned int mssIngressLutData_18 : 16; /* 1E.80B2.F:0 R/W Default = 0x0000 */ + /* LUT data bits 303:288 + */ + } bits_18; + uint16_t word_18; + } u18; + /*! \brief Union for bit and word level access of word 19 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B3.F:0 R/W MSS Ingress LUT Data 19 [13F:130] + AQ_MssIngressLutDataControlRegister_HHD.u19.bits_19.mssIngressLutData_19 + + Default = 0x0000 + + LUT data bits 319:304 + + */ + unsigned int mssIngressLutData_19 : 16; /* 1E.80B3.F:0 R/W Default = 0x0000 */ + /* LUT data bits 319:304 + */ + } bits_19; + uint16_t word_19; + } u19; + /*! \brief Union for bit and word level access of word 20 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B4.F:0 R/W MSS Ingress LUT Data 20 [14F:140] + AQ_MssIngressLutDataControlRegister_HHD.u20.bits_20.mssIngressLutData_20 + + Default = 0x0000 + + LUT data bits 335:320 + + */ + unsigned int mssIngressLutData_20 : 16; /* 1E.80B4.F:0 R/W Default = 0x0000 */ + /* LUT data bits 335:320 + */ + } bits_20; + uint16_t word_20; + } u20; + /*! \brief Union for bit and word level access of word 21 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B5.F:0 R/W MSS Ingress LUT Data 21 [15F:150] + AQ_MssIngressLutDataControlRegister_HHD.u21.bits_21.mssIngressLutData_21 + + Default = 0x0000 + + LUT data bits 351:336 + + */ + unsigned int mssIngressLutData_21 : 16; /* 1E.80B5.F:0 R/W Default = 0x0000 */ + /* LUT data bits 351:336 + */ + } bits_21; + uint16_t word_21; + } u21; + /*! \brief Union for bit and word level access of word 22 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B6.F:0 R/W MSS Ingress LUT Data 22 [16F:160] + AQ_MssIngressLutDataControlRegister_HHD.u22.bits_22.mssIngressLutData_22 + + Default = 0x0000 + + LUT data bits 367:352 + + */ + unsigned int mssIngressLutData_22 : 16; /* 1E.80B6.F:0 R/W Default = 0x0000 */ + /* LUT data bits 367:352 + */ + } bits_22; + uint16_t word_22; + } u22; + /*! \brief Union for bit and word level access of word 23 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B7.F:0 R/W MSS Ingress LUT Data 23 [17F:170] + AQ_MssIngressLutDataControlRegister_HHD.u23.bits_23.mssIngressLutData_23 + + Default = 0x0000 + + LUT data bits 383:368 + + */ + unsigned int mssIngressLutData_23 : 16; /* 1E.80B7.F:0 R/W Default = 0x0000 */ + /* LUT data bits 383:368 + */ + } bits_23; + uint16_t word_23; + } u23; +} AQ_MssIngressLutDataControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line General Control Register: 1E.9004 */ +/* MSM Line General Control Register: 1E.9004 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line General Control Register */ + union + { + struct + { + /*! \brief 1E.9004.0 R/W MSM Line Tx Enable + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineTxEnable + + Default = 0x0 + + 1 = Tx enable + + Notes: + MAC Rx path enable. Should be set to 1 to enable the MAC Rx path. Should be set to 0 to disable the MAC Rx path. */ + unsigned int msmLineTxEnable : 1; /* 1E.9004.0 R/W Default = 0x0 */ + /* 1 = Tx enable */ + /*! \brief 1E.9004.1 R/W MSM Line Rx Enable + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineRxEnable + + Default = 0x0 + + 1 = Rx enable + + Notes: + MAC Tx path enable. Should be set to 1 to enable the MAC Tx path. Should be set to 0 to disable the MAC Tx path. */ + unsigned int msmLineRxEnable : 1; /* 1E.9004.1 R/W Default = 0x0 */ + /* 1 = Rx enable */ + unsigned int reserved0 : 1; + /*! \brief 1E.9004.3 R/W MSM Line WAN Mode + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineWanMode + + Default = 0x0 + + 1 = WAN mode + 0 = LAN mode + + + Notes: + WAN mode enable. Sets WAN mode when set to 1 and LAN mode when set to 0. Note: When changing the mode, verifiy correct setting of the Tx IPG. */ + unsigned int msmLineWanMode : 1; /* 1E.9004.3 R/W Default = 0x0 */ + /* 1 = WAN mode + 0 = LAN mode + */ + /*! \brief 1E.9004.4 R/W MSM Line Promiscuous Mode + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLinePromiscuousMode + + Default = 0x0 + + 1 = Promiscuous mode + + + Notes: + When set to 1, all frames are received without any MAC address filtering. */ + unsigned int msmLinePromiscuousMode : 1; /* 1E.9004.4 R/W Default = 0x0 */ + /* 1 = Promiscuous mode + */ + /*! \brief 1E.9004.5 R/W MSM Line PAD Enable + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLinePadEnable + + Default = 0x0 + + 1 = Enable frame padding removal on Rx + + + Notes: + When set to 1, enable frame padding removal on the Rx path. If enabled, padding is removed before the frame is transferred to the MAC client application. If disabled, no padding is removed on the Rx by the MAC. + Note : On Tx, the MAC always adds padding as required. */ + unsigned int msmLinePadEnable : 1; /* 1E.9004.5 R/W Default = 0x0 */ + /* 1 = Enable frame padding removal on Rx + */ + /*! \brief 1E.9004.6 R/W MSM Line CRC Forward + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineCrcForward + + Default = 0x0 + + 1 = Enable CRC forwarding + + + Notes: + When set to 1, the CRC field of the received frames is forwarded with the frame to the user application. If disabled, the CRC field is stripped from the frame. + Note : If padding is enabled ( See MAC PAD Enable set to 1), this bit is ignored. */ + unsigned int msmLineCrcForward : 1; /* 1E.9004.6 R/W Default = 0x0 */ + /* 1 = Enable CRC forwarding + */ + /*! \brief 1E.9004.7 R/W MSM Line Pause Forward + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLinePauseForward + + Default = 0x0 + + 1 = Enable Pause forwarding + + + Notes: + Terminate or forward pause frames. If set to 1, pause frames are forwarded to the user application. In normal mode, when set to 0, pause frames are terminated and discarded within the MAC. */ + unsigned int msmLinePauseForward : 1; /* 1E.9004.7 R/W Default = 0x0 */ + /* 1 = Enable Pause forwarding + */ + /*! \brief 1E.9004.8 R/W MSM Line Pause Ignore + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLinePauseIgnore + + Default = 0x0 + + 1 = Ignore pause frames + + + Notes: + Ignore pause frame quanta. If set to 1, received pause frames are ignored by the MAC. When set to 0, the Tx is stopped for the amount of time specified in the pause quanta received within the pause frame. */ + unsigned int msmLinePauseIgnore : 1; /* 1E.9004.8 R/W Default = 0x0 */ + /* 1 = Ignore pause frames + */ + /*! \brief 1E.9004.9 R/W MSM Line Tx Address Insert Enable + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineTxAddressInsertEnable + + Default = 0x0 + + 1 = Insert Tx MAC source address + + + Notes: + Set the source MAC address on transmit. If set to 1, the MAC overwrites the source MAC address with the MAC programmed address in all transmitted frames. When set to 0, the source MAC address is transmitted unmodified from the MAC Tx client application. */ + unsigned int msmLineTxAddressInsertEnable : 1; /* 1E.9004.9 R/W Default = 0x0 */ + /* 1 = Insert Tx MAC source address + */ + /*! \brief 1E.9004.A R/W MSM Line Tx CRC Append + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineTxCrcAppend + + Default = 0x0 + + 1 = Append Tx CRC + + + Notes: + Permanently enable CRC append on transmit. If set to 1, the Tx will append a CRC to all transmitted frames. If set to 0, CRC append can be controlled on a per frame basis using the pin ff_tx_crc. + This configuration bit is OR'ed with the external ff_tx_crc pin to instruct the Tx to append a CRC to transmitted frames. The ff_tx_crc pin is tied to 0. */ + unsigned int msmLineTxCrcAppend : 1; /* 1E.9004.A R/W Default = 0x0 */ + /* 1 = Append Tx CRC + */ + /*! \brief 1E.9004.B R/W MSM Line Tx Pad Enable + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineTxPadEnable + + Default = 0x1 + + 1 = Enable Tx padding + + + Notes: + When set to 1, enable padding of frames in the Tx direction. When set to 0, the MAC will not extend frames from the application to a minimum of 64 bytes, allowing to transmit short frames (violating the Ethernet mimimum size requirements). Must be set to 1 for normal operation. */ + unsigned int msmLineTxPadEnable : 1; /* 1E.9004.B R/W Default = 0x1 */ + /* 1 = Enable Tx padding + */ + /*! \brief 1E.9004.C R/WSC MSM Line Soft Reset + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineSoftReset + + Default = 0x0 + + 1 = Soft reset + + + Notes: + Software reset. Self clearing bit. When set to 1, resets all statistic counters as well as the Tx and Rx FIFOs. It should be issued after all traffic has been stopped as a result of clearing the Rx/Tx enable bits ( See MAC Rx Enable set to 0 and See MAC Tx Enable set to 0). + Note : Can lead to an Rx interface (ff_rx_xxx) violations to the application if the reset is issued in the middle of a receive frame transfer. Then the end of packet (assertion of ff_rx_eop) is lost and the application should be prepeared to handle this exception. */ + unsigned int msmLineSoftReset : 1; /* 1E.9004.C R/WSC Default = 0x0 */ + /* 1 = Soft reset + */ + /*! \brief 1E.9004.D R/W MSM Line Control Frame Enable + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineControlFrameEnable + + Default = 0x0 + + 1 = Control frame enabled + + + Notes: + MAC control frame enable. When set to 1, the MAC control frames with any Opcode other than 0x0001 are accepted and forwarded to the client interface. When set to 0, MAC control frames with any opcode other than 0x0001 are silently discarded. */ + unsigned int msmLineControlFrameEnable : 1; /* 1E.9004.D R/W Default = 0x0 */ + /* 1 = Control frame enabled + */ + /*! \brief 1E.9004.E R/W MSM Line Rx Error Discard + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineRxErrorDiscard + + Default = 0x0 + + 1 = Enable discard of received errored frames + + + Notes: + Rx errored frame discard enable. When set to 1, any frame received with an error is discarded and not forwarded to the client interface. When set to 0, errored frames are forwarded to the client interface with ff_rx_err asserted. + Note : It is recommended to set this bit to 1 only when store and forward operation is enabled (RX_SECTION_FULL TBD). */ + unsigned int msmLineRxErrorDiscard : 1; /* 1E.9004.E R/W Default = 0x0 */ + /* 1 = Enable discard of received errored frames + */ + /*! \brief 1E.9004.F R/W MSM Line PHY Tx Enable + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLinePhyTxEnable + + Default = 0x0 + + 1 = Enable PHY Tx + + + Notes: + Directly controls the phy_tx_ena pin. */ + unsigned int msmLinePhyTxEnable : 1; /* 1E.9004.F R/W Default = 0x0 */ + /* 1 = Enable PHY Tx + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line General Control Register */ + union + { + struct + { + /*! \brief 1E.9005.0 R/W MSM Line Force Send IDLE + AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLineForceSendIdle + + Default = 0x0 + + 1 = Force send idle + + Notes: + When set to 1, suppress any frame transmissions and forces IDLE n the Tx interface instead of frames. This control affects the MAC reconciliation layer (RS) which acts after all MAC datapath has processed the frame. + Note : Does not have an effect on fault handling (i.e. reception of local fault will still cause transmit of remote fault). + Must be 0 for normal operation. */ + unsigned int msmLineForceSendIdle : 1; /* 1E.9005.0 R/W Default = 0x0 */ + /* 1 = Force send idle */ + /*! \brief 1E.9005.1 R/W MSM Line Length Check Disable + AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLineLengthCheckDisable + + Default = 0x0 + + 1 = Disable length check + + Notes: + Payload length check disable. When set to 0, the MAC checks the frames payload length with the frame length/type field. When set to 1, the payload length check is disabled. */ + unsigned int msmLineLengthCheckDisable : 1; /* 1E.9005.1 R/W Default = 0x0 */ + /* 1 = Disable length check */ + /*! \brief 1E.9005.2 R/W MSM Line IDLE Column Count Extend + AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLineIdleColumnCountExtend + + Default = 0x0 + + 1 = Extend IDLE column count + + Notes: + When set to 1, extends the RS layer IDLE column counter by 2x. The IEEE 802.3ae defines the fault condition to be cleared after 128 columns of IDLE have been received. If the MAC operates together with a WAN mode PCS (WIS) it may may happen (depending on PCS) that this period is too short to bridge the IDLE stuffing occurring in this mode, leading to a toggling fault indication. In this case, extending the counter helps to aoivd toggling fault indications. */ + unsigned int msmLineIdleColumnCountExtend : 1; /* 1E.9005.2 R/W Default = 0x0 */ + /* 1 = Extend IDLE column count */ + /*! \brief 1E.9005.3 R/W MSM Line Priority Flow Control Enable + AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLinePriorityFlowControlEnable + + Default = 0x0 + + 1 = Enable priority flow control + 0 = Enable link flow control + + + Notes: + Enable priority flow control (PFC) mode of operation. When set to 0, the MAC uses standard link pause frames. When set to 1, the MAC will transmit and accept PFC frames. */ + unsigned int msmLinePriorityFlowControlEnable : 1; /* 1E.9005.3 R/W Default = 0x0 */ + /* 1 = Enable priority flow control + 0 = Enable link flow control + */ + unsigned int reserved2 : 1; + /*! \brief 1E.9005.5 R/W MSM Line SFD Check Disable + AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLineSfdCheckDisable + + Default = 0x0 + + 1 = Disable SFD check + + + Notes: + Disable check of SFD (0xD5) character at frame start. When set to 1, the frame is accepted even if the SFD byte following the preamble is not 0xD5. When set to 0, a frame is accepted only if the SFD byte is found with the value 0xD5. */ + unsigned int msmLineSfdCheckDisable : 1; /* 1E.9005.5 R/W Default = 0x0 */ + /* 1 = Disable SFD check + */ + unsigned int reserved1 : 1; + /*! \brief 1E.9005.7 R/W MSM Line Tx Low Power IDLE Enable + AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLineTxLowPowerIdleEnable + + Default = 0x0 + + 1 = Transmit LPI enable + + + Notes: + Transmit low power IDLE enable. When set to 1, the MAC completes the transmission of the current frame and generates low power IDLE sequences (LPI) to the XGMII/SGMII. When set to 0, the MAC operates in normal mode. This bit is OR'ed with the reg_lowp_ena pin. */ + unsigned int msmLineTxLowPowerIdleEnable : 1; /* 1E.9005.7 R/W Default = 0x0 */ + /* 1 = Transmit LPI enable + */ + unsigned int reserved0 : 8; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineGeneralControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line FIFO Control Register: 1E.900E */ +/* MSM Line FIFO Control Register: 1E.900E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.900E.7:0 R/W MSM Line Rx FIFO Full Threshold [7:0] + AQ_MsmLineFifoControlRegister_HHD.u0.bits_0.msmLineRxFifoFullThreshold + + Default = 0x08 + + Rx FIFO full threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmLineRxFifoFullThreshold : 8; /* 1E.900E.7:0 R/W Default = 0x08 */ + /* Rx FIFO full threshold */ + unsigned int reserved0 : 8; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.900F.7:0 R/W MSM Line Rx FIFO Empty Threshold [7:0] + AQ_MsmLineFifoControlRegister_HHD.u1.bits_1.msmLineRxFifoEmptyThreshold + + Default = 0x00 + + Rx FIFO empty threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmLineRxFifoEmptyThreshold : 8; /* 1E.900F.7:0 R/W Default = 0x00 */ + /* Rx FIFO empty threshold */ + unsigned int reserved0 : 8; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of MSM Line FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.9010.5:0 R/W MSM Line Tx FIFO Full Threshold [5:0] + AQ_MsmLineFifoControlRegister_HHD.u2.bits_2.msmLineTxFifoFullThreshold + + Default = 0x08 + + Tx FIFO full threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmLineTxFifoFullThreshold : 6; /* 1E.9010.5:0 R/W Default = 0x08 */ + /* Tx FIFO full threshold */ + unsigned int reserved0 : 10; + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of MSM Line FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.9011.5:0 R/W MSM Line Tx FIFO Empty Threshold [5:0] + AQ_MsmLineFifoControlRegister_HHD.u3.bits_3.msmLineTxFifoEmptyThreshold + + Default = 0x00 + + Tx FIFO empty threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmLineTxFifoEmptyThreshold : 6; /* 1E.9011.5:0 R/W Default = 0x00 */ + /* Tx FIFO empty threshold */ + unsigned int reserved0 : 10; + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of MSM Line FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.9012.7:0 ROS MSM Line Rx FIFO Almost Full Threshold [7:0] + AQ_MsmLineFifoControlRegister_HHD.u4.bits_4.msmLineRxFifoAlmostFullThreshold + + Default = 0x00 + + Rx FIFO almost full threshold + + Notes: + Unused. */ + unsigned int msmLineRxFifoAlmostFullThreshold : 8; /* 1E.9012.7:0 ROS Default = 0x00 */ + /* Rx FIFO almost full threshold */ + unsigned int reserved0 : 8; + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of MSM Line FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.9013.7:0 ROS MSM Line Rx FIFO Almost Empty Threshold [7:0] + AQ_MsmLineFifoControlRegister_HHD.u5.bits_5.msmLineRxFifoAlmostEmptyThreshold + + Default = 0x00 + + Rx FIFO almost empty threshold + + Notes: + Unused. */ + unsigned int msmLineRxFifoAlmostEmptyThreshold : 8; /* 1E.9013.7:0 ROS Default = 0x00 */ + /* Rx FIFO almost empty threshold */ + unsigned int reserved0 : 8; + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of MSM Line FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.9014.7:0 ROS MSM Line Tx FIFO Almost Full Threshold [7:0] + AQ_MsmLineFifoControlRegister_HHD.u6.bits_6.msmLineTxFifoAlmostFullThreshold + + Default = 0x00 + + Tx FIFO almost full threshold + + Notes: + Unused. */ + unsigned int msmLineTxFifoAlmostFullThreshold : 8; /* 1E.9014.7:0 ROS Default = 0x00 */ + /* Tx FIFO almost full threshold */ + unsigned int reserved0 : 8; + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of MSM Line FIFO Control Register */ + union + { + struct + { + /*! \brief 1E.9015.7:0 ROS MSM Line Tx FIFO Almost Empty Threshold [7:0] + AQ_MsmLineFifoControlRegister_HHD.u7.bits_7.msmLineTxFifoAlmostEmptyThreshold + + Default = 0x00 + + Tx FIFO almost empty threshold + + Notes: + Unused. */ + unsigned int msmLineTxFifoAlmostEmptyThreshold : 8; /* 1E.9015.7:0 ROS Default = 0x00 */ + /* Tx FIFO almost empty threshold */ + unsigned int reserved0 : 8; + } bits_7; + uint16_t word_7; + } u7; +} AQ_MsmLineFifoControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line General Status Register: 1E.9020 */ +/* MSM Line General Status Register: 1E.9020 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line General Status Register */ + union + { + struct + { + /*! \brief 1E.9020.0 BLH MSM Line Rx Local Fault + AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLineRxLocalFault + + + + Rx local fault detected + + Notes: + Latch high local fault status. Set to 1, whent he MAC detects Rx local fault sequences on the Rx interface. Reset to 0 after read and after reset. */ + unsigned int msmLineRxLocalFault : 1; /* 1E.9020.0 BLH */ + /* Rx local fault detected */ + /*! \brief 1E.9020.1 BLH MSM Line Rx Remote Fault + AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLineRxRemoteFault + + + + Rx remote fault detected + + Notes: + Latch high local fault status. Set to 1, whent he MAC detects Rx local fault sequences on the Rx interface. Reset to 0 after read and after reset. */ + unsigned int msmLineRxRemoteFault : 1; /* 1E.9020.1 BLH */ + /* Rx remote fault detected */ + /*! \brief 1E.9020.2 RO MSM Line PHY Loss of Signal + AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLinePhyLossOfSignal + + + + PHY loss of signal + + Notes: + PHY indicates loss of signal. This is the value of pin phy_los which is tied to 0. */ + unsigned int msmLinePhyLossOfSignal : 1; /* 1E.9020.2 RO */ + /* PHY loss of signal */ + /*! \brief 1E.9020.3 R/W MSM Line Timestamp Available + AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLineTimestampAvailable + + Default = 0x0 + + Timestamp available + + Notes: + Transmit timestamp available. Indicates that the timestamp of the last transmitted event frame (which had ff_tx_ts_frm=1) is available in the register See MAC Time Stamp Status 0 [F:0] and See MAC Time Stamp Status 1 [F:0] . To clear this bit, the bit must be written with a 1. + */ + unsigned int msmLineTimestampAvailable : 1; /* 1E.9020.3 R/W Default = 0x0 */ + /* Timestamp available */ + /*! \brief 1E.9020.4 RO MSM Line Rx Low Power IDLE + AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLineRxLowPowerIdle + + + + Rx LPI detected + + Notes: + Receive low power IDLE (LPI). Set to 1 when LPI is currently detected on the MAC Rx interface. Set to 0, when the MAC currently operates in normal mode. */ + unsigned int msmLineRxLowPowerIdle : 1; /* 1E.9020.4 RO */ + /* Rx LPI detected */ + /*! \brief 1E.9020.5 RO MSM Line Tx FIFO Empty + AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLineTxFifoEmpty + + + + Tx FIFO empty + + Notes: + When set to 1, indicates the Tx FIFO is empty. When set to 0, Tx FIFO is non-empty. */ + unsigned int msmLineTxFifoEmpty : 1; /* 1E.9020.5 RO */ + /* Tx FIFO empty */ + unsigned int reserved0 : 10; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line General Status Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineGeneralStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx IPG Control Register: 1E.9022 */ +/* MSM Line Tx IPG Control Register: 1E.9022 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx IPG Control Register */ + union + { + struct + { + /*! \brief 1E.9022.5:0 R/W MSM Line Tx IPG Length [5:0] + AQ_MsmLineTxIpgControlRegister_HHD.u0.bits_0.msmLineTxIpgLength + + Default = 0x0C + + Tx IPG length + + Notes: + Tx inter-packet gap (IPG) value. Depending on LAN or WAN mode of operation. + LAN Mode : Number of octets in steps of 4. Valid values are 8, 12, 16,..., 100. DIC is supported for any setting > 8. A default of 12 must be set to conform to IEEE802.3ae. + WAN Mode : Stretch factor. Valid values are 4 ... 15. The stretch factor is calculated as (value+1)*8. A default of 12 must be set to conform to IEEE802.3ae (i.e. 13*8=104). A larger value shrinks the IPG (increasing bandwidth). + The reset value of 12 leads to IEEE802.3ae conformant behavior in both modes. + Note : WAN mode is only available in 10G mode of operation. */ + unsigned int msmLineTxIpgLength : 6; /* 1E.9022.5:0 R/W Default = 0x0C */ + /* Tx IPG length */ + unsigned int reserved0 : 10; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx IPG Control Register */ + union + { + struct + { + /*! \brief 1E.9023.F:0 MSM Line Tx IPG Reserved + AQ_MsmLineTxIpgControlRegister_HHD.u1.bits_1.msmLineTxIpgReserved + + + + Value always 0, writes ignored + */ + unsigned int msmLineTxIpgReserved : 16; /* 1E.9023.F:0 */ + /* Value always 0, writes ignored */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxIpgControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx Good Frames Counter Register: 1E.9040 */ +/* MSM Line Tx Good Frames Counter Register: 1E.9040 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9040.F:0 ROS MSM Line Tx Good Frames Counter 0 [F:0] + AQ_MsmLineTxGoodFramesCounterRegister_HHD.u0.bits_0.msmLineTxGoodFramesCounter_0 + + Default = 0x0000 + + Tx good frame counter bits 15:0 + + Notes: + Count of frames transmitted without error (Including pause frames). */ + unsigned int msmLineTxGoodFramesCounter_0 : 16; /* 1E.9040.F:0 ROS Default = 0x0000 */ + /* Tx good frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9041.F:0 ROS MSM Line Tx Good Frames Counter 1 [F:0] + AQ_MsmLineTxGoodFramesCounterRegister_HHD.u1.bits_1.msmLineTxGoodFramesCounter_1 + + Default = 0x0000 + + Tx good frame counter bits 31:16 + + + Notes: + Count of frames transmitted without error (Including pause frames). */ + unsigned int msmLineTxGoodFramesCounter_1 : 16; /* 1E.9041.F:0 ROS Default = 0x0000 */ + /* Tx good frame counter bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxGoodFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Good Frames Counter Register: 1E.9044 */ +/* MSM Line Rx Good Frames Counter Register: 1E.9044 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9044.F:0 ROS MSM Line Rx Good Frames Counter 0 [F:0] + AQ_MsmLineRxGoodFramesCounterRegister_HHD.u0.bits_0.msmLineRxGoodFramesCounter_0 + + Default = 0x0000 + + Rx good frame counter bits 15:0 + + Notes: + Count of frames received without error (Including pause frames). */ + unsigned int msmLineRxGoodFramesCounter_0 : 16; /* 1E.9044.F:0 ROS Default = 0x0000 */ + /* Rx good frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9045.F:0 ROS MSM Line Rx Good Frames Counter 1 [F:0] + AQ_MsmLineRxGoodFramesCounterRegister_HHD.u1.bits_1.msmLineRxGoodFramesCounter_1 + + Default = 0x0000 + + Rx good frame counter bits 31:16 + + Notes: + Count of frames received without error (Including pause frames). */ + unsigned int msmLineRxGoodFramesCounter_1 : 16; /* 1E.9045.F:0 ROS Default = 0x0000 */ + /* Rx good frame counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxGoodFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx FCS Errors Counter Register: 1E.9048 */ +/* MSM Line Rx FCS Errors Counter Register: 1E.9048 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx FCS Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.9048.F:0 ROS MSM Line FCS Error Counter 0 [F:0] + AQ_MsmLineRxFcsErrorsCounterRegister_HHD.u0.bits_0.msmLineFcsErrorCounter_0 + + Default = 0x0000 + + Frame check sequence error counter bits 15:0 + + Notes: + Count of frames for which a CRC-32 Error is detected but the frame is otherwise of correct length. */ + unsigned int msmLineFcsErrorCounter_0 : 16; /* 1E.9048.F:0 ROS Default = 0x0000 */ + /* Frame check sequence error counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx FCS Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.9049.F:0 ROS MSM Line FCS Error Counter 1 [F:0] + AQ_MsmLineRxFcsErrorsCounterRegister_HHD.u1.bits_1.msmLineFcsErrorCounter_1 + + Default = 0x0000 + + Frame check sequence error counter bits 31:16 + + Notes: + Count of frames for which a CRC-32 Error is detected but the frame is otherwise of correct length. */ + unsigned int msmLineFcsErrorCounter_1 : 16; /* 1E.9049.F:0 ROS Default = 0x0000 */ + /* Frame check sequence error counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxFcsErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Alignment Errors Counter Register: 1E.904C */ +/* MSM Line Rx Alignment Errors Counter Register: 1E.904C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Alignment Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.904C.F:0 ROS MSM Line Alignment Error Counter 0 [F:0] + AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD.u0.bits_0.msmLineAlignmentErrorCounter_0 + + Default = 0x0000 + + Alignment error counter bits 15:0 + + Notes: + Count of frames received with an alignment error. */ + unsigned int msmLineAlignmentErrorCounter_0 : 16; /* 1E.904C.F:0 ROS Default = 0x0000 */ + /* Alignment error counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Alignment Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.904D.F:0 ROS MSM Line Alignment Error Counter 1 [F:0] + AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD.u1.bits_1.msmLineAlignmentErrorCounter_1 + + Default = 0x0000 + + Alignment error counter bits 31:16 + + Notes: + Count of frames received with an alignment error. */ + unsigned int msmLineAlignmentErrorCounter_1 : 16; /* 1E.904D.F:0 ROS Default = 0x0000 */ + /* Alignment error counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx Pause Frames Counter Register: 1E.9050 */ +/* MSM Line Tx Pause Frames Counter Register: 1E.9050 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9050.F:0 ROS MSM Line Tx Pause Frames Counter 0 [F:0] + AQ_MsmLineTxPauseFramesCounterRegister_HHD.u0.bits_0.msmLineTxPauseFramesCounter_0 + + Default = 0x0000 + + Tx pause frame counter bits 15:0 + + Notes: + Valid pause frames transmitted. */ + unsigned int msmLineTxPauseFramesCounter_0 : 16; /* 1E.9050.F:0 ROS Default = 0x0000 */ + /* Tx pause frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9051.F:0 ROS MSM Line Tx Pause Frames Counter 1 [F:0] + AQ_MsmLineTxPauseFramesCounterRegister_HHD.u1.bits_1.msmLineTxPauseFramesCounter_1 + + Default = 0x0000 + + Tx pause frame counter bits 31:16 + + + Notes: + Valid pause frames transmitted. */ + unsigned int msmLineTxPauseFramesCounter_1 : 16; /* 1E.9051.F:0 ROS Default = 0x0000 */ + /* Tx pause frame counter bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxPauseFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Pause Frames Counter Register: 1E.9054 */ +/* MSM Line Rx Pause Frames Counter Register: 1E.9054 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9054.F:0 ROS MSM Line Rx Pause Frames Counter 0 [F:0] + AQ_MsmLineRxPauseFramesCounterRegister_HHD.u0.bits_0.msmLineRxPauseFramesCounter_0 + + Default = 0x0000 + + Rx pause frame counter bits 15:0 + + Notes: + Valid pause frames received. */ + unsigned int msmLineRxPauseFramesCounter_0 : 16; /* 1E.9054.F:0 ROS Default = 0x0000 */ + /* Rx pause frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9055.F:0 ROS MSM Line Rx Pause Frames Counter 1 [F:0] + AQ_MsmLineRxPauseFramesCounterRegister_HHD.u1.bits_1.msmLineRxPauseFramesCounter_1 + + Default = 0x0000 + + Rx pause frame counter bits 31:16 + + Notes: + Valid pause frames received. */ + unsigned int msmLineRxPauseFramesCounter_1 : 16; /* 1E.9055.F:0 ROS Default = 0x0000 */ + /* Rx pause frame counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxPauseFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Too Long Errors Counter Register: 1E.9058 */ +/* MSM Line Rx Too Long Errors Counter Register: 1E.9058 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Too Long Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.9058.F:0 ROS MSM Line Rx Too Long Errors Counter 0 [F:0] + AQ_MsmLineRxTooLongErrorsCounterRegister_HHD.u0.bits_0.msmLineRxTooLongErrorsCounter_0 + + Default = 0x0000 + + Too-long errors counter bits 15:0 + + Notes: + Frame received exceeded the maximum length programmed with register FRM_LGTH. */ + unsigned int msmLineRxTooLongErrorsCounter_0 : 16; /* 1E.9058.F:0 ROS Default = 0x0000 */ + /* Too-long errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Too Long Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.9059.F:0 ROS MSM Line Rx Too Long Errors Counter 1 [F:0] + AQ_MsmLineRxTooLongErrorsCounterRegister_HHD.u1.bits_1.msmLineRxTooLongErrorsCounter_1 + + Default = 0x0000 + + Too-long errors counter bits 31:16 + + Notes: + Frame received exceeded the maximum length programmed with register FRM_LGTH. */ + unsigned int msmLineRxTooLongErrorsCounter_1 : 16; /* 1E.9059.F:0 ROS Default = 0x0000 */ + /* Too-long errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxTooLongErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx In Range Length Errors Counter Register: 1E.905C */ +/* MSM Line Rx In Range Length Errors Counter Register: 1E.905C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx In Range Length Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.905C.F:0 ROS MSM Line Rx In Range Length Errors Counter 0 [F:0] + AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD.u0.bits_0.msmLineRxInRangeLengthErrorsCounter_0 + + Default = 0x0000 + + In-range-length errors counter bits 15:0 + + Notes: + A count of frames with a length/type field value between 46 (VLAN: 42) and less than 0x0600, that does not match the number of payload data octets received. Should count also if length/type field is less than 46 (VLAN: 42) and the frame is longer than 64 bytes. */ + unsigned int msmLineRxInRangeLengthErrorsCounter_0 : 16; /* 1E.905C.F:0 ROS Default = 0x0000 */ + /* In-range-length errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx In Range Length Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.905D.F:0 ROS MSM Line Rx In Range Length Errors Counter 1 [F:0] + AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD.u1.bits_1.msmLineRxInRangeLengthErrorsCounter_1 + + Default = 0x0000 + + In-range-length errors counter bits 31:16 + + Notes: + A count of frames with a length/type field value between 46 (VLAN: 42) and less than 0x0600, that does not match the number of payload data octets received. Should count also if length/type field is less than 46 (VLAN: 42) and the frame is longer than 64 bytes. */ + unsigned int msmLineRxInRangeLengthErrorsCounter_1 : 16; /* 1E.905D.F:0 ROS Default = 0x0000 */ + /* In-range-length errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx VLAN Frames Counter Register: 1E.9060 */ +/* MSM Line Tx VLAN Frames Counter Register: 1E.9060 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9060.F:0 ROS MSM Line Tx VLAN Frames Counter 0 [F:0] + AQ_MsmLineTxVlanFramesCounterRegister_HHD.u0.bits_0.msmLineTxVlanFramesCounter_0 + + Default = 0x0000 + + Tx VLAN frames counter bits 15:0 + + Notes: + Valid VLAN tagged frames transmitted. */ + unsigned int msmLineTxVlanFramesCounter_0 : 16; /* 1E.9060.F:0 ROS Default = 0x0000 */ + /* Tx VLAN frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9061.F:0 ROS MSM Line Tx VLAN Frames Counter 1 [F:0] + AQ_MsmLineTxVlanFramesCounterRegister_HHD.u1.bits_1.msmLineTxVlanFramesCounter_1 + + Default = 0x0000 + + Tx VLAN frames counter bits 31:16 + + Notes: + Valid VLAN tagged frames transmitted. */ + unsigned int msmLineTxVlanFramesCounter_1 : 16; /* 1E.9061.F:0 ROS Default = 0x0000 */ + /* Tx VLAN frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxVlanFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx VLAN Frames Counter Register: 1E.9064 */ +/* MSM Line Rx VLAN Frames Counter Register: 1E.9064 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9064.F:0 ROS MSM Line Rx VLAN Frames Counter 0 [F:0] + AQ_MsmLineRxVlanFramesCounterRegister_HHD.u0.bits_0.msmLineRxVlanFramesCounter_0 + + Default = 0x0000 + + Rx VLAN frames counter bits 15:0 + + Notes: + Valid VLAN tagged frames received. */ + unsigned int msmLineRxVlanFramesCounter_0 : 16; /* 1E.9064.F:0 ROS Default = 0x0000 */ + /* Rx VLAN frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9065.F:0 ROS MSM Line Rx VLAN Frames Counter 1 [F:0] + AQ_MsmLineRxVlanFramesCounterRegister_HHD.u1.bits_1.msmLineRxVlanFramesCounter_1 + + Default = 0x0000 + + Rx VLAN frames counter bits 31:16 + + Notes: + Valid VLAN tagged frames received. */ + unsigned int msmLineRxVlanFramesCounter_1 : 16; /* 1E.9065.F:0 ROS Default = 0x0000 */ + /* Rx VLAN frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxVlanFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx Octets Counter Register: 1E.9068 */ +/* MSM Line Tx Octets Counter Register: 1E.9068 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.9068.F:0 ROS MSM Line Tx Octets Counter 0 [F:0] + AQ_MsmLineTxOctetsCounterRegister_HHD.u0.bits_0.msmLineTxOctetsCounter_0 + + Default = 0x0000 + + Tx octets counter bits 15:0 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmLineTxOctetsCounter_0 : 16; /* 1E.9068.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.9069.F:0 ROS MSM Line Tx Octets Counter 1 [F:0] + AQ_MsmLineTxOctetsCounterRegister_HHD.u1.bits_1.msmLineTxOctetsCounter_1 + + Default = 0x0000 + + Tx octets counter bits 31:16 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmLineTxOctetsCounter_1 : 16; /* 1E.9069.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of MSM Line Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.906A.F:0 ROS MSM Line Tx Octets Counter 2 [F:0] + AQ_MsmLineTxOctetsCounterRegister_HHD.u2.bits_2.msmLineTxOctetsCounter_2 + + Default = 0x0000 + + Tx octets counter bits 47:32 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmLineTxOctetsCounter_2 : 16; /* 1E.906A.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 47:32 */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of MSM Line Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.906B.F:0 ROS MSM Line Tx Octets Counter 3 [F:0] + AQ_MsmLineTxOctetsCounterRegister_HHD.u3.bits_3.msmLineTxOctetsCounter_3 + + Default = 0x0000 + + Tx octets counter bits 63:48 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmLineTxOctetsCounter_3 : 16; /* 1E.906B.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 63:48 */ + } bits_3; + uint16_t word_3; + } u3; +} AQ_MsmLineTxOctetsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Octets Counter Register: 1E.906C */ +/* MSM Line Rx Octets Counter Register: 1E.906C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.906C.F:0 ROS MSM Line Rx Octets Counter 0 [F:0] + AQ_MsmLineRxOctetsCounterRegister_HHD.u0.bits_0.msmLineRxOctetsCounter_0 + + Default = 0x0000 + + Rx octets counter bits 15:0 + + Notes: + All octets received except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames received. */ + unsigned int msmLineRxOctetsCounter_0 : 16; /* 1E.906C.F:0 ROS Default = 0x0000 */ + /* Rx octets counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.906D.F:0 ROS MSM Line Rx Octets Counter 1 [F:0] + AQ_MsmLineRxOctetsCounterRegister_HHD.u1.bits_1.msmLineRxOctetsCounter_1 + + Default = 0x0000 + + Rx octets counter bits 31:16 + + Notes: + All octets received except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames received. */ + unsigned int msmLineRxOctetsCounter_1 : 16; /* 1E.906D.F:0 ROS Default = 0x0000 */ + /* Rx octets counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxOctetsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Unicast Frames Counter Register: 1E.9070 */ +/* MSM Line Rx Unicast Frames Counter Register: 1E.9070 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9070.F:0 ROS MSM Line Rx Unicast Frames Counter 0 [F:0] + AQ_MsmLineRxUnicastFramesCounterRegister_HHD.u0.bits_0.msmLineRxUnicastFramesCounter_0 + + Default = 0x0000 + + Rx unicast frames counter bits 15:0 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '0'. */ + unsigned int msmLineRxUnicastFramesCounter_0 : 16; /* 1E.9070.F:0 ROS Default = 0x0000 */ + /* Rx unicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9071.F:0 ROS MSM Line Rx Unicast Frames Counter 1 [F:0] + AQ_MsmLineRxUnicastFramesCounterRegister_HHD.u1.bits_1.msmLineRxUnicastFramesCounter_1 + + Default = 0x0000 + + Rx unicast frames counter bits 31:16 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '0'. */ + unsigned int msmLineRxUnicastFramesCounter_1 : 16; /* 1E.9071.F:0 ROS Default = 0x0000 */ + /* Rx unicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxUnicastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Multicast Frames Counter Register: 1E.9074 */ +/* MSM Line Rx Multicast Frames Counter Register: 1E.9074 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9074.F:0 ROS MSM Line Rx Multicast Frames Counter 0 [F:0] + AQ_MsmLineRxMulticastFramesCounterRegister_HHD.u0.bits_0.msmLineRxMulticastFramesCounter_0 + + Default = 0x0000 + + Rx multicast frames counter bits 15:0 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '1' but not the broadcast address (all bits set '1' ). Pause frames are not counted. */ + unsigned int msmLineRxMulticastFramesCounter_0 : 16; /* 1E.9074.F:0 ROS Default = 0x0000 */ + /* Rx multicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9075.F:0 ROS MSM Line Rx Multicast Frames Counter 1 [F:0] + AQ_MsmLineRxMulticastFramesCounterRegister_HHD.u1.bits_1.msmLineRxMulticastFramesCounter_1 + + Default = 0x0000 + + Rx multicast frames counter bits 31:16 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '1' but not the broadcast address (all bits set '1' ). Pause frames are not counted. */ + unsigned int msmLineRxMulticastFramesCounter_1 : 16; /* 1E.9075.F:0 ROS Default = 0x0000 */ + /* Rx multicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxMulticastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Broadcast Frames Counter Register: 1E.9078 */ +/* MSM Line Rx Broadcast Frames Counter Register: 1E.9078 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9078.F:0 ROS MSM Line Rx Broadcast Frames Counter 0 [F:0] + AQ_MsmLineRxBroadcastFramesCounterRegister_HHD.u0.bits_0.msmLineRxBroadcastFramesCounter_0 + + Default = 0x0000 + + Rx broadcast frames counter bits 15:0 + + Notes: + Incremented with each valid frame received on the receive FIFO interface (FIFO) and all bits of the destination address were set '1'. */ + unsigned int msmLineRxBroadcastFramesCounter_0 : 16; /* 1E.9078.F:0 ROS Default = 0x0000 */ + /* Rx broadcast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9079.F:0 ROS MSM Line Rx Broadcast Frames Counter 1 [F:0] + AQ_MsmLineRxBroadcastFramesCounterRegister_HHD.u1.bits_1.msmLineRxBroadcastFramesCounter_1 + + Default = 0x0000 + + Rx broadcast frames counter bits 31:16 + + Notes: + Incremented with each valid frame received on the receive FIFO interface (FIFO) and all bits of the destination address were set '1'. */ + unsigned int msmLineRxBroadcastFramesCounter_1 : 16; /* 1E.9079.F:0 ROS Default = 0x0000 */ + /* Rx broadcast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxBroadcastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx Errors Counter Register: 1E.907C */ +/* MSM Line Tx Errors Counter Register: 1E.907C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.907C.F:0 ROS MSM Line Tx Errors Counter 0 [F:0] + AQ_MsmLineTxErrorsCounterRegister_HHD.u0.bits_0.msmLineTxErrorsCounter_0 + + Default = 0x0000 + + Rx errors counter bits 15:0 + + Notes: + Number of frames transmitted with error: + - FIFO Overflow Errors + - FIFO Underflow Errors */ + unsigned int msmLineTxErrorsCounter_0 : 16; /* 1E.907C.F:0 ROS Default = 0x0000 */ + /* Rx errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.907D.F:0 ROS MSM Line Tx Errors Counter 1 [F:0] + AQ_MsmLineTxErrorsCounterRegister_HHD.u1.bits_1.msmLineTxErrorsCounter_1 + + Default = 0x0000 + + Tx errors counter bits 31:16 + + Notes: + Number of frames transmitted with error: + - FIFO Overflow Errors + - FIFO Underflow Errors */ + unsigned int msmLineTxErrorsCounter_1 : 16; /* 1E.907D.F:0 ROS Default = 0x0000 */ + /* Tx errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx Unicast Frames Counter Register: 1E.9084 */ +/* MSM Line Tx Unicast Frames Counter Register: 1E.9084 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9084.F:0 ROS MSM Line Tx Unicast Frames Counter 0 [F:0] + AQ_MsmLineTxUnicastFramesCounterRegister_HHD.u0.bits_0.msmLineTxUnicastFramesCounter_0 + + Default = 0x0000 + + Tx unicast frames counter bits 15:0 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '0'. */ + unsigned int msmLineTxUnicastFramesCounter_0 : 16; /* 1E.9084.F:0 ROS Default = 0x0000 */ + /* Tx unicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9085.F:0 ROS MSM Line Tx Unicast Frames Counter 1 [F:0] + AQ_MsmLineTxUnicastFramesCounterRegister_HHD.u1.bits_1.msmLineTxUnicastFramesCounter_1 + + Default = 0x0000 + + Tx unicast frames counter bits 31:16 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '0'. */ + unsigned int msmLineTxUnicastFramesCounter_1 : 16; /* 1E.9085.F:0 ROS Default = 0x0000 */ + /* Tx unicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxUnicastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx Multicast Frames Counter Register: 1E.9088 */ +/* MSM Line Tx Multicast Frames Counter Register: 1E.9088 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9088.F:0 ROS MSM Line Tx Multicast Frames Counter 0 [F:0] + AQ_MsmLineTxMulticastFramesCounterRegister_HHD.u0.bits_0.msmLineTxMulticastFramesCounter_0 + + Default = 0x0000 + + Tx multicast frames counter bits 15:0 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '1' but not the broadcast address (all bits '1'). */ + unsigned int msmLineTxMulticastFramesCounter_0 : 16; /* 1E.9088.F:0 ROS Default = 0x0000 */ + /* Tx multicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9089.F:0 ROS MSM Line Tx Multicast Frames Counter 1 [F:0] + AQ_MsmLineTxMulticastFramesCounterRegister_HHD.u1.bits_1.msmLineTxMulticastFramesCounter_1 + + Default = 0x0000 + + Tx multicast frames counter bits 31:16 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '1' but not the broadcast address (all bits '1'). */ + unsigned int msmLineTxMulticastFramesCounter_1 : 16; /* 1E.9089.F:0 ROS Default = 0x0000 */ + /* Tx multicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxMulticastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx Broadcast Frames Counter Register: 1E.908C */ +/* MSM Line Tx Broadcast Frames Counter Register: 1E.908C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.908C.F:0 ROS MSM Line Tx Broadcast Frames Counter 0 [F:0] + AQ_MsmLineTxBroadcastFramesCounterRegister_HHD.u0.bits_0.msmLineTxBroadcastFramesCounter_0 + + Default = 0x0000 + + Tx broadcast frames counter bits 15:0 + + Notes: + Incremented with each frame written to the FIFO interface and all bits of the destination address set to '1'. */ + unsigned int msmLineTxBroadcastFramesCounter_0 : 16; /* 1E.908C.F:0 ROS Default = 0x0000 */ + /* Tx broadcast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.908D.F:0 ROS MSM Line Tx Broadcast Frames Counter 1 [F:0] + AQ_MsmLineTxBroadcastFramesCounterRegister_HHD.u1.bits_1.msmLineTxBroadcastFramesCounter_1 + + Default = 0x0000 + + Tx broadcast frames counter bits 31:16 + + Notes: + Incremented with each frame written to the FIFO interface and all bits of the destination address set to '1'. */ + unsigned int msmLineTxBroadcastFramesCounter_1 : 16; /* 1E.908D.F:0 ROS Default = 0x0000 */ + /* Tx broadcast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxBroadcastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Errors Counter Register: 1E.90C8 */ +/* MSM Line Rx Errors Counter Register: 1E.90C8 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.90C8.F:0 ROS MSM Line Rx Errors Counter 0 [F:0] + AQ_MsmLineRxErrorsCounterRegister_HHD.u0.bits_0.msmLineRxErrorsCounter_0 + + Default = 0x0000 + + Rx errors counter bits 15:0 + + Notes: + Number of frames received with error: + - FIFO Overflow Errors + - CRC Errors + - Payload Length Errors + - Jabber and Oversized Errors + - Alignment Errors + - The dedicated Error Code (0xfe, not a code error) was received */ + unsigned int msmLineRxErrorsCounter_0 : 16; /* 1E.90C8.F:0 ROS Default = 0x0000 */ + /* Rx errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.90C9.F:0 ROS MSM Line Rx Errors Counter 1 [F:0] + AQ_MsmLineRxErrorsCounterRegister_HHD.u1.bits_1.msmLineRxErrorsCounter_1 + + Default = 0x0000 + + Rx errors counter bits 31:16 + + Notes: + Number of frames received with error: + - FIFO Overflow Errors + - CRC Errors + - Payload Length Errors + - Jabber and Oversized Errors + - Alignment Errors + - The dedicated Error Code (0xfe, not a code error) was received */ + unsigned int msmLineRxErrorsCounter_1 : 16; /* 1E.90C9.F:0 ROS Default = 0x0000 */ + /* Rx errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Control: 1E.C000 */ +/* Global Control: 1E.C000 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Control */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Control */ + union + { + struct + { + /*! \brief 1E.C001.0 R/W uP Run Stall + AQ_GlobalControl_HHD.u1.bits_1.upRunStall + + Default = 0x0 + + 1 = uP Run Stall + 0 = uP normal mode + + + Notes: + Deactivates the uP. */ + unsigned int upRunStall : 1; /* 1E.C001.0 R/W Default = 0x0 */ + /* 1 = uP Run Stall + 0 = uP normal mode + */ + unsigned int reserved1 : 5; + /*! \brief 1E.C001.6 R/W uP Run Stall Override + AQ_GlobalControl_HHD.u1.bits_1.upRunStallOverride + + Default = 0x0 + + 0 = uP Run Stall from "MDIO Boot Load" pin. + 1 = uP Run Stall from See MCP Run Stall bit + + + + Notes: + This bit selects the uP Run Stall from either the "MDIO Boot Load" pin or the See MCP Run Stall bit. Pin no longer brought out as deprecated. */ + unsigned int upRunStallOverride : 1; /* 1E.C001.6 R/W Default = 0x0 */ + /* 0 = uP Run Stall from "MDIO Boot Load" pin. + 1 = uP Run Stall from See MCP Run Stall bit + + */ + unsigned int reserved0 : 8; + /*! \brief 1E.C001.F R/W uP Reset + AQ_GlobalControl_HHD.u1.bits_1.upReset + + Default = 0x0 + + 1 = Reset + + + Notes: + Resets the uP and the PIF master and slave bus. Will be active for a minimum of 100 microseconds. */ + unsigned int upReset : 1; /* 1E.C001.F R/W Default = 0x0 */ + /* 1 = Reset + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalControl_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Reset Control: 1E.C006 */ +/* Global Reset Control: 1E.C006 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Reset Control */ + union + { + struct + { + unsigned int reserved1 : 14; + /*! \brief 1E.C006.E R/WPD Global MMD Reset Disable + AQ_GlobalResetControl_HHD.u0.bits_0.globalMMD_ResetDisable + + Provisionable Default = 0x0 + + 1 = Disable the S/W reset to the Global MMD registers + 0 = Enable the S/W reset to the Global MMD registers + + + Notes: + Setting this bit prevents a Global S/W reset or Global S/W reset from resetting the Global MMD registers */ + unsigned int globalMMD_ResetDisable : 1; /* 1E.C006.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Disable the S/W reset to the Global MMD registers + 0 = Enable the S/W reset to the Global MMD registers + */ + unsigned int reserved0 : 1; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalResetControl_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Diagnostic Provisioning: 1E.C400 */ +/* Global Diagnostic Provisioning: 1E.C400 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Diagnostic Provisioning */ + union + { + struct + { + unsigned int reserved0 : 15; + /*! \brief 1E.C400.F R/WPD Enable Diagnostics + AQ_GlobalDiagnosticProvisioning_HHD.u0.bits_0.enableDiagnostics + + Provisionable Default = 0x1 + + 1 = Chip performs diagnostics on power-up + */ + unsigned int enableDiagnostics : 1; /* 1E.C400.F R/WPD Provisionable Default = 0x1 */ + /* 1 = Chip performs diagnostics on power-up */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalDiagnosticProvisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Thermal Provisioning: 1E.C420 */ +/* Global Thermal Provisioning: 1E.C420 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C420.F:0 R/WPD Reserved 0 [F:0] + AQ_GlobalThermalProvisioning_HHD.u0.bits_0.reserved_0 + + Provisionable Default = 0x0000 + + Internal reserved - do not modify + + */ + unsigned int reserved_0 : 16; /* 1E.C420.F:0 R/WPD Provisionable Default = 0x0000 */ + /* Internal reserved - do not modify + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C421.F:0 R/WPD High Temp Failure Threshold [F:0] + AQ_GlobalThermalProvisioning_HHD.u1.bits_1.highTempFailureThreshold + + Provisionable Default = 0x4600 + + [F:0] of high temperature failure threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 70 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A000 - 1.A001: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int highTempFailureThreshold : 16; /* 1E.C421.F:0 R/WPD Provisionable Default = 0x4600 */ + /* [F:0] of high temperature failure threshold */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C422.F:0 R/WPD Low Temp Failure Threshold [F:0] + AQ_GlobalThermalProvisioning_HHD.u2.bits_2.lowTempFailureThreshold + + Provisionable Default = 0x0000 + + [F:0] of low temperature failure threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 0 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A002 - 1.A003: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int lowTempFailureThreshold : 16; /* 1E.C422.F:0 R/WPD Provisionable Default = 0x0000 */ + /* [F:0] of low temperature failure threshold */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C423.F:0 R/WPD High Temp Warning Threshold [F:0] + AQ_GlobalThermalProvisioning_HHD.u3.bits_3.highTempWarningThreshold + + Provisionable Default = 0x3C00 + + [F:0] of high temperature warning threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD008. Default is 60 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A004 - 1.A005: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int highTempWarningThreshold : 16; /* 1E.C423.F:0 R/WPD Provisionable Default = 0x3C00 */ + /* [F:0] of high temperature warning threshold */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C424.F:0 R/WPD Low Temp Warning Threshold [F:0] + AQ_GlobalThermalProvisioning_HHD.u4.bits_4.lowTempWarningThreshold + + Provisionable Default = 0x0A00 + + [F:0] of low temperature warning threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 10 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A006 - 1.A007: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int lowTempWarningThreshold : 16; /* 1E.C424.F:0 R/WPD Provisionable Default = 0x0A00 */ + /* [F:0] of low temperature warning threshold */ + } bits_4; + uint16_t word_4; + } u4; +} AQ_GlobalThermalProvisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global LED Provisioning: 1E.C430 */ +/* Global LED Provisioning: 1E.C430 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C430.1:0 R/WPD LED #0 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_0ActivityStretch : 2; /* 1E.C430.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + /*! \brief 1E.C430.2 R/WPD LED #0 Transmit Activity + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_0TransmitActivity : 1; /* 1E.C430.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C430.3 R/WPD LED #0 Receive Activity + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_0ReceiveActivity : 1; /* 1E.C430.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C430.4 R/WPD LED #0 Connecting + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_0Connecting : 1; /* 1E.C430.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C430.5 R/WPD LED #0 100 Mb/s Link Established + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s. + + */ + unsigned int led_0_100Mb_sLinkEstablished : 1; /* 1E.C430.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s. + */ + /*! \brief 1E.C430.6 R/WPD LED #0 1 Gb/s Link Established + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_0_1Gb_sLinkEstablished : 1; /* 1E.C430.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C430.7 R/WPD LED #0 10 Gb/s Link Established + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_0_10Gb_sLinkEstablished : 1; /* 1E.C430.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C430.8 R/WPD LED #0 Manual Set + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_0ManualSet : 1; /* 1E.C430.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + /*! \brief 1E.C430.D:9 R/WPD Reserved Provisioning C430 [4:0] + AQ_GlobalLedProvisioning_HHD.u0.bits_0.reservedProvisioningC430 + + Provisionable Default = 0x00 + + Reserved for future use + */ + unsigned int reservedProvisioningC430 : 5; /* 1E.C430.D:9 R/WPD Provisionable Default = 0x00 */ + /* Reserved for future use */ + unsigned int reserved0 : 2; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C431.1:0 R/WPD LED #1 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_1ActivityStretch : 2; /* 1E.C431.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + /*! \brief 1E.C431.2 R/WPD LED #1 Transmit Activity + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_1TransmitActivity : 1; /* 1E.C431.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C431.3 R/WPD LED #1 Receive Activity + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_1ReceiveActivity : 1; /* 1E.C431.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C431.4 R/WPD LED #1 Connecting + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_1Connecting : 1; /* 1E.C431.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C431.5 R/WPD LED #1 100 Mb/s Link Established + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s. + + */ + unsigned int led_1_100Mb_sLinkEstablished : 1; /* 1E.C431.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s. + */ + /*! \brief 1E.C431.6 R/WPD LED #1 1 Gb/s Link Established + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_1_1Gb_sLinkEstablished : 1; /* 1E.C431.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C431.7 R/WPD LED #1 10 Gb/s Link Established + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_1_10Gb_sLinkEstablished : 1; /* 1E.C431.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C431.8 R/WPD LED #1 Manual Set + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_1ManualSet : 1; /* 1E.C431.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + /*! \brief 1E.C431.D:9 R/WPD Reserved Provisioning C431 [4:0] + AQ_GlobalLedProvisioning_HHD.u1.bits_1.reservedProvisioningC431 + + Provisionable Default = 0x00 + + Reserved for future use + */ + unsigned int reservedProvisioningC431 : 5; /* 1E.C431.D:9 R/WPD Provisionable Default = 0x00 */ + /* Reserved for future use */ + unsigned int reserved0 : 2; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C432.1:0 R/WPD LED #2 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_2ActivityStretch : 2; /* 1E.C432.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + /*! \brief 1E.C432.2 R/WPD LED #2 Transmit Activity + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_2TransmitActivity : 1; /* 1E.C432.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C432.3 R/WPD LED #2 Receive Activity + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_2ReceiveActivity : 1; /* 1E.C432.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C432.4 R/WPD LED #2 Connecting + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_2Connecting : 1; /* 1E.C432.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C432.5 R/WPD LED #2 100 Mb/s Link Established + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s. + */ + unsigned int led_2_100Mb_sLinkEstablished : 1; /* 1E.C432.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s. */ + /*! \brief 1E.C432.6 R/WPD LED #2 1 Gb/s Link Established + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_2_1Gb_sLinkEstablished : 1; /* 1E.C432.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C432.7 R/WPD LED #2 10 Gb/s Link Established + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_2_10Gb_sLinkEstablished : 1; /* 1E.C432.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C432.8 R/WPD LED #2 Manual Set + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_2ManualSet : 1; /* 1E.C432.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + /*! \brief 1E.C432.D:9 R/WPD Reserved Provisioning C432 [4:0] + AQ_GlobalLedProvisioning_HHD.u2.bits_2.reservedProvisioningC432 + + Provisionable Default = 0x00 + + Reserved for future use + */ + unsigned int reservedProvisioningC432 : 5; /* 1E.C432.D:9 R/WPD Provisionable Default = 0x00 */ + /* Reserved for future use */ + unsigned int reserved0 : 2; + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of Global LED Provisioning */ + union + { + struct + { + /*! \brief 1E.C437.0 R/WPD LED Operation Mode + AQ_GlobalLedProvisioning_HHD.u7.bits_7.ledOperationMode + + Provisionable Default = 0x0 + + 1 = LED link activity in Mode #2 + 0 = LED link activity in Aquantia classic mode + + + Notes: + When set to 1, the LED blinking rate is based on Mode #2 algorithm. When set to 0, the LED blinking rate is based on the classic Aquantia algorithm. */ + unsigned int ledOperationMode : 1; /* 1E.C437.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED link activity in Mode #2 + 0 = LED link activity in Aquantia classic mode + */ + unsigned int reserved0 : 15; + } bits_7; + uint16_t word_7; + } u7; + /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_8; + uint16_t word_8; + } u8; + /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_9; + uint16_t word_9; + } u9; + /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_10; + uint16_t word_10; + } u10; + /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_11; + uint16_t word_11; + } u11; + /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_12; + uint16_t word_12; + } u12; + /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_13; + uint16_t word_13; + } u13; + /*! \brief Union for bit and word level access of word 14 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_14; + uint16_t word_14; + } u14; +} AQ_GlobalLedProvisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global General Provisioning: 1E.C440 */ +/* Global General Provisioning: 1E.C440 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved3 : 2; + unsigned int reserved2 : 1; + /*! \brief 1E.C441.3 R/WPD MDIO Preamble Detection Disable + AQ_GlobalGeneralProvisioning_HHD.u1.bits_1.mdioPreambleDetectionDisable + + Provisionable Default = 0x0 + + 1 = Suppress preamble detection on MDIO + 0 = Enable preamble detection on MDIO + + */ + unsigned int mdioPreambleDetectionDisable : 1; /* 1E.C441.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = Suppress preamble detection on MDIO + 0 = Enable preamble detection on MDIO + */ + /*! \brief 1E.C441.4 R/WPD MDIO Drive Configuration + AQ_GlobalGeneralProvisioning_HHD.u1.bits_1.mdioDriveConfiguration + + Provisionable Default = 0x0 + + 0 = MDIO driver is in normal mode + 1 = MDIO driver is in open drain mode + + + Notes: + When the MDIO driver is in open drain mode during a read cycle, "0" data will be actively driven out of the MDIO, "1" data will set the MDIO driver in high impedance state and an external pullup will set the MDIO line to "1". The Turn-Around "0" will also be actively driven out of the MDIO, therefore in open drain mode, the Turn-Around is still "Z0". */ + unsigned int mdioDriveConfiguration : 1; /* 1E.C441.4 R/WPD Provisionable Default = 0x0 */ + /* 0 = MDIO driver is in normal mode + 1 = MDIO driver is in open drain mode + */ + unsigned int reserved1 : 8; + /*! \brief 1E.C441.D R/WPD MDIO Read MSW First Enable + AQ_GlobalGeneralProvisioning_HHD.u1.bits_1.mdioReadMSW_FirstEnable + + Provisionable Default = 0x0 + + 1 = MSW of counter must be read first + 0 = LSW of counter must be read first + + + Notes: + This bit configures whether the MSW or LSW must be read first for counters greater than 16 bits. */ + unsigned int mdioReadMSW_FirstEnable : 1; /* 1E.C441.D R/WPD Provisionable Default = 0x0 */ + /* 1 = MSW of counter must be read first + 0 = LSW of counter must be read first + */ + /*! \brief 1E.C441.E R/WPD MDIO Broadcast Mode Enable + AQ_GlobalGeneralProvisioning_HHD.u1.bits_1.mdioBroadcastModeEnable + + Provisionable Default = 0x0 + + 1 = Enable broadcast on address set in 1E.C446 + 0 = Disable broadcast on n address set in 1E.C446 + + + Notes: + When enabled, writes and load MMD address opcodes are supported. Read opcodes are ignored. */ + unsigned int mdioBroadcastModeEnable : 1; /* 1E.C441.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable broadcast on address set in 1E.C446 + 0 = Disable broadcast on n address set in 1E.C446 + */ + unsigned int reserved0 : 1; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global General Provisioning */ + union + { + struct + { + /*! \brief 1E.C442.0 R/W Daisy Chain Reset + AQ_GlobalGeneralProvisioning_HHD.u2.bits_2.daisyChainReset + + Default = 0x0 + + 1 = Reset the daisy chain + + + Notes: + Toggling this bit from 0 to 1 will reload the IRAM and DRAM and reset the uP. The uP will be in uP run stall during the reload process. After the reload process, uP run stall will be de-asserted and the uP reset will be asserted. Note that before setting this bit, the See Soft Reset bit needs to be de-asserted. */ + unsigned int daisyChainReset : 1; /* 1E.C442.0 R/W Default = 0x0 */ + /* 1 = Reset the daisy chain + */ + unsigned int reserved0 : 15; + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of Global General Provisioning */ + union + { + struct + { + /*! \brief 1E.C447.4:0 R/WPD MDIO Broadcast Address Configuration [4:0] + AQ_GlobalGeneralProvisioning_HHD.u7.bits_7.mdioBroadcastAddressConfiguration + + Provisionable Default = 0x1F + + Broadcast address + + + Notes: + Allows setting the broadcast address. By default this is set to 0x1F */ + unsigned int mdioBroadcastAddressConfiguration : 5; /* 1E.C447.4:0 R/WPD Provisionable Default = 0x1F */ + /* Broadcast address + */ + unsigned int reserved0 : 11; + } bits_7; + uint16_t word_7; + } u7; + /*! \brief Union for bit and word level access of word 8 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_8; + uint16_t word_8; + } u8; + /*! \brief Union for bit and word level access of word 9 of Global General Provisioning */ + union + { + struct + { + /*! \brief 1E.C449.6:0 R/W MDIO Preamble Length [6:0] + AQ_GlobalGeneralProvisioning_HHD.u9.bits_9.mdioPreambleLength + + Default = 0x02 + + MDIO Preamble Length + + */ + unsigned int mdioPreambleLength : 7; /* 1E.C449.6:0 R/W Default = 0x02 */ + /* MDIO Preamble Length + */ + unsigned int reserved0 : 9; + } bits_9; + uint16_t word_9; + } u9; +} AQ_GlobalGeneralProvisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global NVR Provisioning: 1E.C450 */ +/* Global NVR Provisioning: 1E.C450 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global NVR Provisioning */ + union + { + struct + { + /*! \brief 1E.C450.1:0 R/WPD NVR Address Length [1:0] + AQ_GlobalNvrProvisioning_HHD.u0.bits_0.nvrAddressLength + + Provisionable Default = 0x2 + + NVR address length ranges from 0 bytes up to 3 bytes + + + Notes: + This sets the length of the address field used in read and write operations. Use of this field is enabled via Bit 8 of See Global NVR Provisioning 2: Address 1E.C451 . + */ + unsigned int nvrAddressLength : 2; /* 1E.C450.1:0 R/WPD Provisionable Default = 0x2 */ + /* NVR address length ranges from 0 bytes up to 3 bytes + */ + unsigned int reserved2 : 2; + /*! \brief 1E.C450.6:4 R/WPD NVR Dummy Length [2:0] + AQ_GlobalNvrProvisioning_HHD.u0.bits_0.nvrDummyLength + + Provisionable Default = 0x0 + + NVR dummy length ranges from 0 bytes to 4 bytes + + + Notes: + This sets the length of the dummy field used in some manufacturer's read status and write status operations. + */ + unsigned int nvrDummyLength : 3; /* 1E.C450.6:4 R/WPD Provisionable Default = 0x0 */ + /* NVR dummy length ranges from 0 bytes to 4 bytes + */ + unsigned int reserved1 : 1; + /*! \brief 1E.C450.A:8 R/WPD NVR Data Length [2:0] + AQ_GlobalNvrProvisioning_HHD.u0.bits_0.nvrDataLength + + Provisionable Default = 0x4 + + NVR data length ranges from 0 bytes to 4 bytes + + + Notes: + This sets the length of the data burst used in read and write operations. + */ + unsigned int nvrDataLength : 3; /* 1E.C450.A:8 R/WPD Provisionable Default = 0x4 */ + /* NVR data length ranges from 0 bytes to 4 bytes + */ + unsigned int reserved0 : 5; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global NVR Provisioning */ + union + { + struct + { + /*! \brief 1E.C451.7:0 R/WPD NVR Clock Divide [7:0] + AQ_GlobalNvrProvisioning_HHD.u1.bits_1.nvrClockDivide + + Provisionable Default = 0xA0 + + NVR clock divide. Clock frequency is divided by the NVR clock divide + 1 + + */ + unsigned int nvrClockDivide : 8; /* 1E.C451.7:0 R/WPD Provisionable Default = 0xA0 */ + /* NVR clock divide. Clock frequency is divided by the NVR clock divide + 1 + */ + /*! \brief 1E.C451.8 R/WPD NVR Address Length Override + AQ_GlobalNvrProvisioning_HHD.u1.bits_1.nvrAddressLengthOverride + + Provisionable Default = 0x0 + + 0 = NVR address length is based on the "NVR_SIZE" pin. + 1 = NVR address length is based on the See NVR Address Length [1:0] register + + + Notes: + When this bit = 0 and NVR_SIZE pin = 0, the NVR address length is 2 bytes. When this bit = 0 and the NVR_SIZE pin = 1, the NVR address length is 3 bytes. When this bit = 1 the NVR address length is from the See NVR Address Length [1:0] */ + unsigned int nvrAddressLengthOverride : 1; /* 1E.C451.8 R/WPD Provisionable Default = 0x0 */ + /* 0 = NVR address length is based on the "NVR_SIZE" pin. + 1 = NVR address length is based on the See NVR Address Length [1:0] register + */ + unsigned int reserved0 : 7; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global NVR Provisioning */ + union + { + struct + { + /*! \brief 1E.C452.0 R/W NVR Daisy Chain Disable + AQ_GlobalNvrProvisioning_HHD.u2.bits_2.nvrDaisyChainDisable + + Default = 0x0 + + 1 = Disable the Daisy Chain + + + Notes: + When in daisy chain master mode, the daisy chain and MDIO can both access the SPI. Setting this bit to 1 will disable the daisy chain from accessing the SPI and force it into a reset state. */ + unsigned int nvrDaisyChainDisable : 1; /* 1E.C452.0 R/W Default = 0x0 */ + /* 1 = Disable the Daisy Chain + */ + /*! \brief 1E.C452.1 R/W NVR Daisy Chain Clock Divide Override + AQ_GlobalNvrProvisioning_HHD.u2.bits_2.nvrDaisyChainClockDivideOverride + + Default = 0x0 + + 1 = Override NVR clock divide when in daisy chain master mode + + + Notes: + When in daisy chain master mode, the clock divide configuration is received from the FLASH. This bit will override the clock divide configuration from the FLASH with the See NVR Clock Divide [7:0] . */ + unsigned int nvrDaisyChainClockDivideOverride : 1; /* 1E.C452.1 R/W Default = 0x0 */ + /* 1 = Override NVR clock divide when in daisy chain master mode + */ + unsigned int reserved0 : 14; + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global NVR Provisioning */ + union + { + struct + { + unsigned int reserved1 : 4; + /*! \brief 1E.C453.4 R/W NVR Reset + AQ_GlobalNvrProvisioning_HHD.u3.bits_3.nvrReset + + Default = 0x0 + + 1 = Reset SPI + + */ + unsigned int nvrReset : 1; /* 1E.C453.4 R/W Default = 0x0 */ + /* 1 = Reset SPI + */ + unsigned int reserved0 : 11; + } bits_3; + uint16_t word_3; + } u3; +} AQ_GlobalNvrProvisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Reserved Provisioning: 1E.C470 */ +/* Global Reserved Provisioning: 1E.C470 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved2 : 4; + /*! \brief 1E.C470.4 R/WSC Initiate Cable Diagnostics + AQ_GlobalReservedProvisioning_HHD.u0.bits_0.initiateCableDiagnostics + + Default = 0x0 + + 1 = Perform cable diagnostics + + + Notes: + Perform cable diagnostics regardless of link state. If link is up, setting this bit will cause the link to drop while diagnostics are performed. This bit is self-clearing upon completion of the cable diagnostics. + + NOTE!! This is a processor intensive operation. Completion of this operation can also be monitored via 1E.C831.F */ + unsigned int initiateCableDiagnostics : 1; /* 1E.C470.4 R/WSC Default = 0x0 */ + /* 1 = Perform cable diagnostics + */ + unsigned int reserved1 : 3; + unsigned int reserved0 : 5; + /*! \brief 1E.C470.E:D R/WPD Extended MDI Diagnostics Select [1:0] + AQ_GlobalReservedProvisioning_HHD.u0.bits_0.extendedMdiDiagnosticsSelect + + Provisionable Default = 0x0 + + 0x0 = TDR Data + 0x1 = RFI Channel PSD + 0x2 = Noise PSD while the local Tx is Off + 0x3 = Noise PSD while the local Tx is On + + + Notes: + These bits select what sort of cable diagnostics to perform. For regular cable diagnostics, Bit F is set to zero, and the diagnostics are triggered by setting Bit 4. For extended diagnostics, Bit F is set to 1, and the desired extended diagnostics are selected by Bits E:D. The routine is then triggered by setting Bit 4. Each of the extended diagnostic routines present data for all for MDI pairs (A, B, C, D) consecutively, and after the data for each channel is gathered Bits F:D are reset. To get the data for the next pair, Bits F:D must be set back to the desired value (which must be the same as the initial channel). This continues until the data for all channels has been gathered. The address in memory where the data is stored is given in 1E.C802 and 1E.C804. + + For the case of PSD, the structure is as follows: + Int32 info + Int16 data[Len] + Info = Len << 16 | TxEnable << 8 | Pair (0 = A, etc.) + + For TDR: + Int32 info + Int16 tdr_A[Len] + Int16 tdr_B[Len] + Int16 tdr_C[Len] + Int16 tdr_D[Len] + + Info = Len << 16 | Channel + + TDR data is from the current pair to all other pairs. + + At the end of retrieving extended MDI diag data, the part will be reset. Conversely the only way to exit this routine once it starts is to issue a PMA reset. */ + unsigned int extendedMdiDiagnosticsSelect : 2; /* 1E.C470.E:D R/WPD Provisionable Default = 0x0 */ + /* 0x0 = TDR Data + 0x1 = RFI Channel PSD + 0x2 = Noise PSD while the local Tx is Off + 0x3 = Noise PSD while the local Tx is On + */ + /*! \brief 1E.C470.F R/WPD Diagnostics Select + AQ_GlobalReservedProvisioning_HHD.u0.bits_0.diagnosticsSelect + + Provisionable Default = 0x0 + + 1 = Provide Extended MDI Diagnostics Information. + 0 = Provide normal cable diagnostics + + + Notes: + These bits select what sort of cable diagnostics to perform. For regular cable diagnostics, Bit F is set to zero, and the diagnostics are triggered by setting Bit 4. For extended diagnostics, Bit F is set to 1, and the desired extended diagnostics are selected by Bits E:D. The routine is then triggered by setting Bit 4. Each of the extended diagnostic routines present data for all for MDI pairs (A, B, C, D) consecutively, and after the data for each channel is gathered Bits F:D are reset. To get the data for the next pair, Bits F:D must be set back to the desired value (which must be the same as the initial channel). This continues until the data for all channels has been gathered. The address in memory where the data is stored is given in 1E.C802 and 1E.C804. + + For the case of PSD, the structure is as follows: + Int32 info + Int16 data[Len] + Info = Len << 16 | TxEnable << 8 | Pair (0 = A, etc.) + + For TDR: + Int32 info + Int16 tdr_A[Len] + Int16 tdr_B[Len] + Int16 tdr_C[Len] + Int16 tdr_D[Len] + + Info = Len << 16 | Channel + + TDR data is from the current pair to all other pairs. + + At the end of retrieving extended MDI diag data, the part will be reset. Conversely the only way to exit this routine once it starts is to issue a PMA reset. */ + unsigned int diagnosticsSelect : 1; /* 1E.C470.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Provide Extended MDI Diagnostics Information. + 0 = Provide normal cable diagnostics + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C471.5:0 R/WuP Daisy-Chain Hop-Count Override Value [5:0] + AQ_GlobalReservedProvisioning_HHD.u1.bits_1.daisy_chainHop_countOverrideValue + + Default = 0x00 + + The value to use for the PHY's daisy-chain hop-count. Valid values are from 0 -> 47 + + + Notes: + Daisy-Chain Hop-Count Override should be used during MDIO boot-load operation, as the daisy-chain hop-count does not function when the daisy-chain is disabled (1E.C452.0). Setting this bit tells the processor where in the daisy-chain it is, so that the provisioning operation will function correctly. */ + unsigned int daisy_chainHop_countOverrideValue : 6; /* 1E.C471.5:0 R/WuP Default = 0x00 */ + /* The value to use for the PHY's daisy-chain hop-count. Valid values are from 0 -> 47 + */ + /*! \brief 1E.C471.6 R/WuP Enable Daisy-Chain Hop-Count Override + AQ_GlobalReservedProvisioning_HHD.u1.bits_1.enableDaisy_chainHop_countOverride + + Default = 0x0 + + 1 = Hop-count is set by Bits 5:0 + 0 = Hop-count is determined by the daisy-chain + + + Notes: + Daisy-Chain Hop-Count Override should be used during MDIO boot-load operation, as the daisy-chain hop-count does not function when the daisy-chain is disabled (1E.C452.0). Setting this bit tells the processor where in the daisy-chain it is, so that the provisioning operation will function correctly. */ + unsigned int enableDaisy_chainHop_countOverride : 1; /* 1E.C471.6 R/WuP Default = 0x0 */ + /* 1 = Hop-count is set by Bits 5:0 + 0 = Hop-count is determined by the daisy-chain + */ + unsigned int reserved0 : 9; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C472.0 R/WPDuP Enable 5th Channel RFI Cancellation + AQ_GlobalReservedProvisioning_HHD.u2.bits_2.enable_5thChannelRfiCancellation + + Provisionable Default = 0x0 + + 1 = 5th channel and RFI cancellers operation enabled + 0 = 5th channel AFE is powered down, 5th channel digital is clock gated, RFI cancellers are disabled + + + Notes: + Note: The value of this bit at the time of Autonegotiation sets the local PHY behavior until the next time Autonegotiation occurs. */ + unsigned int enable_5thChannelRfiCancellation : 1; /* 1E.C472.0 R/WPDuP Provisionable Default = 0x0 */ + /* 1 = 5th channel and RFI cancellers operation enabled + 0 = 5th channel AFE is powered down, 5th channel digital is clock gated, RFI cancellers are disabled + */ + /*! \brief 1E.C472.1 R/WPDuP Enable XENPAK Register Space + AQ_GlobalReservedProvisioning_HHD.u2.bits_2.enableXenpakRegisterSpace + + Provisionable Default = 0x0 + + 1 = XENPAK register space enabled + 0 = XENPAK register space disabled + + */ + unsigned int enableXenpakRegisterSpace : 1; /* 1E.C472.1 R/WPDuP Provisionable Default = 0x0 */ + /* 1 = XENPAK register space enabled + 0 = XENPAK register space disabled + */ + /*! \brief 1E.C472.5:2 R/WPD External VDD Change Request [3:0] + AQ_GlobalReservedProvisioning_HHD.u2.bits_2.externalVddChangeRequest + + Provisionable Default = 0x0 + + The amount of VDD change requested by firmware, in mV (2's complement value). + + */ + unsigned int externalVddChangeRequest : 4; /* 1E.C472.5:2 R/WPD Provisionable Default = 0x0 */ + /* The amount of VDD change requested by firmware, in mV (2's complement value). + */ + /*! \brief 1E.C472.6 R/WPD Tunable External VDD Power Supply Present + AQ_GlobalReservedProvisioning_HHD.u2.bits_2.tunableExternalVddPowerSupplyPresent + + Provisionable Default = 0x0 + + 1 = Tunable external VDD power supply present + 0 = No tunable external VDD power supply present + + + Notes: + This bit must be set if tuning of external power supply is desired. */ + unsigned int tunableExternalVddPowerSupplyPresent : 1; /* 1E.C472.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Tunable external VDD power supply present + 0 = No tunable external VDD power supply present + */ + unsigned int reserved1 : 7; + /*! \brief 1E.C472.E R/WPD Enable VDD Power Supply Tuning + AQ_GlobalReservedProvisioning_HHD.u2.bits_2.enableVddPowerSupplyTuning + + Provisionable Default = 0x0 + + 1 = Enable external VDD power supply tuning + 0 = Disable external VDD power supply tuning is disabled + + + Notes: + This bit controls whether the PHY attempts to tune the external VDD power supply via the SMBus. This bit is only operational if the external supply is present. (See 1E.C472.6) */ + unsigned int enableVddPowerSupplyTuning : 1; /* 1E.C472.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable external VDD power supply tuning + 0 = Disable external VDD power supply tuning is disabled + */ + unsigned int reserved0 : 1; + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C473.7:0 R/WPD Training SNR [7:0] + AQ_GlobalReservedProvisioning_HHD.u3.bits_3.trainingSNR + + Provisionable Default = 0x00 + + SNR during 10G training on the worst channel. SNR is in steps of 0.1dB + + + Notes: + The SNR margin that is enjoyed by the worst channel, over and above the minimum SNR required to operate at a BER of 10-12. It is reported with 0.1 dB of resolution to an accuracy of 0.5 dB within the range of -12.7 dB to 12.7 dB. The number is in offset binary, with 0.0 dB represented by 0x8000. */ + unsigned int trainingSNR : 8; /* 1E.C473.7:0 R/WPD Provisionable Default = 0x00 */ + /* SNR during 10G training on the worst channel. SNR is in steps of 0.1dB + */ + /*! \brief 1E.C473.A:8 R/WPD Rate Transition Request [2:0] + AQ_GlobalReservedProvisioning_HHD.u3.bits_3.rateTransitionRequest + + Provisionable Default = 0x0 + + 0 = No Transition + 1 = Reserved + 2 = Reserved + 3 = Retrain at 10G + 4 = Retrain at 5G + 5 = Retrain at 2.5G + 6 = Retrain at 1G + 7 = Reserved + + */ + unsigned int rateTransitionRequest : 3; /* 1E.C473.A:8 R/WPD Provisionable Default = 0x0 */ + /* 0 = No Transition + 1 = Reserved + 2 = Reserved + 3 = Retrain at 10G + 4 = Retrain at 5G + 5 = Retrain at 2.5G + 6 = Retrain at 1G + 7 = Reserved + */ + unsigned int reserved0 : 5; + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C474.0 R/W NVR Daisy Chain Kickstart + AQ_GlobalReservedProvisioning_HHD.u4.bits_4.nvrDaisyChainKickstart + + Default = 0x0 + + 1 = Kickstart the Daisy Chain + + + Notes: + When in daisy chain master mode, the PHY0 can kickstart the daisy chain. The kickstart will not reload the IRAM/DRAM or reset the uP for PHY0. It will just read the FLASH and transfer the FLASH data to the daisy chain. */ + unsigned int nvrDaisyChainKickstart : 1; /* 1E.C474.0 R/W Default = 0x0 */ + /* 1 = Kickstart the Daisy Chain + */ + /*! \brief 1E.C474.F:1 R/WPD Reserved Provisioning 5 [F:1] + AQ_GlobalReservedProvisioning_HHD.u4.bits_4.reservedProvisioning_5 + + Provisionable Default = 0x0000 + + Reserved for future use + + */ + unsigned int reservedProvisioning_5 : 15; /* 1E.C474.F:1 R/WPD Provisionable Default = 0x0000 */ + /* Reserved for future use + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved1 : 2; + /*! \brief 1E.C475.2 R/WPD Smart Power-Down Enable + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.smartPower_downEnable + + Provisionable Default = 0x0 + + 1 = Enable smart power down mode + 0 = Smart power-down mode disabled + + + Notes: + Smart power down (SPD) is the lowest power mode at which PHY is able to autonegotiate. SPD can be enabled with bit 1E.C475.2 */ + unsigned int smartPower_downEnable : 1; /* 1E.C475.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable smart power down mode + 0 = Smart power-down mode disabled + */ + /*! \brief 1E.C475.3 R/WPD Deadlock Avoidance Enable + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.deadlockAvoidanceEnable + + Provisionable Default = 0x0 + + 1 = SPD with deadlock avoidance: PHY transmits autonegotiation pulses (FLPs) at a slower rate (~ 1 FLP/ 100ms) than specified by autonegotiation standard (~1 FLP / 8.25ms). Receiver is active and able to detect the pulses. + 0 = SPD without deadlock avoidance: PHY transmitter is shut down, no autonegotiation pulses are sent on the line but the receiver is active and able to detect the pulses + + */ + unsigned int deadlockAvoidanceEnable : 1; /* 1E.C475.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = SPD with deadlock avoidance: PHY transmits autonegotiation pulses (FLPs) at a slower rate (~ 1 FLP/ 100ms) than specified by autonegotiation standard (~1 FLP / 8.25ms). Receiver is active and able to detect the pulses. + 0 = SPD without deadlock avoidance: PHY transmitter is shut down, no autonegotiation pulses are sent on the line but the receiver is active and able to detect the pulses + */ + /*! \brief 1E.C475.4 R/WPD CFR Support + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrSupport + + Provisionable Default = 0x0 + + 1 = Local PHY supports Cisco Fast Retrain + 0 = Local PHY does support Cisco Fast Retrain + + */ + unsigned int cfrSupport : 1; /* 1E.C475.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY supports Cisco Fast Retrain + 0 = Local PHY does support Cisco Fast Retrain + */ + /*! \brief 1E.C475.5 R/WPD CFR THP + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrTHP + + Provisionable Default = 0x0 + + 1 = Local PHY requires local PHY to enable THP + 0 = Local PHY does not require local PHY to enable THP + + */ + unsigned int cfrTHP : 1; /* 1E.C475.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY requires local PHY to enable THP + 0 = Local PHY does not require local PHY to enable THP + */ + /*! \brief 1E.C475.6 R/WPD CFR Extended Maxwait + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrExtendedMaxwait + + Provisionable Default = 0x0 + + 1 = Local PHY requires extended maxwait + 0 = Local PHY does not require extended maxwait + + */ + unsigned int cfrExtendedMaxwait : 1; /* 1E.C475.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY requires extended maxwait + 0 = Local PHY does not require extended maxwait + */ + /*! \brief 1E.C475.7 R/WPD CFR Disable Timer + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrDisableTimer + + Provisionable Default = 0x0 + + 1 = Local PHY requires cfr_disable timer + 0 = Local PHY does not require cfr_disable timer + + */ + unsigned int cfrDisableTimer : 1; /* 1E.C475.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY requires cfr_disable timer + 0 = Local PHY does not require cfr_disable timer + */ + /*! \brief 1E.C475.8 R/WPD CFR LP Support + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrLpSupport + + Provisionable Default = 0x0 + + 1 = Link partner supports Cisco Fast Retrain + 0 = Link partner does support Cisco Fast Retrain + + */ + unsigned int cfrLpSupport : 1; /* 1E.C475.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner supports Cisco Fast Retrain + 0 = Link partner does support Cisco Fast Retrain + */ + /*! \brief 1E.C475.9 R/WPD CFR LP THP + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrLpTHP + + Provisionable Default = 0x0 + + 1 = Link partner requires local PHY to enable THP + 0 = Link partner does not require local PHY to enable THP + + */ + unsigned int cfrLpTHP : 1; /* 1E.C475.9 R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner requires local PHY to enable THP + 0 = Link partner does not require local PHY to enable THP + */ + /*! \brief 1E.C475.A R/WPD CFR LP Extended Maxwait + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrLpExtendedMaxwait + + Provisionable Default = 0x0 + + 1 = Link partner requires extended maxwait + 0 = Link partner does not require extended maxwait + + */ + unsigned int cfrLpExtendedMaxwait : 1; /* 1E.C475.A R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner requires extended maxwait + 0 = Link partner does not require extended maxwait + */ + /*! \brief 1E.C475.B R/WPD CFR LP Disable Timer + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrLpDisableTimer + + Provisionable Default = 0x0 + + 1 = Link partner requires cfr_disable timer + 0 = Link partner does not require cfr_disable timer + + */ + unsigned int cfrLpDisableTimer : 1; /* 1E.C475.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner requires cfr_disable timer + 0 = Link partner does not require cfr_disable timer + */ + /*! \brief 1E.C475.C R/WPD Reserved Provisioning 6 + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.reservedProvisioning_6 + + Provisionable Default = 0x0 + + Internal reserved - do not modify + + */ + unsigned int reservedProvisioning_6 : 1; /* 1E.C475.C R/WPD Provisionable Default = 0x0 */ + /* Internal reserved - do not modify + */ + /*! \brief 1E.C475.D R/WPD Smart Power-Down Status + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.smartPower_downStatus + + Provisionable Default = 0x0 + + 1 = Smart Power-Down Active + 0 = Smart Power-Down Inactive + + */ + unsigned int smartPower_downStatus : 1; /* 1E.C475.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Smart Power-Down Active + 0 = Smart Power-Down Inactive + */ + unsigned int reserved0 : 2; + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Dummy union to fill space in the structure Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Dummy union to fill space in the structure Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_7; + uint16_t word_7; + } u7; + /*! \brief Union for bit and word level access of word 8 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C478.A:0 R/WPD Reserved Provisioning 9 [A:0] + AQ_GlobalReservedProvisioning_HHD.u8.bits_8.reservedProvisioning_9 + + Provisionable Default = 0x000 + + Reserved for future use + + */ + unsigned int reservedProvisioning_9 : 11; /* 1E.C478.A:0 R/WPD Provisionable Default = 0x000 */ + /* Reserved for future use + */ + /*! \brief 1E.C478.E:B R/WPD DTE Drop Reporting Timer [3:0] + AQ_GlobalReservedProvisioning_HHD.u8.bits_8.dteDropReportingTimer + + Provisionable Default = 0x0 + + Number of seconds between loss of link partner filter and assertion of no-power-needed state, in 5 second increments (e.g. 0x4 = 20 seconds). + + + Notes: + These bits are used to set how long the PHY waits after it no longer detects the link partner filter before declaring that power is not needed. */ + unsigned int dteDropReportingTimer : 4; /* 1E.C478.E:B R/WPD Provisionable Default = 0x0 */ + /* Number of seconds between loss of link partner filter and assertion of no-power-needed state, in 5 second increments (e.g. 0x4 = 20 seconds). + */ + /*! \brief 1E.C478.F R/WPD DTE Enable + AQ_GlobalReservedProvisioning_HHD.u8.bits_8.dteEnable + + Provisionable Default = 0x0 + + 1 = Enable DTE + 0 = Disable DTE + + */ + unsigned int dteEnable : 1; /* 1E.C478.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable DTE + 0 = Disable DTE + */ + } bits_8; + uint16_t word_8; + } u8; + /*! \brief Union for bit and word level access of word 9 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C479.E:0 R/WPD Reserved Provisioning 10 [E:0] + AQ_GlobalReservedProvisioning_HHD.u9.bits_9.reservedProvisioning_10 + + Provisionable Default = 0x0000 + + Reserved for future use + + */ + unsigned int reservedProvisioning_10 : 15; /* 1E.C479.E:0 R/WPD Provisionable Default = 0x0000 */ + /* Reserved for future use + */ + /*! \brief 1E.C479.F R/WPD Power Up Stall + AQ_GlobalReservedProvisioning_HHD.u9.bits_9.powerUpStall + + Provisionable Default = 0x0 + + 1 = Stall FW at Power Up + 0 = Unstall the FW + + + Notes: + This bit needs to be provisioned in Power Up Init for firmware to stall. */ + unsigned int powerUpStall : 1; /* 1E.C479.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Stall FW at Power Up + 0 = Unstall the FW + */ + } bits_9; + uint16_t word_9; + } u9; + /*! \brief Union for bit and word level access of word 10 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C47A.1:0 R/WPD Rate [1:0] + AQ_GlobalReservedProvisioning_HHD.u10.bits_10.rate + + Provisionable Default = 0x0 + + 0x3 = 10G + 0x2 = 1G + 0x1 = 100M + 0x0 = reserved + + + Notes: + These bits select the rate for the loopback and packet generation. SERDES configuration, as well autonegotiation is controlled accordingly when a loopback is selected. For instance, if 100M system loopback on the network interface is selected, SGMII on the system interface is enabled to connect at 100M, and if passthrough is enabled 100BASE-TX will be the only advertised rate and will force a re-autonegotiation if not already connected at 100M. + + NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F + + The controls in this register are identical to, and mirrored with, the controls in 4.C444. */ + unsigned int rate : 2; /* 1E.C47A.1:0 R/WPD Provisionable Default = 0x0 */ + /* 0x3 = 10G + 0x2 = 1G + 0x1 = 100M + 0x0 = reserved + */ + /*! \brief 1E.C47A.2 R/WPD Reserved Provisioning 11a + AQ_GlobalReservedProvisioning_HHD.u10.bits_10.reservedProvisioning_11a + + Provisionable Default = 0x0 + + Reserved for future use + + */ + unsigned int reservedProvisioning_11a : 1; /* 1E.C47A.2 R/WPD Provisionable Default = 0x0 */ + /* Reserved for future use + */ + /*! \brief 1E.C47A.3 R/WPD System I/F Packet Generation + AQ_GlobalReservedProvisioning_HHD.u10.bits_10.systemI_fPacketGeneration + + Provisionable Default = 0x0 + + 1 = CRPAT packet generation out 10G system interface + 0 = No CRPAT packet generation out 10G system interface + + + Notes: + Selecting this mode of operation causes the CRPAT packet generator in the PHY to output CRPAT packets on the selected 10G system interface (4.C441.F:E) + + NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F + + The controls in this register are identical to, and mirrored with, the controls in 4.C444. */ + unsigned int systemI_fPacketGeneration : 1; /* 1E.C47A.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = CRPAT packet generation out 10G system interface + 0 = No CRPAT packet generation out 10G system interface + */ + /*! \brief 1E.C47A.4 R/WPD Look-Aside Port Packet Generation + AQ_GlobalReservedProvisioning_HHD.u10.bits_10.look_asidePortPacketGeneration + + Provisionable Default = 0x0 + + 1 = CRPAT packet generation out 10G look-aside interface (KR0) + 0 = No CRPAT packet generation out 10G look-aside interface (KR0) + + + Notes: + Selecting this mode of operation causes the CRPAT packet generator in the PHY to output on KR0. + + NOTE!! This only functions if KR1 (SERDES2) is selected as the system interface in (4.C441.F:E). + + NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F + + The controls in this register are identical to, and mirrored with, the controls in 4.C444. */ + unsigned int look_asidePortPacketGeneration : 1; /* 1E.C47A.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = CRPAT packet generation out 10G look-aside interface (KR0) + 0 = No CRPAT packet generation out 10G look-aside interface (KR0) + */ + /*! \brief 1E.C47A.5 R/WPD MDI Packet Generation + AQ_GlobalReservedProvisioning_HHD.u10.bits_10.mdiPacketGeneration + + Provisionable Default = 0x0 + + 1 = CRPAT packet generation out MDI interface + 0 = No CRPAT packet generation out MDI interface + + + Notes: + Selecting this mode of operation causes the CRPAT packet generator in the PHY to output on the MDI interface at the selected rate. + + NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F + + The controls in this register are identical to, and mirrored with, the controls in 4.C444. */ + unsigned int mdiPacketGeneration : 1; /* 1E.C47A.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = CRPAT packet generation out MDI interface + 0 = No CRPAT packet generation out MDI interface + */ + /*! \brief 1E.C47A.A:6 R/WPD Reserved Provisioning 11 [4:0] + AQ_GlobalReservedProvisioning_HHD.u10.bits_10.reservedProvisioning_11 + + Provisionable Default = 0x00 + + Reserved for future use + + */ + unsigned int reservedProvisioning_11 : 5; /* 1E.C47A.A:6 R/WPD Provisionable Default = 0x00 */ + /* Reserved for future use + */ + /*! \brief 1E.C47A.F:B R/WPD Loopback Control [4:0] + AQ_GlobalReservedProvisioning_HHD.u10.bits_10.loopbackControl + + Provisionable Default = 0x00 + + 0x00 = No loopback + 0x01 = System Interface - System Loopback + 0x02 = System Interface - System Loopback with Passthrough + 0x03 = System Interface - Network Loopback + 0x04 = System Interface - Network Loopback with Passthrough + 0x05 = System Interface - Network Loopback with Passthrough and Merge + 0x06 = System Interface - Peer-to-peer loopback + 0x07 - 0x08 = Reserved + 0x09 = Network Interface - System Loopback + 0x0A = Network Interface - System Loopback with Passthrough + 0x0B = Network Interface - Network Loopback + 0x0C = Network Interface - Network Loopback with Passthrough + 0x0D = Network Interface - Peer-to-peer loopback + 0x0E - 0x0F = Reserved + 0x10 = Cross-connect System Loopback + 0x11 = Cross-connect Network Loopback + 0x12 - 0x13 = Reserved + 0x14 = Network Interface - System Loopback via Loopback Plug + 0x15 - 0x1F = Reserved + + + Notes: + These bits, in conjunction with the chip configuration and the rate (Bits 1:0), select the loopback to configure for the chip. Setting one of these loopbacks provisions the chip for the specified loopback. Upon clearing the loopback, the chip returns to it's configuration prior to entering loopback (irregardless of whether other loopbacks were selected after the initial loopback). + + NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F. + + The controls in this register are identical to, and mirrored with, the controls in 4.C444. + */ + unsigned int loopbackControl : 5; /* 1E.C47A.F:B R/WPD Provisionable Default = 0x00 */ + /* 0x00 = No loopback + 0x01 = System Interface - System Loopback + 0x02 = System Interface - System Loopback with Passthrough + 0x03 = System Interface - Network Loopback + 0x04 = System Interface - Network Loopback with Passthrough + 0x05 = System Interface - Network Loopback with Passthrough and Merge + 0x06 = System Interface - Peer-to-peer loopback + 0x07 - 0x08 = Reserved + 0x09 = Network Interface - System Loopback + 0x0A = Network Interface - System Loopback with Passthrough + 0x0B = Network Interface - Network Loopback + 0x0C = Network Interface - Network Loopback with Passthrough + 0x0D = Network Interface - Peer-to-peer loopback + 0x0E - 0x0F = Reserved + 0x10 = Cross-connect System Loopback + 0x11 = Cross-connect Network Loopback + 0x12 - 0x13 = Reserved + 0x14 = Network Interface - System Loopback via Loopback Plug + 0x15 - 0x1F = Reserved + */ + } bits_10; + uint16_t word_10; + } u10; + /*! \brief Union for bit and word level access of word 11 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C47B.0 R/WPD Enable PTP + AQ_GlobalReservedProvisioning_HHD.u11.bits_11.enablePtp + + Provisionable Default = 0x0 + + 1 = PTP functionality is enabled + 0 = PTP functionality is disabled + + + Notes: + If this bit is 1, the PTP/SEC block will be included in the data path, regardless of operating mode. */ + unsigned int enablePtp : 1; /* 1E.C47B.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = PTP functionality is enabled + 0 = PTP functionality is disabled + */ + /*! \brief 1E.C47B.1 R/WPD Enable MACSec + AQ_GlobalReservedProvisioning_HHD.u11.bits_11.enableMacsec + + Provisionable Default = 0x0 + + 1 = MACSec functionality is enabled + 0 = MACSec functionality is disabled + + + Notes: + If this bit is 1, the PTP/SEC block will be included in the data path, regardless of operating mode. */ + unsigned int enableMacsec : 1; /* 1E.C47B.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = MACSec functionality is enabled + 0 = MACSec functionality is disabled + */ + /*! \brief 1E.C47B.F:2 R/WPD Reserved Provisioning 12 [D:0] + AQ_GlobalReservedProvisioning_HHD.u11.bits_11.reservedProvisioning_12 + + Provisionable Default = 0x0000 + + Reserved for future use + + */ + unsigned int reservedProvisioning_12 : 14; /* 1E.C47B.F:2 R/WPD Provisionable Default = 0x0000 */ + /* Reserved for future use + */ + } bits_11; + uint16_t word_11; + } u11; +} AQ_GlobalReservedProvisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief PIF Mailbox Control: 1E.C47C */ +/* PIF Mailbox Control: 1E.C47C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of PIF Mailbox Control */ + union + { + struct + { + /*! \brief 1E.C47C.F:0 R/WPDuP PIF Mailbox Address [F:0] + AQ_PifMailboxControl_HHD.u0.bits_0.pifMailboxAddress + + Provisionable Default = 0x0000 + + The least 16 bits of the PIF address to read or write. + + */ + unsigned int pifMailboxAddress : 16; /* 1E.C47C.F:0 R/WPDuP Provisionable Default = 0x0000 */ + /* The least 16 bits of the PIF address to read or write. + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of PIF Mailbox Control */ + union + { + struct + { + /*! \brief 1E.C47D.F:0 R/WPDuP PIF Mailbox Data [F:0] + AQ_PifMailboxControl_HHD.u1.bits_1.pifMailboxData + + Provisionable Default = 0x0000 + + The data to be written, or that had been read. + + */ + unsigned int pifMailboxData : 16; /* 1E.C47D.F:0 R/WPDuP Provisionable Default = 0x0000 */ + /* The data to be written, or that had been read. + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of PIF Mailbox Control */ + union + { + struct + { + /*! \brief 1E.C47E.7:0 R/WPDuP PIF Mailbox MMD [7:0] + AQ_PifMailboxControl_HHD.u2.bits_2.pifMailboxMMD + + Provisionable Default = 0x00 + + MMD (upper 8 bits) of the PID address to read or write. + + */ + unsigned int pifMailboxMMD : 8; /* 1E.C47E.7:0 R/WPDuP Provisionable Default = 0x00 */ + /* MMD (upper 8 bits) of the PID address to read or write. + */ + /*! \brief 1E.C47E.B:8 R/WPDuP PIF Mailbox Command Type [3:0] + AQ_PifMailboxControl_HHD.u2.bits_2.pifMailboxCommandType + + Provisionable Default = 0x0 + + 0 = No Action + 1 = Read + 2 = Write + + + Notes: + System SW writes non-zero value to start a PIF command. */ + unsigned int pifMailboxCommandType : 4; /* 1E.C47E.B:8 R/WPDuP Provisionable Default = 0x0 */ + /* 0 = No Action + 1 = Read + 2 = Write + */ + /*! \brief 1E.C47E.F:C R/WPD Reserved PIF Mailbox Control 3 [3:0] + AQ_PifMailboxControl_HHD.u2.bits_2.reservedPifMailboxControl_3 + + Provisionable Default = 0x0 + + Reserved for future use + + */ + unsigned int reservedPifMailboxControl_3 : 4; /* 1E.C47E.F:C R/WPD Provisionable Default = 0x0 */ + /* Reserved for future use + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of PIF Mailbox Control */ + union + { + struct + { + /*! \brief 1E.C47F.3:0 R/WPDuP PIF Mailbox Command Status [3:0] + AQ_PifMailboxControl_HHD.u3.bits_3.pifMailboxCommandStatus + + Provisionable Default = 0x0 + + 0 = Idle + 1 = Command completed + 2 = Command did not complete + + + Notes: + System SW should write 0 before writing Command Type to clear completion status */ + unsigned int pifMailboxCommandStatus : 4; /* 1E.C47F.3:0 R/WPDuP Provisionable Default = 0x0 */ + /* 0 = Idle + 1 = Command completed + 2 = Command did not complete + */ + /*! \brief 1E.C47F.F:4 R/WPD Reserved PIF Mailbox Control 4 [B:0] + AQ_PifMailboxControl_HHD.u3.bits_3.reservedPifMailboxControl_4 + + Provisionable Default = 0x000 + + Reserved for future use + + */ + unsigned int reservedPifMailboxControl_4 : 12; /* 1E.C47F.F:4 R/WPD Provisionable Default = 0x000 */ + /* Reserved for future use + */ + } bits_3; + uint16_t word_3; + } u3; +} AQ_PifMailboxControl_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global SMBus 0 Provisioning: 1E.C485 */ +/* Global SMBus 0 Provisioning: 1E.C485 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global SMBus 0 Provisioning */ + union + { + struct + { + unsigned int reserved1 : 1; + /*! \brief 1E.C485.7:1 R/W SMB 0 Slave Address [7:1] + AQ_GlobalSmbus_0Provisioning_HHD.u0.bits_0.smb_0SlaveAddress + + Default = 0x00 + + SMB slave address configuration + + */ + unsigned int smb_0SlaveAddress : 7; /* 1E.C485.7:1 R/W Default = 0x00 */ + /* SMB slave address configuration + */ + unsigned int reserved0 : 8; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalSmbus_0Provisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global SMBus 1 Provisioning: 1E.C495 */ +/* Global SMBus 1 Provisioning: 1E.C495 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global SMBus 1 Provisioning */ + union + { + struct + { + unsigned int reserved1 : 1; + /*! \brief 1E.C495.7:1 R/W SMB 1 Slave Address [7:1] + AQ_GlobalSmbus_1Provisioning_HHD.u0.bits_0.smb_1SlaveAddress + + Default = 0x00 + + SMB slave address configuration + + */ + unsigned int smb_1SlaveAddress : 7; /* 1E.C495.7:1 R/W Default = 0x00 */ + /* SMB slave address configuration + */ + unsigned int reserved0 : 8; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalSmbus_1Provisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global EEE Provisioning: 1E.C4A0 */ +/* Global EEE Provisioning: 1E.C4A0 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global EEE Provisioning */ + union + { + struct + { + /*! \brief 1E.C4A0.0 R/WPD EEE Mode + AQ_GlobalEeeProvisioning_HHD.u0.bits_0.eeeMode + + Provisionable Default = 0x0 + + 1 = EEE mode of operation + + + Notes: + EEE mode of operation (0=disable, 1=enable, default:0) */ + unsigned int eeeMode : 1; /* 1E.C4A0.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = EEE mode of operation + */ + unsigned int reserved0 : 15; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalEeeProvisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Cable Diagnostic Status: 1E.C800 */ +/* Global Cable Diagnostic Status: 1E.C800 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C800.2:0 RO Pair D Status [2:0] + AQ_GlobalCableDiagnosticStatus_HHD.u0.bits_0.pairDStatus + + + + [6:4] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair C + 010= Connected to Pair B + 001= Connected to Pair A + 000= OK + + Notes: + This register summarizes the worst impairment on Pair D. */ + unsigned int pairDStatus : 3; /* 1E.C800.2:0 RO */ + /* [6:4] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair C + 010= Connected to Pair B + 001= Connected to Pair A + 000= OK */ + unsigned int reserved3 : 1; + /*! \brief 1E.C800.6:4 RO Pair C Status [2:0] + AQ_GlobalCableDiagnosticStatus_HHD.u0.bits_0.pairCStatus + + + + [9:7] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair B + 010= Connected to Pair A + 001= Connected to Pair D + 000= OK + + Notes: + This register summarizes the worst impairment on Pair C. */ + unsigned int pairCStatus : 3; /* 1E.C800.6:4 RO */ + /* [9:7] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair B + 010= Connected to Pair A + 001= Connected to Pair D + 000= OK */ + unsigned int reserved2 : 1; + /*! \brief 1E.C800.A:8 RO Pair B Status [2:0] + AQ_GlobalCableDiagnosticStatus_HHD.u0.bits_0.pairBStatus + + + + [C:A] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair A + 010= Connected to Pair D + 001= Connected to Pair C + 000= OK + + Notes: + This register summarizes the worst impairment on Pair B. */ + unsigned int pairBStatus : 3; /* 1E.C800.A:8 RO */ + /* [C:A] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair A + 010= Connected to Pair D + 001= Connected to Pair C + 000= OK */ + unsigned int reserved1 : 1; + /*! \brief 1E.C800.E:C RO Pair A Status [2:0] + AQ_GlobalCableDiagnosticStatus_HHD.u0.bits_0.pairAStatus + + + + [F:D] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair D + 010= Connected to Pair C + 001= Connected to Pair B + 000= OK + + Notes: + This register summarizes the worst impairment on Pair A. */ + unsigned int pairAStatus : 3; /* 1E.C800.E:C RO */ + /* [F:D] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair D + 010= Connected to Pair C + 001= Connected to Pair B + 000= OK */ + unsigned int reserved0 : 1; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C801.7:0 RO Pair A Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u1.bits_1.pairAReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair A + + Notes: + The distance to this reflection is given in See Global Reserved Status 1: Address 1E.C870 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairAReflection_2 : 8; /* 1E.C801.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair A */ + /*! \brief 1E.C801.F:8 RO Pair A Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u1.bits_1.pairAReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair A + + Notes: + The distance to this reflection is given in See Global Reserved Status 1: Address 1E.C870 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairAReflection_1 : 8; /* 1E.C801.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair A */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C802.F:0 RO Impulse Response MSW [F:0] + AQ_GlobalCableDiagnosticStatus_HHD.u2.bits_2.impulseResponseMSW + + + + The MSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type in 1E.C470.E:D + + Notes: + See 1E.C470 for more information */ + unsigned int impulseResponseMSW : 16; /* 1E.C802.F:0 RO */ + /* The MSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type in 1E.C470.E:D */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C803.7:0 RO Pair B Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u3.bits_3.pairBReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair B + + Notes: + The distance to this reflection is given in See Global Reserved Status 2: Address 1E.C871 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairBReflection_2 : 8; /* 1E.C803.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair B */ + /*! \brief 1E.C803.F:8 RO Pair B Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u3.bits_3.pairBReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair B + + Notes: + The distance to this reflection is given in See Global Reserved Status 2: Address 1E.C871 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairBReflection_1 : 8; /* 1E.C803.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair B */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C804.F:0 RO Impulse Response LSW [F:0] + AQ_GlobalCableDiagnosticStatus_HHD.u4.bits_4.impulseResponseLSW + + + + The LSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type specified in 1E.C470.E:D + + Notes: + See 1E.C470 for more information */ + unsigned int impulseResponseLSW : 16; /* 1E.C804.F:0 RO */ + /* The LSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type specified in 1E.C470.E:D */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C805.7:0 RO Pair C Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u5.bits_5.pairCReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair C + + Notes: + The distance to this reflection is given in See Global Reserved Status 3: Address 1E.C872 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairCReflection_2 : 8; /* 1E.C805.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair C */ + /*! \brief 1E.C805.F:8 RO Pair C Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u5.bits_5.pairCReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair C + + Notes: + The distance to this reflection is given in See Global Reserved Status 3: Address 1E.C872 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairCReflection_1 : 8; /* 1E.C805.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair C */ + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C806.F:0 RO Reserved 1 [F:0] + AQ_GlobalCableDiagnosticStatus_HHD.u6.bits_6.reserved_1 + + + + Reserved for future use + */ + unsigned int reserved_1 : 16; /* 1E.C806.F:0 RO */ + /* Reserved for future use */ + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C807.7:0 RO Pair D Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u7.bits_7.pairDReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair D + + Notes: + The distance to this reflection is given in See Global Reserved Status 4: Address 1E.C873 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairDReflection_2 : 8; /* 1E.C807.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair D */ + /*! \brief 1E.C807.F:8 RO Pair D Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u7.bits_7.pairDReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair D + + Notes: + The distance to this reflection is given in See Global Reserved Status 4: Address 1E.C873 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairDReflection_1 : 8; /* 1E.C807.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair D */ + } bits_7; + uint16_t word_7; + } u7; +} AQ_GlobalCableDiagnosticStatus_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Thermal Status: 1E.C820 */ +/* Global Thermal Status: 1E.C820 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Thermal Status */ + union + { + struct + { + /*! \brief 1E.C820.F:0 RO Temperature [F:0] + AQ_GlobalThermalStatus_HHD.u0.bits_0.temperature + + + + [F:0] of temperature + + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 70 degreesC. This is a mirror of the XENPAK register 1.A060 - 1.A061. The mirror is performed in H/W. */ + unsigned int temperature : 16; /* 1E.C820.F:0 RO */ + /* [F:0] of temperature + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Thermal Status */ + union + { + struct + { + /*! \brief 1E.C821.0 RO Temperature Ready + AQ_GlobalThermalStatus_HHD.u1.bits_1.temperatureReady + + + + 1 = Temperature measurement is valid + + + Notes: + This is a mirror of the XENPAK register 1.A06E. */ + unsigned int temperatureReady : 1; /* 1E.C821.0 RO */ + /* 1 = Temperature measurement is valid + */ + unsigned int reserved0 : 15; + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalThermalStatus_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global General Status: 1E.C830 */ +/* Global General Status: 1E.C830 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global General Status */ + union + { + struct + { + unsigned int reserved1 : 11; + /*! \brief 1E.C830.B RO Low Temperature Warning State + AQ_GlobalGeneralStatus_HHD.u0.bits_0.lowTemperatureWarningState + + + + 1 = Low temperature warning threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A074.6 register. + + */ + unsigned int lowTemperatureWarningState : 1; /* 1E.C830.B RO */ + /* 1 = Low temperature warning threshold has been exceeded */ + /*! \brief 1E.C830.C RO High Temperature Warning State + AQ_GlobalGeneralStatus_HHD.u0.bits_0.highTemperatureWarningState + + + + 1 = High temperature warning threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A074.7 register. + + */ + unsigned int highTemperatureWarningState : 1; /* 1E.C830.C RO */ + /* 1 = High temperature warning threshold has been exceeded */ + /*! \brief 1E.C830.D RO Low Temperature Failure State + AQ_GlobalGeneralStatus_HHD.u0.bits_0.lowTemperatureFailureState + + + + 1 = Low temperature failure threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A070.6 register. + + */ + unsigned int lowTemperatureFailureState : 1; /* 1E.C830.D RO */ + /* 1 = Low temperature failure threshold has been exceeded */ + /*! \brief 1E.C830.E RO High Temperature Failure State + AQ_GlobalGeneralStatus_HHD.u0.bits_0.highTemperatureFailureState + + + + 1 = High temperature failure threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A070.7 register. + + */ + unsigned int highTemperatureFailureState : 1; /* 1E.C830.E RO */ + /* 1 = High temperature failure threshold has been exceeded */ + unsigned int reserved0 : 1; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global General Status */ + union + { + struct + { + unsigned int reserved0 : 15; + /*! \brief 1E.C831.F RO Processor Intensive MDIO Operation In- Progress + AQ_GlobalGeneralStatus_HHD.u1.bits_1.processorIntensiveMdioOperationIn_Progress + + + + 1 = PHY microprocessor is busy with a processor-intensive MDIO operation + 0 = Processor-intensive MDIO operation completed + + + Notes: + This bit should may be used with certain processor-intensive MDIO commands (such as Loopbacks, Test Modes, Low power modes, Tx-Disable, Restart autonegotiation, Cable Diagnostics, etc.) that take longer than an MDIO cycle to complete. Upon receiving an MDIO command that involves the PHY's microprocessor, this bit is set, and when the command is completed, this bit is cleared. + + NOTE!!! This bit should be checked only after 1 ms of issuing a processor-intensive MDIO operation. + + The list of operations that set this bit are as follows: + + 1.0.0, PMA Loopback + 1.0.B, Low power mode + 1.9.4:0, Tx Disable + 1.84, 10G Test modes + 1.8000.5, XENPAK Control + 1.9000, XENPAK Rx Fault Enable + 1.9002, XENPAK Alarm Enable + 1.E400.F, External loopback + 3.0.B, Low power mode + 3.0.E, System PCS loopback + 3.C471.5, PRBS Test + 3.C471.6, PRBS Test + 3.E471.5, PRBS Test + 3.E471.6, PRBS Test + 4.0.B, Low power mode + 4.0.E, PHY-XS network loopback + 4.C440, Output clock control, Load SERDES parameters + 4.F802.E, System loopback + 4.C444.F:B, Loopback Control + 4.C444.4:2, Packet generation + 4.C445.C, SERDES calibration + 7.0.9, Restart autonegotiation + 1D.C280, 1G/100M Network loopback + 1D.C500, 1G System loopback + 1D.C501, 1G / 100M Test modes + 1E.C470.4, Cable diagnostics + 1E.C47A.F:B, Loopback Control + 1E.C47A.4:2, Packet generation */ + unsigned int processorIntensiveMdioOperationIn_Progress : 1; /* 1E.C831.F RO */ + /* 1 = PHY microprocessor is busy with a processor-intensive MDIO operation + 0 = Processor-intensive MDIO operation completed + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalGeneralStatus_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Pin Status: 1E.C840 */ +/* Global Pin Status: 1E.C840 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Pin Status */ + union + { + struct + { + /*! \brief 1E.C840.5:0 RO LED Pullup State [5:0] + AQ_GlobalPinStatus_HHD.u0.bits_0.ledPullupState + + + + 1 = LED output pin is pulled high + 0 = LED output pin is pulled low + + */ + unsigned int ledPullupState : 6; /* 1E.C840.5:0 RO */ + /* 1 = LED output pin is pulled high + 0 = LED output pin is pulled low + */ + unsigned int reserved4 : 1; + /*! \brief 1E.C840.7 RO Tx Enable + AQ_GlobalPinStatus_HHD.u0.bits_0.txEnable + + + + Current Value of Tx Enable pin + + + Notes: + 0 = Disable Transmitter */ + unsigned int txEnable : 1; /* 1E.C840.7 RO */ + /* Current Value of Tx Enable pin + */ + unsigned int reserved3 : 1; + /*! \brief 1E.C840.9 RO Package Connectivity + AQ_GlobalPinStatus_HHD.u0.bits_0.packageConnectivity + + + + Value of the package connection pin + + */ + unsigned int packageConnectivity : 1; /* 1E.C840.9 RO */ + /* Value of the package connection pin + */ + unsigned int reserved2 : 3; + /*! \brief 1E.C840.D RO DC_MASTER_N + AQ_GlobalPinStatus_HHD.u0.bits_0.dcMasterN + + + + Value of DC_MASTER_N pin: + + 0x1 = PHY Slave Daisy Chain Boot + 0x0 = PHY Master Daisy Chain Boot from FLASH + */ + unsigned int dcMasterN : 1; /* 1E.C840.D RO */ + /* Value of DC_MASTER_N pin: + + 0x1 = PHY Slave Daisy Chain Boot + 0x0 = PHY Master Daisy Chain Boot from FLASH */ + unsigned int reserved1 : 1; + unsigned int reserved0 : 1; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalPinStatus_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Daisy Chain Status: 1E.C842 */ +/* Global Daisy Chain Status: 1E.C842 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Daisy Chain Status */ + union + { + struct + { + /*! \brief 1E.C842.F:0 RO Rx Daisy Chain Calculated CRC [F:0] + AQ_GlobalDaisyChainStatus_HHD.u0.bits_0.rxDaisyChainCalculatedCrc + + + + Rx Daisy Chain Calculated CRC + + + Notes: + This is the calculated daisy chain CRC. */ + unsigned int rxDaisyChainCalculatedCrc : 16; /* 1E.C842.F:0 RO */ + /* Rx Daisy Chain Calculated CRC + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalDaisyChainStatus_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Fault Message: 1E.C850 */ +/* Global Fault Message: 1E.C850 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Fault Message */ + union + { + struct + { + /*! \brief 1E.C850.F:0 RO Message [F:0] + AQ_GlobalFaultMessage_HHD.u0.bits_0.message + + + + Error code describing fault + + Notes: + Code 0x8001: Firmware not compatible with chip architecture. This fault occurs when firmware compiled for a different microprocessor core is loaded. + Code 0x8002: VCO calibration failed. This occurs when the main PLLs on chip fail to lock: this is not possible to trigger. + Code 0x8003: XAUI calibration failed. This occurs when the XAUI PLLs fail to lock: this is not possible to trigger. + Code 0x8005: Unexpected device ID. This occurs if the device ID programmed into the internal E-Fuse registers in not valid: this is not possible to trigger. + Code 0x8006: Computed checksum does not match expected checksum. This occurs when the FLASH checksum check performed at boot time fails. This only occurs when the system boots from FLASH. + Code 0x8007: Detected a bit error in static memory. To trigger, corrupt one of the static regions. + Code 0xC001: Illegal Instruction exception. This occurs when the processor attempts to execute an illegal instruction. To trigger this, write an illegal instruction to program memory. It's possible that the bit error check will trigger before the illegal instruction is executed. + Code 0xC002 Instruction Fetch Error. Internal physical address or a data error during instruction fetch: this is not possible to trigger. + Code 0xC003 Load Store Error. Internal physical address or data error during load store operation: this is not possible to trigger.. + Code 0xC004 Privileged Instruction. Attempt to execute a privileged operation without sufficient privilege: this is not possible to trigger. + Code 0xC005 Unaligned Load or Store. Attempt to load or store data at an address which cannot be handled due to alignment: this is not possible to trigger. + Code 0xC006 Instruction fetch from prohibited space: this is not possible to trigger. + Code 0xC007 Data load from prohibited space: this is not possible to trigger. + Code 0xC008 Data store into prohibited space: this is not possible to trigger. */ + unsigned int message : 16; /* 1E.C850.F:0 RO */ + /* Error code describing fault */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalFaultMessage_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Cable Diagnostic Impedance: 1E.C880 */ +/* Global Cable Diagnostic Impedance: 1E.C880 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C880.2:0 RO Pair A Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.pairAReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_4 : 3; /* 1E.C880.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C880.3 RO Reserved 4 + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.reserved_4 + + + + Reserved + + */ + unsigned int reserved_4 : 1; /* 1E.C880.3 RO */ + /* Reserved + */ + /*! \brief 1E.C880.6:4 RO Pair A Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.pairAReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_3 : 3; /* 1E.C880.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C880.7 RO Reserved 3 + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.reserved_3 + + + + Reserved + + */ + unsigned int reserved_3 : 1; /* 1E.C880.7 RO */ + /* Reserved + */ + /*! \brief 1E.C880.A:8 RO Pair A Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.pairAReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_2 : 3; /* 1E.C880.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C880.B RO Reserved 2 + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.reserved_2 + + + + Reserved + + */ + unsigned int reserved_2 : 1; /* 1E.C880.B RO */ + /* Reserved + */ + /*! \brief 1E.C880.E:C RO Pair A Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.pairAReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_1 : 3; /* 1E.C880.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C880.F RO Reserved 1 + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.reserved_1 + + + + Reserved + + */ + unsigned int reserved_1 : 1; /* 1E.C880.F RO */ + /* Reserved + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C881.2:0 RO Pair B Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.pairBReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_4 : 3; /* 1E.C881.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C881.3 RO Reserved 8 + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.reserved_8 + + + + Reserved + + */ + unsigned int reserved_8 : 1; /* 1E.C881.3 RO */ + /* Reserved + */ + /*! \brief 1E.C881.6:4 RO Pair B Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.pairBReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_3 : 3; /* 1E.C881.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C881.7 RO Reserved 7 + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.reserved_7 + + + + Reserved + + */ + unsigned int reserved_7 : 1; /* 1E.C881.7 RO */ + /* Reserved + */ + /*! \brief 1E.C881.A:8 RO Pair B Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.pairBReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_2 : 3; /* 1E.C881.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C881.B RO Reserved 6 + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.reserved_6 + + + + Reserved + + */ + unsigned int reserved_6 : 1; /* 1E.C881.B RO */ + /* Reserved + */ + /*! \brief 1E.C881.E:C RO Pair B Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.pairBReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_1 : 3; /* 1E.C881.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C881.F RO Reserved 5 + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.reserved_5 + + + + Reserved + + */ + unsigned int reserved_5 : 1; /* 1E.C881.F RO */ + /* Reserved + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C882.2:0 RO Pair C Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.pairCReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_4 : 3; /* 1E.C882.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C882.3 RO Reserved 12 + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.reserved_12 + + + + Reserved + + */ + unsigned int reserved_12 : 1; /* 1E.C882.3 RO */ + /* Reserved + */ + /*! \brief 1E.C882.6:4 RO Pair C Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.pairCReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_3 : 3; /* 1E.C882.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C882.7 RO Reserved 11 + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.reserved_11 + + + + Reserved + + */ + unsigned int reserved_11 : 1; /* 1E.C882.7 RO */ + /* Reserved + */ + /*! \brief 1E.C882.A:8 RO Pair C Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.pairCReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_2 : 3; /* 1E.C882.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C882.B RO Reserved 10 + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.reserved_10 + + + + Reserved + + */ + unsigned int reserved_10 : 1; /* 1E.C882.B RO */ + /* Reserved + */ + /*! \brief 1E.C882.E:C RO Pair C Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.pairCReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_1 : 3; /* 1E.C882.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C882.F RO Reserved 9 + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.reserved_9 + + + + Reserved + + */ + unsigned int reserved_9 : 1; /* 1E.C882.F RO */ + /* Reserved + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C883.2:0 RO Pair D Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.pairDReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_4 : 3; /* 1E.C883.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C883.3 RO Reserved 16 + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.reserved_16 + + + + Reserved + + */ + unsigned int reserved_16 : 1; /* 1E.C883.3 RO */ + /* Reserved + */ + /*! \brief 1E.C883.6:4 RO Pair D Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.pairDReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_3 : 3; /* 1E.C883.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C883.7 RO Reserved 15 + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.reserved_15 + + + + Reserved + + */ + unsigned int reserved_15 : 1; /* 1E.C883.7 RO */ + /* Reserved + */ + /*! \brief 1E.C883.A:8 RO Pair D Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.pairDReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_2 : 3; /* 1E.C883.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C883.B RO Reserved 14 + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.reserved_14 + + + + Reserved + + */ + unsigned int reserved_14 : 1; /* 1E.C883.B RO */ + /* Reserved + */ + /*! \brief 1E.C883.E:C RO Pair D Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.pairDReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_1 : 3; /* 1E.C883.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C883.F RO Reserved 13 + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.reserved_13 + + + + Reserved + + */ + unsigned int reserved_13 : 1; /* 1E.C883.F RO */ + /* Reserved + */ + } bits_3; + uint16_t word_3; + } u3; +} AQ_GlobalCableDiagnosticImpedance_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Status: 1E.C884 */ +/* Global Status: 1E.C884 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Status */ + union + { + struct + { + /*! \brief 1E.C884.7:0 RO Cable Length [7:0] + AQ_GlobalStatus_HHD.u0.bits_0.cableLength + + + + The estimated length of the cable in meters + + + Notes: + The length of the cable shown here is estimated from the cable diagnostic engine and should be accurate to +/-1m. */ + unsigned int cableLength : 8; /* 1E.C884.7:0 RO */ + /* The estimated length of the cable in meters + */ + /*! \brief 1E.C884.F:8 RO Reserved Status 0 [7:0] + AQ_GlobalStatus_HHD.u0.bits_0.reservedStatus_0 + + + + Reserved + + */ + unsigned int reservedStatus_0 : 8; /* 1E.C884.F:8 RO */ + /* Reserved + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStatus_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Reserved Status: 1E.C885 */ +/* Global Reserved Status: 1E.C885 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Reserved Status */ + union + { + struct + { + /*! \brief 1E.C885.3:0 ROSPD Provisioning ID [3:0] + AQ_GlobalReservedStatus_HHD.u0.bits_0.provisioningID + + Provisionable Default = 0x0 + + Provisioning ID + + + Notes: + Customers may receive multiple ROM images that differ only in their provisioning. This field is used to differentiate those images. This field is used in conjunction with the firmware major and minor revision numbers to uniquely identify ROM images. */ + unsigned int provisioningID : 4; /* 1E.C885.3:0 ROSPD Provisionable Default = 0x0 */ + /* Provisioning ID + */ + /*! \brief 1E.C885.7:4 ROSPD Firmware Build ID [3:0] + AQ_GlobalReservedStatus_HHD.u0.bits_0.firmwareBuildID + + Provisionable Default = 0x0 + + Firmware Build ID + + + Notes: + Customers may receive multiple ROM images that differ only in their provisioning. This field is used to differentiate those images. This field is used in conjunction with the firmware major and minor revision numbers to uniquely identify ROM images. */ + unsigned int firmwareBuildID : 4; /* 1E.C885.7:4 ROSPD Provisionable Default = 0x0 */ + /* Firmware Build ID + */ + /*! \brief 1E.C885.9:8 ROSPD XENPAK NVR Status [1:0] + AQ_GlobalReservedStatus_HHD.u0.bits_0.xenpakNvrStatus + + Provisionable Default = 0x0 + + Status of XENPAK NVR: + 0: NVR not enabled + 1: Last NVR operation succeeded + 2: Last NVR operation failed + 3: Reserved + + + Notes: + XENPAK register space is mirrored in NVR (SPI ROM). This register indicates the status of the last NVR operation. */ + unsigned int xenpakNvrStatus : 2; /* 1E.C885.9:8 ROSPD Provisionable Default = 0x0 */ + /* Status of XENPAK NVR: + 0: NVR not enabled + 1: Last NVR operation succeeded + 2: Last NVR operation failed + 3: Reserved + */ + /*! \brief 1E.C885.F:A RO Nearly Seconds MSW[5:0] + AQ_GlobalReservedStatus_HHD.u0.bits_0.nearlySecondsMSW + + + + Bits 16 to 21 of the 22 bit "Nearly Seconds" uptime counter. + + + Notes: + The "Nearly Seconds" counter is incremented every 1024 milliseconds. */ + unsigned int nearlySecondsMSW : 6; /* 1E.C885.F:A RO */ + /* Bits 16 to 21 of the 22 bit "Nearly Seconds" uptime counter. + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Reserved Status */ + union + { + struct + { + /*! \brief 1E.C886.F:0 RO Nearly Seconds LSW [F:0] + AQ_GlobalReservedStatus_HHD.u1.bits_1.nearlySecondsLSW + + + + Bits 0 to 15 of the 22 bit "Nearly Seconds" uptime counter + + + Notes: + The "Nearly Seconds" counter is incremented every 1024 milliseconds. */ + unsigned int nearlySecondsLSW : 16; /* 1E.C886.F:0 RO */ + /* Bits 0 to 15 of the 22 bit "Nearly Seconds" uptime counter + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Reserved Status */ + union + { + struct + { + /*! \brief 1E.C887.D:0 RO Reserved Status 3 [D:0] + AQ_GlobalReservedStatus_HHD.u2.bits_2.reservedStatus_3 + + + + Reserved for future use + + */ + unsigned int reservedStatus_3 : 14; /* 1E.C887.D:0 RO */ + /* Reserved for future use + */ + /*! \brief 1E.C887.E ROS Power Up Stall Status + AQ_GlobalReservedStatus_HHD.u2.bits_2.powerUpStallStatus + + Default = 0x0 + + 1 = FW is stalled at power up + 0 = Firmware is unstalled + + */ + unsigned int powerUpStallStatus : 1; /* 1E.C887.E ROS Default = 0x0 */ + /* 1 = FW is stalled at power up + 0 = Firmware is unstalled + */ + /*! \brief 1E.C887.F ROS DTE Status + AQ_GlobalReservedStatus_HHD.u2.bits_2.dteStatus + + Default = 0x0 + + 1 = Need power + 0 = Don't need power + + */ + unsigned int dteStatus : 1; /* 1E.C887.F ROS Default = 0x0 */ + /* 1 = Need power + 0 = Don't need power + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Reserved Status */ + union + { + struct + { + /*! \brief 1E.C888.1:0 RO Rate [1:0] + AQ_GlobalReservedStatus_HHD.u3.bits_3.rate + + Default = 0x0 + + 0x3 = 10G + 0x2 = 1G + 0x1 = 100M + 0x0 = invalid + + + Notes: + These bits report the selected rate for the loopback and packet generation. */ + unsigned int rate : 2; /* 1E.C888.1:0 RO Default = 0x0 */ + /* 0x3 = 10G + 0x2 = 1G + 0x1 = 100M + 0x0 = invalid + */ + /*! \brief 1E.C888.2 RO Reserved Status 4a + AQ_GlobalReservedStatus_HHD.u3.bits_3.reservedStatus_4a + + Default = 0x0 + + Reserved for future use + + */ + unsigned int reservedStatus_4a : 1; /* 1E.C888.2 RO Default = 0x0 */ + /* Reserved for future use + */ + /*! \brief 1E.C888.3 RO System I/F Packet Generation Status + AQ_GlobalReservedStatus_HHD.u3.bits_3.systemI_fPacketGenerationStatus + + Default = 0x0 + + 1 = CRPAT packet generation out 10G system interface + 0 = No CRPAT packet generation out 10G system interface + + + Notes: + Reports whether the CRPAT packet generator in the PHY outputs on the selected system interface at the selected rate. */ + unsigned int systemI_fPacketGenerationStatus : 1; /* 1E.C888.3 RO Default = 0x0 */ + /* 1 = CRPAT packet generation out 10G system interface + 0 = No CRPAT packet generation out 10G system interface + */ + /*! \brief 1E.C888.4 RO Look-Aside Port Packet Generation Status + AQ_GlobalReservedStatus_HHD.u3.bits_3.look_asidePortPacketGenerationStatus + + Default = 0x0 + + 1 = CRPAT packet generation out 10G look-aside interface (KR0) + 0 = No CRPAT packet generation out 10G look-aside interface (KR0) + + + Notes: + Reports whether the CRPAT packet generator in the PHY outputs on the KR0 interface at the selected rate. */ + unsigned int look_asidePortPacketGenerationStatus : 1; /* 1E.C888.4 RO Default = 0x0 */ + /* 1 = CRPAT packet generation out 10G look-aside interface (KR0) + 0 = No CRPAT packet generation out 10G look-aside interface (KR0) + */ + /*! \brief 1E.C888.5 RO MDI Packet Generation Status + AQ_GlobalReservedStatus_HHD.u3.bits_3.mdiPacketGenerationStatus + + Default = 0x0 + + 1 = CRPAT packet generation out MDI interface + 0 = No CRPAT packet generation out MDI interface + + + Notes: + Reports whether the CRPAT packet generator in the PHY outputs on the MDI interface at the selected rate. */ + unsigned int mdiPacketGenerationStatus : 1; /* 1E.C888.5 RO Default = 0x0 */ + /* 1 = CRPAT packet generation out MDI interface + 0 = No CRPAT packet generation out MDI interface + */ + /*! \brief 1E.C888.A:6 RO Reserved Status 4 [4:0] + AQ_GlobalReservedStatus_HHD.u3.bits_3.reservedStatus_4 + + Default = 0x00 + + Reserved for future use + + */ + unsigned int reservedStatus_4 : 5; /* 1E.C888.A:6 RO Default = 0x00 */ + /* Reserved for future use + */ + /*! \brief 1E.C888.F:B RO Loopback Status [4:0] + AQ_GlobalReservedStatus_HHD.u3.bits_3.loopbackStatus + + Default = 0x00 + + 0x00 = No loopback + 0x01 = System Interface - System Loopback + 0x02 = System Interface - System Loopback with Passthrough + 0x03 = System Interface - Network Loopback + 0x04 = System Interface - Network Loopback with Passthrough + 0x05 = System Interface - Network Loopback with Passthrough and Merge + 0x06 = System Interface - Peer-to-peer loopback + 0x07 - 0x08 = Reserved + 0x09 = Network Interface - System Loopback + 0x0A = Network Interface - System Loopback with Passthrough + 0x0B = Network Interface - Network Loopback + 0x0C = Network Interface - Network Loopback with Passthrough + 0x0D = Network Interface - Peer-to-peer loopback + 0x0E - 0x0F = Reserved + 0x10 = Cross-connect System Loopback + 0x11 = Cross-connect Network Loopback + 0x12 - 0x13 = Reserved + 0x14 = Network Interface - System Loopback via Loopback Plug + 0x15 - 0x1F = Reserved + + + Notes: + These bits, in conjunction with the chip configuration and the rate (Bits 1:0), report the selected loopback. + + */ + unsigned int loopbackStatus : 5; /* 1E.C888.F:B RO Default = 0x00 */ + /* 0x00 = No loopback + 0x01 = System Interface - System Loopback + 0x02 = System Interface - System Loopback with Passthrough + 0x03 = System Interface - Network Loopback + 0x04 = System Interface - Network Loopback with Passthrough + 0x05 = System Interface - Network Loopback with Passthrough and Merge + 0x06 = System Interface - Peer-to-peer loopback + 0x07 - 0x08 = Reserved + 0x09 = Network Interface - System Loopback + 0x0A = Network Interface - System Loopback with Passthrough + 0x0B = Network Interface - Network Loopback + 0x0C = Network Interface - Network Loopback with Passthrough + 0x0D = Network Interface - Peer-to-peer loopback + 0x0E - 0x0F = Reserved + 0x10 = Cross-connect System Loopback + 0x11 = Cross-connect Network Loopback + 0x12 - 0x13 = Reserved + 0x14 = Network Interface - System Loopback via Loopback Plug + 0x15 - 0x1F = Reserved + */ + } bits_3; + uint16_t word_3; + } u3; +} AQ_GlobalReservedStatus_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Alarms: 1E.CC00 */ +/* Global Alarms: 1E.CC00 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Alarms */ + union + { + struct + { + /*! \brief 1E.CC00.0 LH Reserved Alarm D + AQ_GlobalAlarms_HHD.u0.bits_0.reservedAlarmD + + + + Reserved for future use + + */ + unsigned int reservedAlarmD : 1; /* 1E.CC00.0 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC00.1 LH Reserved Alarm C + AQ_GlobalAlarms_HHD.u0.bits_0.reservedAlarmC + + + + Reserved for future use + + */ + unsigned int reservedAlarmC : 1; /* 1E.CC00.1 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC00.2 LH Reserved Alarm B + AQ_GlobalAlarms_HHD.u0.bits_0.reservedAlarmB + + + + Reserved for future use + + */ + unsigned int reservedAlarmB : 1; /* 1E.CC00.2 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC00.3 LH Reserved Alarm A + AQ_GlobalAlarms_HHD.u0.bits_0.reservedAlarmA + + + + Reserved for future use + + */ + unsigned int reservedAlarmA : 1; /* 1E.CC00.3 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC00.4 LH Device Fault + AQ_GlobalAlarms_HHD.u0.bits_0.deviceFault + + + + 1 = Fault + + Notes: + When set, a fault has been detected by the uP and the associated 16 bit error code is visible in See Global Configuration Fault Message: Address 1E.C850 */ + unsigned int deviceFault : 1; /* 1E.CC00.4 LH */ + /* 1 = Fault */ + unsigned int reserved2 : 1; + /*! \brief 1E.CC00.6 LH Reset completed + AQ_GlobalAlarms_HHD.u0.bits_0.resetCompleted + + + + 1 = Chip wide reset completed + + Notes: + This bit is set by the microprocessor when it has completed it's initialization sequence. This bit is mirrored in 1.CC02.0 */ + unsigned int resetCompleted : 1; /* 1E.CC00.6 LH */ + /* 1 = Chip wide reset completed */ + unsigned int reserved1 : 4; + /*! \brief 1E.CC00.B LH Low Temperature Warning + AQ_GlobalAlarms_HHD.u0.bits_0.lowTemperatureWarning + + + + 1 = Low temperature warning threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int lowTemperatureWarning : 1; /* 1E.CC00.B LH */ + /* 1 = Low temperature warning threshold has been exceeded + */ + /*! \brief 1E.CC00.C LH High Temperature Warning + AQ_GlobalAlarms_HHD.u0.bits_0.highTemperatureWarning + + + + 1 = High temperature warning threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int highTemperatureWarning : 1; /* 1E.CC00.C LH */ + /* 1 = High temperature warning threshold has been exceeded + */ + /*! \brief 1E.CC00.D LH Low Temperature Failure + AQ_GlobalAlarms_HHD.u0.bits_0.lowTemperatureFailure + + + + 1 = Low temperature failure threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int lowTemperatureFailure : 1; /* 1E.CC00.D LH */ + /* 1 = Low temperature failure threshold has been exceeded + */ + /*! \brief 1E.CC00.E LH High Temperature Failure + AQ_GlobalAlarms_HHD.u0.bits_0.highTemperatureFailure + + + + 1 = High temperature failure threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int highTemperatureFailure : 1; /* 1E.CC00.E LH */ + /* 1 = High temperature failure threshold has been exceeded + */ + unsigned int reserved0 : 1; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Alarms */ + union + { + struct + { + unsigned int reserved2 : 1; + unsigned int reserved1 : 6; + /*! \brief 1E.CC01.7 LH MDIO Command Handling Overflow + AQ_GlobalAlarms_HHD.u1.bits_1.mdioCommandHandlingOverflow + + + + 1 = PHY was issued more MDIO requests than it could service in it's request buffer + + + Notes: + Assertion of this bit means that more MDIO commands were issued than FW could handle. */ + unsigned int mdioCommandHandlingOverflow : 1; /* 1E.CC01.7 LH */ + /* 1 = PHY was issued more MDIO requests than it could service in it's request buffer + */ + /*! \brief 1E.CC01.A:8 LH Reserved Alarms [2:0] + AQ_GlobalAlarms_HHD.u1.bits_1.reservedAlarms + + + + Reserved + + + */ + unsigned int reservedAlarms : 3; /* 1E.CC01.A:8 LH */ + /* Reserved + + */ + /*! \brief 1E.CC01.B LH DTE Status Change + AQ_GlobalAlarms_HHD.u1.bits_1.dteStatusChange + + + + 1 = DTE status change + + + Notes: + Change in 1E.C887[F]. */ + unsigned int dteStatusChange : 1; /* 1E.CC01.B LH */ + /* 1 = DTE status change + */ + /*! \brief 1E.CC01.C LH IP Phone Detect + AQ_GlobalAlarms_HHD.u1.bits_1.ipPhoneDetect + + + + 1 = IP Phone Detect + + + Notes: + Assertion of this bit means that the presence of an IP Phone has been detected. */ + unsigned int ipPhoneDetect : 1; /* 1E.CC01.C LH */ + /* 1 = IP Phone Detect + */ + /*! \brief 1E.CC01.D RO XENPAK Alarm + AQ_GlobalAlarms_HHD.u1.bits_1.xenpakAlarm + + + + 1 = XENPAK Alarm + + */ + unsigned int xenpakAlarm : 1; /* 1E.CC01.D RO */ + /* 1 = XENPAK Alarm + */ + /*! \brief 1E.CC01.E LH Smart Power-Down Entered + AQ_GlobalAlarms_HHD.u1.bits_1.smartPower_downEntered + + + + 1 = Smart Power-Down State Entered + + + Notes: + When this bit is set, it indicates that the Smart Power-Down state was entered */ + unsigned int smartPower_downEntered : 1; /* 1E.CC01.E LH */ + /* 1 = Smart Power-Down State Entered + */ + unsigned int reserved0 : 1; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Alarms */ + union + { + struct + { + /*! \brief 1E.CC02.0 LH Watchdog Timer Alarm + AQ_GlobalAlarms_HHD.u2.bits_2.watchdogTimerAlarm + + + + 1 = Watchdog timer alarm + + */ + unsigned int watchdogTimerAlarm : 1; /* 1E.CC02.0 LH */ + /* 1 = Watchdog timer alarm + */ + /*! \brief 1E.CC02.1 LH MDIO Timeout Error + AQ_GlobalAlarms_HHD.u2.bits_2.mdioTimeoutError + + + + 1 = MDIO timeout detected + + */ + unsigned int mdioTimeoutError : 1; /* 1E.CC02.1 LH */ + /* 1 = MDIO timeout detected + */ + /*! \brief 1E.CC02.2 LH MDIO MMD Error + AQ_GlobalAlarms_HHD.u2.bits_2.mdioMMD_Error + + + + 1 = Invalid MMD address detected + + */ + unsigned int mdioMMD_Error : 1; /* 1E.CC02.2 LH */ + /* 1 = Invalid MMD address detected + */ + unsigned int reserved2 : 2; + /*! \brief 1E.CC02.5 LRF Tx Enable State Change + AQ_GlobalAlarms_HHD.u2.bits_2.txEnableStateChange + + + + 1 = TX_EN pin has changed state + + */ + unsigned int txEnableStateChange : 1; /* 1E.CC02.5 LRF */ + /* 1 = TX_EN pin has changed state + */ + unsigned int reserved1 : 2; + /*! \brief 1E.CC02.9:8 LH uP IRAM Parity Error [1:0] + AQ_GlobalAlarms_HHD.u2.bits_2.upIramParityError + + + + 1 = Parity error detected in the uP IRAM + + + Notes: + Bit 0 indicates a parity error was detected in the uP IRAM but was corrected. + Bit 1 indicates a multiple parity errors were detected in the uP IRAM and could not be corrected. + The uP IRAM is protected with ECC. */ + unsigned int upIramParityError : 2; /* 1E.CC02.9:8 LH */ + /* 1 = Parity error detected in the uP IRAM + */ + /*! \brief 1E.CC02.A LH uP DRAM Parity Error + AQ_GlobalAlarms_HHD.u2.bits_2.upDramParityError + + + + 1 = Parity error detected in the uP DRAM + + */ + unsigned int upDramParityError : 1; /* 1E.CC02.A LH */ + /* 1 = Parity error detected in the uP DRAM + */ + unsigned int reserved0 : 3; + /*! \brief 1E.CC02.E LH Mailbox Operation: Complete + AQ_GlobalAlarms_HHD.u2.bits_2.mailboxOperation_Complete + + + + 1 = Mailbox operation is complete + + + Notes: + Mailbox interface is ready interrupt for registers See Global Vendor Specific Control - Address 1E.C000 - See Global Vendor Specific Provisioning 5 - Address 1E.C404 */ + unsigned int mailboxOperation_Complete : 1; /* 1E.CC02.E LH */ + /* 1 = Mailbox operation is complete + */ + /*! \brief 1E.CC02.F LH NVR Operation Complete + AQ_GlobalAlarms_HHD.u2.bits_2.nvrOperationComplete + + + + 1 = NVR operation is complete + + + Notes: + NVR interface is ready interrupt for registers See Global NVR Interface 1: Address 1E.100 - See Global NVR Provisioning Data MSW - Address 1E.17 . */ + unsigned int nvrOperationComplete : 1; /* 1E.CC02.F LH */ + /* 1 = NVR operation is complete + */ + } bits_2; + uint16_t word_2; + } u2; +} AQ_GlobalAlarms_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Interrupt Mask: 1E.D400 */ +/* Global Interrupt Mask: 1E.D400 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Interrupt Mask */ + union + { + struct + { + /*! \brief 1E.D400.0 R/WPD Reserved Alarm D Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.reservedAlarmDMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmDMask : 1; /* 1E.D400.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D400.1 R/WPD Reserved Alarm C Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.reservedAlarmCMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmCMask : 1; /* 1E.D400.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D400.2 R/WPD Reserved Alarm B Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.reservedAlarmBMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmBMask : 1; /* 1E.D400.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D400.3 R/WPD Reserved Alarm A Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.reservedAlarmAMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmAMask : 1; /* 1E.D400.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D400.4 R/WPD Device Fault Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.deviceFaultMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int deviceFaultMask : 1; /* 1E.D400.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved2 : 1; + /*! \brief 1E.D400.6 R/WPD Reset completed Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.resetCompletedMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int resetCompletedMask : 1; /* 1E.D400.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved1 : 4; + /*! \brief 1E.D400.B R/WPD Low Temperature Warning Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.lowTemperatureWarningMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int lowTemperatureWarningMask : 1; /* 1E.D400.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D400.C R/WPD High Temperature Warning Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.highTemperatureWarningMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int highTemperatureWarningMask : 1; /* 1E.D400.C R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D400.D R/WPD Low Temperature Failure Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.lowTemperatureFailureMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int lowTemperatureFailureMask : 1; /* 1E.D400.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D400.E R/WPD High Temperature Failure Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.highTemperatureFailureMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int highTemperatureFailureMask : 1; /* 1E.D400.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved0 : 1; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Interrupt Mask */ + union + { + struct + { + /*! \brief 1E.D401.0 R/WPD Diagnostic Alarm Mask + AQ_GlobalInterruptMask_HHD.u1.bits_1.diagnosticAlarmMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int diagnosticAlarmMask : 1; /* 1E.D401.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int reserved1 : 6; + /*! \brief 1E.D401.7 R/WPD MDIO Command Handling Overflow Mask + AQ_GlobalInterruptMask_HHD.u1.bits_1.mdioCommandHandlingOverflowMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int mdioCommandHandlingOverflowMask : 1; /* 1E.D401.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D401.A:8 R/WPD Reserved Alarms Mask [2:0] + AQ_GlobalInterruptMask_HHD.u1.bits_1.reservedAlarmsMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmsMask : 3; /* 1E.D401.A:8 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D401.B R/WPD DTE Status Change Mask + AQ_GlobalInterruptMask_HHD.u1.bits_1.dteStatusChangeMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int dteStatusChangeMask : 1; /* 1E.D401.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D401.C R/WPD IP Phone Detect Mask + AQ_GlobalInterruptMask_HHD.u1.bits_1.ipPhoneDetectMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int ipPhoneDetectMask : 1; /* 1E.D401.C R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D401.D R/WPD XENPAK Alarm Mask + AQ_GlobalInterruptMask_HHD.u1.bits_1.xenpakAlarmMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int xenpakAlarmMask : 1; /* 1E.D401.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D401.E R/WPD Smart Power-Down Entered Mask + AQ_GlobalInterruptMask_HHD.u1.bits_1.smartPower_downEnteredMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int smartPower_downEnteredMask : 1; /* 1E.D401.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int reserved0 : 1; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Interrupt Mask */ + union + { + struct + { + /*! \brief 1E.D402.0 R/WPD Watchdog Timer Alarm Mask + AQ_GlobalInterruptMask_HHD.u2.bits_2.watchdogTimerAlarmMask + + Provisionable Default = 0x1 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int watchdogTimerAlarmMask : 1; /* 1E.D402.0 R/WPD Provisionable Default = 0x1 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D402.1 R/WPD MDIO Timeout Error Mask + AQ_GlobalInterruptMask_HHD.u2.bits_2.mdioTimeoutErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int mdioTimeoutErrorMask : 1; /* 1E.D402.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D402.2 R/WPD MDIO MMD Error Mask + AQ_GlobalInterruptMask_HHD.u2.bits_2.mdioMMD_ErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int mdioMMD_ErrorMask : 1; /* 1E.D402.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved2 : 2; + /*! \brief 1E.D402.5 R/WPD Tx Enable State Change Mask + AQ_GlobalInterruptMask_HHD.u2.bits_2.txEnableStateChangeMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int txEnableStateChangeMask : 1; /* 1E.D402.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved1 : 2; + /*! \brief 1E.D402.9:8 R/WPD uP IRAM Parity Error Mask [1:0] + AQ_GlobalInterruptMask_HHD.u2.bits_2.upIramParityErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int upIramParityErrorMask : 2; /* 1E.D402.9:8 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D402.A R/WPD uP DRAM Parity Error Mask + AQ_GlobalInterruptMask_HHD.u2.bits_2.upDramParityErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int upDramParityErrorMask : 1; /* 1E.D402.A R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int reserved0 : 3; + /*! \brief 1E.D402.E R/WPD Mailbox Operation Complete Mask + AQ_GlobalInterruptMask_HHD.u2.bits_2.mailboxOperationCompleteMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + Notes: + Mailbox interface is ready interrupt for registers See Global Vendor Specific Control - Address 1E.C000 - See Global Vendor Specific Provisioning 5 - Address 1E.C404 */ + unsigned int mailboxOperationCompleteMask : 1; /* 1E.D402.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D402.F R/WPD NVR Operation Complete Mask + AQ_GlobalInterruptMask_HHD.u2.bits_2.nvrOperationCompleteMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + Notes: + NVR interface is ready interrupt for registers See Global NVR Interface 1: Address 1E.100 - See Global NVR Provisioning Data MSW - Address 1E.17 */ + unsigned int nvrOperationCompleteMask : 1; /* 1E.D402.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + } bits_2; + uint16_t word_2; + } u2; +} AQ_GlobalInterruptMask_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Chip-Wide Standard Interrupt Flags: 1E.FC00 */ +/* Global Chip-Wide Standard Interrupt Flags: 1E.FC00 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Chip-Wide Standard Interrupt Flags */ + union + { + struct + { + /*! \brief 1E.FC00.0 RO All Vendor Alarms Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.allVendorAlarmsInterrupt + + + + 1 = Interrupt in all vendor alarms + + + Notes: + An interrupt was generated from status register ( See Global Chip-Wide LASI Vendor Interrupt Flags: Address 1E.FC01 ) and the corresponding mask register. ( See Global Interrupt LASI Mask: Address 1E.FF01 ) */ + unsigned int allVendorAlarmsInterrupt : 1; /* 1E.FC00.0 RO */ + /* 1 = Interrupt in all vendor alarms + */ + unsigned int reserved0 : 5; + /*! \brief 1E.FC00.6 RO GbE Standard Alarms Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.gbeStandardAlarmsInterrupt + + + + 1 = Interrupt in GbE standard alarms + + + Notes: + An interrupt was generated from the TGE core. */ + unsigned int gbeStandardAlarmsInterrupt : 1; /* 1E.FC00.6 RO */ + /* 1 = Interrupt in GbE standard alarms + */ + /*! \brief 1E.FC00.7 RO Autonegotiation Standard Alarms 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.autonegotiationStandardAlarms_2Interrupt + + + + 1 = Interrupt in Autonegotiation standard alarms 2 + + + Notes: + An interrupt was generated from status register ( See Autonegotiation 10GBASE-T Status Register - Address 7.21 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int autonegotiationStandardAlarms_2Interrupt : 1; /* 1E.FC00.7 RO */ + /* 1 = Interrupt in Autonegotiation standard alarms 2 + */ + /*! \brief 1E.FC00.8 RO Autonegotiation Standard Alarms 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.autonegotiationStandardAlarms_1Interrupt + + + + 1 = Interrupt in Autonegotiation standard alarms 1 + + + Notes: + An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See Autonegotiation Standard LASI Interrupt Mask 1: Address 7.D000 ) */ + unsigned int autonegotiationStandardAlarms_1Interrupt : 1; /* 1E.FC00.8 RO */ + /* 1 = Interrupt in Autonegotiation standard alarms 1 + */ + /*! \brief 1E.FC00.9 RO PHY XS Standard Alarms 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.phyXS_StandardAlarms_2Interrupt + + + + 1 = Interrupt in PHY XS standard alarms 2 + + + Notes: + An interrupt was generated from the status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int phyXS_StandardAlarms_2Interrupt : 1; /* 1E.FC00.9 RO */ + /* 1 = Interrupt in PHY XS standard alarms 2 + */ + /*! \brief 1E.FC00.A RO PHY XS Standard Alarms 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.phyXS_StandardAlarms_1Interrupt + + + + 1 = Interrupt in PHY XS standard alarms 1 + + + Notes: + An interrupt was generated from the status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ + unsigned int phyXS_StandardAlarms_1Interrupt : 1; /* 1E.FC00.A RO */ + /* 1 = Interrupt in PHY XS standard alarms 1 + */ + /*! \brief 1E.FC00.B RO PCS Standard Alarm 3 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.pcsStandardAlarm_3Interrupt + + + + 1 = Interrupt in PCS standard alarms 3 + + + Notes: + An interrupt was generated from status register ( See PCS 10GBASE-T Status 2 - Address 3.21 ) and the corresponding mask register. ( See PCS Standard Interrupt Mask 1 - Address 3.E021 ) */ + unsigned int pcsStandardAlarm_3Interrupt : 1; /* 1E.FC00.B RO */ + /* 1 = Interrupt in PCS standard alarms 3 + */ + /*! \brief 1E.FC00.C RO PCS Standard Alarm 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.pcsStandardAlarm_2Interrupt + + + + 1 = Interrupt in PCS standard alarms 2 + + + Notes: + An interrupt was generated from status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int pcsStandardAlarm_2Interrupt : 1; /* 1E.FC00.C RO */ + /* 1 = Interrupt in PCS standard alarms 2 + */ + /*! \brief 1E.FC00.D RO PCS Standard Alarm 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.pcsStandardAlarm_1Interrupt + + + + 1 = Interrupt in PCS standard alarms 1 + + + Notes: + An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ + unsigned int pcsStandardAlarm_1Interrupt : 1; /* 1E.FC00.D RO */ + /* 1 = Interrupt in PCS standard alarms 1 + */ + /*! \brief 1E.FC00.E RO PMA Standard Alarm 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.pmaStandardAlarm_2Interrupt + + + + 1 = Interrupt in PMA standard alarms 2 + + + Notes: + An interrupt was generated from either bit 1.8.B or 1.8.A. + An interrupt was generated from status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int pmaStandardAlarm_2Interrupt : 1; /* 1E.FC00.E RO */ + /* 1 = Interrupt in PMA standard alarms 2 + */ + /*! \brief 1E.FC00.F RO PMA Standard Alarm 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.pmaStandardAlarm_1Interrupt + + + + 1 = Interrupt in PMA standard alarms 1 + + + Notes: + An interrupt was generated from bit 1.1.2. + An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ + unsigned int pmaStandardAlarm_1Interrupt : 1; /* 1E.FC00.F RO */ + /* 1 = Interrupt in PMA standard alarms 1 + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalChip_wideStandardInterruptFlags_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Chip-Wide Vendor Interrupt Flags: 1E.FC01 */ +/* Global Chip-Wide Vendor Interrupt Flags: 1E.FC01 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Chip-Wide Vendor Interrupt Flags */ + union + { + struct + { + /*! \brief 1E.FC01.0 RO Global Alarms 3 Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.globalAlarms_3Interrupt + + + + 1 = Interrupt in Global alarms 3 + + + Notes: + An interrupt was generated from status register ( See Global Vendor Alarms 2: Address 1E.CC01 ) and the corresponding mask register. ( See Global LASI Interrupt Mask 2: Address 1E.D401 ) */ + unsigned int globalAlarms_3Interrupt : 1; /* 1E.FC01.0 RO */ + /* 1 = Interrupt in Global alarms 3 + */ + /*! \brief 1E.FC01.1 RO Global Alarms 2 Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.globalAlarms_2Interrupt + + + + 1 = Interrupt in Global alarms 2 + + + Notes: + An interrupt was generated from status register ( See Global Alarms 2: Address 1E.CC01 ) and the corresponding mask register. ( See Global LASI Interrupt Mask 2: Address 1E.D401 ) */ + unsigned int globalAlarms_2Interrupt : 1; /* 1E.FC01.1 RO */ + /* 1 = Interrupt in Global alarms 2 + */ + /*! \brief 1E.FC01.2 RO Global Alarms 1 Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.globalAlarms_1Interrupt + + + + 1 = Interrupt in Global alarms 1 + + + Notes: + An interrupt was generated from status register ( See Global Vendor Alarms 1 - Address 1E.CC00 ) and the corresponding mask register. ( See Global Vendor Interrupt Mask - Address 1E.D400 ) */ + unsigned int globalAlarms_1Interrupt : 1; /* 1E.FC01.2 RO */ + /* 1 = Interrupt in Global alarms 1 + */ + unsigned int reserved0 : 8; + /*! \brief 1E.FC01.B RO GbE Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.gbeVendorAlarmInterrupt + + + + 1 = Interrupt in GbE vendor specific alarm + + + Notes: + A GbE alarm was generated. ( See GbE PHY Vendor Global LASI Interrupt Flags 1: Address 1D.FC00 ) */ + unsigned int gbeVendorAlarmInterrupt : 1; /* 1E.FC01.B RO */ + /* 1 = Interrupt in GbE vendor specific alarm + */ + /*! \brief 1E.FC01.C RO Autonegotiation Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.autonegotiationVendorAlarmInterrupt + + + + 1 = Interrupt in Autonegotiation vendor specific alarm + + + Notes: + An Autonegotiation alarm was generated. ( See Autonegotiation Vendor Global LASI Interrupt Flags 1: Address 7.FC00 ) */ + unsigned int autonegotiationVendorAlarmInterrupt : 1; /* 1E.FC01.C RO */ + /* 1 = Interrupt in Autonegotiation vendor specific alarm + */ + /*! \brief 1E.FC01.D RO PHY XS Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.phyXS_VendorAlarmInterrupt + + + + 1 = Interrupt in PHY XS vendor specific alarm + + + Notes: + A PHY XS alarm was generated. ( See PHY XS Vendor Global LASI Interrupt Flags 1: Address 4.FC00 ) */ + unsigned int phyXS_VendorAlarmInterrupt : 1; /* 1E.FC01.D RO */ + /* 1 = Interrupt in PHY XS vendor specific alarm + */ + /*! \brief 1E.FC01.E RO PCS Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.pcsVendorAlarmInterrupt + + + + 1 = Interrupt in PCS vendor specific alarm + + + Notes: + A PCS alarm was generated. ( See PHY XS Vendor Global Interrupt Flags 1- Address 4.F800 ) */ + unsigned int pcsVendorAlarmInterrupt : 1; /* 1E.FC01.E RO */ + /* 1 = Interrupt in PCS vendor specific alarm + */ + /*! \brief 1E.FC01.F RO PMA Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.pmaVendorAlarmInterrupt + + + + 1 = Interrupt in PMA vendor specific alarm + + + Notes: + A PMA alarm was generated. ( See PHY XS Vendor Global Interrupt Flags 1- Address 4.F800 ) */ + unsigned int pmaVendorAlarmInterrupt : 1; /* 1E.FC01.F RO */ + /* 1 = Interrupt in PMA vendor specific alarm + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalChip_wideVendorInterruptFlags_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Interrupt Chip-Wide Standard Mask: 1E.FF00 */ +/* Global Interrupt Chip-Wide Standard Mask: 1E.FF00 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Interrupt Chip-Wide Standard Mask */ + union + { + struct + { + /*! \brief 1E.FF00.0 R/WPD All Vendor Alarms Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.allVendorAlarmsInterruptMask + + Provisionable Default = 0x1 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int allVendorAlarmsInterruptMask : 1; /* 1E.FF00.0 R/WPD Provisionable Default = 0x1 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved0 : 5; + /*! \brief 1E.FF00.6 R/WPD Gbe Standard Alarms Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.gbeStandardAlarmsInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int gbeStandardAlarmsInterruptMask : 1; /* 1E.FF00.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.7 R/WPD Autonegotiation Standard Alarms 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.autonegotiationStandardAlarms_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int autonegotiationStandardAlarms_2InterruptMask : 1; /* 1E.FF00.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.8 R/WPD Autonegotiation Standard Alarms 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.autonegotiationStandardAlarms_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int autonegotiationStandardAlarms_1InterruptMask : 1; /* 1E.FF00.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.9 R/WPD PHY XS Standard Alarms 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.phyXS_StandardAlarms_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int phyXS_StandardAlarms_2InterruptMask : 1; /* 1E.FF00.9 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.A R/WPD PHY XS Standard Alarms 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.phyXS_StandardAlarms_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int phyXS_StandardAlarms_1InterruptMask : 1; /* 1E.FF00.A R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.B R/WPD PCS Standard Alarm 3 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.pcsStandardAlarm_3InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsStandardAlarm_3InterruptMask : 1; /* 1E.FF00.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.C R/WPD PCS Standard Alarm 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.pcsStandardAlarm_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsStandardAlarm_2InterruptMask : 1; /* 1E.FF00.C R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.D R/WPD PCS Standard Alarm 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.pcsStandardAlarm_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsStandardAlarm_1InterruptMask : 1; /* 1E.FF00.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.E R/WPD PMA Standard Alarm 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.pmaStandardAlarm_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pmaStandardAlarm_2InterruptMask : 1; /* 1E.FF00.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.F R/WPD PMA Standard Alarm 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.pmaStandardAlarm_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pmaStandardAlarm_1InterruptMask : 1; /* 1E.FF00.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalInterruptChip_wideStandardMask_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Interrupt Chip-Wide Vendor Mask: 1E.FF01 */ +/* Global Interrupt Chip-Wide Vendor Mask: 1E.FF01 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Interrupt Chip-Wide Vendor Mask */ + union + { + struct + { + /*! \brief 1E.FF01.0 R/WPD Global Alarms 3 Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.globalAlarms_3InterruptMask + + Provisionable Default = 0x1 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int globalAlarms_3InterruptMask : 1; /* 1E.FF01.0 R/WPD Provisionable Default = 0x1 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.1 R/WPD Global Alarms 2 Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.globalAlarms_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int globalAlarms_2InterruptMask : 1; /* 1E.FF01.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.2 R/WPD Global Alarms 1 Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.globalAlarms_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int globalAlarms_1InterruptMask : 1; /* 1E.FF01.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved0 : 8; + /*! \brief 1E.FF01.B R/WPD GbE Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.gbeVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int gbeVendorAlarmInterruptMask : 1; /* 1E.FF01.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.C R/WPD Autonegotiation Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.autonegotiationVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int autonegotiationVendorAlarmInterruptMask : 1; /* 1E.FF01.C R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.D R/WPD PHY XS Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.phyXS_VendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int phyXS_VendorAlarmInterruptMask : 1; /* 1E.FF01.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.E R/WPD PCS Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.pcsVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsVendorAlarmInterruptMask : 1; /* 1E.FF01.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.F R/WPD PMA Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.pmaVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pmaVendorAlarmInterruptMask : 1; /* 1E.FF01.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalInterruptChip_wideVendorMask_HHD; + +#endif +/*@}*/ +/*@}*/ diff --git a/qca/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers_Defines.h b/qca/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers_Defines.h new file mode 100644 index 000000000..d9a4429d5 --- /dev/null +++ b/qca/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers_Defines.h @@ -0,0 +1,4413 @@ +/*! \file +* This file contains the compiler assist macros and doxygen comments +* for the Global Registers block. +*/ + +/*! \defgroup Global_registers_Defines Global Registers Defines +* This module contains the compiler assist macros and doxygen comments +* for the Global Registers block. +*/ +/*********************************************************************** +* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +* +* $File: //depot/icm/proj/Dena/rev1.0/c/Systems/tools/windows/regMapParser/src/gencheaders.py $ +* +* $Revision: #10 $ +* +* $DateTime: 2014/04/08 16:55:58 $ +* +* $Author: joshd $ +* +* $Label: $ +* +* Description: +* +* This file contains the compiler assist macros for the registers contained in the Global Registers block. +* +* +***********************************************************************/ + + +/*@{*/ +#ifndef AQ_HHD_GLOBAL_REGS_DEFINES_HEADER +#define AQ_HHD_GLOBAL_REGS_DEFINES_HEADER + + +/*-----------------------------------------------------------------------------*/ +/*Access macro definitions */ +/*-----------------------------------------------------------------------------*/ +/*! \brief Base register address of structure AQ_GlobalStandardControl_1_HHD */ +#define AQ_GlobalStandardControl_1_HHD_baseRegisterAddress 0x0000 +/*! \brief MMD address of structure AQ_GlobalStandardControl_1_HHD */ +#define AQ_GlobalStandardControl_1_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure softReset in AQ_GlobalStandardControl_1_HHD */ +#define AQ_GlobalStandardControl_1_HHD_softReset 0 +/*! \brief Preprocessor variable to relate field to bit position in structure softReset in AQ_GlobalStandardControl_1_HHD */ +#define bits_AQ_GlobalStandardControl_1_HHD_softReset u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure softReset in AQ_GlobalStandardControl_1_HHD */ +#define word_AQ_GlobalStandardControl_1_HHD_softReset u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure lowPower in AQ_GlobalStandardControl_1_HHD */ +#define AQ_GlobalStandardControl_1_HHD_lowPower 0 +/*! \brief Preprocessor variable to relate field to bit position in structure lowPower in AQ_GlobalStandardControl_1_HHD */ +#define bits_AQ_GlobalStandardControl_1_HHD_lowPower u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure lowPower in AQ_GlobalStandardControl_1_HHD */ +#define word_AQ_GlobalStandardControl_1_HHD_lowPower u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalStandardDeviceIdentifier_HHD */ +#define AQ_GlobalStandardDeviceIdentifier_HHD_baseRegisterAddress 0x0002 +/*! \brief MMD address of structure AQ_GlobalStandardDeviceIdentifier_HHD */ +#define AQ_GlobalStandardDeviceIdentifier_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure deviceIdMSW in AQ_GlobalStandardDeviceIdentifier_HHD */ +#define AQ_GlobalStandardDeviceIdentifier_HHD_deviceIdMSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure deviceIdMSW in AQ_GlobalStandardDeviceIdentifier_HHD */ +#define bits_AQ_GlobalStandardDeviceIdentifier_HHD_deviceIdMSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure deviceIdMSW in AQ_GlobalStandardDeviceIdentifier_HHD */ +#define word_AQ_GlobalStandardDeviceIdentifier_HHD_deviceIdMSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure deviceIdLSW in AQ_GlobalStandardDeviceIdentifier_HHD */ +#define AQ_GlobalStandardDeviceIdentifier_HHD_deviceIdLSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure deviceIdLSW in AQ_GlobalStandardDeviceIdentifier_HHD */ +#define bits_AQ_GlobalStandardDeviceIdentifier_HHD_deviceIdLSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure deviceIdLSW in AQ_GlobalStandardDeviceIdentifier_HHD */ +#define word_AQ_GlobalStandardDeviceIdentifier_HHD_deviceIdLSW u1.word_1 + +/*! \brief Base register address of structure AQ_GlobalStandardDevicesInPackage_HHD */ +#define AQ_GlobalStandardDevicesInPackage_HHD_baseRegisterAddress 0x0005 +/*! \brief MMD address of structure AQ_GlobalStandardDevicesInPackage_HHD */ +#define AQ_GlobalStandardDevicesInPackage_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define AQ_GlobalStandardDevicesInPackage_HHD_autonegotiationPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define bits_AQ_GlobalStandardDevicesInPackage_HHD_autonegotiationPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define word_AQ_GlobalStandardDevicesInPackage_HHD_autonegotiationPresent u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure tcPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define AQ_GlobalStandardDevicesInPackage_HHD_tcPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure tcPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define bits_AQ_GlobalStandardDevicesInPackage_HHD_tcPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure tcPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define word_AQ_GlobalStandardDevicesInPackage_HHD_tcPresent u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure dteXsPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define AQ_GlobalStandardDevicesInPackage_HHD_dteXsPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure dteXsPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define bits_AQ_GlobalStandardDevicesInPackage_HHD_dteXsPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure dteXsPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define word_AQ_GlobalStandardDevicesInPackage_HHD_dteXsPresent u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure phyXS_Present in AQ_GlobalStandardDevicesInPackage_HHD */ +#define AQ_GlobalStandardDevicesInPackage_HHD_phyXS_Present 0 +/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_Present in AQ_GlobalStandardDevicesInPackage_HHD */ +#define bits_AQ_GlobalStandardDevicesInPackage_HHD_phyXS_Present u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure phyXS_Present in AQ_GlobalStandardDevicesInPackage_HHD */ +#define word_AQ_GlobalStandardDevicesInPackage_HHD_phyXS_Present u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define AQ_GlobalStandardDevicesInPackage_HHD_pcsPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define bits_AQ_GlobalStandardDevicesInPackage_HHD_pcsPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define word_AQ_GlobalStandardDevicesInPackage_HHD_pcsPresent u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure wisPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define AQ_GlobalStandardDevicesInPackage_HHD_wisPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure wisPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define bits_AQ_GlobalStandardDevicesInPackage_HHD_wisPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure wisPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define word_AQ_GlobalStandardDevicesInPackage_HHD_wisPresent u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pmaPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define AQ_GlobalStandardDevicesInPackage_HHD_pmaPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pmaPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define bits_AQ_GlobalStandardDevicesInPackage_HHD_pmaPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pmaPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define word_AQ_GlobalStandardDevicesInPackage_HHD_pmaPresent u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure clause_22RegistersPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define AQ_GlobalStandardDevicesInPackage_HHD_clause_22RegistersPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure clause_22RegistersPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define bits_AQ_GlobalStandardDevicesInPackage_HHD_clause_22RegistersPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure clause_22RegistersPresent in AQ_GlobalStandardDevicesInPackage_HHD */ +#define word_AQ_GlobalStandardDevicesInPackage_HHD_clause_22RegistersPresent u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalStandardVendorDevicesInPackage_HHD */ +#define AQ_GlobalStandardVendorDevicesInPackage_HHD_baseRegisterAddress 0x0006 +/*! \brief MMD address of structure AQ_GlobalStandardVendorDevicesInPackage_HHD */ +#define AQ_GlobalStandardVendorDevicesInPackage_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure vendorSpecificDevice_2Present in AQ_GlobalStandardVendorDevicesInPackage_HHD */ +#define AQ_GlobalStandardVendorDevicesInPackage_HHD_vendorSpecificDevice_2Present 0 +/*! \brief Preprocessor variable to relate field to bit position in structure vendorSpecificDevice_2Present in AQ_GlobalStandardVendorDevicesInPackage_HHD */ +#define bits_AQ_GlobalStandardVendorDevicesInPackage_HHD_vendorSpecificDevice_2Present u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure vendorSpecificDevice_2Present in AQ_GlobalStandardVendorDevicesInPackage_HHD */ +#define word_AQ_GlobalStandardVendorDevicesInPackage_HHD_vendorSpecificDevice_2Present u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure vendorSpecificDevice_1Present in AQ_GlobalStandardVendorDevicesInPackage_HHD */ +#define AQ_GlobalStandardVendorDevicesInPackage_HHD_vendorSpecificDevice_1Present 0 +/*! \brief Preprocessor variable to relate field to bit position in structure vendorSpecificDevice_1Present in AQ_GlobalStandardVendorDevicesInPackage_HHD */ +#define bits_AQ_GlobalStandardVendorDevicesInPackage_HHD_vendorSpecificDevice_1Present u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure vendorSpecificDevice_1Present in AQ_GlobalStandardVendorDevicesInPackage_HHD */ +#define word_AQ_GlobalStandardVendorDevicesInPackage_HHD_vendorSpecificDevice_1Present u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure clause_22ExtensionPresent in AQ_GlobalStandardVendorDevicesInPackage_HHD */ +#define AQ_GlobalStandardVendorDevicesInPackage_HHD_clause_22ExtensionPresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure clause_22ExtensionPresent in AQ_GlobalStandardVendorDevicesInPackage_HHD */ +#define bits_AQ_GlobalStandardVendorDevicesInPackage_HHD_clause_22ExtensionPresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure clause_22ExtensionPresent in AQ_GlobalStandardVendorDevicesInPackage_HHD */ +#define word_AQ_GlobalStandardVendorDevicesInPackage_HHD_clause_22ExtensionPresent u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalStandardStatus_2_HHD */ +#define AQ_GlobalStandardStatus_2_HHD_baseRegisterAddress 0x0008 +/*! \brief MMD address of structure AQ_GlobalStandardStatus_2_HHD */ +#define AQ_GlobalStandardStatus_2_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure devicePresent in AQ_GlobalStandardStatus_2_HHD */ +#define AQ_GlobalStandardStatus_2_HHD_devicePresent 0 +/*! \brief Preprocessor variable to relate field to bit position in structure devicePresent in AQ_GlobalStandardStatus_2_HHD */ +#define bits_AQ_GlobalStandardStatus_2_HHD_devicePresent u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure devicePresent in AQ_GlobalStandardStatus_2_HHD */ +#define word_AQ_GlobalStandardStatus_2_HHD_devicePresent u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalStandardPackageIdentifier_HHD */ +#define AQ_GlobalStandardPackageIdentifier_HHD_baseRegisterAddress 0x000E +/*! \brief MMD address of structure AQ_GlobalStandardPackageIdentifier_HHD */ +#define AQ_GlobalStandardPackageIdentifier_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure packageIdMSW in AQ_GlobalStandardPackageIdentifier_HHD */ +#define AQ_GlobalStandardPackageIdentifier_HHD_packageIdMSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure packageIdMSW in AQ_GlobalStandardPackageIdentifier_HHD */ +#define bits_AQ_GlobalStandardPackageIdentifier_HHD_packageIdMSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure packageIdMSW in AQ_GlobalStandardPackageIdentifier_HHD */ +#define word_AQ_GlobalStandardPackageIdentifier_HHD_packageIdMSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure packageIdLSW in AQ_GlobalStandardPackageIdentifier_HHD */ +#define AQ_GlobalStandardPackageIdentifier_HHD_packageIdLSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure packageIdLSW in AQ_GlobalStandardPackageIdentifier_HHD */ +#define bits_AQ_GlobalStandardPackageIdentifier_HHD_packageIdLSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure packageIdLSW in AQ_GlobalStandardPackageIdentifier_HHD */ +#define word_AQ_GlobalStandardPackageIdentifier_HHD_packageIdLSW u1.word_1 + +/*! \brief Base register address of structure AQ_GlobalFirmwareID_HHD */ +#define AQ_GlobalFirmwareID_HHD_baseRegisterAddress 0x0020 +/*! \brief MMD address of structure AQ_GlobalFirmwareID_HHD */ +#define AQ_GlobalFirmwareID_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure firmwareMajorRevisionNumber in AQ_GlobalFirmwareID_HHD */ +#define AQ_GlobalFirmwareID_HHD_firmwareMajorRevisionNumber 0 +/*! \brief Preprocessor variable to relate field to bit position in structure firmwareMajorRevisionNumber in AQ_GlobalFirmwareID_HHD */ +#define bits_AQ_GlobalFirmwareID_HHD_firmwareMajorRevisionNumber u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure firmwareMajorRevisionNumber in AQ_GlobalFirmwareID_HHD */ +#define word_AQ_GlobalFirmwareID_HHD_firmwareMajorRevisionNumber u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure firmwareMinorRevisionNumber in AQ_GlobalFirmwareID_HHD */ +#define AQ_GlobalFirmwareID_HHD_firmwareMinorRevisionNumber 0 +/*! \brief Preprocessor variable to relate field to bit position in structure firmwareMinorRevisionNumber in AQ_GlobalFirmwareID_HHD */ +#define bits_AQ_GlobalFirmwareID_HHD_firmwareMinorRevisionNumber u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure firmwareMinorRevisionNumber in AQ_GlobalFirmwareID_HHD */ +#define word_AQ_GlobalFirmwareID_HHD_firmwareMinorRevisionNumber u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalNvrInterface_HHD */ +#define AQ_GlobalNvrInterface_HHD_baseRegisterAddress 0x0100 +/*! \brief MMD address of structure AQ_GlobalNvrInterface_HHD */ +#define AQ_GlobalNvrInterface_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure nvrExecuteOperation in AQ_GlobalNvrInterface_HHD */ +#define AQ_GlobalNvrInterface_HHD_nvrExecuteOperation 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrExecuteOperation in AQ_GlobalNvrInterface_HHD */ +#define bits_AQ_GlobalNvrInterface_HHD_nvrExecuteOperation u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrExecuteOperation in AQ_GlobalNvrInterface_HHD */ +#define word_AQ_GlobalNvrInterface_HHD_nvrExecuteOperation u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrWriteMode in AQ_GlobalNvrInterface_HHD */ +#define AQ_GlobalNvrInterface_HHD_nvrWriteMode 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrWriteMode in AQ_GlobalNvrInterface_HHD */ +#define bits_AQ_GlobalNvrInterface_HHD_nvrWriteMode u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrWriteMode in AQ_GlobalNvrInterface_HHD */ +#define word_AQ_GlobalNvrInterface_HHD_nvrWriteMode u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure freezeNvrCrc in AQ_GlobalNvrInterface_HHD */ +#define AQ_GlobalNvrInterface_HHD_freezeNvrCrc 0 +/*! \brief Preprocessor variable to relate field to bit position in structure freezeNvrCrc in AQ_GlobalNvrInterface_HHD */ +#define bits_AQ_GlobalNvrInterface_HHD_freezeNvrCrc u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure freezeNvrCrc in AQ_GlobalNvrInterface_HHD */ +#define word_AQ_GlobalNvrInterface_HHD_freezeNvrCrc u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure resetNvrCrc in AQ_GlobalNvrInterface_HHD */ +#define AQ_GlobalNvrInterface_HHD_resetNvrCrc 0 +/*! \brief Preprocessor variable to relate field to bit position in structure resetNvrCrc in AQ_GlobalNvrInterface_HHD */ +#define bits_AQ_GlobalNvrInterface_HHD_resetNvrCrc u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure resetNvrCrc in AQ_GlobalNvrInterface_HHD */ +#define word_AQ_GlobalNvrInterface_HHD_resetNvrCrc u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrBurst in AQ_GlobalNvrInterface_HHD */ +#define AQ_GlobalNvrInterface_HHD_nvrBurst 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrBurst in AQ_GlobalNvrInterface_HHD */ +#define bits_AQ_GlobalNvrInterface_HHD_nvrBurst u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrBurst in AQ_GlobalNvrInterface_HHD */ +#define word_AQ_GlobalNvrInterface_HHD_nvrBurst u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrBusy in AQ_GlobalNvrInterface_HHD */ +#define AQ_GlobalNvrInterface_HHD_nvrBusy 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrBusy in AQ_GlobalNvrInterface_HHD */ +#define bits_AQ_GlobalNvrInterface_HHD_nvrBusy u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrBusy in AQ_GlobalNvrInterface_HHD */ +#define word_AQ_GlobalNvrInterface_HHD_nvrBusy u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrOpcode in AQ_GlobalNvrInterface_HHD */ +#define AQ_GlobalNvrInterface_HHD_nvrOpcode 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrOpcode in AQ_GlobalNvrInterface_HHD */ +#define bits_AQ_GlobalNvrInterface_HHD_nvrOpcode u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrOpcode in AQ_GlobalNvrInterface_HHD */ +#define word_AQ_GlobalNvrInterface_HHD_nvrOpcode u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrMailboxCrc in AQ_GlobalNvrInterface_HHD */ +#define AQ_GlobalNvrInterface_HHD_nvrMailboxCrc 1 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrMailboxCrc in AQ_GlobalNvrInterface_HHD */ +#define bits_AQ_GlobalNvrInterface_HHD_nvrMailboxCrc u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure nvrMailboxCrc in AQ_GlobalNvrInterface_HHD */ +#define word_AQ_GlobalNvrInterface_HHD_nvrMailboxCrc u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure nvrAddressMSW in AQ_GlobalNvrInterface_HHD */ +#define AQ_GlobalNvrInterface_HHD_nvrAddressMSW 2 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrAddressMSW in AQ_GlobalNvrInterface_HHD */ +#define bits_AQ_GlobalNvrInterface_HHD_nvrAddressMSW u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure nvrAddressMSW in AQ_GlobalNvrInterface_HHD */ +#define word_AQ_GlobalNvrInterface_HHD_nvrAddressMSW u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure nvrAddressLSW in AQ_GlobalNvrInterface_HHD */ +#define AQ_GlobalNvrInterface_HHD_nvrAddressLSW 3 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrAddressLSW in AQ_GlobalNvrInterface_HHD */ +#define bits_AQ_GlobalNvrInterface_HHD_nvrAddressLSW u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure nvrAddressLSW in AQ_GlobalNvrInterface_HHD */ +#define word_AQ_GlobalNvrInterface_HHD_nvrAddressLSW u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure nvrDataMSW in AQ_GlobalNvrInterface_HHD */ +#define AQ_GlobalNvrInterface_HHD_nvrDataMSW 4 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrDataMSW in AQ_GlobalNvrInterface_HHD */ +#define bits_AQ_GlobalNvrInterface_HHD_nvrDataMSW u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure nvrDataMSW in AQ_GlobalNvrInterface_HHD */ +#define word_AQ_GlobalNvrInterface_HHD_nvrDataMSW u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure nvrDataLSW in AQ_GlobalNvrInterface_HHD */ +#define AQ_GlobalNvrInterface_HHD_nvrDataLSW 5 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrDataLSW in AQ_GlobalNvrInterface_HHD */ +#define bits_AQ_GlobalNvrInterface_HHD_nvrDataLSW u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure nvrDataLSW in AQ_GlobalNvrInterface_HHD */ +#define word_AQ_GlobalNvrInterface_HHD_nvrDataLSW u5.word_5 + +/*! \brief Base register address of structure AQ_GlobalMailboxInterface_HHD */ +#define AQ_GlobalMailboxInterface_HHD_baseRegisterAddress 0x0200 +/*! \brief MMD address of structure AQ_GlobalMailboxInterface_HHD */ +#define AQ_GlobalMailboxInterface_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxExecuteOperation in AQ_GlobalMailboxInterface_HHD */ +#define AQ_GlobalMailboxInterface_HHD_upMailboxExecuteOperation 0 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxExecuteOperation in AQ_GlobalMailboxInterface_HHD */ +#define bits_AQ_GlobalMailboxInterface_HHD_upMailboxExecuteOperation u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxExecuteOperation in AQ_GlobalMailboxInterface_HHD */ +#define word_AQ_GlobalMailboxInterface_HHD_upMailboxExecuteOperation u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxWriteMode in AQ_GlobalMailboxInterface_HHD */ +#define AQ_GlobalMailboxInterface_HHD_upMailboxWriteMode 0 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxWriteMode in AQ_GlobalMailboxInterface_HHD */ +#define bits_AQ_GlobalMailboxInterface_HHD_upMailboxWriteMode u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxWriteMode in AQ_GlobalMailboxInterface_HHD */ +#define word_AQ_GlobalMailboxInterface_HHD_upMailboxWriteMode u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure resetUpMailboxCrc in AQ_GlobalMailboxInterface_HHD */ +#define AQ_GlobalMailboxInterface_HHD_resetUpMailboxCrc 0 +/*! \brief Preprocessor variable to relate field to bit position in structure resetUpMailboxCrc in AQ_GlobalMailboxInterface_HHD */ +#define bits_AQ_GlobalMailboxInterface_HHD_resetUpMailboxCrc u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure resetUpMailboxCrc in AQ_GlobalMailboxInterface_HHD */ +#define word_AQ_GlobalMailboxInterface_HHD_resetUpMailboxCrc u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxBusy in AQ_GlobalMailboxInterface_HHD */ +#define AQ_GlobalMailboxInterface_HHD_upMailboxBusy 0 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxBusy in AQ_GlobalMailboxInterface_HHD */ +#define bits_AQ_GlobalMailboxInterface_HHD_upMailboxBusy u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxBusy in AQ_GlobalMailboxInterface_HHD */ +#define word_AQ_GlobalMailboxInterface_HHD_upMailboxBusy u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxCrc in AQ_GlobalMailboxInterface_HHD */ +#define AQ_GlobalMailboxInterface_HHD_upMailboxCrc 1 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxCrc in AQ_GlobalMailboxInterface_HHD */ +#define bits_AQ_GlobalMailboxInterface_HHD_upMailboxCrc u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxCrc in AQ_GlobalMailboxInterface_HHD */ +#define word_AQ_GlobalMailboxInterface_HHD_upMailboxCrc u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxAddressMSW in AQ_GlobalMailboxInterface_HHD */ +#define AQ_GlobalMailboxInterface_HHD_upMailboxAddressMSW 2 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxAddressMSW in AQ_GlobalMailboxInterface_HHD */ +#define bits_AQ_GlobalMailboxInterface_HHD_upMailboxAddressMSW u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxAddressMSW in AQ_GlobalMailboxInterface_HHD */ +#define word_AQ_GlobalMailboxInterface_HHD_upMailboxAddressMSW u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxAddressLSW in AQ_GlobalMailboxInterface_HHD */ +#define AQ_GlobalMailboxInterface_HHD_upMailboxAddressLSW 3 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxAddressLSW in AQ_GlobalMailboxInterface_HHD */ +#define bits_AQ_GlobalMailboxInterface_HHD_upMailboxAddressLSW u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxAddressLSW in AQ_GlobalMailboxInterface_HHD */ +#define word_AQ_GlobalMailboxInterface_HHD_upMailboxAddressLSW u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxAddressLSW_Don_tCare in AQ_GlobalMailboxInterface_HHD */ +#define AQ_GlobalMailboxInterface_HHD_upMailboxAddressLSW_Don_tCare 3 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxAddressLSW_Don_tCare in AQ_GlobalMailboxInterface_HHD */ +#define bits_AQ_GlobalMailboxInterface_HHD_upMailboxAddressLSW_Don_tCare u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxAddressLSW_Don_tCare in AQ_GlobalMailboxInterface_HHD */ +#define word_AQ_GlobalMailboxInterface_HHD_upMailboxAddressLSW_Don_tCare u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxDataMSW in AQ_GlobalMailboxInterface_HHD */ +#define AQ_GlobalMailboxInterface_HHD_upMailboxDataMSW 4 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxDataMSW in AQ_GlobalMailboxInterface_HHD */ +#define bits_AQ_GlobalMailboxInterface_HHD_upMailboxDataMSW u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxDataMSW in AQ_GlobalMailboxInterface_HHD */ +#define word_AQ_GlobalMailboxInterface_HHD_upMailboxDataMSW u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxDataLSW in AQ_GlobalMailboxInterface_HHD */ +#define AQ_GlobalMailboxInterface_HHD_upMailboxDataLSW 5 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxDataLSW in AQ_GlobalMailboxInterface_HHD */ +#define bits_AQ_GlobalMailboxInterface_HHD_upMailboxDataLSW u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxDataLSW in AQ_GlobalMailboxInterface_HHD */ +#define word_AQ_GlobalMailboxInterface_HHD_upMailboxDataLSW u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure upMailboxCrcReadEnable in AQ_GlobalMailboxInterface_HHD */ +#define AQ_GlobalMailboxInterface_HHD_upMailboxCrcReadEnable 6 +/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxCrcReadEnable in AQ_GlobalMailboxInterface_HHD */ +#define bits_AQ_GlobalMailboxInterface_HHD_upMailboxCrcReadEnable u6.bits_6 +/*! \brief Preprocessor variable to relate field to word position in structure upMailboxCrcReadEnable in AQ_GlobalMailboxInterface_HHD */ +#define word_AQ_GlobalMailboxInterface_HHD_upMailboxCrcReadEnable u6.word_6 + +/*! \brief Base register address of structure AQ_GlobalMicroprocessorScratchPad_HHD */ +#define AQ_GlobalMicroprocessorScratchPad_HHD_baseRegisterAddress 0x0300 +/*! \brief MMD address of structure AQ_GlobalMicroprocessorScratchPad_HHD */ +#define AQ_GlobalMicroprocessorScratchPad_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure scratchPad_1 in AQ_GlobalMicroprocessorScratchPad_HHD */ +#define AQ_GlobalMicroprocessorScratchPad_HHD_scratchPad_1 0 +/*! \brief Preprocessor variable to relate field to bit position in structure scratchPad_1 in AQ_GlobalMicroprocessorScratchPad_HHD */ +#define bits_AQ_GlobalMicroprocessorScratchPad_HHD_scratchPad_1 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure scratchPad_1 in AQ_GlobalMicroprocessorScratchPad_HHD */ +#define word_AQ_GlobalMicroprocessorScratchPad_HHD_scratchPad_1 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure scratchPad_2 in AQ_GlobalMicroprocessorScratchPad_HHD */ +#define AQ_GlobalMicroprocessorScratchPad_HHD_scratchPad_2 1 +/*! \brief Preprocessor variable to relate field to bit position in structure scratchPad_2 in AQ_GlobalMicroprocessorScratchPad_HHD */ +#define bits_AQ_GlobalMicroprocessorScratchPad_HHD_scratchPad_2 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure scratchPad_2 in AQ_GlobalMicroprocessorScratchPad_HHD */ +#define word_AQ_GlobalMicroprocessorScratchPad_HHD_scratchPad_2 u1.word_1 + +/*! \brief Base register address of structure AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_baseRegisterAddress 0x5002 +/*! \brief MMD address of structure AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressEthertypeExplicitSectagLsb in AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mssEgressEthertypeExplicitSectagLsb 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressEthertypeExplicitSectagLsb in AQ_MssEgressControlRegister_HHD */ +#define bits_AQ_MssEgressControlRegister_HHD_mssEgressEthertypeExplicitSectagLsb u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressEthertypeExplicitSectagLsb in AQ_MssEgressControlRegister_HHD */ +#define word_AQ_MssEgressControlRegister_HHD_mssEgressEthertypeExplicitSectagLsb u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressClearGlobalTime in AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mssEgressClearGlobalTime 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressClearGlobalTime in AQ_MssEgressControlRegister_HHD */ +#define bits_AQ_MssEgressControlRegister_HHD_mssEgressClearGlobalTime u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressClearGlobalTime in AQ_MssEgressControlRegister_HHD */ +#define word_AQ_MssEgressControlRegister_HHD_mssEgressClearGlobalTime u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressClearCounter in AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mssEgressClearCounter 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressClearCounter in AQ_MssEgressControlRegister_HHD */ +#define bits_AQ_MssEgressControlRegister_HHD_mssEgressClearCounter u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressClearCounter in AQ_MssEgressControlRegister_HHD */ +#define word_AQ_MssEgressControlRegister_HHD_mssEgressClearCounter u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressHighPriority in AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mssEgressHighPriority 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressHighPriority in AQ_MssEgressControlRegister_HHD */ +#define bits_AQ_MssEgressControlRegister_HHD_mssEgressHighPriority u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressHighPriority in AQ_MssEgressControlRegister_HHD */ +#define word_AQ_MssEgressControlRegister_HHD_mssEgressHighPriority u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressIcvLsb_8BytesEnable in AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mssEgressIcvLsb_8BytesEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressIcvLsb_8BytesEnable in AQ_MssEgressControlRegister_HHD */ +#define bits_AQ_MssEgressControlRegister_HHD_mssEgressIcvLsb_8BytesEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressIcvLsb_8BytesEnable in AQ_MssEgressControlRegister_HHD */ +#define word_AQ_MssEgressControlRegister_HHD_mssEgressIcvLsb_8BytesEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressExternalClassificationEnable in AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mssEgressExternalClassificationEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressExternalClassificationEnable in AQ_MssEgressControlRegister_HHD */ +#define bits_AQ_MssEgressControlRegister_HHD_mssEgressExternalClassificationEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressExternalClassificationEnable in AQ_MssEgressControlRegister_HHD */ +#define word_AQ_MssEgressControlRegister_HHD_mssEgressExternalClassificationEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressExplicitSectagReportShortLength in AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mssEgressExplicitSectagReportShortLength 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressExplicitSectagReportShortLength in AQ_MssEgressControlRegister_HHD */ +#define bits_AQ_MssEgressControlRegister_HHD_mssEgressExplicitSectagReportShortLength u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressExplicitSectagReportShortLength in AQ_MssEgressControlRegister_HHD */ +#define word_AQ_MssEgressControlRegister_HHD_mssEgressExplicitSectagReportShortLength u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressDropInvalidSa_scPackets in AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mssEgressDropInvalidSa_scPackets 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressDropInvalidSa_scPackets in AQ_MssEgressControlRegister_HHD */ +#define bits_AQ_MssEgressControlRegister_HHD_mssEgressDropInvalidSa_scPackets u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressDropInvalidSa_scPackets in AQ_MssEgressControlRegister_HHD */ +#define word_AQ_MssEgressControlRegister_HHD_mssEgressDropInvalidSa_scPackets u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressUnmatchedUseSc_0 in AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mssEgressUnmatchedUseSc_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressUnmatchedUseSc_0 in AQ_MssEgressControlRegister_HHD */ +#define bits_AQ_MssEgressControlRegister_HHD_mssEgressUnmatchedUseSc_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressUnmatchedUseSc_0 in AQ_MssEgressControlRegister_HHD */ +#define word_AQ_MssEgressControlRegister_HHD_mssEgressUnmatchedUseSc_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgresssGcmTestMode in AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mssEgresssGcmTestMode 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgresssGcmTestMode in AQ_MssEgressControlRegister_HHD */ +#define bits_AQ_MssEgressControlRegister_HHD_mssEgresssGcmTestMode u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgresssGcmTestMode in AQ_MssEgressControlRegister_HHD */ +#define word_AQ_MssEgressControlRegister_HHD_mssEgresssGcmTestMode u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressGcmStart in AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mssEgressGcmStart 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressGcmStart in AQ_MssEgressControlRegister_HHD */ +#define bits_AQ_MssEgressControlRegister_HHD_mssEgressGcmStart u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressGcmStart in AQ_MssEgressControlRegister_HHD */ +#define word_AQ_MssEgressControlRegister_HHD_mssEgressGcmStart u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressDropEgprcLutMiss in AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mssEgressDropEgprcLutMiss 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressDropEgprcLutMiss in AQ_MssEgressControlRegister_HHD */ +#define bits_AQ_MssEgressControlRegister_HHD_mssEgressDropEgprcLutMiss u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressDropEgprcLutMiss in AQ_MssEgressControlRegister_HHD */ +#define word_AQ_MssEgressControlRegister_HHD_mssEgressDropEgprcLutMiss u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressDropKayPacket in AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mssEgressDropKayPacket 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressDropKayPacket in AQ_MssEgressControlRegister_HHD */ +#define bits_AQ_MssEgressControlRegister_HHD_mssEgressDropKayPacket u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressDropKayPacket in AQ_MssEgressControlRegister_HHD */ +#define word_AQ_MssEgressControlRegister_HHD_mssEgressDropKayPacket u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSoftReset in AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mssEgressSoftReset 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSoftReset in AQ_MssEgressControlRegister_HHD */ +#define bits_AQ_MssEgressControlRegister_HHD_mssEgressSoftReset u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSoftReset in AQ_MssEgressControlRegister_HHD */ +#define word_AQ_MssEgressControlRegister_HHD_mssEgressSoftReset u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressEthertypeExplicitSectagMsb in AQ_MssEgressControlRegister_HHD */ +#define AQ_MssEgressControlRegister_HHD_mssEgressEthertypeExplicitSectagMsb 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressEthertypeExplicitSectagMsb in AQ_MssEgressControlRegister_HHD */ +#define bits_AQ_MssEgressControlRegister_HHD_mssEgressEthertypeExplicitSectagMsb u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressEthertypeExplicitSectagMsb in AQ_MssEgressControlRegister_HHD */ +#define word_AQ_MssEgressControlRegister_HHD_mssEgressEthertypeExplicitSectagMsb u1.word_1 + +/*! \brief Base register address of structure AQ_MssEgressVlanTpid_0Register_HHD */ +#define AQ_MssEgressVlanTpid_0Register_HHD_baseRegisterAddress 0x5008 +/*! \brief MMD address of structure AQ_MssEgressVlanTpid_0Register_HHD */ +#define AQ_MssEgressVlanTpid_0Register_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressVlanStagTpid in AQ_MssEgressVlanTpid_0Register_HHD */ +#define AQ_MssEgressVlanTpid_0Register_HHD_mssEgressVlanStagTpid 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressVlanStagTpid in AQ_MssEgressVlanTpid_0Register_HHD */ +#define bits_AQ_MssEgressVlanTpid_0Register_HHD_mssEgressVlanStagTpid u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressVlanStagTpid in AQ_MssEgressVlanTpid_0Register_HHD */ +#define word_AQ_MssEgressVlanTpid_0Register_HHD_mssEgressVlanStagTpid u0.word_0 + +/*! \brief Base register address of structure AQ_MssEgressVlanTpid_1Register_HHD */ +#define AQ_MssEgressVlanTpid_1Register_HHD_baseRegisterAddress 0x500A +/*! \brief MMD address of structure AQ_MssEgressVlanTpid_1Register_HHD */ +#define AQ_MssEgressVlanTpid_1Register_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressVlanQtagTpid in AQ_MssEgressVlanTpid_1Register_HHD */ +#define AQ_MssEgressVlanTpid_1Register_HHD_mssEgressVlanQtagTpid 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressVlanQtagTpid in AQ_MssEgressVlanTpid_1Register_HHD */ +#define bits_AQ_MssEgressVlanTpid_1Register_HHD_mssEgressVlanQtagTpid u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressVlanQtagTpid in AQ_MssEgressVlanTpid_1Register_HHD */ +#define word_AQ_MssEgressVlanTpid_1Register_HHD_mssEgressVlanQtagTpid u0.word_0 + +/*! \brief Base register address of structure AQ_MssEgressVlanControlRegister_HHD */ +#define AQ_MssEgressVlanControlRegister_HHD_baseRegisterAddress 0x500C +/*! \brief MMD address of structure AQ_MssEgressVlanControlRegister_HHD */ +#define AQ_MssEgressVlanControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressVlanUpMapTable in AQ_MssEgressVlanControlRegister_HHD */ +#define AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanUpMapTable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressVlanUpMapTable in AQ_MssEgressVlanControlRegister_HHD */ +#define bits_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanUpMapTable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressVlanUpMapTable in AQ_MssEgressVlanControlRegister_HHD */ +#define word_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanUpMapTable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressVlanQtagParseEnable in AQ_MssEgressVlanControlRegister_HHD */ +#define AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanQtagParseEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressVlanQtagParseEnable in AQ_MssEgressVlanControlRegister_HHD */ +#define bits_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanQtagParseEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressVlanQtagParseEnable in AQ_MssEgressVlanControlRegister_HHD */ +#define word_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanQtagParseEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressVlanStagParseEnable in AQ_MssEgressVlanControlRegister_HHD */ +#define AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanStagParseEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressVlanStagParseEnable in AQ_MssEgressVlanControlRegister_HHD */ +#define bits_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanStagParseEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressVlanStagParseEnable in AQ_MssEgressVlanControlRegister_HHD */ +#define word_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanStagParseEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressVlanQinqParseEnable in AQ_MssEgressVlanControlRegister_HHD */ +#define AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanQinqParseEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressVlanQinqParseEnable in AQ_MssEgressVlanControlRegister_HHD */ +#define bits_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanQinqParseEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressVlanQinqParseEnable in AQ_MssEgressVlanControlRegister_HHD */ +#define word_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanQinqParseEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressVlanQtagUpParseEnable in AQ_MssEgressVlanControlRegister_HHD */ +#define AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanQtagUpParseEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressVlanQtagUpParseEnable in AQ_MssEgressVlanControlRegister_HHD */ +#define bits_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanQtagUpParseEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressVlanQtagUpParseEnable in AQ_MssEgressVlanControlRegister_HHD */ +#define word_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanQtagUpParseEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressVlanStagUpParseEnable in AQ_MssEgressVlanControlRegister_HHD */ +#define AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanStagUpParseEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressVlanStagUpParseEnable in AQ_MssEgressVlanControlRegister_HHD */ +#define bits_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanStagUpParseEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressVlanStagUpParseEnable in AQ_MssEgressVlanControlRegister_HHD */ +#define word_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanStagUpParseEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressVlanUpDefault in AQ_MssEgressVlanControlRegister_HHD */ +#define AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanUpDefault 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressVlanUpDefault in AQ_MssEgressVlanControlRegister_HHD */ +#define bits_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanUpDefault u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressVlanUpDefault in AQ_MssEgressVlanControlRegister_HHD */ +#define word_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanUpDefault u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressVlanUpMapTableMSW in AQ_MssEgressVlanControlRegister_HHD */ +#define AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanUpMapTableMSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressVlanUpMapTableMSW in AQ_MssEgressVlanControlRegister_HHD */ +#define bits_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanUpMapTableMSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressVlanUpMapTableMSW in AQ_MssEgressVlanControlRegister_HHD */ +#define word_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanUpMapTableMSW u1.word_1 + +/*! \brief Base register address of structure AQ_MssEgressPnControlRegister_HHD */ +#define AQ_MssEgressPnControlRegister_HHD_baseRegisterAddress 0x500E +/*! \brief MMD address of structure AQ_MssEgressPnControlRegister_HHD */ +#define AQ_MssEgressPnControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaPnThresholdLSW in AQ_MssEgressPnControlRegister_HHD */ +#define AQ_MssEgressPnControlRegister_HHD_mssEgressSaPnThresholdLSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaPnThresholdLSW in AQ_MssEgressPnControlRegister_HHD */ +#define bits_AQ_MssEgressPnControlRegister_HHD_mssEgressSaPnThresholdLSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaPnThresholdLSW in AQ_MssEgressPnControlRegister_HHD */ +#define word_AQ_MssEgressPnControlRegister_HHD_mssEgressSaPnThresholdLSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaPnThresholdMSW in AQ_MssEgressPnControlRegister_HHD */ +#define AQ_MssEgressPnControlRegister_HHD_mssEgressSaPnThresholdMSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaPnThresholdMSW in AQ_MssEgressPnControlRegister_HHD */ +#define bits_AQ_MssEgressPnControlRegister_HHD_mssEgressSaPnThresholdMSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaPnThresholdMSW in AQ_MssEgressPnControlRegister_HHD */ +#define word_AQ_MssEgressPnControlRegister_HHD_mssEgressSaPnThresholdMSW u1.word_1 + +/*! \brief Base register address of structure AQ_MssEgressMtuSizeControlRegister_HHD */ +#define AQ_MssEgressMtuSizeControlRegister_HHD_baseRegisterAddress 0x5010 +/*! \brief MMD address of structure AQ_MssEgressMtuSizeControlRegister_HHD */ +#define AQ_MssEgressMtuSizeControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressControlledPacketMtuSize in AQ_MssEgressMtuSizeControlRegister_HHD */ +#define AQ_MssEgressMtuSizeControlRegister_HHD_mssEgressControlledPacketMtuSize 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressControlledPacketMtuSize in AQ_MssEgressMtuSizeControlRegister_HHD */ +#define bits_AQ_MssEgressMtuSizeControlRegister_HHD_mssEgressControlledPacketMtuSize u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressControlledPacketMtuSize in AQ_MssEgressMtuSizeControlRegister_HHD */ +#define word_AQ_MssEgressMtuSizeControlRegister_HHD_mssEgressControlledPacketMtuSize u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressUncontrolledPacketMtuSize in AQ_MssEgressMtuSizeControlRegister_HHD */ +#define AQ_MssEgressMtuSizeControlRegister_HHD_mssEgressUncontrolledPacketMtuSize 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressUncontrolledPacketMtuSize in AQ_MssEgressMtuSizeControlRegister_HHD */ +#define bits_AQ_MssEgressMtuSizeControlRegister_HHD_mssEgressUncontrolledPacketMtuSize u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressUncontrolledPacketMtuSize in AQ_MssEgressMtuSizeControlRegister_HHD */ +#define word_AQ_MssEgressMtuSizeControlRegister_HHD_mssEgressUncontrolledPacketMtuSize u1.word_1 + +/*! \brief Base register address of structure AQ_MssEgressInterruptStatusRegister_HHD */ +#define AQ_MssEgressInterruptStatusRegister_HHD_baseRegisterAddress 0x505C +/*! \brief MMD address of structure AQ_MssEgressInterruptStatusRegister_HHD */ +#define AQ_MssEgressInterruptStatusRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressEccErrorInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ +#define AQ_MssEgressInterruptStatusRegister_HHD_mssEgressEccErrorInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressEccErrorInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ +#define bits_AQ_MssEgressInterruptStatusRegister_HHD_mssEgressEccErrorInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressEccErrorInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ +#define word_AQ_MssEgressInterruptStatusRegister_HHD_mssEgressEccErrorInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressMibSaturationInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ +#define AQ_MssEgressInterruptStatusRegister_HHD_mssEgressMibSaturationInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressMibSaturationInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ +#define bits_AQ_MssEgressInterruptStatusRegister_HHD_mssEgressMibSaturationInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressMibSaturationInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ +#define word_AQ_MssEgressInterruptStatusRegister_HHD_mssEgressMibSaturationInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaThresholdExpiredInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ +#define AQ_MssEgressInterruptStatusRegister_HHD_mssEgressSaThresholdExpiredInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaThresholdExpiredInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ +#define bits_AQ_MssEgressInterruptStatusRegister_HHD_mssEgressSaThresholdExpiredInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaThresholdExpiredInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ +#define word_AQ_MssEgressInterruptStatusRegister_HHD_mssEgressSaThresholdExpiredInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaExpiredInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ +#define AQ_MssEgressInterruptStatusRegister_HHD_mssEgressSaExpiredInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaExpiredInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ +#define bits_AQ_MssEgressInterruptStatusRegister_HHD_mssEgressSaExpiredInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaExpiredInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ +#define word_AQ_MssEgressInterruptStatusRegister_HHD_mssEgressSaExpiredInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressMasterInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ +#define AQ_MssEgressInterruptStatusRegister_HHD_mssEgressMasterInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressMasterInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ +#define bits_AQ_MssEgressInterruptStatusRegister_HHD_mssEgressMasterInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressMasterInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ +#define word_AQ_MssEgressInterruptStatusRegister_HHD_mssEgressMasterInterrupt u0.word_0 + +/*! \brief Base register address of structure AQ_MssEgressInterruptMaskRegister_HHD */ +#define AQ_MssEgressInterruptMaskRegister_HHD_baseRegisterAddress 0x505E +/*! \brief MMD address of structure AQ_MssEgressInterruptMaskRegister_HHD */ +#define AQ_MssEgressInterruptMaskRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressEccErrorInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ +#define AQ_MssEgressInterruptMaskRegister_HHD_mssEgressEccErrorInterruptEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressEccErrorInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ +#define bits_AQ_MssEgressInterruptMaskRegister_HHD_mssEgressEccErrorInterruptEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressEccErrorInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ +#define word_AQ_MssEgressInterruptMaskRegister_HHD_mssEgressEccErrorInterruptEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressMibSaturationInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ +#define AQ_MssEgressInterruptMaskRegister_HHD_mssEgressMibSaturationInterruptEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressMibSaturationInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ +#define bits_AQ_MssEgressInterruptMaskRegister_HHD_mssEgressMibSaturationInterruptEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressMibSaturationInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ +#define word_AQ_MssEgressInterruptMaskRegister_HHD_mssEgressMibSaturationInterruptEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaExpiredThresholdInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ +#define AQ_MssEgressInterruptMaskRegister_HHD_mssEgressSaExpiredThresholdInterruptEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaExpiredThresholdInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ +#define bits_AQ_MssEgressInterruptMaskRegister_HHD_mssEgressSaExpiredThresholdInterruptEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaExpiredThresholdInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ +#define word_AQ_MssEgressInterruptMaskRegister_HHD_mssEgressSaExpiredThresholdInterruptEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaExpiredInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ +#define AQ_MssEgressInterruptMaskRegister_HHD_mssEgressSaExpiredInterruptEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaExpiredInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ +#define bits_AQ_MssEgressInterruptMaskRegister_HHD_mssEgressSaExpiredInterruptEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaExpiredInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ +#define word_AQ_MssEgressInterruptMaskRegister_HHD_mssEgressSaExpiredInterruptEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressMasterInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ +#define AQ_MssEgressInterruptMaskRegister_HHD_mssEgressMasterInterruptEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressMasterInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ +#define bits_AQ_MssEgressInterruptMaskRegister_HHD_mssEgressMasterInterruptEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressMasterInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ +#define word_AQ_MssEgressInterruptMaskRegister_HHD_mssEgressMasterInterruptEnable u0.word_0 + +/*! \brief Base register address of structure AQ_MssEgressSaExpiredStatusRegister_HHD */ +#define AQ_MssEgressSaExpiredStatusRegister_HHD_baseRegisterAddress 0x5060 +/*! \brief MMD address of structure AQ_MssEgressSaExpiredStatusRegister_HHD */ +#define AQ_MssEgressSaExpiredStatusRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaExpiredLSW in AQ_MssEgressSaExpiredStatusRegister_HHD */ +#define AQ_MssEgressSaExpiredStatusRegister_HHD_mssEgressSaExpiredLSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaExpiredLSW in AQ_MssEgressSaExpiredStatusRegister_HHD */ +#define bits_AQ_MssEgressSaExpiredStatusRegister_HHD_mssEgressSaExpiredLSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaExpiredLSW in AQ_MssEgressSaExpiredStatusRegister_HHD */ +#define word_AQ_MssEgressSaExpiredStatusRegister_HHD_mssEgressSaExpiredLSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaExpiredMSW in AQ_MssEgressSaExpiredStatusRegister_HHD */ +#define AQ_MssEgressSaExpiredStatusRegister_HHD_mssEgressSaExpiredMSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaExpiredMSW in AQ_MssEgressSaExpiredStatusRegister_HHD */ +#define bits_AQ_MssEgressSaExpiredStatusRegister_HHD_mssEgressSaExpiredMSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaExpiredMSW in AQ_MssEgressSaExpiredStatusRegister_HHD */ +#define word_AQ_MssEgressSaExpiredStatusRegister_HHD_mssEgressSaExpiredMSW u1.word_1 + +/*! \brief Base register address of structure AQ_MssEgressSaThresholdExpiredStatusRegister_HHD */ +#define AQ_MssEgressSaThresholdExpiredStatusRegister_HHD_baseRegisterAddress 0x5062 +/*! \brief MMD address of structure AQ_MssEgressSaThresholdExpiredStatusRegister_HHD */ +#define AQ_MssEgressSaThresholdExpiredStatusRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaThresholdExpiredLSW in AQ_MssEgressSaThresholdExpiredStatusRegister_HHD */ +#define AQ_MssEgressSaThresholdExpiredStatusRegister_HHD_mssEgressSaThresholdExpiredLSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaThresholdExpiredLSW in AQ_MssEgressSaThresholdExpiredStatusRegister_HHD */ +#define bits_AQ_MssEgressSaThresholdExpiredStatusRegister_HHD_mssEgressSaThresholdExpiredLSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaThresholdExpiredLSW in AQ_MssEgressSaThresholdExpiredStatusRegister_HHD */ +#define word_AQ_MssEgressSaThresholdExpiredStatusRegister_HHD_mssEgressSaThresholdExpiredLSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaThresholdExpiredMSW in AQ_MssEgressSaThresholdExpiredStatusRegister_HHD */ +#define AQ_MssEgressSaThresholdExpiredStatusRegister_HHD_mssEgressSaThresholdExpiredMSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaThresholdExpiredMSW in AQ_MssEgressSaThresholdExpiredStatusRegister_HHD */ +#define bits_AQ_MssEgressSaThresholdExpiredStatusRegister_HHD_mssEgressSaThresholdExpiredMSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaThresholdExpiredMSW in AQ_MssEgressSaThresholdExpiredStatusRegister_HHD */ +#define word_AQ_MssEgressSaThresholdExpiredStatusRegister_HHD_mssEgressSaThresholdExpiredMSW u1.word_1 + +/*! \brief Base register address of structure AQ_MssEgressEccInterruptStatusRegister_HHD */ +#define AQ_MssEgressEccInterruptStatusRegister_HHD_baseRegisterAddress 0x5064 +/*! \brief MMD address of structure AQ_MssEgressEccInterruptStatusRegister_HHD */ +#define AQ_MssEgressEccInterruptStatusRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaEccErrorInterruptLSW in AQ_MssEgressEccInterruptStatusRegister_HHD */ +#define AQ_MssEgressEccInterruptStatusRegister_HHD_mssEgressSaEccErrorInterruptLSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaEccErrorInterruptLSW in AQ_MssEgressEccInterruptStatusRegister_HHD */ +#define bits_AQ_MssEgressEccInterruptStatusRegister_HHD_mssEgressSaEccErrorInterruptLSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaEccErrorInterruptLSW in AQ_MssEgressEccInterruptStatusRegister_HHD */ +#define word_AQ_MssEgressEccInterruptStatusRegister_HHD_mssEgressSaEccErrorInterruptLSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaEccErrorInterruptMSW in AQ_MssEgressEccInterruptStatusRegister_HHD */ +#define AQ_MssEgressEccInterruptStatusRegister_HHD_mssEgressSaEccErrorInterruptMSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaEccErrorInterruptMSW in AQ_MssEgressEccInterruptStatusRegister_HHD */ +#define bits_AQ_MssEgressEccInterruptStatusRegister_HHD_mssEgressSaEccErrorInterruptMSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaEccErrorInterruptMSW in AQ_MssEgressEccInterruptStatusRegister_HHD */ +#define word_AQ_MssEgressEccInterruptStatusRegister_HHD_mssEgressSaEccErrorInterruptMSW u1.word_1 + +/*! \brief Base register address of structure AQ_MssEgressLutAddressControlRegister_HHD */ +#define AQ_MssEgressLutAddressControlRegister_HHD_baseRegisterAddress 0x5080 +/*! \brief MMD address of structure AQ_MssEgressLutAddressControlRegister_HHD */ +#define AQ_MssEgressLutAddressControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutSelect in AQ_MssEgressLutAddressControlRegister_HHD */ +#define AQ_MssEgressLutAddressControlRegister_HHD_mssEgressLutSelect 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutSelect in AQ_MssEgressLutAddressControlRegister_HHD */ +#define bits_AQ_MssEgressLutAddressControlRegister_HHD_mssEgressLutSelect u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutSelect in AQ_MssEgressLutAddressControlRegister_HHD */ +#define word_AQ_MssEgressLutAddressControlRegister_HHD_mssEgressLutSelect u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutAddress in AQ_MssEgressLutAddressControlRegister_HHD */ +#define AQ_MssEgressLutAddressControlRegister_HHD_mssEgressLutAddress 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutAddress in AQ_MssEgressLutAddressControlRegister_HHD */ +#define bits_AQ_MssEgressLutAddressControlRegister_HHD_mssEgressLutAddress u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutAddress in AQ_MssEgressLutAddressControlRegister_HHD */ +#define word_AQ_MssEgressLutAddressControlRegister_HHD_mssEgressLutAddress u0.word_0 + +/*! \brief Base register address of structure AQ_MssEgressLutControlRegister_HHD */ +#define AQ_MssEgressLutControlRegister_HHD_baseRegisterAddress 0x5081 +/*! \brief MMD address of structure AQ_MssEgressLutControlRegister_HHD */ +#define AQ_MssEgressLutControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutWrite in AQ_MssEgressLutControlRegister_HHD */ +#define AQ_MssEgressLutControlRegister_HHD_mssEgressLutWrite 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutWrite in AQ_MssEgressLutControlRegister_HHD */ +#define bits_AQ_MssEgressLutControlRegister_HHD_mssEgressLutWrite u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutWrite in AQ_MssEgressLutControlRegister_HHD */ +#define word_AQ_MssEgressLutControlRegister_HHD_mssEgressLutWrite u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutRead in AQ_MssEgressLutControlRegister_HHD */ +#define AQ_MssEgressLutControlRegister_HHD_mssEgressLutRead 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutRead in AQ_MssEgressLutControlRegister_HHD */ +#define bits_AQ_MssEgressLutControlRegister_HHD_mssEgressLutRead u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutRead in AQ_MssEgressLutControlRegister_HHD */ +#define word_AQ_MssEgressLutControlRegister_HHD_mssEgressLutRead u0.word_0 + +/*! \brief Base register address of structure AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_baseRegisterAddress 0x50A0 +/*! \brief MMD address of structure AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_0 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_0 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_0 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_1 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_1 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_1 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_1 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_2 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_2 2 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_2 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_2 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_2 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_2 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_3 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_3 3 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_3 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_3 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_3 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_3 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_4 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_4 4 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_4 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_4 u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_4 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_4 u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_5 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_5 5 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_5 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_5 u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_5 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_5 u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_6 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_6 6 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_6 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_6 u6.bits_6 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_6 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_6 u6.word_6 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_7 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_7 7 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_7 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_7 u7.bits_7 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_7 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_7 u7.word_7 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_8 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_8 8 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_8 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_8 u8.bits_8 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_8 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_8 u8.word_8 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_9 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_9 9 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_9 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_9 u9.bits_9 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_9 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_9 u9.word_9 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_10 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_10 10 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_10 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_10 u10.bits_10 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_10 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_10 u10.word_10 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_11 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_11 11 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_11 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_11 u11.bits_11 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_11 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_11 u11.word_11 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_12 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_12 12 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_12 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_12 u12.bits_12 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_12 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_12 u12.word_12 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_13 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_13 13 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_13 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_13 u13.bits_13 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_13 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_13 u13.word_13 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_14 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_14 14 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_14 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_14 u14.bits_14 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_14 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_14 u14.word_14 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_15 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_15 15 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_15 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_15 u15.bits_15 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_15 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_15 u15.word_15 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_16 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_16 16 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_16 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_16 u16.bits_16 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_16 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_16 u16.word_16 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_17 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_17 17 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_17 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_17 u17.bits_17 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_17 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_17 u17.word_17 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_18 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_18 18 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_18 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_18 u18.bits_18 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_18 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_18 u18.word_18 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_19 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_19 19 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_19 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_19 u19.bits_19 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_19 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_19 u19.word_19 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_20 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_20 20 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_20 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_20 u20.bits_20 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_20 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_20 u20.word_20 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_21 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_21 21 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_21 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_21 u21.bits_21 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_21 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_21 u21.word_21 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_22 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_22 22 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_22 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_22 u22.bits_22 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_22 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_22 u22.word_22 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_23 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_23 23 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_23 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_23 u23.bits_23 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_23 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_23 u23.word_23 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_24 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_24 24 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_24 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_24 u24.bits_24 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_24 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_24 u24.word_24 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_25 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_25 25 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_25 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_25 u25.bits_25 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_25 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_25 u25.word_25 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_26 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_26 26 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_26 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_26 u26.bits_26 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_26 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_26 u26.word_26 +/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_27 in AQ_MssEgressLutDataControlRegister_HHD */ +#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_27 27 +/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_27 in AQ_MssEgressLutDataControlRegister_HHD */ +#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_27 u27.bits_27 +/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_27 in AQ_MssEgressLutDataControlRegister_HHD */ +#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_27 u27.word_27 + +/*! \brief Base register address of structure AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_baseRegisterAddress 0x6004 +/*! \brief MMD address of structure AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemPhyTxEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPhyTxEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemPhyTxEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPhyTxEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemPhyTxEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPhyTxEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxErrorDiscard in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemRxErrorDiscard 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxErrorDiscard in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemRxErrorDiscard u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxErrorDiscard in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemRxErrorDiscard u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemControlFrameEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemControlFrameEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemControlFrameEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemControlFrameEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemControlFrameEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemControlFrameEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemSoftReset in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemSoftReset 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemSoftReset in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemSoftReset u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemSoftReset in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemSoftReset u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxPadEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxPadEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxPadEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxPadEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxPadEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxPadEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxCrcAppend in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxCrcAppend 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxCrcAppend in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxCrcAppend u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxCrcAppend in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxCrcAppend u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxAddressInsertEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxAddressInsertEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxAddressInsertEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxAddressInsertEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxAddressInsertEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxAddressInsertEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemPauseIgnore in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPauseIgnore 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemPauseIgnore in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPauseIgnore u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemPauseIgnore in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPauseIgnore u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemPauseForward in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPauseForward 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemPauseForward in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPauseForward u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemPauseForward in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPauseForward u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemCrcForward in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemCrcForward 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemCrcForward in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemCrcForward u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemCrcForward in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemCrcForward u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemPadEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPadEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemPadEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPadEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemPadEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPadEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemPromiscuousMode in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPromiscuousMode 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemPromiscuousMode in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPromiscuousMode u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemPromiscuousMode in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPromiscuousMode u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemWanMode in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemWanMode 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemWanMode in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemWanMode u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemWanMode in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemWanMode u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemRxEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemRxEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemRxEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxLowPowerIdleEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxLowPowerIdleEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxLowPowerIdleEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxLowPowerIdleEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxLowPowerIdleEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxLowPowerIdleEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemSfdCheckDisable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemSfdCheckDisable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemSfdCheckDisable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemSfdCheckDisable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemSfdCheckDisable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemSfdCheckDisable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemPriorityFlowControlEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPriorityFlowControlEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemPriorityFlowControlEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPriorityFlowControlEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemPriorityFlowControlEnable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPriorityFlowControlEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemIdleColumnCountExtend in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemIdleColumnCountExtend 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemIdleColumnCountExtend in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemIdleColumnCountExtend u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemIdleColumnCountExtend in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemIdleColumnCountExtend u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemLengthCheckDisable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemLengthCheckDisable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemLengthCheckDisable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemLengthCheckDisable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemLengthCheckDisable in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemLengthCheckDisable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemForceSendIdle in AQ_MsmSystemGeneralControlRegister_HHD */ +#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemForceSendIdle 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemForceSendIdle in AQ_MsmSystemGeneralControlRegister_HHD */ +#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemForceSendIdle u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemForceSendIdle in AQ_MsmSystemGeneralControlRegister_HHD */ +#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemForceSendIdle u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemFifoControlRegister_HHD */ +#define AQ_MsmSystemFifoControlRegister_HHD_baseRegisterAddress 0x600E +/*! \brief MMD address of structure AQ_MsmSystemFifoControlRegister_HHD */ +#define AQ_MsmSystemFifoControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxFifoFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoFullThreshold 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxFifoFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define bits_AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoFullThreshold u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxFifoFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define word_AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoFullThreshold u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxFifoEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoEmptyThreshold 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxFifoEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define bits_AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoEmptyThreshold u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxFifoEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define word_AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoEmptyThreshold u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxFifoFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoFullThreshold 2 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxFifoFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define bits_AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoFullThreshold u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxFifoFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define word_AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoFullThreshold u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxFifoEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoEmptyThreshold 3 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxFifoEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define bits_AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoEmptyThreshold u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxFifoEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define word_AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoEmptyThreshold u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxFifoAlmostFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoAlmostFullThreshold 4 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxFifoAlmostFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define bits_AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoAlmostFullThreshold u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxFifoAlmostFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define word_AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoAlmostFullThreshold u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxFifoAlmostEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoAlmostEmptyThreshold 5 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxFifoAlmostEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define bits_AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoAlmostEmptyThreshold u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxFifoAlmostEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define word_AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoAlmostEmptyThreshold u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxFifoAlmostFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoAlmostFullThreshold 6 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxFifoAlmostFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define bits_AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoAlmostFullThreshold u6.bits_6 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxFifoAlmostFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define word_AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoAlmostFullThreshold u6.word_6 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxFifoAlmostEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoAlmostEmptyThreshold 7 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxFifoAlmostEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define bits_AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoAlmostEmptyThreshold u7.bits_7 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxFifoAlmostEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ +#define word_AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoAlmostEmptyThreshold u7.word_7 + +/*! \brief Base register address of structure AQ_MsmSystemGeneralStatusRegister_HHD */ +#define AQ_MsmSystemGeneralStatusRegister_HHD_baseRegisterAddress 0x6020 +/*! \brief MMD address of structure AQ_MsmSystemGeneralStatusRegister_HHD */ +#define AQ_MsmSystemGeneralStatusRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxFifoEmpty in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemTxFifoEmpty 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxFifoEmpty in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define bits_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemTxFifoEmpty u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxFifoEmpty in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define word_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemTxFifoEmpty u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxLowPowerIdle in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemRxLowPowerIdle 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxLowPowerIdle in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define bits_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemRxLowPowerIdle u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxLowPowerIdle in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define word_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemRxLowPowerIdle u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTimestampAvailable in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemTimestampAvailable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTimestampAvailable in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define bits_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemTimestampAvailable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTimestampAvailable in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define word_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemTimestampAvailable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemPhyLossOfSignal in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemPhyLossOfSignal 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemPhyLossOfSignal in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define bits_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemPhyLossOfSignal u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemPhyLossOfSignal in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define word_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemPhyLossOfSignal u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxRemoteFault in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemRxRemoteFault 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxRemoteFault in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define bits_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemRxRemoteFault u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxRemoteFault in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define word_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemRxRemoteFault u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxLocalFault in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemRxLocalFault 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxLocalFault in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define bits_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemRxLocalFault u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxLocalFault in AQ_MsmSystemGeneralStatusRegister_HHD */ +#define word_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemRxLocalFault u0.word_0 + +/*! \brief Base register address of structure AQ_MsmSystemTxIpgControlRegister_HHD */ +#define AQ_MsmSystemTxIpgControlRegister_HHD_baseRegisterAddress 0x6022 +/*! \brief MMD address of structure AQ_MsmSystemTxIpgControlRegister_HHD */ +#define AQ_MsmSystemTxIpgControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxIpgLength in AQ_MsmSystemTxIpgControlRegister_HHD */ +#define AQ_MsmSystemTxIpgControlRegister_HHD_msmSystemTxIpgLength 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxIpgLength in AQ_MsmSystemTxIpgControlRegister_HHD */ +#define bits_AQ_MsmSystemTxIpgControlRegister_HHD_msmSystemTxIpgLength u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxIpgLength in AQ_MsmSystemTxIpgControlRegister_HHD */ +#define word_AQ_MsmSystemTxIpgControlRegister_HHD_msmSystemTxIpgLength u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxIpgReserved in AQ_MsmSystemTxIpgControlRegister_HHD */ +#define AQ_MsmSystemTxIpgControlRegister_HHD_msmSystemTxIpgReserved 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxIpgReserved in AQ_MsmSystemTxIpgControlRegister_HHD */ +#define bits_AQ_MsmSystemTxIpgControlRegister_HHD_msmSystemTxIpgReserved u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxIpgReserved in AQ_MsmSystemTxIpgControlRegister_HHD */ +#define word_AQ_MsmSystemTxIpgControlRegister_HHD_msmSystemTxIpgReserved u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemTxGoodFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxGoodFramesCounterRegister_HHD_baseRegisterAddress 0x6040 +/*! \brief MMD address of structure AQ_MsmSystemTxGoodFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxGoodFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxGoodFramesCounter_0 in AQ_MsmSystemTxGoodFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxGoodFramesCounterRegister_HHD_msmSystemTxGoodFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxGoodFramesCounter_0 in AQ_MsmSystemTxGoodFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxGoodFramesCounterRegister_HHD_msmSystemTxGoodFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxGoodFramesCounter_0 in AQ_MsmSystemTxGoodFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemTxGoodFramesCounterRegister_HHD_msmSystemTxGoodFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxGoodFramesCounter_1 in AQ_MsmSystemTxGoodFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxGoodFramesCounterRegister_HHD_msmSystemTxGoodFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxGoodFramesCounter_1 in AQ_MsmSystemTxGoodFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxGoodFramesCounterRegister_HHD_msmSystemTxGoodFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxGoodFramesCounter_1 in AQ_MsmSystemTxGoodFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemTxGoodFramesCounterRegister_HHD_msmSystemTxGoodFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemRxGoodFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxGoodFramesCounterRegister_HHD_baseRegisterAddress 0x6044 +/*! \brief MMD address of structure AQ_MsmSystemRxGoodFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxGoodFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxGoodFramesCounter_0 in AQ_MsmSystemRxGoodFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxGoodFramesCounterRegister_HHD_msmSystemRxGoodFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxGoodFramesCounter_0 in AQ_MsmSystemRxGoodFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxGoodFramesCounterRegister_HHD_msmSystemRxGoodFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxGoodFramesCounter_0 in AQ_MsmSystemRxGoodFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemRxGoodFramesCounterRegister_HHD_msmSystemRxGoodFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxGoodFramesCounter_1 in AQ_MsmSystemRxGoodFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxGoodFramesCounterRegister_HHD_msmSystemRxGoodFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxGoodFramesCounter_1 in AQ_MsmSystemRxGoodFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxGoodFramesCounterRegister_HHD_msmSystemRxGoodFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxGoodFramesCounter_1 in AQ_MsmSystemRxGoodFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemRxGoodFramesCounterRegister_HHD_msmSystemRxGoodFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemRxFcsErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxFcsErrorsCounterRegister_HHD_baseRegisterAddress 0x6048 +/*! \brief MMD address of structure AQ_MsmSystemRxFcsErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxFcsErrorsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemFcsErrorCounter_0 in AQ_MsmSystemRxFcsErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxFcsErrorsCounterRegister_HHD_msmSystemFcsErrorCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemFcsErrorCounter_0 in AQ_MsmSystemRxFcsErrorsCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxFcsErrorsCounterRegister_HHD_msmSystemFcsErrorCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemFcsErrorCounter_0 in AQ_MsmSystemRxFcsErrorsCounterRegister_HHD */ +#define word_AQ_MsmSystemRxFcsErrorsCounterRegister_HHD_msmSystemFcsErrorCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemFcsErrorCounter_1 in AQ_MsmSystemRxFcsErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxFcsErrorsCounterRegister_HHD_msmSystemFcsErrorCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemFcsErrorCounter_1 in AQ_MsmSystemRxFcsErrorsCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxFcsErrorsCounterRegister_HHD_msmSystemFcsErrorCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemFcsErrorCounter_1 in AQ_MsmSystemRxFcsErrorsCounterRegister_HHD */ +#define word_AQ_MsmSystemRxFcsErrorsCounterRegister_HHD_msmSystemFcsErrorCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD_baseRegisterAddress 0x604C +/*! \brief MMD address of structure AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemAlignmentErrorCounter_0 in AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD_msmSystemAlignmentErrorCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemAlignmentErrorCounter_0 in AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD_msmSystemAlignmentErrorCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemAlignmentErrorCounter_0 in AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD */ +#define word_AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD_msmSystemAlignmentErrorCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemAlignmentErrorCounter_1 in AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD_msmSystemAlignmentErrorCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemAlignmentErrorCounter_1 in AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD_msmSystemAlignmentErrorCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemAlignmentErrorCounter_1 in AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD */ +#define word_AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD_msmSystemAlignmentErrorCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemTxPauseFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxPauseFramesCounterRegister_HHD_baseRegisterAddress 0x6050 +/*! \brief MMD address of structure AQ_MsmSystemTxPauseFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxPauseFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxPauseFramesCounter_0 in AQ_MsmSystemTxPauseFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxPauseFramesCounterRegister_HHD_msmSystemTxPauseFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxPauseFramesCounter_0 in AQ_MsmSystemTxPauseFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxPauseFramesCounterRegister_HHD_msmSystemTxPauseFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxPauseFramesCounter_0 in AQ_MsmSystemTxPauseFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemTxPauseFramesCounterRegister_HHD_msmSystemTxPauseFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxPauseFramesCounter_1 in AQ_MsmSystemTxPauseFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxPauseFramesCounterRegister_HHD_msmSystemTxPauseFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxPauseFramesCounter_1 in AQ_MsmSystemTxPauseFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxPauseFramesCounterRegister_HHD_msmSystemTxPauseFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxPauseFramesCounter_1 in AQ_MsmSystemTxPauseFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemTxPauseFramesCounterRegister_HHD_msmSystemTxPauseFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemRxPauseFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxPauseFramesCounterRegister_HHD_baseRegisterAddress 0x6054 +/*! \brief MMD address of structure AQ_MsmSystemRxPauseFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxPauseFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxPauseFramesCounter_0 in AQ_MsmSystemRxPauseFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxPauseFramesCounterRegister_HHD_msmSystemRxPauseFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxPauseFramesCounter_0 in AQ_MsmSystemRxPauseFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxPauseFramesCounterRegister_HHD_msmSystemRxPauseFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxPauseFramesCounter_0 in AQ_MsmSystemRxPauseFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemRxPauseFramesCounterRegister_HHD_msmSystemRxPauseFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxPauseFramesCounter_1 in AQ_MsmSystemRxPauseFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxPauseFramesCounterRegister_HHD_msmSystemRxPauseFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxPauseFramesCounter_1 in AQ_MsmSystemRxPauseFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxPauseFramesCounterRegister_HHD_msmSystemRxPauseFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxPauseFramesCounter_1 in AQ_MsmSystemRxPauseFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemRxPauseFramesCounterRegister_HHD_msmSystemRxPauseFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD_baseRegisterAddress 0x6058 +/*! \brief MMD address of structure AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxTooLongErrorsCounter_0 in AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD_msmSystemRxTooLongErrorsCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxTooLongErrorsCounter_0 in AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD_msmSystemRxTooLongErrorsCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxTooLongErrorsCounter_0 in AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD */ +#define word_AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD_msmSystemRxTooLongErrorsCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxTooLongErrorsCounter_1 in AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD_msmSystemRxTooLongErrorsCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxTooLongErrorsCounter_1 in AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD_msmSystemRxTooLongErrorsCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxTooLongErrorsCounter_1 in AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD */ +#define word_AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD_msmSystemRxTooLongErrorsCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD_baseRegisterAddress 0x605C +/*! \brief MMD address of structure AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxInRangeLengthErrorsCounter_0 in AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD_msmSystemRxInRangeLengthErrorsCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxInRangeLengthErrorsCounter_0 in AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD_msmSystemRxInRangeLengthErrorsCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxInRangeLengthErrorsCounter_0 in AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD */ +#define word_AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD_msmSystemRxInRangeLengthErrorsCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxInRangeLengthErrorsCounter_1 in AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD_msmSystemRxInRangeLengthErrorsCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxInRangeLengthErrorsCounter_1 in AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD_msmSystemRxInRangeLengthErrorsCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxInRangeLengthErrorsCounter_1 in AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD */ +#define word_AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD_msmSystemRxInRangeLengthErrorsCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemTxVlanFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxVlanFramesCounterRegister_HHD_baseRegisterAddress 0x6060 +/*! \brief MMD address of structure AQ_MsmSystemTxVlanFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxVlanFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxVlanFramesCounter_0 in AQ_MsmSystemTxVlanFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxVlanFramesCounterRegister_HHD_msmSystemTxVlanFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxVlanFramesCounter_0 in AQ_MsmSystemTxVlanFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxVlanFramesCounterRegister_HHD_msmSystemTxVlanFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxVlanFramesCounter_0 in AQ_MsmSystemTxVlanFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemTxVlanFramesCounterRegister_HHD_msmSystemTxVlanFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxVlanFramesCounter_1 in AQ_MsmSystemTxVlanFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxVlanFramesCounterRegister_HHD_msmSystemTxVlanFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxVlanFramesCounter_1 in AQ_MsmSystemTxVlanFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxVlanFramesCounterRegister_HHD_msmSystemTxVlanFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxVlanFramesCounter_1 in AQ_MsmSystemTxVlanFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemTxVlanFramesCounterRegister_HHD_msmSystemTxVlanFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemRxVlanFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxVlanFramesCounterRegister_HHD_baseRegisterAddress 0x6064 +/*! \brief MMD address of structure AQ_MsmSystemRxVlanFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxVlanFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxVlanFramesCounter_0 in AQ_MsmSystemRxVlanFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxVlanFramesCounterRegister_HHD_msmSystemRxVlanFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxVlanFramesCounter_0 in AQ_MsmSystemRxVlanFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxVlanFramesCounterRegister_HHD_msmSystemRxVlanFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxVlanFramesCounter_0 in AQ_MsmSystemRxVlanFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemRxVlanFramesCounterRegister_HHD_msmSystemRxVlanFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxVlanFramesCounter_1 in AQ_MsmSystemRxVlanFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxVlanFramesCounterRegister_HHD_msmSystemRxVlanFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxVlanFramesCounter_1 in AQ_MsmSystemRxVlanFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxVlanFramesCounterRegister_HHD_msmSystemRxVlanFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxVlanFramesCounter_1 in AQ_MsmSystemRxVlanFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemRxVlanFramesCounterRegister_HHD_msmSystemRxVlanFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemTxOctetsCounterRegister_HHD */ +#define AQ_MsmSystemTxOctetsCounterRegister_HHD_baseRegisterAddress 0x6068 +/*! \brief MMD address of structure AQ_MsmSystemTxOctetsCounterRegister_HHD */ +#define AQ_MsmSystemTxOctetsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxOctetsCounter_0 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ +#define AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxOctetsCounter_0 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxOctetsCounter_0 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ +#define word_AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxOctetsCounter_1 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ +#define AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxOctetsCounter_1 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxOctetsCounter_1 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ +#define word_AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_1 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxOctetsCounter_2 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ +#define AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_2 2 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxOctetsCounter_2 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_2 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxOctetsCounter_2 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ +#define word_AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_2 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxOctetsCounter_3 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ +#define AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_3 3 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxOctetsCounter_3 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_3 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxOctetsCounter_3 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ +#define word_AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_3 u3.word_3 + +/*! \brief Base register address of structure AQ_MsmSystemRxOctetsCounterRegister_HHD */ +#define AQ_MsmSystemRxOctetsCounterRegister_HHD_baseRegisterAddress 0x606C +/*! \brief MMD address of structure AQ_MsmSystemRxOctetsCounterRegister_HHD */ +#define AQ_MsmSystemRxOctetsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxOctetsCounter_0 in AQ_MsmSystemRxOctetsCounterRegister_HHD */ +#define AQ_MsmSystemRxOctetsCounterRegister_HHD_msmSystemRxOctetsCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxOctetsCounter_0 in AQ_MsmSystemRxOctetsCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxOctetsCounterRegister_HHD_msmSystemRxOctetsCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxOctetsCounter_0 in AQ_MsmSystemRxOctetsCounterRegister_HHD */ +#define word_AQ_MsmSystemRxOctetsCounterRegister_HHD_msmSystemRxOctetsCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxOctetsCounter_1 in AQ_MsmSystemRxOctetsCounterRegister_HHD */ +#define AQ_MsmSystemRxOctetsCounterRegister_HHD_msmSystemRxOctetsCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxOctetsCounter_1 in AQ_MsmSystemRxOctetsCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxOctetsCounterRegister_HHD_msmSystemRxOctetsCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxOctetsCounter_1 in AQ_MsmSystemRxOctetsCounterRegister_HHD */ +#define word_AQ_MsmSystemRxOctetsCounterRegister_HHD_msmSystemRxOctetsCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemRxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxUnicastFramesCounterRegister_HHD_baseRegisterAddress 0x6070 +/*! \brief MMD address of structure AQ_MsmSystemRxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxUnicastFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxUnicastFramesCounter_0 in AQ_MsmSystemRxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxUnicastFramesCounterRegister_HHD_msmSystemRxUnicastFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxUnicastFramesCounter_0 in AQ_MsmSystemRxUnicastFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxUnicastFramesCounterRegister_HHD_msmSystemRxUnicastFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxUnicastFramesCounter_0 in AQ_MsmSystemRxUnicastFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemRxUnicastFramesCounterRegister_HHD_msmSystemRxUnicastFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxUnicastFramesCounter_1 in AQ_MsmSystemRxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxUnicastFramesCounterRegister_HHD_msmSystemRxUnicastFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxUnicastFramesCounter_1 in AQ_MsmSystemRxUnicastFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxUnicastFramesCounterRegister_HHD_msmSystemRxUnicastFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxUnicastFramesCounter_1 in AQ_MsmSystemRxUnicastFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemRxUnicastFramesCounterRegister_HHD_msmSystemRxUnicastFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemRxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxMulticastFramesCounterRegister_HHD_baseRegisterAddress 0x6074 +/*! \brief MMD address of structure AQ_MsmSystemRxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxMulticastFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxMulticastFramesCounter_0 in AQ_MsmSystemRxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxMulticastFramesCounterRegister_HHD_msmSystemRxMulticastFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxMulticastFramesCounter_0 in AQ_MsmSystemRxMulticastFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxMulticastFramesCounterRegister_HHD_msmSystemRxMulticastFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxMulticastFramesCounter_0 in AQ_MsmSystemRxMulticastFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemRxMulticastFramesCounterRegister_HHD_msmSystemRxMulticastFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxMulticastFramesCounter_1 in AQ_MsmSystemRxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxMulticastFramesCounterRegister_HHD_msmSystemRxMulticastFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxMulticastFramesCounter_1 in AQ_MsmSystemRxMulticastFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxMulticastFramesCounterRegister_HHD_msmSystemRxMulticastFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxMulticastFramesCounter_1 in AQ_MsmSystemRxMulticastFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemRxMulticastFramesCounterRegister_HHD_msmSystemRxMulticastFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD_baseRegisterAddress 0x6078 +/*! \brief MMD address of structure AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxBroadcastFramesCounter_0 in AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD_msmSystemRxBroadcastFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxBroadcastFramesCounter_0 in AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD_msmSystemRxBroadcastFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxBroadcastFramesCounter_0 in AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD_msmSystemRxBroadcastFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxBroadcastFramesCounter_1 in AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD_msmSystemRxBroadcastFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxBroadcastFramesCounter_1 in AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD_msmSystemRxBroadcastFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxBroadcastFramesCounter_1 in AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD_msmSystemRxBroadcastFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemTxErrorsCounterRegister_HHD */ +#define AQ_MsmSystemTxErrorsCounterRegister_HHD_baseRegisterAddress 0x607C +/*! \brief MMD address of structure AQ_MsmSystemTxErrorsCounterRegister_HHD */ +#define AQ_MsmSystemTxErrorsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxErrorsCounter_0 in AQ_MsmSystemTxErrorsCounterRegister_HHD */ +#define AQ_MsmSystemTxErrorsCounterRegister_HHD_msmSystemTxErrorsCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxErrorsCounter_0 in AQ_MsmSystemTxErrorsCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxErrorsCounterRegister_HHD_msmSystemTxErrorsCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxErrorsCounter_0 in AQ_MsmSystemTxErrorsCounterRegister_HHD */ +#define word_AQ_MsmSystemTxErrorsCounterRegister_HHD_msmSystemTxErrorsCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxErrorsCounter_1 in AQ_MsmSystemTxErrorsCounterRegister_HHD */ +#define AQ_MsmSystemTxErrorsCounterRegister_HHD_msmSystemTxErrorsCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxErrorsCounter_1 in AQ_MsmSystemTxErrorsCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxErrorsCounterRegister_HHD_msmSystemTxErrorsCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxErrorsCounter_1 in AQ_MsmSystemTxErrorsCounterRegister_HHD */ +#define word_AQ_MsmSystemTxErrorsCounterRegister_HHD_msmSystemTxErrorsCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemTxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxUnicastFramesCounterRegister_HHD_baseRegisterAddress 0x6084 +/*! \brief MMD address of structure AQ_MsmSystemTxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxUnicastFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxUnicastFramesCounter_0 in AQ_MsmSystemTxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxUnicastFramesCounterRegister_HHD_msmSystemTxUnicastFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxUnicastFramesCounter_0 in AQ_MsmSystemTxUnicastFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxUnicastFramesCounterRegister_HHD_msmSystemTxUnicastFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxUnicastFramesCounter_0 in AQ_MsmSystemTxUnicastFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemTxUnicastFramesCounterRegister_HHD_msmSystemTxUnicastFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxUnicastFramesCounter_1 in AQ_MsmSystemTxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxUnicastFramesCounterRegister_HHD_msmSystemTxUnicastFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxUnicastFramesCounter_1 in AQ_MsmSystemTxUnicastFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxUnicastFramesCounterRegister_HHD_msmSystemTxUnicastFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxUnicastFramesCounter_1 in AQ_MsmSystemTxUnicastFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemTxUnicastFramesCounterRegister_HHD_msmSystemTxUnicastFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemTxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxMulticastFramesCounterRegister_HHD_baseRegisterAddress 0x6088 +/*! \brief MMD address of structure AQ_MsmSystemTxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxMulticastFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxMulticastFramesCounter_0 in AQ_MsmSystemTxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxMulticastFramesCounterRegister_HHD_msmSystemTxMulticastFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxMulticastFramesCounter_0 in AQ_MsmSystemTxMulticastFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxMulticastFramesCounterRegister_HHD_msmSystemTxMulticastFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxMulticastFramesCounter_0 in AQ_MsmSystemTxMulticastFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemTxMulticastFramesCounterRegister_HHD_msmSystemTxMulticastFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxMulticastFramesCounter_1 in AQ_MsmSystemTxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxMulticastFramesCounterRegister_HHD_msmSystemTxMulticastFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxMulticastFramesCounter_1 in AQ_MsmSystemTxMulticastFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxMulticastFramesCounterRegister_HHD_msmSystemTxMulticastFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxMulticastFramesCounter_1 in AQ_MsmSystemTxMulticastFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemTxMulticastFramesCounterRegister_HHD_msmSystemTxMulticastFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD_baseRegisterAddress 0x608C +/*! \brief MMD address of structure AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxBroadcastFramesCounter_0 in AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD_msmSystemTxBroadcastFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxBroadcastFramesCounter_0 in AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD_msmSystemTxBroadcastFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxBroadcastFramesCounter_0 in AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD_msmSystemTxBroadcastFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxBroadcastFramesCounter_1 in AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD_msmSystemTxBroadcastFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxBroadcastFramesCounter_1 in AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD */ +#define bits_AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD_msmSystemTxBroadcastFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxBroadcastFramesCounter_1 in AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD */ +#define word_AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD_msmSystemTxBroadcastFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmSystemRxErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxErrorsCounterRegister_HHD_baseRegisterAddress 0x60C8 +/*! \brief MMD address of structure AQ_MsmSystemRxErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxErrorsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxErrorsCounter_0 in AQ_MsmSystemRxErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxErrorsCounterRegister_HHD_msmSystemRxErrorsCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxErrorsCounter_0 in AQ_MsmSystemRxErrorsCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxErrorsCounterRegister_HHD_msmSystemRxErrorsCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxErrorsCounter_0 in AQ_MsmSystemRxErrorsCounterRegister_HHD */ +#define word_AQ_MsmSystemRxErrorsCounterRegister_HHD_msmSystemRxErrorsCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxErrorsCounter_1 in AQ_MsmSystemRxErrorsCounterRegister_HHD */ +#define AQ_MsmSystemRxErrorsCounterRegister_HHD_msmSystemRxErrorsCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxErrorsCounter_1 in AQ_MsmSystemRxErrorsCounterRegister_HHD */ +#define bits_AQ_MsmSystemRxErrorsCounterRegister_HHD_msmSystemRxErrorsCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxErrorsCounter_1 in AQ_MsmSystemRxErrorsCounterRegister_HHD */ +#define word_AQ_MsmSystemRxErrorsCounterRegister_HHD_msmSystemRxErrorsCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MssIngressVlanTpid_0Register_HHD */ +#define AQ_MssIngressVlanTpid_0Register_HHD_baseRegisterAddress 0x8006 +/*! \brief MMD address of structure AQ_MssIngressVlanTpid_0Register_HHD */ +#define AQ_MssIngressVlanTpid_0Register_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressVlanStag in AQ_MssIngressVlanTpid_0Register_HHD */ +#define AQ_MssIngressVlanTpid_0Register_HHD_mssIngressVlanStag 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressVlanStag in AQ_MssIngressVlanTpid_0Register_HHD */ +#define bits_AQ_MssIngressVlanTpid_0Register_HHD_mssIngressVlanStag u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressVlanStag in AQ_MssIngressVlanTpid_0Register_HHD */ +#define word_AQ_MssIngressVlanTpid_0Register_HHD_mssIngressVlanStag u0.word_0 + +/*! \brief Base register address of structure AQ_MssIngressVlanTpid_1Register_HHD */ +#define AQ_MssIngressVlanTpid_1Register_HHD_baseRegisterAddress 0x8008 +/*! \brief MMD address of structure AQ_MssIngressVlanTpid_1Register_HHD */ +#define AQ_MssIngressVlanTpid_1Register_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressVlanQtag in AQ_MssIngressVlanTpid_1Register_HHD */ +#define AQ_MssIngressVlanTpid_1Register_HHD_mssIngressVlanQtag 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressVlanQtag in AQ_MssIngressVlanTpid_1Register_HHD */ +#define bits_AQ_MssIngressVlanTpid_1Register_HHD_mssIngressVlanQtag u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressVlanQtag in AQ_MssIngressVlanTpid_1Register_HHD */ +#define word_AQ_MssIngressVlanTpid_1Register_HHD_mssIngressVlanQtag u0.word_0 + +/*! \brief Base register address of structure AQ_MssIngressVlanControlRegister_HHD */ +#define AQ_MssIngressVlanControlRegister_HHD_baseRegisterAddress 0x800A +/*! \brief MMD address of structure AQ_MssIngressVlanControlRegister_HHD */ +#define AQ_MssIngressVlanControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressVlanUpMapTableLSW in AQ_MssIngressVlanControlRegister_HHD */ +#define AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanUpMapTableLSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressVlanUpMapTableLSW in AQ_MssIngressVlanControlRegister_HHD */ +#define bits_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanUpMapTableLSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressVlanUpMapTableLSW in AQ_MssIngressVlanControlRegister_HHD */ +#define word_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanUpMapTableLSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressVlanQtagParseEnable in AQ_MssIngressVlanControlRegister_HHD */ +#define AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanQtagParseEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressVlanQtagParseEnable in AQ_MssIngressVlanControlRegister_HHD */ +#define bits_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanQtagParseEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressVlanQtagParseEnable in AQ_MssIngressVlanControlRegister_HHD */ +#define word_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanQtagParseEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressVlanStagParseEnable in AQ_MssIngressVlanControlRegister_HHD */ +#define AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanStagParseEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressVlanStagParseEnable in AQ_MssIngressVlanControlRegister_HHD */ +#define bits_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanStagParseEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressVlanStagParseEnable in AQ_MssIngressVlanControlRegister_HHD */ +#define word_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanStagParseEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressVlanQinqParseEnable in AQ_MssIngressVlanControlRegister_HHD */ +#define AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanQinqParseEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressVlanQinqParseEnable in AQ_MssIngressVlanControlRegister_HHD */ +#define bits_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanQinqParseEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressVlanQinqParseEnable in AQ_MssIngressVlanControlRegister_HHD */ +#define word_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanQinqParseEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressVlanQtagUpParseEnable in AQ_MssIngressVlanControlRegister_HHD */ +#define AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanQtagUpParseEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressVlanQtagUpParseEnable in AQ_MssIngressVlanControlRegister_HHD */ +#define bits_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanQtagUpParseEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressVlanQtagUpParseEnable in AQ_MssIngressVlanControlRegister_HHD */ +#define word_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanQtagUpParseEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressVlanStagUpParseEnable in AQ_MssIngressVlanControlRegister_HHD */ +#define AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanStagUpParseEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressVlanStagUpParseEnable in AQ_MssIngressVlanControlRegister_HHD */ +#define bits_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanStagUpParseEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressVlanStagUpParseEnable in AQ_MssIngressVlanControlRegister_HHD */ +#define word_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanStagUpParseEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressVlanUpDefault in AQ_MssIngressVlanControlRegister_HHD */ +#define AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanUpDefault 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressVlanUpDefault in AQ_MssIngressVlanControlRegister_HHD */ +#define bits_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanUpDefault u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressVlanUpDefault in AQ_MssIngressVlanControlRegister_HHD */ +#define word_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanUpDefault u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressVlanUpMapTableMSW in AQ_MssIngressVlanControlRegister_HHD */ +#define AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanUpMapTableMSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressVlanUpMapTableMSW in AQ_MssIngressVlanControlRegister_HHD */ +#define bits_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanUpMapTableMSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressVlanUpMapTableMSW in AQ_MssIngressVlanControlRegister_HHD */ +#define word_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanUpMapTableMSW u1.word_1 + +/*! \brief Base register address of structure AQ_MssIngressMtuSizeControlRegister_HHD */ +#define AQ_MssIngressMtuSizeControlRegister_HHD_baseRegisterAddress 0x800C +/*! \brief MMD address of structure AQ_MssIngressMtuSizeControlRegister_HHD */ +#define AQ_MssIngressMtuSizeControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressControlledPacketMtuSize in AQ_MssIngressMtuSizeControlRegister_HHD */ +#define AQ_MssIngressMtuSizeControlRegister_HHD_mssIngressControlledPacketMtuSize 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressControlledPacketMtuSize in AQ_MssIngressMtuSizeControlRegister_HHD */ +#define bits_AQ_MssIngressMtuSizeControlRegister_HHD_mssIngressControlledPacketMtuSize u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressControlledPacketMtuSize in AQ_MssIngressMtuSizeControlRegister_HHD */ +#define word_AQ_MssIngressMtuSizeControlRegister_HHD_mssIngressControlledPacketMtuSize u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressUncontrolledPacketMtuSize in AQ_MssIngressMtuSizeControlRegister_HHD */ +#define AQ_MssIngressMtuSizeControlRegister_HHD_mssIngressUncontrolledPacketMtuSize 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressUncontrolledPacketMtuSize in AQ_MssIngressMtuSizeControlRegister_HHD */ +#define bits_AQ_MssIngressMtuSizeControlRegister_HHD_mssIngressUncontrolledPacketMtuSize u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressUncontrolledPacketMtuSize in AQ_MssIngressMtuSizeControlRegister_HHD */ +#define word_AQ_MssIngressMtuSizeControlRegister_HHD_mssIngressUncontrolledPacketMtuSize u1.word_1 + +/*! \brief Base register address of structure AQ_MssIngressControlRegister_HHD */ +#define AQ_MssIngressControlRegister_HHD_baseRegisterAddress 0x800E +/*! \brief MMD address of structure AQ_MssIngressControlRegister_HHD */ +#define AQ_MssIngressControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressIcvLsb_8BytesEnable in AQ_MssIngressControlRegister_HHD */ +#define AQ_MssIngressControlRegister_HHD_mssIngressIcvLsb_8BytesEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressIcvLsb_8BytesEnable in AQ_MssIngressControlRegister_HHD */ +#define bits_AQ_MssIngressControlRegister_HHD_mssIngressIcvLsb_8BytesEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressIcvLsb_8BytesEnable in AQ_MssIngressControlRegister_HHD */ +#define word_AQ_MssIngressControlRegister_HHD_mssIngressIcvLsb_8BytesEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressGlobalValidateFrames in AQ_MssIngressControlRegister_HHD */ +#define AQ_MssIngressControlRegister_HHD_mssIngressGlobalValidateFrames 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressGlobalValidateFrames in AQ_MssIngressControlRegister_HHD */ +#define bits_AQ_MssIngressControlRegister_HHD_mssIngressGlobalValidateFrames u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressGlobalValidateFrames in AQ_MssIngressControlRegister_HHD */ +#define word_AQ_MssIngressControlRegister_HHD_mssIngressGlobalValidateFrames u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressRemoveSectag in AQ_MssIngressControlRegister_HHD */ +#define AQ_MssIngressControlRegister_HHD_mssIngressRemoveSectag 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressRemoveSectag in AQ_MssIngressControlRegister_HHD */ +#define bits_AQ_MssIngressControlRegister_HHD_mssIngressRemoveSectag u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressRemoveSectag in AQ_MssIngressControlRegister_HHD */ +#define word_AQ_MssIngressControlRegister_HHD_mssIngressRemoveSectag u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressHighPriority in AQ_MssIngressControlRegister_HHD */ +#define AQ_MssIngressControlRegister_HHD_mssIngressHighPriority 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressHighPriority in AQ_MssIngressControlRegister_HHD */ +#define bits_AQ_MssIngressControlRegister_HHD_mssIngressHighPriority u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressHighPriority in AQ_MssIngressControlRegister_HHD */ +#define word_AQ_MssIngressControlRegister_HHD_mssIngressHighPriority u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressClearCount in AQ_MssIngressControlRegister_HHD */ +#define AQ_MssIngressControlRegister_HHD_mssIngressClearCount 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressClearCount in AQ_MssIngressControlRegister_HHD */ +#define bits_AQ_MssIngressControlRegister_HHD_mssIngressClearCount u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressClearCount in AQ_MssIngressControlRegister_HHD */ +#define word_AQ_MssIngressControlRegister_HHD_mssIngressClearCount u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressClearGlobalTime in AQ_MssIngressControlRegister_HHD */ +#define AQ_MssIngressControlRegister_HHD_mssIngressClearGlobalTime 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressClearGlobalTime in AQ_MssIngressControlRegister_HHD */ +#define bits_AQ_MssIngressControlRegister_HHD_mssIngressClearGlobalTime u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressClearGlobalTime in AQ_MssIngressControlRegister_HHD */ +#define word_AQ_MssIngressControlRegister_HHD_mssIngressClearGlobalTime u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressCheckIcv in AQ_MssIngressControlRegister_HHD */ +#define AQ_MssIngressControlRegister_HHD_mssIngressCheckIcv 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressCheckIcv in AQ_MssIngressControlRegister_HHD */ +#define bits_AQ_MssIngressControlRegister_HHD_mssIngressCheckIcv u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressCheckIcv in AQ_MssIngressControlRegister_HHD */ +#define word_AQ_MssIngressControlRegister_HHD_mssIngressCheckIcv u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressDropIgprcMiss in AQ_MssIngressControlRegister_HHD */ +#define AQ_MssIngressControlRegister_HHD_mssIngressDropIgprcMiss 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressDropIgprcMiss in AQ_MssIngressControlRegister_HHD */ +#define bits_AQ_MssIngressControlRegister_HHD_mssIngressDropIgprcMiss u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressDropIgprcMiss in AQ_MssIngressControlRegister_HHD */ +#define word_AQ_MssIngressControlRegister_HHD_mssIngressDropIgprcMiss u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressDropKayPacket in AQ_MssIngressControlRegister_HHD */ +#define AQ_MssIngressControlRegister_HHD_mssIngressDropKayPacket 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressDropKayPacket in AQ_MssIngressControlRegister_HHD */ +#define bits_AQ_MssIngressControlRegister_HHD_mssIngressDropKayPacket u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressDropKayPacket in AQ_MssIngressControlRegister_HHD */ +#define word_AQ_MssIngressControlRegister_HHD_mssIngressDropKayPacket u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressMaskShortLengthError in AQ_MssIngressControlRegister_HHD */ +#define AQ_MssIngressControlRegister_HHD_mssIngressMaskShortLengthError 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressMaskShortLengthError in AQ_MssIngressControlRegister_HHD */ +#define bits_AQ_MssIngressControlRegister_HHD_mssIngressMaskShortLengthError u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressMaskShortLengthError in AQ_MssIngressControlRegister_HHD */ +#define word_AQ_MssIngressControlRegister_HHD_mssIngressMaskShortLengthError u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressCreateSci in AQ_MssIngressControlRegister_HHD */ +#define AQ_MssIngressControlRegister_HHD_mssIngressCreateSci 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressCreateSci in AQ_MssIngressControlRegister_HHD */ +#define bits_AQ_MssIngressControlRegister_HHD_mssIngressCreateSci u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressCreateSci in AQ_MssIngressControlRegister_HHD */ +#define word_AQ_MssIngressControlRegister_HHD_mssIngressCreateSci u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressOperationPointToPoint in AQ_MssIngressControlRegister_HHD */ +#define AQ_MssIngressControlRegister_HHD_mssIngressOperationPointToPoint 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressOperationPointToPoint in AQ_MssIngressControlRegister_HHD */ +#define bits_AQ_MssIngressControlRegister_HHD_mssIngressOperationPointToPoint u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressOperationPointToPoint in AQ_MssIngressControlRegister_HHD */ +#define word_AQ_MssIngressControlRegister_HHD_mssIngressOperationPointToPoint u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSoftReset in AQ_MssIngressControlRegister_HHD */ +#define AQ_MssIngressControlRegister_HHD_mssIngressSoftReset 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSoftReset in AQ_MssIngressControlRegister_HHD */ +#define bits_AQ_MssIngressControlRegister_HHD_mssIngressSoftReset u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSoftReset in AQ_MssIngressControlRegister_HHD */ +#define word_AQ_MssIngressControlRegister_HHD_mssIngressSoftReset u0.word_0 + +/*! \brief Base register address of structure AQ_MssIngressSaControlRegister_HHD */ +#define AQ_MssIngressSaControlRegister_HHD_baseRegisterAddress 0x8010 +/*! \brief MMD address of structure AQ_MssIngressSaControlRegister_HHD */ +#define AQ_MssIngressSaControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaThresholdLSW in AQ_MssIngressSaControlRegister_HHD */ +#define AQ_MssIngressSaControlRegister_HHD_mssIngressSaThresholdLSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaThresholdLSW in AQ_MssIngressSaControlRegister_HHD */ +#define bits_AQ_MssIngressSaControlRegister_HHD_mssIngressSaThresholdLSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaThresholdLSW in AQ_MssIngressSaControlRegister_HHD */ +#define word_AQ_MssIngressSaControlRegister_HHD_mssIngressSaThresholdLSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaThresholdMSW in AQ_MssIngressSaControlRegister_HHD */ +#define AQ_MssIngressSaControlRegister_HHD_mssIngressSaThresholdMSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaThresholdMSW in AQ_MssIngressSaControlRegister_HHD */ +#define bits_AQ_MssIngressSaControlRegister_HHD_mssIngressSaThresholdMSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaThresholdMSW in AQ_MssIngressSaControlRegister_HHD */ +#define word_AQ_MssIngressSaControlRegister_HHD_mssIngressSaThresholdMSW u1.word_1 + +/*! \brief Base register address of structure AQ_MssIngressInterruptStatusRegister_HHD */ +#define AQ_MssIngressInterruptStatusRegister_HHD_baseRegisterAddress 0x802E +/*! \brief MMD address of structure AQ_MssIngressInterruptStatusRegister_HHD */ +#define AQ_MssIngressInterruptStatusRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressIgpocMissInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define AQ_MssIngressInterruptStatusRegister_HHD_mssIngressIgpocMissInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressIgpocMissInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define bits_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressIgpocMissInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressIgpocMissInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define word_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressIgpocMissInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressTciE_cErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define AQ_MssIngressInterruptStatusRegister_HHD_mssIngressTciE_cErrorInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressTciE_cErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define bits_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressTciE_cErrorInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressTciE_cErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define word_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressTciE_cErrorInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressEccErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define AQ_MssIngressInterruptStatusRegister_HHD_mssIngressEccErrorInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressEccErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define bits_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressEccErrorInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressEccErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define word_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressEccErrorInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressMibSaturationInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define AQ_MssIngressInterruptStatusRegister_HHD_mssIngressMibSaturationInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressMibSaturationInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define bits_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressMibSaturationInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressMibSaturationInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define word_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressMibSaturationInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressReplayErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define AQ_MssIngressInterruptStatusRegister_HHD_mssIngressReplayErrorInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressReplayErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define bits_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressReplayErrorInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressReplayErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define word_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressReplayErrorInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressIcvErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define AQ_MssIngressInterruptStatusRegister_HHD_mssIngressIcvErrorInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressIcvErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define bits_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressIcvErrorInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressIcvErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define word_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressIcvErrorInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaThresholdExpiredInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define AQ_MssIngressInterruptStatusRegister_HHD_mssIngressSaThresholdExpiredInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaThresholdExpiredInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define bits_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressSaThresholdExpiredInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaThresholdExpiredInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define word_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressSaThresholdExpiredInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaExpiredInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define AQ_MssIngressInterruptStatusRegister_HHD_mssIngressSaExpiredInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaExpiredInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define bits_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressSaExpiredInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaExpiredInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define word_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressSaExpiredInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssMasterIngressInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define AQ_MssIngressInterruptStatusRegister_HHD_mssMasterIngressInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssMasterIngressInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define bits_AQ_MssIngressInterruptStatusRegister_HHD_mssMasterIngressInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssMasterIngressInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ +#define word_AQ_MssIngressInterruptStatusRegister_HHD_mssMasterIngressInterrupt u0.word_0 + +/*! \brief Base register address of structure AQ_MssIngressInterruptMaskRegister_HHD */ +#define AQ_MssIngressInterruptMaskRegister_HHD_baseRegisterAddress 0x8030 +/*! \brief MMD address of structure AQ_MssIngressInterruptMaskRegister_HHD */ +#define AQ_MssIngressInterruptMaskRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressIgpocMissInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define AQ_MssIngressInterruptMaskRegister_HHD_mssIngressIgpocMissInterruptEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressIgpocMissInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define bits_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressIgpocMissInterruptEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressIgpocMissInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define word_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressIgpocMissInterruptEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressTciE_cErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define AQ_MssIngressInterruptMaskRegister_HHD_mssIngressTciE_cErrorInterruptEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressTciE_cErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define bits_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressTciE_cErrorInterruptEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressTciE_cErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define word_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressTciE_cErrorInterruptEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressEccErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define AQ_MssIngressInterruptMaskRegister_HHD_mssIngressEccErrorInterruptEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressEccErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define bits_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressEccErrorInterruptEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressEccErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define word_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressEccErrorInterruptEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressMibSaturationInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define AQ_MssIngressInterruptMaskRegister_HHD_mssIngressMibSaturationInterruptEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressMibSaturationInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define bits_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressMibSaturationInterruptEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressMibSaturationInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define word_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressMibSaturationInterruptEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressReplayErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define AQ_MssIngressInterruptMaskRegister_HHD_mssIngressReplayErrorInterruptEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressReplayErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define bits_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressReplayErrorInterruptEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressReplayErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define word_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressReplayErrorInterruptEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressIcvErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define AQ_MssIngressInterruptMaskRegister_HHD_mssIngressIcvErrorInterruptEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressIcvErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define bits_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressIcvErrorInterruptEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressIcvErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define word_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressIcvErrorInterruptEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaThresholdExpiredInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define AQ_MssIngressInterruptMaskRegister_HHD_mssIngressSaThresholdExpiredInterruptEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaThresholdExpiredInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define bits_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressSaThresholdExpiredInterruptEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaThresholdExpiredInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define word_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressSaThresholdExpiredInterruptEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaExpiredInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define AQ_MssIngressInterruptMaskRegister_HHD_mssIngressSaExpiredInterruptEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaExpiredInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define bits_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressSaExpiredInterruptEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaExpiredInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define word_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressSaExpiredInterruptEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressMasterInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define AQ_MssIngressInterruptMaskRegister_HHD_mssIngressMasterInterruptEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressMasterInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define bits_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressMasterInterruptEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressMasterInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ +#define word_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressMasterInterruptEnable u0.word_0 + +/*! \brief Base register address of structure AQ_MssIngressSaIcvErrorStatusRegister_HHD */ +#define AQ_MssIngressSaIcvErrorStatusRegister_HHD_baseRegisterAddress 0x8032 +/*! \brief MMD address of structure AQ_MssIngressSaIcvErrorStatusRegister_HHD */ +#define AQ_MssIngressSaIcvErrorStatusRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaIcvErrorLSW in AQ_MssIngressSaIcvErrorStatusRegister_HHD */ +#define AQ_MssIngressSaIcvErrorStatusRegister_HHD_mssIngressSaIcvErrorLSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaIcvErrorLSW in AQ_MssIngressSaIcvErrorStatusRegister_HHD */ +#define bits_AQ_MssIngressSaIcvErrorStatusRegister_HHD_mssIngressSaIcvErrorLSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaIcvErrorLSW in AQ_MssIngressSaIcvErrorStatusRegister_HHD */ +#define word_AQ_MssIngressSaIcvErrorStatusRegister_HHD_mssIngressSaIcvErrorLSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaIcvErrorMSW in AQ_MssIngressSaIcvErrorStatusRegister_HHD */ +#define AQ_MssIngressSaIcvErrorStatusRegister_HHD_mssIngressSaIcvErrorMSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaIcvErrorMSW in AQ_MssIngressSaIcvErrorStatusRegister_HHD */ +#define bits_AQ_MssIngressSaIcvErrorStatusRegister_HHD_mssIngressSaIcvErrorMSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaIcvErrorMSW in AQ_MssIngressSaIcvErrorStatusRegister_HHD */ +#define word_AQ_MssIngressSaIcvErrorStatusRegister_HHD_mssIngressSaIcvErrorMSW u1.word_1 + +/*! \brief Base register address of structure AQ_MssIngressSaReplayErrorStatusRegister_HHD */ +#define AQ_MssIngressSaReplayErrorStatusRegister_HHD_baseRegisterAddress 0x8034 +/*! \brief MMD address of structure AQ_MssIngressSaReplayErrorStatusRegister_HHD */ +#define AQ_MssIngressSaReplayErrorStatusRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaReplayErrorLSW in AQ_MssIngressSaReplayErrorStatusRegister_HHD */ +#define AQ_MssIngressSaReplayErrorStatusRegister_HHD_mssIngressSaReplayErrorLSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaReplayErrorLSW in AQ_MssIngressSaReplayErrorStatusRegister_HHD */ +#define bits_AQ_MssIngressSaReplayErrorStatusRegister_HHD_mssIngressSaReplayErrorLSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaReplayErrorLSW in AQ_MssIngressSaReplayErrorStatusRegister_HHD */ +#define word_AQ_MssIngressSaReplayErrorStatusRegister_HHD_mssIngressSaReplayErrorLSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaReplayErrorMSW in AQ_MssIngressSaReplayErrorStatusRegister_HHD */ +#define AQ_MssIngressSaReplayErrorStatusRegister_HHD_mssIngressSaReplayErrorMSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaReplayErrorMSW in AQ_MssIngressSaReplayErrorStatusRegister_HHD */ +#define bits_AQ_MssIngressSaReplayErrorStatusRegister_HHD_mssIngressSaReplayErrorMSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaReplayErrorMSW in AQ_MssIngressSaReplayErrorStatusRegister_HHD */ +#define word_AQ_MssIngressSaReplayErrorStatusRegister_HHD_mssIngressSaReplayErrorMSW u1.word_1 + +/*! \brief Base register address of structure AQ_MssIngressSaExpiredStatusRegister_HHD */ +#define AQ_MssIngressSaExpiredStatusRegister_HHD_baseRegisterAddress 0x8036 +/*! \brief MMD address of structure AQ_MssIngressSaExpiredStatusRegister_HHD */ +#define AQ_MssIngressSaExpiredStatusRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaExpiredLSW in AQ_MssIngressSaExpiredStatusRegister_HHD */ +#define AQ_MssIngressSaExpiredStatusRegister_HHD_mssIngressSaExpiredLSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaExpiredLSW in AQ_MssIngressSaExpiredStatusRegister_HHD */ +#define bits_AQ_MssIngressSaExpiredStatusRegister_HHD_mssIngressSaExpiredLSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaExpiredLSW in AQ_MssIngressSaExpiredStatusRegister_HHD */ +#define word_AQ_MssIngressSaExpiredStatusRegister_HHD_mssIngressSaExpiredLSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaExpiredMSW in AQ_MssIngressSaExpiredStatusRegister_HHD */ +#define AQ_MssIngressSaExpiredStatusRegister_HHD_mssIngressSaExpiredMSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaExpiredMSW in AQ_MssIngressSaExpiredStatusRegister_HHD */ +#define bits_AQ_MssIngressSaExpiredStatusRegister_HHD_mssIngressSaExpiredMSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaExpiredMSW in AQ_MssIngressSaExpiredStatusRegister_HHD */ +#define word_AQ_MssIngressSaExpiredStatusRegister_HHD_mssIngressSaExpiredMSW u1.word_1 + +/*! \brief Base register address of structure AQ_MssIngressSaThresholdExpiredStatusRegister_HHD */ +#define AQ_MssIngressSaThresholdExpiredStatusRegister_HHD_baseRegisterAddress 0x8038 +/*! \brief MMD address of structure AQ_MssIngressSaThresholdExpiredStatusRegister_HHD */ +#define AQ_MssIngressSaThresholdExpiredStatusRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaThresholdExpiredLSW in AQ_MssIngressSaThresholdExpiredStatusRegister_HHD */ +#define AQ_MssIngressSaThresholdExpiredStatusRegister_HHD_mssIngressSaThresholdExpiredLSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaThresholdExpiredLSW in AQ_MssIngressSaThresholdExpiredStatusRegister_HHD */ +#define bits_AQ_MssIngressSaThresholdExpiredStatusRegister_HHD_mssIngressSaThresholdExpiredLSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaThresholdExpiredLSW in AQ_MssIngressSaThresholdExpiredStatusRegister_HHD */ +#define word_AQ_MssIngressSaThresholdExpiredStatusRegister_HHD_mssIngressSaThresholdExpiredLSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaThresholdExpiredMSW in AQ_MssIngressSaThresholdExpiredStatusRegister_HHD */ +#define AQ_MssIngressSaThresholdExpiredStatusRegister_HHD_mssIngressSaThresholdExpiredMSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaThresholdExpiredMSW in AQ_MssIngressSaThresholdExpiredStatusRegister_HHD */ +#define bits_AQ_MssIngressSaThresholdExpiredStatusRegister_HHD_mssIngressSaThresholdExpiredMSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaThresholdExpiredMSW in AQ_MssIngressSaThresholdExpiredStatusRegister_HHD */ +#define word_AQ_MssIngressSaThresholdExpiredStatusRegister_HHD_mssIngressSaThresholdExpiredMSW u1.word_1 + +/*! \brief Base register address of structure AQ_MssIngressEccInterruptStatusRegister_HHD */ +#define AQ_MssIngressEccInterruptStatusRegister_HHD_baseRegisterAddress 0x803A +/*! \brief MMD address of structure AQ_MssIngressEccInterruptStatusRegister_HHD */ +#define AQ_MssIngressEccInterruptStatusRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaEccErrorInterruptLSW in AQ_MssIngressEccInterruptStatusRegister_HHD */ +#define AQ_MssIngressEccInterruptStatusRegister_HHD_mssIngressSaEccErrorInterruptLSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaEccErrorInterruptLSW in AQ_MssIngressEccInterruptStatusRegister_HHD */ +#define bits_AQ_MssIngressEccInterruptStatusRegister_HHD_mssIngressSaEccErrorInterruptLSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaEccErrorInterruptLSW in AQ_MssIngressEccInterruptStatusRegister_HHD */ +#define word_AQ_MssIngressEccInterruptStatusRegister_HHD_mssIngressSaEccErrorInterruptLSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaEccErrorInterruptMSW in AQ_MssIngressEccInterruptStatusRegister_HHD */ +#define AQ_MssIngressEccInterruptStatusRegister_HHD_mssIngressSaEccErrorInterruptMSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaEccErrorInterruptMSW in AQ_MssIngressEccInterruptStatusRegister_HHD */ +#define bits_AQ_MssIngressEccInterruptStatusRegister_HHD_mssIngressSaEccErrorInterruptMSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaEccErrorInterruptMSW in AQ_MssIngressEccInterruptStatusRegister_HHD */ +#define word_AQ_MssIngressEccInterruptStatusRegister_HHD_mssIngressSaEccErrorInterruptMSW u1.word_1 + +/*! \brief Base register address of structure AQ_MssIngressLutAddressControlRegister_HHD */ +#define AQ_MssIngressLutAddressControlRegister_HHD_baseRegisterAddress 0x8080 +/*! \brief MMD address of structure AQ_MssIngressLutAddressControlRegister_HHD */ +#define AQ_MssIngressLutAddressControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutSelect in AQ_MssIngressLutAddressControlRegister_HHD */ +#define AQ_MssIngressLutAddressControlRegister_HHD_mssIngressLutSelect 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutSelect in AQ_MssIngressLutAddressControlRegister_HHD */ +#define bits_AQ_MssIngressLutAddressControlRegister_HHD_mssIngressLutSelect u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutSelect in AQ_MssIngressLutAddressControlRegister_HHD */ +#define word_AQ_MssIngressLutAddressControlRegister_HHD_mssIngressLutSelect u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutAddress in AQ_MssIngressLutAddressControlRegister_HHD */ +#define AQ_MssIngressLutAddressControlRegister_HHD_mssIngressLutAddress 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutAddress in AQ_MssIngressLutAddressControlRegister_HHD */ +#define bits_AQ_MssIngressLutAddressControlRegister_HHD_mssIngressLutAddress u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutAddress in AQ_MssIngressLutAddressControlRegister_HHD */ +#define word_AQ_MssIngressLutAddressControlRegister_HHD_mssIngressLutAddress u0.word_0 + +/*! \brief Base register address of structure AQ_MssIngressLutControlRegister_HHD */ +#define AQ_MssIngressLutControlRegister_HHD_baseRegisterAddress 0x8081 +/*! \brief MMD address of structure AQ_MssIngressLutControlRegister_HHD */ +#define AQ_MssIngressLutControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutWrite in AQ_MssIngressLutControlRegister_HHD */ +#define AQ_MssIngressLutControlRegister_HHD_mssIngressLutWrite 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutWrite in AQ_MssIngressLutControlRegister_HHD */ +#define bits_AQ_MssIngressLutControlRegister_HHD_mssIngressLutWrite u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutWrite in AQ_MssIngressLutControlRegister_HHD */ +#define word_AQ_MssIngressLutControlRegister_HHD_mssIngressLutWrite u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutRead in AQ_MssIngressLutControlRegister_HHD */ +#define AQ_MssIngressLutControlRegister_HHD_mssIngressLutRead 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutRead in AQ_MssIngressLutControlRegister_HHD */ +#define bits_AQ_MssIngressLutControlRegister_HHD_mssIngressLutRead u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutRead in AQ_MssIngressLutControlRegister_HHD */ +#define word_AQ_MssIngressLutControlRegister_HHD_mssIngressLutRead u0.word_0 + +/*! \brief Base register address of structure AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_baseRegisterAddress 0x80A0 +/*! \brief MMD address of structure AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_0 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_0 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_0 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_1 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_1 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_1 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_1 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_2 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_2 2 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_2 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_2 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_2 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_2 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_3 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_3 3 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_3 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_3 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_3 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_3 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_4 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_4 4 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_4 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_4 u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_4 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_4 u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_5 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_5 5 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_5 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_5 u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_5 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_5 u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_6 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_6 6 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_6 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_6 u6.bits_6 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_6 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_6 u6.word_6 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_7 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_7 7 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_7 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_7 u7.bits_7 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_7 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_7 u7.word_7 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_8 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_8 8 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_8 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_8 u8.bits_8 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_8 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_8 u8.word_8 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_9 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_9 9 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_9 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_9 u9.bits_9 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_9 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_9 u9.word_9 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_10 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_10 10 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_10 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_10 u10.bits_10 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_10 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_10 u10.word_10 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_11 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_11 11 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_11 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_11 u11.bits_11 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_11 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_11 u11.word_11 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_12 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_12 12 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_12 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_12 u12.bits_12 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_12 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_12 u12.word_12 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_13 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_13 13 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_13 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_13 u13.bits_13 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_13 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_13 u13.word_13 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_14 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_14 14 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_14 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_14 u14.bits_14 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_14 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_14 u14.word_14 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_15 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_15 15 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_15 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_15 u15.bits_15 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_15 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_15 u15.word_15 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_16 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_16 16 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_16 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_16 u16.bits_16 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_16 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_16 u16.word_16 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_17 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_17 17 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_17 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_17 u17.bits_17 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_17 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_17 u17.word_17 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_18 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_18 18 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_18 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_18 u18.bits_18 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_18 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_18 u18.word_18 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_19 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_19 19 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_19 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_19 u19.bits_19 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_19 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_19 u19.word_19 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_20 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_20 20 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_20 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_20 u20.bits_20 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_20 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_20 u20.word_20 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_21 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_21 21 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_21 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_21 u21.bits_21 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_21 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_21 u21.word_21 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_22 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_22 22 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_22 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_22 u22.bits_22 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_22 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_22 u22.word_22 +/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_23 in AQ_MssIngressLutDataControlRegister_HHD */ +#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_23 23 +/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_23 in AQ_MssIngressLutDataControlRegister_HHD */ +#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_23 u23.bits_23 +/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_23 in AQ_MssIngressLutDataControlRegister_HHD */ +#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_23 u23.word_23 + +/*! \brief Base register address of structure AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_baseRegisterAddress 0x9004 +/*! \brief MMD address of structure AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLinePhyTxEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLinePhyTxEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLinePhyTxEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLinePhyTxEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLinePhyTxEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLinePhyTxEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxErrorDiscard in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLineRxErrorDiscard 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxErrorDiscard in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineRxErrorDiscard u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxErrorDiscard in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineRxErrorDiscard u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineControlFrameEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLineControlFrameEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineControlFrameEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineControlFrameEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineControlFrameEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineControlFrameEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineSoftReset in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLineSoftReset 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineSoftReset in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineSoftReset u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineSoftReset in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineSoftReset u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxPadEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLineTxPadEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxPadEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineTxPadEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxPadEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineTxPadEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxCrcAppend in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLineTxCrcAppend 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxCrcAppend in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineTxCrcAppend u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxCrcAppend in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineTxCrcAppend u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxAddressInsertEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLineTxAddressInsertEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxAddressInsertEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineTxAddressInsertEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxAddressInsertEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineTxAddressInsertEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLinePauseIgnore in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLinePauseIgnore 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLinePauseIgnore in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLinePauseIgnore u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLinePauseIgnore in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLinePauseIgnore u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLinePauseForward in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLinePauseForward 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLinePauseForward in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLinePauseForward u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLinePauseForward in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLinePauseForward u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineCrcForward in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLineCrcForward 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineCrcForward in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineCrcForward u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineCrcForward in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineCrcForward u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLinePadEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLinePadEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLinePadEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLinePadEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLinePadEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLinePadEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLinePromiscuousMode in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLinePromiscuousMode 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLinePromiscuousMode in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLinePromiscuousMode u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLinePromiscuousMode in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLinePromiscuousMode u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineWanMode in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLineWanMode 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineWanMode in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineWanMode u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineWanMode in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineWanMode u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLineRxEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineRxEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineRxEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLineTxEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineTxEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineTxEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxLowPowerIdleEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLineTxLowPowerIdleEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxLowPowerIdleEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineTxLowPowerIdleEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxLowPowerIdleEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineTxLowPowerIdleEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineSfdCheckDisable in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLineSfdCheckDisable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineSfdCheckDisable in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineSfdCheckDisable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineSfdCheckDisable in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineSfdCheckDisable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure msmLinePriorityFlowControlEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLinePriorityFlowControlEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLinePriorityFlowControlEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLinePriorityFlowControlEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLinePriorityFlowControlEnable in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLinePriorityFlowControlEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineIdleColumnCountExtend in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLineIdleColumnCountExtend 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineIdleColumnCountExtend in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineIdleColumnCountExtend u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineIdleColumnCountExtend in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineIdleColumnCountExtend u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineLengthCheckDisable in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLineLengthCheckDisable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineLengthCheckDisable in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineLengthCheckDisable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineLengthCheckDisable in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineLengthCheckDisable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineForceSendIdle in AQ_MsmLineGeneralControlRegister_HHD */ +#define AQ_MsmLineGeneralControlRegister_HHD_msmLineForceSendIdle 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineForceSendIdle in AQ_MsmLineGeneralControlRegister_HHD */ +#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineForceSendIdle u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineForceSendIdle in AQ_MsmLineGeneralControlRegister_HHD */ +#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineForceSendIdle u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineFifoControlRegister_HHD */ +#define AQ_MsmLineFifoControlRegister_HHD_baseRegisterAddress 0x900E +/*! \brief MMD address of structure AQ_MsmLineFifoControlRegister_HHD */ +#define AQ_MsmLineFifoControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxFifoFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoFullThreshold 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxFifoFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define bits_AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoFullThreshold u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxFifoFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define word_AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoFullThreshold u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxFifoEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoEmptyThreshold 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxFifoEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define bits_AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoEmptyThreshold u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxFifoEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define word_AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoEmptyThreshold u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxFifoFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoFullThreshold 2 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxFifoFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define bits_AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoFullThreshold u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxFifoFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define word_AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoFullThreshold u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxFifoEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoEmptyThreshold 3 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxFifoEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define bits_AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoEmptyThreshold u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxFifoEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define word_AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoEmptyThreshold u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxFifoAlmostFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoAlmostFullThreshold 4 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxFifoAlmostFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define bits_AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoAlmostFullThreshold u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxFifoAlmostFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define word_AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoAlmostFullThreshold u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxFifoAlmostEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoAlmostEmptyThreshold 5 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxFifoAlmostEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define bits_AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoAlmostEmptyThreshold u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxFifoAlmostEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define word_AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoAlmostEmptyThreshold u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxFifoAlmostFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoAlmostFullThreshold 6 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxFifoAlmostFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define bits_AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoAlmostFullThreshold u6.bits_6 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxFifoAlmostFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define word_AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoAlmostFullThreshold u6.word_6 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxFifoAlmostEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoAlmostEmptyThreshold 7 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxFifoAlmostEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define bits_AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoAlmostEmptyThreshold u7.bits_7 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxFifoAlmostEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ +#define word_AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoAlmostEmptyThreshold u7.word_7 + +/*! \brief Base register address of structure AQ_MsmLineGeneralStatusRegister_HHD */ +#define AQ_MsmLineGeneralStatusRegister_HHD_baseRegisterAddress 0x9020 +/*! \brief MMD address of structure AQ_MsmLineGeneralStatusRegister_HHD */ +#define AQ_MsmLineGeneralStatusRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxFifoEmpty in AQ_MsmLineGeneralStatusRegister_HHD */ +#define AQ_MsmLineGeneralStatusRegister_HHD_msmLineTxFifoEmpty 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxFifoEmpty in AQ_MsmLineGeneralStatusRegister_HHD */ +#define bits_AQ_MsmLineGeneralStatusRegister_HHD_msmLineTxFifoEmpty u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxFifoEmpty in AQ_MsmLineGeneralStatusRegister_HHD */ +#define word_AQ_MsmLineGeneralStatusRegister_HHD_msmLineTxFifoEmpty u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxLowPowerIdle in AQ_MsmLineGeneralStatusRegister_HHD */ +#define AQ_MsmLineGeneralStatusRegister_HHD_msmLineRxLowPowerIdle 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxLowPowerIdle in AQ_MsmLineGeneralStatusRegister_HHD */ +#define bits_AQ_MsmLineGeneralStatusRegister_HHD_msmLineRxLowPowerIdle u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxLowPowerIdle in AQ_MsmLineGeneralStatusRegister_HHD */ +#define word_AQ_MsmLineGeneralStatusRegister_HHD_msmLineRxLowPowerIdle u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTimestampAvailable in AQ_MsmLineGeneralStatusRegister_HHD */ +#define AQ_MsmLineGeneralStatusRegister_HHD_msmLineTimestampAvailable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTimestampAvailable in AQ_MsmLineGeneralStatusRegister_HHD */ +#define bits_AQ_MsmLineGeneralStatusRegister_HHD_msmLineTimestampAvailable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTimestampAvailable in AQ_MsmLineGeneralStatusRegister_HHD */ +#define word_AQ_MsmLineGeneralStatusRegister_HHD_msmLineTimestampAvailable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLinePhyLossOfSignal in AQ_MsmLineGeneralStatusRegister_HHD */ +#define AQ_MsmLineGeneralStatusRegister_HHD_msmLinePhyLossOfSignal 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLinePhyLossOfSignal in AQ_MsmLineGeneralStatusRegister_HHD */ +#define bits_AQ_MsmLineGeneralStatusRegister_HHD_msmLinePhyLossOfSignal u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLinePhyLossOfSignal in AQ_MsmLineGeneralStatusRegister_HHD */ +#define word_AQ_MsmLineGeneralStatusRegister_HHD_msmLinePhyLossOfSignal u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxRemoteFault in AQ_MsmLineGeneralStatusRegister_HHD */ +#define AQ_MsmLineGeneralStatusRegister_HHD_msmLineRxRemoteFault 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxRemoteFault in AQ_MsmLineGeneralStatusRegister_HHD */ +#define bits_AQ_MsmLineGeneralStatusRegister_HHD_msmLineRxRemoteFault u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxRemoteFault in AQ_MsmLineGeneralStatusRegister_HHD */ +#define word_AQ_MsmLineGeneralStatusRegister_HHD_msmLineRxRemoteFault u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxLocalFault in AQ_MsmLineGeneralStatusRegister_HHD */ +#define AQ_MsmLineGeneralStatusRegister_HHD_msmLineRxLocalFault 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxLocalFault in AQ_MsmLineGeneralStatusRegister_HHD */ +#define bits_AQ_MsmLineGeneralStatusRegister_HHD_msmLineRxLocalFault u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxLocalFault in AQ_MsmLineGeneralStatusRegister_HHD */ +#define word_AQ_MsmLineGeneralStatusRegister_HHD_msmLineRxLocalFault u0.word_0 + +/*! \brief Base register address of structure AQ_MsmLineTxIpgControlRegister_HHD */ +#define AQ_MsmLineTxIpgControlRegister_HHD_baseRegisterAddress 0x9022 +/*! \brief MMD address of structure AQ_MsmLineTxIpgControlRegister_HHD */ +#define AQ_MsmLineTxIpgControlRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxIpgLength in AQ_MsmLineTxIpgControlRegister_HHD */ +#define AQ_MsmLineTxIpgControlRegister_HHD_msmLineTxIpgLength 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxIpgLength in AQ_MsmLineTxIpgControlRegister_HHD */ +#define bits_AQ_MsmLineTxIpgControlRegister_HHD_msmLineTxIpgLength u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxIpgLength in AQ_MsmLineTxIpgControlRegister_HHD */ +#define word_AQ_MsmLineTxIpgControlRegister_HHD_msmLineTxIpgLength u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxIpgReserved in AQ_MsmLineTxIpgControlRegister_HHD */ +#define AQ_MsmLineTxIpgControlRegister_HHD_msmLineTxIpgReserved 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxIpgReserved in AQ_MsmLineTxIpgControlRegister_HHD */ +#define bits_AQ_MsmLineTxIpgControlRegister_HHD_msmLineTxIpgReserved u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxIpgReserved in AQ_MsmLineTxIpgControlRegister_HHD */ +#define word_AQ_MsmLineTxIpgControlRegister_HHD_msmLineTxIpgReserved u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineTxGoodFramesCounterRegister_HHD */ +#define AQ_MsmLineTxGoodFramesCounterRegister_HHD_baseRegisterAddress 0x9040 +/*! \brief MMD address of structure AQ_MsmLineTxGoodFramesCounterRegister_HHD */ +#define AQ_MsmLineTxGoodFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxGoodFramesCounter_0 in AQ_MsmLineTxGoodFramesCounterRegister_HHD */ +#define AQ_MsmLineTxGoodFramesCounterRegister_HHD_msmLineTxGoodFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxGoodFramesCounter_0 in AQ_MsmLineTxGoodFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineTxGoodFramesCounterRegister_HHD_msmLineTxGoodFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxGoodFramesCounter_0 in AQ_MsmLineTxGoodFramesCounterRegister_HHD */ +#define word_AQ_MsmLineTxGoodFramesCounterRegister_HHD_msmLineTxGoodFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxGoodFramesCounter_1 in AQ_MsmLineTxGoodFramesCounterRegister_HHD */ +#define AQ_MsmLineTxGoodFramesCounterRegister_HHD_msmLineTxGoodFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxGoodFramesCounter_1 in AQ_MsmLineTxGoodFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineTxGoodFramesCounterRegister_HHD_msmLineTxGoodFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxGoodFramesCounter_1 in AQ_MsmLineTxGoodFramesCounterRegister_HHD */ +#define word_AQ_MsmLineTxGoodFramesCounterRegister_HHD_msmLineTxGoodFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineRxGoodFramesCounterRegister_HHD */ +#define AQ_MsmLineRxGoodFramesCounterRegister_HHD_baseRegisterAddress 0x9044 +/*! \brief MMD address of structure AQ_MsmLineRxGoodFramesCounterRegister_HHD */ +#define AQ_MsmLineRxGoodFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxGoodFramesCounter_0 in AQ_MsmLineRxGoodFramesCounterRegister_HHD */ +#define AQ_MsmLineRxGoodFramesCounterRegister_HHD_msmLineRxGoodFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxGoodFramesCounter_0 in AQ_MsmLineRxGoodFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineRxGoodFramesCounterRegister_HHD_msmLineRxGoodFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxGoodFramesCounter_0 in AQ_MsmLineRxGoodFramesCounterRegister_HHD */ +#define word_AQ_MsmLineRxGoodFramesCounterRegister_HHD_msmLineRxGoodFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxGoodFramesCounter_1 in AQ_MsmLineRxGoodFramesCounterRegister_HHD */ +#define AQ_MsmLineRxGoodFramesCounterRegister_HHD_msmLineRxGoodFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxGoodFramesCounter_1 in AQ_MsmLineRxGoodFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineRxGoodFramesCounterRegister_HHD_msmLineRxGoodFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxGoodFramesCounter_1 in AQ_MsmLineRxGoodFramesCounterRegister_HHD */ +#define word_AQ_MsmLineRxGoodFramesCounterRegister_HHD_msmLineRxGoodFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineRxFcsErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxFcsErrorsCounterRegister_HHD_baseRegisterAddress 0x9048 +/*! \brief MMD address of structure AQ_MsmLineRxFcsErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxFcsErrorsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineFcsErrorCounter_0 in AQ_MsmLineRxFcsErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxFcsErrorsCounterRegister_HHD_msmLineFcsErrorCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineFcsErrorCounter_0 in AQ_MsmLineRxFcsErrorsCounterRegister_HHD */ +#define bits_AQ_MsmLineRxFcsErrorsCounterRegister_HHD_msmLineFcsErrorCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineFcsErrorCounter_0 in AQ_MsmLineRxFcsErrorsCounterRegister_HHD */ +#define word_AQ_MsmLineRxFcsErrorsCounterRegister_HHD_msmLineFcsErrorCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineFcsErrorCounter_1 in AQ_MsmLineRxFcsErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxFcsErrorsCounterRegister_HHD_msmLineFcsErrorCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineFcsErrorCounter_1 in AQ_MsmLineRxFcsErrorsCounterRegister_HHD */ +#define bits_AQ_MsmLineRxFcsErrorsCounterRegister_HHD_msmLineFcsErrorCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineFcsErrorCounter_1 in AQ_MsmLineRxFcsErrorsCounterRegister_HHD */ +#define word_AQ_MsmLineRxFcsErrorsCounterRegister_HHD_msmLineFcsErrorCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD_baseRegisterAddress 0x904C +/*! \brief MMD address of structure AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineAlignmentErrorCounter_0 in AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD_msmLineAlignmentErrorCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineAlignmentErrorCounter_0 in AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD */ +#define bits_AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD_msmLineAlignmentErrorCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineAlignmentErrorCounter_0 in AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD */ +#define word_AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD_msmLineAlignmentErrorCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineAlignmentErrorCounter_1 in AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD_msmLineAlignmentErrorCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineAlignmentErrorCounter_1 in AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD */ +#define bits_AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD_msmLineAlignmentErrorCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineAlignmentErrorCounter_1 in AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD */ +#define word_AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD_msmLineAlignmentErrorCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineTxPauseFramesCounterRegister_HHD */ +#define AQ_MsmLineTxPauseFramesCounterRegister_HHD_baseRegisterAddress 0x9050 +/*! \brief MMD address of structure AQ_MsmLineTxPauseFramesCounterRegister_HHD */ +#define AQ_MsmLineTxPauseFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxPauseFramesCounter_0 in AQ_MsmLineTxPauseFramesCounterRegister_HHD */ +#define AQ_MsmLineTxPauseFramesCounterRegister_HHD_msmLineTxPauseFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxPauseFramesCounter_0 in AQ_MsmLineTxPauseFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineTxPauseFramesCounterRegister_HHD_msmLineTxPauseFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxPauseFramesCounter_0 in AQ_MsmLineTxPauseFramesCounterRegister_HHD */ +#define word_AQ_MsmLineTxPauseFramesCounterRegister_HHD_msmLineTxPauseFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxPauseFramesCounter_1 in AQ_MsmLineTxPauseFramesCounterRegister_HHD */ +#define AQ_MsmLineTxPauseFramesCounterRegister_HHD_msmLineTxPauseFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxPauseFramesCounter_1 in AQ_MsmLineTxPauseFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineTxPauseFramesCounterRegister_HHD_msmLineTxPauseFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxPauseFramesCounter_1 in AQ_MsmLineTxPauseFramesCounterRegister_HHD */ +#define word_AQ_MsmLineTxPauseFramesCounterRegister_HHD_msmLineTxPauseFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineRxPauseFramesCounterRegister_HHD */ +#define AQ_MsmLineRxPauseFramesCounterRegister_HHD_baseRegisterAddress 0x9054 +/*! \brief MMD address of structure AQ_MsmLineRxPauseFramesCounterRegister_HHD */ +#define AQ_MsmLineRxPauseFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxPauseFramesCounter_0 in AQ_MsmLineRxPauseFramesCounterRegister_HHD */ +#define AQ_MsmLineRxPauseFramesCounterRegister_HHD_msmLineRxPauseFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxPauseFramesCounter_0 in AQ_MsmLineRxPauseFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineRxPauseFramesCounterRegister_HHD_msmLineRxPauseFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxPauseFramesCounter_0 in AQ_MsmLineRxPauseFramesCounterRegister_HHD */ +#define word_AQ_MsmLineRxPauseFramesCounterRegister_HHD_msmLineRxPauseFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxPauseFramesCounter_1 in AQ_MsmLineRxPauseFramesCounterRegister_HHD */ +#define AQ_MsmLineRxPauseFramesCounterRegister_HHD_msmLineRxPauseFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxPauseFramesCounter_1 in AQ_MsmLineRxPauseFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineRxPauseFramesCounterRegister_HHD_msmLineRxPauseFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxPauseFramesCounter_1 in AQ_MsmLineRxPauseFramesCounterRegister_HHD */ +#define word_AQ_MsmLineRxPauseFramesCounterRegister_HHD_msmLineRxPauseFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineRxTooLongErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxTooLongErrorsCounterRegister_HHD_baseRegisterAddress 0x9058 +/*! \brief MMD address of structure AQ_MsmLineRxTooLongErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxTooLongErrorsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxTooLongErrorsCounter_0 in AQ_MsmLineRxTooLongErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxTooLongErrorsCounterRegister_HHD_msmLineRxTooLongErrorsCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxTooLongErrorsCounter_0 in AQ_MsmLineRxTooLongErrorsCounterRegister_HHD */ +#define bits_AQ_MsmLineRxTooLongErrorsCounterRegister_HHD_msmLineRxTooLongErrorsCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxTooLongErrorsCounter_0 in AQ_MsmLineRxTooLongErrorsCounterRegister_HHD */ +#define word_AQ_MsmLineRxTooLongErrorsCounterRegister_HHD_msmLineRxTooLongErrorsCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxTooLongErrorsCounter_1 in AQ_MsmLineRxTooLongErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxTooLongErrorsCounterRegister_HHD_msmLineRxTooLongErrorsCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxTooLongErrorsCounter_1 in AQ_MsmLineRxTooLongErrorsCounterRegister_HHD */ +#define bits_AQ_MsmLineRxTooLongErrorsCounterRegister_HHD_msmLineRxTooLongErrorsCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxTooLongErrorsCounter_1 in AQ_MsmLineRxTooLongErrorsCounterRegister_HHD */ +#define word_AQ_MsmLineRxTooLongErrorsCounterRegister_HHD_msmLineRxTooLongErrorsCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD_baseRegisterAddress 0x905C +/*! \brief MMD address of structure AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxInRangeLengthErrorsCounter_0 in AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD_msmLineRxInRangeLengthErrorsCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxInRangeLengthErrorsCounter_0 in AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD */ +#define bits_AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD_msmLineRxInRangeLengthErrorsCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxInRangeLengthErrorsCounter_0 in AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD */ +#define word_AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD_msmLineRxInRangeLengthErrorsCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxInRangeLengthErrorsCounter_1 in AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD_msmLineRxInRangeLengthErrorsCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxInRangeLengthErrorsCounter_1 in AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD */ +#define bits_AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD_msmLineRxInRangeLengthErrorsCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxInRangeLengthErrorsCounter_1 in AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD */ +#define word_AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD_msmLineRxInRangeLengthErrorsCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineTxVlanFramesCounterRegister_HHD */ +#define AQ_MsmLineTxVlanFramesCounterRegister_HHD_baseRegisterAddress 0x9060 +/*! \brief MMD address of structure AQ_MsmLineTxVlanFramesCounterRegister_HHD */ +#define AQ_MsmLineTxVlanFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxVlanFramesCounter_0 in AQ_MsmLineTxVlanFramesCounterRegister_HHD */ +#define AQ_MsmLineTxVlanFramesCounterRegister_HHD_msmLineTxVlanFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxVlanFramesCounter_0 in AQ_MsmLineTxVlanFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineTxVlanFramesCounterRegister_HHD_msmLineTxVlanFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxVlanFramesCounter_0 in AQ_MsmLineTxVlanFramesCounterRegister_HHD */ +#define word_AQ_MsmLineTxVlanFramesCounterRegister_HHD_msmLineTxVlanFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxVlanFramesCounter_1 in AQ_MsmLineTxVlanFramesCounterRegister_HHD */ +#define AQ_MsmLineTxVlanFramesCounterRegister_HHD_msmLineTxVlanFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxVlanFramesCounter_1 in AQ_MsmLineTxVlanFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineTxVlanFramesCounterRegister_HHD_msmLineTxVlanFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxVlanFramesCounter_1 in AQ_MsmLineTxVlanFramesCounterRegister_HHD */ +#define word_AQ_MsmLineTxVlanFramesCounterRegister_HHD_msmLineTxVlanFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineRxVlanFramesCounterRegister_HHD */ +#define AQ_MsmLineRxVlanFramesCounterRegister_HHD_baseRegisterAddress 0x9064 +/*! \brief MMD address of structure AQ_MsmLineRxVlanFramesCounterRegister_HHD */ +#define AQ_MsmLineRxVlanFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxVlanFramesCounter_0 in AQ_MsmLineRxVlanFramesCounterRegister_HHD */ +#define AQ_MsmLineRxVlanFramesCounterRegister_HHD_msmLineRxVlanFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxVlanFramesCounter_0 in AQ_MsmLineRxVlanFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineRxVlanFramesCounterRegister_HHD_msmLineRxVlanFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxVlanFramesCounter_0 in AQ_MsmLineRxVlanFramesCounterRegister_HHD */ +#define word_AQ_MsmLineRxVlanFramesCounterRegister_HHD_msmLineRxVlanFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxVlanFramesCounter_1 in AQ_MsmLineRxVlanFramesCounterRegister_HHD */ +#define AQ_MsmLineRxVlanFramesCounterRegister_HHD_msmLineRxVlanFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxVlanFramesCounter_1 in AQ_MsmLineRxVlanFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineRxVlanFramesCounterRegister_HHD_msmLineRxVlanFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxVlanFramesCounter_1 in AQ_MsmLineRxVlanFramesCounterRegister_HHD */ +#define word_AQ_MsmLineRxVlanFramesCounterRegister_HHD_msmLineRxVlanFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineTxOctetsCounterRegister_HHD */ +#define AQ_MsmLineTxOctetsCounterRegister_HHD_baseRegisterAddress 0x9068 +/*! \brief MMD address of structure AQ_MsmLineTxOctetsCounterRegister_HHD */ +#define AQ_MsmLineTxOctetsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxOctetsCounter_0 in AQ_MsmLineTxOctetsCounterRegister_HHD */ +#define AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxOctetsCounter_0 in AQ_MsmLineTxOctetsCounterRegister_HHD */ +#define bits_AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxOctetsCounter_0 in AQ_MsmLineTxOctetsCounterRegister_HHD */ +#define word_AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxOctetsCounter_1 in AQ_MsmLineTxOctetsCounterRegister_HHD */ +#define AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxOctetsCounter_1 in AQ_MsmLineTxOctetsCounterRegister_HHD */ +#define bits_AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxOctetsCounter_1 in AQ_MsmLineTxOctetsCounterRegister_HHD */ +#define word_AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_1 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxOctetsCounter_2 in AQ_MsmLineTxOctetsCounterRegister_HHD */ +#define AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_2 2 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxOctetsCounter_2 in AQ_MsmLineTxOctetsCounterRegister_HHD */ +#define bits_AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_2 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxOctetsCounter_2 in AQ_MsmLineTxOctetsCounterRegister_HHD */ +#define word_AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_2 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxOctetsCounter_3 in AQ_MsmLineTxOctetsCounterRegister_HHD */ +#define AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_3 3 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxOctetsCounter_3 in AQ_MsmLineTxOctetsCounterRegister_HHD */ +#define bits_AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_3 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxOctetsCounter_3 in AQ_MsmLineTxOctetsCounterRegister_HHD */ +#define word_AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_3 u3.word_3 + +/*! \brief Base register address of structure AQ_MsmLineRxOctetsCounterRegister_HHD */ +#define AQ_MsmLineRxOctetsCounterRegister_HHD_baseRegisterAddress 0x906C +/*! \brief MMD address of structure AQ_MsmLineRxOctetsCounterRegister_HHD */ +#define AQ_MsmLineRxOctetsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxOctetsCounter_0 in AQ_MsmLineRxOctetsCounterRegister_HHD */ +#define AQ_MsmLineRxOctetsCounterRegister_HHD_msmLineRxOctetsCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxOctetsCounter_0 in AQ_MsmLineRxOctetsCounterRegister_HHD */ +#define bits_AQ_MsmLineRxOctetsCounterRegister_HHD_msmLineRxOctetsCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxOctetsCounter_0 in AQ_MsmLineRxOctetsCounterRegister_HHD */ +#define word_AQ_MsmLineRxOctetsCounterRegister_HHD_msmLineRxOctetsCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxOctetsCounter_1 in AQ_MsmLineRxOctetsCounterRegister_HHD */ +#define AQ_MsmLineRxOctetsCounterRegister_HHD_msmLineRxOctetsCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxOctetsCounter_1 in AQ_MsmLineRxOctetsCounterRegister_HHD */ +#define bits_AQ_MsmLineRxOctetsCounterRegister_HHD_msmLineRxOctetsCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxOctetsCounter_1 in AQ_MsmLineRxOctetsCounterRegister_HHD */ +#define word_AQ_MsmLineRxOctetsCounterRegister_HHD_msmLineRxOctetsCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineRxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmLineRxUnicastFramesCounterRegister_HHD_baseRegisterAddress 0x9070 +/*! \brief MMD address of structure AQ_MsmLineRxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmLineRxUnicastFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxUnicastFramesCounter_0 in AQ_MsmLineRxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmLineRxUnicastFramesCounterRegister_HHD_msmLineRxUnicastFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxUnicastFramesCounter_0 in AQ_MsmLineRxUnicastFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineRxUnicastFramesCounterRegister_HHD_msmLineRxUnicastFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxUnicastFramesCounter_0 in AQ_MsmLineRxUnicastFramesCounterRegister_HHD */ +#define word_AQ_MsmLineRxUnicastFramesCounterRegister_HHD_msmLineRxUnicastFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxUnicastFramesCounter_1 in AQ_MsmLineRxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmLineRxUnicastFramesCounterRegister_HHD_msmLineRxUnicastFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxUnicastFramesCounter_1 in AQ_MsmLineRxUnicastFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineRxUnicastFramesCounterRegister_HHD_msmLineRxUnicastFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxUnicastFramesCounter_1 in AQ_MsmLineRxUnicastFramesCounterRegister_HHD */ +#define word_AQ_MsmLineRxUnicastFramesCounterRegister_HHD_msmLineRxUnicastFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineRxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmLineRxMulticastFramesCounterRegister_HHD_baseRegisterAddress 0x9074 +/*! \brief MMD address of structure AQ_MsmLineRxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmLineRxMulticastFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxMulticastFramesCounter_0 in AQ_MsmLineRxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmLineRxMulticastFramesCounterRegister_HHD_msmLineRxMulticastFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxMulticastFramesCounter_0 in AQ_MsmLineRxMulticastFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineRxMulticastFramesCounterRegister_HHD_msmLineRxMulticastFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxMulticastFramesCounter_0 in AQ_MsmLineRxMulticastFramesCounterRegister_HHD */ +#define word_AQ_MsmLineRxMulticastFramesCounterRegister_HHD_msmLineRxMulticastFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxMulticastFramesCounter_1 in AQ_MsmLineRxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmLineRxMulticastFramesCounterRegister_HHD_msmLineRxMulticastFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxMulticastFramesCounter_1 in AQ_MsmLineRxMulticastFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineRxMulticastFramesCounterRegister_HHD_msmLineRxMulticastFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxMulticastFramesCounter_1 in AQ_MsmLineRxMulticastFramesCounterRegister_HHD */ +#define word_AQ_MsmLineRxMulticastFramesCounterRegister_HHD_msmLineRxMulticastFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineRxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmLineRxBroadcastFramesCounterRegister_HHD_baseRegisterAddress 0x9078 +/*! \brief MMD address of structure AQ_MsmLineRxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmLineRxBroadcastFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxBroadcastFramesCounter_0 in AQ_MsmLineRxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmLineRxBroadcastFramesCounterRegister_HHD_msmLineRxBroadcastFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxBroadcastFramesCounter_0 in AQ_MsmLineRxBroadcastFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineRxBroadcastFramesCounterRegister_HHD_msmLineRxBroadcastFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxBroadcastFramesCounter_0 in AQ_MsmLineRxBroadcastFramesCounterRegister_HHD */ +#define word_AQ_MsmLineRxBroadcastFramesCounterRegister_HHD_msmLineRxBroadcastFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxBroadcastFramesCounter_1 in AQ_MsmLineRxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmLineRxBroadcastFramesCounterRegister_HHD_msmLineRxBroadcastFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxBroadcastFramesCounter_1 in AQ_MsmLineRxBroadcastFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineRxBroadcastFramesCounterRegister_HHD_msmLineRxBroadcastFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxBroadcastFramesCounter_1 in AQ_MsmLineRxBroadcastFramesCounterRegister_HHD */ +#define word_AQ_MsmLineRxBroadcastFramesCounterRegister_HHD_msmLineRxBroadcastFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineTxErrorsCounterRegister_HHD */ +#define AQ_MsmLineTxErrorsCounterRegister_HHD_baseRegisterAddress 0x907C +/*! \brief MMD address of structure AQ_MsmLineTxErrorsCounterRegister_HHD */ +#define AQ_MsmLineTxErrorsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxErrorsCounter_0 in AQ_MsmLineTxErrorsCounterRegister_HHD */ +#define AQ_MsmLineTxErrorsCounterRegister_HHD_msmLineTxErrorsCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxErrorsCounter_0 in AQ_MsmLineTxErrorsCounterRegister_HHD */ +#define bits_AQ_MsmLineTxErrorsCounterRegister_HHD_msmLineTxErrorsCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxErrorsCounter_0 in AQ_MsmLineTxErrorsCounterRegister_HHD */ +#define word_AQ_MsmLineTxErrorsCounterRegister_HHD_msmLineTxErrorsCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxErrorsCounter_1 in AQ_MsmLineTxErrorsCounterRegister_HHD */ +#define AQ_MsmLineTxErrorsCounterRegister_HHD_msmLineTxErrorsCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxErrorsCounter_1 in AQ_MsmLineTxErrorsCounterRegister_HHD */ +#define bits_AQ_MsmLineTxErrorsCounterRegister_HHD_msmLineTxErrorsCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxErrorsCounter_1 in AQ_MsmLineTxErrorsCounterRegister_HHD */ +#define word_AQ_MsmLineTxErrorsCounterRegister_HHD_msmLineTxErrorsCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineTxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmLineTxUnicastFramesCounterRegister_HHD_baseRegisterAddress 0x9084 +/*! \brief MMD address of structure AQ_MsmLineTxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmLineTxUnicastFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxUnicastFramesCounter_0 in AQ_MsmLineTxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmLineTxUnicastFramesCounterRegister_HHD_msmLineTxUnicastFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxUnicastFramesCounter_0 in AQ_MsmLineTxUnicastFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineTxUnicastFramesCounterRegister_HHD_msmLineTxUnicastFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxUnicastFramesCounter_0 in AQ_MsmLineTxUnicastFramesCounterRegister_HHD */ +#define word_AQ_MsmLineTxUnicastFramesCounterRegister_HHD_msmLineTxUnicastFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxUnicastFramesCounter_1 in AQ_MsmLineTxUnicastFramesCounterRegister_HHD */ +#define AQ_MsmLineTxUnicastFramesCounterRegister_HHD_msmLineTxUnicastFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxUnicastFramesCounter_1 in AQ_MsmLineTxUnicastFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineTxUnicastFramesCounterRegister_HHD_msmLineTxUnicastFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxUnicastFramesCounter_1 in AQ_MsmLineTxUnicastFramesCounterRegister_HHD */ +#define word_AQ_MsmLineTxUnicastFramesCounterRegister_HHD_msmLineTxUnicastFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineTxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmLineTxMulticastFramesCounterRegister_HHD_baseRegisterAddress 0x9088 +/*! \brief MMD address of structure AQ_MsmLineTxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmLineTxMulticastFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxMulticastFramesCounter_0 in AQ_MsmLineTxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmLineTxMulticastFramesCounterRegister_HHD_msmLineTxMulticastFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxMulticastFramesCounter_0 in AQ_MsmLineTxMulticastFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineTxMulticastFramesCounterRegister_HHD_msmLineTxMulticastFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxMulticastFramesCounter_0 in AQ_MsmLineTxMulticastFramesCounterRegister_HHD */ +#define word_AQ_MsmLineTxMulticastFramesCounterRegister_HHD_msmLineTxMulticastFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxMulticastFramesCounter_1 in AQ_MsmLineTxMulticastFramesCounterRegister_HHD */ +#define AQ_MsmLineTxMulticastFramesCounterRegister_HHD_msmLineTxMulticastFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxMulticastFramesCounter_1 in AQ_MsmLineTxMulticastFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineTxMulticastFramesCounterRegister_HHD_msmLineTxMulticastFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxMulticastFramesCounter_1 in AQ_MsmLineTxMulticastFramesCounterRegister_HHD */ +#define word_AQ_MsmLineTxMulticastFramesCounterRegister_HHD_msmLineTxMulticastFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineTxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmLineTxBroadcastFramesCounterRegister_HHD_baseRegisterAddress 0x908C +/*! \brief MMD address of structure AQ_MsmLineTxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmLineTxBroadcastFramesCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxBroadcastFramesCounter_0 in AQ_MsmLineTxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmLineTxBroadcastFramesCounterRegister_HHD_msmLineTxBroadcastFramesCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxBroadcastFramesCounter_0 in AQ_MsmLineTxBroadcastFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineTxBroadcastFramesCounterRegister_HHD_msmLineTxBroadcastFramesCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxBroadcastFramesCounter_0 in AQ_MsmLineTxBroadcastFramesCounterRegister_HHD */ +#define word_AQ_MsmLineTxBroadcastFramesCounterRegister_HHD_msmLineTxBroadcastFramesCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxBroadcastFramesCounter_1 in AQ_MsmLineTxBroadcastFramesCounterRegister_HHD */ +#define AQ_MsmLineTxBroadcastFramesCounterRegister_HHD_msmLineTxBroadcastFramesCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxBroadcastFramesCounter_1 in AQ_MsmLineTxBroadcastFramesCounterRegister_HHD */ +#define bits_AQ_MsmLineTxBroadcastFramesCounterRegister_HHD_msmLineTxBroadcastFramesCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxBroadcastFramesCounter_1 in AQ_MsmLineTxBroadcastFramesCounterRegister_HHD */ +#define word_AQ_MsmLineTxBroadcastFramesCounterRegister_HHD_msmLineTxBroadcastFramesCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_MsmLineRxErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxErrorsCounterRegister_HHD_baseRegisterAddress 0x90C8 +/*! \brief MMD address of structure AQ_MsmLineRxErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxErrorsCounterRegister_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxErrorsCounter_0 in AQ_MsmLineRxErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxErrorsCounterRegister_HHD_msmLineRxErrorsCounter_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxErrorsCounter_0 in AQ_MsmLineRxErrorsCounterRegister_HHD */ +#define bits_AQ_MsmLineRxErrorsCounterRegister_HHD_msmLineRxErrorsCounter_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxErrorsCounter_0 in AQ_MsmLineRxErrorsCounterRegister_HHD */ +#define word_AQ_MsmLineRxErrorsCounterRegister_HHD_msmLineRxErrorsCounter_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxErrorsCounter_1 in AQ_MsmLineRxErrorsCounterRegister_HHD */ +#define AQ_MsmLineRxErrorsCounterRegister_HHD_msmLineRxErrorsCounter_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxErrorsCounter_1 in AQ_MsmLineRxErrorsCounterRegister_HHD */ +#define bits_AQ_MsmLineRxErrorsCounterRegister_HHD_msmLineRxErrorsCounter_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxErrorsCounter_1 in AQ_MsmLineRxErrorsCounterRegister_HHD */ +#define word_AQ_MsmLineRxErrorsCounterRegister_HHD_msmLineRxErrorsCounter_1 u1.word_1 + +/*! \brief Base register address of structure AQ_GlobalControl_HHD */ +#define AQ_GlobalControl_HHD_baseRegisterAddress 0xC000 +/*! \brief MMD address of structure AQ_GlobalControl_HHD */ +#define AQ_GlobalControl_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure upReset in AQ_GlobalControl_HHD */ +#define AQ_GlobalControl_HHD_upReset 1 +/*! \brief Preprocessor variable to relate field to bit position in structure upReset in AQ_GlobalControl_HHD */ +#define bits_AQ_GlobalControl_HHD_upReset u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure upReset in AQ_GlobalControl_HHD */ +#define word_AQ_GlobalControl_HHD_upReset u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure upRunStallOverride in AQ_GlobalControl_HHD */ +#define AQ_GlobalControl_HHD_upRunStallOverride 1 +/*! \brief Preprocessor variable to relate field to bit position in structure upRunStallOverride in AQ_GlobalControl_HHD */ +#define bits_AQ_GlobalControl_HHD_upRunStallOverride u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure upRunStallOverride in AQ_GlobalControl_HHD */ +#define word_AQ_GlobalControl_HHD_upRunStallOverride u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure upRunStall in AQ_GlobalControl_HHD */ +#define AQ_GlobalControl_HHD_upRunStall 1 +/*! \brief Preprocessor variable to relate field to bit position in structure upRunStall in AQ_GlobalControl_HHD */ +#define bits_AQ_GlobalControl_HHD_upRunStall u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure upRunStall in AQ_GlobalControl_HHD */ +#define word_AQ_GlobalControl_HHD_upRunStall u1.word_1 + +/*! \brief Base register address of structure AQ_GlobalResetControl_HHD */ +#define AQ_GlobalResetControl_HHD_baseRegisterAddress 0xC006 +/*! \brief MMD address of structure AQ_GlobalResetControl_HHD */ +#define AQ_GlobalResetControl_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure globalMMD_ResetDisable in AQ_GlobalResetControl_HHD */ +#define AQ_GlobalResetControl_HHD_globalMMD_ResetDisable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure globalMMD_ResetDisable in AQ_GlobalResetControl_HHD */ +#define bits_AQ_GlobalResetControl_HHD_globalMMD_ResetDisable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure globalMMD_ResetDisable in AQ_GlobalResetControl_HHD */ +#define word_AQ_GlobalResetControl_HHD_globalMMD_ResetDisable u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalDiagnosticProvisioning_HHD */ +#define AQ_GlobalDiagnosticProvisioning_HHD_baseRegisterAddress 0xC400 +/*! \brief MMD address of structure AQ_GlobalDiagnosticProvisioning_HHD */ +#define AQ_GlobalDiagnosticProvisioning_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure enableDiagnostics in AQ_GlobalDiagnosticProvisioning_HHD */ +#define AQ_GlobalDiagnosticProvisioning_HHD_enableDiagnostics 0 +/*! \brief Preprocessor variable to relate field to bit position in structure enableDiagnostics in AQ_GlobalDiagnosticProvisioning_HHD */ +#define bits_AQ_GlobalDiagnosticProvisioning_HHD_enableDiagnostics u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure enableDiagnostics in AQ_GlobalDiagnosticProvisioning_HHD */ +#define word_AQ_GlobalDiagnosticProvisioning_HHD_enableDiagnostics u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalThermalProvisioning_HHD */ +#define AQ_GlobalThermalProvisioning_HHD_baseRegisterAddress 0xC420 +/*! \brief MMD address of structure AQ_GlobalThermalProvisioning_HHD */ +#define AQ_GlobalThermalProvisioning_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure reserved_0 in AQ_GlobalThermalProvisioning_HHD */ +#define AQ_GlobalThermalProvisioning_HHD_reserved_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_0 in AQ_GlobalThermalProvisioning_HHD */ +#define bits_AQ_GlobalThermalProvisioning_HHD_reserved_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_0 in AQ_GlobalThermalProvisioning_HHD */ +#define word_AQ_GlobalThermalProvisioning_HHD_reserved_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure highTempFailureThreshold in AQ_GlobalThermalProvisioning_HHD */ +#define AQ_GlobalThermalProvisioning_HHD_highTempFailureThreshold 1 +/*! \brief Preprocessor variable to relate field to bit position in structure highTempFailureThreshold in AQ_GlobalThermalProvisioning_HHD */ +#define bits_AQ_GlobalThermalProvisioning_HHD_highTempFailureThreshold u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure highTempFailureThreshold in AQ_GlobalThermalProvisioning_HHD */ +#define word_AQ_GlobalThermalProvisioning_HHD_highTempFailureThreshold u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure lowTempFailureThreshold in AQ_GlobalThermalProvisioning_HHD */ +#define AQ_GlobalThermalProvisioning_HHD_lowTempFailureThreshold 2 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTempFailureThreshold in AQ_GlobalThermalProvisioning_HHD */ +#define bits_AQ_GlobalThermalProvisioning_HHD_lowTempFailureThreshold u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure lowTempFailureThreshold in AQ_GlobalThermalProvisioning_HHD */ +#define word_AQ_GlobalThermalProvisioning_HHD_lowTempFailureThreshold u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure highTempWarningThreshold in AQ_GlobalThermalProvisioning_HHD */ +#define AQ_GlobalThermalProvisioning_HHD_highTempWarningThreshold 3 +/*! \brief Preprocessor variable to relate field to bit position in structure highTempWarningThreshold in AQ_GlobalThermalProvisioning_HHD */ +#define bits_AQ_GlobalThermalProvisioning_HHD_highTempWarningThreshold u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure highTempWarningThreshold in AQ_GlobalThermalProvisioning_HHD */ +#define word_AQ_GlobalThermalProvisioning_HHD_highTempWarningThreshold u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure lowTempWarningThreshold in AQ_GlobalThermalProvisioning_HHD */ +#define AQ_GlobalThermalProvisioning_HHD_lowTempWarningThreshold 4 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTempWarningThreshold in AQ_GlobalThermalProvisioning_HHD */ +#define bits_AQ_GlobalThermalProvisioning_HHD_lowTempWarningThreshold u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure lowTempWarningThreshold in AQ_GlobalThermalProvisioning_HHD */ +#define word_AQ_GlobalThermalProvisioning_HHD_lowTempWarningThreshold u4.word_4 + +/*! \brief Base register address of structure AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_baseRegisterAddress 0xC430 +/*! \brief MMD address of structure AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioningC430 in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_reservedProvisioningC430 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioningC430 in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_reservedProvisioningC430 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioningC430 in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_reservedProvisioningC430 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_0ManualSet in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_0ManualSet 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0ManualSet in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_0ManualSet u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0ManualSet in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_0ManualSet u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_0_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_0_10Gb_sLinkEstablished 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_0_10Gb_sLinkEstablished u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_0_10Gb_sLinkEstablished u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_0_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_0_1Gb_sLinkEstablished 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_0_1Gb_sLinkEstablished u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_0_1Gb_sLinkEstablished u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_0_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_0_100Mb_sLinkEstablished 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_0_100Mb_sLinkEstablished u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_0_100Mb_sLinkEstablished u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_0Connecting in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_0Connecting 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0Connecting in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_0Connecting u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0Connecting in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_0Connecting u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_0ReceiveActivity in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_0ReceiveActivity 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0ReceiveActivity in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_0ReceiveActivity u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0ReceiveActivity in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_0ReceiveActivity u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_0TransmitActivity in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_0TransmitActivity 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0TransmitActivity in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_0TransmitActivity u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0TransmitActivity in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_0TransmitActivity u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure led_0ActivityStretch in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_0ActivityStretch 0 +/*! \brief Preprocessor variable to relate field to bit position in structure led_0ActivityStretch in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_0ActivityStretch u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure led_0ActivityStretch in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_0ActivityStretch u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioningC431 in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_reservedProvisioningC431 1 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioningC431 in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_reservedProvisioningC431 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioningC431 in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_reservedProvisioningC431 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_1ManualSet in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_1ManualSet 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1ManualSet in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_1ManualSet u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1ManualSet in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_1ManualSet u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_1_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_1_10Gb_sLinkEstablished 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_1_10Gb_sLinkEstablished u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_1_10Gb_sLinkEstablished u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_1_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_1_1Gb_sLinkEstablished 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_1_1Gb_sLinkEstablished u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_1_1Gb_sLinkEstablished u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_1_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_1_100Mb_sLinkEstablished 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_1_100Mb_sLinkEstablished u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_1_100Mb_sLinkEstablished u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_1Connecting in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_1Connecting 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1Connecting in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_1Connecting u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1Connecting in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_1Connecting u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_1ReceiveActivity in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_1ReceiveActivity 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1ReceiveActivity in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_1ReceiveActivity u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1ReceiveActivity in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_1ReceiveActivity u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_1TransmitActivity in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_1TransmitActivity 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1TransmitActivity in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_1TransmitActivity u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1TransmitActivity in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_1TransmitActivity u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure led_1ActivityStretch in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_1ActivityStretch 1 +/*! \brief Preprocessor variable to relate field to bit position in structure led_1ActivityStretch in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_1ActivityStretch u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure led_1ActivityStretch in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_1ActivityStretch u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioningC432 in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_reservedProvisioningC432 2 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioningC432 in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_reservedProvisioningC432 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioningC432 in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_reservedProvisioningC432 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_2ManualSet in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_2ManualSet 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2ManualSet in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_2ManualSet u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2ManualSet in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_2ManualSet u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_2_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_2_10Gb_sLinkEstablished 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_2_10Gb_sLinkEstablished u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_2_10Gb_sLinkEstablished u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_2_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_2_1Gb_sLinkEstablished 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_2_1Gb_sLinkEstablished u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_2_1Gb_sLinkEstablished u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_2_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_2_100Mb_sLinkEstablished 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_2_100Mb_sLinkEstablished u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_2_100Mb_sLinkEstablished u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_2Connecting in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_2Connecting 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2Connecting in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_2Connecting u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2Connecting in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_2Connecting u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_2ReceiveActivity in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_2ReceiveActivity 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2ReceiveActivity in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_2ReceiveActivity u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2ReceiveActivity in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_2ReceiveActivity u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_2TransmitActivity in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_2TransmitActivity 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2TransmitActivity in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_2TransmitActivity u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2TransmitActivity in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_2TransmitActivity u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure led_2ActivityStretch in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_led_2ActivityStretch 2 +/*! \brief Preprocessor variable to relate field to bit position in structure led_2ActivityStretch in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_led_2ActivityStretch u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure led_2ActivityStretch in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_led_2ActivityStretch u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure ledOperationMode in AQ_GlobalLedProvisioning_HHD */ +#define AQ_GlobalLedProvisioning_HHD_ledOperationMode 7 +/*! \brief Preprocessor variable to relate field to bit position in structure ledOperationMode in AQ_GlobalLedProvisioning_HHD */ +#define bits_AQ_GlobalLedProvisioning_HHD_ledOperationMode u7.bits_7 +/*! \brief Preprocessor variable to relate field to word position in structure ledOperationMode in AQ_GlobalLedProvisioning_HHD */ +#define word_AQ_GlobalLedProvisioning_HHD_ledOperationMode u7.word_7 + +/*! \brief Base register address of structure AQ_GlobalGeneralProvisioning_HHD */ +#define AQ_GlobalGeneralProvisioning_HHD_baseRegisterAddress 0xC440 +/*! \brief MMD address of structure AQ_GlobalGeneralProvisioning_HHD */ +#define AQ_GlobalGeneralProvisioning_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure mdioBroadcastModeEnable in AQ_GlobalGeneralProvisioning_HHD */ +#define AQ_GlobalGeneralProvisioning_HHD_mdioBroadcastModeEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioBroadcastModeEnable in AQ_GlobalGeneralProvisioning_HHD */ +#define bits_AQ_GlobalGeneralProvisioning_HHD_mdioBroadcastModeEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mdioBroadcastModeEnable in AQ_GlobalGeneralProvisioning_HHD */ +#define word_AQ_GlobalGeneralProvisioning_HHD_mdioBroadcastModeEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mdioReadMSW_FirstEnable in AQ_GlobalGeneralProvisioning_HHD */ +#define AQ_GlobalGeneralProvisioning_HHD_mdioReadMSW_FirstEnable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioReadMSW_FirstEnable in AQ_GlobalGeneralProvisioning_HHD */ +#define bits_AQ_GlobalGeneralProvisioning_HHD_mdioReadMSW_FirstEnable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mdioReadMSW_FirstEnable in AQ_GlobalGeneralProvisioning_HHD */ +#define word_AQ_GlobalGeneralProvisioning_HHD_mdioReadMSW_FirstEnable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mdioDriveConfiguration in AQ_GlobalGeneralProvisioning_HHD */ +#define AQ_GlobalGeneralProvisioning_HHD_mdioDriveConfiguration 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioDriveConfiguration in AQ_GlobalGeneralProvisioning_HHD */ +#define bits_AQ_GlobalGeneralProvisioning_HHD_mdioDriveConfiguration u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mdioDriveConfiguration in AQ_GlobalGeneralProvisioning_HHD */ +#define word_AQ_GlobalGeneralProvisioning_HHD_mdioDriveConfiguration u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mdioPreambleDetectionDisable in AQ_GlobalGeneralProvisioning_HHD */ +#define AQ_GlobalGeneralProvisioning_HHD_mdioPreambleDetectionDisable 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioPreambleDetectionDisable in AQ_GlobalGeneralProvisioning_HHD */ +#define bits_AQ_GlobalGeneralProvisioning_HHD_mdioPreambleDetectionDisable u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mdioPreambleDetectionDisable in AQ_GlobalGeneralProvisioning_HHD */ +#define word_AQ_GlobalGeneralProvisioning_HHD_mdioPreambleDetectionDisable u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure daisyChainReset in AQ_GlobalGeneralProvisioning_HHD */ +#define AQ_GlobalGeneralProvisioning_HHD_daisyChainReset 2 +/*! \brief Preprocessor variable to relate field to bit position in structure daisyChainReset in AQ_GlobalGeneralProvisioning_HHD */ +#define bits_AQ_GlobalGeneralProvisioning_HHD_daisyChainReset u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure daisyChainReset in AQ_GlobalGeneralProvisioning_HHD */ +#define word_AQ_GlobalGeneralProvisioning_HHD_daisyChainReset u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure mdioBroadcastAddressConfiguration in AQ_GlobalGeneralProvisioning_HHD */ +#define AQ_GlobalGeneralProvisioning_HHD_mdioBroadcastAddressConfiguration 7 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioBroadcastAddressConfiguration in AQ_GlobalGeneralProvisioning_HHD */ +#define bits_AQ_GlobalGeneralProvisioning_HHD_mdioBroadcastAddressConfiguration u7.bits_7 +/*! \brief Preprocessor variable to relate field to word position in structure mdioBroadcastAddressConfiguration in AQ_GlobalGeneralProvisioning_HHD */ +#define word_AQ_GlobalGeneralProvisioning_HHD_mdioBroadcastAddressConfiguration u7.word_7 +/*! \brief Preprocessor variable to relate field to word number in structure mdioPreambleLength in AQ_GlobalGeneralProvisioning_HHD */ +#define AQ_GlobalGeneralProvisioning_HHD_mdioPreambleLength 9 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioPreambleLength in AQ_GlobalGeneralProvisioning_HHD */ +#define bits_AQ_GlobalGeneralProvisioning_HHD_mdioPreambleLength u9.bits_9 +/*! \brief Preprocessor variable to relate field to word position in structure mdioPreambleLength in AQ_GlobalGeneralProvisioning_HHD */ +#define word_AQ_GlobalGeneralProvisioning_HHD_mdioPreambleLength u9.word_9 + +/*! \brief Base register address of structure AQ_GlobalNvrProvisioning_HHD */ +#define AQ_GlobalNvrProvisioning_HHD_baseRegisterAddress 0xC450 +/*! \brief MMD address of structure AQ_GlobalNvrProvisioning_HHD */ +#define AQ_GlobalNvrProvisioning_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure nvrDataLength in AQ_GlobalNvrProvisioning_HHD */ +#define AQ_GlobalNvrProvisioning_HHD_nvrDataLength 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrDataLength in AQ_GlobalNvrProvisioning_HHD */ +#define bits_AQ_GlobalNvrProvisioning_HHD_nvrDataLength u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrDataLength in AQ_GlobalNvrProvisioning_HHD */ +#define word_AQ_GlobalNvrProvisioning_HHD_nvrDataLength u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrDummyLength in AQ_GlobalNvrProvisioning_HHD */ +#define AQ_GlobalNvrProvisioning_HHD_nvrDummyLength 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrDummyLength in AQ_GlobalNvrProvisioning_HHD */ +#define bits_AQ_GlobalNvrProvisioning_HHD_nvrDummyLength u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrDummyLength in AQ_GlobalNvrProvisioning_HHD */ +#define word_AQ_GlobalNvrProvisioning_HHD_nvrDummyLength u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrAddressLength in AQ_GlobalNvrProvisioning_HHD */ +#define AQ_GlobalNvrProvisioning_HHD_nvrAddressLength 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrAddressLength in AQ_GlobalNvrProvisioning_HHD */ +#define bits_AQ_GlobalNvrProvisioning_HHD_nvrAddressLength u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nvrAddressLength in AQ_GlobalNvrProvisioning_HHD */ +#define word_AQ_GlobalNvrProvisioning_HHD_nvrAddressLength u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nvrAddressLengthOverride in AQ_GlobalNvrProvisioning_HHD */ +#define AQ_GlobalNvrProvisioning_HHD_nvrAddressLengthOverride 1 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrAddressLengthOverride in AQ_GlobalNvrProvisioning_HHD */ +#define bits_AQ_GlobalNvrProvisioning_HHD_nvrAddressLengthOverride u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure nvrAddressLengthOverride in AQ_GlobalNvrProvisioning_HHD */ +#define word_AQ_GlobalNvrProvisioning_HHD_nvrAddressLengthOverride u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure nvrClockDivide in AQ_GlobalNvrProvisioning_HHD */ +#define AQ_GlobalNvrProvisioning_HHD_nvrClockDivide 1 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrClockDivide in AQ_GlobalNvrProvisioning_HHD */ +#define bits_AQ_GlobalNvrProvisioning_HHD_nvrClockDivide u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure nvrClockDivide in AQ_GlobalNvrProvisioning_HHD */ +#define word_AQ_GlobalNvrProvisioning_HHD_nvrClockDivide u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure nvrDaisyChainClockDivideOverride in AQ_GlobalNvrProvisioning_HHD */ +#define AQ_GlobalNvrProvisioning_HHD_nvrDaisyChainClockDivideOverride 2 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrDaisyChainClockDivideOverride in AQ_GlobalNvrProvisioning_HHD */ +#define bits_AQ_GlobalNvrProvisioning_HHD_nvrDaisyChainClockDivideOverride u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure nvrDaisyChainClockDivideOverride in AQ_GlobalNvrProvisioning_HHD */ +#define word_AQ_GlobalNvrProvisioning_HHD_nvrDaisyChainClockDivideOverride u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure nvrDaisyChainDisable in AQ_GlobalNvrProvisioning_HHD */ +#define AQ_GlobalNvrProvisioning_HHD_nvrDaisyChainDisable 2 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrDaisyChainDisable in AQ_GlobalNvrProvisioning_HHD */ +#define bits_AQ_GlobalNvrProvisioning_HHD_nvrDaisyChainDisable u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure nvrDaisyChainDisable in AQ_GlobalNvrProvisioning_HHD */ +#define word_AQ_GlobalNvrProvisioning_HHD_nvrDaisyChainDisable u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure nvrReset in AQ_GlobalNvrProvisioning_HHD */ +#define AQ_GlobalNvrProvisioning_HHD_nvrReset 3 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrReset in AQ_GlobalNvrProvisioning_HHD */ +#define bits_AQ_GlobalNvrProvisioning_HHD_nvrReset u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure nvrReset in AQ_GlobalNvrProvisioning_HHD */ +#define word_AQ_GlobalNvrProvisioning_HHD_nvrReset u3.word_3 + +/*! \brief Base register address of structure AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_baseRegisterAddress 0xC470 +/*! \brief MMD address of structure AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure diagnosticsSelect in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_diagnosticsSelect 0 +/*! \brief Preprocessor variable to relate field to bit position in structure diagnosticsSelect in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_diagnosticsSelect u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure diagnosticsSelect in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_diagnosticsSelect u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure extendedMdiDiagnosticsSelect in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_extendedMdiDiagnosticsSelect 0 +/*! \brief Preprocessor variable to relate field to bit position in structure extendedMdiDiagnosticsSelect in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_extendedMdiDiagnosticsSelect u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure extendedMdiDiagnosticsSelect in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_extendedMdiDiagnosticsSelect u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure initiateCableDiagnostics in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_initiateCableDiagnostics 0 +/*! \brief Preprocessor variable to relate field to bit position in structure initiateCableDiagnostics in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_initiateCableDiagnostics u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure initiateCableDiagnostics in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_initiateCableDiagnostics u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure enableDaisy_chainHop_countOverride in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_enableDaisy_chainHop_countOverride 1 +/*! \brief Preprocessor variable to relate field to bit position in structure enableDaisy_chainHop_countOverride in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_enableDaisy_chainHop_countOverride u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure enableDaisy_chainHop_countOverride in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_enableDaisy_chainHop_countOverride u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure daisy_chainHop_countOverrideValue in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_daisy_chainHop_countOverrideValue 1 +/*! \brief Preprocessor variable to relate field to bit position in structure daisy_chainHop_countOverrideValue in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_daisy_chainHop_countOverrideValue u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure daisy_chainHop_countOverrideValue in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_daisy_chainHop_countOverrideValue u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure enableVddPowerSupplyTuning in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_enableVddPowerSupplyTuning 2 +/*! \brief Preprocessor variable to relate field to bit position in structure enableVddPowerSupplyTuning in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_enableVddPowerSupplyTuning u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure enableVddPowerSupplyTuning in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_enableVddPowerSupplyTuning u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure tunableExternalVddPowerSupplyPresent in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_tunableExternalVddPowerSupplyPresent 2 +/*! \brief Preprocessor variable to relate field to bit position in structure tunableExternalVddPowerSupplyPresent in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_tunableExternalVddPowerSupplyPresent u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure tunableExternalVddPowerSupplyPresent in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_tunableExternalVddPowerSupplyPresent u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure externalVddChangeRequest in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_externalVddChangeRequest 2 +/*! \brief Preprocessor variable to relate field to bit position in structure externalVddChangeRequest in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_externalVddChangeRequest u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure externalVddChangeRequest in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_externalVddChangeRequest u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure enableXenpakRegisterSpace in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_enableXenpakRegisterSpace 2 +/*! \brief Preprocessor variable to relate field to bit position in structure enableXenpakRegisterSpace in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_enableXenpakRegisterSpace u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure enableXenpakRegisterSpace in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_enableXenpakRegisterSpace u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure enable_5thChannelRfiCancellation in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_enable_5thChannelRfiCancellation 2 +/*! \brief Preprocessor variable to relate field to bit position in structure enable_5thChannelRfiCancellation in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_enable_5thChannelRfiCancellation u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure enable_5thChannelRfiCancellation in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_enable_5thChannelRfiCancellation u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure rateTransitionRequest in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_rateTransitionRequest 3 +/*! \brief Preprocessor variable to relate field to bit position in structure rateTransitionRequest in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_rateTransitionRequest u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure rateTransitionRequest in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_rateTransitionRequest u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure trainingSNR in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_trainingSNR 3 +/*! \brief Preprocessor variable to relate field to bit position in structure trainingSNR in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_trainingSNR u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure trainingSNR in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_trainingSNR u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioning_5 in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_5 4 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioning_5 in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_5 u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioning_5 in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_5 u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure nvrDaisyChainKickstart in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_nvrDaisyChainKickstart 4 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrDaisyChainKickstart in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_nvrDaisyChainKickstart u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure nvrDaisyChainKickstart in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_nvrDaisyChainKickstart u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure smartPower_downStatus in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_smartPower_downStatus 5 +/*! \brief Preprocessor variable to relate field to bit position in structure smartPower_downStatus in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_smartPower_downStatus u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure smartPower_downStatus in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_smartPower_downStatus u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioning_6 in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_6 5 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioning_6 in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_6 u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioning_6 in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_6 u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrLpDisableTimer in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_cfrLpDisableTimer 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrLpDisableTimer in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_cfrLpDisableTimer u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrLpDisableTimer in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_cfrLpDisableTimer u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrLpExtendedMaxwait in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_cfrLpExtendedMaxwait 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrLpExtendedMaxwait in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_cfrLpExtendedMaxwait u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrLpExtendedMaxwait in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_cfrLpExtendedMaxwait u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrLpTHP in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_cfrLpTHP 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrLpTHP in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_cfrLpTHP u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrLpTHP in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_cfrLpTHP u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrLpSupport in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_cfrLpSupport 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrLpSupport in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_cfrLpSupport u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrLpSupport in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_cfrLpSupport u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrDisableTimer in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_cfrDisableTimer 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrDisableTimer in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_cfrDisableTimer u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrDisableTimer in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_cfrDisableTimer u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrExtendedMaxwait in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_cfrExtendedMaxwait 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrExtendedMaxwait in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_cfrExtendedMaxwait u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrExtendedMaxwait in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_cfrExtendedMaxwait u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrTHP in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_cfrTHP 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrTHP in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_cfrTHP u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrTHP in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_cfrTHP u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure cfrSupport in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_cfrSupport 5 +/*! \brief Preprocessor variable to relate field to bit position in structure cfrSupport in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_cfrSupport u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure cfrSupport in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_cfrSupport u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure deadlockAvoidanceEnable in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_deadlockAvoidanceEnable 5 +/*! \brief Preprocessor variable to relate field to bit position in structure deadlockAvoidanceEnable in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_deadlockAvoidanceEnable u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure deadlockAvoidanceEnable in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_deadlockAvoidanceEnable u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure smartPower_downEnable in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_smartPower_downEnable 5 +/*! \brief Preprocessor variable to relate field to bit position in structure smartPower_downEnable in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_smartPower_downEnable u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure smartPower_downEnable in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_smartPower_downEnable u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure dteEnable in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_dteEnable 8 +/*! \brief Preprocessor variable to relate field to bit position in structure dteEnable in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_dteEnable u8.bits_8 +/*! \brief Preprocessor variable to relate field to word position in structure dteEnable in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_dteEnable u8.word_8 +/*! \brief Preprocessor variable to relate field to word number in structure dteDropReportingTimer in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_dteDropReportingTimer 8 +/*! \brief Preprocessor variable to relate field to bit position in structure dteDropReportingTimer in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_dteDropReportingTimer u8.bits_8 +/*! \brief Preprocessor variable to relate field to word position in structure dteDropReportingTimer in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_dteDropReportingTimer u8.word_8 +/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioning_9 in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_9 8 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioning_9 in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_9 u8.bits_8 +/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioning_9 in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_9 u8.word_8 +/*! \brief Preprocessor variable to relate field to word number in structure powerUpStall in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_powerUpStall 9 +/*! \brief Preprocessor variable to relate field to bit position in structure powerUpStall in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_powerUpStall u9.bits_9 +/*! \brief Preprocessor variable to relate field to word position in structure powerUpStall in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_powerUpStall u9.word_9 +/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioning_10 in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_10 9 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioning_10 in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_10 u9.bits_9 +/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioning_10 in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_10 u9.word_9 +/*! \brief Preprocessor variable to relate field to word number in structure loopbackControl in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_loopbackControl 10 +/*! \brief Preprocessor variable to relate field to bit position in structure loopbackControl in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_loopbackControl u10.bits_10 +/*! \brief Preprocessor variable to relate field to word position in structure loopbackControl in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_loopbackControl u10.word_10 +/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioning_11 in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_11 10 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioning_11 in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_11 u10.bits_10 +/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioning_11 in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_11 u10.word_10 +/*! \brief Preprocessor variable to relate field to word number in structure mdiPacketGeneration in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_mdiPacketGeneration 10 +/*! \brief Preprocessor variable to relate field to bit position in structure mdiPacketGeneration in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_mdiPacketGeneration u10.bits_10 +/*! \brief Preprocessor variable to relate field to word position in structure mdiPacketGeneration in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_mdiPacketGeneration u10.word_10 +/*! \brief Preprocessor variable to relate field to word number in structure look_asidePortPacketGeneration in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_look_asidePortPacketGeneration 10 +/*! \brief Preprocessor variable to relate field to bit position in structure look_asidePortPacketGeneration in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_look_asidePortPacketGeneration u10.bits_10 +/*! \brief Preprocessor variable to relate field to word position in structure look_asidePortPacketGeneration in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_look_asidePortPacketGeneration u10.word_10 +/*! \brief Preprocessor variable to relate field to word number in structure systemI_fPacketGeneration in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_systemI_fPacketGeneration 10 +/*! \brief Preprocessor variable to relate field to bit position in structure systemI_fPacketGeneration in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_systemI_fPacketGeneration u10.bits_10 +/*! \brief Preprocessor variable to relate field to word position in structure systemI_fPacketGeneration in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_systemI_fPacketGeneration u10.word_10 +/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioning_11a in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_11a 10 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioning_11a in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_11a u10.bits_10 +/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioning_11a in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_11a u10.word_10 +/*! \brief Preprocessor variable to relate field to word number in structure rate in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_rate 10 +/*! \brief Preprocessor variable to relate field to bit position in structure rate in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_rate u10.bits_10 +/*! \brief Preprocessor variable to relate field to word position in structure rate in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_rate u10.word_10 +/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioning_12 in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_12 11 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioning_12 in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_12 u11.bits_11 +/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioning_12 in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_12 u11.word_11 +/*! \brief Preprocessor variable to relate field to word number in structure enableMacsec in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_enableMacsec 11 +/*! \brief Preprocessor variable to relate field to bit position in structure enableMacsec in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_enableMacsec u11.bits_11 +/*! \brief Preprocessor variable to relate field to word position in structure enableMacsec in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_enableMacsec u11.word_11 +/*! \brief Preprocessor variable to relate field to word number in structure enablePtp in AQ_GlobalReservedProvisioning_HHD */ +#define AQ_GlobalReservedProvisioning_HHD_enablePtp 11 +/*! \brief Preprocessor variable to relate field to bit position in structure enablePtp in AQ_GlobalReservedProvisioning_HHD */ +#define bits_AQ_GlobalReservedProvisioning_HHD_enablePtp u11.bits_11 +/*! \brief Preprocessor variable to relate field to word position in structure enablePtp in AQ_GlobalReservedProvisioning_HHD */ +#define word_AQ_GlobalReservedProvisioning_HHD_enablePtp u11.word_11 + +/*! \brief Base register address of structure AQ_PifMailboxControl_HHD */ +#define AQ_PifMailboxControl_HHD_baseRegisterAddress 0xC47C +/*! \brief MMD address of structure AQ_PifMailboxControl_HHD */ +#define AQ_PifMailboxControl_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure pifMailboxAddress in AQ_PifMailboxControl_HHD */ +#define AQ_PifMailboxControl_HHD_pifMailboxAddress 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pifMailboxAddress in AQ_PifMailboxControl_HHD */ +#define bits_AQ_PifMailboxControl_HHD_pifMailboxAddress u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pifMailboxAddress in AQ_PifMailboxControl_HHD */ +#define word_AQ_PifMailboxControl_HHD_pifMailboxAddress u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pifMailboxData in AQ_PifMailboxControl_HHD */ +#define AQ_PifMailboxControl_HHD_pifMailboxData 1 +/*! \brief Preprocessor variable to relate field to bit position in structure pifMailboxData in AQ_PifMailboxControl_HHD */ +#define bits_AQ_PifMailboxControl_HHD_pifMailboxData u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure pifMailboxData in AQ_PifMailboxControl_HHD */ +#define word_AQ_PifMailboxControl_HHD_pifMailboxData u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure reservedPifMailboxControl_3 in AQ_PifMailboxControl_HHD */ +#define AQ_PifMailboxControl_HHD_reservedPifMailboxControl_3 2 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedPifMailboxControl_3 in AQ_PifMailboxControl_HHD */ +#define bits_AQ_PifMailboxControl_HHD_reservedPifMailboxControl_3 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure reservedPifMailboxControl_3 in AQ_PifMailboxControl_HHD */ +#define word_AQ_PifMailboxControl_HHD_reservedPifMailboxControl_3 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure pifMailboxCommandType in AQ_PifMailboxControl_HHD */ +#define AQ_PifMailboxControl_HHD_pifMailboxCommandType 2 +/*! \brief Preprocessor variable to relate field to bit position in structure pifMailboxCommandType in AQ_PifMailboxControl_HHD */ +#define bits_AQ_PifMailboxControl_HHD_pifMailboxCommandType u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure pifMailboxCommandType in AQ_PifMailboxControl_HHD */ +#define word_AQ_PifMailboxControl_HHD_pifMailboxCommandType u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure pifMailboxMMD in AQ_PifMailboxControl_HHD */ +#define AQ_PifMailboxControl_HHD_pifMailboxMMD 2 +/*! \brief Preprocessor variable to relate field to bit position in structure pifMailboxMMD in AQ_PifMailboxControl_HHD */ +#define bits_AQ_PifMailboxControl_HHD_pifMailboxMMD u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure pifMailboxMMD in AQ_PifMailboxControl_HHD */ +#define word_AQ_PifMailboxControl_HHD_pifMailboxMMD u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure reservedPifMailboxControl_4 in AQ_PifMailboxControl_HHD */ +#define AQ_PifMailboxControl_HHD_reservedPifMailboxControl_4 3 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedPifMailboxControl_4 in AQ_PifMailboxControl_HHD */ +#define bits_AQ_PifMailboxControl_HHD_reservedPifMailboxControl_4 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure reservedPifMailboxControl_4 in AQ_PifMailboxControl_HHD */ +#define word_AQ_PifMailboxControl_HHD_reservedPifMailboxControl_4 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure pifMailboxCommandStatus in AQ_PifMailboxControl_HHD */ +#define AQ_PifMailboxControl_HHD_pifMailboxCommandStatus 3 +/*! \brief Preprocessor variable to relate field to bit position in structure pifMailboxCommandStatus in AQ_PifMailboxControl_HHD */ +#define bits_AQ_PifMailboxControl_HHD_pifMailboxCommandStatus u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure pifMailboxCommandStatus in AQ_PifMailboxControl_HHD */ +#define word_AQ_PifMailboxControl_HHD_pifMailboxCommandStatus u3.word_3 + +/*! \brief Base register address of structure AQ_GlobalSmbus_0Provisioning_HHD */ +#define AQ_GlobalSmbus_0Provisioning_HHD_baseRegisterAddress 0xC485 +/*! \brief MMD address of structure AQ_GlobalSmbus_0Provisioning_HHD */ +#define AQ_GlobalSmbus_0Provisioning_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure smb_0SlaveAddress in AQ_GlobalSmbus_0Provisioning_HHD */ +#define AQ_GlobalSmbus_0Provisioning_HHD_smb_0SlaveAddress 0 +/*! \brief Preprocessor variable to relate field to bit position in structure smb_0SlaveAddress in AQ_GlobalSmbus_0Provisioning_HHD */ +#define bits_AQ_GlobalSmbus_0Provisioning_HHD_smb_0SlaveAddress u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure smb_0SlaveAddress in AQ_GlobalSmbus_0Provisioning_HHD */ +#define word_AQ_GlobalSmbus_0Provisioning_HHD_smb_0SlaveAddress u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalSmbus_1Provisioning_HHD */ +#define AQ_GlobalSmbus_1Provisioning_HHD_baseRegisterAddress 0xC495 +/*! \brief MMD address of structure AQ_GlobalSmbus_1Provisioning_HHD */ +#define AQ_GlobalSmbus_1Provisioning_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure smb_1SlaveAddress in AQ_GlobalSmbus_1Provisioning_HHD */ +#define AQ_GlobalSmbus_1Provisioning_HHD_smb_1SlaveAddress 0 +/*! \brief Preprocessor variable to relate field to bit position in structure smb_1SlaveAddress in AQ_GlobalSmbus_1Provisioning_HHD */ +#define bits_AQ_GlobalSmbus_1Provisioning_HHD_smb_1SlaveAddress u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure smb_1SlaveAddress in AQ_GlobalSmbus_1Provisioning_HHD */ +#define word_AQ_GlobalSmbus_1Provisioning_HHD_smb_1SlaveAddress u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalEeeProvisioning_HHD */ +#define AQ_GlobalEeeProvisioning_HHD_baseRegisterAddress 0xC4A0 +/*! \brief MMD address of structure AQ_GlobalEeeProvisioning_HHD */ +#define AQ_GlobalEeeProvisioning_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure eeeMode in AQ_GlobalEeeProvisioning_HHD */ +#define AQ_GlobalEeeProvisioning_HHD_eeeMode 0 +/*! \brief Preprocessor variable to relate field to bit position in structure eeeMode in AQ_GlobalEeeProvisioning_HHD */ +#define bits_AQ_GlobalEeeProvisioning_HHD_eeeMode u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure eeeMode in AQ_GlobalEeeProvisioning_HHD */ +#define word_AQ_GlobalEeeProvisioning_HHD_eeeMode u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_baseRegisterAddress 0xC800 +/*! \brief MMD address of structure AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure pairAStatus in AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_pairAStatus 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairAStatus in AQ_GlobalCableDiagnosticStatus_HHD */ +#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairAStatus u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairAStatus in AQ_GlobalCableDiagnosticStatus_HHD */ +#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairAStatus u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairBStatus in AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_pairBStatus 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairBStatus in AQ_GlobalCableDiagnosticStatus_HHD */ +#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairBStatus u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairBStatus in AQ_GlobalCableDiagnosticStatus_HHD */ +#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairBStatus u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairCStatus in AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_pairCStatus 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairCStatus in AQ_GlobalCableDiagnosticStatus_HHD */ +#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairCStatus u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairCStatus in AQ_GlobalCableDiagnosticStatus_HHD */ +#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairCStatus u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairDStatus in AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_pairDStatus 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairDStatus in AQ_GlobalCableDiagnosticStatus_HHD */ +#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairDStatus u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairDStatus in AQ_GlobalCableDiagnosticStatus_HHD */ +#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairDStatus u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_pairAReflection_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairAReflection_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairAReflection_1 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_pairAReflection_2 1 +/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairAReflection_2 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairAReflection_2 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure impulseResponseMSW in AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_impulseResponseMSW 2 +/*! \brief Preprocessor variable to relate field to bit position in structure impulseResponseMSW in AQ_GlobalCableDiagnosticStatus_HHD */ +#define bits_AQ_GlobalCableDiagnosticStatus_HHD_impulseResponseMSW u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure impulseResponseMSW in AQ_GlobalCableDiagnosticStatus_HHD */ +#define word_AQ_GlobalCableDiagnosticStatus_HHD_impulseResponseMSW u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_pairBReflection_1 3 +/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairBReflection_1 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairBReflection_1 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_pairBReflection_2 3 +/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairBReflection_2 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairBReflection_2 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure impulseResponseLSW in AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_impulseResponseLSW 4 +/*! \brief Preprocessor variable to relate field to bit position in structure impulseResponseLSW in AQ_GlobalCableDiagnosticStatus_HHD */ +#define bits_AQ_GlobalCableDiagnosticStatus_HHD_impulseResponseLSW u4.bits_4 +/*! \brief Preprocessor variable to relate field to word position in structure impulseResponseLSW in AQ_GlobalCableDiagnosticStatus_HHD */ +#define word_AQ_GlobalCableDiagnosticStatus_HHD_impulseResponseLSW u4.word_4 +/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_pairCReflection_1 5 +/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairCReflection_1 u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairCReflection_1 u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_pairCReflection_2 5 +/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairCReflection_2 u5.bits_5 +/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairCReflection_2 u5.word_5 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_1 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_reserved_1 6 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_1 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define bits_AQ_GlobalCableDiagnosticStatus_HHD_reserved_1 u6.bits_6 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_1 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define word_AQ_GlobalCableDiagnosticStatus_HHD_reserved_1 u6.word_6 +/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_pairDReflection_1 7 +/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairDReflection_1 u7.bits_7 +/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairDReflection_1 u7.word_7 +/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define AQ_GlobalCableDiagnosticStatus_HHD_pairDReflection_2 7 +/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairDReflection_2 u7.bits_7 +/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ +#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairDReflection_2 u7.word_7 + +/*! \brief Base register address of structure AQ_GlobalThermalStatus_HHD */ +#define AQ_GlobalThermalStatus_HHD_baseRegisterAddress 0xC820 +/*! \brief MMD address of structure AQ_GlobalThermalStatus_HHD */ +#define AQ_GlobalThermalStatus_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure temperature in AQ_GlobalThermalStatus_HHD */ +#define AQ_GlobalThermalStatus_HHD_temperature 0 +/*! \brief Preprocessor variable to relate field to bit position in structure temperature in AQ_GlobalThermalStatus_HHD */ +#define bits_AQ_GlobalThermalStatus_HHD_temperature u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure temperature in AQ_GlobalThermalStatus_HHD */ +#define word_AQ_GlobalThermalStatus_HHD_temperature u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure temperatureReady in AQ_GlobalThermalStatus_HHD */ +#define AQ_GlobalThermalStatus_HHD_temperatureReady 1 +/*! \brief Preprocessor variable to relate field to bit position in structure temperatureReady in AQ_GlobalThermalStatus_HHD */ +#define bits_AQ_GlobalThermalStatus_HHD_temperatureReady u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure temperatureReady in AQ_GlobalThermalStatus_HHD */ +#define word_AQ_GlobalThermalStatus_HHD_temperatureReady u1.word_1 + +/*! \brief Base register address of structure AQ_GlobalGeneralStatus_HHD */ +#define AQ_GlobalGeneralStatus_HHD_baseRegisterAddress 0xC830 +/*! \brief MMD address of structure AQ_GlobalGeneralStatus_HHD */ +#define AQ_GlobalGeneralStatus_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureFailureState in AQ_GlobalGeneralStatus_HHD */ +#define AQ_GlobalGeneralStatus_HHD_highTemperatureFailureState 0 +/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureFailureState in AQ_GlobalGeneralStatus_HHD */ +#define bits_AQ_GlobalGeneralStatus_HHD_highTemperatureFailureState u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureFailureState in AQ_GlobalGeneralStatus_HHD */ +#define word_AQ_GlobalGeneralStatus_HHD_highTemperatureFailureState u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureFailureState in AQ_GlobalGeneralStatus_HHD */ +#define AQ_GlobalGeneralStatus_HHD_lowTemperatureFailureState 0 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureFailureState in AQ_GlobalGeneralStatus_HHD */ +#define bits_AQ_GlobalGeneralStatus_HHD_lowTemperatureFailureState u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureFailureState in AQ_GlobalGeneralStatus_HHD */ +#define word_AQ_GlobalGeneralStatus_HHD_lowTemperatureFailureState u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureWarningState in AQ_GlobalGeneralStatus_HHD */ +#define AQ_GlobalGeneralStatus_HHD_highTemperatureWarningState 0 +/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureWarningState in AQ_GlobalGeneralStatus_HHD */ +#define bits_AQ_GlobalGeneralStatus_HHD_highTemperatureWarningState u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureWarningState in AQ_GlobalGeneralStatus_HHD */ +#define word_AQ_GlobalGeneralStatus_HHD_highTemperatureWarningState u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureWarningState in AQ_GlobalGeneralStatus_HHD */ +#define AQ_GlobalGeneralStatus_HHD_lowTemperatureWarningState 0 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureWarningState in AQ_GlobalGeneralStatus_HHD */ +#define bits_AQ_GlobalGeneralStatus_HHD_lowTemperatureWarningState u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureWarningState in AQ_GlobalGeneralStatus_HHD */ +#define word_AQ_GlobalGeneralStatus_HHD_lowTemperatureWarningState u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure processorIntensiveMdioOperationIn_Progress in AQ_GlobalGeneralStatus_HHD */ +#define AQ_GlobalGeneralStatus_HHD_processorIntensiveMdioOperationIn_Progress 1 +/*! \brief Preprocessor variable to relate field to bit position in structure processorIntensiveMdioOperationIn_Progress in AQ_GlobalGeneralStatus_HHD */ +#define bits_AQ_GlobalGeneralStatus_HHD_processorIntensiveMdioOperationIn_Progress u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure processorIntensiveMdioOperationIn_Progress in AQ_GlobalGeneralStatus_HHD */ +#define word_AQ_GlobalGeneralStatus_HHD_processorIntensiveMdioOperationIn_Progress u1.word_1 + +/*! \brief Base register address of structure AQ_GlobalPinStatus_HHD */ +#define AQ_GlobalPinStatus_HHD_baseRegisterAddress 0xC840 +/*! \brief MMD address of structure AQ_GlobalPinStatus_HHD */ +#define AQ_GlobalPinStatus_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure dcMasterN in AQ_GlobalPinStatus_HHD */ +#define AQ_GlobalPinStatus_HHD_dcMasterN 0 +/*! \brief Preprocessor variable to relate field to bit position in structure dcMasterN in AQ_GlobalPinStatus_HHD */ +#define bits_AQ_GlobalPinStatus_HHD_dcMasterN u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure dcMasterN in AQ_GlobalPinStatus_HHD */ +#define word_AQ_GlobalPinStatus_HHD_dcMasterN u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure packageConnectivity in AQ_GlobalPinStatus_HHD */ +#define AQ_GlobalPinStatus_HHD_packageConnectivity 0 +/*! \brief Preprocessor variable to relate field to bit position in structure packageConnectivity in AQ_GlobalPinStatus_HHD */ +#define bits_AQ_GlobalPinStatus_HHD_packageConnectivity u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure packageConnectivity in AQ_GlobalPinStatus_HHD */ +#define word_AQ_GlobalPinStatus_HHD_packageConnectivity u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure txEnable in AQ_GlobalPinStatus_HHD */ +#define AQ_GlobalPinStatus_HHD_txEnable 0 +/*! \brief Preprocessor variable to relate field to bit position in structure txEnable in AQ_GlobalPinStatus_HHD */ +#define bits_AQ_GlobalPinStatus_HHD_txEnable u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure txEnable in AQ_GlobalPinStatus_HHD */ +#define word_AQ_GlobalPinStatus_HHD_txEnable u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure ledPullupState in AQ_GlobalPinStatus_HHD */ +#define AQ_GlobalPinStatus_HHD_ledPullupState 0 +/*! \brief Preprocessor variable to relate field to bit position in structure ledPullupState in AQ_GlobalPinStatus_HHD */ +#define bits_AQ_GlobalPinStatus_HHD_ledPullupState u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure ledPullupState in AQ_GlobalPinStatus_HHD */ +#define word_AQ_GlobalPinStatus_HHD_ledPullupState u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalDaisyChainStatus_HHD */ +#define AQ_GlobalDaisyChainStatus_HHD_baseRegisterAddress 0xC842 +/*! \brief MMD address of structure AQ_GlobalDaisyChainStatus_HHD */ +#define AQ_GlobalDaisyChainStatus_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure rxDaisyChainCalculatedCrc in AQ_GlobalDaisyChainStatus_HHD */ +#define AQ_GlobalDaisyChainStatus_HHD_rxDaisyChainCalculatedCrc 0 +/*! \brief Preprocessor variable to relate field to bit position in structure rxDaisyChainCalculatedCrc in AQ_GlobalDaisyChainStatus_HHD */ +#define bits_AQ_GlobalDaisyChainStatus_HHD_rxDaisyChainCalculatedCrc u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure rxDaisyChainCalculatedCrc in AQ_GlobalDaisyChainStatus_HHD */ +#define word_AQ_GlobalDaisyChainStatus_HHD_rxDaisyChainCalculatedCrc u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalFaultMessage_HHD */ +#define AQ_GlobalFaultMessage_HHD_baseRegisterAddress 0xC850 +/*! \brief MMD address of structure AQ_GlobalFaultMessage_HHD */ +#define AQ_GlobalFaultMessage_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure message in AQ_GlobalFaultMessage_HHD */ +#define AQ_GlobalFaultMessage_HHD_message 0 +/*! \brief Preprocessor variable to relate field to bit position in structure message in AQ_GlobalFaultMessage_HHD */ +#define bits_AQ_GlobalFaultMessage_HHD_message u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure message in AQ_GlobalFaultMessage_HHD */ +#define word_AQ_GlobalFaultMessage_HHD_message u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_baseRegisterAddress 0xC880 +/*! \brief MMD address of structure AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure reserved_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_1 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_1 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_1 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_1 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_1 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_1 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_2 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_2 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_2 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_2 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_2 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_2 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_3 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_3 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_3 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_3 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_3 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_3 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_4 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_4 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_4 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_4 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_4 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_4 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_5 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_5 1 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_5 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_5 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_5 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_5 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_1 1 +/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_1 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_1 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_6 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_6 1 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_6 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_6 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_6 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_6 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_2 1 +/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_2 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_2 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_7 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_7 1 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_7 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_7 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_7 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_7 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_3 1 +/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_3 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_3 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_8 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_8 1 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_8 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_8 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_8 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_8 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_4 1 +/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_4 u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_4 u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_9 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_9 2 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_9 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_9 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_9 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_9 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_1 2 +/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_1 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_1 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_10 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_10 2 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_10 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_10 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_10 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_10 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_2 2 +/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_2 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_2 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_11 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_11 2 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_11 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_11 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_11 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_11 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_3 2 +/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_3 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_3 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_12 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_12 2 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_12 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_12 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_12 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_12 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_4 2 +/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_4 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_4 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_13 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_13 3 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_13 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_13 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_13 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_13 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_1 3 +/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_1 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_1 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_14 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_14 3 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_14 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_14 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_14 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_14 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_2 3 +/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_2 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_2 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_15 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_15 3 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_15 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_15 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_15 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_15 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_3 3 +/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_3 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_3 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure reserved_16 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_16 3 +/*! \brief Preprocessor variable to relate field to bit position in structure reserved_16 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_16 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure reserved_16 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_16 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_4 3 +/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_4 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ +#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_4 u3.word_3 + +/*! \brief Base register address of structure AQ_GlobalStatus_HHD */ +#define AQ_GlobalStatus_HHD_baseRegisterAddress 0xC884 +/*! \brief MMD address of structure AQ_GlobalStatus_HHD */ +#define AQ_GlobalStatus_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure reservedStatus_0 in AQ_GlobalStatus_HHD */ +#define AQ_GlobalStatus_HHD_reservedStatus_0 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedStatus_0 in AQ_GlobalStatus_HHD */ +#define bits_AQ_GlobalStatus_HHD_reservedStatus_0 u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedStatus_0 in AQ_GlobalStatus_HHD */ +#define word_AQ_GlobalStatus_HHD_reservedStatus_0 u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure cableLength in AQ_GlobalStatus_HHD */ +#define AQ_GlobalStatus_HHD_cableLength 0 +/*! \brief Preprocessor variable to relate field to bit position in structure cableLength in AQ_GlobalStatus_HHD */ +#define bits_AQ_GlobalStatus_HHD_cableLength u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure cableLength in AQ_GlobalStatus_HHD */ +#define word_AQ_GlobalStatus_HHD_cableLength u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_baseRegisterAddress 0xC885 +/*! \brief MMD address of structure AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure nearlySecondsMSW in AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_nearlySecondsMSW 0 +/*! \brief Preprocessor variable to relate field to bit position in structure nearlySecondsMSW in AQ_GlobalReservedStatus_HHD */ +#define bits_AQ_GlobalReservedStatus_HHD_nearlySecondsMSW u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure nearlySecondsMSW in AQ_GlobalReservedStatus_HHD */ +#define word_AQ_GlobalReservedStatus_HHD_nearlySecondsMSW u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure xenpakNvrStatus in AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_xenpakNvrStatus 0 +/*! \brief Preprocessor variable to relate field to bit position in structure xenpakNvrStatus in AQ_GlobalReservedStatus_HHD */ +#define bits_AQ_GlobalReservedStatus_HHD_xenpakNvrStatus u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure xenpakNvrStatus in AQ_GlobalReservedStatus_HHD */ +#define word_AQ_GlobalReservedStatus_HHD_xenpakNvrStatus u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure firmwareBuildID in AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_firmwareBuildID 0 +/*! \brief Preprocessor variable to relate field to bit position in structure firmwareBuildID in AQ_GlobalReservedStatus_HHD */ +#define bits_AQ_GlobalReservedStatus_HHD_firmwareBuildID u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure firmwareBuildID in AQ_GlobalReservedStatus_HHD */ +#define word_AQ_GlobalReservedStatus_HHD_firmwareBuildID u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure provisioningID in AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_provisioningID 0 +/*! \brief Preprocessor variable to relate field to bit position in structure provisioningID in AQ_GlobalReservedStatus_HHD */ +#define bits_AQ_GlobalReservedStatus_HHD_provisioningID u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure provisioningID in AQ_GlobalReservedStatus_HHD */ +#define word_AQ_GlobalReservedStatus_HHD_provisioningID u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure nearlySecondsLSW in AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_nearlySecondsLSW 1 +/*! \brief Preprocessor variable to relate field to bit position in structure nearlySecondsLSW in AQ_GlobalReservedStatus_HHD */ +#define bits_AQ_GlobalReservedStatus_HHD_nearlySecondsLSW u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure nearlySecondsLSW in AQ_GlobalReservedStatus_HHD */ +#define word_AQ_GlobalReservedStatus_HHD_nearlySecondsLSW u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure dteStatus in AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_dteStatus 2 +/*! \brief Preprocessor variable to relate field to bit position in structure dteStatus in AQ_GlobalReservedStatus_HHD */ +#define bits_AQ_GlobalReservedStatus_HHD_dteStatus u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure dteStatus in AQ_GlobalReservedStatus_HHD */ +#define word_AQ_GlobalReservedStatus_HHD_dteStatus u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure powerUpStallStatus in AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_powerUpStallStatus 2 +/*! \brief Preprocessor variable to relate field to bit position in structure powerUpStallStatus in AQ_GlobalReservedStatus_HHD */ +#define bits_AQ_GlobalReservedStatus_HHD_powerUpStallStatus u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure powerUpStallStatus in AQ_GlobalReservedStatus_HHD */ +#define word_AQ_GlobalReservedStatus_HHD_powerUpStallStatus u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure reservedStatus_3 in AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_reservedStatus_3 2 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedStatus_3 in AQ_GlobalReservedStatus_HHD */ +#define bits_AQ_GlobalReservedStatus_HHD_reservedStatus_3 u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure reservedStatus_3 in AQ_GlobalReservedStatus_HHD */ +#define word_AQ_GlobalReservedStatus_HHD_reservedStatus_3 u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure loopbackStatus in AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_loopbackStatus 3 +/*! \brief Preprocessor variable to relate field to bit position in structure loopbackStatus in AQ_GlobalReservedStatus_HHD */ +#define bits_AQ_GlobalReservedStatus_HHD_loopbackStatus u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure loopbackStatus in AQ_GlobalReservedStatus_HHD */ +#define word_AQ_GlobalReservedStatus_HHD_loopbackStatus u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure reservedStatus_4 in AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_reservedStatus_4 3 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedStatus_4 in AQ_GlobalReservedStatus_HHD */ +#define bits_AQ_GlobalReservedStatus_HHD_reservedStatus_4 u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure reservedStatus_4 in AQ_GlobalReservedStatus_HHD */ +#define word_AQ_GlobalReservedStatus_HHD_reservedStatus_4 u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure mdiPacketGenerationStatus in AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_mdiPacketGenerationStatus 3 +/*! \brief Preprocessor variable to relate field to bit position in structure mdiPacketGenerationStatus in AQ_GlobalReservedStatus_HHD */ +#define bits_AQ_GlobalReservedStatus_HHD_mdiPacketGenerationStatus u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure mdiPacketGenerationStatus in AQ_GlobalReservedStatus_HHD */ +#define word_AQ_GlobalReservedStatus_HHD_mdiPacketGenerationStatus u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure look_asidePortPacketGenerationStatus in AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_look_asidePortPacketGenerationStatus 3 +/*! \brief Preprocessor variable to relate field to bit position in structure look_asidePortPacketGenerationStatus in AQ_GlobalReservedStatus_HHD */ +#define bits_AQ_GlobalReservedStatus_HHD_look_asidePortPacketGenerationStatus u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure look_asidePortPacketGenerationStatus in AQ_GlobalReservedStatus_HHD */ +#define word_AQ_GlobalReservedStatus_HHD_look_asidePortPacketGenerationStatus u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure systemI_fPacketGenerationStatus in AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_systemI_fPacketGenerationStatus 3 +/*! \brief Preprocessor variable to relate field to bit position in structure systemI_fPacketGenerationStatus in AQ_GlobalReservedStatus_HHD */ +#define bits_AQ_GlobalReservedStatus_HHD_systemI_fPacketGenerationStatus u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure systemI_fPacketGenerationStatus in AQ_GlobalReservedStatus_HHD */ +#define word_AQ_GlobalReservedStatus_HHD_systemI_fPacketGenerationStatus u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure reservedStatus_4a in AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_reservedStatus_4a 3 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedStatus_4a in AQ_GlobalReservedStatus_HHD */ +#define bits_AQ_GlobalReservedStatus_HHD_reservedStatus_4a u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure reservedStatus_4a in AQ_GlobalReservedStatus_HHD */ +#define word_AQ_GlobalReservedStatus_HHD_reservedStatus_4a u3.word_3 +/*! \brief Preprocessor variable to relate field to word number in structure rate in AQ_GlobalReservedStatus_HHD */ +#define AQ_GlobalReservedStatus_HHD_rate 3 +/*! \brief Preprocessor variable to relate field to bit position in structure rate in AQ_GlobalReservedStatus_HHD */ +#define bits_AQ_GlobalReservedStatus_HHD_rate u3.bits_3 +/*! \brief Preprocessor variable to relate field to word position in structure rate in AQ_GlobalReservedStatus_HHD */ +#define word_AQ_GlobalReservedStatus_HHD_rate u3.word_3 + +/*! \brief Base register address of structure AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_baseRegisterAddress 0xCC00 +/*! \brief MMD address of structure AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureFailure in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_highTemperatureFailure 0 +/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureFailure in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_highTemperatureFailure u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureFailure in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_highTemperatureFailure u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureFailure in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_lowTemperatureFailure 0 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureFailure in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_lowTemperatureFailure u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureFailure in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_lowTemperatureFailure u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureWarning in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_highTemperatureWarning 0 +/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureWarning in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_highTemperatureWarning u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureWarning in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_highTemperatureWarning u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureWarning in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_lowTemperatureWarning 0 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureWarning in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_lowTemperatureWarning u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureWarning in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_lowTemperatureWarning u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure resetCompleted in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_resetCompleted 0 +/*! \brief Preprocessor variable to relate field to bit position in structure resetCompleted in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_resetCompleted u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure resetCompleted in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_resetCompleted u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure deviceFault in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_deviceFault 0 +/*! \brief Preprocessor variable to relate field to bit position in structure deviceFault in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_deviceFault u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure deviceFault in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_deviceFault u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmA in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_reservedAlarmA 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmA in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_reservedAlarmA u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmA in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_reservedAlarmA u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmB in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_reservedAlarmB 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmB in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_reservedAlarmB u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmB in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_reservedAlarmB u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmC in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_reservedAlarmC 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmC in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_reservedAlarmC u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmC in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_reservedAlarmC u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmD in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_reservedAlarmD 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmD in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_reservedAlarmD u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmD in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_reservedAlarmD u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure smartPower_downEntered in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_smartPower_downEntered 1 +/*! \brief Preprocessor variable to relate field to bit position in structure smartPower_downEntered in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_smartPower_downEntered u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure smartPower_downEntered in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_smartPower_downEntered u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure xenpakAlarm in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_xenpakAlarm 1 +/*! \brief Preprocessor variable to relate field to bit position in structure xenpakAlarm in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_xenpakAlarm u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure xenpakAlarm in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_xenpakAlarm u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure ipPhoneDetect in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_ipPhoneDetect 1 +/*! \brief Preprocessor variable to relate field to bit position in structure ipPhoneDetect in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_ipPhoneDetect u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure ipPhoneDetect in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_ipPhoneDetect u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure dteStatusChange in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_dteStatusChange 1 +/*! \brief Preprocessor variable to relate field to bit position in structure dteStatusChange in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_dteStatusChange u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure dteStatusChange in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_dteStatusChange u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarms in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_reservedAlarms 1 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarms in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_reservedAlarms u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarms in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_reservedAlarms u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mdioCommandHandlingOverflow in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_mdioCommandHandlingOverflow 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioCommandHandlingOverflow in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_mdioCommandHandlingOverflow u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mdioCommandHandlingOverflow in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_mdioCommandHandlingOverflow u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure nvrOperationComplete in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_nvrOperationComplete 2 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrOperationComplete in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_nvrOperationComplete u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure nvrOperationComplete in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_nvrOperationComplete u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure mailboxOperation_Complete in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_mailboxOperation_Complete 2 +/*! \brief Preprocessor variable to relate field to bit position in structure mailboxOperation_Complete in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_mailboxOperation_Complete u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure mailboxOperation_Complete in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_mailboxOperation_Complete u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure upDramParityError in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_upDramParityError 2 +/*! \brief Preprocessor variable to relate field to bit position in structure upDramParityError in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_upDramParityError u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure upDramParityError in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_upDramParityError u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure upIramParityError in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_upIramParityError 2 +/*! \brief Preprocessor variable to relate field to bit position in structure upIramParityError in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_upIramParityError u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure upIramParityError in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_upIramParityError u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure txEnableStateChange in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_txEnableStateChange 2 +/*! \brief Preprocessor variable to relate field to bit position in structure txEnableStateChange in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_txEnableStateChange u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure txEnableStateChange in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_txEnableStateChange u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure mdioMMD_Error in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_mdioMMD_Error 2 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioMMD_Error in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_mdioMMD_Error u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure mdioMMD_Error in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_mdioMMD_Error u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure mdioTimeoutError in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_mdioTimeoutError 2 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioTimeoutError in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_mdioTimeoutError u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure mdioTimeoutError in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_mdioTimeoutError u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure watchdogTimerAlarm in AQ_GlobalAlarms_HHD */ +#define AQ_GlobalAlarms_HHD_watchdogTimerAlarm 2 +/*! \brief Preprocessor variable to relate field to bit position in structure watchdogTimerAlarm in AQ_GlobalAlarms_HHD */ +#define bits_AQ_GlobalAlarms_HHD_watchdogTimerAlarm u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure watchdogTimerAlarm in AQ_GlobalAlarms_HHD */ +#define word_AQ_GlobalAlarms_HHD_watchdogTimerAlarm u2.word_2 + +/*! \brief Base register address of structure AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_baseRegisterAddress 0xD400 +/*! \brief MMD address of structure AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureFailureMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_highTemperatureFailureMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureFailureMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_highTemperatureFailureMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureFailureMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_highTemperatureFailureMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureFailureMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_lowTemperatureFailureMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureFailureMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_lowTemperatureFailureMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureFailureMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_lowTemperatureFailureMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureWarningMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_highTemperatureWarningMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureWarningMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_highTemperatureWarningMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureWarningMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_highTemperatureWarningMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureWarningMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_lowTemperatureWarningMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureWarningMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_lowTemperatureWarningMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureWarningMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_lowTemperatureWarningMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure resetCompletedMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_resetCompletedMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure resetCompletedMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_resetCompletedMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure resetCompletedMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_resetCompletedMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure deviceFaultMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_deviceFaultMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure deviceFaultMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_deviceFaultMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure deviceFaultMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_deviceFaultMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmAMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_reservedAlarmAMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmAMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_reservedAlarmAMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmAMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_reservedAlarmAMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmBMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_reservedAlarmBMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmBMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_reservedAlarmBMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmBMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_reservedAlarmBMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmCMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_reservedAlarmCMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmCMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_reservedAlarmCMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmCMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_reservedAlarmCMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmDMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_reservedAlarmDMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmDMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_reservedAlarmDMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmDMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_reservedAlarmDMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure smartPower_downEnteredMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_smartPower_downEnteredMask 1 +/*! \brief Preprocessor variable to relate field to bit position in structure smartPower_downEnteredMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_smartPower_downEnteredMask u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure smartPower_downEnteredMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_smartPower_downEnteredMask u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure xenpakAlarmMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_xenpakAlarmMask 1 +/*! \brief Preprocessor variable to relate field to bit position in structure xenpakAlarmMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_xenpakAlarmMask u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure xenpakAlarmMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_xenpakAlarmMask u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure ipPhoneDetectMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_ipPhoneDetectMask 1 +/*! \brief Preprocessor variable to relate field to bit position in structure ipPhoneDetectMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_ipPhoneDetectMask u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure ipPhoneDetectMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_ipPhoneDetectMask u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure dteStatusChangeMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_dteStatusChangeMask 1 +/*! \brief Preprocessor variable to relate field to bit position in structure dteStatusChangeMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_dteStatusChangeMask u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure dteStatusChangeMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_dteStatusChangeMask u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmsMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_reservedAlarmsMask 1 +/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmsMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_reservedAlarmsMask u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmsMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_reservedAlarmsMask u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure mdioCommandHandlingOverflowMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_mdioCommandHandlingOverflowMask 1 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioCommandHandlingOverflowMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_mdioCommandHandlingOverflowMask u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure mdioCommandHandlingOverflowMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_mdioCommandHandlingOverflowMask u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure diagnosticAlarmMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_diagnosticAlarmMask 1 +/*! \brief Preprocessor variable to relate field to bit position in structure diagnosticAlarmMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_diagnosticAlarmMask u1.bits_1 +/*! \brief Preprocessor variable to relate field to word position in structure diagnosticAlarmMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_diagnosticAlarmMask u1.word_1 +/*! \brief Preprocessor variable to relate field to word number in structure nvrOperationCompleteMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_nvrOperationCompleteMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure nvrOperationCompleteMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_nvrOperationCompleteMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure nvrOperationCompleteMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_nvrOperationCompleteMask u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure mailboxOperationCompleteMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_mailboxOperationCompleteMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure mailboxOperationCompleteMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_mailboxOperationCompleteMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure mailboxOperationCompleteMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_mailboxOperationCompleteMask u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure upDramParityErrorMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_upDramParityErrorMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure upDramParityErrorMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_upDramParityErrorMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure upDramParityErrorMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_upDramParityErrorMask u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure upIramParityErrorMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_upIramParityErrorMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure upIramParityErrorMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_upIramParityErrorMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure upIramParityErrorMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_upIramParityErrorMask u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure txEnableStateChangeMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_txEnableStateChangeMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure txEnableStateChangeMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_txEnableStateChangeMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure txEnableStateChangeMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_txEnableStateChangeMask u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure mdioMMD_ErrorMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_mdioMMD_ErrorMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioMMD_ErrorMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_mdioMMD_ErrorMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure mdioMMD_ErrorMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_mdioMMD_ErrorMask u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure mdioTimeoutErrorMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_mdioTimeoutErrorMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure mdioTimeoutErrorMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_mdioTimeoutErrorMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure mdioTimeoutErrorMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_mdioTimeoutErrorMask u2.word_2 +/*! \brief Preprocessor variable to relate field to word number in structure watchdogTimerAlarmMask in AQ_GlobalInterruptMask_HHD */ +#define AQ_GlobalInterruptMask_HHD_watchdogTimerAlarmMask 2 +/*! \brief Preprocessor variable to relate field to bit position in structure watchdogTimerAlarmMask in AQ_GlobalInterruptMask_HHD */ +#define bits_AQ_GlobalInterruptMask_HHD_watchdogTimerAlarmMask u2.bits_2 +/*! \brief Preprocessor variable to relate field to word position in structure watchdogTimerAlarmMask in AQ_GlobalInterruptMask_HHD */ +#define word_AQ_GlobalInterruptMask_HHD_watchdogTimerAlarmMask u2.word_2 + +/*! \brief Base register address of structure AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_baseRegisterAddress 0xFC00 +/*! \brief MMD address of structure AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure pmaStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_pmaStandardAlarm_1Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pmaStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_pmaStandardAlarm_1Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pmaStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_pmaStandardAlarm_1Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pmaStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_pmaStandardAlarm_2Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pmaStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_pmaStandardAlarm_2Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pmaStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_pmaStandardAlarm_2Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_pcsStandardAlarm_1Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_pcsStandardAlarm_1Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_pcsStandardAlarm_1Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_pcsStandardAlarm_2Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_pcsStandardAlarm_2Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_pcsStandardAlarm_2Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_3Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_pcsStandardAlarm_3Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_3Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_pcsStandardAlarm_3Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_3Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_pcsStandardAlarm_3Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure phyXS_StandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_phyXS_StandardAlarms_1Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_StandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_phyXS_StandardAlarms_1Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure phyXS_StandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_phyXS_StandardAlarms_1Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure phyXS_StandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_phyXS_StandardAlarms_2Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_StandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_phyXS_StandardAlarms_2Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure phyXS_StandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_phyXS_StandardAlarms_2Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationStandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_autonegotiationStandardAlarms_1Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationStandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_autonegotiationStandardAlarms_1Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationStandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_autonegotiationStandardAlarms_1Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationStandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_autonegotiationStandardAlarms_2Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationStandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_autonegotiationStandardAlarms_2Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationStandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_autonegotiationStandardAlarms_2Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure gbeStandardAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_gbeStandardAlarmsInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure gbeStandardAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_gbeStandardAlarmsInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure gbeStandardAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_gbeStandardAlarmsInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure allVendorAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_allVendorAlarmsInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure allVendorAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_allVendorAlarmsInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure allVendorAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_allVendorAlarmsInterrupt u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define AQ_GlobalChip_wideVendorInterruptFlags_HHD_baseRegisterAddress 0xFC01 +/*! \brief MMD address of structure AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define AQ_GlobalChip_wideVendorInterruptFlags_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure pmaVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define AQ_GlobalChip_wideVendorInterruptFlags_HHD_pmaVendorAlarmInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pmaVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_HHD_pmaVendorAlarmInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pmaVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_HHD_pmaVendorAlarmInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define AQ_GlobalChip_wideVendorInterruptFlags_HHD_pcsVendorAlarmInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_HHD_pcsVendorAlarmInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_HHD_pcsVendorAlarmInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure phyXS_VendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define AQ_GlobalChip_wideVendorInterruptFlags_HHD_phyXS_VendorAlarmInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_VendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_HHD_phyXS_VendorAlarmInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure phyXS_VendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_HHD_phyXS_VendorAlarmInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define AQ_GlobalChip_wideVendorInterruptFlags_HHD_autonegotiationVendorAlarmInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_HHD_autonegotiationVendorAlarmInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_HHD_autonegotiationVendorAlarmInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure gbeVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define AQ_GlobalChip_wideVendorInterruptFlags_HHD_gbeVendorAlarmInterrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure gbeVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_HHD_gbeVendorAlarmInterrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure gbeVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_HHD_gbeVendorAlarmInterrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_1Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define AQ_GlobalChip_wideVendorInterruptFlags_HHD_globalAlarms_1Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_1Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_HHD_globalAlarms_1Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_1Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_HHD_globalAlarms_1Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_2Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define AQ_GlobalChip_wideVendorInterruptFlags_HHD_globalAlarms_2Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_2Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_HHD_globalAlarms_2Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_2Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_HHD_globalAlarms_2Interrupt u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_3Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define AQ_GlobalChip_wideVendorInterruptFlags_HHD_globalAlarms_3Interrupt 0 +/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_3Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define bits_AQ_GlobalChip_wideVendorInterruptFlags_HHD_globalAlarms_3Interrupt u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_3Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ +#define word_AQ_GlobalChip_wideVendorInterruptFlags_HHD_globalAlarms_3Interrupt u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define AQ_GlobalInterruptChip_wideStandardMask_HHD_baseRegisterAddress 0xFF00 +/*! \brief MMD address of structure AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define AQ_GlobalInterruptChip_wideStandardMask_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure pmaStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define AQ_GlobalInterruptChip_wideStandardMask_HHD_pmaStandardAlarm_1InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pmaStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_pmaStandardAlarm_1InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pmaStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_pmaStandardAlarm_1InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pmaStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define AQ_GlobalInterruptChip_wideStandardMask_HHD_pmaStandardAlarm_2InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pmaStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_pmaStandardAlarm_2InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pmaStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_pmaStandardAlarm_2InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define AQ_GlobalInterruptChip_wideStandardMask_HHD_pcsStandardAlarm_1InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_pcsStandardAlarm_1InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_pcsStandardAlarm_1InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define AQ_GlobalInterruptChip_wideStandardMask_HHD_pcsStandardAlarm_2InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_pcsStandardAlarm_2InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_pcsStandardAlarm_2InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_3InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define AQ_GlobalInterruptChip_wideStandardMask_HHD_pcsStandardAlarm_3InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_3InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_pcsStandardAlarm_3InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_3InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_pcsStandardAlarm_3InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure phyXS_StandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define AQ_GlobalInterruptChip_wideStandardMask_HHD_phyXS_StandardAlarms_1InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_StandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_phyXS_StandardAlarms_1InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure phyXS_StandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_phyXS_StandardAlarms_1InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure phyXS_StandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define AQ_GlobalInterruptChip_wideStandardMask_HHD_phyXS_StandardAlarms_2InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_StandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_phyXS_StandardAlarms_2InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure phyXS_StandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_phyXS_StandardAlarms_2InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationStandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define AQ_GlobalInterruptChip_wideStandardMask_HHD_autonegotiationStandardAlarms_1InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationStandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_autonegotiationStandardAlarms_1InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationStandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_autonegotiationStandardAlarms_1InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationStandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define AQ_GlobalInterruptChip_wideStandardMask_HHD_autonegotiationStandardAlarms_2InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationStandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_autonegotiationStandardAlarms_2InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationStandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_autonegotiationStandardAlarms_2InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure gbeStandardAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define AQ_GlobalInterruptChip_wideStandardMask_HHD_gbeStandardAlarmsInterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure gbeStandardAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_gbeStandardAlarmsInterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure gbeStandardAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_gbeStandardAlarmsInterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure allVendorAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define AQ_GlobalInterruptChip_wideStandardMask_HHD_allVendorAlarmsInterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure allVendorAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_allVendorAlarmsInterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure allVendorAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_allVendorAlarmsInterruptMask u0.word_0 + +/*! \brief Base register address of structure AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define AQ_GlobalInterruptChip_wideVendorMask_HHD_baseRegisterAddress 0xFF01 +/*! \brief MMD address of structure AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define AQ_GlobalInterruptChip_wideVendorMask_HHD_mmdAddress 0x1E +/*! \brief Preprocessor variable to relate field to word number in structure pmaVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define AQ_GlobalInterruptChip_wideVendorMask_HHD_pmaVendorAlarmInterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pmaVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_HHD_pmaVendorAlarmInterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pmaVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_HHD_pmaVendorAlarmInterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure pcsVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define AQ_GlobalInterruptChip_wideVendorMask_HHD_pcsVendorAlarmInterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure pcsVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_HHD_pcsVendorAlarmInterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure pcsVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_HHD_pcsVendorAlarmInterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure phyXS_VendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define AQ_GlobalInterruptChip_wideVendorMask_HHD_phyXS_VendorAlarmInterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_VendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_HHD_phyXS_VendorAlarmInterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure phyXS_VendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_HHD_phyXS_VendorAlarmInterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define AQ_GlobalInterruptChip_wideVendorMask_HHD_autonegotiationVendorAlarmInterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_HHD_autonegotiationVendorAlarmInterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_HHD_autonegotiationVendorAlarmInterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure gbeVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define AQ_GlobalInterruptChip_wideVendorMask_HHD_gbeVendorAlarmInterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure gbeVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_HHD_gbeVendorAlarmInterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure gbeVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_HHD_gbeVendorAlarmInterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define AQ_GlobalInterruptChip_wideVendorMask_HHD_globalAlarms_1InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_HHD_globalAlarms_1InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_HHD_globalAlarms_1InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define AQ_GlobalInterruptChip_wideVendorMask_HHD_globalAlarms_2InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_HHD_globalAlarms_2InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_HHD_globalAlarms_2InterruptMask u0.word_0 +/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_3InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define AQ_GlobalInterruptChip_wideVendorMask_HHD_globalAlarms_3InterruptMask 0 +/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_3InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define bits_AQ_GlobalInterruptChip_wideVendorMask_HHD_globalAlarms_3InterruptMask u0.bits_0 +/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_3InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ +#define word_AQ_GlobalInterruptChip_wideVendorMask_HHD_globalAlarms_3InterruptMask u0.word_0 +#endif +/*@}*/ +/*@}*/ diff --git a/qca/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers_reversed.h b/qca/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers_reversed.h new file mode 100644 index 000000000..f6fe99831 --- /dev/null +++ b/qca/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers_reversed.h @@ -0,0 +1,12123 @@ +/*! \file +* This file contains the data structures and doxygen comments +* for the Global Registers block. + */ + +/*! \addtogroup registerMap + @{ +*/ + +/*! \defgroup Global_registers Global Registers +* This module contains the data structures and doxygen comments +* for the Global Registers block. + */ +/*********************************************************************** +* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +* +* $Date: 2014/04/08 $ +* +* $Label: $ +* +* Description: +* +* This file contains the c header structures for the registers contained in the Global Registers block. +* +* The bit fields in this structure are from MSbit to LSbit +* +***********************************************************************/ + + +/*@{*/ +#ifndef AQ_HHD_GLOBAL_REGS_HEADER +#define AQ_HHD_GLOBAL_REGS_HEADER + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Control 1: 1E.0000 */ +/* Global Standard Control 1: 1E.0000 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Control 1 */ + union + { + struct + { + /*! \brief 1E.0000.F R/WSC Soft Reset + AQ_GlobalStandardControl_1_HHD.u0.bits_0.softReset + + Default = 0x1 + + 1 = Global soft reset + 0 = Normal operation + + + Notes: + Resets the entire PHY. + Setting this bit initiates a global soft reset on all of the digital logic not including the microprocessor (i.e. microprocessor is not reset). Upon completion of the reset sequence, this bit is set back to 0by the microprocessor. Note this bit is OR'ed with the individual MMD resets. This bit should be set to 0 before setting the individual MMD resets. */ + unsigned int softReset : 1; /* 1E.0000.F R/WSC Default = 0x1 */ + /* 1 = Global soft reset + 0 = Normal operation + */ + unsigned int reserved0 : 3; + /*! \brief 1E.0000.B R/WPD Low Power + AQ_GlobalStandardControl_1_HHD.u0.bits_0.lowPower + + Provisionable Default = 0x0 + + 1 = Low-power mode + 0 = Normal operation + + + Notes: + A one written to this register causes the chip to enter low-power mode. This bit puts the entire chip in low-power mode, with only the MDIO and microprocessor functioning, and turns off the analog front-end: i.e. places it in high-impedance mode. Setting this bit also sets all of the Low Power bits in the other MMDs. */ + unsigned int lowPower : 1; /* 1E.0000.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Low-power mode + 0 = Normal operation + */ + unsigned int reserved1 : 11; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardControl_1_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Device Identifier: 1E.0002 */ +/* Global Standard Device Identifier: 1E.0002 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Device Identifier */ + union + { + struct + { + /*! \brief 1E.0002.F:0 RO Device ID MSW [1F:10] + AQ_GlobalStandardDeviceIdentifier_HHD.u0.bits_0.deviceIdMSW + + + + Bits 31 - 16 of Device ID + */ + unsigned int deviceIdMSW : 16; /* 1E.0002.F:0 RO */ + /* Bits 31 - 16 of Device ID */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Standard Device Identifier */ + union + { + struct + { + /*! \brief 1E.0003.F:0 RO Device ID LSW [F:0] + AQ_GlobalStandardDeviceIdentifier_HHD.u1.bits_1.deviceIdLSW + + + + Bits 15 - 0 of Device ID + */ + unsigned int deviceIdLSW : 16; /* 1E.0003.F:0 RO */ + /* Bits 15 - 0 of Device ID */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalStandardDeviceIdentifier_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Devices in Package: 1E.0005 */ +/* Global Standard Devices in Package: 1E.0005 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Devices in Package */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.0005.7 ROS Autonegotiation Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.autonegotiationPresent + + Default = 0x1 + + 1 = Autonegotiation is present in package + 0 = Autonegotiation is not present in package + + Notes: + This is always set to 1, as there is Autonegotiation in the PHY. */ + unsigned int autonegotiationPresent : 1; /* 1E.0005.7 ROS Default = 0x1 */ + /* 1 = Autonegotiation is present in package + 0 = Autonegotiation is not present in package */ + /*! \brief 1E.0005.6 ROS TC Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.tcPresent + + Default = 0x0 + + 1 = TC is present in package + 0 = TC is not present in package + + Notes: + This is always set to 0, as there is no TC functionality in the PHY. */ + unsigned int tcPresent : 1; /* 1E.0005.6 ROS Default = 0x0 */ + /* 1 = TC is present in package + 0 = TC is not present in package */ + /*! \brief 1E.0005.5 ROS DTE XS Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.dteXsPresent + + Default = 0x0 + + 1 = DTE XS is present in package + 0 = DTE XS is not present in package + + + Notes: + This is always set to 0, as there is no DTE XAUI interface in the PHY. */ + unsigned int dteXsPresent : 1; /* 1E.0005.5 ROS Default = 0x0 */ + /* 1 = DTE XS is present in package + 0 = DTE XS is not present in package + */ + /*! \brief 1E.0005.4 ROS PHY XS Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.phyXS_Present + + Default = 0x1 + + 1 = PHY XS is present in package + 0 = PHY XS is not present in package + + Notes: + This is always set to 1 as there is a PHY XS interface in the PHY. */ + unsigned int phyXS_Present : 1; /* 1E.0005.4 ROS Default = 0x1 */ + /* 1 = PHY XS is present in package + 0 = PHY XS is not present in package */ + /*! \brief 1E.0005.3 ROS PCS Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.pcsPresent + + Default = 0x1 + + 1 = PCS is present in package + 0 = PCS is not present in package + + Notes: + This is always set to 1 as there is PCS functionality in the PHY. */ + unsigned int pcsPresent : 1; /* 1E.0005.3 ROS Default = 0x1 */ + /* 1 = PCS is present in package + 0 = PCS is not present in package */ + /*! \brief 1E.0005.2 ROS WIS Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.wisPresent + + Default = 0x0 + + 1 = WIS is present in package + 0 = WIS is not present in package + + Notes: + This is always set to 0, as there is no WIS functionality in the PHY. */ + unsigned int wisPresent : 1; /* 1E.0005.2 ROS Default = 0x0 */ + /* 1 = WIS is present in package + 0 = WIS is not present in package */ + /*! \brief 1E.0005.1 ROS PMA Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.pmaPresent + + Default = 0x1 + + 1 = PMA is present in package + 0 = PMA is not present + + Notes: + This is always set to 1 as there is PMA functionality in the PHY. */ + unsigned int pmaPresent : 1; /* 1E.0005.1 ROS Default = 0x1 */ + /* 1 = PMA is present in package + 0 = PMA is not present */ + /*! \brief 1E.0005.0 ROS Clause 22 Registers Present + AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.clause_22RegistersPresent + + Default = 0x0 + + 1 = Clause 22 registers are present in package + 0 = Clause 22 registers are not present in package + + Notes: + This is always set to 0 in the PHY, as there are no Clause 22 registers in the device. */ + unsigned int clause_22RegistersPresent : 1; /* 1E.0005.0 ROS Default = 0x0 */ + /* 1 = Clause 22 registers are present in package + 0 = Clause 22 registers are not present in package */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardDevicesInPackage_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Vendor Devices in Package: 1E.0006 */ +/* Global Standard Vendor Devices in Package: 1E.0006 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Vendor Devices in Package */ + union + { + struct + { + /*! \brief 1E.0006.F ROS Vendor Specific Device #2 Present + AQ_GlobalStandardVendorDevicesInPackage_HHD.u0.bits_0.vendorSpecificDevice_2Present + + Default = 0x1 + + 1 = Device #2 is present in package + 0 = Device #2 is not present in package + + Notes: + This is always set to 1 as the PHY utilizes this device for the DSP PMA registers. */ + unsigned int vendorSpecificDevice_2Present : 1; /* 1E.0006.F ROS Default = 0x1 */ + /* 1 = Device #2 is present in package + 0 = Device #2 is not present in package */ + /*! \brief 1E.0006.E ROS Vendor Specific Device #1 Present + AQ_GlobalStandardVendorDevicesInPackage_HHD.u0.bits_0.vendorSpecificDevice_1Present + + Default = 0x1 + + 1 = Device #1 is present in package + 0 = Device #1 is not present in package + + Notes: + This is always set to 1 as the PHY utilizes this device for the global control registers. */ + unsigned int vendorSpecificDevice_1Present : 1; /* 1E.0006.E ROS Default = 0x1 */ + /* 1 = Device #1 is present in package + 0 = Device #1 is not present in package */ + /*! \brief 1E.0006.D ROS Clause 22 Extension Present + AQ_GlobalStandardVendorDevicesInPackage_HHD.u0.bits_0.clause_22ExtensionPresent + + Default = 0x1 + + 1 = Clause 22 Extension is present in package + 0 = Clause 22 Extension is not present in package + + Notes: + This is always set to 1 as the PHY utilizes this device for the GbE registers. */ + unsigned int clause_22ExtensionPresent : 1; /* 1E.0006.D ROS Default = 0x1 */ + /* 1 = Clause 22 Extension is present in package + 0 = Clause 22 Extension is not present in package */ + unsigned int reserved0 : 13; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardVendorDevicesInPackage_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Status 2: 1E.0008 */ +/* Global Standard Status 2: 1E.0008 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Status 2 */ + union + { + struct + { + /*! \brief 1E.0008.F:E ROS Device Present [1:0] + AQ_GlobalStandardStatus_2_HHD.u0.bits_0.devicePresent + + Default = 0x2 + + [F:E] + 0x3 = No device at this address + 0x2 = Device present at this address + 0x1 = No device at this address + 0x0 = No device at this address + + Notes: + This field is always set to 0x2, as the Global MMD resides here in the PHY. */ + unsigned int devicePresent : 2; /* 1E.0008.F:E ROS Default = 0x2 */ + /* [F:E] + 0x3 = No device at this address + 0x2 = Device present at this address + 0x1 = No device at this address + 0x0 = No device at this address */ + unsigned int reserved0 : 14; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStandardStatus_2_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Standard Package Identifier: 1E.000E */ +/* Global Standard Package Identifier: 1E.000E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Standard Package Identifier */ + union + { + struct + { + /*! \brief 1E.000E.F:0 RO Package ID MSW [1F:10] + AQ_GlobalStandardPackageIdentifier_HHD.u0.bits_0.packageIdMSW + + + + Bits 31- 16 of Package ID + */ + unsigned int packageIdMSW : 16; /* 1E.000E.F:0 RO */ + /* Bits 31- 16 of Package ID */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Standard Package Identifier */ + union + { + struct + { + /*! \brief 1E.000F.F:0 RO Package ID LSW [F:0] + AQ_GlobalStandardPackageIdentifier_HHD.u1.bits_1.packageIdLSW + + + + Bits 15 - 0 of Package ID + */ + unsigned int packageIdLSW : 16; /* 1E.000F.F:0 RO */ + /* Bits 15 - 0 of Package ID */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalStandardPackageIdentifier_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Firmware ID: 1E.0020 */ +/* Global Firmware ID: 1E.0020 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Firmware ID */ + union + { + struct + { + /*! \brief 1E.0020.F:8 RO Firmware Major Revision Number [7:0] + AQ_GlobalFirmwareID_HHD.u0.bits_0.firmwareMajorRevisionNumber + + + + [F:8] = Major revision number + + Notes: + + + The lower six bits of major and minor firmware revision are exchanged in autonegotiation when the PHYID message is sent. */ + unsigned int firmwareMajorRevisionNumber : 8; /* 1E.0020.F:8 RO */ + /* [F:8] = Major revision number */ + /*! \brief 1E.0020.7:0 RO Firmware Minor Revision Number [7:0] + AQ_GlobalFirmwareID_HHD.u0.bits_0.firmwareMinorRevisionNumber + + + + [7:0] = Minor revision number + + Notes: + + + The lower six bits of major and minor firmware revision are exchanged in autonegotiation when the PHYID message is sent. */ + unsigned int firmwareMinorRevisionNumber : 8; /* 1E.0020.7:0 RO */ + /* [7:0] = Minor revision number */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalFirmwareID_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global NVR Interface: 1E.0100 */ +/* Global NVR Interface: 1E.0100 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0100.F R/WSC NVR Execute Operation + AQ_GlobalNvrInterface_HHD.u0.bits_0.nvrExecuteOperation + + Default = 0x0 + + 1 = Start NVR Operation + + + + Notes: + When set to 1, the NVR operation will begin. Ensure that the uP is stalled using the See MCP Run Stall bit to ensure no NVR contention. */ + unsigned int nvrExecuteOperation : 1; /* 1E.0100.F R/WSC Default = 0x0 */ + /* 1 = Start NVR Operation + + */ + /*! \brief 1E.0100.E R/W NVR Write Mode + AQ_GlobalNvrInterface_HHD.u0.bits_0.nvrWriteMode + + Default = 0x0 + + 1 = Write to NVR + 0 = Read from NVR + + */ + unsigned int nvrWriteMode : 1; /* 1E.0100.E R/W Default = 0x0 */ + /* 1 = Write to NVR + 0 = Read from NVR + */ + /*! \brief 1E.0100.D R/W Freeze NVR CRC + AQ_GlobalNvrInterface_HHD.u0.bits_0.freezeNvrCrc + + Default = 0x0 + + 1 = Freeze NVR Mailbox CRC calculation register + + + Notes: + To prevent an erroneous answer, this bit should not be set at the same time the See NVR Operation Valid bit is set. */ + unsigned int freezeNvrCrc : 1; /* 1E.0100.D R/W Default = 0x0 */ + /* 1 = Freeze NVR Mailbox CRC calculation register + */ + /*! \brief 1E.0100.C R/WSC Reset NVR CRC + AQ_GlobalNvrInterface_HHD.u0.bits_0.resetNvrCrc + + Default = 0x0 + + 1 = Reset NVR Mailbox CRC calculation register + + + + Notes: + To prevent an erroneous answer, this bit should not be set at the same time the See NVR Operation Valid bit is set. */ + unsigned int resetNvrCrc : 1; /* 1E.0100.C R/WSC Default = 0x0 */ + /* 1 = Reset NVR Mailbox CRC calculation register + + */ + unsigned int reserved0 : 1; + /*! \brief 1E.0100.A R/W NVR Burst + AQ_GlobalNvrInterface_HHD.u0.bits_0.nvrBurst + + Default = 0x0 + + 0 = Single read or write operation of up to 4 bytes + 1 = Burst operation + + + Notes: + When this bit is set, the operation is a burst operation where more than 32-bits is read from the NVR or written to the NVR. This bit should be set to one until the last burst in the read or write operation, when it should be set to zero. It operates by gating the SPI clock, and not restarting it until new data is ready to be written, or the previous contents have been read. Each burst of data requires the NVR Execute Operation bit to be set to initiate the next phase. */ + unsigned int nvrBurst : 1; /* 1E.0100.A R/W Default = 0x0 */ + /* 0 = Single read or write operation of up to 4 bytes + 1 = Burst operation + */ + unsigned int reserved1 : 1; + /*! \brief 1E.0100.8 RO NVR Busy + AQ_GlobalNvrInterface_HHD.u0.bits_0.nvrBusy + + + + 1 = NVR is busy + 0 = NVR is ready + + + Notes: + When set to 1, the NVR is busy. A new NVR operation should not occur until this bit is 0. If the NVR clock is greater than 64/63 of the MDIO clock, this bit never needs to be polled when operating over the MDIO. */ + unsigned int nvrBusy : 1; /* 1E.0100.8 RO */ + /* 1 = NVR is busy + 0 = NVR is ready + */ + /*! \brief 1E.0100.7:0 R/W NVR Opcode [7:0] + AQ_GlobalNvrInterface_HHD.u0.bits_0.nvrOpcode + + Default = 0x03 + + NVR instruction opcode + + */ + unsigned int nvrOpcode : 8; /* 1E.0100.7:0 R/W Default = 0x03 */ + /* NVR instruction opcode + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0101.F:0 RO NVR Mailbox CRC [F:0] + AQ_GlobalNvrInterface_HHD.u1.bits_1.nvrMailboxCrc + + + + The running CRC-16 of everything passing through the NVR interface + + + Notes: + The CRC-16 over all data written or read through the NVR interface. The CRC-16 is calculated by dividing the data by: + x^16 + x^12 + x^5 + 1 */ + unsigned int nvrMailboxCrc : 16; /* 1E.0101.F:0 RO */ + /* The running CRC-16 of everything passing through the NVR interface + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global NVR Interface */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.0102.7:0 R/W NVR Address MSW [17:10] + AQ_GlobalNvrInterface_HHD.u2.bits_2.nvrAddressMSW + + Default = 0x00 + + NVR address MSW bits [17:10] + + + Notes: + The address of where to read and write from in the NVR. This is self-incrementing and will automatically increment after each read or write operation. The increment amount is based on the data length (i.e. increments by 4 if the data length is 4 bytes) */ + unsigned int nvrAddressMSW : 8; /* 1E.0102.7:0 R/W Default = 0x00 */ + /* NVR address MSW bits [17:10] + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0103.F:0 R/W NVR Address LSW [F:0] + AQ_GlobalNvrInterface_HHD.u3.bits_3.nvrAddressLSW + + Default = 0x0000 + + NVR address LSW bits [F:0] + + + Notes: + The address of where to read and write from in the NVR. This is self-incrementing and will automatically increment after each read or write operation. */ + unsigned int nvrAddressLSW : 16; /* 1E.0103.F:0 R/W Default = 0x0000 */ + /* NVR address LSW bits [F:0] + */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0104.F:0 R/W NVR Data MSW [1F:10] + AQ_GlobalNvrInterface_HHD.u4.bits_4.nvrDataMSW + + Default = 0x0000 + + NVR data MSW bits [1F:10] + + + Notes: + Data is stored and read-out from these registers in little-endian format for operations such as FLASH device ID, and for programming the processor. + + For instance the 64K Atmel device code reads out as two bytes 0x651F into the LSW register, whereas the datasheet indicates that 1F is the first byte read, followed by 65 as the second byte. + + To burst read and write these 4 bytes in the correct order (where DD is written to address x), they should be stored as: + + AA BB in the MSW + CC DD in the LSW. */ + unsigned int nvrDataMSW : 16; /* 1E.0104.F:0 R/W Default = 0x0000 */ + /* NVR data MSW bits [1F:10] + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global NVR Interface */ + union + { + struct + { + /*! \brief 1E.0105.F:0 R/W NVR Data LSW [F:0] + AQ_GlobalNvrInterface_HHD.u5.bits_5.nvrDataLSW + + Default = 0x0000 + + NVR data LSW bits [F:0] + + + Notes: + Data is stored and read-out from these registers in little-endian format for operations such as FLASH device ID, and for programming the processor. + + For instance the 64K Atmel device code reads out as two bytes 0x651F into the LSW register, whereas the datasheet indicates that 1F is the first byte read, followed by 65 as the second byte. + To burst read and write these 4 bytes in the correct order (where DD is written to address x), they should be stored as: + + AA BB in the MSW + CC DD in the LSW. */ + unsigned int nvrDataLSW : 16; /* 1E.0105.F:0 R/W Default = 0x0000 */ + /* NVR data LSW bits [F:0] + */ + } bits_5; + uint16_t word_5; + } u5; +} AQ_GlobalNvrInterface_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Mailbox Interface: 1E.0200 */ +/* Global Mailbox Interface: 1E.0200 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0200.F R/WSC uP Mailbox Execute Operation + AQ_GlobalMailboxInterface_HHD.u0.bits_0.upMailboxExecuteOperation + + Default = 0x0 + + 1 = Start of mailbox Operation + + + + Notes: + Indicates mailbox is loaded and ready */ + unsigned int upMailboxExecuteOperation : 1; /* 1E.0200.F R/WSC Default = 0x0 */ + /* 1 = Start of mailbox Operation + + */ + /*! \brief 1E.0200.E R/W uP Mailbox Write Mode + AQ_GlobalMailboxInterface_HHD.u0.bits_0.upMailboxWriteMode + + Default = 0x0 + + 1 = Write + 0 = Read + + + Notes: + Mailbox direction */ + unsigned int upMailboxWriteMode : 1; /* 1E.0200.E R/W Default = 0x0 */ + /* 1 = Write + 0 = Read + */ + unsigned int reserved0 : 1; + /*! \brief 1E.0200.C R/WSC Reset uP Mailbox CRC + AQ_GlobalMailboxInterface_HHD.u0.bits_0.resetUpMailboxCrc + + Default = 0x0 + + 1 = Reset uP mailbox CRC calculation register + + + */ + unsigned int resetUpMailboxCrc : 1; /* 1E.0200.C R/WSC Default = 0x0 */ + /* 1 = Reset uP mailbox CRC calculation register + + */ + unsigned int reserved1 : 3; + /*! \brief 1E.0200.8 RO uP Mailbox Busy + AQ_GlobalMailboxInterface_HHD.u0.bits_0.upMailboxBusy + + + + 1 = uP mailbox busy + 0 = uP mailbox ready + + + Notes: + In general the uP will respond within a few processor cycles to any PIF slave request, much faster than the MDIO. If the busy is asserted over multiple MDIO polling cycles, then a H/W error may have occurred and a Global S/W reset or uP reset is required. */ + unsigned int upMailboxBusy : 1; /* 1E.0200.8 RO */ + /* 1 = uP mailbox busy + 0 = uP mailbox ready + */ + unsigned int reserved2 : 8; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0201.F:0 RO uP Mailbox CRC [F:0] + AQ_GlobalMailboxInterface_HHD.u1.bits_1.upMailboxCrc + + + + The running CRC-16 of everything passing through the mailbox interface + + */ + unsigned int upMailboxCrc : 16; /* 1E.0201.F:0 RO */ + /* The running CRC-16 of everything passing through the mailbox interface + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0202.F:0 R/W uP Mailbox Address MSW [1F:10] + AQ_GlobalMailboxInterface_HHD.u2.bits_2.upMailboxAddressMSW + + Default = 0x0000 + + uP Mailbox MSW address + + + Notes: + The address of where to read and write from in the Microcontroller Mailbox. This is self-incrementing and automatically increments after each read and write operation.PHY */ + unsigned int upMailboxAddressMSW : 16; /* 1E.0202.F:0 R/W Default = 0x0000 */ + /* uP Mailbox MSW address + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0203.F:2 R/W uP Mailbox Address LSW [F:2] + AQ_GlobalMailboxInterface_HHD.u3.bits_3.upMailboxAddressLSW + + Default = 0x0000 + + uP LSW Mailbox address [F:2] + + + Notes: + The address of where to read and write from in the Microcontroller Mailbox. This is self-incrementing and automatically increments after each read and write operation.PHY */ + unsigned int upMailboxAddressLSW : 14; /* 1E.0203.F:2 R/W Default = 0x0000 */ + /* uP LSW Mailbox address [F:2] + */ + /*! \brief 1E.0203.1:0 RO uP Mailbox Address LSW Don't Care [1:0] + AQ_GlobalMailboxInterface_HHD.u3.bits_3.upMailboxAddressLSW_Don_tCare + + + + Least significant uP LSW Mailbox address bits [1:0] + + + Notes: + These bits are always set to 0 since each memory access is on a 4-byte boundary. */ + unsigned int upMailboxAddressLSW_Don_tCare : 2; /* 1E.0203.1:0 RO */ + /* Least significant uP LSW Mailbox address bits [1:0] + */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0204.F:0 R/W uP Mailbox Data MSW [1F:10] + AQ_GlobalMailboxInterface_HHD.u4.bits_4.upMailboxDataMSW + + Default = 0x0000 + + uP Mailbox data MSW + + */ + unsigned int upMailboxDataMSW : 16; /* 1E.0204.F:0 R/W Default = 0x0000 */ + /* uP Mailbox data MSW + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global Mailbox Interface */ + union + { + struct + { + /*! \brief 1E.0205.F:0 R/W uP Mailbox Data LSW [F:0] + AQ_GlobalMailboxInterface_HHD.u5.bits_5.upMailboxDataLSW + + Default = 0x0000 + + uP Mailbox data LSW + + */ + unsigned int upMailboxDataLSW : 16; /* 1E.0205.F:0 R/W Default = 0x0000 */ + /* uP Mailbox data LSW + */ + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of Global Mailbox Interface */ + union + { + struct + { + unsigned int reserved0 : 14; + /*! \brief 1E.0206.1 R/W uP Mailbox CRC Read Enable + AQ_GlobalMailboxInterface_HHD.u6.bits_6.upMailboxCrcReadEnable + + Default = 0x0 + + 1 = Update uP mailbox CRC on read + + */ + unsigned int upMailboxCrcReadEnable : 1; /* 1E.0206.1 R/W Default = 0x0 */ + /* 1 = Update uP mailbox CRC on read + */ + unsigned int reserved1 : 1; + } bits_6; + uint16_t word_6; + } u6; +} AQ_GlobalMailboxInterface_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Microprocessor Scratch Pad: 1E.0300 */ +/* Global Microprocessor Scratch Pad: 1E.0300 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Microprocessor Scratch Pad */ + union + { + struct + { + /*! \brief 1E.0300.F:0 R/W Scratch Pad 1[F:0] + AQ_GlobalMicroprocessorScratchPad_HHD.u0.bits_0.scratchPad_1 + + Default = 0x0000 + + General Purpose Scratch Pad + */ + unsigned int scratchPad_1 : 16; /* 1E.0300.F:0 R/W Default = 0x0000 */ + /* General Purpose Scratch Pad */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Microprocessor Scratch Pad */ + union + { + struct + { + /*! \brief 1E.0301.F:0 R/W Scratch Pad 2 [F:0] + AQ_GlobalMicroprocessorScratchPad_HHD.u1.bits_1.scratchPad_2 + + Default = 0x0000 + + General Purpose Scratch Pad + */ + unsigned int scratchPad_2 : 16; /* 1E.0301.F:0 R/W Default = 0x0000 */ + /* General Purpose Scratch Pad */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalMicroprocessorScratchPad_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress Control Register: 1E.5002 */ +/* MSS Egress Control Register: 1E.5002 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress Control Register */ + union + { + struct + { + /*! \brief 1E.5002.F:D R/W MSS Egress Ethertype Explicit SECTag LSB [2:0] + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressEthertypeExplicitSectagLsb + + Default = 0x0 + + Ethertype for explicit SECTag bits 2:0. + + + Notes: + Ethertype for explicity SECTag. */ + unsigned int mssEgressEthertypeExplicitSectagLsb : 3; /* 1E.5002.F:D R/W Default = 0x0 */ + /* Ethertype for explicit SECTag bits 2:0. + */ + /*! \brief 1E.5002.C R/W MSS Egress Clear Global Time + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressClearGlobalTime + + Default = 0x0 + + 1 = Clear global time + + + + Notes: + Clear global time. */ + unsigned int mssEgressClearGlobalTime : 1; /* 1E.5002.C R/W Default = 0x0 */ + /* 1 = Clear global time + + */ + /*! \brief 1E.5002.B R/W MSS Egress Clear Counter + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressClearCounter + + Default = 0x0 + + 1 = Clear all MIB counters + + + + Notes: + If this bit is set to 1, all MIB counters will be cleared. */ + unsigned int mssEgressClearCounter : 1; /* 1E.5002.B R/W Default = 0x0 */ + /* 1 = Clear all MIB counters + + */ + /*! \brief 1E.5002.A R/W MSS Egress High Priority + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressHighPriority + + Default = 0x0 + + 1 = MIB counter clear on read enable + + + + Notes: + If this bit is set to 1, read is given high priority and the MIB count value becomes 0 after read. */ + unsigned int mssEgressHighPriority : 1; /* 1E.5002.A R/W Default = 0x0 */ + /* 1 = MIB counter clear on read enable + + */ + /*! \brief 1E.5002.9 R/W MSS Egress ICV LSB 8 Bytes Enable + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressIcvLsb_8BytesEnable + + Default = 0x0 + + 1 = Use LSB + 0 = Use MSB + + + + Notes: + This bit selects MSB or LSB 8 bytes selection in the case where the ICV is 8 bytes. + 0 = MSB is used. */ + unsigned int mssEgressIcvLsb_8BytesEnable : 1; /* 1E.5002.9 R/W Default = 0x0 */ + /* 1 = Use LSB + 0 = Use MSB + + */ + /*! \brief 1E.5002.8 R/W MSS Egress External Classification Enable + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressExternalClassificationEnable + + Default = 0x0 + + 1 = Drop EGPRC miss packets + + + + Notes: + If set, internal classification is bypassed. Should always be set to 0. */ + unsigned int mssEgressExternalClassificationEnable : 1; /* 1E.5002.8 R/W Default = 0x0 */ + /* 1 = Drop EGPRC miss packets + + */ + /*! \brief 1E.5002.7 R/W MSS Egress Explicit SECTag Report Short Length + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressExplicitSectagReportShortLength + + Default = 0x0 + + Reserved + + + + Notes: + Unused. */ + unsigned int mssEgressExplicitSectagReportShortLength : 1; /* 1E.5002.7 R/W Default = 0x0 */ + /* Reserved + + */ + /*! \brief 1E.5002.6 R/W MSS Egress Drop Invalid SA/SC Packets + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressDropInvalidSa_scPackets + + Default = 0x0 + + 1 = Drop invalid SA/SC packets + + + + Notes: + Enables dropping of invalid SA/SC packets. */ + unsigned int mssEgressDropInvalidSa_scPackets : 1; /* 1E.5002.6 R/W Default = 0x0 */ + /* 1 = Drop invalid SA/SC packets + + */ + /*! \brief 1E.5002.5 R/W MSS Egress Unmatched Use SC 0 + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressUnmatchedUseSc_0 + + Default = 0x0 + + 1 = Use SC 0 for unmatched packets + 0 = Unmatched packets are uncontrolled packets + + + + Notes: + Use SC-Index 0 as default SC for unmatched packets. Otherwise the packets are treated as uncontrolled packets. */ + unsigned int mssEgressUnmatchedUseSc_0 : 1; /* 1E.5002.5 R/W Default = 0x0 */ + /* 1 = Use SC 0 for unmatched packets + 0 = Unmatched packets are uncontrolled packets + + */ + /*! \brief 1E.5002.4 R/W MSS Egresss GCM Test Mode + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgresssGcmTestMode + + Default = 0x0 + + 1 = Enable GCM test mode + + + + Notes: + Enables GCM test mode */ + unsigned int mssEgresssGcmTestMode : 1; /* 1E.5002.4 R/W Default = 0x0 */ + /* 1 = Enable GCM test mode + + */ + /*! \brief 1E.5002.3 R/W MSS Egress GCM Start + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressGcmStart + + Default = 0x0 + + 1 = Start GCM + + + + Notes: + Indicates GCM to start */ + unsigned int mssEgressGcmStart : 1; /* 1E.5002.3 R/W Default = 0x0 */ + /* 1 = Start GCM + + */ + /*! \brief 1E.5002.2 R/W MSS Egress Drop EGPRC LUT Miss + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressDropEgprcLutMiss + + Default = 0x0 + + 1 = Drop Egress Classification LUT miss packets + + + + Notes: + Decides whether Egress Pre-Security Classification (EGPRC) LUT miss packets are to be dropped */ + unsigned int mssEgressDropEgprcLutMiss : 1; /* 1E.5002.2 R/W Default = 0x0 */ + /* 1 = Drop Egress Classification LUT miss packets + + */ + /*! \brief 1E.5002.1 R/W MSS Egress Drop KAY Packet + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressDropKayPacket + + Default = 0x0 + + 1 = Drop KAY packet + + + Notes: + Decides whether KAY packets have to be dropped */ + unsigned int mssEgressDropKayPacket : 1; /* 1E.5002.1 R/W Default = 0x0 */ + /* 1 = Drop KAY packet + */ + /*! \brief 1E.5002.0 R/W MSS Egress Soft Reset + AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressSoftReset + + Default = 0x0 + + 1 = Soft reset + + + Notes: + S/W reset */ + unsigned int mssEgressSoftReset : 1; /* 1E.5002.0 R/W Default = 0x0 */ + /* 1 = Soft reset + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress Control Register */ + union + { + struct + { + unsigned int reserved0 : 3; + /*! \brief 1E.5003.C:0 R/W MSS Egress Ethertype Explicit SECTag MSB [F:3] + AQ_MssEgressControlRegister_HHD.u1.bits_1.mssEgressEthertypeExplicitSectagMsb + + Default = 0x0000 + + Ethertype for explicit SECTag bits 15:3. + + + Notes: + Ethertype for explicity SECTag. */ + unsigned int mssEgressEthertypeExplicitSectagMsb : 13; /* 1E.5003.C:0 R/W Default = 0x0000 */ + /* Ethertype for explicit SECTag bits 15:3. + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress VLAN TPID 0 Register: 1E.5008 */ +/* MSS Egress VLAN TPID 0 Register: 1E.5008 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress VLAN TPID 0 Register */ + union + { + struct + { + /*! \brief 1E.5008.F:0 R/W MSS Egress VLAN STag TPID [F:0] + AQ_MssEgressVlanTpid_0Register_HHD.u0.bits_0.mssEgressVlanStagTpid + + Default = 0x0000 + + STag TPID + + + Notes: + Service Tag Protocol Identifier (TPID) values to identify a VLAN tag. The " See SEC Egress VLAN CP Tag Parse STag " bit must be set to 1 for the incoming packet's TPID to be parsed. */ + unsigned int mssEgressVlanStagTpid : 16; /* 1E.5008.F:0 R/W Default = 0x0000 */ + /* STag TPID + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress VLAN TPID 0 Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressVlanTpid_0Register_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress VLAN TPID 1 Register: 1E.500A */ +/* MSS Egress VLAN TPID 1 Register: 1E.500A */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress VLAN TPID 1 Register */ + union + { + struct + { + /*! \brief 1E.500A.F:0 R/W MSS Egress VLAN QTag TPID [F:0] + AQ_MssEgressVlanTpid_1Register_HHD.u0.bits_0.mssEgressVlanQtagTpid + + Default = 0x0000 + + QTag TPID + + + Notes: + Customer Tag Protocol Identifier (TPID) values to identify a VLAN tag. The " See SEC Egress VLAN CP Tag Parse QTag " bit must be set to 1 for the incoming packet's TPID to be parsed. */ + unsigned int mssEgressVlanQtagTpid : 16; /* 1E.500A.F:0 R/W Default = 0x0000 */ + /* QTag TPID + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress VLAN TPID 1 Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressVlanTpid_1Register_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress VLAN Control Register: 1E.500C */ +/* MSS Egress VLAN Control Register: 1E.500C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress VLAN Control Register */ + union + { + struct + { + /*! \brief 1E.500C.F:0 R/W MSS Egress VLAN UP Map Table [F:0] + AQ_MssEgressVlanControlRegister_HHD.u0.bits_0.mssEgressVlanUpMapTable + + Default = 0x0000 + + UP Map table bits 15:0 + + + Notes: + If there is a customer TPID Tag match and no service TPID Tag match or the service TPID Tag match is disabled, the outer TAG's PCP is used to index into this map table to generate the packets user priority. + 2:0 : UP value for customer Tag PCP 0x0 + 5:3: UP value for customer Tag PCP 0x0 + 8:6 : UP value for customer Tag PCP 0x0 + 11:9 : UP value for customer Tag PCP 0x0 + 14:12 : UP value for customer Tag PCP 0x0 + 17:15 : UP value for customer Tag PCP 0x0 + 20:18 : UP value for customer Tag PCP 0x0 + 23:21 : UP value for customer Tag PCP 0x0 */ + unsigned int mssEgressVlanUpMapTable : 16; /* 1E.500C.F:0 R/W Default = 0x0000 */ + /* UP Map table bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress VLAN Control Register */ + union + { + struct + { + /*! \brief 1E.500D.F R/W MSS Egress VLAN QTag Parse Enable + AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanQtagParseEnable + + Default = 0x0 + + 1 = Enable VLAN QTag parsing + + + Notes: + Enable controlled port VLAN customer Tag parsing. When this bit is set to 1, the incoming packet's outer TPID will be compared with the configured " See SEC Egress TPID 1 [F:0] " for matching. If the " See SEC Egress VLAN CP Tag Parse QinQ " bit is set to1, this will also be used to compare the incoming packet's inner TPID. */ + unsigned int mssEgressVlanQtagParseEnable : 1; /* 1E.500D.F R/W Default = 0x0 */ + /* 1 = Enable VLAN QTag parsing + */ + /*! \brief 1E.500D.E R/W MSS Egress VLAN STag Parse Enable + AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanStagParseEnable + + Default = 0x0 + + 1 = Enable VLAN STag parsing + + + Notes: + Enable controlled port VLAN service Tag parsing. When this bit is set to 1, the incoming packets outer TPID will be compared with the configured " See SEC Egress TPID 0 [F:0] " for matching. If the " See SEC Egress VLAN CP Tag Parse QinQ " bit is set to1, this will also be used to compare the incoming packet's inner TPID. */ + unsigned int mssEgressVlanStagParseEnable : 1; /* 1E.500D.E R/W Default = 0x0 */ + /* 1 = Enable VLAN STag parsing + */ + /*! \brief 1E.500D.D R/W MSS Egress VLAN QinQ Parse Enable + AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanQinqParseEnable + + Default = 0x0 + + VLAN CP Tag Parse QinQ + + + Notes: + Enable controlled port VLAN QinQ Tag parsing. When this bit is set to 1 both the outer and inner VLAN Tags will be parsed. */ + unsigned int mssEgressVlanQinqParseEnable : 1; /* 1E.500D.D R/W Default = 0x0 */ + /* VLAN CP Tag Parse QinQ + */ + /*! \brief 1E.500D.C R/W MSS Egress VLAN QTag UP Parse Enable + AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanQtagUpParseEnable + + Default = 0x0 + + VLAN CP Tag QTag UP enable + + + Notes: + Enable controlled port customer VLAN customer Tag user priority field parsing. */ + unsigned int mssEgressVlanQtagUpParseEnable : 1; /* 1E.500D.C R/W Default = 0x0 */ + /* VLAN CP Tag QTag UP enable + */ + /*! \brief 1E.500D.B R/W MSS Egress VLAN STag UP Parse Enable + AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanStagUpParseEnable + + Default = 0x0 + + VLAN CP Tag STag UP enable + + + Notes: + Enable controlled port service VLAN service Tag user priority field parsing. */ + unsigned int mssEgressVlanStagUpParseEnable : 1; /* 1E.500D.B R/W Default = 0x0 */ + /* VLAN CP Tag STag UP enable + */ + /*! \brief 1E.500D.A:8 R/W MSS Egress VLAN UP Default [2:0] + AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanUpDefault + + Default = 0x0 + + UP default + + + Notes: + User priority default */ + unsigned int mssEgressVlanUpDefault : 3; /* 1E.500D.A:8 R/W Default = 0x0 */ + /* UP default + */ + /*! \brief 1E.500D.7:0 R/W MSS Egress VLAN UP Map Table MSW [17:10] + AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanUpMapTableMSW + + Default = 0x00 + + UP Map table bits 23:16 + + + Notes: + If there is a customer TPID Tag match and no service TPID Tag match or the service TPID Tag match is disabled, the outer TAG's PCP is used to index into this map table to generate the packets user priority. + 2:0 : UP value for customer Tag PCP 0x0 + 5:3: UP value for customer Tag PCP 0x0 + 8:6 : UP value for customer Tag PCP 0x0 + 11:9 : UP value for customer Tag PCP 0x0 + 14:12 : UP value for customer Tag PCP 0x0 + 17:15 : UP value for customer Tag PCP 0x0 + 20:18 : UP value for customer Tag PCP 0x0 + 23:21 : UP value for customer Tag PCP 0x0 */ + unsigned int mssEgressVlanUpMapTableMSW : 8; /* 1E.500D.7:0 R/W Default = 0x00 */ + /* UP Map table bits 23:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressVlanControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress PN Control Register: 1E.500E */ +/* MSS Egress PN Control Register: 1E.500E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress PN Control Register */ + union + { + struct + { + /*! \brief 1E.500E.F:0 R/W MSS Egress SA PN Threshold LSW [F:0] + AQ_MssEgressPnControlRegister_HHD.u0.bits_0.mssEgressSaPnThresholdLSW + + Default = 0x0000 + + PN threshold bits 15:0 + + + Notes: + Egress PN threshold to generate SA threshold interrupt. */ + unsigned int mssEgressSaPnThresholdLSW : 16; /* 1E.500E.F:0 R/W Default = 0x0000 */ + /* PN threshold bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress PN Control Register */ + union + { + struct + { + /*! \brief 1E.500F.F:0 R/W MSS Egress SA PN Threshold MSW [1F:10] + AQ_MssEgressPnControlRegister_HHD.u1.bits_1.mssEgressSaPnThresholdMSW + + Default = 0x0000 + + PN threshold bits 31:16 + + + Notes: + Egress PN threshold to generate SA threshold interrupt. */ + unsigned int mssEgressSaPnThresholdMSW : 16; /* 1E.500F.F:0 R/W Default = 0x0000 */ + /* PN threshold bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressPnControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress MTU Size Control Register: 1E.5010 */ +/* MSS Egress MTU Size Control Register: 1E.5010 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress MTU Size Control Register */ + union + { + struct + { + /*! \brief 1E.5010.F:0 R/W MSS Egress Controlled Packet MTU Size [F:0] + AQ_MssEgressMtuSizeControlRegister_HHD.u0.bits_0.mssEgressControlledPacketMtuSize + + Default = 0x05DC + + Maximum transmission unit for controlled packet + + + Notes: + Maximum transmission unit of controlled packet */ + unsigned int mssEgressControlledPacketMtuSize : 16; /* 1E.5010.F:0 R/W Default = 0x05DC */ + /* Maximum transmission unit for controlled packet + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress MTU Size Control Register */ + union + { + struct + { + /*! \brief 1E.5011.F:0 R/W MSS Egress Uncontrolled Packet MTU Size [F:0] + AQ_MssEgressMtuSizeControlRegister_HHD.u1.bits_1.mssEgressUncontrolledPacketMtuSize + + Default = 0x05DC + + Maximum transmission unit for uncontrolled packet + + + Notes: + Maximum transmission unit of uncontrolled packet */ + unsigned int mssEgressUncontrolledPacketMtuSize : 16; /* 1E.5011.F:0 R/W Default = 0x05DC */ + /* Maximum transmission unit for uncontrolled packet + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressMtuSizeControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress Interrupt Status Register: 1E.505C */ +/* MSS Egress Interrupt Status Register: 1E.505C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress Interrupt Status Register */ + union + { + struct + { + unsigned int reserved0 : 11; + /*! \brief 1E.505C.4 COW MSS Egress ECC Error Interrupt + AQ_MssEgressInterruptStatusRegister_HHD.u0.bits_0.mssEgressEccErrorInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when anyone of the memories detects an ECC error. */ + unsigned int mssEgressEccErrorInterrupt : 1; /* 1E.505C.4 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.505C.3 COW MSS Egress MIB Saturation Interrupt + AQ_MssEgressInterruptStatusRegister_HHD.u0.bits_0.mssEgressMibSaturationInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when the MIB counters reaches all ones saturation. */ + unsigned int mssEgressMibSaturationInterrupt : 1; /* 1E.505C.3 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.505C.2 COW MSS Egress SA Threshold Expired Interrupt + AQ_MssEgressInterruptStatusRegister_HHD.u0.bits_0.mssEgressSaThresholdExpiredInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when the SA PN reaches the See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . */ + unsigned int mssEgressSaThresholdExpiredInterrupt : 1; /* 1E.505C.2 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.505C.1 COW MSS Egress SA Expired Interrupt + AQ_MssEgressInterruptStatusRegister_HHD.u0.bits_0.mssEgressSaExpiredInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when the SA PN reaches all ones saturation. */ + unsigned int mssEgressSaExpiredInterrupt : 1; /* 1E.505C.1 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.505C.0 COW MSS Egress Master Interrupt + AQ_MssEgressInterruptStatusRegister_HHD.u0.bits_0.mssEgressMasterInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when any one of the above interrupt and the corresponding interrupt enable are both set. The interrupt enable for this bit must also be set for this bit to be set. */ + unsigned int mssEgressMasterInterrupt : 1; /* 1E.505C.0 COW Default = 0x0 */ + /* 1 = Interrupt + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress Interrupt Status Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressInterruptStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress Interrupt Mask Register: 1E.505E */ +/* MSS Egress Interrupt Mask Register: 1E.505E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress Interrupt Mask Register */ + union + { + struct + { + unsigned int reserved0 : 11; + /*! \brief 1E.505E.4 COW MSS Egress ECC Error Interrupt Enable + AQ_MssEgressInterruptMaskRegister_HHD.u0.bits_0.mssEgressEccErrorInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + + Notes: + Write to 1 to clear. This bit is set when anyone of the memories detects an ECC error. */ + unsigned int mssEgressEccErrorInterruptEnable : 1; /* 1E.505E.4 COW Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.505E.3 COW MSS Egress MIB Saturation Interrupt Enable + AQ_MssEgressInterruptMaskRegister_HHD.u0.bits_0.mssEgressMibSaturationInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + + Notes: + Write to 1 to clear. This bit is set when the MIB counters reaches all ones saturation. */ + unsigned int mssEgressMibSaturationInterruptEnable : 1; /* 1E.505E.3 COW Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.505E.2 COW MSS Egress SA Expired Threshold Interrupt Enable + AQ_MssEgressInterruptMaskRegister_HHD.u0.bits_0.mssEgressSaExpiredThresholdInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + + Notes: + Write to 1 to clear. This bit is set when the SA PN reaches the configured threshold See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . */ + unsigned int mssEgressSaExpiredThresholdInterruptEnable : 1; /* 1E.505E.2 COW Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.505E.1 COW MSS Egress SA Expired Interrupt Enable + AQ_MssEgressInterruptMaskRegister_HHD.u0.bits_0.mssEgressSaExpiredInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + + Notes: + Write to 1 to clear. This bit is set when the SA PN reaches all ones saturation. */ + unsigned int mssEgressSaExpiredInterruptEnable : 1; /* 1E.505E.1 COW Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.505E.0 COW MSS Egress Master Interrupt Enable + AQ_MssEgressInterruptMaskRegister_HHD.u0.bits_0.mssEgressMasterInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + + Notes: + Write to 1 to clear. */ + unsigned int mssEgressMasterInterruptEnable : 1; /* 1E.505E.0 COW Default = 0x0 */ + /* 1 = Interrupt enabled + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress Interrupt Mask Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressInterruptMaskRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress SA Expired Status Register: 1E.5060 */ +/* MSS Egress SA Expired Status Register: 1E.5060 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress SA Expired Status Register */ + union + { + struct + { + /*! \brief 1E.5060.F:0 COW MSS Egress SA Expired LSW [F:0] + AQ_MssEgressSaExpiredStatusRegister_HHD.u0.bits_0.mssEgressSaExpiredLSW + + Default = 0x0000 + + SA expired bits 15:0 + + + Notes: + Write these bits to 1 to clear. + When set, these bits identify the SA that has expired when the SA PN reaches all-ones saturation. */ + unsigned int mssEgressSaExpiredLSW : 16; /* 1E.5060.F:0 COW Default = 0x0000 */ + /* SA expired bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress SA Expired Status Register */ + union + { + struct + { + /*! \brief 1E.5061.F:0 COW MSS Egress SA Expired MSW [1F:10] + AQ_MssEgressSaExpiredStatusRegister_HHD.u1.bits_1.mssEgressSaExpiredMSW + + Default = 0x0000 + + SA expired bits 31:16 + + + Notes: + Write these bits to 1 to clear. + When set, these bits identify the SA that has expired when the SA PN reaches all-ones saturation. */ + unsigned int mssEgressSaExpiredMSW : 16; /* 1E.5061.F:0 COW Default = 0x0000 */ + /* SA expired bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressSaExpiredStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress SA Threshold Expired Status Register: 1E.5062 */ +/* MSS Egress SA Threshold Expired Status Register: 1E.5062 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress SA Threshold Expired Status Register */ + union + { + struct + { + /*! \brief 1E.5062.F:0 COW MSS Egress SA Threshold Expired LSW [F:0] + AQ_MssEgressSaThresholdExpiredStatusRegister_HHD.u0.bits_0.mssEgressSaThresholdExpiredLSW + + Default = 0x0000 + + SA threshold expired bits 15:0 + + + Notes: + Write these bits to 1 to clear. + When set, these bits identify the SA that has expired when the SA PN has reached the configured threshold See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . */ + unsigned int mssEgressSaThresholdExpiredLSW : 16; /* 1E.5062.F:0 COW Default = 0x0000 */ + /* SA threshold expired bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress SA Threshold Expired Status Register */ + union + { + struct + { + /*! \brief 1E.5063.F:0 COW MSS Egress SA Threshold Expired MSW [1F:10] + AQ_MssEgressSaThresholdExpiredStatusRegister_HHD.u1.bits_1.mssEgressSaThresholdExpiredMSW + + Default = 0x0000 + + SA threshold expired bits 31:16 + + + Notes: + Write these bits to 1 to clear. + When set, these bits identify the SA that has expired when the SA PN has reached the configured threshold See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . */ + unsigned int mssEgressSaThresholdExpiredMSW : 16; /* 1E.5063.F:0 COW Default = 0x0000 */ + /* SA threshold expired bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressSaThresholdExpiredStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress ECC Interrupt Status Register: 1E.5064 */ +/* MSS Egress ECC Interrupt Status Register: 1E.5064 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress ECC Interrupt Status Register */ + union + { + struct + { + /*! \brief 1E.5064.F:0 COW MSS Egress SA ECC Error Interrupt LSW [F:0] + AQ_MssEgressEccInterruptStatusRegister_HHD.u0.bits_0.mssEgressSaEccErrorInterruptLSW + + Default = 0x0000 + + SA ECC error interrupt bits 15:0 + + + Notes: + Write these bits to 1 to clear. + When set to 1, indicates that an ECC error occured for the SA. */ + unsigned int mssEgressSaEccErrorInterruptLSW : 16; /* 1E.5064.F:0 COW Default = 0x0000 */ + /* SA ECC error interrupt bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress ECC Interrupt Status Register */ + union + { + struct + { + /*! \brief 1E.5065.F:0 COW MSS Egress SA ECC Error Interrupt MSW [1F:10] + AQ_MssEgressEccInterruptStatusRegister_HHD.u1.bits_1.mssEgressSaEccErrorInterruptMSW + + Default = 0x0000 + + SA ECC error interrupt bits 31:16 + + + Notes: + Write these bits to 1 to clear. + When set to 1, indicates that an ECC error occured for the SA. */ + unsigned int mssEgressSaEccErrorInterruptMSW : 16; /* 1E.5065.F:0 COW Default = 0x0000 */ + /* SA ECC error interrupt bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssEgressEccInterruptStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress LUT Address Control Register: 1E.5080 */ +/* MSS Egress LUT Address Control Register: 1E.5080 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress LUT Address Control Register */ + union + { + struct + { + /*! \brief 1E.5080.F:C R/W MSS Egress LUT Select [3:0] + AQ_MssEgressLutAddressControlRegister_HHD.u0.bits_0.mssEgressLutSelect + + Default = 0x0 + + LUT select + + + Notes: + 0x0 : Egress MAC Control FIlter (CTLF) LUT + 0x1 : Egress Classification LUT + 0x2 : Egress SC/SA LUT + 0x3 : Egress SMIB */ + unsigned int mssEgressLutSelect : 4; /* 1E.5080.F:C R/W Default = 0x0 */ + /* LUT select + */ + unsigned int reserved0 : 3; + /*! \brief 1E.5080.8:0 R/W MSS Egress LUT Address [8:0] + AQ_MssEgressLutAddressControlRegister_HHD.u0.bits_0.mssEgressLutAddress + + Default = 0x000 + + LUT address + + */ + unsigned int mssEgressLutAddress : 9; /* 1E.5080.8:0 R/W Default = 0x000 */ + /* LUT address + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_MssEgressLutAddressControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress LUT Control Register: 1E.5081 */ +/* MSS Egress LUT Control Register: 1E.5081 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress LUT Control Register */ + union + { + struct + { + /*! \brief 1E.5081.F R/W MSS Egress LUT Write + AQ_MssEgressLutControlRegister_HHD.u0.bits_0.mssEgressLutWrite + + Default = 0x0 + + 1 = LUT write + + + Notes: + Setting this bit to 1, will write the LUT. This bit will automatically clear to 0. */ + unsigned int mssEgressLutWrite : 1; /* 1E.5081.F R/W Default = 0x0 */ + /* 1 = LUT write + */ + /*! \brief 1E.5081.E R/W MSS Egress LUT Read + AQ_MssEgressLutControlRegister_HHD.u0.bits_0.mssEgressLutRead + + Default = 0x0 + + 1 = LUT read + + + Notes: + Setting this bit to 1, will read the LUT. This bit will automatically clear to 0. */ + unsigned int mssEgressLutRead : 1; /* 1E.5081.E R/W Default = 0x0 */ + /* 1 = LUT read + */ + unsigned int reserved0 : 14; + } bits_0; + uint16_t word_0; + } u0; +} AQ_MssEgressLutControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Egress LUT Data Control Register: 1E.50A0 */ +/* MSS Egress LUT Data Control Register: 1E.50A0 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A0.F:0 R/W MSS Egress LUT Data 0 [F:0] + AQ_MssEgressLutDataControlRegister_HHD.u0.bits_0.mssEgressLutData_0 + + Default = 0x0000 + + LUT data bits 15:0 + + */ + unsigned int mssEgressLutData_0 : 16; /* 1E.50A0.F:0 R/W Default = 0x0000 */ + /* LUT data bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A1.F:0 R/W MSS Egress LUT Data 1 [1F:10] + AQ_MssEgressLutDataControlRegister_HHD.u1.bits_1.mssEgressLutData_1 + + Default = 0x0000 + + LUT data bits 31:16 + + */ + unsigned int mssEgressLutData_1 : 16; /* 1E.50A1.F:0 R/W Default = 0x0000 */ + /* LUT data bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A2.F:0 R/W MSS Egress LUT Data 2 [2F:20] + AQ_MssEgressLutDataControlRegister_HHD.u2.bits_2.mssEgressLutData_2 + + Default = 0x0000 + + LUT data bits 47:32 + + */ + unsigned int mssEgressLutData_2 : 16; /* 1E.50A2.F:0 R/W Default = 0x0000 */ + /* LUT data bits 47:32 + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A3.F:0 R/W MSS Egress LUT Data 3 [3F:30] + AQ_MssEgressLutDataControlRegister_HHD.u3.bits_3.mssEgressLutData_3 + + Default = 0x0000 + + LUT data bits 63:48 + + */ + unsigned int mssEgressLutData_3 : 16; /* 1E.50A3.F:0 R/W Default = 0x0000 */ + /* LUT data bits 63:48 + */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A4.F:0 R/W MSS Egress LUT Data 4 [4F:40] + AQ_MssEgressLutDataControlRegister_HHD.u4.bits_4.mssEgressLutData_4 + + Default = 0x0000 + + LUT data bits 79:64 + + */ + unsigned int mssEgressLutData_4 : 16; /* 1E.50A4.F:0 R/W Default = 0x0000 */ + /* LUT data bits 79:64 + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A5.F:0 R/W MSS Egress LUT Data 5 [5F:50] + AQ_MssEgressLutDataControlRegister_HHD.u5.bits_5.mssEgressLutData_5 + + Default = 0x0000 + + LUT data bits 95:80 + + */ + unsigned int mssEgressLutData_5 : 16; /* 1E.50A5.F:0 R/W Default = 0x0000 */ + /* LUT data bits 95:80 + */ + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A6.F:0 R/W MSS Egress LUT Data 6 [6F:60] + AQ_MssEgressLutDataControlRegister_HHD.u6.bits_6.mssEgressLutData_6 + + Default = 0x0000 + + LUT data bits 111:96 + + */ + unsigned int mssEgressLutData_6 : 16; /* 1E.50A6.F:0 R/W Default = 0x0000 */ + /* LUT data bits 111:96 + */ + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A7.F:0 R/W MSS Egress LUT Data 7 [7F:70] + AQ_MssEgressLutDataControlRegister_HHD.u7.bits_7.mssEgressLutData_7 + + Default = 0x0000 + + LUT data bits 127:112 + + */ + unsigned int mssEgressLutData_7 : 16; /* 1E.50A7.F:0 R/W Default = 0x0000 */ + /* LUT data bits 127:112 + */ + } bits_7; + uint16_t word_7; + } u7; + /*! \brief Union for bit and word level access of word 8 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A8.F:0 R/W MSS Egress LUT Data 8 [8F:80] + AQ_MssEgressLutDataControlRegister_HHD.u8.bits_8.mssEgressLutData_8 + + Default = 0x0000 + + LUT data bits 143:128 + + */ + unsigned int mssEgressLutData_8 : 16; /* 1E.50A8.F:0 R/W Default = 0x0000 */ + /* LUT data bits 143:128 + */ + } bits_8; + uint16_t word_8; + } u8; + /*! \brief Union for bit and word level access of word 9 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50A9.F:0 R/W MSS Egress LUT Data 9 [9F:90] + AQ_MssEgressLutDataControlRegister_HHD.u9.bits_9.mssEgressLutData_9 + + Default = 0x0000 + + LUT data bits 159:144 + + */ + unsigned int mssEgressLutData_9 : 16; /* 1E.50A9.F:0 R/W Default = 0x0000 */ + /* LUT data bits 159:144 + */ + } bits_9; + uint16_t word_9; + } u9; + /*! \brief Union for bit and word level access of word 10 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50AA.F:0 R/W MSS Egress LUT Data 10 [AF:A0] + AQ_MssEgressLutDataControlRegister_HHD.u10.bits_10.mssEgressLutData_10 + + Default = 0x0000 + + LUT data bits 175:160 + + */ + unsigned int mssEgressLutData_10 : 16; /* 1E.50AA.F:0 R/W Default = 0x0000 */ + /* LUT data bits 175:160 + */ + } bits_10; + uint16_t word_10; + } u10; + /*! \brief Union for bit and word level access of word 11 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50AB.F:0 R/W MSS Egress LUT Data 11 [BF:B0] + AQ_MssEgressLutDataControlRegister_HHD.u11.bits_11.mssEgressLutData_11 + + Default = 0x0000 + + LUT data bits 191:176 + + */ + unsigned int mssEgressLutData_11 : 16; /* 1E.50AB.F:0 R/W Default = 0x0000 */ + /* LUT data bits 191:176 + */ + } bits_11; + uint16_t word_11; + } u11; + /*! \brief Union for bit and word level access of word 12 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50AC.F:0 R/W MSS Egress LUT Data 12 [CF:C0] + AQ_MssEgressLutDataControlRegister_HHD.u12.bits_12.mssEgressLutData_12 + + Default = 0x0000 + + LUT data bits 207:192 + + */ + unsigned int mssEgressLutData_12 : 16; /* 1E.50AC.F:0 R/W Default = 0x0000 */ + /* LUT data bits 207:192 + */ + } bits_12; + uint16_t word_12; + } u12; + /*! \brief Union for bit and word level access of word 13 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50AD.F:0 R/W MSS Egress LUT Data 13 [DF:D0] + AQ_MssEgressLutDataControlRegister_HHD.u13.bits_13.mssEgressLutData_13 + + Default = 0x0000 + + LUT data bits 223:208 + + */ + unsigned int mssEgressLutData_13 : 16; /* 1E.50AD.F:0 R/W Default = 0x0000 */ + /* LUT data bits 223:208 + */ + } bits_13; + uint16_t word_13; + } u13; + /*! \brief Union for bit and word level access of word 14 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50AE.F:0 R/W MSS Egress LUT Data 14 [EF:E0] + AQ_MssEgressLutDataControlRegister_HHD.u14.bits_14.mssEgressLutData_14 + + Default = 0x0000 + + LUT data bits 239:224 + + */ + unsigned int mssEgressLutData_14 : 16; /* 1E.50AE.F:0 R/W Default = 0x0000 */ + /* LUT data bits 239:224 + */ + } bits_14; + uint16_t word_14; + } u14; + /*! \brief Union for bit and word level access of word 15 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50AF.F:0 R/W MSS Egress LUT Data 15 [FF:F0] + AQ_MssEgressLutDataControlRegister_HHD.u15.bits_15.mssEgressLutData_15 + + Default = 0x0000 + + LUT data bits 255:240 + + */ + unsigned int mssEgressLutData_15 : 16; /* 1E.50AF.F:0 R/W Default = 0x0000 */ + /* LUT data bits 255:240 + */ + } bits_15; + uint16_t word_15; + } u15; + /*! \brief Union for bit and word level access of word 16 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B0.F:0 R/W MSS Egress LUT Data 16 [10F:100] + AQ_MssEgressLutDataControlRegister_HHD.u16.bits_16.mssEgressLutData_16 + + Default = 0x0000 + + LUT data bits 271:256 + + */ + unsigned int mssEgressLutData_16 : 16; /* 1E.50B0.F:0 R/W Default = 0x0000 */ + /* LUT data bits 271:256 + */ + } bits_16; + uint16_t word_16; + } u16; + /*! \brief Union for bit and word level access of word 17 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B1.F:0 R/W MSS Egress LUT Data 17 [11F:110] + AQ_MssEgressLutDataControlRegister_HHD.u17.bits_17.mssEgressLutData_17 + + Default = 0x0000 + + LUT data bits 287:272 + + */ + unsigned int mssEgressLutData_17 : 16; /* 1E.50B1.F:0 R/W Default = 0x0000 */ + /* LUT data bits 287:272 + */ + } bits_17; + uint16_t word_17; + } u17; + /*! \brief Union for bit and word level access of word 18 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B2.F:0 R/W MSS Egress LUT Data 18 [12F:120] + AQ_MssEgressLutDataControlRegister_HHD.u18.bits_18.mssEgressLutData_18 + + Default = 0x0000 + + LUT data bits 303:288 + + */ + unsigned int mssEgressLutData_18 : 16; /* 1E.50B2.F:0 R/W Default = 0x0000 */ + /* LUT data bits 303:288 + */ + } bits_18; + uint16_t word_18; + } u18; + /*! \brief Union for bit and word level access of word 19 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B3.F:0 R/W MSS Egress LUT Data 19 [13F:130] + AQ_MssEgressLutDataControlRegister_HHD.u19.bits_19.mssEgressLutData_19 + + Default = 0x0000 + + LUT data bits 319:304 + + */ + unsigned int mssEgressLutData_19 : 16; /* 1E.50B3.F:0 R/W Default = 0x0000 */ + /* LUT data bits 319:304 + */ + } bits_19; + uint16_t word_19; + } u19; + /*! \brief Union for bit and word level access of word 20 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B4.F:0 R/W MSS Egress LUT Data 20 [14F:140] + AQ_MssEgressLutDataControlRegister_HHD.u20.bits_20.mssEgressLutData_20 + + Default = 0x0000 + + LUT data bits 335:320 + + */ + unsigned int mssEgressLutData_20 : 16; /* 1E.50B4.F:0 R/W Default = 0x0000 */ + /* LUT data bits 335:320 + */ + } bits_20; + uint16_t word_20; + } u20; + /*! \brief Union for bit and word level access of word 21 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B5.F:0 R/W MSS Egress LUT Data 21 [15F:150] + AQ_MssEgressLutDataControlRegister_HHD.u21.bits_21.mssEgressLutData_21 + + Default = 0x0000 + + LUT data bits 351:336 + + */ + unsigned int mssEgressLutData_21 : 16; /* 1E.50B5.F:0 R/W Default = 0x0000 */ + /* LUT data bits 351:336 + */ + } bits_21; + uint16_t word_21; + } u21; + /*! \brief Union for bit and word level access of word 22 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B6.F:0 R/W MSS Egress LUT Data 22 [16F:160] + AQ_MssEgressLutDataControlRegister_HHD.u22.bits_22.mssEgressLutData_22 + + Default = 0x0000 + + LUT data bits 367:352 + + */ + unsigned int mssEgressLutData_22 : 16; /* 1E.50B6.F:0 R/W Default = 0x0000 */ + /* LUT data bits 367:352 + */ + } bits_22; + uint16_t word_22; + } u22; + /*! \brief Union for bit and word level access of word 23 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B7.F:0 R/W MSS Egress LUT Data 23 [17F:170] + AQ_MssEgressLutDataControlRegister_HHD.u23.bits_23.mssEgressLutData_23 + + Default = 0x0000 + + LUT data bits 383:368 + + */ + unsigned int mssEgressLutData_23 : 16; /* 1E.50B7.F:0 R/W Default = 0x0000 */ + /* LUT data bits 383:368 + */ + } bits_23; + uint16_t word_23; + } u23; + /*! \brief Union for bit and word level access of word 24 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B8.F:0 R/W MSS Egress LUT Data 24 [18F:180] + AQ_MssEgressLutDataControlRegister_HHD.u24.bits_24.mssEgressLutData_24 + + Default = 0x0000 + + LUT data bits 399:384 + + */ + unsigned int mssEgressLutData_24 : 16; /* 1E.50B8.F:0 R/W Default = 0x0000 */ + /* LUT data bits 399:384 + */ + } bits_24; + uint16_t word_24; + } u24; + /*! \brief Union for bit and word level access of word 25 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50B9.F:0 R/W MSS Egress LUT Data 25 [19F:190] + AQ_MssEgressLutDataControlRegister_HHD.u25.bits_25.mssEgressLutData_25 + + Default = 0x0000 + + LUT data bits 415:400 + + */ + unsigned int mssEgressLutData_25 : 16; /* 1E.50B9.F:0 R/W Default = 0x0000 */ + /* LUT data bits 415:400 + */ + } bits_25; + uint16_t word_25; + } u25; + /*! \brief Union for bit and word level access of word 26 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50BA.F:0 R/W MSS Egress LUT Data 26 [1AF:1A0] + AQ_MssEgressLutDataControlRegister_HHD.u26.bits_26.mssEgressLutData_26 + + Default = 0x0000 + + LUT data bits 431:416 + + */ + unsigned int mssEgressLutData_26 : 16; /* 1E.50BA.F:0 R/W Default = 0x0000 */ + /* LUT data bits 431:416 + */ + } bits_26; + uint16_t word_26; + } u26; + /*! \brief Union for bit and word level access of word 27 of MSS Egress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.50BB.F:0 R/W MSS Egress LUT Data 27 [1BF:1B0] + AQ_MssEgressLutDataControlRegister_HHD.u27.bits_27.mssEgressLutData_27 + + Default = 0x0000 + + LUT data bits 447:432 + + */ + unsigned int mssEgressLutData_27 : 16; /* 1E.50BB.F:0 R/W Default = 0x0000 */ + /* LUT data bits 447:432 + */ + } bits_27; + uint16_t word_27; + } u27; +} AQ_MssEgressLutDataControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System General Control Register: 1E.6004 */ +/* MSM System General Control Register: 1E.6004 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System General Control Register */ + union + { + struct + { + /*! \brief 1E.6004.F R/W MSM System PHY Tx Enable + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemPhyTxEnable + + Default = 0x0 + + 1 = Enable PHY Tx + + + Notes: + Directly controls the phy_tx_ena pin. */ + unsigned int msmSystemPhyTxEnable : 1; /* 1E.6004.F R/W Default = 0x0 */ + /* 1 = Enable PHY Tx + */ + /*! \brief 1E.6004.E R/W MSM System Rx Error Discard + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemRxErrorDiscard + + Default = 0x0 + + 1 = Enable discard of received errored frames + + + Notes: + Rx errored frame discard enable. When set to 1, any frame received with an error is discarded and not forwarded to the client interface. When set to 0, errored frames are forwarded to the client interface with ff_rx_err asserted. + Note : It is recommended to set this bit to 1 only when store and forward operation is enabled (RX_SECTION_FULL TBD). */ + unsigned int msmSystemRxErrorDiscard : 1; /* 1E.6004.E R/W Default = 0x0 */ + /* 1 = Enable discard of received errored frames + */ + /*! \brief 1E.6004.D R/W MSM System Control Frame Enable + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemControlFrameEnable + + Default = 0x0 + + 1 = Control frame enabled + + + Notes: + MAC control frame enable. When set to 1, the MAC control frames with any Opcode other than 0x0001 are accepted and forwarded to the client interface. When set to 0, MAC control frames with any opcode other than 0x0001 are silently discarded. */ + unsigned int msmSystemControlFrameEnable : 1; /* 1E.6004.D R/W Default = 0x0 */ + /* 1 = Control frame enabled + */ + /*! \brief 1E.6004.C R/WSC MSM System Soft Reset + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemSoftReset + + Default = 0x0 + + 1 = Soft reset + + + Notes: + Software reset. Self clearing bit. When set to 1, resets all statistic counters as well as the Tx and Rx FIFOs. It should be issued after all traffic has been stopped as a result of clearing the Rx/Tx enable bits ( See MAC Rx Enable set to 0 and See MAC Tx Enable set to 0). + Note : Can lead to an Rx interface (ff_rx_xxx) violations to the application if the reset is issued in the middle of a receive frame transfer. Then the end of packet (assertion of ff_rx_eop) is lost and the application should be prepeared to handle this exception. */ + unsigned int msmSystemSoftReset : 1; /* 1E.6004.C R/WSC Default = 0x0 */ + /* 1 = Soft reset + */ + /*! \brief 1E.6004.B R/W MSM System Tx Pad Enable + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemTxPadEnable + + Default = 0x1 + + 1 = Enable Tx padding + + + Notes: + When set to 1, enable padding of frames in the Tx direction. When set to 0, the MAC will not extend frames from the application to a minimum of 64 bytes, allowing to transmit short frames (violating the Ethernet mimimum size requirements). Must be set to 1 for normal operation. */ + unsigned int msmSystemTxPadEnable : 1; /* 1E.6004.B R/W Default = 0x1 */ + /* 1 = Enable Tx padding + */ + /*! \brief 1E.6004.A R/W MSM System Tx CRC Append + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemTxCrcAppend + + Default = 0x0 + + 1 = Append Tx CRC + + + Notes: + Permanently enable CRC append on transmit. If set to 1, the Tx will append a CRC to all transmitted frames. If set to 0, CRC append can be controlled on a per frame basis using the pin ff_tx_crc. + This configuration bit is OR'ed with the external ff_tx_crc pin to instruct the Tx to append a CRC to transmitted frames. The ff_tx_crc pin is tied to 0. */ + unsigned int msmSystemTxCrcAppend : 1; /* 1E.6004.A R/W Default = 0x0 */ + /* 1 = Append Tx CRC + */ + /*! \brief 1E.6004.9 R/W MSM System Tx Address Insert Enable + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemTxAddressInsertEnable + + Default = 0x0 + + 1 = Insert Tx MAC source address + + + Notes: + Set the source MAC address on transmit. If set to 1, the MAC overwrites the source MAC address with the MAC programmed address in all transmitted frames. When set to 0, the source MAC address is transmitted unmodified from the MAC Tx client application. */ + unsigned int msmSystemTxAddressInsertEnable : 1; /* 1E.6004.9 R/W Default = 0x0 */ + /* 1 = Insert Tx MAC source address + */ + /*! \brief 1E.6004.8 R/W MSM System Pause Ignore + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemPauseIgnore + + Default = 0x0 + + 1 = Ignore pause frames + + + Notes: + Ignore pause frame quanta. If set to 1, received pause frames are ignored by the MAC. When set to 0, the Tx is stopped for the amount of time specified in the pause quanta received within the pause frame. */ + unsigned int msmSystemPauseIgnore : 1; /* 1E.6004.8 R/W Default = 0x0 */ + /* 1 = Ignore pause frames + */ + /*! \brief 1E.6004.7 R/W MSM System Pause Forward + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemPauseForward + + Default = 0x0 + + 1 = Enable Pause forwarding + + + Notes: + Terminate or forward pause frames. If set to 1, pause frames are forwarded to the user application. In normal mode, when set to 0, pause frames are terminated and discarded within the MAC. */ + unsigned int msmSystemPauseForward : 1; /* 1E.6004.7 R/W Default = 0x0 */ + /* 1 = Enable Pause forwarding + */ + /*! \brief 1E.6004.6 R/W MSM System CRC Forward + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemCrcForward + + Default = 0x0 + + 1 = Enable CRC forwarding + + + Notes: + When set to 1, the CRC field of the received frames is forwarded with the frame to the user application. If disabled, the CRC field is stripped from the frame. + Note : If padding is enabled ( See MAC PAD Enable set to 1), this bit is ignored. */ + unsigned int msmSystemCrcForward : 1; /* 1E.6004.6 R/W Default = 0x0 */ + /* 1 = Enable CRC forwarding + */ + /*! \brief 1E.6004.5 R/W MSM System PAD Enable + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemPadEnable + + Default = 0x0 + + 1 = Enable frame padding removal on Rx + + + Notes: + When set to 1, enable frame padding removal on the Rx path. If enabled, padding is removed before the frame is transferred to the MAC client application. If disabled, no padding is removed on the Rx by the MAC. + Note : On Tx, the MAC always adds padding as required. */ + unsigned int msmSystemPadEnable : 1; /* 1E.6004.5 R/W Default = 0x0 */ + /* 1 = Enable frame padding removal on Rx + */ + /*! \brief 1E.6004.4 R/W MSM System Promiscuous Mode + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemPromiscuousMode + + Default = 0x0 + + 1 = Promiscuous mode + + + Notes: + When set to 1, all frames are received without any MAC address filtering. */ + unsigned int msmSystemPromiscuousMode : 1; /* 1E.6004.4 R/W Default = 0x0 */ + /* 1 = Promiscuous mode + */ + /*! \brief 1E.6004.3 R/W MSM System WAN Mode + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemWanMode + + Default = 0x0 + + 1 = WAN mode + 0 = LAN mode + + + Notes: + WAN mode enable. Sets WAN mode when set to 1 and LAN mode when set to 0. Note: When changing the mode, verifiy correct setting of the Tx IPG. */ + unsigned int msmSystemWanMode : 1; /* 1E.6004.3 R/W Default = 0x0 */ + /* 1 = WAN mode + 0 = LAN mode + */ + unsigned int reserved0 : 1; + /*! \brief 1E.6004.1 R/W MSM System Rx Enable + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemRxEnable + + Default = 0x0 + + 1 = Rx enable + + Notes: + MAC Tx path enable. Should be set to 1 to enable the MAC Tx path. Should be set to 0 to disable the MAC Tx path. */ + unsigned int msmSystemRxEnable : 1; /* 1E.6004.1 R/W Default = 0x0 */ + /* 1 = Rx enable */ + /*! \brief 1E.6004.0 R/W MSM System Tx Enable + AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemTxEnable + + Default = 0x0 + + 1 = Tx enable + + Notes: + MAC Rx path enable. Should be set to 1 to enable the MAC Rx path. Should be set to 0 to disable the MAC Rx path. */ + unsigned int msmSystemTxEnable : 1; /* 1E.6004.0 R/W Default = 0x0 */ + /* 1 = Tx enable */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System General Control Register */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.6005.7 R/W MSM System Tx Low Power IDLE Enable + AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemTxLowPowerIdleEnable + + Default = 0x0 + + 1 = Transmit LPI enable + + + Notes: + Transmit low power IDLE enable. When set to 1, the MAC completes the transmission of the current frame and generates low power IDLE sequences (LPI) to the XGMII/SGMII. When set to 0, the MAC operates in normal mode. This bit is OR'ed with the reg_lowp_ena pin. */ + unsigned int msmSystemTxLowPowerIdleEnable : 1; /* 1E.6005.7 R/W Default = 0x0 */ + /* 1 = Transmit LPI enable + */ + unsigned int reserved1 : 1; + /*! \brief 1E.6005.5 R/W MSM System SFD Check Disable + AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemSfdCheckDisable + + Default = 0x0 + + 1 = Disable SFD check + + + Notes: + Disable check of SFD (0xD5) character at frame start. When set to 1, the frame is accepted even if the SFD byte following the preamble is not 0xD5. When set to 0, a frame is accepted only if the SFD byte is found with the value 0xD5. */ + unsigned int msmSystemSfdCheckDisable : 1; /* 1E.6005.5 R/W Default = 0x0 */ + /* 1 = Disable SFD check + */ + unsigned int reserved2 : 1; + /*! \brief 1E.6005.3 R/W MSM System Priority Flow Control Enable + AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemPriorityFlowControlEnable + + Default = 0x0 + + 1 = Enable priority flow control + 0 = Enable link flow control + + + Notes: + Enable priority flow control (PFC) mode of operation. When set to 0, the MAC uses standard link pause frames. When set to 1, the MAC will transmit and accept PFC frames. */ + unsigned int msmSystemPriorityFlowControlEnable : 1; /* 1E.6005.3 R/W Default = 0x0 */ + /* 1 = Enable priority flow control + 0 = Enable link flow control + */ + /*! \brief 1E.6005.2 R/W MSM System IDLE Column Count Extend + AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemIdleColumnCountExtend + + Default = 0x0 + + 1 = Extend IDLE column count + + Notes: + When set to 1, extends the RS layer IDLE column counter by 2x. The IEEE 802.3ae defines the fault condition to be cleared after 128 columns of IDLE have been received. If the MAC operates together with a WAN mode PCS (WIS) it may may happen (depending on PCS) that this period is too short to bridge the IDLE stuffing occurring in this mode, leading to a toggling fault indication. In this case, extending the counter helps to aoivd toggling fault indications. */ + unsigned int msmSystemIdleColumnCountExtend : 1; /* 1E.6005.2 R/W Default = 0x0 */ + /* 1 = Extend IDLE column count */ + /*! \brief 1E.6005.1 R/W MSM System Length Check Disable + AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemLengthCheckDisable + + Default = 0x0 + + 1 = Disable length check + + Notes: + Payload length check disable. When set to 0, the MAC checks the frames payload length with the frame length/type field. When set to 1, the payload length check is disabled. */ + unsigned int msmSystemLengthCheckDisable : 1; /* 1E.6005.1 R/W Default = 0x0 */ + /* 1 = Disable length check */ + /*! \brief 1E.6005.0 R/W MSM System Force Send IDLE + AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemForceSendIdle + + Default = 0x0 + + 1 = Force send idle + + Notes: + When set to 1, suppress any frame transmissions and forces IDLE n the Tx interface instead of frames. This control affects the MAC reconciliation layer (RS) which acts after all MAC datapath has processed the frame. + Note : Does not have an effect on fault handling (i.e. reception of local fault will still cause transmit of remote fault). + Must be 0 for normal operation. */ + unsigned int msmSystemForceSendIdle : 1; /* 1E.6005.0 R/W Default = 0x0 */ + /* 1 = Force send idle */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemGeneralControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System FIFO Control Register: 1E.600E */ +/* MSM System FIFO Control Register: 1E.600E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.600E.7:0 R/W MSM System Rx FIFO Full Threshold [7:0] + AQ_MsmSystemFifoControlRegister_HHD.u0.bits_0.msmSystemRxFifoFullThreshold + + Default = 0x08 + + Rx FIFO full threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmSystemRxFifoFullThreshold : 8; /* 1E.600E.7:0 R/W Default = 0x08 */ + /* Rx FIFO full threshold */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.600F.7:0 R/W MSM System Rx FIFO Empty Threshold [7:0] + AQ_MsmSystemFifoControlRegister_HHD.u1.bits_1.msmSystemRxFifoEmptyThreshold + + Default = 0x00 + + Rx FIFO empty threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmSystemRxFifoEmptyThreshold : 8; /* 1E.600F.7:0 R/W Default = 0x00 */ + /* Rx FIFO empty threshold */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of MSM System FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 10; + /*! \brief 1E.6010.5:0 R/W MSM System Tx FIFO Full Threshold [5:0] + AQ_MsmSystemFifoControlRegister_HHD.u2.bits_2.msmSystemTxFifoFullThreshold + + Default = 0x08 + + Tx FIFO full threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmSystemTxFifoFullThreshold : 6; /* 1E.6010.5:0 R/W Default = 0x08 */ + /* Tx FIFO full threshold */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of MSM System FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 10; + /*! \brief 1E.6011.5:0 R/W MSM System Tx FIFO Empty Threshold [5:0] + AQ_MsmSystemFifoControlRegister_HHD.u3.bits_3.msmSystemTxFifoEmptyThreshold + + Default = 0x00 + + Tx FIFO empty threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmSystemTxFifoEmptyThreshold : 6; /* 1E.6011.5:0 R/W Default = 0x00 */ + /* Tx FIFO empty threshold */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of MSM System FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.6012.7:0 ROS MSM System Rx FIFO Almost Full Threshold [7:0] + AQ_MsmSystemFifoControlRegister_HHD.u4.bits_4.msmSystemRxFifoAlmostFullThreshold + + Default = 0x00 + + Rx FIFO almost full threshold + + Notes: + Unused. */ + unsigned int msmSystemRxFifoAlmostFullThreshold : 8; /* 1E.6012.7:0 ROS Default = 0x00 */ + /* Rx FIFO almost full threshold */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of MSM System FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.6013.7:0 ROS MSM System Rx FIFO Almost Empty Threshold [7:0] + AQ_MsmSystemFifoControlRegister_HHD.u5.bits_5.msmSystemRxFifoAlmostEmptyThreshold + + Default = 0x00 + + Rx FIFO almost empty threshold + + Notes: + Unused. */ + unsigned int msmSystemRxFifoAlmostEmptyThreshold : 8; /* 1E.6013.7:0 ROS Default = 0x00 */ + /* Rx FIFO almost empty threshold */ + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of MSM System FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.6014.7:0 ROS MSM System Tx FIFO Almost Full Threshold [7:0] + AQ_MsmSystemFifoControlRegister_HHD.u6.bits_6.msmSystemTxFifoAlmostFullThreshold + + Default = 0x00 + + Tx FIFO almost full threshold + + Notes: + Unused. */ + unsigned int msmSystemTxFifoAlmostFullThreshold : 8; /* 1E.6014.7:0 ROS Default = 0x00 */ + /* Tx FIFO almost full threshold */ + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of MSM System FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.6015.7:0 ROS MSM System Tx FIFO Almost Empty Threshold [7:0] + AQ_MsmSystemFifoControlRegister_HHD.u7.bits_7.msmSystemTxFifoAlmostEmptyThreshold + + Default = 0x00 + + Tx FIFO almost empty threshold + + Notes: + Unused. */ + unsigned int msmSystemTxFifoAlmostEmptyThreshold : 8; /* 1E.6015.7:0 ROS Default = 0x00 */ + /* Tx FIFO almost empty threshold */ + } bits_7; + uint16_t word_7; + } u7; +} AQ_MsmSystemFifoControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System General Status Register: 1E.6020 */ +/* MSM System General Status Register: 1E.6020 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System General Status Register */ + union + { + struct + { + unsigned int reserved0 : 10; + /*! \brief 1E.6020.5 RO MSM System Tx FIFO Empty + AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemTxFifoEmpty + + + + Tx FIFO empty + + Notes: + When set to 1, indicates the Tx FIFO is empty. When set to 0, Tx FIFO is non-empty. */ + unsigned int msmSystemTxFifoEmpty : 1; /* 1E.6020.5 RO */ + /* Tx FIFO empty */ + /*! \brief 1E.6020.4 RO MSM System Rx Low Power IDLE + AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemRxLowPowerIdle + + + + Rx LPI detected + + Notes: + Receive low power IDLE (LPI). Set to 1 when LPI is currently detected on the MAC Rx interface. Set to 0, when the MAC currently operates in normal mode. */ + unsigned int msmSystemRxLowPowerIdle : 1; /* 1E.6020.4 RO */ + /* Rx LPI detected */ + /*! \brief 1E.6020.3 R/W MSM System Timestamp Available + AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemTimestampAvailable + + Default = 0x0 + + Timestamp available + + Notes: + Transmit timestamp available. Indicates that the timestamp of the last transmitted event frame (which had ff_tx_ts_frm=1) is available in the register See MAC Time Stamp Status 0 [F:0] and See MAC Time Stamp Status 1 [F:0] . To clear this bit, the bit must be written with a 1. + */ + unsigned int msmSystemTimestampAvailable : 1; /* 1E.6020.3 R/W Default = 0x0 */ + /* Timestamp available */ + /*! \brief 1E.6020.2 RO MSM System PHY Loss of Signal + AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemPhyLossOfSignal + + + + PHY loss of signal + + Notes: + PHY indicates loss of signal. This is the value of pin phy_los which is tied to 0. */ + unsigned int msmSystemPhyLossOfSignal : 1; /* 1E.6020.2 RO */ + /* PHY loss of signal */ + /*! \brief 1E.6020.1 BLH MSM System Rx Remote Fault + AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemRxRemoteFault + + + + Rx remote fault detected + + Notes: + Latch high local fault status. Set to 1, whent he MAC detects Rx local fault sequences on the Rx interface. Reset to 0 after read and after reset. */ + unsigned int msmSystemRxRemoteFault : 1; /* 1E.6020.1 BLH */ + /* Rx remote fault detected */ + /*! \brief 1E.6020.0 BLH MSM System Rx Local Fault + AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemRxLocalFault + + + + Rx local fault detected + + Notes: + Latch high local fault status. Set to 1, whent he MAC detects Rx local fault sequences on the Rx interface. Reset to 0 after read and after reset. */ + unsigned int msmSystemRxLocalFault : 1; /* 1E.6020.0 BLH */ + /* Rx local fault detected */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System General Status Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemGeneralStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx IPG Control Register: 1E.6022 */ +/* MSM System Tx IPG Control Register: 1E.6022 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx IPG Control Register */ + union + { + struct + { + unsigned int reserved0 : 10; + /*! \brief 1E.6022.5:0 R/W MSM System Tx IPG Length [5:0] + AQ_MsmSystemTxIpgControlRegister_HHD.u0.bits_0.msmSystemTxIpgLength + + Default = 0x0C + + Tx IPG length + + Notes: + Tx inter-packet gap (IPG) value. Depending on LAN or WAN mode of operation. + LAN Mode : Number of octets in steps of 4. Valid values are 8, 12, 16,..., 100. DIC is supported for any setting > 8. A default of 12 must be set to conform to IEEE802.3ae. + WAN Mode : Stretch factor. Valid values are 4 ... 15. The stretch factor is calculated as (value+1)*8. A default of 12 must be set to conform to IEEE802.3ae (i.e. 13*8=104). A larger value shrinks the IPG (increasing bandwidth). + The reset value of 12 leads to IEEE802.3ae conformant behavior in both modes. + Note : WAN mode is only available in 10G mode of operation. */ + unsigned int msmSystemTxIpgLength : 6; /* 1E.6022.5:0 R/W Default = 0x0C */ + /* Tx IPG length */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx IPG Control Register */ + union + { + struct + { + /*! \brief 1E.6023.F:0 MSM System Tx IPG Reserved + AQ_MsmSystemTxIpgControlRegister_HHD.u1.bits_1.msmSystemTxIpgReserved + + + + Value always 0, writes ignored + */ + unsigned int msmSystemTxIpgReserved : 16; /* 1E.6023.F:0 */ + /* Value always 0, writes ignored */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxIpgControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx Good Frames Counter Register: 1E.6040 */ +/* MSM System Tx Good Frames Counter Register: 1E.6040 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6040.F:0 ROS MSM System Tx Good Frames Counter 0 [F:0] + AQ_MsmSystemTxGoodFramesCounterRegister_HHD.u0.bits_0.msmSystemTxGoodFramesCounter_0 + + Default = 0x0000 + + Tx good frame counter bits 15:0 + + Notes: + Count of frames transmitted without error (Including pause frames). */ + unsigned int msmSystemTxGoodFramesCounter_0 : 16; /* 1E.6040.F:0 ROS Default = 0x0000 */ + /* Tx good frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6041.F:0 ROS MSM System Tx Good Frames Counter 1 [F:0] + AQ_MsmSystemTxGoodFramesCounterRegister_HHD.u1.bits_1.msmSystemTxGoodFramesCounter_1 + + Default = 0x0000 + + Tx good frame counter bits 31:16 + + + Notes: + Count of frames transmitted without error (Including pause frames). */ + unsigned int msmSystemTxGoodFramesCounter_1 : 16; /* 1E.6041.F:0 ROS Default = 0x0000 */ + /* Tx good frame counter bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxGoodFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Good Frames Counter Register: 1E.6044 */ +/* MSM System Rx Good Frames Counter Register: 1E.6044 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6044.F:0 ROS MSM System Rx Good Frames Counter 0 [F:0] + AQ_MsmSystemRxGoodFramesCounterRegister_HHD.u0.bits_0.msmSystemRxGoodFramesCounter_0 + + Default = 0x0000 + + Rx good frame counter bits 15:0 + + Notes: + Count of frames received without error (Including pause frames). */ + unsigned int msmSystemRxGoodFramesCounter_0 : 16; /* 1E.6044.F:0 ROS Default = 0x0000 */ + /* Rx good frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6045.F:0 ROS MSM System Rx Good Frames Counter 1 [F:0] + AQ_MsmSystemRxGoodFramesCounterRegister_HHD.u1.bits_1.msmSystemRxGoodFramesCounter_1 + + Default = 0x0000 + + Rx good frame counter bits 31:16 + + Notes: + Count of frames received without error (Including pause frames). */ + unsigned int msmSystemRxGoodFramesCounter_1 : 16; /* 1E.6045.F:0 ROS Default = 0x0000 */ + /* Rx good frame counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxGoodFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx FCS Errors Counter Register: 1E.6048 */ +/* MSM System Rx FCS Errors Counter Register: 1E.6048 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx FCS Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.6048.F:0 ROS MSM System FCS Error Counter 0 [F:0] + AQ_MsmSystemRxFcsErrorsCounterRegister_HHD.u0.bits_0.msmSystemFcsErrorCounter_0 + + Default = 0x0000 + + Frame check sequence error counter bits 15:0 + + Notes: + Count of frames for which a CRC-32 Error is detected but the frame is otherwise of correct length. */ + unsigned int msmSystemFcsErrorCounter_0 : 16; /* 1E.6048.F:0 ROS Default = 0x0000 */ + /* Frame check sequence error counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx FCS Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.6049.F:0 ROS MSM System FCS Error Counter 1 [F:0] + AQ_MsmSystemRxFcsErrorsCounterRegister_HHD.u1.bits_1.msmSystemFcsErrorCounter_1 + + Default = 0x0000 + + Frame check sequence error counter bits 31:16 + + Notes: + Count of frames for which a CRC-32 Error is detected but the frame is otherwise of correct length. */ + unsigned int msmSystemFcsErrorCounter_1 : 16; /* 1E.6049.F:0 ROS Default = 0x0000 */ + /* Frame check sequence error counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxFcsErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Alignment Errors Counter Register: 1E.604C */ +/* MSM System Rx Alignment Errors Counter Register: 1E.604C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Alignment Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.604C.F:0 ROS MSM System Alignment Error Counter 0 [F:0] + AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD.u0.bits_0.msmSystemAlignmentErrorCounter_0 + + Default = 0x0000 + + Alignment error counter bits 15:0 + + Notes: + Count of frames received with an alignment error. */ + unsigned int msmSystemAlignmentErrorCounter_0 : 16; /* 1E.604C.F:0 ROS Default = 0x0000 */ + /* Alignment error counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Alignment Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.604D.F:0 ROS MSM System Alignment Error Counter 1 [F:0] + AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD.u1.bits_1.msmSystemAlignmentErrorCounter_1 + + Default = 0x0000 + + Alignment error counter bits 31:16 + + Notes: + Count of frames received with an alignment error. */ + unsigned int msmSystemAlignmentErrorCounter_1 : 16; /* 1E.604D.F:0 ROS Default = 0x0000 */ + /* Alignment error counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx Pause Frames Counter Register: 1E.6050 */ +/* MSM System Tx Pause Frames Counter Register: 1E.6050 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6050.F:0 ROS MSM System Tx Pause Frames Counter 0 [F:0] + AQ_MsmSystemTxPauseFramesCounterRegister_HHD.u0.bits_0.msmSystemTxPauseFramesCounter_0 + + Default = 0x0000 + + Tx pause frame counter bits 15:0 + + Notes: + Valid pause frames transmitted. */ + unsigned int msmSystemTxPauseFramesCounter_0 : 16; /* 1E.6050.F:0 ROS Default = 0x0000 */ + /* Tx pause frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6051.F:0 ROS MSM System Tx Pause Frames Counter 1 [F:0] + AQ_MsmSystemTxPauseFramesCounterRegister_HHD.u1.bits_1.msmSystemTxPauseFramesCounter_1 + + Default = 0x0000 + + Tx pause frame counter bits 31:16 + + + Notes: + Valid pause frames transmitted. */ + unsigned int msmSystemTxPauseFramesCounter_1 : 16; /* 1E.6051.F:0 ROS Default = 0x0000 */ + /* Tx pause frame counter bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxPauseFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Pause Frames Counter Register: 1E.6054 */ +/* MSM System Rx Pause Frames Counter Register: 1E.6054 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6054.F:0 ROS MSM System Rx Pause Frames Counter 0 [F:0] + AQ_MsmSystemRxPauseFramesCounterRegister_HHD.u0.bits_0.msmSystemRxPauseFramesCounter_0 + + Default = 0x0000 + + Rx pause frame counter bits 15:0 + + Notes: + Valid pause frames received. */ + unsigned int msmSystemRxPauseFramesCounter_0 : 16; /* 1E.6054.F:0 ROS Default = 0x0000 */ + /* Rx pause frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6055.F:0 ROS MSM System Rx Pause Frames Counter 1 [F:0] + AQ_MsmSystemRxPauseFramesCounterRegister_HHD.u1.bits_1.msmSystemRxPauseFramesCounter_1 + + Default = 0x0000 + + Rx pause frame counter bits 31:16 + + Notes: + Valid pause frames received. */ + unsigned int msmSystemRxPauseFramesCounter_1 : 16; /* 1E.6055.F:0 ROS Default = 0x0000 */ + /* Rx pause frame counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxPauseFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Too Long Errors Counter Register: 1E.6058 */ +/* MSM System Rx Too Long Errors Counter Register: 1E.6058 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Too Long Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.6058.F:0 ROS MSM System Rx Too Long Errors Counter 0 [F:0] + AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD.u0.bits_0.msmSystemRxTooLongErrorsCounter_0 + + Default = 0x0000 + + Too-long errors counter bits 15:0 + + Notes: + Frame received exceeded the maximum length programmed with register FRM_LGTH. */ + unsigned int msmSystemRxTooLongErrorsCounter_0 : 16; /* 1E.6058.F:0 ROS Default = 0x0000 */ + /* Too-long errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Too Long Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.6059.F:0 ROS MSM System Rx Too Long Errors Counter 1 [F:0] + AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD.u1.bits_1.msmSystemRxTooLongErrorsCounter_1 + + Default = 0x0000 + + Too-long errors counter bits 31:16 + + Notes: + Frame received exceeded the maximum length programmed with register FRM_LGTH. */ + unsigned int msmSystemRxTooLongErrorsCounter_1 : 16; /* 1E.6059.F:0 ROS Default = 0x0000 */ + /* Too-long errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx In Range Length Errors Counter Register: 1E.605C */ +/* MSM System Rx In Range Length Errors Counter Register: 1E.605C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx In Range Length Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.605C.F:0 ROS MSM System Rx In Range Length Errors Counter 0 [F:0] + AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD.u0.bits_0.msmSystemRxInRangeLengthErrorsCounter_0 + + Default = 0x0000 + + In-range-length errors counter bits 15:0 + + Notes: + A count of frames with a length/type field value between 46 (VLAN: 42) and less than 0x0600, that does not match the number of payload data octets received. Should count also if length/type field is less than 46 (VLAN: 42) and the frame is longer than 64 bytes. */ + unsigned int msmSystemRxInRangeLengthErrorsCounter_0 : 16; /* 1E.605C.F:0 ROS Default = 0x0000 */ + /* In-range-length errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx In Range Length Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.605D.F:0 ROS MSM System Rx In Range Length Errors Counter 1 [F:0] + AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD.u1.bits_1.msmSystemRxInRangeLengthErrorsCounter_1 + + Default = 0x0000 + + In-range-length errors counter bits 31:16 + + Notes: + A count of frames with a length/type field value between 46 (VLAN: 42) and less than 0x0600, that does not match the number of payload data octets received. Should count also if length/type field is less than 46 (VLAN: 42) and the frame is longer than 64 bytes. */ + unsigned int msmSystemRxInRangeLengthErrorsCounter_1 : 16; /* 1E.605D.F:0 ROS Default = 0x0000 */ + /* In-range-length errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx VLAN Frames Counter Register: 1E.6060 */ +/* MSM System Tx VLAN Frames Counter Register: 1E.6060 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6060.F:0 ROS MSM System Tx VLAN Frames Counter 0 [F:0] + AQ_MsmSystemTxVlanFramesCounterRegister_HHD.u0.bits_0.msmSystemTxVlanFramesCounter_0 + + Default = 0x0000 + + Tx VLAN frames counter bits 15:0 + + Notes: + Valid VLAN tagged frames transmitted. */ + unsigned int msmSystemTxVlanFramesCounter_0 : 16; /* 1E.6060.F:0 ROS Default = 0x0000 */ + /* Tx VLAN frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6061.F:0 ROS MSM System Tx VLAN Frames Counter 1 [F:0] + AQ_MsmSystemTxVlanFramesCounterRegister_HHD.u1.bits_1.msmSystemTxVlanFramesCounter_1 + + Default = 0x0000 + + Tx VLAN frames counter bits 31:16 + + Notes: + Valid VLAN tagged frames transmitted. */ + unsigned int msmSystemTxVlanFramesCounter_1 : 16; /* 1E.6061.F:0 ROS Default = 0x0000 */ + /* Tx VLAN frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxVlanFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx VLAN Frames Counter Register: 1E.6064 */ +/* MSM System Rx VLAN Frames Counter Register: 1E.6064 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6064.F:0 ROS MSM System Rx VLAN Frames Counter 0 [F:0] + AQ_MsmSystemRxVlanFramesCounterRegister_HHD.u0.bits_0.msmSystemRxVlanFramesCounter_0 + + Default = 0x0000 + + Rx VLAN frames counter bits 15:0 + + Notes: + Valid VLAN tagged frames received. */ + unsigned int msmSystemRxVlanFramesCounter_0 : 16; /* 1E.6064.F:0 ROS Default = 0x0000 */ + /* Rx VLAN frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6065.F:0 ROS MSM System Rx VLAN Frames Counter 1 [F:0] + AQ_MsmSystemRxVlanFramesCounterRegister_HHD.u1.bits_1.msmSystemRxVlanFramesCounter_1 + + Default = 0x0000 + + Rx VLAN frames counter bits 31:16 + + Notes: + Valid VLAN tagged frames received. */ + unsigned int msmSystemRxVlanFramesCounter_1 : 16; /* 1E.6065.F:0 ROS Default = 0x0000 */ + /* Rx VLAN frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxVlanFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx Octets Counter Register: 1E.6068 */ +/* MSM System Tx Octets Counter Register: 1E.6068 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.6068.F:0 ROS MSM System Tx Octets Counter 0 [F:0] + AQ_MsmSystemTxOctetsCounterRegister_HHD.u0.bits_0.msmSystemTxOctetsCounter_0 + + Default = 0x0000 + + Tx octets counter bits 15:0 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmSystemTxOctetsCounter_0 : 16; /* 1E.6068.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.6069.F:0 ROS MSM System Tx Octets Counter 1 [F:0] + AQ_MsmSystemTxOctetsCounterRegister_HHD.u1.bits_1.msmSystemTxOctetsCounter_1 + + Default = 0x0000 + + Tx octets counter bits 31:16 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmSystemTxOctetsCounter_1 : 16; /* 1E.6069.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of MSM System Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.606A.F:0 ROS MSM System Tx Octets Counter 2 [F:0] + AQ_MsmSystemTxOctetsCounterRegister_HHD.u2.bits_2.msmSystemTxOctetsCounter_2 + + Default = 0x0000 + + Tx octets counter bits 47:32 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmSystemTxOctetsCounter_2 : 16; /* 1E.606A.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 47:32 */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of MSM System Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.606B.F:0 ROS MSM System Tx Octets Counter 3 [F:0] + AQ_MsmSystemTxOctetsCounterRegister_HHD.u3.bits_3.msmSystemTxOctetsCounter_3 + + Default = 0x0000 + + Tx octets counter bits 63:48 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmSystemTxOctetsCounter_3 : 16; /* 1E.606B.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 63:48 */ + } bits_3; + uint16_t word_3; + } u3; +} AQ_MsmSystemTxOctetsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Octets Counter Register: 1E.606C */ +/* MSM System Rx Octets Counter Register: 1E.606C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.606C.F:0 ROS MSM System Rx Octets Counter 0 [F:0] + AQ_MsmSystemRxOctetsCounterRegister_HHD.u0.bits_0.msmSystemRxOctetsCounter_0 + + Default = 0x0000 + + Rx octets counter bits 15:0 + + Notes: + All octets received except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames received. */ + unsigned int msmSystemRxOctetsCounter_0 : 16; /* 1E.606C.F:0 ROS Default = 0x0000 */ + /* Rx octets counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.606D.F:0 ROS MSM System Rx Octets Counter 1 [F:0] + AQ_MsmSystemRxOctetsCounterRegister_HHD.u1.bits_1.msmSystemRxOctetsCounter_1 + + Default = 0x0000 + + Rx octets counter bits 31:16 + + Notes: + All octets received except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames received. */ + unsigned int msmSystemRxOctetsCounter_1 : 16; /* 1E.606D.F:0 ROS Default = 0x0000 */ + /* Rx octets counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxOctetsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Unicast Frames Counter Register: 1E.6070 */ +/* MSM System Rx Unicast Frames Counter Register: 1E.6070 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6070.F:0 ROS MSM System Rx Unicast Frames Counter 0 [F:0] + AQ_MsmSystemRxUnicastFramesCounterRegister_HHD.u0.bits_0.msmSystemRxUnicastFramesCounter_0 + + Default = 0x0000 + + Rx unicast frames counter bits 15:0 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '0'. */ + unsigned int msmSystemRxUnicastFramesCounter_0 : 16; /* 1E.6070.F:0 ROS Default = 0x0000 */ + /* Rx unicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6071.F:0 ROS MSM System Rx Unicast Frames Counter 1 [F:0] + AQ_MsmSystemRxUnicastFramesCounterRegister_HHD.u1.bits_1.msmSystemRxUnicastFramesCounter_1 + + Default = 0x0000 + + Rx unicast frames counter bits 31:16 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '0'. */ + unsigned int msmSystemRxUnicastFramesCounter_1 : 16; /* 1E.6071.F:0 ROS Default = 0x0000 */ + /* Rx unicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxUnicastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Multicast Frames Counter Register: 1E.6074 */ +/* MSM System Rx Multicast Frames Counter Register: 1E.6074 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6074.F:0 ROS MSM System Rx Multicast Frames Counter 0 [F:0] + AQ_MsmSystemRxMulticastFramesCounterRegister_HHD.u0.bits_0.msmSystemRxMulticastFramesCounter_0 + + Default = 0x0000 + + Rx multicast frames counter bits 15:0 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '1' but not the broadcast address (all bits set '1' ). Pause frames are not counted. */ + unsigned int msmSystemRxMulticastFramesCounter_0 : 16; /* 1E.6074.F:0 ROS Default = 0x0000 */ + /* Rx multicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6075.F:0 ROS MSM System Rx Multicast Frames Counter 1 [F:0] + AQ_MsmSystemRxMulticastFramesCounterRegister_HHD.u1.bits_1.msmSystemRxMulticastFramesCounter_1 + + Default = 0x0000 + + Rx multicast frames counter bits 31:16 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '1' but not the broadcast address (all bits set '1' ). Pause frames are not counted. */ + unsigned int msmSystemRxMulticastFramesCounter_1 : 16; /* 1E.6075.F:0 ROS Default = 0x0000 */ + /* Rx multicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxMulticastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Broadcast Frames Counter Register: 1E.6078 */ +/* MSM System Rx Broadcast Frames Counter Register: 1E.6078 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6078.F:0 ROS MSM System Rx Broadcast Frames Counter 0 [F:0] + AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD.u0.bits_0.msmSystemRxBroadcastFramesCounter_0 + + Default = 0x0000 + + Rx broadcast frames counter bits 15:0 + + Notes: + Incremented with each valid frame received on the receive FIFO interface (FIFO) and all bits of the destination address were set '1'. */ + unsigned int msmSystemRxBroadcastFramesCounter_0 : 16; /* 1E.6078.F:0 ROS Default = 0x0000 */ + /* Rx broadcast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6079.F:0 ROS MSM System Rx Broadcast Frames Counter 1 [F:0] + AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD.u1.bits_1.msmSystemRxBroadcastFramesCounter_1 + + Default = 0x0000 + + Rx broadcast frames counter bits 31:16 + + Notes: + Incremented with each valid frame received on the receive FIFO interface (FIFO) and all bits of the destination address were set '1'. */ + unsigned int msmSystemRxBroadcastFramesCounter_1 : 16; /* 1E.6079.F:0 ROS Default = 0x0000 */ + /* Rx broadcast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx Errors Counter Register: 1E.607C */ +/* MSM System Tx Errors Counter Register: 1E.607C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.607C.F:0 ROS MSM System Tx Errors Counter 0 [F:0] + AQ_MsmSystemTxErrorsCounterRegister_HHD.u0.bits_0.msmSystemTxErrorsCounter_0 + + Default = 0x0000 + + Rx errors counter bits 15:0 + + Notes: + Number of frames transmitted with error: + - FIFO Overflow Errors + - FIFO Underflow Errors */ + unsigned int msmSystemTxErrorsCounter_0 : 16; /* 1E.607C.F:0 ROS Default = 0x0000 */ + /* Rx errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.607D.F:0 ROS MSM System Tx Errors Counter 1 [F:0] + AQ_MsmSystemTxErrorsCounterRegister_HHD.u1.bits_1.msmSystemTxErrorsCounter_1 + + Default = 0x0000 + + Tx errors counter bits 31:16 + + Notes: + Number of frames transmitted with error: + - FIFO Overflow Errors + - FIFO Underflow Errors */ + unsigned int msmSystemTxErrorsCounter_1 : 16; /* 1E.607D.F:0 ROS Default = 0x0000 */ + /* Tx errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx Unicast Frames Counter Register: 1E.6084 */ +/* MSM System Tx Unicast Frames Counter Register: 1E.6084 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6084.F:0 ROS MSM System Tx Unicast Frames Counter 0 [F:0] + AQ_MsmSystemTxUnicastFramesCounterRegister_HHD.u0.bits_0.msmSystemTxUnicastFramesCounter_0 + + Default = 0x0000 + + Tx unicast frames counter bits 15:0 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '0'. */ + unsigned int msmSystemTxUnicastFramesCounter_0 : 16; /* 1E.6084.F:0 ROS Default = 0x0000 */ + /* Tx unicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6085.F:0 ROS MSM System Tx Unicast Frames Counter 1 [F:0] + AQ_MsmSystemTxUnicastFramesCounterRegister_HHD.u1.bits_1.msmSystemTxUnicastFramesCounter_1 + + Default = 0x0000 + + Tx unicast frames counter bits 31:16 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '0'. */ + unsigned int msmSystemTxUnicastFramesCounter_1 : 16; /* 1E.6085.F:0 ROS Default = 0x0000 */ + /* Tx unicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxUnicastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx Multicast Frames Counter Register: 1E.6088 */ +/* MSM System Tx Multicast Frames Counter Register: 1E.6088 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6088.F:0 ROS MSM System Tx Multicast Frames Counter 0 [F:0] + AQ_MsmSystemTxMulticastFramesCounterRegister_HHD.u0.bits_0.msmSystemTxMulticastFramesCounter_0 + + Default = 0x0000 + + Tx multicast frames counter bits 15:0 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '1' but not the broadcast address (all bits '1'). */ + unsigned int msmSystemTxMulticastFramesCounter_0 : 16; /* 1E.6088.F:0 ROS Default = 0x0000 */ + /* Tx multicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.6089.F:0 ROS MSM System Tx Multicast Frames Counter 1 [F:0] + AQ_MsmSystemTxMulticastFramesCounterRegister_HHD.u1.bits_1.msmSystemTxMulticastFramesCounter_1 + + Default = 0x0000 + + Tx multicast frames counter bits 31:16 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '1' but not the broadcast address (all bits '1'). */ + unsigned int msmSystemTxMulticastFramesCounter_1 : 16; /* 1E.6089.F:0 ROS Default = 0x0000 */ + /* Tx multicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxMulticastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Tx Broadcast Frames Counter Register: 1E.608C */ +/* MSM System Tx Broadcast Frames Counter Register: 1E.608C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Tx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.608C.F:0 ROS MSM System Tx Broadcast Frames Counter 0 [F:0] + AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD.u0.bits_0.msmSystemTxBroadcastFramesCounter_0 + + Default = 0x0000 + + Tx broadcast frames counter bits 15:0 + + Notes: + Incremented with each frame written to the FIFO interface and all bits of the destination address set to '1'. */ + unsigned int msmSystemTxBroadcastFramesCounter_0 : 16; /* 1E.608C.F:0 ROS Default = 0x0000 */ + /* Tx broadcast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Tx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.608D.F:0 ROS MSM System Tx Broadcast Frames Counter 1 [F:0] + AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD.u1.bits_1.msmSystemTxBroadcastFramesCounter_1 + + Default = 0x0000 + + Tx broadcast frames counter bits 31:16 + + Notes: + Incremented with each frame written to the FIFO interface and all bits of the destination address set to '1'. */ + unsigned int msmSystemTxBroadcastFramesCounter_1 : 16; /* 1E.608D.F:0 ROS Default = 0x0000 */ + /* Tx broadcast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM System Rx Errors Counter Register: 1E.60C8 */ +/* MSM System Rx Errors Counter Register: 1E.60C8 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM System Rx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.60C8.F:0 ROS MSM System Rx Errors Counter 0 [F:0] + AQ_MsmSystemRxErrorsCounterRegister_HHD.u0.bits_0.msmSystemRxErrorsCounter_0 + + Default = 0x0000 + + Rx errors counter bits 15:0 + + Notes: + Number of frames received with error: + - FIFO Overflow Errors + - CRC Errors + - Payload Length Errors + - Jabber and Oversized Errors + - Alignment Errors + - The dedicated Error Code (0xfe, not a code error) was received */ + unsigned int msmSystemRxErrorsCounter_0 : 16; /* 1E.60C8.F:0 ROS Default = 0x0000 */ + /* Rx errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM System Rx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.60C9.F:0 ROS MSM System Rx Errors Counter 1 [F:0] + AQ_MsmSystemRxErrorsCounterRegister_HHD.u1.bits_1.msmSystemRxErrorsCounter_1 + + Default = 0x0000 + + Rx errors counter bits 31:16 + + Notes: + Number of frames received with error: + - FIFO Overflow Errors + - CRC Errors + - Payload Length Errors + - Jabber and Oversized Errors + - Alignment Errors + - The dedicated Error Code (0xfe, not a code error) was received */ + unsigned int msmSystemRxErrorsCounter_1 : 16; /* 1E.60C9.F:0 ROS Default = 0x0000 */ + /* Rx errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmSystemRxErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress VLAN TPID 0 Register: 1E.8006 */ +/* MSS Ingress VLAN TPID 0 Register: 1E.8006 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress VLAN TPID 0 Register */ + union + { + struct + { + /*! \brief 1E.8006.F:0 R/W MSS Ingress VLAN STag [F:0] + AQ_MssIngressVlanTpid_0Register_HHD.u0.bits_0.mssIngressVlanStag + + Default = 0x0000 + + STag TPID + + + Notes: + Service Tag Protocol Identifier (TPID) values to identify a VLAN tag. The " See SEC Egress VLAN CP Tag Parse STag " bit must be set to 1 for the incoming packet's TPID to be parsed. */ + unsigned int mssIngressVlanStag : 16; /* 1E.8006.F:0 R/W Default = 0x0000 */ + /* STag TPID + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress VLAN TPID 0 Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressVlanTpid_0Register_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress VLAN TPID 1 Register: 1E.8008 */ +/* MSS Ingress VLAN TPID 1 Register: 1E.8008 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress VLAN TPID 1 Register */ + union + { + struct + { + /*! \brief 1E.8008.F:0 R/W MSS Ingress VLAN QTag [F:0] + AQ_MssIngressVlanTpid_1Register_HHD.u0.bits_0.mssIngressVlanQtag + + Default = 0x0000 + + QTag TPID + + + Notes: + Customer Tag Protocol Identifier (TPID) values to identify a VLAN tag. The " See SEC Egress VLAN CP Tag Parse QTag " bit must be set to 1 for the incoming packet's TPID to be parsed. */ + unsigned int mssIngressVlanQtag : 16; /* 1E.8008.F:0 R/W Default = 0x0000 */ + /* QTag TPID + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress VLAN TPID 1 Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressVlanTpid_1Register_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress VLAN Control Register: 1E.800A */ +/* MSS Ingress VLAN Control Register: 1E.800A */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress VLAN Control Register */ + union + { + struct + { + /*! \brief 1E.800A.F:0 R/W MSS Ingress VLAN UP Map Table LSW [F:0] + AQ_MssIngressVlanControlRegister_HHD.u0.bits_0.mssIngressVlanUpMapTableLSW + + Default = 0x0000 + + Map table bits 15:0 + + + Notes: + If there is a customer TPID Tag match and no service TPID Tag match or the service TPID Tag match is disabled, the outer TAG's PCP is used to index into this map table to generate the packets user priority. + 2:0 : UP value for customer Tag PCP 0x0 + 5:3: UP value for customer Tag PCP 0x0 + 8:6 : UP value for customer Tag PCP 0x0 + 11:9 : UP value for customer Tag PCP 0x0 + 14:12 : UP value for customer Tag PCP 0x0 + 17:15 : UP value for customer Tag PCP 0x0 */ + unsigned int mssIngressVlanUpMapTableLSW : 16; /* 1E.800A.F:0 R/W Default = 0x0000 */ + /* Map table bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress VLAN Control Register */ + union + { + struct + { + /*! \brief 1E.800B.F R/W MSS Ingress VLAN QTag Parse Enable + AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanQtagParseEnable + + Default = 0x0 + + 1 = Enable VLAN QTag parsing + + + Notes: + Enable controlled port VLAN customer Tag parsing. When this bit is set to 1, the incoming packet's outer TPID will be compared with the configured " See MSS Ingress VLAN QTag [F:0] " for matching. If the " See SEC Egress VLAN CP Tag Parse QinQ " bit is set to1, this will also be used to compare the incoming packet's inner TPID. */ + unsigned int mssIngressVlanQtagParseEnable : 1; /* 1E.800B.F R/W Default = 0x0 */ + /* 1 = Enable VLAN QTag parsing + */ + /*! \brief 1E.800B.E R/W MSS Ingress VLAN STag Parse Enable + AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanStagParseEnable + + Default = 0x0 + + 1 = Enable VLAN STag parsing + + + Notes: + Enable controlled port VLAN service Tag parsing. When this bit is set to 1, the incoming packets outer TPID will be compared with the configured " See MSS Ingress VLAN Stag [F:0] " for matching. If the " See SEC Egress VLAN CP Tag Parse QinQ " bit is set to1, this will also be used to compare the incoming packet's inner TPID. */ + unsigned int mssIngressVlanStagParseEnable : 1; /* 1E.800B.E R/W Default = 0x0 */ + /* 1 = Enable VLAN STag parsing + */ + /*! \brief 1E.800B.D R/W MSS Ingress VLAN QinQ Parse Enable + AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanQinqParseEnable + + Default = 0x0 + + VLAN CP Tag Parse QinQ + + + Notes: + Enable controlled port VLAN QinQ Tag parsing. When this bit is set to 1 both the outer and inner VLAN Tags will be parsed. */ + unsigned int mssIngressVlanQinqParseEnable : 1; /* 1E.800B.D R/W Default = 0x0 */ + /* VLAN CP Tag Parse QinQ + */ + /*! \brief 1E.800B.C R/W MSS Ingress VLAN QTag UP Parse Enable + AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanQtagUpParseEnable + + Default = 0x0 + + VLAN CP Tag QTag UP enable + + + Notes: + Enable controlled port customer VLAN customer Tag user priority field parsing. */ + unsigned int mssIngressVlanQtagUpParseEnable : 1; /* 1E.800B.C R/W Default = 0x0 */ + /* VLAN CP Tag QTag UP enable + */ + /*! \brief 1E.800B.B R/W MSS Ingress VLAN STag UP Parse Enable + AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanStagUpParseEnable + + Default = 0x0 + + VLAN CP Tag STag UP enable + + + Notes: + Enable controlled port service VLAN service Tag user priority field parsing. */ + unsigned int mssIngressVlanStagUpParseEnable : 1; /* 1E.800B.B R/W Default = 0x0 */ + /* VLAN CP Tag STag UP enable + */ + /*! \brief 1E.800B.A:8 R/W MSS Ingress VLAN UP Default [2:0] + AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanUpDefault + + Default = 0x0 + + UP default + + + Notes: + User priority default */ + unsigned int mssIngressVlanUpDefault : 3; /* 1E.800B.A:8 R/W Default = 0x0 */ + /* UP default + */ + /*! \brief 1E.800B.7:0 R/W MSS Ingress VLAN UP Map Table MSW [17:10] + AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanUpMapTableMSW + + Default = 0x00 + + UP Map table bits 23:16 + + + Notes: + If there is a customer TPID Tag match and no service TPID Tag match or the service TPID Tag match is disabled, the outer TAG's PCP is used to index into this map table to generate the packets user priority. + 2:0 : UP value for customer Tag PCP 0x0 + 5:3: UP value for customer Tag PCP 0x0 + 8:6 : UP value for customer Tag PCP 0x0 + 11:9 : UP value for customer Tag PCP 0x0 + 14:12 : UP value for customer Tag PCP 0x0 + 17:15 : UP value for customer Tag PCP 0x0 + 20:18 : UP value for customer Tag PCP 0x0 + 23:21 : UP value for customer Tag PCP 0x0 */ + unsigned int mssIngressVlanUpMapTableMSW : 8; /* 1E.800B.7:0 R/W Default = 0x00 */ + /* UP Map table bits 23:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressVlanControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress MTU Size Control Register: 1E.800C */ +/* MSS Ingress MTU Size Control Register: 1E.800C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress MTU Size Control Register */ + union + { + struct + { + /*! \brief 1E.800C.F:0 R/W MSS Ingress Controlled Packet MTU Size [F:0] + AQ_MssIngressMtuSizeControlRegister_HHD.u0.bits_0.mssIngressControlledPacketMtuSize + + Default = 0x05DC + + Maximum transmission unit for controlled packet + + + Notes: + Maximum transmission unit of controlled packet */ + unsigned int mssIngressControlledPacketMtuSize : 16; /* 1E.800C.F:0 R/W Default = 0x05DC */ + /* Maximum transmission unit for controlled packet + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress MTU Size Control Register */ + union + { + struct + { + /*! \brief 1E.800D.F:0 R/W MSS Ingress Uncontrolled Packet MTU Size [F:0] + AQ_MssIngressMtuSizeControlRegister_HHD.u1.bits_1.mssIngressUncontrolledPacketMtuSize + + Default = 0x05DC + + Maximum transmission unit for uncontrolled packet + + + Notes: + Maximum transmission unit of uncontrolled packet */ + unsigned int mssIngressUncontrolledPacketMtuSize : 16; /* 1E.800D.F:0 R/W Default = 0x05DC */ + /* Maximum transmission unit for uncontrolled packet + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressMtuSizeControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress Control Register: 1E.800E */ +/* MSS Ingress Control Register: 1E.800E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress Control Register */ + union + { + struct + { + unsigned int reserved0 : 2; + /*! \brief 1E.800E.D R/W MSS Ingress ICV LSB 8 Bytes Enable + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressIcvLsb_8BytesEnable + + Default = 0x0 + + 1 = Use LSB + 0 = Use MSB + + + + Notes: + This bit selects MSB or LSB 8 bytes selection in the case where the ICV is 8 bytes. + 0 = MSB is used. */ + unsigned int mssIngressIcvLsb_8BytesEnable : 1; /* 1E.800E.D R/W Default = 0x0 */ + /* 1 = Use LSB + 0 = Use MSB + + */ + /*! \brief 1E.800E.C:B R/W MSS Ingress Global Validate Frames [1:0] + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressGlobalValidateFrames + + Default = 0x0 + + Default validate frames configuration + + + Notes: + If the SC is invalid or if an IGPRC miss packet condition occurs, this default will be used for the validate frames configuration instead of the validate frame entry in the Ingress SC Table (IGSCT). */ + unsigned int mssIngressGlobalValidateFrames : 2; /* 1E.800E.C:B R/W Default = 0x0 */ + /* Default validate frames configuration + */ + /*! \brief 1E.800E.A R/W MSS Ingress Remove SECTag + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressRemoveSectag + + Default = 0x0 + + 1 = Enable removal of SECTag + + + Notes: + If this bit is set and either of the following two conditions occurs, the SECTag will be removed. + Controlled packet and either the SA or SC is invalid. + IGPRC miss. */ + unsigned int mssIngressRemoveSectag : 1; /* 1E.800E.A R/W Default = 0x0 */ + /* 1 = Enable removal of SECTag + */ + /*! \brief 1E.800E.9 R/W MSS Ingress High Priority + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressHighPriority + + Default = 0x0 + + 1 = MIB counter clear on read enable + + + Notes: + If this bit is set to 1, read is given high priority and the MIB count value becomes 0 after read. */ + unsigned int mssIngressHighPriority : 1; /* 1E.800E.9 R/W Default = 0x0 */ + /* 1 = MIB counter clear on read enable + */ + /*! \brief 1E.800E.8 R/W MSS Ingress Clear Count + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressClearCount + + Default = 0x0 + + 1 = Clear all MIB counters + + + Notes: + If this bit is set to 1, all MIB counters will be cleared. */ + unsigned int mssIngressClearCount : 1; /* 1E.800E.8 R/W Default = 0x0 */ + /* 1 = Clear all MIB counters + */ + /*! \brief 1E.800E.7 R/W MSS Ingress Clear Global Time + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressClearGlobalTime + + Default = 0x0 + + 1 = Clear global time + + + Notes: + Clear global time */ + unsigned int mssIngressClearGlobalTime : 1; /* 1E.800E.7 R/W Default = 0x0 */ + /* 1 = Clear global time + */ + /*! \brief 1E.800E.6 R/W MSS Ingress Check ICV + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressCheckIcv + + Default = 0x0 + + Unused + + + Notes: + Unused */ + unsigned int mssIngressCheckIcv : 1; /* 1E.800E.6 R/W Default = 0x0 */ + /* Unused + */ + /*! \brief 1E.800E.5 R/W MSS Ingress Drop IGPRC Miss + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressDropIgprcMiss + + Default = 0x0 + + 1 = Drop IGPRC miss packets + + + Notes: + Decides whether Ingress Pre-Security Classification (IGPRC) LUT miss packets are to be dropped */ + unsigned int mssIngressDropIgprcMiss : 1; /* 1E.800E.5 R/W Default = 0x0 */ + /* 1 = Drop IGPRC miss packets + */ + /*! \brief 1E.800E.4 R/W MSS Ingress Drop Kay Packet + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressDropKayPacket + + Default = 0x0 + + 1 = Drop KaY packets + + + Notes: + Decides whether KaY packets have to be dropped */ + unsigned int mssIngressDropKayPacket : 1; /* 1E.800E.4 R/W Default = 0x0 */ + /* 1 = Drop KaY packets + */ + /*! \brief 1E.800E.3 R/W MSS Ingress Mask Short Length Error + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressMaskShortLengthError + + Default = 0x0 + + Unused + + + Notes: + Unused */ + unsigned int mssIngressMaskShortLengthError : 1; /* 1E.800E.3 R/W Default = 0x0 */ + /* Unused + */ + /*! \brief 1E.800E.2 R/W MSS Ingress Create SCI + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressCreateSci + + Default = 0x0 + + 0 = SCI from IGPRC LUT + + + Notes: + If the SCI is not in the packet and this bit is set to 0, the SCI will be taken from the IGPRC LUT. */ + unsigned int mssIngressCreateSci : 1; /* 1E.800E.2 R/W Default = 0x0 */ + /* 0 = SCI from IGPRC LUT + */ + /*! \brief 1E.800E.1 R/W MSS Ingress Operation Point To Point + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressOperationPointToPoint + + Default = 0x0 + + 1 = Enable the SCI for authorization default + + + Notes: + The default SCI for authorization is configured in See MSS Ingress SCI Default [F:0] See MSS Ingress SCI Default [1F:10] , See MSS Ingress SCI Default [2F:20] , and See MSS Ingress SCI Default [3F:30] . */ + unsigned int mssIngressOperationPointToPoint : 1; /* 1E.800E.1 R/W Default = 0x0 */ + /* 1 = Enable the SCI for authorization default + */ + /*! \brief 1E.800E.0 R/W MSS Ingress Soft Reset + AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressSoftReset + + Default = 0x0 + + 1 = Soft reset + + + Notes: + S/W reset */ + unsigned int mssIngressSoftReset : 1; /* 1E.800E.0 R/W Default = 0x0 */ + /* 1 = Soft reset + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress Control Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress SA Control Register: 1E.8010 */ +/* MSS Ingress SA Control Register: 1E.8010 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress SA Control Register */ + union + { + struct + { + /*! \brief 1E.8010.F:0 R/W MSS Ingress SA Threshold LSW [F:0] + AQ_MssIngressSaControlRegister_HHD.u0.bits_0.mssIngressSaThresholdLSW + + Default = 0x0000 + + SA threshold bits 15:0 + + + Notes: + Ingress PN threshold to generate SA threshold interrupt. */ + unsigned int mssIngressSaThresholdLSW : 16; /* 1E.8010.F:0 R/W Default = 0x0000 */ + /* SA threshold bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress SA Control Register */ + union + { + struct + { + /*! \brief 1E.8011.F:0 R/W MSS Ingress SA Threshold MSW [1F:10] + AQ_MssIngressSaControlRegister_HHD.u1.bits_1.mssIngressSaThresholdMSW + + Default = 0x0000 + + SA threshold bits 31:16 + + + Notes: + Ingress PN threshold to generate SA threshold interrupt. */ + unsigned int mssIngressSaThresholdMSW : 16; /* 1E.8011.F:0 R/W Default = 0x0000 */ + /* SA threshold bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressSaControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress Interrupt Status Register: 1E.802E */ +/* MSS Ingress Interrupt Status Register: 1E.802E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress Interrupt Status Register */ + union + { + struct + { + unsigned int reserved0 : 7; + /*! \brief 1E.802E.8 COW MSS Ingress IGPOC Miss Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressIgpocMissInterrupt + + Default = 0x0 + + 1 = Interrupt + + */ + unsigned int mssIngressIgpocMissInterrupt : 1; /* 1E.802E.8 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.7 COW MSS Ingress TCI E/C Error Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressTciE_cErrorInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This error occurs when the TCI E bit is 1 and the TCI C bit is 0. The packet is not dropped, uncontrolled, or untagged. */ + unsigned int mssIngressTciE_cErrorInterrupt : 1; /* 1E.802E.7 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.6 COW MSS Ingress ECC Error Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressEccErrorInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. */ + unsigned int mssIngressEccErrorInterrupt : 1; /* 1E.802E.6 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.5 COW MSS Ingress MIB Saturation Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressMibSaturationInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when the MIB counters reaches all ones saturation. */ + unsigned int mssIngressMibSaturationInterrupt : 1; /* 1E.802E.5 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.4 COW MSS Ingress Replay Error Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressReplayErrorInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. */ + unsigned int mssIngressReplayErrorInterrupt : 1; /* 1E.802E.4 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.3 COW MSS Ingress ICV Error Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressIcvErrorInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. */ + unsigned int mssIngressIcvErrorInterrupt : 1; /* 1E.802E.3 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.2 COW MSS Ingress SA Threshold Expired Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressSaThresholdExpiredInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when the SA PN reaches the See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . */ + unsigned int mssIngressSaThresholdExpiredInterrupt : 1; /* 1E.802E.2 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.1 COW MSS Ingress SA Expired Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressSaExpiredInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when the SA PN reaches all ones saturation. */ + unsigned int mssIngressSaExpiredInterrupt : 1; /* 1E.802E.1 COW Default = 0x0 */ + /* 1 = Interrupt + */ + /*! \brief 1E.802E.0 COW MSS Master Ingress Interrupt + AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssMasterIngressInterrupt + + Default = 0x0 + + 1 = Interrupt + + + Notes: + Write to 1 to clear. This bit is set when any one of the above interrupt and the corresponding interrupt enable are both set. The interrupt enable for this bit must also be set for this bit to be set. */ + unsigned int mssMasterIngressInterrupt : 1; /* 1E.802E.0 COW Default = 0x0 */ + /* 1 = Interrupt + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress Interrupt Status Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressInterruptStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress Interrupt Mask Register: 1E.8030 */ +/* MSS Ingress Interrupt Mask Register: 1E.8030 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress Interrupt Mask Register */ + union + { + struct + { + unsigned int reserved0 : 7; + /*! \brief 1E.8030.8 R/W MSS Ingress IGPOC Miss Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressIgpocMissInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressIgpocMissInterruptEnable : 1; /* 1E.8030.8 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.7 R/W MSS Ingress TCI E/C Error Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressTciE_cErrorInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressTciE_cErrorInterruptEnable : 1; /* 1E.8030.7 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.6 R/W MSS Ingress ECC Error Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressEccErrorInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressEccErrorInterruptEnable : 1; /* 1E.8030.6 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.5 R/W MSS Ingress MIB Saturation Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressMibSaturationInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressMibSaturationInterruptEnable : 1; /* 1E.8030.5 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.4 R/W MSS Ingress Replay Error Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressReplayErrorInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressReplayErrorInterruptEnable : 1; /* 1E.8030.4 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.3 R/W MSS Ingress ICV Error Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressIcvErrorInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressIcvErrorInterruptEnable : 1; /* 1E.8030.3 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.2 R/W MSS Ingress SA Threshold Expired Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressSaThresholdExpiredInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressSaThresholdExpiredInterruptEnable : 1; /* 1E.8030.2 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.1 R/W MSS Ingress SA Expired Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressSaExpiredInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressSaExpiredInterruptEnable : 1; /* 1E.8030.1 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + /*! \brief 1E.8030.0 R/W MSS Ingress Master Interrupt Enable + AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressMasterInterruptEnable + + Default = 0x0 + + 1 = Interrupt enabled + + */ + unsigned int mssIngressMasterInterruptEnable : 1; /* 1E.8030.0 R/W Default = 0x0 */ + /* 1 = Interrupt enabled + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress Interrupt Mask Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressInterruptMaskRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress SA ICV Error Status Register: 1E.8032 */ +/* MSS Ingress SA ICV Error Status Register: 1E.8032 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress SA ICV Error Status Register */ + union + { + struct + { + /*! \brief 1E.8032.F:0 COW MSS Ingress SA ICV Error LSW [F:0] + AQ_MssIngressSaIcvErrorStatusRegister_HHD.u0.bits_0.mssIngressSaIcvErrorLSW + + Default = 0x0000 + + SA ICV error bits 15:0 + + + Notes: + When set, these bits identify the SA that has an ICV error. Write these bits to 1 to clear. */ + unsigned int mssIngressSaIcvErrorLSW : 16; /* 1E.8032.F:0 COW Default = 0x0000 */ + /* SA ICV error bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress SA ICV Error Status Register */ + union + { + struct + { + /*! \brief 1E.8033.F:0 COW MSS Ingress SA ICV Error MSW [1F:10] + AQ_MssIngressSaIcvErrorStatusRegister_HHD.u1.bits_1.mssIngressSaIcvErrorMSW + + Default = 0x0000 + + SA ICV error bits 31:16 + + + Notes: + When set, these bits identify the SA that has an ICV error. Write these bits to 1 to clear. */ + unsigned int mssIngressSaIcvErrorMSW : 16; /* 1E.8033.F:0 COW Default = 0x0000 */ + /* SA ICV error bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressSaIcvErrorStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress SA Replay Error Status Register: 1E.8034 */ +/* MSS Ingress SA Replay Error Status Register: 1E.8034 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress SA Replay Error Status Register */ + union + { + struct + { + /*! \brief 1E.8034.F:0 COW MSS Ingress SA Replay Error LSW [F:0] + AQ_MssIngressSaReplayErrorStatusRegister_HHD.u0.bits_0.mssIngressSaReplayErrorLSW + + Default = 0x0000 + + SA replay error bits 15:0 + + + Notes: + When set, these bits identify the SA that has a replay error. Write these bits to 1 to clear. */ + unsigned int mssIngressSaReplayErrorLSW : 16; /* 1E.8034.F:0 COW Default = 0x0000 */ + /* SA replay error bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress SA Replay Error Status Register */ + union + { + struct + { + /*! \brief 1E.8035.F:0 COW MSS Ingress SA Replay Error MSW [1F:10] + AQ_MssIngressSaReplayErrorStatusRegister_HHD.u1.bits_1.mssIngressSaReplayErrorMSW + + Default = 0x0000 + + SA replay error bits 31:16 + + + Notes: + When set, these bits identify the SA that has a replay error. Write these bits to 1 to clear. */ + unsigned int mssIngressSaReplayErrorMSW : 16; /* 1E.8035.F:0 COW Default = 0x0000 */ + /* SA replay error bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressSaReplayErrorStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress SA Expired Status Register: 1E.8036 */ +/* MSS Ingress SA Expired Status Register: 1E.8036 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress SA Expired Status Register */ + union + { + struct + { + /*! \brief 1E.8036.F:0 ROS MSS Ingress SA Expired LSW [F:0] + AQ_MssIngressSaExpiredStatusRegister_HHD.u0.bits_0.mssIngressSaExpiredLSW + + Default = 0x0000 + + SA expired bits 15:0 + + + Notes: + When set, these bits identify the SA that has expired when the SA PN reaches all-ones saturation. Write these bits to 1 to clear. */ + unsigned int mssIngressSaExpiredLSW : 16; /* 1E.8036.F:0 ROS Default = 0x0000 */ + /* SA expired bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress SA Expired Status Register */ + union + { + struct + { + /*! \brief 1E.8037.F:0 ROS MSS Ingress SA Expired MSW [1F:10] + AQ_MssIngressSaExpiredStatusRegister_HHD.u1.bits_1.mssIngressSaExpiredMSW + + Default = 0x0000 + + SA expired bits 31:16 + + + Notes: + When set, these bits identify the SA that has expired when the SA PN reaches all-ones saturation. Write these bits to 1 to clear. */ + unsigned int mssIngressSaExpiredMSW : 16; /* 1E.8037.F:0 ROS Default = 0x0000 */ + /* SA expired bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressSaExpiredStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress SA Threshold Expired Status Register: 1E.8038 */ +/* MSS Ingress SA Threshold Expired Status Register: 1E.8038 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress SA Threshold Expired Status Register */ + union + { + struct + { + /*! \brief 1E.8038.F:0 ROS MSS Ingress SA Threshold Expired LSW [F:0] + AQ_MssIngressSaThresholdExpiredStatusRegister_HHD.u0.bits_0.mssIngressSaThresholdExpiredLSW + + Default = 0x0000 + + SA threshold expired bits 15:0 + + + Notes: + When set, these bits identify the SA that has expired when the SA PN has reached the configured threshold See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . Write these bits to 1 to clear. */ + unsigned int mssIngressSaThresholdExpiredLSW : 16; /* 1E.8038.F:0 ROS Default = 0x0000 */ + /* SA threshold expired bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress SA Threshold Expired Status Register */ + union + { + struct + { + /*! \brief 1E.8039.F:0 ROS MSS Ingress SA Threshold Expired MSW [1F:10] + AQ_MssIngressSaThresholdExpiredStatusRegister_HHD.u1.bits_1.mssIngressSaThresholdExpiredMSW + + Default = 0x0000 + + SA threshold expired bits 31:16 + + + Notes: + When set, these bits identify the SA that has expired when the SA PN has reached the configured threshold See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . Write these bits to 1 to clear. */ + unsigned int mssIngressSaThresholdExpiredMSW : 16; /* 1E.8039.F:0 ROS Default = 0x0000 */ + /* SA threshold expired bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressSaThresholdExpiredStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress ECC Interrupt Status Register: 1E.803A */ +/* MSS Ingress ECC Interrupt Status Register: 1E.803A */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress ECC Interrupt Status Register */ + union + { + struct + { + /*! \brief 1E.803A.F:0 R/W MSS Ingress SA ECC Error Interrupt LSW [F:0] + AQ_MssIngressEccInterruptStatusRegister_HHD.u0.bits_0.mssIngressSaEccErrorInterruptLSW + + Default = 0x0000 + + SA ECC error interrupt bits 15:0 + + + Notes: + When set to 1, indicates that an ECC error occured for the SA. */ + unsigned int mssIngressSaEccErrorInterruptLSW : 16; /* 1E.803A.F:0 R/W Default = 0x0000 */ + /* SA ECC error interrupt bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress ECC Interrupt Status Register */ + union + { + struct + { + /*! \brief 1E.803B.F:0 R/W MSS Ingress SA ECC Error Interrupt MSW [1F:10] + AQ_MssIngressEccInterruptStatusRegister_HHD.u1.bits_1.mssIngressSaEccErrorInterruptMSW + + Default = 0x0000 + + SA ECC error interrupt bits 31:16 + + + Notes: + When set to 1, indicates that an ECC error occured for the SA. */ + unsigned int mssIngressSaEccErrorInterruptMSW : 16; /* 1E.803B.F:0 R/W Default = 0x0000 */ + /* SA ECC error interrupt bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MssIngressEccInterruptStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress LUT Address Control Register: 1E.8080 */ +/* MSS Ingress LUT Address Control Register: 1E.8080 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress LUT Address Control Register */ + union + { + struct + { + /*! \brief 1E.8080.F:C R/W MSS Ingress LUT Select [3:0] + AQ_MssIngressLutAddressControlRegister_HHD.u0.bits_0.mssIngressLutSelect + + Default = 0x0 + + LUT select + + + Notes: + 0x0 : Ingress Pre-Security MAC Control FIlter (IGPRCTLF) LUT + 0x1 : Ingress Pre-Security Classification LUT (IGPRC) + 0x2 : Ingress Packet Format (IGPFMT) SAKey LUT + 0x3 : Ingress Packet Format (IGPFMT) SC/SA LUT + 0x4 : Ingress Post-Security Classification LUT (IGPOC) + 0x5 : Ingress Post-Security MAC Control Filter (IGPOCTLF) LUT + 0x6 : Ingress MIB (IGMIB) */ + unsigned int mssIngressLutSelect : 4; /* 1E.8080.F:C R/W Default = 0x0 */ + /* LUT select + */ + unsigned int reserved0 : 3; + /*! \brief 1E.8080.8:0 R/W MSS Ingress LUT Address [8:0] + AQ_MssIngressLutAddressControlRegister_HHD.u0.bits_0.mssIngressLutAddress + + Default = 0x000 + + LUT address + + */ + unsigned int mssIngressLutAddress : 9; /* 1E.8080.8:0 R/W Default = 0x000 */ + /* LUT address + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_MssIngressLutAddressControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress LUT Control Register: 1E.8081 */ +/* MSS Ingress LUT Control Register: 1E.8081 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress LUT Control Register */ + union + { + struct + { + /*! \brief 1E.8081.F R/W MSS Ingress LUT Write + AQ_MssIngressLutControlRegister_HHD.u0.bits_0.mssIngressLutWrite + + Default = 0x0 + + 1 = LUT write + + + Notes: + Setting this bit to 1, will write the LUT. This bit will automatically clear to 0. */ + unsigned int mssIngressLutWrite : 1; /* 1E.8081.F R/W Default = 0x0 */ + /* 1 = LUT write + */ + /*! \brief 1E.8081.E R/W MSS Ingress LUT Read + AQ_MssIngressLutControlRegister_HHD.u0.bits_0.mssIngressLutRead + + Default = 0x0 + + 1 = LUT read + + + Notes: + Setting this bit to 1, will read the LUT. This bit will automatically clear to 0. */ + unsigned int mssIngressLutRead : 1; /* 1E.8081.E R/W Default = 0x0 */ + /* 1 = LUT read + */ + unsigned int reserved0 : 14; + } bits_0; + uint16_t word_0; + } u0; +} AQ_MssIngressLutControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSS Ingress LUT Data Control Register: 1E.80A0 */ +/* MSS Ingress LUT Data Control Register: 1E.80A0 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A0.F:0 R/W MSS Ingress LUT Data 0 [F:0] + AQ_MssIngressLutDataControlRegister_HHD.u0.bits_0.mssIngressLutData_0 + + Default = 0x0000 + + LUT data bits 15:0 + + */ + unsigned int mssIngressLutData_0 : 16; /* 1E.80A0.F:0 R/W Default = 0x0000 */ + /* LUT data bits 15:0 + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A1.F:0 R/W MSS Ingress LUT Data 1 [1F:10] + AQ_MssIngressLutDataControlRegister_HHD.u1.bits_1.mssIngressLutData_1 + + Default = 0x0000 + + LUT data bits 31:16 + + */ + unsigned int mssIngressLutData_1 : 16; /* 1E.80A1.F:0 R/W Default = 0x0000 */ + /* LUT data bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A2.F:0 R/W MSS Ingress LUT Data 2 [2F:20] + AQ_MssIngressLutDataControlRegister_HHD.u2.bits_2.mssIngressLutData_2 + + Default = 0x0000 + + LUT data bits 47:32 + + */ + unsigned int mssIngressLutData_2 : 16; /* 1E.80A2.F:0 R/W Default = 0x0000 */ + /* LUT data bits 47:32 + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A3.F:0 R/W MSS Ingress LUT Data 3 [3F:30] + AQ_MssIngressLutDataControlRegister_HHD.u3.bits_3.mssIngressLutData_3 + + Default = 0x0000 + + LUT data bits 63:48 + + */ + unsigned int mssIngressLutData_3 : 16; /* 1E.80A3.F:0 R/W Default = 0x0000 */ + /* LUT data bits 63:48 + */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A4.F:0 R/W MSS Ingress LUT Data 4 [4F:40] + AQ_MssIngressLutDataControlRegister_HHD.u4.bits_4.mssIngressLutData_4 + + Default = 0x0000 + + LUT data bits 79:64 + + */ + unsigned int mssIngressLutData_4 : 16; /* 1E.80A4.F:0 R/W Default = 0x0000 */ + /* LUT data bits 79:64 + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A5.F:0 R/W MSS Ingress LUT Data 5 [5F:50] + AQ_MssIngressLutDataControlRegister_HHD.u5.bits_5.mssIngressLutData_5 + + Default = 0x0000 + + LUT data bits 95:80 + + */ + unsigned int mssIngressLutData_5 : 16; /* 1E.80A5.F:0 R/W Default = 0x0000 */ + /* LUT data bits 95:80 + */ + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A6.F:0 R/W MSS Ingress LUT Data 6 [6F:60] + AQ_MssIngressLutDataControlRegister_HHD.u6.bits_6.mssIngressLutData_6 + + Default = 0x0000 + + LUT data bits 111:96 + + */ + unsigned int mssIngressLutData_6 : 16; /* 1E.80A6.F:0 R/W Default = 0x0000 */ + /* LUT data bits 111:96 + */ + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A7.F:0 R/W MSS Ingress LUT Data 7 [7F:70] + AQ_MssIngressLutDataControlRegister_HHD.u7.bits_7.mssIngressLutData_7 + + Default = 0x0000 + + LUT data bits 127:112 + + */ + unsigned int mssIngressLutData_7 : 16; /* 1E.80A7.F:0 R/W Default = 0x0000 */ + /* LUT data bits 127:112 + */ + } bits_7; + uint16_t word_7; + } u7; + /*! \brief Union for bit and word level access of word 8 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A8.F:0 R/W MSS Ingress LUT Data 8 [8F:80] + AQ_MssIngressLutDataControlRegister_HHD.u8.bits_8.mssIngressLutData_8 + + Default = 0x0000 + + LUT data bits 143:128 + + */ + unsigned int mssIngressLutData_8 : 16; /* 1E.80A8.F:0 R/W Default = 0x0000 */ + /* LUT data bits 143:128 + */ + } bits_8; + uint16_t word_8; + } u8; + /*! \brief Union for bit and word level access of word 9 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80A9.F:0 R/W MSS Ingress LUT Data 9 [9F:90] + AQ_MssIngressLutDataControlRegister_HHD.u9.bits_9.mssIngressLutData_9 + + Default = 0x0000 + + LUT data bits 159:144 + + */ + unsigned int mssIngressLutData_9 : 16; /* 1E.80A9.F:0 R/W Default = 0x0000 */ + /* LUT data bits 159:144 + */ + } bits_9; + uint16_t word_9; + } u9; + /*! \brief Union for bit and word level access of word 10 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80AA.F:0 R/W MSS Ingress LUT Data 10 [AF:A0] + AQ_MssIngressLutDataControlRegister_HHD.u10.bits_10.mssIngressLutData_10 + + Default = 0x0000 + + LUT data bits 175:160 + + */ + unsigned int mssIngressLutData_10 : 16; /* 1E.80AA.F:0 R/W Default = 0x0000 */ + /* LUT data bits 175:160 + */ + } bits_10; + uint16_t word_10; + } u10; + /*! \brief Union for bit and word level access of word 11 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80AB.F:0 R/W MSS Ingress LUT Data 11 [BF:B0] + AQ_MssIngressLutDataControlRegister_HHD.u11.bits_11.mssIngressLutData_11 + + Default = 0x0000 + + LUT data bits 191:176 + + */ + unsigned int mssIngressLutData_11 : 16; /* 1E.80AB.F:0 R/W Default = 0x0000 */ + /* LUT data bits 191:176 + */ + } bits_11; + uint16_t word_11; + } u11; + /*! \brief Union for bit and word level access of word 12 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80AC.F:0 R/W MSS Ingress LUT Data 12 [CF:C0] + AQ_MssIngressLutDataControlRegister_HHD.u12.bits_12.mssIngressLutData_12 + + Default = 0x0000 + + LUT data bits 207:192 + + */ + unsigned int mssIngressLutData_12 : 16; /* 1E.80AC.F:0 R/W Default = 0x0000 */ + /* LUT data bits 207:192 + */ + } bits_12; + uint16_t word_12; + } u12; + /*! \brief Union for bit and word level access of word 13 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80AD.F:0 R/W MSS Ingress LUT Data 13 [DF:D0] + AQ_MssIngressLutDataControlRegister_HHD.u13.bits_13.mssIngressLutData_13 + + Default = 0x0000 + + LUT data bits 223:208 + + */ + unsigned int mssIngressLutData_13 : 16; /* 1E.80AD.F:0 R/W Default = 0x0000 */ + /* LUT data bits 223:208 + */ + } bits_13; + uint16_t word_13; + } u13; + /*! \brief Union for bit and word level access of word 14 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80AE.F:0 R/W MSS Ingress LUT Data 14 [EF:E0] + AQ_MssIngressLutDataControlRegister_HHD.u14.bits_14.mssIngressLutData_14 + + Default = 0x0000 + + LUT data bits 239:224 + + */ + unsigned int mssIngressLutData_14 : 16; /* 1E.80AE.F:0 R/W Default = 0x0000 */ + /* LUT data bits 239:224 + */ + } bits_14; + uint16_t word_14; + } u14; + /*! \brief Union for bit and word level access of word 15 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80AF.F:0 R/W MSS Ingress LUT Data 15 [FF:F0] + AQ_MssIngressLutDataControlRegister_HHD.u15.bits_15.mssIngressLutData_15 + + Default = 0x0000 + + LUT data bits 255:240 + + */ + unsigned int mssIngressLutData_15 : 16; /* 1E.80AF.F:0 R/W Default = 0x0000 */ + /* LUT data bits 255:240 + */ + } bits_15; + uint16_t word_15; + } u15; + /*! \brief Union for bit and word level access of word 16 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B0.F:0 R/W MSS Ingress LUT Data 16 [10F:100] + AQ_MssIngressLutDataControlRegister_HHD.u16.bits_16.mssIngressLutData_16 + + Default = 0x0000 + + LUT data bits 271:256 + + */ + unsigned int mssIngressLutData_16 : 16; /* 1E.80B0.F:0 R/W Default = 0x0000 */ + /* LUT data bits 271:256 + */ + } bits_16; + uint16_t word_16; + } u16; + /*! \brief Union for bit and word level access of word 17 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B1.F:0 R/W MSS Ingress LUT Data 17 [11F:110] + AQ_MssIngressLutDataControlRegister_HHD.u17.bits_17.mssIngressLutData_17 + + Default = 0x0000 + + LUT data bits 287:272 + + */ + unsigned int mssIngressLutData_17 : 16; /* 1E.80B1.F:0 R/W Default = 0x0000 */ + /* LUT data bits 287:272 + */ + } bits_17; + uint16_t word_17; + } u17; + /*! \brief Union for bit and word level access of word 18 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B2.F:0 R/W MSS Ingress LUT Data 18 [12F:120] + AQ_MssIngressLutDataControlRegister_HHD.u18.bits_18.mssIngressLutData_18 + + Default = 0x0000 + + LUT data bits 303:288 + + */ + unsigned int mssIngressLutData_18 : 16; /* 1E.80B2.F:0 R/W Default = 0x0000 */ + /* LUT data bits 303:288 + */ + } bits_18; + uint16_t word_18; + } u18; + /*! \brief Union for bit and word level access of word 19 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B3.F:0 R/W MSS Ingress LUT Data 19 [13F:130] + AQ_MssIngressLutDataControlRegister_HHD.u19.bits_19.mssIngressLutData_19 + + Default = 0x0000 + + LUT data bits 319:304 + + */ + unsigned int mssIngressLutData_19 : 16; /* 1E.80B3.F:0 R/W Default = 0x0000 */ + /* LUT data bits 319:304 + */ + } bits_19; + uint16_t word_19; + } u19; + /*! \brief Union for bit and word level access of word 20 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B4.F:0 R/W MSS Ingress LUT Data 20 [14F:140] + AQ_MssIngressLutDataControlRegister_HHD.u20.bits_20.mssIngressLutData_20 + + Default = 0x0000 + + LUT data bits 335:320 + + */ + unsigned int mssIngressLutData_20 : 16; /* 1E.80B4.F:0 R/W Default = 0x0000 */ + /* LUT data bits 335:320 + */ + } bits_20; + uint16_t word_20; + } u20; + /*! \brief Union for bit and word level access of word 21 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B5.F:0 R/W MSS Ingress LUT Data 21 [15F:150] + AQ_MssIngressLutDataControlRegister_HHD.u21.bits_21.mssIngressLutData_21 + + Default = 0x0000 + + LUT data bits 351:336 + + */ + unsigned int mssIngressLutData_21 : 16; /* 1E.80B5.F:0 R/W Default = 0x0000 */ + /* LUT data bits 351:336 + */ + } bits_21; + uint16_t word_21; + } u21; + /*! \brief Union for bit and word level access of word 22 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B6.F:0 R/W MSS Ingress LUT Data 22 [16F:160] + AQ_MssIngressLutDataControlRegister_HHD.u22.bits_22.mssIngressLutData_22 + + Default = 0x0000 + + LUT data bits 367:352 + + */ + unsigned int mssIngressLutData_22 : 16; /* 1E.80B6.F:0 R/W Default = 0x0000 */ + /* LUT data bits 367:352 + */ + } bits_22; + uint16_t word_22; + } u22; + /*! \brief Union for bit and word level access of word 23 of MSS Ingress LUT Data Control Register */ + union + { + struct + { + /*! \brief 1E.80B7.F:0 R/W MSS Ingress LUT Data 23 [17F:170] + AQ_MssIngressLutDataControlRegister_HHD.u23.bits_23.mssIngressLutData_23 + + Default = 0x0000 + + LUT data bits 383:368 + + */ + unsigned int mssIngressLutData_23 : 16; /* 1E.80B7.F:0 R/W Default = 0x0000 */ + /* LUT data bits 383:368 + */ + } bits_23; + uint16_t word_23; + } u23; +} AQ_MssIngressLutDataControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line General Control Register: 1E.9004 */ +/* MSM Line General Control Register: 1E.9004 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line General Control Register */ + union + { + struct + { + /*! \brief 1E.9004.F R/W MSM Line PHY Tx Enable + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLinePhyTxEnable + + Default = 0x0 + + 1 = Enable PHY Tx + + + Notes: + Directly controls the phy_tx_ena pin. */ + unsigned int msmLinePhyTxEnable : 1; /* 1E.9004.F R/W Default = 0x0 */ + /* 1 = Enable PHY Tx + */ + /*! \brief 1E.9004.E R/W MSM Line Rx Error Discard + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineRxErrorDiscard + + Default = 0x0 + + 1 = Enable discard of received errored frames + + + Notes: + Rx errored frame discard enable. When set to 1, any frame received with an error is discarded and not forwarded to the client interface. When set to 0, errored frames are forwarded to the client interface with ff_rx_err asserted. + Note : It is recommended to set this bit to 1 only when store and forward operation is enabled (RX_SECTION_FULL TBD). */ + unsigned int msmLineRxErrorDiscard : 1; /* 1E.9004.E R/W Default = 0x0 */ + /* 1 = Enable discard of received errored frames + */ + /*! \brief 1E.9004.D R/W MSM Line Control Frame Enable + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineControlFrameEnable + + Default = 0x0 + + 1 = Control frame enabled + + + Notes: + MAC control frame enable. When set to 1, the MAC control frames with any Opcode other than 0x0001 are accepted and forwarded to the client interface. When set to 0, MAC control frames with any opcode other than 0x0001 are silently discarded. */ + unsigned int msmLineControlFrameEnable : 1; /* 1E.9004.D R/W Default = 0x0 */ + /* 1 = Control frame enabled + */ + /*! \brief 1E.9004.C R/WSC MSM Line Soft Reset + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineSoftReset + + Default = 0x0 + + 1 = Soft reset + + + Notes: + Software reset. Self clearing bit. When set to 1, resets all statistic counters as well as the Tx and Rx FIFOs. It should be issued after all traffic has been stopped as a result of clearing the Rx/Tx enable bits ( See MAC Rx Enable set to 0 and See MAC Tx Enable set to 0). + Note : Can lead to an Rx interface (ff_rx_xxx) violations to the application if the reset is issued in the middle of a receive frame transfer. Then the end of packet (assertion of ff_rx_eop) is lost and the application should be prepeared to handle this exception. */ + unsigned int msmLineSoftReset : 1; /* 1E.9004.C R/WSC Default = 0x0 */ + /* 1 = Soft reset + */ + /*! \brief 1E.9004.B R/W MSM Line Tx Pad Enable + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineTxPadEnable + + Default = 0x1 + + 1 = Enable Tx padding + + + Notes: + When set to 1, enable padding of frames in the Tx direction. When set to 0, the MAC will not extend frames from the application to a minimum of 64 bytes, allowing to transmit short frames (violating the Ethernet mimimum size requirements). Must be set to 1 for normal operation. */ + unsigned int msmLineTxPadEnable : 1; /* 1E.9004.B R/W Default = 0x1 */ + /* 1 = Enable Tx padding + */ + /*! \brief 1E.9004.A R/W MSM Line Tx CRC Append + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineTxCrcAppend + + Default = 0x0 + + 1 = Append Tx CRC + + + Notes: + Permanently enable CRC append on transmit. If set to 1, the Tx will append a CRC to all transmitted frames. If set to 0, CRC append can be controlled on a per frame basis using the pin ff_tx_crc. + This configuration bit is OR'ed with the external ff_tx_crc pin to instruct the Tx to append a CRC to transmitted frames. The ff_tx_crc pin is tied to 0. */ + unsigned int msmLineTxCrcAppend : 1; /* 1E.9004.A R/W Default = 0x0 */ + /* 1 = Append Tx CRC + */ + /*! \brief 1E.9004.9 R/W MSM Line Tx Address Insert Enable + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineTxAddressInsertEnable + + Default = 0x0 + + 1 = Insert Tx MAC source address + + + Notes: + Set the source MAC address on transmit. If set to 1, the MAC overwrites the source MAC address with the MAC programmed address in all transmitted frames. When set to 0, the source MAC address is transmitted unmodified from the MAC Tx client application. */ + unsigned int msmLineTxAddressInsertEnable : 1; /* 1E.9004.9 R/W Default = 0x0 */ + /* 1 = Insert Tx MAC source address + */ + /*! \brief 1E.9004.8 R/W MSM Line Pause Ignore + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLinePauseIgnore + + Default = 0x0 + + 1 = Ignore pause frames + + + Notes: + Ignore pause frame quanta. If set to 1, received pause frames are ignored by the MAC. When set to 0, the Tx is stopped for the amount of time specified in the pause quanta received within the pause frame. */ + unsigned int msmLinePauseIgnore : 1; /* 1E.9004.8 R/W Default = 0x0 */ + /* 1 = Ignore pause frames + */ + /*! \brief 1E.9004.7 R/W MSM Line Pause Forward + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLinePauseForward + + Default = 0x0 + + 1 = Enable Pause forwarding + + + Notes: + Terminate or forward pause frames. If set to 1, pause frames are forwarded to the user application. In normal mode, when set to 0, pause frames are terminated and discarded within the MAC. */ + unsigned int msmLinePauseForward : 1; /* 1E.9004.7 R/W Default = 0x0 */ + /* 1 = Enable Pause forwarding + */ + /*! \brief 1E.9004.6 R/W MSM Line CRC Forward + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineCrcForward + + Default = 0x0 + + 1 = Enable CRC forwarding + + + Notes: + When set to 1, the CRC field of the received frames is forwarded with the frame to the user application. If disabled, the CRC field is stripped from the frame. + Note : If padding is enabled ( See MAC PAD Enable set to 1), this bit is ignored. */ + unsigned int msmLineCrcForward : 1; /* 1E.9004.6 R/W Default = 0x0 */ + /* 1 = Enable CRC forwarding + */ + /*! \brief 1E.9004.5 R/W MSM Line PAD Enable + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLinePadEnable + + Default = 0x0 + + 1 = Enable frame padding removal on Rx + + + Notes: + When set to 1, enable frame padding removal on the Rx path. If enabled, padding is removed before the frame is transferred to the MAC client application. If disabled, no padding is removed on the Rx by the MAC. + Note : On Tx, the MAC always adds padding as required. */ + unsigned int msmLinePadEnable : 1; /* 1E.9004.5 R/W Default = 0x0 */ + /* 1 = Enable frame padding removal on Rx + */ + /*! \brief 1E.9004.4 R/W MSM Line Promiscuous Mode + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLinePromiscuousMode + + Default = 0x0 + + 1 = Promiscuous mode + + + Notes: + When set to 1, all frames are received without any MAC address filtering. */ + unsigned int msmLinePromiscuousMode : 1; /* 1E.9004.4 R/W Default = 0x0 */ + /* 1 = Promiscuous mode + */ + /*! \brief 1E.9004.3 R/W MSM Line WAN Mode + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineWanMode + + Default = 0x0 + + 1 = WAN mode + 0 = LAN mode + + + Notes: + WAN mode enable. Sets WAN mode when set to 1 and LAN mode when set to 0. Note: When changing the mode, verifiy correct setting of the Tx IPG. */ + unsigned int msmLineWanMode : 1; /* 1E.9004.3 R/W Default = 0x0 */ + /* 1 = WAN mode + 0 = LAN mode + */ + unsigned int reserved0 : 1; + /*! \brief 1E.9004.1 R/W MSM Line Rx Enable + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineRxEnable + + Default = 0x0 + + 1 = Rx enable + + Notes: + MAC Tx path enable. Should be set to 1 to enable the MAC Tx path. Should be set to 0 to disable the MAC Tx path. */ + unsigned int msmLineRxEnable : 1; /* 1E.9004.1 R/W Default = 0x0 */ + /* 1 = Rx enable */ + /*! \brief 1E.9004.0 R/W MSM Line Tx Enable + AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineTxEnable + + Default = 0x0 + + 1 = Tx enable + + Notes: + MAC Rx path enable. Should be set to 1 to enable the MAC Rx path. Should be set to 0 to disable the MAC Rx path. */ + unsigned int msmLineTxEnable : 1; /* 1E.9004.0 R/W Default = 0x0 */ + /* 1 = Tx enable */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line General Control Register */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.9005.7 R/W MSM Line Tx Low Power IDLE Enable + AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLineTxLowPowerIdleEnable + + Default = 0x0 + + 1 = Transmit LPI enable + + + Notes: + Transmit low power IDLE enable. When set to 1, the MAC completes the transmission of the current frame and generates low power IDLE sequences (LPI) to the XGMII/SGMII. When set to 0, the MAC operates in normal mode. This bit is OR'ed with the reg_lowp_ena pin. */ + unsigned int msmLineTxLowPowerIdleEnable : 1; /* 1E.9005.7 R/W Default = 0x0 */ + /* 1 = Transmit LPI enable + */ + unsigned int reserved1 : 1; + /*! \brief 1E.9005.5 R/W MSM Line SFD Check Disable + AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLineSfdCheckDisable + + Default = 0x0 + + 1 = Disable SFD check + + + Notes: + Disable check of SFD (0xD5) character at frame start. When set to 1, the frame is accepted even if the SFD byte following the preamble is not 0xD5. When set to 0, a frame is accepted only if the SFD byte is found with the value 0xD5. */ + unsigned int msmLineSfdCheckDisable : 1; /* 1E.9005.5 R/W Default = 0x0 */ + /* 1 = Disable SFD check + */ + unsigned int reserved2 : 1; + /*! \brief 1E.9005.3 R/W MSM Line Priority Flow Control Enable + AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLinePriorityFlowControlEnable + + Default = 0x0 + + 1 = Enable priority flow control + 0 = Enable link flow control + + + Notes: + Enable priority flow control (PFC) mode of operation. When set to 0, the MAC uses standard link pause frames. When set to 1, the MAC will transmit and accept PFC frames. */ + unsigned int msmLinePriorityFlowControlEnable : 1; /* 1E.9005.3 R/W Default = 0x0 */ + /* 1 = Enable priority flow control + 0 = Enable link flow control + */ + /*! \brief 1E.9005.2 R/W MSM Line IDLE Column Count Extend + AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLineIdleColumnCountExtend + + Default = 0x0 + + 1 = Extend IDLE column count + + Notes: + When set to 1, extends the RS layer IDLE column counter by 2x. The IEEE 802.3ae defines the fault condition to be cleared after 128 columns of IDLE have been received. If the MAC operates together with a WAN mode PCS (WIS) it may may happen (depending on PCS) that this period is too short to bridge the IDLE stuffing occurring in this mode, leading to a toggling fault indication. In this case, extending the counter helps to aoivd toggling fault indications. */ + unsigned int msmLineIdleColumnCountExtend : 1; /* 1E.9005.2 R/W Default = 0x0 */ + /* 1 = Extend IDLE column count */ + /*! \brief 1E.9005.1 R/W MSM Line Length Check Disable + AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLineLengthCheckDisable + + Default = 0x0 + + 1 = Disable length check + + Notes: + Payload length check disable. When set to 0, the MAC checks the frames payload length with the frame length/type field. When set to 1, the payload length check is disabled. */ + unsigned int msmLineLengthCheckDisable : 1; /* 1E.9005.1 R/W Default = 0x0 */ + /* 1 = Disable length check */ + /*! \brief 1E.9005.0 R/W MSM Line Force Send IDLE + AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLineForceSendIdle + + Default = 0x0 + + 1 = Force send idle + + Notes: + When set to 1, suppress any frame transmissions and forces IDLE n the Tx interface instead of frames. This control affects the MAC reconciliation layer (RS) which acts after all MAC datapath has processed the frame. + Note : Does not have an effect on fault handling (i.e. reception of local fault will still cause transmit of remote fault). + Must be 0 for normal operation. */ + unsigned int msmLineForceSendIdle : 1; /* 1E.9005.0 R/W Default = 0x0 */ + /* 1 = Force send idle */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineGeneralControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line FIFO Control Register: 1E.900E */ +/* MSM Line FIFO Control Register: 1E.900E */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.900E.7:0 R/W MSM Line Rx FIFO Full Threshold [7:0] + AQ_MsmLineFifoControlRegister_HHD.u0.bits_0.msmLineRxFifoFullThreshold + + Default = 0x08 + + Rx FIFO full threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmLineRxFifoFullThreshold : 8; /* 1E.900E.7:0 R/W Default = 0x08 */ + /* Rx FIFO full threshold */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.900F.7:0 R/W MSM Line Rx FIFO Empty Threshold [7:0] + AQ_MsmLineFifoControlRegister_HHD.u1.bits_1.msmLineRxFifoEmptyThreshold + + Default = 0x00 + + Rx FIFO empty threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmLineRxFifoEmptyThreshold : 8; /* 1E.900F.7:0 R/W Default = 0x00 */ + /* Rx FIFO empty threshold */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of MSM Line FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 10; + /*! \brief 1E.9010.5:0 R/W MSM Line Tx FIFO Full Threshold [5:0] + AQ_MsmLineFifoControlRegister_HHD.u2.bits_2.msmLineTxFifoFullThreshold + + Default = 0x08 + + Tx FIFO full threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmLineTxFifoFullThreshold : 6; /* 1E.9010.5:0 R/W Default = 0x08 */ + /* Tx FIFO full threshold */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of MSM Line FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 10; + /*! \brief 1E.9011.5:0 R/W MSM Line Tx FIFO Empty Threshold [5:0] + AQ_MsmLineFifoControlRegister_HHD.u3.bits_3.msmLineTxFifoEmptyThreshold + + Default = 0x00 + + Tx FIFO empty threshold + + Notes: + All threshold values are in steps of FIFO words. */ + unsigned int msmLineTxFifoEmptyThreshold : 6; /* 1E.9011.5:0 R/W Default = 0x00 */ + /* Tx FIFO empty threshold */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of MSM Line FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.9012.7:0 ROS MSM Line Rx FIFO Almost Full Threshold [7:0] + AQ_MsmLineFifoControlRegister_HHD.u4.bits_4.msmLineRxFifoAlmostFullThreshold + + Default = 0x00 + + Rx FIFO almost full threshold + + Notes: + Unused. */ + unsigned int msmLineRxFifoAlmostFullThreshold : 8; /* 1E.9012.7:0 ROS Default = 0x00 */ + /* Rx FIFO almost full threshold */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of MSM Line FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.9013.7:0 ROS MSM Line Rx FIFO Almost Empty Threshold [7:0] + AQ_MsmLineFifoControlRegister_HHD.u5.bits_5.msmLineRxFifoAlmostEmptyThreshold + + Default = 0x00 + + Rx FIFO almost empty threshold + + Notes: + Unused. */ + unsigned int msmLineRxFifoAlmostEmptyThreshold : 8; /* 1E.9013.7:0 ROS Default = 0x00 */ + /* Rx FIFO almost empty threshold */ + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of MSM Line FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.9014.7:0 ROS MSM Line Tx FIFO Almost Full Threshold [7:0] + AQ_MsmLineFifoControlRegister_HHD.u6.bits_6.msmLineTxFifoAlmostFullThreshold + + Default = 0x00 + + Tx FIFO almost full threshold + + Notes: + Unused. */ + unsigned int msmLineTxFifoAlmostFullThreshold : 8; /* 1E.9014.7:0 ROS Default = 0x00 */ + /* Tx FIFO almost full threshold */ + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of MSM Line FIFO Control Register */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.9015.7:0 ROS MSM Line Tx FIFO Almost Empty Threshold [7:0] + AQ_MsmLineFifoControlRegister_HHD.u7.bits_7.msmLineTxFifoAlmostEmptyThreshold + + Default = 0x00 + + Tx FIFO almost empty threshold + + Notes: + Unused. */ + unsigned int msmLineTxFifoAlmostEmptyThreshold : 8; /* 1E.9015.7:0 ROS Default = 0x00 */ + /* Tx FIFO almost empty threshold */ + } bits_7; + uint16_t word_7; + } u7; +} AQ_MsmLineFifoControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line General Status Register: 1E.9020 */ +/* MSM Line General Status Register: 1E.9020 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line General Status Register */ + union + { + struct + { + unsigned int reserved0 : 10; + /*! \brief 1E.9020.5 RO MSM Line Tx FIFO Empty + AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLineTxFifoEmpty + + + + Tx FIFO empty + + Notes: + When set to 1, indicates the Tx FIFO is empty. When set to 0, Tx FIFO is non-empty. */ + unsigned int msmLineTxFifoEmpty : 1; /* 1E.9020.5 RO */ + /* Tx FIFO empty */ + /*! \brief 1E.9020.4 RO MSM Line Rx Low Power IDLE + AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLineRxLowPowerIdle + + + + Rx LPI detected + + Notes: + Receive low power IDLE (LPI). Set to 1 when LPI is currently detected on the MAC Rx interface. Set to 0, when the MAC currently operates in normal mode. */ + unsigned int msmLineRxLowPowerIdle : 1; /* 1E.9020.4 RO */ + /* Rx LPI detected */ + /*! \brief 1E.9020.3 R/W MSM Line Timestamp Available + AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLineTimestampAvailable + + Default = 0x0 + + Timestamp available + + Notes: + Transmit timestamp available. Indicates that the timestamp of the last transmitted event frame (which had ff_tx_ts_frm=1) is available in the register See MAC Time Stamp Status 0 [F:0] and See MAC Time Stamp Status 1 [F:0] . To clear this bit, the bit must be written with a 1. + */ + unsigned int msmLineTimestampAvailable : 1; /* 1E.9020.3 R/W Default = 0x0 */ + /* Timestamp available */ + /*! \brief 1E.9020.2 RO MSM Line PHY Loss of Signal + AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLinePhyLossOfSignal + + + + PHY loss of signal + + Notes: + PHY indicates loss of signal. This is the value of pin phy_los which is tied to 0. */ + unsigned int msmLinePhyLossOfSignal : 1; /* 1E.9020.2 RO */ + /* PHY loss of signal */ + /*! \brief 1E.9020.1 BLH MSM Line Rx Remote Fault + AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLineRxRemoteFault + + + + Rx remote fault detected + + Notes: + Latch high local fault status. Set to 1, whent he MAC detects Rx local fault sequences on the Rx interface. Reset to 0 after read and after reset. */ + unsigned int msmLineRxRemoteFault : 1; /* 1E.9020.1 BLH */ + /* Rx remote fault detected */ + /*! \brief 1E.9020.0 BLH MSM Line Rx Local Fault + AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLineRxLocalFault + + + + Rx local fault detected + + Notes: + Latch high local fault status. Set to 1, whent he MAC detects Rx local fault sequences on the Rx interface. Reset to 0 after read and after reset. */ + unsigned int msmLineRxLocalFault : 1; /* 1E.9020.0 BLH */ + /* Rx local fault detected */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line General Status Register */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineGeneralStatusRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx IPG Control Register: 1E.9022 */ +/* MSM Line Tx IPG Control Register: 1E.9022 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx IPG Control Register */ + union + { + struct + { + unsigned int reserved0 : 10; + /*! \brief 1E.9022.5:0 R/W MSM Line Tx IPG Length [5:0] + AQ_MsmLineTxIpgControlRegister_HHD.u0.bits_0.msmLineTxIpgLength + + Default = 0x0C + + Tx IPG length + + Notes: + Tx inter-packet gap (IPG) value. Depending on LAN or WAN mode of operation. + LAN Mode : Number of octets in steps of 4. Valid values are 8, 12, 16,..., 100. DIC is supported for any setting > 8. A default of 12 must be set to conform to IEEE802.3ae. + WAN Mode : Stretch factor. Valid values are 4 ... 15. The stretch factor is calculated as (value+1)*8. A default of 12 must be set to conform to IEEE802.3ae (i.e. 13*8=104). A larger value shrinks the IPG (increasing bandwidth). + The reset value of 12 leads to IEEE802.3ae conformant behavior in both modes. + Note : WAN mode is only available in 10G mode of operation. */ + unsigned int msmLineTxIpgLength : 6; /* 1E.9022.5:0 R/W Default = 0x0C */ + /* Tx IPG length */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx IPG Control Register */ + union + { + struct + { + /*! \brief 1E.9023.F:0 MSM Line Tx IPG Reserved + AQ_MsmLineTxIpgControlRegister_HHD.u1.bits_1.msmLineTxIpgReserved + + + + Value always 0, writes ignored + */ + unsigned int msmLineTxIpgReserved : 16; /* 1E.9023.F:0 */ + /* Value always 0, writes ignored */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxIpgControlRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx Good Frames Counter Register: 1E.9040 */ +/* MSM Line Tx Good Frames Counter Register: 1E.9040 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9040.F:0 ROS MSM Line Tx Good Frames Counter 0 [F:0] + AQ_MsmLineTxGoodFramesCounterRegister_HHD.u0.bits_0.msmLineTxGoodFramesCounter_0 + + Default = 0x0000 + + Tx good frame counter bits 15:0 + + Notes: + Count of frames transmitted without error (Including pause frames). */ + unsigned int msmLineTxGoodFramesCounter_0 : 16; /* 1E.9040.F:0 ROS Default = 0x0000 */ + /* Tx good frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9041.F:0 ROS MSM Line Tx Good Frames Counter 1 [F:0] + AQ_MsmLineTxGoodFramesCounterRegister_HHD.u1.bits_1.msmLineTxGoodFramesCounter_1 + + Default = 0x0000 + + Tx good frame counter bits 31:16 + + + Notes: + Count of frames transmitted without error (Including pause frames). */ + unsigned int msmLineTxGoodFramesCounter_1 : 16; /* 1E.9041.F:0 ROS Default = 0x0000 */ + /* Tx good frame counter bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxGoodFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Good Frames Counter Register: 1E.9044 */ +/* MSM Line Rx Good Frames Counter Register: 1E.9044 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9044.F:0 ROS MSM Line Rx Good Frames Counter 0 [F:0] + AQ_MsmLineRxGoodFramesCounterRegister_HHD.u0.bits_0.msmLineRxGoodFramesCounter_0 + + Default = 0x0000 + + Rx good frame counter bits 15:0 + + Notes: + Count of frames received without error (Including pause frames). */ + unsigned int msmLineRxGoodFramesCounter_0 : 16; /* 1E.9044.F:0 ROS Default = 0x0000 */ + /* Rx good frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Good Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9045.F:0 ROS MSM Line Rx Good Frames Counter 1 [F:0] + AQ_MsmLineRxGoodFramesCounterRegister_HHD.u1.bits_1.msmLineRxGoodFramesCounter_1 + + Default = 0x0000 + + Rx good frame counter bits 31:16 + + Notes: + Count of frames received without error (Including pause frames). */ + unsigned int msmLineRxGoodFramesCounter_1 : 16; /* 1E.9045.F:0 ROS Default = 0x0000 */ + /* Rx good frame counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxGoodFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx FCS Errors Counter Register: 1E.9048 */ +/* MSM Line Rx FCS Errors Counter Register: 1E.9048 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx FCS Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.9048.F:0 ROS MSM Line FCS Error Counter 0 [F:0] + AQ_MsmLineRxFcsErrorsCounterRegister_HHD.u0.bits_0.msmLineFcsErrorCounter_0 + + Default = 0x0000 + + Frame check sequence error counter bits 15:0 + + Notes: + Count of frames for which a CRC-32 Error is detected but the frame is otherwise of correct length. */ + unsigned int msmLineFcsErrorCounter_0 : 16; /* 1E.9048.F:0 ROS Default = 0x0000 */ + /* Frame check sequence error counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx FCS Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.9049.F:0 ROS MSM Line FCS Error Counter 1 [F:0] + AQ_MsmLineRxFcsErrorsCounterRegister_HHD.u1.bits_1.msmLineFcsErrorCounter_1 + + Default = 0x0000 + + Frame check sequence error counter bits 31:16 + + Notes: + Count of frames for which a CRC-32 Error is detected but the frame is otherwise of correct length. */ + unsigned int msmLineFcsErrorCounter_1 : 16; /* 1E.9049.F:0 ROS Default = 0x0000 */ + /* Frame check sequence error counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxFcsErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Alignment Errors Counter Register: 1E.904C */ +/* MSM Line Rx Alignment Errors Counter Register: 1E.904C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Alignment Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.904C.F:0 ROS MSM Line Alignment Error Counter 0 [F:0] + AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD.u0.bits_0.msmLineAlignmentErrorCounter_0 + + Default = 0x0000 + + Alignment error counter bits 15:0 + + Notes: + Count of frames received with an alignment error. */ + unsigned int msmLineAlignmentErrorCounter_0 : 16; /* 1E.904C.F:0 ROS Default = 0x0000 */ + /* Alignment error counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Alignment Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.904D.F:0 ROS MSM Line Alignment Error Counter 1 [F:0] + AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD.u1.bits_1.msmLineAlignmentErrorCounter_1 + + Default = 0x0000 + + Alignment error counter bits 31:16 + + Notes: + Count of frames received with an alignment error. */ + unsigned int msmLineAlignmentErrorCounter_1 : 16; /* 1E.904D.F:0 ROS Default = 0x0000 */ + /* Alignment error counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx Pause Frames Counter Register: 1E.9050 */ +/* MSM Line Tx Pause Frames Counter Register: 1E.9050 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9050.F:0 ROS MSM Line Tx Pause Frames Counter 0 [F:0] + AQ_MsmLineTxPauseFramesCounterRegister_HHD.u0.bits_0.msmLineTxPauseFramesCounter_0 + + Default = 0x0000 + + Tx pause frame counter bits 15:0 + + Notes: + Valid pause frames transmitted. */ + unsigned int msmLineTxPauseFramesCounter_0 : 16; /* 1E.9050.F:0 ROS Default = 0x0000 */ + /* Tx pause frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9051.F:0 ROS MSM Line Tx Pause Frames Counter 1 [F:0] + AQ_MsmLineTxPauseFramesCounterRegister_HHD.u1.bits_1.msmLineTxPauseFramesCounter_1 + + Default = 0x0000 + + Tx pause frame counter bits 31:16 + + + Notes: + Valid pause frames transmitted. */ + unsigned int msmLineTxPauseFramesCounter_1 : 16; /* 1E.9051.F:0 ROS Default = 0x0000 */ + /* Tx pause frame counter bits 31:16 + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxPauseFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Pause Frames Counter Register: 1E.9054 */ +/* MSM Line Rx Pause Frames Counter Register: 1E.9054 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9054.F:0 ROS MSM Line Rx Pause Frames Counter 0 [F:0] + AQ_MsmLineRxPauseFramesCounterRegister_HHD.u0.bits_0.msmLineRxPauseFramesCounter_0 + + Default = 0x0000 + + Rx pause frame counter bits 15:0 + + Notes: + Valid pause frames received. */ + unsigned int msmLineRxPauseFramesCounter_0 : 16; /* 1E.9054.F:0 ROS Default = 0x0000 */ + /* Rx pause frame counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Pause Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9055.F:0 ROS MSM Line Rx Pause Frames Counter 1 [F:0] + AQ_MsmLineRxPauseFramesCounterRegister_HHD.u1.bits_1.msmLineRxPauseFramesCounter_1 + + Default = 0x0000 + + Rx pause frame counter bits 31:16 + + Notes: + Valid pause frames received. */ + unsigned int msmLineRxPauseFramesCounter_1 : 16; /* 1E.9055.F:0 ROS Default = 0x0000 */ + /* Rx pause frame counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxPauseFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Too Long Errors Counter Register: 1E.9058 */ +/* MSM Line Rx Too Long Errors Counter Register: 1E.9058 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Too Long Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.9058.F:0 ROS MSM Line Rx Too Long Errors Counter 0 [F:0] + AQ_MsmLineRxTooLongErrorsCounterRegister_HHD.u0.bits_0.msmLineRxTooLongErrorsCounter_0 + + Default = 0x0000 + + Too-long errors counter bits 15:0 + + Notes: + Frame received exceeded the maximum length programmed with register FRM_LGTH. */ + unsigned int msmLineRxTooLongErrorsCounter_0 : 16; /* 1E.9058.F:0 ROS Default = 0x0000 */ + /* Too-long errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Too Long Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.9059.F:0 ROS MSM Line Rx Too Long Errors Counter 1 [F:0] + AQ_MsmLineRxTooLongErrorsCounterRegister_HHD.u1.bits_1.msmLineRxTooLongErrorsCounter_1 + + Default = 0x0000 + + Too-long errors counter bits 31:16 + + Notes: + Frame received exceeded the maximum length programmed with register FRM_LGTH. */ + unsigned int msmLineRxTooLongErrorsCounter_1 : 16; /* 1E.9059.F:0 ROS Default = 0x0000 */ + /* Too-long errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxTooLongErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx In Range Length Errors Counter Register: 1E.905C */ +/* MSM Line Rx In Range Length Errors Counter Register: 1E.905C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx In Range Length Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.905C.F:0 ROS MSM Line Rx In Range Length Errors Counter 0 [F:0] + AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD.u0.bits_0.msmLineRxInRangeLengthErrorsCounter_0 + + Default = 0x0000 + + In-range-length errors counter bits 15:0 + + Notes: + A count of frames with a length/type field value between 46 (VLAN: 42) and less than 0x0600, that does not match the number of payload data octets received. Should count also if length/type field is less than 46 (VLAN: 42) and the frame is longer than 64 bytes. */ + unsigned int msmLineRxInRangeLengthErrorsCounter_0 : 16; /* 1E.905C.F:0 ROS Default = 0x0000 */ + /* In-range-length errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx In Range Length Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.905D.F:0 ROS MSM Line Rx In Range Length Errors Counter 1 [F:0] + AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD.u1.bits_1.msmLineRxInRangeLengthErrorsCounter_1 + + Default = 0x0000 + + In-range-length errors counter bits 31:16 + + Notes: + A count of frames with a length/type field value between 46 (VLAN: 42) and less than 0x0600, that does not match the number of payload data octets received. Should count also if length/type field is less than 46 (VLAN: 42) and the frame is longer than 64 bytes. */ + unsigned int msmLineRxInRangeLengthErrorsCounter_1 : 16; /* 1E.905D.F:0 ROS Default = 0x0000 */ + /* In-range-length errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx VLAN Frames Counter Register: 1E.9060 */ +/* MSM Line Tx VLAN Frames Counter Register: 1E.9060 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9060.F:0 ROS MSM Line Tx VLAN Frames Counter 0 [F:0] + AQ_MsmLineTxVlanFramesCounterRegister_HHD.u0.bits_0.msmLineTxVlanFramesCounter_0 + + Default = 0x0000 + + Tx VLAN frames counter bits 15:0 + + Notes: + Valid VLAN tagged frames transmitted. */ + unsigned int msmLineTxVlanFramesCounter_0 : 16; /* 1E.9060.F:0 ROS Default = 0x0000 */ + /* Tx VLAN frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9061.F:0 ROS MSM Line Tx VLAN Frames Counter 1 [F:0] + AQ_MsmLineTxVlanFramesCounterRegister_HHD.u1.bits_1.msmLineTxVlanFramesCounter_1 + + Default = 0x0000 + + Tx VLAN frames counter bits 31:16 + + Notes: + Valid VLAN tagged frames transmitted. */ + unsigned int msmLineTxVlanFramesCounter_1 : 16; /* 1E.9061.F:0 ROS Default = 0x0000 */ + /* Tx VLAN frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxVlanFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx VLAN Frames Counter Register: 1E.9064 */ +/* MSM Line Rx VLAN Frames Counter Register: 1E.9064 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9064.F:0 ROS MSM Line Rx VLAN Frames Counter 0 [F:0] + AQ_MsmLineRxVlanFramesCounterRegister_HHD.u0.bits_0.msmLineRxVlanFramesCounter_0 + + Default = 0x0000 + + Rx VLAN frames counter bits 15:0 + + Notes: + Valid VLAN tagged frames received. */ + unsigned int msmLineRxVlanFramesCounter_0 : 16; /* 1E.9064.F:0 ROS Default = 0x0000 */ + /* Rx VLAN frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx VLAN Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9065.F:0 ROS MSM Line Rx VLAN Frames Counter 1 [F:0] + AQ_MsmLineRxVlanFramesCounterRegister_HHD.u1.bits_1.msmLineRxVlanFramesCounter_1 + + Default = 0x0000 + + Rx VLAN frames counter bits 31:16 + + Notes: + Valid VLAN tagged frames received. */ + unsigned int msmLineRxVlanFramesCounter_1 : 16; /* 1E.9065.F:0 ROS Default = 0x0000 */ + /* Rx VLAN frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxVlanFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx Octets Counter Register: 1E.9068 */ +/* MSM Line Tx Octets Counter Register: 1E.9068 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.9068.F:0 ROS MSM Line Tx Octets Counter 0 [F:0] + AQ_MsmLineTxOctetsCounterRegister_HHD.u0.bits_0.msmLineTxOctetsCounter_0 + + Default = 0x0000 + + Tx octets counter bits 15:0 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmLineTxOctetsCounter_0 : 16; /* 1E.9068.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.9069.F:0 ROS MSM Line Tx Octets Counter 1 [F:0] + AQ_MsmLineTxOctetsCounterRegister_HHD.u1.bits_1.msmLineTxOctetsCounter_1 + + Default = 0x0000 + + Tx octets counter bits 31:16 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmLineTxOctetsCounter_1 : 16; /* 1E.9069.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of MSM Line Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.906A.F:0 ROS MSM Line Tx Octets Counter 2 [F:0] + AQ_MsmLineTxOctetsCounterRegister_HHD.u2.bits_2.msmLineTxOctetsCounter_2 + + Default = 0x0000 + + Tx octets counter bits 47:32 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmLineTxOctetsCounter_2 : 16; /* 1E.906A.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 47:32 */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of MSM Line Tx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.906B.F:0 ROS MSM Line Tx Octets Counter 3 [F:0] + AQ_MsmLineTxOctetsCounterRegister_HHD.u3.bits_3.msmLineTxOctetsCounter_3 + + Default = 0x0000 + + Tx octets counter bits 63:48 + + Notes: + All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ + unsigned int msmLineTxOctetsCounter_3 : 16; /* 1E.906B.F:0 ROS Default = 0x0000 */ + /* Tx octets counter bits 63:48 */ + } bits_3; + uint16_t word_3; + } u3; +} AQ_MsmLineTxOctetsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Octets Counter Register: 1E.906C */ +/* MSM Line Rx Octets Counter Register: 1E.906C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.906C.F:0 ROS MSM Line Rx Octets Counter 0 [F:0] + AQ_MsmLineRxOctetsCounterRegister_HHD.u0.bits_0.msmLineRxOctetsCounter_0 + + Default = 0x0000 + + Rx octets counter bits 15:0 + + Notes: + All octets received except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames received. */ + unsigned int msmLineRxOctetsCounter_0 : 16; /* 1E.906C.F:0 ROS Default = 0x0000 */ + /* Rx octets counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Octets Counter Register */ + union + { + struct + { + /*! \brief 1E.906D.F:0 ROS MSM Line Rx Octets Counter 1 [F:0] + AQ_MsmLineRxOctetsCounterRegister_HHD.u1.bits_1.msmLineRxOctetsCounter_1 + + Default = 0x0000 + + Rx octets counter bits 31:16 + + Notes: + All octets received except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames received. */ + unsigned int msmLineRxOctetsCounter_1 : 16; /* 1E.906D.F:0 ROS Default = 0x0000 */ + /* Rx octets counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxOctetsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Unicast Frames Counter Register: 1E.9070 */ +/* MSM Line Rx Unicast Frames Counter Register: 1E.9070 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9070.F:0 ROS MSM Line Rx Unicast Frames Counter 0 [F:0] + AQ_MsmLineRxUnicastFramesCounterRegister_HHD.u0.bits_0.msmLineRxUnicastFramesCounter_0 + + Default = 0x0000 + + Rx unicast frames counter bits 15:0 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '0'. */ + unsigned int msmLineRxUnicastFramesCounter_0 : 16; /* 1E.9070.F:0 ROS Default = 0x0000 */ + /* Rx unicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9071.F:0 ROS MSM Line Rx Unicast Frames Counter 1 [F:0] + AQ_MsmLineRxUnicastFramesCounterRegister_HHD.u1.bits_1.msmLineRxUnicastFramesCounter_1 + + Default = 0x0000 + + Rx unicast frames counter bits 31:16 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '0'. */ + unsigned int msmLineRxUnicastFramesCounter_1 : 16; /* 1E.9071.F:0 ROS Default = 0x0000 */ + /* Rx unicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxUnicastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Multicast Frames Counter Register: 1E.9074 */ +/* MSM Line Rx Multicast Frames Counter Register: 1E.9074 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9074.F:0 ROS MSM Line Rx Multicast Frames Counter 0 [F:0] + AQ_MsmLineRxMulticastFramesCounterRegister_HHD.u0.bits_0.msmLineRxMulticastFramesCounter_0 + + Default = 0x0000 + + Rx multicast frames counter bits 15:0 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '1' but not the broadcast address (all bits set '1' ). Pause frames are not counted. */ + unsigned int msmLineRxMulticastFramesCounter_0 : 16; /* 1E.9074.F:0 ROS Default = 0x0000 */ + /* Rx multicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9075.F:0 ROS MSM Line Rx Multicast Frames Counter 1 [F:0] + AQ_MsmLineRxMulticastFramesCounterRegister_HHD.u1.bits_1.msmLineRxMulticastFramesCounter_1 + + Default = 0x0000 + + Rx multicast frames counter bits 31:16 + + Notes: + Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '1' but not the broadcast address (all bits set '1' ). Pause frames are not counted. */ + unsigned int msmLineRxMulticastFramesCounter_1 : 16; /* 1E.9075.F:0 ROS Default = 0x0000 */ + /* Rx multicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxMulticastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Broadcast Frames Counter Register: 1E.9078 */ +/* MSM Line Rx Broadcast Frames Counter Register: 1E.9078 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9078.F:0 ROS MSM Line Rx Broadcast Frames Counter 0 [F:0] + AQ_MsmLineRxBroadcastFramesCounterRegister_HHD.u0.bits_0.msmLineRxBroadcastFramesCounter_0 + + Default = 0x0000 + + Rx broadcast frames counter bits 15:0 + + Notes: + Incremented with each valid frame received on the receive FIFO interface (FIFO) and all bits of the destination address were set '1'. */ + unsigned int msmLineRxBroadcastFramesCounter_0 : 16; /* 1E.9078.F:0 ROS Default = 0x0000 */ + /* Rx broadcast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9079.F:0 ROS MSM Line Rx Broadcast Frames Counter 1 [F:0] + AQ_MsmLineRxBroadcastFramesCounterRegister_HHD.u1.bits_1.msmLineRxBroadcastFramesCounter_1 + + Default = 0x0000 + + Rx broadcast frames counter bits 31:16 + + Notes: + Incremented with each valid frame received on the receive FIFO interface (FIFO) and all bits of the destination address were set '1'. */ + unsigned int msmLineRxBroadcastFramesCounter_1 : 16; /* 1E.9079.F:0 ROS Default = 0x0000 */ + /* Rx broadcast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxBroadcastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx Errors Counter Register: 1E.907C */ +/* MSM Line Tx Errors Counter Register: 1E.907C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.907C.F:0 ROS MSM Line Tx Errors Counter 0 [F:0] + AQ_MsmLineTxErrorsCounterRegister_HHD.u0.bits_0.msmLineTxErrorsCounter_0 + + Default = 0x0000 + + Rx errors counter bits 15:0 + + Notes: + Number of frames transmitted with error: + - FIFO Overflow Errors + - FIFO Underflow Errors */ + unsigned int msmLineTxErrorsCounter_0 : 16; /* 1E.907C.F:0 ROS Default = 0x0000 */ + /* Rx errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.907D.F:0 ROS MSM Line Tx Errors Counter 1 [F:0] + AQ_MsmLineTxErrorsCounterRegister_HHD.u1.bits_1.msmLineTxErrorsCounter_1 + + Default = 0x0000 + + Tx errors counter bits 31:16 + + Notes: + Number of frames transmitted with error: + - FIFO Overflow Errors + - FIFO Underflow Errors */ + unsigned int msmLineTxErrorsCounter_1 : 16; /* 1E.907D.F:0 ROS Default = 0x0000 */ + /* Tx errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx Unicast Frames Counter Register: 1E.9084 */ +/* MSM Line Tx Unicast Frames Counter Register: 1E.9084 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9084.F:0 ROS MSM Line Tx Unicast Frames Counter 0 [F:0] + AQ_MsmLineTxUnicastFramesCounterRegister_HHD.u0.bits_0.msmLineTxUnicastFramesCounter_0 + + Default = 0x0000 + + Tx unicast frames counter bits 15:0 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '0'. */ + unsigned int msmLineTxUnicastFramesCounter_0 : 16; /* 1E.9084.F:0 ROS Default = 0x0000 */ + /* Tx unicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Unicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9085.F:0 ROS MSM Line Tx Unicast Frames Counter 1 [F:0] + AQ_MsmLineTxUnicastFramesCounterRegister_HHD.u1.bits_1.msmLineTxUnicastFramesCounter_1 + + Default = 0x0000 + + Tx unicast frames counter bits 31:16 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '0'. */ + unsigned int msmLineTxUnicastFramesCounter_1 : 16; /* 1E.9085.F:0 ROS Default = 0x0000 */ + /* Tx unicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxUnicastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx Multicast Frames Counter Register: 1E.9088 */ +/* MSM Line Tx Multicast Frames Counter Register: 1E.9088 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9088.F:0 ROS MSM Line Tx Multicast Frames Counter 0 [F:0] + AQ_MsmLineTxMulticastFramesCounterRegister_HHD.u0.bits_0.msmLineTxMulticastFramesCounter_0 + + Default = 0x0000 + + Tx multicast frames counter bits 15:0 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '1' but not the broadcast address (all bits '1'). */ + unsigned int msmLineTxMulticastFramesCounter_0 : 16; /* 1E.9088.F:0 ROS Default = 0x0000 */ + /* Tx multicast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Multicast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.9089.F:0 ROS MSM Line Tx Multicast Frames Counter 1 [F:0] + AQ_MsmLineTxMulticastFramesCounterRegister_HHD.u1.bits_1.msmLineTxMulticastFramesCounter_1 + + Default = 0x0000 + + Tx multicast frames counter bits 31:16 + + Notes: + Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '1' but not the broadcast address (all bits '1'). */ + unsigned int msmLineTxMulticastFramesCounter_1 : 16; /* 1E.9089.F:0 ROS Default = 0x0000 */ + /* Tx multicast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxMulticastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Tx Broadcast Frames Counter Register: 1E.908C */ +/* MSM Line Tx Broadcast Frames Counter Register: 1E.908C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.908C.F:0 ROS MSM Line Tx Broadcast Frames Counter 0 [F:0] + AQ_MsmLineTxBroadcastFramesCounterRegister_HHD.u0.bits_0.msmLineTxBroadcastFramesCounter_0 + + Default = 0x0000 + + Tx broadcast frames counter bits 15:0 + + Notes: + Incremented with each frame written to the FIFO interface and all bits of the destination address set to '1'. */ + unsigned int msmLineTxBroadcastFramesCounter_0 : 16; /* 1E.908C.F:0 ROS Default = 0x0000 */ + /* Tx broadcast frames counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Broadcast Frames Counter Register */ + union + { + struct + { + /*! \brief 1E.908D.F:0 ROS MSM Line Tx Broadcast Frames Counter 1 [F:0] + AQ_MsmLineTxBroadcastFramesCounterRegister_HHD.u1.bits_1.msmLineTxBroadcastFramesCounter_1 + + Default = 0x0000 + + Tx broadcast frames counter bits 31:16 + + Notes: + Incremented with each frame written to the FIFO interface and all bits of the destination address set to '1'. */ + unsigned int msmLineTxBroadcastFramesCounter_1 : 16; /* 1E.908D.F:0 ROS Default = 0x0000 */ + /* Tx broadcast frames counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineTxBroadcastFramesCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief MSM Line Rx Errors Counter Register: 1E.90C8 */ +/* MSM Line Rx Errors Counter Register: 1E.90C8 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.90C8.F:0 ROS MSM Line Rx Errors Counter 0 [F:0] + AQ_MsmLineRxErrorsCounterRegister_HHD.u0.bits_0.msmLineRxErrorsCounter_0 + + Default = 0x0000 + + Rx errors counter bits 15:0 + + Notes: + Number of frames received with error: + - FIFO Overflow Errors + - CRC Errors + - Payload Length Errors + - Jabber and Oversized Errors + - Alignment Errors + - The dedicated Error Code (0xfe, not a code error) was received */ + unsigned int msmLineRxErrorsCounter_0 : 16; /* 1E.90C8.F:0 ROS Default = 0x0000 */ + /* Rx errors counter bits 15:0 */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Errors Counter Register */ + union + { + struct + { + /*! \brief 1E.90C9.F:0 ROS MSM Line Rx Errors Counter 1 [F:0] + AQ_MsmLineRxErrorsCounterRegister_HHD.u1.bits_1.msmLineRxErrorsCounter_1 + + Default = 0x0000 + + Rx errors counter bits 31:16 + + Notes: + Number of frames received with error: + - FIFO Overflow Errors + - CRC Errors + - Payload Length Errors + - Jabber and Oversized Errors + - Alignment Errors + - The dedicated Error Code (0xfe, not a code error) was received */ + unsigned int msmLineRxErrorsCounter_1 : 16; /* 1E.90C9.F:0 ROS Default = 0x0000 */ + /* Rx errors counter bits 31:16 */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_MsmLineRxErrorsCounterRegister_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Control: 1E.C000 */ +/* Global Control: 1E.C000 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Control */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Control */ + union + { + struct + { + /*! \brief 1E.C001.F R/W uP Reset + AQ_GlobalControl_HHD.u1.bits_1.upReset + + Default = 0x0 + + 1 = Reset + + + Notes: + Resets the uP and the PIF master and slave bus. Will be active for a minimum of 100 microseconds. */ + unsigned int upReset : 1; /* 1E.C001.F R/W Default = 0x0 */ + /* 1 = Reset + */ + unsigned int reserved0 : 8; + /*! \brief 1E.C001.6 R/W uP Run Stall Override + AQ_GlobalControl_HHD.u1.bits_1.upRunStallOverride + + Default = 0x0 + + 0 = uP Run Stall from "MDIO Boot Load" pin. + 1 = uP Run Stall from See MCP Run Stall bit + + + + Notes: + This bit selects the uP Run Stall from either the "MDIO Boot Load" pin or the See MCP Run Stall bit. Pin no longer brought out as deprecated. */ + unsigned int upRunStallOverride : 1; /* 1E.C001.6 R/W Default = 0x0 */ + /* 0 = uP Run Stall from "MDIO Boot Load" pin. + 1 = uP Run Stall from See MCP Run Stall bit + + */ + unsigned int reserved1 : 5; + /*! \brief 1E.C001.0 R/W uP Run Stall + AQ_GlobalControl_HHD.u1.bits_1.upRunStall + + Default = 0x0 + + 1 = uP Run Stall + 0 = uP normal mode + + + Notes: + Deactivates the uP. */ + unsigned int upRunStall : 1; /* 1E.C001.0 R/W Default = 0x0 */ + /* 1 = uP Run Stall + 0 = uP normal mode + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalControl_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Reset Control: 1E.C006 */ +/* Global Reset Control: 1E.C006 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Reset Control */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.C006.E R/WPD Global MMD Reset Disable + AQ_GlobalResetControl_HHD.u0.bits_0.globalMMD_ResetDisable + + Provisionable Default = 0x0 + + 1 = Disable the S/W reset to the Global MMD registers + 0 = Enable the S/W reset to the Global MMD registers + + + Notes: + Setting this bit prevents a Global S/W reset or Global S/W reset from resetting the Global MMD registers */ + unsigned int globalMMD_ResetDisable : 1; /* 1E.C006.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Disable the S/W reset to the Global MMD registers + 0 = Enable the S/W reset to the Global MMD registers + */ + unsigned int reserved1 : 14; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalResetControl_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Diagnostic Provisioning: 1E.C400 */ +/* Global Diagnostic Provisioning: 1E.C400 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Diagnostic Provisioning */ + union + { + struct + { + /*! \brief 1E.C400.F R/WPD Enable Diagnostics + AQ_GlobalDiagnosticProvisioning_HHD.u0.bits_0.enableDiagnostics + + Provisionable Default = 0x1 + + 1 = Chip performs diagnostics on power-up + */ + unsigned int enableDiagnostics : 1; /* 1E.C400.F R/WPD Provisionable Default = 0x1 */ + /* 1 = Chip performs diagnostics on power-up */ + unsigned int reserved0 : 15; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalDiagnosticProvisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Thermal Provisioning: 1E.C420 */ +/* Global Thermal Provisioning: 1E.C420 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C420.F:0 R/WPD Reserved 0 [F:0] + AQ_GlobalThermalProvisioning_HHD.u0.bits_0.reserved_0 + + Provisionable Default = 0x0000 + + Internal reserved - do not modify + + */ + unsigned int reserved_0 : 16; /* 1E.C420.F:0 R/WPD Provisionable Default = 0x0000 */ + /* Internal reserved - do not modify + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C421.F:0 R/WPD High Temp Failure Threshold [F:0] + AQ_GlobalThermalProvisioning_HHD.u1.bits_1.highTempFailureThreshold + + Provisionable Default = 0x4600 + + [F:0] of high temperature failure threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 70 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A000 - 1.A001: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int highTempFailureThreshold : 16; /* 1E.C421.F:0 R/WPD Provisionable Default = 0x4600 */ + /* [F:0] of high temperature failure threshold */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C422.F:0 R/WPD Low Temp Failure Threshold [F:0] + AQ_GlobalThermalProvisioning_HHD.u2.bits_2.lowTempFailureThreshold + + Provisionable Default = 0x0000 + + [F:0] of low temperature failure threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 0 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A002 - 1.A003: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int lowTempFailureThreshold : 16; /* 1E.C422.F:0 R/WPD Provisionable Default = 0x0000 */ + /* [F:0] of low temperature failure threshold */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C423.F:0 R/WPD High Temp Warning Threshold [F:0] + AQ_GlobalThermalProvisioning_HHD.u3.bits_3.highTempWarningThreshold + + Provisionable Default = 0x3C00 + + [F:0] of high temperature warning threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD008. Default is 60 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A004 - 1.A005: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int highTempWarningThreshold : 16; /* 1E.C423.F:0 R/WPD Provisionable Default = 0x3C00 */ + /* [F:0] of high temperature warning threshold */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Thermal Provisioning */ + union + { + struct + { + /*! \brief 1E.C424.F:0 R/WPD Low Temp Warning Threshold [F:0] + AQ_GlobalThermalProvisioning_HHD.u4.bits_4.lowTempWarningThreshold + + Provisionable Default = 0x0A00 + + [F:0] of low temperature warning threshold + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 10 degreesC. + + In XENPAK mode, F/W will use the XENPAK register 1.A006 - 1.A007: instead of this register. + + NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ + unsigned int lowTempWarningThreshold : 16; /* 1E.C424.F:0 R/WPD Provisionable Default = 0x0A00 */ + /* [F:0] of low temperature warning threshold */ + } bits_4; + uint16_t word_4; + } u4; +} AQ_GlobalThermalProvisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global LED Provisioning: 1E.C430 */ +/* Global LED Provisioning: 1E.C430 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 2; + /*! \brief 1E.C430.D:9 R/WPD Reserved Provisioning C430 [4:0] + AQ_GlobalLedProvisioning_HHD.u0.bits_0.reservedProvisioningC430 + + Provisionable Default = 0x00 + + Reserved for future use + */ + unsigned int reservedProvisioningC430 : 5; /* 1E.C430.D:9 R/WPD Provisionable Default = 0x00 */ + /* Reserved for future use */ + /*! \brief 1E.C430.8 R/WPD LED #0 Manual Set + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_0ManualSet : 1; /* 1E.C430.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + /*! \brief 1E.C430.7 R/WPD LED #0 10 Gb/s Link Established + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_0_10Gb_sLinkEstablished : 1; /* 1E.C430.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C430.6 R/WPD LED #0 1 Gb/s Link Established + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_0_1Gb_sLinkEstablished : 1; /* 1E.C430.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C430.5 R/WPD LED #0 100 Mb/s Link Established + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s. + + */ + unsigned int led_0_100Mb_sLinkEstablished : 1; /* 1E.C430.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s. + */ + /*! \brief 1E.C430.4 R/WPD LED #0 Connecting + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_0Connecting : 1; /* 1E.C430.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C430.3 R/WPD LED #0 Receive Activity + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_0ReceiveActivity : 1; /* 1E.C430.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C430.2 R/WPD LED #0 Transmit Activity + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_0TransmitActivity : 1; /* 1E.C430.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C430.1:0 R/WPD LED #0 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_0ActivityStretch : 2; /* 1E.C430.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 2; + /*! \brief 1E.C431.D:9 R/WPD Reserved Provisioning C431 [4:0] + AQ_GlobalLedProvisioning_HHD.u1.bits_1.reservedProvisioningC431 + + Provisionable Default = 0x00 + + Reserved for future use + */ + unsigned int reservedProvisioningC431 : 5; /* 1E.C431.D:9 R/WPD Provisionable Default = 0x00 */ + /* Reserved for future use */ + /*! \brief 1E.C431.8 R/WPD LED #1 Manual Set + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_1ManualSet : 1; /* 1E.C431.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + /*! \brief 1E.C431.7 R/WPD LED #1 10 Gb/s Link Established + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_1_10Gb_sLinkEstablished : 1; /* 1E.C431.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C431.6 R/WPD LED #1 1 Gb/s Link Established + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_1_1Gb_sLinkEstablished : 1; /* 1E.C431.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C431.5 R/WPD LED #1 100 Mb/s Link Established + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s. + + */ + unsigned int led_1_100Mb_sLinkEstablished : 1; /* 1E.C431.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s. + */ + /*! \brief 1E.C431.4 R/WPD LED #1 Connecting + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_1Connecting : 1; /* 1E.C431.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C431.3 R/WPD LED #1 Receive Activity + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_1ReceiveActivity : 1; /* 1E.C431.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C431.2 R/WPD LED #1 Transmit Activity + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_1TransmitActivity : 1; /* 1E.C431.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C431.1:0 R/WPD LED #1 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_1ActivityStretch : 2; /* 1E.C431.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 2; + /*! \brief 1E.C432.D:9 R/WPD Reserved Provisioning C432 [4:0] + AQ_GlobalLedProvisioning_HHD.u2.bits_2.reservedProvisioningC432 + + Provisionable Default = 0x00 + + Reserved for future use + */ + unsigned int reservedProvisioningC432 : 5; /* 1E.C432.D:9 R/WPD Provisionable Default = 0x00 */ + /* Reserved for future use */ + /*! \brief 1E.C432.8 R/WPD LED #2 Manual Set + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2ManualSet + + Provisionable Default = 0x0 + + 1 = LED On + + */ + unsigned int led_2ManualSet : 1; /* 1E.C432.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED On + */ + /*! \brief 1E.C432.7 R/WPD LED #2 10 Gb/s Link Established + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2_10Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 10 Gb/s + + */ + unsigned int led_2_10Gb_sLinkEstablished : 1; /* 1E.C432.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 10 Gb/s + */ + /*! \brief 1E.C432.6 R/WPD LED #2 1 Gb/s Link Established + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2_1Gb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 1 Gb/s + + */ + unsigned int led_2_1Gb_sLinkEstablished : 1; /* 1E.C432.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 1 Gb/s + */ + /*! \brief 1E.C432.5 R/WPD LED #2 100 Mb/s Link Established + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2_100Mb_sLinkEstablished + + Provisionable Default = 0x0 + + 1 = LED is on when link connects at 100 Mb/s. + */ + unsigned int led_2_100Mb_sLinkEstablished : 1; /* 1E.C432.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when link connects at 100 Mb/s. */ + /*! \brief 1E.C432.4 R/WPD LED #2 Connecting + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2Connecting + + Provisionable Default = 0x0 + + 1 = LED is on when attempting to connect. + + */ + unsigned int led_2Connecting : 1; /* 1E.C432.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED is on when attempting to connect. + */ + /*! \brief 1E.C432.3 R/WPD LED #2 Receive Activity + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2ReceiveActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on receive activity + + */ + unsigned int led_2ReceiveActivity : 1; /* 1E.C432.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on receive activity + */ + /*! \brief 1E.C432.2 R/WPD LED #2 Transmit Activity + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2TransmitActivity + + Provisionable Default = 0x0 + + 1 = LED toggles on transmit activity + + */ + unsigned int led_2TransmitActivity : 1; /* 1E.C432.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED toggles on transmit activity + */ + /*! \brief 1E.C432.1:0 R/WPD LED #2 Activity Stretch [1:0] + AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2ActivityStretch + + Provisionable Default = 0x3 + + [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + + */ + unsigned int led_2ActivityStretch : 2; /* 1E.C432.1:0 R/WPD Provisionable Default = 0x3 */ + /* [1:0] + 0x3 = stretch activity by 100 ms + 0x2 = stretch activity by 60 ms + 0x1 = stretch activity by 28 ms + 0x0 = no stretching + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 15; + /*! \brief 1E.C437.0 R/WPD LED Operation Mode + AQ_GlobalLedProvisioning_HHD.u7.bits_7.ledOperationMode + + Provisionable Default = 0x0 + + 1 = LED link activity in Mode #2 + 0 = LED link activity in Aquantia classic mode + + + Notes: + When set to 1, the LED blinking rate is based on Mode #2 algorithm. When set to 0, the LED blinking rate is based on the classic Aquantia algorithm. */ + unsigned int ledOperationMode : 1; /* 1E.C437.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = LED link activity in Mode #2 + 0 = LED link activity in Aquantia classic mode + */ + } bits_7; + uint16_t word_7; + } u7; + /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_8; + uint16_t word_8; + } u8; + /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_9; + uint16_t word_9; + } u9; + /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_10; + uint16_t word_10; + } u10; + /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_11; + uint16_t word_11; + } u11; + /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_12; + uint16_t word_12; + } u12; + /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_13; + uint16_t word_13; + } u13; + /*! \brief Union for bit and word level access of word 14 of Global LED Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_14; + uint16_t word_14; + } u14; +} AQ_GlobalLedProvisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global General Provisioning: 1E.C440 */ +/* Global General Provisioning: 1E.C440 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.C441.E R/WPD MDIO Broadcast Mode Enable + AQ_GlobalGeneralProvisioning_HHD.u1.bits_1.mdioBroadcastModeEnable + + Provisionable Default = 0x0 + + 1 = Enable broadcast on address set in 1E.C446 + 0 = Disable broadcast on n address set in 1E.C446 + + + Notes: + When enabled, writes and load MMD address opcodes are supported. Read opcodes are ignored. */ + unsigned int mdioBroadcastModeEnable : 1; /* 1E.C441.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable broadcast on address set in 1E.C446 + 0 = Disable broadcast on n address set in 1E.C446 + */ + /*! \brief 1E.C441.D R/WPD MDIO Read MSW First Enable + AQ_GlobalGeneralProvisioning_HHD.u1.bits_1.mdioReadMSW_FirstEnable + + Provisionable Default = 0x0 + + 1 = MSW of counter must be read first + 0 = LSW of counter must be read first + + + Notes: + This bit configures whether the MSW or LSW must be read first for counters greater than 16 bits. */ + unsigned int mdioReadMSW_FirstEnable : 1; /* 1E.C441.D R/WPD Provisionable Default = 0x0 */ + /* 1 = MSW of counter must be read first + 0 = LSW of counter must be read first + */ + unsigned int reserved1 : 8; + /*! \brief 1E.C441.4 R/WPD MDIO Drive Configuration + AQ_GlobalGeneralProvisioning_HHD.u1.bits_1.mdioDriveConfiguration + + Provisionable Default = 0x0 + + 0 = MDIO driver is in normal mode + 1 = MDIO driver is in open drain mode + + + Notes: + When the MDIO driver is in open drain mode during a read cycle, "0" data will be actively driven out of the MDIO, "1" data will set the MDIO driver in high impedance state and an external pullup will set the MDIO line to "1". The Turn-Around "0" will also be actively driven out of the MDIO, therefore in open drain mode, the Turn-Around is still "Z0". */ + unsigned int mdioDriveConfiguration : 1; /* 1E.C441.4 R/WPD Provisionable Default = 0x0 */ + /* 0 = MDIO driver is in normal mode + 1 = MDIO driver is in open drain mode + */ + /*! \brief 1E.C441.3 R/WPD MDIO Preamble Detection Disable + AQ_GlobalGeneralProvisioning_HHD.u1.bits_1.mdioPreambleDetectionDisable + + Provisionable Default = 0x0 + + 1 = Suppress preamble detection on MDIO + 0 = Enable preamble detection on MDIO + + */ + unsigned int mdioPreambleDetectionDisable : 1; /* 1E.C441.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = Suppress preamble detection on MDIO + 0 = Enable preamble detection on MDIO + */ + unsigned int reserved2 : 1; + unsigned int reserved3 : 2; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 15; + /*! \brief 1E.C442.0 R/W Daisy Chain Reset + AQ_GlobalGeneralProvisioning_HHD.u2.bits_2.daisyChainReset + + Default = 0x0 + + 1 = Reset the daisy chain + + + Notes: + Toggling this bit from 0 to 1 will reload the IRAM and DRAM and reset the uP. The uP will be in uP run stall during the reload process. After the reload process, uP run stall will be de-asserted and the uP reset will be asserted. Note that before setting this bit, the See Soft Reset bit needs to be de-asserted. */ + unsigned int daisyChainReset : 1; /* 1E.C442.0 R/W Default = 0x0 */ + /* 1 = Reset the daisy chain + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 11; + /*! \brief 1E.C447.4:0 R/WPD MDIO Broadcast Address Configuration [4:0] + AQ_GlobalGeneralProvisioning_HHD.u7.bits_7.mdioBroadcastAddressConfiguration + + Provisionable Default = 0x1F + + Broadcast address + + + Notes: + Allows setting the broadcast address. By default this is set to 0x1F */ + unsigned int mdioBroadcastAddressConfiguration : 5; /* 1E.C447.4:0 R/WPD Provisionable Default = 0x1F */ + /* Broadcast address + */ + } bits_7; + uint16_t word_7; + } u7; + /*! \brief Union for bit and word level access of word 8 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 16; + } bits_8; + uint16_t word_8; + } u8; + /*! \brief Union for bit and word level access of word 9 of Global General Provisioning */ + union + { + struct + { + unsigned int reserved0 : 9; + /*! \brief 1E.C449.6:0 R/W MDIO Preamble Length [6:0] + AQ_GlobalGeneralProvisioning_HHD.u9.bits_9.mdioPreambleLength + + Default = 0x02 + + MDIO Preamble Length + + */ + unsigned int mdioPreambleLength : 7; /* 1E.C449.6:0 R/W Default = 0x02 */ + /* MDIO Preamble Length + */ + } bits_9; + uint16_t word_9; + } u9; +} AQ_GlobalGeneralProvisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global NVR Provisioning: 1E.C450 */ +/* Global NVR Provisioning: 1E.C450 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global NVR Provisioning */ + union + { + struct + { + unsigned int reserved0 : 5; + /*! \brief 1E.C450.A:8 R/WPD NVR Data Length [2:0] + AQ_GlobalNvrProvisioning_HHD.u0.bits_0.nvrDataLength + + Provisionable Default = 0x4 + + NVR data length ranges from 0 bytes to 4 bytes + + + Notes: + This sets the length of the data burst used in read and write operations. + */ + unsigned int nvrDataLength : 3; /* 1E.C450.A:8 R/WPD Provisionable Default = 0x4 */ + /* NVR data length ranges from 0 bytes to 4 bytes + */ + unsigned int reserved1 : 1; + /*! \brief 1E.C450.6:4 R/WPD NVR Dummy Length [2:0] + AQ_GlobalNvrProvisioning_HHD.u0.bits_0.nvrDummyLength + + Provisionable Default = 0x0 + + NVR dummy length ranges from 0 bytes to 4 bytes + + + Notes: + This sets the length of the dummy field used in some manufacturer's read status and write status operations. + */ + unsigned int nvrDummyLength : 3; /* 1E.C450.6:4 R/WPD Provisionable Default = 0x0 */ + /* NVR dummy length ranges from 0 bytes to 4 bytes + */ + unsigned int reserved2 : 2; + /*! \brief 1E.C450.1:0 R/WPD NVR Address Length [1:0] + AQ_GlobalNvrProvisioning_HHD.u0.bits_0.nvrAddressLength + + Provisionable Default = 0x2 + + NVR address length ranges from 0 bytes up to 3 bytes + + + Notes: + This sets the length of the address field used in read and write operations. Use of this field is enabled via Bit 8 of See Global NVR Provisioning 2: Address 1E.C451 . + */ + unsigned int nvrAddressLength : 2; /* 1E.C450.1:0 R/WPD Provisionable Default = 0x2 */ + /* NVR address length ranges from 0 bytes up to 3 bytes + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global NVR Provisioning */ + union + { + struct + { + unsigned int reserved0 : 7; + /*! \brief 1E.C451.8 R/WPD NVR Address Length Override + AQ_GlobalNvrProvisioning_HHD.u1.bits_1.nvrAddressLengthOverride + + Provisionable Default = 0x0 + + 0 = NVR address length is based on the "NVR_SIZE" pin. + 1 = NVR address length is based on the See NVR Address Length [1:0] register + + + Notes: + When this bit = 0 and NVR_SIZE pin = 0, the NVR address length is 2 bytes. When this bit = 0 and the NVR_SIZE pin = 1, the NVR address length is 3 bytes. When this bit = 1 the NVR address length is from the See NVR Address Length [1:0] */ + unsigned int nvrAddressLengthOverride : 1; /* 1E.C451.8 R/WPD Provisionable Default = 0x0 */ + /* 0 = NVR address length is based on the "NVR_SIZE" pin. + 1 = NVR address length is based on the See NVR Address Length [1:0] register + */ + /*! \brief 1E.C451.7:0 R/WPD NVR Clock Divide [7:0] + AQ_GlobalNvrProvisioning_HHD.u1.bits_1.nvrClockDivide + + Provisionable Default = 0xA0 + + NVR clock divide. Clock frequency is divided by the NVR clock divide + 1 + + */ + unsigned int nvrClockDivide : 8; /* 1E.C451.7:0 R/WPD Provisionable Default = 0xA0 */ + /* NVR clock divide. Clock frequency is divided by the NVR clock divide + 1 + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global NVR Provisioning */ + union + { + struct + { + unsigned int reserved0 : 14; + /*! \brief 1E.C452.1 R/W NVR Daisy Chain Clock Divide Override + AQ_GlobalNvrProvisioning_HHD.u2.bits_2.nvrDaisyChainClockDivideOverride + + Default = 0x0 + + 1 = Override NVR clock divide when in daisy chain master mode + + + Notes: + When in daisy chain master mode, the clock divide configuration is received from the FLASH. This bit will override the clock divide configuration from the FLASH with the See NVR Clock Divide [7:0] . */ + unsigned int nvrDaisyChainClockDivideOverride : 1; /* 1E.C452.1 R/W Default = 0x0 */ + /* 1 = Override NVR clock divide when in daisy chain master mode + */ + /*! \brief 1E.C452.0 R/W NVR Daisy Chain Disable + AQ_GlobalNvrProvisioning_HHD.u2.bits_2.nvrDaisyChainDisable + + Default = 0x0 + + 1 = Disable the Daisy Chain + + + Notes: + When in daisy chain master mode, the daisy chain and MDIO can both access the SPI. Setting this bit to 1 will disable the daisy chain from accessing the SPI and force it into a reset state. */ + unsigned int nvrDaisyChainDisable : 1; /* 1E.C452.0 R/W Default = 0x0 */ + /* 1 = Disable the Daisy Chain + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global NVR Provisioning */ + union + { + struct + { + unsigned int reserved0 : 11; + /*! \brief 1E.C453.4 R/W NVR Reset + AQ_GlobalNvrProvisioning_HHD.u3.bits_3.nvrReset + + Default = 0x0 + + 1 = Reset SPI + + */ + unsigned int nvrReset : 1; /* 1E.C453.4 R/W Default = 0x0 */ + /* 1 = Reset SPI + */ + unsigned int reserved1 : 4; + } bits_3; + uint16_t word_3; + } u3; +} AQ_GlobalNvrProvisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Reserved Provisioning: 1E.C470 */ +/* Global Reserved Provisioning: 1E.C470 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C470.F R/WPD Diagnostics Select + AQ_GlobalReservedProvisioning_HHD.u0.bits_0.diagnosticsSelect + + Provisionable Default = 0x0 + + 1 = Provide Extended MDI Diagnostics Information. + 0 = Provide normal cable diagnostics + + + Notes: + These bits select what sort of cable diagnostics to perform. For regular cable diagnostics, Bit F is set to zero, and the diagnostics are triggered by setting Bit 4. For extended diagnostics, Bit F is set to 1, and the desired extended diagnostics are selected by Bits E:D. The routine is then triggered by setting Bit 4. Each of the extended diagnostic routines present data for all for MDI pairs (A, B, C, D) consecutively, and after the data for each channel is gathered Bits F:D are reset. To get the data for the next pair, Bits F:D must be set back to the desired value (which must be the same as the initial channel). This continues until the data for all channels has been gathered. The address in memory where the data is stored is given in 1E.C802 and 1E.C804. + + For the case of PSD, the structure is as follows: + Int32 info + Int16 data[Len] + Info = Len << 16 | TxEnable << 8 | Pair (0 = A, etc.) + + For TDR: + Int32 info + Int16 tdr_A[Len] + Int16 tdr_B[Len] + Int16 tdr_C[Len] + Int16 tdr_D[Len] + + Info = Len << 16 | Channel + + TDR data is from the current pair to all other pairs. + + At the end of retrieving extended MDI diag data, the part will be reset. Conversely the only way to exit this routine once it starts is to issue a PMA reset. */ + unsigned int diagnosticsSelect : 1; /* 1E.C470.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Provide Extended MDI Diagnostics Information. + 0 = Provide normal cable diagnostics + */ + /*! \brief 1E.C470.E:D R/WPD Extended MDI Diagnostics Select [1:0] + AQ_GlobalReservedProvisioning_HHD.u0.bits_0.extendedMdiDiagnosticsSelect + + Provisionable Default = 0x0 + + 0x0 = TDR Data + 0x1 = RFI Channel PSD + 0x2 = Noise PSD while the local Tx is Off + 0x3 = Noise PSD while the local Tx is On + + + Notes: + These bits select what sort of cable diagnostics to perform. For regular cable diagnostics, Bit F is set to zero, and the diagnostics are triggered by setting Bit 4. For extended diagnostics, Bit F is set to 1, and the desired extended diagnostics are selected by Bits E:D. The routine is then triggered by setting Bit 4. Each of the extended diagnostic routines present data for all for MDI pairs (A, B, C, D) consecutively, and after the data for each channel is gathered Bits F:D are reset. To get the data for the next pair, Bits F:D must be set back to the desired value (which must be the same as the initial channel). This continues until the data for all channels has been gathered. The address in memory where the data is stored is given in 1E.C802 and 1E.C804. + + For the case of PSD, the structure is as follows: + Int32 info + Int16 data[Len] + Info = Len << 16 | TxEnable << 8 | Pair (0 = A, etc.) + + For TDR: + Int32 info + Int16 tdr_A[Len] + Int16 tdr_B[Len] + Int16 tdr_C[Len] + Int16 tdr_D[Len] + + Info = Len << 16 | Channel + + TDR data is from the current pair to all other pairs. + + At the end of retrieving extended MDI diag data, the part will be reset. Conversely the only way to exit this routine once it starts is to issue a PMA reset. */ + unsigned int extendedMdiDiagnosticsSelect : 2; /* 1E.C470.E:D R/WPD Provisionable Default = 0x0 */ + /* 0x0 = TDR Data + 0x1 = RFI Channel PSD + 0x2 = Noise PSD while the local Tx is Off + 0x3 = Noise PSD while the local Tx is On + */ + unsigned int reserved0 : 5; + unsigned int reserved1 : 3; + /*! \brief 1E.C470.4 R/WSC Initiate Cable Diagnostics + AQ_GlobalReservedProvisioning_HHD.u0.bits_0.initiateCableDiagnostics + + Default = 0x0 + + 1 = Perform cable diagnostics + + + Notes: + Perform cable diagnostics regardless of link state. If link is up, setting this bit will cause the link to drop while diagnostics are performed. This bit is self-clearing upon completion of the cable diagnostics. + + NOTE!! This is a processor intensive operation. Completion of this operation can also be monitored via 1E.C831.F */ + unsigned int initiateCableDiagnostics : 1; /* 1E.C470.4 R/WSC Default = 0x0 */ + /* 1 = Perform cable diagnostics + */ + unsigned int reserved2 : 4; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved0 : 9; + /*! \brief 1E.C471.6 R/WuP Enable Daisy-Chain Hop-Count Override + AQ_GlobalReservedProvisioning_HHD.u1.bits_1.enableDaisy_chainHop_countOverride + + Default = 0x0 + + 1 = Hop-count is set by Bits 5:0 + 0 = Hop-count is determined by the daisy-chain + + + Notes: + Daisy-Chain Hop-Count Override should be used during MDIO boot-load operation, as the daisy-chain hop-count does not function when the daisy-chain is disabled (1E.C452.0). Setting this bit tells the processor where in the daisy-chain it is, so that the provisioning operation will function correctly. */ + unsigned int enableDaisy_chainHop_countOverride : 1; /* 1E.C471.6 R/WuP Default = 0x0 */ + /* 1 = Hop-count is set by Bits 5:0 + 0 = Hop-count is determined by the daisy-chain + */ + /*! \brief 1E.C471.5:0 R/WuP Daisy-Chain Hop-Count Override Value [5:0] + AQ_GlobalReservedProvisioning_HHD.u1.bits_1.daisy_chainHop_countOverrideValue + + Default = 0x00 + + The value to use for the PHY's daisy-chain hop-count. Valid values are from 0 -> 47 + + + Notes: + Daisy-Chain Hop-Count Override should be used during MDIO boot-load operation, as the daisy-chain hop-count does not function when the daisy-chain is disabled (1E.C452.0). Setting this bit tells the processor where in the daisy-chain it is, so that the provisioning operation will function correctly. */ + unsigned int daisy_chainHop_countOverrideValue : 6; /* 1E.C471.5:0 R/WuP Default = 0x00 */ + /* The value to use for the PHY's daisy-chain hop-count. Valid values are from 0 -> 47 + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.C472.E R/WPD Enable VDD Power Supply Tuning + AQ_GlobalReservedProvisioning_HHD.u2.bits_2.enableVddPowerSupplyTuning + + Provisionable Default = 0x0 + + 1 = Enable external VDD power supply tuning + 0 = Disable external VDD power supply tuning is disabled + + + Notes: + This bit controls whether the PHY attempts to tune the external VDD power supply via the SMBus. This bit is only operational if the external supply is present. (See 1E.C472.6) */ + unsigned int enableVddPowerSupplyTuning : 1; /* 1E.C472.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable external VDD power supply tuning + 0 = Disable external VDD power supply tuning is disabled + */ + unsigned int reserved1 : 7; + /*! \brief 1E.C472.6 R/WPD Tunable External VDD Power Supply Present + AQ_GlobalReservedProvisioning_HHD.u2.bits_2.tunableExternalVddPowerSupplyPresent + + Provisionable Default = 0x0 + + 1 = Tunable external VDD power supply present + 0 = No tunable external VDD power supply present + + + Notes: + This bit must be set if tuning of external power supply is desired. */ + unsigned int tunableExternalVddPowerSupplyPresent : 1; /* 1E.C472.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Tunable external VDD power supply present + 0 = No tunable external VDD power supply present + */ + /*! \brief 1E.C472.5:2 R/WPD External VDD Change Request [3:0] + AQ_GlobalReservedProvisioning_HHD.u2.bits_2.externalVddChangeRequest + + Provisionable Default = 0x0 + + The amount of VDD change requested by firmware, in mV (2's complement value). + + */ + unsigned int externalVddChangeRequest : 4; /* 1E.C472.5:2 R/WPD Provisionable Default = 0x0 */ + /* The amount of VDD change requested by firmware, in mV (2's complement value). + */ + /*! \brief 1E.C472.1 R/WPDuP Enable XENPAK Register Space + AQ_GlobalReservedProvisioning_HHD.u2.bits_2.enableXenpakRegisterSpace + + Provisionable Default = 0x0 + + 1 = XENPAK register space enabled + 0 = XENPAK register space disabled + + */ + unsigned int enableXenpakRegisterSpace : 1; /* 1E.C472.1 R/WPDuP Provisionable Default = 0x0 */ + /* 1 = XENPAK register space enabled + 0 = XENPAK register space disabled + */ + /*! \brief 1E.C472.0 R/WPDuP Enable 5th Channel RFI Cancellation + AQ_GlobalReservedProvisioning_HHD.u2.bits_2.enable_5thChannelRfiCancellation + + Provisionable Default = 0x0 + + 1 = 5th channel and RFI cancellers operation enabled + 0 = 5th channel AFE is powered down, 5th channel digital is clock gated, RFI cancellers are disabled + + + Notes: + Note: The value of this bit at the time of Autonegotiation sets the local PHY behavior until the next time Autonegotiation occurs. */ + unsigned int enable_5thChannelRfiCancellation : 1; /* 1E.C472.0 R/WPDuP Provisionable Default = 0x0 */ + /* 1 = 5th channel and RFI cancellers operation enabled + 0 = 5th channel AFE is powered down, 5th channel digital is clock gated, RFI cancellers are disabled + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved0 : 5; + /*! \brief 1E.C473.A:8 R/WPD Rate Transition Request [2:0] + AQ_GlobalReservedProvisioning_HHD.u3.bits_3.rateTransitionRequest + + Provisionable Default = 0x0 + + 0 = No Transition + 1 = Reserved + 2 = Reserved + 3 = Retrain at 10G + 4 = Retrain at 5G + 5 = Retrain at 2.5G + 6 = Retrain at 1G + 7 = Reserved + + */ + unsigned int rateTransitionRequest : 3; /* 1E.C473.A:8 R/WPD Provisionable Default = 0x0 */ + /* 0 = No Transition + 1 = Reserved + 2 = Reserved + 3 = Retrain at 10G + 4 = Retrain at 5G + 5 = Retrain at 2.5G + 6 = Retrain at 1G + 7 = Reserved + */ + /*! \brief 1E.C473.7:0 R/WPD Training SNR [7:0] + AQ_GlobalReservedProvisioning_HHD.u3.bits_3.trainingSNR + + Provisionable Default = 0x00 + + SNR during 10G training on the worst channel. SNR is in steps of 0.1dB + + + Notes: + The SNR margin that is enjoyed by the worst channel, over and above the minimum SNR required to operate at a BER of 10-12. It is reported with 0.1 dB of resolution to an accuracy of 0.5 dB within the range of -12.7 dB to 12.7 dB. The number is in offset binary, with 0.0 dB represented by 0x8000. */ + unsigned int trainingSNR : 8; /* 1E.C473.7:0 R/WPD Provisionable Default = 0x00 */ + /* SNR during 10G training on the worst channel. SNR is in steps of 0.1dB + */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C474.F:1 R/WPD Reserved Provisioning 5 [F:1] + AQ_GlobalReservedProvisioning_HHD.u4.bits_4.reservedProvisioning_5 + + Provisionable Default = 0x0000 + + Reserved for future use + + */ + unsigned int reservedProvisioning_5 : 15; /* 1E.C474.F:1 R/WPD Provisionable Default = 0x0000 */ + /* Reserved for future use + */ + /*! \brief 1E.C474.0 R/W NVR Daisy Chain Kickstart + AQ_GlobalReservedProvisioning_HHD.u4.bits_4.nvrDaisyChainKickstart + + Default = 0x0 + + 1 = Kickstart the Daisy Chain + + + Notes: + When in daisy chain master mode, the PHY0 can kickstart the daisy chain. The kickstart will not reload the IRAM/DRAM or reset the uP for PHY0. It will just read the FLASH and transfer the FLASH data to the daisy chain. */ + unsigned int nvrDaisyChainKickstart : 1; /* 1E.C474.0 R/W Default = 0x0 */ + /* 1 = Kickstart the Daisy Chain + */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved0 : 2; + /*! \brief 1E.C475.D R/WPD Smart Power-Down Status + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.smartPower_downStatus + + Provisionable Default = 0x0 + + 1 = Smart Power-Down Active + 0 = Smart Power-Down Inactive + + */ + unsigned int smartPower_downStatus : 1; /* 1E.C475.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Smart Power-Down Active + 0 = Smart Power-Down Inactive + */ + /*! \brief 1E.C475.C R/WPD Reserved Provisioning 6 + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.reservedProvisioning_6 + + Provisionable Default = 0x0 + + Internal reserved - do not modify + + */ + unsigned int reservedProvisioning_6 : 1; /* 1E.C475.C R/WPD Provisionable Default = 0x0 */ + /* Internal reserved - do not modify + */ + /*! \brief 1E.C475.B R/WPD CFR LP Disable Timer + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrLpDisableTimer + + Provisionable Default = 0x0 + + 1 = Link partner requires cfr_disable timer + 0 = Link partner does not require cfr_disable timer + + */ + unsigned int cfrLpDisableTimer : 1; /* 1E.C475.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner requires cfr_disable timer + 0 = Link partner does not require cfr_disable timer + */ + /*! \brief 1E.C475.A R/WPD CFR LP Extended Maxwait + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrLpExtendedMaxwait + + Provisionable Default = 0x0 + + 1 = Link partner requires extended maxwait + 0 = Link partner does not require extended maxwait + + */ + unsigned int cfrLpExtendedMaxwait : 1; /* 1E.C475.A R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner requires extended maxwait + 0 = Link partner does not require extended maxwait + */ + /*! \brief 1E.C475.9 R/WPD CFR LP THP + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrLpTHP + + Provisionable Default = 0x0 + + 1 = Link partner requires local PHY to enable THP + 0 = Link partner does not require local PHY to enable THP + + */ + unsigned int cfrLpTHP : 1; /* 1E.C475.9 R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner requires local PHY to enable THP + 0 = Link partner does not require local PHY to enable THP + */ + /*! \brief 1E.C475.8 R/WPD CFR LP Support + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrLpSupport + + Provisionable Default = 0x0 + + 1 = Link partner supports Cisco Fast Retrain + 0 = Link partner does support Cisco Fast Retrain + + */ + unsigned int cfrLpSupport : 1; /* 1E.C475.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = Link partner supports Cisco Fast Retrain + 0 = Link partner does support Cisco Fast Retrain + */ + /*! \brief 1E.C475.7 R/WPD CFR Disable Timer + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrDisableTimer + + Provisionable Default = 0x0 + + 1 = Local PHY requires cfr_disable timer + 0 = Local PHY does not require cfr_disable timer + + */ + unsigned int cfrDisableTimer : 1; /* 1E.C475.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY requires cfr_disable timer + 0 = Local PHY does not require cfr_disable timer + */ + /*! \brief 1E.C475.6 R/WPD CFR Extended Maxwait + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrExtendedMaxwait + + Provisionable Default = 0x0 + + 1 = Local PHY requires extended maxwait + 0 = Local PHY does not require extended maxwait + + */ + unsigned int cfrExtendedMaxwait : 1; /* 1E.C475.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY requires extended maxwait + 0 = Local PHY does not require extended maxwait + */ + /*! \brief 1E.C475.5 R/WPD CFR THP + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrTHP + + Provisionable Default = 0x0 + + 1 = Local PHY requires local PHY to enable THP + 0 = Local PHY does not require local PHY to enable THP + + */ + unsigned int cfrTHP : 1; /* 1E.C475.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY requires local PHY to enable THP + 0 = Local PHY does not require local PHY to enable THP + */ + /*! \brief 1E.C475.4 R/WPD CFR Support + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrSupport + + Provisionable Default = 0x0 + + 1 = Local PHY supports Cisco Fast Retrain + 0 = Local PHY does support Cisco Fast Retrain + + */ + unsigned int cfrSupport : 1; /* 1E.C475.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = Local PHY supports Cisco Fast Retrain + 0 = Local PHY does support Cisco Fast Retrain + */ + /*! \brief 1E.C475.3 R/WPD Deadlock Avoidance Enable + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.deadlockAvoidanceEnable + + Provisionable Default = 0x0 + + 1 = SPD with deadlock avoidance: PHY transmits autonegotiation pulses (FLPs) at a slower rate (~ 1 FLP/ 100ms) than specified by autonegotiation standard (~1 FLP / 8.25ms). Receiver is active and able to detect the pulses. + 0 = SPD without deadlock avoidance: PHY transmitter is shut down, no autonegotiation pulses are sent on the line but the receiver is active and able to detect the pulses + + */ + unsigned int deadlockAvoidanceEnable : 1; /* 1E.C475.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = SPD with deadlock avoidance: PHY transmits autonegotiation pulses (FLPs) at a slower rate (~ 1 FLP/ 100ms) than specified by autonegotiation standard (~1 FLP / 8.25ms). Receiver is active and able to detect the pulses. + 0 = SPD without deadlock avoidance: PHY transmitter is shut down, no autonegotiation pulses are sent on the line but the receiver is active and able to detect the pulses + */ + /*! \brief 1E.C475.2 R/WPD Smart Power-Down Enable + AQ_GlobalReservedProvisioning_HHD.u5.bits_5.smartPower_downEnable + + Provisionable Default = 0x0 + + 1 = Enable smart power down mode + 0 = Smart power-down mode disabled + + + Notes: + Smart power down (SPD) is the lowest power mode at which PHY is able to autonegotiate. SPD can be enabled with bit 1E.C475.2 */ + unsigned int smartPower_downEnable : 1; /* 1E.C475.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable smart power down mode + 0 = Smart power-down mode disabled + */ + unsigned int reserved1 : 2; + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Dummy union to fill space in the structure Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Dummy union to fill space in the structure Global Reserved Provisioning */ + union + { + struct + { + unsigned int reserved : 16; + } bits_7; + uint16_t word_7; + } u7; + /*! \brief Union for bit and word level access of word 8 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C478.F R/WPD DTE Enable + AQ_GlobalReservedProvisioning_HHD.u8.bits_8.dteEnable + + Provisionable Default = 0x0 + + 1 = Enable DTE + 0 = Disable DTE + + */ + unsigned int dteEnable : 1; /* 1E.C478.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable DTE + 0 = Disable DTE + */ + /*! \brief 1E.C478.E:B R/WPD DTE Drop Reporting Timer [3:0] + AQ_GlobalReservedProvisioning_HHD.u8.bits_8.dteDropReportingTimer + + Provisionable Default = 0x0 + + Number of seconds between loss of link partner filter and assertion of no-power-needed state, in 5 second increments (e.g. 0x4 = 20 seconds). + + + Notes: + These bits are used to set how long the PHY waits after it no longer detects the link partner filter before declaring that power is not needed. */ + unsigned int dteDropReportingTimer : 4; /* 1E.C478.E:B R/WPD Provisionable Default = 0x0 */ + /* Number of seconds between loss of link partner filter and assertion of no-power-needed state, in 5 second increments (e.g. 0x4 = 20 seconds). + */ + /*! \brief 1E.C478.A:0 R/WPD Reserved Provisioning 9 [A:0] + AQ_GlobalReservedProvisioning_HHD.u8.bits_8.reservedProvisioning_9 + + Provisionable Default = 0x000 + + Reserved for future use + + */ + unsigned int reservedProvisioning_9 : 11; /* 1E.C478.A:0 R/WPD Provisionable Default = 0x000 */ + /* Reserved for future use + */ + } bits_8; + uint16_t word_8; + } u8; + /*! \brief Union for bit and word level access of word 9 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C479.F R/WPD Power Up Stall + AQ_GlobalReservedProvisioning_HHD.u9.bits_9.powerUpStall + + Provisionable Default = 0x0 + + 1 = Stall FW at Power Up + 0 = Unstall the FW + + + Notes: + This bit needs to be provisioned in Power Up Init for firmware to stall. */ + unsigned int powerUpStall : 1; /* 1E.C479.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Stall FW at Power Up + 0 = Unstall the FW + */ + /*! \brief 1E.C479.E:0 R/WPD Reserved Provisioning 10 [E:0] + AQ_GlobalReservedProvisioning_HHD.u9.bits_9.reservedProvisioning_10 + + Provisionable Default = 0x0000 + + Reserved for future use + + */ + unsigned int reservedProvisioning_10 : 15; /* 1E.C479.E:0 R/WPD Provisionable Default = 0x0000 */ + /* Reserved for future use + */ + } bits_9; + uint16_t word_9; + } u9; + /*! \brief Union for bit and word level access of word 10 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C47A.F:B R/WPD Loopback Control [4:0] + AQ_GlobalReservedProvisioning_HHD.u10.bits_10.loopbackControl + + Provisionable Default = 0x00 + + 0x00 = No loopback + 0x01 = System Interface - System Loopback + 0x02 = System Interface - System Loopback with Passthrough + 0x03 = System Interface - Network Loopback + 0x04 = System Interface - Network Loopback with Passthrough + 0x05 = System Interface - Network Loopback with Passthrough and Merge + 0x06 = System Interface - Peer-to-peer loopback + 0x07 - 0x08 = Reserved + 0x09 = Network Interface - System Loopback + 0x0A = Network Interface - System Loopback with Passthrough + 0x0B = Network Interface - Network Loopback + 0x0C = Network Interface - Network Loopback with Passthrough + 0x0D = Network Interface - Peer-to-peer loopback + 0x0E - 0x0F = Reserved + 0x10 = Cross-connect System Loopback + 0x11 = Cross-connect Network Loopback + 0x12 - 0x13 = Reserved + 0x14 = Network Interface - System Loopback via Loopback Plug + 0x15 - 0x1F = Reserved + + + Notes: + These bits, in conjunction with the chip configuration and the rate (Bits 1:0), select the loopback to configure for the chip. Setting one of these loopbacks provisions the chip for the specified loopback. Upon clearing the loopback, the chip returns to it's configuration prior to entering loopback (irregardless of whether other loopbacks were selected after the initial loopback). + + NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F. + + The controls in this register are identical to, and mirrored with, the controls in 4.C444. + */ + unsigned int loopbackControl : 5; /* 1E.C47A.F:B R/WPD Provisionable Default = 0x00 */ + /* 0x00 = No loopback + 0x01 = System Interface - System Loopback + 0x02 = System Interface - System Loopback with Passthrough + 0x03 = System Interface - Network Loopback + 0x04 = System Interface - Network Loopback with Passthrough + 0x05 = System Interface - Network Loopback with Passthrough and Merge + 0x06 = System Interface - Peer-to-peer loopback + 0x07 - 0x08 = Reserved + 0x09 = Network Interface - System Loopback + 0x0A = Network Interface - System Loopback with Passthrough + 0x0B = Network Interface - Network Loopback + 0x0C = Network Interface - Network Loopback with Passthrough + 0x0D = Network Interface - Peer-to-peer loopback + 0x0E - 0x0F = Reserved + 0x10 = Cross-connect System Loopback + 0x11 = Cross-connect Network Loopback + 0x12 - 0x13 = Reserved + 0x14 = Network Interface - System Loopback via Loopback Plug + 0x15 - 0x1F = Reserved + */ + /*! \brief 1E.C47A.A:6 R/WPD Reserved Provisioning 11 [4:0] + AQ_GlobalReservedProvisioning_HHD.u10.bits_10.reservedProvisioning_11 + + Provisionable Default = 0x00 + + Reserved for future use + + */ + unsigned int reservedProvisioning_11 : 5; /* 1E.C47A.A:6 R/WPD Provisionable Default = 0x00 */ + /* Reserved for future use + */ + /*! \brief 1E.C47A.5 R/WPD MDI Packet Generation + AQ_GlobalReservedProvisioning_HHD.u10.bits_10.mdiPacketGeneration + + Provisionable Default = 0x0 + + 1 = CRPAT packet generation out MDI interface + 0 = No CRPAT packet generation out MDI interface + + + Notes: + Selecting this mode of operation causes the CRPAT packet generator in the PHY to output on the MDI interface at the selected rate. + + NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F + + The controls in this register are identical to, and mirrored with, the controls in 4.C444. */ + unsigned int mdiPacketGeneration : 1; /* 1E.C47A.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = CRPAT packet generation out MDI interface + 0 = No CRPAT packet generation out MDI interface + */ + /*! \brief 1E.C47A.4 R/WPD Look-Aside Port Packet Generation + AQ_GlobalReservedProvisioning_HHD.u10.bits_10.look_asidePortPacketGeneration + + Provisionable Default = 0x0 + + 1 = CRPAT packet generation out 10G look-aside interface (KR0) + 0 = No CRPAT packet generation out 10G look-aside interface (KR0) + + + Notes: + Selecting this mode of operation causes the CRPAT packet generator in the PHY to output on KR0. + + NOTE!! This only functions if KR1 (SERDES2) is selected as the system interface in (4.C441.F:E). + + NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F + + The controls in this register are identical to, and mirrored with, the controls in 4.C444. */ + unsigned int look_asidePortPacketGeneration : 1; /* 1E.C47A.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = CRPAT packet generation out 10G look-aside interface (KR0) + 0 = No CRPAT packet generation out 10G look-aside interface (KR0) + */ + /*! \brief 1E.C47A.3 R/WPD System I/F Packet Generation + AQ_GlobalReservedProvisioning_HHD.u10.bits_10.systemI_fPacketGeneration + + Provisionable Default = 0x0 + + 1 = CRPAT packet generation out 10G system interface + 0 = No CRPAT packet generation out 10G system interface + + + Notes: + Selecting this mode of operation causes the CRPAT packet generator in the PHY to output CRPAT packets on the selected 10G system interface (4.C441.F:E) + + NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F + + The controls in this register are identical to, and mirrored with, the controls in 4.C444. */ + unsigned int systemI_fPacketGeneration : 1; /* 1E.C47A.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = CRPAT packet generation out 10G system interface + 0 = No CRPAT packet generation out 10G system interface + */ + /*! \brief 1E.C47A.2 R/WPD Reserved Provisioning 11a + AQ_GlobalReservedProvisioning_HHD.u10.bits_10.reservedProvisioning_11a + + Provisionable Default = 0x0 + + Reserved for future use + + */ + unsigned int reservedProvisioning_11a : 1; /* 1E.C47A.2 R/WPD Provisionable Default = 0x0 */ + /* Reserved for future use + */ + /*! \brief 1E.C47A.1:0 R/WPD Rate [1:0] + AQ_GlobalReservedProvisioning_HHD.u10.bits_10.rate + + Provisionable Default = 0x0 + + 0x3 = 10G + 0x2 = 1G + 0x1 = 100M + 0x0 = reserved + + + Notes: + These bits select the rate for the loopback and packet generation. SERDES configuration, as well autonegotiation is controlled accordingly when a loopback is selected. For instance, if 100M system loopback on the network interface is selected, SGMII on the system interface is enabled to connect at 100M, and if passthrough is enabled 100BASE-TX will be the only advertised rate and will force a re-autonegotiation if not already connected at 100M. + + NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F + + The controls in this register are identical to, and mirrored with, the controls in 4.C444. */ + unsigned int rate : 2; /* 1E.C47A.1:0 R/WPD Provisionable Default = 0x0 */ + /* 0x3 = 10G + 0x2 = 1G + 0x1 = 100M + 0x0 = reserved + */ + } bits_10; + uint16_t word_10; + } u10; + /*! \brief Union for bit and word level access of word 11 of Global Reserved Provisioning */ + union + { + struct + { + /*! \brief 1E.C47B.F:2 R/WPD Reserved Provisioning 12 [D:0] + AQ_GlobalReservedProvisioning_HHD.u11.bits_11.reservedProvisioning_12 + + Provisionable Default = 0x0000 + + Reserved for future use + + */ + unsigned int reservedProvisioning_12 : 14; /* 1E.C47B.F:2 R/WPD Provisionable Default = 0x0000 */ + /* Reserved for future use + */ + /*! \brief 1E.C47B.1 R/WPD Enable MACSec + AQ_GlobalReservedProvisioning_HHD.u11.bits_11.enableMacsec + + Provisionable Default = 0x0 + + 1 = MACSec functionality is enabled + 0 = MACSec functionality is disabled + + + Notes: + If this bit is 1, the PTP/SEC block will be included in the data path, regardless of operating mode. */ + unsigned int enableMacsec : 1; /* 1E.C47B.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = MACSec functionality is enabled + 0 = MACSec functionality is disabled + */ + /*! \brief 1E.C47B.0 R/WPD Enable PTP + AQ_GlobalReservedProvisioning_HHD.u11.bits_11.enablePtp + + Provisionable Default = 0x0 + + 1 = PTP functionality is enabled + 0 = PTP functionality is disabled + + + Notes: + If this bit is 1, the PTP/SEC block will be included in the data path, regardless of operating mode. */ + unsigned int enablePtp : 1; /* 1E.C47B.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = PTP functionality is enabled + 0 = PTP functionality is disabled + */ + } bits_11; + uint16_t word_11; + } u11; +} AQ_GlobalReservedProvisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief PIF Mailbox Control: 1E.C47C */ +/* PIF Mailbox Control: 1E.C47C */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of PIF Mailbox Control */ + union + { + struct + { + /*! \brief 1E.C47C.F:0 R/WPDuP PIF Mailbox Address [F:0] + AQ_PifMailboxControl_HHD.u0.bits_0.pifMailboxAddress + + Provisionable Default = 0x0000 + + The least 16 bits of the PIF address to read or write. + + */ + unsigned int pifMailboxAddress : 16; /* 1E.C47C.F:0 R/WPDuP Provisionable Default = 0x0000 */ + /* The least 16 bits of the PIF address to read or write. + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of PIF Mailbox Control */ + union + { + struct + { + /*! \brief 1E.C47D.F:0 R/WPDuP PIF Mailbox Data [F:0] + AQ_PifMailboxControl_HHD.u1.bits_1.pifMailboxData + + Provisionable Default = 0x0000 + + The data to be written, or that had been read. + + */ + unsigned int pifMailboxData : 16; /* 1E.C47D.F:0 R/WPDuP Provisionable Default = 0x0000 */ + /* The data to be written, or that had been read. + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of PIF Mailbox Control */ + union + { + struct + { + /*! \brief 1E.C47E.F:C R/WPD Reserved PIF Mailbox Control 3 [3:0] + AQ_PifMailboxControl_HHD.u2.bits_2.reservedPifMailboxControl_3 + + Provisionable Default = 0x0 + + Reserved for future use + + */ + unsigned int reservedPifMailboxControl_3 : 4; /* 1E.C47E.F:C R/WPD Provisionable Default = 0x0 */ + /* Reserved for future use + */ + /*! \brief 1E.C47E.B:8 R/WPDuP PIF Mailbox Command Type [3:0] + AQ_PifMailboxControl_HHD.u2.bits_2.pifMailboxCommandType + + Provisionable Default = 0x0 + + 0 = No Action + 1 = Read + 2 = Write + + + Notes: + System SW writes non-zero value to start a PIF command. */ + unsigned int pifMailboxCommandType : 4; /* 1E.C47E.B:8 R/WPDuP Provisionable Default = 0x0 */ + /* 0 = No Action + 1 = Read + 2 = Write + */ + /*! \brief 1E.C47E.7:0 R/WPDuP PIF Mailbox MMD [7:0] + AQ_PifMailboxControl_HHD.u2.bits_2.pifMailboxMMD + + Provisionable Default = 0x00 + + MMD (upper 8 bits) of the PID address to read or write. + + */ + unsigned int pifMailboxMMD : 8; /* 1E.C47E.7:0 R/WPDuP Provisionable Default = 0x00 */ + /* MMD (upper 8 bits) of the PID address to read or write. + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of PIF Mailbox Control */ + union + { + struct + { + /*! \brief 1E.C47F.F:4 R/WPD Reserved PIF Mailbox Control 4 [B:0] + AQ_PifMailboxControl_HHD.u3.bits_3.reservedPifMailboxControl_4 + + Provisionable Default = 0x000 + + Reserved for future use + + */ + unsigned int reservedPifMailboxControl_4 : 12; /* 1E.C47F.F:4 R/WPD Provisionable Default = 0x000 */ + /* Reserved for future use + */ + /*! \brief 1E.C47F.3:0 R/WPDuP PIF Mailbox Command Status [3:0] + AQ_PifMailboxControl_HHD.u3.bits_3.pifMailboxCommandStatus + + Provisionable Default = 0x0 + + 0 = Idle + 1 = Command completed + 2 = Command did not complete + + + Notes: + System SW should write 0 before writing Command Type to clear completion status */ + unsigned int pifMailboxCommandStatus : 4; /* 1E.C47F.3:0 R/WPDuP Provisionable Default = 0x0 */ + /* 0 = Idle + 1 = Command completed + 2 = Command did not complete + */ + } bits_3; + uint16_t word_3; + } u3; +} AQ_PifMailboxControl_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global SMBus 0 Provisioning: 1E.C485 */ +/* Global SMBus 0 Provisioning: 1E.C485 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global SMBus 0 Provisioning */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.C485.7:1 R/W SMB 0 Slave Address [7:1] + AQ_GlobalSmbus_0Provisioning_HHD.u0.bits_0.smb_0SlaveAddress + + Default = 0x00 + + SMB slave address configuration + + */ + unsigned int smb_0SlaveAddress : 7; /* 1E.C485.7:1 R/W Default = 0x00 */ + /* SMB slave address configuration + */ + unsigned int reserved1 : 1; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalSmbus_0Provisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global SMBus 1 Provisioning: 1E.C495 */ +/* Global SMBus 1 Provisioning: 1E.C495 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global SMBus 1 Provisioning */ + union + { + struct + { + unsigned int reserved0 : 8; + /*! \brief 1E.C495.7:1 R/W SMB 1 Slave Address [7:1] + AQ_GlobalSmbus_1Provisioning_HHD.u0.bits_0.smb_1SlaveAddress + + Default = 0x00 + + SMB slave address configuration + + */ + unsigned int smb_1SlaveAddress : 7; /* 1E.C495.7:1 R/W Default = 0x00 */ + /* SMB slave address configuration + */ + unsigned int reserved1 : 1; + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalSmbus_1Provisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global EEE Provisioning: 1E.C4A0 */ +/* Global EEE Provisioning: 1E.C4A0 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global EEE Provisioning */ + union + { + struct + { + unsigned int reserved0 : 15; + /*! \brief 1E.C4A0.0 R/WPD EEE Mode + AQ_GlobalEeeProvisioning_HHD.u0.bits_0.eeeMode + + Provisionable Default = 0x0 + + 1 = EEE mode of operation + + + Notes: + EEE mode of operation (0=disable, 1=enable, default:0) */ + unsigned int eeeMode : 1; /* 1E.C4A0.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = EEE mode of operation + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalEeeProvisioning_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Cable Diagnostic Status: 1E.C800 */ +/* Global Cable Diagnostic Status: 1E.C800 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Cable Diagnostic Status */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.C800.E:C RO Pair A Status [2:0] + AQ_GlobalCableDiagnosticStatus_HHD.u0.bits_0.pairAStatus + + + + [F:D] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair D + 010= Connected to Pair C + 001= Connected to Pair B + 000= OK + + Notes: + This register summarizes the worst impairment on Pair A. */ + unsigned int pairAStatus : 3; /* 1E.C800.E:C RO */ + /* [F:D] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair D + 010= Connected to Pair C + 001= Connected to Pair B + 000= OK */ + unsigned int reserved1 : 1; + /*! \brief 1E.C800.A:8 RO Pair B Status [2:0] + AQ_GlobalCableDiagnosticStatus_HHD.u0.bits_0.pairBStatus + + + + [C:A] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair A + 010= Connected to Pair D + 001= Connected to Pair C + 000= OK + + Notes: + This register summarizes the worst impairment on Pair B. */ + unsigned int pairBStatus : 3; /* 1E.C800.A:8 RO */ + /* [C:A] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair A + 010= Connected to Pair D + 001= Connected to Pair C + 000= OK */ + unsigned int reserved2 : 1; + /*! \brief 1E.C800.6:4 RO Pair C Status [2:0] + AQ_GlobalCableDiagnosticStatus_HHD.u0.bits_0.pairCStatus + + + + [9:7] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair B + 010= Connected to Pair A + 001= Connected to Pair D + 000= OK + + Notes: + This register summarizes the worst impairment on Pair C. */ + unsigned int pairCStatus : 3; /* 1E.C800.6:4 RO */ + /* [9:7] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair B + 010= Connected to Pair A + 001= Connected to Pair D + 000= OK */ + unsigned int reserved3 : 1; + /*! \brief 1E.C800.2:0 RO Pair D Status [2:0] + AQ_GlobalCableDiagnosticStatus_HHD.u0.bits_0.pairDStatus + + + + [6:4] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair C + 010= Connected to Pair B + 001= Connected to Pair A + 000= OK + + Notes: + This register summarizes the worst impairment on Pair D. */ + unsigned int pairDStatus : 3; /* 1E.C800.2:0 RO */ + /* [6:4] + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 011= Connected to Pair C + 010= Connected to Pair B + 001= Connected to Pair A + 000= OK */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C801.F:8 RO Pair A Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u1.bits_1.pairAReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair A + + Notes: + The distance to this reflection is given in See Global Reserved Status 1: Address 1E.C870 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairAReflection_1 : 8; /* 1E.C801.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair A */ + /*! \brief 1E.C801.7:0 RO Pair A Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u1.bits_1.pairAReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair A + + Notes: + The distance to this reflection is given in See Global Reserved Status 1: Address 1E.C870 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairAReflection_2 : 8; /* 1E.C801.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair A */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C802.F:0 RO Impulse Response MSW [F:0] + AQ_GlobalCableDiagnosticStatus_HHD.u2.bits_2.impulseResponseMSW + + + + The MSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type in 1E.C470.E:D + + Notes: + See 1E.C470 for more information */ + unsigned int impulseResponseMSW : 16; /* 1E.C802.F:0 RO */ + /* The MSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type in 1E.C470.E:D */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C803.F:8 RO Pair B Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u3.bits_3.pairBReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair B + + Notes: + The distance to this reflection is given in See Global Reserved Status 2: Address 1E.C871 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairBReflection_1 : 8; /* 1E.C803.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair B */ + /*! \brief 1E.C803.7:0 RO Pair B Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u3.bits_3.pairBReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair B + + Notes: + The distance to this reflection is given in See Global Reserved Status 2: Address 1E.C871 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairBReflection_2 : 8; /* 1E.C803.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair B */ + } bits_3; + uint16_t word_3; + } u3; + /*! \brief Union for bit and word level access of word 4 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C804.F:0 RO Impulse Response LSW [F:0] + AQ_GlobalCableDiagnosticStatus_HHD.u4.bits_4.impulseResponseLSW + + + + The LSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type specified in 1E.C470.E:D + + Notes: + See 1E.C470 for more information */ + unsigned int impulseResponseLSW : 16; /* 1E.C804.F:0 RO */ + /* The LSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type specified in 1E.C470.E:D */ + } bits_4; + uint16_t word_4; + } u4; + /*! \brief Union for bit and word level access of word 5 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C805.F:8 RO Pair C Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u5.bits_5.pairCReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair C + + Notes: + The distance to this reflection is given in See Global Reserved Status 3: Address 1E.C872 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairCReflection_1 : 8; /* 1E.C805.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair C */ + /*! \brief 1E.C805.7:0 RO Pair C Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u5.bits_5.pairCReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair C + + Notes: + The distance to this reflection is given in See Global Reserved Status 3: Address 1E.C872 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairCReflection_2 : 8; /* 1E.C805.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair C */ + } bits_5; + uint16_t word_5; + } u5; + /*! \brief Union for bit and word level access of word 6 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C806.F:0 RO Reserved 1 [F:0] + AQ_GlobalCableDiagnosticStatus_HHD.u6.bits_6.reserved_1 + + + + Reserved for future use + */ + unsigned int reserved_1 : 16; /* 1E.C806.F:0 RO */ + /* Reserved for future use */ + } bits_6; + uint16_t word_6; + } u6; + /*! \brief Union for bit and word level access of word 7 of Global Cable Diagnostic Status */ + union + { + struct + { + /*! \brief 1E.C807.F:8 RO Pair D Reflection #1 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u7.bits_7.pairDReflection_1 + + + + The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair D + + Notes: + The distance to this reflection is given in See Global Reserved Status 4: Address 1E.C873 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairDReflection_1 : 8; /* 1E.C807.F:8 RO */ + /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair D */ + /*! \brief 1E.C807.7:0 RO Pair D Reflection #2 [7:0] + AQ_GlobalCableDiagnosticStatus_HHD.u7.bits_7.pairDReflection_2 + + + + The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair D + + Notes: + The distance to this reflection is given in See Global Reserved Status 4: Address 1E.C873 . A value of zero indicates that this reflection does not exist or was not computed. */ + unsigned int pairDReflection_2 : 8; /* 1E.C807.7:0 RO */ + /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair D */ + } bits_7; + uint16_t word_7; + } u7; +} AQ_GlobalCableDiagnosticStatus_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Thermal Status: 1E.C820 */ +/* Global Thermal Status: 1E.C820 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Thermal Status */ + union + { + struct + { + /*! \brief 1E.C820.F:0 RO Temperature [F:0] + AQ_GlobalThermalStatus_HHD.u0.bits_0.temperature + + + + [F:0] of temperature + + + Notes: + 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 70 degreesC. This is a mirror of the XENPAK register 1.A060 - 1.A061. The mirror is performed in H/W. */ + unsigned int temperature : 16; /* 1E.C820.F:0 RO */ + /* [F:0] of temperature + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Thermal Status */ + union + { + struct + { + unsigned int reserved0 : 15; + /*! \brief 1E.C821.0 RO Temperature Ready + AQ_GlobalThermalStatus_HHD.u1.bits_1.temperatureReady + + + + 1 = Temperature measurement is valid + + + Notes: + This is a mirror of the XENPAK register 1.A06E. */ + unsigned int temperatureReady : 1; /* 1E.C821.0 RO */ + /* 1 = Temperature measurement is valid + */ + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalThermalStatus_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global General Status: 1E.C830 */ +/* Global General Status: 1E.C830 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global General Status */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.C830.E RO High Temperature Failure State + AQ_GlobalGeneralStatus_HHD.u0.bits_0.highTemperatureFailureState + + + + 1 = High temperature failure threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A070.7 register. + + */ + unsigned int highTemperatureFailureState : 1; /* 1E.C830.E RO */ + /* 1 = High temperature failure threshold has been exceeded */ + /*! \brief 1E.C830.D RO Low Temperature Failure State + AQ_GlobalGeneralStatus_HHD.u0.bits_0.lowTemperatureFailureState + + + + 1 = Low temperature failure threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A070.6 register. + + */ + unsigned int lowTemperatureFailureState : 1; /* 1E.C830.D RO */ + /* 1 = Low temperature failure threshold has been exceeded */ + /*! \brief 1E.C830.C RO High Temperature Warning State + AQ_GlobalGeneralStatus_HHD.u0.bits_0.highTemperatureWarningState + + + + 1 = High temperature warning threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A074.7 register. + + */ + unsigned int highTemperatureWarningState : 1; /* 1E.C830.C RO */ + /* 1 = High temperature warning threshold has been exceeded */ + /*! \brief 1E.C830.B RO Low Temperature Warning State + AQ_GlobalGeneralStatus_HHD.u0.bits_0.lowTemperatureWarningState + + + + 1 = Low temperature warning threshold has been exceeded + + Notes: + In XENPAK mode, F/W will copy this register to the 1.A074.6 register. + + */ + unsigned int lowTemperatureWarningState : 1; /* 1E.C830.B RO */ + /* 1 = Low temperature warning threshold has been exceeded */ + unsigned int reserved1 : 11; + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global General Status */ + union + { + struct + { + /*! \brief 1E.C831.F RO Processor Intensive MDIO Operation In- Progress + AQ_GlobalGeneralStatus_HHD.u1.bits_1.processorIntensiveMdioOperationIn_Progress + + + + 1 = PHY microprocessor is busy with a processor-intensive MDIO operation + 0 = Processor-intensive MDIO operation completed + + + Notes: + This bit should may be used with certain processor-intensive MDIO commands (such as Loopbacks, Test Modes, Low power modes, Tx-Disable, Restart autonegotiation, Cable Diagnostics, etc.) that take longer than an MDIO cycle to complete. Upon receiving an MDIO command that involves the PHY's microprocessor, this bit is set, and when the command is completed, this bit is cleared. + + NOTE!!! This bit should be checked only after 1 ms of issuing a processor-intensive MDIO operation. + + The list of operations that set this bit are as follows: + + 1.0.0, PMA Loopback + 1.0.B, Low power mode + 1.9.4:0, Tx Disable + 1.84, 10G Test modes + 1.8000.5, XENPAK Control + 1.9000, XENPAK Rx Fault Enable + 1.9002, XENPAK Alarm Enable + 1.E400.F, External loopback + 3.0.B, Low power mode + 3.0.E, System PCS loopback + 3.C471.5, PRBS Test + 3.C471.6, PRBS Test + 3.E471.5, PRBS Test + 3.E471.6, PRBS Test + 4.0.B, Low power mode + 4.0.E, PHY-XS network loopback + 4.C440, Output clock control, Load SERDES parameters + 4.F802.E, System loopback + 4.C444.F:B, Loopback Control + 4.C444.4:2, Packet generation + 4.C445.C, SERDES calibration + 7.0.9, Restart autonegotiation + 1D.C280, 1G/100M Network loopback + 1D.C500, 1G System loopback + 1D.C501, 1G / 100M Test modes + 1E.C470.4, Cable diagnostics + 1E.C47A.F:B, Loopback Control + 1E.C47A.4:2, Packet generation */ + unsigned int processorIntensiveMdioOperationIn_Progress : 1; /* 1E.C831.F RO */ + /* 1 = PHY microprocessor is busy with a processor-intensive MDIO operation + 0 = Processor-intensive MDIO operation completed + */ + unsigned int reserved0 : 15; + } bits_1; + uint16_t word_1; + } u1; +} AQ_GlobalGeneralStatus_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Pin Status: 1E.C840 */ +/* Global Pin Status: 1E.C840 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Pin Status */ + union + { + struct + { + unsigned int reserved0 : 1; + unsigned int reserved1 : 1; + /*! \brief 1E.C840.D RO DC_MASTER_N + AQ_GlobalPinStatus_HHD.u0.bits_0.dcMasterN + + + + Value of DC_MASTER_N pin: + + 0x1 = PHY Slave Daisy Chain Boot + 0x0 = PHY Master Daisy Chain Boot from FLASH + */ + unsigned int dcMasterN : 1; /* 1E.C840.D RO */ + /* Value of DC_MASTER_N pin: + + 0x1 = PHY Slave Daisy Chain Boot + 0x0 = PHY Master Daisy Chain Boot from FLASH */ + unsigned int reserved2 : 3; + /*! \brief 1E.C840.9 RO Package Connectivity + AQ_GlobalPinStatus_HHD.u0.bits_0.packageConnectivity + + + + Value of the package connection pin + + */ + unsigned int packageConnectivity : 1; /* 1E.C840.9 RO */ + /* Value of the package connection pin + */ + unsigned int reserved3 : 1; + /*! \brief 1E.C840.7 RO Tx Enable + AQ_GlobalPinStatus_HHD.u0.bits_0.txEnable + + + + Current Value of Tx Enable pin + + + Notes: + 0 = Disable Transmitter */ + unsigned int txEnable : 1; /* 1E.C840.7 RO */ + /* Current Value of Tx Enable pin + */ + unsigned int reserved4 : 1; + /*! \brief 1E.C840.5:0 RO LED Pullup State [5:0] + AQ_GlobalPinStatus_HHD.u0.bits_0.ledPullupState + + + + 1 = LED output pin is pulled high + 0 = LED output pin is pulled low + + */ + unsigned int ledPullupState : 6; /* 1E.C840.5:0 RO */ + /* 1 = LED output pin is pulled high + 0 = LED output pin is pulled low + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalPinStatus_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Daisy Chain Status: 1E.C842 */ +/* Global Daisy Chain Status: 1E.C842 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Daisy Chain Status */ + union + { + struct + { + /*! \brief 1E.C842.F:0 RO Rx Daisy Chain Calculated CRC [F:0] + AQ_GlobalDaisyChainStatus_HHD.u0.bits_0.rxDaisyChainCalculatedCrc + + + + Rx Daisy Chain Calculated CRC + + + Notes: + This is the calculated daisy chain CRC. */ + unsigned int rxDaisyChainCalculatedCrc : 16; /* 1E.C842.F:0 RO */ + /* Rx Daisy Chain Calculated CRC + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalDaisyChainStatus_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Fault Message: 1E.C850 */ +/* Global Fault Message: 1E.C850 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Fault Message */ + union + { + struct + { + /*! \brief 1E.C850.F:0 RO Message [F:0] + AQ_GlobalFaultMessage_HHD.u0.bits_0.message + + + + Error code describing fault + + Notes: + Code 0x8001: Firmware not compatible with chip architecture. This fault occurs when firmware compiled for a different microprocessor core is loaded. + Code 0x8002: VCO calibration failed. This occurs when the main PLLs on chip fail to lock: this is not possible to trigger. + Code 0x8003: XAUI calibration failed. This occurs when the XAUI PLLs fail to lock: this is not possible to trigger. + Code 0x8005: Unexpected device ID. This occurs if the device ID programmed into the internal E-Fuse registers in not valid: this is not possible to trigger. + Code 0x8006: Computed checksum does not match expected checksum. This occurs when the FLASH checksum check performed at boot time fails. This only occurs when the system boots from FLASH. + Code 0x8007: Detected a bit error in static memory. To trigger, corrupt one of the static regions. + Code 0xC001: Illegal Instruction exception. This occurs when the processor attempts to execute an illegal instruction. To trigger this, write an illegal instruction to program memory. It's possible that the bit error check will trigger before the illegal instruction is executed. + Code 0xC002 Instruction Fetch Error. Internal physical address or a data error during instruction fetch: this is not possible to trigger. + Code 0xC003 Load Store Error. Internal physical address or data error during load store operation: this is not possible to trigger.. + Code 0xC004 Privileged Instruction. Attempt to execute a privileged operation without sufficient privilege: this is not possible to trigger. + Code 0xC005 Unaligned Load or Store. Attempt to load or store data at an address which cannot be handled due to alignment: this is not possible to trigger. + Code 0xC006 Instruction fetch from prohibited space: this is not possible to trigger. + Code 0xC007 Data load from prohibited space: this is not possible to trigger. + Code 0xC008 Data store into prohibited space: this is not possible to trigger. */ + unsigned int message : 16; /* 1E.C850.F:0 RO */ + /* Error code describing fault */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalFaultMessage_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Cable Diagnostic Impedance: 1E.C880 */ +/* Global Cable Diagnostic Impedance: 1E.C880 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C880.F RO Reserved 1 + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.reserved_1 + + + + Reserved + + */ + unsigned int reserved_1 : 1; /* 1E.C880.F RO */ + /* Reserved + */ + /*! \brief 1E.C880.E:C RO Pair A Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.pairAReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_1 : 3; /* 1E.C880.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C880.B RO Reserved 2 + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.reserved_2 + + + + Reserved + + */ + unsigned int reserved_2 : 1; /* 1E.C880.B RO */ + /* Reserved + */ + /*! \brief 1E.C880.A:8 RO Pair A Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.pairAReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_2 : 3; /* 1E.C880.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C880.7 RO Reserved 3 + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.reserved_3 + + + + Reserved + + */ + unsigned int reserved_3 : 1; /* 1E.C880.7 RO */ + /* Reserved + */ + /*! \brief 1E.C880.6:4 RO Pair A Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.pairAReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_3 : 3; /* 1E.C880.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C880.3 RO Reserved 4 + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.reserved_4 + + + + Reserved + + */ + unsigned int reserved_4 : 1; /* 1E.C880.3 RO */ + /* Reserved + */ + /*! \brief 1E.C880.2:0 RO Pair A Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.pairAReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ + unsigned int pairAReflection_4 : 3; /* 1E.C880.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C881.F RO Reserved 5 + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.reserved_5 + + + + Reserved + + */ + unsigned int reserved_5 : 1; /* 1E.C881.F RO */ + /* Reserved + */ + /*! \brief 1E.C881.E:C RO Pair B Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.pairBReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_1 : 3; /* 1E.C881.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C881.B RO Reserved 6 + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.reserved_6 + + + + Reserved + + */ + unsigned int reserved_6 : 1; /* 1E.C881.B RO */ + /* Reserved + */ + /*! \brief 1E.C881.A:8 RO Pair B Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.pairBReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_2 : 3; /* 1E.C881.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C881.7 RO Reserved 7 + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.reserved_7 + + + + Reserved + + */ + unsigned int reserved_7 : 1; /* 1E.C881.7 RO */ + /* Reserved + */ + /*! \brief 1E.C881.6:4 RO Pair B Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.pairBReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_3 : 3; /* 1E.C881.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C881.3 RO Reserved 8 + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.reserved_8 + + + + Reserved + + */ + unsigned int reserved_8 : 1; /* 1E.C881.3 RO */ + /* Reserved + */ + /*! \brief 1E.C881.2:0 RO Pair B Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.pairBReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ + unsigned int pairBReflection_4 : 3; /* 1E.C881.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C882.F RO Reserved 9 + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.reserved_9 + + + + Reserved + + */ + unsigned int reserved_9 : 1; /* 1E.C882.F RO */ + /* Reserved + */ + /*! \brief 1E.C882.E:C RO Pair C Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.pairCReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_1 : 3; /* 1E.C882.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C882.B RO Reserved 10 + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.reserved_10 + + + + Reserved + + */ + unsigned int reserved_10 : 1; /* 1E.C882.B RO */ + /* Reserved + */ + /*! \brief 1E.C882.A:8 RO Pair C Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.pairCReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_2 : 3; /* 1E.C882.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C882.7 RO Reserved 11 + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.reserved_11 + + + + Reserved + + */ + unsigned int reserved_11 : 1; /* 1E.C882.7 RO */ + /* Reserved + */ + /*! \brief 1E.C882.6:4 RO Pair C Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.pairCReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_3 : 3; /* 1E.C882.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C882.3 RO Reserved 12 + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.reserved_12 + + + + Reserved + + */ + unsigned int reserved_12 : 1; /* 1E.C882.3 RO */ + /* Reserved + */ + /*! \brief 1E.C882.2:0 RO Pair C Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.pairCReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ + unsigned int pairCReflection_4 : 3; /* 1E.C882.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Cable Diagnostic Impedance */ + union + { + struct + { + /*! \brief 1E.C883.F RO Reserved 13 + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.reserved_13 + + + + Reserved + + */ + unsigned int reserved_13 : 1; /* 1E.C883.F RO */ + /* Reserved + */ + /*! \brief 1E.C883.E:C RO Pair D Reflection #1 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.pairDReflection_1 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the first worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_1 : 3; /* 1E.C883.E:C RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C883.B RO Reserved 14 + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.reserved_14 + + + + Reserved + + */ + unsigned int reserved_14 : 1; /* 1E.C883.B RO */ + /* Reserved + */ + /*! \brief 1E.C883.A:8 RO Pair D Reflection #2 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.pairDReflection_2 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the second worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_2 : 3; /* 1E.C883.A:8 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C883.7 RO Reserved 15 + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.reserved_15 + + + + Reserved + + */ + unsigned int reserved_15 : 1; /* 1E.C883.7 RO */ + /* Reserved + */ + /*! \brief 1E.C883.6:4 RO Pair D Reflection #3 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.pairDReflection_3 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the third worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_3 : 3; /* 1E.C883.6:4 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + /*! \brief 1E.C883.3 RO Reserved 16 + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.reserved_16 + + + + Reserved + + */ + unsigned int reserved_16 : 1; /* 1E.C883.3 RO */ + /* Reserved + */ + /*! \brief 1E.C883.2:0 RO Pair D Reflection #4 [2:0] + AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.pairDReflection_4 + + + + 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + + + Notes: + The impedance of the fourth worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ + unsigned int pairDReflection_4 : 3; /* 1E.C883.2:0 RO */ + /* 111 = Open Circuit (> 300W) + 110 = High Mismatch (> 115W) + 101 = Low Mismatch (< 85W) + 100 = Short Circuit (< 30W) + 0xx= No information available + */ + } bits_3; + uint16_t word_3; + } u3; +} AQ_GlobalCableDiagnosticImpedance_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Status: 1E.C884 */ +/* Global Status: 1E.C884 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Status */ + union + { + struct + { + /*! \brief 1E.C884.F:8 RO Reserved Status 0 [7:0] + AQ_GlobalStatus_HHD.u0.bits_0.reservedStatus_0 + + + + Reserved + + */ + unsigned int reservedStatus_0 : 8; /* 1E.C884.F:8 RO */ + /* Reserved + */ + /*! \brief 1E.C884.7:0 RO Cable Length [7:0] + AQ_GlobalStatus_HHD.u0.bits_0.cableLength + + + + The estimated length of the cable in meters + + + Notes: + The length of the cable shown here is estimated from the cable diagnostic engine and should be accurate to +/-1m. */ + unsigned int cableLength : 8; /* 1E.C884.7:0 RO */ + /* The estimated length of the cable in meters + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalStatus_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Reserved Status: 1E.C885 */ +/* Global Reserved Status: 1E.C885 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Reserved Status */ + union + { + struct + { + /*! \brief 1E.C885.F:A RO Nearly Seconds MSW[5:0] + AQ_GlobalReservedStatus_HHD.u0.bits_0.nearlySecondsMSW + + + + Bits 16 to 21 of the 22 bit "Nearly Seconds" uptime counter. + + + Notes: + The "Nearly Seconds" counter is incremented every 1024 milliseconds. */ + unsigned int nearlySecondsMSW : 6; /* 1E.C885.F:A RO */ + /* Bits 16 to 21 of the 22 bit "Nearly Seconds" uptime counter. + */ + /*! \brief 1E.C885.9:8 ROSPD XENPAK NVR Status [1:0] + AQ_GlobalReservedStatus_HHD.u0.bits_0.xenpakNvrStatus + + Provisionable Default = 0x0 + + Status of XENPAK NVR: + 0: NVR not enabled + 1: Last NVR operation succeeded + 2: Last NVR operation failed + 3: Reserved + + + Notes: + XENPAK register space is mirrored in NVR (SPI ROM). This register indicates the status of the last NVR operation. */ + unsigned int xenpakNvrStatus : 2; /* 1E.C885.9:8 ROSPD Provisionable Default = 0x0 */ + /* Status of XENPAK NVR: + 0: NVR not enabled + 1: Last NVR operation succeeded + 2: Last NVR operation failed + 3: Reserved + */ + /*! \brief 1E.C885.7:4 ROSPD Firmware Build ID [3:0] + AQ_GlobalReservedStatus_HHD.u0.bits_0.firmwareBuildID + + Provisionable Default = 0x0 + + Firmware Build ID + + + Notes: + Customers may receive multiple ROM images that differ only in their provisioning. This field is used to differentiate those images. This field is used in conjunction with the firmware major and minor revision numbers to uniquely identify ROM images. */ + unsigned int firmwareBuildID : 4; /* 1E.C885.7:4 ROSPD Provisionable Default = 0x0 */ + /* Firmware Build ID + */ + /*! \brief 1E.C885.3:0 ROSPD Provisioning ID [3:0] + AQ_GlobalReservedStatus_HHD.u0.bits_0.provisioningID + + Provisionable Default = 0x0 + + Provisioning ID + + + Notes: + Customers may receive multiple ROM images that differ only in their provisioning. This field is used to differentiate those images. This field is used in conjunction with the firmware major and minor revision numbers to uniquely identify ROM images. */ + unsigned int provisioningID : 4; /* 1E.C885.3:0 ROSPD Provisionable Default = 0x0 */ + /* Provisioning ID + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Reserved Status */ + union + { + struct + { + /*! \brief 1E.C886.F:0 RO Nearly Seconds LSW [F:0] + AQ_GlobalReservedStatus_HHD.u1.bits_1.nearlySecondsLSW + + + + Bits 0 to 15 of the 22 bit "Nearly Seconds" uptime counter + + + Notes: + The "Nearly Seconds" counter is incremented every 1024 milliseconds. */ + unsigned int nearlySecondsLSW : 16; /* 1E.C886.F:0 RO */ + /* Bits 0 to 15 of the 22 bit "Nearly Seconds" uptime counter + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Reserved Status */ + union + { + struct + { + /*! \brief 1E.C887.F ROS DTE Status + AQ_GlobalReservedStatus_HHD.u2.bits_2.dteStatus + + Default = 0x0 + + 1 = Need power + 0 = Don't need power + + */ + unsigned int dteStatus : 1; /* 1E.C887.F ROS Default = 0x0 */ + /* 1 = Need power + 0 = Don't need power + */ + /*! \brief 1E.C887.E ROS Power Up Stall Status + AQ_GlobalReservedStatus_HHD.u2.bits_2.powerUpStallStatus + + Default = 0x0 + + 1 = FW is stalled at power up + 0 = Firmware is unstalled + + */ + unsigned int powerUpStallStatus : 1; /* 1E.C887.E ROS Default = 0x0 */ + /* 1 = FW is stalled at power up + 0 = Firmware is unstalled + */ + /*! \brief 1E.C887.D:0 RO Reserved Status 3 [D:0] + AQ_GlobalReservedStatus_HHD.u2.bits_2.reservedStatus_3 + + + + Reserved for future use + + */ + unsigned int reservedStatus_3 : 14; /* 1E.C887.D:0 RO */ + /* Reserved for future use + */ + } bits_2; + uint16_t word_2; + } u2; + /*! \brief Union for bit and word level access of word 3 of Global Reserved Status */ + union + { + struct + { + /*! \brief 1E.C888.F:B RO Loopback Status [4:0] + AQ_GlobalReservedStatus_HHD.u3.bits_3.loopbackStatus + + Default = 0x00 + + 0x00 = No loopback + 0x01 = System Interface - System Loopback + 0x02 = System Interface - System Loopback with Passthrough + 0x03 = System Interface - Network Loopback + 0x04 = System Interface - Network Loopback with Passthrough + 0x05 = System Interface - Network Loopback with Passthrough and Merge + 0x06 = System Interface - Peer-to-peer loopback + 0x07 - 0x08 = Reserved + 0x09 = Network Interface - System Loopback + 0x0A = Network Interface - System Loopback with Passthrough + 0x0B = Network Interface - Network Loopback + 0x0C = Network Interface - Network Loopback with Passthrough + 0x0D = Network Interface - Peer-to-peer loopback + 0x0E - 0x0F = Reserved + 0x10 = Cross-connect System Loopback + 0x11 = Cross-connect Network Loopback + 0x12 - 0x13 = Reserved + 0x14 = Network Interface - System Loopback via Loopback Plug + 0x15 - 0x1F = Reserved + + + Notes: + These bits, in conjunction with the chip configuration and the rate (Bits 1:0), report the selected loopback. + + */ + unsigned int loopbackStatus : 5; /* 1E.C888.F:B RO Default = 0x00 */ + /* 0x00 = No loopback + 0x01 = System Interface - System Loopback + 0x02 = System Interface - System Loopback with Passthrough + 0x03 = System Interface - Network Loopback + 0x04 = System Interface - Network Loopback with Passthrough + 0x05 = System Interface - Network Loopback with Passthrough and Merge + 0x06 = System Interface - Peer-to-peer loopback + 0x07 - 0x08 = Reserved + 0x09 = Network Interface - System Loopback + 0x0A = Network Interface - System Loopback with Passthrough + 0x0B = Network Interface - Network Loopback + 0x0C = Network Interface - Network Loopback with Passthrough + 0x0D = Network Interface - Peer-to-peer loopback + 0x0E - 0x0F = Reserved + 0x10 = Cross-connect System Loopback + 0x11 = Cross-connect Network Loopback + 0x12 - 0x13 = Reserved + 0x14 = Network Interface - System Loopback via Loopback Plug + 0x15 - 0x1F = Reserved + */ + /*! \brief 1E.C888.A:6 RO Reserved Status 4 [4:0] + AQ_GlobalReservedStatus_HHD.u3.bits_3.reservedStatus_4 + + Default = 0x00 + + Reserved for future use + + */ + unsigned int reservedStatus_4 : 5; /* 1E.C888.A:6 RO Default = 0x00 */ + /* Reserved for future use + */ + /*! \brief 1E.C888.5 RO MDI Packet Generation Status + AQ_GlobalReservedStatus_HHD.u3.bits_3.mdiPacketGenerationStatus + + Default = 0x0 + + 1 = CRPAT packet generation out MDI interface + 0 = No CRPAT packet generation out MDI interface + + + Notes: + Reports whether the CRPAT packet generator in the PHY outputs on the MDI interface at the selected rate. */ + unsigned int mdiPacketGenerationStatus : 1; /* 1E.C888.5 RO Default = 0x0 */ + /* 1 = CRPAT packet generation out MDI interface + 0 = No CRPAT packet generation out MDI interface + */ + /*! \brief 1E.C888.4 RO Look-Aside Port Packet Generation Status + AQ_GlobalReservedStatus_HHD.u3.bits_3.look_asidePortPacketGenerationStatus + + Default = 0x0 + + 1 = CRPAT packet generation out 10G look-aside interface (KR0) + 0 = No CRPAT packet generation out 10G look-aside interface (KR0) + + + Notes: + Reports whether the CRPAT packet generator in the PHY outputs on the KR0 interface at the selected rate. */ + unsigned int look_asidePortPacketGenerationStatus : 1; /* 1E.C888.4 RO Default = 0x0 */ + /* 1 = CRPAT packet generation out 10G look-aside interface (KR0) + 0 = No CRPAT packet generation out 10G look-aside interface (KR0) + */ + /*! \brief 1E.C888.3 RO System I/F Packet Generation Status + AQ_GlobalReservedStatus_HHD.u3.bits_3.systemI_fPacketGenerationStatus + + Default = 0x0 + + 1 = CRPAT packet generation out 10G system interface + 0 = No CRPAT packet generation out 10G system interface + + + Notes: + Reports whether the CRPAT packet generator in the PHY outputs on the selected system interface at the selected rate. */ + unsigned int systemI_fPacketGenerationStatus : 1; /* 1E.C888.3 RO Default = 0x0 */ + /* 1 = CRPAT packet generation out 10G system interface + 0 = No CRPAT packet generation out 10G system interface + */ + /*! \brief 1E.C888.2 RO Reserved Status 4a + AQ_GlobalReservedStatus_HHD.u3.bits_3.reservedStatus_4a + + Default = 0x0 + + Reserved for future use + + */ + unsigned int reservedStatus_4a : 1; /* 1E.C888.2 RO Default = 0x0 */ + /* Reserved for future use + */ + /*! \brief 1E.C888.1:0 RO Rate [1:0] + AQ_GlobalReservedStatus_HHD.u3.bits_3.rate + + Default = 0x0 + + 0x3 = 10G + 0x2 = 1G + 0x1 = 100M + 0x0 = invalid + + + Notes: + These bits report the selected rate for the loopback and packet generation. */ + unsigned int rate : 2; /* 1E.C888.1:0 RO Default = 0x0 */ + /* 0x3 = 10G + 0x2 = 1G + 0x1 = 100M + 0x0 = invalid + */ + } bits_3; + uint16_t word_3; + } u3; +} AQ_GlobalReservedStatus_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Alarms: 1E.CC00 */ +/* Global Alarms: 1E.CC00 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Alarms */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.CC00.E LH High Temperature Failure + AQ_GlobalAlarms_HHD.u0.bits_0.highTemperatureFailure + + + + 1 = High temperature failure threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int highTemperatureFailure : 1; /* 1E.CC00.E LH */ + /* 1 = High temperature failure threshold has been exceeded + */ + /*! \brief 1E.CC00.D LH Low Temperature Failure + AQ_GlobalAlarms_HHD.u0.bits_0.lowTemperatureFailure + + + + 1 = Low temperature failure threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int lowTemperatureFailure : 1; /* 1E.CC00.D LH */ + /* 1 = Low temperature failure threshold has been exceeded + */ + /*! \brief 1E.CC00.C LH High Temperature Warning + AQ_GlobalAlarms_HHD.u0.bits_0.highTemperatureWarning + + + + 1 = High temperature warning threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int highTemperatureWarning : 1; /* 1E.CC00.C LH */ + /* 1 = High temperature warning threshold has been exceeded + */ + /*! \brief 1E.CC00.B LH Low Temperature Warning + AQ_GlobalAlarms_HHD.u0.bits_0.lowTemperatureWarning + + + + 1 = Low temperature warning threshold has been exceeded + + + Notes: + + + + + These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ + unsigned int lowTemperatureWarning : 1; /* 1E.CC00.B LH */ + /* 1 = Low temperature warning threshold has been exceeded + */ + unsigned int reserved1 : 4; + /*! \brief 1E.CC00.6 LH Reset completed + AQ_GlobalAlarms_HHD.u0.bits_0.resetCompleted + + + + 1 = Chip wide reset completed + + Notes: + This bit is set by the microprocessor when it has completed it's initialization sequence. This bit is mirrored in 1.CC02.0 */ + unsigned int resetCompleted : 1; /* 1E.CC00.6 LH */ + /* 1 = Chip wide reset completed */ + unsigned int reserved2 : 1; + /*! \brief 1E.CC00.4 LH Device Fault + AQ_GlobalAlarms_HHD.u0.bits_0.deviceFault + + + + 1 = Fault + + Notes: + When set, a fault has been detected by the uP and the associated 16 bit error code is visible in See Global Configuration Fault Message: Address 1E.C850 */ + unsigned int deviceFault : 1; /* 1E.CC00.4 LH */ + /* 1 = Fault */ + /*! \brief 1E.CC00.3 LH Reserved Alarm A + AQ_GlobalAlarms_HHD.u0.bits_0.reservedAlarmA + + + + Reserved for future use + + */ + unsigned int reservedAlarmA : 1; /* 1E.CC00.3 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC00.2 LH Reserved Alarm B + AQ_GlobalAlarms_HHD.u0.bits_0.reservedAlarmB + + + + Reserved for future use + + */ + unsigned int reservedAlarmB : 1; /* 1E.CC00.2 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC00.1 LH Reserved Alarm C + AQ_GlobalAlarms_HHD.u0.bits_0.reservedAlarmC + + + + Reserved for future use + + */ + unsigned int reservedAlarmC : 1; /* 1E.CC00.1 LH */ + /* Reserved for future use + */ + /*! \brief 1E.CC00.0 LH Reserved Alarm D + AQ_GlobalAlarms_HHD.u0.bits_0.reservedAlarmD + + + + Reserved for future use + + */ + unsigned int reservedAlarmD : 1; /* 1E.CC00.0 LH */ + /* Reserved for future use + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Alarms */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.CC01.E LH Smart Power-Down Entered + AQ_GlobalAlarms_HHD.u1.bits_1.smartPower_downEntered + + + + 1 = Smart Power-Down State Entered + + + Notes: + When this bit is set, it indicates that the Smart Power-Down state was entered */ + unsigned int smartPower_downEntered : 1; /* 1E.CC01.E LH */ + /* 1 = Smart Power-Down State Entered + */ + /*! \brief 1E.CC01.D RO XENPAK Alarm + AQ_GlobalAlarms_HHD.u1.bits_1.xenpakAlarm + + + + 1 = XENPAK Alarm + + */ + unsigned int xenpakAlarm : 1; /* 1E.CC01.D RO */ + /* 1 = XENPAK Alarm + */ + /*! \brief 1E.CC01.C LH IP Phone Detect + AQ_GlobalAlarms_HHD.u1.bits_1.ipPhoneDetect + + + + 1 = IP Phone Detect + + + Notes: + Assertion of this bit means that the presence of an IP Phone has been detected. */ + unsigned int ipPhoneDetect : 1; /* 1E.CC01.C LH */ + /* 1 = IP Phone Detect + */ + /*! \brief 1E.CC01.B LH DTE Status Change + AQ_GlobalAlarms_HHD.u1.bits_1.dteStatusChange + + + + 1 = DTE status change + + + Notes: + Change in 1E.C887[F]. */ + unsigned int dteStatusChange : 1; /* 1E.CC01.B LH */ + /* 1 = DTE status change + */ + /*! \brief 1E.CC01.A:8 LH Reserved Alarms [2:0] + AQ_GlobalAlarms_HHD.u1.bits_1.reservedAlarms + + + + Reserved + + + */ + unsigned int reservedAlarms : 3; /* 1E.CC01.A:8 LH */ + /* Reserved + + */ + /*! \brief 1E.CC01.7 LH MDIO Command Handling Overflow + AQ_GlobalAlarms_HHD.u1.bits_1.mdioCommandHandlingOverflow + + + + 1 = PHY was issued more MDIO requests than it could service in it's request buffer + + + Notes: + Assertion of this bit means that more MDIO commands were issued than FW could handle. */ + unsigned int mdioCommandHandlingOverflow : 1; /* 1E.CC01.7 LH */ + /* 1 = PHY was issued more MDIO requests than it could service in it's request buffer + */ + unsigned int reserved1 : 6; + unsigned int reserved2 : 1; + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Alarms */ + union + { + struct + { + /*! \brief 1E.CC02.F LH NVR Operation Complete + AQ_GlobalAlarms_HHD.u2.bits_2.nvrOperationComplete + + + + 1 = NVR operation is complete + + + Notes: + NVR interface is ready interrupt for registers See Global NVR Interface 1: Address 1E.100 - See Global NVR Provisioning Data MSW - Address 1E.17 . */ + unsigned int nvrOperationComplete : 1; /* 1E.CC02.F LH */ + /* 1 = NVR operation is complete + */ + /*! \brief 1E.CC02.E LH Mailbox Operation: Complete + AQ_GlobalAlarms_HHD.u2.bits_2.mailboxOperation_Complete + + + + 1 = Mailbox operation is complete + + + Notes: + Mailbox interface is ready interrupt for registers See Global Vendor Specific Control - Address 1E.C000 - See Global Vendor Specific Provisioning 5 - Address 1E.C404 */ + unsigned int mailboxOperation_Complete : 1; /* 1E.CC02.E LH */ + /* 1 = Mailbox operation is complete + */ + unsigned int reserved0 : 3; + /*! \brief 1E.CC02.A LH uP DRAM Parity Error + AQ_GlobalAlarms_HHD.u2.bits_2.upDramParityError + + + + 1 = Parity error detected in the uP DRAM + + */ + unsigned int upDramParityError : 1; /* 1E.CC02.A LH */ + /* 1 = Parity error detected in the uP DRAM + */ + /*! \brief 1E.CC02.9:8 LH uP IRAM Parity Error [1:0] + AQ_GlobalAlarms_HHD.u2.bits_2.upIramParityError + + + + 1 = Parity error detected in the uP IRAM + + + Notes: + Bit 0 indicates a parity error was detected in the uP IRAM but was corrected. + Bit 1 indicates a multiple parity errors were detected in the uP IRAM and could not be corrected. + The uP IRAM is protected with ECC. */ + unsigned int upIramParityError : 2; /* 1E.CC02.9:8 LH */ + /* 1 = Parity error detected in the uP IRAM + */ + unsigned int reserved1 : 2; + /*! \brief 1E.CC02.5 LRF Tx Enable State Change + AQ_GlobalAlarms_HHD.u2.bits_2.txEnableStateChange + + + + 1 = TX_EN pin has changed state + + */ + unsigned int txEnableStateChange : 1; /* 1E.CC02.5 LRF */ + /* 1 = TX_EN pin has changed state + */ + unsigned int reserved2 : 2; + /*! \brief 1E.CC02.2 LH MDIO MMD Error + AQ_GlobalAlarms_HHD.u2.bits_2.mdioMMD_Error + + + + 1 = Invalid MMD address detected + + */ + unsigned int mdioMMD_Error : 1; /* 1E.CC02.2 LH */ + /* 1 = Invalid MMD address detected + */ + /*! \brief 1E.CC02.1 LH MDIO Timeout Error + AQ_GlobalAlarms_HHD.u2.bits_2.mdioTimeoutError + + + + 1 = MDIO timeout detected + + */ + unsigned int mdioTimeoutError : 1; /* 1E.CC02.1 LH */ + /* 1 = MDIO timeout detected + */ + /*! \brief 1E.CC02.0 LH Watchdog Timer Alarm + AQ_GlobalAlarms_HHD.u2.bits_2.watchdogTimerAlarm + + + + 1 = Watchdog timer alarm + + */ + unsigned int watchdogTimerAlarm : 1; /* 1E.CC02.0 LH */ + /* 1 = Watchdog timer alarm + */ + } bits_2; + uint16_t word_2; + } u2; +} AQ_GlobalAlarms_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Interrupt Mask: 1E.D400 */ +/* Global Interrupt Mask: 1E.D400 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Interrupt Mask */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.D400.E R/WPD High Temperature Failure Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.highTemperatureFailureMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int highTemperatureFailureMask : 1; /* 1E.D400.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D400.D R/WPD Low Temperature Failure Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.lowTemperatureFailureMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int lowTemperatureFailureMask : 1; /* 1E.D400.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D400.C R/WPD High Temperature Warning Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.highTemperatureWarningMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int highTemperatureWarningMask : 1; /* 1E.D400.C R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D400.B R/WPD Low Temperature Warning Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.lowTemperatureWarningMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int lowTemperatureWarningMask : 1; /* 1E.D400.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved1 : 4; + /*! \brief 1E.D400.6 R/WPD Reset completed Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.resetCompletedMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int resetCompletedMask : 1; /* 1E.D400.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved2 : 1; + /*! \brief 1E.D400.4 R/WPD Device Fault Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.deviceFaultMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int deviceFaultMask : 1; /* 1E.D400.4 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D400.3 R/WPD Reserved Alarm A Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.reservedAlarmAMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmAMask : 1; /* 1E.D400.3 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D400.2 R/WPD Reserved Alarm B Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.reservedAlarmBMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmBMask : 1; /* 1E.D400.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D400.1 R/WPD Reserved Alarm C Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.reservedAlarmCMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmCMask : 1; /* 1E.D400.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D400.0 R/WPD Reserved Alarm D Mask + AQ_GlobalInterruptMask_HHD.u0.bits_0.reservedAlarmDMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmDMask : 1; /* 1E.D400.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + } bits_0; + uint16_t word_0; + } u0; + /*! \brief Union for bit and word level access of word 1 of Global Interrupt Mask */ + union + { + struct + { + unsigned int reserved0 : 1; + /*! \brief 1E.D401.E R/WPD Smart Power-Down Entered Mask + AQ_GlobalInterruptMask_HHD.u1.bits_1.smartPower_downEnteredMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int smartPower_downEnteredMask : 1; /* 1E.D401.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D401.D R/WPD XENPAK Alarm Mask + AQ_GlobalInterruptMask_HHD.u1.bits_1.xenpakAlarmMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int xenpakAlarmMask : 1; /* 1E.D401.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D401.C R/WPD IP Phone Detect Mask + AQ_GlobalInterruptMask_HHD.u1.bits_1.ipPhoneDetectMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int ipPhoneDetectMask : 1; /* 1E.D401.C R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D401.B R/WPD DTE Status Change Mask + AQ_GlobalInterruptMask_HHD.u1.bits_1.dteStatusChangeMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int dteStatusChangeMask : 1; /* 1E.D401.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D401.A:8 R/WPD Reserved Alarms Mask [2:0] + AQ_GlobalInterruptMask_HHD.u1.bits_1.reservedAlarmsMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int reservedAlarmsMask : 3; /* 1E.D401.A:8 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D401.7 R/WPD MDIO Command Handling Overflow Mask + AQ_GlobalInterruptMask_HHD.u1.bits_1.mdioCommandHandlingOverflowMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int mdioCommandHandlingOverflowMask : 1; /* 1E.D401.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int reserved1 : 6; + /*! \brief 1E.D401.0 R/WPD Diagnostic Alarm Mask + AQ_GlobalInterruptMask_HHD.u1.bits_1.diagnosticAlarmMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int diagnosticAlarmMask : 1; /* 1E.D401.0 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + } bits_1; + uint16_t word_1; + } u1; + /*! \brief Union for bit and word level access of word 2 of Global Interrupt Mask */ + union + { + struct + { + /*! \brief 1E.D402.F R/WPD NVR Operation Complete Mask + AQ_GlobalInterruptMask_HHD.u2.bits_2.nvrOperationCompleteMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + Notes: + NVR interface is ready interrupt for registers See Global NVR Interface 1: Address 1E.100 - See Global NVR Provisioning Data MSW - Address 1E.17 */ + unsigned int nvrOperationCompleteMask : 1; /* 1E.D402.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D402.E R/WPD Mailbox Operation Complete Mask + AQ_GlobalInterruptMask_HHD.u2.bits_2.mailboxOperationCompleteMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + Notes: + Mailbox interface is ready interrupt for registers See Global Vendor Specific Control - Address 1E.C000 - See Global Vendor Specific Provisioning 5 - Address 1E.C404 */ + unsigned int mailboxOperationCompleteMask : 1; /* 1E.D402.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved0 : 3; + /*! \brief 1E.D402.A R/WPD uP DRAM Parity Error Mask + AQ_GlobalInterruptMask_HHD.u2.bits_2.upDramParityErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int upDramParityErrorMask : 1; /* 1E.D402.A R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + /*! \brief 1E.D402.9:8 R/WPD uP IRAM Parity Error Mask [1:0] + AQ_GlobalInterruptMask_HHD.u2.bits_2.upIramParityErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + + */ + unsigned int upIramParityErrorMask : 2; /* 1E.D402.9:8 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int reserved1 : 2; + /*! \brief 1E.D402.5 R/WPD Tx Enable State Change Mask + AQ_GlobalInterruptMask_HHD.u2.bits_2.txEnableStateChangeMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int txEnableStateChangeMask : 1; /* 1E.D402.5 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved2 : 2; + /*! \brief 1E.D402.2 R/WPD MDIO MMD Error Mask + AQ_GlobalInterruptMask_HHD.u2.bits_2.mdioMMD_ErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int mdioMMD_ErrorMask : 1; /* 1E.D402.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D402.1 R/WPD MDIO Timeout Error Mask + AQ_GlobalInterruptMask_HHD.u2.bits_2.mdioTimeoutErrorMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int mdioTimeoutErrorMask : 1; /* 1E.D402.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.D402.0 R/WPD Watchdog Timer Alarm Mask + AQ_GlobalInterruptMask_HHD.u2.bits_2.watchdogTimerAlarmMask + + Provisionable Default = 0x1 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int watchdogTimerAlarmMask : 1; /* 1E.D402.0 R/WPD Provisionable Default = 0x1 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + } bits_2; + uint16_t word_2; + } u2; +} AQ_GlobalInterruptMask_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Chip-Wide Standard Interrupt Flags: 1E.FC00 */ +/* Global Chip-Wide Standard Interrupt Flags: 1E.FC00 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Chip-Wide Standard Interrupt Flags */ + union + { + struct + { + /*! \brief 1E.FC00.F RO PMA Standard Alarm 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.pmaStandardAlarm_1Interrupt + + + + 1 = Interrupt in PMA standard alarms 1 + + + Notes: + An interrupt was generated from bit 1.1.2. + An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ + unsigned int pmaStandardAlarm_1Interrupt : 1; /* 1E.FC00.F RO */ + /* 1 = Interrupt in PMA standard alarms 1 + */ + /*! \brief 1E.FC00.E RO PMA Standard Alarm 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.pmaStandardAlarm_2Interrupt + + + + 1 = Interrupt in PMA standard alarms 2 + + + Notes: + An interrupt was generated from either bit 1.8.B or 1.8.A. + An interrupt was generated from status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int pmaStandardAlarm_2Interrupt : 1; /* 1E.FC00.E RO */ + /* 1 = Interrupt in PMA standard alarms 2 + */ + /*! \brief 1E.FC00.D RO PCS Standard Alarm 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.pcsStandardAlarm_1Interrupt + + + + 1 = Interrupt in PCS standard alarms 1 + + + Notes: + An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ + unsigned int pcsStandardAlarm_1Interrupt : 1; /* 1E.FC00.D RO */ + /* 1 = Interrupt in PCS standard alarms 1 + */ + /*! \brief 1E.FC00.C RO PCS Standard Alarm 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.pcsStandardAlarm_2Interrupt + + + + 1 = Interrupt in PCS standard alarms 2 + + + Notes: + An interrupt was generated from status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int pcsStandardAlarm_2Interrupt : 1; /* 1E.FC00.C RO */ + /* 1 = Interrupt in PCS standard alarms 2 + */ + /*! \brief 1E.FC00.B RO PCS Standard Alarm 3 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.pcsStandardAlarm_3Interrupt + + + + 1 = Interrupt in PCS standard alarms 3 + + + Notes: + An interrupt was generated from status register ( See PCS 10GBASE-T Status 2 - Address 3.21 ) and the corresponding mask register. ( See PCS Standard Interrupt Mask 1 - Address 3.E021 ) */ + unsigned int pcsStandardAlarm_3Interrupt : 1; /* 1E.FC00.B RO */ + /* 1 = Interrupt in PCS standard alarms 3 + */ + /*! \brief 1E.FC00.A RO PHY XS Standard Alarms 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.phyXS_StandardAlarms_1Interrupt + + + + 1 = Interrupt in PHY XS standard alarms 1 + + + Notes: + An interrupt was generated from the status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ + unsigned int phyXS_StandardAlarms_1Interrupt : 1; /* 1E.FC00.A RO */ + /* 1 = Interrupt in PHY XS standard alarms 1 + */ + /*! \brief 1E.FC00.9 RO PHY XS Standard Alarms 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.phyXS_StandardAlarms_2Interrupt + + + + 1 = Interrupt in PHY XS standard alarms 2 + + + Notes: + An interrupt was generated from the status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int phyXS_StandardAlarms_2Interrupt : 1; /* 1E.FC00.9 RO */ + /* 1 = Interrupt in PHY XS standard alarms 2 + */ + /*! \brief 1E.FC00.8 RO Autonegotiation Standard Alarms 1 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.autonegotiationStandardAlarms_1Interrupt + + + + 1 = Interrupt in Autonegotiation standard alarms 1 + + + Notes: + An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See Autonegotiation Standard LASI Interrupt Mask 1: Address 7.D000 ) */ + unsigned int autonegotiationStandardAlarms_1Interrupt : 1; /* 1E.FC00.8 RO */ + /* 1 = Interrupt in Autonegotiation standard alarms 1 + */ + /*! \brief 1E.FC00.7 RO Autonegotiation Standard Alarms 2 Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.autonegotiationStandardAlarms_2Interrupt + + + + 1 = Interrupt in Autonegotiation standard alarms 2 + + + Notes: + An interrupt was generated from status register ( See Autonegotiation 10GBASE-T Status Register - Address 7.21 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ + unsigned int autonegotiationStandardAlarms_2Interrupt : 1; /* 1E.FC00.7 RO */ + /* 1 = Interrupt in Autonegotiation standard alarms 2 + */ + /*! \brief 1E.FC00.6 RO GbE Standard Alarms Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.gbeStandardAlarmsInterrupt + + + + 1 = Interrupt in GbE standard alarms + + + Notes: + An interrupt was generated from the TGE core. */ + unsigned int gbeStandardAlarmsInterrupt : 1; /* 1E.FC00.6 RO */ + /* 1 = Interrupt in GbE standard alarms + */ + unsigned int reserved0 : 5; + /*! \brief 1E.FC00.0 RO All Vendor Alarms Interrupt + AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.allVendorAlarmsInterrupt + + + + 1 = Interrupt in all vendor alarms + + + Notes: + An interrupt was generated from status register ( See Global Chip-Wide LASI Vendor Interrupt Flags: Address 1E.FC01 ) and the corresponding mask register. ( See Global Interrupt LASI Mask: Address 1E.FF01 ) */ + unsigned int allVendorAlarmsInterrupt : 1; /* 1E.FC00.0 RO */ + /* 1 = Interrupt in all vendor alarms + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalChip_wideStandardInterruptFlags_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Chip-Wide Vendor Interrupt Flags: 1E.FC01 */ +/* Global Chip-Wide Vendor Interrupt Flags: 1E.FC01 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Chip-Wide Vendor Interrupt Flags */ + union + { + struct + { + /*! \brief 1E.FC01.F RO PMA Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.pmaVendorAlarmInterrupt + + + + 1 = Interrupt in PMA vendor specific alarm + + + Notes: + A PMA alarm was generated. ( See PHY XS Vendor Global Interrupt Flags 1- Address 4.F800 ) */ + unsigned int pmaVendorAlarmInterrupt : 1; /* 1E.FC01.F RO */ + /* 1 = Interrupt in PMA vendor specific alarm + */ + /*! \brief 1E.FC01.E RO PCS Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.pcsVendorAlarmInterrupt + + + + 1 = Interrupt in PCS vendor specific alarm + + + Notes: + A PCS alarm was generated. ( See PHY XS Vendor Global Interrupt Flags 1- Address 4.F800 ) */ + unsigned int pcsVendorAlarmInterrupt : 1; /* 1E.FC01.E RO */ + /* 1 = Interrupt in PCS vendor specific alarm + */ + /*! \brief 1E.FC01.D RO PHY XS Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.phyXS_VendorAlarmInterrupt + + + + 1 = Interrupt in PHY XS vendor specific alarm + + + Notes: + A PHY XS alarm was generated. ( See PHY XS Vendor Global LASI Interrupt Flags 1: Address 4.FC00 ) */ + unsigned int phyXS_VendorAlarmInterrupt : 1; /* 1E.FC01.D RO */ + /* 1 = Interrupt in PHY XS vendor specific alarm + */ + /*! \brief 1E.FC01.C RO Autonegotiation Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.autonegotiationVendorAlarmInterrupt + + + + 1 = Interrupt in Autonegotiation vendor specific alarm + + + Notes: + An Autonegotiation alarm was generated. ( See Autonegotiation Vendor Global LASI Interrupt Flags 1: Address 7.FC00 ) */ + unsigned int autonegotiationVendorAlarmInterrupt : 1; /* 1E.FC01.C RO */ + /* 1 = Interrupt in Autonegotiation vendor specific alarm + */ + /*! \brief 1E.FC01.B RO GbE Vendor Alarm Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.gbeVendorAlarmInterrupt + + + + 1 = Interrupt in GbE vendor specific alarm + + + Notes: + A GbE alarm was generated. ( See GbE PHY Vendor Global LASI Interrupt Flags 1: Address 1D.FC00 ) */ + unsigned int gbeVendorAlarmInterrupt : 1; /* 1E.FC01.B RO */ + /* 1 = Interrupt in GbE vendor specific alarm + */ + unsigned int reserved0 : 8; + /*! \brief 1E.FC01.2 RO Global Alarms 1 Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.globalAlarms_1Interrupt + + + + 1 = Interrupt in Global alarms 1 + + + Notes: + An interrupt was generated from status register ( See Global Vendor Alarms 1 - Address 1E.CC00 ) and the corresponding mask register. ( See Global Vendor Interrupt Mask - Address 1E.D400 ) */ + unsigned int globalAlarms_1Interrupt : 1; /* 1E.FC01.2 RO */ + /* 1 = Interrupt in Global alarms 1 + */ + /*! \brief 1E.FC01.1 RO Global Alarms 2 Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.globalAlarms_2Interrupt + + + + 1 = Interrupt in Global alarms 2 + + + Notes: + An interrupt was generated from status register ( See Global Alarms 2: Address 1E.CC01 ) and the corresponding mask register. ( See Global LASI Interrupt Mask 2: Address 1E.D401 ) */ + unsigned int globalAlarms_2Interrupt : 1; /* 1E.FC01.1 RO */ + /* 1 = Interrupt in Global alarms 2 + */ + /*! \brief 1E.FC01.0 RO Global Alarms 3 Interrupt + AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.globalAlarms_3Interrupt + + + + 1 = Interrupt in Global alarms 3 + + + Notes: + An interrupt was generated from status register ( See Global Vendor Alarms 2: Address 1E.CC01 ) and the corresponding mask register. ( See Global LASI Interrupt Mask 2: Address 1E.D401 ) */ + unsigned int globalAlarms_3Interrupt : 1; /* 1E.FC01.0 RO */ + /* 1 = Interrupt in Global alarms 3 + */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalChip_wideVendorInterruptFlags_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Interrupt Chip-Wide Standard Mask: 1E.FF00 */ +/* Global Interrupt Chip-Wide Standard Mask: 1E.FF00 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Interrupt Chip-Wide Standard Mask */ + union + { + struct + { + /*! \brief 1E.FF00.F R/WPD PMA Standard Alarm 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.pmaStandardAlarm_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pmaStandardAlarm_1InterruptMask : 1; /* 1E.FF00.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.E R/WPD PMA Standard Alarm 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.pmaStandardAlarm_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pmaStandardAlarm_2InterruptMask : 1; /* 1E.FF00.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.D R/WPD PCS Standard Alarm 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.pcsStandardAlarm_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsStandardAlarm_1InterruptMask : 1; /* 1E.FF00.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.C R/WPD PCS Standard Alarm 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.pcsStandardAlarm_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsStandardAlarm_2InterruptMask : 1; /* 1E.FF00.C R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.B R/WPD PCS Standard Alarm 3 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.pcsStandardAlarm_3InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsStandardAlarm_3InterruptMask : 1; /* 1E.FF00.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.A R/WPD PHY XS Standard Alarms 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.phyXS_StandardAlarms_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int phyXS_StandardAlarms_1InterruptMask : 1; /* 1E.FF00.A R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.9 R/WPD PHY XS Standard Alarms 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.phyXS_StandardAlarms_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int phyXS_StandardAlarms_2InterruptMask : 1; /* 1E.FF00.9 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.8 R/WPD Autonegotiation Standard Alarms 1 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.autonegotiationStandardAlarms_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int autonegotiationStandardAlarms_1InterruptMask : 1; /* 1E.FF00.8 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.7 R/WPD Autonegotiation Standard Alarms 2 Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.autonegotiationStandardAlarms_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int autonegotiationStandardAlarms_2InterruptMask : 1; /* 1E.FF00.7 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF00.6 R/WPD Gbe Standard Alarms Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.gbeStandardAlarmsInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int gbeStandardAlarmsInterruptMask : 1; /* 1E.FF00.6 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved0 : 5; + /*! \brief 1E.FF00.0 R/WPD All Vendor Alarms Interrupt Mask + AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.allVendorAlarmsInterruptMask + + Provisionable Default = 0x1 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int allVendorAlarmsInterruptMask : 1; /* 1E.FF00.0 R/WPD Provisionable Default = 0x1 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalInterruptChip_wideStandardMask_HHD; + + +/*---------------------------------------------------------------------------------*/ +/*! \brief Global Interrupt Chip-Wide Vendor Mask: 1E.FF01 */ +/* Global Interrupt Chip-Wide Vendor Mask: 1E.FF01 */ +/*---------------------------------------------------------------------------------*/ +typedef struct +{ + /*! \brief Union for bit and word level access of word 0 of Global Interrupt Chip-Wide Vendor Mask */ + union + { + struct + { + /*! \brief 1E.FF01.F R/WPD PMA Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.pmaVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pmaVendorAlarmInterruptMask : 1; /* 1E.FF01.F R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.E R/WPD PCS Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.pcsVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int pcsVendorAlarmInterruptMask : 1; /* 1E.FF01.E R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.D R/WPD PHY XS Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.phyXS_VendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int phyXS_VendorAlarmInterruptMask : 1; /* 1E.FF01.D R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.C R/WPD Autonegotiation Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.autonegotiationVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int autonegotiationVendorAlarmInterruptMask : 1; /* 1E.FF01.C R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.B R/WPD GbE Vendor Alarm Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.gbeVendorAlarmInterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int gbeVendorAlarmInterruptMask : 1; /* 1E.FF01.B R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + unsigned int reserved0 : 8; + /*! \brief 1E.FF01.2 R/WPD Global Alarms 1 Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.globalAlarms_1InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int globalAlarms_1InterruptMask : 1; /* 1E.FF01.2 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.1 R/WPD Global Alarms 2 Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.globalAlarms_2InterruptMask + + Provisionable Default = 0x0 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int globalAlarms_2InterruptMask : 1; /* 1E.FF01.1 R/WPD Provisionable Default = 0x0 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + /*! \brief 1E.FF01.0 R/WPD Global Alarms 3 Interrupt Mask + AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.globalAlarms_3InterruptMask + + Provisionable Default = 0x1 + + 1 = Enable interrupt generation + 0 = Disable interrupt generation + */ + unsigned int globalAlarms_3InterruptMask : 1; /* 1E.FF01.0 R/WPD Provisionable Default = 0x1 */ + /* 1 = Enable interrupt generation + 0 = Disable interrupt generation */ + } bits_0; + uint16_t word_0; + } u0; +} AQ_GlobalInterruptChip_wideVendorMask_HHD; + +#endif +/*@}*/ +/*@}*/ diff --git a/qca/aq-fw-download/src/mdioBootLoadCLD.c b/qca/aq-fw-download/src/mdioBootLoadCLD.c new file mode 100644 index 000000000..a8e09d8c9 --- /dev/null +++ b/qca/aq-fw-download/src/mdioBootLoadCLD.c @@ -0,0 +1,193 @@ +/* mdioBootLoadCLD.c */ + +/************************************************************************************ +* Copyright (c) 2015 Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +* +* $File: //depot/icm/proj/Dena/rev1.0/c/Systems/tools/windows/flashUtilities/src/mdioBootLoadCLD.c $ +* +* $Revision: #12 $ +* +* $DateTime: 2014/05/19 15:34:49 $ +* +* $Author: joshd $ +* +* $Label: $ +* +************************************************************************************/ + +/*! \file +This file contains the main (int, char**) file for the mdioBootLoadCLD program, which burns a flash image into a target +Aquantia PHY using the AQ_API. This program calls the API function:

    + + uint8_t AQ_API_WriteBootLoadImage (uint8_t PHY_ID, uint8_t *image, uint16_t *crc16)

    + +to boot load a cld flash image into an Aquantia PHY */ + +/*! \addtogroup mdioBootLoad +@{ +*/ + + + +/*! \def DEBUG +Uncomment this to compile in debug mode. This sets the source to an arbitrary file, defined by DEBUG_FILENAME, +and an arbitrary PHY_ID, defined by DEBUG_PHY_ID. */ +/* #define DEBUG */ + +/*! The debug source file name */ +#define DEBUG_FILENAME "HelloWorld.cld" + +/*! The debug PHY ID */ +#define DEBUG_PHY_ID 0 + + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "AQ_API.h" +#include "AQ_PhyInterface.h" + +int sock; +char devname[7]; + +int sock_init() +{ + if ((sock = socket(AF_INET, SOCK_DGRAM, 0)) < 0) { + fprintf(stderr, "Error creating socket: %s\n", strerror(errno)); + return -1; + } + + return 0; +} + +int main ( int argc, char **argp) +{ + /* declare local variables */ + FILE *pFile; + uint8_t* image; + uint8_t byte; + unsigned int PHY_ID; + AQ_Retcode resultCode; + AQ_Retcode resultCodes[4]; + uint32_t i; + uint32_t imageSize; + char sourceFileName[1000]; + AQ_API_Port targetPort0; + AQ_API_Port* targetPorts[1]; + AQ_API_Port broadcastPort; + unsigned int provisioningAddresses[1] = {0}; + uint32_t reg1, reg2; + + targetPorts[0] = &targetPort0; + + if(argc < 4) { + fprintf (stderr, "enter file name/netdev name/phy address\n"); + return (101); + } + + /*Copy the file name from command line arg*/ + if (strlcpy (sourceFileName, argp[1], sizeof(sourceFileName)) >= sizeof(sourceFileName)) { + fprintf (stderr, "Filename: %s too long \n", argp[1]); + return (101); + } + /*Copy the interface name from command line arg*/ + strlcpy (devname, argp[2], sizeof(devname)); + /*Get PHY Address from command line arg*/ + PHY_ID = (unsigned int)strtoul(argp[3], NULL, 0); + + /* FIXME: set port and device type */ + targetPort0.device = AQ_DEVICE_HHD; + targetPort0.PHY_ID = PHY_ID; + + broadcastPort.device = AQ_DEVICE_HHD; + broadcastPort.PHY_ID = PHY_ID; + + /* open the source in binary read mode */ + pFile = fopen(sourceFileName, "rb"); + if (pFile == NULL) + { + fprintf (stderr, "Unable to open source file %s\n", sourceFileName); + return (101); + } + fseek (pFile, 0, SEEK_END); + imageSize = ftell (pFile); + + image = (uint8_t*) malloc (imageSize * sizeof(uint8_t)); + fseek (pFile, 0, SEEK_SET); + + /* load the file */ + for (i = 0; i < imageSize; i++) + { + byte = (uint8_t) fgetc (pFile); + image[i] = byte; + } + fclose(pFile); + + + if (sock_init() < 0) + { + fprintf (stderr, "Unable to initialize interface\n"); + return (200); + } + + /* Write in the Auantia phy scratch pad register, + * read back the same reg and match the values written. + */ + AQ_API_MDIO_Write(PHY_ID, 0x1e, 0x300, 0xdead); + AQ_API_MDIO_Write(PHY_ID, 0x1e, 0x301, 0xbeaf); + reg1 = AQ_API_MDIO_Read(PHY_ID, 0x1e, 0x300); + reg2 = AQ_API_MDIO_Read(PHY_ID, 0x1e, 0x301); + if(reg1 != 0xdead && reg2 != 0xbeaf) { + fprintf (stderr, "Scratchpad Read/Write test fail\n"); + return (101); + } + + /* call the boot-load function */ + resultCode = AQ_API_WriteBootLoadImage(targetPorts, 1, provisioningAddresses, resultCodes, &imageSize, image, PHY_ID, &broadcastPort); + + switch (resultCode) + { + case 0: + printf("Image load good - mailbox CRC-16 matches\n"); + free (image); + close(sock); + return 0; + + case 1: + fprintf (stderr, "CRC-16 on file is bad\n"); + free (image); + close(sock); + return 1; + + case 2: + fprintf (stderr, "CRC-16 check on image load failed (mailbox CRC-16 check)\n"); + free (image); + close(sock); + return 2; + + default: + fprintf (stderr, "Invalid return code\n"); + free (image); + close(sock); + } + return 12; +} +/*@}*/ diff --git a/qca/aq-fw-download/src/src/AQ_API.c b/qca/aq-fw-download/src/src/AQ_API.c new file mode 100644 index 000000000..89e73344f --- /dev/null +++ b/qca/aq-fw-download/src/src/AQ_API.c @@ -0,0 +1,1021 @@ +/*AQ_API.c*/ + +/************************************************************************************ +* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +* +* Description: +* +* This file contains the code for all of the API functions defined in AQ_API.h +* +************************************************************************************/ + + +/*! \file +* This file contains the code for all of the API functions defined in AQ_API.h + */ + +#include +#include + +#include "AQ_API.h" +#include "AQ_User.h" +#include "AQ_RegMacro.h" +#include "AQ_PlatformRoutines.h" +#include "AQ_RegMaps.h" +#include "AQ_ReturnCodes.h" + +#ifdef AQ_VERBOSE + #include + #include +#endif + + +#ifndef AQ_TIME_T_EXISTS + #ifndef AQ_MDIO_READS_PER_SECOND + #error AQ_MDIO_READS_PER_SECOND in AQ_User.h must be defined, as AQ_TIME_T_EXISTS is currently undefined! + #endif +#endif + +#ifdef AQ_TIME_T_EXISTS + #include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef AQ_ENABLE_UP_BUSY_CHECKS + #ifdef AQ_VERBOSE + #define AQ_API_UP_BUSY_PRINT_STATEMENT printf("uP-busy check timed out.\n"); + #else + #define AQ_API_UP_BUSY_PRINT_STATEMENT /* nothing */ + #endif + + #ifdef AQ_TIME_T_EXISTS + #define AQ_API_UP_BUSY_TIMEOUT (CLOCKS_PER_SEC / 10) + + #define AQ_API_DECLARE_UP_BUSY_VARS AQ_API_Variable(AQ_GlobalGeneralStatus) \ + uint16_t uPbusy; \ + clock_t startTime; \ + AQ_boolean uPBusyTimeoutOccurred = False; + + #define AQ_API_CHECK_UP_NOT_BUSY AQ_API_Wait(1, port); \ + startTime = clock(); \ + do \ + { \ + AQ_API_Get(port->PHY_ID, AQ_GlobalGeneralStatus, processorIntensiveMdioOperationIn_Progress, uPbusy); \ + if ((clock() - startTime) > AQ_API_UP_BUSY_TIMEOUT) \ + { \ + AQ_API_UP_BUSY_PRINT_STATEMENT \ + uPBusyTimeoutOccurred = True; \ + break; \ + } \ + } while (uPbusy != 0); + #else + #define AQ_API_UP_BUSY_MAX_CHECKS (AQ_MDIO_READS_PER_SECOND * 5) + + #define AQ_API_DECLARE_UP_BUSY_VARS AQ_API_Variable(AQ_GlobalGeneralStatus) \ + uint16_t uPbusy; \ + uint32_t numChecks; \ + AQ_boolean uPBusyTimeoutOccurred = False; + + #define AQ_API_CHECK_UP_NOT_BUSY AQ_API_Wait(1, port); \ + numChecks = 0; \ + do \ + { \ + AQ_API_Get(port->PHY_ID, AQ_GlobalGeneralStatus, processorIntensiveMdioOperationIn_Progress, uPbusy); \ + if (numChecks++ > AQ_API_UP_BUSY_MAX_CHECKS) \ + { \ + AQ_API_UP_BUSY_PRINT_STATEMENT \ + uPBusyTimeoutOccurred = True; \ + break; \ + } \ + } while (uPbusy != 0); + #endif + + /* If a uP busy timeout occurred, return the corresponding return code; otherwise, return + * retval. retval should be a return code defined in AQ_ReturnCodes. */ + #define AQ_API_RETURN_UP_BUSY(retval) return (uPBusyTimeoutOccurred ? AQ_RET_UP_BUSY_TIMEOUT : retval); + +#else + #define AQ_API_DECLARE_UP_BUSY_VARS /* nothing */ + #define AQ_API_CHECK_UP_NOT_BUSY /* nothing */ + #define AQ_API_RETURN_UP_BUSY(retval) return retval; +#endif + + +/*! FW image version string maximum length. */ +#define AQ_VERSION_STRING_SIZE 0x40 + +/*! The byte offset from top of DRAM to the FW image version string. */ +#define AQ_VERSION_STRING_BLOCK_OFFSET 0x0200 + +/*! The byte address, in processor memory, of the start of the IRAM segment. */ +#define AQ_IRAM_BASE_ADDRESS 0x40000000 + +/*! The byte address, in processor memory, of the start of the DRAM segment. */ +#define AQ_DRAM_BASE_ADDRESS 0x3FFE0000 + +/*! The byte offset from the top of the PHY image to the header content (HHD devices). */ +#define AQ_PHY_IMAGE_HEADER_CONTENT_OFFSET_HHD 0x300 + +/*! The byte offset from the top of the PHY image to the header content (APPIA devices). */ +#define AQ_PHY_IMAGE_HEADER_CONTENT_OFFSET_APPIA 0 + +/*! The offset, from the start of DRAM, where the provisioning block begins. */ +#define AQ_PHY_IMAGE_PROVTABLE_OFFSET 0x680 + +/*! The offset, from the start of DRAM, where the provisioning block's ending address is recorded. */ +#define AQ_PHY_IMAGE_PROVTABLE_TERM_OFFSET 0x028C + +/*! The size of the space alloted within the PHY image for the provisioning table. */ +#define AQ_PHY_IMAGE_PROVTABLE_MAXSIZE 0x800 + +/*! The maximum number of polling cycles ever required before the FLASH interface is ready. */ +#define AQ_FLASH_INTERFACE_MAX_POLL_COUNT 20 + +/*! The maximum number of ports that can be MDIO bootloaded at once. */ +#define AQ_MAX_NUM_PHY_IDS 48 + +/*! The maximum allowed number of times to poll for debug-trace-freeze acknowledgement. */ +#define AQ_MAX_FREEZE_CHECKS 2000 + +/*! The maximum size of the debug trace buffer. */ +#define AQ_MAX_TRACE_BUFFER_LENGTH 8192 + +/*! The maximum allowed number of times to poll for SERDES Rx eye measurement done. */ +#define AQ_SERDESEYE_MAX_DONE_CHECKS 50 + +/*! The maximum allowed number of times to poll for PIF mailbox status. */ +#define MAX_NUM_COMMAND_STATUS_POLLS 700 + +/* REGDOC_START */ + + +/********************************************************************************************************************** +* MDIO Boot Load +**********************************************************************************************************************/ + +const uint16_t AQ_CRC16Table[256] = {0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50a5, 0x60c6, 0x70e7, + 0x8108, 0x9129, 0xa14a, 0xb16b, 0xc18c, 0xd1ad, 0xe1ce, 0xf1ef, + 0x1231, 0x0210, 0x3273, 0x2252, 0x52b5, 0x4294, 0x72f7, 0x62d6, + 0x9339, 0x8318, 0xb37b, 0xa35a, 0xd3bd, 0xc39c, 0xf3ff, 0xe3de, + 0x2462, 0x3443, 0x0420, 0x1401, 0x64e6, 0x74c7, 0x44a4, 0x5485, + 0xa56a, 0xb54b, 0x8528, 0x9509, 0xe5ee, 0xf5cf, 0xc5ac, 0xd58d, + 0x3653, 0x2672, 0x1611, 0x0630, 0x76d7, 0x66f6, 0x5695, 0x46b4, + 0xb75b, 0xa77a, 0x9719, 0x8738, 0xf7df, 0xe7fe, 0xd79d, 0xc7bc, + 0x48c4, 0x58e5, 0x6886, 0x78a7, 0x0840, 0x1861, 0x2802, 0x3823, + 0xc9cc, 0xd9ed, 0xe98e, 0xf9af, 0x8948, 0x9969, 0xa90a, 0xb92b, + 0x5af5, 0x4ad4, 0x7ab7, 0x6a96, 0x1a71, 0x0a50, 0x3a33, 0x2a12, + 0xdbfd, 0xcbdc, 0xfbbf, 0xeb9e, 0x9b79, 0x8b58, 0xbb3b, 0xab1a, + 0x6ca6, 0x7c87, 0x4ce4, 0x5cc5, 0x2c22, 0x3c03, 0x0c60, 0x1c41, + 0xedae, 0xfd8f, 0xcdec, 0xddcd, 0xad2a, 0xbd0b, 0x8d68, 0x9d49, + 0x7e97, 0x6eb6, 0x5ed5, 0x4ef4, 0x3e13, 0x2e32, 0x1e51, 0x0e70, + 0xff9f, 0xefbe, 0xdfdd, 0xcffc, 0xbf1b, 0xaf3a, 0x9f59, 0x8f78, + 0x9188, 0x81a9, 0xb1ca, 0xa1eb, 0xd10c, 0xc12d, 0xf14e, 0xe16f, + 0x1080, 0x00a1, 0x30c2, 0x20e3, 0x5004, 0x4025, 0x7046, 0x6067, + 0x83b9, 0x9398, 0xa3fb, 0xb3da, 0xc33d, 0xd31c, 0xe37f, 0xf35e, + 0x02b1, 0x1290, 0x22f3, 0x32d2, 0x4235, 0x5214, 0x6277, 0x7256, + 0xb5ea, 0xa5cb, 0x95a8, 0x8589, 0xf56e, 0xe54f, 0xd52c, 0xc50d, + 0x34e2, 0x24c3, 0x14a0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405, + 0xa7db, 0xb7fa, 0x8799, 0x97b8, 0xe75f, 0xf77e, 0xc71d, 0xd73c, + 0x26d3, 0x36f2, 0x0691, 0x16b0, 0x6657, 0x7676, 0x4615, 0x5634, + 0xd94c, 0xc96d, 0xf90e, 0xe92f, 0x99c8, 0x89e9, 0xb98a, 0xa9ab, + 0x5844, 0x4865, 0x7806, 0x6827, 0x18c0, 0x08e1, 0x3882, 0x28a3, + 0xcb7d, 0xdb5c, 0xeb3f, 0xfb1e, 0x8bf9, 0x9bd8, 0xabbb, 0xbb9a, + 0x4a75, 0x5a54, 0x6a37, 0x7a16, 0x0af1, 0x1ad0, 0x2ab3, 0x3a92, + 0xfd2e, 0xed0f, 0xdd6c, 0xcd4d, 0xbdaa, 0xad8b, 0x9de8, 0x8dc9, + 0x7c26, 0x6c07, 0x5c64, 0x4c45, 0x3ca2, 0x2c83, 0x1ce0, 0x0cc1, + 0xef1f, 0xff3e, 0xcf5d, 0xdf7c, 0xaf9b, 0xbfba, 0x8fd9, 0x9ff8, + 0x6e17, 0x7e36, 0x4e55, 0x5e74, 0x2e93, 0x3eb2, 0x0ed1, 0x1ef0}; + +/*! \addtogroup writingImages + @{ +*/ + +/*! Prepare the specified port for MDIO bootloading. Disables the daisy-chain, + * and explicitly sets the port's provisioningAddress. */ +void AQ_API_EnableMDIO_BootLoadMode +( + /*! The target PHY port.*/ + AQ_API_Port* port, + /*! The provisioning address to use when the FW starts and applies the + * bootloaded image's provisioned values. */ + unsigned int provisioningAddress +) +{ + AQ_API_Variable(AQ_GlobalNvrProvisioning) + + AQ_API_DeclareLocalStruct(AQ_GlobalReservedProvisioning, globalReservedProvisioning) + + + /* disable the daisy-chain */ + /* REGDOC: Read-Modify-Write bitfield (HHD/APPIA: 1E.C452.0) */ + AQ_API_Set(port->PHY_ID, AQ_GlobalNvrProvisioning, nvrDaisyChainDisable, 1); + + /* override the hop-count */ + AQ_API_AssignWordOfLocalStruct(globalReservedProvisioning, 1, + /* REGDOC: Read register (HHD/APPIA: 1E.C470 + 1) */ + AQ_API_ReadRegister(port->PHY_ID, AQ_GlobalReservedProvisioning, 1)); + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C471.5:0) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalReservedProvisioning, globalReservedProvisioning, + daisy_chainHop_countOverrideValue, provisioningAddress); + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C471.6) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalReservedProvisioning, globalReservedProvisioning, + enableDaisy_chainHop_countOverride, 1); + /* REGDOC: Write register (HHD/APPIA: 1E.C470 + 1) */ + AQ_API_WriteRegister(port->PHY_ID, AQ_GlobalReservedProvisioning, 1, + AQ_API_WordOfLocalStruct(globalReservedProvisioning, 1)); + + return; +} + + +/*! Prepare the specified port for MDIO bootloading, and set the temporary MDIO + * address to be used during the bootload process. Disables the daisy-chain, + * and explicitly sets the port's provisioningAddress. */ +void AQ_API_EnableGangLoadMode +( + /*! The target PHY port.*/ + AQ_API_Port* port, + /*! The provisioning address to use when the FW starts and applies the + * bootloaded image's provisioned values. */ + unsigned int provisioningAddress, + /*! The PHY's MDIO address will be changed to this value during the + * bootload process. */ + unsigned int gangLoadAddress +) +{ + /*AQ_API_Variable_DeviceRestricted(APPIA, AQ_GlobalGeneralProvisioning)*/ + AQ_API_Variable(AQ_GlobalGeneralProvisioning) + + + /* Get ready for MDIO bootloading. */ + AQ_API_EnableMDIO_BootLoadMode(port, provisioningAddress); + + /* Enable gangload mode. After doing this, the PHY will be + * addressable at the MDIO address indicated by gangLoadAddress. + * Now that the PHY is in gangload mode, MDIO reads are prohibited + * until AQ_API_DisableGangLoadMode is called. */ + if (AQ_DEVICE_APPIA == port->device) + { + /* REGDOC: Read-Modify-Write bitfield (APPIA: 1E.C440.8:4) */ + AQ_API_Set_DeviceRestricted(APPIA, port->PHY_ID, AQ_GlobalGeneralProvisioning, + gangLoadMdioAddress, gangLoadAddress); + } + else if (AQ_DEVICE_HHD == port->device) + { + /* REGDOC: Read-Modify-Write bitfield (HHD: 1E.C447.4:0) */ + AQ_API_Set_DeviceRestricted(HHD, port->PHY_ID, AQ_GlobalGeneralProvisioning, + mdioBroadcastAddressConfiguration, gangLoadAddress); + /* REGDOC: Read-Modify-Write bitfield (HHD: 1E.C441.E) */ + AQ_API_Set_DeviceRestricted(HHD, port->PHY_ID, AQ_GlobalGeneralProvisioning, + mdioBroadcastModeEnable, 1); + } + + return; +} + + +/*! Restore the PHY's MDIO address to the pin-specified value. Should be + * called when MDIO bootloading is complete, to return to normal MDIO + * addressing. + * This is a gang-load function, hence write-only! */ +void AQ_API_DisableGangLoadMode +( + /*! The target PHY port.*/ + AQ_API_Port* port, + /*! The value to write to of AQ_GlobalGeneralProvisioning.u1.word_1. */ + uint16_t origVal_GGP1 +) +{ + AQ_API_DeclareLocalStruct(AQ_GlobalGeneralProvisioning, globalGeneralProvisioning) + + + /* Restore the original value of globalGeneralProvisioning.u1, and set + * the MDIO address reset bit. This will cause the MDIO address to be + * reset to the value indicated by the pins. */ + AQ_API_AssignWordOfLocalStruct(globalGeneralProvisioning, 1, origVal_GGP1); + if (AQ_DEVICE_APPIA == port->device) + { + /* REGDOC: Assign to local representation of bitfield (APPIA: 1E.C441.2) */ + AQ_API_AssignBitfieldOfLocalStruct_DeviceRestricted(APPIA, AQ_GlobalGeneralProvisioning, + globalGeneralProvisioning, mdioAddressReset, 1); + } + else if (AQ_DEVICE_HHD == port->device) + { + /* REGDOC: Assign to local representation of bitfield (HHD: 1E.C441.E) */ + AQ_API_AssignBitfieldOfLocalStruct_DeviceRestricted(HHD, AQ_GlobalGeneralProvisioning, + globalGeneralProvisioning, mdioBroadcastModeEnable, 0); + } + /* REGDOC: Write register (HHD/APPIA: 1E.C440 + 1) */ + AQ_API_WriteRegister(port->PHY_ID, AQ_GlobalGeneralProvisioning, 1, + AQ_API_WordOfLocalStruct(globalGeneralProvisioning, 1)); + + /* The PHY has now exited gang-load mode. */ + return; +} + + +AQ_Retcode AQ_API_WriteBootLoadImageWithProvTable +( + AQ_API_Port** ports, + unsigned int numPorts, + unsigned int* provisioningAddresses, + AQ_Retcode* resultCodes, + uint32_t* imageSizePointer, + uint8_t* image, + uint8_t gangload_MDIO_address, + AQ_API_Port* gangloadPort, + uint32_t* provTableSizePointer, + uint8_t* provTableImage +) +{ + /*------------------------------------- NOTE!!!!!!!!!! ----------------------------------------------------------*/ + /* This function uses word level writes here as in gang-load mode we cannot do a read in a read-modify-write */ + /* operation */ + /*---------------------------------------------------------------------------------------------------------------*/ + + AQ_API_Variable_DeviceRestricted(APPIA, AQ_GlobalPinStatus) + + AQ_API_DeclareLocalStruct(AQ_GlobalControl, globalControl) + AQ_API_DeclareLocalStruct(AQ_GlobalMailboxInterface, globalMailboxInterface) + + AQ_API_Port* port; + uint32_t primaryHeaderPtr = 0x00000000; + uint32_t primaryIramPtr = 0x00000000; + uint32_t primaryDramPtr = 0x00000000; + uint32_t primaryIramSize = 0x00000000; + uint32_t primaryDramSize = 0x00000000; + uint32_t terminatorPtr = 0x00000000; + uint32_t phyImageHeaderContentOffset; + uint32_t i; + uint32_t j; + uint32_t imageSize; + uint32_t provTableImageSize = 0; + uint32_t bytePointer; + uint32_t byteSize; + uint32_t dWordSize; +#ifdef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE + uint32_t countPendingOps; /* A count of block MDIO operation pending... necessary to keep a count + in order to ensure we don't exceed the maximum pending operations. */ +#endif + uint16_t msw; + uint16_t lsw; + uint16_t crc16Calculated; + uint16_t provTableCrc16Calculated; + uint16_t fileCRC; + uint16_t provTableFileCRC; + uint16_t mailboxCRC; + uint16_t mailboxWrite; + uint16_t bootLoadMode; + uint16_t recordedGGP1Values[AQ_MAX_NUM_PHY_IDS]; /* When entering/exiting gangload mode, we record and restore + the AQ_GlobalGeneralProvisioning.u1 register values. */ + + + /* store the CRC-16 for the image, which is the last two bytes */ + imageSize = *imageSizePointer; + fileCRC = image[imageSize-2] << 8 | image[imageSize-1]; + + /*------------------------------------- Check the image integrity ------------------------------------------------*/ + crc16Calculated = 0x0000; + for (i = 0; i < imageSize-2; i++) + { + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ image[i]]; + } + + if (crc16Calculated != fileCRC) + { + #ifdef AQ_VERBOSE + printf ("CRC check failed on image file (expected 0x%X, found 0x%X)\n", + fileCRC, crc16Calculated); + #endif + for (j = 0; j < numPorts; j++) + { + /* Before returning, set ALL result codes to indicate "bad image". */ + resultCodes[j] = AQ_RET_FLASH_IMAGE_CORRUPT; + } + return AQ_RET_ERROR; + } +#ifdef AQ_VERBOSE + else + { + printf ("CRC check good on image file (0x%04X)\n", crc16Calculated); + } +#endif + + /*-------------------------------- Check the provisioning table image integrity ----------------------------------*/ + if (provTableSizePointer != NULL && provTableImage != NULL) + { + provTableImageSize = (*provTableSizePointer) - 2; + provTableFileCRC = provTableImage[provTableImageSize + 1] << 8 | + provTableImage[provTableImageSize]; + + provTableCrc16Calculated = 0x0000; + for (i = 0; i < provTableImageSize; i++) + { + provTableCrc16Calculated = ((provTableCrc16Calculated & 0xFF) << 8) ^ + AQ_CRC16Table[(provTableCrc16Calculated >> 8) ^ provTableImage[i]]; + } + + if (provTableCrc16Calculated != provTableFileCRC) + { + #ifdef AQ_VERBOSE + printf ("CRC check failed on provisioning table file (expected 0x%X, found 0x%X)\n", + provTableFileCRC, provTableCrc16Calculated); + #endif + for (j = 0; j < numPorts; j++) + { + /* Before returning, set ALL result codes to indicate "bad image". */ + resultCodes[j] = AQ_RET_FLASH_IMAGE_CORRUPT; + } + return AQ_RET_ERROR; + } + #ifdef AQ_VERBOSE + else + { + printf ("CRC check good on provisioning table file (0x%04X)\n", + provTableCrc16Calculated); + } + #endif + } + + /*------------------------ Check that all provisioning addresses are in the proper range. ------------------------*/ + for (j = 0; j < numPorts; j++) + { + if (provisioningAddresses[j] > 47) + { + #ifdef AQ_VERBOSE + printf ("Provisioning address out of range 0-47 (index %u: %d)\n", j, provisioningAddresses[j]); + #endif + for (j = 0; j < numPorts; j++) + { + /* Before returning, set ALL result codes to indicate "provisioning address out-of-range". */ + resultCodes[j] = AQ_RET_BOOTLOAD_PROVADDR_OOR; + } + return AQ_RET_ERROR; + } + } + + /*--------------------------- Store 1E.C441 values for later use. Enforce uniformity. ---------------------------*/ + for (j = 0; j < numPorts; j++) + { + /* Record the original value of AQ_GlobalGeneralProvisioning.u1.word_1, + * so that we can restore it later after exiting gangload mode. */ + port = ports[j]; + /* REGDOC: Read register (HHD/APPIA: 1E.C440 + 1) */ + recordedGGP1Values[j] = AQ_API_ReadRegister(port->PHY_ID, AQ_GlobalGeneralProvisioning, 1); + + /* If any of the PHYs' GGP1 values don't match the others, set the appropriate + * error code and return. */ + if (j > 0 && recordedGGP1Values[j] != recordedGGP1Values[0]) + { + #ifdef AQ_VERBOSE + printf ("Non-uniform value of 1E.C441 found (expected 0x%X, found 0x%X)\n", + recordedGGP1Values[0], recordedGGP1Values[j]); + #endif + for (j = 0; j < numPorts; j++) + { + /* Before returning, set ALL result codes to indicate "non-uniform GGP1 values". */ + resultCodes[j] = AQ_RET_BOOTLOAD_NONUNIFORM_REGVALS; + } + return AQ_RET_ERROR; + } + } + + /*--------------------------- Put each PHY into gangload mode at the specified address ---------------------------*/ + for (j = 0; j < numPorts; j++) + { + AQ_API_EnableGangLoadMode(ports[j], provisioningAddresses[j], gangload_MDIO_address); + } + /* Set up the port context for using device-restricted macros while in + * gangload mode. */ + port = gangloadPort; + + /*------------------------------------- Stall the uP ------------------------------------------------------------*/ + AQ_API_AssignWordOfLocalStruct(globalControl, 1, 0x0000); + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.6) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upRunStallOverride, 1); + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.0) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upRunStall, 1); + /* REGDOC: Write register (HHD/APPIA: 1E.C000 + 1) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalControl, 1, + AQ_API_WordOfLocalStruct(globalControl, 1)); + + /*------------------------------------- Initialize the mailbox write command -------------------------------------*/ + AQ_API_AssignWordOfLocalStruct(globalMailboxInterface, 0, 0x0000); + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.0200.E) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalMailboxInterface, globalMailboxInterface, upMailboxWriteMode, 1); + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.0200.F) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalMailboxInterface, globalMailboxInterface, upMailboxExecuteOperation, 1); + mailboxWrite = AQ_API_WordOfLocalStruct(globalMailboxInterface, 0); + + /*------------------------------------- Read the segment addresses and sizes -------------------------------------*/ + primaryHeaderPtr = (((image[0x9] & 0x0F) << 8) | image[0x8]) << 12; + + if (AQ_DEVICE_APPIA == port->device) + phyImageHeaderContentOffset = AQ_PHY_IMAGE_HEADER_CONTENT_OFFSET_APPIA; + else /* HHD */ + phyImageHeaderContentOffset = AQ_PHY_IMAGE_HEADER_CONTENT_OFFSET_HHD; + + primaryIramPtr = (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0x4 + 2] << 16) | + (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0x4 + 1] << 8) | + image[primaryHeaderPtr + phyImageHeaderContentOffset + 0x4]; + primaryIramSize = (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0x7 + 2] << 16) | + (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0x7 + 1] << 8) | + image[primaryHeaderPtr + phyImageHeaderContentOffset + 0x7]; + primaryDramPtr = (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0xA + 2] << 16) | + (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0xA + 1] << 8) | + image[primaryHeaderPtr + phyImageHeaderContentOffset + 0xA]; + primaryDramSize = (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0xD + 2] << 16) | + (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0xD + 1] << 8) | + image[primaryHeaderPtr + phyImageHeaderContentOffset + 0xD]; + + if (AQ_DEVICE_HHD == port->device) + { + primaryIramPtr += primaryHeaderPtr; + primaryDramPtr += primaryHeaderPtr; + } + +#ifdef AQ_VERBOSE + printf ("\nSegment Addresses and Sizes as read from the PHY ROM image header:\n\n"); + printf ("Primary Iram Address: 0x%x\n", primaryIramPtr); + printf ("Primary Iram Size: 0x%x\n", primaryIramSize); + printf ("Primary Dram Address: 0x%x\n", primaryDramPtr); + printf ("Primary Dram Size: 0x%x\n\n", primaryDramSize); +#endif + + /*----------------------------- Merge the provisioning table into the main image ---------------------------------*/ + if (provTableSizePointer != NULL && provTableImage != NULL) + { + /* Locate the terminator of the built-in provisioning table */ + terminatorPtr = primaryDramPtr + + ((image[primaryDramPtr + AQ_PHY_IMAGE_PROVTABLE_TERM_OFFSET + 1] << 8) | + image[primaryDramPtr + AQ_PHY_IMAGE_PROVTABLE_TERM_OFFSET]); + + #ifdef AQ_VERBOSE + printf("Supplied Provisioning Table At Address: 0x%x\n\n", terminatorPtr); + #endif + + /* Check that the supplied provisioning table will fit within the alloted + * space. */ + if (terminatorPtr - (primaryDramPtr + AQ_PHY_IMAGE_PROVTABLE_OFFSET) + + provTableImageSize > AQ_PHY_IMAGE_PROVTABLE_MAXSIZE) + { + for (j = 0; j < numPorts; j++) + { + /* Before returning, set ALL result codes to indicate "provisioning + * table too large". */ + resultCodes[j] = AQ_RET_BOOTLOAD_PROVTABLE_TOO_LARGE; + } + return AQ_RET_ERROR; + } + + /* Write the supplied provisioning table into the image, starting at the + * terminator address. */ + for (i = 0; i < provTableImageSize; i++) + { + image[terminatorPtr + i] = provTableImage[i]; + } + } + + /*------------------------------------- Load IRAM and DRAM -------------------------------------------------------*/ + /* clear the mailbox CRC */ + AQ_API_AssignWordOfLocalStruct(globalMailboxInterface, 0, 0x0000); + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.0200.C) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalMailboxInterface, globalMailboxInterface, resetUpMailboxCrc, 1); + /* REGDOC: Write register (HHD/APPIA: 1E.0200) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, + AQ_API_WordOfLocalStruct(globalMailboxInterface, 0)); + /* REGDOC: Write register (HHD/APPIA: 1E.0200) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, 0x0000); + + crc16Calculated = 0; /* This is to calculate what was written through the mailbox */ + + /* load the IRAM */ +#ifdef AQ_VERBOSE + printf ("\nLoading IRAM:\n\n"); +#endif + + /* dWord align the address: note the image addressing is byte based, but is properly aligned on dWord + boundaries, so the 2 LSbits of the block start are always zero. */ + msw = (uint16_t) (AQ_IRAM_BASE_ADDRESS >> 16); + AQ_API_AssignWordOfLocalStruct(globalMailboxInterface, 3, 0x0000); + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.0203.1:0) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalMailboxInterface, globalMailboxInterface, + upMailboxAddressLSW , (AQ_IRAM_BASE_ADDRESS & 0xFFFF) >> 2); + lsw = AQ_API_WordOfLocalStruct(globalMailboxInterface, 3); + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 2) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 2, msw); /* MSW */ + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 3) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 3, lsw); /* LSW */ + + + /* set block size so that there are from 0-3 bytes remaining */ + byteSize = primaryIramSize; + dWordSize = byteSize >> 2; + + bytePointer = primaryIramPtr; +#ifdef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE + countPendingOps = 0; +#endif + for (i = 0; i < dWordSize; i++) + { + /* write 4 bytes of data */ + lsw = (image[bytePointer+1] << 8) | image[bytePointer]; + bytePointer += 2; + msw = (image[bytePointer+1] << 8) | image[bytePointer]; + bytePointer += 2; + + #ifdef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE + AQ_API_BlockWriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 4, msw); + AQ_API_BlockWriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 5, lsw); + AQ_API_BlockWriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, mailboxWrite); + + countPendingOps += 3; + /* Check if we've filled our output buffer, and if so, flush. */ + if (countPendingOps >= AQ_API_MDIO_MaxBlockOperations() - 3 ) + { + AQ_API_MDIO_BlockOperationExecute (gangloadPort->PHY_ID); + countPendingOps = 0; + } + #else + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 4) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 4, msw); + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 5) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 5, lsw); + /* REGDOC: Write register (HHD/APPIA: 1E.0200) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, mailboxWrite); + #endif + + /* update the calculated CRC */ + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (msw >> 8)]; + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (msw & 0xFF)]; + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (lsw >> 8)]; + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (lsw & 0xFF)]; + + #ifdef AQ_VERBOSE + if (i && ((i % 512) == 0)) printf(" Byte: %X:\n", i << 2); + #endif + } + +#ifdef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE + /* flush the output buffer one last time. */ + AQ_API_MDIO_BlockOperationExecute(gangloadPort->PHY_ID); + countPendingOps = 0; +#endif + + /* Note: this final write right-justifies non-dWord data in the final dWord */ + switch (byteSize & 0x3) + { + case 0x1: + /* write 1 byte of data */ + lsw = image[bytePointer++]; + msw = 0x0000; + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 4) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 4, msw); + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 5) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 5, lsw); + + /* no polling */ + /* REGDOC: Write register (HHD/APPIA: 1E.0200) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, mailboxWrite); + break; + + case 0x2: + /* write 2 bytes of data */ + lsw = (image[bytePointer+1] << 8) | image[bytePointer]; + bytePointer += 2; + msw = 0x0000; + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 4) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 4, msw); + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 5) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 5, lsw); + + /* no polling */ + /* REGDOC: Write register (HHD/APPIA: 1E.0200) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, mailboxWrite); + break; + + case 0x3: + /* write 3 bytes of data */ + lsw = (image[bytePointer+1] << 8) | image[bytePointer]; + bytePointer += 2; + msw = image[bytePointer++]; + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 4) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 4, msw); + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 5) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 5, lsw); + + /* no polling */ + /* REGDOC: Write register (HHD/APPIA: 1E.0200) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, mailboxWrite); + break; + } + + if (byteSize & 0x3) + { + /* update the calculated CRC */ + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (msw >> 8)]; + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (msw & 0xFF)]; + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (lsw >> 8)]; + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (lsw & 0xFF)]; + } + + /* load the DRAM */ +#ifdef AQ_VERBOSE + printf ("\nCRC-16 after loading IRAM: 0x%X\n", crc16Calculated); + printf ("\nLoading DRAM:\n\n"); +#endif + + /* dWord align the address: note the image addressing is byte based, but is properly aligned on dWord + boundaries, so the 2 LSbits of the block start are always zero. */ + msw = (uint16_t) (AQ_DRAM_BASE_ADDRESS >> 16); + AQ_API_AssignWordOfLocalStruct(globalMailboxInterface, 3, 0x0000); + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.0203.1:0) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalMailboxInterface, globalMailboxInterface, + upMailboxAddressLSW, (AQ_DRAM_BASE_ADDRESS & 0xFFFF) >> 2); + lsw = AQ_API_WordOfLocalStruct(globalMailboxInterface, 3); + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 2) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 2, msw); /* MSW */ + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 3) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 3, lsw); /* LSW */ + + + /* set block size so that there are from 0-3 bytes remaining */ + byteSize = primaryDramSize; + dWordSize = byteSize >> 2; + + bytePointer = primaryDramPtr; + for (i = 0; i < dWordSize; i++) + { + /* write 4 bytes of data */ + lsw = (image[bytePointer+1] << 8) | image[bytePointer]; + bytePointer += 2; + msw = (image[bytePointer+1] << 8) | image[bytePointer]; + bytePointer += 2; + + #ifdef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE + AQ_API_BlockWriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 4, msw); + AQ_API_BlockWriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 5, lsw); + AQ_API_BlockWriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, mailboxWrite); + + countPendingOps += 3; + /* Check if we've filled our output buffer, and if so, flush. */ + if (countPendingOps >= AQ_API_MDIO_MaxBlockOperations() - 3 ) + { + AQ_API_MDIO_BlockOperationExecute (gangloadPort->PHY_ID); + countPendingOps = 0; + } + #else + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 4) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 4, msw); + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 5) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 5, lsw); + /* REGDOC: Write register (HHD/APPIA: 1E.0200) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, mailboxWrite); + #endif + + /* update the calculated CRC */ + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (msw >> 8)]; + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (msw & 0xFF)]; + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (lsw >> 8)]; + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (lsw & 0xFF)]; + + #ifdef AQ_VERBOSE + if (i && ((i % 512) == 0)) printf(" Byte: %X:\n", i << 2); + #endif + } + +#ifdef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE + /* flush the output buffer one last time. */ + AQ_API_MDIO_BlockOperationExecute(gangloadPort->PHY_ID); + countPendingOps = 0; +#endif + + /* Note: this final write right-justifies non-dWord data in the final dWord */ + switch (byteSize & 0x3) + { + case 0x1: + /* write 1 byte of data */ + lsw = image[bytePointer++]; + msw = 0x0000; + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 4) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 4, msw); + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 5) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 5, lsw); + + /* no polling */ + /* REGDOC: Write register (HHD/APPIA: 1E.0200) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, mailboxWrite); + break; + + case 0x2: + /* write 2 bytes of data */ + lsw = (image[bytePointer+1] << 8) | image[bytePointer]; + bytePointer += 2; + msw = 0x0000; + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 4) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 4, msw); + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 5) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 5, lsw); + + /* no polling */ + /* REGDOC: Write register (HHD/APPIA: 1E.0200) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, mailboxWrite); + break; + + case 0x3: + /* write 3 bytes of data */ + lsw = (image[bytePointer+1] << 8) | image[bytePointer]; + bytePointer += 2; + msw = image[bytePointer++]; + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 4) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 4, msw); + /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 5) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 5, lsw); + + /* no polling */ + /* REGDOC: Write register (HHD/APPIA: 1E.0200) */ + AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, mailboxWrite); + break; + } + + if (byteSize & 0x3) + { + /* update the calculated CRC */ + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (msw >> 8)]; + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (msw & 0xFF)]; + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (lsw >> 8)]; + crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (lsw & 0xFF)]; + } + + /*------------------------------------- Exit gangload mode -------------------------------------------------------*/ + AQ_API_DisableGangLoadMode(gangloadPort, recordedGGP1Values[0]); + + /*------------------------------------- Check mailbox CRCs -------------------------------------------------------*/ + /* check to make sure the mailbox CRC matches the calculated CRC */ + /*foundMailboxCRCMismatch = False;*/ + for (j = 0; j < numPorts; j++) + { + /* REGDOC: Read register (HHD/APPIA: 1E.0200 + 1) */ + mailboxCRC = AQ_API_ReadRegister(ports[j]->PHY_ID,AQ_GlobalMailboxInterface, 1); + if (mailboxCRC != crc16Calculated) + { + #ifdef AQ_VERBOSE + printf("\n%uth port: Mailbox CRC-16 (0x%X) does not match calculated CRC-16 (0x%X)\n", + j, mailboxCRC, crc16Calculated); + #endif + /* Note that we can't just return here, because we still need to + * release the uPs for the other PHYs that might have been + * bootloaded successfully. */ + resultCodes[j] = AQ_RET_BOOTLOAD_CRC_MISMATCH; + } + #ifdef AQ_VERBOSE + else + { + printf("\n%uth port: Image load good - mailbox CRC-16 matches (0x%X)\n", + j, mailboxCRC); + resultCodes[j] = AQ_RET_OK; + } + #endif + } + + /*------------------------------------- Clear any resets ---------------------------------------------------------*/ + for (j = 0; j < numPorts; j++) + { + /* REGDOC: Write register (HHD/APPIA: 1E.0000) */ + AQ_API_WriteRegister(ports[j]->PHY_ID,AQ_GlobalStandardControl_1, 0, 0x0000); + } + + /*------------------------------------- Release the uP -----------------------------------------------------------*/ + AQ_API_AssignWordOfLocalStruct(globalControl, 1, 0x0000); + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.6) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upRunStallOverride, 1); + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.0) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upRunStall, 1); + for (j = 0; j < numPorts; j++) + { + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.F) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upReset, 0); + /* REGDOC: Write register (HHD/APPIA: 1E.C000 + 1) */ + AQ_API_WriteRegister(ports[j]->PHY_ID,AQ_GlobalControl, 1, + AQ_API_WordOfLocalStruct(globalControl, 1)); + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.F) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upReset, 1); + /* REGDOC: Write register (HHD/APPIA: 1E.C000 + 1) */ + AQ_API_WriteRegister(ports[j]->PHY_ID,AQ_GlobalControl, 1, + AQ_API_WordOfLocalStruct(globalControl, 1)); + } + + /* Need to wait at least 100us. */ + AQ_API_Wait(1, ports[0]); + + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.F) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upReset, 0); + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.0) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upRunStall, 0); + for (j = 0; j < numPorts; j++) + { + if (AQ_DEVICE_APPIA == port->device) + { + /* If the BOOT_LD pins are set to MDIO boot load mode, we can't clear the + * uP run stall override bit. If we did, the uP would stall. */ + /* REGDOC: Read bitfield (APPIA: 1E.C840.E:D) */ + AQ_API_Get_DeviceRestricted(APPIA, j, AQ_GlobalPinStatus, mdioBootLoad, bootLoadMode); + if (bootLoadMode == 0x1) + { + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.6) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upRunStallOverride, 1); + } + else + { + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.6) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upRunStallOverride, 0); + } + } + else + { + /* For post-APPIA devices, always set the uP stall override bit to + * smooth over any packaging differences WRT the boot load pin. */ + /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.6) */ + AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upRunStallOverride, 1); + } + + /* REGDOC: Write register (HHD/APPIA: 1E.C000 + 1) */ + AQ_API_WriteRegister(ports[j]->PHY_ID,AQ_GlobalControl, 1, + AQ_API_WordOfLocalStruct(globalControl, 1)); + } + + /* NOTE!!! We can't re-enable the daisy-chain here, as this will overwrite the IRAM and DRAM with the FLASH contents*/ + + /* If any of the ports was not bootloaded successfully, return AQ_RET_ERROR */ + for (j = 0; j < numPorts; j++) + { + if (resultCodes[j] != AQ_RET_OK) + return AQ_RET_ERROR; + } + + /* All ports were bootloaded successfully. */ + return AQ_RET_OK; +} + + +AQ_Retcode AQ_API_WriteBootLoadImage +( + AQ_API_Port** ports, + unsigned int numPorts, + unsigned int* provisioningAddresses, + AQ_Retcode* resultCodes, + uint32_t* imageSizePointer, + uint8_t* image, + uint8_t gangload_MDIO_address, + AQ_API_Port* gangloadPort +) +{ + return AQ_API_WriteBootLoadImageWithProvTable(ports, numPorts, + provisioningAddresses, resultCodes, imageSizePointer, image, + gangload_MDIO_address, gangloadPort, NULL, NULL); +} + + +AQ_Retcode AQ_API_EnableDaisyChain +( + /*! The target PHY port.*/ + AQ_API_Port* port +) +{ + + /* declare local variables */ + AQ_API_Variable(AQ_GlobalNvrProvisioning) + AQ_API_Variable(AQ_GlobalReservedProvisioning) + + /* disable the hop-count override */ + /* REGDOC: Read-Modify-Write bitfield (HHD/APPIA: 1E.C471.6) */ + AQ_API_Set(port->PHY_ID, AQ_GlobalReservedProvisioning, enableDaisy_chainHop_countOverride, 0); + + /* enable the daisy-chain */ + /* REGDOC: Read-Modify-Write bitfield (HHD/APPIA: 1E.C452.0) */ + AQ_API_Set(port->PHY_ID, AQ_GlobalNvrProvisioning, nvrDaisyChainDisable, 0); + + return AQ_RET_OK; +} + +/*@}*/ + + +#ifdef __cplusplus +} +#endif diff --git a/qca/aq-fw-download/src/src/AQ_PhyInterface.c b/qca/aq-fw-download/src/src/AQ_PhyInterface.c new file mode 100644 index 000000000..6a8fce125 --- /dev/null +++ b/qca/aq-fw-download/src/src/AQ_PhyInterface.c @@ -0,0 +1,141 @@ +/* AQ_PhyInterface.c */ + +/************************************************************************************ +* Copyright (c) 2015, Aquantia +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +* +* $Revision: #12 $ +* +* $DateTime: 2015/02/25 15:34:49 $ +* +* $Label: $ +* +************************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include "AQ_PhyInterface.h" +#include "AQ_PlatformRoutines.h" + +#define MII_ADDR_C45 (0x8000) + +extern int sock; +extern char devname[7]; + +static struct ifreq ifr; + +/*! Provides generic synchronous PHY register write functionality. It is the + * responsibility of the system designer to provide the specific MDIO address + * pointer updates, etc. in order to accomplish this write operation. + * It will be assumed that the write has been completed by the time this + * function returns.*/ +void AQ_API_MDIO_Write( + /*! Uniquely identifies the port within the system. AQ_Port must be + * defined to a whatever data type is suitable for the platform.*/ + AQ_Port PHY_ID, + /*! The address of the MMD within the target PHY. */ + unsigned int MMD, + /*! The 16-bit address of the PHY register being written. */ + unsigned int address, + /*! The 16-bits of data to write to the specified PHY register. */ + unsigned int data) +{ + struct mii_ioctl_data mii; + + /* + * Frame the control structures + * and send the ioctl to kernel. + */ + memset(&ifr, 0, sizeof(ifr)); + strlcpy(ifr.ifr_name, devname, sizeof(ifr.ifr_name)); + memset(&mii, 0, sizeof(mii)); + memcpy(&mii, &ifr.ifr_data, sizeof(mii)); + mii.phy_id = MII_ADDR_C45 | PHY_ID << 5 | MMD; + mii.reg_num = address; + mii.val_in = data; + memcpy(&ifr.ifr_data, &mii, sizeof(mii)); + + if (ioctl(sock, SIOCSMIIREG, &ifr) < 0) { + fprintf(stderr, "SIOCSMIIREG on %s failed: %s\n", ifr.ifr_name, + strerror(errno)); + } + + return; +} + +/*! Provides generic synchronous PHY register read functionality. It is the + * responsibility of the system designer to provide the specific MDIO address + * pointer updates, etc. in order to accomplish this read operation.*/ +unsigned int AQ_API_MDIO_Read +( + /*! Uniquely identifies the port within the system. AQ_Port must be + * defined to a whatever data type is suitable for the platform.*/ + AQ_Port PHY_ID, + /*! The address of the MMD within the target PHY. */ + unsigned int MMD, + /*! The 16-bit address of the PHY register being read. */ + unsigned int address) +{ + struct mii_ioctl_data mii; + + /* + * Frame the control structures + * and send the ioctl to kernel. + */ + memset(&ifr, 0, sizeof(ifr)); + strlcpy(ifr.ifr_name, devname, sizeof(ifr.ifr_name)); + memset(&mii, 0, sizeof(mii)); + memcpy(&mii, &ifr.ifr_data, sizeof(mii)); + mii.phy_id = MII_ADDR_C45 | PHY_ID << 5 | MMD; + mii.reg_num = address; + memcpy(&ifr.ifr_data, &mii, sizeof(mii)); + + if (ioctl(sock, SIOCGMIIREG, &ifr) < 0) { + fprintf(stderr, "SIOCGMIIREG on %s failed: %s\n", ifr.ifr_name, + strerror(errno)); + return -1; + } else { + memcpy(&mii, &ifr.ifr_data, sizeof(mii)); + } + + + return mii.val_out; +} + +/*! Returns after at least milliseconds have elapsed. This must be implemented + * * in a platform-approriate way. AQ_API functions will call this function to + * * block for the specified period of time. If necessary, PHY register reads + * * may be performed on port to busy-wait. */ +void AQ_API_Wait( + uint32_t milliseconds, /*!< The delay in milliseconds */ + AQ_API_Port* port /*!< The PHY to use if delay reads are necessary*/ ) +{ + unsigned long long mirco = milliseconds *1000; + usleep(mirco); +} diff --git a/qca/nss-eip-firmware/Makefile b/qca/nss-eip-firmware/Makefile new file mode 100644 index 000000000..a20c9afd6 --- /dev/null +++ b/qca/nss-eip-firmware/Makefile @@ -0,0 +1,34 @@ +include $(TOPDIR)/rules.mk + +PKG_NAME:=nss-eip-firmware +PKG_VERSION=2.5.7 +PKG_RELEASE:=$(AUTORELEASE) + +PKG_MAINTAINER:=Robert Marko + +include $(INCLUDE_DIR)/package.mk + +define Package/nss-eip-firmware + SECTION:=firmware + CATEGORY:=Firmware + TITLE:=NSS EIP-197 firmware + DEPENDS:=@(TARGET_ipq807x||TARGET_ipq60xx) +endef + +define Build/Compile + +endef + +define Package/nss-eip-firmware/install + $(INSTALL_DIR) $(1)/lib/firmware/ + $(INSTALL_DATA) \ + $(PKG_BUILD_DIR)/ifpp.bin $(1)/lib/firmware/ifpp.bin + $(INSTALL_DATA) \ + $(PKG_BUILD_DIR)/ipue.bin $(1)/lib/firmware/ipue.bin + $(INSTALL_DATA) \ + $(PKG_BUILD_DIR)/ofpp.bin $(1)/lib/firmware/ofpp.bin + $(INSTALL_DATA) \ + $(PKG_BUILD_DIR)/opue.bin $(1)/lib/firmware/opue.bin +endef + +$(eval $(call BuildPackage,nss-eip-firmware)) diff --git a/qca/nss-eip-firmware/src/.gitkeep b/qca/nss-eip-firmware/src/.gitkeep new file mode 100644 index 000000000..e69de29bb diff --git a/qca/nss-firmware/Makefile b/qca/nss-firmware/Makefile new file mode 100644 index 000000000..eff44a8fb --- /dev/null +++ b/qca/nss-firmware/Makefile @@ -0,0 +1,72 @@ +# +# Copyright (C) 2021 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +include $(TOPDIR)/rules.mk + +PKG_NAME:=nss-firmware +PKG_SOURCE_DATE:=2022-05-16 +PKG_SOURCE_VERSION:=20c9a9b7e0ea2935b0a54f112104e433009312ca +PKG_MIRROR_HASH:=376b3605776f75bccb1da2b30dd522cc22d3f6b17dff6c954dd9b7222418d6c6 +PKG_RELEASE:=$(AUTORELEASE) + +PKG_SOURCE_PROTO:=git +PKG_SOURCE_URL:=https://github.com/quic/qca-sdk-nss-fw.git + +PKG_LICENSE_FILES:=LICENSE.md + +PKG_MAINTAINER:=Robert Marko + +include $(INCLUDE_DIR)/package.mk + +VERSION_PATH=$(PKG_BUILD_DIR)/QCA_Networking.SPF_11.5.0/CS + +define Package/nss-firmware-default + SECTION:=firmware + CATEGORY:=Firmware + URL:=$(PKG_SOURCE_URL) + DEPENDS:=@(TARGET_ipq807x||TARGET_ipq60xx) +endef + +define Package/nss-firmware-ipq6018 +$(Package/nss-firmware-default) + TITLE:=NSS firmware for IPQ6018 devices + NSS_ARCHIVE:=$(VERSION_PATH)/IPQ6018.ATH.11.4/BIN-NSS.CP.11.4.0.5-5-R.tar.bz2 +endef + +define Package/nss-firmware-ipq8074 +$(Package/nss-firmware-default) + TITLE:=NSS firmware for IPQ8074 devices + NSS_ARCHIVE:=$(VERSION_PATH)/IPQ8074.ATH.11.5.0/BIN-NSS.FW.12.0.r1-002-HK.R.tar.bz2 +endef + +define Build/Compile + +endef + +define Package/nss-firmware-ipq6018/install + mkdir -p $(PKG_BUILD_DIR)/IPQ6018 + $(TAR) -C $(PKG_BUILD_DIR)/IPQ6018 -xf $(NSS_ARCHIVE) --strip-components=1 + $(INSTALL_DIR) $(1)/lib/firmware/ + $(INSTALL_DATA) \ + $(PKG_BUILD_DIR)/IPQ6018/retail_router0.bin \ + $(1)/lib/firmware/qca-nss0-retail.bin +endef + +define Package/nss-firmware-ipq8074/install + mkdir -p $(PKG_BUILD_DIR)/IPQ8074 + $(TAR) -C $(PKG_BUILD_DIR)/IPQ8074 -xf $(NSS_ARCHIVE) --strip-components=1 + $(INSTALL_DIR) $(1)/lib/firmware/ + $(INSTALL_DATA) \ + $(PKG_BUILD_DIR)/IPQ8074/retail_router0.bin \ + $(1)/lib/firmware/qca-nss0-retail.bin + $(INSTALL_DATA) \ + $(PKG_BUILD_DIR)/IPQ8074/retail_router1.bin \ + $(1)/lib/firmware/qca-nss1-retail.bin +endef + +$(eval $(call BuildPackage,nss-firmware-ipq6018)) +$(eval $(call BuildPackage,nss-firmware-ipq8074)) diff --git a/qca/qca-nss-cfi/Makefile b/qca/qca-nss-cfi/Makefile new file mode 100644 index 000000000..64f7bd7ab --- /dev/null +++ b/qca/qca-nss-cfi/Makefile @@ -0,0 +1,71 @@ +include $(TOPDIR)/rules.mk + +PKG_NAME:=qca-nss-cfi +PKG_RELEASE:=1 + +PKG_SOURCE_PROTO:=git +PKG_SOURCE_DATE:=2021-03-22 +PKG_SOURCE_URL:=https://source.codeaurora.org/quic/qsdk/oss/lklm/nss-cfi +PKG_SOURCE_VERSION:=73f2e5f5bf93cc244036ce5641faf9f859692cdf +PKG_MIRROR_HASH:=8c8edc9b8d8c68fdd14640152245013a93c123957b6b338c06f266f6c9db8cbd + +include $(INCLUDE_DIR)/kernel.mk +include $(INCLUDE_DIR)/package.mk + +# v1.0 is for Akronite +# v2.0 is for Hawkeye/Cypress/Maple +ifneq (, $(findstring $(BOARD), ipq50xx ipq60xx ipq807x)) + CFI_OCF_DIR:=ocf/v2.0 + CFI_CRYPTOAPI_DIR:=cryptoapi/v2.0 +else + CFI_CRYPTOAPI_DIR:=cryptoapi/v1.1 + CFI_OCF_DIR:=ocf/v1.0 + CFI_IPSEC_DIR:=ipsec/v1.0 +endif + +define KernelPackage/qca-nss-cfi-cryptoapi + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + DEPENDS:=@TARGET_ipq60xx +kmod-crypto-authenc +kmod-qca-nss-crypto + TITLE:=Kernel driver for NSS cfi + FILES:=$(PKG_BUILD_DIR)/$(CFI_CRYPTOAPI_DIR)/qca-nss-cfi-cryptoapi.ko + AUTOLOAD:=$(call AutoLoad,59,qca-nss-cfi-cryptoapi) +endef + +define Build/InstallDev + $(INSTALL_DIR) $(1)/usr/include/qca-nss-cfi + $(CP) $(PKG_BUILD_DIR)/$(CFI_CRYPTOAPI_DIR)/../exports/* $(1)/usr/include/qca-nss-cfi + $(CP) $(PKG_BUILD_DIR)/include/* $(1)/usr/include/qca-nss-cfi +endef + +define KernelPackage/qca-nss-cfi/Description +This package contains a NSS cfi driver for QCA chipset +endef + +EXTRA_CFLAGS+= \ + -DCONFIG_NSS_DEBUG_LEVEL=4 \ + -I$(LINUX_DIR)/crypto/ocf \ + -I$(STAGING_DIR)/usr/include/qca-nss-crypto \ + -I$(STAGING_DIR)/usr/include/crypto \ + -I$(STAGING_DIR)/usr/include/qca-nss-drv + +ifneq (, $(findstring $(BOARD), ipq50xx ipq60xx ipq807x)) +EXTRA_CFLAGS+= -I$(STAGING_DIR)/usr/include/qca-nss-clients +endif + +define Build/Compile + $(MAKE) -C "$(LINUX_DIR)" \ + CROSS_COMPILE="$(TARGET_CROSS)" \ + EXTRA_CFLAGS="$(EXTRA_CFLAGS)" \ + CFI_CRYPTOAPI_DIR=$(CFI_CRYPTOAPI_DIR) \ + CFI_IPSEC_DIR=$(CFI_IPSEC_DIR) \ + CFI_OCF_DIR=$(CFI_OCF_DIR) \ + $(KERNEL_MAKE_FLAGS) \ + M="$(PKG_BUILD_DIR)" \ + SoC="$(BOARD)_64" \ + "cryptoapi=y" \ + modules +endef + +$(eval $(call KernelPackage,qca-nss-cfi-cryptoapi)) diff --git a/qca/qca-nss-cfi/patches/100-remove-noise-logs.patch b/qca/qca-nss-cfi/patches/100-remove-noise-logs.patch new file mode 100644 index 000000000..085aeaf24 --- /dev/null +++ b/qca/qca-nss-cfi/patches/100-remove-noise-logs.patch @@ -0,0 +1,30 @@ +--- a/cryptoapi/v2.0/nss_cryptoapi_ahash.c ++++ b/cryptoapi/v2.0/nss_cryptoapi_ahash.c +@@ -449,9 +449,12 @@ int nss_cryptoapi_ahash_digest(struct ahash_request *req) + int nss_cryptoapi_ahash_export(struct ahash_request *req, void *out) + { + struct nss_cryptoapi_ctx *ctx __attribute__((unused)) = crypto_tfm_ctx(req->base.tfm); ++ struct nss_cryptoapi_req_ctx *rctx = ahash_request_ctx(req); ++ struct nss_cryptoapi_req_ctx *state = out; ++ ++ *state = *rctx; + +- nss_cfi_warn("%px: ahash .export is not supported", ctx); +- return -ENOSYS; ++ return 0; + }; + + /* +@@ -464,7 +467,10 @@ int nss_cryptoapi_ahash_export(struct ahash_request *req, void *out) + int nss_cryptoapi_ahash_import(struct ahash_request *req, const void *in) + { + struct nss_cryptoapi_ctx *ctx __attribute__((unused)) = crypto_tfm_ctx(req->base.tfm); ++ struct nss_cryptoapi_req_ctx *rctx = ahash_request_ctx(req); ++ const struct nss_cryptoapi_req_ctx *state = in; ++ ++ *rctx = *state; + +- nss_cfi_warn("%px: ahash .import is not supported", ctx); +- return -ENOSYS; ++ return 0; + } diff --git a/qca/qca-nss-clients/Makefile b/qca/qca-nss-clients/Makefile new file mode 100644 index 000000000..274512780 --- /dev/null +++ b/qca/qca-nss-clients/Makefile @@ -0,0 +1,102 @@ +include $(TOPDIR)/rules.mk + +PKG_NAME:=qca-nss-clients +PKG_RELEASE:=$(AUTORELEASE) + +PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/nss-clients.git +PKG_SOURCE_PROTO:=git +PKG_SOURCE_DATE:=2021-07-23 +PKG_SOURCE_VERSION:=ec7a57bed8914adcbd5bf95de1f0b630296489c1 +PKG_MIRROR_HASH:=b7413c5b20a341d3d7ea49c1b86ff92b4a8795aa7c64986ca820ba18205e332d + +include $(INCLUDE_DIR)/kernel.mk +include $(INCLUDE_DIR)/package.mk + +define KernelPackage/qca-nss-drv-pppoe + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=Kernel driver for NSS (connection manager) - PPPoE + DEPENDS:=@LINUX_5_10 @TARGET_ipq807x +kmod-qca-nss-drv +kmod-ppp +kmod-pppoe + FILES:=$(PKG_BUILD_DIR)/pppoe/qca-nss-pppoe.ko + AUTOLOAD:=$(call AutoLoad,51,qca-nss-pppoe) +endef + +define KernelPackage/qca-nss-drv-pppoe/Description +Kernel modules for NSS connection manager - Support for PPPoE +endef + +define KernelPackage/qca-nss-drv-bridge-mgr + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=Kernel driver for NSS bridge manager + DEPENDS:=@LINUX_5_10 @TARGET_ipq807x +kmod-qca-nss-drv +kmod-qca-nss-drv-vlan-mgr + FILES:=$(PKG_BUILD_DIR)/bridge/qca-nss-bridge-mgr.ko + AUTOLOAD:=$(call AutoLoad,51,qca-nss-bridge-mgr) +endef + +define KernelPackage/qca-nss-drv-bridge-mgr/Description +Kernel modules for NSS bridge manager +endef + +define KernelPackage/qca-nss-drv-vlan-mgr + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=Kernel driver for NSS vlan manager + DEPENDS:=@LINUX_5_10 @TARGET_ipq807x +kmod-qca-nss-drv + FILES:=$(PKG_BUILD_DIR)/vlan/qca-nss-vlan.ko + AUTOLOAD:=$(call AutoLoad,51,qca-nss-vlan) +endef + +define KernelPackage/qca-nss-drv-vlan-mgr/Description +Kernel modules for NSS vlan manager +endef + +EXTRA_CFLAGS+= \ + -I$(STAGING_DIR)/usr/include/qca-nss-drv \ + -I$(STAGING_DIR)/usr/include/qca-nss-crypto \ + -I$(STAGING_DIR)/usr/include/qca-nss-cfi \ + -I$(STAGING_DIR)/usr/include/qca-nss-gmac \ + -I$(STAGING_DIR)/usr/include/qca-ssdk \ + -I$(STAGING_DIR)/usr/include/qca-ssdk/fal \ + -I$(STAGING_DIR)/usr/include/nat46 + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-pppoe),) +NSS_CLIENTS_MAKE_OPTS+=pppoe=y +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-bridge-mgr),) +NSS_CLIENTS_MAKE_OPTS+=bridge-mgr=y +#enable OVS bridge if ovsmgr is enabled +ifneq ($(CONFIG_PACKAGE_kmod-qca-ovsmgr),) +NSS_CLIENTS_MAKE_OPTS+= NSS_BRIDGE_MGR_OVS_ENABLE=y +EXTRA_CFLAGS+= -I$(STAGING_DIR)/usr/include/qca-ovsmgr +endif +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-vlan-mgr),) +NSS_CLIENTS_MAKE_OPTS+=vlan-mgr=y +endif + +ifeq ($(CONFIG_TARGET_BOARD), "ipq807x") + SOC="ipq807x_64" +else ifeq ($(CONFIG_TARGET_BOARD), "ipq60xx") + SOC="ipq60xx_64" +endif + +define Build/Compile + $(MAKE) -C "$(LINUX_DIR)" $(strip $(NSS_CLIENTS_MAKE_OPTS)) \ + CROSS_COMPILE="$(TARGET_CROSS)" \ + ARCH="$(LINUX_KARCH)" \ + M="$(PKG_BUILD_DIR)" \ + EXTRA_CFLAGS="$(EXTRA_CFLAGS)" \ + SoC=$(SOC) \ + $(KERNEL_MAKE_FLAGS) \ + modules +endef + +$(eval $(call KernelPackage,qca-nss-drv-pppoe)) +$(eval $(call KernelPackage,qca-nss-drv-bridge-mgr)) +$(eval $(call KernelPackage,qca-nss-drv-vlan-mgr)) diff --git a/qca/qca-nss-clients/files/qca-nss-ipsec b/qca/qca-nss-clients/files/qca-nss-ipsec new file mode 100644 index 000000000..5f682c8e9 --- /dev/null +++ b/qca/qca-nss-clients/files/qca-nss-ipsec @@ -0,0 +1,214 @@ +#!/bin/sh /etc/rc.common +# +# Copyright (c) 2018-2019, 2021 The Linux Foundation. All rights reserved. +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +NSS_IPSEC_LOG_FILE=/tmp/.nss_ipsec_log +NSS_IPSEC_LOG_STR_ECM="ECM_Loaded" +NSS_IPSEC_OL_FILE=/tmp/qca_nss_ipsec_ol + +ecm_load () { + if [ ! -d /sys/module/ecm ]; then + /etc/init.d/qca-nss-ecm start + if [ -d /sys/module/ecm ]; then + echo ${NSS_IPSEC_LOG_STR_ECM} >> ${NSS_IPSEC_LOG_FILE} + fi + fi +} + +ecm_unload () { + if [ -f /tmp/.nss_ipsec_log ]; then + str=`grep ${NSS_IPSEC_LOG_STR_ECM} ${NSS_IPSEC_LOG_FILE}` + if [[ $str == ${NSS_IPSEC_LOG_STR_ECM} ]]; then + /etc/init.d/qca-nss-ecm stop + `sed 's/${NSS_IPSEC_LOG_STR_ECM}/ /g' $NSS_IPSEC_LOG_FILE > $NSS_IPSEC_LOG_FILE` + fi + fi +} + +ecm_disable() { + + if [ ! -d /sys/module/ecm ]; then + return; + fi + + echo 1 > /sys/kernel/debug/ecm/front_end_ipv4_stop + echo 1 > /sys/kernel/debug/ecm/front_end_ipv6_stop + echo 1 > /sys/kernel/debug/ecm/ecm_db/defunct_all + sleep 2 +} + +ecm_enable() { + if [ ! -d /sys/module/ecm ]; then + return; + fi + + echo 0 > /sys/kernel/debug/ecm/ecm_db/defunct_all + echo 0 > /sys/kernel/debug/ecm/front_end_ipv4_stop + echo 0 > /sys/kernel/debug/ecm/front_end_ipv6_stop +} + +kernel_version_check_5_4() { + major_ver=$(uname -r | awk -F '.' '{print $1}') + minor_ver=$(uname -r | awk -F '.' '{print $2}') + if [ $major_ver -lt 5 ] || ([ $major_ver -eq 5 ] && [ $minor_ver -lt 4 ] ) ; then + return 1 + else + return 0 + fi +} + +start_klips() { + if kernel_version_check_5_4 + then + echo "Kernel 5.4 doesn't support klips stack." + return $? + fi + + touch $NSS_IPSEC_OL_FILE + ecm_load + + local kernel_version=$(uname -r) + + insmod /lib/modules/${kernel_version}/qca-nss-ipsec-klips.ko + if [ "$?" -gt 0 ]; then + echo "Failed to load plugin. Please start ecm if not done already" + ecm_enable + rm $NSS_IPSEC_OL_FILE + return + fi + + /etc/init.d/ipsec start + sleep 2 + ipsec eroute + + ecm_enable +} + +stop_klips() { + if kernel_version_check_5_4 + then + echo "Kernel 5.4 doesn't support klips stack." + return $? + fi + + ecm_disable + + /etc/init.d/ipsec stop + rmmod qca-nss-ipsec-klips + rm $NSS_IPSEC_OL_FILE + + ecm_unload +} + +start_xfrm() { + touch $NSS_IPSEC_OL_FILE + ecm_load + + local kernel_version=$(uname -r) + + # load all NETKEY modules first. + for mod in xfrm_ipcomp ipcomp xfrm6_tunnel ipcomp6 xfrm6_mode_tunnel xfrm6_mode_beet xfrm6_mode_ro \ + xfrm6_mode_transport xfrm4_mode_transport xfrm4_mode_tunnel \ + xfrm4_tunnel xfrm4_mode_beet esp4 esp6 ah4 ah6 af_key + do + insmod $mod 2> /dev/null + done + + # Now load the xfrm plugin + insmod /lib/modules/${kernel_version}/qca-nss-ipsec-xfrm.ko + if [ "$?" -gt 0 ]; then + echo "Failed to load plugin. Please start ecm if not done already" + ecm_enable + rm $NSS_IPSEC_OL_FILE + return + fi + + /etc/init.d/ipsec start + sleep 2 + + ecm_enable +} + +stop_xfrm() { + ecm_disable + + #Shutdown Pluto first. Then only plugin can be removed. + plutopid=/var/run/pluto/pluto.pid + if [ -f $plutopid ]; then + pid=`cat $plutopid` + if [ ! -z "$pid" ]; then + ipsec whack --shutdown | grep -v "002"; + if [ -s $plutopid ]; then + echo "Attempt to shut Pluto down failed! Trying kill:" + kill $pid; + sleep 5; + fi + fi + rm -rf $plutopid + fi + ip xfrm state flush; + ip xfrm policy flush; + sleep 2 + + #Now we can remove the plugin + retries=5 + while [ -d /sys/module/qca_nss_ipsec_xfrm ] + do + rmmod qca-nss-ipsec-xfrm + if [ "$?" -eq 0 ]; then + rm $NSS_IPSEC_OL_FILE + break + fi + + if [ ${retries} -eq 0 ]; then + echo "Failed to unload qca-nss-ipsec-xfrm plugin!" + exit + fi + + echo "XFRM plugin unload failed; retrying ${retries} times" + sleep 1 + retries=`expr ${retries} - 1` + done + + /etc/init.d/ipsec stop + ecm_unload +} + +start() { + local protostack=`uci -q get ipsec.setup.protostack` + if [ "$protostack" = "klips" ]; then + start_klips + return $? + fi + + start_xfrm + return $? +} + +stop() { + local protostack=`uci -q get ipsec.setup.protostack` + if [ "$protostack" = "klips" ]; then + stop_klips + return $? + fi + + stop_xfrm + return $? +} + +restart() { + stop + start +} diff --git a/qca/qca-nss-clients/files/qca-nss-mirred.init b/qca/qca-nss-clients/files/qca-nss-mirred.init new file mode 100644 index 000000000..1f931f090 --- /dev/null +++ b/qca/qca-nss-clients/files/qca-nss-mirred.init @@ -0,0 +1,28 @@ +#!/bin/sh /etc/rc.common + +########################################################################### +# Copyright (c) 2019, The Linux Foundation. All rights reserved. +# Permission to use, copy, modify, and/or distribute this software for +# any purpose with or without fee is hereby granted, provided that the +# above copyright notice and this permission notice appear in all copies. +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT +# OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +########################################################################### + +restart() { + rmmod act_nssmirred.ko + insmod act_nssmirred.ko +} + +start() { + insmod act_nssmirred.ko +} + +stop() { + rmmod act_nssmirred.ko +} diff --git a/qca/qca-nss-clients/files/qca-nss-ovpn.init b/qca/qca-nss-clients/files/qca-nss-ovpn.init new file mode 100644 index 000000000..622e295ee --- /dev/null +++ b/qca/qca-nss-clients/files/qca-nss-ovpn.init @@ -0,0 +1,69 @@ +#!/bin/sh /etc/rc.common + +########################################################################### +# Copyright (c) 2019, The Linux Foundation. All rights reserved. +# Permission to use, copy, modify, and/or distribute this software for +# any purpose with or without fee is hereby granted, provided that the +# above copyright notice and this permission notice appear in all copies. +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT +# OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +########################################################################### + +ecm_disable() { + if [ ! -d /sys/module/ecm ]; then + return + fi + + echo 1 > /sys/kernel/debug/ecm/front_end_ipv4_stop + echo 1 > /sys/kernel/debug/ecm/front_end_ipv6_stop + echo 1 > /sys/kernel/debug/ecm/ecm_db/defunct_all + sleep 2 +} + +ecm_enable() { + if [ ! -d /sys/module/ecm ]; then + return + fi + + echo 0 > /sys/kernel/debug/ecm/ecm_db/defunct_all + echo 0 > /sys/kernel/debug/ecm/front_end_ipv4_stop + echo 0 > /sys/kernel/debug/ecm/front_end_ipv6_stop +} + +restart() { + ecm_disable + + /etc/init.d/openvpn stop + rmmod qca-nss-ovpn-link + rmmod qca-nss-ovpn-mgr + + insmod qca-nss-ovpn-mgr + insmod qca-nss-ovpn-link + + if [ "$?" -gt 0 ]; then + echo "Failed to load plugin. Please start ecm if not done already" + ecm_enable + return + fi + + ecm_enable +} + +start() { + restart +} + +stop() { + ecm_disable + + /etc/init.d/openvpn stop + rmmod qca-nss-ovpn-link + rmmod qca-nss-ovpn-mgr + + ecm_enable +} diff --git a/qca/qca-nss-crypto/Makefile b/qca/qca-nss-crypto/Makefile new file mode 100644 index 000000000..5c1003b89 --- /dev/null +++ b/qca/qca-nss-crypto/Makefile @@ -0,0 +1,72 @@ +include $(TOPDIR)/rules.mk + +PKG_NAME:=qca-nss-crypto +PKG_RELEASE:=$(AUTORELEASE) + +PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/nss-crypto.git +PKG_SOURCE_PROTO:=git +PKG_SOURCE_DATE:=2021-03-20 +PKG_SOURCE_VERSION:=2271a3a66f7e8284d42a9e787ddec6f24a1d2e15 +PKG_MIRROR_HASH:=afd2b746779bf9abb72dfb58c755acf54d1cb51085b879013dd0edf9ba98d3c9 + +PKG_BUILD_PARALLEL:=1 + +include $(INCLUDE_DIR)/kernel.mk +include $(INCLUDE_DIR)/package.mk + +ifeq ($(CONFIG_TARGET_BOARD), "ipq807x") + SOC="ipq807x_64" +else ifeq ($(CONFIG_TARGET_BOARD), "ipq60xx") + SOC="ipq60xx_64" +endif + +# v1.0 is for Akronite +# v2.0 is for Hawkeye/Cypress/Maple +ifneq (, $(findstring $(CONFIG_TARGET_BOARD), "ipq807x" "ipq60xx")) +NSS_CRYPTO_DIR:=v2.0 +else +NSS_CRYPTO_DIR:=v1.0 +endif + +define KernelPackage/qca-nss-crypto + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Cryptographic API modules + DEPENDS:=@(TARGET_ipq807x||TARGET_ipq60xx) +kmod-qca-nss-drv +nss-eip-firmware + TITLE:=Kernel driver for NSS crypto driver + FILES:=$(PKG_BUILD_DIR)/$(NSS_CRYPTO_DIR)/src/qca-nss-crypto.ko \ + $(PKG_BUILD_DIR)/$(NSS_CRYPTO_DIR)/tool/qca-nss-crypto-tool.ko + AUTOLOAD:=$(call AutoLoad,52,qca-nss-crypto) +endef + +define KernelPackage/qca-nss-crypto/Description +This package contains a NSS crypto driver for QCA chipset +endef + +define Build/InstallDev + $(INSTALL_DIR) $(1)/usr/include/qca-nss-crypto + $(CP) $(PKG_BUILD_DIR)/$(NSS_CRYPTO_DIR)/include/* $(1)/usr/include/qca-nss-crypto +endef + +EXTRA_CFLAGS+= \ + -DCONFIG_NSS_DEBUG_LEVEL=4 \ + -I$(STAGING_DIR)/usr/include/qca-nss-crypto \ + -I$(STAGING_DIR)/usr/include/qca-nss-drv \ + -I$(PKG_BUILD_DIR)/$(NSS_CRYPTO_DIR)/include \ + -I$(PKG_BUILD_DIR)/$(NSS_CRYPTO_DIR)/src + +define Build/Compile + +$(MAKE) -C "$(LINUX_DIR)" \ + CC="$(TARGET_CC)" \ + CROSS_COMPILE="$(TARGET_CROSS)" \ + ARCH="$(LINUX_KARCH)" \ + M="$(PKG_BUILD_DIR)" \ + EXTRA_CFLAGS="$(EXTRA_CFLAGS)" \ + NSS_CRYPTO_DIR=$(NSS_CRYPTO_DIR) \ + SoC=$(SOC) \ + $(KERNEL_MAKE_FLAGS) \ + $(PKG_JOBS) \ + modules +endef + +$(eval $(call KernelPackage,qca-nss-crypto)) diff --git a/qca/qca-nss-crypto/patches/0001-nss-crypto-fix-SHA1-header-include.patch b/qca/qca-nss-crypto/patches/0001-nss-crypto-fix-SHA1-header-include.patch new file mode 100644 index 000000000..757b172ea --- /dev/null +++ b/qca/qca-nss-crypto/patches/0001-nss-crypto-fix-SHA1-header-include.patch @@ -0,0 +1,32 @@ +From 68b7776673aabc2f93bd75e73ef4b45a1ac561d9 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Sun, 13 Mar 2022 13:44:47 +0100 +Subject: [PATCH 1/3] nss-crypto: fix SHA1 header include + +SHA1 header has been merged to the generic SHA one, +and with that the cryptohash.h was dropped. + +So, fix include in kernels 5.8 and newer. + +Signed-off-by: Robert Marko +--- + v2.0/src/nss_crypto_hlos.h | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/v2.0/src/nss_crypto_hlos.h b/v2.0/src/nss_crypto_hlos.h +index 84740c2..e827f4f 100644 +--- a/v2.0/src/nss_crypto_hlos.h ++++ b/v2.0/src/nss_crypto_hlos.h +@@ -55,7 +55,9 @@ + #include + #include + #include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 8, 0) + #include ++#endif + #include + #include + #include +-- +2.35.1 + diff --git a/qca/qca-nss-crypto/patches/0002-nss-crypto-replace-ioremap_nocache-with-ioremap.patch b/qca/qca-nss-crypto/patches/0002-nss-crypto-replace-ioremap_nocache-with-ioremap.patch new file mode 100644 index 000000000..8c829c11e --- /dev/null +++ b/qca/qca-nss-crypto/patches/0002-nss-crypto-replace-ioremap_nocache-with-ioremap.patch @@ -0,0 +1,69 @@ +From 80393ab565e26d572de56b7502b069b0a944bd40 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Tue, 8 Jun 2021 22:14:34 +0200 +Subject: [PATCH 2/3] nss-crypto: replace ioremap_nocache() with ioremap + +ioremap_nocache() was dropped in kernel 5.5 as regular +ioremap() was exactly the same. + +So, simply replace all of the ioremap_nocache() calls +with ioremap(). + +Signed-off-by: Robert Marko +--- + v2.0/src/hal/ipq50xx/nss_crypto_ce5.c | 4 ++-- + v2.0/src/hal/ipq60xx/nss_crypto_eip197.c | 2 +- + v2.0/src/hal/ipq807x/nss_crypto_eip197.c | 2 +- + 3 files changed, 4 insertions(+), 4 deletions(-) + +diff --git a/v2.0/src/hal/ipq50xx/nss_crypto_ce5.c b/v2.0/src/hal/ipq50xx/nss_crypto_ce5.c +index c89cd38..a7a46e0 100644 +--- a/v2.0/src/hal/ipq50xx/nss_crypto_ce5.c ++++ b/v2.0/src/hal/ipq50xx/nss_crypto_ce5.c +@@ -288,7 +288,7 @@ int nss_crypto_ce5_engine_init(struct platform_device *pdev, struct resource *cr + * remap the I/O addresses for crypto + */ + eng->crypto_paddr = crypto_res->start; +- eng->crypto_vaddr = ioremap_nocache(crypto_res->start, resource_size(crypto_res)); ++ eng->crypto_vaddr = ioremap(crypto_res->start, resource_size(crypto_res)); + if (!eng->crypto_vaddr) { + nss_crypto_warn("%px: unable to remap crypto_addr(0x%px)\n", node, (void *)eng->crypto_paddr); + nss_crypto_engine_free(eng); +@@ -299,7 +299,7 @@ int nss_crypto_ce5_engine_init(struct platform_device *pdev, struct resource *cr + * remap the I/O addresses for bam + */ + eng->dma_paddr = bam_res->start; +- eng->dma_vaddr = ioremap_nocache(bam_res->start, resource_size(bam_res)); ++ eng->dma_vaddr = ioremap(bam_res->start, resource_size(bam_res)); + if (!eng->dma_vaddr) { + iounmap(eng->crypto_vaddr); + nss_crypto_warn("%px: unable to remap dma_addr(0x%px)\n", node, (void *)eng->dma_paddr); +diff --git a/v2.0/src/hal/ipq60xx/nss_crypto_eip197.c b/v2.0/src/hal/ipq60xx/nss_crypto_eip197.c +index 8dfc35d..79649f9 100644 +--- a/v2.0/src/hal/ipq60xx/nss_crypto_eip197.c ++++ b/v2.0/src/hal/ipq60xx/nss_crypto_eip197.c +@@ -490,7 +490,7 @@ int nss_crypto_eip197_engine_init(struct platform_device *pdev, struct device_no + * remap the I/O addresses + */ + paddr = res->start + offset; +- vaddr = ioremap_nocache(paddr, resource_size(res)); ++ vaddr = ioremap(paddr, resource_size(res)); + if (!vaddr) { + nss_crypto_warn("%px: unable to remap crypto_addr(0x%px)\n", node, (void *)paddr); + return -EIO; +diff --git a/v2.0/src/hal/ipq807x/nss_crypto_eip197.c b/v2.0/src/hal/ipq807x/nss_crypto_eip197.c +index 632adca..5e2c146 100644 +--- a/v2.0/src/hal/ipq807x/nss_crypto_eip197.c ++++ b/v2.0/src/hal/ipq807x/nss_crypto_eip197.c +@@ -490,7 +490,7 @@ int nss_crypto_eip197_engine_init(struct platform_device *pdev, struct device_no + * remap the I/O addresses + */ + paddr = res->start + offset; +- vaddr = ioremap_nocache(paddr, resource_size(res)); ++ vaddr = ioremap(paddr, resource_size(res)); + if (!vaddr) { + nss_crypto_warn("%px: unable to remap crypto_addr(0x%px)\n", node, (void *)paddr); + return -EIO; +-- +2.35.1 + diff --git a/qca/qca-nss-crypto/patches/0003-nss-crypto-fix-SHA-header-include-in-5.15.patch b/qca/qca-nss-crypto/patches/0003-nss-crypto-fix-SHA-header-include-in-5.15.patch new file mode 100644 index 000000000..311070d91 --- /dev/null +++ b/qca/qca-nss-crypto/patches/0003-nss-crypto-fix-SHA-header-include-in-5.15.patch @@ -0,0 +1,51 @@ +From 4c0cc66cde0c4a30aa049b586af311501304e9ce Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Sun, 13 Mar 2022 13:47:24 +0100 +Subject: [PATCH 3/3] nss-crypto: fix SHA header include in 5.15 + +SHA header was split into SHA-1 and SHA-2 headers in kernel 5.11, so +fix the include for newer kernels. + +Signed-off-by: Robert Marko +--- + v2.0/src/nss_crypto_ctrl.c | 6 ++++++ + v2.0/src/nss_crypto_hlos.h | 4 ++++ + 2 files changed, 10 insertions(+) + +diff --git a/v2.0/src/nss_crypto_ctrl.c b/v2.0/src/nss_crypto_ctrl.c +index 72d1602..a462705 100644 +--- a/v2.0/src/nss_crypto_ctrl.c ++++ b/v2.0/src/nss_crypto_ctrl.c +@@ -38,7 +38,13 @@ + #include + #include + #include ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 11, 0) + #include ++#else ++#include ++#include ++#endif + #include + #include + #include +diff --git a/v2.0/src/nss_crypto_hlos.h b/v2.0/src/nss_crypto_hlos.h +index e827f4f..5565472 100644 +--- a/v2.0/src/nss_crypto_hlos.h ++++ b/v2.0/src/nss_crypto_hlos.h +@@ -58,7 +58,11 @@ + #if LINUX_VERSION_CODE < KERNEL_VERSION(5, 8, 0) + #include + #endif ++#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 11, 0) + #include ++#else ++#include ++#endif + #include + #include + #include +-- +2.35.1 + diff --git a/qca/qca-nss-dp/Makefile b/qca/qca-nss-dp/Makefile new file mode 100644 index 000000000..17627674a --- /dev/null +++ b/qca/qca-nss-dp/Makefile @@ -0,0 +1,56 @@ +include $(TOPDIR)/rules.mk + +PKG_NAME:=qca-nss-dp +PKG_RELEASE:=$(AUTORELEASE) + +PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/nss-dp.git +PKG_SOURCE_PROTO:=git +PKG_SOURCE_DATE:=2022-04-30 +PKG_SOURCE_VERSION:=72e9ec4187414461cbcf6ccff100e8b5ebe5f40b +PKG_MIRROR_HASH:=805f16e59c75511132922f97740ebf6bf953845b0bbfd2089c4615456893bb37 + +PKG_BUILD_PARALLEL:=1 + +include $(INCLUDE_DIR)/kernel.mk +include $(INCLUDE_DIR)/package.mk + +define KernelPackage/qca-nss-dp + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + DEPENDS:=@(TARGET_ipq807x||TARGET_ipq60xx) +kmod-qca-ssdk-nohnat + TITLE:=Kernel driver for NSS data plane + FILES:=$(PKG_BUILD_DIR)/qca-nss-dp.ko + AUTOLOAD:=$(call AutoLoad,31,qca-nss-dp,1) +endef + +define KernelPackage/qca-nss-dp/Description +This package contains a NSS data plane driver for QCA chipset +endef + +define Build/InstallDev + mkdir -p $(1)/usr/include/qca-nss-dp + $(CP) $(PKG_BUILD_DIR)/exports/* $(1)/usr/include/qca-nss-dp/ +endef + +EXTRA_CFLAGS+= \ + -I$(STAGING_DIR)/usr/include/qca-ssdk + +NSS_DP_HAL_DIR:=$(PKG_BUILD_DIR)/hal +define Build/Configure + $(LN) $(NSS_DP_HAL_DIR)/soc_ops/$(CONFIG_TARGET_BOARD)/nss_$(CONFIG_TARGET_BOARD).h \ + $(PKG_BUILD_DIR)/exports/nss_dp_arch.h +endef + +define Build/Compile + +$(MAKE) -C "$(LINUX_DIR)" \ + CROSS_COMPILE="$(TARGET_CROSS)" \ + ARCH="$(LINUX_KARCH)" \ + M="$(PKG_BUILD_DIR)" \ + EXTRA_CFLAGS="$(EXTRA_CFLAGS)" SoC="$(CONFIG_TARGET_BOARD)" \ + $(KERNEL_MAKE_FLAGS) \ + $(PKG_JOBS) \ + modules +endef + +$(eval $(call KernelPackage,qca-nss-dp)) diff --git a/qca/qca-nss-dp/patches/0001-edma_tx_rx-support-newer-kernels-time-stamping-API.patch b/qca/qca-nss-dp/patches/0001-edma_tx_rx-support-newer-kernels-time-stamping-API.patch new file mode 100644 index 000000000..1fed4ba8a --- /dev/null +++ b/qca/qca-nss-dp/patches/0001-edma_tx_rx-support-newer-kernels-time-stamping-API.patch @@ -0,0 +1,44 @@ +From 40979666b4371012405715ffa61ab5760fcdc6b3 Mon Sep 17 00:00:00 2001 +Message-Id: <40979666b4371012405715ffa61ab5760fcdc6b3.1620066716.git.baruch@tkos.co.il> +From: Baruch Siach +Date: Mon, 3 May 2021 20:07:36 +0300 +Subject: [PATCH 1/3] edma_tx_rx: support newer kernels time stamping API + +--- + hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +--- a/hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c ++++ b/hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c +@@ -227,10 +227,16 @@ void nss_phy_tstamp_rx_buf(__attribute__ + * set to the correct PTP class value by calling ptp_classify_raw + * in drv->rxtstamp function. + */ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 6, 0)) + if (ndev && ndev->phydev && ndev->phydev->drv && + ndev->phydev->drv->rxtstamp) + if(ndev->phydev->drv->rxtstamp(ndev->phydev, skb, 0)) + return; ++#else ++ if (ndev && phy_has_rxtstamp(ndev->phydev)) ++ if (phy_rxtstamp(ndev->phydev, skb, 0)) ++ return; ++#endif + + netif_receive_skb(skb); + } +@@ -248,9 +254,14 @@ void nss_phy_tstamp_tx_buf(struct net_de + * set to the correct PTP class value by calling ptp_classify_raw + * in the drv->txtstamp function. + */ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 6, 0)) + if (ndev && ndev->phydev && ndev->phydev->drv && + ndev->phydev->drv->txtstamp) + ndev->phydev->drv->txtstamp(ndev->phydev, skb, 0); ++#else ++ if (ndev && phy_has_txtstamp(ndev->phydev)) ++ phy_rxtstamp(ndev->phydev, skb, 0); ++#endif + } + EXPORT_SYMBOL(nss_phy_tstamp_tx_buf); + diff --git a/qca/qca-nss-dp/patches/0002-nss_dp_main-make-phy-mode-code-compatible-with-newer.patch b/qca/qca-nss-dp/patches/0002-nss_dp_main-make-phy-mode-code-compatible-with-newer.patch new file mode 100644 index 000000000..04adad86f --- /dev/null +++ b/qca/qca-nss-dp/patches/0002-nss_dp_main-make-phy-mode-code-compatible-with-newer.patch @@ -0,0 +1,48 @@ +From cef7873a2d77df13ee702d902ed4e06b2248904b Mon Sep 17 00:00:00 2001 +Message-Id: +In-Reply-To: <40979666b4371012405715ffa61ab5760fcdc6b3.1620066716.git.baruch@tkos.co.il> +References: <40979666b4371012405715ffa61ab5760fcdc6b3.1620066716.git.baruch@tkos.co.il> +From: Baruch Siach +Date: Mon, 3 May 2021 20:17:22 +0300 +Subject: [PATCH 2/3] nss_dp_main: make phy mode code compatible with newer + kernels + +--- + include/nss_dp_dev.h | 4 ++-- + nss_dp_main.c | 4 ++++ + 2 files changed, 6 insertions(+), 2 deletions(-) + +--- a/include/nss_dp_dev.h ++++ b/include/nss_dp_dev.h +@@ -22,7 +22,7 @@ + #include + #include + #include +-#include ++#include + #include + + #include "nss_dp_api_if.h" +@@ -99,7 +99,7 @@ struct nss_dp_dev { + /* Phy related stuff */ + struct phy_device *phydev; /* Phy device */ + struct mii_bus *miibus; /* MII bus */ +- uint32_t phy_mii_type; /* RGMII/SGMII/QSGMII */ ++ phy_interface_t phy_mii_type; /* RGMII/SGMII/QSGMII */ + uint32_t phy_mdio_addr; /* Mdio address */ + bool link_poll; /* Link polling enable? */ + uint32_t forced_speed; /* Forced speed? */ +--- a/nss_dp_main.c ++++ b/nss_dp_main.c +@@ -584,7 +584,11 @@ static int32_t nss_dp_of_get_pdata(struc + hal_pdata->netdev = netdev; + hal_pdata->macid = dp_priv->macid; + ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 5, 0)) + dp_priv->phy_mii_type = of_get_phy_mode(np); ++#else ++ of_get_phy_mode(np, &dp_priv->phy_mii_type); ++#endif + dp_priv->link_poll = of_property_read_bool(np, "qcom,link-poll"); + if (of_property_read_u32(np, "qcom,phy-mdio-addr", + &dp_priv->phy_mdio_addr) && dp_priv->link_poll) { diff --git a/qca/qca-nss-dp/patches/0003-Drop-_nocache-variants-of-ioremap.patch b/qca/qca-nss-dp/patches/0003-Drop-_nocache-variants-of-ioremap.patch new file mode 100644 index 000000000..18bd85c8c --- /dev/null +++ b/qca/qca-nss-dp/patches/0003-Drop-_nocache-variants-of-ioremap.patch @@ -0,0 +1,48 @@ +From c8c52512ff48bee578901c381a42f027e79eadf9 Mon Sep 17 00:00:00 2001 +Message-Id: +In-Reply-To: <40979666b4371012405715ffa61ab5760fcdc6b3.1620066716.git.baruch@tkos.co.il> +References: <40979666b4371012405715ffa61ab5760fcdc6b3.1620066716.git.baruch@tkos.co.il> +From: Baruch Siach +Date: Mon, 3 May 2021 20:20:29 +0300 +Subject: [PATCH 3/3] Drop _nocache variants of ioremap() + +Recent kernels removed them. +--- + hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c | 2 +- + hal/gmac_ops/qcom/qcom_if.c | 2 +- + hal/gmac_ops/syn/xgmac/syn_if.c | 2 +- + 3 files changed, 3 insertions(+), 3 deletions(-) + +--- a/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c ++++ b/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c +@@ -279,7 +279,7 @@ int edma_init(void) + /* + * Remap register resource + */ +- edma_hw.reg_base = ioremap_nocache((edma_hw.reg_resource)->start, ++ edma_hw.reg_base = ioremap((edma_hw.reg_resource)->start, + resource_size(edma_hw.reg_resource)); + if (!edma_hw.reg_base) { + pr_warn("Unable to remap EDMA register memory.\n"); +--- a/hal/gmac_ops/qcom/qcom_if.c ++++ b/hal/gmac_ops/qcom/qcom_if.c +@@ -418,7 +418,7 @@ static void *qcom_init(struct nss_gmac_h + qhd->nghd.mac_id = gmacpdata->macid; + + /* Populate the mac base addresses */ +- qhd->nghd.mac_base = devm_ioremap_nocache(&dp_priv->pdev->dev, ++ qhd->nghd.mac_base = devm_ioremap(&dp_priv->pdev->dev, + res->start, resource_size(res)); + if (!qhd->nghd.mac_base) { + netdev_dbg(ndev, "ioremap fail.\n"); +--- a/hal/gmac_ops/syn/xgmac/syn_if.c ++++ b/hal/gmac_ops/syn/xgmac/syn_if.c +@@ -432,7 +432,7 @@ static void *syn_init(struct nss_gmac_ha + + /* Populate the mac base addresses */ + shd->nghd.mac_base = +- devm_ioremap_nocache(&dp_priv->pdev->dev, res->start, ++ devm_ioremap(&dp_priv->pdev->dev, res->start, + resource_size(res)); + if (!shd->nghd.mac_base) { + netdev_dbg(ndev, "ioremap fail.\n"); diff --git a/qca/qca-nss-dp/patches/0004-EDMA-Fix-NAPI-packet-counting.patch b/qca/qca-nss-dp/patches/0004-EDMA-Fix-NAPI-packet-counting.patch new file mode 100644 index 000000000..f7653729a --- /dev/null +++ b/qca/qca-nss-dp/patches/0004-EDMA-Fix-NAPI-packet-counting.patch @@ -0,0 +1,31 @@ +From d74920e2a7c413ef40eed72f9cf287cf6fbd5fb8 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Thu, 20 May 2021 14:56:46 +0200 +Subject: [PATCH 1/2] EDMA: Fix NAPI packet counting + +There is a bug in the NAPI packet counting that will +cause NAPI over budget warnings. + +Signed-off-by: Baruch Siach +Signed-off-by: Robert Marko +--- + hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c ++++ b/hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c +@@ -459,12 +459,12 @@ int edma_napi(struct napi_struct *napi, + + for (i = 0; i < ehw->txcmpl_rings; i++) { + txcmpl_ring = &ehw->txcmpl_ring[i]; +- work_done += edma_clean_tx(ehw, txcmpl_ring); ++ edma_clean_tx(ehw, txcmpl_ring); + } + + for (i = 0; i < ehw->rxfill_rings; i++) { + rxfill_ring = &ehw->rxfill_ring[i]; +- work_done += edma_alloc_rx_buffer(ehw, rxfill_ring); ++ edma_alloc_rx_buffer(ehw, rxfill_ring); + } + + /* diff --git a/qca/qca-nss-dp/patches/0005-EDMA-Use-NAPI_POLL_WEIGHT-as-NAPI-weight.patch b/qca/qca-nss-dp/patches/0005-EDMA-Use-NAPI_POLL_WEIGHT-as-NAPI-weight.patch new file mode 100644 index 000000000..9c22fa790 --- /dev/null +++ b/qca/qca-nss-dp/patches/0005-EDMA-Use-NAPI_POLL_WEIGHT-as-NAPI-weight.patch @@ -0,0 +1,41 @@ +From 44a30d94abcbb10aacc21db29be212518a6b1bf7 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Thu, 20 May 2021 14:57:46 +0200 +Subject: [PATCH] EDMA: Use NAPI_POLL_WEIGHT as NAPI weight + +Currently a weight of 100 is used by the EDMA, according +to upstream max of 64 should be used and that is used for +almost any driver. + +They also introduced NAPI_POLL_WEIGHT define which equals +to 64. + +So use NAPI_POLL_WEIGHT as the weight. + +Signed-off-by: Robert Marko +--- + hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c | 2 +- + hal/dp_ops/edma_dp/edma_v1/edma_data_plane.h | 1 - + 2 files changed, 1 insertion(+), 2 deletions(-) + +--- a/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c ++++ b/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c +@@ -837,7 +837,7 @@ static int edma_register_netdevice(struc + */ + if (!edma_hw.napi_added) { + netif_napi_add(netdev, &edma_hw.napi, edma_napi, +- EDMA_NAPI_WORK); ++ NAPI_POLL_WEIGHT); + /* + * Register the interrupt handlers and enable interrupts + */ +--- a/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.h ++++ b/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.h +@@ -26,7 +26,6 @@ + #define EDMA_RX_PREHDR_SIZE (sizeof(struct edma_rx_preheader)) + #define EDMA_TX_PREHDR_SIZE (sizeof(struct edma_tx_preheader)) + #define EDMA_RING_SIZE 128 +-#define EDMA_NAPI_WORK 100 + #define EDMA_START_GMACS NSS_DP_HAL_START_IFNUM + #define EDMA_MAX_GMACS NSS_DP_HAL_MAX_PORTS + #define EDMA_TX_PKT_MIN_SIZE 33 /* IPQ807x EDMA needs a minimum packet size of 33 bytes */ diff --git a/qca/qca-nss-dp/patches/0006-NSS-DP-fix-of_get_mac_address.patch b/qca/qca-nss-dp/patches/0006-NSS-DP-fix-of_get_mac_address.patch new file mode 100644 index 000000000..1d7b49129 --- /dev/null +++ b/qca/qca-nss-dp/patches/0006-NSS-DP-fix-of_get_mac_address.patch @@ -0,0 +1,46 @@ +From cadeb62a42296563141d6954eec58e34ef86778d Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Fri, 13 Aug 2021 20:12:08 +0200 +Subject: [PATCH] NSS-DP: fix of_get_mac_address() + +Recently OpenWrt backported the updated of_get_mac_address() +function which returns and error code instead. + +So, patch the SSDK to use it and fix the compilation error. + +Signed-off-by: Robert Marko +--- + nss_dp_main.c | 13 ++++--------- + 1 file changed, 4 insertions(+), 9 deletions(-) + +--- a/nss_dp_main.c ++++ b/nss_dp_main.c +@@ -555,9 +555,10 @@ static int32_t nss_dp_of_get_pdata(struc + struct net_device *netdev, + struct nss_gmac_hal_platform_data *hal_pdata) + { +- uint8_t *maddr; ++ u8 maddr[ETH_ALEN]; + struct nss_dp_dev *dp_priv; + struct resource memres_devtree = {0}; ++ int ret; + + dp_priv = netdev_priv(netdev); + +@@ -600,14 +601,8 @@ static int32_t nss_dp_of_get_pdata(struc + of_property_read_u32(np, "qcom,forced-speed", &dp_priv->forced_speed); + of_property_read_u32(np, "qcom,forced-duplex", &dp_priv->forced_duplex); + +- maddr = (uint8_t *)of_get_mac_address(np); +-#if (LINUX_VERSION_CODE > KERNEL_VERSION(5, 4, 0)) +- if (IS_ERR((void *)maddr)) { +- maddr = NULL; +- } +-#endif +- +- if (maddr && is_valid_ether_addr(maddr)) { ++ ret = of_get_mac_address(np, maddr); ++ if (!ret && is_valid_ether_addr(maddr)) { + ether_addr_copy(netdev->dev_addr, maddr); + } else { + random_ether_addr(netdev->dev_addr); diff --git a/qca/qca-nss-dp/patches/0007-NSS-DP-implement-ethernet-IOCTL-s.patch b/qca/qca-nss-dp/patches/0007-NSS-DP-implement-ethernet-IOCTL-s.patch new file mode 100644 index 000000000..824f18634 --- /dev/null +++ b/qca/qca-nss-dp/patches/0007-NSS-DP-implement-ethernet-IOCTL-s.patch @@ -0,0 +1,29 @@ +From 5da62ba19f554bf437752a44360fb5ae9f1a7f5e Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Tue, 8 Mar 2022 10:48:32 +0100 +Subject: [PATCH] NSS-DP: implement ethernet IOCTL-s + +Since kernel 5.15 ethernet/PHY related IOCTL-s have been split from the +generic IOCTL netdev op. +So, implement the new op instead of the generic one which is considered +for private IOCTL-s only now for 5.15+. + +Signed-off-by: Robert Marko +--- + nss_dp_main.c | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/nss_dp_main.c ++++ b/nss_dp_main.c +@@ -532,7 +532,11 @@ static const struct net_device_ops nss_d + .ndo_set_mac_address = nss_dp_set_mac_address, + .ndo_validate_addr = eth_validate_addr, + .ndo_change_mtu = nss_dp_change_mtu, ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 15, 0)) + .ndo_do_ioctl = nss_dp_do_ioctl, ++#else ++ .ndo_eth_ioctl = nss_dp_do_ioctl, ++#endif + + #if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 5, 0)) + .ndo_bridge_setlink = switchdev_port_bridge_setlink, diff --git a/qca/qca-nss-dp/patches/0008-switchdev-remove-the-transaction-structure.patch b/qca/qca-nss-dp/patches/0008-switchdev-remove-the-transaction-structure.patch new file mode 100644 index 000000000..220be961a --- /dev/null +++ b/qca/qca-nss-dp/patches/0008-switchdev-remove-the-transaction-structure.patch @@ -0,0 +1,48 @@ +From c9afdcdd2642485a6476906be9da2e811090fc7a Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Fri, 18 Mar 2022 18:06:03 +0100 +Subject: [PATCH] switchdev: remove the transaction structure + +Since 5.12 there is no transaction structure anymore, so drop it for +5.12 and newer. + +Signed-off-by: Robert Marko +--- + nss_dp_switchdev.c | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +--- a/nss_dp_switchdev.c ++++ b/nss_dp_switchdev.c +@@ -279,13 +279,19 @@ void nss_dp_switchdev_setup(struct net_d + * Sets attributes + */ + static int nss_dp_port_attr_set(struct net_device *dev, ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 12, 0)) + const struct switchdev_attr *attr, + struct switchdev_trans *trans) ++#else ++ const struct switchdev_attr *attr) ++#endif + { + struct nss_dp_dev *dp_priv = (struct nss_dp_dev *)netdev_priv(dev); + ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 12, 0)) + if (switchdev_trans_ph_prepare(trans)) + return 0; ++#endif + + switch (attr->id) { + case SWITCHDEV_ATTR_ID_PORT_BRIDGE_FLAGS: +@@ -309,8 +315,12 @@ static int nss_dp_switchdev_port_attr_se + { + int err; + ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 12, 0)) + err = nss_dp_port_attr_set(netdev, port_attr_info->attr, + port_attr_info->trans); ++#else ++ err = nss_dp_port_attr_set(netdev, port_attr_info->attr); ++#endif + + port_attr_info->handled = true; + return notifier_from_errno(err); diff --git a/qca/qca-nss-dp/patches/0009-switchdev-use-new-switchdev-flags.patch b/qca/qca-nss-dp/patches/0009-switchdev-use-new-switchdev-flags.patch new file mode 100644 index 000000000..ecc84c174 --- /dev/null +++ b/qca/qca-nss-dp/patches/0009-switchdev-use-new-switchdev-flags.patch @@ -0,0 +1,51 @@ +From f95868d54301c0f54e968ec9d978c9caa02ee425 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Fri, 18 Mar 2022 18:24:18 +0100 +Subject: [PATCH] switchdev: use new switchdev flags + +Since kernel 5.12 switched utilizes a new way of setting the flags by +using a dedicated structure with flags and mask. + +So fix using kernels 5.12 and later. + +Signed-off-by: Robert Marko +--- + include/nss_dp_dev.h | 7 +++++++ + nss_dp_switchdev.c | 2 +- + 2 files changed, 8 insertions(+), 1 deletion(-) + +--- a/include/nss_dp_dev.h ++++ b/include/nss_dp_dev.h +@@ -24,6 +24,9 @@ + #include + #include + #include ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 12, 0)) ++#include ++#endif + + #include "nss_dp_api_if.h" + #include "nss_dp_hal_if.h" +@@ -126,7 +129,11 @@ struct nss_dp_dev { + /* switchdev related attributes */ + #ifdef CONFIG_NET_SWITCHDEV + u8 stp_state; /* STP state of this physical port */ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 12, 0)) + unsigned long brport_flags; /* bridge port flags */ ++#else ++ struct switchdev_brport_flags brport_flags; /* bridge port flags */ ++#endif + #endif + uint32_t rx_page_mode; /* page mode for Rx processing */ + uint32_t rx_jumbo_mru; /* Jumbo mru value for Rx processing */ +--- a/nss_dp_switchdev.c ++++ b/nss_dp_switchdev.c +@@ -296,7 +296,7 @@ static int nss_dp_port_attr_set(struct n + switch (attr->id) { + case SWITCHDEV_ATTR_ID_PORT_BRIDGE_FLAGS: + dp_priv->brport_flags = attr->u.brport_flags; +- netdev_dbg(dev, "set brport_flags %lu\n", attr->u.brport_flags); ++ netdev_dbg(dev, "set brport_flags %lu\n", attr->u.brport_flags.val); + return 0; + case SWITCHDEV_ATTR_ID_PORT_STP_STATE: + return nss_dp_stp_state_set(dp_priv, attr->u.stp_state); diff --git a/qca/qca-nss-dp/patches/0010-switchdev-fix-FDB-roaming.patch b/qca/qca-nss-dp/patches/0010-switchdev-fix-FDB-roaming.patch new file mode 100644 index 000000000..19395ac42 --- /dev/null +++ b/qca/qca-nss-dp/patches/0010-switchdev-fix-FDB-roaming.patch @@ -0,0 +1,110 @@ +From d16102cad769f430144ca8094d928762b445e9b0 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Fri, 18 Mar 2022 22:02:01 +0100 +Subject: [PATCH] switchdev: fix FDB roaming + +Try and solve the roaming issue by trying to replicate what NSS bridge +module is doing, but by utilizing switchdev FDB notifiers instead of +adding new notifiers to the bridge code. + +We register a new non-blocking switchdev notifier and simply wait for +notification, and then process the SWITCHDEV_FDB_DEL_TO_DEVICE +notifications. + +Those tell us that a certain FDB entry should be removed, then a VSI ID +is fetched for the physical PPE port and using that VSI ID and the +notification provided MAC adress existing FDB entry gets removed. + +Signed-off-by: Robert Marko +--- + nss_dp_switchdev.c | 61 ++++++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 61 insertions(+) + +--- a/nss_dp_switchdev.c ++++ b/nss_dp_switchdev.c +@@ -24,6 +24,8 @@ + #include "nss_dp_dev.h" + #include "fal/fal_stp.h" + #include "fal/fal_ctrlpkt.h" ++#include "fal/fal_fdb.h" ++#include "ref/ref_vsi.h" + + #define NSS_DP_SWITCH_ID 0 + #define NSS_DP_SW_ETHTYPE_PID 0 /* PPE ethtype profile ID for slow protocols */ +@@ -348,10 +350,64 @@ static int nss_dp_switchdev_event(struct + return NOTIFY_DONE; + } + ++static int nss_dp_switchdev_fdb_del_event(struct net_device *netdev, ++ struct switchdev_notifier_fdb_info *fdb_info) ++{ ++ struct nss_dp_dev *dp_priv = (struct nss_dp_dev *)netdev_priv(netdev); ++ fal_fdb_entry_t entry; ++ a_uint32_t vsi_id; ++ sw_error_t rv; ++ ++ netdev_dbg(netdev, "FDB DEL %pM port %d\n", fdb_info->addr, dp_priv->macid); ++ ++ rv = ppe_port_vsi_get(NSS_DP_SWITCH_ID, dp_priv->macid, &vsi_id); ++ if (rv) { ++ netdev_err(netdev, "cannot get VSI ID for port %d\n", dp_priv->macid); ++ return notifier_from_errno(rv); ++ } ++ ++ memset(&entry, 0, sizeof(entry)); ++ memcpy(&entry.addr, fdb_info->addr, ETH_ALEN); ++ entry.fid = vsi_id; ++ ++ rv = fal_fdb_entry_del_bymac(NSS_DP_SWITCH_ID, &entry); ++ if (rv) { ++ netdev_err(netdev, "FDB entry delete failed with MAC %pM and fid %d\n", ++ &entry.addr, entry.fid); ++ return notifier_from_errno(rv); ++ } ++ ++ return notifier_from_errno(rv); ++} ++ ++static int nss_dp_fdb_switchdev_event(struct notifier_block *nb, ++ unsigned long event, void *ptr) ++{ ++ struct net_device *dev = switchdev_notifier_info_to_dev(ptr); ++ ++ /* ++ * Handle switchdev event only for physical devices ++ */ ++ if (!nss_dp_is_phy_dev(dev)) { ++ return NOTIFY_DONE; ++ } ++ ++ switch (event) { ++ case SWITCHDEV_FDB_DEL_TO_DEVICE: ++ return nss_dp_switchdev_fdb_del_event(dev, ptr); ++ } ++ ++ return NOTIFY_DONE; ++} ++ + static struct notifier_block nss_dp_switchdev_notifier = { + .notifier_call = nss_dp_switchdev_event, + }; + ++static struct notifier_block nss_dp_switchdev_fdb_notifier = { ++ .notifier_call = nss_dp_fdb_switchdev_event, ++}; ++ + static bool switch_init_done; + + /* +@@ -366,6 +422,11 @@ void nss_dp_switchdev_setup(struct net_d + return; + } + ++ err = register_switchdev_notifier(&nss_dp_switchdev_fdb_notifier); ++ if (err) { ++ netdev_dbg(dev, "%px:Failed to register switchdev FDB notifier\n", dev); ++ } ++ + err = register_switchdev_blocking_notifier(&nss_dp_switchdev_notifier); + if (err) { + netdev_dbg(dev, "%px:Failed to register switchdev notifier\n", dev); diff --git a/qca/qca-nss-dp/patches/0011-treewide-fix-confusing-printing-of-registered-netdev.patch b/qca/qca-nss-dp/patches/0011-treewide-fix-confusing-printing-of-registered-netdev.patch new file mode 100644 index 000000000..63fea1982 --- /dev/null +++ b/qca/qca-nss-dp/patches/0011-treewide-fix-confusing-printing-of-registered-netdev.patch @@ -0,0 +1,48 @@ +From 7e4ae2d6285095794d73d2f2ce61404f61d4e633 Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Tue, 17 May 2022 15:55:36 +0200 +Subject: [PATCH 11/11] treewide: fix confusing printing of registered netdev + +Net core implementation changed and now printing the netdev name cause +confusing printing if done before register_netdev. Move the old printing +to dbg and add an additional info log right after register_netdev to +give the user some info on correct nss-dp probe. + +Signed-off-by: Ansuel Smith +--- + hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c | 4 ++-- + nss_dp_main.c | 3 +++ + 2 files changed, 5 insertions(+), 2 deletions(-) + +diff --git a/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c b/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c +index 0af39c2..1d748db 100644 +--- a/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c ++++ b/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c +@@ -822,8 +822,8 @@ static int edma_register_netdevice(struct net_device *netdev, uint32_t macid) + return -EINVAL; + } + +- netdev_info(netdev, "nss_dp_edma: Registering netdev %s(qcom-id:%d) with EDMA\n", +- netdev->name, macid); ++ netdev_dbg(netdev, "nss_dp_edma: Registering netdev %s(qcom-id:%d) with EDMA\n", ++ netdev->name, macid); + + /* + * We expect 'macid' to correspond to ports numbers on +diff --git a/nss_dp_main.c b/nss_dp_main.c +index c0ae9d6..441c300 100644 +--- a/nss_dp_main.c ++++ b/nss_dp_main.c +@@ -875,6 +875,9 @@ static int32_t nss_dp_probe(struct platform_device *pdev) + goto phy_setup_fail; + } + ++ netdev_info(netdev, "Registered netdev %s(qcom-id:%d)\n", ++ netdev->name, port_id); ++ + dp_global_ctx.nss_dp[dp_priv->macid - 1] = dp_priv; + dp_global_ctx.slowproto_acl_bm = 0; + +-- +2.34.1 + diff --git a/qca/qca-nss-dp/patches/0012-gmac-syn-xgmac-silence-debug-log-on-probe.patch b/qca/qca-nss-dp/patches/0012-gmac-syn-xgmac-silence-debug-log-on-probe.patch new file mode 100644 index 000000000..2bc576ccb --- /dev/null +++ b/qca/qca-nss-dp/patches/0012-gmac-syn-xgmac-silence-debug-log-on-probe.patch @@ -0,0 +1,28 @@ +From fee52ef165e9fab2fca15492677082fd8e9e891f Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Thu, 19 May 2022 23:40:24 +0200 +Subject: [PATCH 12/12] gmac: syn: xgmac: silence debug log on probe + +Silence debug log set as info in xgmac port probe. + +Signed-off-by: Ansuel Smith +--- + hal/gmac_ops/syn/xgmac/syn_if.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/hal/gmac_ops/syn/xgmac/syn_if.c b/hal/gmac_ops/syn/xgmac/syn_if.c +index 1152f5c..bc2880d 100644 +--- a/hal/gmac_ops/syn/xgmac/syn_if.c ++++ b/hal/gmac_ops/syn/xgmac/syn_if.c +@@ -445,7 +445,7 @@ static void *syn_init(struct nss_gmac_hal_platform_data *gmacpdata) + + spin_lock_init(&shd->nghd.slock); + +- netdev_info(ndev, "ioremap OK.Size 0x%x Ndev base 0x%lx macbase 0x%px\n", ++ netdev_dbg(ndev, "ioremap OK.Size 0x%x Ndev base 0x%lx macbase 0x%px\n", + gmacpdata->reg_len, + ndev->base_addr, + shd->nghd.mac_base); +-- +2.34.1 + diff --git a/qca/qca-nss-dp/patches/0013-nss_dp_main-Use-a-phy-handle-property-to-connect-to-.patch b/qca/qca-nss-dp/patches/0013-nss_dp_main-Use-a-phy-handle-property-to-connect-to-.patch new file mode 100644 index 000000000..ea6993d75 --- /dev/null +++ b/qca/qca-nss-dp/patches/0013-nss_dp_main-Use-a-phy-handle-property-to-connect-to-.patch @@ -0,0 +1,189 @@ +From 8293a26ca56ee2e9a88e4efb5dcc7f647803cd8c Mon Sep 17 00:00:00 2001 +From: Alexandru Gagniuc +Date: Sun, 5 Jun 2022 21:45:09 -0500 +Subject: [PATCH] nss_dp_main: Use a 'phy-handle' property to connect to the + PHY + +The original method of connecting a PHY to the ethernet controller +requires the "qcom,link-poll", and "qcom,phy-mdio-addr" devicetree +properties. This is redundant. The PHY node already contains the MDIO +address, and attaching a PHY implies "link-poll". + +Allow using a "phy-handle" property. Remove the following properties, +as they are no longer used: + * "qcom,link-poll" + * "qcom,phy-mdio-addr" + * "mdio-bus" + * "qcom,forced-speed" + * "qcom,forced-duplex" + +Signed-off-by: Alexandru Gagniuc +--- + include/nss_dp_dev.h | 5 +-- + nss_dp_main.c | 91 +++++--------------------------------------- + 2 files changed, 10 insertions(+), 86 deletions(-) + +diff --git a/include/nss_dp_dev.h b/include/nss_dp_dev.h +index 19b3e78..63a857a 100644 +--- a/include/nss_dp_dev.h ++++ b/include/nss_dp_dev.h +@@ -100,13 +100,10 @@ struct nss_dp_dev { + unsigned long drv_flags; /* Driver specific feature flags */ + + /* Phy related stuff */ ++ struct device_node *phy_node; + struct phy_device *phydev; /* Phy device */ + struct mii_bus *miibus; /* MII bus */ + phy_interface_t phy_mii_type; /* RGMII/SGMII/QSGMII */ +- uint32_t phy_mdio_addr; /* Mdio address */ +- bool link_poll; /* Link polling enable? */ +- uint32_t forced_speed; /* Forced speed? */ +- uint32_t forced_duplex; /* Forced duplex? */ + uint32_t link_state; /* Current link state */ + uint32_t pause; /* Current flow control settings */ + +diff --git a/nss_dp_main.c b/nss_dp_main.c +index 441c300..a1e8627 100644 +--- a/nss_dp_main.c ++++ b/nss_dp_main.c +@@ -399,7 +399,7 @@ static int nss_dp_open(struct net_device *netdev) + + netif_start_queue(netdev); + +- if (!dp_priv->link_poll) { ++ if (!dp_priv->phydev) { + /* Notify data plane link is up */ + if (dp_priv->data_plane_ops->link_state(dp_priv->dpc, 1)) { + netdev_dbg(netdev, "Data plane set link failed\n"); +@@ -576,6 +576,8 @@ static int32_t nss_dp_of_get_pdata(struct device_node *np, + return -EFAULT; + } + ++ dp_priv->phy_node = of_parse_phandle(np, "phy-handle", 0); ++ + if (of_property_read_u32(np, "qcom,mactype", &hal_pdata->mactype)) { + pr_err("%s: error reading mactype\n", np->name); + return -EFAULT; +@@ -594,16 +596,6 @@ static int32_t nss_dp_of_get_pdata(struct device_node *np, + #else + of_get_phy_mode(np, &dp_priv->phy_mii_type); + #endif +- dp_priv->link_poll = of_property_read_bool(np, "qcom,link-poll"); +- if (of_property_read_u32(np, "qcom,phy-mdio-addr", +- &dp_priv->phy_mdio_addr) && dp_priv->link_poll) { +- pr_err("%s: mdio addr required if link polling is enabled\n", +- np->name); +- return -EFAULT; +- } +- +- of_property_read_u32(np, "qcom,forced-speed", &dp_priv->forced_speed); +- of_property_read_u32(np, "qcom,forced-duplex", &dp_priv->forced_duplex); + + ret = of_get_mac_address(np, maddr); + if (!ret && is_valid_ether_addr(maddr)) { +@@ -636,50 +628,6 @@ static int32_t nss_dp_of_get_pdata(struct device_node *np, + return 0; + } + +-/* +- * nss_dp_mdio_attach() +- */ +-static struct mii_bus *nss_dp_mdio_attach(struct platform_device *pdev) +-{ +- struct device_node *mdio_node; +- struct platform_device *mdio_plat; +- struct ipq40xx_mdio_data *mdio_data; +- +- /* +- * Find mii_bus using "mdio-bus" handle. +- */ +- mdio_node = of_parse_phandle(pdev->dev.of_node, "mdio-bus", 0); +- if (mdio_node) { +- return of_mdio_find_bus(mdio_node); +- } +- +- mdio_node = of_find_compatible_node(NULL, NULL, "qcom,qca-mdio"); +- if (!mdio_node) { +- mdio_node = of_find_compatible_node(NULL, NULL, +- "qcom,ipq40xx-mdio"); +- if (!mdio_node) { +- dev_err(&pdev->dev, "cannot find mdio node by phandle\n"); +- return NULL; +- } +- } +- +- mdio_plat = of_find_device_by_node(mdio_node); +- if (!mdio_plat) { +- dev_err(&pdev->dev, "cannot find platform device from mdio node\n"); +- of_node_put(mdio_node); +- return NULL; +- } +- +- mdio_data = dev_get_drvdata(&mdio_plat->dev); +- if (!mdio_data) { +- dev_err(&pdev->dev, "cannot get mii bus reference from device data\n"); +- of_node_put(mdio_node); +- return NULL; +- } +- +- return mdio_data->mii_bus; +-} +- + #ifdef CONFIG_NET_SWITCHDEV + /* + * nss_dp_is_phy_dev() +@@ -738,7 +686,6 @@ static int32_t nss_dp_probe(struct platform_device *pdev) + struct device_node *np = pdev->dev.of_node; + struct nss_gmac_hal_platform_data gmac_hal_pdata; + int32_t ret = 0; +- uint8_t phy_id[MII_BUS_ID_SIZE + 3]; + #if defined(NSS_DP_PPE_SUPPORT) + uint32_t vsi_id; + fal_port_t port_id; +@@ -813,37 +760,17 @@ static int32_t nss_dp_probe(struct platform_device *pdev) + + dp_priv->drv_flags |= NSS_DP_PRIV_FLAG(INIT_DONE); + +- if (dp_priv->link_poll) { +- dp_priv->miibus = nss_dp_mdio_attach(pdev); +- if (!dp_priv->miibus) { +- netdev_dbg(netdev, "failed to find miibus\n"); +- goto phy_setup_fail; +- } +- snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, +- dp_priv->miibus->id, dp_priv->phy_mdio_addr); +- ++ if (dp_priv->phy_node) { + SET_NETDEV_DEV(netdev, &pdev->dev); +- +- dp_priv->phydev = phy_connect(netdev, phy_id, +- &nss_dp_adjust_link, +- dp_priv->phy_mii_type); ++ dp_priv->phydev = of_phy_connect(netdev, dp_priv->phy_node, ++ &nss_dp_adjust_link, 0, ++ dp_priv->phy_mii_type); + if (IS_ERR(dp_priv->phydev)) { +- netdev_dbg(netdev, "failed to connect to phy device\n"); ++ dev_err(&pdev->dev, "Could not attach to PHY\n"); + goto phy_setup_fail; + } + +-#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 5, 0)) +- dp_priv->phydev->advertising |= +- (ADVERTISED_Pause | ADVERTISED_Asym_Pause); +- dp_priv->phydev->supported |= +- (SUPPORTED_Pause | SUPPORTED_Asym_Pause); +-#else +- linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, dp_priv->phydev->advertising); +- linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, dp_priv->phydev->advertising); +- +- linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, dp_priv->phydev->supported); +- linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, dp_priv->phydev->supported); +-#endif ++ phy_attached_info(dp_priv->phydev); + } + + #if defined(NSS_DP_PPE_SUPPORT) +-- +2.36.1 + diff --git a/qca/qca-nss-dp/patches/0014-nss-dp-edma-v1-switch-to-napi_gro_receive.patch b/qca/qca-nss-dp/patches/0014-nss-dp-edma-v1-switch-to-napi_gro_receive.patch new file mode 100644 index 000000000..3a437bd37 --- /dev/null +++ b/qca/qca-nss-dp/patches/0014-nss-dp-edma-v1-switch-to-napi_gro_receive.patch @@ -0,0 +1,46 @@ +From 57b521e876986844dfe34457f39c62dc8100424d Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Thu, 23 Jun 2022 14:18:50 +0200 +Subject: [PATCH] nss-dp: edma-v1: switch to napi_gro_receive + +Utilize napi_gro_receive instead of plain netif_receive_skb on EDMA v1. +It provides significant performance improvements when testing with iperf3. + +Signed-off-by: Robert Marko +--- + Makefile | 2 +- + hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c | 4 ++++ + 2 files changed, 5 insertions(+), 1 deletion(-) + +diff --git a/Makefile b/Makefile +index 8e81317..dcfa8ca 100644 +--- a/Makefile ++++ b/Makefile +@@ -25,7 +25,7 @@ qca-nss-dp-objs += hal/dp_ops/edma_dp/edma_v1/edma_cfg.o \ + hal/gmac_ops/qcom/qcom_if.o \ + hal/gmac_ops/syn/xgmac/syn_if.o + NSS_DP_INCLUDE += -I$(obj)/hal/dp_ops/edma_dp/edma_v1/include +-ccflags-y += -DNSS_DP_PPE_SUPPORT ++ccflags-y += -DNSS_DP_PPE_SUPPORT -DNSS_DP_ENABLE_NAPI_GRO + endif + + ifeq ($(SoC),$(filter $(SoC),ipq807x)) +diff --git a/hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c b/hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c +index 5780a30..6ee1451 100644 +--- a/hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c ++++ b/hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c +@@ -411,7 +411,11 @@ static uint32_t edma_clean_rx(struct edma_hw *ehw, + NSS_PTP_EVENT_SERVICE_CODE)) + nss_phy_tstamp_rx_buf(ndev, skb); + else ++#if defined(NSS_DP_ENABLE_NAPI_GRO) ++ napi_gro_receive(&ehw->napi, skb); ++#else + netif_receive_skb(skb); ++#endif + + next_rx_desc: + /* +-- +2.36.1 + diff --git a/qca/qca-nss-drv/Makefile b/qca/qca-nss-drv/Makefile new file mode 100644 index 000000000..92616caaa --- /dev/null +++ b/qca/qca-nss-drv/Makefile @@ -0,0 +1,129 @@ +include $(TOPDIR)/rules.mk + +PKG_NAME:=qca-nss-drv +PKG_RELEASE:=$(AUTORELEASE) + +PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/nss-drv.git +PKG_SOURCE_PROTO:=git +PKG_SOURCE_DATE:=2022-03-07 +PKG_SOURCE_VERSION:=397c88cf184e0eb011dd44ad82c2dfae60ece1b4 +PKG_MIRROR_HASH:=a3bea305d85fcec3d77f9b40d06a71b65ccf3d8b98018d9c8c23d6ad95e6aedc + +PKG_BUILD_PARALLEL:=1 + +include $(INCLUDE_DIR)/kernel.mk +include $(INCLUDE_DIR)/package.mk + +NSS_CLIENTS_DIR:=$(TOPDIR)/qca/src/qca-nss-clients + +define KernelPackage/qca-nss-drv + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + DEPENDS:=@(TARGET_ipq807x||TARGET_ipq60xx) +kmod-qca-nss-dp + TITLE:=Kernel driver for NSS (core driver) + FILES:=$(PKG_BUILD_DIR)/qca-nss-drv.ko + AUTOLOAD:=$(call AutoLoad,32,qca-nss-drv) +endef + +define KernelPackage/qca-nss-drv/install + $(INSTALL_DIR) $(1)/lib/debug + $(INSTALL_DIR) $(1)/etc/init.d + $(INSTALL_DIR) $(1)/etc/sysctl.d + $(INSTALL_DIR) $(1)/etc/hotplug.d/firmware + $(INSTALL_DIR) $(1)/etc/config + + $(INSTALL_BIN) ./files/qca-nss-drv.debug $(1)/lib/debug/qca-nss-drv + $(INSTALL_BIN) ./files/qca-nss-drv.init $(1)/etc/init.d/qca-nss-drv + $(INSTALL_BIN) ./files/qca-nss-drv.sysctl $(1)/etc/sysctl.d/qca-nss-drv.conf + $(INSTALL_BIN) ./files/qca-nss-drv.hotplug $(1)/etc/hotplug.d/firmware/10-qca-nss-fw + $(INSTALL_BIN) ./files/qca-nss-drv.conf $(1)/etc/config/nss + +endef + +define KernelPackage/qca-nss-drv/Description +This package contains a NSS driver for QCA chipset +endef + +define Build/InstallDev + mkdir -p $(1)/usr/include/qca-nss-drv + $(CP) $(PKG_BUILD_DIR)/exports/* $(1)/usr/include/qca-nss-drv/ +endef + +EXTRA_CFLAGS+= -I$(STAGING_DIR)/usr/include/qca-nss-gmac \ + -I$(STAGING_DIR)/usr/include/qca-nss-dp \ + -I$(STAGING_DIR)/usr/include/qca-ssdk \ + -Wno-unused-variable + +ifneq (, $(findstring $(CONFIG_TARGET_BOARD), "ipq807x" "ipq60xx")) +EXTRA_CFLAGS+= -DNSS_MEM_PROFILE_MEDIUM +LOW_MEM_PROFILE_MAKE_OPTS=y +endif + +ifeq ($(CONFIG_KERNEL_SKB_FIXED_SIZE_2K),y) +EXTRA_CFLAGS+= -DNSS_SKB_FIXED_SIZE_2K +endif + +DRV_MAKE_OPTS:= +ifeq ($(LOW_MEM_PROFILE_MAKE_OPTS),y) +DRV_MAKE_OPTS+= \ + NSS_DRV_C2C_ENABLE=n \ + NSS_DRV_CAPWAP_ENABLE=n \ + NSS_DRV_CLMAP_ENABLE=n \ + NSS_DRV_CRYPTO_ENABLE=y \ + NSS_DRV_DTLS_ENABLE=n \ + NSS_DRV_GRE_ENABLE=n \ + NSS_DRV_GRE_REDIR_ENABLE=n \ + NSS_DRV_GRE_TUNNEL_ENABLE=n \ + NSS_DRV_IGS_ENABLE=n \ + NSS_DRV_IPSEC_ENABLE=n \ + NSS_DRV_LAG_ENABLE=n \ + NSS_DRV_L2TP_ENABLE=n \ + NSS_DRV_MAPT_ENABLE=n \ + NSS_DRV_OAM_ENABLE=n \ + NSS_DRV_PPTP_ENABLE=n \ + NSS_DRV_PORTID_ENABLE=n \ + NSS_DRV_PVXLAN_ENABLE=n \ + NSS_DRV_QRFS_ENABLE=n \ + NSS_DRV_QVPN_ENABLE=n \ + NSS_DRV_RMNET_ENABLE=n \ + NSS_DRV_SHAPER_ENABLE=n \ + NSS_DRV_SJACK_ENABLE=n \ + NSS_DRV_TLS_ENABLE=n \ + NSS_DRV_TRUSTSEC_ENABLE=n \ + NSS_DRV_TSTAMP_ENABLE=n \ + NSS_DRV_TUN6RD_ENABLE=n \ + NSS_DRV_TUNIPIP6_ENABLE=n \ + NSS_DRV_VXLAN_ENABLE=n \ + NSS_DRV_MATCH_ENABLE=n \ + NSS_DRV_MIRROR_ENABLE=n \ + NSS_DRV_PPPOE_ENABLE=n \ + NSS_DRV_VIRT_IF_ENABLE=n \ + NSS_DRV_VLAN_ENABLE=n \ + NSS_DRV_BRIDGE_ENABLE=n \ + NSS_DRV_WIFI_EXT_VDEV_ENABLE=n \ + NSS_DRV_WIFI_MESH_ENABLE=n +endif + +ifeq ($(CONFIG_TARGET_BOARD), "ipq807x") + SOC="ipq807x_64" +else ifeq ($(CONFIG_TARGET_BOARD), "ipq60xx") + SOC="ipq60xx_64" +endif + +define Build/Configure + $(LN) arch/nss_$(SOC).h $(PKG_BUILD_DIR)/exports/nss_arch.h +endef + +define Build/Compile + +$(MAKE) -C "$(LINUX_DIR)" $(strip $(DRV_MAKE_OPTS)) \ + CROSS_COMPILE="$(TARGET_CROSS)" \ + ARCH="$(LINUX_KARCH)" \ + M="$(PKG_BUILD_DIR)" \ + EXTRA_CFLAGS="$(EXTRA_CFLAGS)" SoC=$(SOC) \ + $(KERNEL_MAKE_FLAGS) \ + $(PKG_JOBS) \ + modules +endef + +$(eval $(call KernelPackage,qca-nss-drv)) diff --git a/qca/qca-nss-drv/files/qca-nss-drv.conf b/qca/qca-nss-drv/files/qca-nss-drv.conf new file mode 100644 index 000000000..a8a1fbf40 --- /dev/null +++ b/qca/qca-nss-drv/files/qca-nss-drv.conf @@ -0,0 +1,6 @@ +config nss_firmware 'qca_nss_0' + +config nss_firmware 'qca_nss_1' + +config general + option enable_rps '1' diff --git a/qca/qca-nss-drv/files/qca-nss-drv.debug b/qca/qca-nss-drv/files/qca-nss-drv.debug new file mode 100644 index 000000000..5d435c3a7 --- /dev/null +++ b/qca/qca-nss-drv/files/qca-nss-drv.debug @@ -0,0 +1,26 @@ +#!/bin/sh /sbin/sysdebug +# +# Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +# + +log cat /sys/kernel/debug/qca-nss-drv/stats/pppoe +log cat /sys/kernel/debug/qca-nss-drv/stats/n2h +log cat /sys/kernel/debug/qca-nss-drv/stats/ipv6 +log cat /sys/kernel/debug/qca-nss-drv/stats/ipv4 +log cat /sys/kernel/debug/qca-nss-drv/stats/gmac +log cat /sys/kernel/debug/qca-nss-drv/stats/drv +log cat /sys/kernel/debug/qca-nss-drv/stats/wifi +log cat /sys/kernel/debug/qca-nss-drv/stats/wifi_if +log cat /sys/kernel/debug/qca-nss-drv/stats/eth_rx diff --git a/qca/qca-nss-drv/files/qca-nss-drv.hotplug b/qca/qca-nss-drv/files/qca-nss-drv.hotplug new file mode 100644 index 000000000..1e4813838 --- /dev/null +++ b/qca/qca-nss-drv/files/qca-nss-drv.hotplug @@ -0,0 +1,70 @@ +#!/bin/sh +# +# Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +# + +KERNEL=`uname -r` +case "${KERNEL}" in + 3.4*) + select_or_load=load_nss_fw + ;; + *) + select_or_load=select_nss_fw + ;; +esac + +load_nss_fw () { + ls -l $1 | awk ' { print $9,$5 } '> /dev/console + echo 1 > /sys/class/firmware/$DEVICENAME/loading + cat $1 > /sys/class/firmware/$DEVICENAME/data + echo 0 > /sys/class/firmware/$DEVICENAME/loading +} + +select_nss_fw () { + rm -f /lib/firmware/$DEVICENAME + ln -s $1 /lib/firmware/$DEVICENAME + ls -l /lib/firmware/$DEVICENAME | awk ' { print $9,$5 } '> /dev/console +} + +[ "$ACTION" != "add" ] && exit + +# dev name for UCI, since it doesn't let you use . or - +SDEVNAME=$(echo ${DEVICENAME} | sed s/[.-]/_/g) + +SELECTED_FW=$(uci get nss.${SDEVNAME}.firmware 2>/dev/null) +[ -e "${SELECTED_FW}" ] && { + $select_or_load ${SELECTED_FW} + exit +} + +case $DEVICENAME in + qca-nss0* | qca-nss.0*) + if [ -e /lib/firmware/qca-nss0-enterprise.bin ] ; then + $select_or_load /lib/firmware/qca-nss0-enterprise.bin + else + $select_or_load /lib/firmware/qca-nss0-retail.bin + fi + exit + ;; + qca-nss1* | qca-nss.1*) + if [ -e /lib/firmware/qca-nss1-enterprise.bin ] ; then + $select_or_load /lib/firmware/qca-nss1-enterprise.bin + else + $select_or_load /lib/firmware/qca-nss1-retail.bin + fi + exit + ;; +esac + diff --git a/qca/qca-nss-drv/files/qca-nss-drv.init b/qca/qca-nss-drv/files/qca-nss-drv.init new file mode 100644 index 000000000..de12cb6d1 --- /dev/null +++ b/qca/qca-nss-drv/files/qca-nss-drv.init @@ -0,0 +1,50 @@ +#!/bin/sh /etc/rc.common +# +# Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +# + +START=70 + +enable_rps() { + irq_nss_rps=`grep nss_queue1 /proc/interrupts | cut -d ':' -f 1 | tr -d ' '` + for entry in $irq_nss_rps + do + echo 2 > /proc/irq/$entry/smp_affinity + done + + irq_nss_rps=`grep nss_queue2 /proc/interrupts | cut -d ':' -f 1 | tr -d ' '` + for entry in $irq_nss_rps + do + echo 4 > /proc/irq/$entry/smp_affinity + done + + irq_nss_rps=`grep nss_queue3 /proc/interrupts | cut -d ':' -f 1 | tr -d ' '` + for entry in $irq_nss_rps + do + echo 8 > /proc/irq/$entry/smp_affinity + done + + # Enable NSS RPS + sysctl -w dev.nss.rps.enable=1 >/dev/null 2>/dev/null + +} + + +start() { + local rps_enabled="$(uci_get nss @general[0] enable_rps)" + if [ "$rps_enabled" -eq 1 ]; then + enable_rps + fi +} diff --git a/qca/qca-nss-drv/files/qca-nss-drv.sysctl b/qca/qca-nss-drv/files/qca-nss-drv.sysctl new file mode 100644 index 000000000..fc36c33eb --- /dev/null +++ b/qca/qca-nss-drv/files/qca-nss-drv.sysctl @@ -0,0 +1,4 @@ +# Default Number of connection configuration +dev.nss.ipv4cfg.ipv4_conn=4096 +dev.nss.ipv6cfg.ipv6_conn=4096 + diff --git a/qca/qca-nss-drv/patches/0001-core-add-5.10-kernel-to-version-check.patch b/qca/qca-nss-drv/patches/0001-core-add-5.10-kernel-to-version-check.patch new file mode 100644 index 000000000..3fea9b5ce --- /dev/null +++ b/qca/qca-nss-drv/patches/0001-core-add-5.10-kernel-to-version-check.patch @@ -0,0 +1,25 @@ +From 3885c752e12f74cad6c97888b797e5903ad1930d Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Thu, 13 May 2021 23:22:38 +0200 +Subject: [PATCH] core: add 5.10 kernel to version check + +NSS DRV has a kernel version check, so simply add +5.10 as supported. + +Signed-off-by: Robert Marko +--- + nss_core.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/nss_core.c ++++ b/nss_core.c +@@ -52,7 +52,8 @@ + (((LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0)))) || \ + (((LINUX_VERSION_CODE >= KERNEL_VERSION(3, 18, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 19, 0)))) || \ + (((LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(4, 5, 0)))) || \ +-(((LINUX_VERSION_CODE >= KERNEL_VERSION(5, 4, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 5, 0)))))) ++(((LINUX_VERSION_CODE >= KERNEL_VERSION(5, 4, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 5, 0)))) || \ ++(((LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 11, 0)))))) + #error "Check skb recycle code in this file to match Linux version" + #endif + diff --git a/qca/qca-nss-drv/patches/0002-nss-drv-replace-ioremap_nocache-with-ioremap.patch b/qca/qca-nss-drv/patches/0002-nss-drv-replace-ioremap_nocache-with-ioremap.patch new file mode 100644 index 000000000..89d650be1 --- /dev/null +++ b/qca/qca-nss-drv/patches/0002-nss-drv-replace-ioremap_nocache-with-ioremap.patch @@ -0,0 +1,181 @@ +From 0cffa7bb366a4e0ff5665d6fc2fa33c1437cb397 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Thu, 13 May 2021 23:33:18 +0200 +Subject: [PATCH 2/8] nss-drv: replace ioremap_nocache() with ioremap() + +ioremap_nocache() does not exist anymore. + +Signed-off-by: Robert Marko +--- + nss_hal/ipq50xx/nss_hal_pvt.c | 6 +++--- + nss_hal/ipq60xx/nss_hal_pvt.c | 8 ++++---- + nss_hal/ipq806x/nss_hal_pvt.c | 4 ++-- + nss_hal/ipq807x/nss_hal_pvt.c | 6 +++--- + nss_hal/nss_hal.c | 4 ++-- + nss_meminfo.c | 2 +- + nss_ppe.c | 2 +- + 7 files changed, 16 insertions(+), 16 deletions(-) + +diff --git a/nss_hal/ipq50xx/nss_hal_pvt.c b/nss_hal/ipq50xx/nss_hal_pvt.c +index 3d6dfd0..e3e4bd2 100644 +--- a/nss_hal/ipq50xx/nss_hal_pvt.c ++++ b/nss_hal/ipq50xx/nss_hal_pvt.c +@@ -184,13 +184,13 @@ static struct nss_platform_data *__nss_hal_of_get_pdata(struct platform_device * + npd->nphys = res_nphys.start; + npd->qgic_phys = res_qgic_phys.start; + +- npd->nmap = ioremap_nocache(npd->nphys, resource_size(&res_nphys)); ++ npd->nmap = ioremap(npd->nphys, resource_size(&res_nphys)); + if (!npd->nmap) { + nss_info_always("%px: nss%d: ioremap() fail for nphys\n", nss_ctx, nss_ctx->id); + goto out; + } + +- npd->qgic_map = ioremap_nocache(npd->qgic_phys, resource_size(&res_qgic_phys)); ++ npd->qgic_map = ioremap(npd->qgic_phys, resource_size(&res_qgic_phys)); + if (!npd->qgic_map) { + nss_info_always("%px: nss%d: ioremap() fail for qgic map\n", nss_ctx, nss_ctx->id); + goto out; +@@ -348,7 +348,7 @@ static int __nss_hal_common_reset(struct platform_device *nss_dev) + + of_node_put(cmn); + +- nss_misc_reset = ioremap_nocache(res_nss_misc_reset.start, resource_size(&res_nss_misc_reset)); ++ nss_misc_reset = ioremap(res_nss_misc_reset.start, resource_size(&res_nss_misc_reset)); + if (!nss_misc_reset) { + pr_err("%px: ioremap fail for nss_misc_reset\n", nss_dev); + return -EFAULT; +diff --git a/nss_hal/ipq60xx/nss_hal_pvt.c b/nss_hal/ipq60xx/nss_hal_pvt.c +index 4c84cb9..e76ef6d 100644 +--- a/nss_hal/ipq60xx/nss_hal_pvt.c ++++ b/nss_hal/ipq60xx/nss_hal_pvt.c +@@ -207,13 +207,13 @@ static struct nss_platform_data *__nss_hal_of_get_pdata(struct platform_device * + npd->nphys = res_nphys.start; + npd->qgic_phys = res_qgic_phys.start; + +- npd->nmap = ioremap_nocache(npd->nphys, resource_size(&res_nphys)); ++ npd->nmap = ioremap(npd->nphys, resource_size(&res_nphys)); + if (!npd->nmap) { + nss_info_always("%px: nss%d: ioremap() fail for nphys\n", nss_ctx, nss_ctx->id); + goto out; + } + +- npd->qgic_map = ioremap_nocache(npd->qgic_phys, resource_size(&res_qgic_phys)); ++ npd->qgic_map = ioremap(npd->qgic_phys, resource_size(&res_qgic_phys)); + if (!npd->qgic_map) { + nss_info_always("%px: nss%d: ioremap() fail for qgic map\n", nss_ctx, nss_ctx->id); + goto out; +@@ -433,13 +433,13 @@ static int __nss_hal_common_reset(struct platform_device *nss_dev) + + of_node_put(cmn); + +- nss_misc_reset = ioremap_nocache(res_nss_misc_reset.start, resource_size(&res_nss_misc_reset)); ++ nss_misc_reset = ioremap(res_nss_misc_reset.start, resource_size(&res_nss_misc_reset)); + if (!nss_misc_reset) { + pr_err("%px: ioremap fail for nss_misc_reset\n", nss_dev); + return -EFAULT; + } + +- nss_misc_reset_flag = ioremap_nocache(res_nss_misc_reset_flag.start, resource_size(&res_nss_misc_reset_flag)); ++ nss_misc_reset_flag = ioremap(res_nss_misc_reset_flag.start, resource_size(&res_nss_misc_reset_flag)); + if (!nss_misc_reset_flag) { + pr_err("%px: ioremap fail for nss_misc_reset_flag\n", nss_dev); + return -EFAULT; +diff --git a/nss_hal/ipq806x/nss_hal_pvt.c b/nss_hal/ipq806x/nss_hal_pvt.c +index b8733e0..52d63b0 100644 +--- a/nss_hal/ipq806x/nss_hal_pvt.c ++++ b/nss_hal/ipq806x/nss_hal_pvt.c +@@ -458,7 +458,7 @@ static struct nss_platform_data *__nss_hal_of_get_pdata(struct platform_device * + npd->nphys = res_nphys.start; + npd->vphys = res_vphys.start; + +- npd->nmap = ioremap_nocache(npd->nphys, resource_size(&res_nphys)); ++ npd->nmap = ioremap(npd->nphys, resource_size(&res_nphys)); + if (!npd->nmap) { + nss_info_always("%px: nss%d: ioremap() fail for nphys\n", nss_ctx, nss_ctx->id); + goto out; +@@ -711,7 +711,7 @@ static int __nss_hal_common_reset(struct platform_device *nss_dev) + } + of_node_put(cmn); + +- fpb_base = ioremap_nocache(res_nss_fpb_base.start, resource_size(&res_nss_fpb_base)); ++ fpb_base = ioremap(res_nss_fpb_base.start, resource_size(&res_nss_fpb_base)); + if (!fpb_base) { + pr_err("%px: ioremap fail for nss_fpb_base\n", nss_dev); + return -EFAULT; +diff --git a/nss_hal/ipq807x/nss_hal_pvt.c b/nss_hal/ipq807x/nss_hal_pvt.c +index b95a23c..bb8f42f 100644 +--- a/nss_hal/ipq807x/nss_hal_pvt.c ++++ b/nss_hal/ipq807x/nss_hal_pvt.c +@@ -234,7 +234,7 @@ static struct nss_platform_data *__nss_hal_of_get_pdata(struct platform_device * + npd->vphys = res_vphys.start; + npd->qgic_phys = res_qgic_phys.start; + +- npd->nmap = ioremap_nocache(npd->nphys, resource_size(&res_nphys)); ++ npd->nmap = ioremap(npd->nphys, resource_size(&res_nphys)); + if (!npd->nmap) { + nss_info_always("%px: nss%d: ioremap() fail for nphys\n", nss_ctx, nss_ctx->id); + goto out; +@@ -247,7 +247,7 @@ static struct nss_platform_data *__nss_hal_of_get_pdata(struct platform_device * + goto out; + } + +- npd->qgic_map = ioremap_nocache(npd->qgic_phys, resource_size(&res_qgic_phys)); ++ npd->qgic_map = ioremap(npd->qgic_phys, resource_size(&res_qgic_phys)); + if (!npd->qgic_map) { + nss_info_always("%px: nss%d: ioremap() fail for qgic map\n", nss_ctx, nss_ctx->id); + goto out; +@@ -467,7 +467,7 @@ static int __nss_hal_common_reset(struct platform_device *nss_dev) + } + of_node_put(cmn); + +- nss_misc_reset = ioremap_nocache(res_nss_misc_reset.start, resource_size(&res_nss_misc_reset)); ++ nss_misc_reset = ioremap(res_nss_misc_reset.start, resource_size(&res_nss_misc_reset)); + if (!nss_misc_reset) { + pr_err("%px: ioremap fail for nss_misc_reset\n", nss_dev); + return -EFAULT; +diff --git a/nss_hal/nss_hal.c b/nss_hal/nss_hal.c +index d58bb57..57974c1 100644 +--- a/nss_hal/nss_hal.c ++++ b/nss_hal/nss_hal.c +@@ -78,9 +78,9 @@ int nss_hal_firmware_load(struct nss_ctx_instance *nss_ctx, struct platform_devi + return rc; + } + +- load_mem = ioremap_nocache(npd->load_addr, nss_fw->size); ++ load_mem = ioremap(npd->load_addr, nss_fw->size); + if (!load_mem) { +- nss_info_always("%px: ioremap_nocache failed: %x", nss_ctx, npd->load_addr); ++ nss_info_always("%px: ioremap failed: %x", nss_ctx, npd->load_addr); + release_firmware(nss_fw); + return rc; + } +diff --git a/nss_meminfo.c b/nss_meminfo.c +index e24e6be..2255eae 100644 +--- a/nss_meminfo.c ++++ b/nss_meminfo.c +@@ -728,7 +728,7 @@ bool nss_meminfo_init(struct nss_ctx_instance *nss_ctx) + /* + * meminfo_start is the label where the start address of meminfo map is stored. + */ +- meminfo_start = (uint32_t *)ioremap_nocache(nss_ctx->load + NSS_MEMINFO_MAP_START_OFFSET, ++ meminfo_start = (uint32_t *)ioremap(nss_ctx->load + NSS_MEMINFO_MAP_START_OFFSET, + NSS_MEMINFO_RESERVE_AREA_SIZE); + if (!meminfo_start) { + nss_info_always("%px: cannot remap meminfo start\n", nss_ctx); +diff --git a/nss_ppe.c b/nss_ppe.c +index 46ce217..644fc98 100644 +--- a/nss_ppe.c ++++ b/nss_ppe.c +@@ -357,7 +357,7 @@ void nss_ppe_init(void) + /* + * Get the PPE base address + */ +- ppe_pvt.ppe_base = ioremap_nocache(PPE_BASE_ADDR, PPE_REG_SIZE); ++ ppe_pvt.ppe_base = ioremap(PPE_BASE_ADDR, PPE_REG_SIZE); + if (!ppe_pvt.ppe_base) { + nss_warning("DRV can't get PPE base address\n"); + return; +-- +2.34.1 + diff --git a/qca/qca-nss-drv/patches/0003-DMA-Fix-NULL-pointer-exceptions.patch b/qca/qca-nss-drv/patches/0003-DMA-Fix-NULL-pointer-exceptions.patch new file mode 100644 index 000000000..0c13a7887 --- /dev/null +++ b/qca/qca-nss-drv/patches/0003-DMA-Fix-NULL-pointer-exceptions.patch @@ -0,0 +1,49 @@ +From 62e457f262aaa0db7113ad3ccbcb7ae49d4d7ea8 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Tue, 8 Jun 2021 23:24:43 +0200 +Subject: [PATCH] DMA: Fix NULL pointer exceptions + +There are multiple instances that pass NULL instead +of device to DMA functions. +That is incorrect and will cause kernel NULL pointer +exceptions. + +So, simply pass the device structure pointers. + +Signed-off-by: Robert Marko +--- + nss_core.c | 2 +- + nss_coredump.c | 4 ++-- + 2 files changed, 3 insertions(+), 3 deletions(-) + +--- a/nss_core.c ++++ b/nss_core.c +@@ -1617,7 +1617,7 @@ static int32_t nss_core_handle_cause_que + * + */ + if (unlikely((buffer_type == N2H_BUFFER_CRYPTO_RESP))) { +- dma_unmap_single(NULL, (desc->buffer + desc->payload_offs), desc->payload_len, DMA_FROM_DEVICE); ++ dma_unmap_single(nss_ctx->dev, (desc->buffer + desc->payload_offs), desc->payload_len, DMA_FROM_DEVICE); + goto consume; + } + +--- a/nss_coredump.c ++++ b/nss_coredump.c +@@ -154,7 +154,7 @@ void nss_fw_coredump_notify(struct nss_c + dma_addr = nss_own->meminfo_ctx.logbuffer_dma; + } + +- dma_sync_single_for_cpu(NULL, dma_addr, sizeof(struct nss_log_descriptor), DMA_FROM_DEVICE); ++ dma_sync_single_for_cpu(nss_own->dev, dma_addr, sizeof(struct nss_log_descriptor), DMA_FROM_DEVICE); + + /* + * If the current entry is smaller than or equal to the number of NSS_LOG_COREDUMP_LINE_NUM, +@@ -181,7 +181,7 @@ void nss_fw_coredump_notify(struct nss_c + + offset = (index * sizeof(struct nss_log_entry)) + + offsetof(struct nss_log_descriptor, log_ring_buffer); +- dma_sync_single_for_cpu(NULL, dma_addr + offset, ++ dma_sync_single_for_cpu(nss_own->dev, dma_addr + offset, + sizeof(struct nss_log_entry), DMA_FROM_DEVICE); + nss_info_always("%px: %s\n", nss_own, nle_print->message); + nle_print++; diff --git a/qca/qca-nss-drv/patches/0004-nss-drv-rework-NSS_CORE_DMA_CACHE_MAINT-ops.patch b/qca/qca-nss-drv/patches/0004-nss-drv-rework-NSS_CORE_DMA_CACHE_MAINT-ops.patch new file mode 100644 index 000000000..6ef442aad --- /dev/null +++ b/qca/qca-nss-drv/patches/0004-nss-drv-rework-NSS_CORE_DMA_CACHE_MAINT-ops.patch @@ -0,0 +1,573 @@ +From 12cf63f66bfe509da6d845e5c716efd99dadf01e Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Tue, 5 Apr 2022 15:38:18 +0200 +Subject: [PATCH 4/8] nss-drv: rework NSS_CORE_DMA_CACHE_MAINT ops + +Rework NSS_CORE_DMA_CACHE_MAINT ops to use standard dma sync ops instead +of using the direct arch function. This permit to skip any hack/patch +needed for nss-drv to correctly compile on upstream kernel. + +We drop any NSS_CORE_DMA_CACHE_MAINT use in nss_core and we correctly +use the dma_sync_single_for_device we correctly dma addr using the new +DMA helper. +We drop sync for IOREMAP addr and we just leave a memory block. +We hope the nss_profiler is correctly ported. +We finally drop the NSS_CORE_DMA_CACHE_MAINT jus in case someone wants +to use it. + +Signed-off-by: Ansuel Smith +--- + nss_core.c | 136 +++++++++++++++++++++++++--------- + nss_core.h | 41 +++++----- + nss_hal/ipq806x/nss_hal_pvt.c | 5 +- + nss_hal/ipq807x/nss_hal_pvt.c | 5 +- + nss_meminfo.c | 5 +- + nss_profiler.c | 3 +- + 6 files changed, 127 insertions(+), 68 deletions(-) + +diff --git a/nss_core.c b/nss_core.c +index 23dc155..f9e6014 100644 +--- a/nss_core.c ++++ b/nss_core.c +@@ -1429,6 +1429,8 @@ static inline void nss_core_handle_empty_buffers(struct nss_ctx_instance *nss_ct + uint32_t count, uint32_t hlos_index, + uint16_t mask) + { ++ struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; ++ + while (count) { + /* + * Since we only return the primary skb, we have no way to unmap +@@ -1482,7 +1484,9 @@ next: + n2h_desc_ring->hlos_index = hlos_index; + if_map->n2h_hlos_index[NSS_IF_N2H_EMPTY_BUFFER_RETURN_QUEUE] = hlos_index; + +- NSS_CORE_DMA_CACHE_MAINT((void *)&if_map->n2h_hlos_index[NSS_IF_N2H_EMPTY_BUFFER_RETURN_QUEUE], sizeof(uint32_t), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, ++ n2h_hlos_index_to_dma(mem_ctx->if_map_dma, NSS_IF_N2H_EMPTY_BUFFER_RETURN_QUEUE), ++ sizeof(uint32_t), DMA_TO_DEVICE); + NSS_CORE_DSB(); + } + +@@ -1504,6 +1508,7 @@ static int32_t nss_core_handle_cause_queue(struct int_ctx_instance *int_ctx, uin + struct nss_ctx_instance *nss_ctx = int_ctx->nss_ctx; + struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; + struct nss_if_mem_map *if_map = mem_ctx->if_map; ++ int dma_size; + + qid = nss_core_cause_to_queue(cause); + +@@ -1515,7 +1520,8 @@ static int32_t nss_core_handle_cause_queue(struct int_ctx_instance *int_ctx, uin + n2h_desc_ring = &nss_ctx->n2h_desc_ring[qid]; + desc_if = &n2h_desc_ring->desc_ring; + desc_ring = desc_if->desc; +- NSS_CORE_DMA_CACHE_MAINT((void *)&if_map->n2h_nss_index[qid], sizeof(uint32_t), DMA_FROM_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, n2h_nss_index_to_dma(mem_ctx->if_map_dma, qid), ++ sizeof(uint32_t), DMA_FROM_DEVICE); + NSS_CORE_DSB(); + nss_index = if_map->n2h_nss_index[qid]; + +@@ -1544,13 +1550,23 @@ static int32_t nss_core_handle_cause_queue(struct int_ctx_instance *int_ctx, uin + start = hlos_index; + end = (hlos_index + count) & mask; + if (end > start) { +- dmac_inv_range((void *)&desc_ring[start], (void *)&desc_ring[end] + sizeof(struct n2h_descriptor)); ++ dma_size = sizeof(struct n2h_descriptor) * (end - start + 1); ++ ++ dma_sync_single_for_device(nss_ctx->dev, n2h_desc_index_to_dma(if_map, qid, start), ++ dma_size, DMA_FROM_DEVICE); + } else { + /* + * We have wrapped around + */ +- dmac_inv_range((void *)&desc_ring[start], (void *)&desc_ring[mask] + sizeof(struct n2h_descriptor)); +- dmac_inv_range((void *)&desc_ring[0], (void *)&desc_ring[end] + sizeof(struct n2h_descriptor)); ++ dma_size = sizeof(struct n2h_descriptor) * (mask - start + 1); ++ ++ dma_sync_single_for_device(nss_ctx->dev, n2h_desc_index_to_dma(if_map, qid, start), ++ dma_size, DMA_FROM_DEVICE); ++ ++ dma_size = sizeof(struct n2h_descriptor) * (end + 1); ++ ++ dma_sync_single_for_device(nss_ctx->dev, n2h_desc_index_to_dma(if_map, qid, 0), dma_size, ++ DMA_FROM_DEVICE); + } + + /* +@@ -1679,7 +1695,8 @@ next: + n2h_desc_ring->hlos_index = hlos_index; + if_map->n2h_hlos_index[qid] = hlos_index; + +- NSS_CORE_DMA_CACHE_MAINT((void *)&if_map->n2h_hlos_index[qid], sizeof(uint32_t), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, n2h_hlos_index_to_dma(mem_ctx->if_map_dma, qid), ++ sizeof(uint32_t), DMA_TO_DEVICE); + NSS_CORE_DSB(); + + return count; +@@ -1691,11 +1708,12 @@ next: + */ + static void nss_core_init_nss(struct nss_ctx_instance *nss_ctx, struct nss_if_mem_map *if_map) + { ++ struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; + struct nss_top_instance *nss_top; + int ret; + int i; + +- NSS_CORE_DMA_CACHE_MAINT((void *)if_map, sizeof(*if_map), DMA_FROM_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, mem_ctx->if_map_dma, sizeof(*if_map), DMA_FROM_DEVICE); + NSS_CORE_DSB(); + + /* +@@ -1762,6 +1780,7 @@ static void nss_core_alloc_paged_buffers(struct nss_ctx_instance *nss_ctx, struc + uint16_t count, int16_t mask, int32_t hlos_index, uint32_t alloc_fail_count, + uint32_t buffer_type, uint32_t buffer_queue, uint32_t stats_index) + { ++ struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; + struct sk_buff *nbuf; + struct page *npage; + struct hlos_h2n_desc_rings *h2n_desc_ring = &nss_ctx->h2n_desc_rings[buffer_queue]; +@@ -1831,7 +1850,9 @@ static void nss_core_alloc_paged_buffers(struct nss_ctx_instance *nss_ctx, struc + /* + * Flush the descriptor + */ +- NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, ++ h2n_desc_index_to_dma(if_map, buffer_queue, hlos_index), ++ sizeof(*desc), DMA_TO_DEVICE); + + hlos_index = (hlos_index + 1) & (mask); + count--; +@@ -1845,7 +1866,8 @@ static void nss_core_alloc_paged_buffers(struct nss_ctx_instance *nss_ctx, struc + h2n_desc_ring->hlos_index = hlos_index; + if_map->h2n_hlos_index[buffer_queue] = hlos_index; + +- NSS_CORE_DMA_CACHE_MAINT(&if_map->h2n_hlos_index[buffer_queue], sizeof(uint32_t), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, h2n_hlos_index_to_dma(mem_ctx->if_map_dma, buffer_queue), ++ sizeof(uint32_t), DMA_TO_DEVICE); + NSS_CORE_DSB(); + + NSS_PKT_STATS_INC(&nss_top->stats_drv[stats_index]); +@@ -1858,7 +1880,7 @@ static void nss_core_alloc_paged_buffers(struct nss_ctx_instance *nss_ctx, struc + static void nss_core_alloc_jumbo_mru_buffers(struct nss_ctx_instance *nss_ctx, struct nss_if_mem_map *if_map, + int jumbo_mru, uint16_t count, int16_t mask, int32_t hlos_index) + { +- ++ struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; + struct sk_buff *nbuf; + struct hlos_h2n_desc_rings *h2n_desc_ring = &nss_ctx->h2n_desc_rings[NSS_IF_H2N_EMPTY_BUFFER_QUEUE]; + struct h2n_desc_if_instance *desc_if = &h2n_desc_ring->desc_ring; +@@ -1905,7 +1927,9 @@ static void nss_core_alloc_jumbo_mru_buffers(struct nss_ctx_instance *nss_ctx, s + /* + * Flush the descriptor + */ +- NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, ++ h2n_desc_index_to_dma(if_map, NSS_IF_H2N_EMPTY_BUFFER_QUEUE, hlos_index), ++ sizeof(*desc), DMA_TO_DEVICE); + + hlos_index = (hlos_index + 1) & (mask); + count--; +@@ -1919,7 +1943,8 @@ static void nss_core_alloc_jumbo_mru_buffers(struct nss_ctx_instance *nss_ctx, s + h2n_desc_ring->hlos_index = hlos_index; + if_map->h2n_hlos_index[NSS_IF_H2N_EMPTY_BUFFER_QUEUE] = hlos_index; + +- NSS_CORE_DMA_CACHE_MAINT(&if_map->h2n_hlos_index[NSS_IF_H2N_EMPTY_BUFFER_QUEUE], sizeof(uint32_t), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, h2n_hlos_index_to_dma(mem_ctx->if_map_dma, NSS_IF_H2N_EMPTY_BUFFER_QUEUE), ++ sizeof(uint32_t), DMA_TO_DEVICE); + NSS_CORE_DSB(); + + NSS_PKT_STATS_INC(&nss_top->stats_drv[NSS_DRV_STATS_TX_EMPTY]); +@@ -1932,6 +1957,7 @@ static void nss_core_alloc_jumbo_mru_buffers(struct nss_ctx_instance *nss_ctx, s + static void nss_core_alloc_max_avail_size_buffers(struct nss_ctx_instance *nss_ctx, struct nss_if_mem_map *if_map, + uint16_t max_buf_size, uint16_t count, int16_t mask, int32_t hlos_index) + { ++ struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; + struct hlos_h2n_desc_rings *h2n_desc_ring = &nss_ctx->h2n_desc_rings[NSS_IF_H2N_EMPTY_BUFFER_QUEUE]; + struct h2n_desc_if_instance *desc_if = &h2n_desc_ring->desc_ring; + struct h2n_descriptor *desc_ring = desc_if->desc; +@@ -1939,6 +1965,7 @@ static void nss_core_alloc_max_avail_size_buffers(struct nss_ctx_instance *nss_c + uint16_t payload_len = max_buf_size + NET_SKB_PAD; + uint16_t start = hlos_index; + uint16_t prev_hlos_index; ++ int dma_size; + + while (count) { + dma_addr_t buffer; +@@ -1991,13 +2018,26 @@ static void nss_core_alloc_max_avail_size_buffers(struct nss_ctx_instance *nss_c + * Flush the descriptors, including the descriptor at prev_hlos_index. + */ + if (prev_hlos_index > start) { +- dmac_clean_range((void *)&desc_ring[start], (void *)&desc_ring[prev_hlos_index] + sizeof(struct h2n_descriptor)); ++ dma_size = sizeof(struct h2n_descriptor) * (prev_hlos_index - start + 1); ++ ++ dma_sync_single_for_device(nss_ctx->dev, ++ h2n_desc_index_to_dma(if_map, NSS_IF_H2N_EMPTY_BUFFER_QUEUE, start), ++ dma_size, DMA_TO_DEVICE); + } else { + /* + * We have wrapped around + */ +- dmac_clean_range((void *)&desc_ring[start], (void *)&desc_ring[mask] + sizeof(struct h2n_descriptor)); +- dmac_clean_range((void *)&desc_ring[0], (void *)&desc_ring[prev_hlos_index] + sizeof(struct h2n_descriptor)); ++ dma_size = sizeof(struct h2n_descriptor) * (mask - start + 1); ++ ++ dma_sync_single_for_device(nss_ctx->dev, ++ h2n_desc_index_to_dma(if_map, NSS_IF_H2N_EMPTY_BUFFER_QUEUE, start), ++ dma_size, DMA_TO_DEVICE); ++ ++ dma_size = sizeof(struct h2n_descriptor) * (prev_hlos_index + 1); ++ ++ dma_sync_single_for_device(nss_ctx->dev, ++ h2n_desc_index_to_dma(if_map, NSS_IF_H2N_EMPTY_BUFFER_QUEUE, 0), ++ dma_size, DMA_TO_DEVICE); + } + + /* +@@ -2008,7 +2048,8 @@ static void nss_core_alloc_max_avail_size_buffers(struct nss_ctx_instance *nss_c + h2n_desc_ring->hlos_index = hlos_index; + if_map->h2n_hlos_index[NSS_IF_H2N_EMPTY_BUFFER_QUEUE] = hlos_index; + +- NSS_CORE_DMA_CACHE_MAINT(&if_map->h2n_hlos_index[NSS_IF_H2N_EMPTY_BUFFER_QUEUE], sizeof(uint32_t), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, h2n_hlos_index_to_dma(mem_ctx->if_map_dma, NSS_IF_H2N_EMPTY_BUFFER_QUEUE), ++ sizeof(uint32_t), DMA_TO_DEVICE); + NSS_CORE_DSB(); + + NSS_PKT_STATS_INC(&nss_top->stats_drv[NSS_DRV_STATS_TX_EMPTY]); +@@ -2021,6 +2062,7 @@ static void nss_core_alloc_max_avail_size_buffers(struct nss_ctx_instance *nss_c + static inline void nss_core_handle_empty_buffer_sos(struct nss_ctx_instance *nss_ctx, + struct nss_if_mem_map *if_map, uint16_t max_buf_size) + { ++ struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; + uint16_t count, size, mask; + int32_t nss_index, hlos_index; + struct hlos_h2n_desc_rings *h2n_desc_ring = &nss_ctx->h2n_desc_rings[NSS_IF_H2N_EMPTY_BUFFER_QUEUE]; +@@ -2031,7 +2073,8 @@ static inline void nss_core_handle_empty_buffer_sos(struct nss_ctx_instance *nss + /* + * Check how many empty buffers could be filled in queue + */ +- NSS_CORE_DMA_CACHE_MAINT(&if_map->h2n_nss_index[NSS_IF_H2N_EMPTY_BUFFER_QUEUE], sizeof(uint32_t), DMA_FROM_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, h2n_nss_index_to_dma(mem_ctx->if_map_dma, NSS_IF_H2N_EMPTY_BUFFER_QUEUE), ++ sizeof(uint32_t), DMA_FROM_DEVICE); + NSS_CORE_DSB(); + nss_index = if_map->h2n_nss_index[NSS_IF_H2N_EMPTY_BUFFER_QUEUE]; + +@@ -2076,6 +2119,7 @@ static inline void nss_core_handle_empty_buffer_sos(struct nss_ctx_instance *nss + static inline void nss_core_handle_paged_empty_buffer_sos(struct nss_ctx_instance *nss_ctx, + struct nss_if_mem_map *if_map, uint16_t max_buf_size) + { ++ struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; + uint16_t count, size, mask; + int32_t nss_index, hlos_index; + struct hlos_h2n_desc_rings *h2n_desc_ring = &nss_ctx->h2n_desc_rings[NSS_IF_H2N_EMPTY_PAGED_BUFFER_QUEUE]; +@@ -2083,7 +2127,8 @@ static inline void nss_core_handle_paged_empty_buffer_sos(struct nss_ctx_instanc + /* + * Check how many empty buffers could be filled in queue + */ +- NSS_CORE_DMA_CACHE_MAINT((void *)&if_map->h2n_nss_index[NSS_IF_H2N_EMPTY_PAGED_BUFFER_QUEUE], sizeof(uint32_t), DMA_FROM_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, h2n_nss_index_to_dma(mem_ctx->if_map_dma, NSS_IF_H2N_EMPTY_PAGED_BUFFER_QUEUE), ++ sizeof(uint32_t), DMA_FROM_DEVICE); + NSS_CORE_DSB(); + nss_index = if_map->h2n_nss_index[NSS_IF_H2N_EMPTY_PAGED_BUFFER_QUEUE]; + +@@ -2651,9 +2696,11 @@ void nss_skb_reuse(struct sk_buff *nbuf) + * Sends one skb to NSS FW + */ + static inline int32_t nss_core_send_buffer_simple_skb(struct nss_ctx_instance *nss_ctx, +- struct h2n_desc_if_instance *desc_if, uint32_t if_num, +- struct sk_buff *nbuf, uint16_t hlos_index, uint16_t flags, uint8_t buffer_type, uint16_t mss) ++ struct h2n_desc_if_instance *desc_if, uint32_t if_num, struct sk_buff *nbuf, ++ uint16_t qid, uint16_t hlos_index, uint16_t flags, uint8_t buffer_type, uint16_t mss) + { ++ struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; ++ struct nss_if_mem_map *if_map = mem_ctx->if_map; + struct h2n_descriptor *desc_ring = desc_if->desc; + struct h2n_descriptor *desc; + uint16_t bit_flags; +@@ -2707,7 +2754,8 @@ static inline int32_t nss_core_send_buffer_simple_skb(struct nss_ctx_instance *n + (nss_ptr_t)nbuf, (uint16_t)(nbuf->data - nbuf->head), nbuf->len, + sz, (uint32_t)nbuf->priority, mss, bit_flags); + +- NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, h2n_desc_index_to_dma(if_map, qid, hlos_index), ++ sizeof(*desc), DMA_TO_DEVICE); + + /* + * We are done using the skb fields and can reuse it now +@@ -2731,7 +2779,8 @@ no_reuse: + (nss_ptr_t)nbuf, (uint16_t)(nbuf->data - nbuf->head), nbuf->len, + (uint16_t)skb_end_offset(nbuf), (uint32_t)nbuf->priority, mss, bit_flags); + +- NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, h2n_desc_index_to_dma(if_map, qid, hlos_index), ++ sizeof(*desc), DMA_TO_DEVICE); + + NSS_PKT_STATS_INC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_TX_SIMPLE]); + return 1; +@@ -2745,9 +2794,11 @@ no_reuse: + * Used to differentiate from FRAGLIST + */ + static inline int32_t nss_core_send_buffer_nr_frags(struct nss_ctx_instance *nss_ctx, +- struct h2n_desc_if_instance *desc_if, uint32_t if_num, +- struct sk_buff *nbuf, uint16_t hlos_index, uint16_t flags, uint8_t buffer_type, uint16_t mss) ++ struct h2n_desc_if_instance *desc_if, uint32_t if_num, struct sk_buff *nbuf, ++ uint16_t qid, uint16_t hlos_index, uint16_t flags, uint8_t buffer_type, uint16_t mss) + { ++ struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; ++ struct nss_if_mem_map *if_map = mem_ctx->if_map; + struct h2n_descriptor *desc_ring = desc_if->desc; + struct h2n_descriptor *desc; + const skb_frag_t *frag; +@@ -2787,7 +2838,8 @@ static inline int32_t nss_core_send_buffer_nr_frags(struct nss_ctx_instance *nss + (nss_ptr_t)NULL, nbuf->data - nbuf->head, nbuf->len - nbuf->data_len, + skb_end_offset(nbuf), (uint32_t)nbuf->priority, mss, bit_flags | H2N_BIT_FLAG_FIRST_SEGMENT); + +- NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, h2n_desc_index_to_dma(if_map, qid, hlos_index), ++ sizeof(*desc), DMA_TO_DEVICE); + + /* + * Now handle rest of the fragments. +@@ -2811,7 +2863,8 @@ static inline int32_t nss_core_send_buffer_nr_frags(struct nss_ctx_instance *nss + (nss_ptr_t)NULL, 0, skb_frag_size(frag), skb_frag_size(frag), + nbuf->priority, mss, bit_flags); + +- NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, h2n_desc_index_to_dma(if_map, qid, hlos_index), ++ sizeof(*desc), DMA_TO_DEVICE); + } + + /* +@@ -2827,7 +2880,8 @@ static inline int32_t nss_core_send_buffer_nr_frags(struct nss_ctx_instance *nss + desc->bit_flags &= ~(H2N_BIT_FLAG_DISCARD); + desc->opaque = (nss_ptr_t)nbuf; + +- NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, h2n_desc_index_to_dma(if_map, qid, hlos_index), ++ sizeof(*desc), DMA_TO_DEVICE); + + NSS_PKT_STATS_INC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_TX_NR_FRAGS]); + return i+1; +@@ -2841,9 +2895,11 @@ static inline int32_t nss_core_send_buffer_nr_frags(struct nss_ctx_instance *nss + * Used to differentiate from FRAGS + */ + static inline int32_t nss_core_send_buffer_fraglist(struct nss_ctx_instance *nss_ctx, +- struct h2n_desc_if_instance *desc_if, uint32_t if_num, +- struct sk_buff *nbuf, uint16_t hlos_index, uint16_t flags, uint8_t buffer_type, uint16_t mss) ++ struct h2n_desc_if_instance *desc_if, uint32_t if_num, struct sk_buff *nbuf, ++ uint16_t qid, uint16_t hlos_index, uint16_t flags, uint8_t buffer_type, uint16_t mss) + { ++ struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; ++ struct nss_if_mem_map *if_map = mem_ctx->if_map; + struct h2n_descriptor *desc_ring = desc_if->desc; + struct h2n_descriptor *desc; + dma_addr_t buffer; +@@ -2882,7 +2938,8 @@ static inline int32_t nss_core_send_buffer_fraglist(struct nss_ctx_instance *nss + (nss_ptr_t)nbuf, nbuf->data - nbuf->head, nbuf->len - nbuf->data_len, + skb_end_offset(nbuf), (uint32_t)nbuf->priority, mss, bit_flags | H2N_BIT_FLAG_FIRST_SEGMENT); + +- NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, h2n_desc_index_to_dma(if_map, qid, hlos_index), ++ sizeof(*desc), DMA_TO_DEVICE); + + /* + * Walk the frag_list in nbuf +@@ -2935,7 +2992,8 @@ static inline int32_t nss_core_send_buffer_fraglist(struct nss_ctx_instance *nss + (nss_ptr_t)iter, iter->data - iter->head, iter->len - iter->data_len, + skb_end_offset(iter), iter->priority, mss, bit_flags); + +- NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, h2n_desc_index_to_dma(if_map, qid, hlos_index), ++ sizeof(*desc), DMA_TO_DEVICE); + + i++; + } +@@ -2954,7 +3012,8 @@ static inline int32_t nss_core_send_buffer_fraglist(struct nss_ctx_instance *nss + * Update bit flag for last descriptor. + */ + desc->bit_flags |= H2N_BIT_FLAG_LAST_SEGMENT; +- NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, h2n_desc_index_to_dma(if_map, qid, hlos_index), ++ sizeof(*desc), DMA_TO_DEVICE); + + NSS_PKT_STATS_INC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_TX_FRAGLIST]); + return i+1; +@@ -3025,8 +3084,10 @@ int32_t nss_core_send_buffer(struct nss_ctx_instance *nss_ctx, uint32_t if_num, + * We need to work out if there's sufficent space in our transmit descriptor + * ring to place all the segments of a nbuf. + */ +- NSS_CORE_DMA_CACHE_MAINT((void *)&if_map->h2n_nss_index[qid], sizeof(uint32_t), DMA_FROM_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, h2n_nss_index_to_dma(mem_ctx->if_map_dma, qid), ++ sizeof(uint32_t), DMA_FROM_DEVICE); + NSS_CORE_DSB(); ++ + nss_index = if_map->h2n_nss_index[qid]; + h2n_desc_ring->nss_index_local = nss_index; + count = ((nss_index - hlos_index - 1) + size) & (mask); +@@ -3095,13 +3156,13 @@ int32_t nss_core_send_buffer(struct nss_ctx_instance *nss_ctx, uint32_t if_num, + count = 0; + if (likely((segments == 0) || is_bounce)) { + count = nss_core_send_buffer_simple_skb(nss_ctx, desc_if, if_num, +- nbuf, hlos_index, flags, buffer_type, mss); ++ nbuf, qid, hlos_index, flags, buffer_type, mss); + } else if (skb_has_frag_list(nbuf)) { + count = nss_core_send_buffer_fraglist(nss_ctx, desc_if, if_num, +- nbuf, hlos_index, flags, buffer_type, mss); ++ nbuf, qid, hlos_index, flags, buffer_type, mss); + } else { + count = nss_core_send_buffer_nr_frags(nss_ctx, desc_if, if_num, +- nbuf, hlos_index, flags, buffer_type, mss); ++ nbuf, qid, hlos_index, flags, buffer_type, mss); + } + + if (unlikely(count <= 0)) { +@@ -3125,7 +3186,8 @@ int32_t nss_core_send_buffer(struct nss_ctx_instance *nss_ctx, uint32_t if_num, + h2n_desc_ring->hlos_index = hlos_index; + if_map->h2n_hlos_index[qid] = hlos_index; + +- NSS_CORE_DMA_CACHE_MAINT(&if_map->h2n_hlos_index[qid], sizeof(uint32_t), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, h2n_hlos_index_to_dma(mem_ctx->if_map_dma, qid), ++ sizeof(uint32_t), DMA_TO_DEVICE); + NSS_CORE_DSB(); + + #ifdef CONFIG_DEBUG_KMEMLEAK +diff --git a/nss_core.h b/nss_core.h +index d7f62fe..7ddf6ce 100644 +--- a/nss_core.h ++++ b/nss_core.h +@@ -100,31 +100,30 @@ + #endif + + /* +- * Cache operation ++ * DMA Offset helper + */ +-#define NSS_CORE_DSB() dsb(sy) +-#define NSS_CORE_DMA_CACHE_MAINT(start, size, dir) nss_core_dma_cache_maint(start, size, dir) ++#define n2h_desc_index_offset(_index) sizeof(struct n2h_descriptor) * (_index) ++#define h2n_desc_index_offset(_index) sizeof(struct h2n_descriptor) * (_index) ++ ++#define n2h_desc_index_to_dma(_if_map_addr, _qid, _index) (_if_map_addr)->n2h_desc_if[(_qid)].desc_addr + n2h_desc_index_offset(_index) ++#define h2n_desc_index_to_dma(_if_map_addr, _qid, _index) (_if_map_addr)->h2n_desc_if[(_qid)].desc_addr + h2n_desc_index_offset(_index) ++ ++#define h2n_nss_index_offset offsetof(struct nss_if_mem_map, h2n_nss_index) ++#define n2h_nss_index_offset offsetof(struct nss_if_mem_map, n2h_nss_index) ++#define h2n_hlos_index_offset offsetof(struct nss_if_mem_map, h2n_hlos_index) ++#define n2h_hlos_index_offset offsetof(struct nss_if_mem_map, n2h_hlos_index) ++ ++#define h2n_nss_index_to_dma(_if_map_addr, _index) (_if_map_addr) + h2n_nss_index_offset + (sizeof(uint32_t) * (_index)) ++#define n2h_nss_index_to_dma(_if_map_addr, _index) (_if_map_addr) + n2h_nss_index_offset + (sizeof(uint32_t) * (_index)) ++#define h2n_hlos_index_to_dma(_if_map_addr, _index) (_if_map_addr) + h2n_hlos_index_offset + (sizeof(uint32_t) * (_index)) ++#define n2h_hlos_index_to_dma(_if_map_addr, _index) (_if_map_addr) + n2h_hlos_index_offset + (sizeof(uint32_t) * (_index)) + + /* +- * nss_core_dma_cache_maint() +- * Perform the appropriate cache op based on direction ++ * Cache operation + */ +-static inline void nss_core_dma_cache_maint(void *start, uint32_t size, int direction) +-{ +- switch (direction) { +- case DMA_FROM_DEVICE:/* invalidate only */ +- dmac_inv_range(start, start + size); +- break; +- case DMA_TO_DEVICE:/* writeback only */ +- dmac_clean_range(start, start + size); +- break; +- case DMA_BIDIRECTIONAL:/* writeback and invalidate */ +- dmac_flush_range(start, start + size); +- break; +- default: +- BUG(); +- } +-} ++#define NSS_CORE_DSB() dsb(sy) ++#define NSS_CORE_DMA_CACHE_MAINT(dev, start, size, dir) BUILD_BUG_ON_MSG(1, \ ++ "NSS_CORE_DMA_CACHE_MAINT is deprecated. Fix the code to use correct dma_sync_* API") + + #define NSS_DEVICE_IF_START NSS_PHYSICAL_IF_START + +diff --git a/nss_hal/ipq806x/nss_hal_pvt.c b/nss_hal/ipq806x/nss_hal_pvt.c +index 52d63b0..5375087 100644 +--- a/nss_hal/ipq806x/nss_hal_pvt.c ++++ b/nss_hal/ipq806x/nss_hal_pvt.c +@@ -474,10 +474,9 @@ static struct nss_platform_data *__nss_hal_of_get_pdata(struct platform_device * + /* + * Clear TCM memory used by this core + */ +- for (i = 0; i < resource_size(&res_vphys) ; i += 4) { ++ for (i = 0; i < resource_size(&res_vphys) ; i += 4) + nss_write_32(npd->vmap, i, 0); +- NSS_CORE_DMA_CACHE_MAINT((npd->vmap + i), 4, DMA_TO_DEVICE); +- } ++ + NSS_CORE_DSB(); + + /* +diff --git a/nss_hal/ipq807x/nss_hal_pvt.c b/nss_hal/ipq807x/nss_hal_pvt.c +index bb8f42f..733d7f1 100644 +--- a/nss_hal/ipq807x/nss_hal_pvt.c ++++ b/nss_hal/ipq807x/nss_hal_pvt.c +@@ -256,10 +256,9 @@ static struct nss_platform_data *__nss_hal_of_get_pdata(struct platform_device * + /* + * Clear TCM memory used by this core + */ +- for (i = 0; i < resource_size(&res_vphys) ; i += 4) { ++ for (i = 0; i < resource_size(&res_vphys) ; i += 4) + nss_write_32(npd->vmap, i, 0); +- NSS_CORE_DMA_CACHE_MAINT((npd->vmap + i), 4, DMA_TO_DEVICE); +- } ++ + NSS_CORE_DSB(); + + /* +diff --git a/nss_meminfo.c b/nss_meminfo.c +index 2255eae..d804524 100644 +--- a/nss_meminfo.c ++++ b/nss_meminfo.c +@@ -414,7 +414,6 @@ static bool nss_meminfo_init_block_lists(struct nss_ctx_instance *nss_ctx) + /* + * Flush the updated meminfo request. + */ +- NSS_CORE_DMA_CACHE_MAINT(r, sizeof(struct nss_meminfo_request), DMA_TO_DEVICE); + NSS_CORE_DSB(); + + /* +@@ -538,7 +537,7 @@ static bool nss_meminfo_configure_n2h_h2n_rings(struct nss_ctx_instance *nss_ctx + * Bring a fresh copy of if_map from memory in order to read it correctly. + */ + if_map = mem_ctx->if_map; +- NSS_CORE_DMA_CACHE_MAINT((void *)if_map, sizeof(struct nss_if_mem_map), DMA_FROM_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, mem_ctx->if_map_dma, sizeof(struct nss_if_mem_map), DMA_FROM_DEVICE); + NSS_CORE_DSB(); + + if_map->n2h_rings = NSS_N2H_RING_COUNT; +@@ -576,7 +575,7 @@ static bool nss_meminfo_configure_n2h_h2n_rings(struct nss_ctx_instance *nss_ctx + /* + * Flush the updated nss_if_mem_map. + */ +- NSS_CORE_DMA_CACHE_MAINT((void *)if_map, sizeof(struct nss_if_mem_map), DMA_TO_DEVICE); ++ dma_sync_single_for_device(nss_ctx->dev, mem_ctx->if_map_dma, sizeof(struct nss_if_mem_map), DMA_TO_DEVICE); + NSS_CORE_DSB(); + + return true; +diff --git a/nss_profiler.c b/nss_profiler.c +index 5717ac3..aadc7c9 100755 +--- a/nss_profiler.c ++++ b/nss_profiler.c +@@ -199,11 +199,12 @@ EXPORT_SYMBOL(nss_profile_dma_deregister_cb); + struct nss_profile_sdma_ctrl *nss_profile_dma_get_ctrl(struct nss_ctx_instance *nss_ctx) + { + struct nss_profile_sdma_ctrl *ctrl = nss_ctx->meminfo_ctx.sdma_ctrl; ++ int size = offsetof(struct nss_profile_sdma_ctrl, cidx); + if (!ctrl) { + return ctrl; + } + +- dmac_inv_range(ctrl, &ctrl->cidx); ++ dma_sync_single_for_device(nss_ctx->dev, (dma_addr_t) ctrl, size, DMA_FROM_DEVICE); + dsb(sy); + return ctrl; + } +-- +2.34.1 + diff --git a/qca/qca-nss-drv/patches/0005-nss-drv-add-support-for-kernel-5.15.patch b/qca/qca-nss-drv/patches/0005-nss-drv-add-support-for-kernel-5.15.patch new file mode 100644 index 000000000..0995e2a07 --- /dev/null +++ b/qca/qca-nss-drv/patches/0005-nss-drv-add-support-for-kernel-5.15.patch @@ -0,0 +1,70 @@ +From 6e65f6daecb09463688eaea0a234018a728196b8 Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Tue, 5 Apr 2022 18:10:57 +0200 +Subject: [PATCH 5/8] nss-drv: add support for kernel 5.15 + +- Fix coredump panic notifier include change. +- Fix skb ZEROCOPY flag. +- Add skb reuse support for 5.15 kernel version. + +Signed-off-by: Ansuel Smith +--- + nss_core.c | 5 +++-- + nss_coredump.c | 4 ++++ + nss_hal/nss_hal.c | 1 + + 3 files changed, 8 insertions(+), 2 deletions(-) + +diff --git a/nss_core.c b/nss_core.c +index f9e6014..8cd1d4b 100644 +--- a/nss_core.c ++++ b/nss_core.c +@@ -53,7 +53,8 @@ + (((LINUX_VERSION_CODE >= KERNEL_VERSION(3, 18, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 19, 0)))) || \ + (((LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(4, 5, 0)))) || \ + (((LINUX_VERSION_CODE >= KERNEL_VERSION(5, 4, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 5, 0)))) || \ +-(((LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 11, 0)))))) ++(((LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 11, 0)))) || \ ++(((LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 16, 0)))))) + #error "Check skb recycle code in this file to match Linux version" + #endif + +@@ -2623,7 +2624,7 @@ static inline bool nss_core_skb_can_reuse(struct nss_ctx_instance *nss_ctx, + if (unlikely(irqs_disabled())) + return false; + +- if (unlikely(skb_shinfo(nbuf)->tx_flags & SKBTX_DEV_ZEROCOPY)) ++ if (unlikely(skb_shinfo(nbuf)->flags & SKBFL_ZEROCOPY_ENABLE)) + return false; + + if (unlikely(skb_is_nonlinear(nbuf))) +diff --git a/nss_coredump.c b/nss_coredump.c +index ecad659..3ecef7e 100644 +--- a/nss_coredump.c ++++ b/nss_coredump.c +@@ -23,7 +23,11 @@ + #include "nss_hal.h" + #include "nss_log.h" + #include ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 14, 0)) + #include /* for panic_notifier_list */ ++#else ++#include ++#endif + #include /* for time */ + #include "nss_tx_rx_common.h" + +diff --git a/nss_hal/nss_hal.c b/nss_hal/nss_hal.c +index 57974c1..d8c703b 100644 +--- a/nss_hal/nss_hal.c ++++ b/nss_hal/nss_hal.c +@@ -24,6 +24,7 @@ + #include + #include + #include ++#include + + #include "nss_hal.h" + #include "nss_arch.h" +-- +2.34.1 + diff --git a/qca/qca-nss-drv/patches/0005-nss-drv-use-standard-skb_skip_tc_classify-instead-of.patch b/qca/qca-nss-drv/patches/0005-nss-drv-use-standard-skb_skip_tc_classify-instead-of.patch new file mode 100644 index 000000000..6e8b4cdfd --- /dev/null +++ b/qca/qca-nss-drv/patches/0005-nss-drv-use-standard-skb_skip_tc_classify-instead-of.patch @@ -0,0 +1,30 @@ +From 4dd701916186803172a9f35e7e982a953613ad55 Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Mon, 11 Apr 2022 21:32:41 +0200 +Subject: [PATCH 5/9] nss-drv: use standard skb_skip_tc_classify instead of + custom api + +Use skb_skip_tc_classify to skip classify for packet handled by nss +instead of custom api. + +Signed-off-by: Ansuel Smith +--- + nss_core.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/nss_core.c b/nss_core.c +index f9e6014..6ab8038 100644 +--- a/nss_core.c ++++ b/nss_core.c +@@ -1075,7 +1075,7 @@ static inline void nss_core_set_skb_classify(struct sk_buff *nbuf) + #if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0)) + nbuf->tc_verd = SET_TC_NCLS_NSS(nbuf->tc_verd); + #else +- skb_set_tc_classify_offload(nbuf); ++ skb_skip_tc_classify(nbuf); + #endif + #endif + } +-- +2.34.1 + diff --git a/qca/qca-nss-drv/patches/0008-Makefile-modularize-driver-even-more.patch b/qca/qca-nss-drv/patches/0008-Makefile-modularize-driver-even-more.patch new file mode 100644 index 000000000..eb7f27d06 --- /dev/null +++ b/qca/qca-nss-drv/patches/0008-Makefile-modularize-driver-even-more.patch @@ -0,0 +1,172 @@ +From 895de8e4119afe3cbad2aa81566b1ebcb2b39dcd Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Tue, 17 May 2022 20:23:19 +0200 +Subject: [PATCH] Makefile: modularize driver even more + +Permit to disable even more module. + +Signed-off-by: Ansuel Smith +--- + Makefile | 56 ++++++++++++++++++++++++++++++++--------------- + nss_hal/nss_hal.c | 6 +++++ + nss_init.c | 4 ++++ + 3 files changed, 48 insertions(+), 18 deletions(-) + +diff --git a/Makefile b/Makefile +index f5c4b90..0194dbd 100644 +--- a/Makefile ++++ b/Makefile +@@ -39,35 +39,55 @@ qca-nss-drv-objs := \ + nss_pm.o \ + nss_profiler.o \ + nss_project.o \ +- nss_pppoe.o \ +- nss_pppoe_log.o \ +- nss_pppoe_stats.o \ +- nss_pppoe_strings.o \ + nss_rps.o \ + nss_stats.o \ + nss_strings.o \ + nss_tx_msg_sync.o \ + nss_unaligned.o \ + nss_unaligned_log.o \ +- nss_unaligned_stats.o \ +- nss_virt_if.o \ +- nss_virt_if_stats.o \ +- nss_vlan.o \ +- nss_vlan_log.o \ +- nss_wifi.o \ +- nss_wifi_log.o \ +- nss_wifi_stats.o \ +- nss_wifi_vdev.o \ +- nss_wifili.o \ +- nss_wifili_log.o \ +- nss_wifili_stats.o \ +- nss_wifili_strings.o \ +- nss_wifi_mac_db.o ++ nss_unaligned_stats.o + + # Base NSS data plane/HAL support + qca-nss-drv-objs += nss_data_plane/nss_data_plane_common.o + qca-nss-drv-objs += nss_hal/nss_hal.o + ++ifneq "$(NSS_DRV_PPPOE_ENABLE)" "n" ++ccflags-y += -DNSS_DRV_PPPOE_ENABLE ++qca-nss-drv-objs += \ ++ nss_pppoe.o \ ++ nss_pppoe_log.o \ ++ nss_pppoe_stats.o \ ++ nss_pppoe_strings.o ++endif ++ ++ifneq "$(NSS_DRV_VIRT_IF_ENABLE)" "n" ++ccflags-y += -DNSS_DRV_VIRT_IF_ENABLE ++qca-nss-drv-objs += \ ++ nss_virt_if.o \ ++ nss_virt_if_stats.o ++endif ++ ++ifneq "$(NSS_DRV_VLAN_ENABLE)" "n" ++ccflags-y += -DNSS_DRV_VLAN_ENABLE ++qca-nss-drv-objs += \ ++ nss_vlan.o \ ++ nss_vlan_log.o ++endif ++ ++ifneq "$(NSS_DRV_WIFI_ENABLE)" "n" ++ccflags-y += -DNSS_DRV_WIFI_ENABLE ++qca-nss-drv-objs += \ ++ nss_wifi.o \ ++ nss_wifi_log.o \ ++ nss_wifi_stats.o \ ++ nss_wifi_vdev.o \ ++ nss_wifili.o \ ++ nss_wifili_log.o \ ++ nss_wifili_stats.o \ ++ nss_wifili_strings.o \ ++ nss_wifi_mac_db.o ++endif ++ + ifneq "$(NSS_DRV_BRIDGE_ENABLE)" "n" + ccflags-y += -DNSS_DRV_BRIDGE_ENABLE + qca-nss-drv-objs += \ +diff --git a/nss_hal/nss_hal.c b/nss_hal/nss_hal.c +index 7e9a044..c0051e4 100644 +--- a/nss_hal/nss_hal.c ++++ b/nss_hal/nss_hal.c +@@ -460,10 +460,12 @@ int nss_hal_probe(struct platform_device *nss_dev) + } + #endif + ++#ifdef NSS_DRV_PPPOE_ENABLE + if (npd->pppoe_enabled == NSS_FEATURE_ENABLED) { + nss_top->pppoe_handler_id = nss_dev->id; + nss_pppoe_register_handler(); + } ++#endif + + #ifdef NSS_DRV_PPE_ENABLE + if (npd->ppe_enabled == NSS_FEATURE_ENABLED) { +@@ -558,6 +560,7 @@ int nss_hal_probe(struct platform_device *nss_dev) + } + #endif + ++#ifdef NSS_DRV_WIFI_ENABLE + if (npd->wifioffload_enabled == NSS_FEATURE_ENABLED) { + nss_top->wifi_handler_id = nss_dev->id; + nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_VAP] = nss_dev->id; +@@ -585,6 +588,7 @@ int nss_hal_probe(struct platform_device *nss_dev) + */ + nss_wifili_thread_scheme_db_init(nss_dev->id); + } ++#endif + + #ifdef NSS_DRV_OAM_ENABLE + if (npd->oam_enabled == NSS_FEATURE_ENABLED) { +@@ -601,11 +605,13 @@ int nss_hal_probe(struct platform_device *nss_dev) + } + #endif + ++#ifdef NSS_DRV_VLAN_ENABLE + if (npd->vlan_enabled == NSS_FEATURE_ENABLED) { + nss_top->vlan_handler_id = nss_dev->id; + nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_VLAN] = nss_dev->id; + nss_vlan_register_handler(); + } ++#endif + + #ifdef NSS_DRV_QVPN_ENABLE + #if defined(NSS_HAL_IPQ807x_SUPPORT) || defined(NSS_HAL_IPQ60XX_SUPPORT) +diff --git a/nss_init.c b/nss_init.c +index ebd2a12..40e9351 100644 +--- a/nss_init.c ++++ b/nss_init.c +@@ -775,10 +775,12 @@ static int __init nss_init(void) + */ + nss_project_register_sysctl(); + ++#ifdef NSS_DRV_PPPOE_ENABLE + /* + * Registering sysctl for pppoe specific config. + */ + nss_pppoe_register_sysctl(); ++#endif + + /* + * Setup Runtime Sample values +@@ -913,10 +915,12 @@ static void __exit nss_cleanup(void) + nss_c2c_tx_unregister_sysctl(); + #endif + ++#ifdef NSS_DRV_PPPOE_ENABLE + /* + * Unregister pppoe specific sysctl + */ + nss_pppoe_unregister_sysctl(); ++#endif + + /* + * Unregister ipv4/6 specific sysctl and free allocated to connection tables +-- +2.34.1 + diff --git a/qca/qca-nss-ecm/Makefile b/qca/qca-nss-ecm/Makefile new file mode 100644 index 000000000..ceedc1988 --- /dev/null +++ b/qca/qca-nss-ecm/Makefile @@ -0,0 +1,97 @@ +include $(TOPDIR)/rules.mk + +PKG_NAME:=qca-nss-ecm +PKG_RELEASE:=$(AUTORELEASE) + +PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/qca-nss-ecm.git +PKG_SOURCE_PROTO:=git +PKG_SOURCE_DATE:=2021-06-15 +PKG_SOURCE_VERSION:=34267065855d32f33264dc3054efb0e8103d627b +PKG_MIRROR_HASH:=0917659d69c5f3e6067d6671b9393b4b2d6b6cd5a7bacf5e7d6cf842dc906eca + +PKG_BUILD_PARALLEL:=1 + +include $(INCLUDE_DIR)/kernel.mk +include $(INCLUDE_DIR)/package.mk + +define KernelPackage/qca-nss-ecm + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Support + DEPENDS:=@LINUX_5_10 @(TARGET_ipq807x||TARGET_ipq60xx) \ + +kmod-qca-nss-drv \ + +iptables-mod-extra \ + +kmod-ipt-conntrack \ + +kmod-ipt-physdev \ + +iptables-mod-physdev \ + +kmod-ppp \ + +kmod-pppoe + TITLE:=QCA NSS Enhanced Connection Manager (ECM) + FILES:=$(PKG_BUILD_DIR)/*.ko + KCONFIG:=CONFIG_BRIDGE_NETFILTER=y \ + CONFIG_NF_CONNTRACK_EVENTS=y \ + CONFIG_NF_CONNTRACK_CHAIN_EVENTS=n \ + CONFIG_NF_CONNTRACK_DSCPREMARK_EXT=n +endef + +define KernelPackage/qca-nss-ecm/Description +This package contains the QCA NSS Enhanced Connection Manager +endef + +define KernelPackage/qca-nss-ecm/install + $(INSTALL_DIR) $(1)/etc/firewall.d $(1)/etc/init.d $(1)/usr/bin $(1)/lib/netifd/offload $(1)/etc/config $(1)/etc/uci-defaults $(1)/etc/sysctl.d + $(INSTALL_DATA) ./files/qca-nss-ecm.firewall $(1)/etc/firewall.d/qca-nss-ecm + $(INSTALL_BIN) ./files/qca-nss-ecm.init $(1)/etc/init.d/qca-nss-ecm + $(INSTALL_BIN) ./files/ecm_dump.sh $(1)/usr/bin/ + $(INSTALL_BIN) ./files/on-demand-down $(1)/lib/netifd/offload/on-demand-down + $(INSTALL_DATA) ./files/qca-nss-ecm.uci $(1)/etc/config/ecm + $(INSTALL_DATA) ./files/qca-nss-ecm.defaults $(1)/etc/uci-defaults/99-qca-nss-ecm + $(INSTALL_BIN) ./files/qca-nss-ecm.sysctl $(1)/etc/sysctl.d/qca-nss-ecm.conf + echo 'net.netfilter.nf_conntrack_max=8192' >> $(1)/etc/sysctl.d/qca-nss-ecm.conf +endef + +EXTRA_CFLAGS+=-I$(STAGING_DIR)/usr/include/qca-nss-drv + +ifneq (, $(findstring $(CONFIG_TARGET_BOARD), "ipq807x" "ipq60xx")) +ECM_MAKE_OPTS+= ECM_FRONT_END_NSS_ENABLE=y \ + ECM_CLASSIFIER_HYFI_ENABLE=n \ + ECM_MULTICAST_ENABLE=n \ + ECM_INTERFACE_IPSEC_ENABLE=n \ + ECM_INTERFACE_PPTP_ENABLE=n \ + ECM_INTERFACE_L2TPV2_ENABLE=n \ + ECM_INTERFACE_GRE_TAP_ENABLE=n \ + ECM_INTERFACE_GRE_TUN_ENABLE=n \ + ECM_INTERFACE_SIT_ENABLE=n \ + ECM_INTERFACE_TUNIPIP6_ENABLE=n \ + ECM_INTERFACE_RAWIP_ENABLE=n \ + ECM_INTERFACE_VLAN_ENABLE=n \ + ECM_CLASSIFIER_MARK_ENABLE=n \ + ECM_CLASSIFIER_DSCP_ENABLE=n \ + ECM_CLASSIFIER_PCC_ENABLE=n \ + ECM_BAND_STEERING_ENABLE=n \ + ECM_INTERFACE_PPPOE_ENABLE=y +endif + +ifeq ($(CONFIG_TARGET_BOARD), "ipq807x") + SOC="ipq807x_64" +else ifeq ($(CONFIG_TARGET_BOARD), "ipq60xx") + SOC="ipq60xx_64" +endif + +define Build/InstallDev + mkdir -p $(1)/usr/include/qca-nss-ecm + $(CP) $(PKG_BUILD_DIR)/exports/* $(1)/usr/include/qca-nss-ecm +endef + +define Build/Compile + +$(MAKE) -C "$(LINUX_DIR)" $(strip $(ECM_MAKE_OPTS)) \ + CROSS_COMPILE="$(TARGET_CROSS)" \ + ARCH="$(LINUX_KARCH)" \ + M="$(PKG_BUILD_DIR)" \ + EXTRA_CFLAGS="$(EXTRA_CFLAGS)" SoC=$(SOC) \ + $(KERNEL_MAKE_FLAGS) \ + $(PKG_JOBS) \ + modules +endef + +$(eval $(call KernelPackage,qca-nss-ecm)) diff --git a/qca/qca-nss-ecm/files/ecm_dump.sh b/qca/qca-nss-ecm/files/ecm_dump.sh new file mode 100644 index 000000000..dbf7de753 --- /dev/null +++ b/qca/qca-nss-ecm/files/ecm_dump.sh @@ -0,0 +1,95 @@ +#!/bin/sh +# +# Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +# + +ECM_MODULE=${1:-ecm_state} +MOUNT_ROOT=/dev/ecm + +# +# usage: ecm_dump.sh [module=ecm_db] +# +# with no parameters, ecm_dump.sh will attempt to mount the +# ecm_db state file and cat its contents. +# +# example with a parameter: ecm_dump.sh ecm_classifier_default +# +# this will cause ecm_dump to attempt to find and mount the state +# file for the ecm_classifier_default module, and if successful +# cat the contents. +# + +# this is one of the state files, which happens to be the +# last module started in ecm +ECM_STATE=/sys/kernel/debug/ecm/ecm_state/state_dev_major + +# tests to see if ECM is up and ready to receive commands. +# returns 0 if ECM is fully up and ready, else 1 +ecm_is_ready() { + if [ ! -e "${ECM_STATE}" ] + then + return 1 + fi + return 0 +} + +# +# module_state_mount(module_name) +# Mounts the state file of the module, if supported +# +module_state_mount() { + local module_name=$1 + local mount_dir=$2 + local state_file="/sys/kernel/debug/ecm/${module_name}/state_dev_major" + + if [ -e "${mount_dir}/${module_name}" ] + then + # already mounted + return 0 + fi + + #echo "Mount state file for $module_name ..." + if [ ! -e "$state_file" ] + then + #echo "... $module_name does not support state" + return 1 + fi + + local major="`cat $state_file`" + #echo "... Mounting state $state_file with major: $major" + mknod "${mount_dir}/${module_name}" c $major 0 +} + +# +# main +# +ecm_is_ready || { + #echo "ECM is not running" + exit 1 +} + +# all state files are mounted under MOUNT_ROOT, so make sure it exists +mkdir -p ${MOUNT_ROOT} + +# +# attempt to mount state files for the requested module and cat it +# if the mount succeeded +# +module_state_mount ${ECM_MODULE} ${MOUNT_ROOT} && { + cat ${MOUNT_ROOT}/${ECM_MODULE} + exit 0 +} + +exit 2 diff --git a/qca/qca-nss-ecm/files/on-demand-down b/qca/qca-nss-ecm/files/on-demand-down new file mode 100644 index 000000000..02d708e03 --- /dev/null +++ b/qca/qca-nss-ecm/files/on-demand-down @@ -0,0 +1,6 @@ +#!/bin/sh +# Copyright (c) 2016 The Linux Foundation. All rights reserved. + +[ -e "/sys/kernel/debug/ecm/ecm_db/defunct_all" ] && { + echo 1 > /sys/kernel/debug/ecm/ecm_db/defunct_all +} diff --git a/qca/qca-nss-ecm/files/qca-nss-ecm.defaults b/qca/qca-nss-ecm/files/qca-nss-ecm.defaults new file mode 100644 index 000000000..308e265c9 --- /dev/null +++ b/qca/qca-nss-ecm/files/qca-nss-ecm.defaults @@ -0,0 +1,28 @@ +#!/bin/sh +# +# Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +# + +uci -q batch << EOF + delete firewall.qcanssecm + set firewall.qcanssecm=include + set firewall.qcanssecm.type=script + set firewall.qcanssecm.path=/etc/firewall.d/qca-nss-ecm + set firewall.qcanssecm.family=any + set firewall.qcanssecm.reload=1 + commit firewall +EOF + +exit 0 diff --git a/qca/qca-nss-ecm/files/qca-nss-ecm.firewall b/qca/qca-nss-ecm/files/qca-nss-ecm.firewall new file mode 100644 index 000000000..24c64def2 --- /dev/null +++ b/qca/qca-nss-ecm/files/qca-nss-ecm.firewall @@ -0,0 +1,18 @@ +#!/bin/sh +# +# Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +# + +iptables -A FORWARD -m physdev --physdev-is-bridged -j ACCEPT diff --git a/qca/qca-nss-ecm/files/qca-nss-ecm.init b/qca/qca-nss-ecm/files/qca-nss-ecm.init new file mode 100644 index 000000000..e64f077bb --- /dev/null +++ b/qca/qca-nss-ecm/files/qca-nss-ecm.init @@ -0,0 +1,142 @@ +#!/bin/sh /etc/rc.common +# +# Copyright (c) 2014, 2019-2020 The Linux Foundation. All rights reserved. +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +# The shebang above has an extra space intentially to avoid having +# openwrt build scripts automatically enable this package starting +# at boot. + +START=19 + +get_front_end_mode() { + config_load "ecm" + config_get front_end global acceleration_engine "auto" + + case $front_end in + auto) + echo '0' + ;; + nss) + echo '1' + ;; + sfe) + echo '2' + ;; + *) + echo 'uci_option_acceleration_engine is invalid' + esac +} + +support_bridge() { + #NSS support bridge acceleration + [ -d /sys/kernel/debug/ecm/ecm_nss_ipv4 ] && return 0 + #SFE doesn't support bridge acceleration + [ -d /sys/kernel/debug/ecm/ecm_sfe_ipv4 ] && return 1 +} + +load_sfe() { + local kernel_version=$(uname -r) + + [ -e "/lib/modules/$kernel_version/shortcut-fe.ko" ] && { + [ -d /sys/module/shortcut_fe ] || insmod shortcut-fe + } + + [ -e "/lib/modules/$kernel_version/shortcut-fe-ipv6.ko" ] && { + [ -d /sys/module/shortcut_fe_ipv6 ] || insmod shortcut-fe-ipv6 + } + + [ -e "/lib/modules/$kernel_version/shortcut-fe-drv.ko" ] && { + [ -d /sys/module/shortcut_fe_drv ] || insmod shortcut-fe-drv + } +} + +load_ecm() { + [ -d /sys/module/ecm ] || { + [ ! -e /proc/device-tree/MP_256 ] && load_sfe + insmod ecm front_end_selection=$(get_front_end_mode) + } + + support_bridge && { + sysctl -w net.bridge.bridge-nf-call-ip6tables=1 + sysctl -w net.bridge.bridge-nf-call-iptables=1 + } +} + +unload_ecm() { + sysctl -w net.bridge.bridge-nf-call-ip6tables=0 + sysctl -w net.bridge.bridge-nf-call-iptables=0 + + if [ -d /sys/module/ecm ]; then + # + # Stop ECM frontends + # + echo 1 > /sys/kernel/debug/ecm/front_end_ipv4_stop + echo 1 > /sys/kernel/debug/ecm/front_end_ipv6_stop + + # + # Defunct the connections + # + echo 1 > /sys/kernel/debug/ecm/ecm_db/defunct_all + sleep 5; + + rmmod ecm + sleep 1 + fi +} + +start() { + # If SFE CM is loaded, return. + if [ -d /sys/module/shortcut_fe_cm ]; then + echo "shortcut_fe CM is loaded, unload it first" + echo "cmd: /etc/init.d/shortcut_fe stop" + return + fi + + load_ecm + + # If the acceleration engine is NSS, enable wifi redirect. + [ -d /sys/kernel/debug/ecm/ecm_nss_ipv4 ] && sysctl -w dev.nss.general.redirect=1 + + support_bridge && { + if ([ -z "$(grep "net.bridge.bridge-nf-call-ip6tables=1" /etc/sysctl.d/qca-nss-ecm.conf)" ] && [ -z "$(grep "net.bridge.bridge-nf-call-iptables=1" /etc/sysctl.d/qca-nss-ecm.conf)" ]); then + echo 'net.bridge.bridge-nf-call-ip6tables=1' >> /etc/sysctl.d/qca-nss-ecm.conf + echo 'net.bridge.bridge-nf-call-iptables=1' >> /etc/sysctl.d/qca-nss-ecm.conf + fi + } + + if [ -d /sys/module/qca_ovsmgr ]; then + insmod ecm_ovs + fi + +} + +stop() { + # If ECM is already not loaded, just return. + if [ ! -d /sys/module/ecm ]; then + return + fi + + # If the acceleration engine is NSS, disable wifi redirect. + [ -d /sys/kernel/debug/ecm/ecm_nss_ipv4 ] && sysctl -w dev.nss.general.redirect=0 + + sed '/net.bridge.bridge-nf-call-ip6tables=1/d' -i /etc/sysctl.d/qca-nss-ecm.conf + sed '/net.bridge.bridge-nf-call-iptables=1/d' -i /etc/sysctl.d/qca-nss-ecm.conf + + if [ -d /sys/module/ecm_ovs ]; then + rmmod ecm_ovs + fi + + unload_ecm +} diff --git a/qca/qca-nss-ecm/files/qca-nss-ecm.sysctl b/qca/qca-nss-ecm/files/qca-nss-ecm.sysctl new file mode 100644 index 000000000..1a3d76b18 --- /dev/null +++ b/qca/qca-nss-ecm/files/qca-nss-ecm.sysctl @@ -0,0 +1,2 @@ +# nf_conntrack_tcp_no_window_check is 0 by default, set it to 1 +net.netfilter.nf_conntrack_tcp_no_window_check=1 diff --git a/qca/qca-nss-ecm/files/qca-nss-ecm.uci b/qca/qca-nss-ecm/files/qca-nss-ecm.uci new file mode 100644 index 000000000..4f2de6877 --- /dev/null +++ b/qca/qca-nss-ecm/files/qca-nss-ecm.uci @@ -0,0 +1,2 @@ +config ecm 'global' + option acceleration_engine 'auto' diff --git a/qca/qca-nss-ecm/patches/001-treewide-componentize-the-module-even-more.patch b/qca/qca-nss-ecm/patches/001-treewide-componentize-the-module-even-more.patch new file mode 100644 index 000000000..4e7932c9d --- /dev/null +++ b/qca/qca-nss-ecm/patches/001-treewide-componentize-the-module-even-more.patch @@ -0,0 +1,335 @@ +From 73345c87b28a473b35b57e673f8de963c3d73da1 Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Wed, 19 May 2021 02:38:53 +0200 +Subject: [PATCH] treewide: componentize the module even more + +Signed-off-by: Ansuel Smith +--- + Makefile | 56 +++++++++++++++++++++++++------- + ecm_db/ecm_db_connection.c | 8 +++++ + ecm_db/ecm_db_node.c | 4 +++ + ecm_interface.c | 8 +++++ + frontends/ecm_front_end_common.c | 7 ++++ + 5 files changed, 72 insertions(+), 11 deletions(-) + +--- a/Makefile ++++ b/Makefile +@@ -82,10 +82,18 @@ ccflags-$(ECM_INTERFACE_BOND_ENABLE) += + # Define ECM_INTERFACE_PPPOE_ENABLE=y in order + # to enable support for PPPoE acceleration. + # ############################################################################# +-ECM_INTERFACE_PPPOE_ENABLE=y ++ifndef $(ECM_INTERFACE_PPPOE_ENABLE) ++ ECM_INTERFACE_PPPOE_ENABLE=y ++endif + ccflags-$(ECM_INTERFACE_PPPOE_ENABLE) += -DECM_INTERFACE_PPPOE_ENABLE + + # ############################################################################# ++# Define ECM_INTERFACE_L2TPV2_PPTP_ENABLE=y in order ++# to enable support for l2tpv2 or PPTP detection. ++# ############################################################################# ++ccflags-$(ECM_INTERFACE_L2TPV2_PPTP_ENABLE) += -DECM_INTERFACE_L2TPV2_PPTP_ENABLE ++ ++# ############################################################################# + # Define ECM_INTERFACE_L2TPV2_ENABLE=y in order + # to enable support for l2tpv2 acceleration. + # ############################################################################# +@@ -118,6 +126,12 @@ ccflags-$(ECM_INTERFACE_PPP_ENABLE) += - + ccflags-$(ECM_INTERFACE_MAP_T_ENABLE) += -DECM_INTERFACE_MAP_T_ENABLE + + # ############################################################################# ++# Define ECM_INTERFACE_GRE_ENABLE=y in order ++# to enable support for GRE detection. ++# ############################################################################# ++ccflags-$(ECM_INTERFACE_GRE_ENABLE) += -DECM_INTERFACE_GRE_ENABLE ++ ++# ############################################################################# + # Define ECM_INTERFACE_GRE_TAP_ENABLE=y in order + # to enable support for GRE TAP interface. + # ############################################################################# +@@ -186,7 +200,9 @@ ccflags-$(ECM_INTERFACE_OVS_BRIDGE_ENABL + # ############################################################################# + # Define ECM_INTERFACE_VLAN_ENABLE=y in order to enable support for VLAN + # ############################################################################# +-ECM_INTERFACE_VLAN_ENABLE=y ++ifndef $(ECM_INTERFACE_VLAN_ENABLE) ++ ECM_INTERFACE_VLAN_ENABLE=y ++endif + ccflags-$(ECM_INTERFACE_VLAN_ENABLE) += -DECM_INTERFACE_VLAN_ENABLE + + # ############################################################################# +@@ -228,7 +244,9 @@ ccflags-$(ECM_CLASSIFIER_OVS_ENABLE) += + # ############################################################################# + # Define ECM_CLASSIFIER_MARK_ENABLE=y in order to enable mark classifier. + # ############################################################################# +-ECM_CLASSIFIER_MARK_ENABLE=y ++ifndef $(ECM_CLASSIFIER_MARK_ENABLE) ++ ECM_CLASSIFIER_MARK_ENABLE=y ++endif + ecm-$(ECM_CLASSIFIER_MARK_ENABLE) += ecm_classifier_mark.o + ccflags-$(ECM_CLASSIFIER_MARK_ENABLE) += -DECM_CLASSIFIER_MARK_ENABLE + +@@ -247,7 +265,9 @@ ccflags-$(ECM_CLASSIFIER_NL_ENABLE) += - + # ############################################################################# + # Define ECM_CLASSIFIER_DSCP_ENABLE=y in order to enable DSCP classifier. + # ############################################################################# +-ECM_CLASSIFIER_DSCP_ENABLE=y ++ifndef $(ECM_CLASSIFIER_DSCP_ENABLE) ++ ECM_CLASSIFIER_DSCP_ENABLE=y ++endif + ecm-$(ECM_CLASSIFIER_DSCP_ENABLE) += ecm_classifier_dscp.o + ccflags-$(ECM_CLASSIFIER_DSCP_ENABLE) += -DECM_CLASSIFIER_DSCP_ENABLE + ccflags-$(ECM_CLASSIFIER_DSCP_IGS) += -DECM_CLASSIFIER_DSCP_IGS +@@ -274,7 +294,9 @@ endif + # the Parental Controls subsystem classifier in ECM. Currently disabled until + # customers require it / if they need to integrate their Parental Controls with it. + # ############################################################################# +-ECM_CLASSIFIER_PCC_ENABLE=y ++ifndef $(ECM_CLASSIFIER_PCC_ENABLE) ++ ECM_CLASSIFIER_PCC_ENABLE=y ++endif + ecm-$(ECM_CLASSIFIER_PCC_ENABLE) += ecm_classifier_pcc.o + ccflags-$(ECM_CLASSIFIER_PCC_ENABLE) += -DECM_CLASSIFIER_PCC_ENABLE + +@@ -301,28 +323,36 @@ ccflags-$(ECM_NON_PORTED_SUPPORT_ENABLE) + # ############################################################################# + # Define ECM_STATE_OUTPUT_ENABLE=y to support XML state output + # ############################################################################# +-ECM_STATE_OUTPUT_ENABLE=y ++ifndef $(ECM_STATE_OUTPUT_ENABLE) ++ ECM_STATE_OUTPUT_ENABLE=y ++endif + ecm-$(ECM_STATE_OUTPUT_ENABLE) += ecm_state.o + ccflags-$(ECM_STATE_OUTPUT_ENABLE) += -DECM_STATE_OUTPUT_ENABLE + + # ############################################################################# + # Define ECM_DB_ADVANCED_STATS_ENABLE to support XML state output + # ############################################################################# +-ECM_DB_ADVANCED_STATS_ENABLE=y ++ifndef $(ECM_DB_ADVANCED_STATS_ENABLE) ++ ECM_DB_ADVANCED_STATS_ENABLE=y ++endif + ccflags-$(ECM_DB_ADVANCED_STATS_ENABLE) += -DECM_DB_ADVANCED_STATS_ENABLE + + # ############################################################################# + # Define ECM_DB_CONNECTION_CROSS_REFERENCING_ENABLE=y in order to enable + # the database to track relationships between objects. + # ############################################################################# +-ECM_DB_CONNECTION_CROSS_REFERENCING_ENABLE=y ++ifndef $(ECM_DB_CONNECTION_CROSS_REFERENCING_ENABLE) ++ ECM_DB_CONNECTION_CROSS_REFERENCING_ENABLE=y ++endif + ccflags-$(ECM_DB_CONNECTION_CROSS_REFERENCING_ENABLE) += -DECM_DB_XREF_ENABLE + + # ############################################################################# + # Define ECM_TRACKER_DPI_SUPPORT_ENABLE=y in order to enable support for + # deep packet inspection and tracking of data with the trackers. + # ############################################################################# +-ECM_TRACKER_DPI_SUPPORT_ENABLE=y ++ifndef $(ECM_TRACKER_DPI_SUPPORT_ENABLE) ++ ECM_TRACKER_DPI_SUPPORT_ENABLE=y ++endif + ccflags-$(ECM_TRACKER_DPI_SUPPORT_ENABLE) += -DECM_TRACKER_DPI_SUPPORT_ENABLE + + # ############################################################################# +@@ -330,14 +360,18 @@ ccflags-$(ECM_TRACKER_DPI_SUPPORT_ENABLE + # support for the database keeping lists of connections that are assigned + # on a per TYPE of classifier basis. + # ############################################################################# +-ECM_DB_CLASSIFIER_TYPE_ASSIGNMENTS_TRACK_ENABLE=y ++ifndef $(ECM_DB_CLASSIFIER_TYPE_ASSIGNMENTS_TRACK_ENABLE) ++ ECM_DB_CLASSIFIER_TYPE_ASSIGNMENTS_TRACK_ENABLE=y ++endif + ccflags-$(ECM_DB_CLASSIFIER_TYPE_ASSIGNMENTS_TRACK_ENABLE) += -DECM_DB_CTA_TRACK_ENABLE + + # ############################################################################# + # Define ECM_BAND_STEERING_ENABLE=y in order to enable + # band steering feature. + # ############################################################################# +-ECM_BAND_STEERING_ENABLE=y ++ifndef $(ECM_BAND_STEERING_ENABLE) ++ ECM_BAND_STEERING_ENABLE=y ++endif + ccflags-$(ECM_BAND_STEERING_ENABLE) += -DECM_BAND_STEERING_ENABLE + + # ############################################################################# +--- a/ecm_db/ecm_db_connection.c ++++ b/ecm_db/ecm_db_connection.c +@@ -430,7 +430,9 @@ EXPORT_SYMBOL(ecm_db_connection_make_def + */ + void ecm_db_connection_data_totals_update(struct ecm_db_connection_instance *ci, bool is_from, uint64_t size, uint64_t packets) + { ++#ifdef ECM_DB_ADVANCED_STATS_ENABLE + int32_t i; ++#endif + + DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed\n", ci); + +@@ -529,7 +531,9 @@ EXPORT_SYMBOL(ecm_db_connection_data_tot + */ + void ecm_db_connection_data_totals_update_dropped(struct ecm_db_connection_instance *ci, bool is_from, uint64_t size, uint64_t packets) + { ++#ifdef ECM_DB_ADVANCED_STATS_ENABLE + int32_t i; ++#endif + + DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed\n", ci); + +@@ -1508,6 +1512,7 @@ void ecm_db_connection_defunct_all(void) + } + EXPORT_SYMBOL(ecm_db_connection_defunct_all); + ++#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE + /* + * ecm_db_connection_defunct_by_classifier() + * Make defunct based on masked fields +@@ -1667,6 +1672,7 @@ next_ci: + ECM_IP_ADDR_TO_OCTAL(dest_addr_mask), dest_port_mask, proto_mask, cnt); + } + } ++#endif + + /* + * ecm_db_connection_defunct_by_port() +@@ -1956,6 +1962,7 @@ struct ecm_db_node_instance *ecm_db_conn + } + EXPORT_SYMBOL(ecm_db_connection_node_get_and_ref); + ++#ifdef ECM_DB_XREF_ENABLE + /* + * ecm_db_connection_mapping_get_and_ref_next() + * Return reference to next connection in the mapping chain in the specified direction. +@@ -1997,6 +2004,7 @@ struct ecm_db_connection_instance *ecm_d + return nci; + } + EXPORT_SYMBOL(ecm_db_connection_iface_get_and_ref_next); ++#endif + + /* + * ecm_db_connection_mapping_get_and_ref() +--- a/ecm_db/ecm_db_node.c ++++ b/ecm_db/ecm_db_node.c +@@ -224,9 +224,11 @@ EXPORT_SYMBOL(ecm_db_node_get_and_ref_ne + */ + int ecm_db_node_deref(struct ecm_db_node_instance *ni) + { ++#ifdef ECM_DB_XREF_ENABLE + #if (DEBUG_LEVEL >= 1) + int dir; + #endif ++#endif + DEBUG_CHECK_MAGIC(ni, ECM_DB_NODE_INSTANCE_MAGIC, "%px: magic failed\n", ni); + + spin_lock_bh(&ecm_db_lock); +@@ -486,9 +488,11 @@ EXPORT_SYMBOL(ecm_db_node_iface_get_and_ + void ecm_db_node_add(struct ecm_db_node_instance *ni, struct ecm_db_iface_instance *ii, uint8_t *address, + ecm_db_node_final_callback_t final, void *arg) + { ++#ifdef ECM_DB_XREF_ENABLE + #if (DEBUG_LEVEL >= 1) + int dir; + #endif ++#endif + ecm_db_node_hash_t hash_index; + struct ecm_db_listener_instance *li; + +--- a/ecm_interface.c ++++ b/ecm_interface.c +@@ -1343,6 +1343,7 @@ struct neighbour *ecm_interface_ipv6_nei + */ + bool ecm_interface_is_pptp(struct sk_buff *skb, const struct net_device *out) + { ++#ifdef ECM_INTERFACE_PPTP_ENABLE + struct net_device *in; + + /* +@@ -1367,6 +1368,7 @@ bool ecm_interface_is_pptp(struct sk_buf + } + + dev_put(in); ++#endif + return false; + } + +@@ -1379,6 +1381,7 @@ bool ecm_interface_is_pptp(struct sk_buf + */ + bool ecm_interface_is_l2tp_packet_by_version(struct sk_buff *skb, const struct net_device *out, int ver) + { ++#ifdef ECM_INTERFACE_L2TPV2_PPTP_ENABLE + uint32_t flag = 0; + struct net_device *in; + +@@ -1411,6 +1414,7 @@ bool ecm_interface_is_l2tp_packet_by_ver + } + + dev_put(in); ++#endif + return false; + } + +@@ -1423,6 +1427,7 @@ bool ecm_interface_is_l2tp_packet_by_ver + */ + bool ecm_interface_is_l2tp_pptp(struct sk_buff *skb, const struct net_device *out) + { ++#ifdef ECM_INTERFACE_L2TPV2_PPTP_ENABLE + struct net_device *in; + + /* +@@ -1445,6 +1450,7 @@ bool ecm_interface_is_l2tp_pptp(struct s + } + + dev_put(in); ++#endif + return false; + } + +@@ -6630,6 +6636,7 @@ static void ecm_interface_regenerate_con + return; + } + ++#ifdef ECM_DB_XREF_ENABLE + for (dir = 0; dir < ECM_DB_OBJ_DIR_MAX; dir++) { + /* + * Re-generate all connections associated with this interface +@@ -6645,6 +6652,7 @@ static void ecm_interface_regenerate_con + ci[dir] = cin; + } + } ++#endif + + #ifdef ECM_MULTICAST_ENABLE + /* +--- a/frontends/ecm_front_end_common.c ++++ b/frontends/ecm_front_end_common.c +@@ -106,6 +106,7 @@ bool ecm_front_end_gre_proto_is_accel_al + struct nf_conntrack_tuple *tuple, + int ip_version) + { ++#ifdef ECM_INTERFACE_GRE_ENABLE + struct net_device *dev; + struct gre_base_hdr *greh; + +@@ -117,10 +118,12 @@ bool ecm_front_end_gre_proto_is_accel_al + /* + * Case 1: PPTP locally terminated + */ ++#ifdef ECM_INTERFACE_PPTP_ENABLE + if (ecm_interface_is_pptp(skb, outdev)) { + DEBUG_TRACE("%px: PPTP GRE locally terminated - allow acceleration\n", skb); + return true; + } ++#endif + + /* + * Case 2: PPTP pass through +@@ -223,6 +226,10 @@ bool ecm_front_end_gre_proto_is_accel_al + */ + DEBUG_TRACE("%px: GRE IPv%d pass through - allow acceleration\n", skb, ip_version); + return true; ++#else ++ DEBUG_TRACE("%px: GRE%d feature is disabled - do not allow acceleration\n", skb, ip_version); ++ return false; ++#endif + } + + #ifdef ECM_CLASSIFIER_DSCP_ENABLE diff --git a/qca/qca-nss-ecm/patches/100-kernel-5.10-support.patch b/qca/qca-nss-ecm/patches/100-kernel-5.10-support.patch new file mode 100644 index 000000000..3729dd3b9 --- /dev/null +++ b/qca/qca-nss-ecm/patches/100-kernel-5.10-support.patch @@ -0,0 +1,831 @@ +From e8b642c23af9146c973e828a7f4e0fb56cfc8d0b Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Sat, 15 May 2021 03:51:14 +0200 +Subject: [PATCH] add support for kernel 5.10 + +Signed-off-by: Ansuel Smith +--- + ecm_classifier_default.c | 24 +++--------- + ecm_classifier_dscp.c | 8 +--- + ecm_classifier_emesh.c | 16 ++------ + ecm_classifier_hyfi.c | 7 +--- + ecm_classifier_mark.c | 8 +--- + ecm_classifier_ovs.c | 8 +--- + ecm_classifier_pcc.c | 8 +--- + ecm_conntrack_notifier.c | 8 +--- + ecm_db/ecm_db_connection.c | 7 +--- + ecm_db/ecm_db_host.c | 7 +--- + ecm_db/ecm_db_iface.c | 7 +--- + ecm_db/ecm_db_mapping.c | 7 +--- + ecm_db/ecm_db_node.c | 7 +--- + ecm_interface.c | 4 +- + ecm_state.c | 14 ++----- + frontends/ecm_front_end_common.c | 4 +- + frontends/ecm_front_end_ipv4.c | 7 +--- + frontends/ecm_front_end_ipv6.c | 7 +--- + frontends/nss/ecm_nss_bond_notifier.c | 8 +--- + frontends/nss/ecm_nss_ipv4.c | 49 +++++++------------------ + frontends/nss/ecm_nss_ipv6.c | 49 +++++++------------------ + frontends/nss/ecm_nss_multicast_ipv4.c | 7 +--- + frontends/nss/ecm_nss_multicast_ipv6.c | 7 +--- + frontends/nss/ecm_nss_non_ported_ipv4.c | 7 +--- + frontends/nss/ecm_nss_non_ported_ipv6.c | 7 +--- + frontends/nss/ecm_nss_ported_ipv4.c | 8 +--- + frontends/nss/ecm_nss_ported_ipv6.c | 8 +--- + frontends/sfe/ecm_sfe_ipv4.c | 49 +++++++------------------ + frontends/sfe/ecm_sfe_ipv6.c | 49 +++++++------------------ + frontends/sfe/ecm_sfe_non_ported_ipv4.c | 7 +--- + frontends/sfe/ecm_sfe_non_ported_ipv6.c | 7 +--- + frontends/sfe/ecm_sfe_ported_ipv4.c | 8 +--- + frontends/sfe/ecm_sfe_ported_ipv6.c | 8 +--- + 33 files changed, 122 insertions(+), 314 deletions(-) + +--- a/ecm_classifier_default.c ++++ b/ecm_classifier_default.c +@@ -776,26 +776,14 @@ int ecm_classifier_default_init(struct d + return -1; + } + +- if (!debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_default_dentry, +- (u32 *)&ecm_classifier_default_enabled)) { +- DEBUG_ERROR("Failed to create ecm deafult classifier enabled file in debugfs\n"); +- debugfs_remove_recursive(ecm_classifier_default_dentry); +- return -1; +- } ++ debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_default_dentry, ++ (u32 *)&ecm_classifier_default_enabled); + +- if (!debugfs_create_u32("accel_mode", S_IRUGO | S_IWUSR, ecm_classifier_default_dentry, +- (u32 *)&ecm_classifier_default_accel_mode)) { +- DEBUG_ERROR("Failed to create ecm deafult classifier accel_mode file in debugfs\n"); +- debugfs_remove_recursive(ecm_classifier_default_dentry); +- return -1; +- } ++ debugfs_create_u32("accel_mode", S_IRUGO | S_IWUSR, ecm_classifier_default_dentry, ++ (u32 *)&ecm_classifier_default_accel_mode); + +- if (!debugfs_create_u32("accel_delay_pkts", S_IRUGO | S_IWUSR, ecm_classifier_default_dentry, +- (u32 *)&ecm_classifier_accel_delay_pkts)) { +- DEBUG_ERROR("Failed to create accel delay packet counts in debugfs\n"); +- debugfs_remove_recursive(ecm_classifier_default_dentry); +- return -1; +- } ++ debugfs_create_u32("accel_delay_pkts", S_IRUGO | S_IWUSR, ecm_classifier_default_dentry, ++ (u32 *)&ecm_classifier_accel_delay_pkts); + + return 0; + } +--- a/ecm_classifier_dscp.c ++++ b/ecm_classifier_dscp.c +@@ -747,12 +747,8 @@ int ecm_classifier_dscp_init(struct dent + return -1; + } + +- if (!debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_dscp_dentry, +- (u32 *)&ecm_classifier_dscp_enabled)) { +- DEBUG_ERROR("Failed to create dscp enabled file in debugfs\n"); +- debugfs_remove_recursive(ecm_classifier_dscp_dentry); +- return -1; +- } ++ debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_dscp_dentry, ++ (u32 *)&ecm_classifier_dscp_enabled); + + return 0; + } +--- a/ecm_classifier_emesh.c ++++ b/ecm_classifier_emesh.c +@@ -974,19 +974,11 @@ int ecm_classifier_emesh_init(struct den + return -1; + } + +- if (!debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_emesh_dentry, +- (u32 *)&ecm_classifier_emesh_enabled)) { +- DEBUG_ERROR("Failed to create ecm emesh classifier enabled file in debugfs\n"); +- debugfs_remove_recursive(ecm_classifier_emesh_dentry); +- return -1; +- } ++ debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_emesh_dentry, ++ (u32 *)&ecm_classifier_emesh_enabled); + +- if (!debugfs_create_u32("latency_config_enabled", S_IRUGO | S_IWUSR, ecm_classifier_emesh_dentry, +- (u32 *)&ecm_classifier_emesh_latency_config_enabled)) { +- DEBUG_ERROR("Failed to create ecm emesh classifier latency config enabled file in debugfs\n"); +- debugfs_remove_recursive(ecm_classifier_emesh_dentry); +- return -1; +- } ++ debugfs_create_u32("latency_config_enabled", S_IRUGO | S_IWUSR, ecm_classifier_emesh_dentry, ++ (u32 *)&ecm_classifier_emesh_latency_config_enabled); + + /* + * Register for service prioritization notification update. +--- a/ecm_classifier_hyfi.c ++++ b/ecm_classifier_hyfi.c +@@ -1099,11 +1099,8 @@ int ecm_classifier_hyfi_rules_init(struc + goto classifier_task_cleanup; + } + +- if (!debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_hyfi_dentry, +- (u32 *)&ecm_classifier_hyfi_enabled)) { +- DEBUG_ERROR("Failed to create ecm hyfi classifier enabled file in debugfs\n"); +- goto classifier_task_cleanup; +- } ++ debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_hyfi_dentry, ++ (u32 *)&ecm_classifier_hyfi_enabled); + + if (!debugfs_create_file("cmd", S_IWUSR, ecm_classifier_hyfi_dentry, + NULL, &ecm_classifier_hyfi_cmd_fops)) { +--- a/ecm_classifier_mark.c ++++ b/ecm_classifier_mark.c +@@ -753,12 +753,8 @@ int ecm_classifier_mark_init(struct dent + return -1; + } + +- if (!debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_mark_dentry, +- (u32 *)&ecm_classifier_mark_enabled)) { +- DEBUG_ERROR("Failed to create mark enabled file in debugfs\n"); +- debugfs_remove_recursive(ecm_classifier_mark_dentry); +- return -1; +- } ++ debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_mark_dentry, ++ (u32 *)&ecm_classifier_mark_enabled); + + return 0; + } +--- a/ecm_classifier_ovs.c ++++ b/ecm_classifier_ovs.c +@@ -2200,12 +2200,8 @@ int ecm_classifier_ovs_init(struct dentr + return -1; + } + +- if (!debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_ovs_dentry, +- (u32 *)&ecm_classifier_ovs_enabled)) { +- DEBUG_ERROR("Failed to create ovs enabled file in debugfs\n"); +- debugfs_remove_recursive(ecm_classifier_ovs_dentry); +- return -1; +- } ++ debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_ovs_dentry, ++ (u32 *)&ecm_classifier_ovs_enabled); + + return 0; + } +--- a/ecm_classifier_pcc.c ++++ b/ecm_classifier_pcc.c +@@ -1308,12 +1308,8 @@ int ecm_classifier_pcc_init(struct dentr + return -1; + } + +- if (!debugfs_create_u32("enabled", S_IRUGO, ecm_classifier_pcc_dentry, +- (u32 *)&ecm_classifier_pcc_enabled)) { +- DEBUG_ERROR("Failed to create pcc enabled file in debugfs\n"); +- debugfs_remove_recursive(ecm_classifier_pcc_dentry); +- return -1; +- } ++ debugfs_create_u32("enabled", S_IRUGO, ecm_classifier_pcc_dentry, ++ (u32 *)&ecm_classifier_pcc_enabled); + + return 0; + } +--- a/ecm_conntrack_notifier.c ++++ b/ecm_conntrack_notifier.c +@@ -414,12 +414,8 @@ int ecm_conntrack_notifier_init(struct d + return -1; + } + +- if (!debugfs_create_u32("stop", S_IRUGO | S_IWUSR, ecm_conntrack_notifier_dentry, +- (u32 *)&ecm_conntrack_notifier_stopped)) { +- DEBUG_ERROR("Failed to create ecm conntrack notifier stopped file in debugfs\n"); +- debugfs_remove_recursive(ecm_conntrack_notifier_dentry); +- return -1; +- } ++ debugfs_create_u32("stop", S_IRUGO | S_IWUSR, ecm_conntrack_notifier_dentry, ++ (u32 *)&ecm_conntrack_notifier_stopped); + + #ifdef CONFIG_NF_CONNTRACK_EVENTS + /* +--- a/ecm_db/ecm_db_connection.c ++++ b/ecm_db/ecm_db_connection.c +@@ -3642,11 +3642,8 @@ static struct file_operations ecm_db_con + */ + bool ecm_db_connection_init(struct dentry *dentry) + { +- if (!debugfs_create_u32("connection_count", S_IRUGO, dentry, +- (u32 *)&ecm_db_connection_count)) { +- DEBUG_ERROR("Failed to create ecm db connection count file in debugfs\n"); +- return false; +- } ++ debugfs_create_u32("connection_count", S_IRUGO, dentry, ++ (u32 *)&ecm_db_connection_count); + + if (!debugfs_create_file("connection_count_simple", S_IRUGO, dentry, + NULL, &ecm_db_connection_count_simple_fops)) { +--- a/ecm_db/ecm_db_host.c ++++ b/ecm_db/ecm_db_host.c +@@ -770,11 +770,8 @@ EXPORT_SYMBOL(ecm_db_host_alloc); + bool ecm_db_host_init(struct dentry *dentry) + { + +- if (!debugfs_create_u32("host_count", S_IRUGO, dentry, +- (u32 *)&ecm_db_host_count)) { +- DEBUG_ERROR("Failed to create ecm db host count file in debugfs\n"); +- return false;; +- } ++ debugfs_create_u32("host_count", S_IRUGO, dentry, ++ (u32 *)&ecm_db_host_count); + + ecm_db_host_table = vzalloc(sizeof(struct ecm_db_host_instance *) * ECM_DB_HOST_HASH_SLOTS); + if (!ecm_db_host_table) { +--- a/ecm_db/ecm_db_iface.c ++++ b/ecm_db/ecm_db_iface.c +@@ -3670,11 +3670,8 @@ EXPORT_SYMBOL(ecm_db_iface_alloc); + */ + bool ecm_db_iface_init(struct dentry *dentry) + { +- if (!debugfs_create_u32("iface_count", S_IRUGO, dentry, +- (u32 *)&ecm_db_iface_count)) { +- DEBUG_ERROR("Failed to create ecm db iface count file in debugfs\n"); +- return false; +- } ++ debugfs_create_u32("iface_count", S_IRUGO, dentry, ++ (u32 *)&ecm_db_iface_count); + + return true; + } +--- a/ecm_db/ecm_db_mapping.c ++++ b/ecm_db/ecm_db_mapping.c +@@ -806,11 +806,8 @@ EXPORT_SYMBOL(ecm_db_mapping_alloc); + */ + bool ecm_db_mapping_init(struct dentry *dentry) + { +- if (!debugfs_create_u32("mapping_count", S_IRUGO, dentry, +- (u32 *)&ecm_db_mapping_count)) { +- DEBUG_ERROR("Failed to create ecm db mapping count file in debugfs\n"); +- return false; +- } ++ debugfs_create_u32("mapping_count", S_IRUGO, dentry, ++ (u32 *)&ecm_db_mapping_count); + + ecm_db_mapping_table = vzalloc(sizeof(struct ecm_db_mapping_instance *) * ECM_DB_MAPPING_HASH_SLOTS); + if (!ecm_db_mapping_table) { +--- a/ecm_db/ecm_db_node.c ++++ b/ecm_db/ecm_db_node.c +@@ -1187,11 +1187,8 @@ keep_sni_conn: + */ + bool ecm_db_node_init(struct dentry *dentry) + { +- if (!debugfs_create_u32("node_count", S_IRUGO, dentry, +- (u32 *)&ecm_db_node_count)) { +- DEBUG_ERROR("Failed to create ecm db node count file in debugfs\n"); +- return false; +- } ++ debugfs_create_u32("node_count", S_IRUGO, dentry, ++ (u32 *)&ecm_db_node_count); + + ecm_db_node_table = vzalloc(sizeof(struct ecm_db_node_instance *) * ECM_DB_NODE_HASH_SLOTS); + if (!ecm_db_node_table) { +--- a/ecm_interface.c ++++ b/ecm_interface.c +@@ -332,7 +332,7 @@ static struct net_device *ecm_interface_ + struct net_device *dev; + + ECM_IP_ADDR_TO_NIN6_ADDR(addr6, addr); +- dev = (struct net_device *)ipv6_dev_find(&init_net, &addr6, 1); ++ dev = (struct net_device *)ipv6_dev_find_and_hold(&init_net, &addr6, 1); + return dev; + } + #endif +@@ -734,7 +734,7 @@ static bool ecm_interface_mac_addr_get_i + * Get the MAC address that corresponds to IP address given. + */ + ECM_IP_ADDR_TO_NIN6_ADDR(daddr, addr); +- local_dev = ipv6_dev_find(&init_net, &daddr, 1); ++ local_dev = ipv6_dev_find_and_hold(&init_net, &daddr, 1); + if (local_dev) { + DEBUG_TRACE("%pi6 is a local address\n", &daddr); + memcpy(mac_addr, dev->dev_addr, ETH_ALEN); +--- a/ecm_state.c ++++ b/ecm_state.c +@@ -899,17 +899,11 @@ int ecm_state_init(struct dentry *dentry + return -1; + } + +- if (!debugfs_create_u32("state_dev_major", S_IRUGO, ecm_state_dentry, +- (u32 *)&ecm_state_dev_major_id)) { +- DEBUG_ERROR("Failed to create ecm state dev major file in debugfs\n"); +- goto init_cleanup; +- } ++ debugfs_create_u32("state_dev_major", S_IRUGO, ecm_state_dentry, ++ (u32 *)&ecm_state_dev_major_id); + +- if (!debugfs_create_u32("state_file_output_mask", S_IRUGO | S_IWUSR, ecm_state_dentry, +- (u32 *)&ecm_state_file_output_mask)) { +- DEBUG_ERROR("Failed to create ecm state output mask file in debugfs\n"); +- goto init_cleanup; +- } ++ debugfs_create_u32("state_file_output_mask", S_IRUGO | S_IWUSR, ecm_state_dentry, ++ (u32 *)&ecm_state_file_output_mask); + + /* + * Register a char device that we will use to provide a dump of our state +--- a/frontends/ecm_front_end_common.c ++++ b/frontends/ecm_front_end_common.c +@@ -192,7 +192,7 @@ bool ecm_front_end_gre_proto_is_accel_al + return false; + } + } else { +- dev = ipv6_dev_find(&init_net, &(tuple->src.u3.in6), 1); ++ dev = ipv6_dev_find_and_hold(&init_net, &(tuple->src.u3.in6), 1); + if (dev) { + /* + * Source IP address is local +@@ -202,7 +202,7 @@ bool ecm_front_end_gre_proto_is_accel_al + return false; + } + +- dev = ipv6_dev_find(&init_net, &(tuple->dst.u3.in6), 1); ++ dev = ipv6_dev_find_and_hold(&init_net, &(tuple->dst.u3.in6), 1); + if (dev) { + /* + * Destination IP address is local +--- a/frontends/ecm_front_end_ipv4.c ++++ b/frontends/ecm_front_end_ipv4.c +@@ -376,11 +376,8 @@ void ecm_front_end_ipv4_stop(int num) + */ + int ecm_front_end_ipv4_init(struct dentry *dentry) + { +- if (!debugfs_create_u32("front_end_ipv4_stop", S_IRUGO | S_IWUSR, dentry, +- (u32 *)&ecm_front_end_ipv4_stopped)) { +- DEBUG_ERROR("Failed to create ecm front end ipv4 stop file in debugfs\n"); +- return -1; +- } ++ debugfs_create_u32("front_end_ipv4_stop", S_IRUGO | S_IWUSR, dentry, ++ (u32 *)&ecm_front_end_ipv4_stopped); + + switch (ecm_front_end_type_get()) { + case ECM_FRONT_END_TYPE_NSS: +--- a/frontends/ecm_front_end_ipv6.c ++++ b/frontends/ecm_front_end_ipv6.c +@@ -255,11 +255,8 @@ void ecm_front_end_ipv6_stop(int num) + */ + int ecm_front_end_ipv6_init(struct dentry *dentry) + { +- if (!debugfs_create_u32("front_end_ipv6_stop", S_IRUGO | S_IWUSR, dentry, +- (u32 *)&ecm_front_end_ipv6_stopped)) { +- DEBUG_ERROR("Failed to create ecm front end ipv6 stop file in debugfs\n"); +- return -1; +- } ++ debugfs_create_u32("front_end_ipv6_stop", S_IRUGO | S_IWUSR, dentry, ++ (u32 *)&ecm_front_end_ipv6_stopped); + + switch (ecm_front_end_type_get()) { + case ECM_FRONT_END_TYPE_NSS: +--- a/frontends/nss/ecm_nss_bond_notifier.c ++++ b/frontends/nss/ecm_nss_bond_notifier.c +@@ -240,12 +240,8 @@ int ecm_nss_bond_notifier_init(struct de + return -1; + } + +- if (!debugfs_create_u32("stop", S_IRUGO | S_IWUSR, ecm_nss_bond_notifier_dentry, +- (u32 *)&ecm_nss_bond_notifier_stopped)) { +- DEBUG_ERROR("Failed to create ecm bond notifier stopped file in debugfs\n"); +- debugfs_remove_recursive(ecm_nss_bond_notifier_dentry); +- return -1; +- } ++ debugfs_create_u32("stop", S_IRUGO | S_IWUSR, ecm_nss_bond_notifier_dentry, ++ (u32 *)&ecm_nss_bond_notifier_stopped); + + /* + * Register Link Aggregation callbacks with the bonding driver +--- a/frontends/nss/ecm_nss_ipv4.c ++++ b/frontends/nss/ecm_nss_ipv4.c +@@ -2802,41 +2802,23 @@ int ecm_nss_ipv4_init(struct dentry *den + return result; + } + +- if (!debugfs_create_u32("no_action_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, +- (u32 *)&ecm_nss_ipv4_no_action_limit_default)) { +- DEBUG_ERROR("Failed to create ecm nss ipv4 no_action_limit_default file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("no_action_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, ++ (u32 *)&ecm_nss_ipv4_no_action_limit_default); + +- if (!debugfs_create_u32("driver_fail_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, +- (u32 *)&ecm_nss_ipv4_driver_fail_limit_default)) { +- DEBUG_ERROR("Failed to create ecm nss ipv4 driver_fail_limit_default file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("driver_fail_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, ++ (u32 *)&ecm_nss_ipv4_driver_fail_limit_default); + +- if (!debugfs_create_u32("nack_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, +- (u32 *)&ecm_nss_ipv4_nack_limit_default)) { +- DEBUG_ERROR("Failed to create ecm nss ipv4 nack_limit_default file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("nack_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, ++ (u32 *)&ecm_nss_ipv4_nack_limit_default); + +- if (!debugfs_create_u32("accelerated_count", S_IRUGO, ecm_nss_ipv4_dentry, +- (u32 *)&ecm_nss_ipv4_accelerated_count)) { +- DEBUG_ERROR("Failed to create ecm nss ipv4 accelerated_count file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("accelerated_count", S_IRUGO, ecm_nss_ipv4_dentry, ++ (u32 *)&ecm_nss_ipv4_accelerated_count); + +- if (!debugfs_create_u32("pending_accel_count", S_IRUGO, ecm_nss_ipv4_dentry, +- (u32 *)&ecm_nss_ipv4_pending_accel_count)) { +- DEBUG_ERROR("Failed to create ecm nss ipv4 pending_accel_count file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("pending_accel_count", S_IRUGO, ecm_nss_ipv4_dentry, ++ (u32 *)&ecm_nss_ipv4_pending_accel_count); + +- if (!debugfs_create_u32("pending_decel_count", S_IRUGO, ecm_nss_ipv4_dentry, +- (u32 *)&ecm_nss_ipv4_pending_decel_count)) { +- DEBUG_ERROR("Failed to create ecm nss ipv4 pending_decel_count file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("pending_decel_count", S_IRUGO, ecm_nss_ipv4_dentry, ++ (u32 *)&ecm_nss_ipv4_pending_decel_count); + + if (!debugfs_create_file("accel_limit_mode", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, + NULL, &ecm_nss_ipv4_accel_limit_mode_fops)) { +@@ -2867,11 +2849,8 @@ int ecm_nss_ipv4_init(struct dentry *den + goto task_cleanup; + } + +- if (!debugfs_create_u32("vlan_passthrough_set", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, +- (u32 *)&ecm_nss_ipv4_vlan_passthrough_enable)) { +- DEBUG_ERROR("Failed to create ecm nss ipv4 vlan passthrough file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("vlan_passthrough_set", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, ++ (u32 *)&ecm_nss_ipv4_vlan_passthrough_enable); + + #ifdef ECM_NON_PORTED_SUPPORT_ENABLE + if (!ecm_nss_non_ported_ipv4_debugfs_init(ecm_nss_ipv4_dentry)) { +--- a/frontends/nss/ecm_nss_ipv6.c ++++ b/frontends/nss/ecm_nss_ipv6.c +@@ -2542,41 +2542,23 @@ int ecm_nss_ipv6_init(struct dentry *den + return result; + } + +- if (!debugfs_create_u32("no_action_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, +- (u32 *)&ecm_nss_ipv6_no_action_limit_default)) { +- DEBUG_ERROR("Failed to create ecm nss ipv6 no_action_limit_default file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("no_action_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, ++ (u32 *)&ecm_nss_ipv6_no_action_limit_default); + +- if (!debugfs_create_u32("driver_fail_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, +- (u32 *)&ecm_nss_ipv6_driver_fail_limit_default)) { +- DEBUG_ERROR("Failed to create ecm nss ipv6 driver_fail_limit_default file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("driver_fail_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, ++ (u32 *)&ecm_nss_ipv6_driver_fail_limit_default); + +- if (!debugfs_create_u32("nack_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, +- (u32 *)&ecm_nss_ipv6_nack_limit_default)) { +- DEBUG_ERROR("Failed to create ecm nss ipv6 nack_limit_default file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("nack_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, ++ (u32 *)&ecm_nss_ipv6_nack_limit_default); + +- if (!debugfs_create_u32("accelerated_count", S_IRUGO, ecm_nss_ipv6_dentry, +- (u32 *)&ecm_nss_ipv6_accelerated_count)) { +- DEBUG_ERROR("Failed to create ecm nss ipv6 accelerated_count file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("accelerated_count", S_IRUGO, ecm_nss_ipv6_dentry, ++ (u32 *)&ecm_nss_ipv6_accelerated_count); + +- if (!debugfs_create_u32("pending_accel_count", S_IRUGO, ecm_nss_ipv6_dentry, +- (u32 *)&ecm_nss_ipv6_pending_accel_count)) { +- DEBUG_ERROR("Failed to create ecm nss ipv6 pending_accel_count file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("pending_accel_count", S_IRUGO, ecm_nss_ipv6_dentry, ++ (u32 *)&ecm_nss_ipv6_pending_accel_count); + +- if (!debugfs_create_u32("pending_decel_count", S_IRUGO, ecm_nss_ipv6_dentry, +- (u32 *)&ecm_nss_ipv6_pending_decel_count)) { +- DEBUG_ERROR("Failed to create ecm nss ipv6 pending_decel_count file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("pending_decel_count", S_IRUGO, ecm_nss_ipv6_dentry, ++ (u32 *)&ecm_nss_ipv6_pending_decel_count); + + if (!debugfs_create_file("accel_limit_mode", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, + NULL, &ecm_nss_ipv6_accel_limit_mode_fops)) { +@@ -2607,11 +2589,8 @@ int ecm_nss_ipv6_init(struct dentry *den + goto task_cleanup; + } + +- if (!debugfs_create_u32("vlan_passthrough_set", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, +- (u32 *)&ecm_nss_ipv6_vlan_passthrough_enable)) { +- DEBUG_ERROR("Failed to create ecm nss ipv6 vlan passthrough file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("vlan_passthrough_set", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, ++ (u32 *)&ecm_nss_ipv6_vlan_passthrough_enable); + + #ifdef ECM_NON_PORTED_SUPPORT_ENABLE + if (!ecm_nss_non_ported_ipv6_debugfs_init(ecm_nss_ipv6_dentry)) { +--- a/frontends/nss/ecm_nss_multicast_ipv4.c ++++ b/frontends/nss/ecm_nss_multicast_ipv4.c +@@ -4139,11 +4139,8 @@ void ecm_nss_multicast_ipv4_stop(int num + */ + int ecm_nss_multicast_ipv4_init(struct dentry *dentry) + { +- if (!debugfs_create_u32("ecm_nss_multicast_ipv4_stop", S_IRUGO | S_IWUSR, dentry, +- (u32 *)&ecm_front_end_ipv4_mc_stopped)) { +- DEBUG_ERROR("Failed to create ecm front end ipv4 mc stop file in debugfs\n"); +- return -1; +- } ++ debugfs_create_u32("ecm_nss_multicast_ipv4_stop", S_IRUGO | S_IWUSR, dentry, ++ (u32 *)&ecm_front_end_ipv4_mc_stopped); + + /* + * Register multicast update callback to MCS snooper +--- a/frontends/nss/ecm_nss_multicast_ipv6.c ++++ b/frontends/nss/ecm_nss_multicast_ipv6.c +@@ -3939,11 +3939,8 @@ void ecm_nss_multicast_ipv6_stop(int num + */ + int ecm_nss_multicast_ipv6_init(struct dentry *dentry) + { +- if (!debugfs_create_u32("ecm_nss_multicast_ipv6_stop", S_IRUGO | S_IWUSR, dentry, +- (u32 *)&ecm_front_end_ipv6_mc_stopped)) { +- DEBUG_ERROR("Failed to create ecm front end ipv6 mc stop file in debugfs\n"); +- return -1; +- } ++ debugfs_create_u32("ecm_nss_multicast_ipv6_stop", S_IRUGO | S_IWUSR, dentry, ++ (u32 *)&ecm_front_end_ipv6_mc_stopped); + + /* + * Register multicast update callback to MCS snooper +--- a/frontends/nss/ecm_nss_non_ported_ipv4.c ++++ b/frontends/nss/ecm_nss_non_ported_ipv4.c +@@ -2615,11 +2615,8 @@ done: + */ + bool ecm_nss_non_ported_ipv4_debugfs_init(struct dentry *dentry) + { +- if (!debugfs_create_u32("non_ported_accelerated_count", S_IRUGO, dentry, +- (u32 *)&ecm_nss_non_ported_ipv4_accelerated_count)) { +- DEBUG_ERROR("Failed to create ecm nss ipv4 non_ported_accelerated_count file in debugfs\n"); +- return false; +- } ++ debugfs_create_u32("non_ported_accelerated_count", S_IRUGO, dentry, ++ (u32 *)&ecm_nss_non_ported_ipv4_accelerated_count); + + return true; + } +--- a/frontends/nss/ecm_nss_non_ported_ipv6.c ++++ b/frontends/nss/ecm_nss_non_ported_ipv6.c +@@ -2329,11 +2329,8 @@ done: + */ + bool ecm_nss_non_ported_ipv6_debugfs_init(struct dentry *dentry) + { +- if (!debugfs_create_u32("non_ported_accelerated_count", S_IRUGO, dentry, +- (u32 *)&ecm_nss_non_ported_ipv6_accelerated_count)) { +- DEBUG_ERROR("Failed to create ecm nss ipv6 non_ported_accelerated_count file in debugfs\n"); +- return false; +- } ++ debugfs_create_u32("non_ported_accelerated_count", S_IRUGO, dentry, ++ (u32 *)&ecm_nss_non_ported_ipv6_accelerated_count); + + return true; + } +--- a/frontends/nss/ecm_nss_ported_ipv4.c ++++ b/frontends/nss/ecm_nss_ported_ipv4.c +@@ -2944,12 +2944,8 @@ bool ecm_nss_ported_ipv4_debugfs_init(st + return false; + } + +- if (!debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, +- &ecm_nss_ported_ipv4_accelerated_count[ECM_NSS_PORTED_IPV4_PROTO_TCP])) { +- DEBUG_ERROR("Failed to create ecm nss ipv4 tcp_accelerated_count file in debugfs\n"); +- debugfs_remove(udp_dentry); +- return false; +- } ++ debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, ++ &ecm_nss_ported_ipv4_accelerated_count[ECM_NSS_PORTED_IPV4_PROTO_TCP]); + + return true; + } +--- a/frontends/nss/ecm_nss_ported_ipv6.c ++++ b/frontends/nss/ecm_nss_ported_ipv6.c +@@ -2732,12 +2732,8 @@ bool ecm_nss_ported_ipv6_debugfs_init(st + return false; + } + +- if (!debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, +- &ecm_nss_ported_ipv6_accelerated_count[ECM_NSS_PORTED_IPV6_PROTO_TCP])) { +- DEBUG_ERROR("Failed to create ecm nss ipv6 tcp_accelerated_count file in debugfs\n"); +- debugfs_remove(udp_dentry); +- return false; +- } ++ debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, ++ &ecm_nss_ported_ipv6_accelerated_count[ECM_NSS_PORTED_IPV6_PROTO_TCP]); + + return true; + } +--- a/frontends/sfe/ecm_sfe_ipv4.c ++++ b/frontends/sfe/ecm_sfe_ipv4.c +@@ -1808,48 +1808,27 @@ int ecm_sfe_ipv4_init(struct dentry *den + } + + #ifdef CONFIG_XFRM +- if (!debugfs_create_u32("reject_acceleration_for_ipsec", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, +- (u32 *)&ecm_sfe_ipv4_reject_acceleration_for_ipsec)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv4 reject_acceleration_for_ipsec file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("reject_acceleration_for_ipsec", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, ++ (u32 *)&ecm_sfe_ipv4_reject_acceleration_for_ipsec); + #endif + +- if (!debugfs_create_u32("no_action_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, +- (u32 *)&ecm_sfe_ipv4_no_action_limit_default)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv4 no_action_limit_default file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("no_action_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, ++ (u32 *)&ecm_sfe_ipv4_no_action_limit_default); + +- if (!debugfs_create_u32("driver_fail_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, +- (u32 *)&ecm_sfe_ipv4_driver_fail_limit_default)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv4 driver_fail_limit_default file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("driver_fail_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, ++ (u32 *)&ecm_sfe_ipv4_driver_fail_limit_default); + +- if (!debugfs_create_u32("nack_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, +- (u32 *)&ecm_sfe_ipv4_nack_limit_default)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv4 nack_limit_default file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("nack_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, ++ (u32 *)&ecm_sfe_ipv4_nack_limit_default); + +- if (!debugfs_create_u32("accelerated_count", S_IRUGO, ecm_sfe_ipv4_dentry, +- (u32 *)&ecm_sfe_ipv4_accelerated_count)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv4 accelerated_count file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("accelerated_count", S_IRUGO, ecm_sfe_ipv4_dentry, ++ (u32 *)&ecm_sfe_ipv4_accelerated_count); + +- if (!debugfs_create_u32("pending_accel_count", S_IRUGO, ecm_sfe_ipv4_dentry, +- (u32 *)&ecm_sfe_ipv4_pending_accel_count)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv4 pending_accel_count file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("pending_accel_count", S_IRUGO, ecm_sfe_ipv4_dentry, ++ (u32 *)&ecm_sfe_ipv4_pending_accel_count); + +- if (!debugfs_create_u32("pending_decel_count", S_IRUGO, ecm_sfe_ipv4_dentry, +- (u32 *)&ecm_sfe_ipv4_pending_decel_count)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv4 pending_decel_count file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("pending_decel_count", S_IRUGO, ecm_sfe_ipv4_dentry, ++ (u32 *)&ecm_sfe_ipv4_pending_decel_count); + + if (!debugfs_create_file("accel_limit_mode", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, + NULL, &ecm_sfe_ipv4_accel_limit_mode_fops)) { +--- a/frontends/sfe/ecm_sfe_ipv6.c ++++ b/frontends/sfe/ecm_sfe_ipv6.c +@@ -1532,48 +1532,27 @@ int ecm_sfe_ipv6_init(struct dentry *den + } + + #ifdef CONFIG_XFRM +- if (!debugfs_create_u32("reject_acceleration_for_ipsec", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, +- (u32 *)&ecm_sfe_ipv6_reject_acceleration_for_ipsec)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv6 reject_acceleration_for_ipsec file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("reject_acceleration_for_ipsec", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, ++ (u32 *)&ecm_sfe_ipv6_reject_acceleration_for_ipsec); + #endif + +- if (!debugfs_create_u32("no_action_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, +- (u32 *)&ecm_sfe_ipv6_no_action_limit_default)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv6 no_action_limit_default file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("no_action_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, ++ (u32 *)&ecm_sfe_ipv6_no_action_limit_default); + +- if (!debugfs_create_u32("driver_fail_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, +- (u32 *)&ecm_sfe_ipv6_driver_fail_limit_default)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv6 driver_fail_limit_default file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("driver_fail_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, ++ (u32 *)&ecm_sfe_ipv6_driver_fail_limit_default); + +- if (!debugfs_create_u32("nack_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, +- (u32 *)&ecm_sfe_ipv6_nack_limit_default)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv6 nack_limit_default file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("nack_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, ++ (u32 *)&ecm_sfe_ipv6_nack_limit_default); + +- if (!debugfs_create_u32("accelerated_count", S_IRUGO, ecm_sfe_ipv6_dentry, +- (u32 *)&ecm_sfe_ipv6_accelerated_count)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv6 accelerated_count file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("accelerated_count", S_IRUGO, ecm_sfe_ipv6_dentry, ++ (u32 *)&ecm_sfe_ipv6_accelerated_count); + +- if (!debugfs_create_u32("pending_accel_count", S_IRUGO, ecm_sfe_ipv6_dentry, +- (u32 *)&ecm_sfe_ipv6_pending_accel_count)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv6 pending_accel_count file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("pending_accel_count", S_IRUGO, ecm_sfe_ipv6_dentry, ++ (u32 *)&ecm_sfe_ipv6_pending_accel_count); + +- if (!debugfs_create_u32("pending_decel_count", S_IRUGO, ecm_sfe_ipv6_dentry, +- (u32 *)&ecm_sfe_ipv6_pending_decel_count)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv6 pending_decel_count file in debugfs\n"); +- goto task_cleanup; +- } ++ debugfs_create_u32("pending_decel_count", S_IRUGO, ecm_sfe_ipv6_dentry, ++ (u32 *)&ecm_sfe_ipv6_pending_decel_count); + + if (!debugfs_create_file("accel_limit_mode", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, + NULL, &ecm_sfe_ipv6_accel_limit_mode_fops)) { +--- a/frontends/sfe/ecm_sfe_non_ported_ipv4.c ++++ b/frontends/sfe/ecm_sfe_non_ported_ipv4.c +@@ -2284,11 +2284,8 @@ done: + */ + bool ecm_sfe_non_ported_ipv4_debugfs_init(struct dentry *dentry) + { +- if (!debugfs_create_u32("non_ported_accelerated_count", S_IRUGO, dentry, +- (u32 *)&ecm_sfe_non_ported_ipv4_accelerated_count)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv4 non_ported_accelerated_count file in debugfs\n"); +- return false; +- } ++ debugfs_create_u32("non_ported_accelerated_count", S_IRUGO, dentry, ++ (u32 *)&ecm_sfe_non_ported_ipv4_accelerated_count); + + return true; + } +--- a/frontends/sfe/ecm_sfe_non_ported_ipv6.c ++++ b/frontends/sfe/ecm_sfe_non_ported_ipv6.c +@@ -2083,11 +2083,8 @@ done: + */ + bool ecm_sfe_non_ported_ipv6_debugfs_init(struct dentry *dentry) + { +- if (!debugfs_create_u32("non_ported_accelerated_count", S_IRUGO, dentry, +- (u32 *)&ecm_sfe_non_ported_ipv6_accelerated_count)) { +- DEBUG_ERROR("Failed to create ecm sfe ipv6 non_ported_accelerated_count file in debugfs\n"); +- return false; +- } ++ debugfs_create_u32("non_ported_accelerated_count", S_IRUGO, dentry, ++ (u32 *)&ecm_sfe_non_ported_ipv6_accelerated_count); + + return true; + } +--- a/frontends/sfe/ecm_sfe_ported_ipv4.c ++++ b/frontends/sfe/ecm_sfe_ported_ipv4.c +@@ -2528,12 +2528,8 @@ bool ecm_sfe_ported_ipv4_debugfs_init(st + return false; + } + +- if (!debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, +- &ecm_sfe_ported_ipv4_accelerated_count[ECM_SFE_PORTED_IPV4_PROTO_TCP])) { +- DEBUG_ERROR("Failed to create ecm sfe ipv4 tcp_accelerated_count file in debugfs\n"); +- debugfs_remove(udp_dentry); +- return false; +- } ++ debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, ++ &ecm_sfe_ported_ipv4_accelerated_count[ECM_SFE_PORTED_IPV4_PROTO_TCP]); + + return true; + } +--- a/frontends/sfe/ecm_sfe_ported_ipv6.c ++++ b/frontends/sfe/ecm_sfe_ported_ipv6.c +@@ -2374,12 +2374,8 @@ bool ecm_sfe_ported_ipv6_debugfs_init(st + return false; + } + +- if (!debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, +- &ecm_sfe_ported_ipv6_accelerated_count[ECM_SFE_PORTED_IPV6_PROTO_TCP])) { +- DEBUG_ERROR("Failed to create ecm sfe ipv6 tcp_accelerated_count file in debugfs\n"); +- debugfs_remove(udp_dentry); +- return false; +- } ++ debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, ++ &ecm_sfe_ported_ipv6_accelerated_count[ECM_SFE_PORTED_IPV6_PROTO_TCP]); + + return true; + } diff --git a/qca/qca-nss-ecm/patches/200-resolve-high-load.patch b/qca/qca-nss-ecm/patches/200-resolve-high-load.patch new file mode 100644 index 000000000..253b450a5 --- /dev/null +++ b/qca/qca-nss-ecm/patches/200-resolve-high-load.patch @@ -0,0 +1,61 @@ +From 6924b71ed809b37fffd74d6428a8ca83e5919746 Mon Sep 17 00:00:00 2001 +From: Dirk Buchwalder +Date: Sun, 27 Jun 2021 16:52:39 +0200 +Subject: [PATCH] qca-nss-ecm: resolve the cpu high load regarding ecm + +If using ECM, cpu load goes up (around 1.0) and stucks there. +This is due to using uninterruptible sleep function, +the patch changes this to interruptible sleep function. + +Signed-off-by: Dirk Buchwalder +--- + frontends/nss/ecm_nss_ipv4.c | 4 ++-- + frontends/nss/ecm_nss_ipv6.c | 4 ++-- + 2 files changed, 4 insertions(+), 4 deletions(-) + +diff --git a/frontends/nss/ecm_nss_ipv4.c b/frontends/nss/ecm_nss_ipv4.c +index e00553c..94b39cd 100644 +--- a/frontends/nss/ecm_nss_ipv4.c ++++ b/frontends/nss/ecm_nss_ipv4.c +@@ -2471,7 +2471,7 @@ static void ecm_nss_ipv4_stats_sync_req_work(struct work_struct *work) + } + spin_unlock_bh(&ecm_nss_ipv4_lock); + +- usleep_range(ECM_NSS_IPV4_STATS_SYNC_UDELAY - 100, ECM_NSS_IPV4_STATS_SYNC_UDELAY); ++ msleep_interruptible(ECM_NSS_IPV4_STATS_SYNC_UDELAY / 1000); + + /* + * If index is 0, we are starting a new round, but if we still have time remain +@@ -2485,7 +2485,7 @@ static void ecm_nss_ipv4_stats_sync_req_work(struct work_struct *work) + } + + if (time_after(ecm_nss_ipv4_next_req_time, current_jiffies)) { +- msleep(jiffies_to_msecs(ecm_nss_ipv4_next_req_time - current_jiffies)); ++ msleep_interruptible(jiffies_to_msecs(ecm_nss_ipv4_next_req_time - current_jiffies)); + } + ecm_nss_ipv4_roll_check_jiffies = jiffies; + ecm_nss_ipv4_next_req_time = ecm_nss_ipv4_roll_check_jiffies + ECM_NSS_IPV4_STATS_SYNC_PERIOD; +diff --git a/frontends/nss/ecm_nss_ipv6.c b/frontends/nss/ecm_nss_ipv6.c +index 82e739f..30af050 100644 +--- a/frontends/nss/ecm_nss_ipv6.c ++++ b/frontends/nss/ecm_nss_ipv6.c +@@ -2210,7 +2210,7 @@ static void ecm_nss_ipv6_stats_sync_req_work(struct work_struct *work) + } + spin_unlock_bh(&ecm_nss_ipv6_lock); + +- usleep_range(ECM_NSS_IPV6_STATS_SYNC_UDELAY - 100, ECM_NSS_IPV6_STATS_SYNC_UDELAY); ++ msleep_interruptible(ECM_NSS_IPV6_STATS_SYNC_UDELAY / 1000); + + /* + * If index is 0, we are starting a new round, but if we still have time remain +@@ -2224,7 +2224,7 @@ static void ecm_nss_ipv6_stats_sync_req_work(struct work_struct *work) + } + + if (time_after(ecm_nss_ipv6_next_req_time, current_jiffies)) { +- msleep(jiffies_to_msecs(ecm_nss_ipv6_next_req_time - current_jiffies)); ++ msleep_interruptible(jiffies_to_msecs(ecm_nss_ipv6_next_req_time - current_jiffies)); + } + ecm_nss_ipv6_roll_check_jiffies = jiffies; + ecm_nss_ipv6_next_req_time = ecm_nss_ipv6_roll_check_jiffies + ECM_NSS_IPV6_STATS_SYNC_PERIOD; +-- +2.31.1 diff --git a/qca/qca-nss-ecm/patches/203-rework-nfct-notification.patch b/qca/qca-nss-ecm/patches/203-rework-nfct-notification.patch new file mode 100644 index 000000000..72005cd70 --- /dev/null +++ b/qca/qca-nss-ecm/patches/203-rework-nfct-notification.patch @@ -0,0 +1,25 @@ +--- a/ecm_conntrack_notifier.c ++++ b/ecm_conntrack_notifier.c +@@ -421,7 +421,11 @@ int ecm_conntrack_notifier_init(struct d + /* + * Eventing subsystem is available so we register a notifier hook to get fast notifications of expired connections + */ ++#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS ++ result = nf_conntrack_register_chain_notifier(&init_net, &ecm_conntrack_notifier); ++#else + result = nf_conntrack_register_notifier(&init_net, &ecm_conntrack_notifier); ++#endif + if (result < 0) { + DEBUG_ERROR("Can't register nf notifier hook.\n"); + debugfs_remove_recursive(ecm_conntrack_notifier_dentry); +@@ -439,7 +443,9 @@ EXPORT_SYMBOL(ecm_conntrack_notifier_ini + void ecm_conntrack_notifier_exit(void) + { + DEBUG_INFO("ECM Conntrack Notifier exit\n"); +-#ifdef CONFIG_NF_CONNTRACK_EVENTS ++#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS ++ nf_conntrack_unregister_chain_notifier(&init_net, &ecm_conntrack_notifier); ++#else + nf_conntrack_unregister_notifier(&init_net, &ecm_conntrack_notifier); + #endif + /* diff --git a/qca/qca-nss-ecm/patches/204-More-compile-fixes.patch b/qca/qca-nss-ecm/patches/204-More-compile-fixes.patch new file mode 100644 index 000000000..63a83c193 --- /dev/null +++ b/qca/qca-nss-ecm/patches/204-More-compile-fixes.patch @@ -0,0 +1,49 @@ +From e6d701c0d454d841366c556b2ef07a5203ffb35d Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Fri, 21 May 2021 21:41:31 +0200 +Subject: [PATCH] More compile fixes + +More runtime compile fixes. + +Signed-off-by: Robert Marko +--- + frontends/nss/ecm_nss_ported_ipv4.c | 12 +++--------- + frontends/nss/ecm_nss_ported_ipv6.c | 12 +++--------- + 2 files changed, 6 insertions(+), 18 deletions(-) + +--- a/frontends/nss/ecm_nss_ported_ipv4.c ++++ b/frontends/nss/ecm_nss_ported_ipv4.c +@@ -2935,14 +2935,8 @@ done: + */ + bool ecm_nss_ported_ipv4_debugfs_init(struct dentry *dentry) + { +- struct dentry *udp_dentry; +- +- udp_dentry = debugfs_create_u32("udp_accelerated_count", S_IRUGO, dentry, ++ debugfs_create_u32("udp_accelerated_count", S_IRUGO, dentry, + &ecm_nss_ported_ipv4_accelerated_count[ECM_NSS_PORTED_IPV4_PROTO_UDP]); +- if (!udp_dentry) { +- DEBUG_ERROR("Failed to create ecm nss ipv4 udp_accelerated_count file in debugfs\n"); +- return false; +- } + + debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, + &ecm_nss_ported_ipv4_accelerated_count[ECM_NSS_PORTED_IPV4_PROTO_TCP]); +--- a/frontends/nss/ecm_nss_ported_ipv6.c ++++ b/frontends/nss/ecm_nss_ported_ipv6.c +@@ -2723,14 +2723,8 @@ done: + */ + bool ecm_nss_ported_ipv6_debugfs_init(struct dentry *dentry) + { +- struct dentry *udp_dentry; +- +- udp_dentry = debugfs_create_u32("udp_accelerated_count", S_IRUGO, dentry, ++ debugfs_create_u32("udp_accelerated_count", S_IRUGO, dentry, + &ecm_nss_ported_ipv6_accelerated_count[ECM_NSS_PORTED_IPV6_PROTO_UDP]); +- if (!udp_dentry) { +- DEBUG_ERROR("Failed to create ecm nss ipv6 udp_accelerated_count file in debugfs\n"); +- return false; +- } + + debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, + &ecm_nss_ported_ipv6_accelerated_count[ECM_NSS_PORTED_IPV6_PROTO_TCP]); diff --git a/qca/qca-nss-ecm/patches/205-resolve-high-load.patch b/qca/qca-nss-ecm/patches/205-resolve-high-load.patch new file mode 100644 index 000000000..dd1ee13af --- /dev/null +++ b/qca/qca-nss-ecm/patches/205-resolve-high-load.patch @@ -0,0 +1,55 @@ +From 6924b71ed809b37fffd74d6428a8ca83e5919746 Mon Sep 17 00:00:00 2001 +From: Dirk Buchwalder +Date: Sun, 27 Jun 2021 16:52:39 +0200 +Subject: [PATCH] qca-nss-ecm: resolve the cpu high load regarding ecm + +If using ECM, cpu load goes up (around 1.0) and stucks there. +This is due to using uninterruptible sleep function, +the patch changes this to interruptible sleep function. + +Signed-off-by: Dirk Buchwalder buchwalder@posteo.de +--- + frontends/nss/ecm_nss_ipv4.c | 4 ++-- + frontends/nss/ecm_nss_ipv6.c | 4 ++-- + 2 files changed, 4 insertions(+), 4 deletions(-) + +--- a/frontends/nss/ecm_nss_ipv4.c ++++ b/frontends/nss/ecm_nss_ipv4.c +@@ -2471,7 +2471,7 @@ static void ecm_nss_ipv4_stats_sync_req_ + } + spin_unlock_bh(&ecm_nss_ipv4_lock); + +- usleep_range(ECM_NSS_IPV4_STATS_SYNC_UDELAY - 100, ECM_NSS_IPV4_STATS_SYNC_UDELAY); ++ msleep_interruptible(ECM_NSS_IPV4_STATS_SYNC_UDELAY / 1000); + + /* + * If index is 0, we are starting a new round, but if we still have time remain +@@ -2485,7 +2485,7 @@ static void ecm_nss_ipv4_stats_sync_req_ + } + + if (time_after(ecm_nss_ipv4_next_req_time, current_jiffies)) { +- msleep(jiffies_to_msecs(ecm_nss_ipv4_next_req_time - current_jiffies)); ++ msleep_interruptible(jiffies_to_msecs(ecm_nss_ipv4_next_req_time - current_jiffies)); + } + ecm_nss_ipv4_roll_check_jiffies = jiffies; + ecm_nss_ipv4_next_req_time = ecm_nss_ipv4_roll_check_jiffies + ECM_NSS_IPV4_STATS_SYNC_PERIOD; +--- a/frontends/nss/ecm_nss_ipv6.c ++++ b/frontends/nss/ecm_nss_ipv6.c +@@ -2210,7 +2210,7 @@ static void ecm_nss_ipv6_stats_sync_req_ + } + spin_unlock_bh(&ecm_nss_ipv6_lock); + +- usleep_range(ECM_NSS_IPV6_STATS_SYNC_UDELAY - 100, ECM_NSS_IPV6_STATS_SYNC_UDELAY); ++ msleep_interruptible(ECM_NSS_IPV6_STATS_SYNC_UDELAY / 1000); + + /* + * If index is 0, we are starting a new round, but if we still have time remain +@@ -2224,7 +2224,7 @@ static void ecm_nss_ipv6_stats_sync_req_ + } + + if (time_after(ecm_nss_ipv6_next_req_time, current_jiffies)) { +- msleep(jiffies_to_msecs(ecm_nss_ipv6_next_req_time - current_jiffies)); ++ msleep_interruptible(jiffies_to_msecs(ecm_nss_ipv6_next_req_time - current_jiffies)); + } + ecm_nss_ipv6_roll_check_jiffies = jiffies; + ecm_nss_ipv6_next_req_time = ecm_nss_ipv6_roll_check_jiffies + ECM_NSS_IPV6_STATS_SYNC_PERIOD; diff --git a/qca/qca-ssdk-shell/Makefile b/qca/qca-ssdk-shell/Makefile new file mode 100644 index 000000000..f872e431e --- /dev/null +++ b/qca/qca-ssdk-shell/Makefile @@ -0,0 +1,48 @@ +include $(TOPDIR)/rules.mk + +PKG_NAME:=qca-ssdk-shell +PKG_RELEASE:=$(AUTORELEASE) + +PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/ssdk-shell.git +PKG_SOURCE_PROTO:=git +PKG_SOURCE_DATE:=2022-03-16 +PKG_SOURCE_VERSION:=72a7dc725ae9ccbe7d99f451a6518e7c0dde4740 +PKG_MIRROR_HASH:=a591875ad05d7a6779cf9da575d890bc470889308f239c89a14721924420ac2b + +include $(INCLUDE_DIR)/kernel.mk +include $(INCLUDE_DIR)/package.mk + +define Package/qca-ssdk-shell + SECTION:=QCA + CATEGORY:=Utilities + TITLE:=Shell application for QCA SSDK +endef + + +define Package/qca-ssdk-shell/Description + This package contains a qca-ssdk shell application for QCA chipset +endef + +ifndef CONFIG_TOOLCHAIN_BIN_PATH +CONFIG_TOOLCHAIN_BIN_PATH=$(TOOLCHAIN_DIR)/bin +endif + +QCASSDK_CONFIG_OPTS+= TOOL_PATH=$(CONFIG_TOOLCHAIN_BIN_PATH) \ + SYS_PATH=$(LINUX_DIR) \ + TOOLPREFIX=$(TARGET_CROSS) \ + KVER=$(LINUX_VERSION) \ + CFLAGS="$(TARGET_CFLAGS)" \ + LDFLAGS="$(TARGET_LDFLAGS)" \ + ARCH=$(LINUX_KARCH) + +define Build/Compile + $(MAKE) -C $(PKG_BUILD_DIR) $(strip $(QCASSDK_CONFIG_OPTS)) +endef + +define Package/qca-ssdk-shell/install + $(INSTALL_DIR) $(1)/usr/sbin + $(INSTALL_BIN) $(PKG_BUILD_DIR)/build/bin/ssdk_sh $(1)/usr/sbin/ +endef + + +$(eval $(call BuildPackage,qca-ssdk-shell)) diff --git a/qca/qca-ssdk/Makefile b/qca/qca-ssdk/Makefile new file mode 100644 index 000000000..5b1a7956f --- /dev/null +++ b/qca/qca-ssdk/Makefile @@ -0,0 +1,91 @@ +include $(TOPDIR)/rules.mk + +PKG_NAME:=qca-ssdk +PKG_RELEASE:=$(AUTORELEASE) + +PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/qca-ssdk.git +PKG_SOURCE_PROTO:=git +PKG_SOURCE_DATE:=2022-04-07 +PKG_SOURCE_VERSION:=62955de3c838028d3f72313eef99c57fa4babb71 +PKG_MIRROR_HASH:=84c7de6d1ce82fb15acebea0e44158695a33ed6f18335da32ec9f248dcb4b285 + +include $(INCLUDE_DIR)/kernel.mk +include $(INCLUDE_DIR)/package.mk + +define KernelPackage/qca-ssdk-nohnat + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=Kernel driver for QCA SSDK + DEPENDS:=@(TARGET_ipq807x) + FILES:=$(PKG_BUILD_DIR)/build/bin/qca-ssdk.ko + AUTOLOAD:=$(call AutoLoad,30,qca-ssdk) +endef + +define KernelPackage/qca-ssdk-nohnat/Description +This package contains a qca-ssdk driver for QCA chipset +endef + +GCC_VERSION=$(shell echo "$(CONFIG_GCC_VERSION)" | sed 's/[^0-9.]*\([0-9.]*\).*/\1/') + +ifdef CONFIG_TOOLCHAIN_BIN_PATH +TOOLCHAIN_BIN_PATH=$(CONFIG_TOOLCHAIN_BIN_PATH) +else +TOOLCHAIN_BIN_PATH=$(TOOLCHAIN_DIR)/bin +endif + +MAKE_FLAGS+= \ + TARGET_NAME=$(CONFIG_TARGET_NAME) \ + TOOL_PATH=$(TOOLCHAIN_BIN_PATH) \ + SYS_PATH=$(LINUX_DIR) \ + TOOLPREFIX=$(TARGET_CROSS) \ + KVER=$(LINUX_VERSION) \ + ARCH=$(LINUX_KARCH) \ + TARGET_SUFFIX=$(CONFIG_TARGET_SUFFIX) \ + GCC_VERSION=$(GCC_VERSION) \ + EXTRA_CFLAGS=-fno-stack-protector -I$(STAGING_DIR)/usr/include \ + $(KERNEL_MAKE_FLAGS) + +ifneq (, $(findstring $(CONFIG_TARGET_BOARD), "ipq60xx" "ipq807x")) + MAKE_FLAGS+= PTP_FEATURE=disable SWCONFIG_FEATURE=disable +endif + +ifeq ($(CONFIG_TARGET_BOARD), "ipq807x") + MAKE_FLAGS+= CHIP_TYPE=HPPE +else ifeq ($(CONFIG_TARGET_BOARD), "ipq60xx") + MAKE_FLAGS+= CHIP_TYPE=CPPE +endif + +define Build/InstallDev + $(INSTALL_DIR) $(1)/usr/include/qca-ssdk + $(INSTALL_DIR) $(1)/usr/include/qca-ssdk/api + $(INSTALL_DIR) $(1)/usr/include/qca-ssdk/ref + $(INSTALL_DIR) $(1)/usr/include/qca-ssdk/fal + $(INSTALL_DIR) $(1)/usr/include/qca-ssdk/sal + $(INSTALL_DIR) $(1)/usr/include/qca-ssdk/init + $(CP) -rf $(PKG_BUILD_DIR)/include/api/sw_ioctl.h $(1)/usr/include/qca-ssdk/api + if [ -f $(PKG_BUILD_DIR)/include/ref/ref_vsi.h ]; then \ + $(CP) -rf $(PKG_BUILD_DIR)/include/ref/ref_vsi.h $(1)/usr/include/qca-ssdk/ref/; \ + fi + if [ -f $(PKG_BUILD_DIR)/include/ref/ref_fdb.h ]; then \ + $(CP) -rf $(PKG_BUILD_DIR)/include/ref/ref_fdb.h $(1)/usr/include/qca-ssdk/ref/; \ + fi + if [ -f $(PKG_BUILD_DIR)/include/ref/ref_port_ctrl.h ]; then \ + $(CP) -rf $(PKG_BUILD_DIR)/include/ref/ref_port_ctrl.h $(1)/usr/include/qca-ssdk/ref/; \ + fi + if [ -f $(PKG_BUILD_DIR)/include/init/ssdk_init.h ]; then \ + $(CP) -rf $(PKG_BUILD_DIR)/include/init/ssdk_init.h $(1)/usr/include/qca-ssdk/init/; \ + fi + $(CP) -rf $(PKG_BUILD_DIR)/include/fal $(1)/usr/include/qca-ssdk + $(CP) -rf $(PKG_BUILD_DIR)/include/common/*.h $(1)/usr/include/qca-ssdk + $(CP) -rf $(PKG_BUILD_DIR)/include/sal/os/linux/*.h $(1)/usr/include/qca-ssdk + $(CP) -rf $(PKG_BUILD_DIR)/include/sal/os/*.h $(1)/usr/include/qca-ssdk + +endef + +define KernelPackage/qca-ssdk-nohnat/install + $(INSTALL_DIR) $(1)/etc/init.d + $(INSTALL_BIN) ./files/qca-ssdk $(1)/etc/init.d/qca-ssdk +endef + +$(eval $(call KernelPackage,qca-ssdk-nohnat)) diff --git a/qca/qca-ssdk/files/qca-ssdk b/qca/qca-ssdk/files/qca-ssdk new file mode 100644 index 000000000..389279c0c --- /dev/null +++ b/qca/qca-ssdk/files/qca-ssdk @@ -0,0 +1,206 @@ +#!/bin/sh /etc/rc.common +# Copyright (c) 2018, The Linux Foundation. All rights reserved. +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +# + +START=16 + +#!/bin/sh +ruletype="ip4 ip6" +side="wan lan" +qwan="1 3 2 0 5 7 6 4" +qlan="0 1 2 3 4 5 6 7" + +function create_war_acl_rules(){ + for lw in $side + do + #echo $lw + if [ "$lw" == "wan" ];then + listid=254 + queue=$qwan + portmap=0x20 + else + listid=255 + queue=$qlan + portmap=0x1e + fi + #echo $queue + #echo "creating list $listid" + ssdk_sh acl list create $listid 255 + ruleid=0 + for rt in $ruletype + do + for qid in $queue + do + cmd="ssdk_sh acl rule add $listid $ruleid 1 n 0 0" + #echo $cmd + if [ "$rt" == "ip4" ];then + cmd="$cmd ip4 n n n n n n n n n n n n n n n n n n n n n n n n n n n n n" + #echo $cmd + else + cmd="$cmd ip6 n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n" + #echo $cmd + fi + if [ $ruleid -le 3 ];then + #non-zero dscp + cmd="$cmd y 0x0 0xff" + elif [ $ruleid -le 7 ];then + #zero dscp + cmd="$cmd n" + elif [ $ruleid -le 11 ];then + #non-zero dscp + cmd="$cmd y 0x0 0xff" + else + #zero dscp + cmd="$cmd n" + fi + p=$((ruleid/2)) + cmd="$cmd y mask $((ruleid%2)) 0x1 y mask $((p%2)) 0x1 n n n n n n n n n n n n n n n y n n n n n n n y $qid n n 0 0 n n n n n n n n n n n n n n n n n n n n 0" + #echo $cmd + $cmd + ruleid=`expr $ruleid + 1` + done + done + ssdk_sh acl list bind $listid 0 1 $portmap + done +} + +function create_war_cosmap(){ + ssdk_sh cosmap pri2q set 0 0 + ssdk_sh cosmap pri2q set 1 0 + ssdk_sh cosmap pri2q set 2 0 + ssdk_sh cosmap pri2q set 3 0 + ssdk_sh cosmap pri2q set 4 1 + ssdk_sh cosmap pri2q set 5 1 + ssdk_sh cosmap pri2q set 6 1 + ssdk_sh cosmap pri2q set 7 1 + ssdk_sh cosmap pri2ehq set 0 0 + ssdk_sh cosmap pri2ehq set 1 0 + ssdk_sh cosmap pri2ehq set 2 0 + ssdk_sh cosmap pri2ehq set 3 0 + ssdk_sh cosmap pri2ehq set 4 1 + ssdk_sh cosmap pri2ehq set 5 1 + ssdk_sh cosmap pri2ehq set 6 1 + ssdk_sh cosmap pri2ehq set 7 1 +} + +function create_acl_byp_egstp_rules(){ + ssdk_sh debug module_func set servcode 0xf 0x0 0x0 + ssdk_sh servcode config set 1 n 0 0xfffefc7f 0xffbdff 0 0 0 0 0 0 + ssdk_sh debug module_func set servcode 0x0 0x0 0x0 + ssdk_sh acl list create 56 48 + ssdk_sh acl rule add 56 0 1 n 0 0 mac n n n n n y 01-80-c2-00-00-00 ff-ff-ff-ff-ff-ff n n n n n n n n n n n n n n n n n n n n n n n y n n n n n n n n n n 0 0 n n n n n n n n n n n n n y n n n n n n n n n n n n y n n n n n n n n n n n n 0 + ssdk_sh acl rule add 56 1 1 n 0 0 mac n n n n n n n yes 0x8809 0xffff n n n n n n n n n n n n n n n n n n n n n y n n n n n n n n n n 0 0 n n n n n n n n n n n n n y n n n n n n n n n n n n y n n n n n n n n n n n n 0 + ssdk_sh acl rule add 56 2 1 n 0 0 mac n n n n n n n yes 0x888e 0xffff n n n n n n n n n n n n n n n n n n n n n y n n n n n n n n n n 0 0 n n n n n n n n n n n n n y n n n n n n n n n n n n y n n n n n n n n n n n n 0 + ssdk_sh acl list bind 56 0 2 1 +} + +function delete_war_acl_rules(){ + for lw in $side + do + #echo $lw + if [ "$lw" == "wan" ];then + listid=254 + queue=$qwan + portmap=0x20 + else + listid=255 + queue=$qlan + portmap=0x1e + fi + ssdk_sh acl list unbind $listid 0 1 $portmap + for rt in $ruletype + do + for qid in $queue + do + cmd="ssdk_sh acl rule del $listid 0 1" + echo $cmd + $cmd + done + done + #echo "deleting list $listid" + ssdk_sh acl list destroy $listid + done +} + +function delete_war_cosmap(){ + ssdk_sh cosmap pri2q set 0 0 + ssdk_sh cosmap pri2q set 1 0 + ssdk_sh cosmap pri2q set 2 1 + ssdk_sh cosmap pri2q set 3 1 + ssdk_sh cosmap pri2q set 4 2 + ssdk_sh cosmap pri2q set 5 2 + ssdk_sh cosmap pri2q set 6 3 + ssdk_sh cosmap pri2q set 7 3 + ssdk_sh cosmap pri2ehq set 0 1 + ssdk_sh cosmap pri2ehq set 1 0 + ssdk_sh cosmap pri2ehq set 2 2 + ssdk_sh cosmap pri2ehq set 3 2 + ssdk_sh cosmap pri2ehq set 4 3 + ssdk_sh cosmap pri2ehq set 5 3 + ssdk_sh cosmap pri2ehq set 6 4 + ssdk_sh cosmap pri2ehq set 7 5 +} + +function delete_acl_byp_egstp_rules(){ + ssdk_sh debug module_func set servcode 0xf 0x0 0x0 + ssdk_sh servcode config set 1 n 0 0xfffefcff 0xffbfff 0 0 0 0 0 0 + ssdk_sh debug module_func set servcode 0x0 0x0 0x0 + ssdk_sh acl list unbind 56 0 2 1 + ssdk_sh acl rule del 56 0 1 + ssdk_sh acl rule del 56 1 1 + ssdk_sh acl rule del 56 2 1 + ssdk_sh acl list destroy 56 +} + +function edma_war_config_add(){ + create_war_cosmap + ssdk_sh acl status set enable + create_war_acl_rules +} + +function edma_war_config_del(){ + delete_war_acl_rules + delete_war_cosmap +} + +start() { + chip_ver=`ssdk_sh debug reg get 0 4 | grep Data | tr -d 'SSDK Init OK![Data]:'` + #The following commands should be uncommented to enable EDMA WAR + if [ "$chip_ver" = "0x1401" ]; then + #edma_war_config_add + echo '' + fi + #The following commands should be uncommented to add acl egress stp bypass rules + if [ "$chip_ver" = "0x1500" ] || [ "$chip_ver" = "0x1501" ]; then + #create_acl_byp_egstp_rules + echo '' + fi + echo starting +} + +stop() { + chip_ver=`ssdk_sh debug reg get 0 4 | grep Data | tr -d 'SSDK Init OK![Data]:'` + #The following commands should be uncommented to disable EDMA WAR + if [ "$chip_ver" = "0x1401" ]; then + #edma_war_config_del + echo '' + fi + #The following commands should be uncommented to delete acl egress stp bypass rules + if [ "$chip_ver" = "0x1500" ] || [ "$chip_ver" = "0x1501" ]; then + #delete_acl_byp_egstp_rules + echo '' + fi + echo stoping +} diff --git a/qca/qca-ssdk/patches/0001-SSDK-config-add-kernel-5.10.patch b/qca/qca-ssdk/patches/0001-SSDK-config-add-kernel-5.10.patch new file mode 100644 index 000000000..8ad541ebf --- /dev/null +++ b/qca/qca-ssdk/patches/0001-SSDK-config-add-kernel-5.10.patch @@ -0,0 +1,56 @@ +From 472c0c8132784608312c80c4b02c03ea7c132235 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Wed, 12 May 2021 13:41:12 +0200 +Subject: [PATCH] SSDK: config: add kernel 5.10 + +This is purely to identify it and be able to set +flags correctly. + +Signed-off-by: Robert Marko +--- + config | 6 +++++- + make/linux_opt.mk | 4 ++-- + 2 files changed, 7 insertions(+), 3 deletions(-) + +--- a/config ++++ b/config +@@ -22,6 +22,10 @@ ifeq ($(KVER),$(filter 5.4%,$(KVER))) + OS_VER=5_4 + endif + ++ifeq ($(KVER),$(filter 5.10%,$(KVER))) ++OS_VER=5_10 ++endif ++ + ifeq ($(KVER), 3.4.0) + OS_VER=3_4 + endif +@@ -123,7 +127,7 @@ endif + endif + + ifeq ($(ARCH), arm64) +- ifeq ($(KVER),$(filter 4.1% 4.4% 4.9% 5.4%,$(KVER))) ++ ifeq ($(KVER),$(filter 4.1% 4.4% 4.9% 5.4% 5.10%,$(KVER))) + CPU_CFLAG= -DMODULE -Os -pipe -march=armv8-a -mcpu=cortex-a53+crypto -fno-caller-saves -fno-strict-aliasing -Werror -fno-common -Wno-format-security -Wno-pointer-sign -Wno-unused-but-set-variable -Wno-error=unused-result -mcmodel=large + endif + endif +--- a/make/linux_opt.mk ++++ b/make/linux_opt.mk +@@ -388,7 +388,7 @@ ifeq (KSLIB, $(MODULE_TYPE)) + KASAN_SHADOW_SCALE_SHIFT := 3 + endif + +- ifeq (5_4, $(OS_VER)) ++ ifeq ($(OS_VER),$(filter 5_4 5_10, $(OS_VER))) + ifeq ($(ARCH), arm64) + KASAN_OPTION += -DKASAN_SHADOW_SCALE_SHIFT=$(KASAN_SHADOW_SCALE_SHIFT) + endif +@@ -419,7 +419,7 @@ ifeq (KSLIB, $(MODULE_TYPE)) + + endif + +- ifeq ($(OS_VER),$(filter 4_4 5_4, $(OS_VER))) ++ ifeq ($(OS_VER),$(filter 4_4 5_4 5_10, $(OS_VER))) + MODULE_CFLAG += -DKVER34 + MODULE_CFLAG += -DKVER32 + MODULE_CFLAG += -DLNX26_22 diff --git a/qca/qca-ssdk/patches/0002-SSDK-replace-ioremap_nocache-with-ioremap.patch b/qca/qca-ssdk/patches/0002-SSDK-replace-ioremap_nocache-with-ioremap.patch new file mode 100644 index 000000000..b293ad295 --- /dev/null +++ b/qca/qca-ssdk/patches/0002-SSDK-replace-ioremap_nocache-with-ioremap.patch @@ -0,0 +1,102 @@ +From 784f2cfdfaf3bdf44917924e157049230a0ef5f8 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Wed, 12 May 2021 13:45:45 +0200 +Subject: [PATCH] SSDK: replace ioremap_nocache with ioremap + +ioremap_nocache was dropped upstream, simply use the +generic variety. + +Signed-off-by: Robert Marko +--- + src/init/ssdk_clk.c | 10 +++++----- + src/init/ssdk_init.c | 2 +- + src/init/ssdk_plat.c | 6 +++--- + 3 files changed, 9 insertions(+), 9 deletions(-) + +--- a/src/init/ssdk_clk.c ++++ b/src/init/ssdk_clk.c +@@ -623,7 +623,7 @@ ssdk_mp_tcsr_get(a_uint32_t tcsr_offset, + { + void __iomem *tcsr_base = NULL; + +- tcsr_base = ioremap_nocache(TCSR_ETH_ADDR, TCSR_ETH_SIZE); ++ tcsr_base = ioremap(TCSR_ETH_ADDR, TCSR_ETH_SIZE); + if (!tcsr_base) + { + SSDK_ERROR("Failed to map tcsr eth address!\n"); +@@ -640,7 +640,7 @@ ssdk_mp_tcsr_set(a_uint32_t tcsr_offset, + { + void __iomem *tcsr_base = NULL; + +- tcsr_base = ioremap_nocache(TCSR_ETH_ADDR, TCSR_ETH_SIZE); ++ tcsr_base = ioremap(TCSR_ETH_ADDR, TCSR_ETH_SIZE); + if (!tcsr_base) + { + SSDK_ERROR("Failed to map tcsr eth address!\n"); +@@ -688,7 +688,7 @@ ssdk_mp_cmnblk_stable_check(void) + a_uint32_t reg_val; + int i, loops = 20; + +- pll_lock = ioremap_nocache(CMN_PLL_LOCKED_ADDR, CMN_PLL_LOCKED_SIZE); ++ pll_lock = ioremap(CMN_PLL_LOCKED_ADDR, CMN_PLL_LOCKED_SIZE); + if (!pll_lock) { + SSDK_ERROR("Failed to map CMN PLL LOCK register!\n"); + return A_FALSE; +@@ -745,7 +745,7 @@ static void ssdk_cmnblk_pll_src_set(enum + void __iomem *cmn_pll_src_base = NULL; + a_uint32_t reg_val; + +- cmn_pll_src_base = ioremap_nocache(CMN_BLK_PLL_SRC_ADDR, CMN_BLK_SIZE); ++ cmn_pll_src_base = ioremap(CMN_BLK_PLL_SRC_ADDR, CMN_BLK_SIZE); + if (!cmn_pll_src_base) { + SSDK_ERROR("Failed to map cmn pll source address!\n"); + return; +@@ -766,7 +766,7 @@ static void ssdk_cmnblk_init(enum cmnblk + void __iomem *gcc_pll_base = NULL; + a_uint32_t reg_val; + +- gcc_pll_base = ioremap_nocache(CMN_BLK_ADDR, CMN_BLK_SIZE); ++ gcc_pll_base = ioremap(CMN_BLK_ADDR, CMN_BLK_SIZE); + if (!gcc_pll_base) { + SSDK_ERROR("Failed to map gcc pll address!\n"); + return; +--- a/src/init/ssdk_init.c ++++ b/src/init/ssdk_init.c +@@ -2770,7 +2770,7 @@ static int ssdk_dess_mac_mode_init(a_uin + (a_uint8_t *)®_value, 4); + mdelay(10); + /*softreset psgmii, fixme*/ +- gcc_addr = ioremap_nocache(0x1812000, 0x200); ++ gcc_addr = ioremap(0x1812000, 0x200); + if (!gcc_addr) { + SSDK_ERROR("gcc map fail!\n"); + return 0; +--- a/src/init/ssdk_plat.c ++++ b/src/init/ssdk_plat.c +@@ -1312,7 +1312,7 @@ ssdk_plat_init(ssdk_init_cfg *cfg, a_uin + reg_mode = ssdk_uniphy_reg_access_mode_get(dev_id); + if(reg_mode == HSL_REG_LOCAL_BUS) { + ssdk_uniphy_reg_map_info_get(dev_id, &map); +- qca_phy_priv_global[dev_id]->uniphy_hw_addr = ioremap_nocache(map.base_addr, ++ qca_phy_priv_global[dev_id]->uniphy_hw_addr = ioremap(map.base_addr, + map.size); + if (!qca_phy_priv_global[dev_id]->uniphy_hw_addr) { + SSDK_ERROR("%s ioremap fail.", __func__); +@@ -1327,7 +1327,7 @@ ssdk_plat_init(ssdk_init_cfg *cfg, a_uin + reg_mode = ssdk_switch_reg_access_mode_get(dev_id); + if(reg_mode == HSL_REG_LOCAL_BUS) { + ssdk_switch_reg_map_info_get(dev_id, &map); +- qca_phy_priv_global[dev_id]->hw_addr = ioremap_nocache(map.base_addr, ++ qca_phy_priv_global[dev_id]->hw_addr = ioremap(map.base_addr, + map.size); + if (!qca_phy_priv_global[dev_id]->hw_addr) { + SSDK_ERROR("%s ioremap fail.", __func__); +@@ -1358,7 +1358,7 @@ ssdk_plat_init(ssdk_init_cfg *cfg, a_uin + return -1; + } + +- qca_phy_priv_global[dev_id]->psgmii_hw_addr = ioremap_nocache(map.base_addr, ++ qca_phy_priv_global[dev_id]->psgmii_hw_addr = ioremap(map.base_addr, + map.size); + if (!qca_phy_priv_global[dev_id]->psgmii_hw_addr) { + SSDK_ERROR("%s ioremap fail.", __func__); diff --git a/qca/qca-ssdk/patches/0004-platform-use-of_mdio_find_bus-to-get-MDIO-bus.patch b/qca/qca-ssdk/patches/0004-platform-use-of_mdio_find_bus-to-get-MDIO-bus.patch new file mode 100644 index 000000000..3bcbcccf6 --- /dev/null +++ b/qca/qca-ssdk/patches/0004-platform-use-of_mdio_find_bus-to-get-MDIO-bus.patch @@ -0,0 +1,40 @@ +From b6190ca46287d01a895c7cc14de30410c09ff1b8 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Wed, 12 May 2021 17:15:46 +0200 +Subject: [PATCH] SSDK: platform: use of_mdio_find_bus() to get MDIO bus + +Kernel has a generic of_mdio_find_bus() which can get the appropriate +MDIO bus based on the DT node. +So, drop the getting MDIO from platform data, which no longer works +in 5.4 and later and use of_mdio_find_bus(). + +Signed-off-by: Baruch Siach +Signed-off-by: Robert Marko +--- + src/init/ssdk_plat.c | 8 +------- + 1 file changed, 1 insertion(+), 7 deletions(-) + +--- a/src/init/ssdk_plat.c ++++ b/src/init/ssdk_plat.c +@@ -551,7 +551,6 @@ static int miibus_get(a_uint32_t dev_id) + struct device_node *mdio_node = NULL; + struct device_node *switch_node = NULL; + struct platform_device *mdio_plat = NULL; +- struct ipq40xx_mdio_data *mdio_data = NULL; + struct qca_phy_priv *priv; + hsl_reg_mode reg_mode = HSL_REG_LOCAL_BUS; + priv = qca_phy_priv_global[dev_id]; +@@ -584,12 +583,7 @@ static int miibus_get(a_uint32_t dev_id) + + if(reg_mode == HSL_REG_LOCAL_BUS) + { +- mdio_data = dev_get_drvdata(&mdio_plat->dev); +- if (!mdio_data) { +- SSDK_ERROR("cannot get mdio_data reference from device data\n"); +- return 1; +- } +- priv->miibus = mdio_data->mii_bus; ++ priv->miibus = of_mdio_find_bus(mdio_node); + } + else + priv->miibus = dev_get_drvdata(&mdio_plat->dev); diff --git a/qca/qca-ssdk/patches/0005-SSDK-dts-fix-of_get_mac_address.patch b/qca/qca-ssdk/patches/0005-SSDK-dts-fix-of_get_mac_address.patch new file mode 100644 index 000000000..29be93128 --- /dev/null +++ b/qca/qca-ssdk/patches/0005-SSDK-dts-fix-of_get_mac_address.patch @@ -0,0 +1,42 @@ +From f3a7b93137c1a6a1b8010b86296242178eed5d9e Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Fri, 13 Aug 2021 20:03:21 +0200 +Subject: [PATCH] SSDK: dts: fix of_get_mac_address() + +Recently OpenWrt backported the updated of_get_mac_address() +function which returns and error code instead. + +So, patch the SSDK to use it and fix the compilation error. + +Signed-off-by: Robert Marko +--- + src/init/ssdk_dts.c | 7 ++++--- + 1 file changed, 4 insertions(+), 3 deletions(-) + +--- a/src/init/ssdk_dts.c ++++ b/src/init/ssdk_dts.c +@@ -779,8 +779,9 @@ static void ssdk_dt_parse_intf_mac(void) + { + struct device_node *dp_node = NULL; + a_uint32_t dp = 0; +- a_uint8_t *maddr = NULL; ++ u8 maddr[ETH_ALEN]; + char dp_name[8] = {0}; ++ int ret; + + for (dp = 1; dp <= SSDK_MAX_NR_ETH; dp++) { + snprintf(dp_name, sizeof(dp_name), "dp%d", dp); +@@ -788,11 +789,11 @@ static void ssdk_dt_parse_intf_mac(void) + if (!dp_node) { + continue; + } +- maddr = (a_uint8_t *)of_get_mac_address(dp_node); ++ ret = of_get_mac_address(dp_node, maddr); + #if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0)) + if (maddr && is_valid_ether_addr(maddr)) { + #else +- if (!IS_ERR(maddr) && is_valid_ether_addr(maddr)) { ++ if (!ret && is_valid_ether_addr(maddr)) { + #endif + ssdk_dt_global.num_intf_mac++; + ether_addr_copy(ssdk_dt_global.intf_mac[dp-1].uc, maddr); diff --git a/qca/qca-ssdk/patches/0006-SSDK-config-add-kernel-5.15.patch b/qca/qca-ssdk/patches/0006-SSDK-config-add-kernel-5.15.patch new file mode 100644 index 000000000..a4e1b2782 --- /dev/null +++ b/qca/qca-ssdk/patches/0006-SSDK-config-add-kernel-5.15.patch @@ -0,0 +1,56 @@ +From 599f19551dc8db3cb396e4c139a73bd72300ebf5 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Fri, 24 Dec 2021 19:39:02 +0100 +Subject: [PATCH] SSDK: config: add kernel 5.15 + +This is purely to identify it and be able to set +flags correctly. + +Signed-off-by: Robert Marko +--- + config | 6 +++++- + make/linux_opt.mk | 4 ++-- + 2 files changed, 7 insertions(+), 3 deletions(-) + +--- a/config ++++ b/config +@@ -26,6 +26,10 @@ ifeq ($(KVER),$(filter 5.10%,$(KVER))) + OS_VER=5_10 + endif + ++ifeq ($(KVER),$(filter 5.15%,$(KVER))) ++OS_VER=5_15 ++endif ++ + ifeq ($(KVER), 3.4.0) + OS_VER=3_4 + endif +@@ -127,7 +131,7 @@ endif + endif + + ifeq ($(ARCH), arm64) +- ifeq ($(KVER),$(filter 4.1% 4.4% 4.9% 5.4% 5.10%,$(KVER))) ++ ifeq ($(KVER),$(filter 4.1% 4.4% 4.9% 5.4% 5.10% 5.15%,$(KVER))) + CPU_CFLAG= -DMODULE -Os -pipe -march=armv8-a -mcpu=cortex-a53+crypto -fno-caller-saves -fno-strict-aliasing -Werror -fno-common -Wno-format-security -Wno-pointer-sign -Wno-unused-but-set-variable -Wno-error=unused-result -mcmodel=large + endif + endif +--- a/make/linux_opt.mk ++++ b/make/linux_opt.mk +@@ -388,7 +388,7 @@ ifeq (KSLIB, $(MODULE_TYPE)) + KASAN_SHADOW_SCALE_SHIFT := 3 + endif + +- ifeq ($(OS_VER),$(filter 5_4 5_10, $(OS_VER))) ++ ifeq ($(OS_VER),$(filter 5_4 5_10 5_15, $(OS_VER))) + ifeq ($(ARCH), arm64) + KASAN_OPTION += -DKASAN_SHADOW_SCALE_SHIFT=$(KASAN_SHADOW_SCALE_SHIFT) + endif +@@ -419,7 +419,7 @@ ifeq (KSLIB, $(MODULE_TYPE)) + + endif + +- ifeq ($(OS_VER),$(filter 4_4 5_4 5_10, $(OS_VER))) ++ ifeq ($(OS_VER),$(filter 4_4 5_4 5_10 5_15, $(OS_VER))) + MODULE_CFLAG += -DKVER34 + MODULE_CFLAG += -DKVER32 + MODULE_CFLAG += -DLNX26_22 diff --git a/qca/qca-ssdk/patches/0007-qca8081-convert-to-5.11-IRQ-model.patch b/qca/qca-ssdk/patches/0007-qca8081-convert-to-5.11-IRQ-model.patch new file mode 100644 index 000000000..b0c272b17 --- /dev/null +++ b/qca/qca-ssdk/patches/0007-qca8081-convert-to-5.11-IRQ-model.patch @@ -0,0 +1,83 @@ +From 25ff0ae02accadd7b05f1dae788505f833d5c019 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Fri, 24 Dec 2021 20:02:32 +0100 +Subject: [PATCH] qca8081: convert to 5.11 IRQ model + +Kernel 5.11 introduced new IRQ handling model for PHY-s, +so provide those if 5.11 or later is used. + +Signed-off-by: Robert Marko +--- + src/hsl/phy/qca808x.c | 46 +++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 46 insertions(+) + +--- a/src/hsl/phy/qca808x.c ++++ b/src/hsl/phy/qca808x.c +@@ -238,6 +238,7 @@ static int qca808x_config_intr(struct ph + return err; + } + ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 11, 0)) + static int qca808x_ack_interrupt(struct phy_device *phydev) + { + int err; +@@ -257,6 +258,47 @@ static int qca808x_ack_interrupt(struct + + return (err < 0) ? err : 0; + } ++#endif ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(5, 11, 0)) ++static irqreturn_t qca808x_handle_interrupt(struct phy_device *phydev) ++{ ++ a_uint16_t irq_status, int_enabled; ++ a_uint32_t dev_id = 0, phy_id = 0; ++ qca808x_priv *priv = phydev->priv; ++ const struct qca808x_phy_info *pdata = priv->phy_info; ++ ++ if (!pdata) { ++ return SW_FAIL; ++ } ++ ++ dev_id = pdata->dev_id; ++ phy_id = pdata->phy_addr; ++ ++ irq_status = qca808x_phy_reg_read(dev_id, phy_id, ++ QCA808X_PHY_INTR_STATUS); ++ if (irq_status < 0) { ++ phy_error(phydev); ++ return IRQ_NONE; ++ } ++ ++ /* Read the current enabled interrupts */ ++ int_enabled = qca808x_phy_reg_read(dev_id, phy_id, ++ QCA808X_PHY_INTR_MASK); ++ if (int_enabled < 0) { ++ phy_error(phydev); ++ return IRQ_NONE; ++ } ++ ++ /* See if this was one of our enabled interrupts */ ++ if (!(irq_status & int_enabled)) ++ return IRQ_NONE; ++ ++ phy_trigger_machine(phydev); ++ ++ return IRQ_HANDLED; ++} ++#endif + + /* switch linux negtiation capability to fal avariable */ + #if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0)) +@@ -559,7 +601,11 @@ struct phy_driver qca808x_phy_driver = { + .config_intr = qca808x_config_intr, + .config_aneg = qca808x_config_aneg, + .aneg_done = qca808x_aneg_done, ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 11, 0)) + .ack_interrupt = qca808x_ack_interrupt, ++#else ++ .handle_interrupt = qca808x_handle_interrupt, ++#endif + .read_status = qca808x_read_status, + .suspend = qca808x_suspend, + .resume = qca808x_resume, diff --git a/qca/qca-ssdk/patches/0008-qca807x-add-a-LED-quirk-for-Xiaomi-AX9000.patch b/qca/qca-ssdk/patches/0008-qca807x-add-a-LED-quirk-for-Xiaomi-AX9000.patch new file mode 100644 index 000000000..76f71be46 --- /dev/null +++ b/qca/qca-ssdk/patches/0008-qca807x-add-a-LED-quirk-for-Xiaomi-AX9000.patch @@ -0,0 +1,74 @@ +From 86624624c2b593c57999780a3838e6a9fe40b30c Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Tue, 11 Jan 2022 00:28:42 +0100 +Subject: [PATCH] qca807x: add a LED quirk for Xiaomi AX9000 + +Xiaomi AX9000 has a single LED for each of 4 gigabit ethernet ports that +are connected to QCA8075, and that LED is connected to the 100M LED pin. + +So, by default it will only work when in 10 or 100Mbit mode, this is quite +annoying and makes no sense(If they have connected it to the 1000Mbit LED +pin then it would have worked for 10/100 by default as well). + +So, to solve this add a check for system compatible as we cant parse if +from DTS in any other way and set the 100M LED to blink on 1000Base-T +as well. + +Signed-off-by: Robert Marko +--- + include/hsl/phy/malibu_phy.h | 2 ++ + src/hsl/phy/malibu_phy.c | 11 +++++++++++ + 2 files changed, 13 insertions(+) + +diff --git a/include/hsl/phy/malibu_phy.h b/include/hsl/phy/malibu_phy.h +index b7354041..ec7a0621 100755 +--- a/include/hsl/phy/malibu_phy.h ++++ b/include/hsl/phy/malibu_phy.h +@@ -94,6 +94,7 @@ extern "C" + #define MALIBU_DAC_CTRL_MASK 0x380 + #define MALIBU_DAC_CTRL_VALUE 0x280 + #define MALIBU_LED_1000_CTRL1_100_10_MASK 0x30 ++#define MALIBU_LED_100_CTRL1_1000_MASK 0x40 + + #define MALIBU_PHY_EEE_ADV_100M 0x0002 + #define MALIBU_PHY_EEE_ADV_1000M 0x0004 +@@ -118,6 +119,7 @@ extern "C" + #define MALIBU_PHY_MMD7_EGRESS_COUNTER_HIGH 0x802d + #define MALIBU_PHY_MMD7_EGRESS_COUNTER_LOW 0x802e + #define MALIBU_PHY_MMD7_EGRESS_ERROR_COUNTER 0x802f ++#define MALIBU_PHY_MMD7_LED_100_CTRL1 0x8074 + #define MALIBU_PHY_MMD7_LED_1000_CTRL1 0x8076 + + +diff --git a/src/hsl/phy/malibu_phy.c b/src/hsl/phy/malibu_phy.c +index 1f4dba15..2bef9fa3 100644 +--- a/src/hsl/phy/malibu_phy.c ++++ b/src/hsl/phy/malibu_phy.c +@@ -12,6 +12,8 @@ + * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + ++#include ++ + #include "sw.h" + #include "fal_port_ctrl.h" + #include "hsl_api.h" +@@ -2726,6 +2728,15 @@ malibu_phy_hw_init(a_uint32_t dev_id, a_uint32_t port_bmp) + led_status |= MALIBU_LED_1000_CTRL1_100_10_MASK; + malibu_phy_mmd_write(dev_id, phy_addr, MALIBU_PHY_MMD7_NUM, + MALIBU_PHY_MMD7_LED_1000_CTRL1, led_status); ++ if (of_machine_is_compatible("xiaomi,ax9000")) { ++ /* add 1000M link LED behavior for Xiaomi AX9000 */ ++ led_status = malibu_phy_mmd_read(dev_id, phy_addr, MALIBU_PHY_MMD7_NUM, ++ MALIBU_PHY_MMD7_LED_100_CTRL1); ++ led_status &= ~MALIBU_LED_100_CTRL1_1000_MASK; ++ led_status |= MALIBU_LED_100_CTRL1_1000_MASK; ++ malibu_phy_mmd_write(dev_id, phy_addr, MALIBU_PHY_MMD7_NUM, ++ MALIBU_PHY_MMD7_LED_100_CTRL1, led_status); ++ } + /*disable Extended next page*/ + phy_data = malibu_phy_reg_read(dev_id, phy_addr, MALIBU_AUTONEG_ADVERT); + phy_data &= ~MALIBU_EXTENDED_NEXT_PAGE_EN; +-- +2.34.1 + diff --git a/qca/qca-ssdk/patches/0009-qca807x-add-a-LED-quirk-for-Xiaomi-AX3600.patch b/qca/qca-ssdk/patches/0009-qca807x-add-a-LED-quirk-for-Xiaomi-AX3600.patch new file mode 100644 index 000000000..c31ea6da9 --- /dev/null +++ b/qca/qca-ssdk/patches/0009-qca807x-add-a-LED-quirk-for-Xiaomi-AX3600.patch @@ -0,0 +1,29 @@ +From 913514b9177e77836f2c8d61fc498b54f54c6775 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Wed, 26 Jan 2022 14:47:33 +0100 +Subject: [PATCH] qca807x: add a LED quirk for Xiaomi AX3600 + +AX3600 requires the same LED quirk so that PHY LED-s will blink even +once Linux resets the PHY. + +So, just check for its compatible. + +Signed-off-by: Robert Marko +--- + src/hsl/phy/malibu_phy.c | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +--- a/src/hsl/phy/malibu_phy.c ++++ b/src/hsl/phy/malibu_phy.c +@@ -2728,8 +2728,9 @@ malibu_phy_hw_init(a_uint32_t dev_id, a_ + led_status |= MALIBU_LED_1000_CTRL1_100_10_MASK; + malibu_phy_mmd_write(dev_id, phy_addr, MALIBU_PHY_MMD7_NUM, + MALIBU_PHY_MMD7_LED_1000_CTRL1, led_status); +- if (of_machine_is_compatible("xiaomi,ax9000")) { +- /* add 1000M link LED behavior for Xiaomi AX9000 */ ++ /* add 1000M link LED behavior for Xiaomi boards */ ++ if (of_machine_is_compatible("xiaomi,ax9000") || ++ of_machine_is_compatible("xiaomi,ax3600")) { + led_status = malibu_phy_mmd_read(dev_id, phy_addr, MALIBU_PHY_MMD7_NUM, + MALIBU_PHY_MMD7_LED_100_CTRL1); + led_status &= ~MALIBU_LED_100_CTRL1_1000_MASK; diff --git a/qca/qca-ssdk/patches/0012-include-fix-compilation-error-for-parse_uci_option.patch b/qca/qca-ssdk/patches/0012-include-fix-compilation-error-for-parse_uci_option.patch new file mode 100644 index 000000000..01b8deda9 --- /dev/null +++ b/qca/qca-ssdk/patches/0012-include-fix-compilation-error-for-parse_uci_option.patch @@ -0,0 +1,27 @@ +From 8e3500df074625b3eb3a8ed4e8e0b1b116f13d0c Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Sat, 7 May 2022 19:03:55 +0200 +Subject: [PATCH] include: fix compilation error for parse_uci_option + +Fix missing include for parse_uci_option + +Signed-off-by: Ansuel Smith +--- + include/ref/ref_uci.h | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/include/ref/ref_uci.h b/include/ref/ref_uci.h +index a42ea153..0906c5ba 100755 +--- a/include/ref/ref_uci.h ++++ b/include/ref/ref_uci.h +@@ -19,6 +19,7 @@ + extern "C" { + #endif /* __cplusplus */ + ++#include + + #if defined(IN_SWCONFIG) + int +-- +2.34.1 + From e4349ee2d5effe26b34f7aedcb7f7b8c6b4c21ee Mon Sep 17 00:00:00 2001 From: suyuan <175338101@qq.com> Date: Tue, 13 Sep 2022 16:52:05 +0800 Subject: [PATCH 18/19] fix --- qaa/firmware/nss-firmware/Makefile | 70 - qaa/nss/nss-ifb/Makefile | 49 - qaa/nss/nss-ifb/README.md | 45 - qaa/nss/nss-ifb/src/Makefile | 3 - qaa/nss/nss-ifb/src/nss_ifb.c | 304 - qaa/nss/qca-nss-cfi/Makefile | 99 - .../patches/0001-compile-only-cryptoapi.patch | 30 - .../patches/0002-wip-support-5.4.patch | 78 - .../0003-Convert-ablkcipher-to-skcipher.patch | 707 - qaa/nss/qca-nss-clients-64/Makefile | 97 - .../qca-nss-clients-64/files/qca-nss-ipsec | 214 - .../files/qca-nss-mirred.init | 28 - .../files/qca-nss-ovpn.init | 69 - qaa/nss/qca-nss-clients/Makefile | 469 - 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-PKG_MIRROR_HASH:=0c21afe29002754edf2983bc9e8543dddd722e75bd12e961e300e99a310d1f62 -PKG_RELEASE:=$(AUTORELEASE) - -PKG_SOURCE_PROTO:=git -PKG_SOURCE_URL:=https://github.com/quic/qca-sdk-nss-fw.git - -PKG_LICENSE_FILES:=LICENSE.md - -PKG_MAINTAINER:=Robert Marko - -include $(INCLUDE_DIR)/package.mk - -VERSION_PATH=$(PKG_BUILD_DIR)/QCA_Networking_2020.SPF_11.3/CS - -define Package/nss-firmware-default - SECTION:=firmware - CATEGORY:=Firmware - URL:=$(PKG_SOURCE_URL) - DEPENDS:=@(TARGET_ipq807x||TARGET_ipq60xx) -endef - -define Package/nss-firmware-ipq6018 -$(Package/nss-firmware-default) - TITLE:=NSS firmware for IPQ6018 devices - NSS_ARCHIVE:=$(VERSION_PATH)/IPQ6018.ATH.11.3/BIN-NSS.CP.11.3-9-R.tar.bz2 -endef - -define Package/nss-firmware-ipq8074 -$(Package/nss-firmware-default) - TITLE:=NSS firmware for IPQ8074 devices - NSS_ARCHIVE:=$(VERSION_PATH)/IPQ8074.ATH.11.3/BIN-NSS.HK.11.3-9-R.tar.bz2 -endef - -define Build/Compile - -endef - -define Package/nss-firmware-ipq6018/install - $(TAR) -C $(PKG_BUILD_DIR) -xf $(NSS_ARCHIVE) - $(INSTALL_DIR) $(1)/lib/firmware/ - $(INSTALL_DATA) \ - $(PKG_BUILD_DIR)/BIN-NSS.CP.11.3-9-R/retail_router0.bin \ - $(1)/lib/firmware/qca-nss0-retail.bin -endef - -define Package/nss-firmware-ipq8074/install - $(TAR) -C $(PKG_BUILD_DIR) -xf $(NSS_ARCHIVE) - $(INSTALL_DIR) $(1)/lib/firmware/ - $(INSTALL_DATA) \ - $(PKG_BUILD_DIR)/BIN-NSS.HK.11.3-9-R/retail_router0.bin \ - $(1)/lib/firmware/qca-nss0-retail.bin - $(INSTALL_DATA) \ - $(PKG_BUILD_DIR)/BIN-NSS.HK.11.3-9-R/retail_router1.bin \ - $(1)/lib/firmware/qca-nss1-retail.bin -endef - -$(eval $(call BuildPackage,nss-firmware-ipq6018)) -$(eval $(call BuildPackage,nss-firmware-ipq8074)) diff --git a/qaa/nss/nss-ifb/Makefile b/qaa/nss/nss-ifb/Makefile deleted file mode 100644 index 6b7f0b480..000000000 --- a/qaa/nss/nss-ifb/Makefile +++ /dev/null @@ -1,49 +0,0 @@ -# -# Copyright (C) 2008-2012 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# - -include $(TOPDIR)/rules.mk -include $(INCLUDE_DIR)/kernel.mk - -PKG_NAME:=nss-ifb -PKG_RELEASE:=1 - -include $(INCLUDE_DIR)/package.mk - -define KernelPackage/nss-ifb - SECTION:=kernel - CATEGORY:=Kernel modules - SUBMENU:=Network Devices - TITLE:=NSS IFB Interface - DEPENDS:=+kmod-qca-nss-drv @LINUX_5_4 - FILES:=$(PKG_BUILD_DIR)/nss-ifb.ko - KCONFIG:= -endef - -define KernelPackage/nss-ifb/description - Kernel module to register a NSS aware IFB interface. -endef - -EXTRA_KCONFIG:= \ - CONFIG_NET_CLS=y - -EXTRA_CFLAGS:= \ - -I$(STAGING_DIR)/usr/include/qca-nss-drv - -MAKE_OPTS:= \ - $(KERNEL_MAKE_FLAGS) \ - M="$(PKG_BUILD_DIR)" \ - EXTRA_CFLAGS="$(EXTRA_CFLAGS)" \ - $(EXTRA_KCONFIG) - -define Build/Compile - $(MAKE) -C "$(LINUX_DIR)" \ - $(MAKE_OPTS) \ - modules -endef - -$(eval $(call KernelPackage,nss-ifb)) - diff --git a/qaa/nss/nss-ifb/README.md b/qaa/nss/nss-ifb/README.md deleted file mode 100644 index a0af7a5eb..000000000 --- a/qaa/nss/nss-ifb/README.md +++ /dev/null @@ -1,45 +0,0 @@ -NSS Physical Interface Ingress Driver -===================================== - -This driver redirect NSS physical interface (namely GMACs) ingress traffic to itself -and sends it back to the Linux network stack (as the source GMACs packets) as it's -egress traffic. - -This allows the NSS QDISC drivers to manage the egress traffic of this driver's -NSS virtual interface. - -This driver will create a single network interface named 'nssifb'. The default -source interface is defined as 'eth0'. It can be changed using the following module -parameter path: - -/sys/module/nss-ifb/parameter/nss_src_dev - -To change the source NSS physical interface to 'eth1', use the following command: - -printf eth1 > /sys/module/nss-ifb/parameter/nss_src_dev - -You need to change the source interface first before bringing up the 'nssifb' -interface. Changing it after the interface is up will have no effect. You need -to bring down the interface and bring it back up to have the changes take effect. - -CPU load imposed on the Krait CPUs appears negligible with this driver intercepting -the physical interface's ingress traffic. Full line speed of the GMAC interface -could still be achieved. - -The commands below shows an example to shape ingress traffic to 500 Mbps and egress -to 200 Mbps for the 'eth0' interface. - -# Load the module if it's not loaded -modprobe nss-ifb - -# Bring up the nssifb interface to active ingress redirect -ip link set up nssifb - -# Shape ingress traffic to 500 Mbit with chained NSSFQ_CODEL -tc qdisc add dev nssifb root handle 1: nsstbl rate 500Mbit burst 1Mb -tc qdisc add dev nssifb parent 1: handle 10: nssfq_codel limit 10240 flows 1024 quantum 1514 target 5ms interval 100ms set_default - -# Shape egress traffic to 200 Mbit with chained NSSFQ_CODEL -tc qdisc add dev eth0 root handle 1: nsstbl rate 200Mbit burst 1Mb -tc qdisc add dev eth0 parent 1: handle 10: nssfq_codel limit 10240 flows 1024 quantum 1514 target 5ms interval 100ms set_default - diff --git a/qaa/nss/nss-ifb/src/Makefile b/qaa/nss/nss-ifb/src/Makefile deleted file mode 100644 index 332b9b4ed..000000000 --- a/qaa/nss/nss-ifb/src/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -obj-m += nss-ifb.o - -nss-ifb-objs := nss_ifb.o diff --git a/qaa/nss/nss-ifb/src/nss_ifb.c b/qaa/nss/nss-ifb/src/nss_ifb.c deleted file mode 100644 index 18c017fe0..000000000 --- a/qaa/nss/nss-ifb/src/nss_ifb.c +++ /dev/null @@ -1,304 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later - -/* - * This driver is adapted from the Linux /drivers/net/ifb.c file. - * - * Redirect QCA NSS physical interface ingress traffic to this driver's - * virtual interface. This will allow ingress traffic shaping using the - * QCA NSS shaper. - */ - -#include - -#define TX_Q_LIMIT 32 - -struct nss_ifb_dev_private { - struct nss_virt_if_handle *nssctx; - struct net_device *nss_src_dev; - uint32_t nss_src_if_num; - char nss_src_dev_name[32]; -}; - -char nss_dev_name_array[32] = "eth0"; -char *nss_dev_name = nss_dev_name_array; -module_param(nss_dev_name, charp, 0644); -MODULE_PARM_DESC(nss_dev_name, "NSS physical interface source device name"); - -/* - * Virtual interface egress packet callback. - * - * We send it back to the Linux network stack. - */ -static void nss_ifb_data_cb(struct net_device *netdev, struct sk_buff *skb, struct napi_struct *napi) -{ - struct nss_ifb_dev_private *dp = netdev_priv(netdev); - - skb->protocol = eth_type_trans(skb, dp->nss_src_dev); - skb->ip_summed = CHECKSUM_UNNECESSARY; - - napi_gro_receive(napi, skb); -} - -/* - * Virtual interface ingress packet callback. - * - * We just send it back to the NSS firmware to let the shaper work on it. - */ -static void nss_ifb_xmit_cb(struct net_device *netdev, struct sk_buff *skb) -{ - struct nss_ifb_dev_private *dp = netdev_priv(netdev); - int ret; - - ret = nss_virt_if_tx_buf(dp->nssctx, skb); - if (unlikely(ret)) { - pr_warn("Failed [%d] to send skb [len: %d, protocol: 0x%X] to NSS!\n", - ret, skb->len, ntohs(skb->protocol)); - } -} - -static void nss_ifb_stats64(struct net_device *dev, - struct rtnl_link_stats64 *stats) -{ - -} - -static int nss_ifb_dev_init(struct net_device *dev) -{ - struct nss_ifb_dev_private *dp = netdev_priv(dev); - - dp->nssctx = nss_virt_if_create_sync_nexthop(dev, NSS_ETH_RX_INTERFACE, NSS_ETH_RX_INTERFACE); - if (!dp->nssctx) { - dp->nssctx = NULL; - pr_warn("Could not create a NSS virtual interface for dev [%s]\n", - dev->name); - - return -ENODEV; - } - pr_info("Created a NSS virtual interface for dev [%s]\n", dev->name); - - nss_virt_if_register(dp->nssctx, nss_ifb_data_cb, dev); - pr_info("NSS IFB data callback registered\n"); - - nss_virt_if_xmit_callback_register(dp->nssctx, nss_ifb_xmit_cb); - pr_info("NSS IFB transmit callback registered\n"); - - return 0; -} - -static void nss_ifb_dev_uninit(struct net_device *dev) -{ - struct nss_ifb_dev_private *dp = netdev_priv(dev); - int ret; - - nss_virt_if_xmit_callback_unregister(dp->nssctx); - pr_info("NSS IFB transmit callback unregistered\n"); - - ret = nss_virt_if_destroy_sync(dp->nssctx); - if (ret == NSS_TX_SUCCESS) { - pr_info("NSS virtual interface destroyed for dev [%s]\n", dev->name); - } - else { - pr_warn("Unable to destroy NSS virtual interface for dev [%s], error[%d]\n", - dev->name, ret); - } - dp->nssctx = NULL; -} - -static netdev_tx_t nss_ifb_xmit(struct sk_buff *skb, struct net_device *dev) -{ - return NETDEV_TX_OK; -} - -static int nss_ifb_close(struct net_device *dev) -{ - struct nss_ifb_dev_private *dp = netdev_priv(dev); - struct nss_ctx_instance *nss_ctx; - struct net_device *src_dev; - uint32_t src_if_num; - int ret; - - nss_ctx = dp->nssctx->nss_ctx; - src_dev = dp->nss_src_dev; - src_if_num = dp->nss_src_if_num; - - ret = nss_phys_if_set_nexthop(nss_ctx, src_if_num, NSS_ETH_RX_INTERFACE); - if (ret != NSS_TX_SUCCESS) { - pr_warn("%p: Failed to reset next hop for net device [%s].\n", - nss_ctx, src_dev->name); - } - else { - pr_info("%p: Reset nexthop successful for net device [%s].\n", - nss_ctx, src_dev->name); - } - - dev_put(src_dev); - dp->nss_src_dev = NULL; - dp->nss_src_if_num = -1; - - return 0; -} - -static int nss_ifb_open(struct net_device *dev) -{ - struct nss_ifb_dev_private *dp = netdev_priv(dev); - struct net_device *src_dev; - uint32_t src_if_num; - uint32_t nh_if_num; - nss_tx_status_t nss_tx_status; - struct nss_ctx_instance *nss_ctx; - - nss_ctx = dp->nssctx->nss_ctx; - nh_if_num = dp->nssctx->if_num_n2h; - - strcpy(dp->nss_src_dev_name, nss_dev_name); - - src_dev = dev_get_by_name(&init_net, dp->nss_src_dev_name); - if (!src_dev) { - pr_warn("%p: Cannot find the net device [%s]\n", - nss_ctx, dp->nss_src_dev_name); - - return -ENODEV; - } - pr_info("%p: Found net device [%s]\n", nss_ctx, dp->nss_src_dev_name); - - src_if_num = nss_cmn_get_interface_number_by_dev(src_dev); - if (src_if_num < 0) { - pr_warn("%p: Invalid interface number:%d\n", nss_ctx, src_if_num); - dev_put(src_dev); - - return -ENODEV; - } - pr_info("%p: Net device [%s] has NSS intf_num [%d]\n", - nss_ctx, dp->nss_src_dev_name, src_if_num); - - nss_tx_status = nss_phys_if_set_nexthop(nss_ctx, src_if_num, nh_if_num); - if (nss_tx_status != NSS_TX_SUCCESS) { - pr_warn("%p: Sending message failed, cannot change nexthop for [%s]\n", - nss_ctx, dp->nss_src_dev_name); - } - else { - pr_info("Nexthop successfully set for [%s] to [%s]\n", - dp->nss_src_dev_name, dev->name); - } - - dp->nss_src_dev = src_dev; - dp->nss_src_if_num = src_if_num; - - return 0; -} - -static const struct net_device_ops nss_ifb_netdev_ops = { - .ndo_open = nss_ifb_open, - .ndo_stop = nss_ifb_close, - .ndo_get_stats64 = nss_ifb_stats64, - .ndo_start_xmit = nss_ifb_xmit, - .ndo_validate_addr = eth_validate_addr, - .ndo_init = nss_ifb_dev_init, - .ndo_uninit = nss_ifb_dev_uninit, -}; - -#define IFB_FEATURES (NETIF_F_HW_CSUM | NETIF_F_SG | NETIF_F_FRAGLIST | \ - NETIF_F_TSO_ECN | NETIF_F_TSO | NETIF_F_TSO6 | \ - NETIF_F_GSO_ENCAP_ALL | \ - NETIF_F_HIGHDMA | NETIF_F_HW_VLAN_CTAG_TX | \ - NETIF_F_HW_VLAN_STAG_TX) - -static void nss_ifb_dev_free(struct net_device *dev) -{ - -} - -static void nss_ifb_setup(struct net_device *dev) -{ - /* Initialize the device structure. */ - dev->netdev_ops = &nss_ifb_netdev_ops; - - /* Fill in device structure with ethernet-generic values. */ - ether_setup(dev); - dev->tx_queue_len = TX_Q_LIMIT; - - dev->features |= IFB_FEATURES; - dev->hw_features |= dev->features; - dev->hw_enc_features |= dev->features; - dev->vlan_features |= IFB_FEATURES & ~(NETIF_F_HW_VLAN_CTAG_TX | - NETIF_F_HW_VLAN_STAG_TX); - - dev->flags |= IFF_NOARP; - dev->flags &= ~IFF_MULTICAST; - dev->priv_flags &= ~IFF_TX_SKB_SHARING; - netif_keep_dst(dev); - eth_hw_addr_random(dev); - dev->needs_free_netdev = true; - dev->priv_destructor = nss_ifb_dev_free; - - dev->min_mtu = 0; - dev->max_mtu = 0; -} - -static int nss_ifb_validate(struct nlattr *tb[], struct nlattr *data[], - struct netlink_ext_ack *extack) -{ - if (tb[IFLA_ADDRESS]) { - if (nla_len(tb[IFLA_ADDRESS]) != ETH_ALEN) - return -EINVAL; - if (!is_valid_ether_addr(nla_data(tb[IFLA_ADDRESS]))) - return -EADDRNOTAVAIL; - } - return 0; -} - -static struct rtnl_link_ops nss_ifb_link_ops __read_mostly = { - .kind = "nss_ifb", - .priv_size = sizeof(struct nss_ifb_dev_private), - .setup = nss_ifb_setup, - .validate = nss_ifb_validate, -}; - -static int __init nss_ifb_init_module(void) -{ - struct net_device *dev; - int err; - - down_write(&pernet_ops_rwsem); - rtnl_lock(); - err = __rtnl_link_register(&nss_ifb_link_ops); - if (err < 0) - goto out; - - dev = alloc_netdev(sizeof(struct nss_ifb_dev_private), "nssifb", - NET_NAME_UNKNOWN, nss_ifb_setup); - - if (dev) { - dev->rtnl_link_ops = &nss_ifb_link_ops; - err = register_netdevice(dev); - } - else { - err = -ENOMEM; - } - - if (err) - __rtnl_link_unregister(&nss_ifb_link_ops); - -out: - rtnl_unlock(); - up_write(&pernet_ops_rwsem); - - if (!err) - pr_info("NSS IFB module loaded.\n"); - else - pr_warn("Failed to load NSS IFB module.\n"); - - return err; -} - -static void __exit nss_ifb_cleanup_module(void) -{ - rtnl_link_unregister(&nss_ifb_link_ops); - - pr_info("NSS IFB module unloaded.\n"); -} - -module_init(nss_ifb_init_module); -module_exit(nss_ifb_cleanup_module); -MODULE_LICENSE("GPL"); -MODULE_ALIAS_RTNL_LINK("nss_ifb"); diff --git a/qaa/nss/qca-nss-cfi/Makefile b/qaa/nss/qca-nss-cfi/Makefile deleted file mode 100644 index 570b45cf2..000000000 --- a/qaa/nss/qca-nss-cfi/Makefile +++ /dev/null @@ -1,99 +0,0 @@ -include $(TOPDIR)/rules.mk -include $(INCLUDE_DIR)/kernel.mk - -PKG_NAME:=qca-nss-cfi -PKG_RELEASE:=2 - -PKG_SOURCE_URL:=https://source.codeaurora.org/quic/qsdk/oss/lklm/nss-cfi -PKG_SOURCE_PROTO:=git -PKG_SOURCE_VERSION:=8035a8ddefdcc8a2f06c96b2a82618ca6ce6406d -PKG_MIRROR_HASH:=23316395d1346994d069eb41ef73a5505853687f8beab14f83545b3a05e52429 - -include $(INCLUDE_DIR)/package.mk - -ifeq ($(CONFIG_TARGET_ipq),y) -subtarget:=$(SUBTARGET) -else -subtarget:=$(CONFIG_TARGET_BOARD) -endif - -# v1.0 is for Akronite -# v2.0 is for Hawkeye/Cypress/Maple -ifneq (, $(findstring $(subtarget), "ipq807x" "ipq807x_64" "ipq60xx" "ipq60xx_64")) - CFI_OCF_DIR:=ocf/v2.0 - CFI_CRYPTOAPI_DIR:=cryptoapi/v2.0 -else - CFI_CRYPTOAPI_DIR:=cryptoapi/v1.1 - CFI_OCF_DIR:=ocf/v1.0 - CFI_IPSEC_DIR:=ipsec/v1.0 -endif - -define KernelPackage/qca-nss-cfi-cryptoapi - SECTION:=kernel - CATEGORY:=Kernel modules - SUBMENU:=Network Devices - DEPENDS:=@TARGET_ipq806x||TARGET_ipq_ipq806x||TARGET_ipq_ipq807x||TARGET_ipq_ipq807x_64||TARGET_ipq807x||TARGET_ipq807x_64||TARGET_ipq_ipq60xx||TARGET_ipq_ipq60xx_64 \ - +kmod-qca-nss-crypto +kmod-crypto-authenc @LINUX_5_4 - TITLE:=Kernel driver for NSS cfi - FILES:=$(PKG_BUILD_DIR)/$(CFI_CRYPTOAPI_DIR)/qca-nss-cfi-cryptoapi.ko - AUTOLOAD:=$(call AutoLoad,59,qca-nss-cfi-cryptoapi) -endef - -# OCF should be dropped -# define KernelPackage/qca-nss-cfi-ocf -# SECTION:=kernel -# CATEGORY:=Kernel modules -# SUBMENU:=Network Devices -# DEPENDS:=@TARGET_ipq806x||TARGET_ipq_ipq806x||TARGET_ipq_ipq807x||TARGET_ipq_ipq807x_64||TARGET_ipq807x||TARGET_ipq807x_64||TARGET_ipq_ipq60xx||TARGET_ipq_ipq60xx_64 \ -# +kmod-qca-nss-crypto +PACKAGE_kmod-crypto-ocf:kmod-crypto-ocf @!LINUX_3_18 -# TITLE:=Kernel driver for NSS cfi -# FILES:=$(PKG_BUILD_DIR)/$(CFI_OCF_DIR)/qca-nss-cfi-ocf.ko - -# ifdef CFI_IPSEC_DIR -# FILES+=$(PKG_BUILD_DIR)/$(CFI_IPSEC_DIR)/qca-nss-ipsec.ko -# AUTOLOAD:=$(call AutoLoad,61,qca-nss-cfi-ocf qca-nss-ipsec) -# else -# AUTOLOAD:=$(call AutoLoad,61,qca-nss-cfi-ocf) -# endif -# endef - -define Build/InstallDev/qca-nss-cfi - $(INSTALL_DIR) $(1)/usr/include/qca-nss-cfi - $(CP) $(PKG_BUILD_DIR)/$(CFI_CRYPTOAPI_DIR)/../exports/* $(1)/usr/include/qca-nss-cfi - $(CP) $(PKG_BUILD_DIR)/include/* $(1)/usr/include/qca-nss-cfi -endef - -define Build/InstallDev - $(call Build/InstallDev/qca-nss-cfi,$(1)) -endef - -define KernelPackage/qca-nss-cfi/Description -This package contains a NSS cfi driver for QCA chipset -endef - -EXTRA_CFLAGS+= \ - -DCONFIG_NSS_DEBUG_LEVEL=4 \ - -I$(LINUX_DIR)/crypto/ocf \ - -I$(STAGING_DIR)/usr/include/qca-nss-crypto \ - -I$(STAGING_DIR)/usr/include/crypto \ - -I$(STAGING_DIR)/usr/include/qca-nss-drv - -ifneq (, $(findstring $(subtarget), "ipq807x" "ipq807x_64" "ipq60xx" "ipq60xx_64")) -EXTRA_CFLAGS+= -I$(STAGING_DIR)/usr/include/qca-nss-clients -endif - -define Build/Compile - $(MAKE) $(PKG_JOBS) -C "$(LINUX_DIR)" \ - $(KERNEL_MAKE_FLAGS) \ - $(PKG_MAKE_FLAGS) \ - M="$(PKG_BUILD_DIR)" \ - EXTRA_CFLAGS="$(EXTRA_CFLAGS)" \ - CFI_CRYPTOAPI_DIR=$(CFI_CRYPTOAPI_DIR) \ - CFI_OCF_DIR=$(CFI_OCF_DIR) \ - CFI_IPSEC_DIR=$(CFI_IPSEC_DIR) \ - SoC=$(subtarget) \ - modules -endef - -$(eval $(call KernelPackage,qca-nss-cfi-cryptoapi)) -#$(eval $(call KernelPackage,qca-nss-cfi-ocf)) diff --git a/qaa/nss/qca-nss-cfi/patches/0001-compile-only-cryptoapi.patch b/qaa/nss/qca-nss-cfi/patches/0001-compile-only-cryptoapi.patch deleted file mode 100644 index 00968f5fe..000000000 --- a/qaa/nss/qca-nss-cfi/patches/0001-compile-only-cryptoapi.patch +++ /dev/null @@ -1,30 +0,0 @@ -From a8a573c5ce83bdddca9a60c62161638a5fd906d4 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Sat, 13 Jun 2020 12:57:14 +0200 -Subject: [PATCH 1/3] compile only cryptoapi - ---- - Makefile | 8 ++++---- - 1 file changed, 4 insertions(+), 4 deletions(-) - -diff --git a/Makefile b/Makefile -index c42adca..36a9d3f 100644 ---- a/Makefile -+++ b/Makefile -@@ -4,9 +4,9 @@ - - export BUILD_ID = \"Build Id: $(shell date +'%m/%d/%y, %H:%M:%S')\" - --obj-m += $(CFI_OCF_DIR)/ -+# obj-m += $(CFI_OCF_DIR)/ - obj-m += $(CFI_CRYPTOAPI_DIR)/ - --ifeq ($(SoC),$(filter $(SoC),ipq806x)) --obj-m += $(CFI_IPSEC_DIR)/ --endif -+# ifeq ($(SoC),$(filter $(SoC),ipq806x)) -+# obj-m += $(CFI_IPSEC_DIR)/ -+# endif --- -2.27.0.rc0 - diff --git a/qaa/nss/qca-nss-cfi/patches/0002-wip-support-5.4.patch b/qaa/nss/qca-nss-cfi/patches/0002-wip-support-5.4.patch deleted file mode 100644 index d68fc939b..000000000 --- a/qaa/nss/qca-nss-cfi/patches/0002-wip-support-5.4.patch +++ /dev/null @@ -1,78 +0,0 @@ -From 202f57bae49947a04301ac8ac9bdc00f28f09355 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Sat, 13 Jun 2020 12:58:26 +0200 -Subject: [PATCH 2/3] wip: support 5.4 - ---- - cryptoapi/v1.1/nss_cryptoapi.c | 1 - - cryptoapi/v1.1/nss_cryptoapi_ablk.c | 12 ++++++------ - cryptoapi/v1.1/nss_cryptoapi_aead.c | 2 +- - 3 files changed, 7 insertions(+), 8 deletions(-) - -diff --git a/cryptoapi/v1.1/nss_cryptoapi.c b/cryptoapi/v1.1/nss_cryptoapi.c -index d1a7313..a10590e 100644 ---- a/cryptoapi/v1.1/nss_cryptoapi.c -+++ b/cryptoapi/v1.1/nss_cryptoapi.c -@@ -231,7 +231,6 @@ static struct crypto_alg cryptoapi_ablkcipher_algs[] = { - .cra_u = { - .ablkcipher = { - .ivsize = CTR_RFC3686_IV_SIZE, -- .geniv = "seqiv", - .min_keysize = AES_MIN_KEY_SIZE + CTR_RFC3686_NONCE_SIZE, - .max_keysize = AES_MAX_KEY_SIZE + CTR_RFC3686_NONCE_SIZE, - .setkey = nss_cryptoapi_ablk_aes_setkey, -diff --git a/cryptoapi/v1.1/nss_cryptoapi_ablk.c b/cryptoapi/v1.1/nss_cryptoapi_ablk.c -index 223591c..9b6c65e 100644 ---- a/cryptoapi/v1.1/nss_cryptoapi_ablk.c -+++ b/cryptoapi/v1.1/nss_cryptoapi_ablk.c -@@ -108,7 +108,7 @@ EXPORT_SYMBOL(nss_cryptoapi_skcipher_ctx2session); - int nss_cryptoapi_ablkcipher_init(struct crypto_tfm *tfm) - { - struct nss_cryptoapi_ctx *ctx = crypto_tfm_ctx(tfm); -- struct crypto_ablkcipher *sw_tfm; -+ struct crypto_cipher *sw_tfm; - - nss_cfi_assert(ctx); - -@@ -122,20 +122,20 @@ int nss_cryptoapi_ablkcipher_init(struct crypto_tfm *tfm) - - nss_cryptoapi_set_magic(ctx); - -- if (!(crypto_tfm_alg_flags(tfm) & CRYPTO_ALG_NEED_FALLBACK)) -+ if (!(crypto_tfm_alg_type(tfm) & CRYPTO_ALG_NEED_FALLBACK)) - return 0; - - /* Alloc fallback transform for future use */ -- sw_tfm = crypto_alloc_ablkcipher(crypto_tfm_alg_name(tfm), 0, CRYPTO_ALG_ASYNC | -- CRYPTO_ALG_NEED_FALLBACK); -+ sw_tfm = crypto_alloc_cipher(crypto_tfm_alg_name(tfm), 0, CRYPTO_ALG_ASYNC | -+ CRYPTO_ALG_NEED_FALLBACK); - if (IS_ERR(sw_tfm)) { - nss_cfi_err("unable to alloc software crypto for %s\n", crypto_tfm_alg_name(tfm)); - return -EINVAL; - } - - /* set this tfm reqsize same to fallback tfm */ -- tfm->crt_ablkcipher.reqsize = crypto_ablkcipher_reqsize(sw_tfm); -- ctx->sw_tfm = crypto_ablkcipher_tfm(sw_tfm); -+ tfm->crt_ablkcipher.reqsize = sizeof(struct nss_cryptoapi_ctx); -+ ctx->sw_tfm = crypto_cipher_tfm(sw_tfm); - - return 0; - } -diff --git a/cryptoapi/v1.1/nss_cryptoapi_aead.c b/cryptoapi/v1.1/nss_cryptoapi_aead.c -index 527936b..53e4bed 100644 ---- a/cryptoapi/v1.1/nss_cryptoapi_aead.c -+++ b/cryptoapi/v1.1/nss_cryptoapi_aead.c -@@ -103,7 +103,7 @@ int nss_cryptoapi_aead_init(struct crypto_aead *aead) - - nss_cryptoapi_set_magic(ctx); - -- if (!(crypto_tfm_alg_flags(tfm) & CRYPTO_ALG_NEED_FALLBACK)) -+ if (!(crypto_tfm_alg_type(tfm) & CRYPTO_ALG_NEED_FALLBACK)) - return 0; - - /* Alloc fallback transform for future use */ --- -2.27.0.rc0 - diff --git a/qaa/nss/qca-nss-cfi/patches/0003-Convert-ablkcipher-to-skcipher.patch b/qaa/nss/qca-nss-cfi/patches/0003-Convert-ablkcipher-to-skcipher.patch deleted file mode 100644 index b4520a3d6..000000000 --- a/qaa/nss/qca-nss-cfi/patches/0003-Convert-ablkcipher-to-skcipher.patch +++ /dev/null @@ -1,707 +0,0 @@ -From e3a53a6d11b2c1770545a2820a58c117799bcb70 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Tue, 16 Jun 2020 18:12:34 +0200 -Subject: [PATCH 3/3] Convert ablkcipher to skcipher - ---- - cryptoapi/v1.1/nss_cryptoapi.c | 149 +++++++++++-------------- - cryptoapi/v1.1/nss_cryptoapi_ablk.c | 136 +++++++++++----------- - cryptoapi/v1.1/nss_cryptoapi_debugfs.c | 1 + - cryptoapi/v1.1/nss_cryptoapi_private.h | 16 +-- - 4 files changed, 145 insertions(+), 157 deletions(-) - -diff --git a/cryptoapi/v1.1/nss_cryptoapi.c b/cryptoapi/v1.1/nss_cryptoapi.c -index a10590e..3a835dc 100644 ---- a/cryptoapi/v1.1/nss_cryptoapi.c -+++ b/cryptoapi/v1.1/nss_cryptoapi.c -@@ -66,7 +66,7 @@ struct aead_alg cryptoapi_aead_algs[] = { - .cra_name = "echainiv(authenc(hmac(sha1),cbc(aes)))", - .cra_driver_name = "nss-hmac-sha1-cbc-aes", - .cra_priority = 10000, -- .cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NOSUPP_SG | CRYPTO_ALG_NEED_FALLBACK, -+ .cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NOSUPP_SG | CRYPTO_ALG_NEED_FALLBACK | CRYPTO_ALG_KERN_DRIVER_ONLY, - .cra_blocksize = AES_BLOCK_SIZE, - .cra_ctxsize = sizeof(struct nss_cryptoapi_ctx), - .cra_alignmask = 0, -@@ -87,7 +87,7 @@ struct aead_alg cryptoapi_aead_algs[] = { - .cra_name = "seqiv(authenc(hmac(sha1),rfc3686(ctr(aes))))", - .cra_driver_name = "nss-hmac-sha1-rfc3686-ctr-aes", - .cra_priority = 10000, -- .cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NOSUPP_SG | CRYPTO_ALG_NEED_FALLBACK, -+ .cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NOSUPP_SG | CRYPTO_ALG_NEED_FALLBACK | CRYPTO_ALG_KERN_DRIVER_ONLY, - .cra_blocksize = AES_BLOCK_SIZE, - .cra_ctxsize = sizeof(struct nss_cryptoapi_ctx), - .cra_alignmask = 0, -@@ -108,7 +108,7 @@ struct aead_alg cryptoapi_aead_algs[] = { - .cra_name = "echainiv(authenc(hmac(sha1),cbc(des3_ede)))", - .cra_driver_name = "nss-hmac-sha1-cbc-3des", - .cra_priority = 300, -- .cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NOSUPP_SG, -+ .cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NOSUPP_SG | CRYPTO_ALG_KERN_DRIVER_ONLY, - .cra_blocksize = DES3_EDE_BLOCK_SIZE, - .cra_ctxsize = sizeof(struct nss_cryptoapi_ctx), - .cra_alignmask = 0, -@@ -129,7 +129,7 @@ struct aead_alg cryptoapi_aead_algs[] = { - .cra_name = "echainiv(authenc(hmac(sha256),cbc(aes)))", - .cra_driver_name = "nss-hmac-sha256-cbc-aes", - .cra_priority = 10000, -- .cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NOSUPP_SG | CRYPTO_ALG_NEED_FALLBACK, -+ .cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NOSUPP_SG | CRYPTO_ALG_NEED_FALLBACK | CRYPTO_ALG_KERN_DRIVER_ONLY, - .cra_blocksize = AES_BLOCK_SIZE, - .cra_ctxsize = sizeof(struct nss_cryptoapi_ctx), - .cra_alignmask = 0, -@@ -150,7 +150,7 @@ struct aead_alg cryptoapi_aead_algs[] = { - .cra_name = "seqiv(authenc(hmac(sha256),rfc3686(ctr(aes))))", - .cra_driver_name = "nss-hmac-sha256-rfc3686-ctr-aes", - .cra_priority = 10000, -- .cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NOSUPP_SG | CRYPTO_ALG_NEED_FALLBACK, -+ .cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NOSUPP_SG | CRYPTO_ALG_NEED_FALLBACK | CRYPTO_ALG_KERN_DRIVER_ONLY, - .cra_blocksize = AES_BLOCK_SIZE, - .cra_ctxsize = sizeof(struct nss_cryptoapi_ctx), - .cra_alignmask = 0, -@@ -171,7 +171,7 @@ struct aead_alg cryptoapi_aead_algs[] = { - .cra_name = "echainiv(authenc(hmac(sha256),cbc(des3_ede)))", - .cra_driver_name = "nss-hmac-sha256-cbc-3des", - .cra_priority = 300, -- .cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NOSUPP_SG, -+ .cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NOSUPP_SG | CRYPTO_ALG_KERN_DRIVER_ONLY, - .cra_blocksize = DES3_EDE_BLOCK_SIZE, - .cra_ctxsize = sizeof(struct nss_cryptoapi_ctx), - .cra_alignmask = 0, -@@ -192,75 +192,66 @@ struct aead_alg cryptoapi_aead_algs[] = { - /* - * ABLK cipher algorithms - */ --static struct crypto_alg cryptoapi_ablkcipher_algs[] = { -+static struct skcipher_alg cryptoapi_skcipher_algs[] = { - { -- .cra_name = "cbc(aes)", -- .cra_driver_name = "nss-cbc-aes", -- .cra_priority = 10000, -- .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_NOSUPP_SG | CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK, -- .cra_blocksize = AES_BLOCK_SIZE, -- .cra_ctxsize = sizeof(struct nss_cryptoapi_ctx), -- .cra_alignmask = 0, -- .cra_type = &crypto_ablkcipher_type, -- .cra_module = THIS_MODULE, -- .cra_init = nss_cryptoapi_ablkcipher_init, -- .cra_exit = nss_cryptoapi_ablkcipher_exit, -- .cra_u = { -- .ablkcipher = { -- .ivsize = AES_BLOCK_SIZE, -- .min_keysize = AES_MIN_KEY_SIZE, -- .max_keysize = AES_MAX_KEY_SIZE, -- .setkey = nss_cryptoapi_ablk_aes_setkey, -- .encrypt = nss_cryptoapi_ablk_aes_encrypt, -- .decrypt = nss_cryptoapi_ablk_aes_decrypt, -- }, -+ .base = { -+ .cra_name = "cbc(aes)", -+ .cra_driver_name = "nss-cbc-aes", -+ .cra_priority = 10000, -+ .cra_flags = CRYPTO_ALG_TYPE_SKCIPHER | CRYPTO_ALG_NOSUPP_SG | CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK | CRYPTO_ALG_KERN_DRIVER_ONLY, -+ .cra_blocksize = AES_BLOCK_SIZE, -+ .cra_ctxsize = sizeof(struct nss_cryptoapi_ctx), -+ .cra_alignmask = 0, -+ .cra_module = THIS_MODULE, - }, -+ .init = nss_cryptoapi_skcipher_init, -+ .exit = nss_cryptoapi_skcipher_exit, -+ .ivsize = AES_BLOCK_SIZE, -+ .min_keysize = AES_MIN_KEY_SIZE, -+ .max_keysize = AES_MAX_KEY_SIZE, -+ .setkey = nss_cryptoapi_ablk_aes_setkey, -+ .encrypt = nss_cryptoapi_ablk_aes_encrypt, -+ .decrypt = nss_cryptoapi_ablk_aes_decrypt, - }, - { -- .cra_name = "rfc3686(ctr(aes))", -- .cra_driver_name = "nss-rfc3686-ctr-aes", -- .cra_priority = 30000, -- .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_NOSUPP_SG | CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK, -- .cra_blocksize = AES_BLOCK_SIZE, -- .cra_ctxsize = sizeof(struct nss_cryptoapi_ctx), -- .cra_alignmask = 0, -- .cra_type = &crypto_ablkcipher_type, -- .cra_module = THIS_MODULE, -- .cra_init = nss_cryptoapi_ablkcipher_init, -- .cra_exit = nss_cryptoapi_ablkcipher_exit, -- .cra_u = { -- .ablkcipher = { -- .ivsize = CTR_RFC3686_IV_SIZE, -- .min_keysize = AES_MIN_KEY_SIZE + CTR_RFC3686_NONCE_SIZE, -- .max_keysize = AES_MAX_KEY_SIZE + CTR_RFC3686_NONCE_SIZE, -- .setkey = nss_cryptoapi_ablk_aes_setkey, -- .encrypt = nss_cryptoapi_ablk_aes_encrypt, -- .decrypt = nss_cryptoapi_ablk_aes_decrypt, -- }, -+ .base = { -+ .cra_name = "rfc3686(ctr(aes))", -+ .cra_driver_name = "nss-rfc3686-ctr-aes", -+ .cra_priority = 30000, -+ .cra_flags = CRYPTO_ALG_TYPE_SKCIPHER | CRYPTO_ALG_NOSUPP_SG | CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK | CRYPTO_ALG_KERN_DRIVER_ONLY, -+ .cra_blocksize = AES_BLOCK_SIZE, -+ .cra_ctxsize = sizeof(struct nss_cryptoapi_ctx), -+ .cra_alignmask = 0, -+ .cra_module = THIS_MODULE, - }, -+ .init = nss_cryptoapi_skcipher_init, -+ .exit = nss_cryptoapi_skcipher_exit, -+ .ivsize = CTR_RFC3686_IV_SIZE, -+ .min_keysize = AES_MIN_KEY_SIZE + CTR_RFC3686_NONCE_SIZE, -+ .max_keysize = AES_MAX_KEY_SIZE + CTR_RFC3686_NONCE_SIZE, -+ .setkey = nss_cryptoapi_ablk_aes_setkey, -+ .encrypt = nss_cryptoapi_ablk_aes_encrypt, -+ .decrypt = nss_cryptoapi_ablk_aes_decrypt, - }, - { -- .cra_name = "cbc(des3_ede)", -- .cra_driver_name = "nss-cbc-3des", -- .cra_priority = 1000, -- .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_NOSUPP_SG | CRYPTO_ALG_ASYNC, -- .cra_blocksize = DES3_EDE_BLOCK_SIZE, -- .cra_ctxsize = sizeof(struct nss_cryptoapi_ctx), -- .cra_alignmask = 0, -- .cra_type = &crypto_ablkcipher_type, -- .cra_module = THIS_MODULE, -- .cra_init = nss_cryptoapi_ablkcipher_init, -- .cra_exit = nss_cryptoapi_ablkcipher_exit, -- .cra_u = { -- .ablkcipher = { -- .ivsize = DES3_EDE_BLOCK_SIZE, -- .min_keysize = DES3_EDE_KEY_SIZE, -- .max_keysize = DES3_EDE_KEY_SIZE, -- .setkey = nss_cryptoapi_3des_cbc_setkey, -- .encrypt = nss_cryptoapi_3des_cbc_encrypt, -- .decrypt = nss_cryptoapi_3des_cbc_decrypt, -- }, -+ .base = { -+ .cra_name = "cbc(des3_ede)", -+ .cra_driver_name = "nss-cbc-3des", -+ .cra_priority = 1000, -+ .cra_flags = CRYPTO_ALG_TYPE_SKCIPHER | CRYPTO_ALG_NOSUPP_SG | CRYPTO_ALG_ASYNC | CRYPTO_ALG_KERN_DRIVER_ONLY, -+ .cra_blocksize = DES3_EDE_BLOCK_SIZE, -+ .cra_ctxsize = sizeof(struct nss_cryptoapi_ctx), -+ .cra_alignmask = 0, -+ .cra_module = THIS_MODULE, - }, -+ .init = nss_cryptoapi_skcipher_init, -+ .exit = nss_cryptoapi_skcipher_exit, -+ .ivsize = DES3_EDE_BLOCK_SIZE, -+ .min_keysize = DES3_EDE_KEY_SIZE, -+ .max_keysize = DES3_EDE_KEY_SIZE, -+ .setkey = nss_cryptoapi_3des_cbc_setkey, -+ .encrypt = nss_cryptoapi_3des_cbc_encrypt, -+ .decrypt = nss_cryptoapi_3des_cbc_decrypt, - }, - }; - -@@ -277,14 +268,14 @@ static nss_crypto_user_ctx_t nss_cryptoapi_register(nss_crypto_handle_t crypto) - - sc->crypto = crypto; - -- for (i = 0; i < ARRAY_SIZE(cryptoapi_ablkcipher_algs); i++) { -- rc = crypto_register_alg(&cryptoapi_ablkcipher_algs[i]); -+ for (i = 0; i < ARRAY_SIZE(cryptoapi_skcipher_algs); i++) { -+ rc = crypto_register_skcipher(&cryptoapi_skcipher_algs[i]); - if (rc) { -- nss_cfi_trace("Ablk registration failed, algo: %s\n", cryptoapi_ablkcipher_algs[i].cra_name); -- cryptoapi_ablkcipher_algs[i].cra_flags = 0; -+ nss_cfi_trace("Ablk registration failed, algo: %s\n", cryptoapi_skcipher_algs[i].base.cra_name); -+ cryptoapi_skcipher_algs[i].base.cra_flags = 0; - continue; - } -- nss_cfi_info("Ablk registration succeeded, algo: %s\n", cryptoapi_ablkcipher_algs[i].cra_name); -+ nss_cfi_info("Ablk registration succeeded, algo: %s\n", cryptoapi_skcipher_algs[i].base.cra_name); - } - - for (i = 0; i < ARRAY_SIZE(cryptoapi_aead_algs); i++) { -@@ -317,7 +308,7 @@ static nss_crypto_user_ctx_t nss_cryptoapi_register(nss_crypto_handle_t crypto) - static void nss_cryptoapi_unregister(nss_crypto_user_ctx_t cfi) - { - struct nss_cryptoapi *sc = &gbl_ctx; -- int i, ret = 0; -+ int i; - - nss_cfi_info("unregister nss_cryptoapi\n"); - -@@ -326,16 +317,12 @@ static void nss_cryptoapi_unregister(nss_crypto_user_ctx_t cfi) - */ - atomic_set(&gbl_ctx.registered, 0); - -- for (i = 0; i < ARRAY_SIZE(cryptoapi_ablkcipher_algs); i++) { -- if (!cryptoapi_ablkcipher_algs[i].cra_flags) { -- continue; -- } -- ret = crypto_unregister_alg(&cryptoapi_ablkcipher_algs[i]); -- if (ret) { -- nss_cfi_err("Ablk unregister failed, algo: %s\n", cryptoapi_ablkcipher_algs[i].cra_name); -+ for (i = 0; i < ARRAY_SIZE(cryptoapi_skcipher_algs); i++) { -+ if (!cryptoapi_skcipher_algs[i].base.cra_flags) { - continue; - } -- nss_cfi_info("Ablk unregister succeeded, algo: %s\n", cryptoapi_ablkcipher_algs[i].cra_name); -+ crypto_unregister_skcipher(&cryptoapi_skcipher_algs[i]); -+ nss_cfi_info("Ablk unregister succeeded, algo: %s\n", cryptoapi_skcipher_algs[i].base.cra_name); - } - - for (i = 0; i < ARRAY_SIZE(cryptoapi_aead_algs); i++) { -diff --git a/cryptoapi/v1.1/nss_cryptoapi_ablk.c b/cryptoapi/v1.1/nss_cryptoapi_ablk.c -index 9b6c65e..913e9cc 100644 ---- a/cryptoapi/v1.1/nss_cryptoapi_ablk.c -+++ b/cryptoapi/v1.1/nss_cryptoapi_ablk.c -@@ -102,12 +102,12 @@ int nss_cryptoapi_skcipher_ctx2session(struct crypto_skcipher *sk, uint32_t *sid - EXPORT_SYMBOL(nss_cryptoapi_skcipher_ctx2session); - - /* -- * nss_cryptoapi_ablkcipher_init() -- * Cryptoapi ablkcipher init function. -+ * nss_cryptoapi_skcipher_init() -+ * Cryptoapi skcipher init function. - */ --int nss_cryptoapi_ablkcipher_init(struct crypto_tfm *tfm) -+int nss_cryptoapi_skcipher_init(struct crypto_skcipher *tfm) - { -- struct nss_cryptoapi_ctx *ctx = crypto_tfm_ctx(tfm); -+ struct nss_cryptoapi_ctx *ctx = crypto_skcipher_ctx(tfm); - struct crypto_cipher *sw_tfm; - - nss_cfi_assert(ctx); -@@ -122,31 +122,31 @@ int nss_cryptoapi_ablkcipher_init(struct crypto_tfm *tfm) - - nss_cryptoapi_set_magic(ctx); - -- if (!(crypto_tfm_alg_type(tfm) & CRYPTO_ALG_NEED_FALLBACK)) -+ if (!(crypto_tfm_alg_type(&tfm->base) & CRYPTO_ALG_NEED_FALLBACK)) - return 0; - - /* Alloc fallback transform for future use */ -- sw_tfm = crypto_alloc_cipher(crypto_tfm_alg_name(tfm), 0, CRYPTO_ALG_ASYNC | -+ sw_tfm = crypto_alloc_cipher(crypto_tfm_alg_name(&tfm->base), 0, CRYPTO_ALG_ASYNC | - CRYPTO_ALG_NEED_FALLBACK); - if (IS_ERR(sw_tfm)) { -- nss_cfi_err("unable to alloc software crypto for %s\n", crypto_tfm_alg_name(tfm)); -+ nss_cfi_err("unable to alloc software crypto for %s\n", crypto_tfm_alg_name(&tfm->base)); - return -EINVAL; - } - - /* set this tfm reqsize same to fallback tfm */ -- tfm->crt_ablkcipher.reqsize = sizeof(struct nss_cryptoapi_ctx); -+ crypto_skcipher_set_reqsize(tfm, sizeof(struct nss_cryptoapi_ctx)); - ctx->sw_tfm = crypto_cipher_tfm(sw_tfm); - - return 0; - } - - /* -- * nss_cryptoapi_ablkcipher_exit() -- * Cryptoapi ablkcipher exit function. -+ * nss_cryptoapi_skcipher_exit() -+ * Cryptoapi skcipher exit function. - */ --void nss_cryptoapi_ablkcipher_exit(struct crypto_tfm *tfm) -+void nss_cryptoapi_skcipher_exit(struct crypto_skcipher *tfm) - { -- struct nss_cryptoapi_ctx *ctx = crypto_tfm_ctx(tfm); -+ struct nss_cryptoapi_ctx *ctx = crypto_skcipher_ctx(tfm); - struct nss_cryptoapi *sc = &gbl_ctx; - nss_crypto_status_t status; - -@@ -158,7 +158,7 @@ void nss_cryptoapi_ablkcipher_exit(struct crypto_tfm *tfm) - } - - if (ctx->sw_tfm) { -- crypto_free_ablkcipher(__crypto_ablkcipher_cast(ctx->sw_tfm)); -+ crypto_free_skcipher(__crypto_skcipher_cast(ctx->sw_tfm)); - ctx->sw_tfm = NULL; - } - -@@ -183,9 +183,9 @@ void nss_cryptoapi_ablkcipher_exit(struct crypto_tfm *tfm) - * nss_cryptoapi_ablk_aes_setkey() - * Cryptoapi setkey routine for aes. - */ --int nss_cryptoapi_ablk_aes_setkey(struct crypto_ablkcipher *cipher, const u8 *key, unsigned int keylen) -+int nss_cryptoapi_ablk_aes_setkey(struct crypto_skcipher *cipher, const u8 *key, unsigned int keylen) - { -- struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher); -+ struct crypto_tfm *tfm = crypto_skcipher_tfm(cipher); - struct nss_cryptoapi_ctx *ctx = crypto_tfm_ctx(tfm); - struct nss_cryptoapi *sc = &gbl_ctx; - struct nss_crypto_key cip; -@@ -255,10 +255,10 @@ int nss_cryptoapi_ablk_aes_setkey(struct crypto_ablkcipher *cipher, const u8 *ke - - /* set flag to fallback tfm */ - crypto_tfm_clear_flags(ctx->sw_tfm, CRYPTO_TFM_REQ_MASK); -- crypto_tfm_set_flags(ctx->sw_tfm, crypto_ablkcipher_get_flags(cipher) & CRYPTO_TFM_REQ_MASK); -+ crypto_tfm_set_flags(ctx->sw_tfm, crypto_skcipher_get_flags(cipher) & CRYPTO_TFM_REQ_MASK); - - /* Set key to the fallback tfm */ -- ret = crypto_ablkcipher_setkey(__crypto_ablkcipher_cast(ctx->sw_tfm), key, keylen); -+ ret = crypto_skcipher_setkey(__crypto_skcipher_cast(ctx->sw_tfm), key, keylen); - if (ret) { - nss_cfi_err("Failed to set key to the sw crypto"); - -@@ -266,7 +266,7 @@ int nss_cryptoapi_ablk_aes_setkey(struct crypto_ablkcipher *cipher, const u8 *ke - * Set back the fallback tfm flag to the original flag one after - * doing setkey - */ -- crypto_ablkcipher_set_flags(cipher, crypto_tfm_get_flags(ctx->sw_tfm)); -+ crypto_skcipher_set_flags(cipher, crypto_tfm_get_flags(ctx->sw_tfm)); - } - return ret; - default: -@@ -289,23 +289,23 @@ int nss_cryptoapi_ablk_aes_setkey(struct crypto_ablkcipher *cipher, const u8 *ke - return 0; - - fail: -- crypto_ablkcipher_set_flags(cipher, flag); -+ crypto_skcipher_set_flags(cipher, flag); - return -EINVAL; - } - - /* -- * nss_cryptoapi_ablkcipher_done() -+ * nss_cryptoapi_skcipher_done() - * Cipher operation completion callback function - */ --void nss_cryptoapi_ablkcipher_done(struct nss_crypto_buf *buf) -+void nss_cryptoapi_skcipher_done(struct nss_crypto_buf *buf) - { - struct nss_cryptoapi_ctx *ctx; -- struct ablkcipher_request *req; -+ struct skcipher_request *req; - int err = 0; - - nss_cfi_assert(buf); - -- req = (struct ablkcipher_request *)nss_crypto_get_cb_ctx(buf); -+ req = (struct skcipher_request *)nss_crypto_get_cb_ctx(buf); - - /* - * check cryptoapi context magic number. -@@ -319,7 +319,7 @@ void nss_cryptoapi_ablkcipher_done(struct nss_crypto_buf *buf) - nss_crypto_buf_free(gbl_ctx.crypto, buf); - - nss_cfi_dbg("after transformation\n"); -- nss_cfi_dbg_data(sg_virt(req->dst), req->nbytes, ' '); -+ nss_cfi_dbg_data(sg_virt(req->dst), req->cryptlen, ' '); - - /* - * Passing always pass in case of encrypt. -@@ -337,7 +337,7 @@ void nss_cryptoapi_ablkcipher_done(struct nss_crypto_buf *buf) - * Cryptoapi: obtain sg to virtual address mapping. - * Check for multiple sg in src and dst - */ --int nss_cryptoapi_ablk_checkaddr(struct ablkcipher_request *req) -+int nss_cryptoapi_ablk_checkaddr(struct skcipher_request *req) - { - /* - * Currently only single sg is supported -@@ -356,7 +356,7 @@ int nss_cryptoapi_ablk_checkaddr(struct ablkcipher_request *req) - /* - * If the size of data is more than 65K reject transformation - */ -- if (req->nbytes > NSS_CRYPTOAPI_MAX_DATA_LEN) { -+ if (req->cryptlen > NSS_CRYPTOAPI_MAX_DATA_LEN) { - nss_cfi_err("Buffer length exceeded limit\n"); - return -EINVAL; - } -@@ -368,10 +368,10 @@ int nss_cryptoapi_ablk_checkaddr(struct ablkcipher_request *req) - * nss_cryptoapi_ablk_transform() - * Crytoapi common routine for encryption and decryption operations. - */ --struct nss_crypto_buf *nss_cryptoapi_ablk_transform(struct ablkcipher_request *req, struct nss_cryptoapi_ablk_info *info) -+struct nss_crypto_buf *nss_cryptoapi_ablk_transform(struct skcipher_request *req, struct nss_cryptoapi_ablk_info *info) - { -- struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(req); -- struct nss_cryptoapi_ctx *ctx = crypto_ablkcipher_ctx(cipher); -+ struct crypto_skcipher *cipher = crypto_skcipher_reqtfm(req); -+ struct nss_cryptoapi_ctx *ctx = crypto_skcipher_ctx(cipher); - struct nss_crypto_buf *buf; - struct nss_cryptoapi *sc = &gbl_ctx; - nss_crypto_status_t status; -@@ -382,7 +382,7 @@ struct nss_crypto_buf *nss_cryptoapi_ablk_transform(struct ablkcipher_request *r - nss_cfi_assert(ctx); - - nss_cfi_dbg("src_vaddr: 0x%p, dst_vaddr: 0x%p, iv: 0x%p\n", -- sg_virt(req->src), sg_virt(req->dst), req->info); -+ sg_virt(req->src), sg_virt(req->dst), req->iv); - - info->params->cipher_skip = 0; - info->params->auth_skip = 0; -@@ -419,19 +419,19 @@ struct nss_crypto_buf *nss_cryptoapi_ablk_transform(struct ablkcipher_request *r - /* - * Get IV location and memcpy the IV - */ -- iv_size = crypto_ablkcipher_ivsize(cipher); -+ iv_size = crypto_skcipher_ivsize(cipher); - iv_addr = nss_crypto_get_ivaddr(buf); - - switch (ctx->cip_alg) { - case NSS_CRYPTO_CIPHER_AES_CBC: - case NSS_CRYPTO_CIPHER_DES: -- memcpy(iv_addr, req->info, iv_size); -+ memcpy(iv_addr, req->iv, iv_size); - break; - - case NSS_CRYPTO_CIPHER_AES_CTR: - ((uint32_t *)iv_addr)[0] = ctx->ctx_iv[0]; -- ((uint32_t *)iv_addr)[1] = ((uint32_t *)req->info)[0]; -- ((uint32_t *)iv_addr)[2] = ((uint32_t *)req->info)[1]; -+ ((uint32_t *)iv_addr)[1] = ((uint32_t *)req->iv)[0]; -+ ((uint32_t *)iv_addr)[2] = ((uint32_t *)req->iv)[1]; - ((uint32_t *)iv_addr)[3] = ctx->ctx_iv[3]; - break; - -@@ -446,7 +446,7 @@ struct nss_crypto_buf *nss_cryptoapi_ablk_transform(struct ablkcipher_request *r - /* - * Fill Cipher and Auth len - */ -- cipher_len = req->nbytes; -+ cipher_len = req->cryptlen; - auth_len = 0; - - nss_crypto_set_data(buf, sg_virt(req->src), sg_virt(req->dst), cipher_len); -@@ -463,12 +463,12 @@ struct nss_crypto_buf *nss_cryptoapi_ablk_transform(struct ablkcipher_request *r - } - - /* -- * nss_cryptoapi_ablkcipher_fallback() -- * Cryptoapi fallback for ablkcipher algorithm. -+ * nss_cryptoapi_skcipher_fallback() -+ * Cryptoapi fallback for skcipher algorithm. - */ --int nss_cryptoapi_ablkcipher_fallback(struct nss_cryptoapi_ctx *ctx, struct ablkcipher_request *req, int type) -+int nss_cryptoapi_skcipher_fallback(struct nss_cryptoapi_ctx *ctx, struct skcipher_request *req, int type) - { -- struct crypto_ablkcipher *orig_tfm = crypto_ablkcipher_reqtfm(req); -+ struct crypto_skcipher *orig_tfm = crypto_skcipher_reqtfm(req); - int err; - - if (!ctx->sw_tfm) { -@@ -476,16 +476,16 @@ int nss_cryptoapi_ablkcipher_fallback(struct nss_cryptoapi_ctx *ctx, struct ablk - } - - /* Set new fallback tfm to the request */ -- ablkcipher_request_set_tfm(req, __crypto_ablkcipher_cast(ctx->sw_tfm)); -+ skcipher_request_set_tfm(req, __crypto_skcipher_cast(ctx->sw_tfm)); - - ctx->queued++; - - switch (type) { - case NSS_CRYPTOAPI_ENCRYPT: -- err = crypto_ablkcipher_encrypt(req); -+ err = crypto_skcipher_encrypt(req); - break; - case NSS_CRYPTOAPI_DECRYPT: -- err = crypto_ablkcipher_decrypt(req); -+ err = crypto_skcipher_decrypt(req); - break; - default: - err = -EINVAL; -@@ -495,7 +495,7 @@ int nss_cryptoapi_ablkcipher_fallback(struct nss_cryptoapi_ctx *ctx, struct ablk - ctx->completed++; - - /* Set original tfm to the request */ -- ablkcipher_request_set_tfm(req, orig_tfm); -+ skcipher_request_set_tfm(req, orig_tfm); - - return err; - } -@@ -504,13 +504,13 @@ int nss_cryptoapi_ablkcipher_fallback(struct nss_cryptoapi_ctx *ctx, struct ablk - * nss_cryptoapi_ablk_aes_encrypt() - * Crytoapi encrypt for aes(aes-cbc/rfc3686-aes-ctr) algorithms. - */ --int nss_cryptoapi_ablk_aes_encrypt(struct ablkcipher_request *req) -+int nss_cryptoapi_ablk_aes_encrypt(struct skcipher_request *req) - { - struct nss_crypto_params params = { .req_type = NSS_CRYPTO_REQ_TYPE_ENCRYPT }; -- struct nss_cryptoapi_ablk_info info = {.cb_fn = nss_cryptoapi_ablkcipher_done, -+ struct nss_cryptoapi_ablk_info info = {.cb_fn = nss_cryptoapi_skcipher_done, - .params = ¶ms}; -- struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(req); -- struct nss_cryptoapi_ctx *ctx = crypto_ablkcipher_ctx(cipher); -+ struct crypto_skcipher *cipher = crypto_skcipher_reqtfm(req); -+ struct nss_cryptoapi_ctx *ctx = crypto_skcipher_ctx(cipher); - struct nss_cryptoapi *sc = &gbl_ctx; - struct nss_crypto_buf *buf; - -@@ -520,7 +520,7 @@ int nss_cryptoapi_ablk_aes_encrypt(struct ablkcipher_request *req) - nss_cryptoapi_verify_magic(ctx); - - if (ctx->fallback_req) -- return nss_cryptoapi_ablkcipher_fallback(ctx, req, NSS_CRYPTOAPI_ENCRYPT); -+ return nss_cryptoapi_skcipher_fallback(ctx, req, NSS_CRYPTOAPI_ENCRYPT); - - /* - * Check if previous call to setkey couldn't allocate session with core crypto. -@@ -539,9 +539,9 @@ int nss_cryptoapi_ablk_aes_encrypt(struct ablkcipher_request *req) - * According to RFC3686, AES-CTR algo need not be padded if the - * plaintext or ciphertext is unaligned to block size boundary. - */ -- if (nss_cryptoapi_check_unalign(req->nbytes, AES_BLOCK_SIZE) && (ctx->cip_alg != NSS_CRYPTO_CIPHER_AES_CTR)) { -+ if (nss_cryptoapi_check_unalign(req->cryptlen, AES_BLOCK_SIZE) && (ctx->cip_alg != NSS_CRYPTO_CIPHER_AES_CTR)) { - nss_cfi_err("Invalid cipher len - Not aligned to algo blocksize\n"); -- crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_BLOCK_LEN); -+ crypto_skcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_BLOCK_LEN); - return -EINVAL; - } - -@@ -571,13 +571,13 @@ int nss_cryptoapi_ablk_aes_encrypt(struct ablkcipher_request *req) - * nss_cryptoapi_ablk_aes_decrypt() - * Crytoapi decrypt for aes(aes-cbc/rfc3686-aes-ctr) algorithms. - */ --int nss_cryptoapi_ablk_aes_decrypt(struct ablkcipher_request *req) -+int nss_cryptoapi_ablk_aes_decrypt(struct skcipher_request *req) - { - struct nss_crypto_params params = { .req_type = NSS_CRYPTO_REQ_TYPE_DECRYPT }; -- struct nss_cryptoapi_ablk_info info = {.cb_fn = nss_cryptoapi_ablkcipher_done, -+ struct nss_cryptoapi_ablk_info info = {.cb_fn = nss_cryptoapi_skcipher_done, - .params = ¶ms}; -- struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(req); -- struct nss_cryptoapi_ctx *ctx = crypto_ablkcipher_ctx(cipher); -+ struct crypto_skcipher *cipher = crypto_skcipher_reqtfm(req); -+ struct nss_cryptoapi_ctx *ctx = crypto_skcipher_ctx(cipher); - struct nss_cryptoapi *sc = &gbl_ctx; - struct nss_crypto_buf *buf; - -@@ -587,7 +587,7 @@ int nss_cryptoapi_ablk_aes_decrypt(struct ablkcipher_request *req) - nss_cryptoapi_verify_magic(ctx); - - if (ctx->fallback_req) -- return nss_cryptoapi_ablkcipher_fallback(ctx, req, NSS_CRYPTOAPI_DECRYPT); -+ return nss_cryptoapi_skcipher_fallback(ctx, req, NSS_CRYPTOAPI_DECRYPT); - - /* - * Check if previous call to setkey couldn't allocate session with core crypto. -@@ -606,9 +606,9 @@ int nss_cryptoapi_ablk_aes_decrypt(struct ablkcipher_request *req) - * According to RFC3686, AES-CTR algo need not be padded if the - * plaintext or ciphertext is unaligned to block size boundary. - */ -- if (nss_cryptoapi_check_unalign(req->nbytes, AES_BLOCK_SIZE) && (ctx->cip_alg != NSS_CRYPTO_CIPHER_AES_CTR)) { -+ if (nss_cryptoapi_check_unalign(req->cryptlen, AES_BLOCK_SIZE) && (ctx->cip_alg != NSS_CRYPTO_CIPHER_AES_CTR)) { - nss_cfi_err("Invalid cipher len - Not aligned to algo blocksize\n"); -- crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_BLOCK_LEN); -+ crypto_skcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_BLOCK_LEN); - return -EINVAL; - } - -@@ -638,9 +638,9 @@ int nss_cryptoapi_ablk_aes_decrypt(struct ablkcipher_request *req) - * nss_cryptoapi_3des_cbc_setkey() - * Cryptoapi DES3 CBC setkey function. - */ --int nss_cryptoapi_3des_cbc_setkey(struct crypto_ablkcipher *cipher, const u8 *key, unsigned int keylen) -+int nss_cryptoapi_3des_cbc_setkey(struct crypto_skcipher *cipher, const u8 *key, unsigned int keylen) - { -- struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher); -+ struct crypto_tfm *tfm = crypto_skcipher_tfm(cipher); - struct nss_cryptoapi_ctx *ctx = crypto_tfm_ctx(tfm); - struct nss_cryptoapi *sc = &gbl_ctx; - struct nss_crypto_key cip = { .algo = NSS_CRYPTO_CIPHER_DES }; -@@ -693,7 +693,7 @@ int nss_cryptoapi_3des_cbc_setkey(struct crypto_ablkcipher *cipher, const u8 *ke - return 0; - - fail: -- crypto_ablkcipher_set_flags(cipher, flag); -+ crypto_skcipher_set_flags(cipher, flag); - return -EINVAL; - } - -@@ -701,7 +701,7 @@ fail: - * nss_cryptoapi_3des_cbc_encrypt() - * Cryptoapi DES3 CBC encrypt function. - */ --int nss_cryptoapi_3des_cbc_encrypt(struct ablkcipher_request *req) -+int nss_cryptoapi_3des_cbc_encrypt(struct skcipher_request *req) - { - struct nss_cryptoapi *sc = &gbl_ctx; - struct nss_cryptoapi_ctx *ctx = crypto_tfm_ctx(req->base.tfm); -@@ -727,14 +727,14 @@ int nss_cryptoapi_3des_cbc_encrypt(struct ablkcipher_request *req) - return -EINVAL; - } - -- if (nss_cryptoapi_check_unalign(req->nbytes, DES3_EDE_BLOCK_SIZE)) { -+ if (nss_cryptoapi_check_unalign(req->cryptlen, DES3_EDE_BLOCK_SIZE)) { - nss_cfi_err("Invalid cipher len - Not aligned to algo blocksize\n"); -- crypto_ablkcipher_set_flags(crypto_ablkcipher_reqtfm(req), CRYPTO_TFM_RES_BAD_BLOCK_LEN); -+ crypto_skcipher_set_flags(crypto_skcipher_reqtfm(req), CRYPTO_TFM_RES_BAD_BLOCK_LEN); - return -EINVAL; - } - - info.params = ¶ms; -- info.cb_fn = nss_cryptoapi_ablkcipher_done; -+ info.cb_fn = nss_cryptoapi_skcipher_done; - - buf = nss_cryptoapi_ablk_transform(req, &info); - if (!buf) { -@@ -762,7 +762,7 @@ int nss_cryptoapi_3des_cbc_encrypt(struct ablkcipher_request *req) - * nss_cryptoapi_3des_cbc_decrypt() - * Cryptoapi DES3 CBC decrypt function. - */ --int nss_cryptoapi_3des_cbc_decrypt(struct ablkcipher_request *req) -+int nss_cryptoapi_3des_cbc_decrypt(struct skcipher_request *req) - { - struct nss_cryptoapi *sc = &gbl_ctx; - struct nss_cryptoapi_ctx *ctx = crypto_tfm_ctx(req->base.tfm); -@@ -788,14 +788,14 @@ int nss_cryptoapi_3des_cbc_decrypt(struct ablkcipher_request *req) - return -EINVAL; - } - -- if (nss_cryptoapi_check_unalign(req->nbytes, DES3_EDE_BLOCK_SIZE)) { -+ if (nss_cryptoapi_check_unalign(req->cryptlen, DES3_EDE_BLOCK_SIZE)) { - nss_cfi_err("Invalid cipher len - Not aligned to algo blocksize\n"); -- crypto_ablkcipher_set_flags(crypto_ablkcipher_reqtfm(req), CRYPTO_TFM_RES_BAD_BLOCK_LEN); -+ crypto_skcipher_set_flags(crypto_skcipher_reqtfm(req), CRYPTO_TFM_RES_BAD_BLOCK_LEN); - return -EINVAL; - } - - info.params = ¶ms; -- info.cb_fn = nss_cryptoapi_ablkcipher_done; -+ info.cb_fn = nss_cryptoapi_skcipher_done; - - buf = nss_cryptoapi_ablk_transform(req, &info); - if (!buf) { -diff --git a/cryptoapi/v1.1/nss_cryptoapi_debugfs.c b/cryptoapi/v1.1/nss_cryptoapi_debugfs.c -index dff774c..cf4bc70 100644 ---- a/cryptoapi/v1.1/nss_cryptoapi_debugfs.c -+++ b/cryptoapi/v1.1/nss_cryptoapi_debugfs.c -@@ -55,6 +55,7 @@ - */ - void nss_cryptoapi_debugfs_add_stats(struct dentry *parent, struct nss_cryptoapi_ctx *session_ctx) - { -+ pr_info("add stats"); - debugfs_create_u64("queued", S_IRUGO, parent, &session_ctx->queued); - debugfs_create_u64("completed", S_IRUGO, parent, &session_ctx->completed); - debugfs_create_u64("queue_failed", S_IRUGO, parent, &session_ctx->queue_failed); -diff --git a/cryptoapi/v1.1/nss_cryptoapi_private.h b/cryptoapi/v1.1/nss_cryptoapi_private.h -index 5feb9e3..70c6714 100644 ---- a/cryptoapi/v1.1/nss_cryptoapi_private.h -+++ b/cryptoapi/v1.1/nss_cryptoapi_private.h -@@ -141,16 +141,16 @@ int nss_cryptoapi_sha256_3des_encrypt(struct aead_request *req); - int nss_cryptoapi_sha256_3des_decrypt(struct aead_request *req); - - /* ABLKCIPHER */ --int nss_cryptoapi_ablkcipher_init(struct crypto_tfm *tfm); --void nss_cryptoapi_ablkcipher_exit(struct crypto_tfm *tfm); --int nss_cryptoapi_ablk_aes_setkey(struct crypto_ablkcipher *cipher, const u8 *key, unsigned int len); --int nss_cryptoapi_3des_cbc_setkey(struct crypto_ablkcipher *cipher, const u8 *key, unsigned int len); -+int nss_cryptoapi_skcipher_init(struct crypto_skcipher *tfm); -+void nss_cryptoapi_skcipher_exit(struct crypto_skcipher *tfm); -+int nss_cryptoapi_ablk_aes_setkey(struct crypto_skcipher *cipher, const u8 *key, unsigned int len); -+int nss_cryptoapi_3des_cbc_setkey(struct crypto_skcipher *cipher, const u8 *key, unsigned int len); - --int nss_cryptoapi_ablk_aes_encrypt(struct ablkcipher_request *req); --int nss_cryptoapi_ablk_aes_decrypt(struct ablkcipher_request *req); -+int nss_cryptoapi_ablk_aes_encrypt(struct skcipher_request *req); -+int nss_cryptoapi_ablk_aes_decrypt(struct skcipher_request *req); - --int nss_cryptoapi_3des_cbc_encrypt(struct ablkcipher_request *req); --int nss_cryptoapi_3des_cbc_decrypt(struct ablkcipher_request *req); -+int nss_cryptoapi_3des_cbc_encrypt(struct skcipher_request *req); -+int nss_cryptoapi_3des_cbc_decrypt(struct skcipher_request *req); - - #endif /* __NSS_CRYPTOAPI_PRIVATE_H */ - --- -2.27.0.rc0 - diff --git a/qaa/nss/qca-nss-clients-64/Makefile b/qaa/nss/qca-nss-clients-64/Makefile deleted file mode 100644 index 741646ba8..000000000 --- a/qaa/nss/qca-nss-clients-64/Makefile +++ /dev/null @@ -1,97 +0,0 @@ -include $(TOPDIR)/rules.mk - -PKG_NAME:=qca-nss-clients-64 -PKG_RELEASE:=$(AUTORELEASE) - -PKG_SOURCE_URL:=https://source.codeaurora.org/quic/cc-qrdk/oss/lklm/nss-clients -PKG_SOURCE_PROTO:=git -PKG_SOURCE_DATE:=2021-04-29 -PKG_SOURCE_VERSION:=b93c72c1b72c591c2ddc2f0b24f0e2b457720118 -PKG_MIRROR_HASH:=fbfba64a364b095ea7c9a24cd7af96b63ab0bc29c179e1628c675aa223c0d063 - -include $(INCLUDE_DIR)/kernel.mk -include $(INCLUDE_DIR)/package.mk - -define KernelPackage/qca-nss-drv-pppoe-64 - SECTION:=kernel - CATEGORY:=Kernel modules - SUBMENU:=Network Devices - TITLE:=Kernel driver for NSS (connection manager) - PPPoE - DEPENDS:=@TARGET_ipq807x +kmod-qca-nss-drv-64 +kmod-ppp +kmod-pppoe - FILES:=$(PKG_BUILD_DIR)/pppoe/qca-nss-pppoe.ko - AUTOLOAD:=$(call AutoLoad,51,qca-nss-pppoe) -endef - -define KernelPackage/qca-nss-drv-pppoe-64/Description -Kernel modules for NSS connection manager - Support for PPPoE -endef - -define KernelPackage/qca-nss-drv-bridge-mgr-64 - SECTION:=kernel - CATEGORY:=Kernel modules - SUBMENU:=Network Devices - TITLE:=Kernel driver for NSS bridge manager - DEPENDS:=@LINUX_5_10 @TARGET_ipq807x +kmod-qca-nss-drv-64 +kmod-qca-nss-drv-vlan-mgr-64 - FILES:=$(PKG_BUILD_DIR)/bridge/qca-nss-bridge-mgr.ko - AUTOLOAD:=$(call AutoLoad,51,qca-nss-bridge-mgr) -endef - -define KernelPackage/qca-nss-drv-bridge-mgr-64/Description -Kernel modules for NSS bridge manager -endef - -define KernelPackage/qca-nss-drv-vlan-mgr-64 - SECTION:=kernel - CATEGORY:=Kernel modules - SUBMENU:=Network Devices - TITLE:=Kernel driver for NSS vlan manager - DEPENDS:=@LINUX_5_10 @TARGET_ipq807x +kmod-qca-nss-drv-64 - FILES:=$(PKG_BUILD_DIR)/vlan/qca-nss-vlan.ko - AUTOLOAD:=$(call AutoLoad,51,qca-nss-vlan) -endef - -define KernelPackage/qca-nss-drv-vlan-mgr-64/Description -Kernel modules for NSS vlan manager -endef - -EXTRA_CFLAGS+= \ - -I$(STAGING_DIR)/usr/include/qca-nss-drv \ - -I$(STAGING_DIR)/usr/include/qca-nss-crypto \ - -I$(STAGING_DIR)/usr/include/qca-nss-cfi \ - -I$(STAGING_DIR)/usr/include/qca-nss-gmac \ - -I$(STAGING_DIR)/usr/include/qca-ssdk \ - -I$(STAGING_DIR)/usr/include/qca-ssdk/fal \ - -I$(STAGING_DIR)/usr/include/nat46 - -ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-pppoe-64),) -NSS_CLIENTS_MAKE_OPTS+=pppoe=y -endif - -ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-bridge-mgr-64),) -NSS_CLIENTS_MAKE_OPTS+=bridge-mgr=y -endif - -ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-vlan-mgr-64),) -NSS_CLIENTS_MAKE_OPTS+=vlan-mgr=y -endif - -ifeq ($(CONFIG_TARGET_BOARD), "ipq807x") - SOC="ipq807x_64" -else ifeq ($(CONFIG_TARGET_BOARD), "ipq60xx") - SOC="ipq60xx_64" -endif - -define Build/Compile - $(MAKE) -C "$(LINUX_DIR)" $(strip $(NSS_CLIENTS_MAKE_OPTS)) \ - CROSS_COMPILE="$(TARGET_CROSS)" \ - ARCH="$(LINUX_KARCH)" \ - M="$(PKG_BUILD_DIR)" \ - EXTRA_CFLAGS="$(EXTRA_CFLAGS)" \ - SoC=$(SOC) \ - $(KERNEL_MAKE_FLAGS) \ - modules -endef - -$(eval $(call KernelPackage,qca-nss-drv-pppoe-64)) -$(eval $(call KernelPackage,qca-nss-drv-bridge-mgr-64)) -$(eval $(call KernelPackage,qca-nss-drv-vlan-mgr-64)) diff --git a/qaa/nss/qca-nss-clients-64/files/qca-nss-ipsec b/qaa/nss/qca-nss-clients-64/files/qca-nss-ipsec deleted file mode 100644 index 5f682c8e9..000000000 --- a/qaa/nss/qca-nss-clients-64/files/qca-nss-ipsec +++ /dev/null @@ -1,214 +0,0 @@ -#!/bin/sh /etc/rc.common -# -# Copyright (c) 2018-2019, 2021 The Linux Foundation. All rights reserved. -# -# Permission to use, copy, modify, and/or distribute this software for any -# purpose with or without fee is hereby granted, provided that the above -# copyright notice and this permission notice appear in all copies. -# -# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - -NSS_IPSEC_LOG_FILE=/tmp/.nss_ipsec_log -NSS_IPSEC_LOG_STR_ECM="ECM_Loaded" -NSS_IPSEC_OL_FILE=/tmp/qca_nss_ipsec_ol - -ecm_load () { - if [ ! -d /sys/module/ecm ]; then - /etc/init.d/qca-nss-ecm start - if [ -d /sys/module/ecm ]; then - echo ${NSS_IPSEC_LOG_STR_ECM} >> ${NSS_IPSEC_LOG_FILE} - fi - fi -} - -ecm_unload () { - if [ -f /tmp/.nss_ipsec_log ]; then - str=`grep ${NSS_IPSEC_LOG_STR_ECM} ${NSS_IPSEC_LOG_FILE}` - if [[ $str == ${NSS_IPSEC_LOG_STR_ECM} ]]; then - /etc/init.d/qca-nss-ecm stop - `sed 's/${NSS_IPSEC_LOG_STR_ECM}/ /g' $NSS_IPSEC_LOG_FILE > $NSS_IPSEC_LOG_FILE` - fi - fi -} - -ecm_disable() { - - if [ ! -d /sys/module/ecm ]; then - return; - fi - - echo 1 > /sys/kernel/debug/ecm/front_end_ipv4_stop - echo 1 > /sys/kernel/debug/ecm/front_end_ipv6_stop - echo 1 > /sys/kernel/debug/ecm/ecm_db/defunct_all - sleep 2 -} - -ecm_enable() { - if [ ! -d /sys/module/ecm ]; then - return; - fi - - echo 0 > /sys/kernel/debug/ecm/ecm_db/defunct_all - echo 0 > /sys/kernel/debug/ecm/front_end_ipv4_stop - echo 0 > /sys/kernel/debug/ecm/front_end_ipv6_stop -} - -kernel_version_check_5_4() { - major_ver=$(uname -r | awk -F '.' '{print $1}') - minor_ver=$(uname -r | awk -F '.' '{print $2}') - if [ $major_ver -lt 5 ] || ([ $major_ver -eq 5 ] && [ $minor_ver -lt 4 ] ) ; then - return 1 - else - return 0 - fi -} - -start_klips() { - if kernel_version_check_5_4 - then - echo "Kernel 5.4 doesn't support klips stack." - return $? - fi - - touch $NSS_IPSEC_OL_FILE - ecm_load - - local kernel_version=$(uname -r) - - insmod /lib/modules/${kernel_version}/qca-nss-ipsec-klips.ko - if [ "$?" -gt 0 ]; then - echo "Failed to load plugin. Please start ecm if not done already" - ecm_enable - rm $NSS_IPSEC_OL_FILE - return - fi - - /etc/init.d/ipsec start - sleep 2 - ipsec eroute - - ecm_enable -} - -stop_klips() { - if kernel_version_check_5_4 - then - echo "Kernel 5.4 doesn't support klips stack." - return $? - fi - - ecm_disable - - /etc/init.d/ipsec stop - rmmod qca-nss-ipsec-klips - rm $NSS_IPSEC_OL_FILE - - ecm_unload -} - -start_xfrm() { - touch $NSS_IPSEC_OL_FILE - ecm_load - - local kernel_version=$(uname -r) - - # load all NETKEY modules first. - for mod in xfrm_ipcomp ipcomp xfrm6_tunnel ipcomp6 xfrm6_mode_tunnel xfrm6_mode_beet xfrm6_mode_ro \ - xfrm6_mode_transport xfrm4_mode_transport xfrm4_mode_tunnel \ - xfrm4_tunnel xfrm4_mode_beet esp4 esp6 ah4 ah6 af_key - do - insmod $mod 2> /dev/null - done - - # Now load the xfrm plugin - insmod /lib/modules/${kernel_version}/qca-nss-ipsec-xfrm.ko - if [ "$?" -gt 0 ]; then - echo "Failed to load plugin. Please start ecm if not done already" - ecm_enable - rm $NSS_IPSEC_OL_FILE - return - fi - - /etc/init.d/ipsec start - sleep 2 - - ecm_enable -} - -stop_xfrm() { - ecm_disable - - #Shutdown Pluto first. Then only plugin can be removed. - plutopid=/var/run/pluto/pluto.pid - if [ -f $plutopid ]; then - pid=`cat $plutopid` - if [ ! -z "$pid" ]; then - ipsec whack --shutdown | grep -v "002"; - if [ -s $plutopid ]; then - echo "Attempt to shut Pluto down failed! Trying kill:" - kill $pid; - sleep 5; - fi - fi - rm -rf $plutopid - fi - ip xfrm state flush; - ip xfrm policy flush; - sleep 2 - - #Now we can remove the plugin - retries=5 - while [ -d /sys/module/qca_nss_ipsec_xfrm ] - do - rmmod qca-nss-ipsec-xfrm - if [ "$?" -eq 0 ]; then - rm $NSS_IPSEC_OL_FILE - break - fi - - if [ ${retries} -eq 0 ]; then - echo "Failed to unload qca-nss-ipsec-xfrm plugin!" - exit - fi - - echo "XFRM plugin unload failed; retrying ${retries} times" - sleep 1 - retries=`expr ${retries} - 1` - done - - /etc/init.d/ipsec stop - ecm_unload -} - -start() { - local protostack=`uci -q get ipsec.setup.protostack` - if [ "$protostack" = "klips" ]; then - start_klips - return $? - fi - - start_xfrm - return $? -} - -stop() { - local protostack=`uci -q get ipsec.setup.protostack` - if [ "$protostack" = "klips" ]; then - stop_klips - return $? - fi - - stop_xfrm - return $? -} - -restart() { - stop - start -} diff --git a/qaa/nss/qca-nss-clients-64/files/qca-nss-mirred.init b/qaa/nss/qca-nss-clients-64/files/qca-nss-mirred.init deleted file mode 100644 index 1f931f090..000000000 --- a/qaa/nss/qca-nss-clients-64/files/qca-nss-mirred.init +++ /dev/null @@ -1,28 +0,0 @@ -#!/bin/sh /etc/rc.common - -########################################################################### -# Copyright (c) 2019, The Linux Foundation. All rights reserved. -# Permission to use, copy, modify, and/or distribute this software for -# any purpose with or without fee is hereby granted, provided that the -# above copyright notice and this permission notice appear in all copies. -# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT -# OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -########################################################################### - -restart() { - rmmod act_nssmirred.ko - insmod act_nssmirred.ko -} - -start() { - insmod act_nssmirred.ko -} - -stop() { - rmmod act_nssmirred.ko -} diff --git a/qaa/nss/qca-nss-clients-64/files/qca-nss-ovpn.init b/qaa/nss/qca-nss-clients-64/files/qca-nss-ovpn.init deleted file mode 100644 index 622e295ee..000000000 --- a/qaa/nss/qca-nss-clients-64/files/qca-nss-ovpn.init +++ /dev/null @@ -1,69 +0,0 @@ -#!/bin/sh /etc/rc.common - -########################################################################### -# Copyright (c) 2019, The Linux Foundation. All rights reserved. -# Permission to use, copy, modify, and/or distribute this software for -# any purpose with or without fee is hereby granted, provided that the -# above copyright notice and this permission notice appear in all copies. -# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT -# OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -########################################################################### - -ecm_disable() { - if [ ! -d /sys/module/ecm ]; then - return - fi - - echo 1 > /sys/kernel/debug/ecm/front_end_ipv4_stop - echo 1 > /sys/kernel/debug/ecm/front_end_ipv6_stop - echo 1 > /sys/kernel/debug/ecm/ecm_db/defunct_all - sleep 2 -} - -ecm_enable() { - if [ ! -d /sys/module/ecm ]; then - return - fi - - echo 0 > /sys/kernel/debug/ecm/ecm_db/defunct_all - echo 0 > /sys/kernel/debug/ecm/front_end_ipv4_stop - echo 0 > /sys/kernel/debug/ecm/front_end_ipv6_stop -} - -restart() { - ecm_disable - - /etc/init.d/openvpn stop - rmmod qca-nss-ovpn-link - rmmod qca-nss-ovpn-mgr - - insmod qca-nss-ovpn-mgr - insmod qca-nss-ovpn-link - - if [ "$?" -gt 0 ]; then - echo "Failed to load plugin. Please start ecm if not done already" - ecm_enable - return - fi - - ecm_enable -} - -start() { - restart -} - -stop() { - ecm_disable - - /etc/init.d/openvpn stop - rmmod qca-nss-ovpn-link - rmmod qca-nss-ovpn-mgr - - ecm_enable -} diff --git a/qaa/nss/qca-nss-clients/Makefile b/qaa/nss/qca-nss-clients/Makefile deleted file mode 100644 index e782cf81d..000000000 --- a/qaa/nss/qca-nss-clients/Makefile +++ /dev/null @@ -1,469 +0,0 @@ -include $(TOPDIR)/rules.mk -include $(INCLUDE_DIR)/kernel.mk - -PKG_NAME:=qca-nss-clients -PKG_RELEASE:=2 - -PKG_SOURCE_URL:=https://source.codeaurora.org/quic/qsdk/oss/lklm/nss-clients -PKG_SOURCE_PROTO:=git -PKG_SOURCE_VERSION:=740d0102c518cd49f30c5580982b218b480006b1 -PKG_MIRROR_HASH:=2f427d01dba69b1b89d3a081daf08b36fb345d55b9c9462eb358e5b071e2a171 - -include $(INCLUDE_DIR)/package.mk - -# Keep default as ipq806x for branches that does not have subtarget framework -ifeq ($(CONFIG_TARGET_ipq),y) -subtarget:=$(SUBTARGET) -else -subtarget:=$(CONFIG_TARGET_BOARD) -endif - -ifneq (, $(findstring $(subtarget), "ipq807x" "ipq807x_64" "ipq60xx" "ipq60xx_64")) -# DTLS Manager v2.0 for Hawkeye/Cypress - DTLSMGR_DIR:=v2.0 -# IPsec Manager v2.0 for Hawkeye/Cypress - IPSECMGR_DIR:=v2.0 -# KLIPS plugin - IPSECMGR_KLIPS:= $(PKG_BUILD_DIR)/ipsecmgr/$(IPSECMGR_DIR)/plugins/klips/qca-nss-ipsec-klips.ko -else -# DTLS Manager v1.0 for Akronite. - DTLSMGR_DIR:=v1.0 -# IPsec Manager v1.0 for Akronite. - IPSECMGR_DIR:=v1.0 -# KLIPS plugin not needed - IPSECMGR_KLIPS:= -endif - -define KernelPackage/qca-nss-drv-tun6rd - SECTION:=kernel - CATEGORY:=Kernel modules - SUBMENU:=Network Devices - TITLE:=Kernel driver for NSS (connection manager) - tun6rd - DEPENDS:=+kmod-qca-nss-drv +kmod-sit +6rd @!LINUX_3_18 - FILES:=$(PKG_BUILD_DIR)/qca-nss-tun6rd.ko - AUTOLOAD:=$(call AutoLoad,60,qca-nss-tun6rd) -endef - -define KernelPackage/qca-nss-drv-tun6rd/Description -Kernel modules for NSS connection manager - Support for 6rd tunnel -endef - -define KernelPackage/qca-nss-drv-dtlsmgr - SECTION:=kernel - CATEGORY:=Kernel modules - SUBMENU:=Network Devices - TITLE:=Kernel driver for NSS (connection manager) - dtlsmgr - DEPENDS:=+kmod-qca-nss-drv +kmod-qca-nss-cfi-cryptoapi @!LINUX_3_18 - FILES:=$(PKG_BUILD_DIR)/dtls/$(DTLSMGR_DIR)/qca-nss-dtlsmgr.ko -endef - -define KernelPackage/qca-nss-drv-dtls/Description -Kernel modules for NSS connection manager - Support for DTLS sessions -endef - -define KernelPackage/qca-nss-drv-l2tpv2 - SECTION:=kernel - CATEGORY:=Kernel modules - SUBMENU:=Network Devices - TITLE:=Kernel driver for NSS (connection manager) - l2tp - DEPENDS:=+kmod-qca-nss-drv +kmod-ppp +kmod-l2tp @!LINUX_3_18 - FILES:=$(PKG_BUILD_DIR)/l2tp/l2tpv2/qca-nss-l2tpv2.ko - KCONFIG:=CONFIG_L2TP=y - AUTOLOAD:=$(call AutoLoad,51,qca-nss-l2tpv2) -endef - -define KernelPackage/qca-nss-drv-l2tpv2/Description -Kernel modules for NSS connection manager - Support for l2tp tunnel -endef - -define KernelPackage/qca-nss-drv-pptp - SECTION:=kernel - CATEGORY:=Kernel modules - SUBMENU:=Network Devices - TITLE:=Kernel driver for NSS (connection manager) - PPTP - DEPENDS:=+kmod-qca-nss-drv +kmod-pptp @!LINUX_3_18 - FILES:=$(PKG_BUILD_DIR)/pptp/qca-nss-pptp.ko - AUTOLOAD:=$(call AutoLoad,51,qca-nss-pptp) -endef - -define KernelPackage/qca-nss-drv-pptp/Description -Kernel modules for NSS connection manager - Support for PPTP tunnel -endef - -define KernelPackage/qca-nss-drv-pppoe - SECTION:=kernel - CATEGORY:=Kernel modules - SUBMENU:=Network Devices - TITLE:=Kernel driver for NSS (connection manager) - PPPoE - DEPENDS:=+kmod-qca-nss-drv +kmod-pppoe @!LINUX_3_18 \ - +!(TARGET_ipq_ipq807x_QSDK_256||TARGET_ipq_ipq60xx_QSDK_256):kmod-bonding - FILES:=$(PKG_BUILD_DIR)/pppoe/qca-nss-pppoe.ko - AUTOLOAD:=$(call AutoLoad,51,qca-nss-pppoe) -endef - -define KernelPackage/qca-nss-drv-pppoe/Description -Kernel modules for NSS connection manager - Support for PPPoE -endef - -define KernelPackage/qca-nss-drv-map-t - SECTION:=kernel - CATEGORY:=Kernel modules - SUBMENU:=Network Devices - TITLE:=Kernel driver for NSS (connection manager) - MAP-T - DEPENDS:=+kmod-qca-nss-drv +kmod-nat46 @!LINUX_3_18 - FILES:=$(PKG_BUILD_DIR)/map/map-t/qca-nss-map-t.ko - AUTOLOAD:=$(call AutoLoad,51,qca-nss-map-t) -endef - -define KernelPackage/qca-nss-drv-map-t/Description -Kernel modules for NSS connection manager - Support for MAP-T -endef - -define KernelPackage/qca-nss-drv-gre - SECTION:=kernel - CATEGORY:=Kernel modules - SUBMENU:=Network Devices - TITLE:=Kernel driver for NSS (connection manager) - GRE - DEPENDS:=@TARGET_ipq_ipq806x||TARGET_ipq806x||TARGET_ipq_ipq807x||TARGET_ipq_ipq807x_64||TARGET_ipq807x||TARGET_ipq807x_64||TARGET_ipq_ipq60xx||TARGET_ipq_ipq60xx_64||TARGET_ipq_ipq50xx||TARGET_ipq_ipq50xx_64 \ - +kmod-qca-nss-drv @!LINUX_3_18 +kmod-gre6 - FILES:=$(PKG_BUILD_DIR)/gre/qca-nss-gre.ko $(PKG_BUILD_DIR)/gre/test/qca-nss-gre-test.ko - AUTOLOAD:=$(call AutoLoad,51,qca-nss-gre) -endef - -define KernelPackage/qca-nss-drv-gre/Description -Kernel modules for NSS connection manager - Support for GRE -endef - -define KernelPackage/qca-nss-drv-tunipip6 - SECTION:=kernel - CATEGORY:=Kernel modules - SUBMENU:=Network Devices - TITLE:=Kernel driver for NSS (connection manager) - DS-lite and ipip6 Tunnel - DEPENDS:=+kmod-qca-nss-drv +kmod-iptunnel6 +kmod-ip6-tunnel @!LINUX_3_18 - FILES:=$(PKG_BUILD_DIR)/qca-nss-tunipip6.ko - AUTOLOAD:=$(call AutoLoad,60,qca-nss-tunipip6) -endef - -define KernelPackage/qca-nss-drv-tunipip6/Description -Kernel modules for NSS connection manager -Add support for DS-lite and ipip6 tunnel -endef - -define KernelPackage/qca-nss-drv-profile - SECTION:=kernel - CATEGORY:=Kernel modules - SUBMENU:=Network Devices - DEPENDS:=+kmod-qca-nss-drv @!LINUX_3_18 - TITLE:=Profiler for QCA NSS driver (IPQ806x) - FILES:=$(PKG_BUILD_DIR)/profiler/qca-nss-profile-drv.ko -endef - -define KernelPackage/qca-nss-drv-profile/Description -This package contains a NSS driver profiler for QCA chipset -endef - -define KernelPackage/qca-nss-drv-ipsecmgr - SECTION:=kernel - CATEGORY:=Kernel modules - SUBMENU:=Network Devices - TITLE:=Kernel driver for NSS (ipsec manager) - ipsecmgr - DEPENDS:=@TARGET_ipq806x||TARGET_ipq_ipq806x||TARGET_ipq_ipq807x||TARGET_ipq_ipq807x_64||TARGET_ipq807x||TARGET_ipq807x_64||TARGET_ipq_ipq60xx||TARGET_ipq_ipq60xx_64 \ - +kmod-qca-nss-drv +kmod-qca-nss-ecm-standard +kmod-qca-nss-cfi-cryptoapi @!LINUX_3_18 -ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-l2tpv2),) - DEPENDS+=+kmod-qca-nss-drv-l2tpv2 -endif - FILES:=$(PKG_BUILD_DIR)/ipsecmgr/$(IPSECMGR_DIR)/qca-nss-ipsecmgr.ko $(IPSECMGR_KLIPS) - AUTOLOAD:=$(call AutoLoad,60,qca-nss-ipsecmgr) -endef - -define KernelPackage/qca-nss-drv-ipsecmgr/Description -Kernel module for NSS IPsec offload manager -endef - -define KernelPackage/qca-nss-drv-capwapmgr - SECTION:=kernel - CATEGORY:=Kernel modules - SUBMENU:=Network Devices - DEPENDS:=+kmod-qca-nss-drv +kmod-qca-nss-drv-dtlsmgr @!LINUX_3_18 - TITLE:=NSS CAPWAP Manager for QCA NSS driver (IPQ806x) - FILES:=$(PKG_BUILD_DIR)/capwapmgr/qca-nss-capwapmgr.ko -endef - -define KernelPackage/qca-nss-drv-capwapmgr/Description -This package contains a NSS CAPWAP Manager -endef - -define KernelPackage/qca-nss-drv-bridge-mgr - SECTION:=kernel - CATEGORY:=Kernel modules - SUBMENU:=Network Devices - TITLE:=Kernel driver for NSS bridge manager - DEPENDS:=@TARGET_ipq_ipq807x||TARGET_ipq_ipq807x_64||TARGET_ipq807x||TARGET_ipq807x_64||TARGET_ipq_ipq60xx||TARGET_ipq_ipq60xx_64 \ - +TARGET_ipq_ipq807x:kmod-qca-nss-drv-vlan-mgr \ - +TARGET_ipq_ipq807x_64:kmod-qca-nss-drv-vlan-mgr \ - +TARGET_ipq807x:kmod-qca-nss-drv-vlan-mgr \ - +TARGET_ipq807x_64:kmod-qca-nss-drv-vlan-mgr \ - +TARGET_ipq_ipq60xx:kmod-qca-nss-drv-vlan-mgr \ - +TARGET_ipq_ipq60xx_64:kmod-qca-nss-drv-vlan-mgr @!LINUX_3_18 \ - +!(TARGET_ipq_ipq807x_QSDK_256||TARGET_ipq_ipq60xx_QSDK_256):kmod-bonding - FILES:=$(PKG_BUILD_DIR)/bridge/qca-nss-bridge-mgr.ko - AUTOLOAD:=$(call AutoLoad,51,qca-nss-bridge-mgr) -endef - -define KernelPackage/qca-nss-drv-bridge-mgr/Description -Kernel modules for NSS bridge manager -endef - -define KernelPackage/qca-nss-drv-vlan-mgr - SECTION:=kernel - CATEGORY:=Kernel modules - SUBMENU:=Network Devices - TITLE:=Kernel driver for NSS vlan manager - DEPENDS:=@TARGET_ipq806x||TARGET_ipq807x +kmod-qca-nss-drv @!LINUX_3_18 \ - +!(TARGET_ipq_ipq807x_QSDK_256||TARGET_ipq_ipq60xx_QSDK_256):kmod-bonding - FILES:=$(PKG_BUILD_DIR)/vlan/qca-nss-vlan.ko - AUTOLOAD:=$(call AutoLoad,51,qca-nss-vlan) -endef - -define KernelPackage/qca-nss-drv-vlan-mgr/Description -Kernel modules for NSS vlan manager -endef - -define KernelPackage/qca-nss-drv-qdisc - SECTION:=kernel - CATEGORY:=Kernel modules - SUBMENU:=Network Support - TITLE:=Qdisc for configuring shapers in NSS - DEPENDS:=+kmod-qca-nss-drv @!LINUX_3_18 - FILES:=$(PKG_BUILD_DIR)/nss_qdisc/qca-nss-qdisc.ko - KCONFIG:=CONFIG_NET_CLS_ACT=y - AUTOLOAD:=$(call AutoLoad,58,qca-nss-qdisc) -endef - -define KernelPackage/qca-nss-drv-qdisc/Description -Linux qdisc that aids in configuring shapers in the NSS -endef - -define KernelPackage/qca-nss-drv-lag-mgr - SECTION:=kernel - CATEGORY:=Kernel modules - SUBMENU:=Network Devices - TITLE:=Kernel driver for NSS LAG manager - DEPENDS:=+kmod-qca-nss-drv @!LINUX_3_18 \ - +TARGET_ipq_ipq807x:kmod-qca-nss-drv-vlan-mgr \ - +TARGET_ipq_ipq807x_64:kmod-qca-nss-drv-vlan-mgr @!LINUX_3_18 \ - +TARGET_ipq807x:kmod-qca-nss-drv-vlan-mgr \ - +TARGET_ipq807x_64:kmod-qca-nss-drv-vlan-mgr @!LINUX_3_18 \ - +TARGET_ipq_ipq60xx:kmod-qca-nss-drv-vlan-mgr @!LINUX_3_18 \ - +TARGET_ipq_ipq60xx_64:kmod-qca-nss-drv-vlan-mgr @!LINUX_3_18 \ - +kmod-bonding - FILES:=$(PKG_BUILD_DIR)/lag/qca-nss-lag-mgr.ko - AUTOLOAD:=$(call AutoLoad,51,qca-nss-lag-mgr) -endef - -define KernelPackage/qca-nss-drv-lag-mgr/Description -Kernel modules for NSS LAG manager -endef - -define KernelPackage/qca-nss-drv-netlink - SECTION:=kernel - CATEGORY:=Kernel modules - SUBMENU:=Network Devices - DEPENDS:=@TARGET_ipq807x||TARGET_ipq_ipq807x||TARGET_ipq807x_64||TARGET_ipq_ipq807x_64||TARGET_ipq_ipq60xx||TARGET_ipq_ipq60xx_64||TARGET_ipq_ipq50xx||TARGET_ipq_ipq50xx_64 \ - +kmod-qca-nss-drv @!LINUX_3_18 \ - +PACKAGE_kmod-qca-nss-drv-ipsecmgr:kmod-qca-nss-drv-ipsecmgr \ - +PACKAGE_kmod-qca-nss-drv-dtlsmgr:kmod-qca-nss-drv-dtlsmgr \ - +PACKAGE_kmod-qca-nss-drv-capwapmgr:kmod-qca-nss-drv-capwapmgr @!LINUX_3_18 - TITLE:=NSS NETLINK Manager for QCA NSS driver - FILES:=$(PKG_BUILD_DIR)/netlink/qca-nss-netlink.ko -endef - -define KernelPackage/qca-nss-drv-netlink/Description -Kernel module for NSS netlink manager -endef - -define KernelPackage/qca-nss-drv-ovpn-mgr - SECTION:=kernel - CATEGORY:=Kernel modules - SUBMENU:=Network Devices - TITLE:=Kernel driver for NSS OpenVPN manager - DEPENDS:=+kmod-qca-nss-drv +kmod-qca-nss-cfi-cryptoapi +kmod-tun +kmod-ipt-conntrack @!LINUX_3_18 \ - @TARGET_ipq_ipq807x||TARGET_ipq_ipq807x_64||TARGET_ipq_ipq60xx||TARGET_ipq_ipq60xx_64 - FILES:=$(PKG_BUILD_DIR)/openvpn/src/qca-nss-ovpn-mgr.ko -endef - -define KernelPackage/qca-nss-drv-ovpn-mgr/Description -Kernel module for NSS OpenVPN manager -endef - -define KernelPackage/qca-nss-drv-ovpn-link - SECTION:=kernel - CATEGORY:=Kernel modules - SUBMENU:=Network Devices - TITLE:=Kernel driver for interfacing NSS OpenVPN manager with ECM - DEPENDS:=+kmod-qca-nss-drv-ovpn-mgr +@PACKAGE_kmod-qca-nss-ecm-premium @!LINUX_3_18 \ - @TARGET_ipq_ipq807x||TARGET_ipq_ipq807x_64||TARGET_ipq_ipq60xx||TARGET_ipq_ipq60xx_64 - FILES:=$(PKG_BUILD_DIR)/openvpn/plugins/qca-nss-ovpn-link.ko -endef - -define KernelPackage/qca-nss-drv-ovpn-link/Description -This module registers with ECM and communicates with NSS OpenVPN manager for supporting OpenVPN offload. -endef - -define KernelPackage/qca-nss-drv-pvxlanmgr - SECTION:=kernel - CATEGORY:=Kernel modules - SUBMENU:=Network Devices - DEPENDS:=+kmod-qca-nss-drv @!LINUX_3_18 - TITLE:=NSS PVXLAN Manager for QCA NSS driver - FILES:=$(PKG_BUILD_DIR)/pvxlanmgr/qca-nss-pvxlanmgr.ko -endef - -define KernelPackage/qca-nss-drv-pvxlanmgr/Description -Kernel module for managing NSS PVxLAN -endef - -define Build/InstallDev/qca-nss-clients - $(INSTALL_DIR) $(1)/usr/include/qca-nss-clients - $(CP) $(PKG_BUILD_DIR)/netlink/include/* $(1)/usr/include/qca-nss-clients/ - $(CP) $(PKG_BUILD_DIR)/exports/* $(1)/usr/include/qca-nss-clients/ -endef - -define Build/InstallDev - $(call Build/InstallDev/qca-nss-clients,$(1)) -endef - -define KernelPackage/qca-nss-drv-ovpn-mgr/install - $(INSTALL_DIR) $(1)/etc/init.d - $(INSTALL_BIN) ./files/qca-nss-ovpn.init $(1)/etc/init.d/qca-nss-ovpn -endef - -define KernelPackage/qca-nss-drv-ipsecmgr/install - $(INSTALL_DIR) $(1)/etc/init.d - $(INSTALL_BIN) ./files/qca-nss-ipsec $(1)/etc/init.d/qca-nss-ipsec -endef - - -EXTRA_CFLAGS+= \ - -I$(STAGING_DIR)/usr/include/qca-nss-drv \ - -I$(STAGING_DIR)/usr/include/qca-nss-crypto \ - -I$(STAGING_DIR)/usr/include/qca-nss-cfi \ - -I$(STAGING_DIR)/usr/include/qca-nss-gmac \ - -I$(STAGING_DIR)/usr/include/qca-nss-ecm \ - -I$(STAGING_DIR)/usr/include/qca-ssdk \ - -I$(STAGING_DIR)/usr/include/qca-ssdk/fal \ - -I$(STAGING_DIR)/usr/include/nat46 - -# Build individual packages if selected -ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-profile),) -MAKE_OPTS+=profile=y -endif - -ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-capwapmgr),) -MAKE_OPTS+=capwapmgr=y -EXTRA_CFLAGS += -DNSS_CAPWAPMGR_ONE_NETDEV -endif - -ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-tun6rd),) -MAKE_OPTS+=tun6rd=m -endif - -ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-dtlsmgr),) -MAKE_OPTS+=dtlsmgr=y -endif - -ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-l2tpv2),) -MAKE_OPTS+=l2tpv2=y -EXTRA_CFLAGS += -DNSS_L2TPV2_ENABLED -endif - -ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-pptp),) -MAKE_OPTS+=pptp=y -endif - -ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-map-t),) -MAKE_OPTS+=map-t=y -endif - -ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-tunipip6),) -MAKE_OPTS+=tunipip6=m -endif - -ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-qdisc),) -MAKE_OPTS+=qdisc=y -endif - -ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-ipsecmgr),) -EXTRA_CFLAGS+= -I$(PKG_BUILD_DIR)/exports \ - -I$(STAGING_DIR)/usr/include/qca-nss-ecm -MAKE_OPTS+=ipsecmgr=y -endif - -ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-bridge-mgr),) -MAKE_OPTS+=bridge-mgr=y -endif - -ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-vlan-mgr),) -MAKE_OPTS+=vlan-mgr=y -endif - -ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-lag-mgr),) -MAKE_OPTS+=lag-mgr=y -endif - -ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-gre),) -EXTRA_CFLAGS+= -I$(PKG_BUILD_DIR)/exports -MAKE_OPTS+=gre=y -endif - -ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-pppoe),) -MAKE_OPTS+=pppoe=y -endif - -ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-netlink),) -MAKE_OPTS+=netlink=y -endif - -ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-ovpn-mgr),) -MAKE_OPTS+=ovpn-mgr=y -endif - -ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-ovpn-link),) -MAKE_OPTS+=ovpn-link=y -endif - -ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-pvxlanmgr),) -MAKE_OPTS+=pvxlanmgr=y -endif - -define Build/Compile - $(MAKE) $(PKG_JOBS) -C "$(LINUX_DIR)" $(strip $(MAKE_OPTS)) \ - $(KERNEL_MAKE_FLAGS) \ - $(PKG_MAKE_FLAGS) \ - M="$(PKG_BUILD_DIR)" \ - EXTRA_CFLAGS="$(EXTRA_CFLAGS)" \ - SoC="$(subtarget)" \ - DTLSMGR_DIR="$(DTLSMGR_DIR)" \ - IPSECMGR_DIR="$(IPSECMGR_DIR)" \ - modules -endef - -$(eval $(call KernelPackage,qca-nss-drv-profile)) -$(eval $(call KernelPackage,qca-nss-drv-capwapmgr)) -$(eval $(call KernelPackage,qca-nss-drv-tun6rd)) -$(eval $(call KernelPackage,qca-nss-drv-dtlsmgr)) -$(eval $(call KernelPackage,qca-nss-drv-l2tpv2)) -$(eval $(call KernelPackage,qca-nss-drv-pptp)) -$(eval $(call KernelPackage,qca-nss-drv-pppoe)) -$(eval $(call KernelPackage,qca-nss-drv-map-t)) -$(eval $(call KernelPackage,qca-nss-drv-tunipip6)) -$(eval $(call KernelPackage,qca-nss-drv-qdisc)) -$(eval $(call KernelPackage,qca-nss-drv-netlink)) -$(eval $(call KernelPackage,qca-nss-drv-ipsecmgr)) -$(eval $(call KernelPackage,qca-nss-drv-bridge-mgr)) -$(eval $(call KernelPackage,qca-nss-drv-vlan-mgr)) -$(eval $(call KernelPackage,qca-nss-drv-lag-mgr)) -$(eval $(call KernelPackage,qca-nss-drv-gre)) -$(eval $(call KernelPackage,qca-nss-drv-ovpn-mgr)) -$(eval $(call KernelPackage,qca-nss-drv-ovpn-link)) -$(eval $(call KernelPackage,qca-nss-drv-pvxlanmgr)) diff --git a/qaa/nss/qca-nss-clients/files/qca-nss-ipsec b/qaa/nss/qca-nss-clients/files/qca-nss-ipsec deleted file mode 100644 index bb202e8e7..000000000 --- a/qaa/nss/qca-nss-clients/files/qca-nss-ipsec +++ /dev/null @@ -1,92 +0,0 @@ -#!/bin/sh /etc/rc.common -# -# Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. -# -# Permission to use, copy, modify, and/or distribute this software for any -# purpose with or without fee is hereby granted, provided that the above -# copyright notice and this permission notice appear in all copies. -# -# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - -NSS_IPSEC_LOG_FILE=/tmp/.nss_ipsec_log -NSS_IPSEC_LOG_STR_ECM="ECM_Loaded" - -ecm_load () { - if [ ! -d /sys/module/ecm ]; then - /etc/init.d/qca-nss-ecm start - if [ -d /sys/module/ecm ]; then - echo ${NSS_IPSEC_LOG_STR_ECM} >> ${NSS_IPSEC_LOG_FILE} - fi - fi -} - -ecm_unload () { - if [ -f /tmp/.nss_ipsec_log ]; then - str=`grep ${NSS_IPSEC_LOG_STR_ECM} ${NSS_IPSEC_LOG_FILE}` - if [[ $str == ${NSS_IPSEC_LOG_STR_ECM} ]]; then - /etc/init.d/qca-nss-ecm stop - `sed 's/${NSS_IPSEC_LOG_STR_ECM}/ /g' $NSS_IPSEC_LOG_FILE > $NSS_IPSEC_LOG_FILE` - fi - fi -} - -ecm_disable() { - - if [ ! -d /sys/module/ecm ]; then - return; - fi - - echo 1 > /sys/kernel/debug/ecm/front_end_ipv4_stop - echo 1 > /sys/kernel/debug/ecm/front_end_ipv6_stop - echo 1 > /sys/kernel/debug/ecm/ecm_db/defunct_all - sleep 2 -} - -ecm_enable() { - if [ ! -d /sys/module/ecm ]; then - return; - fi - - echo 0 > /sys/kernel/debug/ecm/ecm_db/defunct_all - echo 0 > /sys/kernel/debug/ecm/front_end_ipv4_stop - echo 0 > /sys/kernel/debug/ecm/front_end_ipv6_stop -} - -start() { - ecm_load - - local kernel_version=$(uname -r) - - insmod /lib/modules/${kernel_version}/qca-nss-ipsec-klips.ko - if [ "$?" -gt 0 ]; then - echo "Failed to load plugin. Please start ecm if not done already" - ecm_enable - return - fi - - /etc/init.d/ipsec start - sleep 2 - ipsec eroute - - ecm_enable -} - -stop() { - ecm_disable - - /etc/init.d/ipsec stop - rmmod qca-nss-ipsec-klips - - ecm_unload -} - -restart() { - stop - start -} diff --git a/qaa/nss/qca-nss-clients/files/qca-nss-mirred.init b/qaa/nss/qca-nss-clients/files/qca-nss-mirred.init deleted file mode 100644 index 1f931f090..000000000 --- a/qaa/nss/qca-nss-clients/files/qca-nss-mirred.init +++ /dev/null @@ -1,28 +0,0 @@ -#!/bin/sh /etc/rc.common - -########################################################################### -# Copyright (c) 2019, The Linux Foundation. All rights reserved. -# Permission to use, copy, modify, and/or distribute this software for -# any purpose with or without fee is hereby granted, provided that the -# above copyright notice and this permission notice appear in all copies. -# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT -# OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -########################################################################### - -restart() { - rmmod act_nssmirred.ko - insmod act_nssmirred.ko -} - -start() { - insmod act_nssmirred.ko -} - -stop() { - rmmod act_nssmirred.ko -} diff --git a/qaa/nss/qca-nss-clients/files/qca-nss-ovpn.init b/qaa/nss/qca-nss-clients/files/qca-nss-ovpn.init deleted file mode 100644 index 622e295ee..000000000 --- a/qaa/nss/qca-nss-clients/files/qca-nss-ovpn.init +++ /dev/null @@ -1,69 +0,0 @@ -#!/bin/sh /etc/rc.common - -########################################################################### -# Copyright (c) 2019, The Linux Foundation. All rights reserved. -# Permission to use, copy, modify, and/or distribute this software for -# any purpose with or without fee is hereby granted, provided that the -# above copyright notice and this permission notice appear in all copies. -# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT -# OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -########################################################################### - -ecm_disable() { - if [ ! -d /sys/module/ecm ]; then - return - fi - - echo 1 > /sys/kernel/debug/ecm/front_end_ipv4_stop - echo 1 > /sys/kernel/debug/ecm/front_end_ipv6_stop - echo 1 > /sys/kernel/debug/ecm/ecm_db/defunct_all - sleep 2 -} - -ecm_enable() { - if [ ! -d /sys/module/ecm ]; then - return - fi - - echo 0 > /sys/kernel/debug/ecm/ecm_db/defunct_all - echo 0 > /sys/kernel/debug/ecm/front_end_ipv4_stop - echo 0 > /sys/kernel/debug/ecm/front_end_ipv6_stop -} - -restart() { - ecm_disable - - /etc/init.d/openvpn stop - rmmod qca-nss-ovpn-link - rmmod qca-nss-ovpn-mgr - - insmod qca-nss-ovpn-mgr - insmod qca-nss-ovpn-link - - if [ "$?" -gt 0 ]; then - echo "Failed to load plugin. Please start ecm if not done already" - ecm_enable - return - fi - - ecm_enable -} - -start() { - restart -} - -stop() { - ecm_disable - - /etc/init.d/openvpn stop - rmmod qca-nss-ovpn-link - rmmod qca-nss-ovpn-mgr - - ecm_enable -} diff --git a/qaa/nss/qca-nss-clients/patches/100-kernel-5.4-support-qdisc.patch b/qaa/nss/qca-nss-clients/patches/100-kernel-5.4-support-qdisc.patch deleted file mode 100644 index 0ec8d766e..000000000 --- a/qaa/nss/qca-nss-clients/patches/100-kernel-5.4-support-qdisc.patch +++ /dev/null @@ -1,1145 +0,0 @@ ---- a/nss_qdisc/nss_qdisc.h -+++ b/nss_qdisc/nss_qdisc.h -@@ -338,7 +340,7 @@ extern void nss_qdisc_destroy(struct nss - * Initializes a shaper in NSS, based on the position of this qdisc (child or root) - * and if its a normal interface or a bridge interface. - */ --extern int nss_qdisc_init(struct Qdisc *sch, struct nss_qdisc *nq, nss_shaper_node_type_t type, uint32_t classid, uint32_t accel_mode); -+extern int nss_qdisc_init(struct Qdisc *sch, struct netlink_ext_ack *extack, struct nss_qdisc *nq, nss_shaper_node_type_t type, uint32_t classid, uint32_t accel_mode); - - /* - * nss_qdisc_start_basic_stats_polling() ---- a/nss_qdisc/nss_bf.c -+++ b/nss_qdisc/nss_bf.c -@@ -69,7 +69,7 @@ static inline struct nss_bf_class_data * - * Configures a new class. - */ - static int nss_bf_change_class(struct Qdisc *sch, u32 classid, u32 parentid, -- struct nlattr **tca, unsigned long *arg) -+ struct nlattr **tca, unsigned long *arg, struct netlink_ext_ack *extack) - { - struct nss_bf_sched_data *q = qdisc_priv(sch); - struct nss_bf_class_data *cl = (struct nss_bf_class_data *)*arg; -@@ -121,7 +121,7 @@ static int nss_bf_change_class(struct Qd - * that is registered to Linux. Therefore we initialize the NSSBF_GROUP shaper - * here. - */ -- if (nss_qdisc_init(sch, &cl->nq, NSS_SHAPER_NODE_TYPE_BF_GROUP, classid, accel_mode) < 0) { -+ if (nss_qdisc_init(sch, extack, &cl->nq, NSS_SHAPER_NODE_TYPE_BF_GROUP, classid, accel_mode) < 0) { - nss_qdisc_error("Nss init for class %u failed\n", classid); - kfree(cl); - return -EINVAL; -@@ -260,7 +260,7 @@ static void nss_bf_destroy_class(struct - /* - * And now we destroy the child. - */ -- qdisc_destroy(cl->qdisc); -+ qdisc_put(cl->qdisc); - - /* - * Stop the stats polling timer and free class -@@ -325,7 +325,7 @@ static int nss_bf_delete_class(struct Qd - * Replaces the qdisc attached to the provided class. - */ - static int nss_bf_graft_class(struct Qdisc *sch, unsigned long arg, struct Qdisc *new, -- struct Qdisc **old) -+ struct Qdisc **old, struct netlink_ext_ack *extack) - { - struct nss_bf_sched_data *q = qdisc_priv(sch); - struct nss_bf_class_data *cl = (struct nss_bf_class_data *)arg; -@@ -432,24 +432,6 @@ static unsigned long nss_bf_get_class(st - } - - /* -- * nss_bf_put_class() -- * Reduces reference count for this class. -- */ --static void nss_bf_put_class(struct Qdisc *sch, unsigned long arg) --{ -- struct nss_bf_class_data *cl = (struct nss_bf_class_data *)arg; -- nss_qdisc_info("bf put class for %p\n", cl); -- -- /* -- * We are safe to destroy the qdisc if the reference count -- * goes down to 0. -- */ -- if (atomic_sub_return(1, &cl->nq.refcnt) == 0) { -- nss_bf_destroy_class(sch, cl); -- } --} -- --/* - * nss_bf_dump_class() - * Dumps all configurable parameters pertaining to this class. - */ -@@ -538,7 +520,7 @@ static void nss_bf_walk(struct Qdisc *sc - * nss_bf_change_qdisc() - * Can be used to configure a nssbf qdisc. - */ --static int nss_bf_change_qdisc(struct Qdisc *sch, struct nlattr *opt) -+static int nss_bf_change_qdisc(struct Qdisc *sch, struct nlattr *opt, struct netlink_ext_ack *extack) - { - struct nss_bf_sched_data *q = qdisc_priv(sch); - struct tc_nssbf_qopt *qopt; -@@ -684,7 +666,7 @@ static void nss_bf_destroy_qdisc(struct - * nss_bf_init_qdisc() - * Initializes the nssbf qdisc. - */ --static int nss_bf_init_qdisc(struct Qdisc *sch, struct nlattr *opt) -+static int nss_bf_init_qdisc(struct Qdisc *sch, struct nlattr *opt, struct netlink_ext_ack *extack) - { - struct nss_bf_sched_data *q = qdisc_priv(sch); - struct tc_nssbf_qopt *qopt; -@@ -720,7 +702,7 @@ static int nss_bf_init_qdisc(struct Qdis - /* - * Initialize the NSSBF shaper in NSS - */ -- if (nss_qdisc_init(sch, &q->nq, NSS_SHAPER_NODE_TYPE_BF, 0, accel_mode) < 0) { -+ if (nss_qdisc_init(sch, extack, &q->nq, NSS_SHAPER_NODE_TYPE_BF, 0, accel_mode) < 0) { - return -EINVAL; - } - -@@ -729,7 +711,7 @@ static int nss_bf_init_qdisc(struct Qdis - /* - * Tune nss_bf parameters. - */ -- if (nss_bf_change_qdisc(sch, opt) < 0) { -+ if (nss_bf_change_qdisc(sch, opt, NULL) < 0) { - nss_qdisc_destroy(&q->nq); - return -EINVAL; - } -@@ -772,7 +754,7 @@ nla_put_failure: - * nss_bf_enqueue() - * Enqueues a skb to nssbf qdisc. - */ --static int nss_bf_enqueue(struct sk_buff *skb, struct Qdisc *sch) -+static int nss_bf_enqueue(struct sk_buff *skb, struct Qdisc *sch, struct sk_buff **to_free) - { - return nss_qdisc_enqueue(skb, sch); - } -@@ -787,18 +769,6 @@ static struct sk_buff *nss_bf_dequeue(st - } - - /* -- * nss_bf_drop() -- * Drops a single skb from linux queue, if not empty. -- * -- * Does not drop packets that are queued in the NSS. -- */ --static unsigned int nss_bf_drop(struct Qdisc *sch) --{ -- printk("In bf drop\n"); -- return nss_qdisc_drop(sch); --} -- --/* - * Registration structure for nssbf class - */ - const struct Qdisc_class_ops nss_bf_class_ops = { -@@ -807,9 +777,8 @@ const struct Qdisc_class_ops nss_bf_clas - .graft = nss_bf_graft_class, - .leaf = nss_bf_leaf_class, - .qlen_notify = nss_bf_qlen_notify, -- .get = nss_bf_get_class, -- .put = nss_bf_put_class, -+ .find = nss_bf_get_class, - .dump = nss_bf_dump_class, - .dump_stats = nss_bf_dump_class_stats, - .walk = nss_bf_walk - }; -@@ -830,7 +798,6 @@ struct Qdisc_ops nss_bf_qdisc_ops __read - .enqueue = nss_bf_enqueue, - .dequeue = nss_bf_dequeue, - .peek = qdisc_peek_dequeued, -- .drop = nss_bf_drop, - .cl_ops = &nss_bf_class_ops, - .priv_size = sizeof(struct nss_bf_sched_data), - .owner = THIS_MODULE ---- a/nss_qdisc/nss_blackhole.c -+++ b/nss_qdisc/nss_blackhole.c -@@ -35,7 +35,7 @@ static struct nla_policy nss_blackhole_p - * nss_blackhole_enqueue() - * Enqueue API for nss blackhole qdisc. - */ --static int nss_blackhole_enqueue(struct sk_buff *skb, struct Qdisc *sch) -+static int nss_blackhole_enqueue(struct sk_buff *skb, struct Qdisc *sch, struct sk_buff **to_free) - { - return nss_qdisc_enqueue(skb, sch); - } -@@ -50,18 +50,6 @@ static struct sk_buff *nss_blackhole_deq - } - - /* -- * nss_blackhole_drop() -- * The following function drops a packet from HLOS queue. -- * -- * Note, this does not drop packets from queues in the NSS. We do not support that. -- */ --static unsigned int nss_blackhole_drop(struct Qdisc *sch) --{ -- nss_qdisc_info("qdisc %x dropping\n", sch->handle); -- return nss_qdisc_drop(sch); --} -- --/* - * nss_blackhole_reset() - * Resets the nss blackhole qdisc. - */ -@@ -92,7 +80,7 @@ static void nss_blackhole_destroy(struct - * nss_blackhole_change() - * Function call used to configure the parameters of the nss blackhole qdisc. - */ --static int nss_blackhole_change(struct Qdisc *sch, struct nlattr *opt) -+static int nss_blackhole_change(struct Qdisc *sch, struct nlattr *opt, struct netlink_ext_ack *extack) - { - struct nss_blackhole_sched_data *q; - struct tc_nssblackhole_qopt *qopt; -@@ -154,7 +142,7 @@ static int nss_blackhole_change(struct Q - * nss_blackhole_init() - * Initializes a nss blackhole qdisc. - */ --static int nss_blackhole_init(struct Qdisc *sch, struct nlattr *opt) -+static int nss_blackhole_init(struct Qdisc *sch, struct nlattr *opt, struct netlink_ext_ack *extack) - { - struct nss_qdisc *nq = qdisc_priv(sch); - struct tc_nssblackhole_qopt *qopt; -@@ -176,12 +164,12 @@ static int nss_blackhole_init(struct Qdi - nss_qdisc_info("qdisc %x initializing\n", sch->handle); - nss_blackhole_reset(sch); - -- if (nss_qdisc_init(sch, nq, NSS_SHAPER_NODE_TYPE_FIFO, 0, accel_mode) < 0) { -+ if (nss_qdisc_init(sch, extack, nq, NSS_SHAPER_NODE_TYPE_FIFO, 0, accel_mode) < 0) { - return -EINVAL; - } - - nss_qdisc_info("qdisc %x initialized with parent %x\n", sch->handle, sch->parent); -- if (nss_blackhole_change(sch, opt) < 0) { -+ if (nss_blackhole_change(sch, opt, NULL) < 0) { - nss_qdisc_destroy(nq); - return -EINVAL; - } -@@ -251,7 +239,6 @@ struct Qdisc_ops nss_blackhole_qdisc_ops - .enqueue = nss_blackhole_enqueue, - .dequeue = nss_blackhole_dequeue, - .peek = nss_blackhole_peek, -- .drop = nss_blackhole_drop, - .init = nss_blackhole_init, - .reset = nss_blackhole_reset, - .destroy = nss_blackhole_destroy, ---- a/nss_qdisc/nss_codel.c -+++ b/nss_qdisc/nss_codel.c -@@ -76,7 +76,7 @@ static struct nla_policy nss_codel_polic - * nss_codel_enqueue() - * Enqueue a packet into nss_codel queue in NSS firmware (bounce). - */ --static int nss_codel_enqueue(struct sk_buff *skb, struct Qdisc *sch) -+static int nss_codel_enqueue(struct sk_buff *skb, struct Qdisc *sch, struct sk_buff **to_free) - { - return nss_qdisc_enqueue(skb, sch); - } -@@ -91,17 +91,6 @@ static struct sk_buff *nss_codel_dequeue - } - - /* -- * nss_codel_drop() -- * Drops a packet from the bounce complete queue. -- * -- * Note: this does not drop packets from the NSS queues. -- */ --static unsigned int nss_codel_drop(struct Qdisc *sch) --{ -- return nss_qdisc_drop(sch); --} -- --/* - * nss_codel_reset() - * Resets nss_codel qdisc. - */ -@@ -234,7 +223,7 @@ static int nss_codel_mem_sz_get(struct Q - * nss_codel_change() - * Used to configure the nss_codel queue in NSS firmware. - */ --static int nss_codel_change(struct Qdisc *sch, struct nlattr *opt) -+static int nss_codel_change(struct Qdisc *sch, struct nlattr *opt, struct netlink_ext_ack *extack) - { - struct nss_codel_sched_data *q = qdisc_priv(sch); - struct tc_nsscodel_qopt *qopt; -@@ -381,7 +370,7 @@ fail: - * nss_codel_init() - * Initializes the nss_codel qdisc. - */ --static int nss_codel_init(struct Qdisc *sch, struct nlattr *opt) -+static int nss_codel_init(struct Qdisc *sch, struct nlattr *opt, struct netlink_ext_ack *extack) - { - struct nss_qdisc *nq = qdisc_priv(sch); - struct tc_nsscodel_qopt *qopt; -@@ -404,7 +393,7 @@ static int nss_codel_init(struct Qdisc * - nss_qdisc_register_configure_callback(nq, nss_codel_configure_callback); - nss_qdisc_register_stats_callback(nq, nss_codel_stats_callback); - -- if (nss_qdisc_init(sch, nq, NSS_SHAPER_NODE_TYPE_CODEL, 0, qopt->accel_mode) < 0) { -+ if (nss_qdisc_init(sch, extack, nq, NSS_SHAPER_NODE_TYPE_CODEL, 0, qopt->accel_mode) < 0) { - return -EINVAL; - } - -@@ -412,7 +401,7 @@ static int nss_codel_init(struct Qdisc * - return -EINVAL; - } - -- if (nss_codel_change(sch, opt) < 0) { -+ if (nss_codel_change(sch, opt, NULL) < 0) { - nss_qdisc_destroy(nq); - return -EINVAL; - } -@@ -511,7 +500,6 @@ struct Qdisc_ops nss_codel_qdisc_ops __r - .enqueue = nss_codel_enqueue, - .dequeue = nss_codel_dequeue, - .peek = nss_codel_peek, -- .drop = nss_codel_drop, - .init = nss_codel_init, - .reset = nss_codel_reset, - .destroy = nss_codel_destroy, -@@ -530,7 +518,6 @@ struct Qdisc_ops nss_fq_codel_qdisc_ops - .enqueue = nss_codel_enqueue, - .dequeue = nss_codel_dequeue, - .peek = nss_codel_peek, -- .drop = nss_codel_drop, - .init = nss_codel_init, - .reset = nss_codel_reset, - .destroy = nss_codel_destroy, ---- a/nss_qdisc/nss_fifo.c -+++ b/nss_qdisc/nss_fifo.c -@@ -29,7 +29,7 @@ static struct nla_policy nss_fifo_policy - [TCA_NSSFIFO_PARMS] = { .len = sizeof(struct tc_nssfifo_qopt) }, - }; - --static int nss_fifo_enqueue(struct sk_buff *skb, struct Qdisc *sch) -+static int nss_fifo_enqueue(struct sk_buff *skb, struct Qdisc *sch, struct sk_buff **to_free) - { - return nss_qdisc_enqueue(skb, sch); - } -@@ -39,12 +39,6 @@ static struct sk_buff *nss_fifo_dequeue( - return nss_qdisc_dequeue(sch); - } - --static unsigned int nss_fifo_drop(struct Qdisc *sch) --{ -- nss_qdisc_info("nss_fifo dropping"); -- return nss_qdisc_drop(sch); --} -- - static void nss_fifo_reset(struct Qdisc *sch) - { - nss_qdisc_info("nss_fifo resetting!"); -@@ -158,7 +152,7 @@ fail: - } - #endif - --static int nss_fifo_change(struct Qdisc *sch, struct nlattr *opt) -+static int nss_fifo_change(struct Qdisc *sch, struct nlattr *opt, struct netlink_ext_ack *extack) - { - struct nss_fifo_sched_data *q = qdisc_priv(sch); - struct nss_qdisc *nq = &q->nq; -@@ -208,7 +202,7 @@ static int nss_fifo_change(struct Qdisc - return 0; - } - --static int nss_fifo_init(struct Qdisc *sch, struct nlattr *opt) -+static int nss_fifo_init(struct Qdisc *sch, struct nlattr *opt, struct netlink_ext_ack *extack) - { - struct nss_qdisc *nq = qdisc_priv(sch); - struct tc_nssfifo_qopt *qopt; -@@ -226,13 +220,13 @@ static int nss_fifo_init(struct Qdisc *s - return -EINVAL; - } - -- if (nss_qdisc_init(sch, nq, NSS_SHAPER_NODE_TYPE_FIFO, 0, qopt->accel_mode) < 0) { -+ if (nss_qdisc_init(sch, extack, nq, NSS_SHAPER_NODE_TYPE_FIFO, 0, qopt->accel_mode) < 0) { - nss_qdisc_warning("Fifo %x init failed", sch->handle); - return -EINVAL; - } - - nss_qdisc_info("NSS fifo initialized - handle %x parent %x\n", sch->handle, sch->parent); -- if (nss_fifo_change(sch, opt) < 0) { -+ if (nss_fifo_change(sch, opt, NULL) < 0) { - nss_qdisc_destroy(nq); - return -EINVAL; - } -@@ -290,7 +284,6 @@ struct Qdisc_ops nss_pfifo_qdisc_ops __r - .enqueue = nss_fifo_enqueue, - .dequeue = nss_fifo_dequeue, - .peek = nss_fifo_peek, -- .drop = nss_fifo_drop, - .init = nss_fifo_init, - .reset = nss_fifo_reset, - .destroy = nss_fifo_destroy, -@@ -305,7 +298,6 @@ struct Qdisc_ops nss_bfifo_qdisc_ops __r - .enqueue = nss_fifo_enqueue, - .dequeue = nss_fifo_dequeue, - .peek = nss_fifo_peek, -- .drop = nss_fifo_drop, - .init = nss_fifo_init, - .reset = nss_fifo_reset, - .destroy = nss_fifo_destroy, ---- a/nss_qdisc/nss_htb.c -+++ b/nss_qdisc/nss_htb.c -@@ -267,7 +267,7 @@ static int nss_htb_ppe_change_class(stru - * Configures a new class. - */ - static int nss_htb_change_class(struct Qdisc *sch, u32 classid, u32 parentid, -- struct nlattr **tca, unsigned long *arg) -+ struct nlattr **tca, unsigned long *arg, struct netlink_ext_ack *extack) - { - struct nss_htb_sched_data *q = qdisc_priv(sch); - struct nss_htb_class_data *cl = (struct nss_htb_class_data *)*arg; -@@ -332,7 +332,7 @@ static int nss_htb_change_class(struct Q - * here. - */ - cl->nq.parent = nq_parent; -- if (nss_qdisc_init(sch, &cl->nq, NSS_SHAPER_NODE_TYPE_HTB_GROUP, classid, accel_mode) < 0) { -+ if (nss_qdisc_init(sch, extack, &cl->nq, NSS_SHAPER_NODE_TYPE_HTB_GROUP, classid, accel_mode) < 0) { - nss_qdisc_error("nss_init for htb class %x failed\n", classid); - goto failure; - } -@@ -478,7 +478,7 @@ static void nss_htb_destroy_class(struct - /* - * And now we destroy the child. - */ -- qdisc_destroy(cl->qdisc); -+ qdisc_put(cl->qdisc); - - /* - * Stop the stats polling timer and free class -@@ -577,7 +577,8 @@ static int nss_htb_delete_class(struct Q - * nss_htb_graft_class() - * Replaces the qdisc attached to the provided class. - */ --static int nss_htb_graft_class(struct Qdisc *sch, unsigned long arg, struct Qdisc *new, struct Qdisc **old) -+static int nss_htb_graft_class(struct Qdisc *sch, unsigned long arg, struct Qdisc *new, struct Qdisc **old, -+ struct netlink_ext_ack *extack) - { - struct nss_htb_class_data *cl = (struct nss_htb_class_data *)arg; - struct nss_if_msg nim_detach; -@@ -682,25 +683,6 @@ static unsigned long nss_htb_get_class(s - } - - /* -- * nss_htb_put_class() -- * Reduces reference count for this class. -- */ --static void nss_htb_put_class(struct Qdisc *sch, unsigned long arg) --{ -- struct nss_htb_class_data *cl = (struct nss_htb_class_data *)arg; -- nss_qdisc_trace("executing put on htb class %x in qdisc %x\n", -- cl->nq.qos_tag, sch->handle); -- -- /* -- * We are safe to destroy the qdisc if the reference count -- * goes down to 0. -- */ -- if (atomic_sub_return(1, &cl->nq.refcnt) == 0) { -- nss_htb_destroy_class(sch, cl); -- } --} -- --/* - * nss_htb_dump_class() - * Dumps all configurable parameters pertaining to this class. - */ -@@ -795,7 +777,7 @@ static void nss_htb_walk(struct Qdisc *s - * nss_htb_change_qdisc() - * Can be used to configure a htb qdisc. - */ --static int nss_htb_change_qdisc(struct Qdisc *sch, struct nlattr *opt) -+static int nss_htb_change_qdisc(struct Qdisc *sch, struct nlattr *opt, struct netlink_ext_ack *extack) - { - struct nss_htb_sched_data *q = qdisc_priv(sch); - struct tc_nsshtb_qopt *qopt; -@@ -945,7 +927,7 @@ static void nss_htb_destroy_qdisc(struct - * nss_htb_init_qdisc() - * Initializes the htb qdisc. - */ --static int nss_htb_init_qdisc(struct Qdisc *sch, struct nlattr *opt) -+static int nss_htb_init_qdisc(struct Qdisc *sch, struct nlattr *opt,struct netlink_ext_ack *extack) - { - struct nss_htb_sched_data *q = qdisc_priv(sch); - struct tc_nsshtb_qopt *qopt; -@@ -977,7 +959,7 @@ static int nss_htb_init_qdisc(struct Qdi - /* - * Initialize the NSSHTB shaper in NSS - */ -- if (nss_qdisc_init(sch, &q->nq, NSS_SHAPER_NODE_TYPE_HTB, 0, accel_mode) < 0) { -+ if (nss_qdisc_init(sch, extack, &q->nq, NSS_SHAPER_NODE_TYPE_HTB, 0, accel_mode) < 0) { - nss_qdisc_error("failed to initialize htb qdisc %x in nss", sch->handle); - return -EINVAL; - } -@@ -987,7 +969,7 @@ static int nss_htb_init_qdisc(struct Qdi - /* - * Tune HTB parameters - */ -- if (nss_htb_change_qdisc(sch, opt) < 0) { -+ if (nss_htb_change_qdisc(sch, opt, NULL) < 0) { - nss_qdisc_destroy(&q->nq); - return -EINVAL; - } -@@ -1032,7 +1014,7 @@ static int nss_htb_dump_qdisc(struct Qdi - * nss_htb_enqueue() - * Enqueues a skb to htb qdisc. - */ --static int nss_htb_enqueue(struct sk_buff *skb, struct Qdisc *sch) -+static int nss_htb_enqueue(struct sk_buff *skb, struct Qdisc *sch, struct sk_buff **to_free) - { - return nss_qdisc_enqueue(skb, sch); - } -@@ -1047,18 +1029,6 @@ static struct sk_buff *nss_htb_dequeue(s - } - - /* -- * nss_htb_drop() -- * Drops a single skb from linux queue, if not empty. -- * -- * Does not drop packets that are queued in the NSS. -- */ --static unsigned int nss_htb_drop(struct Qdisc *sch) --{ -- nss_qdisc_trace("drop called on htb qdisc %x\n", sch->handle); -- return nss_qdisc_drop(sch); --} -- --/* - * Registration structure for htb class - */ - const struct Qdisc_class_ops nss_htb_class_ops = { -@@ -1067,9 +1037,8 @@ const struct Qdisc_class_ops nss_htb_cla - .graft = nss_htb_graft_class, - .leaf = nss_htb_leaf_class, - .qlen_notify = nss_htb_qlen_notify, -- .get = nss_htb_get_class, -- .put = nss_htb_put_class, -+ .find = nss_htb_get_class, - .dump = nss_htb_dump_class, - .dump_stats = nss_htb_dump_class_stats, - .walk = nss_htb_walk - }; -@@ -1090,7 +1058,6 @@ struct Qdisc_ops nss_htb_qdisc_ops __rea - .enqueue = nss_htb_enqueue, - .dequeue = nss_htb_dequeue, - .peek = qdisc_peek_dequeued, -- .drop = nss_htb_drop, - .cl_ops = &nss_htb_class_ops, - .priv_size = sizeof(struct nss_htb_sched_data), - .owner = THIS_MODULE ---- a/nss_qdisc/nss_prio.c -+++ b/nss_qdisc/nss_prio.c -@@ -37,7 +37,7 @@ static struct nla_policy nss_prio_policy - * nss_prio_enqueue() - * Enqueues a skb to nssprio qdisc. - */ --static int nss_prio_enqueue(struct sk_buff *skb, struct Qdisc *sch) -+static int nss_prio_enqueue(struct sk_buff *skb, struct Qdisc *sch, struct sk_buff **to_free) - { - return nss_qdisc_enqueue(skb, sch); - } -@@ -52,17 +52,6 @@ static struct sk_buff *nss_prio_dequeue( - } - - /* -- * nss_prio_drop() -- * Drops a single skb from linux queue, if not empty. -- * -- * Does not drop packets that are queued in the NSS. -- */ --static unsigned int nss_prio_drop(struct Qdisc *sch) --{ -- return nss_qdisc_drop(sch); --} -- --/* - * nss_prio_peek() - * Peeks the first packet in queue for this qdisc. - */ -@@ -117,7 +106,7 @@ static void nss_prio_destroy(struct Qdis - /* - * We can now destroy it - */ -- qdisc_destroy(q->queues[i]); -+ qdisc_put(q->queues[i]); - } - - /* -@@ -157,7 +146,7 @@ static int nss_prio_get_max_bands(struct - * nss_prio_change() - * Function call to configure the nssprio parameters - */ --static int nss_prio_change(struct Qdisc *sch, struct nlattr *opt) -+static int nss_prio_change(struct Qdisc *sch, struct nlattr *opt, struct netlink_ext_ack *extack) - { - struct nss_prio_sched_data *q; - struct tc_nssprio_qopt *qopt; -@@ -209,7 +198,7 @@ static int nss_prio_change(struct Qdisc - * nss_prio_init() - * Initializes the nssprio qdisc - */ --static int nss_prio_init(struct Qdisc *sch, struct nlattr *opt) -+static int nss_prio_init(struct Qdisc *sch, struct nlattr *opt, struct netlink_ext_ack *extack) - { - struct nss_prio_sched_data *q = qdisc_priv(sch); - struct tc_nssprio_qopt *qopt; -@@ -230,14 +219,14 @@ static int nss_prio_init(struct Qdisc *s - accel_mode = qopt->accel_mode; - } - -- if (nss_qdisc_init(sch, &q->nq, NSS_SHAPER_NODE_TYPE_PRIO, 0, accel_mode) < 0) { -+ if (nss_qdisc_init(sch, extack, &q->nq, NSS_SHAPER_NODE_TYPE_PRIO, 0, accel_mode) < 0) { - return -EINVAL; - } - - nss_qdisc_info("Nssprio initialized - handle %x parent %x\n", - sch->handle, sch->parent); - -- if (nss_prio_change(sch, opt) < 0) { -+ if (nss_prio_change(sch, opt, NULL) < 0) { - nss_qdisc_destroy(&q->nq); - return -EINVAL; - } -@@ -280,7 +269,7 @@ nla_put_failure: - * Replaces existing child qdisc with the new qdisc that is passed. - */ - static int nss_prio_graft(struct Qdisc *sch, unsigned long arg, -- struct Qdisc *new, struct Qdisc **old) -+ struct Qdisc *new, struct Qdisc **old, struct netlink_ext_ack *extack) - { - struct nss_prio_sched_data *q = qdisc_priv(sch); - struct nss_qdisc *nq_new = qdisc_priv(new); -@@ -383,15 +372,6 @@ static unsigned long nss_prio_get(struct - } - - /* -- * nss_prio_put() -- * Unused API. -- */ --static void nss_prio_put(struct Qdisc *sch, unsigned long arg) --{ -- nss_qdisc_info("Inside prio put\n"); --} -- --/* - * nss_prio_walk() - * Walks the priority band. - */ -@@ -460,9 +440,8 @@ static int nss_prio_dump_class_stats(str - const struct Qdisc_class_ops nss_prio_class_ops = { - .graft = nss_prio_graft, - .leaf = nss_prio_leaf, -- .get = nss_prio_get, -- .put = nss_prio_put, -+ .find = nss_prio_get, - .walk = nss_prio_walk, - .dump = nss_prio_dump_class, - .dump_stats = nss_prio_dump_class_stats, - }; -@@ -481,7 +459,6 @@ struct Qdisc_ops nss_prio_qdisc_ops __re - .enqueue = nss_prio_enqueue, - .dequeue = nss_prio_dequeue, - .peek = nss_prio_peek, -- .drop = nss_prio_drop, - .init = nss_prio_init, - .reset = nss_prio_reset, - .destroy = nss_prio_destroy, ---- a/nss_qdisc/nss_qdisc.c -+++ b/nss_qdisc/nss_qdisc.c -@@ -929,7 +929,7 @@ static inline void nss_qdisc_add_to_tail - * We do not use the qdisc_enqueue_tail() API here in order - * to prevent stats from getting updated by the API. - */ -- __skb_queue_tail(&sch->q, skb); -+ __qdisc_enqueue_tail(skb, &sch->q); - - spin_unlock_bh(&nq->bounce_protection_lock); - }; -@@ -944,7 +944,7 @@ static inline void nss_qdisc_add_to_tail - * We do not use the qdisc_enqueue_tail() API here in order - * to prevent stats from getting updated by the API. - */ -- __skb_queue_tail(&sch->q, skb); -+ __qdisc_enqueue_tail(skb, &sch->q); - }; - - /* -@@ -966,7 +966,7 @@ static inline struct sk_buff *nss_qdisc_ - * We use __skb_dequeue() to ensure that - * stats don't get updated twice. - */ -- skb = __skb_dequeue(&sch->q); -+ skb = __qdisc_dequeue_head(&sch->q); - - spin_unlock_bh(&nq->bounce_protection_lock); - -@@ -983,7 +983,7 @@ static inline struct sk_buff *nss_qdisc_ - * We use __skb_dequeue() to ensure that - * stats don't get updated twice. - */ -- return __skb_dequeue(&sch->q); -+ return __qdisc_dequeue_head(&sch->q); - }; - - /* -@@ -1064,14 +1064,19 @@ struct Qdisc *nss_qdisc_replace(struct Q - void *nss_qdisc_qopt_get(struct nlattr *opt, struct nla_policy *policy, - uint32_t tca_max, uint32_t tca_params) - { -- struct nlattr *na[tca_max + 1]; -+ struct nlattr *na[8]; - int err; - -+ if (tca_max > 8) { -+ pr_warn("nss_qdisc_qopt_get(): Too many options!\n"); -+ return NULL; -+ } -+ - if (!opt) { - return NULL; - } - -- err = nla_parse_nested(na, tca_max, opt, policy); -+ err = nla_parse_nested_deprecated(na, tca_max, opt, policy, NULL); - if (err < 0) - return NULL; - -@@ -1104,10 +1109,10 @@ struct sk_buff *nss_qdisc_peek(struct Qd - struct sk_buff *skb; - - if (!nq->is_virtual) { -- skb = skb_peek(&sch->q); -+ skb = qdisc_peek_head(sch); - } else { - spin_lock_bh(&nq->bounce_protection_lock); -- skb = skb_peek(&sch->q); -+ skb = qdisc_peek_head(sch); - spin_unlock_bh(&nq->bounce_protection_lock); - } - -@@ -1122,15 +1127,16 @@ unsigned int nss_qdisc_drop(struct Qdisc - { - struct nss_qdisc *nq = qdisc_priv(sch); - unsigned int ret; -+ struct sk_buff *to_free = qdisc_peek_head(sch); - - if (!nq->is_virtual) { -- ret = __qdisc_queue_drop_head(sch, &sch->q); -+ ret = __qdisc_queue_drop_head(sch, &sch->q, &to_free); - } else { - spin_lock_bh(&nq->bounce_protection_lock); - /* - * This function is safe to call within locks - */ -- ret = __qdisc_queue_drop_head(sch, &sch->q); -+ ret = __qdisc_queue_drop_head(sch, &sch->q, &to_free); - spin_unlock_bh(&nq->bounce_protection_lock); - } - -@@ -1958,7 +1964,7 @@ void nss_qdisc_destroy(struct nss_qdisc - * Initializes a shaper in NSS, based on the position of this qdisc (child or root) - * and if its a normal interface or a bridge interface. - */ --int nss_qdisc_init(struct Qdisc *sch, struct nss_qdisc *nq, nss_shaper_node_type_t type, uint32_t classid, uint32_t accel_mode) -+int nss_qdisc_init(struct Qdisc *sch, struct netlink_ext_ack *extack, struct nss_qdisc *nq, nss_shaper_node_type_t type, uint32_t classid, uint32_t accel_mode) - { - struct Qdisc *root; - u32 parent; -@@ -2471,6 +2481,8 @@ static void nss_qdisc_basic_stats_callba - struct gnet_stats_queue *qstats; - struct nss_shaper_node_stats_response *response; - atomic_t *refcnt; -+ refcount_t *refcnt_new; -+ bool is_refcnt_zero = false; - - if (nim->cm.response != NSS_CMN_RESPONSE_ACK) { - nss_qdisc_warning("Qdisc %p (type %d): Receive stats FAILED - " -@@ -2494,7 +2506,7 @@ static void nss_qdisc_basic_stats_callba - } else { - bstats = &qdisc->bstats; - qstats = &qdisc->qstats; -- refcnt = &qdisc->refcnt; -+ refcnt_new = &qdisc->refcnt; - qdisc->q.qlen = response->sn_stats.qlen_packets; - } - -@@ -2533,11 +2545,20 @@ static void nss_qdisc_basic_stats_callba - * All access to nq fields below do not need lock protection. They - * do not get manipulated on different thread contexts. - */ -- if (atomic_read(refcnt) == 0) { -+ if (nq->is_class) { -+ if (atomic_read(refcnt) == 0) -+ is_refcnt_zero = true; -+ } -+ else { -+ if (refcount_read(refcnt_new) == 0) -+ is_refcnt_zero = true; -+ } -+ if (is_refcnt_zero) { - atomic_sub(1, &nq->pending_stat_requests); - wake_up(&nq->wait_queue); - return; - } -+ - - /* - * Requests for stats again, after 1 sec. -@@ -2555,9 +2576,9 @@ static void nss_qdisc_basic_stats_callba - * nss_qdisc_get_stats_timer_callback() - * Invoked periodically to get updated stats - */ --static void nss_qdisc_get_stats_timer_callback(unsigned long int data) -+static void nss_qdisc_get_stats_timer_callback(struct timer_list *arg) - { -- struct nss_qdisc *nq = (struct nss_qdisc *)data; -+ struct nss_qdisc *nq = (struct nss_qdisc *)arg->cust_data; - nss_tx_status_t rc; - struct nss_if_msg nim; - int msg_type; -@@ -2604,9 +2625,8 @@ void nss_qdisc_start_basic_stats_polling - return; - } - -- init_timer(&nq->stats_get_timer); -- nq->stats_get_timer.function = nss_qdisc_get_stats_timer_callback; -- nq->stats_get_timer.data = (unsigned long)nq; -+ timer_setup(&nq->stats_get_timer, nss_qdisc_get_stats_timer_callback, 0); -+ nq->stats_get_timer.cust_data = (unsigned long)nq; - nq->stats_get_timer.expires = jiffies + HZ; - atomic_set(&nq->pending_stat_requests, 1); - add_timer(&nq->stats_get_timer); -@@ -2650,7 +2670,7 @@ int nss_qdisc_gnet_stats_copy_basic(stru - #if (LINUX_VERSION_CODE <= KERNEL_VERSION(3, 18, 0)) - return gnet_stats_copy_basic(d, b); - #else -- return gnet_stats_copy_basic(d, NULL, b); -+ return gnet_stats_copy_basic(NULL, d, NULL, b); - #endif - } - ---- a/nss_qdisc/nss_tbl.c -+++ b/nss_qdisc/nss_tbl.c -@@ -29,7 +29,7 @@ static struct nla_policy nss_tbl_policy[ - [TCA_NSSTBL_PARMS] = { .len = sizeof(struct tc_nsstbl_qopt) }, - }; - --static int nss_tbl_enqueue(struct sk_buff *skb, struct Qdisc *sch) -+static int nss_tbl_enqueue(struct sk_buff *skb, struct Qdisc *sch, struct sk_buff **to_free) - { - return nss_qdisc_enqueue(skb, sch); - } -@@ -39,11 +39,6 @@ static struct sk_buff *nss_tbl_dequeue(s - return nss_qdisc_dequeue(sch); - } - --static unsigned int nss_tbl_drop(struct Qdisc *sch) --{ -- return nss_qdisc_drop(sch); --} -- - static struct sk_buff *nss_tbl_peek(struct Qdisc *sch) - { - return nss_qdisc_peek(sch); -@@ -77,7 +72,7 @@ static void nss_tbl_destroy(struct Qdisc - /* - * Now we can destroy our child qdisc - */ -- qdisc_destroy(q->qdisc); -+ qdisc_put(q->qdisc); - - /* - * Stop the polling of basic stats and destroy qdisc. -@@ -132,7 +127,7 @@ fail: - } - #endif - --static int nss_tbl_change(struct Qdisc *sch, struct nlattr *opt) -+static int nss_tbl_change(struct Qdisc *sch, struct nlattr *opt, struct netlink_ext_ack *extack) - { - struct nss_tbl_sched_data *q = qdisc_priv(sch); - struct tc_nsstbl_qopt *qopt; -@@ -216,7 +211,7 @@ static int nss_tbl_change(struct Qdisc * - return 0; - } - --static int nss_tbl_init(struct Qdisc *sch, struct nlattr *opt) -+static int nss_tbl_init(struct Qdisc *sch, struct nlattr *opt, struct netlink_ext_ack *extack) - { - struct nss_tbl_sched_data *q = qdisc_priv(sch); - struct tc_nsstbl_qopt *qopt; -@@ -232,10 +227,10 @@ static int nss_tbl_init(struct Qdisc *sc - return -EINVAL; - } - -- if (nss_qdisc_init(sch, &q->nq, NSS_SHAPER_NODE_TYPE_TBL, 0, qopt->accel_mode) < 0) -+ if (nss_qdisc_init(sch, extack, &q->nq, NSS_SHAPER_NODE_TYPE_TBL, 0, qopt->accel_mode) < 0) - return -EINVAL; - -- if (nss_tbl_change(sch, opt) < 0) { -+ if (nss_tbl_change(sch, opt, NULL) < 0) { - nss_qdisc_info("Failed to configure tbl\n"); - nss_qdisc_destroy(&q->nq); - return -EINVAL; -@@ -287,7 +282,7 @@ static int nss_tbl_dump_class(struct Qdi - } - - static int nss_tbl_graft(struct Qdisc *sch, unsigned long arg, struct Qdisc *new, -- struct Qdisc **old) -+ struct Qdisc **old, struct netlink_ext_ack *extack) - { - struct nss_tbl_sched_data *q = qdisc_priv(sch); - struct nss_qdisc *nq_new = (struct nss_qdisc *)qdisc_priv(new); -@@ -344,10 +339,6 @@ static unsigned long nss_tbl_get(struct - return 1; - } - --static void nss_tbl_put(struct Qdisc *sch, unsigned long arg) --{ --} -- - static void nss_tbl_walk(struct Qdisc *sch, struct qdisc_walker *walker) - { - nss_qdisc_info("Nsstbl walk called"); -@@ -364,9 +355,8 @@ static void nss_tbl_walk(struct Qdisc *s - const struct Qdisc_class_ops nss_tbl_class_ops = { - .graft = nss_tbl_graft, - .leaf = nss_tbl_leaf, -- .get = nss_tbl_get, -- .put = nss_tbl_put, -+ .find = nss_tbl_get, - .walk = nss_tbl_walk, - .dump = nss_tbl_dump_class, - }; - -@@ -381,7 +370,6 @@ struct Qdisc_ops nss_tbl_qdisc_ops __rea - .enqueue = nss_tbl_enqueue, - .dequeue = nss_tbl_dequeue, - .peek = nss_tbl_peek, -- .drop = nss_tbl_drop, - .init = nss_tbl_init, - .reset = nss_tbl_reset, - .destroy = nss_tbl_destroy, ---- a/nss_qdisc/nss_wred.c -+++ b/nss_qdisc/nss_wred.c -@@ -55,7 +55,7 @@ static struct nla_policy nss_wred_policy - * nss_wred_enqueue() - * Enqueue API for nsswred qdisc - */ --static int nss_wred_enqueue(struct sk_buff *skb, struct Qdisc *sch) -+static int nss_wred_enqueue(struct sk_buff *skb, struct Qdisc *sch, struct sk_buff **to_free) - { - return nss_qdisc_enqueue(skb, sch); - } -@@ -70,16 +70,6 @@ static struct sk_buff *nss_wred_dequeue( - } - - /* -- * nss_wred_drop() -- * Drops a packet from HLOS queue. -- */ --static unsigned int nss_wred_drop(struct Qdisc *sch) --{ -- nss_qdisc_info("nsswred dropping"); -- return nss_qdisc_drop(sch); --} -- --/* - * nss_wred_reset() - * Reset the nsswred qdisc - */ -@@ -171,7 +161,7 @@ fail: - * nss_wred_change() - * Function call to configure the nsswred parameters - */ --static int nss_wred_change(struct Qdisc *sch, struct nlattr *opt) -+static int nss_wred_change(struct Qdisc *sch, struct nlattr *opt, struct netlink_ext_ack *extack) - { - struct nss_wred_sched_data *q = qdisc_priv(sch); - struct tc_nsswred_qopt *qopt; -@@ -298,7 +288,7 @@ static int nss_wred_change(struct Qdisc - * nss_wred_init() - * Init the nsswred qdisc - */ --static int nss_wred_init(struct Qdisc *sch, struct nlattr *opt) -+static int nss_wred_init(struct Qdisc *sch, struct nlattr *opt, struct netlink_ext_ack *extack) - { - struct nss_qdisc *nq = qdisc_priv(sch); - struct tc_nsswred_qopt *qopt; -@@ -315,11 +305,11 @@ static int nss_wred_init(struct Qdisc *s - nss_qdisc_info("Initializing Wred - type %d\n", NSS_SHAPER_NODE_TYPE_WRED); - nss_wred_reset(sch); - -- if (nss_qdisc_init(sch, nq, NSS_SHAPER_NODE_TYPE_WRED, 0, qopt->accel_mode) < 0) -+ if (nss_qdisc_init(sch, extack, nq, NSS_SHAPER_NODE_TYPE_WRED, 0, qopt->accel_mode) < 0) - return -EINVAL; - - nss_qdisc_info("NSS wred initialized - handle %x parent %x\n", sch->handle, sch->parent); -- if (nss_wred_change(sch, opt) < 0) { -+ if (nss_wred_change(sch, opt, NULL) < 0) { - nss_qdisc_destroy(nq); - return -EINVAL; - } -@@ -405,7 +395,6 @@ struct Qdisc_ops nss_red_qdisc_ops __rea - .enqueue = nss_wred_enqueue, - .dequeue = nss_wred_dequeue, - .peek = nss_wred_peek, -- .drop = nss_wred_drop, - .init = nss_wred_init, - .reset = nss_wred_reset, - .destroy = nss_wred_destroy, -@@ -423,7 +412,6 @@ struct Qdisc_ops nss_wred_qdisc_ops __re - .enqueue = nss_wred_enqueue, - .dequeue = nss_wred_dequeue, - .peek = nss_wred_peek, -- .drop = nss_wred_drop, - .init = nss_wred_init, - .reset = nss_wred_reset, - .destroy = nss_wred_destroy, ---- a/nss_qdisc/nss_wrr.c -+++ b/nss_qdisc/nss_wrr.c -@@ -84,7 +84,7 @@ static void nss_wrr_destroy_class(struct - /* - * And now we destroy the child. - */ -- qdisc_destroy(cl->qdisc); -+ qdisc_put(cl->qdisc); - - /* - * Stop the stats polling timer and free class -@@ -219,7 +219,7 @@ static int nss_wrr_ppe_change_class(stru - #endif - - static int nss_wrr_change_class(struct Qdisc *sch, u32 classid, u32 parentid, -- struct nlattr **tca, unsigned long *arg) -+ struct nlattr **tca, unsigned long *arg, struct netlink_ext_ack *extack) - { - struct nss_wrr_sched_data *q = qdisc_priv(sch); - struct nss_wrr_class_data *cl = (struct nss_wrr_class_data *)*arg; -@@ -286,7 +286,7 @@ static int nss_wrr_change_class(struct Q - * here. - */ - cl->nq.parent = &q->nq; -- if (nss_qdisc_init(sch, &cl->nq, NSS_SHAPER_NODE_TYPE_WRR_GROUP, classid, accel_mode) < 0) { -+ if (nss_qdisc_init(sch, extack, &cl->nq, NSS_SHAPER_NODE_TYPE_WRR_GROUP, classid, accel_mode) < 0) { - nss_qdisc_error("Nss init for class %u failed\n", classid); - return -EINVAL; - } -@@ -422,7 +422,7 @@ static int nss_wrr_delete_class(struct Q - } - - static int nss_wrr_graft_class(struct Qdisc *sch, unsigned long arg, struct Qdisc *new, -- struct Qdisc **old) -+ struct Qdisc **old, struct netlink_ext_ack *extack) - { - struct nss_wrr_sched_data *q = qdisc_priv(sch); - struct nss_wrr_class_data *cl = (struct nss_wrr_class_data *)arg; -@@ -517,20 +517,6 @@ static unsigned long nss_wrr_get_class(s - return (unsigned long)cl; - } - --static void nss_wrr_put_class(struct Qdisc *sch, unsigned long arg) --{ -- struct nss_wrr_class_data *cl = (struct nss_wrr_class_data *)arg; -- nss_qdisc_info("nss_wrr put class for %p\n", cl); -- -- /* -- * We are safe to destroy the qdisc if the reference count -- * goes down to 0. -- */ -- if (atomic_sub_return(1, &cl->nq.refcnt) == 0) { -- nss_wrr_destroy_class(sch, cl); -- } --} -- - static int nss_wrr_dump_class(struct Qdisc *sch, unsigned long arg, struct sk_buff *skb, - struct tcmsg *tcm) - { -@@ -600,7 +586,7 @@ static void nss_wrr_walk(struct Qdisc *s - } - } - --static int nss_wrr_init_qdisc(struct Qdisc *sch, struct nlattr *opt) -+static int nss_wrr_init_qdisc(struct Qdisc *sch, struct nlattr *opt, struct netlink_ext_ack *extack) - { - struct nss_wrr_sched_data *q = qdisc_priv(sch); - int err; -@@ -629,7 +615,7 @@ static int nss_wrr_init_qdisc(struct Qdi - /* - * Initialize the NSSWRR shaper in NSS - */ -- if (nss_qdisc_init(sch, &q->nq, NSS_SHAPER_NODE_TYPE_WRR, 0, qopt->accel_mode) < 0) { -+ if (nss_qdisc_init(sch, extack, &q->nq, NSS_SHAPER_NODE_TYPE_WRR, 0, qopt->accel_mode) < 0) { - nss_qdisc_warning("Failed init nss_wrr qdisc"); - return -EINVAL; - } -@@ -669,7 +655,7 @@ static int nss_wrr_init_qdisc(struct Qdi - return 0; - } - --static int nss_wrr_change_qdisc(struct Qdisc *sch, struct nlattr *opt) -+static int nss_wrr_change_qdisc(struct Qdisc *sch, struct nlattr *opt, struct netlink_ext_ack *extack) - { - struct nss_wrr_sched_data *q; - struct tc_nsswrr_qopt *qopt; -@@ -809,7 +795,7 @@ nla_put_failure: - return -EMSGSIZE; - } - --static int nss_wrr_enqueue(struct sk_buff *skb, struct Qdisc *sch) -+static int nss_wrr_enqueue(struct sk_buff *skb, struct Qdisc *sch, struct sk_buff **to_free) - { - return nss_qdisc_enqueue(skb, sch); - } -@@ -819,21 +805,14 @@ static struct sk_buff *nss_wrr_dequeue(s - return nss_qdisc_dequeue(sch); - } - --static unsigned int nss_wrr_drop(struct Qdisc *sch) --{ -- nss_qdisc_info("Nsswrr drop\n"); -- return nss_qdisc_drop(sch); --} -- - const struct Qdisc_class_ops nss_wrr_class_ops = { - .change = nss_wrr_change_class, - .delete = nss_wrr_delete_class, - .graft = nss_wrr_graft_class, - .leaf = nss_wrr_leaf_class, - .qlen_notify = nss_wrr_qlen_notify, -- .get = nss_wrr_get_class, -- .put = nss_wrr_put_class, -+ .find = nss_wrr_get_class, - .dump = nss_wrr_dump_class, - .dump_stats = nss_wrr_dump_class_stats, - .walk = nss_bf_walk - }; -@@ -851,7 +829,6 @@ struct Qdisc_ops nss_wrr_qdisc_ops __rea - .enqueue = nss_wrr_enqueue, - .dequeue = nss_wrr_dequeue, - .peek = qdisc_peek_dequeued, -- .drop = nss_wrr_drop, - .cl_ops = &nss_wrr_class_ops, - .priv_size = sizeof(struct nss_wrr_sched_data), - .owner = THIS_MODULE -@@ -863,9 +840,8 @@ const struct Qdisc_class_ops nss_wfq_cla - .graft = nss_wrr_graft_class, - .leaf = nss_wrr_leaf_class, - .qlen_notify = nss_wrr_qlen_notify, -- .get = nss_wrr_get_class, -- .put = nss_wrr_put_class, -+ .find = nss_wrr_get_class, - .dump = nss_wrr_dump_class, - .dump_stats = nss_wrr_dump_class_stats, - .walk = nss_wrr_walk - }; -@@ -883,7 +858,6 @@ struct Qdisc_ops nss_wfq_qdisc_ops __rea - .enqueue = nss_wrr_enqueue, - .dequeue = nss_wrr_dequeue, - .peek = qdisc_peek_dequeued, -- .drop = nss_wrr_drop, - .cl_ops = &nss_wrr_class_ops, - .priv_size = sizeof(struct nss_wrr_sched_data), - .owner = THIS_MODULE diff --git a/qaa/nss/qca-nss-clients/patches/101-kernel-5.4-support-gre.patch b/qaa/nss/qca-nss-clients/patches/101-kernel-5.4-support-gre.patch deleted file mode 100644 index 705ceabe6..000000000 --- a/qaa/nss/qca-nss-clients/patches/101-kernel-5.4-support-gre.patch +++ /dev/null @@ -1,106 +0,0 @@ -From 7c89187ab2d165ccffed627742e7cb72cce375ef Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Sun, 12 Jul 2020 22:49:30 +0200 -Subject: [PATCH] kernel-5.4-support-gre - ---- - gre/nss_connmgr_gre.c | 16 +++++++--------- - gre/nss_connmgr_gre_v6.c | 4 ++-- - 2 files changed, 9 insertions(+), 11 deletions(-) - -diff --git a/gre/nss_connmgr_gre.c b/gre/nss_connmgr_gre.c -index 52203b1..6de8f6e 100644 ---- a/gre/nss_connmgr_gre.c -+++ b/gre/nss_connmgr_gre.c -@@ -88,7 +88,7 @@ static int nss_connmgr_gre_dev_init(struct net_device *dev) - u64_stats_init(&stats->syncp); - } - -- if ((dev->priv_flags & IFF_GRE_V4_TAP) || (dev->type == ARPHRD_IPGRE)) { -+ if ((dev->priv_flags_qca_ecm & IFF_QCA_ECM_GRE_V4_TAP) || (dev->type == ARPHRD_IPGRE)) { - dev->needed_headroom = sizeof(struct iphdr) + sizeof(struct ethhdr) + MAX_WIFI_HEADROOM + append; - dev->mtu = ETH_DATA_LEN - sizeof(struct iphdr) - append; - dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_SG | NETIF_F_FRAGLIST | NETIF_F_HIGHDMA; -@@ -169,7 +169,7 @@ fail: - * nss_connmgr_gre_dev_stats64() - * Netdev ops function to retrieve stats. - */ --struct rtnl_link_stats64 *nss_connmgr_gre_dev_stats64(struct net_device *dev, -+void nss_connmgr_gre_dev_stats64(struct net_device *dev, - struct rtnl_link_stats64 *tot) - { - uint64_t rx_packets, rx_bytes, tx_packets, tx_bytes; -@@ -202,8 +202,6 @@ struct rtnl_link_stats64 *nss_connmgr_gre_dev_stats64(struct net_device *dev, - tot->rx_dropped = dev->stats.rx_dropped; - tot->tx_dropped = dev->stats.tx_dropped; - } -- -- return tot; - } - - /* -@@ -390,7 +388,7 @@ static int32_t nss_connmgr_gre_prepare_config_cmd(struct net_device *dev, - { - struct nss_gre_config_msg *cmsg = &req->msg.cmsg; - -- if ((dev->type == ARPHRD_ETHER) && (dev->priv_flags & IFF_GRE_V4_TAP)) { -+ if ((dev->type == ARPHRD_ETHER) && (dev->priv_flags_qca_ecm & IFF_QCA_ECM_GRE_V4_TAP)) { - cmsg->mode = NSS_GRE_MODE_TAP; - cmsg->ip_type = NSS_GRE_IP_IPV4; - if (enable_unalign) { -@@ -399,7 +397,7 @@ static int32_t nss_connmgr_gre_prepare_config_cmd(struct net_device *dev, - return nss_connmgr_gre_v4_get_config(dev, req, next_dev, hold); - } - -- if ((dev->type == ARPHRD_ETHER) && (dev->priv_flags & IFF_GRE_V6_TAP)) { -+ if ((dev->type == ARPHRD_ETHER) && (dev->priv_flags_qca_ecm & IFF_QCA_ECM_GRE_V6_TAP)) { - cmsg->mode = NSS_GRE_MODE_TAP; - cmsg->ip_type = NSS_GRE_IP_IPV6; - if (enable_unalign) { -@@ -605,7 +603,7 @@ static bool nss_connmgr_gre_is_gre(struct net_device *dev) - { - if ((dev->type == ARPHRD_IPGRE) || - (dev->type == ARPHRD_IP6GRE) || ((dev->type == ARPHRD_ETHER) && -- (dev->priv_flags & (IFF_GRE_V4_TAP | IFF_GRE_V6_TAP)))) { -+ (dev->priv_flags_qca_ecm & (IFF_QCA_ECM_GRE_V4_TAP | IFF_QCA_ECM_GRE_V6_TAP)))) { - return true; - } - -@@ -692,10 +690,10 @@ static struct net_device *__nss_connmgr_gre_create_interface(struct nss_connmgr_ - nss_connmgr_gre_tap_setup(dev); - - if (cfg->is_ipv6) { -- dev->priv_flags |= IFF_GRE_V6_TAP; -+ dev->priv_flags_qca_ecm |= IFF_QCA_ECM_GRE_V6_TAP; - ret = nss_connmgr_gre_v6_set_config(dev, cfg); - } else { -- dev->priv_flags |= IFF_GRE_V4_TAP; -+ dev->priv_flags_qca_ecm |= IFF_QCA_ECM_GRE_V4_TAP; - ret = nss_connmgr_gre_v4_set_config(dev, cfg); - } - break; -diff --git a/gre/nss_connmgr_gre_v6.c b/gre/nss_connmgr_gre_v6.c -index f9a8e58..e93c7e4 100644 ---- a/gre/nss_connmgr_gre_v6.c -+++ b/gre/nss_connmgr_gre_v6.c -@@ -46,7 +46,7 @@ static struct net_device *nss_connmgr_gre_v6_get_tx_dev(uint8_t *dest_ip) - struct net_device *dev; - - memcpy(ipv6_addr.s6_addr, dest_ip, 16); -- rt = rt6_lookup(&init_net, &ipv6_addr, NULL, 0, 0); -+ rt = rt6_lookup(&init_net, &ipv6_addr, NULL, 0, NULL, 0); - if (!rt) { - return NULL; - } -@@ -92,7 +92,7 @@ static int nss_connmgr_gre_v6_get_mac_address(uint8_t *src_ip, uint8_t *dest_ip, - * Find dest MAC address - */ - memcpy(ipv6_addr.s6_addr, dest_ip, 16); -- rt = rt6_lookup(&init_net, &ipv6_addr, NULL, 0, 0); -+ rt = rt6_lookup(&init_net, &ipv6_addr, NULL, 0, NULL, 0); - if (!rt) { - return GRE_ERR_NEIGH_LOOKUP; - } --- -2.27.0 - diff --git a/qaa/nss/qca-nss-clients/patches/102-kernel-5.4-support-ipsec.patch b/qaa/nss/qca-nss-clients/patches/102-kernel-5.4-support-ipsec.patch deleted file mode 100644 index de43b4d01..000000000 --- a/qaa/nss/qca-nss-clients/patches/102-kernel-5.4-support-ipsec.patch +++ /dev/null @@ -1,29 +0,0 @@ ---- a/ipsecmgr/v1.0/nss_ipsecmgr.c -+++ b/ipsecmgr/v1.0/nss_ipsecmgr.c -@@ -377,7 +377,7 @@ free: - * nss_ipsecmgr_tunnel_stats() - * get tunnel statistics - */ --static struct rtnl_link_stats64 *nss_ipsecmgr_tunnel_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) -+void nss_ipsecmgr_tunnel_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) - { - struct nss_ipsecmgr_priv *priv = netdev_priv(dev); - -@@ -389,8 +389,6 @@ static struct rtnl_link_stats64 *nss_ips - read_lock_bh(&ipsecmgr_ctx->lock); - memcpy(stats, &priv->stats, sizeof(struct rtnl_link_stats64)); - read_unlock_bh(&ipsecmgr_ctx->lock); -- -- return stats; - } - - /* -@@ -442,7 +440,7 @@ static void nss_ipsecmgr_tunnel_setup(st - dev->header_ops = NULL; - dev->netdev_ops = &nss_ipsecmgr_tunnel_ops; - -- dev->destructor = nss_ipsecmgr_tunnel_free; -+ dev->priv_destructor = nss_ipsecmgr_tunnel_free; - - /* - * get the MAC address from the ethernet device diff --git a/qaa/nss/qca-nss-clients/patches/103-kernel-5.4-support-dtls.patch b/qaa/nss/qca-nss-clients/patches/103-kernel-5.4-support-dtls.patch deleted file mode 100644 index ae9c91470..000000000 --- a/qaa/nss/qca-nss-clients/patches/103-kernel-5.4-support-dtls.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/dtls/v1.0/nss_connmgr_dtls_netdev.c -+++ b/dtls/v1.0/nss_connmgr_dtls_netdev.c -@@ -160,7 +160,7 @@ static void nss_dtlsmgr_dev_setup(struct - dev->ethtool_ops = NULL; - dev->header_ops = NULL; - dev->netdev_ops = &nss_dtlsmgr_session_ops; -- dev->destructor = NULL; -+ dev->priv_destructor = NULL; - - memcpy(dev->dev_addr, "\xaa\xbb\xcc\xdd\xee\xff", dev->addr_len); - memset(dev->broadcast, 0xff, dev->addr_len); diff --git a/qaa/nss/qca-nss-clients/patches/104-kernel-5.4-support-l2tp.patch b/qaa/nss/qca-nss-clients/patches/104-kernel-5.4-support-l2tp.patch deleted file mode 100644 index c637235cc..000000000 --- a/qaa/nss/qca-nss-clients/patches/104-kernel-5.4-support-l2tp.patch +++ /dev/null @@ -1,64 +0,0 @@ ---- a/l2tp/l2tpv2/nss_connmgr_l2tpv2.h -+++ b/l2tp/l2tpv2/nss_connmgr_l2tpv2.h -@@ -30,10 +30,10 @@ - - #define L2TP_V_2 2 - --#define tunnel_hold(tunnel) atomic_inc(&tunnel->ref_count) --#define tunnel_put(tunnel) atomic_dec(&tunnel->ref_count) --#define session_hold(session) atomic_inc(&session->ref_count) --#define session_put(session) atomic_dec(&session->ref_count) -+#define tunnel_hold(tunnel) refcount_inc(&tunnel->ref_count) -+#define tunnel_put(tunnel) refcount_dec(&tunnel->ref_count) -+#define session_hold(session) refcount_inc(&session->ref_count) -+#define session_put(session) refcount_dec(&session->ref_count) - - /* - * ---------------------------------------------------------------------------------- ---- a/l2tp/l2tpv2/nss_connmgr_l2tpv2.c -+++ b/l2tp/l2tpv2/nss_connmgr_l2tpv2.c -@@ -244,7 +244,7 @@ static struct nss_connmgr_l2tpv2_session - */ - data->l2tpv2.session.session_id = session->session_id; - data->l2tpv2.session.peer_session_id = session->peer_session_id; -- data->l2tpv2.session.offset = session->offset; -+ data->l2tpv2.session.offset = 0; - data->l2tpv2.session.hdr_len = session->hdr_len; - data->l2tpv2.session.reorder_timeout = session->reorder_timeout; - data->l2tpv2.session.recv_seq = session->recv_seq; -@@ -253,7 +253,7 @@ static struct nss_connmgr_l2tpv2_session - nss_connmgr_l2tpv2_info("sess %u, peer=%u nr=%u ns=%u off=%u hdr_len=%u timeout=%x" - " recv_seq=%x send_seq=%x\n", - session->session_id, session->peer_session_id, session->nr, -- session->ns, session->offset, session->hdr_len, -+ session->ns, 0, session->hdr_len, - session->reorder_timeout, session->recv_seq, - session->send_seq); - ---- a/l2tp/l2tpv2/nss_l2tpv2_stats.c -+++ b/l2tp/l2tpv2/nss_l2tpv2_stats.c -@@ -21,6 +21,7 @@ - */ - - #include -+#include - #include - #include - #include -@@ -103,14 +104,14 @@ void nss_l2tpv2_update_dev_stats(struct - /* - * Update tunnel & session stats - */ -- tunnel = l2tp_tunnel_find(dev_net(dev), data.l2tpv2.tunnel.tunnel_id); -+ tunnel = l2tp_tunnel_get(dev_net(dev), data.l2tpv2.tunnel.tunnel_id); - if (!tunnel) { - dev_put(dev); - return; - } - tunnel_hold(tunnel); - -- session = l2tp_session_find(dev_net(dev), tunnel, data.l2tpv2.session.session_id); -+ session = l2tp_session_get(dev_net(dev), data.l2tpv2.session.session_id); - if (!session) { - tunnel_put(tunnel); - dev_put(dev); diff --git a/qaa/nss/qca-nss-clients/patches/200-qdisc-fix-compile-error.patch b/qaa/nss/qca-nss-clients/patches/200-qdisc-fix-compile-error.patch deleted file mode 100644 index 4e147489b..000000000 --- a/qaa/nss/qca-nss-clients/patches/200-qdisc-fix-compile-error.patch +++ /dev/null @@ -1,14 +0,0 @@ ---- a/nss_qdisc/nss_qdisc.c -+++ b/nss_qdisc/nss_qdisc.c -@@ -2708,9 +2708,11 @@ static int nss_qdisc_if_event_cb(struct - case NETDEV_BR_JOIN: - nss_qdisc_info("Reveived NETDEV_BR_JOIN on interface %s\n", - dev->name); -+ goto fall_through; - case NETDEV_BR_LEAVE: - nss_qdisc_info("Reveived NETDEV_BR_LEAVE on interface %s\n", - dev->name); -+fall_through: - br = nss_qdisc_get_dev_master(dev); - if_num = nss_cmn_get_interface_number(nss_qdisc_ctx, dev); - diff --git a/qaa/nss/qca-nss-clients/patches/202-vlanmgr-fix-compile-error.patch b/qaa/nss/qca-nss-clients/patches/202-vlanmgr-fix-compile-error.patch deleted file mode 100644 index 53af31924..000000000 --- a/qaa/nss/qca-nss-clients/patches/202-vlanmgr-fix-compile-error.patch +++ /dev/null @@ -1,48 +0,0 @@ ---- a/vlan/nss_vlan_mgr.c -+++ b/vlan/nss_vlan_mgr.c -@@ -820,8 +820,10 @@ static struct nss_vlan_pvt *nss_vlan_mgr - */ - static void nss_vlan_mgr_instance_free(struct nss_vlan_pvt *v) - { -+#ifdef NSS_VLAN_MGR_PPE_SUPPORT - int32_t i; - int ret = 0; -+#endif - - spin_lock(&vlan_mgr_ctx.lock); - BUG_ON(--v->refs); -@@ -979,8 +981,11 @@ static int nss_vlan_mgr_register_event(s - int ret; - #endif - uint32_t vlan_tag; -+#ifdef NSS_VLAN_MGR_PPE_SUPPORT - struct net_device *slave; -- int32_t port, port_if; -+ int32_t port; -+#endif -+ int32_t port_if; - struct vlan_dev_priv *vlan; - struct net_device *real_dev; - bool is_bond_master = false; -@@ -1354,8 +1359,10 @@ return_with_error: - int nss_vlan_mgr_join_bridge(struct net_device *dev, uint32_t bridge_vsi) - { - struct nss_vlan_pvt *v = nss_vlan_mgr_instance_find_and_ref(dev); -+#ifdef NSS_VLAN_MGR_PPE_SUPPORT - struct net_device *real_dev; - int ret; -+#endif - - if (!v) - return 0; -@@ -1415,8 +1422,10 @@ EXPORT_SYMBOL(nss_vlan_mgr_join_bridge); - int nss_vlan_mgr_leave_bridge(struct net_device *dev, uint32_t bridge_vsi) - { - struct nss_vlan_pvt *v = nss_vlan_mgr_instance_find_and_ref(dev); -+#ifdef NSS_VLAN_MGR_PPE_SUPPORT - struct net_device *real_dev; - int ret; -+#endif - - if (!v) - return 0; diff --git a/qaa/nss/qca-nss-crypto/Makefile b/qaa/nss/qca-nss-crypto/Makefile deleted file mode 100644 index 213e24471..000000000 --- a/qaa/nss/qca-nss-crypto/Makefile +++ /dev/null @@ -1,74 +0,0 @@ -include $(TOPDIR)/rules.mk -include $(INCLUDE_DIR)/kernel.mk - -PKG_NAME:=qca-nss-crypto -PKG_RELEASE:=1 - -PKG_SOURCE_URL:=https://source.codeaurora.org/quic/qsdk/oss/lklm/nss-crypto -PKG_SOURCE_PROTO:=git -PKG_SOURCE_VERSION:=e7651c2986d30b5e8ca5ad6b9a72c47febdf3cca -PKG_MIRROR_HASH:=381ba448ccd9e0ff69fa52b3e10687b72260b7d0bf865cac10be7f159573b6c8 - -include $(INCLUDE_DIR)/package.mk - -ifeq ($(CONFIG_TARGET_ipq),y) -subtarget:=$(SUBTARGET) -else -subtarget:=$(CONFIG_TARGET_BOARD) -endif - -# v1.0 is for Akronite -# v2.0 is for Hawkeye/Cypress/Maple -ifneq (, $(findstring $(subtarget), "ipq807x" "ipq807x_64" "ipq60xx" "ipq60xx_64" "ipq50xx" "ipq50xx_64")) -NSS_CRYPTO_DIR:=v2.0 -else -NSS_CRYPTO_DIR:=v1.0 -endif - -define KernelPackage/qca-nss-crypto/Default - SECTION:=kernel - CATEGORY:=Kernel modules - SUBMENU:=Network Devices - DEPENDS:=@(TARGET_ipq806x||TARGET_ipq807x||TARGET_ipq50xx||TARGET_ipq60xx) +kmod-qca-nss-drv -endef - -define KernelPackage/qca-nss-crypto - $(call KernelPackage/qca-nss-crypto/Default) - TITLE:=Kernel driver for NSS crypto driver - FILES:=$(PKG_BUILD_DIR)/$(NSS_CRYPTO_DIR)/src/qca-nss-crypto.ko \ - $(PKG_BUILD_DIR)/$(NSS_CRYPTO_DIR)/tool/qca-nss-crypto-tool.ko - AUTOLOAD:=$(call AutoLoad,52,qca-nss-crypto) -endef - -define KernelPackage/qca-nss-crypto/Description -This package contains a NSS crypto driver for QCA chipset -endef - -define Build/InstallDev/qca-nss-crypto - $(INSTALL_DIR) $(1)/usr/include/qca-nss-crypto - $(CP) $(PKG_BUILD_DIR)/$(NSS_CRYPTO_DIR)/include/* $(1)/usr/include/qca-nss-crypto -endef - -define Build/InstallDev - $(call Build/InstallDev/qca-nss-crypto,$(1)) -endef - -EXTRA_CFLAGS+= \ - -DCONFIG_NSS_DEBUG_LEVEL=4 \ - -I$(STAGING_DIR)/usr/include/qca-nss-crypto \ - -I$(STAGING_DIR)/usr/include/qca-nss-drv \ - -I$(PKG_BUILD_DIR)/$(NSS_CRYPTO_DIR)/include \ - -I$(PKG_BUILD_DIR)/$(NSS_CRYPTO_DIR)/src - -define Build/Compile - $(MAKE) $(PKG_JOBS) -C "$(LINUX_DIR)" \ - $(KERNEL_MAKE_FLAGS) \ - $(PKG_MAKE_FLAGS) \ - M="$(PKG_BUILD_DIR)" \ - EXTRA_CFLAGS="$(EXTRA_CFLAGS)" \ - NSS_CRYPTO_DIR=$(NSS_CRYPTO_DIR) \ - SoC="$(subtarget)" \ - modules -endef - -$(eval $(call KernelPackage,qca-nss-crypto)) diff --git a/qaa/nss/qca-nss-crypto/patches/100-kernel-5.4-support.patch b/qaa/nss/qca-nss-crypto/patches/100-kernel-5.4-support.patch deleted file mode 100644 index b9ef6191e..000000000 --- a/qaa/nss/qca-nss-crypto/patches/100-kernel-5.4-support.patch +++ /dev/null @@ -1,42 +0,0 @@ ---- a/v1.0/tool/nss_crypto_bench.c -+++ b/v1.0/tool/nss_crypto_bench.c -@@ -75,8 +75,8 @@ static DECLARE_WAIT_QUEUE_HEAD(tx_comp); - static DECLARE_WAIT_QUEUE_HEAD(tx_start); - static struct task_struct *tx_thread = NULL; - --static struct timeval init_time; --static struct timeval comp_time; -+static struct timespec64 init_time; -+static struct timespec64 comp_time; - static spinlock_t op_lock; - static nss_crypto_handle_t crypto_hdl; - -@@ -782,7 +782,7 @@ static int crypto_bench_tx(void *arg) - crypto_bench_debug("#"); - - /* get start time */ -- do_gettimeofday(&init_time); -+ ktime_get_real_ts64(&init_time); - - /** - * Request submission -@@ -812,8 +812,8 @@ static int crypto_bench_tx(void *arg) - * Calculate time and output the Mbps - */ - -- init_usecs = (init_time.tv_sec * 1000 * 1000) + init_time.tv_usec; -- comp_usecs = (comp_time.tv_sec * 1000 * 1000) + comp_time.tv_usec; -+ init_usecs = (init_time.tv_sec * 1000 * 1000) + (init_time.tv_nsec / NSEC_PER_USEC); -+ comp_usecs = (comp_time.tv_sec * 1000 * 1000) + (comp_time.tv_nsec / NSEC_PER_USEC); - delta_usecs = comp_usecs - init_usecs; - - reqs_completed = param.num_reqs - atomic_read(&tx_reqs); -@@ -870,7 +870,7 @@ static void crypto_bench_done(struct nss - nss_crypto_buf_free(crypto_hdl, buf); - - if (atomic_dec_and_test(&tx_reqs)) { -- do_gettimeofday(&comp_time); -+ ktime_get_real_ts64(&comp_time); - - wake_up_interruptible(&tx_comp); - param.num_loops--; diff --git a/qaa/nss/qca-nss-crypto/patches/200-fix-NULL-pointer-exception.patch b/qaa/nss/qca-nss-crypto/patches/200-fix-NULL-pointer-exception.patch deleted file mode 100644 index 6bd95109a..000000000 --- a/qaa/nss/qca-nss-crypto/patches/200-fix-NULL-pointer-exception.patch +++ /dev/null @@ -1,57 +0,0 @@ ---- a/v1.0/src/nss_crypto_if.c -+++ b/v1.0/src/nss_crypto_if.c -@@ -370,15 +370,16 @@ void nss_crypto_transform_done(struct ne - struct nss_crypto_buf *buf = (struct nss_crypto_buf *)skb->data; - struct nss_crypto_buf_node *entry; - void *addr; -+ struct device *cdev = gbl_crypto_ctrl.eng[0].dev; - - if (likely(buf->data_in == buf->data_out)) { -- dma_unmap_single(NULL, buf->data_in, buf->data_len, DMA_BIDIRECTIONAL); -+ dma_unmap_single(cdev, buf->data_in, buf->data_len, DMA_BIDIRECTIONAL); - } else { -- dma_unmap_single(NULL, buf->data_in, buf->data_len, DMA_TO_DEVICE); -- dma_unmap_single(NULL, buf->data_out, buf->data_len, DMA_FROM_DEVICE); -+ dma_unmap_single(cdev, buf->data_in, buf->data_len, DMA_TO_DEVICE); -+ dma_unmap_single(cdev, buf->data_out, buf->data_len, DMA_FROM_DEVICE); - } - -- dma_unmap_single(NULL, buf->iv_addr, L1_CACHE_BYTES, DMA_BIDIRECTIONAL); -+ dma_unmap_single(cdev, buf->iv_addr, L1_CACHE_BYTES, DMA_BIDIRECTIONAL); - - addr = phys_to_virt(buf->iv_addr); - entry = container_of(addr, struct nss_crypto_buf_node, results); -@@ -531,6 +532,7 @@ nss_crypto_status_t nss_crypto_transform - uint32_t paddr; - void *vaddr; - size_t len; -+ struct device *cdev = gbl_crypto_ctrl.eng[0].dev; - - if (!buf->cb_fn) { - nss_crypto_warn("%p:no buffer(%p) callback present\n", crypto, buf); -@@ -544,7 +546,7 @@ nss_crypto_status_t nss_crypto_transform - */ - vaddr = (void *)buf->data_in; - len = buf->data_len; -- paddr = dma_map_single(NULL, vaddr, len, DMA_TO_DEVICE); -+ paddr = dma_map_single(cdev, vaddr, len, DMA_TO_DEVICE); - buf->data_in = paddr; - - if (vaddr == (void *)buf->data_out) { -@@ -555,14 +557,14 @@ nss_crypto_status_t nss_crypto_transform - */ - vaddr = (void *)buf->data_out; - len = buf->data_len; -- paddr = dma_map_single(NULL, vaddr, len, DMA_FROM_DEVICE); -+ paddr = dma_map_single(cdev, vaddr, len, DMA_FROM_DEVICE); - buf->data_out = paddr; - } - - /* - * We need to map the results into IV - */ -- paddr = dma_map_single(NULL, entry->results, L1_CACHE_BYTES, DMA_BIDIRECTIONAL); -+ paddr = dma_map_single(cdev, entry->results, L1_CACHE_BYTES, DMA_BIDIRECTIONAL); - buf->hash_addr = paddr; - buf->iv_addr = paddr; - diff --git a/qaa/nss/qca-nss-dp/Makefile b/qaa/nss/qca-nss-dp/Makefile deleted file mode 100644 index 8da7d314a..000000000 --- a/qaa/nss/qca-nss-dp/Makefile +++ /dev/null @@ -1,62 +0,0 @@ -include $(TOPDIR)/rules.mk - -PKG_NAME:=qca-nss-dp -PKG_RELEASE:=$(AUTORELEASE) - -PKG_SOURCE_URL:=https://source.codeaurora.org/quic/cc-qrdk/oss/lklm/nss-dp -PKG_SOURCE_PROTO:=git -PKG_SOURCE_DATE:=2021-03-26 -PKG_SOURCE_VERSION:=e0c89348d5ad99559ce2fbe15d37b3b5bc66aa03 -PKG_MIRROR_HASH:=f369f0c3b33b5f4ad6d0a6ad6ac5495f63c9ecaf94e4e7fa345169f3e44fcf45 - -PKG_BUILD_PARALLEL:=1 - -include $(INCLUDE_DIR)/kernel.mk -include $(INCLUDE_DIR)/package.mk - -define KernelPackage/qca-nss-dp - SECTION:=kernel - CATEGORY:=Kernel modules - SUBMENU:=Network Devices - DEPENDS:=@(TARGET_ipq807x||TARGET_ipq60xx) +kmod-qca-ssdk-nohnat - TITLE:=Kernel driver for NSS data plane - FILES:=$(PKG_BUILD_DIR)/qca-nss-dp.ko - AUTOLOAD:=$(call AutoLoad,31,qca-nss-dp) -endef - -define KernelPackage/qca-nss-dp/Description -This package contains a NSS data plane driver for QCA chipset -endef - -define Build/InstallDev - mkdir -p $(1)/usr/include/qca-nss-dp - $(CP) $(PKG_BUILD_DIR)/exports/* $(1)/usr/include/qca-nss-dp/ -endef - -EXTRA_CFLAGS+= \ - -I$(STAGING_DIR)/usr/include/qca-ssdk - -NSS_DP_HAL_DIR:=$(PKG_BUILD_DIR)/hal -define Build/Configure - $(LN) $(NSS_DP_HAL_DIR)/arch/$(CONFIG_TARGET_BOARD)/nss_$(CONFIG_TARGET_BOARD).h \ - $(PKG_BUILD_DIR)/exports/nss_dp_arch.h -endef - -ifeq ($(CONFIG_TARGET_BOARD), "ipq807x") - SOC="ipq807x_64" -else ifeq ($(CONFIG_TARGET_BOARD), "ipq60xx") - SOC="ipq60xx_64" -endif - -define Build/Compile - +$(MAKE) -C "$(LINUX_DIR)" \ - CROSS_COMPILE="$(TARGET_CROSS)" \ - ARCH="$(LINUX_KARCH)" \ - M="$(PKG_BUILD_DIR)" \ - EXTRA_CFLAGS="$(EXTRA_CFLAGS)" SoC="$(SOC)" \ - $(KERNEL_MAKE_FLAGS) \ - $(PKG_JOBS) \ - modules -endef - -$(eval $(call KernelPackage,qca-nss-dp)) diff --git a/qaa/nss/qca-nss-dp/patches/0001-edma_tx_rx-support-newer-kernels-time-stamping-API.patch b/qaa/nss/qca-nss-dp/patches/0001-edma_tx_rx-support-newer-kernels-time-stamping-API.patch deleted file mode 100644 index 15f6caa46..000000000 --- a/qaa/nss/qca-nss-dp/patches/0001-edma_tx_rx-support-newer-kernels-time-stamping-API.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 40979666b4371012405715ffa61ab5760fcdc6b3 Mon Sep 17 00:00:00 2001 -Message-Id: <40979666b4371012405715ffa61ab5760fcdc6b3.1620066716.git.baruch@tkos.co.il> -From: Baruch Siach -Date: Mon, 3 May 2021 20:07:36 +0300 -Subject: [PATCH 1/3] edma_tx_rx: support newer kernels time stamping API - ---- - hal/edma/edma_tx_rx.c | 11 +++++++++++ - 1 file changed, 11 insertions(+) - ---- a/hal/edma/edma_tx_rx.c -+++ b/hal/edma/edma_tx_rx.c -@@ -226,10 +226,16 @@ void nss_phy_tstamp_rx_buf(__attribute__ - * set to the correct PTP class value by calling ptp_classify_raw - * in drv->rxtstamp function. - */ -+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 6, 0)) - if (ndev && ndev->phydev && ndev->phydev->drv && - ndev->phydev->drv->rxtstamp) - if(ndev->phydev->drv->rxtstamp(ndev->phydev, skb, 0)) - return; -+#else -+ if (ndev && phy_has_rxtstamp(ndev->phydev)) -+ if (phy_rxtstamp(ndev->phydev, skb, 0)) -+ return; -+#endif - - netif_receive_skb(skb); - } -@@ -247,9 +253,14 @@ void nss_phy_tstamp_tx_buf(struct net_de - * set to the correct PTP class value by calling ptp_classify_raw - * in the drv->txtstamp function. - */ -+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 6, 0)) - if (ndev && ndev->phydev && ndev->phydev->drv && - ndev->phydev->drv->txtstamp) - ndev->phydev->drv->txtstamp(ndev->phydev, skb, 0); -+#else -+ if (ndev && phy_has_txtstamp(ndev->phydev)) -+ phy_rxtstamp(ndev->phydev, skb, 0); -+#endif - } - EXPORT_SYMBOL(nss_phy_tstamp_tx_buf); - diff --git a/qaa/nss/qca-nss-dp/patches/0002-nss_dp_main-make-phy-mode-code-compatible-with-newer.patch b/qaa/nss/qca-nss-dp/patches/0002-nss_dp_main-make-phy-mode-code-compatible-with-newer.patch deleted file mode 100644 index a3305dd32..000000000 --- a/qaa/nss/qca-nss-dp/patches/0002-nss_dp_main-make-phy-mode-code-compatible-with-newer.patch +++ /dev/null @@ -1,48 +0,0 @@ -From cef7873a2d77df13ee702d902ed4e06b2248904b Mon Sep 17 00:00:00 2001 -Message-Id: -In-Reply-To: <40979666b4371012405715ffa61ab5760fcdc6b3.1620066716.git.baruch@tkos.co.il> -References: <40979666b4371012405715ffa61ab5760fcdc6b3.1620066716.git.baruch@tkos.co.il> -From: Baruch Siach -Date: Mon, 3 May 2021 20:17:22 +0300 -Subject: [PATCH 2/3] nss_dp_main: make phy mode code compatible with newer - kernels - ---- - include/nss_dp_dev.h | 4 ++-- - nss_dp_main.c | 4 ++++ - 2 files changed, 6 insertions(+), 2 deletions(-) - ---- a/include/nss_dp_dev.h -+++ b/include/nss_dp_dev.h -@@ -25,7 +25,7 @@ - #include - #include - #include --#include -+#include - - #include "nss_dp_api_if.h" - #include "nss_dp_hal_if.h" -@@ -46,7 +46,7 @@ struct nss_dp_dev { - /* Phy related stuff */ - struct phy_device *phydev; /* Phy device */ - struct mii_bus *miibus; /* MII bus */ -- uint32_t phy_mii_type; /* RGMII/SGMII/QSGMII */ -+ phy_interface_t phy_mii_type; /* RGMII/SGMII/QSGMII */ - uint32_t phy_mdio_addr; /* Mdio address */ - bool link_poll; /* Link polling enable? */ - uint32_t forced_speed; /* Forced speed? */ ---- a/nss_dp_main.c -+++ b/nss_dp_main.c -@@ -463,7 +463,11 @@ static int32_t nss_dp_of_get_pdata(struc - hal_pdata->netdev = netdev; - hal_pdata->macid = dp_priv->macid; - -+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 5, 0)) - dp_priv->phy_mii_type = of_get_phy_mode(np); -+#else -+ of_get_phy_mode(np, &dp_priv->phy_mii_type); -+#endif - dp_priv->link_poll = of_property_read_bool(np, "qcom,link-poll"); - if (of_property_read_u32(np, "qcom,phy-mdio-addr", - &dp_priv->phy_mdio_addr) && dp_priv->link_poll) { diff --git a/qaa/nss/qca-nss-dp/patches/0003-Drop-_nocache-variants-of-ioremap.patch b/qaa/nss/qca-nss-dp/patches/0003-Drop-_nocache-variants-of-ioremap.patch deleted file mode 100644 index 3139d349b..000000000 --- a/qaa/nss/qca-nss-dp/patches/0003-Drop-_nocache-variants-of-ioremap.patch +++ /dev/null @@ -1,48 +0,0 @@ -From c8c52512ff48bee578901c381a42f027e79eadf9 Mon Sep 17 00:00:00 2001 -Message-Id: -In-Reply-To: <40979666b4371012405715ffa61ab5760fcdc6b3.1620066716.git.baruch@tkos.co.il> -References: <40979666b4371012405715ffa61ab5760fcdc6b3.1620066716.git.baruch@tkos.co.il> -From: Baruch Siach -Date: Mon, 3 May 2021 20:20:29 +0300 -Subject: [PATCH 3/3] Drop _nocache variants of ioremap() - -Recent kernels removed them. ---- - hal/edma/edma_data_plane.c | 2 +- - hal/gmac_hal_ops/qcom/qcom_if.c | 2 +- - hal/gmac_hal_ops/syn/xgmac/syn_if.c | 2 +- - 3 files changed, 3 insertions(+), 3 deletions(-) - ---- a/hal/edma/edma_data_plane.c -+++ b/hal/edma/edma_data_plane.c -@@ -797,7 +797,7 @@ int edma_init(void) - /* - * Remap register resource - */ -- edma_hw.reg_base = ioremap_nocache((edma_hw.reg_resource)->start, -+ edma_hw.reg_base = ioremap((edma_hw.reg_resource)->start, - resource_size(edma_hw.reg_resource)); - if (!edma_hw.reg_base) { - pr_warn("Unable to remap EDMA register memory.\n"); ---- a/hal/gmac_hal_ops/qcom/qcom_if.c -+++ b/hal/gmac_hal_ops/qcom/qcom_if.c -@@ -400,7 +400,7 @@ static void *qcom_init(struct gmac_hal_p - qhd->nghd.mac_id = gmacpdata->macid; - - /* Populate the mac base addresses */ -- qhd->nghd.mac_base = devm_ioremap_nocache(&dp_priv->pdev->dev, -+ qhd->nghd.mac_base = devm_ioremap(&dp_priv->pdev->dev, - res->start, resource_size(res)); - if (!qhd->nghd.mac_base) { - netdev_dbg(ndev, "ioremap fail.\n"); ---- a/hal/gmac_hal_ops/syn/xgmac/syn_if.c -+++ b/hal/gmac_hal_ops/syn/xgmac/syn_if.c -@@ -422,7 +422,7 @@ static void *syn_init(struct gmac_hal_pl - - /* Populate the mac base addresses */ - shd->nghd.mac_base = -- devm_ioremap_nocache(&dp_priv->pdev->dev, res->start, -+ devm_ioremap(&dp_priv->pdev->dev, res->start, - resource_size(res)); - if (!shd->nghd.mac_base) { - netdev_dbg(ndev, "ioremap fail.\n"); diff --git a/qaa/nss/qca-nss-dp/patches/0004-EDMA-Fix-NAPI-packet-counting.patch b/qaa/nss/qca-nss-dp/patches/0004-EDMA-Fix-NAPI-packet-counting.patch deleted file mode 100644 index eb57fe90a..000000000 --- a/qaa/nss/qca-nss-dp/patches/0004-EDMA-Fix-NAPI-packet-counting.patch +++ /dev/null @@ -1,31 +0,0 @@ -From d74920e2a7c413ef40eed72f9cf287cf6fbd5fb8 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Thu, 20 May 2021 14:56:46 +0200 -Subject: [PATCH 1/2] EDMA: Fix NAPI packet counting - -There is a bug in the NAPI packet counting that will -cause NAPI over budget warnings. - -Signed-off-by: Baruch Siach -Signed-off-by: Robert Marko ---- - hal/edma/edma_tx_rx.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/hal/edma/edma_tx_rx.c -+++ b/hal/edma/edma_tx_rx.c -@@ -458,12 +458,12 @@ int edma_napi(struct napi_struct *napi, - - for (i = 0; i < ehw->txcmpl_rings; i++) { - txcmpl_ring = &ehw->txcmpl_ring[i]; -- work_done += edma_clean_tx(ehw, txcmpl_ring); -+ edma_clean_tx(ehw, txcmpl_ring); - } - - for (i = 0; i < ehw->rxfill_rings; i++) { - rxfill_ring = &ehw->rxfill_ring[i]; -- work_done += edma_alloc_rx_buffer(ehw, rxfill_ring); -+ edma_alloc_rx_buffer(ehw, rxfill_ring); - } - - /* diff --git a/qaa/nss/qca-nss-dp/patches/0005-EDMA-Use-NAPI_POLL_WEIGHT-as-NAPI-weight.patch b/qaa/nss/qca-nss-dp/patches/0005-EDMA-Use-NAPI_POLL_WEIGHT-as-NAPI-weight.patch deleted file mode 100644 index f231c514a..000000000 --- a/qaa/nss/qca-nss-dp/patches/0005-EDMA-Use-NAPI_POLL_WEIGHT-as-NAPI-weight.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 44a30d94abcbb10aacc21db29be212518a6b1bf7 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Thu, 20 May 2021 14:57:46 +0200 -Subject: [PATCH] EDMA: Use NAPI_POLL_WEIGHT as NAPI weight - -Currently a weight of 100 is used by the EDMA, according -to upstream max of 64 should be used and that is used for -almost any driver. - -They also introduced NAPI_POLL_WEIGHT define which equals -to 64. - -So use NAPI_POLL_WEIGHT as the weight. - -Signed-off-by: Robert Marko ---- - hal/edma/edma_data_plane.c | 2 +- - hal/edma/edma_data_plane.h | 1 - - 2 files changed, 1 insertion(+), 2 deletions(-) - ---- a/hal/edma/edma_data_plane.c -+++ b/hal/edma/edma_data_plane.c -@@ -582,7 +582,7 @@ static int edma_register_netdevice(struc - */ - if (!edma_hw.napi_added) { - netif_napi_add(netdev, &edma_hw.napi, edma_napi, -- EDMA_NAPI_WORK); -+ NAPI_POLL_WEIGHT); - /* - * Register the interrupt handlers and enable interrupts - */ ---- a/hal/edma/edma_data_plane.h -+++ b/hal/edma/edma_data_plane.h -@@ -27,7 +27,6 @@ - #define EDMA_RX_PREHDR_SIZE (sizeof(struct edma_rx_preheader)) - #define EDMA_TX_PREHDR_SIZE (sizeof(struct edma_tx_preheader)) - #define EDMA_RING_SIZE 128 --#define EDMA_NAPI_WORK 100 - #define EDMA_START_GMACS NSS_DP_START_IFNUM - #define EDMA_MAX_GMACS NSS_DP_HAL_MAX_PORTS - #define EDMA_TX_PKT_MIN_SIZE 33 /* IPQ807x EDMA needs a minimum packet size of 33 bytes */ diff --git a/qaa/nss/qca-nss-dp/patches/0006-NSS-DP-fix-of_get_mac_address.patch b/qaa/nss/qca-nss-dp/patches/0006-NSS-DP-fix-of_get_mac_address.patch deleted file mode 100644 index d4965716d..000000000 --- a/qaa/nss/qca-nss-dp/patches/0006-NSS-DP-fix-of_get_mac_address.patch +++ /dev/null @@ -1,50 +0,0 @@ -From cadeb62a42296563141d6954eec58e34ef86778d Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Fri, 13 Aug 2021 20:12:08 +0200 -Subject: [PATCH] NSS-DP: fix of_get_mac_address() - -Recently OpenWrt backported the updated of_get_mac_address() -function which returns and error code instead. - -So, patch the SSDK to use it and fix the compilation error. - -Signed-off-by: Robert Marko ---- - nss_dp_main.c | 13 ++++--------- - 1 file changed, 4 insertions(+), 9 deletions(-) - -diff --git a/nss_dp_main.c b/nss_dp_main.c -index 5580b13..28df280 100644 ---- a/nss_dp_main.c -+++ b/nss_dp_main.c -@@ -434,9 +434,10 @@ static int32_t nss_dp_of_get_pdata(struct device_node *np, - struct net_device *netdev, - struct gmac_hal_platform_data *hal_pdata) - { -- uint8_t *maddr; -+ u8 maddr[ETH_ALEN]; - struct nss_dp_dev *dp_priv; - struct resource memres_devtree = {0}; -+ int ret; - - dp_priv = netdev_priv(netdev); - -@@ -475,14 +476,8 @@ static int32_t nss_dp_of_get_pdata(struct device_node *np, - of_property_read_u32(np, "qcom,forced-speed", &dp_priv->forced_speed); - of_property_read_u32(np, "qcom,forced-duplex", &dp_priv->forced_duplex); - -- maddr = (uint8_t *)of_get_mac_address(np); --#if (LINUX_VERSION_CODE > KERNEL_VERSION(5, 4, 0)) -- if (IS_ERR((void *)maddr)) { -- maddr = NULL; -- } --#endif -- -- if (maddr && is_valid_ether_addr(maddr)) { -+ ret = of_get_mac_address(np, maddr); -+ if (!ret && is_valid_ether_addr(maddr)) { - ether_addr_copy(netdev->dev_addr, maddr); - } else { - random_ether_addr(netdev->dev_addr); --- -2.31.1 diff --git a/qaa/nss/qca-nss-drv-64/Makefile b/qaa/nss/qca-nss-drv-64/Makefile deleted file mode 100644 index ac73475f7..000000000 --- a/qaa/nss/qca-nss-drv-64/Makefile +++ /dev/null @@ -1,121 +0,0 @@ -include $(TOPDIR)/rules.mk - -PKG_NAME:=qca-nss-drv-64 -PKG_RELEASE:=$(AUTORELEASE) - -PKG_SOURCE_URL:=https://source.codeaurora.org/quic/qsdk/oss/lklm/nss-drv -PKG_SOURCE_PROTO:=git -PKG_SOURCE_DATE:=2021-04-26 -PKG_SOURCE_VERSION:=1cf4bf81fd395f61648efeae78cdf1df60e954ff -PKG_MIRROR_HASH:=3dd84a548a530188021fd4dab54ca4e1eb9056ca77381b24f587365fc7c16f21 - -PKG_BUILD_PARALLEL:=1 - -include $(INCLUDE_DIR)/kernel.mk -include $(INCLUDE_DIR)/package.mk - -NSS_CLIENTS_DIR:=$(TOPDIR)/qca/src/qca-nss-clients - -define KernelPackage/qca-nss-drv-64 - SECTION:=kernel - CATEGORY:=Kernel modules - SUBMENU:=Network Devices - DEPENDS:=@(TARGET_ipq807x||TARGET_ipq60xx) +kmod-qca-nss-dp - TITLE:=Kernel driver for NSS (core driver) - FILES:=$(PKG_BUILD_DIR)/qca-nss-drv.ko - AUTOLOAD:=$(call AutoLoad,32,qca-nss-drv) -endef - -define KernelPackage/qca-nss-drv-64/install - $(INSTALL_DIR) $(1)/lib/debug - $(INSTALL_DIR) $(1)/etc/init.d - $(INSTALL_DIR) $(1)/etc/sysctl.d - $(INSTALL_DIR) $(1)/etc/hotplug.d/firmware - $(INSTALL_DIR) $(1)/etc/config - - $(INSTALL_BIN) ./files/qca-nss-drv.debug $(1)/lib/debug/qca-nss-drv - $(INSTALL_BIN) ./files/qca-nss-drv.init $(1)/etc/init.d/qca-nss-drv - $(INSTALL_BIN) ./files/qca-nss-drv.sysctl $(1)/etc/sysctl.d/qca-nss-drv.conf - $(INSTALL_BIN) ./files/qca-nss-drv.hotplug $(1)/etc/hotplug.d/firmware/10-qca-nss-fw - $(INSTALL_BIN) ./files/qca-nss-drv.conf $(1)/etc/config/nss - -endef - -define KernelPackage/qca-nss-drv-64/Description -This package contains a NSS driver for QCA chipset -endef - -define Build/InstallDev - mkdir -p $(1)/usr/include/qca-nss-drv - $(CP) $(PKG_BUILD_DIR)/exports/* $(1)/usr/include/qca-nss-drv/ -endef - -EXTRA_CFLAGS+= -I$(STAGING_DIR)/usr/include/qca-nss-gmac -I$(STAGING_DIR)/usr/include/qca-nss-dp -I$(STAGING_DIR)/usr/include/qca-ssdk - -ifneq (, $(findstring $(CONFIG_TARGET_BOARD), "ipq807x" "ipq60xx")) -EXTRA_CFLAGS+= -DNSS_MEM_PROFILE_MEDIUM -LOW_MEM_PROFILE_MAKE_OPTS=y -endif - -ifeq ($(CONFIG_KERNEL_SKB_FIXED_SIZE_2K),y) -EXTRA_CFLAGS+= -DNSS_SKB_FIXED_SIZE_2K -endif - -DRV_MAKE_OPTS:= -ifeq ($(LOW_MEM_PROFILE_MAKE_OPTS),y) -DRV_MAKE_OPTS+=NSS_DRV_C2C_ENABLE=n \ - NSS_DRV_CAPWAP_ENABLE=n \ - NSS_DRV_CLMAP_ENABLE=n \ - NSS_DRV_CRYPTO_ENABLE=n \ - NSS_DRV_DTLS_ENABLE=n \ - NSS_DRV_GRE_ENABLE=n \ - NSS_DRV_GRE_REDIR_ENABLE=n \ - NSS_DRV_GRE_TUNNEL_ENABLE=n \ - NSS_DRV_IGS_ENABLE=n \ - NSS_DRV_IPSEC_ENABLE=n \ - NSS_DRV_LAG_ENABLE=n \ - NSS_DRV_L2TP_ENABLE=n \ - NSS_DRV_MAPT_ENABLE=n \ - NSS_DRV_OAM_ENABLE=n \ - NSS_DRV_PPTP_ENABLE=n \ - NSS_DRV_PORTID_ENABLE=n \ - NSS_DRV_PVXLAN_ENABLE=n \ - NSS_DRV_QRFS_ENABLE=n \ - NSS_DRV_QVPN_ENABLE=n \ - NSS_DRV_RMNET_ENABLE=n \ - NSS_DRV_SHAPER_ENABLE=n \ - NSS_DRV_SJACK_ENABLE=n \ - NSS_DRV_TLS_ENABLE=n \ - NSS_DRV_TRUSTSEC_ENABLE=n \ - NSS_DRV_TSTAMP_ENABLE=n \ - NSS_DRV_TUN6RD_ENABLE=n \ - NSS_DRV_TUNIPIP6_ENABLE=n \ - NSS_DRV_VXLAN_ENABLE=n \ - NSS_DRV_MATCH_ENABLE=n \ - NSS_DRV_MIRROR_ENABLE=n -endif - -ifeq ($(CONFIG_TARGET_BOARD), "ipq807x") - SOC="ipq807x_64" -else ifeq ($(CONFIG_TARGET_BOARD), "ipq60xx") - SOC="ipq60xx_64" -endif - -define Build/Configure - $(LN) arch/nss_$(SOC).h $(PKG_BUILD_DIR)/exports/nss_arch.h - sed -i "s/define NSS_FW_VERSION_MAJOR.*/define NSS_FW_VERSION_MAJOR 11/" $(PKG_BUILD_DIR)/exports/nss_fw_version.h - sed -i "s/define NSS_FW_VERSION_MINOR.*/define NSS_FW_VERSION_MINOR 3/" $(PKG_BUILD_DIR)/exports/nss_fw_version.h -endef - -define Build/Compile - +$(MAKE) -C "$(LINUX_DIR)" $(strip $(DRV_MAKE_OPTS)) \ - CROSS_COMPILE="$(TARGET_CROSS)" \ - ARCH="$(LINUX_KARCH)" \ - M="$(PKG_BUILD_DIR)" \ - EXTRA_CFLAGS="$(EXTRA_CFLAGS)" SoC=$(SOC) \ - $(KERNEL_MAKE_FLAGS) \ - $(PKG_JOBS) \ - modules -endef - -$(eval $(call KernelPackage,qca-nss-drv-64)) diff --git a/qaa/nss/qca-nss-drv-64/files/qca-nss-drv.conf b/qaa/nss/qca-nss-drv-64/files/qca-nss-drv.conf deleted file mode 100644 index a8a1fbf40..000000000 --- a/qaa/nss/qca-nss-drv-64/files/qca-nss-drv.conf +++ /dev/null @@ -1,6 +0,0 @@ -config nss_firmware 'qca_nss_0' - -config nss_firmware 'qca_nss_1' - -config general - option enable_rps '1' diff --git a/qaa/nss/qca-nss-drv-64/files/qca-nss-drv.debug b/qaa/nss/qca-nss-drv-64/files/qca-nss-drv.debug deleted file mode 100644 index 5d435c3a7..000000000 --- a/qaa/nss/qca-nss-drv-64/files/qca-nss-drv.debug +++ /dev/null @@ -1,26 +0,0 @@ -#!/bin/sh /sbin/sysdebug -# -# Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. -# -# Permission to use, copy, modify, and/or distribute this software for any -# purpose with or without fee is hereby granted, provided that the above -# copyright notice and this permission notice appear in all copies. -# -# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -# - -log cat /sys/kernel/debug/qca-nss-drv/stats/pppoe -log cat /sys/kernel/debug/qca-nss-drv/stats/n2h -log cat /sys/kernel/debug/qca-nss-drv/stats/ipv6 -log cat /sys/kernel/debug/qca-nss-drv/stats/ipv4 -log cat /sys/kernel/debug/qca-nss-drv/stats/gmac -log cat /sys/kernel/debug/qca-nss-drv/stats/drv -log cat /sys/kernel/debug/qca-nss-drv/stats/wifi -log cat /sys/kernel/debug/qca-nss-drv/stats/wifi_if -log cat /sys/kernel/debug/qca-nss-drv/stats/eth_rx diff --git a/qaa/nss/qca-nss-drv-64/files/qca-nss-drv.hotplug b/qaa/nss/qca-nss-drv-64/files/qca-nss-drv.hotplug deleted file mode 100644 index 1e4813838..000000000 --- a/qaa/nss/qca-nss-drv-64/files/qca-nss-drv.hotplug +++ /dev/null @@ -1,70 +0,0 @@ -#!/bin/sh -# -# Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. -# -# Permission to use, copy, modify, and/or distribute this software for any -# purpose with or without fee is hereby granted, provided that the above -# copyright notice and this permission notice appear in all copies. -# -# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -# - -KERNEL=`uname -r` -case "${KERNEL}" in - 3.4*) - select_or_load=load_nss_fw - ;; - *) - select_or_load=select_nss_fw - ;; -esac - -load_nss_fw () { - ls -l $1 | awk ' { print $9,$5 } '> /dev/console - echo 1 > /sys/class/firmware/$DEVICENAME/loading - cat $1 > /sys/class/firmware/$DEVICENAME/data - echo 0 > /sys/class/firmware/$DEVICENAME/loading -} - -select_nss_fw () { - rm -f /lib/firmware/$DEVICENAME - ln -s $1 /lib/firmware/$DEVICENAME - ls -l /lib/firmware/$DEVICENAME | awk ' { print $9,$5 } '> /dev/console -} - -[ "$ACTION" != "add" ] && exit - -# dev name for UCI, since it doesn't let you use . or - -SDEVNAME=$(echo ${DEVICENAME} | sed s/[.-]/_/g) - -SELECTED_FW=$(uci get nss.${SDEVNAME}.firmware 2>/dev/null) -[ -e "${SELECTED_FW}" ] && { - $select_or_load ${SELECTED_FW} - exit -} - -case $DEVICENAME in - qca-nss0* | qca-nss.0*) - if [ -e /lib/firmware/qca-nss0-enterprise.bin ] ; then - $select_or_load /lib/firmware/qca-nss0-enterprise.bin - else - $select_or_load /lib/firmware/qca-nss0-retail.bin - fi - exit - ;; - qca-nss1* | qca-nss.1*) - if [ -e /lib/firmware/qca-nss1-enterprise.bin ] ; then - $select_or_load /lib/firmware/qca-nss1-enterprise.bin - else - $select_or_load /lib/firmware/qca-nss1-retail.bin - fi - exit - ;; -esac - diff --git a/qaa/nss/qca-nss-drv-64/files/qca-nss-drv.init b/qaa/nss/qca-nss-drv-64/files/qca-nss-drv.init deleted file mode 100644 index de12cb6d1..000000000 --- a/qaa/nss/qca-nss-drv-64/files/qca-nss-drv.init +++ /dev/null @@ -1,50 +0,0 @@ -#!/bin/sh /etc/rc.common -# -# Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. -# -# Permission to use, copy, modify, and/or distribute this software for any -# purpose with or without fee is hereby granted, provided that the above -# copyright notice and this permission notice appear in all copies. -# -# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -# - -START=70 - -enable_rps() { - irq_nss_rps=`grep nss_queue1 /proc/interrupts | cut -d ':' -f 1 | tr -d ' '` - for entry in $irq_nss_rps - do - echo 2 > /proc/irq/$entry/smp_affinity - done - - irq_nss_rps=`grep nss_queue2 /proc/interrupts | cut -d ':' -f 1 | tr -d ' '` - for entry in $irq_nss_rps - do - echo 4 > /proc/irq/$entry/smp_affinity - done - - irq_nss_rps=`grep nss_queue3 /proc/interrupts | cut -d ':' -f 1 | tr -d ' '` - for entry in $irq_nss_rps - do - echo 8 > /proc/irq/$entry/smp_affinity - done - - # Enable NSS RPS - sysctl -w dev.nss.rps.enable=1 >/dev/null 2>/dev/null - -} - - -start() { - local rps_enabled="$(uci_get nss @general[0] enable_rps)" - if [ "$rps_enabled" -eq 1 ]; then - enable_rps - fi -} diff --git a/qaa/nss/qca-nss-drv-64/files/qca-nss-drv.sysctl b/qaa/nss/qca-nss-drv-64/files/qca-nss-drv.sysctl deleted file mode 100644 index fc36c33eb..000000000 --- a/qaa/nss/qca-nss-drv-64/files/qca-nss-drv.sysctl +++ /dev/null @@ -1,4 +0,0 @@ -# Default Number of connection configuration -dev.nss.ipv4cfg.ipv4_conn=4096 -dev.nss.ipv6cfg.ipv6_conn=4096 - diff --git a/qaa/nss/qca-nss-drv-64/patches/0001-core-add-5.10-kernel-to-version-check.patch b/qaa/nss/qca-nss-drv-64/patches/0001-core-add-5.10-kernel-to-version-check.patch deleted file mode 100644 index 3fea9b5ce..000000000 --- a/qaa/nss/qca-nss-drv-64/patches/0001-core-add-5.10-kernel-to-version-check.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 3885c752e12f74cad6c97888b797e5903ad1930d Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Thu, 13 May 2021 23:22:38 +0200 -Subject: [PATCH] core: add 5.10 kernel to version check - -NSS DRV has a kernel version check, so simply add -5.10 as supported. - -Signed-off-by: Robert Marko ---- - nss_core.c | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - ---- a/nss_core.c -+++ b/nss_core.c -@@ -52,7 +52,8 @@ - (((LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0)))) || \ - (((LINUX_VERSION_CODE >= KERNEL_VERSION(3, 18, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 19, 0)))) || \ - (((LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(4, 5, 0)))) || \ --(((LINUX_VERSION_CODE >= KERNEL_VERSION(5, 4, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 5, 0)))))) -+(((LINUX_VERSION_CODE >= KERNEL_VERSION(5, 4, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 5, 0)))) || \ -+(((LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 11, 0)))))) - #error "Check skb recycle code in this file to match Linux version" - #endif - diff --git a/qaa/nss/qca-nss-drv-64/patches/0002-nss-drv-replace-ioremap_nocache-with-ioremap.patch b/qaa/nss/qca-nss-drv-64/patches/0002-nss-drv-replace-ioremap_nocache-with-ioremap.patch deleted file mode 100644 index 77155750c..000000000 --- a/qaa/nss/qca-nss-drv-64/patches/0002-nss-drv-replace-ioremap_nocache-with-ioremap.patch +++ /dev/null @@ -1,164 +0,0 @@ -From b5e2a7167ca3df9fce34f0d7c05468d4f5597275 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Thu, 13 May 2021 23:33:18 +0200 -Subject: [PATCH] nss-drv: replace ioremap_nocache() with ioremap() - -ioremap_nocache() does not exist anymore. - -Signed-off-by: Robert Marko ---- - nss_hal/ipq50xx/nss_hal_pvt.c | 6 +++--- - nss_hal/ipq60xx/nss_hal_pvt.c | 8 ++++---- - nss_hal/ipq806x/nss_hal_pvt.c | 4 ++-- - nss_hal/ipq807x/nss_hal_pvt.c | 6 +++--- - nss_hal/nss_hal.c | 4 ++-- - nss_meminfo.c | 2 +- - nss_ppe.c | 2 +- - 7 files changed, 16 insertions(+), 16 deletions(-) - ---- a/nss_hal/ipq50xx/nss_hal_pvt.c -+++ b/nss_hal/ipq50xx/nss_hal_pvt.c -@@ -184,13 +184,13 @@ static struct nss_platform_data *__nss_h - npd->nphys = res_nphys.start; - npd->qgic_phys = res_qgic_phys.start; - -- npd->nmap = ioremap_nocache(npd->nphys, resource_size(&res_nphys)); -+ npd->nmap = ioremap(npd->nphys, resource_size(&res_nphys)); - if (!npd->nmap) { - nss_info_always("%px: nss%d: ioremap() fail for nphys\n", nss_ctx, nss_ctx->id); - goto out; - } - -- npd->qgic_map = ioremap_nocache(npd->qgic_phys, resource_size(&res_qgic_phys)); -+ npd->qgic_map = ioremap(npd->qgic_phys, resource_size(&res_qgic_phys)); - if (!npd->qgic_map) { - nss_info_always("%px: nss%d: ioremap() fail for qgic map\n", nss_ctx, nss_ctx->id); - goto out; -@@ -348,7 +348,7 @@ static int __nss_hal_common_reset(struct - - of_node_put(cmn); - -- nss_misc_reset = ioremap_nocache(res_nss_misc_reset.start, resource_size(&res_nss_misc_reset)); -+ nss_misc_reset = ioremap(res_nss_misc_reset.start, resource_size(&res_nss_misc_reset)); - if (!nss_misc_reset) { - pr_err("%px: ioremap fail for nss_misc_reset\n", nss_dev); - return -EFAULT; ---- a/nss_hal/ipq60xx/nss_hal_pvt.c -+++ b/nss_hal/ipq60xx/nss_hal_pvt.c -@@ -207,13 +207,13 @@ static struct nss_platform_data *__nss_h - npd->nphys = res_nphys.start; - npd->qgic_phys = res_qgic_phys.start; - -- npd->nmap = ioremap_nocache(npd->nphys, resource_size(&res_nphys)); -+ npd->nmap = ioremap(npd->nphys, resource_size(&res_nphys)); - if (!npd->nmap) { - nss_info_always("%px: nss%d: ioremap() fail for nphys\n", nss_ctx, nss_ctx->id); - goto out; - } - -- npd->qgic_map = ioremap_nocache(npd->qgic_phys, resource_size(&res_qgic_phys)); -+ npd->qgic_map = ioremap(npd->qgic_phys, resource_size(&res_qgic_phys)); - if (!npd->qgic_map) { - nss_info_always("%px: nss%d: ioremap() fail for qgic map\n", nss_ctx, nss_ctx->id); - goto out; -@@ -433,13 +433,13 @@ static int __nss_hal_common_reset(struct - - of_node_put(cmn); - -- nss_misc_reset = ioremap_nocache(res_nss_misc_reset.start, resource_size(&res_nss_misc_reset)); -+ nss_misc_reset = ioremap(res_nss_misc_reset.start, resource_size(&res_nss_misc_reset)); - if (!nss_misc_reset) { - pr_err("%px: ioremap fail for nss_misc_reset\n", nss_dev); - return -EFAULT; - } - -- nss_misc_reset_flag = ioremap_nocache(res_nss_misc_reset_flag.start, resource_size(&res_nss_misc_reset_flag)); -+ nss_misc_reset_flag = ioremap(res_nss_misc_reset_flag.start, resource_size(&res_nss_misc_reset_flag)); - if (!nss_misc_reset_flag) { - pr_err("%px: ioremap fail for nss_misc_reset_flag\n", nss_dev); - return -EFAULT; ---- a/nss_hal/ipq806x/nss_hal_pvt.c -+++ b/nss_hal/ipq806x/nss_hal_pvt.c -@@ -458,7 +458,7 @@ static struct nss_platform_data *__nss_h - npd->nphys = res_nphys.start; - npd->vphys = res_vphys.start; - -- npd->nmap = ioremap_nocache(npd->nphys, resource_size(&res_nphys)); -+ npd->nmap = ioremap(npd->nphys, resource_size(&res_nphys)); - if (!npd->nmap) { - nss_info_always("%px: nss%d: ioremap() fail for nphys\n", nss_ctx, nss_ctx->id); - goto out; -@@ -711,7 +711,7 @@ static int __nss_hal_common_reset(struct - } - of_node_put(cmn); - -- fpb_base = ioremap_nocache(res_nss_fpb_base.start, resource_size(&res_nss_fpb_base)); -+ fpb_base = ioremap(res_nss_fpb_base.start, resource_size(&res_nss_fpb_base)); - if (!fpb_base) { - pr_err("%px: ioremap fail for nss_fpb_base\n", nss_dev); - return -EFAULT; ---- a/nss_hal/ipq807x/nss_hal_pvt.c -+++ b/nss_hal/ipq807x/nss_hal_pvt.c -@@ -234,7 +234,7 @@ static struct nss_platform_data *__nss_h - npd->vphys = res_vphys.start; - npd->qgic_phys = res_qgic_phys.start; - -- npd->nmap = ioremap_nocache(npd->nphys, resource_size(&res_nphys)); -+ npd->nmap = ioremap(npd->nphys, resource_size(&res_nphys)); - if (!npd->nmap) { - nss_info_always("%px: nss%d: ioremap() fail for nphys\n", nss_ctx, nss_ctx->id); - goto out; -@@ -247,7 +247,7 @@ static struct nss_platform_data *__nss_h - goto out; - } - -- npd->qgic_map = ioremap_nocache(npd->qgic_phys, resource_size(&res_qgic_phys)); -+ npd->qgic_map = ioremap(npd->qgic_phys, resource_size(&res_qgic_phys)); - if (!npd->qgic_map) { - nss_info_always("%px: nss%d: ioremap() fail for qgic map\n", nss_ctx, nss_ctx->id); - goto out; -@@ -467,7 +467,7 @@ static int __nss_hal_common_reset(struct - } - of_node_put(cmn); - -- nss_misc_reset = ioremap_nocache(res_nss_misc_reset.start, resource_size(&res_nss_misc_reset)); -+ nss_misc_reset = ioremap(res_nss_misc_reset.start, resource_size(&res_nss_misc_reset)); - if (!nss_misc_reset) { - pr_err("%px: ioremap fail for nss_misc_reset\n", nss_dev); - return -EFAULT; ---- a/nss_hal/nss_hal.c -+++ b/nss_hal/nss_hal.c -@@ -78,9 +78,9 @@ int nss_hal_firmware_load(struct nss_ctx - return rc; - } - -- load_mem = ioremap_nocache(npd->load_addr, nss_fw->size); -+ load_mem = ioremap(npd->load_addr, nss_fw->size); - if (!load_mem) { -- nss_info_always("%px: ioremap_nocache failed: %x", nss_ctx, npd->load_addr); -+ nss_info_always("%px: ioremap failed: %x", nss_ctx, npd->load_addr); - release_firmware(nss_fw); - return rc; - } ---- a/nss_meminfo.c -+++ b/nss_meminfo.c -@@ -728,7 +728,7 @@ bool nss_meminfo_init(struct nss_ctx_ins - /* - * meminfo_start is the label where the start address of meminfo map is stored. - */ -- meminfo_start = (uint32_t *)ioremap_nocache(nss_ctx->load + NSS_MEMINFO_MAP_START_OFFSET, -+ meminfo_start = (uint32_t *)ioremap(nss_ctx->load + NSS_MEMINFO_MAP_START_OFFSET, - NSS_MEMINFO_RESERVE_AREA_SIZE); - if (!meminfo_start) { - nss_info_always("%px: cannot remap meminfo start\n", nss_ctx); ---- a/nss_ppe.c -+++ b/nss_ppe.c -@@ -357,7 +357,7 @@ void nss_ppe_init(void) - /* - * Get the PPE base address - */ -- ppe_pvt.ppe_base = ioremap_nocache(PPE_BASE_ADDR, PPE_REG_SIZE); -+ ppe_pvt.ppe_base = ioremap(PPE_BASE_ADDR, PPE_REG_SIZE); - if (!ppe_pvt.ppe_base) { - nss_warning("DRV can't get PPE base address\n"); - return; diff --git a/qaa/nss/qca-nss-drv-64/patches/0003-DMA-Fix-NULL-pointer-exceptions.patch b/qaa/nss/qca-nss-drv-64/patches/0003-DMA-Fix-NULL-pointer-exceptions.patch deleted file mode 100644 index 0c13a7887..000000000 --- a/qaa/nss/qca-nss-drv-64/patches/0003-DMA-Fix-NULL-pointer-exceptions.patch +++ /dev/null @@ -1,49 +0,0 @@ -From 62e457f262aaa0db7113ad3ccbcb7ae49d4d7ea8 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Tue, 8 Jun 2021 23:24:43 +0200 -Subject: [PATCH] DMA: Fix NULL pointer exceptions - -There are multiple instances that pass NULL instead -of device to DMA functions. -That is incorrect and will cause kernel NULL pointer -exceptions. - -So, simply pass the device structure pointers. - -Signed-off-by: Robert Marko ---- - nss_core.c | 2 +- - nss_coredump.c | 4 ++-- - 2 files changed, 3 insertions(+), 3 deletions(-) - ---- a/nss_core.c -+++ b/nss_core.c -@@ -1617,7 +1617,7 @@ static int32_t nss_core_handle_cause_que - * - */ - if (unlikely((buffer_type == N2H_BUFFER_CRYPTO_RESP))) { -- dma_unmap_single(NULL, (desc->buffer + desc->payload_offs), desc->payload_len, DMA_FROM_DEVICE); -+ dma_unmap_single(nss_ctx->dev, (desc->buffer + desc->payload_offs), desc->payload_len, DMA_FROM_DEVICE); - goto consume; - } - ---- a/nss_coredump.c -+++ b/nss_coredump.c -@@ -154,7 +154,7 @@ void nss_fw_coredump_notify(struct nss_c - dma_addr = nss_own->meminfo_ctx.logbuffer_dma; - } - -- dma_sync_single_for_cpu(NULL, dma_addr, sizeof(struct nss_log_descriptor), DMA_FROM_DEVICE); -+ dma_sync_single_for_cpu(nss_own->dev, dma_addr, sizeof(struct nss_log_descriptor), DMA_FROM_DEVICE); - - /* - * If the current entry is smaller than or equal to the number of NSS_LOG_COREDUMP_LINE_NUM, -@@ -181,7 +181,7 @@ void nss_fw_coredump_notify(struct nss_c - - offset = (index * sizeof(struct nss_log_entry)) - + offsetof(struct nss_log_descriptor, log_ring_buffer); -- dma_sync_single_for_cpu(NULL, dma_addr + offset, -+ dma_sync_single_for_cpu(nss_own->dev, dma_addr + offset, - sizeof(struct nss_log_entry), DMA_FROM_DEVICE); - nss_info_always("%px: %s\n", nss_own, nle_print->message); - nle_print++; diff --git a/qaa/nss/qca-nss-drv-64/patches/999-treewide-hack-support-for-mismatched-firmware.patch b/qaa/nss/qca-nss-drv-64/patches/999-treewide-hack-support-for-mismatched-firmware.patch deleted file mode 100644 index 46025b823..000000000 --- a/qaa/nss/qca-nss-drv-64/patches/999-treewide-hack-support-for-mismatched-firmware.patch +++ /dev/null @@ -1,344 +0,0 @@ -From d0bffc800a50305315a0d7cf37140291ef5b1b61 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Thu, 27 May 2021 03:52:47 +0200 -Subject: [PATCH] treewide: hack support for mismatched firmware - -Make new qsdk feature configurable to support old half compatible -firmware. - -Signed-off-by: Ansuel Smith ---- - exports/nss_fw_version.h | 11 +++++++++++ - exports/nss_ipv4.h | 8 ++++++++ - exports/nss_ipv6.h | 7 +++++++ - exports/nss_wifi_vdev.h | 14 ++++++++++++++ - exports/nss_wifili_if.h | 8 ++++++++ - nss_ipv4_stats.c | 2 ++ - nss_ipv4_strings.c | 2 ++ - nss_ipv6_stats.c | 2 ++ - nss_ipv6_strings.c | 2 ++ - 9 files changed, 56 insertions(+) - create mode 100644 exports/nss_fw_version.h - -diff --git a/exports/nss_fw_version.h b/exports/nss_fw_version.h -new file mode 100644 -index 0000000..895d523 ---- /dev/null -+++ b/exports/nss_fw_version.h -@@ -0,0 +1,11 @@ -+#ifndef __NSS_FW_VERSION_H -+#define __NSS_FW_VERSION_H -+ -+#define NSS_FW_VERSION_MAJOR 11 -+#define NSS_FW_VERSION_MINOR 4 -+ -+#define NSS_FW_VERSION(a,b) (((a) << 8) + (b)) -+ -+#define NSS_FW_VERSION_CODE NSS_FW_VERSION(NSS_FW_VERSION_MAJOR, NSS_FW_VERSION_MINOR) -+ -+#endif /* __NSS_FW_VERSION_H */ -\ No newline at end of file -diff --git a/exports/nss_ipv4.h b/exports/nss_ipv4.h -index ee3a552..25c4d82 100644 ---- a/exports/nss_ipv4.h -+++ b/exports/nss_ipv4.h -@@ -26,6 +26,8 @@ - #include "nss_stats_public.h" - #endif - -+#include "nss_fw_version.h" -+ - /** - * @addtogroup nss_ipv4_subsystem - * @{ -@@ -216,12 +218,14 @@ enum nss_ipv4_stats_types { - /**< Number of IPv4 multicast connection destroy requests that missed the cache. */ - NSS_IPV4_STATS_MC_CONNECTION_FLUSHES, - /**< Number of IPv4 multicast connection flushes. */ -+#if (NSS_FW_VERSION_CODE > NSS_FW_VERSION(11,3)) - NSS_IPV4_STATS_CONNECTION_CREATE_INVALID_MIRROR_IFNUM, - /**< Number of IPv4 mirror connection requests with an invalid interface number. */ - NSS_IPV4_STATS_CONNECTION_CREATE_INVALID_MIRROR_IFTYPE, - /**< Number of IPv4 mirror connection requests with an invalid interface type. */ - NSS_IPV4_STATS_MIRROR_FAILURES, - /**< Number of IPv4 mirror failures. */ -+#endif - NSS_IPV4_STATS_MAX, - /**< Maximum message type. */ - }; -@@ -609,8 +613,10 @@ struct nss_ipv4_rule_create_msg { - /**< Ingress shaping related accleration parameters. */ - struct nss_ipv4_identifier_rule identifier; - /**< Rule for adding identifier. */ -+#if (NSS_FW_VERSION_CODE > NSS_FW_VERSION(11,3)) - struct nss_ipv4_mirror_rule mirror_rule; - /**< Mirror rule parameter. */ -+#endif - }; - - /** -@@ -955,6 +961,7 @@ struct nss_ipv4_node_sync { - uint32_t ipv4_mc_connection_flushes; - /**< Number of multicast connection flushes. */ - -+#if (NSS_FW_VERSION_CODE > NSS_FW_VERSION(11,3)) - uint32_t ipv4_connection_create_invalid_mirror_ifnum; - /**< Number of create request failed with an invalid mirror interface number. */ - -@@ -963,6 +970,7 @@ struct nss_ipv4_node_sync { - - uint32_t ipv4_mirror_failures; - /**< Mirror packet failed. */ -+#endif - - uint32_t exception_events[NSS_IPV4_EXCEPTION_EVENT_MAX]; - /**< Number of exception events. */ -diff --git a/exports/nss_ipv6.h b/exports/nss_ipv6.h -index 930e74c..a21f939 100644 ---- a/exports/nss_ipv6.h -+++ b/exports/nss_ipv6.h -@@ -195,6 +195,8 @@ enum nss_ipv6_stats_types { - /**< Number of IPv6 multicast connection destroy requests that missed the cache. */ - NSS_IPV6_STATS_MC_CONNECTION_FLUSHES, - /**< Number of IPv6 multicast connection flushes. */ -+ -+#if (NSS_FW_VERSION_CODE > NSS_FW_VERSION(11,3)) - NSS_IPV6_STATS_CONNECTION_CREATE_INVALID_MIRROR_IFNUM, - /**< Number of IPv6 mirror connection requests with an invalid interface number. */ - NSS_IPV6_STATS_CONNECTION_CREATE_INVALID_MIRROR_IFTYPE, -@@ -202,6 +204,7 @@ enum nss_ipv6_stats_types { - - NSS_IPV6_STATS_MIRROR_FAILURES, - /**< Number of IPv6 mirror failures. */ -+#endif - - NSS_IPV6_STATS_MAX, - /**< Maximum message type. */ -@@ -702,8 +705,10 @@ struct nss_ipv6_rule_create_msg { - /**< Ingress shaping related accleration parameters. */ - struct nss_ipv6_identifier_rule identifier; - /**< Rule for adding identifier. */ -+#if (NSS_FW_VERSION_CODE > NSS_FW_VERSION(11,3)) - struct nss_ipv6_mirror_rule mirror_rule; - /**< Mirror rule parameter. */ -+#endif - }; - - /** -@@ -950,6 +955,7 @@ struct nss_ipv6_node_sync { - uint32_t ipv6_mc_connection_flushes; - /**< Number of multicast connection flushes. */ - -+#if (NSS_FW_VERSION_CODE > NSS_FW_VERSION(11,3)) - uint32_t ipv6_connection_create_invalid_mirror_ifnum; - /**< Number of create request failed with an invalid mirror interface number. */ - -@@ -958,6 +964,7 @@ struct nss_ipv6_node_sync { - - uint32_t ipv6_mirror_failures; - /**< Mirror packet failed. */ -+#endif - - uint32_t exception_events[NSS_IPV6_EXCEPTION_EVENT_MAX]; - /**< Number of exception events. */ -diff --git a/exports/nss_wifi_vdev.h b/exports/nss_wifi_vdev.h -index 1b52f66..da91b56 100644 ---- a/exports/nss_wifi_vdev.h -+++ b/exports/nss_wifi_vdev.h -@@ -74,8 +74,10 @@ enum nss_wifi_vdev_msg_types { - NSS_WIFI_VDEV_INTERFACE_RECOVERY_RESET_MSG, - NSS_WIFI_VDEV_INTERFACE_RECOVERY_RECONF_MSG, - NSS_WIFI_VDEV_SET_GROUP_KEY, -+#if (NSS_FW_VERSION_CODE > NSS_FW_VERSION(11,3)) - NSS_WIFI_VDEV_HMMC_MEMBER_ADD_MSG, - NSS_WIFI_VDEV_HMMC_MEMBER_DEL_MSG, -+#endif - NSS_WIFI_VDEV_MAX_MSG - }; - -@@ -130,6 +132,7 @@ enum nss_wifi_vdev_err_types { - NSS_WIFI_VDEV_VLAN_MODE_CONFIG_FAIL, - NSS_WIFI_VDEV_RECOVERY_RESET_FAIL, - NSS_WIFI_VDEV_RECOVERY_RECONF_FAIL, -+#if (NSS_FW_VERSION_CODE > NSS_FW_VERSION(11,3)) - NSS_WIFI_VDEV_CONFIG_GROUP_KEY_FAIL, - NSS_WIFI_VDEV_MULTIPASS_NOT_ENABLED, - NSS_WIFI_VDEV_ALLOC_VLAN_MAP_FAILED, -@@ -139,6 +142,7 @@ enum nss_wifi_vdev_err_types { - NSS_WIFI_VDEV_PPE_PORT_DESTROY_FAIL, - NSS_WIFI_VDEV_PPE_VSI_ASSIGN_FAIL, - NSS_WIFI_VDEV_PPE_VSI_UNASSIGN_FAIL, -+#endif - NSS_WIFI_VDEV_EINV_MAX_CFG - }; - -@@ -161,11 +165,13 @@ enum nss_wifi_vdev_ext_data_pkt_type { - NSS_WIFI_VDEV_EXT_TX_COMPL_PKT_TYPE = 11, /**< Tx completion. */ - NSS_WIFI_VDEV_EXT_DATA_PKT_TYPE_WDS_LEARN = 12, /**< WDS source port learning command. */ - NSS_WIFI_VDEV_EXT_DATA_PPDU_INFO = 13, /**< PPDU metadata information. */ -+#if (NSS_FW_VERSION_CODE > NSS_FW_VERSION(11,3)) - NSS_WIFI_VDEV_EXT_DATA_PKT_TYPE_MCBC_RX = 14, /**< Multicast/broadcast packet received. */ - NSS_WIFI_VDEV_MESH_EXT_DATA_PKT_TYPE_RX_SPL_PACKET = 15, - /**< Mesh link VAP special packet. */ - NSS_WIFI_VDEV_MESH_EXT_DATA_PKT_TYPE_RX_MCAST_EXC = 16, - /**< Mesh link VAP multicast packet. */ -+#endif - NSS_WIFI_VDEV_EXT_DATA_PKT_TYPE_MAX - }; - -@@ -201,9 +207,11 @@ enum nss_wifi_vdev_cmd { - NSS_WIFI_VDEV_ENABLE_IGMP_ME_CMD, /**< Configuration to set IGMP multicast enhancement on VAP. */ - NSS_WIFI_VDEV_CFG_WDS_BACKHAUL_CMD, - /**< Configuration to set WDS backhaul extension on VAP. */ -+#if (NSS_FW_VERSION_CODE > NSS_FW_VERSION(11,3)) - NSS_WIFI_VDEV_CFG_MCBC_EXC_TO_HOST_CMD, /**< Configuration to set multicast/broadcast exception to host on VAP. */ - NSS_WIFI_VDEV_CFG_PEER_AUTHORIZE_CMD, - /**< Configuration to enable peer authorization on VAP. */ -+#endif - NSS_WIFI_VDEV_MAX_CMD - }; - -@@ -271,7 +279,9 @@ struct nss_wifi_vdev_config_msg { - uint8_t is_nss_qwrap_en; /**< VAP is configured for NSS firmware QWRAP logic. */ - uint8_t tx_per_pkt_vdev_id_check; /**< Transmit per-packet virtual device ID check. */ - uint8_t align_pad; /**< Reserved field. */ -+#if (NSS_FW_VERSION_CODE > NSS_FW_VERSION(11,3)) - uint32_t vap_ext_mode; /**< Different VAP extended modes. */ -+#endif - }; - - /** -@@ -1037,8 +1047,10 @@ struct nss_wifi_vdev_stats_sync_msg { - uint32_t rx_mcast_bytes; /**< Receive multicast bytes count. */ - uint32_t rx_decrypt_err; /**< Receive decryption error */ - uint32_t rx_mic_err; /**< Receive MIC error */ -+#if (NSS_FW_VERSION_CODE > NSS_FW_VERSION(11,3)) - uint32_t mcbc_exc_host_fail_cnt; - /**< Number of multicast/broadcast packets failed to send to host through exception path. */ -+#endif - }; - - /** -@@ -1070,6 +1082,7 @@ struct nss_wifi_vdev_msg { - /**< Updates a snooplist group member. */ - struct nss_wifi_vdev_me_snptbl_deny_grp_add_msg vdev_deny_member_add; - /**< Add a snooplist member to the deny list. */ -+#if (NSS_FW_VERSION_CODE > NSS_FW_VERSION(11,3)) - struct nss_wifi_vdev_me_hmmc_add_msg vdev_hmmc_member_add; - /**< Adds a new member into the HMMC list. */ - struct nss_wifi_vdev_me_hmmc_del_msg vdev_hmmc_member_del; -@@ -1078,6 +1091,7 @@ struct nss_wifi_vdev_msg { - /**< Adds a new member into the deny list. */ - struct nss_wifi_vdev_me_deny_ip_del_msg vdev_deny_list_member_del; - /**< Delete a member from the deny list. */ -+#endif - struct nss_wifi_vdev_txmsg vdev_txmsgext; - /**< Transmits special data. */ - struct nss_wifi_vdev_vow_dbg_cfg_msg vdev_vow_dbg_cfg; -diff --git a/exports/nss_wifili_if.h b/exports/nss_wifili_if.h -index fce20fd..1f26d67 100644 ---- a/exports/nss_wifili_if.h -+++ b/exports/nss_wifili_if.h -@@ -62,8 +62,12 @@ - /**< Maximum number of bandwidth supported. */ - #define NSS_WIFILI_REPT_MU_MIMO 1 - #define NSS_WIFILI_REPT_MU_OFDMA_MIMO 3 -+#if (NSS_FW_VERSION_CODE > NSS_FW_VERSION(11,3)) -+#define NSS_WIFILI_MAX_RESERVED_TYPE 3 -+#else - #define NSS_WIFILI_MAX_RESERVED_TYPE 2 - /**< Maximum reserved type. */ -+#endif - #define NSS_WIFILI_SOC_PER_PACKET_METADATA_SIZE 60 - /**< Metadata area total size. */ - #define NSS_WIFILI_MEC_PEER_ID 0xDEAD -@@ -1333,7 +1337,9 @@ struct nss_wifili_rx_err { - struct nss_wifili_rx_ctrl_stats { - struct nss_wifili_rx_err err; /**< Rx peer errors. */ - uint32_t multipass_rx_pkt_drop; /**< Total number of multipass packets without a VLAN header. */ -+#if (NSS_FW_VERSION_CODE > NSS_FW_VERSION(11,3)) - uint32_t peer_unauth_rx_pkt_drop; /**< Number of receive packets dropped due to an authorized peer. */ -+#endif - uint32_t reserved_type[NSS_WIFILI_MAX_RESERVED_TYPE]; /**< Reserved type for future use. */ - uint32_t non_amsdu_cnt; /**< Number of MSDUs with no MSDU level aggregation. */ - uint32_t amsdu_cnt; /**< Number of MSDUs part of AMSDU. */ -@@ -1810,10 +1816,12 @@ struct nss_wifili_msg { - /**< Peer four-address event message. */ - struct nss_wifili_dbdc_repeater_loop_detection_msg wdrldm; - /**< Wifili DBDC repeater loop detection message. */ -+#if (NSS_FW_VERSION_CODE > NSS_FW_VERSION(11,3)) - struct nss_wifili_peer_update_auth_flag peer_auth; - /**< Peer authentication flag message. */ - struct nss_wifili_mesh_capability_info cap_info; - /**< Mesh capability flag. */ -+#endif - } msg; /**< Message payload. */ - }; - -diff --git a/nss_ipv4_stats.c b/nss_ipv4_stats.c -index 39b162c..c875a63 100644 ---- a/nss_ipv4_stats.c -+++ b/nss_ipv4_stats.c -@@ -177,9 +177,11 @@ void nss_ipv4_stats_node_sync(struct nss_ctx_instance *nss_ctx, struct nss_ipv4_ - nss_ipv4_stats[NSS_IPV4_STATS_MC_CONNECTION_DESTROY_REQUESTS] += nins->ipv4_mc_connection_destroy_requests; - nss_ipv4_stats[NSS_IPV4_STATS_MC_CONNECTION_DESTROY_MISSES] += nins->ipv4_mc_connection_destroy_misses; - nss_ipv4_stats[NSS_IPV4_STATS_MC_CONNECTION_FLUSHES] += nins->ipv4_mc_connection_flushes; -+#if (NSS_FW_VERSION_CODE > NSS_FW_VERSION(11,3)) - nss_ipv4_stats[NSS_IPV4_STATS_CONNECTION_CREATE_INVALID_MIRROR_IFNUM] += nins->ipv4_connection_create_invalid_mirror_ifnum; - nss_ipv4_stats[NSS_IPV4_STATS_CONNECTION_CREATE_INVALID_MIRROR_IFTYPE] += nins->ipv4_connection_create_invalid_mirror_iftype; - nss_ipv4_stats[NSS_IPV4_STATS_MIRROR_FAILURES] += nins->ipv4_mirror_failures; -+#endif - - for (i = 0; i < NSS_IPV4_EXCEPTION_EVENT_MAX; i++) { - nss_ipv4_exception_stats[i] += nins->exception_events[i]; -diff --git a/nss_ipv4_strings.c b/nss_ipv4_strings.c -index 77ff352..ce4c249 100644 ---- a/nss_ipv4_strings.c -+++ b/nss_ipv4_strings.c -@@ -137,9 +137,11 @@ struct nss_stats_info nss_ipv4_strings_stats[NSS_IPV4_STATS_MAX] = { - {"mc_destroy_requests" , NSS_STATS_TYPE_SPECIAL}, - {"mc_destroy_misses" , NSS_STATS_TYPE_SPECIAL}, - {"mc_flushes" , NSS_STATS_TYPE_SPECIAL}, -+#if (NSS_FW_VERSION_CODE > NSS_FW_VERSION(11,3)) - {"mirror_invalid_ifnum_conn_create_req" , NSS_STATS_TYPE_SPECIAL}, - {"mirror_invalid_iftype_conn_create_req" , NSS_STATS_TYPE_SPECIAL}, - {"mirror_failures" , NSS_STATS_TYPE_SPECIAL}, -+#endif - }; - - /* -diff --git a/nss_ipv6_stats.c b/nss_ipv6_stats.c -index 617f55b..a492a6c 100644 ---- a/nss_ipv6_stats.c -+++ b/nss_ipv6_stats.c -@@ -180,9 +180,11 @@ void nss_ipv6_stats_node_sync(struct nss_ctx_instance *nss_ctx, struct nss_ipv6_ - nss_ipv6_stats[NSS_IPV6_STATS_MC_CONNECTION_DESTROY_REQUESTS] += nins->ipv6_mc_connection_destroy_requests; - nss_ipv6_stats[NSS_IPV6_STATS_MC_CONNECTION_DESTROY_MISSES] += nins->ipv6_mc_connection_destroy_misses; - nss_ipv6_stats[NSS_IPV6_STATS_MC_CONNECTION_FLUSHES] += nins->ipv6_mc_connection_flushes; -+#if (NSS_FW_VERSION_CODE > NSS_FW_VERSION(11,3)) - nss_ipv6_stats[NSS_IPV6_STATS_CONNECTION_CREATE_INVALID_MIRROR_IFNUM] += nins->ipv6_connection_create_invalid_mirror_ifnum; - nss_ipv6_stats[NSS_IPV6_STATS_CONNECTION_CREATE_INVALID_MIRROR_IFTYPE] += nins->ipv6_connection_create_invalid_mirror_iftype; - nss_ipv6_stats[NSS_IPV6_STATS_MIRROR_FAILURES] += nins->ipv6_mirror_failures; -+#endif - - for (i = 0; i < NSS_IPV6_EXCEPTION_EVENT_MAX; i++) { - nss_ipv6_exception_stats[i] += nins->exception_events[i]; -diff --git a/nss_ipv6_strings.c b/nss_ipv6_strings.c -index 57b100f..29df9c9 100644 ---- a/nss_ipv6_strings.c -+++ b/nss_ipv6_strings.c -@@ -115,9 +115,11 @@ struct nss_stats_info nss_ipv6_strings_stats[NSS_IPV6_STATS_MAX] = { - {"mc_destroy_requests" ,NSS_STATS_TYPE_SPECIAL}, - {"mc_destroy_misses" ,NSS_STATS_TYPE_SPECIAL}, - {"mc_flushes" ,NSS_STATS_TYPE_SPECIAL}, -+#if (NSS_FW_VERSION_CODE > NSS_FW_VERSION(11,3)) - {"mirror_invalid_ifnum_conn_create_req" ,NSS_STATS_TYPE_SPECIAL}, - {"mirror_invalid_iftype_conn_create_req" ,NSS_STATS_TYPE_SPECIAL}, - {"mirror_failures" ,NSS_STATS_TYPE_SPECIAL}, -+#endif - }; - - /* --- -2.31.1 - diff --git a/qaa/nss/qca-nss-drv/Makefile b/qaa/nss/qca-nss-drv/Makefile deleted file mode 100644 index 7e695ca38..000000000 --- a/qaa/nss/qca-nss-drv/Makefile +++ /dev/null @@ -1,125 +0,0 @@ -include $(TOPDIR)/rules.mk -include $(INCLUDE_DIR)/kernel.mk - -PKG_NAME:=qca-nss-drv -PKG_RELEASE:=2 - -PKG_SOURCE_URL:=https://source.codeaurora.org/quic/qsdk/oss/lklm/nss-drv -PKG_SOURCE_PROTO:=git -PKG_SOURCE_VERSION:=809a00deffe9f3d4ecd15965790a152757073437 -PKG_MIRROR_HASH:=9c4340561fe9d6ccaa094bbfc5c7f98c27867d2d9a3f1a3f9a7483bca9bbedf8 - -NSS_CLIENTS_DIR:=$(TOPDIR)/qca/src/qca-nss-clients - -include $(INCLUDE_DIR)/package.mk - -define KernelPackage/qca-nss-drv - SECTION:=kernel - CATEGORY:=Kernel modules - SUBMENU:=Network Devices - DEPENDS:=@TARGET_ipq806x||TARGET_ipq_ipq806x||TARGET_ipq_ipq807x||TARGET_ipq_ipq807x_64||TARGET_ipq807x||TARGET_ipq807x_64||TARGET_ipq_ipq60xx||TARGET_ipq_ipq60xx_64||TARGET_ipq_ipq50xx||TARGET_ipq_ipq50xx_64 \ - +PACKAGE_kmod-qca-nss-gmac:kmod-qca-nss-gmac @LINUX_5_4 - TITLE:=Kernel driver for NSS (core driver) - FILES:=$(PKG_BUILD_DIR)/qca-nss-drv.ko - AUTOLOAD:=$(call AutoLoad,32,qca-nss-drv) -endef - -define KernelPackage/qca-nss-drv/install - $(INSTALL_DIR) $(1)/lib/debug - $(INSTALL_DIR) $(1)/etc/init.d - $(INSTALL_DIR) $(1)/etc/sysctl.d - $(INSTALL_DIR) $(1)/etc/hotplug.d/firmware - $(INSTALL_DIR) $(1)/etc/config - $(INSTALL_DIR) $(1)/lib/firmware - - $(INSTALL_BIN) ./files/qca-nss-drv.debug $(1)/lib/debug/qca-nss-drv - $(INSTALL_BIN) ./files/qca-nss-drv.init $(1)/etc/init.d/qca-nss-drv - $(INSTALL_BIN) ./files/qca-nss-drv.sysctl $(1)/etc/sysctl.d/qca-nss-drv.conf - $(INSTALL_BIN) ./files/qca-nss-drv.hotplug $(1)/etc/hotplug.d/firmware/10-qca-nss-fw - $(INSTALL_BIN) ./files/qca-nss-drv.conf $(1)/etc/config/nss - $(INSTALL_BIN) ./files/nss-firmware/qca-nss0-retail.bin $(1)/lib/firmware/qca-nss0.bin - $(INSTALL_BIN) ./files/nss-firmware/qca-nss1-retail.bin $(1)/lib/firmware/qca-nss1.bin - -endef - -define KernelPackage/qca-nss-drv/Description -This package contains a NSS driver for QCA chipset -endef - -define Build/InstallDev - mkdir -p $(1)/usr/include/qca-nss-drv - $(CP) $(PKG_BUILD_DIR)/exports/* $(1)/usr/include/qca-nss-drv/ -ifneq (, $(findstring $(subtarget), "ipq807x" "ipq807x_64" "ipq60xx" "ipq60xx_64" "ipq50xx" "ipq50xx_64")) - $(RM) $(1)/usr/include/qca-nss-drv/nss_ipsecmgr.h - $(INSTALL_DIR) $(1)/usr/include/qca-nss-clients - $(CP) $(NSS_CLIENTS_DIR)/exports/nss_ipsecmgr.h $(1)/usr/include/qca-nss-clients/. -endif -endef - -EXTRA_CFLAGS+= -I$(STAGING_DIR)/usr/include/qca-nss-gmac - -# Keeping default as ipq806x for branches that does not have subtarget framework -ifeq ($(CONFIG_TARGET_ipq),y) -subtarget:=$(SUBTARGET) -else -subtarget:=$(CONFIG_TARGET_BOARD) -endif - -ifeq ($(CONFIG_KERNEL_IPQ_MEM_PROFILE),256) -EXTRA_CFLAGS+= -DNSS_MEM_PROFILE_LOW -endif - -ifeq ($(CONFIG_KERNEL_IPQ_MEM_PROFILE),512) -EXTRA_CFLAGS+= -DNSS_MEM_PROFILE_MEDIUM -endif - -ifeq ($(CONFIG_KERNEL_SKB_FIXED_SIZE_2K),y) -EXTRA_CFLAGS+= -DNSS_SKB_FIXED_SIZE_2K -endif - -DRV_MAKE_OPTS:= -ifeq ($(CONFIG_KERNEL_IPQ_MEM_PROFILE),256) -DRV_MAKE_OPTS+=NSS_DRV_C2C_ENABLE=n \ - NSS_DRV_CAPWAP_ENABLE=n \ - NSS_DRV_CLMAP_ENABLE=n \ - NSS_DRV_CRYPTO_ENABLE=n \ - NSS_DRV_DTLS_ENABLE=n \ - NSS_DRV_GRE_ENABLE=n \ - NSS_DRV_GRE_REDIR_ENABLE=n \ - NSS_DRV_GRE_TUNNEL_ENABLE=n \ - NSS_DRV_IGS_ENABLE=n \ - NSS_DRV_IPSEC_ENABLE=n \ - NSS_DRV_LAG_ENABLE=n \ - NSS_DRV_L2TP_ENABLE=n \ - NSS_DRV_MAPT_ENABLE=n \ - NSS_DRV_OAM_ENABLE=n \ - NSS_DRV_PPTP_ENABLE=n \ - NSS_DRV_PORTID_ENABLE=n \ - NSS_DRV_PVXLAN_ENABLE=n \ - NSS_DRV_QRFS_ENABLE=n \ - NSS_DRV_QVPN_ENABLE=n \ - NSS_DRV_RMNET_ENABLE=n \ - NSS_DRV_SHAPER_ENABLE=n \ - NSS_DRV_SJACK_ENABLE=n \ - NSS_DRV_TLS_ENABLE=n \ - NSS_DRV_TRUSTSEC_ENABLE=n \ - NSS_DRV_TSTAMP_ENABLE=n \ - NSS_DRV_TUN6RD_ENABLE=n \ - NSS_DRV_TUNIPIP6_ENABLE=n \ - NSS_DRV_VXLAN_ENABLE=n -endif - -define Build/Configure - $(LN) arch/nss_$(subtarget).h $(PKG_BUILD_DIR)/exports/nss_arch.h -endef - -define Build/Compile - $(MAKE) $(PKG_JOBS) -C "$(LINUX_DIR)" $(strip $(DRV_MAKE_OPTS)) \ - $(KERNEL_MAKE_FLAGS) \ - $(PKG_MAKE_FLAGS) \ - M="$(PKG_BUILD_DIR)" \ - EXTRA_CFLAGS="$(EXTRA_CFLAGS)" SoC="$(subtarget)" \ - modules -endef - -$(eval $(call KernelPackage,qca-nss-drv)) diff --git a/qaa/nss/qca-nss-drv/files/nss-firmware/LICENSE.TXT b/qaa/nss/qca-nss-drv/files/nss-firmware/LICENSE.TXT deleted file mode 100644 index 41631989a..000000000 --- a/qaa/nss/qca-nss-drv/files/nss-firmware/LICENSE.TXT +++ /dev/null @@ -1,45 +0,0 @@ -Copyright (c) 2014 Qualcomm Atheros, Inc. - -All rights reserved. - -Redistribution and use in binary forms, without -modification, are permitted (subject to the limitations in the -disclaimer below) provided that the following conditions are met: - -*Redistributions must reproduce the above copyright - notice, this list of conditions, and the following disclaimer in the - documentation and/or other materials provided with the distribution. - -*Neither the name of Qualcomm Atheros, Inc. nor the names of its - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - -*No Reverse engineering, decompiling, decrypting, or disassembling of this - software is permitted. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -A PARTICULAR PURPOSE ARE DISCLAIMED. NO LICENSES OR OTHER RIGHTS, -WHETHER EXPRESS, IMPLIED, BASED ON ESTOPPEL OR OTHERWISE, ARE GRANTED -TO ANY PARTY'S PATENTS, PATENT APPLICATIONS, OR PATENTABLE INVENTIONS -BY VIRTUE OF THIS LICENSE OR THE DELIVERY OR PROVISION BY QUALCOMM -ATHEROS, INC. OF THE SOFTWARE. - -IN NO EVENT SHALL THE COPYRIGHT OWNER OR ANY CONTRIBUTOR BE LIABLE FOR -ANY INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND REGARDLESS OF ANY THEORY OF LIABILITY, WHETHER IN -CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR -OTHERWISE) ARISING IN ANY WAY OUT OF OR RESULTING FROM THE USE OF THE -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. IN ANY -EVENT, THE TOTAL AGGREGATE LIABILITY THAT MAY BE IMPOSED ON QUALCOMM -ATHEROS, INC. FOR ANY DIRECT DAMAGES ARISING UNDER OR RESULTING FROM -THIS AGREEMENT OR IN CONNECTION WITH ANY USE OF THE SOFTWARE SHALL NOT -EXCEED A TOTAL AMOUNT OF US$5.00. - -IF ANY OF THE ABOVE PROVISIONS ARE HELD TO BE VOID, INVALID, -UNENFORCEABLE, OR ILLEGAL, THE OTHER PROVISIONS SHALL CONTINUE IN FULL -FORCE AND EFFECT. - diff --git a/qaa/nss/qca-nss-drv/files/nss-firmware/NOTICE.TXT b/qaa/nss/qca-nss-drv/files/nss-firmware/NOTICE.TXT deleted file mode 100644 index ab54aa019..000000000 --- a/qaa/nss/qca-nss-drv/files/nss-firmware/NOTICE.TXT +++ /dev/null @@ -1,217 +0,0 @@ -============================================================================= - -This Notice.txt file contains certain notices of software components included -with the software that Qualcomm Atheros, Inc. ("Qualcomm Atheros") is required -to provide you. Except where prohibited by the open source license, the content -of this notices file is only provided to satisfy Qualcomm Atheros's attribution -and notice requirement; your use of these software components together with the -Qualcomm Atheros software (Qualcomm Atheros software hereinafter referred to as -"Software") is subject to the terms of your license from Qualcomm Atheros. -Compliance with all copyright laws and software license agreements included in -the notice section of this file are the responsibility of the user. Except as -may be granted by separate express written agreement, this file provides no -license to any Qualcomm Atheros patents, trademarks, copyrights, or other -intellectual property. - -Copyright (c) 2014 Qualcomm Atheros, Inc. All rights reserved. - -Qualcomm is a trademark of Qualcomm Incorporated, registered in the United -States and other countries. All Qualcomm Incorporated trademarks are used with -permission. Atheros is a trademark of Qualcomm Atheros, Inc., registered in the -United States and other countries. Other products and brand names may be -trademarks or registered trademarks of their respective owners. - -NOTICES: - -============================================================================= - -/* - * doprint.c - * Formatted string print support. - * - * Copyright 2001-2012 Qualcomm Atheros, Inc. All Rights Reserved. - * - * Qualcomm Atheros Confidential and Proprietary. - * - * This code originates with BSD Unix however it has been extensively - * modified. The original copyright is reproduced below: - * - * Copyright (c) 1988 Regents of the University of California. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted provided - * that: (1) source distributions retain this entire copyright notice and - * comment, and (2) distributions including binaries display the following - * acknowledgement: ``This product includes software developed by the - * University of California, Berkeley and its contributors'' in the - * documentation or other materials provided with the distribution and in - * all advertising materials mentioning features or use of this software. - * Neither the name of the University nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. - */ - - -/* - * math.c - * Support for the standard C library. - * - * Copyright 2006-2012 Qualcomm Atheros, Inc. All Rights Reserved. - * - * Qualcomm Atheros Confidential and Proprietary. - * - * Software contained within this file was originally released with the - * following - * copyright and license statement: - * - * ==================================================== - * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved. - * - * Developed at SunPro, a Sun Microsystems, Inc. business. - * Permission to use, copy, modify, and distribute this - * software is freely granted, provided that this notice - * is preserved. - * ==================================================== - */ - - -/* - * stdlib.c - * Routines from stdlib.h. - * - * Copyright 2004-2012 Qualcomm Atheros, Inc. All Rights Reserved. - * - * Qualcomm Atheros Confidential and Proprietary. - * - * The code for strtol() and strtoul() are also subject to the following: - * - * Copyright (c) 1990, 1993 - * The Regents of the University of California. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by the University of - * California, Berkeley and its contributors. - * 4. Neither the name of the University nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -drr_alg_utils.h: -/****************************************************************************/ -/*- - * Copyright (c) 1992, 1993 - * The Regents of the University of California. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 4. Neither the name of the University nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - - -shaper_list_utils.h: -/****************************************************************************/ -/*- - * Copyright (c) 1992, 1993 - * The Regents of the University of California. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 4. Neither the name of the University nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - - -codel_alg_inv_sqrt.h -/****************************************************************************/ -/*- - * Copyright (c) 1992, 1993 - * The Regents of the University of California. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 4. Neither the name of the University nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ diff --git a/qaa/nss/qca-nss-drv/files/nss-firmware/README.md b/qaa/nss/qca-nss-drv/files/nss-firmware/README.md deleted file mode 100644 index 2d0b47508..000000000 --- a/qaa/nss/qca-nss-drv/files/nss-firmware/README.md +++ /dev/null @@ -1,10 +0,0 @@ -NSS FIRMWARE -============ - -This repo contains firmware files to enable the NSS MAC on QCA IPQ806x SoC. - -This product includes software developed by the University of California, -Berkeley and its contributors. - -NSS firmware extracted from Synology RT2600ac SRM 1.2 - Version: 1.2-7742-4 - diff --git a/qaa/nss/qca-nss-drv/files/nss-firmware/qca-nss0-retail.bin b/qaa/nss/qca-nss-drv/files/nss-firmware/qca-nss0-retail.bin deleted file mode 100644 index 08f6efe6c8d8c476a7b68c8b44e125db75276cef..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 536324 zcmeFa33QyrneScIUENaKvMqItmk9y2HY_lS9SjbcOpw`Z0ZAZ`#W$YNuiY{h5sQNX zHMH#(VKG~f5|Ti|1ewXqgd~$YNoMYZxyjJ--bMxt7#s(%!SYUwvjV}k?(hG0zj8~K zf!uq}ckcP_NT<)cS3ULAv)5Bq#+Y?cv+enYZy0k~b$Qbijst&Q)LO61e(R3qoBPLH zmtVAeQDTwh7vop8DDlCnPsLAcAJc5x$Bgsd@)G_1k8c{|U23iAe%?}Ma6H(b%^R~U z-{0SvKiK~O=iQutpYsmR@8rCT^9MO!&iSL9-@^G_oPUk;Z*%?#=Re^5E1ciW`PVuB z4(ET*`42gNi1Y7p{v*!+j`M%u{Ga*#3%{T6`zgPl@%uTy$N2pRzyHba7yN#iH_1=f z1w9KA{mEwApS*zIh5Rn!_c?2lpXWE5Uy`54Z?3H{6SmuS6E~i57q?eBcf6}pTb;{Q zf`g6Qj7h)Mzjc$|srEun?@bxzJ!{OIq2C_l+duH_2-R`zyVnsm$-cJ3qrrJ{bM3;> zT`SxP+rxdv{?vVZdv#yJhUf>AOoS5FbRO>S-}K);WBT6D^J^=s`)Y@I-f2$QZg_4? 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zBHQFd<~Y)GI&NFDtFo<nKC(3d(J`k+CN5uQqB>s^XE^h{n(@%C)LfLIAz+zd5VCWNR;sB<^PgJf2oi7 z8}`5WSNebX?;6H#X;eLGCTbRH0V+hbqPkE$sD4mM>93c5&b_F0s7FxhHfcCC3Z*vr za0&mM;a?JaDOBOJ(CLX`SKeN1Ci_zHpMoq@v03aswjaM2hgtkC`>|f^R~(j}O0!p} uafZL+@IT7B>?w@XJqz8&{>9IH7dCRM-^EI9i~TM1FaBK|ZmfT%&;J4MG6hNi diff --git a/qaa/nss/qca-nss-drv/files/qca-nss-drv.conf b/qaa/nss/qca-nss-drv/files/qca-nss-drv.conf deleted file mode 100644 index a8a1fbf40..000000000 --- a/qaa/nss/qca-nss-drv/files/qca-nss-drv.conf +++ /dev/null @@ -1,6 +0,0 @@ -config nss_firmware 'qca_nss_0' - -config nss_firmware 'qca_nss_1' - -config general - option enable_rps '1' diff --git a/qaa/nss/qca-nss-drv/files/qca-nss-drv.debug b/qaa/nss/qca-nss-drv/files/qca-nss-drv.debug deleted file mode 100644 index 5d435c3a7..000000000 --- a/qaa/nss/qca-nss-drv/files/qca-nss-drv.debug +++ /dev/null @@ -1,26 +0,0 @@ -#!/bin/sh /sbin/sysdebug -# -# Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. -# -# Permission to use, copy, modify, and/or distribute this software for any -# purpose with or without fee is hereby granted, provided that the above -# copyright notice and this permission notice appear in all copies. -# -# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -# - -log cat /sys/kernel/debug/qca-nss-drv/stats/pppoe -log cat /sys/kernel/debug/qca-nss-drv/stats/n2h -log cat /sys/kernel/debug/qca-nss-drv/stats/ipv6 -log cat /sys/kernel/debug/qca-nss-drv/stats/ipv4 -log cat /sys/kernel/debug/qca-nss-drv/stats/gmac -log cat /sys/kernel/debug/qca-nss-drv/stats/drv -log cat /sys/kernel/debug/qca-nss-drv/stats/wifi -log cat /sys/kernel/debug/qca-nss-drv/stats/wifi_if -log cat /sys/kernel/debug/qca-nss-drv/stats/eth_rx diff --git a/qaa/nss/qca-nss-drv/files/qca-nss-drv.hotplug b/qaa/nss/qca-nss-drv/files/qca-nss-drv.hotplug deleted file mode 100644 index 1e4813838..000000000 --- a/qaa/nss/qca-nss-drv/files/qca-nss-drv.hotplug +++ /dev/null @@ -1,70 +0,0 @@ -#!/bin/sh -# -# Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. -# -# Permission to use, copy, modify, and/or distribute this software for any -# purpose with or without fee is hereby granted, provided that the above -# copyright notice and this permission notice appear in all copies. -# -# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -# - -KERNEL=`uname -r` -case "${KERNEL}" in - 3.4*) - select_or_load=load_nss_fw - ;; - *) - select_or_load=select_nss_fw - ;; -esac - -load_nss_fw () { - ls -l $1 | awk ' { print $9,$5 } '> /dev/console - echo 1 > /sys/class/firmware/$DEVICENAME/loading - cat $1 > /sys/class/firmware/$DEVICENAME/data - echo 0 > /sys/class/firmware/$DEVICENAME/loading -} - -select_nss_fw () { - rm -f /lib/firmware/$DEVICENAME - ln -s $1 /lib/firmware/$DEVICENAME - ls -l /lib/firmware/$DEVICENAME | awk ' { print $9,$5 } '> /dev/console -} - -[ "$ACTION" != "add" ] && exit - -# dev name for UCI, since it doesn't let you use . or - -SDEVNAME=$(echo ${DEVICENAME} | sed s/[.-]/_/g) - -SELECTED_FW=$(uci get nss.${SDEVNAME}.firmware 2>/dev/null) -[ -e "${SELECTED_FW}" ] && { - $select_or_load ${SELECTED_FW} - exit -} - -case $DEVICENAME in - qca-nss0* | qca-nss.0*) - if [ -e /lib/firmware/qca-nss0-enterprise.bin ] ; then - $select_or_load /lib/firmware/qca-nss0-enterprise.bin - else - $select_or_load /lib/firmware/qca-nss0-retail.bin - fi - exit - ;; - qca-nss1* | qca-nss.1*) - if [ -e /lib/firmware/qca-nss1-enterprise.bin ] ; then - $select_or_load /lib/firmware/qca-nss1-enterprise.bin - else - $select_or_load /lib/firmware/qca-nss1-retail.bin - fi - exit - ;; -esac - diff --git a/qaa/nss/qca-nss-drv/files/qca-nss-drv.init b/qaa/nss/qca-nss-drv/files/qca-nss-drv.init deleted file mode 100644 index de12cb6d1..000000000 --- a/qaa/nss/qca-nss-drv/files/qca-nss-drv.init +++ /dev/null @@ -1,50 +0,0 @@ -#!/bin/sh /etc/rc.common -# -# Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. -# -# Permission to use, copy, modify, and/or distribute this software for any -# purpose with or without fee is hereby granted, provided that the above -# copyright notice and this permission notice appear in all copies. -# -# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -# - -START=70 - -enable_rps() { - irq_nss_rps=`grep nss_queue1 /proc/interrupts | cut -d ':' -f 1 | tr -d ' '` - for entry in $irq_nss_rps - do - echo 2 > /proc/irq/$entry/smp_affinity - done - - irq_nss_rps=`grep nss_queue2 /proc/interrupts | cut -d ':' -f 1 | tr -d ' '` - for entry in $irq_nss_rps - do - echo 4 > /proc/irq/$entry/smp_affinity - done - - irq_nss_rps=`grep nss_queue3 /proc/interrupts | cut -d ':' -f 1 | tr -d ' '` - for entry in $irq_nss_rps - do - echo 8 > /proc/irq/$entry/smp_affinity - done - - # Enable NSS RPS - sysctl -w dev.nss.rps.enable=1 >/dev/null 2>/dev/null - -} - - -start() { - local rps_enabled="$(uci_get nss @general[0] enable_rps)" - if [ "$rps_enabled" -eq 1 ]; then - enable_rps - fi -} diff --git a/qaa/nss/qca-nss-drv/files/qca-nss-drv.sysctl b/qaa/nss/qca-nss-drv/files/qca-nss-drv.sysctl deleted file mode 100644 index fc36c33eb..000000000 --- a/qaa/nss/qca-nss-drv/files/qca-nss-drv.sysctl +++ /dev/null @@ -1,4 +0,0 @@ -# Default Number of connection configuration -dev.nss.ipv4cfg.ipv4_conn=4096 -dev.nss.ipv6cfg.ipv6_conn=4096 - diff --git a/qaa/nss/qca-nss-drv/patches/100-kernel-5.4-support.patch b/qaa/nss/qca-nss-drv/patches/100-kernel-5.4-support.patch deleted file mode 100644 index 4268225c3..000000000 --- a/qaa/nss/qca-nss-drv/patches/100-kernel-5.4-support.patch +++ /dev/null @@ -1,107 +0,0 @@ -diff --git a/Makefile b/Makefile -index d998548..b1a4a83 100644 ---- a/Makefile -+++ b/Makefile -@@ -161,7 +161,7 @@ endif - ccflags-y += -I$(obj)/nss_hal/include -I$(obj)/nss_data_plane/include -I$(obj)/exports -DNSS_DEBUG_LEVEL=0 -DNSS_PKT_STATS_ENABLED=1 - - ccflags-y += -DNSS_PM_DEBUG_LEVEL=0 -DNSS_SKB_REUSE_SUPPORT=1 --ccflags-y += -Werror -+# ccflags-y += -Werror - - ifneq ($(findstring 3.4, $(KERNELVERSION)),) - NSS_CCFLAGS = -DNSS_DT_SUPPORT=0 -DNSS_FW_DBG_SUPPORT=1 -DNSS_PM_SUPPORT=1 -DNSS_EMPTY_BUFFER_SIZE=1984 -diff --git a/nss_core.c b/nss_core.c -index 6c9716a..8956eb5 100644 ---- a/nss_core.c -+++ b/nss_core.c -@@ -26,6 +26,7 @@ - #include - #include - #include -+#include - #include "nss_tx_rx_common.h" - #include "nss_data_plane.h" - -@@ -45,7 +46,8 @@ - (((LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 15, 0)))) || \ - (((LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0)))) || \ - (((LINUX_VERSION_CODE >= KERNEL_VERSION(3, 18, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 19, 0)))) || \ --(((LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(4, 5, 0)))))) -+(((LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(4, 5, 0)))) || \ -+(((LINUX_VERSION_CODE >= KERNEL_VERSION(5, 4, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 5, 0)))))) - #error "Check skb recycle code in this file to match Linux version" - #endif - -@@ -395,7 +397,11 @@ static void nss_get_ddr_info(struct nss_mmu_ddr_info *mmu, char *name) - struct device_node *node; - - si_meminfo(&vals); -+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)) -+ cached = global_zone_page_state(NR_FILE_PAGES); -+#else - cached = global_page_state(NR_FILE_PAGES); -+#endif /*KERNEL_VERSION(4, 14, 0)*/ - avail_ddr = (vals.totalram + cached + vals.sharedram) * vals.mem_unit; - - /* -@@ -679,7 +685,11 @@ static inline void nss_core_handle_virt_if_pkt(struct nss_ctx_instance *nss_ctx, - * Mimic Linux behavior to allow multi-queue netdev choose which queue to use - */ - if (ndev->netdev_ops->ndo_select_queue) { -+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0)) -+ queue_offset = ndev->netdev_ops->ndo_select_queue(ndev, nbuf, NULL); -+#else - queue_offset = ndev->netdev_ops->ndo_select_queue(ndev, nbuf, NULL, NULL); -+#endif /*KERNEL_VERSION(5, 3, 0)*/ - } - - skb_set_queue_mapping(nbuf, queue_offset); -@@ -2269,7 +2279,11 @@ static inline bool nss_skb_can_reuse(struct nss_ctx_instance *nss_ctx, - * This check is added to avoid deadlock from nf_conntrack - * when ecm is trying to flush a rule. - */ -+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 11, 0)) -+ if (unlikely(skb_nfct(nbuf))) { -+#else - if (unlikely(nbuf->nfct)) { -+#endif /*KERNEL_VERSION(4, 11, 0)*/ - return false; - } - #endif -@@ -2279,7 +2285,11 @@ static inline bool nss_skb_can_reuse(struct nss_ctx_instance *nss_ctx, - * This check is added to avoid deadlock from nf_bridge - * when ecm is trying to flush a rule. - */ -+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 11, 0)) -+ if (unlikely(skb_ext_exist(nbuf, SKB_EXT_BRIDGE_NF))) { -+#else - if (unlikely(nbuf->nf_bridge)) { -+#endif /*KERNEL_VERSION(4, 11, 0)*/ - return false; - } - #endif -diff --git a/nss_n2h.c b/nss_n2h.c -index 781ce2b..695ac13 100644 ---- a/nss_n2h.c -+++ b/nss_n2h.c -@@ -19,6 +19,7 @@ - * NSS N2H node APIs - */ - -+#include - #include "nss_tx_rx_common.h" - #include "nss_n2h_stats.h" - - ---- a/nss_data_plane/nss_data_plane_gmac.c -+++ b/nss_data_plane/nss_data_plane_gmac.c -@@ -20,7 +20,7 @@ - #include "nss_tx_rx_common.h" - #include - --#define NSS_DP_GMAC_SUPPORTED_FEATURES (NETIF_F_HIGHDMA | NETIF_F_HW_CSUM | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_FRAGLIST | (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_UFO)) -+#define NSS_DP_GMAC_SUPPORTED_FEATURES (NETIF_F_HIGHDMA | NETIF_F_HW_CSUM | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_FRAGLIST | (NETIF_F_TSO | NETIF_F_TSO6)) - #define NSS_DATA_PLANE_GMAC_MAX_INTERFACES 4 - - static DEFINE_SPINLOCK(nss_data_plane_gmac_stats_lock); diff --git a/qaa/nss/qca-nss-drv/patches/101-nss-drv-Control-fab-scaling-from-package-Makefile.patch b/qaa/nss/qca-nss-drv/patches/101-nss-drv-Control-fab-scaling-from-package-Makefile.patch deleted file mode 100644 index b0facc856..000000000 --- a/qaa/nss/qca-nss-drv/patches/101-nss-drv-Control-fab-scaling-from-package-Makefile.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 40d4b080f17883ac6b39c74a5feb1af384ab6a51 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Thu, 11 Jun 2020 16:57:39 +0200 -Subject: [PATCH] nss-drv: Control fab scaling from package Makefile - -Lets control the fab scaling from the package Makefile -instead of using kernel checks that dont work. -Fab scaling in OpenWrt is done in a external way. - -Signed-off-by: Robert Marko ---- - Makefile | 9 --------- - 1 file changed, 9 deletions(-) - -diff --git a/Makefile b/Makefile -index 20729ab..2567dd4 100644 ---- a/Makefile -+++ b/Makefile -@@ -405,15 +405,8 @@ NSS_CCFLAGS = -DNSS_DT_SUPPORT=1 -DNSS_FW_DBG_SUPPORT=0 -DNSS_PM_SUPPORT=0 - ccflags-y += -I$(obj) - endif - --# Fabric scaling is supported in 3.14 and 4.4 only --ifneq ($(findstring 3.14, $(KERNELVERSION)),) --NSS_CCFLAGS += -DNSS_FABRIC_SCALING_SUPPORT=1 --else ifneq ($(findstring 4.4, $(KERNELVERSION)),) --NSS_CCFLAGS += -DNSS_FABRIC_SCALING_SUPPORT=1 --else --NSS_CCFLAGS += -DNSS_FABRIC_SCALING_SUPPORT=0 --endif -+NSS_CCFLAGS += -DNSS_FABRIC_SCALING_SUPPORT=0 - - # Disable Frequency scaling - ifeq "$(NSS_FREQ_SCALE_DISABLE)" "y" - ccflags-y += -DNSS_FREQ_SCALE_SUPPORT=0 --- -2.26.2 - diff --git a/qaa/nss/qca-nss-drv/patches/200-fix-NULL-pointer-exception.patch b/qaa/nss/qca-nss-drv/patches/200-fix-NULL-pointer-exception.patch deleted file mode 100644 index 3d8bba950..000000000 --- a/qaa/nss/qca-nss-drv/patches/200-fix-NULL-pointer-exception.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/nss_core.c -+++ b/nss_core.c -@@ -1599,7 +1599,7 @@ static int32_t nss_core_handle_cause_que - * - */ - if (unlikely((buffer_type == N2H_BUFFER_CRYPTO_RESP))) { -- dma_unmap_single(NULL, (desc->buffer + desc->payload_offs), desc->payload_len, DMA_FROM_DEVICE); -+ dma_unmap_single(nss_ctx->dev, (desc->buffer + desc->payload_offs), desc->payload_len, DMA_FROM_DEVICE); - goto consume; - } - diff --git a/qaa/nss/qca-nss-drv/patches/201-Fix-Kernel-Panic-dma-with-NULL-dev.patch b/qaa/nss/qca-nss-drv/patches/201-Fix-Kernel-Panic-dma-with-NULL-dev.patch deleted file mode 100644 index addfef1bb..000000000 --- a/qaa/nss/qca-nss-drv/patches/201-Fix-Kernel-Panic-dma-with-NULL-dev.patch +++ /dev/null @@ -1,82 +0,0 @@ -From 89949decfd9a0f86427b502aae4fbc3a3ef399f0 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Tue, 23 Jun 2020 19:50:28 +0200 -Subject: [PATCH] Fix Kernel Panic dma with NULL dev - ---- - nss_coredump.c | 4 ++-- - nss_log.c | 8 +++++--- - 2 files changed, 8 insertions(+), 6 deletions(-) - -diff --git a/nss_coredump.c b/nss_coredump.c -index aa4ba82..957eca0 100644 ---- a/nss_coredump.c -+++ b/nss_coredump.c -@@ -154,7 +154,7 @@ void nss_fw_coredump_notify(struct nss_ctx_instance *nss_own, - dma_addr = nss_own->meminfo_ctx.logbuffer_dma; - } - -- dma_sync_single_for_cpu(NULL, dma_addr, sizeof(struct nss_log_descriptor), DMA_FROM_DEVICE); -+ dma_sync_single_for_cpu(nss_own->dev, dma_addr, sizeof(struct nss_log_descriptor), DMA_FROM_DEVICE); - - /* - * If the current entry is smaller than or equal to the number of NSS_LOG_COREDUMP_LINE_NUM, -@@ -181,7 +181,7 @@ void nss_fw_coredump_notify(struct nss_ctx_instance *nss_own, - - offset = (index * sizeof(struct nss_log_entry)) - + offsetof(struct nss_log_descriptor, log_ring_buffer); -- dma_sync_single_for_cpu(NULL, dma_addr + offset, -+ dma_sync_single_for_cpu(nss_own->dev, dma_addr + offset, - sizeof(struct nss_log_entry), DMA_FROM_DEVICE); - nss_info_always("%p: %s\n", nss_own, nle_print->message); - nle_print++; -diff --git a/nss_log.c b/nss_log.c -index 06ebba4..f9bd6c8 100644 ---- a/nss_log.c -+++ b/nss_log.c -@@ -44,6 +44,7 @@ struct nss_log_data { - uint32_t last_entry; /* Last known sampled entry (or index) */ - uint32_t nentries; /* Caches the total number of entries of log buffer */ - int nss_id; /* NSS Core id being used */ -+ struct device *nss_dev; - }; - - struct nss_log_ring_buffer_addr nss_rbe[NSS_MAX_CORES]; -@@ -125,6 +126,7 @@ static int nss_log_open(struct inode *inode, struct file *filp) - data->last_entry = 0; - data->nentries = nss_rbe[nss_id].nentries; - data->dma_addr = nss_rbe[nss_id].dma_addr; -+ data->nss_dev = nss_ctx->dev; - - /* - * Increment the reference count so that we don't free -@@ -207,7 +209,7 @@ static ssize_t nss_log_read(struct file *filp, char __user *buf, size_t size, lo - /* - * Get the current index - */ -- dma_sync_single_for_cpu(NULL, data->dma_addr, sizeof(struct nss_log_descriptor), DMA_FROM_DEVICE); -+ dma_sync_single_for_cpu(data->nss_dev, data->dma_addr, sizeof(struct nss_log_descriptor), DMA_FROM_DEVICE); - entry = nss_log_current_entry(desc); - - /* -@@ -251,7 +253,7 @@ static ssize_t nss_log_read(struct file *filp, char __user *buf, size_t size, lo - offset = (offset * sizeof(struct nss_log_entry)) - + offsetof(struct nss_log_descriptor, log_ring_buffer); - -- dma_sync_single_for_cpu(NULL, data->dma_addr + offset, -+ dma_sync_single_for_cpu(data->nss_dev, data->dma_addr + offset, - sizeof(struct nss_log_entry), DMA_FROM_DEVICE); - rb = &desc->log_ring_buffer[index]; - -@@ -510,7 +512,7 @@ bool nss_debug_log_buffer_alloc(uint8_t nss_id, uint32_t nentry) - return true; - - fail: -- dma_unmap_single(NULL, dma_addr, size, DMA_FROM_DEVICE); -+ dma_unmap_single(nss_ctx->dev, dma_addr, size, DMA_FROM_DEVICE); - kfree(addr); - wake_up(&nss_log_wq); - return false; --- -2.27.0 - diff --git a/qaa/nss/qca-nss-drv/patches/400-Exported-set-nexthop-function.patch b/qaa/nss/qca-nss-drv/patches/400-Exported-set-nexthop-function.patch deleted file mode 100644 index 8c0ffe774..000000000 --- a/qaa/nss/qca-nss-drv/patches/400-Exported-set-nexthop-function.patch +++ /dev/null @@ -1,47 +0,0 @@ -From f8cf061454a3707c0c84d0fca685e84455f91362 Mon Sep 17 00:00:00 2001 -From: Suruchi Suman -Date: Tue, 3 Dec 2019 12:57:38 +0530 -Subject: [qca-nss-drv] Exported set nexhop function from drv. - -Change-Id: I3df6658bef72fe574ac9acfb7aac61785769766f -Signed-off-by: Suruchi Suman ---- - nss_phys_if.c | 9 ++++++++- - 1 file changed, 8 insertions(+), 1 deletion(-) - -diff --git a/nss_phys_if.c b/nss_phys_if.c -index 4f9b20f..0c58d95 100644 ---- a/nss_phys_if.c -+++ b/nss_phys_if.c -@@ -1,6 +1,6 @@ - /* - ************************************************************************** -- * Copyright (c) 2014-2019, The Linux Foundation. All rights reserved. -+ * Copyright (c) 2014-2020, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. -@@ -583,6 +583,12 @@ nss_tx_status_t nss_phys_if_set_nexthop(struct nss_ctx_instance *nss_ctx, uint32 - struct nss_phys_if_msg nim; - - NSS_VERIFY_CTX_MAGIC(nss_ctx); -+ -+ if (nexthop >= NSS_MAX_NET_INTERFACES) { -+ nss_warning("%p: Invalid nexthop interface number: %d", nss_ctx, nexthop); -+ return NSS_TX_FAILURE_BAD_PARAM; -+ } -+ - nss_info("%p: Phys If nexthop will be set to %d, id:%d\n", nss_ctx, nexthop, if_num); - - nss_cmn_msg_init(&nim.cm, if_num, NSS_PHYS_IF_SET_NEXTHOP, -@@ -591,6 +597,7 @@ nss_tx_status_t nss_phys_if_set_nexthop(struct nss_ctx_instance *nss_ctx, uint32 - - return nss_phys_if_msg_sync(nss_ctx, &nim); - } -+EXPORT_SYMBOL(nss_phys_if_set_nexthop); - - /* - * nss_get_state() --- -cgit v1.1 - diff --git a/qaa/nss/qca-nss-ecm-64/Makefile b/qaa/nss/qca-nss-ecm-64/Makefile deleted file mode 100644 index 77afbb204..000000000 --- a/qaa/nss/qca-nss-ecm-64/Makefile +++ /dev/null @@ -1,96 +0,0 @@ -include $(TOPDIR)/rules.mk - -PKG_NAME:=qca-nss-ecm-64 -PKG_RELEASE:=$(AUTORELEASE) - -PKG_SOURCE_URL:=https://source.codeaurora.org/quic/cc-qrdk/oss/lklm/qca-nss-ecm -PKG_SOURCE_PROTO:=git -PKG_SOURCE_DATE:=2021-04-29 -PKG_SOURCE_VERSION:=c115aec34867b582e2e5ea79fc5315971e0e953c -PKG_MIRROR_HASH:=962385b45daa2e552a15018bf2930c2df1f6f575d885375bf935a142b4255da5 - -PKG_BUILD_PARALLEL:=1 - -include $(INCLUDE_DIR)/kernel.mk -include $(INCLUDE_DIR)/package.mk - -define KernelPackage/qca-nss-ecm-64 - SECTION:=kernel - CATEGORY:=Kernel modules - SUBMENU:=Network Support - DEPENDS:=@(TARGET_ipq807x||TARGET_ipq60xx) \ - +kmod-qca-nss-drv-64 \ - +iptables-mod-extra \ - +kmod-ipt-conntrack \ - +kmod-ipt-physdev \ - +iptables-mod-physdev \ - +kmod-ppp \ - +kmod-pppoe - TITLE:=QCA NSS Enhanced Connection Manager (ECM) - FILES:=$(PKG_BUILD_DIR)/*.ko - KCONFIG:=CONFIG_BRIDGE_NETFILTER=y \ - CONFIG_NF_CONNTRACK_EVENTS=y \ - CONFIG_NF_CONNTRACK_CHAIN_EVENTS=y \ - CONFIG_NF_CONNTRACK_DSCPREMARK_EXT=n -endef - -define KernelPackage/qca-nss-ecm-64/Description -This package contains the QCA NSS Enhanced Connection Manager -endef - -define KernelPackage/qca-nss-ecm-64/install - $(INSTALL_DIR) $(1)/etc/firewall.d $(1)/etc/init.d $(1)/usr/bin $(1)/lib/netifd/offload $(1)/etc/config $(1)/etc/uci-defaults $(1)/etc/sysctl.d - $(INSTALL_DATA) ./files/qca-nss-ecm.firewall $(1)/etc/firewall.d/qca-nss-ecm - $(INSTALL_BIN) ./files/qca-nss-ecm.init $(1)/etc/init.d/qca-nss-ecm - $(INSTALL_BIN) ./files/ecm_dump.sh $(1)/usr/bin/ - $(INSTALL_BIN) ./files/on-demand-down $(1)/lib/netifd/offload/on-demand-down - $(INSTALL_DATA) ./files/qca-nss-ecm.uci $(1)/etc/config/ecm - $(INSTALL_DATA) ./files/qca-nss-ecm.defaults $(1)/etc/uci-defaults/99-qca-nss-ecm - $(INSTALL_BIN) ./files/qca-nss-ecm.sysctl $(1)/etc/sysctl.d/qca-nss-ecm.conf -endef - -EXTRA_CFLAGS+=-I$(STAGING_DIR)/usr/include/qca-nss-drv - -ifneq (, $(findstring $(CONFIG_TARGET_BOARD), "ipq807x" "ipq60xx")) -ECM_MAKE_OPTS+= ECM_FRONT_END_NSS_ENABLE=y \ - ECM_CLASSIFIER_HYFI_ENABLE=n \ - ECM_MULTICAST_ENABLE=n \ - ECM_INTERFACE_IPSEC_ENABLE=n \ - ECM_INTERFACE_PPTP_ENABLE=n \ - ECM_INTERFACE_L2TPV2_ENABLE=n \ - ECM_INTERFACE_GRE_TAP_ENABLE=n \ - ECM_INTERFACE_GRE_TUN_ENABLE=n \ - ECM_INTERFACE_SIT_ENABLE=n \ - ECM_INTERFACE_TUNIPIP6_ENABLE=n \ - ECM_INTERFACE_RAWIP_ENABLE=n \ - ECM_INTERFACE_VLAN_ENABLE=n \ - ECM_CLASSIFIER_MARK_ENABLE=n \ - ECM_CLASSIFIER_DSCP_ENABLE=n \ - ECM_CLASSIFIER_PCC_ENABLE=n \ - ECM_BAND_STEERING_ENABLE=n \ - ECM_INTERFACE_PPPOE_ENABLE=y -endif - -ifeq ($(CONFIG_TARGET_BOARD), "ipq807x") - SOC="ipq807x_64" -else ifeq ($(CONFIG_TARGET_BOARD), "ipq60xx") - SOC="ipq60xx_64" -endif - -define Build/InstallDev - mkdir -p $(1)/usr/include/qca-nss-ecm - $(CP) $(PKG_BUILD_DIR)/exports/* $(1)/usr/include/qca-nss-ecm -endef - -define Build/Compile - +$(MAKE) -C "$(LINUX_DIR)" $(strip $(ECM_MAKE_OPTS)) \ - CROSS_COMPILE="$(TARGET_CROSS)" \ - ARCH="$(LINUX_KARCH)" \ - M="$(PKG_BUILD_DIR)" \ - EXTRA_CFLAGS="$(EXTRA_CFLAGS)" SoC=$(SOC) \ - $(KERNEL_MAKE_FLAGS) \ - $(PKG_JOBS) \ - modules -endef - -$(eval $(call KernelPackage,qca-nss-ecm-64)) diff --git a/qaa/nss/qca-nss-ecm-64/files/ecm_dump.sh b/qaa/nss/qca-nss-ecm-64/files/ecm_dump.sh deleted file mode 100644 index dbf7de753..000000000 --- a/qaa/nss/qca-nss-ecm-64/files/ecm_dump.sh +++ /dev/null @@ -1,95 +0,0 @@ -#!/bin/sh -# -# Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. -# -# Permission to use, copy, modify, and/or distribute this software for any -# purpose with or without fee is hereby granted, provided that the above -# copyright notice and this permission notice appear in all copies. -# -# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -# - -ECM_MODULE=${1:-ecm_state} -MOUNT_ROOT=/dev/ecm - -# -# usage: ecm_dump.sh [module=ecm_db] -# -# with no parameters, ecm_dump.sh will attempt to mount the -# ecm_db state file and cat its contents. -# -# example with a parameter: ecm_dump.sh ecm_classifier_default -# -# this will cause ecm_dump to attempt to find and mount the state -# file for the ecm_classifier_default module, and if successful -# cat the contents. -# - -# this is one of the state files, which happens to be the -# last module started in ecm -ECM_STATE=/sys/kernel/debug/ecm/ecm_state/state_dev_major - -# tests to see if ECM is up and ready to receive commands. -# returns 0 if ECM is fully up and ready, else 1 -ecm_is_ready() { - if [ ! -e "${ECM_STATE}" ] - then - return 1 - fi - return 0 -} - -# -# module_state_mount(module_name) -# Mounts the state file of the module, if supported -# -module_state_mount() { - local module_name=$1 - local mount_dir=$2 - local state_file="/sys/kernel/debug/ecm/${module_name}/state_dev_major" - - if [ -e "${mount_dir}/${module_name}" ] - then - # already mounted - return 0 - fi - - #echo "Mount state file for $module_name ..." - if [ ! -e "$state_file" ] - then - #echo "... $module_name does not support state" - return 1 - fi - - local major="`cat $state_file`" - #echo "... Mounting state $state_file with major: $major" - mknod "${mount_dir}/${module_name}" c $major 0 -} - -# -# main -# -ecm_is_ready || { - #echo "ECM is not running" - exit 1 -} - -# all state files are mounted under MOUNT_ROOT, so make sure it exists -mkdir -p ${MOUNT_ROOT} - -# -# attempt to mount state files for the requested module and cat it -# if the mount succeeded -# -module_state_mount ${ECM_MODULE} ${MOUNT_ROOT} && { - cat ${MOUNT_ROOT}/${ECM_MODULE} - exit 0 -} - -exit 2 diff --git a/qaa/nss/qca-nss-ecm-64/files/on-demand-down b/qaa/nss/qca-nss-ecm-64/files/on-demand-down deleted file mode 100644 index 02d708e03..000000000 --- a/qaa/nss/qca-nss-ecm-64/files/on-demand-down +++ /dev/null @@ -1,6 +0,0 @@ -#!/bin/sh -# Copyright (c) 2016 The Linux Foundation. All rights reserved. - -[ -e "/sys/kernel/debug/ecm/ecm_db/defunct_all" ] && { - echo 1 > /sys/kernel/debug/ecm/ecm_db/defunct_all -} diff --git a/qaa/nss/qca-nss-ecm-64/files/qca-nss-ecm.defaults b/qaa/nss/qca-nss-ecm-64/files/qca-nss-ecm.defaults deleted file mode 100644 index 308e265c9..000000000 --- a/qaa/nss/qca-nss-ecm-64/files/qca-nss-ecm.defaults +++ /dev/null @@ -1,28 +0,0 @@ -#!/bin/sh -# -# Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. -# -# Permission to use, copy, modify, and/or distribute this software for any -# purpose with or without fee is hereby granted, provided that the above -# copyright notice and this permission notice appear in all copies. -# -# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -# - -uci -q batch << EOF - delete firewall.qcanssecm - set firewall.qcanssecm=include - set firewall.qcanssecm.type=script - set firewall.qcanssecm.path=/etc/firewall.d/qca-nss-ecm - set firewall.qcanssecm.family=any - set firewall.qcanssecm.reload=1 - commit firewall -EOF - -exit 0 diff --git a/qaa/nss/qca-nss-ecm-64/files/qca-nss-ecm.firewall b/qaa/nss/qca-nss-ecm-64/files/qca-nss-ecm.firewall deleted file mode 100644 index 24c64def2..000000000 --- a/qaa/nss/qca-nss-ecm-64/files/qca-nss-ecm.firewall +++ /dev/null @@ -1,18 +0,0 @@ -#!/bin/sh -# -# Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. -# -# Permission to use, copy, modify, and/or distribute this software for any -# purpose with or without fee is hereby granted, provided that the above -# copyright notice and this permission notice appear in all copies. -# -# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -# - -iptables -A FORWARD -m physdev --physdev-is-bridged -j ACCEPT diff --git a/qaa/nss/qca-nss-ecm-64/files/qca-nss-ecm.init b/qaa/nss/qca-nss-ecm-64/files/qca-nss-ecm.init deleted file mode 100644 index 78cf16dc0..000000000 --- a/qaa/nss/qca-nss-ecm-64/files/qca-nss-ecm.init +++ /dev/null @@ -1,137 +0,0 @@ -#!/bin/sh /etc/rc.common -# -# Copyright (c) 2014, 2019-2020 The Linux Foundation. All rights reserved. -# -# Permission to use, copy, modify, and/or distribute this software for any -# purpose with or without fee is hereby granted, provided that the above -# copyright notice and this permission notice appear in all copies. -# -# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - -# The shebang above has an extra space intentially to avoid having -# openwrt build scripts automatically enable this package starting -# at boot. - -START=19 - -get_front_end_mode() { - config_load "ecm" - config_get front_end global acceleration_engine "auto" - - case $front_end in - auto) - echo '0' - ;; - nss) - echo '1' - ;; - sfe) - echo '2' - ;; - *) - echo 'uci_option_acceleration_engine is invalid' - esac -} - -support_bridge() { - #NSS support bridge acceleration - [ -d /sys/kernel/debug/ecm/ecm_nss_ipv4 ] && return 0 - #SFE doesn't support bridge acceleration - [ -d /sys/kernel/debug/ecm/ecm_sfe_ipv4 ] && return 1 -} - -load_sfe() { - local kernel_version=$(uname -r) - - [ -e "/lib/modules/$kernel_version/shortcut-fe.ko" ] && { - [ -d /sys/module/shortcut_fe ] || insmod shortcut-fe - } - - [ -e "/lib/modules/$kernel_version/shortcut-fe-ipv6.ko" ] && { - [ -d /sys/module/shortcut_fe_ipv6 ] || insmod shortcut-fe-ipv6 - } - - [ -e "/lib/modules/$kernel_version/shortcut-fe-cm.ko" ] && { - [ -d /sys/module/shortcut_fe_cm ] || insmod shortcut-fe-cm - } - - [ -e "/lib/modules/$kernel_version/shortcut-fe-drv.ko" ] && { - [ -d /sys/module/shortcut_fe_drv ] || insmod shortcut-fe-drv - } -} - -load_ecm() { - [ -d /sys/module/ecm ] || { - [ ! -e /proc/device-tree/MP_256 ] && load_sfe - insmod ecm front_end_selection=$(get_front_end_mode) - } - - support_bridge && { - sysctl -w net.bridge.bridge-nf-call-ip6tables=1 - sysctl -w net.bridge.bridge-nf-call-iptables=1 - } -} - -unload_ecm() { - sysctl -w net.bridge.bridge-nf-call-ip6tables=0 - sysctl -w net.bridge.bridge-nf-call-iptables=0 - - if [ -d /sys/module/ecm ]; then - # - # Stop ECM frontends - # - echo 1 > /sys/kernel/debug/ecm/front_end_ipv4_stop - echo 1 > /sys/kernel/debug/ecm/front_end_ipv6_stop - - # - # Defunct the connections - # - echo 1 > /sys/kernel/debug/ecm/ecm_db/defunct_all - sleep 5; - - rmmod ecm - sleep 1 - fi -} - -start() { - load_ecm - - # If the acceleration engine is NSS, enable wifi redirect. - [ -d /sys/kernel/debug/ecm/ecm_nss_ipv4 ] && sysctl -w dev.nss.general.redirect=1 - - support_bridge && { - echo 'net.bridge.bridge-nf-call-ip6tables=1' >> /etc/sysctl.d/qca-nss-ecm.conf - echo 'net.bridge.bridge-nf-call-iptables=1' >> /etc/sysctl.d/qca-nss-ecm.conf - } - - if [ -d /sys/module/qca_ovsmgr ]; then - insmod ecm_ovs - fi - -} - -stop() { - # If ECM is already not loaded, just return. - if [ ! -d /sys/module/ecm ]; then - return - fi - - # If the acceleration engine is NSS, disable wifi redirect. - [ -d /sys/kernel/debug/ecm/ecm_nss_ipv4 ] && sysctl -w dev.nss.general.redirect=0 - - sed '/net.bridge.bridge-nf-call-ip6tables=1/d' -i /etc/sysctl.d/qca-nss-ecm.conf - sed '/net.bridge.bridge-nf-call-iptables=1/d' -i /etc/sysctl.d/qca-nss-ecm.conf - - if [ -d /sys/module/ecm_ovs ]; then - rmmod ecm_ovs - fi - - unload_ecm -} diff --git a/qaa/nss/qca-nss-ecm-64/files/qca-nss-ecm.sysctl b/qaa/nss/qca-nss-ecm-64/files/qca-nss-ecm.sysctl deleted file mode 100644 index 1a3d76b18..000000000 --- a/qaa/nss/qca-nss-ecm-64/files/qca-nss-ecm.sysctl +++ /dev/null @@ -1,2 +0,0 @@ -# nf_conntrack_tcp_no_window_check is 0 by default, set it to 1 -net.netfilter.nf_conntrack_tcp_no_window_check=1 diff --git a/qaa/nss/qca-nss-ecm-64/files/qca-nss-ecm.uci b/qaa/nss/qca-nss-ecm-64/files/qca-nss-ecm.uci deleted file mode 100644 index 4f2de6877..000000000 --- a/qaa/nss/qca-nss-ecm-64/files/qca-nss-ecm.uci +++ /dev/null @@ -1,2 +0,0 @@ -config ecm 'global' - option acceleration_engine 'auto' diff --git a/qaa/nss/qca-nss-ecm-64/patches/001-treewide-componentize-the-module-even-more.patch b/qaa/nss/qca-nss-ecm-64/patches/001-treewide-componentize-the-module-even-more.patch deleted file mode 100644 index 4e7932c9d..000000000 --- a/qaa/nss/qca-nss-ecm-64/patches/001-treewide-componentize-the-module-even-more.patch +++ /dev/null @@ -1,335 +0,0 @@ -From 73345c87b28a473b35b57e673f8de963c3d73da1 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Wed, 19 May 2021 02:38:53 +0200 -Subject: [PATCH] treewide: componentize the module even more - -Signed-off-by: Ansuel Smith ---- - Makefile | 56 +++++++++++++++++++++++++------- - ecm_db/ecm_db_connection.c | 8 +++++ - ecm_db/ecm_db_node.c | 4 +++ - ecm_interface.c | 8 +++++ - frontends/ecm_front_end_common.c | 7 ++++ - 5 files changed, 72 insertions(+), 11 deletions(-) - ---- a/Makefile -+++ b/Makefile -@@ -82,10 +82,18 @@ ccflags-$(ECM_INTERFACE_BOND_ENABLE) += - # Define ECM_INTERFACE_PPPOE_ENABLE=y in order - # to enable support for PPPoE acceleration. - # ############################################################################# --ECM_INTERFACE_PPPOE_ENABLE=y -+ifndef $(ECM_INTERFACE_PPPOE_ENABLE) -+ ECM_INTERFACE_PPPOE_ENABLE=y -+endif - ccflags-$(ECM_INTERFACE_PPPOE_ENABLE) += -DECM_INTERFACE_PPPOE_ENABLE - - # ############################################################################# -+# Define ECM_INTERFACE_L2TPV2_PPTP_ENABLE=y in order -+# to enable support for l2tpv2 or PPTP detection. -+# ############################################################################# -+ccflags-$(ECM_INTERFACE_L2TPV2_PPTP_ENABLE) += -DECM_INTERFACE_L2TPV2_PPTP_ENABLE -+ -+# ############################################################################# - # Define ECM_INTERFACE_L2TPV2_ENABLE=y in order - # to enable support for l2tpv2 acceleration. - # ############################################################################# -@@ -118,6 +126,12 @@ ccflags-$(ECM_INTERFACE_PPP_ENABLE) += - - ccflags-$(ECM_INTERFACE_MAP_T_ENABLE) += -DECM_INTERFACE_MAP_T_ENABLE - - # ############################################################################# -+# Define ECM_INTERFACE_GRE_ENABLE=y in order -+# to enable support for GRE detection. -+# ############################################################################# -+ccflags-$(ECM_INTERFACE_GRE_ENABLE) += -DECM_INTERFACE_GRE_ENABLE -+ -+# ############################################################################# - # Define ECM_INTERFACE_GRE_TAP_ENABLE=y in order - # to enable support for GRE TAP interface. - # ############################################################################# -@@ -186,7 +200,9 @@ ccflags-$(ECM_INTERFACE_OVS_BRIDGE_ENABL - # ############################################################################# - # Define ECM_INTERFACE_VLAN_ENABLE=y in order to enable support for VLAN - # ############################################################################# --ECM_INTERFACE_VLAN_ENABLE=y -+ifndef $(ECM_INTERFACE_VLAN_ENABLE) -+ ECM_INTERFACE_VLAN_ENABLE=y -+endif - ccflags-$(ECM_INTERFACE_VLAN_ENABLE) += -DECM_INTERFACE_VLAN_ENABLE - - # ############################################################################# -@@ -228,7 +244,9 @@ ccflags-$(ECM_CLASSIFIER_OVS_ENABLE) += - # ############################################################################# - # Define ECM_CLASSIFIER_MARK_ENABLE=y in order to enable mark classifier. - # ############################################################################# --ECM_CLASSIFIER_MARK_ENABLE=y -+ifndef $(ECM_CLASSIFIER_MARK_ENABLE) -+ ECM_CLASSIFIER_MARK_ENABLE=y -+endif - ecm-$(ECM_CLASSIFIER_MARK_ENABLE) += ecm_classifier_mark.o - ccflags-$(ECM_CLASSIFIER_MARK_ENABLE) += -DECM_CLASSIFIER_MARK_ENABLE - -@@ -247,7 +265,9 @@ ccflags-$(ECM_CLASSIFIER_NL_ENABLE) += - - # ############################################################################# - # Define ECM_CLASSIFIER_DSCP_ENABLE=y in order to enable DSCP classifier. - # ############################################################################# --ECM_CLASSIFIER_DSCP_ENABLE=y -+ifndef $(ECM_CLASSIFIER_DSCP_ENABLE) -+ ECM_CLASSIFIER_DSCP_ENABLE=y -+endif - ecm-$(ECM_CLASSIFIER_DSCP_ENABLE) += ecm_classifier_dscp.o - ccflags-$(ECM_CLASSIFIER_DSCP_ENABLE) += -DECM_CLASSIFIER_DSCP_ENABLE - ccflags-$(ECM_CLASSIFIER_DSCP_IGS) += -DECM_CLASSIFIER_DSCP_IGS -@@ -274,7 +294,9 @@ endif - # the Parental Controls subsystem classifier in ECM. Currently disabled until - # customers require it / if they need to integrate their Parental Controls with it. - # ############################################################################# --ECM_CLASSIFIER_PCC_ENABLE=y -+ifndef $(ECM_CLASSIFIER_PCC_ENABLE) -+ ECM_CLASSIFIER_PCC_ENABLE=y -+endif - ecm-$(ECM_CLASSIFIER_PCC_ENABLE) += ecm_classifier_pcc.o - ccflags-$(ECM_CLASSIFIER_PCC_ENABLE) += -DECM_CLASSIFIER_PCC_ENABLE - -@@ -301,28 +323,36 @@ ccflags-$(ECM_NON_PORTED_SUPPORT_ENABLE) - # ############################################################################# - # Define ECM_STATE_OUTPUT_ENABLE=y to support XML state output - # ############################################################################# --ECM_STATE_OUTPUT_ENABLE=y -+ifndef $(ECM_STATE_OUTPUT_ENABLE) -+ ECM_STATE_OUTPUT_ENABLE=y -+endif - ecm-$(ECM_STATE_OUTPUT_ENABLE) += ecm_state.o - ccflags-$(ECM_STATE_OUTPUT_ENABLE) += -DECM_STATE_OUTPUT_ENABLE - - # ############################################################################# - # Define ECM_DB_ADVANCED_STATS_ENABLE to support XML state output - # ############################################################################# --ECM_DB_ADVANCED_STATS_ENABLE=y -+ifndef $(ECM_DB_ADVANCED_STATS_ENABLE) -+ ECM_DB_ADVANCED_STATS_ENABLE=y -+endif - ccflags-$(ECM_DB_ADVANCED_STATS_ENABLE) += -DECM_DB_ADVANCED_STATS_ENABLE - - # ############################################################################# - # Define ECM_DB_CONNECTION_CROSS_REFERENCING_ENABLE=y in order to enable - # the database to track relationships between objects. - # ############################################################################# --ECM_DB_CONNECTION_CROSS_REFERENCING_ENABLE=y -+ifndef $(ECM_DB_CONNECTION_CROSS_REFERENCING_ENABLE) -+ ECM_DB_CONNECTION_CROSS_REFERENCING_ENABLE=y -+endif - ccflags-$(ECM_DB_CONNECTION_CROSS_REFERENCING_ENABLE) += -DECM_DB_XREF_ENABLE - - # ############################################################################# - # Define ECM_TRACKER_DPI_SUPPORT_ENABLE=y in order to enable support for - # deep packet inspection and tracking of data with the trackers. - # ############################################################################# --ECM_TRACKER_DPI_SUPPORT_ENABLE=y -+ifndef $(ECM_TRACKER_DPI_SUPPORT_ENABLE) -+ ECM_TRACKER_DPI_SUPPORT_ENABLE=y -+endif - ccflags-$(ECM_TRACKER_DPI_SUPPORT_ENABLE) += -DECM_TRACKER_DPI_SUPPORT_ENABLE - - # ############################################################################# -@@ -330,14 +360,18 @@ ccflags-$(ECM_TRACKER_DPI_SUPPORT_ENABLE - # support for the database keeping lists of connections that are assigned - # on a per TYPE of classifier basis. - # ############################################################################# --ECM_DB_CLASSIFIER_TYPE_ASSIGNMENTS_TRACK_ENABLE=y -+ifndef $(ECM_DB_CLASSIFIER_TYPE_ASSIGNMENTS_TRACK_ENABLE) -+ ECM_DB_CLASSIFIER_TYPE_ASSIGNMENTS_TRACK_ENABLE=y -+endif - ccflags-$(ECM_DB_CLASSIFIER_TYPE_ASSIGNMENTS_TRACK_ENABLE) += -DECM_DB_CTA_TRACK_ENABLE - - # ############################################################################# - # Define ECM_BAND_STEERING_ENABLE=y in order to enable - # band steering feature. - # ############################################################################# --ECM_BAND_STEERING_ENABLE=y -+ifndef $(ECM_BAND_STEERING_ENABLE) -+ ECM_BAND_STEERING_ENABLE=y -+endif - ccflags-$(ECM_BAND_STEERING_ENABLE) += -DECM_BAND_STEERING_ENABLE - - # ############################################################################# ---- a/ecm_db/ecm_db_connection.c -+++ b/ecm_db/ecm_db_connection.c -@@ -430,7 +430,9 @@ EXPORT_SYMBOL(ecm_db_connection_make_def - */ - void ecm_db_connection_data_totals_update(struct ecm_db_connection_instance *ci, bool is_from, uint64_t size, uint64_t packets) - { -+#ifdef ECM_DB_ADVANCED_STATS_ENABLE - int32_t i; -+#endif - - DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed\n", ci); - -@@ -529,7 +531,9 @@ EXPORT_SYMBOL(ecm_db_connection_data_tot - */ - void ecm_db_connection_data_totals_update_dropped(struct ecm_db_connection_instance *ci, bool is_from, uint64_t size, uint64_t packets) - { -+#ifdef ECM_DB_ADVANCED_STATS_ENABLE - int32_t i; -+#endif - - DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed\n", ci); - -@@ -1508,6 +1512,7 @@ void ecm_db_connection_defunct_all(void) - } - EXPORT_SYMBOL(ecm_db_connection_defunct_all); - -+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE - /* - * ecm_db_connection_defunct_by_classifier() - * Make defunct based on masked fields -@@ -1667,6 +1672,7 @@ next_ci: - ECM_IP_ADDR_TO_OCTAL(dest_addr_mask), dest_port_mask, proto_mask, cnt); - } - } -+#endif - - /* - * ecm_db_connection_defunct_by_port() -@@ -1956,6 +1962,7 @@ struct ecm_db_node_instance *ecm_db_conn - } - EXPORT_SYMBOL(ecm_db_connection_node_get_and_ref); - -+#ifdef ECM_DB_XREF_ENABLE - /* - * ecm_db_connection_mapping_get_and_ref_next() - * Return reference to next connection in the mapping chain in the specified direction. -@@ -1997,6 +2004,7 @@ struct ecm_db_connection_instance *ecm_d - return nci; - } - EXPORT_SYMBOL(ecm_db_connection_iface_get_and_ref_next); -+#endif - - /* - * ecm_db_connection_mapping_get_and_ref() ---- a/ecm_db/ecm_db_node.c -+++ b/ecm_db/ecm_db_node.c -@@ -224,9 +224,11 @@ EXPORT_SYMBOL(ecm_db_node_get_and_ref_ne - */ - int ecm_db_node_deref(struct ecm_db_node_instance *ni) - { -+#ifdef ECM_DB_XREF_ENABLE - #if (DEBUG_LEVEL >= 1) - int dir; - #endif -+#endif - DEBUG_CHECK_MAGIC(ni, ECM_DB_NODE_INSTANCE_MAGIC, "%px: magic failed\n", ni); - - spin_lock_bh(&ecm_db_lock); -@@ -486,9 +488,11 @@ EXPORT_SYMBOL(ecm_db_node_iface_get_and_ - void ecm_db_node_add(struct ecm_db_node_instance *ni, struct ecm_db_iface_instance *ii, uint8_t *address, - ecm_db_node_final_callback_t final, void *arg) - { -+#ifdef ECM_DB_XREF_ENABLE - #if (DEBUG_LEVEL >= 1) - int dir; - #endif -+#endif - ecm_db_node_hash_t hash_index; - struct ecm_db_listener_instance *li; - ---- a/ecm_interface.c -+++ b/ecm_interface.c -@@ -1343,6 +1343,7 @@ struct neighbour *ecm_interface_ipv6_nei - */ - bool ecm_interface_is_pptp(struct sk_buff *skb, const struct net_device *out) - { -+#ifdef ECM_INTERFACE_PPTP_ENABLE - struct net_device *in; - - /* -@@ -1367,6 +1368,7 @@ bool ecm_interface_is_pptp(struct sk_buf - } - - dev_put(in); -+#endif - return false; - } - -@@ -1379,6 +1381,7 @@ bool ecm_interface_is_pptp(struct sk_buf - */ - bool ecm_interface_is_l2tp_packet_by_version(struct sk_buff *skb, const struct net_device *out, int ver) - { -+#ifdef ECM_INTERFACE_L2TPV2_PPTP_ENABLE - uint32_t flag = 0; - struct net_device *in; - -@@ -1411,6 +1414,7 @@ bool ecm_interface_is_l2tp_packet_by_ver - } - - dev_put(in); -+#endif - return false; - } - -@@ -1423,6 +1427,7 @@ bool ecm_interface_is_l2tp_packet_by_ver - */ - bool ecm_interface_is_l2tp_pptp(struct sk_buff *skb, const struct net_device *out) - { -+#ifdef ECM_INTERFACE_L2TPV2_PPTP_ENABLE - struct net_device *in; - - /* -@@ -1445,6 +1450,7 @@ bool ecm_interface_is_l2tp_pptp(struct s - } - - dev_put(in); -+#endif - return false; - } - -@@ -6630,6 +6636,7 @@ static void ecm_interface_regenerate_con - return; - } - -+#ifdef ECM_DB_XREF_ENABLE - for (dir = 0; dir < ECM_DB_OBJ_DIR_MAX; dir++) { - /* - * Re-generate all connections associated with this interface -@@ -6645,6 +6652,7 @@ static void ecm_interface_regenerate_con - ci[dir] = cin; - } - } -+#endif - - #ifdef ECM_MULTICAST_ENABLE - /* ---- a/frontends/ecm_front_end_common.c -+++ b/frontends/ecm_front_end_common.c -@@ -106,6 +106,7 @@ bool ecm_front_end_gre_proto_is_accel_al - struct nf_conntrack_tuple *tuple, - int ip_version) - { -+#ifdef ECM_INTERFACE_GRE_ENABLE - struct net_device *dev; - struct gre_base_hdr *greh; - -@@ -117,10 +118,12 @@ bool ecm_front_end_gre_proto_is_accel_al - /* - * Case 1: PPTP locally terminated - */ -+#ifdef ECM_INTERFACE_PPTP_ENABLE - if (ecm_interface_is_pptp(skb, outdev)) { - DEBUG_TRACE("%px: PPTP GRE locally terminated - allow acceleration\n", skb); - return true; - } -+#endif - - /* - * Case 2: PPTP pass through -@@ -223,6 +226,10 @@ bool ecm_front_end_gre_proto_is_accel_al - */ - DEBUG_TRACE("%px: GRE IPv%d pass through - allow acceleration\n", skb, ip_version); - return true; -+#else -+ DEBUG_TRACE("%px: GRE%d feature is disabled - do not allow acceleration\n", skb, ip_version); -+ return false; -+#endif - } - - #ifdef ECM_CLASSIFIER_DSCP_ENABLE diff --git a/qaa/nss/qca-nss-ecm-64/patches/100-kernel-5.10-support.patch b/qaa/nss/qca-nss-ecm-64/patches/100-kernel-5.10-support.patch deleted file mode 100644 index 107b9571b..000000000 --- a/qaa/nss/qca-nss-ecm-64/patches/100-kernel-5.10-support.patch +++ /dev/null @@ -1,831 +0,0 @@ -From e8b642c23af9146c973e828a7f4e0fb56cfc8d0b Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Sat, 15 May 2021 03:51:14 +0200 -Subject: [PATCH] add support for kernel 5.10 - -Signed-off-by: Ansuel Smith ---- - ecm_classifier_default.c | 24 +++--------- - ecm_classifier_dscp.c | 8 +--- - ecm_classifier_emesh.c | 16 ++------ - ecm_classifier_hyfi.c | 7 +--- - ecm_classifier_mark.c | 8 +--- - ecm_classifier_ovs.c | 8 +--- - ecm_classifier_pcc.c | 8 +--- - ecm_conntrack_notifier.c | 8 +--- - ecm_db/ecm_db_connection.c | 7 +--- - ecm_db/ecm_db_host.c | 7 +--- - ecm_db/ecm_db_iface.c | 7 +--- - ecm_db/ecm_db_mapping.c | 7 +--- - ecm_db/ecm_db_node.c | 7 +--- - ecm_interface.c | 4 +- - ecm_state.c | 14 ++----- - frontends/ecm_front_end_common.c | 4 +- - frontends/ecm_front_end_ipv4.c | 7 +--- - frontends/ecm_front_end_ipv6.c | 7 +--- - frontends/nss/ecm_nss_bond_notifier.c | 8 +--- - frontends/nss/ecm_nss_ipv4.c | 49 +++++++------------------ - frontends/nss/ecm_nss_ipv6.c | 49 +++++++------------------ - frontends/nss/ecm_nss_multicast_ipv4.c | 7 +--- - frontends/nss/ecm_nss_multicast_ipv6.c | 7 +--- - frontends/nss/ecm_nss_non_ported_ipv4.c | 7 +--- - frontends/nss/ecm_nss_non_ported_ipv6.c | 7 +--- - frontends/nss/ecm_nss_ported_ipv4.c | 8 +--- - frontends/nss/ecm_nss_ported_ipv6.c | 8 +--- - frontends/sfe/ecm_sfe_ipv4.c | 49 +++++++------------------ - frontends/sfe/ecm_sfe_ipv6.c | 49 +++++++------------------ - frontends/sfe/ecm_sfe_non_ported_ipv4.c | 7 +--- - frontends/sfe/ecm_sfe_non_ported_ipv6.c | 7 +--- - frontends/sfe/ecm_sfe_ported_ipv4.c | 8 +--- - frontends/sfe/ecm_sfe_ported_ipv6.c | 8 +--- - 33 files changed, 122 insertions(+), 314 deletions(-) - ---- a/ecm_classifier_default.c -+++ b/ecm_classifier_default.c -@@ -776,26 +776,14 @@ int ecm_classifier_default_init(struct d - return -1; - } - -- if (!debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_default_dentry, -- (u32 *)&ecm_classifier_default_enabled)) { -- DEBUG_ERROR("Failed to create ecm deafult classifier enabled file in debugfs\n"); -- debugfs_remove_recursive(ecm_classifier_default_dentry); -- return -1; -- } -+ debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_default_dentry, -+ (u32 *)&ecm_classifier_default_enabled); - -- if (!debugfs_create_u32("accel_mode", S_IRUGO | S_IWUSR, ecm_classifier_default_dentry, -- (u32 *)&ecm_classifier_default_accel_mode)) { -- DEBUG_ERROR("Failed to create ecm deafult classifier accel_mode file in debugfs\n"); -- debugfs_remove_recursive(ecm_classifier_default_dentry); -- return -1; -- } -+ debugfs_create_u32("accel_mode", S_IRUGO | S_IWUSR, ecm_classifier_default_dentry, -+ (u32 *)&ecm_classifier_default_accel_mode); - -- if (!debugfs_create_u32("accel_delay_pkts", S_IRUGO | S_IWUSR, ecm_classifier_default_dentry, -- (u32 *)&ecm_classifier_accel_delay_pkts)) { -- DEBUG_ERROR("Failed to create accel delay packet counts in debugfs\n"); -- debugfs_remove_recursive(ecm_classifier_default_dentry); -- return -1; -- } -+ debugfs_create_u32("accel_delay_pkts", S_IRUGO | S_IWUSR, ecm_classifier_default_dentry, -+ (u32 *)&ecm_classifier_accel_delay_pkts); - - return 0; - } ---- a/ecm_classifier_dscp.c -+++ b/ecm_classifier_dscp.c -@@ -747,12 +747,8 @@ int ecm_classifier_dscp_init(struct dent - return -1; - } - -- if (!debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_dscp_dentry, -- (u32 *)&ecm_classifier_dscp_enabled)) { -- DEBUG_ERROR("Failed to create dscp enabled file in debugfs\n"); -- debugfs_remove_recursive(ecm_classifier_dscp_dentry); -- return -1; -- } -+ debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_dscp_dentry, -+ (u32 *)&ecm_classifier_dscp_enabled); - - return 0; - } ---- a/ecm_classifier_emesh.c -+++ b/ecm_classifier_emesh.c -@@ -977,19 +977,11 @@ int ecm_classifier_emesh_init(struct den - return -1; - } - -- if (!debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_emesh_dentry, -- (u32 *)&ecm_classifier_emesh_enabled)) { -- DEBUG_ERROR("Failed to create ecm emesh classifier enabled file in debugfs\n"); -- debugfs_remove_recursive(ecm_classifier_emesh_dentry); -- return -1; -- } -+ debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_emesh_dentry, -+ (u32 *)&ecm_classifier_emesh_enabled); - -- if (!debugfs_create_u32("latency_config_enabled", S_IRUGO | S_IWUSR, ecm_classifier_emesh_dentry, -- (u32 *)&ecm_classifier_emesh_latency_config_enabled)) { -- DEBUG_ERROR("Failed to create ecm emesh classifier latency config enabled file in debugfs\n"); -- debugfs_remove_recursive(ecm_classifier_emesh_dentry); -- return -1; -- } -+ debugfs_create_u32("latency_config_enabled", S_IRUGO | S_IWUSR, ecm_classifier_emesh_dentry, -+ (u32 *)&ecm_classifier_emesh_latency_config_enabled); - - /* - * Register for service prioritization notification update. ---- a/ecm_classifier_hyfi.c -+++ b/ecm_classifier_hyfi.c -@@ -1099,11 +1099,8 @@ int ecm_classifier_hyfi_rules_init(struc - goto classifier_task_cleanup; - } - -- if (!debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_hyfi_dentry, -- (u32 *)&ecm_classifier_hyfi_enabled)) { -- DEBUG_ERROR("Failed to create ecm hyfi classifier enabled file in debugfs\n"); -- goto classifier_task_cleanup; -- } -+ debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_hyfi_dentry, -+ (u32 *)&ecm_classifier_hyfi_enabled); - - if (!debugfs_create_file("cmd", S_IWUSR, ecm_classifier_hyfi_dentry, - NULL, &ecm_classifier_hyfi_cmd_fops)) { ---- a/ecm_classifier_mark.c -+++ b/ecm_classifier_mark.c -@@ -753,12 +753,8 @@ int ecm_classifier_mark_init(struct dent - return -1; - } - -- if (!debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_mark_dentry, -- (u32 *)&ecm_classifier_mark_enabled)) { -- DEBUG_ERROR("Failed to create mark enabled file in debugfs\n"); -- debugfs_remove_recursive(ecm_classifier_mark_dentry); -- return -1; -- } -+ debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_mark_dentry, -+ (u32 *)&ecm_classifier_mark_enabled); - - return 0; - } ---- a/ecm_classifier_ovs.c -+++ b/ecm_classifier_ovs.c -@@ -2200,12 +2200,8 @@ int ecm_classifier_ovs_init(struct dentr - return -1; - } - -- if (!debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_ovs_dentry, -- (u32 *)&ecm_classifier_ovs_enabled)) { -- DEBUG_ERROR("Failed to create ovs enabled file in debugfs\n"); -- debugfs_remove_recursive(ecm_classifier_ovs_dentry); -- return -1; -- } -+ debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_ovs_dentry, -+ (u32 *)&ecm_classifier_ovs_enabled); - - return 0; - } ---- a/ecm_classifier_pcc.c -+++ b/ecm_classifier_pcc.c -@@ -1308,12 +1308,8 @@ int ecm_classifier_pcc_init(struct dentr - return -1; - } - -- if (!debugfs_create_u32("enabled", S_IRUGO, ecm_classifier_pcc_dentry, -- (u32 *)&ecm_classifier_pcc_enabled)) { -- DEBUG_ERROR("Failed to create pcc enabled file in debugfs\n"); -- debugfs_remove_recursive(ecm_classifier_pcc_dentry); -- return -1; -- } -+ debugfs_create_u32("enabled", S_IRUGO, ecm_classifier_pcc_dentry, -+ (u32 *)&ecm_classifier_pcc_enabled); - - return 0; - } ---- a/ecm_conntrack_notifier.c -+++ b/ecm_conntrack_notifier.c -@@ -414,12 +414,8 @@ int ecm_conntrack_notifier_init(struct d - return -1; - } - -- if (!debugfs_create_u32("stop", S_IRUGO | S_IWUSR, ecm_conntrack_notifier_dentry, -- (u32 *)&ecm_conntrack_notifier_stopped)) { -- DEBUG_ERROR("Failed to create ecm conntrack notifier stopped file in debugfs\n"); -- debugfs_remove_recursive(ecm_conntrack_notifier_dentry); -- return -1; -- } -+ debugfs_create_u32("stop", S_IRUGO | S_IWUSR, ecm_conntrack_notifier_dentry, -+ (u32 *)&ecm_conntrack_notifier_stopped); - - #ifdef CONFIG_NF_CONNTRACK_EVENTS - /* ---- a/ecm_db/ecm_db_connection.c -+++ b/ecm_db/ecm_db_connection.c -@@ -3642,11 +3642,8 @@ static struct file_operations ecm_db_con - */ - bool ecm_db_connection_init(struct dentry *dentry) - { -- if (!debugfs_create_u32("connection_count", S_IRUGO, dentry, -- (u32 *)&ecm_db_connection_count)) { -- DEBUG_ERROR("Failed to create ecm db connection count file in debugfs\n"); -- return false; -- } -+ debugfs_create_u32("connection_count", S_IRUGO, dentry, -+ (u32 *)&ecm_db_connection_count); - - if (!debugfs_create_file("connection_count_simple", S_IRUGO, dentry, - NULL, &ecm_db_connection_count_simple_fops)) { ---- a/ecm_db/ecm_db_host.c -+++ b/ecm_db/ecm_db_host.c -@@ -770,11 +770,8 @@ EXPORT_SYMBOL(ecm_db_host_alloc); - bool ecm_db_host_init(struct dentry *dentry) - { - -- if (!debugfs_create_u32("host_count", S_IRUGO, dentry, -- (u32 *)&ecm_db_host_count)) { -- DEBUG_ERROR("Failed to create ecm db host count file in debugfs\n"); -- return false;; -- } -+ debugfs_create_u32("host_count", S_IRUGO, dentry, -+ (u32 *)&ecm_db_host_count); - - ecm_db_host_table = vzalloc(sizeof(struct ecm_db_host_instance *) * ECM_DB_HOST_HASH_SLOTS); - if (!ecm_db_host_table) { ---- a/ecm_db/ecm_db_iface.c -+++ b/ecm_db/ecm_db_iface.c -@@ -3670,11 +3670,8 @@ EXPORT_SYMBOL(ecm_db_iface_alloc); - */ - bool ecm_db_iface_init(struct dentry *dentry) - { -- if (!debugfs_create_u32("iface_count", S_IRUGO, dentry, -- (u32 *)&ecm_db_iface_count)) { -- DEBUG_ERROR("Failed to create ecm db iface count file in debugfs\n"); -- return false; -- } -+ debugfs_create_u32("iface_count", S_IRUGO, dentry, -+ (u32 *)&ecm_db_iface_count); - - return true; - } ---- a/ecm_db/ecm_db_mapping.c -+++ b/ecm_db/ecm_db_mapping.c -@@ -806,11 +806,8 @@ EXPORT_SYMBOL(ecm_db_mapping_alloc); - */ - bool ecm_db_mapping_init(struct dentry *dentry) - { -- if (!debugfs_create_u32("mapping_count", S_IRUGO, dentry, -- (u32 *)&ecm_db_mapping_count)) { -- DEBUG_ERROR("Failed to create ecm db mapping count file in debugfs\n"); -- return false; -- } -+ debugfs_create_u32("mapping_count", S_IRUGO, dentry, -+ (u32 *)&ecm_db_mapping_count); - - ecm_db_mapping_table = vzalloc(sizeof(struct ecm_db_mapping_instance *) * ECM_DB_MAPPING_HASH_SLOTS); - if (!ecm_db_mapping_table) { ---- a/ecm_db/ecm_db_node.c -+++ b/ecm_db/ecm_db_node.c -@@ -1187,11 +1187,8 @@ keep_sni_conn: - */ - bool ecm_db_node_init(struct dentry *dentry) - { -- if (!debugfs_create_u32("node_count", S_IRUGO, dentry, -- (u32 *)&ecm_db_node_count)) { -- DEBUG_ERROR("Failed to create ecm db node count file in debugfs\n"); -- return false; -- } -+ debugfs_create_u32("node_count", S_IRUGO, dentry, -+ (u32 *)&ecm_db_node_count); - - ecm_db_node_table = vzalloc(sizeof(struct ecm_db_node_instance *) * ECM_DB_NODE_HASH_SLOTS); - if (!ecm_db_node_table) { ---- a/ecm_interface.c -+++ b/ecm_interface.c -@@ -332,7 +332,7 @@ static struct net_device *ecm_interface_ - struct net_device *dev; - - ECM_IP_ADDR_TO_NIN6_ADDR(addr6, addr); -- dev = (struct net_device *)ipv6_dev_find(&init_net, &addr6, 1); -+ dev = (struct net_device *)ipv6_dev_find_and_hold(&init_net, &addr6, 1); - return dev; - } - #endif -@@ -734,7 +734,7 @@ static bool ecm_interface_mac_addr_get_i - * Get the MAC address that corresponds to IP address given. - */ - ECM_IP_ADDR_TO_NIN6_ADDR(daddr, addr); -- local_dev = ipv6_dev_find(&init_net, &daddr, 1); -+ local_dev = ipv6_dev_find_and_hold(&init_net, &daddr, 1); - if (local_dev) { - DEBUG_TRACE("%pi6 is a local address\n", &daddr); - memcpy(mac_addr, dev->dev_addr, ETH_ALEN); ---- a/ecm_state.c -+++ b/ecm_state.c -@@ -899,17 +899,11 @@ int ecm_state_init(struct dentry *dentry - return -1; - } - -- if (!debugfs_create_u32("state_dev_major", S_IRUGO, ecm_state_dentry, -- (u32 *)&ecm_state_dev_major_id)) { -- DEBUG_ERROR("Failed to create ecm state dev major file in debugfs\n"); -- goto init_cleanup; -- } -+ debugfs_create_u32("state_dev_major", S_IRUGO, ecm_state_dentry, -+ (u32 *)&ecm_state_dev_major_id); - -- if (!debugfs_create_u32("state_file_output_mask", S_IRUGO | S_IWUSR, ecm_state_dentry, -- (u32 *)&ecm_state_file_output_mask)) { -- DEBUG_ERROR("Failed to create ecm state output mask file in debugfs\n"); -- goto init_cleanup; -- } -+ debugfs_create_u32("state_file_output_mask", S_IRUGO | S_IWUSR, ecm_state_dentry, -+ (u32 *)&ecm_state_file_output_mask); - - /* - * Register a char device that we will use to provide a dump of our state ---- a/frontends/ecm_front_end_common.c -+++ b/frontends/ecm_front_end_common.c -@@ -192,7 +192,7 @@ bool ecm_front_end_gre_proto_is_accel_al - return false; - } - } else { -- dev = ipv6_dev_find(&init_net, &(tuple->src.u3.in6), 1); -+ dev = ipv6_dev_find_and_hold(&init_net, &(tuple->src.u3.in6), 1); - if (dev) { - /* - * Source IP address is local -@@ -202,7 +202,7 @@ bool ecm_front_end_gre_proto_is_accel_al - return false; - } - -- dev = ipv6_dev_find(&init_net, &(tuple->dst.u3.in6), 1); -+ dev = ipv6_dev_find_and_hold(&init_net, &(tuple->dst.u3.in6), 1); - if (dev) { - /* - * Destination IP address is local ---- a/frontends/ecm_front_end_ipv4.c -+++ b/frontends/ecm_front_end_ipv4.c -@@ -376,11 +376,8 @@ void ecm_front_end_ipv4_stop(int num) - */ - int ecm_front_end_ipv4_init(struct dentry *dentry) - { -- if (!debugfs_create_u32("front_end_ipv4_stop", S_IRUGO | S_IWUSR, dentry, -- (u32 *)&ecm_front_end_ipv4_stopped)) { -- DEBUG_ERROR("Failed to create ecm front end ipv4 stop file in debugfs\n"); -- return -1; -- } -+ debugfs_create_u32("front_end_ipv4_stop", S_IRUGO | S_IWUSR, dentry, -+ (u32 *)&ecm_front_end_ipv4_stopped); - - switch (ecm_front_end_type_get()) { - case ECM_FRONT_END_TYPE_NSS: ---- a/frontends/ecm_front_end_ipv6.c -+++ b/frontends/ecm_front_end_ipv6.c -@@ -255,11 +255,8 @@ void ecm_front_end_ipv6_stop(int num) - */ - int ecm_front_end_ipv6_init(struct dentry *dentry) - { -- if (!debugfs_create_u32("front_end_ipv6_stop", S_IRUGO | S_IWUSR, dentry, -- (u32 *)&ecm_front_end_ipv6_stopped)) { -- DEBUG_ERROR("Failed to create ecm front end ipv6 stop file in debugfs\n"); -- return -1; -- } -+ debugfs_create_u32("front_end_ipv6_stop", S_IRUGO | S_IWUSR, dentry, -+ (u32 *)&ecm_front_end_ipv6_stopped); - - switch (ecm_front_end_type_get()) { - case ECM_FRONT_END_TYPE_NSS: ---- a/frontends/nss/ecm_nss_bond_notifier.c -+++ b/frontends/nss/ecm_nss_bond_notifier.c -@@ -240,12 +240,8 @@ int ecm_nss_bond_notifier_init(struct de - return -1; - } - -- if (!debugfs_create_u32("stop", S_IRUGO | S_IWUSR, ecm_nss_bond_notifier_dentry, -- (u32 *)&ecm_nss_bond_notifier_stopped)) { -- DEBUG_ERROR("Failed to create ecm bond notifier stopped file in debugfs\n"); -- debugfs_remove_recursive(ecm_nss_bond_notifier_dentry); -- return -1; -- } -+ debugfs_create_u32("stop", S_IRUGO | S_IWUSR, ecm_nss_bond_notifier_dentry, -+ (u32 *)&ecm_nss_bond_notifier_stopped); - - /* - * Register Link Aggregation callbacks with the bonding driver ---- a/frontends/nss/ecm_nss_ipv4.c -+++ b/frontends/nss/ecm_nss_ipv4.c -@@ -2802,41 +2802,23 @@ int ecm_nss_ipv4_init(struct dentry *den - return result; - } - -- if (!debugfs_create_u32("no_action_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, -- (u32 *)&ecm_nss_ipv4_no_action_limit_default)) { -- DEBUG_ERROR("Failed to create ecm nss ipv4 no_action_limit_default file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("no_action_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, -+ (u32 *)&ecm_nss_ipv4_no_action_limit_default); - -- if (!debugfs_create_u32("driver_fail_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, -- (u32 *)&ecm_nss_ipv4_driver_fail_limit_default)) { -- DEBUG_ERROR("Failed to create ecm nss ipv4 driver_fail_limit_default file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("driver_fail_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, -+ (u32 *)&ecm_nss_ipv4_driver_fail_limit_default); - -- if (!debugfs_create_u32("nack_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, -- (u32 *)&ecm_nss_ipv4_nack_limit_default)) { -- DEBUG_ERROR("Failed to create ecm nss ipv4 nack_limit_default file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("nack_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, -+ (u32 *)&ecm_nss_ipv4_nack_limit_default); - -- if (!debugfs_create_u32("accelerated_count", S_IRUGO, ecm_nss_ipv4_dentry, -- (u32 *)&ecm_nss_ipv4_accelerated_count)) { -- DEBUG_ERROR("Failed to create ecm nss ipv4 accelerated_count file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("accelerated_count", S_IRUGO, ecm_nss_ipv4_dentry, -+ (u32 *)&ecm_nss_ipv4_accelerated_count); - -- if (!debugfs_create_u32("pending_accel_count", S_IRUGO, ecm_nss_ipv4_dentry, -- (u32 *)&ecm_nss_ipv4_pending_accel_count)) { -- DEBUG_ERROR("Failed to create ecm nss ipv4 pending_accel_count file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("pending_accel_count", S_IRUGO, ecm_nss_ipv4_dentry, -+ (u32 *)&ecm_nss_ipv4_pending_accel_count); - -- if (!debugfs_create_u32("pending_decel_count", S_IRUGO, ecm_nss_ipv4_dentry, -- (u32 *)&ecm_nss_ipv4_pending_decel_count)) { -- DEBUG_ERROR("Failed to create ecm nss ipv4 pending_decel_count file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("pending_decel_count", S_IRUGO, ecm_nss_ipv4_dentry, -+ (u32 *)&ecm_nss_ipv4_pending_decel_count); - - if (!debugfs_create_file("accel_limit_mode", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, - NULL, &ecm_nss_ipv4_accel_limit_mode_fops)) { -@@ -2867,11 +2849,8 @@ int ecm_nss_ipv4_init(struct dentry *den - goto task_cleanup; - } - -- if (!debugfs_create_u32("vlan_passthrough_set", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, -- (u32 *)&ecm_nss_ipv4_vlan_passthrough_enable)) { -- DEBUG_ERROR("Failed to create ecm nss ipv4 vlan passthrough file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("vlan_passthrough_set", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, -+ (u32 *)&ecm_nss_ipv4_vlan_passthrough_enable); - - #ifdef ECM_NON_PORTED_SUPPORT_ENABLE - if (!ecm_nss_non_ported_ipv4_debugfs_init(ecm_nss_ipv4_dentry)) { ---- a/frontends/nss/ecm_nss_ipv6.c -+++ b/frontends/nss/ecm_nss_ipv6.c -@@ -2542,41 +2542,23 @@ int ecm_nss_ipv6_init(struct dentry *den - return result; - } - -- if (!debugfs_create_u32("no_action_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, -- (u32 *)&ecm_nss_ipv6_no_action_limit_default)) { -- DEBUG_ERROR("Failed to create ecm nss ipv6 no_action_limit_default file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("no_action_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, -+ (u32 *)&ecm_nss_ipv6_no_action_limit_default); - -- if (!debugfs_create_u32("driver_fail_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, -- (u32 *)&ecm_nss_ipv6_driver_fail_limit_default)) { -- DEBUG_ERROR("Failed to create ecm nss ipv6 driver_fail_limit_default file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("driver_fail_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, -+ (u32 *)&ecm_nss_ipv6_driver_fail_limit_default); - -- if (!debugfs_create_u32("nack_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, -- (u32 *)&ecm_nss_ipv6_nack_limit_default)) { -- DEBUG_ERROR("Failed to create ecm nss ipv6 nack_limit_default file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("nack_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, -+ (u32 *)&ecm_nss_ipv6_nack_limit_default); - -- if (!debugfs_create_u32("accelerated_count", S_IRUGO, ecm_nss_ipv6_dentry, -- (u32 *)&ecm_nss_ipv6_accelerated_count)) { -- DEBUG_ERROR("Failed to create ecm nss ipv6 accelerated_count file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("accelerated_count", S_IRUGO, ecm_nss_ipv6_dentry, -+ (u32 *)&ecm_nss_ipv6_accelerated_count); - -- if (!debugfs_create_u32("pending_accel_count", S_IRUGO, ecm_nss_ipv6_dentry, -- (u32 *)&ecm_nss_ipv6_pending_accel_count)) { -- DEBUG_ERROR("Failed to create ecm nss ipv6 pending_accel_count file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("pending_accel_count", S_IRUGO, ecm_nss_ipv6_dentry, -+ (u32 *)&ecm_nss_ipv6_pending_accel_count); - -- if (!debugfs_create_u32("pending_decel_count", S_IRUGO, ecm_nss_ipv6_dentry, -- (u32 *)&ecm_nss_ipv6_pending_decel_count)) { -- DEBUG_ERROR("Failed to create ecm nss ipv6 pending_decel_count file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("pending_decel_count", S_IRUGO, ecm_nss_ipv6_dentry, -+ (u32 *)&ecm_nss_ipv6_pending_decel_count); - - if (!debugfs_create_file("accel_limit_mode", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, - NULL, &ecm_nss_ipv6_accel_limit_mode_fops)) { -@@ -2607,11 +2589,8 @@ int ecm_nss_ipv6_init(struct dentry *den - goto task_cleanup; - } - -- if (!debugfs_create_u32("vlan_passthrough_set", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, -- (u32 *)&ecm_nss_ipv6_vlan_passthrough_enable)) { -- DEBUG_ERROR("Failed to create ecm nss ipv6 vlan passthrough file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("vlan_passthrough_set", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, -+ (u32 *)&ecm_nss_ipv6_vlan_passthrough_enable); - - #ifdef ECM_NON_PORTED_SUPPORT_ENABLE - if (!ecm_nss_non_ported_ipv6_debugfs_init(ecm_nss_ipv6_dentry)) { ---- a/frontends/nss/ecm_nss_multicast_ipv4.c -+++ b/frontends/nss/ecm_nss_multicast_ipv4.c -@@ -4139,11 +4139,8 @@ void ecm_nss_multicast_ipv4_stop(int num - */ - int ecm_nss_multicast_ipv4_init(struct dentry *dentry) - { -- if (!debugfs_create_u32("ecm_nss_multicast_ipv4_stop", S_IRUGO | S_IWUSR, dentry, -- (u32 *)&ecm_front_end_ipv4_mc_stopped)) { -- DEBUG_ERROR("Failed to create ecm front end ipv4 mc stop file in debugfs\n"); -- return -1; -- } -+ debugfs_create_u32("ecm_nss_multicast_ipv4_stop", S_IRUGO | S_IWUSR, dentry, -+ (u32 *)&ecm_front_end_ipv4_mc_stopped); - - /* - * Register multicast update callback to MCS snooper ---- a/frontends/nss/ecm_nss_multicast_ipv6.c -+++ b/frontends/nss/ecm_nss_multicast_ipv6.c -@@ -3939,11 +3939,8 @@ void ecm_nss_multicast_ipv6_stop(int num - */ - int ecm_nss_multicast_ipv6_init(struct dentry *dentry) - { -- if (!debugfs_create_u32("ecm_nss_multicast_ipv6_stop", S_IRUGO | S_IWUSR, dentry, -- (u32 *)&ecm_front_end_ipv6_mc_stopped)) { -- DEBUG_ERROR("Failed to create ecm front end ipv6 mc stop file in debugfs\n"); -- return -1; -- } -+ debugfs_create_u32("ecm_nss_multicast_ipv6_stop", S_IRUGO | S_IWUSR, dentry, -+ (u32 *)&ecm_front_end_ipv6_mc_stopped); - - /* - * Register multicast update callback to MCS snooper ---- a/frontends/nss/ecm_nss_non_ported_ipv4.c -+++ b/frontends/nss/ecm_nss_non_ported_ipv4.c -@@ -2615,11 +2615,8 @@ done: - */ - bool ecm_nss_non_ported_ipv4_debugfs_init(struct dentry *dentry) - { -- if (!debugfs_create_u32("non_ported_accelerated_count", S_IRUGO, dentry, -- (u32 *)&ecm_nss_non_ported_ipv4_accelerated_count)) { -- DEBUG_ERROR("Failed to create ecm nss ipv4 non_ported_accelerated_count file in debugfs\n"); -- return false; -- } -+ debugfs_create_u32("non_ported_accelerated_count", S_IRUGO, dentry, -+ (u32 *)&ecm_nss_non_ported_ipv4_accelerated_count); - - return true; - } ---- a/frontends/nss/ecm_nss_non_ported_ipv6.c -+++ b/frontends/nss/ecm_nss_non_ported_ipv6.c -@@ -2329,11 +2329,8 @@ done: - */ - bool ecm_nss_non_ported_ipv6_debugfs_init(struct dentry *dentry) - { -- if (!debugfs_create_u32("non_ported_accelerated_count", S_IRUGO, dentry, -- (u32 *)&ecm_nss_non_ported_ipv6_accelerated_count)) { -- DEBUG_ERROR("Failed to create ecm nss ipv6 non_ported_accelerated_count file in debugfs\n"); -- return false; -- } -+ debugfs_create_u32("non_ported_accelerated_count", S_IRUGO, dentry, -+ (u32 *)&ecm_nss_non_ported_ipv6_accelerated_count); - - return true; - } ---- a/frontends/nss/ecm_nss_ported_ipv4.c -+++ b/frontends/nss/ecm_nss_ported_ipv4.c -@@ -2944,12 +2944,8 @@ bool ecm_nss_ported_ipv4_debugfs_init(st - return false; - } - -- if (!debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, -- &ecm_nss_ported_ipv4_accelerated_count[ECM_NSS_PORTED_IPV4_PROTO_TCP])) { -- DEBUG_ERROR("Failed to create ecm nss ipv4 tcp_accelerated_count file in debugfs\n"); -- debugfs_remove(udp_dentry); -- return false; -- } -+ debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, -+ &ecm_nss_ported_ipv4_accelerated_count[ECM_NSS_PORTED_IPV4_PROTO_TCP]); - - return true; - } ---- a/frontends/nss/ecm_nss_ported_ipv6.c -+++ b/frontends/nss/ecm_nss_ported_ipv6.c -@@ -2732,12 +2732,8 @@ bool ecm_nss_ported_ipv6_debugfs_init(st - return false; - } - -- if (!debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, -- &ecm_nss_ported_ipv6_accelerated_count[ECM_NSS_PORTED_IPV6_PROTO_TCP])) { -- DEBUG_ERROR("Failed to create ecm nss ipv6 tcp_accelerated_count file in debugfs\n"); -- debugfs_remove(udp_dentry); -- return false; -- } -+ debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, -+ &ecm_nss_ported_ipv6_accelerated_count[ECM_NSS_PORTED_IPV6_PROTO_TCP]); - - return true; - } ---- a/frontends/sfe/ecm_sfe_ipv4.c -+++ b/frontends/sfe/ecm_sfe_ipv4.c -@@ -1808,48 +1808,27 @@ int ecm_sfe_ipv4_init(struct dentry *den - } - - #ifdef CONFIG_XFRM -- if (!debugfs_create_u32("reject_acceleration_for_ipsec", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, -- (u32 *)&ecm_sfe_ipv4_reject_acceleration_for_ipsec)) { -- DEBUG_ERROR("Failed to create ecm sfe ipv4 reject_acceleration_for_ipsec file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("reject_acceleration_for_ipsec", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, -+ (u32 *)&ecm_sfe_ipv4_reject_acceleration_for_ipsec); - #endif - -- if (!debugfs_create_u32("no_action_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, -- (u32 *)&ecm_sfe_ipv4_no_action_limit_default)) { -- DEBUG_ERROR("Failed to create ecm sfe ipv4 no_action_limit_default file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("no_action_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, -+ (u32 *)&ecm_sfe_ipv4_no_action_limit_default); - -- if (!debugfs_create_u32("driver_fail_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, -- (u32 *)&ecm_sfe_ipv4_driver_fail_limit_default)) { -- DEBUG_ERROR("Failed to create ecm sfe ipv4 driver_fail_limit_default file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("driver_fail_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, -+ (u32 *)&ecm_sfe_ipv4_driver_fail_limit_default); - -- if (!debugfs_create_u32("nack_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, -- (u32 *)&ecm_sfe_ipv4_nack_limit_default)) { -- DEBUG_ERROR("Failed to create ecm sfe ipv4 nack_limit_default file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("nack_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, -+ (u32 *)&ecm_sfe_ipv4_nack_limit_default); - -- if (!debugfs_create_u32("accelerated_count", S_IRUGO, ecm_sfe_ipv4_dentry, -- (u32 *)&ecm_sfe_ipv4_accelerated_count)) { -- DEBUG_ERROR("Failed to create ecm sfe ipv4 accelerated_count file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("accelerated_count", S_IRUGO, ecm_sfe_ipv4_dentry, -+ (u32 *)&ecm_sfe_ipv4_accelerated_count); - -- if (!debugfs_create_u32("pending_accel_count", S_IRUGO, ecm_sfe_ipv4_dentry, -- (u32 *)&ecm_sfe_ipv4_pending_accel_count)) { -- DEBUG_ERROR("Failed to create ecm sfe ipv4 pending_accel_count file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("pending_accel_count", S_IRUGO, ecm_sfe_ipv4_dentry, -+ (u32 *)&ecm_sfe_ipv4_pending_accel_count); - -- if (!debugfs_create_u32("pending_decel_count", S_IRUGO, ecm_sfe_ipv4_dentry, -- (u32 *)&ecm_sfe_ipv4_pending_decel_count)) { -- DEBUG_ERROR("Failed to create ecm sfe ipv4 pending_decel_count file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("pending_decel_count", S_IRUGO, ecm_sfe_ipv4_dentry, -+ (u32 *)&ecm_sfe_ipv4_pending_decel_count); - - if (!debugfs_create_file("accel_limit_mode", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, - NULL, &ecm_sfe_ipv4_accel_limit_mode_fops)) { ---- a/frontends/sfe/ecm_sfe_ipv6.c -+++ b/frontends/sfe/ecm_sfe_ipv6.c -@@ -1532,48 +1532,27 @@ int ecm_sfe_ipv6_init(struct dentry *den - } - - #ifdef CONFIG_XFRM -- if (!debugfs_create_u32("reject_acceleration_for_ipsec", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, -- (u32 *)&ecm_sfe_ipv6_reject_acceleration_for_ipsec)) { -- DEBUG_ERROR("Failed to create ecm sfe ipv6 reject_acceleration_for_ipsec file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("reject_acceleration_for_ipsec", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, -+ (u32 *)&ecm_sfe_ipv6_reject_acceleration_for_ipsec); - #endif - -- if (!debugfs_create_u32("no_action_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, -- (u32 *)&ecm_sfe_ipv6_no_action_limit_default)) { -- DEBUG_ERROR("Failed to create ecm sfe ipv6 no_action_limit_default file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("no_action_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, -+ (u32 *)&ecm_sfe_ipv6_no_action_limit_default); - -- if (!debugfs_create_u32("driver_fail_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, -- (u32 *)&ecm_sfe_ipv6_driver_fail_limit_default)) { -- DEBUG_ERROR("Failed to create ecm sfe ipv6 driver_fail_limit_default file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("driver_fail_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, -+ (u32 *)&ecm_sfe_ipv6_driver_fail_limit_default); - -- if (!debugfs_create_u32("nack_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, -- (u32 *)&ecm_sfe_ipv6_nack_limit_default)) { -- DEBUG_ERROR("Failed to create ecm sfe ipv6 nack_limit_default file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("nack_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, -+ (u32 *)&ecm_sfe_ipv6_nack_limit_default); - -- if (!debugfs_create_u32("accelerated_count", S_IRUGO, ecm_sfe_ipv6_dentry, -- (u32 *)&ecm_sfe_ipv6_accelerated_count)) { -- DEBUG_ERROR("Failed to create ecm sfe ipv6 accelerated_count file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("accelerated_count", S_IRUGO, ecm_sfe_ipv6_dentry, -+ (u32 *)&ecm_sfe_ipv6_accelerated_count); - -- if (!debugfs_create_u32("pending_accel_count", S_IRUGO, ecm_sfe_ipv6_dentry, -- (u32 *)&ecm_sfe_ipv6_pending_accel_count)) { -- DEBUG_ERROR("Failed to create ecm sfe ipv6 pending_accel_count file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("pending_accel_count", S_IRUGO, ecm_sfe_ipv6_dentry, -+ (u32 *)&ecm_sfe_ipv6_pending_accel_count); - -- if (!debugfs_create_u32("pending_decel_count", S_IRUGO, ecm_sfe_ipv6_dentry, -- (u32 *)&ecm_sfe_ipv6_pending_decel_count)) { -- DEBUG_ERROR("Failed to create ecm sfe ipv6 pending_decel_count file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("pending_decel_count", S_IRUGO, ecm_sfe_ipv6_dentry, -+ (u32 *)&ecm_sfe_ipv6_pending_decel_count); - - if (!debugfs_create_file("accel_limit_mode", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, - NULL, &ecm_sfe_ipv6_accel_limit_mode_fops)) { ---- a/frontends/sfe/ecm_sfe_non_ported_ipv4.c -+++ b/frontends/sfe/ecm_sfe_non_ported_ipv4.c -@@ -2284,11 +2284,8 @@ done: - */ - bool ecm_sfe_non_ported_ipv4_debugfs_init(struct dentry *dentry) - { -- if (!debugfs_create_u32("non_ported_accelerated_count", S_IRUGO, dentry, -- (u32 *)&ecm_sfe_non_ported_ipv4_accelerated_count)) { -- DEBUG_ERROR("Failed to create ecm sfe ipv4 non_ported_accelerated_count file in debugfs\n"); -- return false; -- } -+ debugfs_create_u32("non_ported_accelerated_count", S_IRUGO, dentry, -+ (u32 *)&ecm_sfe_non_ported_ipv4_accelerated_count); - - return true; - } ---- a/frontends/sfe/ecm_sfe_non_ported_ipv6.c -+++ b/frontends/sfe/ecm_sfe_non_ported_ipv6.c -@@ -2083,11 +2083,8 @@ done: - */ - bool ecm_sfe_non_ported_ipv6_debugfs_init(struct dentry *dentry) - { -- if (!debugfs_create_u32("non_ported_accelerated_count", S_IRUGO, dentry, -- (u32 *)&ecm_sfe_non_ported_ipv6_accelerated_count)) { -- DEBUG_ERROR("Failed to create ecm sfe ipv6 non_ported_accelerated_count file in debugfs\n"); -- return false; -- } -+ debugfs_create_u32("non_ported_accelerated_count", S_IRUGO, dentry, -+ (u32 *)&ecm_sfe_non_ported_ipv6_accelerated_count); - - return true; - } ---- a/frontends/sfe/ecm_sfe_ported_ipv4.c -+++ b/frontends/sfe/ecm_sfe_ported_ipv4.c -@@ -2528,12 +2528,8 @@ bool ecm_sfe_ported_ipv4_debugfs_init(st - return false; - } - -- if (!debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, -- &ecm_sfe_ported_ipv4_accelerated_count[ECM_SFE_PORTED_IPV4_PROTO_TCP])) { -- DEBUG_ERROR("Failed to create ecm sfe ipv4 tcp_accelerated_count file in debugfs\n"); -- debugfs_remove(udp_dentry); -- return false; -- } -+ debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, -+ &ecm_sfe_ported_ipv4_accelerated_count[ECM_SFE_PORTED_IPV4_PROTO_TCP]); - - return true; - } ---- a/frontends/sfe/ecm_sfe_ported_ipv6.c -+++ b/frontends/sfe/ecm_sfe_ported_ipv6.c -@@ -2374,12 +2374,8 @@ bool ecm_sfe_ported_ipv6_debugfs_init(st - return false; - } - -- if (!debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, -- &ecm_sfe_ported_ipv6_accelerated_count[ECM_SFE_PORTED_IPV6_PROTO_TCP])) { -- DEBUG_ERROR("Failed to create ecm sfe ipv6 tcp_accelerated_count file in debugfs\n"); -- debugfs_remove(udp_dentry); -- return false; -- } -+ debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, -+ &ecm_sfe_ported_ipv6_accelerated_count[ECM_SFE_PORTED_IPV6_PROTO_TCP]); - - return true; - } diff --git a/qaa/nss/qca-nss-ecm-64/patches/203-rework-nfct-notification.patch b/qaa/nss/qca-nss-ecm-64/patches/203-rework-nfct-notification.patch deleted file mode 100644 index 72005cd70..000000000 --- a/qaa/nss/qca-nss-ecm-64/patches/203-rework-nfct-notification.patch +++ /dev/null @@ -1,25 +0,0 @@ ---- a/ecm_conntrack_notifier.c -+++ b/ecm_conntrack_notifier.c -@@ -421,7 +421,11 @@ int ecm_conntrack_notifier_init(struct d - /* - * Eventing subsystem is available so we register a notifier hook to get fast notifications of expired connections - */ -+#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS -+ result = nf_conntrack_register_chain_notifier(&init_net, &ecm_conntrack_notifier); -+#else - result = nf_conntrack_register_notifier(&init_net, &ecm_conntrack_notifier); -+#endif - if (result < 0) { - DEBUG_ERROR("Can't register nf notifier hook.\n"); - debugfs_remove_recursive(ecm_conntrack_notifier_dentry); -@@ -439,7 +443,9 @@ EXPORT_SYMBOL(ecm_conntrack_notifier_ini - void ecm_conntrack_notifier_exit(void) - { - DEBUG_INFO("ECM Conntrack Notifier exit\n"); --#ifdef CONFIG_NF_CONNTRACK_EVENTS -+#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS -+ nf_conntrack_unregister_chain_notifier(&init_net, &ecm_conntrack_notifier); -+#else - nf_conntrack_unregister_notifier(&init_net, &ecm_conntrack_notifier); - #endif - /* diff --git a/qaa/nss/qca-nss-ecm-64/patches/204-More-compile-fixes.patch b/qaa/nss/qca-nss-ecm-64/patches/204-More-compile-fixes.patch deleted file mode 100644 index a998d8295..000000000 --- a/qaa/nss/qca-nss-ecm-64/patches/204-More-compile-fixes.patch +++ /dev/null @@ -1,58 +0,0 @@ -From e6d701c0d454d841366c556b2ef07a5203ffb35d Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Fri, 21 May 2021 21:41:31 +0200 -Subject: [PATCH] More compile fixes - -More runtime compile fixes. - -Signed-off-by: Robert Marko ---- - frontends/nss/ecm_nss_ported_ipv4.c | 12 +++--------- - frontends/nss/ecm_nss_ported_ipv6.c | 12 +++--------- - 2 files changed, 6 insertions(+), 18 deletions(-) - -diff --git a/frontends/nss/ecm_nss_ported_ipv4.c b/frontends/nss/ecm_nss_ported_ipv4.c -index 3522f0f..7f5fcd1 100644 ---- a/frontends/nss/ecm_nss_ported_ipv4.c -+++ b/frontends/nss/ecm_nss_ported_ipv4.c -@@ -2935,14 +2935,8 @@ done: - */ - bool ecm_nss_ported_ipv4_debugfs_init(struct dentry *dentry) - { -- struct dentry *udp_dentry; -- -- udp_dentry = debugfs_create_u32("udp_accelerated_count", S_IRUGO, dentry, -+ debugfs_create_u32("udp_accelerated_count", S_IRUGO, dentry, - &ecm_nss_ported_ipv4_accelerated_count[ECM_NSS_PORTED_IPV4_PROTO_UDP]); -- if (!udp_dentry) { -- DEBUG_ERROR("Failed to create ecm nss ipv4 udp_accelerated_count file in debugfs\n"); -- return false; -- } - - debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, - &ecm_nss_ported_ipv4_accelerated_count[ECM_NSS_PORTED_IPV4_PROTO_TCP]); -diff --git a/frontends/nss/ecm_nss_ported_ipv6.c b/frontends/nss/ecm_nss_ported_ipv6.c -index f43ac95..e0f779c 100644 ---- a/frontends/nss/ecm_nss_ported_ipv6.c -+++ b/frontends/nss/ecm_nss_ported_ipv6.c - /* - * ecm_nss_ported_ipv6_connection_callback() -@@ -2723,14 +2723,8 @@ done: - */ - bool ecm_nss_ported_ipv6_debugfs_init(struct dentry *dentry) - { -- struct dentry *udp_dentry; -- -- udp_dentry = debugfs_create_u32("udp_accelerated_count", S_IRUGO, dentry, -+ debugfs_create_u32("udp_accelerated_count", S_IRUGO, dentry, - &ecm_nss_ported_ipv6_accelerated_count[ECM_NSS_PORTED_IPV6_PROTO_UDP]); -- if (!udp_dentry) { -- DEBUG_ERROR("Failed to create ecm nss ipv6 udp_accelerated_count file in debugfs\n"); -- return false; -- } - - debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, - &ecm_nss_ported_ipv6_accelerated_count[ECM_NSS_PORTED_IPV6_PROTO_TCP]); --- -2.31.1 - diff --git a/qaa/nss/qca-nss-ecm-64/patches/205-resolve-high-load.patch b/qaa/nss/qca-nss-ecm-64/patches/205-resolve-high-load.patch deleted file mode 100644 index f4106a355..000000000 --- a/qaa/nss/qca-nss-ecm-64/patches/205-resolve-high-load.patch +++ /dev/null @@ -1,61 +0,0 @@ -From 6924b71ed809b37fffd74d6428a8ca83e5919746 Mon Sep 17 00:00:00 2001 -From: Dirk Buchwalder -Date: Sun, 27 Jun 2021 16:52:39 +0200 -Subject: [PATCH] qca-nss-ecm: resolve the cpu high load regarding ecm - -If using ECM, cpu load goes up (around 1.0) and stucks there. -This is due to using uninterruptible sleep function, -the patch changes this to interruptible sleep function. - -Signed-off-by: Dirk Buchwalder buchwalder@posteo.de ---- - frontends/nss/ecm_nss_ipv4.c | 4 ++-- - frontends/nss/ecm_nss_ipv6.c | 4 ++-- - 2 files changed, 4 insertions(+), 4 deletions(-) - -diff --git a/frontends/nss/ecm_nss_ipv4.c b/frontends/nss/ecm_nss_ipv4.c -index e00553c..94b39cd 100644 ---- a/frontends/nss/ecm_nss_ipv4.c -+++ b/frontends/nss/ecm_nss_ipv4.c -@@ -2471,7 +2471,7 @@ static void ecm_nss_ipv4_stats_sync_req_work(struct work_struct *work) - } - spin_unlock_bh(&ecm_nss_ipv4_lock); - -- usleep_range(ECM_NSS_IPV4_STATS_SYNC_UDELAY - 100, ECM_NSS_IPV4_STATS_SYNC_UDELAY); -+ msleep_interruptible(ECM_NSS_IPV4_STATS_SYNC_UDELAY / 1000); - - /* - * If index is 0, we are starting a new round, but if we still have time remain -@@ -2485,7 +2485,7 @@ static void ecm_nss_ipv4_stats_sync_req_work(struct work_struct *work) - } - - if (time_after(ecm_nss_ipv4_next_req_time, current_jiffies)) { -- msleep(jiffies_to_msecs(ecm_nss_ipv4_next_req_time - current_jiffies)); -+ msleep_interruptible(jiffies_to_msecs(ecm_nss_ipv4_next_req_time - current_jiffies)); - } - ecm_nss_ipv4_roll_check_jiffies = jiffies; - ecm_nss_ipv4_next_req_time = ecm_nss_ipv4_roll_check_jiffies + ECM_NSS_IPV4_STATS_SYNC_PERIOD; -diff --git a/frontends/nss/ecm_nss_ipv6.c b/frontends/nss/ecm_nss_ipv6.c -index 82e739f..30af050 100644 ---- a/frontends/nss/ecm_nss_ipv6.c -+++ b/frontends/nss/ecm_nss_ipv6.c -@@ -2210,7 +2210,7 @@ static void ecm_nss_ipv6_stats_sync_req_work(struct work_struct *work) - } - spin_unlock_bh(&ecm_nss_ipv6_lock); - -- usleep_range(ECM_NSS_IPV6_STATS_SYNC_UDELAY - 100, ECM_NSS_IPV6_STATS_SYNC_UDELAY); -+ msleep_interruptible(ECM_NSS_IPV6_STATS_SYNC_UDELAY / 1000); - - /* - * If index is 0, we are starting a new round, but if we still have time remain -@@ -2224,7 +2224,7 @@ static void ecm_nss_ipv6_stats_sync_req_work(struct work_struct *work) - } - - if (time_after(ecm_nss_ipv6_next_req_time, current_jiffies)) { -- msleep(jiffies_to_msecs(ecm_nss_ipv6_next_req_time - current_jiffies)); -+ msleep_interruptible(jiffies_to_msecs(ecm_nss_ipv6_next_req_time - current_jiffies)); - } - ecm_nss_ipv6_roll_check_jiffies = jiffies; - ecm_nss_ipv6_next_req_time = ecm_nss_ipv6_roll_check_jiffies + ECM_NSS_IPV6_STATS_SYNC_PERIOD; --- -2.31.1 diff --git a/qaa/nss/qca-nss-ecm/Makefile b/qaa/nss/qca-nss-ecm/Makefile deleted file mode 100644 index 0053ff12e..000000000 --- a/qaa/nss/qca-nss-ecm/Makefile +++ /dev/null @@ -1,278 +0,0 @@ -include $(TOPDIR)/rules.mk -include $(INCLUDE_DIR)/kernel.mk - -PKG_NAME:=qca-nss-ecm -PKG_RELEASE:=1 - -PKG_SOURCE_URL:=https://source.codeaurora.org/quic/qsdk/oss/lklm/qca-nss-ecm -PKG_SOURCE_PROTO:=git -PKG_SOURCE_VERSION:=9228212b4238c0d8c296f795948ede8f2ca0242e -PKG_MIRROR_HASH:=02fe4c86c8c88fb15704b1b253ab756a2658f24ce5db64a7909cb60bf9c1cdff - -LOCAL_VARIANT=$(patsubst qca-nss-ecm-%,%,$(patsubst qca-nss-ecm-%,%,$(BUILD_VARIANT))) -include $(INCLUDE_DIR)/package.mk - -ifeq ($(CONFIG_QCA_NSS_ECM_EXAMPLES_PCC),y) - FILES_EXAMPLES=$(PKG_BUILD_DIR)/examples/ecm_pcc_test.ko -endif - -ifeq ($(CONFIG_QCA_NSS_ECM_EXAMPLES_MARK),y) - FILES_EXAMPLES+=$(PKG_BUILD_DIR)/examples/ecm_mark_test.ko -endif - -#Explicitly enable OVS external module, if ovsmgr is enabled. -ifneq ($(CONFIG_PACKAGE_kmod-qca-ovsmgr),) -CONFIG_QCA_NSS_ECM_OVS=y -endif - -ifeq ($(CONFIG_QCA_NSS_ECM_OVS),y) - FILES_EXAMPLES+=$(PKG_BUILD_DIR)/examples/ecm_ovs.ko -endif - -define KernelPackage/qca-nss-ecm/Default - SECTION:=kernel - CATEGORY:=Kernel modules - SUBMENU:=Network Support - DEPENDS:=+TARGET_ipq806x:kmod-qca-nss-drv \ - +TARGET_ipq_ipq806x:kmod-qca-nss-drv \ - +TARGET_ipq_ipq807x:kmod-qca-nss-drv \ - +TARGET_ipq_ipq807x_64:kmod-qca-nss-drv \ - +TARGET_ipq807x:kmod-qca-nss-drv \ - +TARGET_ipq807x_64:kmod-qca-nss-drv \ - +TARGET_ipq_ipq60xx:kmod-qca-nss-drv \ - +TARGET_ipq_ipq60xx_64:kmod-qca-nss-drv \ - +TARGET_ipq_ipq50xx:kmod-qca-nss-drv \ - +TARGET_ipq_ipq50xx_64:kmod-qca-nss-drv \ - +iptables-mod-extra +kmod-ipt-conntrack \ - +kmod-pppoe @LINUX_5_4 \ - +kmod-ipsec - TITLE:=QCA NSS Enhanced Connection Manager (ECM) - FILES:=$(PKG_BUILD_DIR)/*.ko $(FILES_EXAMPLES) - KCONFIG:=CONFIG_BRIDGE_NETFILTER=y \ - CONFIG_NF_CONNTRACK_EVENTS=y \ - CONFIG_NF_CONNTRACK_CHAIN_EVENTS=y \ - CONFIG_NF_CONNTRACK_DSCPREMARK_EXT=y - MENU:=1 - PROVIDES:=kmod-qca-nss-ecm -endef - -define KernelPackage/qca-nss-ecm/Description/Default -This package contains the QCA NSS Enhanced Connection Manager -endef - -define KernelPackage/qca-nss-ecm/Default/install - $(INSTALL_DIR) $(1)/etc/firewall.d $(1)/etc/init.d $(1)/usr/bin $(1)/lib/netifd/offload $(1)/etc/config $(1)/etc/uci-defaults $(1)/etc/sysctl.d - $(INSTALL_DATA) ./files/qca-nss-ecm.firewall $(1)/etc/firewall.d/qca-nss-ecm - $(INSTALL_BIN) ./files/qca-nss-ecm.init $(1)/etc/init.d/qca-nss-ecm - $(INSTALL_BIN) ./files/ecm_dump.sh $(1)/usr/bin/ - $(INSTALL_BIN) ./files/on-demand-down $(1)/lib/netifd/offload/on-demand-down - $(INSTALL_DATA) ./files/qca-nss-ecm.uci $(1)/etc/config/ecm - $(INSTALL_DATA) ./files/qca-nss-ecm.defaults $(1)/etc/uci-defaults/99-qca-nss-ecm - $(INSTALL_BIN) ./files/qca-nss-ecm.sysctl $(1)/etc/sysctl.d/qca-nss-ecm.conf -ifeq ($(CONFIG_KERNEL_IPQ_MEM_PROFILE),256) - echo 'net.netfilter.nf_conntrack_max=2048' >> $(1)/etc/sysctl.d/qca-nss-ecm.conf -endif -ifeq ($(CONFIG_KERNEL_IPQ_MEM_PROFILE),512) - echo 'net.netfilter.nf_conntrack_max=8192' >> $(1)/etc/sysctl.d/qca-nss-ecm.conf -endif -endef - -define KernelPackage/qca-nss-ecm-standard - $(call KernelPackage/qca-nss-ecm/Default) - VARIANT:=standard - DEPENDS+=+PACKAGE_kmod-qca-mcs:kmod-qca-mcs -endef - -define KernelPackage/qca-nss-ecm-standard/Description - $(call KernelPackage/qca-nss-ecm/Description/Default) -endef - -define KernelPackage/qca-nss-ecm-standard/install -$(call KernelPackage/qca-nss-ecm/Default/install, $(1)) -endef - -# Variant with additional features enabled for premium profile -define KernelPackage/qca-nss-ecm-premium/Default -$(call KernelPackage/qca-nss-ecm/Default) - TITLE+= (with premium features) - VARIANT:=premium - DEPENDS+=+kmod-nat46 \ - +kmod-l2tp +kmod-pppol2tp +kmod-pptp \ - +kmod-bonding -endef - -define KernelPackage/qca-nss-ecm-premium/Description/Default -$(call KernelPackage/qca-nss-ecm/Description/Default) -with the premium features enabled -endef - -define KernelPackage/qca-nss-ecm-premium/Default/install -$(call KernelPackage/qca-nss-ecm/install) -endef - -define KernelPackage/qca-nss-ecm-premium -$(call KernelPackage/qca-nss-ecm-premium/Default) -endef - -define KernelPackage/qca-nss-ecm-premium/Description -$(call KernelPackage/qca-nss-ecm-premium/Description/Default) -endef - -define KernelPackage/qca-nss-ecm-premium/install -$(call KernelPackage/qca-nss-ecm-standard/install, $(1)) -endef - -# Variant with additional features enabled for noload profile -define KernelPackage/qca-nss-ecm-noload - $(call KernelPackage/qca-nss-ecm/Default) - TITLE+= (with noload features) - PROVIDES:=kmod-qca-nss-ecm - VARIANT:=noload - DEPENDS+=+kmod-l2tp +kmod-pppol2tp +kmod-pptp \ - +kmod-bonding -endef - -define KernelPackage/qca-nss-ecm-noload/Description - $(call KernelPackage/qca-nss-ecm/Description/Default) - When selected, this package installs the driver but does not load it at init. -endef - -define KernelPackage/qca-nss-ecm-noload/install -$(call KernelPackage/qca-nss-ecm/Default/install, $(1)) - # - # Remove the START line from the init script, so that the symlink - # in the /etc/rc.d directory is not created. - # - sed -i '/START=/d' $(1)/etc/init.d/qca-nss-ecm -endef - -define KernelPackage/qca-nss-ecm-premium-noload - $(call KernelPackage/qca-nss-ecm-premium/Default) - PROVIDES:=kmod-qca-nss-ecm-premium -endef - -define KernelPackage/qca-nss-ecm-premium-noload/Description - $(call KernelPackage/qca-nss-ecm-premium/Description/Default) - When selected, this package installs the driver but does not load it at init. -endef - -define KernelPackage/qca-nss-ecm-premium-noload/install -$(call KernelPackage/qca-nss-ecm-premium/Default/install, $(1)) -endef - -define Build/InstallDev/qca-nss-ecm - $(INSTALL_DIR) $(1)/usr/include/qca-nss-ecm - $(CP) $(PKG_BUILD_DIR)/exports/* $(1)/usr/include/qca-nss-ecm/ -endef - -define Build/InstallDev - $(call Build/InstallDev/qca-nss-ecm,$(1)) -endef - -EXTRA_CFLAGS+= \ - -I$(STAGING_DIR)/usr/include/hyfibr \ - -I$(STAGING_DIR)/usr/include/qca-mcs \ - -I$(STAGING_DIR)/usr/include/qca-nss-drv \ - -I$(STAGING_DIR)/usr/include/shortcut-fe \ - -I$(STAGING_DIR)/usr/include/nat46 - -ECM_MAKE_OPTS:=ECM_CLASSIFIER_HYFI_ENABLE=y -ifneq ($(LOCAL_VARIANT),standard) -ECM_MAKE_OPTS+=ECM_MULTICAST_ENABLE=y \ - ECM_INTERFACE_IPSEC_ENABLE=y \ - # ECM_INTERFACE_PPTP_ENABLE=y \ - ECM_INTERFACE_L2TPV2_ENABLE=y \ - ECM_INTERFACE_GRE_TAP_ENABLE=y \ - ECM_INTERFACE_GRE_TUN_ENABLE=y \ - ECM_INTERFACE_SIT_ENABLE=y \ - ECM_INTERFACE_TUNIPIP6_ENABLE=y \ - ECM_INTERFACE_RAWIP_ENABLE=y - -ifeq ($(CONFIG_TARGET_ipq_ipq40xx)$(CONFIG_TARGET_ipq40xx),) -ECM_MAKE_OPTS+=ECM_INTERFACE_BOND_ENABLE=y -endif -endif - -ifeq ($(filter $(CONFIG_KERNEL_IPQ_MEM_PROFILE), 256),) -ECM_MAKE_OPTS+=ECM_XFRM_ENABLE=y -endif - -# ifneq ($(CONFIG_PACKAGE_kmod-nat46),) -# ECM_MAKE_OPTS+=ECM_INTERFACE_MAP_T_ENABLE=y -# endif - -ifneq ($(CONFIG_PACKAGE_kmod-qca-mcs),) -ECM_MAKE_OPTS+=ECM_MULTICAST_ENABLE=y -endif - -ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-ovpn-link),) -ECM_MAKE_OPTS+=ECM_INTERFACE_OVPN_ENABLE=y -endif - -ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-vxlanmgr),) -ECM_MAKE_OPTS+=ECM_INTERFACE_VXLAN_ENABLE=y -endif - -ifneq ($(CONFIG_PACKAGE_kmod-qca-ovsmgr),) -ECM_MAKE_OPTS+=ECM_INTERFACE_OVS_BRIDGE_ENABLE=y \ - ECM_CLASSIFIER_OVS_ENABLE=y -EXTRA_CFLAGS+= -I$(STAGING_DIR)/usr/include/qca-ovsmgr -endif - -# Keeping default as ipq806x for branches that does not have subtarget framework -ifeq ($(CONFIG_TARGET_ipq),y) -subtarget:=$(SUBTARGET) -else -subtarget:=$(CONFIG_TARGET_BOARD) -endif - -define Build/InstallDev - $(INSTALL_DIR) $(1)/usr/include/qca-nss-ecm - $(CP) $(PKG_BUILD_DIR)/exports/* $(1)/usr/include/qca-nss-ecm -endef - -define Build/Compile - $(MAKE) $(PKG_JOBS) -C "$(LINUX_DIR)" $(strip $(ECM_MAKE_OPTS)) \ - $(KERNEL_MAKE_FLAGS) \ - $(PKG_MAKE_FLAGS) \ - M="$(PKG_BUILD_DIR)" \ - EXTRA_CFLAGS="$(EXTRA_CFLAGS)" SoC="$(subtarget)" \ - EXAMPLES_BUILD_PCC="$(CONFIG_QCA_NSS_ECM_EXAMPLES_PCC)" \ - EXAMPLES_BUILD_MARK="$(CONFIG_QCA_NSS_ECM_EXAMPLES_MARK)" \ - EXAMPLES_BUILD_OVS="$(CONFIG_QCA_NSS_ECM_OVS)" \ - ECM_FRONT_END_SFE_ENABLE="$(CONFIG_QCA_ECM_SFE_SUPPORT)" \ - modules -endef - -define KernelPackage/qca-nss-ecm-premium/config -menu "ECM Configuration" - depends on PACKAGE_kmod_qca-nss-ecm-premium - - config QCA_NSS_ECM_EXAMPLES_PCC - bool "Build PCC usage example" - help - Selecting this will build the PCC classifier usage example module. - default n - - config QCA_NSS_ECM_EXAMPLES_MARK - bool "Build Mark classifier usage example" - help - Selecting this will build the Mark classifier usage example module. - default n - - config QCA_NSS_ECM_OVS - bool "Build OVS classifier external module" - help - Selecting this will build the OVS classifier external module. - default n - - config QCA_ECM_SFE_SUPPORT - bool "Add SFE support to ECM driver" - default n -endmenu -endef - -$(eval $(call KernelPackage,qca-nss-ecm-noload)) -$(eval $(call KernelPackage,qca-nss-ecm-standard)) -$(eval $(call KernelPackage,qca-nss-ecm-premium-noload)) -$(eval $(call KernelPackage,qca-nss-ecm-premium)) diff --git a/qaa/nss/qca-nss-ecm/files/ecm_dump.sh b/qaa/nss/qca-nss-ecm/files/ecm_dump.sh deleted file mode 100644 index dbf7de753..000000000 --- a/qaa/nss/qca-nss-ecm/files/ecm_dump.sh +++ /dev/null @@ -1,95 +0,0 @@ -#!/bin/sh -# -# Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. -# -# Permission to use, copy, modify, and/or distribute this software for any -# purpose with or without fee is hereby granted, provided that the above -# copyright notice and this permission notice appear in all copies. -# -# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -# - -ECM_MODULE=${1:-ecm_state} -MOUNT_ROOT=/dev/ecm - -# -# usage: ecm_dump.sh [module=ecm_db] -# -# with no parameters, ecm_dump.sh will attempt to mount the -# ecm_db state file and cat its contents. -# -# example with a parameter: ecm_dump.sh ecm_classifier_default -# -# this will cause ecm_dump to attempt to find and mount the state -# file for the ecm_classifier_default module, and if successful -# cat the contents. -# - -# this is one of the state files, which happens to be the -# last module started in ecm -ECM_STATE=/sys/kernel/debug/ecm/ecm_state/state_dev_major - -# tests to see if ECM is up and ready to receive commands. -# returns 0 if ECM is fully up and ready, else 1 -ecm_is_ready() { - if [ ! -e "${ECM_STATE}" ] - then - return 1 - fi - return 0 -} - -# -# module_state_mount(module_name) -# Mounts the state file of the module, if supported -# -module_state_mount() { - local module_name=$1 - local mount_dir=$2 - local state_file="/sys/kernel/debug/ecm/${module_name}/state_dev_major" - - if [ -e "${mount_dir}/${module_name}" ] - then - # already mounted - return 0 - fi - - #echo "Mount state file for $module_name ..." - if [ ! -e "$state_file" ] - then - #echo "... $module_name does not support state" - return 1 - fi - - local major="`cat $state_file`" - #echo "... Mounting state $state_file with major: $major" - mknod "${mount_dir}/${module_name}" c $major 0 -} - -# -# main -# -ecm_is_ready || { - #echo "ECM is not running" - exit 1 -} - -# all state files are mounted under MOUNT_ROOT, so make sure it exists -mkdir -p ${MOUNT_ROOT} - -# -# attempt to mount state files for the requested module and cat it -# if the mount succeeded -# -module_state_mount ${ECM_MODULE} ${MOUNT_ROOT} && { - cat ${MOUNT_ROOT}/${ECM_MODULE} - exit 0 -} - -exit 2 diff --git a/qaa/nss/qca-nss-ecm/files/on-demand-down b/qaa/nss/qca-nss-ecm/files/on-demand-down deleted file mode 100644 index 02d708e03..000000000 --- a/qaa/nss/qca-nss-ecm/files/on-demand-down +++ /dev/null @@ -1,6 +0,0 @@ -#!/bin/sh -# Copyright (c) 2016 The Linux Foundation. All rights reserved. - -[ -e "/sys/kernel/debug/ecm/ecm_db/defunct_all" ] && { - echo 1 > /sys/kernel/debug/ecm/ecm_db/defunct_all -} diff --git a/qaa/nss/qca-nss-ecm/files/qca-nss-ecm.defaults b/qaa/nss/qca-nss-ecm/files/qca-nss-ecm.defaults deleted file mode 100644 index 308e265c9..000000000 --- a/qaa/nss/qca-nss-ecm/files/qca-nss-ecm.defaults +++ /dev/null @@ -1,28 +0,0 @@ -#!/bin/sh -# -# Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. -# -# Permission to use, copy, modify, and/or distribute this software for any -# purpose with or without fee is hereby granted, provided that the above -# copyright notice and this permission notice appear in all copies. -# -# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -# - -uci -q batch << EOF - delete firewall.qcanssecm - set firewall.qcanssecm=include - set firewall.qcanssecm.type=script - set firewall.qcanssecm.path=/etc/firewall.d/qca-nss-ecm - set firewall.qcanssecm.family=any - set firewall.qcanssecm.reload=1 - commit firewall -EOF - -exit 0 diff --git a/qaa/nss/qca-nss-ecm/files/qca-nss-ecm.firewall b/qaa/nss/qca-nss-ecm/files/qca-nss-ecm.firewall deleted file mode 100644 index 24c64def2..000000000 --- a/qaa/nss/qca-nss-ecm/files/qca-nss-ecm.firewall +++ /dev/null @@ -1,18 +0,0 @@ -#!/bin/sh -# -# Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. -# -# Permission to use, copy, modify, and/or distribute this software for any -# purpose with or without fee is hereby granted, provided that the above -# copyright notice and this permission notice appear in all copies. -# -# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -# - -iptables -A FORWARD -m physdev --physdev-is-bridged -j ACCEPT diff --git a/qaa/nss/qca-nss-ecm/files/qca-nss-ecm.init b/qaa/nss/qca-nss-ecm/files/qca-nss-ecm.init deleted file mode 100644 index 0d58c3599..000000000 --- a/qaa/nss/qca-nss-ecm/files/qca-nss-ecm.init +++ /dev/null @@ -1,133 +0,0 @@ -#!/bin/sh /etc/rc.common -# -# Copyright (c) 2014, 2019 The Linux Foundation. All rights reserved. -# -# Permission to use, copy, modify, and/or distribute this software for any -# purpose with or without fee is hereby granted, provided that the above -# copyright notice and this permission notice appear in all copies. -# -# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - -# The shebang above has an extra space intentially to avoid having -# openwrt build scripts automatically enable this package starting -# at boot. - -START=19 - -get_front_end_mode() { - config_load "ecm" - config_get front_end global acceleration_engine "auto" - - case $front_end in - auto) - echo '0' - ;; - nss) - echo '1' - ;; - sfe) - echo '2' - ;; - *) - echo 'uci_option_acceleration_engine is invalid' - esac -} - -support_bridge() { - #NSS support bridge acceleration - [ -d /sys/kernel/debug/ecm/ecm_nss_ipv4 ] && return 0 - #SFE doesn't support bridge acceleration - [ -d /sys/kernel/debug/ecm/ecm_sfe_ipv4 ] && return 1 -} - -load_sfe() { - local kernel_version=$(uname -r) - - [ -e "/lib/modules/$kernel_version/shortcut-fe.ko" ] && { - [ -d /sys/module/shortcut_fe ] || insmod shortcut-fe - } - - [ -e "/lib/modules/$kernel_version/shortcut-fe-ipv6.ko" ] && { - [ -d /sys/module/shortcut_fe_ipv6 ] || insmod shortcut-fe-ipv6 - } - - [ -e "/lib/modules/$kernel_version/shortcut-fe-cm.ko" ] && { - [ -d /sys/module/shortcut_fe_cm ] || insmod shortcut-fe-cm - } - - [ -e "/lib/modules/$kernel_version/shortcut-fe-drv.ko" ] && { - [ -d /sys/module/shortcut_fe_drv ] || insmod shortcut-fe-drv - } - -} - -load_ecm() { - [ -d /sys/module/ecm ] || { - [ ! -e /proc/device-tree/MP_256 ] && load_sfe - insmod ecm front_end_selection=$(get_front_end_mode) - } - - support_bridge && { - sysctl -w net.bridge.bridge-nf-call-ip6tables=1 - sysctl -w net.bridge.bridge-nf-call-iptables=1 - } -} - -unload_ecm() { - sysctl -w net.bridge.bridge-nf-call-ip6tables=0 - sysctl -w net.bridge.bridge-nf-call-iptables=0 - - if [ -d /sys/module/ecm ]; then - # - # Stop ECM frontends - # - echo 1 > /sys/kernel/debug/ecm/front_end_ipv4_stop - echo 1 > /sys/kernel/debug/ecm/front_end_ipv6_stop - - # - # Defunct the connections - # - echo 1 > /sys/kernel/debug/ecm/ecm_db/defunct_all - sleep 5; - - rmmod ecm - sleep 1 - fi -} - -start() { - load_ecm - - # If the acceleration engine is NSS, enable wifi redirect. - [ -d /sys/kernel/debug/ecm/ecm_nss_ipv4 ] && sysctl -w dev.nss.general.redirect=1 - - support_bridge && { - echo 'net.bridge.bridge-nf-call-ip6tables=1' >> /etc/sysctl.d/qca-nss-ecm.conf - echo 'net.bridge.bridge-nf-call-iptables=1' >> /etc/sysctl.d/qca-nss-ecm.conf - } - - if [ -d /sys/module/qca_ovsmgr ]; then - insmod ecm_ovs - fi - -} - -stop() { - # If the acceleration engine is NSS, disable wifi redirect. - [ -d /sys/kernel/debug/ecm/ecm_nss_ipv4 ] && sysctl -w dev.nss.general.redirect=0 - - sed '/net.bridge.bridge-nf-call-ip6tables=1/d' -i /etc/sysctl.d/qca-nss-ecm.conf - sed '/net.bridge.bridge-nf-call-iptables=1/d' -i /etc/sysctl.d/qca-nss-ecm.conf - - if [ -d /sys/module/ecm_ovs ]; then - rmmod ecm_ovs - fi - - unload_ecm -} diff --git a/qaa/nss/qca-nss-ecm/files/qca-nss-ecm.sysctl b/qaa/nss/qca-nss-ecm/files/qca-nss-ecm.sysctl deleted file mode 100644 index 1a3d76b18..000000000 --- a/qaa/nss/qca-nss-ecm/files/qca-nss-ecm.sysctl +++ /dev/null @@ -1,2 +0,0 @@ -# nf_conntrack_tcp_no_window_check is 0 by default, set it to 1 -net.netfilter.nf_conntrack_tcp_no_window_check=1 diff --git a/qaa/nss/qca-nss-ecm/files/qca-nss-ecm.uci b/qaa/nss/qca-nss-ecm/files/qca-nss-ecm.uci deleted file mode 100644 index 4f2de6877..000000000 --- a/qaa/nss/qca-nss-ecm/files/qca-nss-ecm.uci +++ /dev/null @@ -1,2 +0,0 @@ -config ecm 'global' - option acceleration_engine 'auto' diff --git a/qaa/nss/qca-nss-ecm/patches/001-Drop_SFE_from_ecm.patch b/qaa/nss/qca-nss-ecm/patches/001-Drop_SFE_from_ecm.patch deleted file mode 100644 index b1cd2b7b1..000000000 --- a/qaa/nss/qca-nss-ecm/patches/001-Drop_SFE_from_ecm.patch +++ /dev/null @@ -1,12 +0,0 @@ ---- a/Makefile -+++ b/Makefile -@@ -66,8 +66,7 @@ endif - # Define ECM_FRONT_END_SFE_ENABLE=y in order to select - # sfe as ECM's front end. - # ############################################################################# --ifeq ($(SoC),$(filter $(SoC),ipq806x ipq40xx)) --ECM_FRONT_END_SFE_ENABLE=y -+ifeq ($(ECM_FRONT_END_SFE_ENABLE), y) - ecm-$(ECM_FRONT_END_SFE_ENABLE) += frontends/sfe/ecm_sfe_ipv4.o - ecm-$(ECM_FRONT_END_SFE_ENABLE) += frontends/sfe/ecm_sfe_ported_ipv4.o - ccflags-$(ECM_FRONT_END_SFE_ENABLE) += -DECM_FRONT_END_SFE_ENABLE diff --git a/qaa/nss/qca-nss-ecm/patches/100-kernel-5.4-support.patch b/qaa/nss/qca-nss-ecm/patches/100-kernel-5.4-support.patch deleted file mode 100644 index b863ad7e0..000000000 --- a/qaa/nss/qca-nss-ecm/patches/100-kernel-5.4-support.patch +++ /dev/null @@ -1,1276 +0,0 @@ ---- a/ecm_classifier_default.c -+++ b/ecm_classifier_default.c -@@ -42,7 +42,6 @@ - #include - #include - #include --#include - #include - #include - #include ---- a/ecm_classifier_dscp.c -+++ b/ecm_classifier_dscp.c -@@ -41,7 +41,6 @@ - #include - #include - #include --#include - #include - #include - #include ---- a/ecm_classifier_hyfi.c -+++ b/ecm_classifier_hyfi.c -@@ -41,7 +41,6 @@ - #include - #include - #include --#include - #include - #include - #include ---- a/ecm_classifier_nl.c -+++ b/ecm_classifier_nl.c -@@ -41,7 +41,6 @@ - #include - #include - #include --#include - #if (LINUX_VERSION_CODE <= KERNEL_VERSION(4, 2, 0)) - #include - #else -@@ -146,12 +145,42 @@ static struct genl_multicast_group ecm_c - }, - }; - -+static int ecm_classifier_nl_genl_msg_ACCEL(struct sk_buff *skb, struct genl_info *info); -+static int ecm_classifier_nl_genl_msg_DUMP(struct sk_buff *skb, struct netlink_callback *cb); -+ -+/* -+ * Generic Netlink message-to-handler mapping -+ */ -+static struct genl_ops ecm_cl_nl_genl_ops[] = { -+ { -+ .cmd = ECM_CL_NL_GENL_CMD_ACCEL, -+ .flags = 0, -+ .doit = ecm_classifier_nl_genl_msg_ACCEL, -+ .dumpit = NULL, -+ }, -+ { -+ .cmd = ECM_CL_NL_GENL_CMD_ACCEL_OK, -+ .flags = 0, -+ .doit = NULL, -+ .dumpit = ecm_classifier_nl_genl_msg_DUMP, -+ }, -+ { -+ .cmd = ECM_CL_NL_GENL_CMD_CONNECTION_CLOSED, -+ .flags = 0, -+ .doit = NULL, -+ .dumpit = ecm_classifier_nl_genl_msg_DUMP, -+ }, -+}; -+ - static struct genl_family ecm_cl_nl_genl_family = { -- .id = GENL_ID_GENERATE, - .hdrsize = 0, - .name = ECM_CL_NL_GENL_NAME, - .version = ECM_CL_NL_GENL_VERSION, - .maxattr = ECM_CL_NL_GENL_ATTR_MAX, -+ .ops = ecm_cl_nl_genl_ops, -+ .n_ops = ARRAY_SIZE(ecm_cl_nl_genl_ops), -+ .mcgrps = ecm_cl_nl_genl_mcgrp, -+ .n_mcgrps = ARRAY_SIZE(ecm_cl_nl_genl_mcgrp), - }; - - /* -@@ -215,12 +244,7 @@ ecm_classifier_nl_send_genl_msg(enum ECM - return ret; - } - -- ret = genlmsg_end(skb, msg_head); -- if (ret < 0) { -- DEBUG_WARN("failed to finalize genl msg: %d\n", ret); -- nlmsg_free(skb); -- return ret; -- } -+ genlmsg_end(skb, msg_head); - - /* genlmsg_multicast frees the skb in both success and error cases */ - #if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 13, 0) -@@ -1377,85 +1401,14 @@ static struct file_operations ecm_classi - .write = ecm_classifier_nl_set_command, - }; - --/* -- * Generic Netlink attr checking policies -- */ --static struct nla_policy --ecm_cl_nl_genl_policy[ECM_CL_NL_GENL_ATTR_COUNT] = { -- [ECM_CL_NL_GENL_ATTR_TUPLE] = { -- .type = NLA_UNSPEC, -- .len = sizeof(struct ecm_cl_nl_genl_attr_tuple), }, --}; -- --/* -- * Generic Netlink message-to-handler mapping -- */ --static struct genl_ops ecm_cl_nl_genl_ops[] = { -- { -- .cmd = ECM_CL_NL_GENL_CMD_ACCEL, -- .flags = 0, -- .policy = ecm_cl_nl_genl_policy, -- .doit = ecm_classifier_nl_genl_msg_ACCEL, -- .dumpit = NULL, -- }, -- { -- .cmd = ECM_CL_NL_GENL_CMD_ACCEL_OK, -- .flags = 0, -- .policy = ecm_cl_nl_genl_policy, -- .doit = NULL, -- .dumpit = ecm_classifier_nl_genl_msg_DUMP, -- }, -- { -- .cmd = ECM_CL_NL_GENL_CMD_CONNECTION_CLOSED, -- .flags = 0, -- .policy = ecm_cl_nl_genl_policy, -- .doit = NULL, -- .dumpit = ecm_classifier_nl_genl_msg_DUMP, -- }, --}; -- - static int ecm_classifier_nl_register_genl(void) - { - int result; - --#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 13, 0) -- result = genl_register_family_with_ops_groups(&ecm_cl_nl_genl_family, -- ecm_cl_nl_genl_ops, -- ecm_cl_nl_genl_mcgrp); -- if (result != 0) { -- DEBUG_ERROR("failed to register genl ops: %d\n", result); -- return result; -- } --#else - result = genl_register_family(&ecm_cl_nl_genl_family); -- if (result != 0) { -+ if (result != 0) - DEBUG_ERROR("failed to register genl family: %d\n", result); -- goto err1; -- } -- -- result = genl_register_ops(&ecm_cl_nl_genl_family, -- ecm_cl_nl_genl_ops); -- if (result != 0) { -- DEBUG_ERROR("failed to register genl ops: %d\n", result); -- goto err2; -- } -- -- result = genl_register_mc_group(&ecm_cl_nl_genl_family, -- ecm_cl_nl_genl_mcgrp); -- if (result != 0) { -- DEBUG_ERROR("failed to register genl multicast group: %d\n", -- result); -- goto err3; -- } -- -- return 0; - --err3: -- genl_unregister_ops(&ecm_cl_nl_genl_family, ecm_cl_nl_genl_ops); --err2: -- genl_unregister_family(&ecm_cl_nl_genl_family); --err1: --#endif - return result; - } - ---- a/ecm_classifier_pcc.c -+++ b/ecm_classifier_pcc.c -@@ -49,7 +49,6 @@ - #include - #include - #include --#include - #include - #include - #include ---- a/ecm_conntrack_notifier.c -+++ b/ecm_conntrack_notifier.c -@@ -51,7 +51,6 @@ - #include - #include - #include --#include - #include - #include - #include -@@ -345,14 +344,6 @@ static int ecm_conntrack_event(unsigned - return NOTIFY_DONE; - } - -- /* -- * Special untracked connection is not monitored -- */ -- if (ct == &nf_conntrack_untracked) { -- DEBUG_TRACE("Fake connection event - ignoring\n"); -- return NOTIFY_DONE; -- } -- - /* - * Only interested if this is IPv4 or IPv6. - */ ---- a/ecm_db/ecm_db.c -+++ b/ecm_db/ecm_db.c -@@ -42,7 +42,6 @@ - #include - #include - #include --#include - #include - #include - #include ---- a/ecm_db/ecm_db_connection.c -+++ b/ecm_db/ecm_db_connection.c -@@ -41,7 +41,6 @@ - #include - #include - #include --#include - #include - #include - #include ---- a/ecm_db/ecm_db_host.c -+++ b/ecm_db/ecm_db_host.c -@@ -41,7 +41,6 @@ - #include - #include - #include --#include - #include - #include - #include ---- a/ecm_db/ecm_db_iface.c -+++ b/ecm_db/ecm_db_iface.c -@@ -41,7 +41,6 @@ - #include - #include - #include --#include - #include - #include - #include ---- a/ecm_db/ecm_db_listener.c -+++ b/ecm_db/ecm_db_listener.c -@@ -41,7 +41,6 @@ - #include - #include - #include --#include - #include - #include - #include ---- a/ecm_db/ecm_db_mapping.c -+++ b/ecm_db/ecm_db_mapping.c -@@ -41,7 +41,6 @@ - #include - #include - #include --#include - #include - #include - #include ---- a/ecm_db/ecm_db_multicast.c -+++ b/ecm_db/ecm_db_multicast.c -@@ -42,7 +42,6 @@ - #include - #include - #include --#include - #include - #include - #include ---- a/ecm_db/ecm_db_node.c -+++ b/ecm_db/ecm_db_node.c -@@ -41,7 +41,6 @@ - #include - #include - #include --#include - #include - #include - #include ---- a/ecm_db/ecm_db_timer.c -+++ b/ecm_db/ecm_db_timer.c -@@ -42,7 +42,6 @@ - #include - #include - #include --#include - #include - #include - #include -@@ -387,7 +386,7 @@ EXPORT_SYMBOL(ecm_db_time_get); - * Manage expiration of connections - * NOTE: This is softirq context - */ --static void ecm_db_timer_callback(unsigned long data) -+static void ecm_db_timer_callback(struct timer_list *arg) - { - uint32_t timer; - -@@ -425,9 +424,7 @@ void ecm_db_timer_init(void) - /* - * Set a timer to manage cleanup of expired connections - */ -- init_timer(&ecm_db_timer); -- ecm_db_timer.function = ecm_db_timer_callback; -- ecm_db_timer.data = 0; -+ timer_setup(&ecm_db_timer, ecm_db_timer_callback, 0); - ecm_db_timer.expires = jiffies + HZ; - add_timer(&ecm_db_timer); - ---- a/ecm_interface.c -+++ b/ecm_interface.c -@@ -66,7 +66,6 @@ - #include - #include - #include --#include - #include - #include - #include -@@ -537,7 +536,7 @@ static bool ecm_interface_find_gateway_ipv4(ip_addr_t addr, ip_addr_t gw_addr) - return false; - } - -- ECM_NIN4_ADDR_TO_IP_ADDR(gw_addr, rt->rt_gateway) -+ ECM_NIN4_ADDR_TO_IP_ADDR(gw_addr, rt->rt_gw4) - ecm_interface_route_release(&ecm_rt); - return true; - } -@@ -596,7 +595,7 @@ static bool ecm_interface_mac_addr_get_ipv4(ip_addr_t addr, uint8_t *mac_addr, b - if (rt->rt_uses_gateway || (rt->rt_flags & RTF_GATEWAY)) { - #endif - *on_link = false; -- ECM_NIN4_ADDR_TO_IP_ADDR(gw_addr, rt->rt_gateway) -+ ECM_NIN4_ADDR_TO_IP_ADDR(gw_addr, rt->rt_gw4) - } else { - *on_link = true; - } -@@ -1003,7 +1002,7 @@ static bool ecm_interface_find_route_by_addr_ipv6(ip_addr_t addr, struct ecm_int - * Get a route to the given IP address, this will allow us to also find the interface - * it is using to communicate with that IP address. - */ -- ecm_rt->rt.rtv6 = rt6_lookup(&init_net, &naddr, NULL, 0, 0); -+ ecm_rt->rt.rtv6 = rt6_lookup(&init_net, &naddr, NULL, 0, NULL, 0); - if (!ecm_rt->rt.rtv6) { - DEBUG_TRACE("No output route to: " ECM_IP_ADDR_OCTAL_FMT "\n", ECM_IP_ADDR_TO_OCTAL(addr)); - return NULL; -@@ -1077,7 +1076,7 @@ void ecm_interface_send_neighbour_solicitation(struct net_device *dev, ip_addr_t - /* - * Find the route entry - */ -- rt6i = rt6_lookup(netf, &dst_addr, NULL, 0, 0); -+ rt6i = rt6_lookup(netf, &dst_addr, NULL, 0, NULL, 0); - if (!rt6i) { - DEBUG_TRACE("IPv6 Route lookup failure for destination IPv6 address " ECM_IP_ADDR_OCTAL_FMT "\n", ECM_IP_ADDR_TO_OCTAL(addr)); - return; -@@ -1104,7 +1103,7 @@ void ecm_interface_send_neighbour_solicitation(struct net_device *dev, ip_addr_t - #if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0)) - ndisc_send_ns(dev, neigh, &dst_addr, &mc_dst_addr, &src_addr); - #else -- ndisc_send_ns(dev, &dst_addr, &mc_dst_addr, &src_addr); -+ ndisc_send_ns(dev, &dst_addr, &mc_dst_addr, &src_addr, 0); - #endif - neigh_release(neigh); - dst_release(&rt6i->dst); -@@ -1194,7 +1193,7 @@ struct neighbour *ecm_interface_ipv6_neigh_get(ip_addr_t addr) - struct in6_addr ipv6_addr; - - ECM_IP_ADDR_TO_NIN6_ADDR(ipv6_addr, addr); -- rt = rt6_lookup(&init_net, &ipv6_addr, NULL, 0, 0); -+ rt = rt6_lookup(&init_net, &ipv6_addr, NULL, 0, NULL, 0); - if (!rt) { - return NULL; - } -@@ -1220,7 +1219,7 @@ bool ecm_interface_is_pptp(struct sk_buff *skb, const struct net_device *out) - * skip first pass of l2tp/pptp tunnel encapsulated traffic - */ - if (out->type == ARPHRD_PPP) { -- if (out->priv_flags & IFF_PPP_PPTP) { -+ if (out->priv_flags_qca_ecm & IFF_QCA_ECM_PPP_PPTP) { - return true; - } - } -@@ -1231,7 +1230,7 @@ bool ecm_interface_is_pptp(struct sk_buff *skb, const struct net_device *out) - } - - if (in->type == ARPHRD_PPP) { -- if (in->priv_flags & IFF_PPP_PPTP) { -+ if (in->priv_flags_qca_ecm & IFF_QCA_ECM_PPP_PPTP) { - dev_put(in); - return true; - } -@@ -1256,10 +1255,10 @@ bool ecm_interface_is_l2tp_packet_by_version(struct sk_buff *skb, const struct n - - switch (ver) { - case 2: -- flag = IFF_PPP_L2TPV2; -+ flag = IFF_QCA_ECM_PPP_L2TPV2; - break; - case 3: -- flag = IFF_PPP_L2TPV3; -+ flag = IFF_QCA_ECM_PPP_L2TPV3; - break; - default: - break; -@@ -1268,10 +1267,8 @@ bool ecm_interface_is_l2tp_packet_by_version(struct sk_buff *skb, const struct n - /* - * skip first pass of l2tp/pptp tunnel encapsulated traffic - */ -- if (out->type == ARPHRD_PPP) { -- if (out->priv_flags & flag) { -- return true; -- } -+ if (out->priv_flags_qca_ecm & flag) { -+ return true; - } - - in = dev_get_by_index(&init_net, skb->skb_iif); -@@ -1279,11 +1276,9 @@ bool ecm_interface_is_l2tp_packet_by_version(struct sk_buff *skb, const struct n - return true; - } - -- if (in->type == ARPHRD_PPP) { -- if (in->priv_flags & flag) { -- dev_put(in); -- return true; -- } -+ if (out->priv_flags_qca_ecm & flag) { -+ dev_put(in); -+ return true; - } - - dev_put(in); -@@ -1304,11 +1299,9 @@ bool ecm_interface_is_l2tp_pptp(struct sk_buff *skb, const struct net_device *ou - /* - * skip first pass of l2tp/pptp tunnel encapsulated traffic - */ -- if (out->type == ARPHRD_PPP) { -- if (out->priv_flags & (IFF_PPP_L2TPV2 | IFF_PPP_L2TPV3 | -- IFF_PPP_PPTP)) { -- return true; -- } -+ if (out->priv_flags_qca_ecm & (IFF_QCA_ECM_PPP_L2TPV2 | IFF_QCA_ECM_PPP_L2TPV3 | -+ IFF_QCA_ECM_PPP_PPTP)) { -+ return true; - } - - in = dev_get_by_index(&init_net, skb->skb_iif); -@@ -1316,12 +1309,10 @@ bool ecm_interface_is_l2tp_pptp(struct sk_buff *skb, const struct net_device *ou - return true; - } - -- if (in->type == ARPHRD_PPP) { -- if (in->priv_flags & (IFF_PPP_L2TPV2 | IFF_PPP_L2TPV3 | -- IFF_PPP_PPTP)) { -- dev_put(in); -- return true; -- } -+ if (out->priv_flags_qca_ecm & (IFF_QCA_ECM_PPP_L2TPV2 | IFF_QCA_ECM_PPP_L2TPV3 | -+ IFF_QCA_ECM_PPP_PPTP)) { -+ dev_put(in); -+ return true; - } - - dev_put(in); -@@ -2416,7 +2407,7 @@ struct ecm_db_iface_instance *ecm_interface_establish_and_ref(struct ecm_front_e - /* - * GRE TAP? - */ -- if (dev->priv_flags & (IFF_GRE_V4_TAP | IFF_GRE_V6_TAP)) { -+ if (dev->priv_flags_qca_ecm & (IFF_QCA_ECM_GRE_V4_TAP | IFF_QCA_ECM_GRE_V6_TAP)) { - interface_type = feci->ae_interface_type_get(feci, dev); - ae_interface_num = feci->ae_interface_number_by_dev_type_get(dev, interface_type); - -@@ -2680,7 +2671,7 @@ identifier_update: - /* - * OVPN Tunnel? - */ -- if ((dev_type == ARPHRD_NONE) && (dev->priv_flags & IFF_TUN_TAP)) { -+ if ((dev_type == ARPHRD_NONE) && (dev->priv_flags_qca_ecm & IFF_QCA_ECM_TUN_TAP)) { - struct net_device *tun_dev = NULL; - ip_addr_t saddr, daddr; - -@@ -2746,7 +2737,7 @@ identifier_update: - * ppp_is_multilink() and ppp_hold_channels() which acquire same lock - */ - -- if ((dev->priv_flags & IFF_PPP_L2TPV2) && ppp_is_xmit_locked(dev)) { -+ if ((dev->priv_flags_qca_ecm & IFF_QCA_ECM_PPP_L2TPV2) && ppp_is_xmit_locked(dev)) { - if (skb && (skb->skb_iif == dev->ifindex)) { - struct pppol2tp_common_addr info; - -@@ -2804,7 +2795,7 @@ identifier_update: - #endif - - #ifdef ECM_INTERFACE_PPTP_ENABLE -- if ((protocol == IPPROTO_GRE) && skb && v4_hdr && (dev->priv_flags & IFF_PPP_PPTP)) { -+ if ((protocol == IPPROTO_GRE) && skb && v4_hdr && (dev->priv_flags_qca_ecm & IFF_QCA_ECM_PPP_PPTP)) { - struct gre_hdr_pptp *gre_hdr; - uint16_t proto; - int ret; -@@ -3972,7 +3963,7 @@ int32_t ecm_interface_heirarchy_construct(struct ecm_front_end_connection_instan - if (((ip_version == 4) && (protocol == IPPROTO_IPV6)) || - ((ip_version == 6) && (protocol == IPPROTO_IPIP)) || - (protocol == IPPROTO_GRE) || -- ((given_dest_dev->type == ARPHRD_NONE) && (given_dest_dev->priv_flags & IFF_TUN_TAP))) { -+ ((given_dest_dev->type == ARPHRD_NONE) && (given_dest_dev->priv_flags_qca_ecm & IFF_QCA_ECM_TUN_TAP))) { - dev_put(dest_dev); - dest_dev = given_dest_dev; - if (dest_dev) { -@@ -3991,7 +3982,7 @@ int32_t ecm_interface_heirarchy_construct(struct ecm_front_end_connection_instan - /* - * if the address is a local address and indev=l2tp. - */ -- if ((given_src_dev->type == ARPHRD_PPP) && (given_src_dev->priv_flags & IFF_PPP_L2TPV2) && ppp_is_xmit_locked(given_src_dev)) { -+ if ((given_src_dev->type == ARPHRD_PPP) && (given_src_dev->priv_flags_qca_ecm & IFF_QCA_ECM_PPP_L2TPV2) && ppp_is_xmit_locked(given_src_dev)) { - dev_put(dest_dev); - dest_dev = given_dest_dev; - if (dest_dev) { -@@ -4005,7 +3996,7 @@ int32_t ecm_interface_heirarchy_construct(struct ecm_front_end_connection_instan - /* - * if the address is a local address and indev=PPTP. - */ -- if (protocol == IPPROTO_GRE && given_dest_dev && (given_dest_dev->priv_flags & IFF_PPP_PPTP)){ -+ if (protocol == IPPROTO_GRE && given_dest_dev && (given_dest_dev->priv_flags_qca_ecm & IFF_QCA_ECM_PPP_PPTP)){ - dev_put(dest_dev); - dest_dev = given_dest_dev; - if (dest_dev) { -@@ -4054,7 +4045,7 @@ int32_t ecm_interface_heirarchy_construct(struct ecm_front_end_connection_instan - if (((ip_version == 4) && (protocol == IPPROTO_IPV6)) || - ((ip_version == 6) && (protocol == IPPROTO_IPIP)) || - (protocol == IPPROTO_GRE) || -- ((given_src_dev->type == ARPHRD_NONE) && (given_src_dev->priv_flags & IFF_TUN_TAP))) { -+ ((given_src_dev->type == ARPHRD_NONE) && (given_src_dev->priv_flags_qca_ecm & IFF_QCA_ECM_TUN_TAP))) { - dev_put(src_dev); - src_dev = given_src_dev; - if (src_dev) { -@@ -4504,7 +4495,7 @@ lag_success: - /* - * OVPN ? - */ -- if ((dest_dev_type == ARPHRD_NONE) && (dest_dev->priv_flags & IFF_TUN_TAP)) { -+ if ((dest_dev_type == ARPHRD_NONE) && (dest_dev->priv_flags_qca_ecm & IFF_QCA_ECM_TUN_TAP)) { - DEBUG_TRACE("Net device: %p is OVPN, device name: %s\n", dest_dev, dest_dev->name); - break; - } -@@ -4523,7 +4514,7 @@ lag_success: - DEBUG_TRACE("%p: Net device: %p is PPP\n", feci, dest_dev); - - #ifdef ECM_INTERFACE_L2TPV2_ENABLE -- if ((given_src_dev->priv_flags & IFF_PPP_L2TPV2) && ppp_is_xmit_locked(given_src_dev)) { -+ if ((given_src_dev->priv_flags_qca_ecm & IFF_QCA_ECM_PPP_L2TPV2) && ppp_is_xmit_locked(given_src_dev)) { - if (skb->skb_iif == dest_dev->ifindex) { - DEBUG_TRACE("%p: Net device: %p PPP channel is PPPoL2TPV2\n", feci, dest_dev); - break; -@@ -4532,7 +4523,7 @@ lag_success: - #endif - - #ifdef ECM_INTERFACE_PPTP_ENABLE -- if (protocol == IPPROTO_GRE && dest_dev && (dest_dev->priv_flags & IFF_PPP_PPTP)) { -+ if (protocol == IPPROTO_GRE && dest_dev && (dest_dev->priv_flags_qca_ecm & IFF_QCA_ECM_PPP_PPTP)) { - DEBUG_TRACE("%p: Net device: %p PPP channel is PPTP\n", feci, dest_dev); - break; - } -@@ -4798,7 +4789,7 @@ int32_t ecm_interface_multicast_from_heirarchy_construct(struct ecm_front_end_co - /* - * if the address is a local address and indev=l2tp. - */ -- if ((given_src_dev->type == ARPHRD_PPP) && (given_src_dev->priv_flags & IFF_PPP_L2TPV2) && ppp_is_xmit_locked(given_src_dev)) { -+ if ((given_src_dev->type == ARPHRD_PPP) && (given_src_dev->priv_flags_qca_ecm & IFF_QCA_ECM_PPP_L2TPV2) && ppp_is_xmit_locked(given_src_dev)) { - dev_put(dest_dev); - dest_dev = given_dest_dev; - if (dest_dev) { -@@ -5265,7 +5256,7 @@ int32_t ecm_interface_multicast_from_heirarchy_construct(struct ecm_front_end_co - DEBUG_TRACE("Net device: %p is PPP\n", dest_dev); - - #ifdef ECM_INTERFACE_L2TPV2_ENABLE -- if ((given_src_dev->priv_flags & IFF_PPP_L2TPV2) && ppp_is_xmit_locked(given_src_dev)) { -+ if ((given_src_dev->priv_flags_qca_ecm & IFF_QCA_ECM_PPP_L2TPV2) && ppp_is_xmit_locked(given_src_dev)) { - if (skb->skb_iif == dest_dev->ifindex) { - DEBUG_TRACE("Net device: %p PPP channel is PPPoL2TPV2\n", dest_dev); - break; -@@ -6520,7 +6511,7 @@ static int ecm_interface_wifi_event_rx(struct socket *sock, struct sockaddr_nl * - #endif - oldfs = get_fs(); - set_fs(KERNEL_DS); -- size = sock_recvmsg(sock, &msg, len, msg.msg_flags); -+ size = sock_recvmsg(sock, &msg, msg.msg_flags); - set_fs(oldfs); - - return size; -@@ -6609,7 +6600,7 @@ int ecm_interface_wifi_event_stop(void) - } - - DEBUG_INFO("kill ecm_interface_wifi_event thread\n"); -- force_sig(SIGKILL, __ewn.thread); -+ send_sig(SIGKILL, __ewn.thread, 1); - err = kthread_stop(__ewn.thread); - __ewn.thread = NULL; - ---- a/ecm_tracker.c -+++ b/ecm_tracker.c -@@ -43,7 +43,6 @@ - #include - #include - #include --#include - #include - #include - #include ---- a/ecm_tracker_datagram.c -+++ b/ecm_tracker_datagram.c -@@ -43,7 +43,6 @@ - #include - #include - #include --#include - #include - #include - #include ---- a/ecm_tracker_tcp.c -+++ b/ecm_tracker_tcp.c -@@ -43,7 +43,6 @@ - #include - #include - #include --#include - #include - #include - #include -@@ -1143,7 +1142,7 @@ static bool ecm_tracker_tcp_extract_mss( - const u8 *hash_location; - tcp_parse_options(skb, &opt_rx, &hash_location, 0); - #elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)) -- tcp_parse_options(skb, &opt_rx, 0, NULL); -+ tcp_parse_options(&init_net, skb, &opt_rx, 0, NULL); - #else - #error "Unsupported kernel version for tcp_parse_options()" - #endif ---- a/ecm_tracker_udp.c -+++ b/ecm_tracker_udp.c -@@ -43,7 +43,6 @@ - #include - #include - #include --#include - #include - #include - #include ---- a/frontends/ecm_front_end_ipv4.c -+++ b/frontends/ecm_front_end_ipv4.c -@@ -215,7 +215,7 @@ bool ecm_front_end_ipv4_interface_constr - * behind a gateway. - */ - DEBUG_TRACE("Gateway address will be looked up overwrite the rt_dst_addr\n"); -- ECM_NIN4_ADDR_TO_IP_ADDR(rt_dst_addr, rt->rt_gateway) -+ ECM_NIN4_ADDR_TO_IP_ADDR(rt_dst_addr, rt->rt_gw4) - gateway = true; - } - ---- a/frontends/include/ecm_front_end_common.h -+++ b/frontends/include/ecm_front_end_common.h -@@ -98,13 +98,6 @@ static inline bool ecm_front_end_acceler - return false; - } - -- if (unlikely(nf_ct_is_untracked(ct))) { -- /* -- * Untracked traffic certainly can't be accelerated. -- */ -- return true; -- } -- - #if (LINUX_VERSION_CODE <= KERNEL_VERSION(3, 6, 0)) - acct = nf_conn_acct_find(ct); - #else ---- a/frontends/nss/ecm_nss_bond_notifier.c -+++ b/frontends/nss/ecm_nss_bond_notifier.c -@@ -52,7 +52,6 @@ - #include - #include - #include --#include - #include - #include - #include ---- a/frontends/nss/ecm_nss_common.h -+++ b/frontends/nss/ecm_nss_common.h -@@ -144,7 +144,7 @@ static inline int32_t ecm_nss_common_get_interface_type(struct ecm_front_end_con - /* - * If device is not GRETAP then return NONE. - */ -- if (!(dev->priv_flags & (IFF_GRE_V4_TAP | IFF_GRE_V6_TAP))) { -+ if (!(dev->priv_flags_qca_ecm & (IFF_QCA_ECM_GRE_V4_TAP | IFF_QCA_ECM_GRE_V6_TAP))) { - break; - } - #endif ---- a/frontends/nss/ecm_nss_ipv4.c -+++ b/frontends/nss/ecm_nss_ipv4.c -@@ -48,7 +48,6 @@ - #include - #include - #include --#include - #if (LINUX_VERSION_CODE <= KERNEL_VERSION(4, 2, 0)) - #include - #else -@@ -1053,7 +1052,7 @@ static unsigned int ecm_nss_ipv4_ip_process(struct net_device *out_dev, struct n - * If any of the input or output interface is a GRE V4 TAP/TUN interface - * we can continue to accelerate it. - */ -- if ((in_dev->priv_flags & IFF_GRE_V4_TAP) || (out_dev->priv_flags & IFF_GRE_V4_TAP)) { -+ if ((in_dev->priv_flags_qca_ecm & IFF_QCA_ECM_GRE_V4_TAP) || (out_dev->priv_flags_qca_ecm & IFF_QCA_ECM_GRE_V4_TAP)) { - #ifndef ECM_INTERFACE_GRE_TAP_ENABLE - DEBUG_TRACE("GRE TAP acceleration is disabled\n"); - return NF_ACCEPT; -@@ -1082,7 +1081,7 @@ static unsigned int ecm_nss_ipv4_ip_process(struct net_device *out_dev, struct n - reply_tuple.dst.u3.ip = orig_tuple.src.u3.ip; - sender = ECM_TRACKER_SENDER_TYPE_SRC; - } else { -- if (unlikely(ct == &nf_conntrack_untracked)) { -+ if (unlikely(ctinfo == IP_CT_UNTRACKED)) { - DEBUG_TRACE("%p: ct: untracked\n", skb); - return NF_ACCEPT; - } -@@ -2097,7 +2096,6 @@ sync_conntrack: - } - - ct = nf_ct_tuplehash_to_ctrack(h); -- NF_CT_ASSERT(ct->timeout.data == (unsigned long)ct); - DEBUG_TRACE("%p: NSS Sync: conntrack connection\n", ct); - - ecm_front_end_flow_and_return_directions_get(ct, flow_ip, 4, &flow_dir, &return_dir); -@@ -2108,7 +2106,7 @@ sync_conntrack: - */ - if (!test_bit(IPS_FIXED_TIMEOUT_BIT, &ct->status)) { - spin_lock_bh(&ct->lock); -- ct->timeout.expires += delta_jiffies; -+ ct->timeout += delta_jiffies; - spin_unlock_bh(&ct->lock); - } - -@@ -2166,17 +2164,15 @@ sync_conntrack: - u_int64_t reply_pkts = atomic64_read(&acct[IP_CT_DIR_REPLY].packets); - - if (reply_pkts != 0) { -- struct nf_conntrack_l4proto *l4proto; - unsigned int *timeouts; - - set_bit(IPS_SEEN_REPLY_BIT, &ct->status); - set_bit(IPS_ASSURED_BIT, &ct->status); - -- l4proto = __nf_ct_l4proto_find(AF_INET, IPPROTO_UDP); -- timeouts = nf_ct_timeout_lookup(&init_net, ct, l4proto); -+ timeouts = nf_ct_timeout_lookup(ct); - - spin_lock_bh(&ct->lock); -- ct->timeout.expires = jiffies + timeouts[UDP_CT_REPLIED]; -+ ct->timeout = jiffies + timeouts[UDP_CT_REPLIED]; - spin_unlock_bh(&ct->lock); - } - } -@@ -2690,7 +2686,8 @@ int ecm_nss_ipv4_init(struct dentry *dentry) - /* - * Register netfilter hooks - */ -- result = nf_register_hooks(ecm_nss_ipv4_netfilter_hooks, ARRAY_SIZE(ecm_nss_ipv4_netfilter_hooks)); -+ result = nf_register_net_hooks(&init_net, ecm_nss_ipv4_netfilter_hooks, \ -+ ARRAY_SIZE(ecm_nss_ipv4_netfilter_hooks)); - if (result < 0) { - DEBUG_ERROR("Can't register netfilter hooks.\n"); - nss_ipv4_notify_unregister(); -@@ -2702,8 +2699,8 @@ int ecm_nss_ipv4_init(struct dentry *dentry) - if (result < 0) { - DEBUG_ERROR("Failed to init ecm ipv4 multicast frontend\n"); - nss_ipv4_notify_unregister(); -- nf_unregister_hooks(ecm_nss_ipv4_netfilter_hooks, -- ARRAY_SIZE(ecm_nss_ipv4_netfilter_hooks)); -+ nf_unregister_net_hooks(&init_net, ecm_nss_ipv4_netfilter_hooks, -+ ARRAY_SIZE(ecm_nss_ipv4_netfilter_hooks)); - goto task_cleanup; - } - #endif -@@ -2714,8 +2711,8 @@ int ecm_nss_ipv4_init(struct dentry *dentry) - #ifdef ECM_MULTICAST_ENABLE - ecm_nss_multicast_ipv4_exit(); - #endif -- nf_unregister_hooks(ecm_nss_ipv4_netfilter_hooks, -- ARRAY_SIZE(ecm_nss_ipv4_netfilter_hooks)); -+ nf_unregister_net_hooks(&init_net, ecm_nss_ipv4_netfilter_hooks, -+ ARRAY_SIZE(ecm_nss_ipv4_netfilter_hooks)); - goto task_cleanup; - } - -@@ -2742,8 +2739,8 @@ void ecm_nss_ipv4_exit(void) - /* - * Stop the network stack hooks - */ -- nf_unregister_hooks(ecm_nss_ipv4_netfilter_hooks, -- ARRAY_SIZE(ecm_nss_ipv4_netfilter_hooks)); -+ nf_unregister_net_hooks(&init_net, ecm_nss_ipv4_netfilter_hooks, -+ ARRAY_SIZE(ecm_nss_ipv4_netfilter_hooks)); - - /* - * Unregister from the Linux NSS Network driver ---- a/frontends/nss/ecm_nss_ipv6.c -+++ b/frontends/nss/ecm_nss_ipv6.c -@@ -51,7 +51,6 @@ - #include - #include - #include --#include - #if (LINUX_VERSION_CODE <= KERNEL_VERSION(4, 2, 0)) - #include - #else -@@ -1035,7 +1034,7 @@ static unsigned int ecm_nss_ipv6_ip_process(struct net_device *out_dev, struct n - * If any of the input or output interface is a GRE V4 TAP/TUN interface - * we can continue to accelerate it. - */ -- if ((in_dev->priv_flags & IFF_GRE_V4_TAP) || (out_dev->priv_flags & IFF_GRE_V4_TAP)) { -+ if ((in_dev->priv_flags_qca_ecm & IFF_QCA_ECM_GRE_V4_TAP) || (out_dev->priv_flags_qca_ecm & IFF_QCA_ECM_GRE_V4_TAP)) { - #ifndef ECM_INTERFACE_GRE_TAP_ENABLE - DEBUG_TRACE("GRE TAP acceleration is disabled\n"); - return NF_ACCEPT; -@@ -1064,7 +1063,7 @@ static unsigned int ecm_nss_ipv6_ip_process(struct net_device *out_dev, struct n - ECM_IP_ADDR_TO_NIN6_ADDR(reply_tuple.dst.u3.in6, ip_hdr.src_addr); - sender = ECM_TRACKER_SENDER_TYPE_SRC; - } else { -- if (unlikely(ct == &nf_conntrack_untracked)) { -+ if (unlikely(ctinfo == IP_CT_UNTRACKED)) { - DEBUG_TRACE("%p: ct: untracked\n", skb); - return NF_ACCEPT; - } -@@ -1809,7 +1808,6 @@ sync_conntrack: - } - - ct = nf_ct_tuplehash_to_ctrack(h); -- NF_CT_ASSERT(ct->timeout.data == (unsigned long)ct); - DEBUG_TRACE("%p: NSS Sync: conntrack connection\n", ct); - - ecm_front_end_flow_and_return_directions_get(ct, flow_ip, 6, &flow_dir, &return_dir); -@@ -1820,7 +1818,7 @@ sync_conntrack: - */ - if (!test_bit(IPS_FIXED_TIMEOUT_BIT, &ct->status)) { - spin_lock_bh(&ct->lock); -- ct->timeout.expires += delta_jiffies; -+ ct->timeout += delta_jiffies; - spin_unlock_bh(&ct->lock); - } - -@@ -1878,17 +1876,15 @@ sync_conntrack: - u_int64_t reply_pkts = atomic64_read(&acct[IP_CT_DIR_REPLY].packets); - - if (reply_pkts != 0) { -- struct nf_conntrack_l4proto *l4proto; - unsigned int *timeouts; - - set_bit(IPS_SEEN_REPLY_BIT, &ct->status); - set_bit(IPS_ASSURED_BIT, &ct->status); - -- l4proto = __nf_ct_l4proto_find(AF_INET6, IPPROTO_UDP); -- timeouts = nf_ct_timeout_lookup(&init_net, ct, l4proto); -+ timeouts = nf_ct_timeout_lookup(ct); - - spin_lock_bh(&ct->lock); -- ct->timeout.expires = jiffies + timeouts[UDP_CT_REPLIED]; -+ ct->timeout = jiffies + timeouts[UDP_CT_REPLIED]; - spin_unlock_bh(&ct->lock); - } - } -@@ -2402,7 +2398,7 @@ int ecm_nss_ipv6_init(struct dentry *dentry) - /* - * Register netfilter hooks - */ -- result = nf_register_hooks(ecm_nss_ipv6_netfilter_hooks, ARRAY_SIZE(ecm_nss_ipv6_netfilter_hooks)); -+ result = nf_register_net_hooks(&init_net, ecm_nss_ipv6_netfilter_hooks, ARRAY_SIZE(ecm_nss_ipv6_netfilter_hooks)); - if (result < 0) { - DEBUG_ERROR("Can't register netfilter hooks.\n"); - nss_ipv6_notify_unregister(); -@@ -2414,8 +2410,8 @@ int ecm_nss_ipv6_init(struct dentry *dentry) - if (result < 0) { - DEBUG_ERROR("Failed to init ecm ipv6 multicast frontend\n"); - nss_ipv6_notify_unregister(); -- nf_unregister_hooks(ecm_nss_ipv6_netfilter_hooks, -- ARRAY_SIZE(ecm_nss_ipv6_netfilter_hooks)); -+ nf_unregister_net_hooks(&init_net, ecm_nss_ipv6_netfilter_hooks, -+ ARRAY_SIZE(ecm_nss_ipv6_netfilter_hooks)); - goto task_cleanup; - } - #endif -@@ -2426,8 +2422,8 @@ int ecm_nss_ipv6_init(struct dentry *dentry) - #ifdef ECM_MULTICAST_ENABLE - ecm_nss_multicast_ipv6_exit(); - #endif -- nf_unregister_hooks(ecm_nss_ipv6_netfilter_hooks, -- ARRAY_SIZE(ecm_nss_ipv6_netfilter_hooks)); -+ nf_unregister_net_hooks(&init_net, ecm_nss_ipv6_netfilter_hooks, -+ ARRAY_SIZE(ecm_nss_ipv6_netfilter_hooks)); - goto task_cleanup; - } - -@@ -2453,8 +2449,8 @@ void ecm_nss_ipv6_exit(void) - /* - * Stop the network stack hooks - */ -- nf_unregister_hooks(ecm_nss_ipv6_netfilter_hooks, -- ARRAY_SIZE(ecm_nss_ipv6_netfilter_hooks)); -+ nf_unregister_net_hooks(&init_net, ecm_nss_ipv6_netfilter_hooks, -+ ARRAY_SIZE(ecm_nss_ipv6_netfilter_hooks)); - - /* - * Unregister from the Linux NSS Network driver ---- a/frontends/nss/ecm_nss_multicast_ipv4.c -+++ b/frontends/nss/ecm_nss_multicast_ipv4.c -@@ -50,7 +50,6 @@ - #include - #include - #include --#include - #include - #include - #include ---- a/frontends/nss/ecm_nss_multicast_ipv6.c -+++ b/frontends/nss/ecm_nss_multicast_ipv6.c -@@ -51,7 +51,6 @@ - #include - #include - #include --#include - #include - #include - #include ---- a/frontends/nss/ecm_nss_non_ported_ipv4.c -+++ b/frontends/nss/ecm_nss_non_ported_ipv4.c -@@ -47,7 +47,6 @@ - #include - #include - #include --#include - #include - #include - #include -@@ -640,7 +639,7 @@ static void ecm_nss_non_ported_ipv4_connection_accelerate(struct ecm_front_end_c - #ifdef ECM_INTERFACE_GRE_TAP_ENABLE - dev = dev_get_by_index(&init_net, ecm_db_iface_interface_identifier_get(ii)); - if (dev) { -- if (dev->priv_flags & IFF_GRE_V4_TAP) { -+ if (dev->priv_flags_qca_ecm & IFF_QCA_ECM_GRE_V4_TAP) { - /* - * Clear QOS_VALID to prevent outer rule from overwriting - * inner flow's QoS classification. ---- a/frontends/nss/ecm_nss_non_ported_ipv6.c -+++ b/frontends/nss/ecm_nss_non_ported_ipv6.c -@@ -47,7 +47,6 @@ - #include - #include - #include --#include - #include - #include - #include -@@ -548,7 +547,7 @@ static void ecm_nss_non_ported_ipv6_connection_accelerate(struct ecm_front_end_c - #ifdef ECM_INTERFACE_GRE_TAP_ENABLE - dev = dev_get_by_index(&init_net, ecm_db_iface_interface_identifier_get(ii)); - if (dev) { -- if (dev->priv_flags & IFF_GRE_V6_TAP) { -+ if (dev->priv_flags_qca_ecm & IFF_QCA_ECM_GRE_V6_TAP) { - /* - * Clear QOS_VALID to prevent outer rule from overwriting - * inner flow's QoS classification. ---- a/frontends/nss/ecm_nss_ported_ipv4.c -+++ b/frontends/nss/ecm_nss_ported_ipv4.c -@@ -47,7 +47,6 @@ - #include - #include - #include --#include - #include - #include - #include ---- a/frontends/nss/ecm_nss_ported_ipv6.c -+++ b/frontends/nss/ecm_nss_ported_ipv6.c -@@ -47,7 +47,6 @@ - #include - #include - #include --#include - #include - #include - #include -@@ -1996,7 +1995,7 @@ unsigned int ecm_nss_ported_ipv6_process - /* - * Deny acceleration for L2TP-over-UDP tunnel - */ -- if ((in_dev->priv_flags & IFF_PPP_L2TPV2) && ppp_is_xmit_locked(in_dev)) { -+ if ((in_dev->priv_flags_qca_ecm & IFF_QCA_ECM_PPP_L2TPV2) && ppp_is_xmit_locked(in_dev)) { - DEBUG_TRACE("Skip packets for L2TP tunnel in skb %p\n", skb); - can_accel = false; - } ---- a/frontends/sfe/ecm_sfe_ipv4.c -+++ b/frontends/sfe/ecm_sfe_ipv4.c -@@ -47,7 +47,6 @@ - #include - #include - #include --#include - #if (LINUX_VERSION_CODE <= KERNEL_VERSION(4, 2, 0)) - #include - #else -@@ -746,7 +745,8 @@ static unsigned int ecm_sfe_ipv4_ip_proc - * If skb_dst(skb)->xfrm is not null, packet is to be encrypted by ipsec, we can't accelerate it. - * If skb->sp is not null, packet is decrypted by ipsec. We only accelerate it when configuration didn't reject ipsec. - */ -- if (unlikely((skb_dst(skb) && skb_dst(skb)->xfrm) || (ecm_sfe_ipv4_reject_acceleration_for_ipsec && skb->sp))) { -+ if (unlikely((skb_dst(skb) && skb_dst(skb)->xfrm) || \ -+ (ecm_sfe_ipv4_reject_acceleration_for_ipsec && skb_ext_exist(skb, SKB_EXT_SEC_PATH)))) { - DEBUG_TRACE("skip local ipsec flows\n"); - return NF_ACCEPT; - } -@@ -762,7 +762,7 @@ static unsigned int ecm_sfe_ipv4_ip_process(struct net_device *out_dev, struct n - reply_tuple.dst.u3.ip = orig_tuple.src.u3.ip; - sender = ECM_TRACKER_SENDER_TYPE_SRC; - } else { -- if (unlikely(ct == &nf_conntrack_untracked)) { -+ if (unlikely(ctinfo == IP_CT_UNTRACKED)) { - DEBUG_TRACE("%p: ct: untracked\n", skb); - return NF_ACCEPT; - } -@@ -1531,7 +1526,6 @@ sync_conntrack: - } - - ct = nf_ct_tuplehash_to_ctrack(h); -- NF_CT_ASSERT(ct->timeout.data == (unsigned long)ct); - DEBUG_TRACE("%p: SFE Sync: conntrack connection\n", ct); - - ecm_front_end_flow_and_return_directions_get(ct, flow_ip, 4, &flow_dir, &return_dir); -@@ -1551,7 +1545,7 @@ sync_conntrack: - delta_jiffies = ((sync->inc_ticks * HZ) + (MSEC_PER_SEC / 2)) / MSEC_PER_SEC; - - spin_lock_bh(&ct->lock); -- ct->timeout.expires += delta_jiffies; -+ ct->timeout += delta_jiffies; - spin_unlock_bh(&ct->lock); - } - -@@ -1609,17 +1603,15 @@ sync_conntrack: - u_int64_t reply_pkts = atomic64_read(&acct[IP_CT_DIR_REPLY].packets); - - if (reply_pkts != 0) { -- struct nf_conntrack_l4proto *l4proto; - unsigned int *timeouts; - - set_bit(IPS_SEEN_REPLY_BIT, &ct->status); - set_bit(IPS_ASSURED_BIT, &ct->status); - -- l4proto = __nf_ct_l4proto_find(AF_INET, IPPROTO_UDP); -- timeouts = nf_ct_timeout_lookup(&init_net, ct, l4proto); -+ timeouts = nf_ct_timeout_lookup(ct); - - spin_lock_bh(&ct->lock); -- ct->timeout.expires = jiffies + timeouts[UDP_CT_REPLIED]; -+ ct->timeout = jiffies + timeouts[UDP_CT_REPLIED]; - spin_unlock_bh(&ct->lock); - } - } -@@ -1901,7 +1893,7 @@ int ecm_sfe_ipv4_init(struct dentry *den - /* - * Register netfilter hooks - */ -- result = nf_register_hooks(ecm_sfe_ipv4_netfilter_hooks, ARRAY_SIZE(ecm_sfe_ipv4_netfilter_hooks)); -+ result = nf_register_net_hooks(&init_net, ecm_sfe_ipv4_netfilter_hooks, ARRAY_SIZE(ecm_sfe_ipv4_netfilter_hooks)); - if (result < 0) { - DEBUG_ERROR("Can't register netfilter hooks.\n"); - sfe_drv_ipv4_notify_unregister(); -@@ -1934,8 +1926,8 @@ void ecm_sfe_ipv4_exit(void) - /* - * Stop the network stack hooks - */ -- nf_unregister_hooks(ecm_sfe_ipv4_netfilter_hooks, -- ARRAY_SIZE(ecm_sfe_ipv4_netfilter_hooks)); -+ nf_unregister_net_hooks(&init_net, ecm_sfe_ipv4_netfilter_hooks, -+ ARRAY_SIZE(ecm_sfe_ipv4_netfilter_hooks)); - - /* - * Unregister from the simulated sfe driver ---- a/frontends/sfe/ecm_sfe_ipv6.c -+++ b/frontends/sfe/ecm_sfe_ipv6.c -@@ -51,7 +51,6 @@ - #include - #include - #include --#include - #if (LINUX_VERSION_CODE <= KERNEL_VERSION(4, 2, 0)) - #include - #else -@@ -714,7 +713,8 @@ static unsigned int ecm_sfe_ipv6_ip_proc - * If skb_dst(skb)->xfrm is not null, packet is to be encrypted by ipsec, we can't accelerate it. - * If skb->sp is not null, packet is decrypted by ipsec. We only accelerate it when configuration didn't reject ipsec. - */ -- if (unlikely((skb_dst(skb) && skb_dst(skb)->xfrm) || (ecm_sfe_ipv6_reject_acceleration_for_ipsec && skb->sp))) { -+ if (unlikely((skb_dst(skb) && skb_dst(skb)->xfrm) || \ -+ (ecm_sfe_ipv6_reject_acceleration_for_ipsec && skb_ext_exist(skb, SKB_EXT_SEC_PATH)))) { - DEBUG_TRACE("skip local ipsec flows\n"); - return NF_ACCEPT; - } -@@ -733,7 +733,7 @@ static unsigned int ecm_sfe_ipv6_ip_proc - ECM_IP_ADDR_TO_NIN6_ADDR(reply_tuple.dst.u3.in6, ip_hdr.src_addr); - sender = ECM_TRACKER_SENDER_TYPE_SRC; - } else { -- if (unlikely(ct == &nf_conntrack_untracked)) { -+ if (unlikely(ctinfo == IP_CT_UNTRACKED)) { - DEBUG_TRACE("%p: ct: untracked\n", skb); - return NF_ACCEPT; - } -@@ -1255,7 +1255,6 @@ sync_conntrack: - } - - ct = nf_ct_tuplehash_to_ctrack(h); -- NF_CT_ASSERT(ct->timeout.data == (unsigned long)ct); - DEBUG_TRACE("%p: SFE Sync: conntrack connection\n", ct); - - ecm_front_end_flow_and_return_directions_get(ct, flow_ip, 6, &flow_dir, &return_dir); -@@ -1275,7 +1274,7 @@ sync_conntrack: - delta_jiffies = ((sync->inc_ticks * HZ) + (MSEC_PER_SEC / 2)) / MSEC_PER_SEC; - - spin_lock_bh(&ct->lock); -- ct->timeout.expires += delta_jiffies; -+ ct->timeout += delta_jiffies; - spin_unlock_bh(&ct->lock); - } - #if (LINUX_VERSION_CODE <= KERNEL_VERSION(3,6,0)) -@@ -1332,17 +1331,15 @@ sync_conntrack: - u_int64_t reply_pkts = atomic64_read(&acct[IP_CT_DIR_REPLY].packets); - - if (reply_pkts != 0) { -- struct nf_conntrack_l4proto *l4proto; - unsigned int *timeouts; - - set_bit(IPS_SEEN_REPLY_BIT, &ct->status); - set_bit(IPS_ASSURED_BIT, &ct->status); - -- l4proto = __nf_ct_l4proto_find(AF_INET6, IPPROTO_UDP); -- timeouts = nf_ct_timeout_lookup(&init_net, ct, l4proto); -+ timeouts = nf_ct_timeout_lookup(ct); - - spin_lock_bh(&ct->lock); -- ct->timeout.expires = jiffies + timeouts[UDP_CT_REPLIED]; -+ ct->timeout = jiffies + timeouts[UDP_CT_REPLIED]; - spin_unlock_bh(&ct->lock); - } - } -@@ -1624,7 +1621,7 @@ int ecm_sfe_ipv6_init(struct dentry *den - /* - * Register netfilter hooks - */ -- result = nf_register_hooks(ecm_sfe_ipv6_netfilter_hooks, ARRAY_SIZE(ecm_sfe_ipv6_netfilter_hooks)); -+ result = nf_register_net_hooks(&init_net, ecm_sfe_ipv6_netfilter_hooks, ARRAY_SIZE(ecm_sfe_ipv6_netfilter_hooks)); - if (result < 0) { - DEBUG_ERROR("Can't register netfilter hooks.\n"); - sfe_drv_ipv6_notify_unregister(); -@@ -1656,8 +1653,8 @@ void ecm_sfe_ipv6_exit(void) - /* - * Stop the network stack hooks - */ -- nf_unregister_hooks(ecm_sfe_ipv6_netfilter_hooks, -- ARRAY_SIZE(ecm_sfe_ipv6_netfilter_hooks)); -+ nf_unregister_net_hooks(&init_net, ecm_sfe_ipv6_netfilter_hooks, -+ ARRAY_SIZE(ecm_sfe_ipv6_netfilter_hooks)); - - /* - * Unregister from the Linux SFE Network driver ---- a/frontends/sfe/ecm_sfe_non_ported_ipv4.c -+++ b/frontends/sfe/ecm_sfe_non_ported_ipv4.c -@@ -46,7 +46,6 @@ - #include - #include - #include --#include - #include - #include - #include -@@ -1829,7 +1828,7 @@ unsigned int ecm_sfe_non_ported_ipv4_pro - /* - * Packet has been decrypted by ipsec, mark it in connection. - */ -- if (unlikely(skb->sp)) { -+ if (unlikely(skb_ext_exist(skb, SKB_EXT_SEC_PATH))) { - ((struct ecm_sfe_non_ported_ipv4_connection_instance *)feci)->flow_ipsec_state = ECM_SFE_IPSEC_STATE_WAS_DECRYPTED; - ((struct ecm_sfe_non_ported_ipv4_connection_instance *)feci)->return_ipsec_state = ECM_SFE_IPSEC_STATE_TO_ENCRYPT; - } ---- a/frontends/sfe/ecm_sfe_non_ported_ipv6.c -+++ b/frontends/sfe/ecm_sfe_non_ported_ipv6.c -@@ -47,7 +47,6 @@ - #include - #include - #include --#include - #include - #include - #include -@@ -1710,7 +1709,7 @@ unsigned int ecm_sfe_non_ported_ipv6_pro - /* - * Packet has been decrypted by ipsec, mark it in connection. - */ -- if (unlikely(skb->sp)) { -+ if (unlikely(skb_ext_exist(skb, SKB_EXT_SEC_PATH))) { - ((struct ecm_sfe_non_ported_ipv6_connection_instance *)feci)->flow_ipsec_state = ECM_SFE_IPSEC_STATE_WAS_DECRYPTED; - ((struct ecm_sfe_non_ported_ipv6_connection_instance *)feci)->return_ipsec_state = ECM_SFE_IPSEC_STATE_TO_ENCRYPT; - } ---- a/frontends/sfe/ecm_sfe_ported_ipv4.c -+++ b/frontends/sfe/ecm_sfe_ported_ipv4.c -@@ -46,7 +46,6 @@ - #include - #include - #include --#include - #include - #include - #include -@@ -2053,7 +2052,7 @@ unsigned int ecm_sfe_ported_ipv4_process - /* - * Packet has been decrypted by ipsec, mark it in connection. - */ -- if (unlikely(skb->sp)) { -+ if (unlikely(skb_ext_exist(skb, SKB_EXT_SEC_PATH))) { - ((struct ecm_sfe_ported_ipv4_connection_instance *)feci)->flow_ipsec_state = ECM_SFE_IPSEC_STATE_WAS_DECRYPTED; - ((struct ecm_sfe_ported_ipv4_connection_instance *)feci)->return_ipsec_state = ECM_SFE_IPSEC_STATE_TO_ENCRYPT; - } ---- a/frontends/sfe/ecm_sfe_ported_ipv6.c -+++ b/frontends/sfe/ecm_sfe_ported_ipv6.c -@@ -47,7 +47,6 @@ - #include - #include - #include --#include - #include - #include - #include -@@ -1826,7 +1825,7 @@ unsigned int ecm_sfe_ported_ipv6_process - /* - * Deny acceleration for L2TP-over-UDP tunnel - */ -- if ((in_dev->priv_flags & IFF_PPP_L2TPV2) && ppp_is_xmit_locked(in_dev)) { -+ if ((in_dev->priv_flags_qca_ecm & IFF_QCA_ECM_PPP_L2TPV2) && ppp_is_xmit_locked(in_dev)) { - DEBUG_TRACE("Skip packets for L2TP tunnel in skb %p\n", skb); - can_accel = false; - } -@@ -1958,7 +1957,7 @@ unsigned int ecm_sfe_ported_ipv6_process - /* - * Packet has been decrypted by ipsec, mark it in connection. - */ -- if (unlikely(skb->sp)) { -+ if (unlikely(skb_ext_exist(skb, SKB_EXT_SEC_PATH))) { - ((struct ecm_sfe_ported_ipv6_connection_instance *)feci)->flow_ipsec_state = ECM_SFE_IPSEC_STATE_WAS_DECRYPTED; - ((struct ecm_sfe_ported_ipv6_connection_instance *)feci)->return_ipsec_state = ECM_SFE_IPSEC_STATE_TO_ENCRYPT; - } diff --git a/qaa/nss/qca-nss-ecm/patches/101-Fix_Kern_Panic_on_UDP_CONNTRACK.patch b/qaa/nss/qca-nss-ecm/patches/101-Fix_Kern_Panic_on_UDP_CONNTRACK.patch deleted file mode 100644 index 6633f72b4..000000000 --- a/qaa/nss/qca-nss-ecm/patches/101-Fix_Kern_Panic_on_UDP_CONNTRACK.patch +++ /dev/null @@ -1,60 +0,0 @@ -diff --git a/frontends/nss/ecm_nss_ipv4.c b/frontends/nss/ecm_nss_ipv4.c -index 1ce4b61..29e70ba 100644 ---- a/frontends/nss/ecm_nss_ipv4.c -+++ b/frontends/nss/ecm_nss_ipv4.c -@@ -2171,6 +2171,10 @@ sync_conntrack: - - timeouts = nf_ct_timeout_lookup(ct); - -+ /* Copy of udp_get_timeouts in kernel */ -+ if (!timeouts) -+ timeouts = nf_udp_pernet(nf_ct_net(ct))->timeouts; -+ - spin_lock_bh(&ct->lock); - ct->timeout = jiffies + timeouts[UDP_CT_REPLIED]; - spin_unlock_bh(&ct->lock); -diff --git a/frontends/nss/ecm_nss_ipv6.c b/frontends/nss/ecm_nss_ipv6.c -index 2adc5ec..08253b6 100644 ---- a/frontends/nss/ecm_nss_ipv6.c -+++ b/frontends/nss/ecm_nss_ipv6.c -@@ -1883,6 +1883,10 @@ sync_conntrack: - - timeouts = nf_ct_timeout_lookup(ct); - -+ /* Copy of udp_get_timeouts in kernel */ -+ if (!timeouts) -+ timeouts = nf_udp_pernet(nf_ct_net(ct))->timeouts; -+ - spin_lock_bh(&ct->lock); - ct->timeout = jiffies + timeouts[UDP_CT_REPLIED]; - spin_unlock_bh(&ct->lock); -diff --git a/frontends/sfe/ecm_sfe_ipv4.c b/frontends/sfe/ecm_sfe_ipv4.c -index 7cfe4fc..8f525ee 100644 ---- a/frontends/sfe/ecm_sfe_ipv4.c -+++ b/frontends/sfe/ecm_sfe_ipv4.c -@@ -1608,6 +1608,10 @@ sync_conntrack: - - timeouts = nf_ct_timeout_lookup(ct); - -+ /* Copy of udp_get_timeouts in kernel */ -+ if (!timeouts) -+ timeouts = nf_udp_pernet(nf_ct_net(ct))->timeouts; -+ - spin_lock_bh(&ct->lock); - ct->timeout = jiffies + timeouts[UDP_CT_REPLIED]; - spin_unlock_bh(&ct->lock); -diff --git a/frontends/sfe/ecm_sfe_ipv6.c b/frontends/sfe/ecm_sfe_ipv6.c -index dfde309..47c531a 100644 ---- a/frontends/sfe/ecm_sfe_ipv6.c -+++ b/frontends/sfe/ecm_sfe_ipv6.c -@@ -1321,6 +1321,10 @@ sync_conntrack: - - timeouts = nf_ct_timeout_lookup(ct); - -+ /* Copy of udp_get_timeouts in kernel */ -+ if (!timeouts) -+ timeouts = nf_udp_pernet(nf_ct_net(ct))->timeouts; -+ - spin_lock_bh(&ct->lock); - ct->timeout = jiffies + timeouts[UDP_CT_REPLIED]; - spin_unlock_bh(&ct->lock); diff --git a/qaa/nss/qca-nss-ecm/patches/200-resolve-high-load.patch b/qaa/nss/qca-nss-ecm/patches/200-resolve-high-load.patch deleted file mode 100644 index 2f39d2770..000000000 --- a/qaa/nss/qca-nss-ecm/patches/200-resolve-high-load.patch +++ /dev/null @@ -1,44 +0,0 @@ -The sync update work queue tasks is calling uninterruptible sleep function, which is -causing high CPU load. Changed to interruptible sleep function. The stats update -task should be interruptible. - ---- a/frontends/nss/ecm_nss_ipv4.c -+++ b.frontends/nss/ecm_nss_ipv4.c -@@ -2411,7 +2411,7 @@ static void ecm_nss_ipv4_stats_sync_req_ - } - spin_unlock_bh(&ecm_nss_ipv4_lock); - -- usleep_range(ECM_NSS_IPV4_STATS_SYNC_UDELAY - 100, ECM_NSS_IPV4_STATS_SYNC_UDELAY); -+ msleep_interruptible(ECM_NSS_IPV4_STATS_SYNC_UDELAY / 1000); - - /* - * If index is 0, we are starting a new round, but if we still have time remain -@@ -2425,7 +2425,7 @@ static void ecm_nss_ipv4_stats_sync_req_ - } - - if (ecm_nss_ipv4_next_req_time > current_jiffies) { -- msleep(jiffies_to_msecs(ecm_nss_ipv4_next_req_time - current_jiffies)); -+ msleep_interruptible(jiffies_to_msecs(ecm_nss_ipv4_next_req_time - current_jiffies)); - } - ecm_nss_ipv4_roll_check_jiffies = jiffies; - ecm_nss_ipv4_next_req_time = ecm_nss_ipv4_roll_check_jiffies + ECM_NSS_IPV4_STATS_SYNC_PERIOD; ---- a/frontends/nss/ecm_nss_ipv6.c -+++ b.frontends/nss/ecm_nss_ipv6.c -@@ -2128,7 +2128,7 @@ static void ecm_nss_ipv6_stats_sync_req_ - } - spin_unlock_bh(&ecm_nss_ipv6_lock); - -- usleep_range(ECM_NSS_IPV6_STATS_SYNC_UDELAY - 100, ECM_NSS_IPV6_STATS_SYNC_UDELAY); -+ msleep_interruptible(ECM_NSS_IPV6_STATS_SYNC_UDELAY / 1000); - - /* - * If index is 0, we are starting a new round, but if we still have time remain -@@ -2142,7 +2142,7 @@ static void ecm_nss_ipv6_stats_sync_req_ - } - - if (ecm_nss_ipv6_next_req_time > current_jiffies) { -- msleep(jiffies_to_msecs(ecm_nss_ipv6_next_req_time - current_jiffies)); -+ msleep_interruptible(jiffies_to_msecs(ecm_nss_ipv6_next_req_time - current_jiffies)); - } - ecm_nss_ipv6_roll_check_jiffies = jiffies; - ecm_nss_ipv6_next_req_time = ecm_nss_ipv6_roll_check_jiffies + ECM_NSS_IPV6_STATS_SYNC_PERIOD; diff --git a/qaa/nss/qca-nss-ecm/patches/203-rework-nfct-notification.patch b/qaa/nss/qca-nss-ecm/patches/203-rework-nfct-notification.patch deleted file mode 100644 index a0e09c1fa..000000000 --- a/qaa/nss/qca-nss-ecm/patches/203-rework-nfct-notification.patch +++ /dev/null @@ -1,20 +0,0 @@ ---- a/ecm_conntrack_notifier.c -+++ b/ecm_conntrack_notifier.c -@@ -411,7 +411,7 @@ int ecm_conntrack_notifier_init(struct d - /* - * Eventing subsystem is available so we register a notifier hook to get fast notifications of expired connections - */ -- result = nf_conntrack_register_notifier(&init_net, &ecm_conntrack_notifier); -+ result = nf_conntrack_register_chain_notifier(&init_net, &ecm_conntrack_notifier); - if (result < 0) { - DEBUG_ERROR("Can't register nf notifier hook.\n"); - debugfs_remove_recursive(ecm_conntrack_notifier_dentry); -@@ -430,7 +430,7 @@ void ecm_conntrack_notifier_exit(void) - { - DEBUG_INFO("ECM Conntrack Notifier exit\n"); - #ifdef CONFIG_NF_CONNTRACK_EVENTS -- nf_conntrack_unregister_notifier(&init_net, &ecm_conntrack_notifier); -+ nf_conntrack_unregister_chain_notifier(&init_net, &ecm_conntrack_notifier); - #endif - /* - * Remove the debugfs files recursively. diff --git a/qaa/nss/qca-nss-ecm/patches/400-Check-TCP_UDP-conntrack-state-earlier.patch b/qaa/nss/qca-nss-ecm/patches/400-Check-TCP_UDP-conntrack-state-earlier.patch deleted file mode 100644 index b7882c1b3..000000000 --- a/qaa/nss/qca-nss-ecm/patches/400-Check-TCP_UDP-conntrack-state-earlier.patch +++ /dev/null @@ -1,236 +0,0 @@ -From 90cace88a342e77ee8ca1e961cf7b7a7930d4c89 Mon Sep 17 00:00:00 2001 -From: Murat Sezgin -Date: Mon, 9 Mar 2020 12:51:03 -0700 -Subject: [qca-nss-ecm] Check TCP/UDP conntrack state earlier - -Check the conntrack state before processing the flow -and adding it to the database. The unconfirmed -connections can be changed after the confirmation. - -Changed the TCP tracker connection state matrix to set the -state of the connection as ESTABLISHED when any of the src or -dest side is set as ESTABLISHED. With this change ECM will not -handle the SYN and SYN-ACK packets of the TCP handshake. Only the -ACK and FIN flaged packets will be used during the creation and -closing the connection respectively. - -Signed-off-by: Murat Sezgin -Change-Id: I3e0a58d604df4c6a85478ca9c05f24d50cd8c894 ---- - ecm_classifier_default.c | 36 ++++++++---------------------------- - ecm_tracker_tcp.c | 4 ++-- - frontends/nss/ecm_nss_ported_ipv4.c | 17 +++++++++++++++++ - frontends/nss/ecm_nss_ported_ipv6.c | 17 +++++++++++++++++ - frontends/sfe/ecm_sfe_ported_ipv4.c | 17 +++++++++++++++++ - frontends/sfe/ecm_sfe_ported_ipv6.c | 17 +++++++++++++++++ - 6 files changed, 78 insertions(+), 30 deletions(-) - -diff --git a/ecm_classifier_default.c b/ecm_classifier_default.c -index 22c4bec..d04cdfa 100644 ---- a/ecm_classifier_default.c -+++ b/ecm_classifier_default.c -@@ -1,6 +1,6 @@ - /* - ************************************************************************** -- * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. -+ * Copyright (c) 2014-2016, 2020, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. -@@ -285,12 +285,12 @@ static void ecm_classifier_default_process(struct ecm_classifier_instance *aci, - } - - /* -- * Check the TCP connection state. -+ * Check the TCP connection state, when the ct is NULL. -+ * ct valid case was already checked in the ecm_nss{sfe}_ported_ipv4{6}_process functions. - * If we are not established then we deny acceleration. -- * Take lead from conntrack if exists. - */ - ct = nf_ct_get(skb, &ctinfo); -- if (ct == NULL) { -+ if (!ct) { - DEBUG_TRACE("%p: No Conntrack found for packet, using ECM tracker state\n", cdii); - if (unlikely(prevailing_state != ECM_TRACKER_CONNECTION_STATE_ESTABLISHED)) { - cdii->process_response.accel_mode = ECM_CLASSIFIER_ACCELERATION_MODE_NO; -@@ -298,29 +298,10 @@ static void ecm_classifier_default_process(struct ecm_classifier_instance *aci, - } - } else { - /* -- * Unconfirmed connection may be dropped by Linux at the final step, -- * So we don't allow acceleration for the unconfirmed connections. -- */ -- if (!nf_ct_is_confirmed(ct)) { -- DEBUG_TRACE("%p: Unconfirmed connection\n", ct); -- cdii->process_response.accel_mode = ECM_CLASSIFIER_ACCELERATION_MODE_NO; -- goto return_response; -- } -- -- /* -- * Don't try to manage a non-established connection. -- */ -- if (!test_bit(IPS_ASSURED_BIT, &ct->status)) { -- DEBUG_TRACE("%p: Non-established connection\n", ct); -- cdii->process_response.accel_mode = ECM_CLASSIFIER_ACCELERATION_MODE_NO; -- goto return_response; -- } -- -- /* -- * If the connection is shutting down do not manage it. -- * state can not be SYN_SENT, SYN_RECV because connection is assured -- * Not managed states: FIN_WAIT, CLOSE_WAIT, LAST_ACK, TIME_WAIT, CLOSE. -- */ -+ * If the connection is shutting down do not manage it. -+ * state can not be SYN_SENT, SYN_RECV because connection is assured -+ * Not managed states: FIN_WAIT, CLOSE_WAIT, LAST_ACK, TIME_WAIT, CLOSE. -+ */ - spin_lock_bh(&ct->lock); - if (ct->proto.tcp.state != TCP_CONNTRACK_ESTABLISHED) { - spin_unlock_bh(&ct->lock); -@@ -333,7 +314,6 @@ static void ecm_classifier_default_process(struct ecm_classifier_instance *aci, - - return_response: - ; -- - /* - * Return the process response - */ -diff --git a/ecm_tracker_tcp.c b/ecm_tracker_tcp.c -index f073c36..e5b327a 100644 ---- a/ecm_tracker_tcp.c -+++ b/ecm_tracker_tcp.c -@@ -257,9 +257,9 @@ static DEFINE_SPINLOCK(ecm_tracker_tcp_lock); /* Global lock for the tracker gl - */ - static ecm_tracker_connection_state_t ecm_tracker_tcp_connection_state_matrix[ECM_TRACKER_SENDER_STATE_MAX][ECM_TRACKER_SENDER_STATE_MAX] = - { /* Unknown Establishing Established Closing Closed Fault */ -- /* Unknown */ {ECM_TRACKER_CONNECTION_STATE_ESTABLISHING, ECM_TRACKER_CONNECTION_STATE_ESTABLISHING, ECM_TRACKER_CONNECTION_STATE_ESTABLISHING, ECM_TRACKER_CONNECTION_STATE_FAULT, ECM_TRACKER_CONNECTION_STATE_FAULT, ECM_TRACKER_CONNECTION_STATE_FAULT}, -+ /* Unknown */ {ECM_TRACKER_CONNECTION_STATE_ESTABLISHING, ECM_TRACKER_CONNECTION_STATE_ESTABLISHING, ECM_TRACKER_CONNECTION_STATE_ESTABLISHED, ECM_TRACKER_CONNECTION_STATE_FAULT, ECM_TRACKER_CONNECTION_STATE_FAULT, ECM_TRACKER_CONNECTION_STATE_FAULT}, - /* Establishing */ {ECM_TRACKER_CONNECTION_STATE_ESTABLISHING, ECM_TRACKER_CONNECTION_STATE_ESTABLISHING, ECM_TRACKER_CONNECTION_STATE_ESTABLISHING, ECM_TRACKER_CONNECTION_STATE_FAULT, ECM_TRACKER_CONNECTION_STATE_FAULT, ECM_TRACKER_CONNECTION_STATE_FAULT}, -- /* Established */ {ECM_TRACKER_CONNECTION_STATE_ESTABLISHING, ECM_TRACKER_CONNECTION_STATE_ESTABLISHING, ECM_TRACKER_CONNECTION_STATE_ESTABLISHED, ECM_TRACKER_CONNECTION_STATE_CLOSING, ECM_TRACKER_CONNECTION_STATE_CLOSING, ECM_TRACKER_CONNECTION_STATE_FAULT}, -+ /* Established */ {ECM_TRACKER_CONNECTION_STATE_ESTABLISHED, ECM_TRACKER_CONNECTION_STATE_ESTABLISHING, ECM_TRACKER_CONNECTION_STATE_ESTABLISHED, ECM_TRACKER_CONNECTION_STATE_CLOSING, ECM_TRACKER_CONNECTION_STATE_CLOSING, ECM_TRACKER_CONNECTION_STATE_FAULT}, - /* Closing */ {ECM_TRACKER_CONNECTION_STATE_FAULT, ECM_TRACKER_CONNECTION_STATE_FAULT, ECM_TRACKER_CONNECTION_STATE_CLOSING, ECM_TRACKER_CONNECTION_STATE_CLOSING, ECM_TRACKER_CONNECTION_STATE_CLOSING, ECM_TRACKER_CONNECTION_STATE_FAULT}, - /* Closed */ {ECM_TRACKER_CONNECTION_STATE_FAULT, ECM_TRACKER_CONNECTION_STATE_FAULT, ECM_TRACKER_CONNECTION_STATE_CLOSING, ECM_TRACKER_CONNECTION_STATE_CLOSING, ECM_TRACKER_CONNECTION_STATE_CLOSED, ECM_TRACKER_CONNECTION_STATE_FAULT}, - /* Fault */ {ECM_TRACKER_CONNECTION_STATE_FAULT, ECM_TRACKER_CONNECTION_STATE_FAULT, ECM_TRACKER_CONNECTION_STATE_FAULT, ECM_TRACKER_CONNECTION_STATE_FAULT, ECM_TRACKER_CONNECTION_STATE_FAULT, ECM_TRACKER_CONNECTION_STATE_FAULT}, -diff --git a/frontends/nss/ecm_nss_ported_ipv4.c b/frontends/nss/ecm_nss_ported_ipv4.c -index 1435ec0..34c056f 100644 ---- a/frontends/nss/ecm_nss_ported_ipv4.c -+++ b/frontends/nss/ecm_nss_ported_ipv4.c -@@ -2002,8 +2002,25 @@ unsigned int ecm_nss_ported_ipv4_process(struct net_device *out_dev, struct net_ - int protocol = (int)orig_tuple->dst.protonum; - __be16 *layer4hdr = NULL; - -+ /* -+ * Unconfirmed connection may be dropped by Linux at the final step, -+ * So we don't allow acceleration for the unconfirmed connections. -+ */ -+ if (likely(ct) && !nf_ct_is_confirmed(ct)) { -+ DEBUG_WARN("%p: Unconfirmed connection\n", ct); -+ return NF_ACCEPT; -+ } -+ - if (protocol == IPPROTO_TCP) { - /* -+ * Don't try to manage a non-established connection. -+ */ -+ if (likely(ct) && !test_bit(IPS_ASSURED_BIT, &ct->status)) { -+ DEBUG_WARN("%p: Non-established TCP connection\n", ct); -+ return NF_ACCEPT; -+ } -+ -+ /* - * Extract TCP header to obtain port information - */ - tcp_hdr = ecm_tracker_tcp_check_header_and_read(skb, iph, &tcp_hdr_buff); -diff --git a/frontends/nss/ecm_nss_ported_ipv6.c b/frontends/nss/ecm_nss_ported_ipv6.c -index 4c154a6..bd6349b 100644 ---- a/frontends/nss/ecm_nss_ported_ipv6.c -+++ b/frontends/nss/ecm_nss_ported_ipv6.c -@@ -1914,8 +1914,25 @@ unsigned int ecm_nss_ported_ipv6_process(struct net_device *out_dev, - int protocol = (int)orig_tuple->dst.protonum; - __be16 *layer4hdr = NULL; - -+ /* -+ * Unconfirmed connection may be dropped by Linux at the final step, -+ * So we don't allow acceleration for the unconfirmed connections. -+ */ -+ if (likely(ct) && !nf_ct_is_confirmed(ct)) { -+ DEBUG_WARN("%p: Unconfirmed connection\n", ct); -+ return NF_ACCEPT; -+ } -+ - if (protocol == IPPROTO_TCP) { - /* -+ * Don't try to manage a non-established connection. -+ */ -+ if (likely(ct) && !test_bit(IPS_ASSURED_BIT, &ct->status)) { -+ DEBUG_WARN("%p: Non-established TCP connection\n", ct); -+ return NF_ACCEPT; -+ } -+ -+ /* - * Extract TCP header to obtain port information - */ - tcp_hdr = ecm_tracker_tcp_check_header_and_read(skb, iph, &tcp_hdr_buff); -diff --git a/frontends/sfe/ecm_sfe_ported_ipv4.c b/frontends/sfe/ecm_sfe_ported_ipv4.c -index e034cde..df1ce57 100644 ---- a/frontends/sfe/ecm_sfe_ported_ipv4.c -+++ b/frontends/sfe/ecm_sfe_ported_ipv4.c -@@ -1805,8 +1805,25 @@ unsigned int ecm_sfe_ported_ipv4_process(struct net_device *out_dev, struct net_ - int protocol = (int)orig_tuple->dst.protonum; - __be16 *layer4hdr = NULL; - -+ /* -+ * Unconfirmed connection may be dropped by Linux at the final step, -+ * So we don't allow acceleration for the unconfirmed connections. -+ */ -+ if (likely(ct) && !nf_ct_is_confirmed(ct)) { -+ DEBUG_WARN("%p: Unconfirmed connection\n", ct); -+ return NF_ACCEPT; -+ } -+ - if (protocol == IPPROTO_TCP) { - /* -+ * Don't try to manage a non-established connection. -+ */ -+ if (likely(ct) && !test_bit(IPS_ASSURED_BIT, &ct->status)) { -+ DEBUG_WARN("%p: Non-established TCP connection\n", ct); -+ return NF_ACCEPT; -+ } -+ -+ /* - * Extract TCP header to obtain port information - */ - tcp_hdr = ecm_tracker_tcp_check_header_and_read(skb, iph, &tcp_hdr_buff); -diff --git a/frontends/sfe/ecm_sfe_ported_ipv6.c b/frontends/sfe/ecm_sfe_ported_ipv6.c -index 6ac05ad..657a1c7 100644 ---- a/frontends/sfe/ecm_sfe_ported_ipv6.c -+++ b/frontends/sfe/ecm_sfe_ported_ipv6.c -@@ -1746,8 +1746,25 @@ unsigned int ecm_sfe_ported_ipv6_process(struct net_device *out_dev, - int protocol = (int)orig_tuple->dst.protonum; - __be16 *layer4hdr = NULL; - -+ /* -+ * Unconfirmed connection may be dropped by Linux at the final step, -+ * So we don't allow acceleration for the unconfirmed connections. -+ */ -+ if (likely(ct) && !nf_ct_is_confirmed(ct)) { -+ DEBUG_WARN("%p: Unconfirmed connection\n", ct); -+ return NF_ACCEPT; -+ } -+ - if (protocol == IPPROTO_TCP) { - /* -+ * Don't try to manage a non-established connection. -+ */ -+ if (likely(ct) && !test_bit(IPS_ASSURED_BIT, &ct->status)) { -+ DEBUG_WARN("%p: Non-established TCP connection\n", ct); -+ return NF_ACCEPT; -+ } -+ -+ /* - * Extract TCP header to obtain port information - */ - tcp_hdr = ecm_tracker_tcp_check_header_and_read(skb, iph, &tcp_hdr_buff); --- -cgit v1.1 - diff --git a/qaa/nss/qca-nss-ecm/patches/401-Fix-NSS-stats-request-roll-over-issue.patch b/qaa/nss/qca-nss-ecm/patches/401-Fix-NSS-stats-request-roll-over-issue.patch deleted file mode 100644 index 217054bb7..000000000 --- a/qaa/nss/qca-nss-ecm/patches/401-Fix-NSS-stats-request-roll-over-issue.patch +++ /dev/null @@ -1,52 +0,0 @@ -From 9ad19ffdcfdf77baf3abd4fcc933fd3dc8e791a5 Mon Sep 17 00:00:00 2001 -From: Murat Sezgin -Date: Sat, 20 Jun 2020 09:41:01 -0700 -Subject: [qca-nss-ecm] Fix NSS stats request roll over issue - -Use the correct timer API to check the next request time -when jiffies wrap happens. - -Signed-off-by: Murat Sezgin -Change-Id: I18646d28df7e17daeff2986dfe4bd73866d47668 ---- - frontends/nss/ecm_nss_ipv4.c | 4 ++-- - frontends/nss/ecm_nss_ipv6.c | 4 ++-- - 2 files changed, 4 insertions(+), 4 deletions(-) - -diff --git a/frontends/nss/ecm_nss_ipv4.c b/frontends/nss/ecm_nss_ipv4.c -index 3eaf5d8..80e1aee 100644 ---- a/frontends/nss/ecm_nss_ipv4.c -+++ b/frontends/nss/ecm_nss_ipv4.c -@@ -2421,10 +2421,10 @@ static void ecm_nss_ipv4_stats_sync_req_work(struct work_struct *work) - current_jiffies = jiffies; - - if (time_is_after_jiffies(ecm_nss_ipv4_roll_check_jiffies)) { -- ecm_nss_ipv4_next_req_time = 0; -+ ecm_nss_ipv4_next_req_time = jiffies + ECM_NSS_IPV4_STATS_SYNC_PERIOD; - } - -- if (ecm_nss_ipv4_next_req_time > current_jiffies) { -+ if (time_after(ecm_nss_ipv4_next_req_time, current_jiffies)) { - msleep_interruptible(jiffies_to_msecs(ecm_nss_ipv4_next_req_time - current_jiffies)); - } - ecm_nss_ipv4_roll_check_jiffies = jiffies; -diff --git a/frontends/nss/ecm_nss_ipv6.c b/frontends/nss/ecm_nss_ipv6.c -index 288dc55..483421e 100644 ---- a/frontends/nss/ecm_nss_ipv6.c -+++ b/frontends/nss/ecm_nss_ipv6.c -@@ -2135,10 +2135,10 @@ static void ecm_nss_ipv6_stats_sync_req_work(struct work_struct *work) - current_jiffies = jiffies; - - if (time_is_after_jiffies(ecm_nss_ipv6_roll_check_jiffies)) { -- ecm_nss_ipv6_next_req_time = 0; -+ ecm_nss_ipv6_next_req_time = jiffies + ECM_NSS_IPV6_STATS_SYNC_PERIOD; - } - -- if (ecm_nss_ipv6_next_req_time > current_jiffies) { -+ if (time_after(ecm_nss_ipv6_next_req_time, current_jiffies)) { - msleep_interruptible(jiffies_to_msecs(ecm_nss_ipv6_next_req_time - current_jiffies)); - } - ecm_nss_ipv6_roll_check_jiffies = jiffies; --- -cgit v1.1 - diff --git a/qaa/nss/qca-nss-ecm/patches/401-Fix-for-ref-leak-during-multicast.patch b/qaa/nss/qca-nss-ecm/patches/401-Fix-for-ref-leak-during-multicast.patch deleted file mode 100644 index e1df653b7..000000000 --- a/qaa/nss/qca-nss-ecm/patches/401-Fix-for-ref-leak-during-multicast.patch +++ /dev/null @@ -1,112 +0,0 @@ -From 4b41703a181b7187d9ff8cb744eb96d09997387c Mon Sep 17 00:00:00 2001 -From: Suman Ghosh -Date: Wed, 19 Feb 2020 15:09:19 +0530 -Subject: [qca-nss-ecm] Fix for ref leak during multicast 'to' hierarchy - creation - -Change-Id: I89df9dbe5ea054cf3b87d55ce68a751cb1d6c24f -Signed-off-by: Suman Ghosh ---- - ecm_interface.c | 34 ++++++++++++++++++++++++++++++---- - 1 file changed, 30 insertions(+), 4 deletions(-) - -diff --git a/ecm_interface.c b/ecm_interface.c -index 4f7a886..2a0ca5b 100644 ---- a/ecm_interface.c -+++ b/ecm_interface.c -@@ -3885,13 +3885,13 @@ int32_t ecm_interface_multicast_heirarchy_construct_routed(struct ecm_front_end_ - dest_dev = dev_get_by_index(&init_net, *dst_if_index); - if (!dest_dev) { - if (!src_dev_is_bridge) { -- int i; -- - /* - * If already constructed any interface heirarchies before hitting - * this error condition then Deref all interface heirarchies. - */ - if (valid_if > 0) { -+ int i; -+ - for (i = 0; i < valid_if; i++) { - ifaces = ecm_db_multicast_if_heirarchy_get(interfaces, i); - ecm_db_multicast_copy_if_heirarchy(to_list_single, ifaces); -@@ -3902,11 +3902,14 @@ int32_t ecm_interface_multicast_heirarchy_construct_routed(struct ecm_front_end_ - /* - * If valid netdev not found, Return 0 - */ -+ if (br_dev_src) { -+ dev_put(br_dev_src); -+ } -+ - return 0; - } - - dest_dev = br_dev_src; -- - } - - dest_dev_type = dest_dev->type; -@@ -3945,6 +3948,10 @@ int32_t ecm_interface_multicast_heirarchy_construct_routed(struct ecm_front_end_ - } - } - -+ if (br_dev_src && (dest_dev != br_dev_src)) { -+ dev_put(br_dev_src); -+ } -+ - dev_put(dest_dev); - return 0; - } -@@ -3972,6 +3979,10 @@ int32_t ecm_interface_multicast_heirarchy_construct_routed(struct ecm_front_end_ - ecm_db_connection_interfaces_deref(to_list_single, interface_first_base[i]); - } - -+ if (br_dev_src && (dest_dev != br_dev_src)) { -+ dev_put(br_dev_src); -+ } -+ - dev_put(dest_dev); - dev_put(mc_br_slave_dev); - return 0; -@@ -3997,6 +4008,10 @@ int32_t ecm_interface_multicast_heirarchy_construct_routed(struct ecm_front_end_ - } - } - -+ if (br_dev_src && (dest_dev != br_dev_src)) { -+ dev_put(br_dev_src); -+ } -+ - dev_put(dest_dev); - dev_put(mc_br_slave_dev); - return 0; -@@ -4032,6 +4047,10 @@ int32_t ecm_interface_multicast_heirarchy_construct_routed(struct ecm_front_end_ - } - } - -+ if (br_dev_src && (dest_dev != br_dev_src)) { -+ dev_put(br_dev_src); -+ } -+ - dev_put(dest_dev); - return 0; - } -@@ -4042,8 +4061,15 @@ int32_t ecm_interface_multicast_heirarchy_construct_routed(struct ecm_front_end_ - valid_if++; - } - -- dev_put(dest_dev); -+ if (dest_dev != br_dev_src) { -+ dev_put(dest_dev); -+ } - } -+ -+ if (br_dev_src) { -+ dev_put(br_dev_src); -+ } -+ - return total_ii_count; - } - EXPORT_SYMBOL(ecm_interface_multicast_heirarchy_construct_routed); --- -cgit v1.1 - diff --git a/qaa/nss/qca-nss-ecm/patches/401-Fix-neighbour-solicitation-send-function.patch b/qaa/nss/qca-nss-ecm/patches/401-Fix-neighbour-solicitation-send-function.patch deleted file mode 100644 index 7d32d6fd5..000000000 --- a/qaa/nss/qca-nss-ecm/patches/401-Fix-neighbour-solicitation-send-function.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 72e3ae508906553e7bc982bf3c0d99bb1cbe9008 Mon Sep 17 00:00:00 2001 -From: Murat Sezgin -Date: Wed, 20 Nov 2019 16:23:06 -0800 -Subject: [qca-nss-ecm] Fix neighbour solicitation send function. - -dst_ops->neigh_lookup function pointer is set to the -ip6_neigh_lookup function. This function returns an -error pointer with the ERR_PTR() macro. So, we should -check the return value of this function pointer with -the IS_ERR() macro. - -Change-Id: I188a6e53278faaa68f1854524f612efc1f7451fe -Signed-off-by: Murat Sezgin ---- - ecm_interface.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/ecm_interface.c b/ecm_interface.c -index 3f8554b..36509f0 100644 ---- a/ecm_interface.c -+++ b/ecm_interface.c -@@ -1100,7 +1100,7 @@ void ecm_interface_send_neighbour_solicitation(struct net_device *dev, ip_addr_t - #else - neigh = rt6i->dst.ops->neigh_lookup(&rt6i->dst, NULL, &dst_addr); - #endif -- if (neigh == NULL) { -+ if (IS_ERR(neigh)) { - DEBUG_TRACE("Neighbour lookup failure for destination IPv6 address " ECM_IP_ADDR_OCTAL_FMT "\n", ECM_IP_ADDR_TO_OCTAL(addr)); - dst_release(&rt6i->dst); - return; --- -cgit v1.1 - diff --git a/qaa/nss/qca-nss-ecm/patches/402-Reference-leak-during-multicast_PPPoE-bridge.patch b/qaa/nss/qca-nss-ecm/patches/402-Reference-leak-during-multicast_PPPoE-bridge.patch deleted file mode 100644 index 97ce7a7e8..000000000 --- a/qaa/nss/qca-nss-ecm/patches/402-Reference-leak-during-multicast_PPPoE-bridge.patch +++ /dev/null @@ -1,260 +0,0 @@ -From 7c0610828b835b2aab96dd50ec841a3a28689112 Mon Sep 17 00:00:00 2001 -From: Suman Ghosh -Date: Mon, 16 Mar 2020 15:22:18 +0530 -Subject: [qca-nss-ecm] Reference leak during multicast + PPPoE bridge - -Signed-off-by: Suman Ghosh -Change-Id: I4472035f1bbb087e637169762ae2648c0fda792a ---- - ecm_interface.c | 136 +++++++++++++++++++++++++------------------------------- - 1 file changed, 60 insertions(+), 76 deletions(-) - -diff --git a/ecm_interface.c b/ecm_interface.c -index 1614336..c0d2357 100644 ---- a/ecm_interface.c -+++ b/ecm_interface.c -@@ -3796,6 +3796,25 @@ fail: - } - - /* -+ * ecm_interface_hierarchy_delete() -+ * Delete hierarchy of the requested interfaces. -+ */ -+static inline void ecm_interface_hierarchy_delete(struct ecm_db_iface_instance *interfaces, -+ uint32_t *interface_first_base, -+ int valid_if) -+{ -+ struct ecm_db_iface_instance *to_list_single[ECM_DB_IFACE_HEIRARCHY_MAX]; -+ struct ecm_db_iface_instance *ifaces; -+ int i; -+ -+ for (i = 0; i < valid_if; i++) { -+ ifaces = ecm_db_multicast_if_heirarchy_get(interfaces, i); -+ ecm_db_multicast_copy_if_heirarchy(to_list_single, ifaces); -+ ecm_db_connection_interfaces_deref(to_list_single, interface_first_base[i]); -+ } -+} -+ -+/* - * ecm_interface_multicast_heirarchy_construct_routed() - * Create destination interface heirarchy for a routed multicast connectiona - * -@@ -3816,7 +3835,6 @@ int32_t ecm_interface_multicast_heirarchy_construct_routed(struct ecm_front_end_ - uint32_t *interface_first_base, bool mfc_update, - __be16 *layer4hdr, struct sk_buff *skb) - { -- struct ecm_db_iface_instance *to_list_single[ECM_DB_IFACE_HEIRARCHY_MAX]; - struct ecm_db_iface_instance *ifaces; - struct net_device *dest_dev = NULL; - struct net_device *br_dev_src = NULL; -@@ -3829,7 +3847,7 @@ int32_t ecm_interface_multicast_heirarchy_construct_routed(struct ecm_front_end_ - int if_index; - int ii_cnt; - int total_ii_count = 0; -- bool src_dev_is_bridge = false; -+ bool src_dev_is_bridge = false, dest_dev_is_br_dev_src = false; - - DEBUG_TRACE("Construct interface heirarchy for dest_addr: " ECM_IP_ADDR_DOT_FMT " src_addr: " ECM_IP_ADDR_DOT_FMT "total destination ifs %d\n", - ECM_IP_ADDR_TO_DOT(packet_dest_addr), ECM_IP_ADDR_TO_DOT(packet_src_addr), max_if); -@@ -3876,6 +3894,7 @@ int32_t ecm_interface_multicast_heirarchy_construct_routed(struct ecm_front_end_ - continue; - } - -+ dest_dev_is_br_dev_src = false; - dest_dev = dev_get_by_index(&init_net, *dst_if_index); - if (!dest_dev) { - if (!src_dev_is_bridge) { -@@ -3884,26 +3903,23 @@ int32_t ecm_interface_multicast_heirarchy_construct_routed(struct ecm_front_end_ - * this error condition then Deref all interface heirarchies. - */ - if (valid_if > 0) { -- int i; -- -- for (i = 0; i < valid_if; i++) { -- ifaces = ecm_db_multicast_if_heirarchy_get(interfaces, i); -- ecm_db_multicast_copy_if_heirarchy(to_list_single, ifaces); -- ecm_db_connection_interfaces_deref(to_list_single, interface_first_base[i]); -- } -+ ecm_interface_hierarchy_delete(interfaces, interface_first_base, valid_if); - } - -- /* -- * If valid netdev not found, Return 0 -- */ -- if (br_dev_src) { -- dev_put(br_dev_src); -- } -- -- return 0; -+ goto fail1; - } - - dest_dev = br_dev_src; -+ -+ /* -+ * In some cases when WAN interface is added to bridge and traffic is downstream, -+ * the bridge device is part of the destination list from MFC, and at the same time -+ * 'src_dev_is_bridge' will be true as well. In such cases we will need to release -+ * the hold on the bridge device separately for dest_dev and br_dev_src. -+ * Setting this flag to true indicates that this is not the case, -+ * and that releasing the hold once is enough -+ */ -+ dest_dev_is_br_dev_src = true; - } - - dest_dev_type = dest_dev->type; -@@ -3927,7 +3943,6 @@ int32_t ecm_interface_multicast_heirarchy_construct_routed(struct ecm_front_end_ - } - - if ((if_num < 0) || (if_num > ECM_DB_MULTICAST_IF_MAX)) { -- int i; - DEBUG_WARN("MCS is not ready\n"); - - /* -@@ -3935,19 +3950,10 @@ int32_t ecm_interface_multicast_heirarchy_construct_routed(struct ecm_front_end_ - * this error condition then Deref all interface heirarchies. - */ - if (valid_if > 0) { -- for (i = 0; i < valid_if; i++) { -- ifaces = ecm_db_multicast_if_heirarchy_get(interfaces, i); -- ecm_db_multicast_copy_if_heirarchy(to_list_single, ifaces); -- ecm_db_connection_interfaces_deref(to_list_single, interface_first_base[i]); -- } -+ ecm_interface_hierarchy_delete(interfaces, interface_first_base, valid_if); - } - -- if (br_dev_src && (dest_dev != br_dev_src)) { -- dev_put(br_dev_src); -- } -- -- dev_put(dest_dev); -- return 0; -+ goto fail2; - } - - if (in_dev && !mfc_update) { -@@ -3955,34 +3961,20 @@ int32_t ecm_interface_multicast_heirarchy_construct_routed(struct ecm_front_end_ - } - - for (br_if = 0; br_if < if_num; br_if++) { -+ int total_if = valid_if + br_if; -+ - mc_br_slave_dev = dev_get_by_index(&init_net, mc_dst_if_index[br_if]); - if (!mc_br_slave_dev) { - continue; - } - -- if ((valid_if + br_if) > ECM_DB_MULTICAST_IF_MAX) { -- int i; -- -- /* -- * If already constructed any interface heirarchies before hitting -- * this error condition then Deref all interface heirarchies. -- */ -- for (i = 0; i < (valid_if + br_if); i++) { -- ifaces = ecm_db_multicast_if_heirarchy_get(interfaces, i); -- ecm_db_multicast_copy_if_heirarchy(to_list_single, ifaces); -- ecm_db_connection_interfaces_deref(to_list_single, interface_first_base[i]); -- } -- -- if (br_dev_src && (dest_dev != br_dev_src)) { -- dev_put(br_dev_src); -- } -- -- dev_put(dest_dev); -+ if (total_if > ECM_DB_MULTICAST_IF_MAX) { -+ ecm_interface_hierarchy_delete(interfaces, interface_first_base, total_if); - dev_put(mc_br_slave_dev); -- return 0; -+ goto fail2; - } - -- ifaces = ecm_db_multicast_if_heirarchy_get(interfaces, valid_if + br_if); -+ ifaces = ecm_db_multicast_if_heirarchy_get(interfaces, total_if); - /* - * Construct a single interface heirarchy of a multicast dev. - */ -@@ -3993,25 +3985,15 @@ int32_t ecm_interface_multicast_heirarchy_construct_routed(struct ecm_front_end_ - * If already constructed any interface heirarchies before hitting - * this error condition then Deref all interface heirarchies. - */ -- if ((valid_if + br_if) > 0) { -- int i; -- for (i = 0; i < (valid_if + br_if); i++) { -- ifaces = ecm_db_multicast_if_heirarchy_get(interfaces, i); -- ecm_db_multicast_copy_if_heirarchy(to_list_single, ifaces); -- ecm_db_connection_interfaces_deref(to_list_single, interface_first_base[i]); -- } -- } -- -- if (br_dev_src && (dest_dev != br_dev_src)) { -- dev_put(br_dev_src); -+ if (total_if > 0) { -+ ecm_interface_hierarchy_delete(interfaces, interface_first_base, total_if); - } - -- dev_put(dest_dev); - dev_put(mc_br_slave_dev); -- return 0; -+ goto fail2; - } - -- interface_first = ecm_db_multicast_if_first_get_at_index(interface_first_base, (valid_if + br_if)); -+ interface_first = ecm_db_multicast_if_first_get_at_index(interface_first_base, total_if); - *interface_first = ii_cnt; - total_ii_count += ii_cnt; - dev_put(mc_br_slave_dev); -@@ -4033,20 +4015,10 @@ int32_t ecm_interface_multicast_heirarchy_construct_routed(struct ecm_front_end_ - * this error condition then Deref all interface heirarchies. - */ - if (valid_if > 0) { -- int i; -- for (i = 0; i < valid_if; i++) { -- ifaces = ecm_db_multicast_if_heirarchy_get(interfaces, i); -- ecm_db_multicast_copy_if_heirarchy(to_list_single, ifaces); -- ecm_db_connection_interfaces_deref(to_list_single, interface_first_base[i]); -- } -- } -- -- if (br_dev_src && (dest_dev != br_dev_src)) { -- dev_put(br_dev_src); -+ ecm_interface_hierarchy_delete(interfaces, interface_first_base, valid_if); - } - -- dev_put(dest_dev); -- return 0; -+ goto fail2; - } - - interface_first = ecm_db_multicast_if_first_get_at_index(interface_first_base, valid_if); -@@ -4055,7 +4027,7 @@ int32_t ecm_interface_multicast_heirarchy_construct_routed(struct ecm_front_end_ - valid_if++; - } - -- if (dest_dev != br_dev_src) { -+ if (!dest_dev_is_br_dev_src) { - dev_put(dest_dev); - } - } -@@ -4065,6 +4037,18 @@ int32_t ecm_interface_multicast_heirarchy_construct_routed(struct ecm_front_end_ - } - - return total_ii_count; -+ -+fail2: -+ if (!dest_dev_is_br_dev_src) { -+ dev_put(dest_dev); -+ } -+ -+fail1: -+ if (br_dev_src) { -+ dev_put(br_dev_src); -+ } -+ -+ return 0; - } - EXPORT_SYMBOL(ecm_interface_multicast_heirarchy_construct_routed); - --- -cgit v1.1 - diff --git a/qaa/nss/qca-nss-ecm/patches/403-Access-global-accelerated-count-under-lock.patch b/qaa/nss/qca-nss-ecm/patches/403-Access-global-accelerated-count-under-lock.patch deleted file mode 100644 index d458e1134..000000000 --- a/qaa/nss/qca-nss-ecm/patches/403-Access-global-accelerated-count-under-lock.patch +++ /dev/null @@ -1,59 +0,0 @@ -From 65a49ebd1bd12b9952dfa214de0a2da43ba2abed Mon Sep 17 00:00:00 2001 -From: Bhaskar Valaboju -Date: Tue, 13 Aug 2019 14:21:03 +0530 -Subject: [qca-nss-ecm]: Access global ipv4/ipv6 accelerated count under lock - -Flow accelerated count maintained as global variables are accessed -in multiple kernel contexts. These counters are updated under lock, -but read without lock. Read is in kernel thread context (workqueue) -and sometimes it is taking stale entry (0) and doesn't change. -Lock is added to read correct value. - -Change-Id: I74cf27fe5097c6ae7dfcc06319762a8a322d79a3 -Signed-off-by: Bhaskar Valaboju ---- - frontends/nss/ecm_nss_ipv4.c | 3 +++ - frontends/nss/ecm_nss_ipv6.c | 3 +++ - 2 files changed, 6 insertions(+) - -(limited to 'frontends') - -diff --git a/frontends/nss/ecm_nss_ipv4.c b/frontends/nss/ecm_nss_ipv4.c -index afd660e..4e66cdf 100644 ---- a/frontends/nss/ecm_nss_ipv4.c -+++ b/frontends/nss/ecm_nss_ipv4.c -@@ -2288,10 +2288,13 @@ static void ecm_nss_ipv4_stats_sync_req_work(struct work_struct *work) - int retry = 3; - unsigned long int current_jiffies; - -+ spin_lock_bh(&ecm_nss_ipv4_lock); - if (ecm_nss_ipv4_accelerated_count == 0) { -+ spin_unlock_bh(&ecm_nss_ipv4_lock); - DEBUG_TRACE("There is no accelerated IPv4 connection\n"); - goto reschedule; - } -+ spin_unlock_bh(&ecm_nss_ipv4_lock); - - usleep_range(ECM_NSS_IPV4_STATS_SYNC_UDELAY - 100, ECM_NSS_IPV4_STATS_SYNC_UDELAY); - -diff --git a/frontends/nss/ecm_nss_ipv6.c b/frontends/nss/ecm_nss_ipv6.c -index 1f7f51e..55849e7 100644 ---- a/frontends/nss/ecm_nss_ipv6.c -+++ b/frontends/nss/ecm_nss_ipv6.c -@@ -1998,10 +1998,13 @@ static void ecm_nss_ipv6_stats_sync_req_work(struct work_struct *work) - int retry = 3; - unsigned long int current_jiffies; - -+ spin_lock_bh(&ecm_nss_ipv6_lock); - if (ecm_nss_ipv6_accelerated_count == 0) { -+ spin_unlock_bh(&ecm_nss_ipv6_lock); - DEBUG_TRACE("There is no accelerated IPv6 connection\n"); - goto reschedule; - } -+ spin_unlock_bh(&ecm_nss_ipv6_lock); - - usleep_range(ECM_NSS_IPV6_STATS_SYNC_UDELAY - 100, ECM_NSS_IPV6_STATS_SYNC_UDELAY); - --- -cgit v1.1 - diff --git a/qaa/nss/qca-nss-ecm/patches/403-Fix-IPv6-neighbor-solicitation-request.patch b/qaa/nss/qca-nss-ecm/patches/403-Fix-IPv6-neighbor-solicitation-request.patch deleted file mode 100644 index 7639b88a0..000000000 --- a/qaa/nss/qca-nss-ecm/patches/403-Fix-IPv6-neighbor-solicitation-request.patch +++ /dev/null @@ -1,83 +0,0 @@ -From b96002061178f399c1e58a9ad821e5096a64f788 Mon Sep 17 00:00:00 2001 -From: Murat Sezgin -Date: Mon, 23 Mar 2020 10:59:39 -0700 -Subject: [qca-nss-ecm] Fix IPv6 neighbor solicitation request - -Send the solicitation request to the GW address, when -a GW address is found, while establishing the node instance. - -Signed-off-by: Murat Sezgin -Change-Id: I2187569bcfd05b0d091cf8c79171ee3c41c39cb9 ---- - frontends/nss/ecm_nss_ipv6.c | 7 ++++--- - frontends/nss/ecm_nss_multicast_ipv6.c | 9 +++++++++ - frontends/sfe/ecm_sfe_ipv6.c | 7 ++++--- - 3 files changed, 17 insertions(+), 6 deletions(-) - -diff --git a/frontends/nss/ecm_nss_ipv6.c b/frontends/nss/ecm_nss_ipv6.c -index c7dd37f..9011e18 100644 ---- a/frontends/nss/ecm_nss_ipv6.c -+++ b/frontends/nss/ecm_nss_ipv6.c -@@ -527,13 +527,14 @@ struct ecm_db_node_instance *ecm_nss_ipv6_node_establish_and_ref(struct ecm_fron - struct net_device *master; - master = ecm_interface_get_and_hold_dev_master(dev); - DEBUG_ASSERT(master, "Expected a master\n"); -- ecm_interface_send_neighbour_solicitation(master, addr); -+ ecm_interface_send_neighbour_solicitation(master, gw_addr); - dev_put(master); - } else { -- ecm_interface_send_neighbour_solicitation(dev, addr); -+ ecm_interface_send_neighbour_solicitation(dev, gw_addr); - } - -- DEBUG_TRACE("Failed to obtain mac for host " ECM_IP_ADDR_OCTAL_FMT "\n", ECM_IP_ADDR_TO_OCTAL(addr)); -+ DEBUG_TRACE("Failed to obtain mac for host " ECM_IP_ADDR_OCTAL_FMT " gw: " ECM_IP_ADDR_OCTAL_FMT "\n", -+ ECM_IP_ADDR_TO_OCTAL(addr), ECM_IP_ADDR_TO_OCTAL(gw_addr)); - return NULL; - } - done: -diff --git a/frontends/nss/ecm_nss_multicast_ipv6.c b/frontends/nss/ecm_nss_multicast_ipv6.c -index a361eec..38fde95 100644 ---- a/frontends/nss/ecm_nss_multicast_ipv6.c -+++ b/frontends/nss/ecm_nss_multicast_ipv6.c -@@ -2558,6 +2558,15 @@ static struct ecm_db_node_instance *ecm_nss_multicast_ipv6_node_establish_and_re - #endif - if (!ecm_interface_mac_addr_get(addr, node_addr, &on_link, gw_addr)) { - DEBUG_TRACE("Failed to obtain mac for host " ECM_IP_ADDR_OCTAL_FMT "\n", ECM_IP_ADDR_TO_OCTAL(addr)); -+ -+ /* -+ * If there is a gw_addr found during the lookup, use that address -+ * for neighbour solicitation request. -+ */ -+ if (!ECM_IP_ADDR_IS_NULL(gw_addr)) { -+ ECM_IP_ADDR_COPY(addr, gw_addr); -+ } -+ - if (ecm_front_end_is_bridge_port(dev)) { - struct net_device *master; - master = ecm_interface_get_and_hold_dev_master(dev); -diff --git a/frontends/sfe/ecm_sfe_ipv6.c b/frontends/sfe/ecm_sfe_ipv6.c -index 3fd5d46..51a9ccb 100644 ---- a/frontends/sfe/ecm_sfe_ipv6.c -+++ b/frontends/sfe/ecm_sfe_ipv6.c -@@ -256,13 +256,14 @@ struct ecm_db_node_instance *ecm_sfe_ipv6_node_establish_and_ref(struct ecm_fron - struct net_device *master; - master = ecm_interface_get_and_hold_dev_master(dev); - DEBUG_ASSERT(master, "Expected a master\n"); -- ecm_interface_send_neighbour_solicitation(master, addr); -+ ecm_interface_send_neighbour_solicitation(master, gw_addr); - dev_put(master); - } else { -- ecm_interface_send_neighbour_solicitation(dev, addr); -+ ecm_interface_send_neighbour_solicitation(dev, gw_addr); - } - -- DEBUG_TRACE("Failed to obtain mac for host " ECM_IP_ADDR_OCTAL_FMT "\n", ECM_IP_ADDR_TO_OCTAL(addr)); -+ DEBUG_TRACE("Failed to obtain mac for host " ECM_IP_ADDR_OCTAL_FMT " gw: " ECM_IP_ADDR_OCTAL_FMT "\n", -+ ECM_IP_ADDR_TO_OCTAL(addr), ECM_IP_ADDR_TO_OCTAL(gw_addr)); - return NULL; - } - done: --- -cgit v1.1 - diff --git a/qaa/nss/qca-nss-ecm/patches/404-IPv6-solicitation-fix-with-zero-gateway-address.patch b/qaa/nss/qca-nss-ecm/patches/404-IPv6-solicitation-fix-with-zero-gateway-address.patch deleted file mode 100644 index bdedff442..000000000 --- a/qaa/nss/qca-nss-ecm/patches/404-IPv6-solicitation-fix-with-zero-gateway-address.patch +++ /dev/null @@ -1,63 +0,0 @@ -From 5b51ae2f1eca61c6f68e40a05333da5a362ff327 Mon Sep 17 00:00:00 2001 -From: Murat Sezgin -Date: Mon, 13 Apr 2020 09:01:48 -0700 -Subject: [qca-nss-ecm] IPv6 solicitation fix with zero gateway address - -The ECM function can find a zero gateway address for -a host IP address. In this case, we need to use the -host IP address while sending the solicitation request. - -Signed-off-by: Murat Sezgin -Change-Id: I1979834088ddfe1843566f51f64348f79e2df0fc ---- - frontends/nss/ecm_nss_ipv6.c | 11 ++++++++++- - frontends/sfe/ecm_sfe_ipv6.c | 11 ++++++++++- - 2 files changed, 20 insertions(+), 2 deletions(-) - -diff --git a/frontends/nss/ecm_nss_ipv6.c b/frontends/nss/ecm_nss_ipv6.c -index a05781b..9eb591c 100644 ---- a/frontends/nss/ecm_nss_ipv6.c -+++ b/frontends/nss/ecm_nss_ipv6.c -@@ -516,7 +516,16 @@ struct ecm_db_node_instance *ecm_nss_ipv6_node_establish_and_ref(struct ecm_fron - return NULL; - } - -- DEBUG_TRACE("Have a gw address " ECM_IP_ADDR_OCTAL_FMT "\n", ECM_IP_ADDR_TO_OCTAL(gw_addr)); -+ /* -+ * The found gateway address can be all zeros, -+ * so in this case use the host address. -+ */ -+ if (ECM_IP_ADDR_IS_NULL(gw_addr)) { -+ DEBUG_TRACE("GW address is found as zeros, so use host IP\n"); -+ ECM_IP_ADDR_COPY(gw_addr, addr); -+ } else { -+ DEBUG_TRACE("Have a gw address " ECM_IP_ADDR_OCTAL_FMT "\n", ECM_IP_ADDR_TO_OCTAL(gw_addr)); -+ } - - if (ecm_interface_mac_addr_get_no_route(dev, gw_addr, node_addr)) { - DEBUG_TRACE("Found the mac address for gateway\n"); -diff --git a/frontends/sfe/ecm_sfe_ipv6.c b/frontends/sfe/ecm_sfe_ipv6.c -index 51a9ccb..e609df7 100644 ---- a/frontends/sfe/ecm_sfe_ipv6.c -+++ b/frontends/sfe/ecm_sfe_ipv6.c -@@ -245,7 +245,16 @@ struct ecm_db_node_instance *ecm_sfe_ipv6_node_establish_and_ref(struct ecm_fron - return NULL; - } - -- DEBUG_TRACE("Have a gw address " ECM_IP_ADDR_OCTAL_FMT "\n", ECM_IP_ADDR_TO_OCTAL(gw_addr)); -+ /* -+ * The found gateway address can be all zeros, -+ * so in this case use the host address. -+ */ -+ if (ECM_IP_ADDR_IS_NULL(gw_addr)) { -+ DEBUG_TRACE("GW address is found as zeros, so use host IP\n"); -+ ECM_IP_ADDR_COPY(gw_addr, addr); -+ } else { -+ DEBUG_TRACE("Have a gw address " ECM_IP_ADDR_OCTAL_FMT "\n", ECM_IP_ADDR_TO_OCTAL(gw_addr)); -+ } - - if (ecm_interface_mac_addr_get_no_route(dev, gw_addr, node_addr)) { - DEBUG_TRACE("Found the mac address for gateway\n"); --- -cgit v1.1 - diff --git a/qaa/nss/qca-nss-ecm/patches/405-Allow-egress-on-same-port-when-bridge-hairpin-is-enabled.patch b/qaa/nss/qca-nss-ecm/patches/405-Allow-egress-on-same-port-when-bridge-hairpin-is-enabled.patch deleted file mode 100644 index a236fb757..000000000 --- a/qaa/nss/qca-nss-ecm/patches/405-Allow-egress-on-same-port-when-bridge-hairpin-is-enabled.patch +++ /dev/null @@ -1,126 +0,0 @@ -From e23eabd570eabde1d1fc803127a97fd101642467 Mon Sep 17 00:00:00 2001 -From: Varsha Mishra -Date: Fri, 12 Jun 2020 01:06:58 +0530 -Subject: [qca-nss-ecm] Allow egress on same port when bridge hairpin is - enabled. - -When bridge hairpin is enabled, allow egress on same port. Wi-Fi intrabss -frames are getting exceptioned to stack. Bridge gets to make the decision -whether these frames need to be forwarded or dropped. - -Signed-off-by: Varsha Mishra -Change-Id: Ibdd72264d8887330ba0297ed12cbcfc390065bff ---- - frontends/nss/ecm_nss_ipv4.c | 28 ++++++++++++++++++++++------ - frontends/nss/ecm_nss_ipv6.c | 28 ++++++++++++++++++++++------ - 2 files changed, 44 insertions(+), 12 deletions(-) - -diff --git a/frontends/nss/ecm_nss_ipv4.c b/frontends/nss/ecm_nss_ipv4.c -index 60f799b..51c9ebf 100644 ---- a/frontends/nss/ecm_nss_ipv4.c -+++ b/frontends/nss/ecm_nss_ipv4.c -@@ -1756,7 +1756,9 @@ static unsigned int ecm_nss_ipv4_bridge_post_routing_hook(void *priv, - * Case 2: - * For routed packets the skb will have the src mac matching the bridge mac. - * Case 3: -- * If the packet was not local (case 1) or routed (case 2) then we process. -+ * If the packet was not local (case 1) or routed (case 2) then -+ * we process. There is an exception to case 2: when hairpin mode -+ * is enabled, we process. - */ - - /* -@@ -1768,14 +1770,28 @@ static unsigned int ecm_nss_ipv4_bridge_post_routing_hook(void *priv, - dev_put(bridge); - return NF_ACCEPT; - } -+ -+ /* -+ * This flag needs to be checked in slave port(eth0/ath0) -+ * and not on master interface(br-lan). Hairpin flag can be -+ * enabled/disabled for ports individually. -+ */ - if (in == out) { -- DEBUG_TRACE("skb: %p, bridge: %p (%s), port bounce on %p (%s)\n", skb, bridge, bridge->name, out, out->name); -- dev_put(in); -- dev_put(bridge); -- return NF_ACCEPT; -+ if (!br_is_hairpin_enabled(in)) { -+ DEBUG_TRACE("skb: %p, bridge: %p (%s), ignoring" -+ "the packet, hairpin not enabled" -+ "on port %p (%s)\n", skb, bridge, -+ bridge->name, out, out->name); -+ dev_put(in); -+ dev_put(bridge); -+ return NF_ACCEPT; -+ } -+ DEBUG_TRACE("skb: %p, bridge: %p (%s), hairpin enabled on port" -+ "%p (%s)\n", skb, bridge, bridge->name, out, out->name); - } -+ -+ /* -+ * Case 2: Routed trafffic would be handled by the INET post routing. -+ */ - if (!ecm_mac_addr_equal(skb_eth_hdr->h_source, bridge->dev_addr)) { -- /* -- * Case 2: Routed trafffic would be handled by the INET post routing. -- */ - DEBUG_TRACE("skb: %p, Ignoring routed packet to bridge: %p (%s)\n", skb, bridge, bridge->name); - goto skip_ipv4_bridge_flow; - } -diff --git a/frontends/nss/ecm_nss_ipv6.c b/frontends/nss/ecm_nss_ipv6.c -index 6ad425e..160c94c 100644 ---- a/frontends/nss/ecm_nss_ipv6.c -+++ b/frontends/nss/ecm_nss_ipv6.c -@@ -1498,7 +1498,9 @@ static unsigned int ecm_nss_ipv6_bridge_post_routing_hook(void *priv, - * Case 2: - * For routed packets the skb will have the src mac matching the bridge mac. - * Case 3: -- * If the packet was not local (case 1) or routed (case 2) then we process. -+ * If the packet was not local (case 1) or routed (case 2) then -+ * we process. There is an exception to case 2: when hairpin mode -+ * is enabled, we process. - */ - - /* -@@ -1510,14 +1512,28 @@ static unsigned int ecm_nss_ipv6_bridge_post_routing_hook(void *priv, - dev_put(bridge); - return NF_ACCEPT; - } -+ -+ /* -+ * This flag needs to be checked in slave port(eth0/ath0) -+ * and not on master interface(br-lan). Hairpin flag can be -+ * enabled/disabled for ports individually. -+ */ - if (in == out) { -- DEBUG_TRACE("skb: %p, bridge: %p (%s), port bounce on %p (%s)\n", skb, bridge, bridge->name, out, out->name); -- dev_put(in); -- dev_put(bridge); -- return NF_ACCEPT; -+ if (!br_is_hairpin_enabled(in)) { -+ DEBUG_TRACE("skb: %p, bridge: %p (%s), ignoring" -+ "the packet, hairpin not enabled" -+ "on port %p (%s)\n", skb, bridge, -+ bridge->name, out, out->name); -+ dev_put(in); -+ dev_put(bridge); -+ return NF_ACCEPT; -+ } -+ DEBUG_TRACE("skb: %p, bridge: %p (%s), hairpin enabled on port" -+ "%p (%s)\n", skb, bridge, bridge->name, out, out->name); - } -+ -+ /* -+ * Case 2: Routed trafffic would be handled by the INET post routing. -+ */ - if (!ecm_mac_addr_equal(skb_eth_hdr->h_source, bridge->dev_addr)) { -- /* -- * Case 2: Routed trafffic would be handled by the INET post routing. -- */ - DEBUG_TRACE("skb: %p, Ignoring routed packet to bridge: %p (%s)\n", skb, bridge, bridge->name); - goto skip_ipv6_bridge_flow; - } --- -cgit v1.1 - diff --git a/qaa/nss/qca-nss-gmac/Makefile b/qaa/nss/qca-nss-gmac/Makefile deleted file mode 100644 index 8b39f0437..000000000 --- a/qaa/nss/qca-nss-gmac/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -include $(TOPDIR)/rules.mk -include $(INCLUDE_DIR)/kernel.mk - -PKG_NAME:=qca-nss-gmac -PKG_RELEASE:=1 - -PKG_SOURCE_PROTO:=git -PKG_SOURCE_URL:=https://source.codeaurora.org/quic/qsdk/oss/lklm/nss-gmac -PKG_SOURCE_VERSION:=9b74deef2816d91e58926e6fab7a6ff931eb3b22 -PKG_MIRROR_HASH:=a1939caa638414323e60f7d29f797ea831c6036e424b8e7bd6cf2d3d874de064 - -include $(INCLUDE_DIR)/package.mk - -define KernelPackage/qca-nss-gmac - SECTION:=kernel - CATEGORY:=Kernel modules - SUBMENU:=Network Devices - DEPENDS:=@TARGET_ipq806x @LINUX_5_4 - TITLE:=Kernel driver for NSS gmac - FILES:=$(PKG_BUILD_DIR)/ipq806x/qca-nss-gmac.ko - AUTOLOAD:=$(call AutoLoad,31,qca-nss-gmac) -endef - -define KernelPackage/qca-nss-gmac/Description -This package contains a NSS driver for QCA chipset -endef - -define Build/InstallDev - mkdir -p $(1)/usr/include/qca-nss-gmac - $(CP) $(PKG_BUILD_DIR)/ipq806x/exports/* $(1)/usr/include/qca-nss-gmac/ -endef - -EXTRA_CFLAGS+= \ - -DCONFIG_NSS_DEBUG_LEVEL=4 \ - -I$(PKG_BUILD_DIR)/nss_hal/include \ - -I$(PKG_BUILD_DIR)/nss_hal/$(BOARD) - -define Build/Compile - $(MAKE) $(PKG_JOBS) -C "$(LINUX_DIR)" \ - $(KERNEL_MAKE_FLAGS) \ - $(PKG_MAKE_FLAGS) \ - M="$(PKG_BUILD_DIR)" \ - EXTRA_CFLAGS="$(EXTRA_CFLAGS)" \ - modules -endef - -$(eval $(call KernelPackage,qca-nss-gmac)) diff --git a/qaa/nss/qca-nss-gmac/patches/100-kernel-5.4-support.patch b/qaa/nss/qca-nss-gmac/patches/100-kernel-5.4-support.patch deleted file mode 100644 index f3b91abc2..000000000 --- a/qaa/nss/qca-nss-gmac/patches/100-kernel-5.4-support.patch +++ /dev/null @@ -1,279 +0,0 @@ ---- a/ipq806x/nss_gmac_ctrl.c -+++ b/ipq806x/nss_gmac_ctrl.c -@@ -322,16 +322,15 @@ void nss_gmac_tx_rx_desc_init(struct nss - * (for example "ifconfig eth0"). - * @param[in] pointer to net_device structure. - * @param[in] pointer to net_device_stats64 structure. -- * @return Returns pointer to net_device_stats64 structure. - */ --struct rtnl_link_stats64 *nss_gmac_get_stats64(struct net_device *netdev, -+void nss_gmac_get_stats64(struct net_device *netdev, - struct rtnl_link_stats64 *stats) - { - struct nss_gmac_dev *gmacdev = (struct nss_gmac_dev *)netdev_priv(netdev); - BUG_ON(gmacdev == NULL); - - if (!gmacdev->data_plane_ops) -- return stats; -+ return; - - spin_lock_bh(&gmacdev->stats_lock); - gmacdev->data_plane_ops->get_stats(gmacdev->data_plane_ctx, &gmacdev->nss_stats); -@@ -354,8 +353,6 @@ struct rtnl_link_stats64 *nss_gmac_get_s - stats->tx_fifo_errors = gmacdev->nss_stats.tx_underflow_errors; - stats->tx_window_errors = gmacdev->nss_stats.tx_late_collision_errors; - spin_unlock_bh(&gmacdev->stats_lock); -- -- return stats; - } - - -@@ -439,7 +436,7 @@ static int nss_gmac_mtnp_show(struct dev - static int nss_gmac_tstamp_show(struct device *dev, struct device_attribute *attr, char *buf) - { - struct nss_gmac_dev *gmacdev = (struct nss_gmac_dev *)netdev_priv(to_net_dev(dev)); -- struct timeval tv; -+ struct timespec64 ts64; - uint32_t ret, timeout; - uint32_t ts_hi, ts_lo; - -@@ -459,11 +456,12 @@ static int nss_gmac_tstamp_show(struct d - return -1; - } - -- do_gettimeofday(&tv); -+ ktime_get_real_ts64(&ts64); - - ret = snprintf( - buf, PAGE_SIZE, -- "sec:%u nsec:%u time-of-day: %12d.%06d \n", ts_hi, ts_lo, (int)tv.tv_sec, (int)tv.tv_usec); -+ "sec:%u nsec:%u time-of-day: %12d.%06d \n", \ -+ ts_hi, ts_lo, (int)ts64.tv_sec, (int)(ts64.tv_nsec / NSEC_PER_USEC)); - - return ret; - } -@@ -951,7 +949,7 @@ static const struct net_device_ops nss_g - * @param[in] pointer to advertised features - * @return void - */ --static void nss_gmac_update_features(uint32_t *supp, uint32_t *adv) -+static void nss_gmac_update_features(long unsigned int *supp, long unsigned int *adv) - { - *supp |= NSS_GMAC_SUPPORTED_FEATURES; - *adv |= NSS_GMAC_ADVERTISED_FEATURES; -@@ -1409,8 +1407,8 @@ static int32_t nss_gmac_probe(struct pla - goto nss_gmac_phy_attach_fail; - } - -- nss_gmac_update_features(&(gmacdev->phydev->supported), -- &(gmacdev->phydev->advertising)); -+ nss_gmac_update_features(gmacdev->phydev->supported, -+ gmacdev->phydev->advertising); - gmacdev->phydev->irq = PHY_POLL; - netdev_dbg(netdev, "PHY %s attach OK\n", phy_id); - -@@ -1440,6 +1438,8 @@ static int32_t nss_gmac_probe(struct pla - netdev_dbg(netdev, "%s MII_PHYSID2 - 0x%04x\n", netdev->name, - nss_gmac_mii_rd_reg(gmacdev, gmacdev->phy_base, MII_PHYSID2)); - } else if (gmacdev->phy_base != NSS_GMAC_NO_MDIO_PHY) { -+ SET_NETDEV_DEV(netdev, gmacdev->miibus->parent); -+ - /* - * Issue a phy_attach for the interface connected to a switch - */ ---- a/ipq806x/nss_gmac_ethtool.c -+++ b/ipq806x/nss_gmac_ethtool.c -@@ -143,9 +143,9 @@ static const struct nss_gmac_ethtool_sta - /** - * @brief Array of strings describing private flag names - */ --static const char *gmac_strings_priv_flags[] = { -- "linkpoll", -- "tstamp", -+static const char *gmac_strings_priv_flags[][ETH_GSTRING_LEN] = { -+ {"linkpoll"}, -+ {"tstamp"}, - }; - - #define NSS_GMAC_STATS_LEN ARRAY_SIZE(gmac_gstrings_stats) -@@ -292,6 +292,7 @@ static int nss_gmac_set_pauseparam(struc - { - struct nss_gmac_dev *gmacdev = (struct nss_gmac_dev *)netdev_priv(netdev); - struct phy_device *phydev; -+ long unsigned int *advertising; - - BUG_ON(gmacdev == NULL); - BUG_ON(gmacdev->netdev != netdev); -@@ -327,14 +328,15 @@ static int nss_gmac_set_pauseparam(struc - phydev = gmacdev->phydev; - - /* Update flow control advertisment */ -- phydev->advertising &= ~(ADVERTISED_Pause | ADVERTISED_Asym_Pause); -+ advertising = phydev->advertising; -+ *advertising &= ~(ADVERTISED_Pause | ADVERTISED_Asym_Pause); - - if (gmacdev->pause & FLOW_CTRL_RX) -- phydev->advertising |= -+ *advertising |= - (ADVERTISED_Pause | ADVERTISED_Asym_Pause); - - if (gmacdev->pause & FLOW_CTRL_TX) -- phydev->advertising |= ADVERTISED_Asym_Pause; -+ *advertising |= ADVERTISED_Asym_Pause; - - genphy_config_aneg(gmacdev->phydev); - -@@ -396,12 +398,13 @@ static uint32_t nss_gmac_get_msglevel(st - * @param[in] pointer to struct net_device. - * @param[in] pointer to struct ethtool_cmd. - */ --static int32_t nss_gmac_get_settings(struct net_device *netdev, -- struct ethtool_cmd *ecmd) -+static int nss_gmac_get_settings(struct net_device *netdev, -+ struct ethtool_link_ksettings *elk) - { - struct nss_gmac_dev *gmacdev = (struct nss_gmac_dev *)netdev_priv(netdev); - struct phy_device *phydev = NULL; - uint16_t phyreg; -+ u32 lp_advertising = 0; - - BUG_ON(gmacdev == NULL); - -@@ -413,10 +416,10 @@ static int32_t nss_gmac_get_settings(str - */ - if (!test_bit(__NSS_GMAC_LINKPOLL, &gmacdev->flags)) { - if (gmacdev->forced_speed != SPEED_UNKNOWN) { -- ethtool_cmd_speed_set(ecmd, gmacdev->forced_speed); -- ecmd->duplex = gmacdev->forced_duplex; -- ecmd->mdio_support = 0; -- ecmd->lp_advertising = 0; -+ elk->base.speed = gmacdev->forced_speed; -+ elk->base.duplex = gmacdev->forced_duplex; -+ elk->base.mdio_support = 0; -+ ethtool_convert_legacy_u32_to_link_mode(elk->link_modes.lp_advertising, 0); - return 0; - } else { - /* Non-link polled interfaced must have a forced -@@ -429,63 +429,59 @@ static int32_t nss_gmac_get_settings(struct net_device *netdev, - - /* update PHY status */ - if (phydev->is_c45 == true) { -- ecmd->mdio_support = ETH_MDIO_SUPPORTS_C45; -+ elk->base.mdio_support = ETH_MDIO_SUPPORTS_C45; - } else { - if (genphy_read_status(phydev) != 0) { - return -EIO; - } -- ecmd->mdio_support = ETH_MDIO_SUPPORTS_C22; -+ elk->base.mdio_support = ETH_MDIO_SUPPORTS_C22; - } - - /* Populate capabilities advertised by self */ -- ecmd->advertising = phydev->advertising; -+ bitmap_copy(elk->link_modes.advertising, phydev->advertising, __ETHTOOL_LINK_MODE_MASK_NBITS); - -- ecmd->autoneg = phydev->autoneg; -- -- if (gmacdev->link_state == LINKDOWN) { -- ethtool_cmd_speed_set(ecmd, SPEED_UNKNOWN); -- ecmd->duplex = DUPLEX_UNKNOWN; -- } else { -- ethtool_cmd_speed_set(ecmd, phydev->speed); -- ecmd->duplex = phydev->duplex; -- } -- -- ecmd->port = PORT_TP; -- ecmd->phy_address = gmacdev->phy_base; -- ecmd->transceiver = XCVR_EXTERNAL; -+ elk->base.autoneg = phydev->autoneg; -+ elk->base.speed = phydev->speed; -+ elk->base.duplex = phydev->duplex; -+ elk->base.port = PORT_TP; -+ elk->base.phy_address = gmacdev->phy_base; -+ elk->base.transceiver = XCVR_EXTERNAL; - - /* Populate supported capabilities */ -- ecmd->supported = phydev->supported; -+ bitmap_copy(elk->link_modes.supported, phydev->supported, __ETHTOOL_LINK_MODE_MASK_NBITS); - - if (phydev->is_c45 == true) - return 0; - - /* Populate capabilities advertised by link partner */ -+ ethtool_convert_link_mode_to_legacy_u32(&lp_advertising, elk->link_modes.lp_advertising); - phyreg = nss_gmac_mii_rd_reg(gmacdev, gmacdev->phy_base, MII_LPA); - if (phyreg & LPA_10HALF) -- ecmd->lp_advertising |= ADVERTISED_10baseT_Half; -+ lp_advertising |= ADVERTISED_10baseT_Half; - - if (phyreg & LPA_10FULL) -- ecmd->lp_advertising |= ADVERTISED_10baseT_Full; -+ lp_advertising |= ADVERTISED_10baseT_Full; - - if (phyreg & LPA_100HALF) -- ecmd->lp_advertising |= ADVERTISED_100baseT_Half; -+ lp_advertising |= ADVERTISED_100baseT_Half; - - if (phyreg & LPA_100FULL) -- ecmd->lp_advertising |= ADVERTISED_100baseT_Full; -+ lp_advertising |= ADVERTISED_100baseT_Full; - - if (phyreg & LPA_PAUSE_CAP) -- ecmd->lp_advertising |= ADVERTISED_Pause; -+ lp_advertising |= ADVERTISED_Pause; - - if (phyreg & LPA_PAUSE_ASYM) -- ecmd->lp_advertising |= ADVERTISED_Asym_Pause; -+ lp_advertising |= ADVERTISED_Asym_Pause; - - phyreg = nss_gmac_mii_rd_reg(gmacdev, gmacdev->phy_base, MII_STAT1000); - if (phyreg & LPA_1000HALF) -- ecmd->lp_advertising |= ADVERTISED_1000baseT_Half; -+ lp_advertising |= ADVERTISED_1000baseT_Half; - - if (phyreg & LPA_1000FULL) -- ecmd->lp_advertising |= ADVERTISED_1000baseT_Full; -+ lp_advertising |= ADVERTISED_1000baseT_Full; -+ -+ ethtool_convert_legacy_u32_to_link_mode(elk->link_modes.lp_advertising, lp_advertising); - - return 0; - } -@@ -489,8 +495,8 @@ static int32_t nss_gmac_get_settings(str - * @param[in] pointer to struct net_device. - * @param[in] pointer to struct ethtool_cmd. - */ --static int32_t nss_gmac_set_settings(struct net_device *netdev, -- struct ethtool_cmd *ecmd) -+static int nss_gmac_set_settings(struct net_device *netdev, -+ const struct ethtool_link_ksettings *elk) - { - struct nss_gmac_dev *gmacdev = (struct nss_gmac_dev *)netdev_priv(netdev); - struct phy_device *phydev = NULL; -@@ -512,13 +518,13 @@ static int32_t nss_gmac_set_settings(str - return -EPERM; - } - -- if (ecmd->autoneg == AUTONEG_ENABLE) { -+ if (elk->base.autoneg == AUTONEG_ENABLE) { - set_bit(__NSS_GMAC_AUTONEG, &gmacdev->flags); - } else { - clear_bit(__NSS_GMAC_AUTONEG, &gmacdev->flags); - } - -- return phy_ethtool_sset(phydev, ecmd); -+ return phy_ethtool_ksettings_set(phydev, elk); - } - - /** -@@ -580,8 +586,8 @@ struct ethtool_ops nss_gmac_ethtool_ops - .set_pauseparam = &nss_gmac_set_pauseparam, - .nway_reset = &nss_gmac_nway_reset, - .get_wol = &nss_gmac_get_wol, -- .get_settings = &nss_gmac_get_settings, -- .set_settings = &nss_gmac_set_settings, -+ .get_link_ksettings = &nss_gmac_get_settings, -+ .set_link_ksettings = &nss_gmac_set_settings, - .get_strings = &nss_gmac_get_strings, - .get_sset_count = &nss_gmac_get_strset_count, - .get_ethtool_stats = &nss_gmac_get_ethtool_stats, diff --git a/qaa/nss/qca-nss-gmac/patches/101-nss-gmac-test-ptr.patch b/qaa/nss/qca-nss-gmac/patches/101-nss-gmac-test-ptr.patch deleted file mode 100644 index a5bff16bd..000000000 --- a/qaa/nss/qca-nss-gmac/patches/101-nss-gmac-test-ptr.patch +++ /dev/null @@ -1,25 +0,0 @@ ---- a/ipq806x/nss_gmac_ctrl.c -+++ b/ipq806x/nss_gmac_ctrl.c -@@ -957,7 +957,8 @@ static int32_t nss_gmac_of_get_pdata(struct device_node *np, - struct net_device *netdev, - struct msm_nss_gmac_platform_data *gmaccfg) - { -- uint8_t *maddr = NULL; -+ int ret; -+ u8 maddr[ETH_ALEN]; - struct nss_gmac_dev *gmacdev = (struct nss_gmac_dev *)netdev_priv(netdev); - struct resource memres_devtree = {0}; - -@@ -991,9 +992,9 @@ static int32_t nss_gmac_of_get_pdata(struct device_node *np, - pr_err("%s: Can't map interrupt\n", np->name); - return -EFAULT; - } -- maddr = (uint8_t *)of_get_mac_address(np); -- if (maddr) -- memcpy(gmaccfg->mac_addr, maddr, ETH_ALEN); -+ ret = of_get_mac_address(np, maddr); -+ if (!ret && is_valid_ether_addr(maddr)) -+ ether_addr_copy(gmaccfg->mac_addr, maddr); - - if (of_address_to_resource(np, 0, &memres_devtree) != 0) - return -EFAULT; diff --git a/qaa/nss/qca-nss-gmac/patches/200-work-around-interface-close-warning.patch b/qaa/nss/qca-nss-gmac/patches/200-work-around-interface-close-warning.patch deleted file mode 100644 index 7cb6d6fac..000000000 --- a/qaa/nss/qca-nss-gmac/patches/200-work-around-interface-close-warning.patch +++ /dev/null @@ -1,15 +0,0 @@ ---- a/ipq806x/nss_gmac_tx_rx_offload.c -+++ b/ipq806x/nss_gmac_tx_rx_offload.c -@@ -1027,8 +1027,10 @@ int nss_gmac_close(struct net_device *ne - nss_gmac_disable_interrupt_all(gmacdev); - gmacdev->data_plane_ops->link_state(gmacdev->data_plane_ctx, 0); - -- if (!IS_ERR(gmacdev->phydev)) -- phy_stop(gmacdev->phydev); -+ if (!IS_ERR(gmacdev->phydev)) { -+ if (test_bit(__NSS_GMAC_LINKPOLL, &gmacdev->flags)) -+ phy_stop(gmacdev->phydev); -+ } - - clear_bit(__NSS_GMAC_UP, &gmacdev->flags); - clear_bit(__NSS_GMAC_CLOSING, &gmacdev->flags); diff --git a/qaa/qca-mcs/Makefile b/qaa/qca-mcs/Makefile deleted file mode 100644 index af9372d89..000000000 --- a/qaa/qca-mcs/Makefile +++ /dev/null @@ -1,54 +0,0 @@ -include $(TOPDIR)/rules.mk - -PKG_NAME:=qca-mcs -PKG_RELEASE:=1 - -PKG_SOURCE_PROTO:=git -PKG_SOURCE_DATE:=2021-10-28 -PKG_SOURCE_URL:=https://source.codeaurora.org/quic/qsdk/oss/lklm/qca-mcs -PKG_SOURCE_VERSION:=31f5cd4b83da5a7c0fdca240b4e72677e4523b6e -PKG_MIRROR_HASH:=3e2e25025dc2e771aafe7d8b12f26ac831d123b34bdd7b7e84bd39c1e933491d - -include $(INCLUDE_DIR)/kernel.mk -include $(INCLUDE_DIR)/package.mk - -define KernelPackage/qca-mcs - SECTION:=kernel - CATEGORY:=Kernel modules - SUBMENU:=Network Support - TITLE:=QCA Multicast Snooping Support - DEPENDS:=@(TARGET_ipq806x||TARGET_ipq807x) - KCONFIG:= \ - CONFIG_NETFILTER=y \ - CONFIG_BRIDGE_NETFILTER=y - FILES:=$(PKG_BUILD_DIR)/qca-mcs.ko - AUTOLOAD:=$(call AutoLoad,52,qca-mcs) -endef - -define KernelPackage/qca-mcs/description - This package installs the IGMP/MLD Snooping Module -endef - -QCA_MC_SNOOPING_HEADERS= \ - $(PKG_BUILD_DIR)/mc_api.h \ - $(PKG_BUILD_DIR)/mc_ecm.h \ - -define Build/InstallDev - $(INSTALL_DIR) $(1)/usr/include/qca-mcs - $(foreach header_file,$(QCA_MC_SNOOPING_HEADERS), $(CP) $(header_file) $(1)/usr/include/qca-mcs;) - $(foreach header_file,$(QCA_MC_SNOOPING_HEADERS), $(CP) $(header_file) $(1)/usr/include/;) -endef - -QCA_MC_SNOOPING_MAKE_OPTS:= \ - $(KERNEL_MAKE_FLAGS) \ - CONFIG_SUPPORT_MLD=y \ - MDIR=$(PKG_BUILD_DIR) \ - KBUILDPATH=$(LINUX_DIR) \ - KERNELPATH=$(LINUX_SRC_DIR) \ - KERNELRELEASE=$(LINUX_RELEASE) - -define Build/Compile - $(MAKE) -C $(LINUX_DIR) M=$(PKG_BUILD_DIR) $(strip $(QCA_MC_SNOOPING_MAKE_OPTS)) -endef - -$(eval $(call KernelPackage,qca-mcs)) diff --git a/qaa/qca-rfs/Makefile b/qaa/qca-rfs/Makefile deleted file mode 100644 index 7831e4d36..000000000 --- a/qaa/qca-rfs/Makefile +++ /dev/null @@ -1,51 +0,0 @@ -include $(TOPDIR)/rules.mk - -PKG_NAME:=qca-rfs -PKG_RELEASE:=1 - -PKG_SOURCE_PROTO:=git -PKG_SOURCE_URL:=https://source.codeaurora.org/quic/qsdk/oss/lklm/qca-rfs -PKG_SOURCE_DATE:=2021-03-17 -PKG_SOURCE_VERSION:=75197c386f477c7b3a6f02489d9903a9409fd5cc -PKG_MIRROR_HASH:=90f1c3ec2e984cf8efa79c85d715ebd8a21e347ab57adbd9695de23e64eea1ec - -include $(INCLUDE_DIR)/kernel.mk -include $(INCLUDE_DIR)/package.mk - -define KernelPackage/qca-rfs - SECTION:=kernel - CATEGORY:=Kernel modules - SUBMENU:=Network Support - DEPENDS:=@TARGET_ipq40xx +kmod-ipt-conntrack - TITLE:=Kernel module for QCA Receiving Flow Steering - FILES:=$(PKG_BUILD_DIR)/qrfs.ko - KCONFIG:=\ - CONFIG_NF_CONNTRACK_EVENTS=y \ - CONFIG_NF_CONNTRACK_CHAIN_EVENTS=y - AUTOLOAD:=$(call AutoLoad,29,qrfs) -endef - -define KernelPackage/qca-rfs/Description -QCA-RFS is a kernel module for ESS Receive Flow Steering. -endef - -define Build/Compile - $(MAKE) $(PKG_JOBS) -C "$(LINUX_DIR)" \ - $(KERNEL_MAKE_FLAGS) \ - $(PKG_MAKE_FLAGS) \ - M="$(PKG_BUILD_DIR)" \ - EXTRA_CFLAGS="$(EXTRA_CFLAGS)" \ - modules -endef - -define Build/InstallDev - $(INSTALL_DIR) $(1)/usr/include/qca-rfs - $(CP) -rf $(PKG_BUILD_DIR)/rfs_dev.h $(1)/usr/include/qca-rfs -endef - -define KernelPackage/qca-rfs/install - $(INSTALL_DIR) $(1)/etc/init.d - $(INSTALL_BIN) ./files/qrfs.init $(1)/etc/init.d/qrfs -endef - -$(eval $(call KernelPackage,qca-rfs)) diff --git a/qaa/qca-rfs/files/qrfs.init b/qaa/qca-rfs/files/qrfs.init deleted file mode 100644 index f3f8a38c8..000000000 --- a/qaa/qca-rfs/files/qrfs.init +++ /dev/null @@ -1,27 +0,0 @@ -#!/bin/sh /etc/rc.common -# -# Copyright (c) 2015 The Linux Foundation. All rights reserved. -# -# Permission to use, copy, modify, and/or distribute this software for any -# purpose with or without fee is hereby granted, provided that the above -# copyright notice and this permission notice appear in all copies. -# -# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - - -START=70 - -start() { - echo "1" > /proc/qrfs/enable - ip neigh flush all -} - -stop() { - echo "0" > /proc/qrfs/enable -} diff --git a/qaa/qca-rfs/patches/100-add-kernel-5.4-support.patch b/qaa/qca-rfs/patches/100-add-kernel-5.4-support.patch deleted file mode 100644 index b7b2db559..000000000 --- a/qaa/qca-rfs/patches/100-add-kernel-5.4-support.patch +++ /dev/null @@ -1,57 +0,0 @@ ---- a/rfs_cm.c -+++ b/rfs_cm.c -@@ -462,14 +462,6 @@ static int rfs_cm_conntrack_event(unsign - } - - /* -- * If this is an untracked connection then we can't have any state either. -- */ -- if (unlikely(ct == &nf_conntrack_untracked)) { -- RFS_TRACE("ignoring untracked conn\n"); -- return NOTIFY_DONE; -- } -- -- /* - * Ignore anything other than IPv4 connections. - */ - if (unlikely(nf_ct_l3num(ct) != AF_INET)) { ---- a/rfs_rule.c -+++ b/rfs_rule.c -@@ -702,7 +702,7 @@ int rfs_rule_init(void) - - RFS_DEBUG("RFS Rule init\n"); - spin_lock_init(&rr->hash_lock); -- memset(&rr->hash, 0, RFS_RULE_HASH_SIZE); -+ memset(&rr->hash, 0, sizeof(rr->hash)); - - rr->proc_rule = proc_create("rule", S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH, - rfs_proc_entry, &rule_proc_fops); -@@ -717,7 +717,7 @@ void rfs_rule_exit(void) - struct rfs_rule *rr = &__rr; - - RFS_DEBUG("RFS Rule exit\n"); -- if (rr->proc_rule); -+ if (rr->proc_rule) - remove_proc_entry("rule", rfs_proc_entry); - rfs_rule_destroy_all(); - } ---- a/rfs_wxt.c -+++ b/rfs_wxt.c -@@ -422,7 +422,7 @@ static int rfs_wxt_rx(struct socket *soc - #else - iov_iter_init(&msg.msg_iter, READ, &iov, 1, len); - #endif -- size = sock_recvmsg(sock, &msg, len, msg.msg_flags); -+ size = sock_recvmsg(sock, &msg, msg.msg_flags); - set_fs(oldfs); - - return size; -@@ -510,7 +510,7 @@ int rfs_wxt_stop(void) - } - - RFS_DEBUG("kill rfs_wxt thread"); -- force_sig(SIGKILL, __rwn.thread); -+ send_sig(SIGKILL, __rwn.thread, 1); - if (__rwn.thread) - err = kthread_stop(__rwn.thread); - __rwn.thread = NULL; diff --git a/qaa/qca-rfs/patches/200-rework-nfct-notification.patch b/qaa/qca-rfs/patches/200-rework-nfct-notification.patch deleted file mode 100644 index 81e608c02..000000000 --- a/qaa/qca-rfs/patches/200-rework-nfct-notification.patch +++ /dev/null @@ -1,20 +0,0 @@ ---- a/rfs_cm.c -+++ b/rfs_cm.c -@@ -709,7 +709,7 @@ int rfs_cm_start(void) - - RFS_DEBUG("RFS cm start\n"); - #ifdef CONFIG_NF_CONNTRACK_EVENTS -- ret = nf_conntrack_register_notifier(&init_net, &rfs_cm_conntrack_notifier); -+ ret = nf_conntrack_register_chain_notifier(&init_net, &rfs_cm_conntrack_notifier); - if (ret < 0) { - RFS_ERROR("can't register nf notifier hook: %d\n", ret); - return -1; -@@ -740,7 +740,7 @@ int rfs_cm_stop(void) - #endif - - #ifdef CONFIG_NF_CONNTRACK_EVENTS -- nf_conntrack_unregister_notifier(&init_net, &rfs_cm_conntrack_notifier); -+ nf_conntrack_unregister_chain_notifier(&init_net, &rfs_cm_conntrack_notifier); - #endif - - rfs_cm_connection_destroy_all(); diff --git a/qaa/qca-ssdk-shell/Makefile b/qaa/qca-ssdk-shell/Makefile deleted file mode 100644 index 90e2c2e64..000000000 --- a/qaa/qca-ssdk-shell/Makefile +++ /dev/null @@ -1,48 +0,0 @@ -include $(TOPDIR)/rules.mk - -PKG_NAME:=qca-ssdk-shell -PKG_RELEASE:=1 - -PKG_SOURCE_PROTO:=git -PKG_SOURCE_URL:=https://source.codeaurora.org/quic/qsdk/oss/ssdk-shell -PKG_SOURCE_DATE:=2021-01-27 -PKG_SOURCE_VERSION:=5661366d471a78314bc7010f985ad8cc15be832a -PKG_MIRROR_HASH:=73111e09e896f0abbe3ee1c358aea7ec14fe5e668ce8753b8968e03c78f9599b - -include $(INCLUDE_DIR)/kernel.mk -include $(INCLUDE_DIR)/package.mk - -define Package/qca-ssdk-shell - SECTION:=utils - CATEGORY:=Utilities - TITLE:=Shell application for QCA SSDK - DEPENDS:=@(TARGET_ipq40xx||TARGET_ipq806x||TARGET_ipq807x) -endef - -define Package/qca-ssdk-shell/Description - This package contains a qca-ssdk shell application for QCA chipset -endef - -ifndef CONFIG_TOOLCHAIN_BIN_PATH -CONFIG_TOOLCHAIN_BIN_PATH=$(TOOLCHAIN_DIR)/bin -endif - -QCASSDK_CONFIG_OPTS+= \ - TOOL_PATH=$(CONFIG_TOOLCHAIN_BIN_PATH) \ - SYS_PATH=$(LINUX_DIR) \ - TOOLPREFIX=$(TARGET_CROSS) \ - KVER=$(LINUX_VERSION) \ - CFLAGS="$(TARGET_CFLAGS)" \ - LDFLAGS="$(TARGET_LDFLAGS)" \ - ARCH=$(LINUX_KARCH) - -define Build/Compile - $(MAKE) -C $(PKG_BUILD_DIR) $(strip $(QCASSDK_CONFIG_OPTS)) -endef - -define Package/qca-ssdk-shell/install - $(INSTALL_DIR) $(1)/usr/sbin - $(INSTALL_BIN) $(PKG_BUILD_DIR)/build/bin/ssdk_sh $(1)/usr/sbin/ -endef - -$(eval $(call BuildPackage,qca-ssdk-shell)) diff --git a/qaa/qca-ssdk/Makefile b/qaa/qca-ssdk/Makefile deleted file mode 100644 index 3a68a50a2..000000000 --- a/qaa/qca-ssdk/Makefile +++ /dev/null @@ -1,125 +0,0 @@ -include $(TOPDIR)/rules.mk - -PKG_NAME:=qca-ssdk -PKG_RELEASE:=1 - -PKG_SOURCE_PROTO:=git -PKG_SOURCE_URL:=https://source.codeaurora.org/quic/qsdk/oss/lklm/qca-ssdk -PKG_SOURCE_DATE:=2021-04-28 -PKG_SOURCE_VERSION:=c9bc3bc34eaaac78083573524097356e2dcc1b66 -PKG_MIRROR_HASH:=29db78529be32427b8b96fcbfec22a016a243676781ec96d9d65b810944fa405 - -LOCAL_VARIANT=$(patsubst qca-ssdk-%,%,$(patsubst qca-ssdk-%,%,$(BUILD_VARIANT))) - -include $(INCLUDE_DIR)/kernel.mk -include $(INCLUDE_DIR)/package.mk - -define KernelPackage/qca-ssdk/default-nohnat - SECTION:=kernel - CATEGORY:=Kernel modules - SUBMENU:=Network Devices - TITLE:=Kernel driver for QCA SSDK - FILES:=$(PKG_BUILD_DIR)/build/bin/qca-ssdk.ko - AUTOLOAD:=$(call AutoLoad,30,qca-ssdk) - PROVIDES:=qca-ssdk -endef - -define KernelPackage/qca-ssdk-nohnat -$(call KernelPackage/qca-ssdk/default-nohnat) - DEPENDS:=@(TARGET_ipq806x||TARGET_ipq807x) - VARIANT:=nohnat -endef - -define KernelPackage/qca-ssdk-nohnat/Description -This package contains a qca-ssdk driver for QCA chipset -endef - -define KernelPackage/qca-ssdk-hnat -$(call KernelPackage/qca-ssdk/default-nohnat) - DEPENDS:=@TARGET_ipq40xx +kmod-ipt-extra +kmod-ipt-filter \ - +kmod-ppp +TARGET_ipq40xx:kmod-qca-rfs - TITLE+= (hnat) - VARIANT:=hnat -endef - -define KernelPackage/qca-ssdk-hnat/Description -This package contains a qca-ssdk-hnat driver for QCA chipset -endef - -ifdef CONFIG_TOOLCHAIN_BIN_PATH -TOOLCHAIN_BIN_PATH=$(CONFIG_TOOLCHAIN_BIN_PATH) -else -TOOLCHAIN_BIN_PATH=$(TOOLCHAIN_DIR)/bin -endif - -QCASSDK_CONFIG_OPTS+= \ - $(KERNEL_MAKE_FLAGS) \ - KVER=$(LINUX_VERSION) \ - SYS_PATH=$(LINUX_DIR) \ - GCC_VERSION=$(GCC_VERSION) \ - TOOLPREFIX=$(TARGET_CROSS) \ - TOOL_PATH=$(TOOLCHAIN_BIN_PATH) \ - TARGET_SUFFIX=$(CONFIG_TARGET_SUFFIX) \ - EXTRA_CFLAGS=-fno-stack-protector -I$(STAGING_DIR)/usr/include - -ifeq ($(LOCAL_VARIANT),hnat) - QCASSDK_CONFIG_OPTS+= HNAT_FEATURE=enable -ifeq ($(BOARD),ipq40xx) - QCASSDK_CONFIG_OPTS+= RFS_FEATURE=enable -endif -endif - -ifeq ($(BOARD),ipq60xx) - QCASSDK_CONFIG_OPTS+= CHIP_TYPE=CPPE -else ifeq ($(BOARD),ipq807x) - QCASSDK_CONFIG_OPTS+= CHIP_TYPE=HPPE -else - QCASSDK_CONFIG_OPTS+= HK_CHIP=enable -endif - -ifneq (, $(findstring $(BOARD), ipq60xx ipq807x)) - QCASSDK_CONFIG_OPTS+= PTP_FEATURE=disable SWCONFIG_FEATURE=disable -endif - -define Build/Compile - $(MAKE) -C $(PKG_BUILD_DIR) $(strip $(QCASSDK_CONFIG_OPTS)) -endef - -define Build/InstallDev - $(INSTALL_DIR) $(1)/usr/include/qca-ssdk - $(INSTALL_DIR) $(1)/usr/include/qca-ssdk/api - $(INSTALL_DIR) $(1)/usr/include/qca-ssdk/ref - $(INSTALL_DIR) $(1)/usr/include/qca-ssdk/fal - $(INSTALL_DIR) $(1)/usr/include/qca-ssdk/sal - $(INSTALL_DIR) $(1)/usr/include/qca-ssdk/init - $(CP) -rf $(PKG_BUILD_DIR)/include/api/sw_ioctl.h $(1)/usr/include/qca-ssdk/api - if [ -f $(PKG_BUILD_DIR)/include/ref/ref_vsi.h ]; then \ - $(CP) -rf $(PKG_BUILD_DIR)/include/ref/ref_vsi.h $(1)/usr/include/qca-ssdk/ref/; \ - fi - if [ -f $(PKG_BUILD_DIR)/include/ref/ref_fdb.h ]; then \ - $(CP) -rf $(PKG_BUILD_DIR)/include/ref/ref_fdb.h $(1)/usr/include/qca-ssdk/ref/; \ - fi - if [ -f $(PKG_BUILD_DIR)/include/ref/ref_port_ctrl.h ]; then \ - $(CP) -rf $(PKG_BUILD_DIR)/include/ref/ref_port_ctrl.h $(1)/usr/include/qca-ssdk/ref/; \ - fi - if [ -f $(PKG_BUILD_DIR)/include/init/ssdk_init.h ]; then \ - $(CP) -rf $(PKG_BUILD_DIR)/include/init/ssdk_init.h $(1)/usr/include/qca-ssdk/init/; \ - fi - $(CP) -rf $(PKG_BUILD_DIR)/include/fal $(1)/usr/include/qca-ssdk - $(CP) -rf $(PKG_BUILD_DIR)/include/common/*.h $(1)/usr/include/qca-ssdk - $(CP) -rf $(PKG_BUILD_DIR)/include/sal/os/linux/*.h $(1)/usr/include/qca-ssdk - $(CP) -rf $(PKG_BUILD_DIR)/include/sal/os/*.h $(1)/usr/include/qca-ssdk -endef - -define KernelPackage/qca-ssdk-nohnat/install - $(INSTALL_DIR) $(1)/etc/init.d - $(INSTALL_BIN) ./files/qca-ssdk $(1)/etc/init.d/qca-ssdk -endef - -define KernelPackage/qca-ssdk-hnat/install - $(INSTALL_DIR) $(1)/etc/init.d - $(INSTALL_BIN) ./files/qca-ssdk $(1)/etc/init.d/qca-ssdk -endef - -$(eval $(call KernelPackage,qca-ssdk-nohnat)) -$(eval $(call KernelPackage,qca-ssdk-hnat)) diff --git a/qaa/qca-ssdk/files/qca-ssdk b/qaa/qca-ssdk/files/qca-ssdk deleted file mode 100644 index 389279c0c..000000000 --- a/qaa/qca-ssdk/files/qca-ssdk +++ /dev/null @@ -1,206 +0,0 @@ -#!/bin/sh /etc/rc.common -# Copyright (c) 2018, The Linux Foundation. All rights reserved. -# -# Permission to use, copy, modify, and/or distribute this software for any -# purpose with or without fee is hereby granted, provided that the above -# copyright notice and this permission notice appear in all copies. -# -# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -# - -START=16 - -#!/bin/sh -ruletype="ip4 ip6" -side="wan lan" -qwan="1 3 2 0 5 7 6 4" -qlan="0 1 2 3 4 5 6 7" - -function create_war_acl_rules(){ - for lw in $side - do - #echo $lw - if [ "$lw" == "wan" ];then - listid=254 - queue=$qwan - portmap=0x20 - else - listid=255 - queue=$qlan - portmap=0x1e - fi - #echo $queue - #echo "creating list $listid" - ssdk_sh acl list create $listid 255 - ruleid=0 - for rt in $ruletype - do - for qid in $queue - do - cmd="ssdk_sh acl rule add $listid $ruleid 1 n 0 0" - #echo $cmd - if [ "$rt" == "ip4" ];then - cmd="$cmd ip4 n n n n n n n n n n n n n n n n n n n n n n n n n n n n n" - #echo $cmd - else - cmd="$cmd ip6 n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n" - #echo $cmd - fi - if [ $ruleid -le 3 ];then - #non-zero dscp - cmd="$cmd y 0x0 0xff" - elif [ $ruleid -le 7 ];then - #zero dscp - cmd="$cmd n" - elif [ $ruleid -le 11 ];then - #non-zero dscp - cmd="$cmd y 0x0 0xff" - else - #zero dscp - cmd="$cmd n" - fi - p=$((ruleid/2)) - cmd="$cmd y mask $((ruleid%2)) 0x1 y mask $((p%2)) 0x1 n n n n n n n n n n n n n n n y n n n n n n n y $qid n n 0 0 n n n n n n n n n n n n n n n n n n n n 0" - #echo $cmd - $cmd - ruleid=`expr $ruleid + 1` - done - done - ssdk_sh acl list bind $listid 0 1 $portmap - done -} - -function create_war_cosmap(){ - ssdk_sh cosmap pri2q set 0 0 - ssdk_sh cosmap pri2q set 1 0 - ssdk_sh cosmap pri2q set 2 0 - ssdk_sh cosmap pri2q set 3 0 - ssdk_sh cosmap pri2q set 4 1 - ssdk_sh cosmap pri2q set 5 1 - ssdk_sh cosmap pri2q set 6 1 - ssdk_sh cosmap pri2q set 7 1 - ssdk_sh cosmap pri2ehq set 0 0 - ssdk_sh cosmap pri2ehq set 1 0 - ssdk_sh cosmap pri2ehq set 2 0 - ssdk_sh cosmap pri2ehq set 3 0 - ssdk_sh cosmap pri2ehq set 4 1 - ssdk_sh cosmap pri2ehq set 5 1 - ssdk_sh cosmap pri2ehq set 6 1 - ssdk_sh cosmap pri2ehq set 7 1 -} - -function create_acl_byp_egstp_rules(){ - ssdk_sh debug module_func set servcode 0xf 0x0 0x0 - ssdk_sh servcode config set 1 n 0 0xfffefc7f 0xffbdff 0 0 0 0 0 0 - ssdk_sh debug module_func set servcode 0x0 0x0 0x0 - ssdk_sh acl list create 56 48 - ssdk_sh acl rule add 56 0 1 n 0 0 mac n n n n n y 01-80-c2-00-00-00 ff-ff-ff-ff-ff-ff n n n n n n n n n n n n n n n n n n n n n n n y n n n n n n n n n n 0 0 n n n n n n n n n n n n n y n n n n n n n n n n n n y n n n n n n n n n n n n 0 - ssdk_sh acl rule add 56 1 1 n 0 0 mac n n n n n n n yes 0x8809 0xffff n n n n n n n n n n n n n n n n n n n n n y n n n n n n n n n n 0 0 n n n n n n n n n n n n n y n n n n n n n n n n n n y n n n n n n n n n n n n 0 - ssdk_sh acl rule add 56 2 1 n 0 0 mac n n n n n n n yes 0x888e 0xffff n n n n n n n n n n n n n n n n n n n n n y n n n n n n n n n n 0 0 n n n n n n n n n n n n n y n n n n n n n n n n n n y n n n n n n n n n n n n 0 - ssdk_sh acl list bind 56 0 2 1 -} - -function delete_war_acl_rules(){ - for lw in $side - do - #echo $lw - if [ "$lw" == "wan" ];then - listid=254 - queue=$qwan - portmap=0x20 - else - listid=255 - queue=$qlan - portmap=0x1e - fi - ssdk_sh acl list unbind $listid 0 1 $portmap - for rt in $ruletype - do - for qid in $queue - do - cmd="ssdk_sh acl rule del $listid 0 1" - echo $cmd - $cmd - done - done - #echo "deleting list $listid" - ssdk_sh acl list destroy $listid - done -} - -function delete_war_cosmap(){ - ssdk_sh cosmap pri2q set 0 0 - ssdk_sh cosmap pri2q set 1 0 - ssdk_sh cosmap pri2q set 2 1 - ssdk_sh cosmap pri2q set 3 1 - ssdk_sh cosmap pri2q set 4 2 - ssdk_sh cosmap pri2q set 5 2 - ssdk_sh cosmap pri2q set 6 3 - ssdk_sh cosmap pri2q set 7 3 - ssdk_sh cosmap pri2ehq set 0 1 - ssdk_sh cosmap pri2ehq set 1 0 - ssdk_sh cosmap pri2ehq set 2 2 - ssdk_sh cosmap pri2ehq set 3 2 - ssdk_sh cosmap pri2ehq set 4 3 - ssdk_sh cosmap pri2ehq set 5 3 - ssdk_sh cosmap pri2ehq set 6 4 - ssdk_sh cosmap pri2ehq set 7 5 -} - -function delete_acl_byp_egstp_rules(){ - ssdk_sh debug module_func set servcode 0xf 0x0 0x0 - ssdk_sh servcode config set 1 n 0 0xfffefcff 0xffbfff 0 0 0 0 0 0 - ssdk_sh debug module_func set servcode 0x0 0x0 0x0 - ssdk_sh acl list unbind 56 0 2 1 - ssdk_sh acl rule del 56 0 1 - ssdk_sh acl rule del 56 1 1 - ssdk_sh acl rule del 56 2 1 - ssdk_sh acl list destroy 56 -} - -function edma_war_config_add(){ - create_war_cosmap - ssdk_sh acl status set enable - create_war_acl_rules -} - -function edma_war_config_del(){ - delete_war_acl_rules - delete_war_cosmap -} - -start() { - chip_ver=`ssdk_sh debug reg get 0 4 | grep Data | tr -d 'SSDK Init OK![Data]:'` - #The following commands should be uncommented to enable EDMA WAR - if [ "$chip_ver" = "0x1401" ]; then - #edma_war_config_add - echo '' - fi - #The following commands should be uncommented to add acl egress stp bypass rules - if [ "$chip_ver" = "0x1500" ] || [ "$chip_ver" = "0x1501" ]; then - #create_acl_byp_egstp_rules - echo '' - fi - echo starting -} - -stop() { - chip_ver=`ssdk_sh debug reg get 0 4 | grep Data | tr -d 'SSDK Init OK![Data]:'` - #The following commands should be uncommented to disable EDMA WAR - if [ "$chip_ver" = "0x1401" ]; then - #edma_war_config_del - echo '' - fi - #The following commands should be uncommented to delete acl egress stp bypass rules - if [ "$chip_ver" = "0x1500" ] || [ "$chip_ver" = "0x1501" ]; then - #delete_acl_byp_egstp_rules - echo '' - fi - echo stoping -} diff --git a/qaa/qca-ssdk/patches/0001-SSDK-config-add-kernel-5.10.patch b/qaa/qca-ssdk/patches/0001-SSDK-config-add-kernel-5.10.patch deleted file mode 100644 index 1ee44fa96..000000000 --- a/qaa/qca-ssdk/patches/0001-SSDK-config-add-kernel-5.10.patch +++ /dev/null @@ -1,56 +0,0 @@ -From 472c0c8132784608312c80c4b02c03ea7c132235 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Wed, 12 May 2021 13:41:12 +0200 -Subject: [PATCH] SSDK: config: add kernel 5.10 - -This is purely to identify it and be able to set -flags correctly. - -Signed-off-by: Robert Marko ---- - config | 6 +++++- - make/linux_opt.mk | 4 ++-- - 2 files changed, 7 insertions(+), 3 deletions(-) - ---- a/config -+++ b/config -@@ -22,6 +22,10 @@ ifeq ($(KVER),$(filter 5.4%,$(KVER))) - OS_VER=5_4 - endif - -+ifeq ($(KVER),$(filter 5.10%,$(KVER))) -+OS_VER=5_10 -+endif -+ - ifeq ($(KVER), 3.4.0) - OS_VER=3_4 - endif -@@ -123,7 +127,7 @@ endif - endif - - ifeq ($(ARCH), arm64) --ifeq ($(KVER),$(filter 4.1% 4.4% 4.9% 5.4%,$(KVER))) -+ifeq ($(KVER),$(filter 4.1% 4.4% 4.9% 5.4% 5.10%,$(KVER))) - CPU_CFLAG= -DMODULE -Os -pipe -march=armv8-a -mcpu=cortex-a53+crypto -fno-caller-saves -fno-strict-aliasing -Werror -fno-common -Wno-format-security -Wno-pointer-sign -Wno-unused-but-set-variable -Wno-error=unused-result -mcmodel=large - endif - endif ---- a/make/linux_opt.mk -+++ b/make/linux_opt.mk -@@ -388,7 +388,7 @@ ifeq (KSLIB, $(MODULE_TYPE)) - KASAN_SHADOW_SCALE_SHIFT := 3 - endif - -- ifeq (5_4, $(OS_VER)) -+ ifeq ($(OS_VER),$(filter 5_4 5_10, $(OS_VER))) - ifeq ($(ARCH), arm64) - KASAN_OPTION += -DKASAN_SHADOW_SCALE_SHIFT=$(KASAN_SHADOW_SCALE_SHIFT) - endif -@@ -419,7 +419,7 @@ ifeq (KSLIB, $(MODULE_TYPE)) - - endif - -- ifeq ($(OS_VER),$(filter 4_4 5_4, $(OS_VER))) -+ ifeq ($(OS_VER),$(filter 4_4 5_4 5_10, $(OS_VER))) - MODULE_CFLAG += -DKVER34 - MODULE_CFLAG += -DKVER32 - MODULE_CFLAG += -DLNX26_22 diff --git a/qaa/qca-ssdk/patches/0002-SSDK-replace-ioremap_nocache-with-ioremap.patch b/qaa/qca-ssdk/patches/0002-SSDK-replace-ioremap_nocache-with-ioremap.patch deleted file mode 100644 index b293ad295..000000000 --- a/qaa/qca-ssdk/patches/0002-SSDK-replace-ioremap_nocache-with-ioremap.patch +++ /dev/null @@ -1,102 +0,0 @@ -From 784f2cfdfaf3bdf44917924e157049230a0ef5f8 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Wed, 12 May 2021 13:45:45 +0200 -Subject: [PATCH] SSDK: replace ioremap_nocache with ioremap - -ioremap_nocache was dropped upstream, simply use the -generic variety. - -Signed-off-by: Robert Marko ---- - src/init/ssdk_clk.c | 10 +++++----- - src/init/ssdk_init.c | 2 +- - src/init/ssdk_plat.c | 6 +++--- - 3 files changed, 9 insertions(+), 9 deletions(-) - ---- a/src/init/ssdk_clk.c -+++ b/src/init/ssdk_clk.c -@@ -623,7 +623,7 @@ ssdk_mp_tcsr_get(a_uint32_t tcsr_offset, - { - void __iomem *tcsr_base = NULL; - -- tcsr_base = ioremap_nocache(TCSR_ETH_ADDR, TCSR_ETH_SIZE); -+ tcsr_base = ioremap(TCSR_ETH_ADDR, TCSR_ETH_SIZE); - if (!tcsr_base) - { - SSDK_ERROR("Failed to map tcsr eth address!\n"); -@@ -640,7 +640,7 @@ ssdk_mp_tcsr_set(a_uint32_t tcsr_offset, - { - void __iomem *tcsr_base = NULL; - -- tcsr_base = ioremap_nocache(TCSR_ETH_ADDR, TCSR_ETH_SIZE); -+ tcsr_base = ioremap(TCSR_ETH_ADDR, TCSR_ETH_SIZE); - if (!tcsr_base) - { - SSDK_ERROR("Failed to map tcsr eth address!\n"); -@@ -688,7 +688,7 @@ ssdk_mp_cmnblk_stable_check(void) - a_uint32_t reg_val; - int i, loops = 20; - -- pll_lock = ioremap_nocache(CMN_PLL_LOCKED_ADDR, CMN_PLL_LOCKED_SIZE); -+ pll_lock = ioremap(CMN_PLL_LOCKED_ADDR, CMN_PLL_LOCKED_SIZE); - if (!pll_lock) { - SSDK_ERROR("Failed to map CMN PLL LOCK register!\n"); - return A_FALSE; -@@ -745,7 +745,7 @@ static void ssdk_cmnblk_pll_src_set(enum - void __iomem *cmn_pll_src_base = NULL; - a_uint32_t reg_val; - -- cmn_pll_src_base = ioremap_nocache(CMN_BLK_PLL_SRC_ADDR, CMN_BLK_SIZE); -+ cmn_pll_src_base = ioremap(CMN_BLK_PLL_SRC_ADDR, CMN_BLK_SIZE); - if (!cmn_pll_src_base) { - SSDK_ERROR("Failed to map cmn pll source address!\n"); - return; -@@ -766,7 +766,7 @@ static void ssdk_cmnblk_init(enum cmnblk - void __iomem *gcc_pll_base = NULL; - a_uint32_t reg_val; - -- gcc_pll_base = ioremap_nocache(CMN_BLK_ADDR, CMN_BLK_SIZE); -+ gcc_pll_base = ioremap(CMN_BLK_ADDR, CMN_BLK_SIZE); - if (!gcc_pll_base) { - SSDK_ERROR("Failed to map gcc pll address!\n"); - return; ---- a/src/init/ssdk_init.c -+++ b/src/init/ssdk_init.c -@@ -2770,7 +2770,7 @@ static int ssdk_dess_mac_mode_init(a_uin - (a_uint8_t *)®_value, 4); - mdelay(10); - /*softreset psgmii, fixme*/ -- gcc_addr = ioremap_nocache(0x1812000, 0x200); -+ gcc_addr = ioremap(0x1812000, 0x200); - if (!gcc_addr) { - SSDK_ERROR("gcc map fail!\n"); - return 0; ---- a/src/init/ssdk_plat.c -+++ b/src/init/ssdk_plat.c -@@ -1312,7 +1312,7 @@ ssdk_plat_init(ssdk_init_cfg *cfg, a_uin - reg_mode = ssdk_uniphy_reg_access_mode_get(dev_id); - if(reg_mode == HSL_REG_LOCAL_BUS) { - ssdk_uniphy_reg_map_info_get(dev_id, &map); -- qca_phy_priv_global[dev_id]->uniphy_hw_addr = ioremap_nocache(map.base_addr, -+ qca_phy_priv_global[dev_id]->uniphy_hw_addr = ioremap(map.base_addr, - map.size); - if (!qca_phy_priv_global[dev_id]->uniphy_hw_addr) { - SSDK_ERROR("%s ioremap fail.", __func__); -@@ -1327,7 +1327,7 @@ ssdk_plat_init(ssdk_init_cfg *cfg, a_uin - reg_mode = ssdk_switch_reg_access_mode_get(dev_id); - if(reg_mode == HSL_REG_LOCAL_BUS) { - ssdk_switch_reg_map_info_get(dev_id, &map); -- qca_phy_priv_global[dev_id]->hw_addr = ioremap_nocache(map.base_addr, -+ qca_phy_priv_global[dev_id]->hw_addr = ioremap(map.base_addr, - map.size); - if (!qca_phy_priv_global[dev_id]->hw_addr) { - SSDK_ERROR("%s ioremap fail.", __func__); -@@ -1358,7 +1358,7 @@ ssdk_plat_init(ssdk_init_cfg *cfg, a_uin - return -1; - } - -- qca_phy_priv_global[dev_id]->psgmii_hw_addr = ioremap_nocache(map.base_addr, -+ qca_phy_priv_global[dev_id]->psgmii_hw_addr = ioremap(map.base_addr, - map.size); - if (!qca_phy_priv_global[dev_id]->psgmii_hw_addr) { - SSDK_ERROR("%s ioremap fail.", __func__); diff --git a/qaa/qca-ssdk/patches/0004-platform-use-of_mdio_find_bus-to-get-MDIO-bus.patch b/qaa/qca-ssdk/patches/0004-platform-use-of_mdio_find_bus-to-get-MDIO-bus.patch deleted file mode 100644 index 3bcbcccf6..000000000 --- a/qaa/qca-ssdk/patches/0004-platform-use-of_mdio_find_bus-to-get-MDIO-bus.patch +++ /dev/null @@ -1,40 +0,0 @@ -From b6190ca46287d01a895c7cc14de30410c09ff1b8 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Wed, 12 May 2021 17:15:46 +0200 -Subject: [PATCH] SSDK: platform: use of_mdio_find_bus() to get MDIO bus - -Kernel has a generic of_mdio_find_bus() which can get the appropriate -MDIO bus based on the DT node. -So, drop the getting MDIO from platform data, which no longer works -in 5.4 and later and use of_mdio_find_bus(). - -Signed-off-by: Baruch Siach -Signed-off-by: Robert Marko ---- - src/init/ssdk_plat.c | 8 +------- - 1 file changed, 1 insertion(+), 7 deletions(-) - ---- a/src/init/ssdk_plat.c -+++ b/src/init/ssdk_plat.c -@@ -551,7 +551,6 @@ static int miibus_get(a_uint32_t dev_id) - struct device_node *mdio_node = NULL; - struct device_node *switch_node = NULL; - struct platform_device *mdio_plat = NULL; -- struct ipq40xx_mdio_data *mdio_data = NULL; - struct qca_phy_priv *priv; - hsl_reg_mode reg_mode = HSL_REG_LOCAL_BUS; - priv = qca_phy_priv_global[dev_id]; -@@ -584,12 +583,7 @@ static int miibus_get(a_uint32_t dev_id) - - if(reg_mode == HSL_REG_LOCAL_BUS) - { -- mdio_data = dev_get_drvdata(&mdio_plat->dev); -- if (!mdio_data) { -- SSDK_ERROR("cannot get mdio_data reference from device data\n"); -- return 1; -- } -- priv->miibus = mdio_data->mii_bus; -+ priv->miibus = of_mdio_find_bus(mdio_node); - } - else - priv->miibus = dev_get_drvdata(&mdio_plat->dev); diff --git a/qaa/qca-ssdk/patches/0005-add-kernel-5.4-support.patch b/qaa/qca-ssdk/patches/0005-add-kernel-5.4-support.patch deleted file mode 100644 index 6b08b05ae..000000000 --- a/qaa/qca-ssdk/patches/0005-add-kernel-5.4-support.patch +++ /dev/null @@ -1,108 +0,0 @@ ---- a/app/nathelper/linux/lib/nat_helper_dt.c -+++ b/app/nathelper/linux/lib/nat_helper_dt.c -@@ -721,7 +721,7 @@ napt_ct_counter_sync(a_uint32_t hw_index) - } - - if (!test_bit(IPS_FIXED_TIMEOUT_BIT, &ct->status)) { -- ct->timeout.expires += delta_jiffies; -+ ct->timeout += delta_jiffies; - } - - if((cct != NULL) && (napt_hw_get_by_index(&napt, hw_index) == 0)) -@@ -770,7 +770,7 @@ napt_ct_timer_update(a_uint32_t hw_index) - } - - if (!test_bit(IPS_FIXED_TIMEOUT_BIT, &ct->status)) { -- ct->timeout.expires += delta_jiffies; -+ ct->timeout += delta_jiffies; - } - - return 0; ---- a/app/nathelper/linux/napt_helper.c -+++ b/app/nathelper/linux/napt_helper.c -@@ -64,11 +64,6 @@ napt_ct_aging_disable(uint32_t ct_addr) - } - - ct = (struct nf_conn *)ct_addr; -- -- if (timer_pending(&ct->timeout)) -- { -- del_timer(&ct->timeout); -- } - } - - int -@@ -85,7 +80,7 @@ napt_ct_aging_is_enable(uint32_t ct_addr) - - ct = (struct nf_conn *)ct_addr; - -- return timer_pending(&(((struct nf_conn *)ct)->timeout)); -+ return (nf_ct_is_expired(ct)); - } - - void -@@ -111,18 +106,17 @@ napt_ct_aging_enable(uint32_t ct_addr) - l3num = ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple.src.l3num; - protonum = ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple.dst.protonum; - -- ct->timeout.expires = jiffies+10*HZ; -+ ct->timeout = jiffies+10*HZ; - - if ((l3num == AF_INET) && (protonum == IPPROTO_TCP)) - { - if (ct->proto.tcp.state == TCP_CONNTRACK_ESTABLISHED) - { -- ct->timeout.expires = jiffies+(5*24*60*60*HZ); -+ ct->timeout = jiffies+(5*24*60*60*HZ); - } - } - - HNAT_PRINTK(" ct:[%x] add timeout again\n", ct_addr); -- add_timer(&ct->timeout); - } - - void -@@ -339,7 +333,6 @@ napt_ct_list_unlock(void) - uint32_t - napt_ct_list_iterate(uint32_t *hash, uint32_t *iterate) - { -- struct net *net = &init_net; - struct nf_conntrack_tuple_hash *h = NULL; - struct nf_conn *ct = NULL; - struct hlist_nulls_node *pos = (struct hlist_nulls_node *) (*iterate); -@@ -349,7 +342,7 @@ napt_ct_list_iterate(uint32_t *hash, uint32_t *iterate) - if(pos == 0) - { - /*get head for list*/ -- pos = rcu_dereference((&net->ct.hash[*hash])->first); -+ pos = rcu_dereference(hlist_nulls_first_rcu(&nf_conntrack_hash[*hash])); - } - - hlist_nulls_for_each_entry_from(h, pos, hnnode) ---- a/app/nathelper/linux/nat_ipt_helper.c -+++ b/app/nathelper/linux/nat_ipt_helper.c -@@ -534,10 +534,10 @@ nat_ipt_data_init(void) - memset(&old_replace, 0, sizeof (old_replace)); - - /*record ipt rule(SNAT) sequence for hw nat*/ -- memset(hw_nat_ipt_seq, 0, NAT_HW_NUM); -+ memset(hw_nat_ipt_seq, 0, sizeof(hw_nat_ipt_seq)); - - /*record ipt rule(SNAT) pubip index for hw nat*/ -- memset(hw_nat_pip_idx, 0, NAT_HW_NUM); -+ memset(hw_nat_pip_idx, 0, sizeof(hw_nat_pip_idx)); - } - - static void ---- a/make/linux_opt.mk -+++ b/make/linux_opt.mk -@@ -449,9 +449,6 @@ ifeq (KSLIB, $(MODULE_TYPE)) - else ifeq ($(ARCH), arm) - MODULE_INC += -I$(SYS_PATH) \ - -I$(TOOL_PATH)/../lib/gcc/$(TARGET_NAME)/$(GCC_VERSION)/include/ \ -- -I$(TOOL_PATH)/../lib/gcc/$(TARGET_NAME)/7.5.0/include/ \ -- -I$(TOOL_PATH)/../../lib/armv7a-vfp-neon-rdk-linux-gnueabi/gcc/arm-rdk-linux-gnueabi/4.8.4/include/ \ -- -I$(TOOL_PATH)/../../lib/arm-rdk-linux-musleabi/gcc/arm-rdk-linux-musleabi/6.4.0/include/ \ - -I$(SYS_PATH)/include \ - -I$(SYS_PATH)/source \ - -I$(SYS_PATH)/source/include \ diff --git a/qaa/qca-ssdk/patches/0006-fix-mdio-probe-on-ipq806x.patch b/qaa/qca-ssdk/patches/0006-fix-mdio-probe-on-ipq806x.patch deleted file mode 100644 index 8e802fe2a..000000000 --- a/qaa/qca-ssdk/patches/0006-fix-mdio-probe-on-ipq806x.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/src/init/ssdk_plat.c -+++ b/src/init/ssdk_plat.c -@@ -568,7 +568,7 @@ static int miibus_get(a_uint32_t dev_id) - if(reg_mode == HSL_REG_LOCAL_BUS) - mdio_node = of_find_compatible_node(NULL, NULL, "qcom,ipq40xx-mdio"); - else -- mdio_node = of_find_compatible_node(NULL, NULL, "virtual,mdio-gpio"); -+ mdio_node = of_find_compatible_node(NULL, NULL, "qcom,ipq8064-mdio"); - - if (!mdio_node) { - SSDK_ERROR("No MDIO node found in DTS!\n"); diff --git a/qaa/qca-ssdk/patches/0007-SSDK-dts-fix-of_get_mac_address.patch b/qaa/qca-ssdk/patches/0007-SSDK-dts-fix-of_get_mac_address.patch deleted file mode 100644 index 29be93128..000000000 --- a/qaa/qca-ssdk/patches/0007-SSDK-dts-fix-of_get_mac_address.patch +++ /dev/null @@ -1,42 +0,0 @@ -From f3a7b93137c1a6a1b8010b86296242178eed5d9e Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Fri, 13 Aug 2021 20:03:21 +0200 -Subject: [PATCH] SSDK: dts: fix of_get_mac_address() - -Recently OpenWrt backported the updated of_get_mac_address() -function which returns and error code instead. - -So, patch the SSDK to use it and fix the compilation error. - -Signed-off-by: Robert Marko ---- - src/init/ssdk_dts.c | 7 ++++--- - 1 file changed, 4 insertions(+), 3 deletions(-) - ---- a/src/init/ssdk_dts.c -+++ b/src/init/ssdk_dts.c -@@ -779,8 +779,9 @@ static void ssdk_dt_parse_intf_mac(void) - { - struct device_node *dp_node = NULL; - a_uint32_t dp = 0; -- a_uint8_t *maddr = NULL; -+ u8 maddr[ETH_ALEN]; - char dp_name[8] = {0}; -+ int ret; - - for (dp = 1; dp <= SSDK_MAX_NR_ETH; dp++) { - snprintf(dp_name, sizeof(dp_name), "dp%d", dp); -@@ -788,11 +789,11 @@ static void ssdk_dt_parse_intf_mac(void) - if (!dp_node) { - continue; - } -- maddr = (a_uint8_t *)of_get_mac_address(dp_node); -+ ret = of_get_mac_address(dp_node, maddr); - #if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0)) - if (maddr && is_valid_ether_addr(maddr)) { - #else -- if (!IS_ERR(maddr) && is_valid_ether_addr(maddr)) { -+ if (!ret && is_valid_ether_addr(maddr)) { - #endif - ssdk_dt_global.num_intf_mac++; - ether_addr_copy(ssdk_dt_global.intf_mac[dp-1].uc, maddr); diff --git a/qaa/qca-ssdk/patches/0008-add-aquantia-phy-id-113CB0.patch b/qaa/qca-ssdk/patches/0008-add-aquantia-phy-id-113CB0.patch deleted file mode 100644 index 69b08a819..000000000 --- a/qaa/qca-ssdk/patches/0008-add-aquantia-phy-id-113CB0.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 440ab349813e5aa9dbeddab4d82ab64ff5347c5f Mon Sep 17 00:00:00 2001 -From: Dirk Buchwalder -Date: Sat, 30 Oct 2021 19:51:06 +0200 -Subject: [PATCH] add aquantia phy id 113CB0 / 0x31c31C12 - -This adds support for the AQR113C with the id -"113CB0 / 0x31c31C12" to the ssdk. - -This is used in the QNAP 301w - -Signed-off-by: Dirk Buchwalder - ---- - include/hsl/phy/hsl_phy.h | 1 + - src/hsl/phy/hsl_phy.c | 1 + - 2 files changed, 2 insertions(+) - ---- a/include/hsl/phy/hsl_phy.h -+++ b/include/hsl/phy/hsl_phy.h -@@ -579,6 +579,7 @@ typedef struct { - #define AQUANTIA_PHY_112 0x03a1b660 - #define AQUANTIA_PHY_113C_A0 0x31c31C10 - #define AQUANTIA_PHY_113C_A1 0x31c31C11 -+#define AQUANTIA_PHY_113CB0 0x31c31C12 - #define AQUANTIA_PHY_112C 0x03a1b792 - - #define PHY_805XV2 0x004DD082 ---- a/src/hsl/phy/hsl_phy.c -+++ b/src/hsl/phy/hsl_phy.c -@@ -235,6 +235,7 @@ phy_type_t hsl_phytype_get_by_phyid(a_ui - case AQUANTIA_PHY_112: - case AQUANTIA_PHY_113C_A0: - case AQUANTIA_PHY_113C_A1: -+ case AQUANTIA_PHY_113CB0: - case AQUANTIA_PHY_112C: - phytype = AQUANTIA_PHY_CHIP; - break; diff --git a/qca/aq-fw-download/Makefile b/qca/aq-fw-download/Makefile deleted file mode 100644 index 97270688b..000000000 --- a/qca/aq-fw-download/Makefile +++ /dev/null @@ -1,26 +0,0 @@ -include $(TOPDIR)/rules.mk - -PKG_NAME:=aq-fw-download -PKG_RELEASE:=$(AUTORELEASE) - -PKG_FLAGS:=nonshared - -include $(INCLUDE_DIR)/package.mk - -define Package/aq-fw-download - SECTION:=firmware - CATEGORY:=Firmware - DEPENDS:=@TARGET_ipq807x - TITLE:=Aquantia FW downloader utitlity -endef - -define Package/aq-fw-download/description - Aquantia FW downloader utitlity -endef - -define Package/aq-fw-download/install - $(INSTALL_DIR) $(1)/sbin - $(INSTALL_BIN) $(PKG_BUILD_DIR)/aq-fw-download $(1)/sbin/aq-fw-download -endef - -$(eval $(call BuildPackage,aq-fw-download)) diff --git a/qca/aq-fw-download/src/Makefile b/qca/aq-fw-download/src/Makefile deleted file mode 100644 index dc141be0e..000000000 --- a/qca/aq-fw-download/src/Makefile +++ /dev/null @@ -1,14 +0,0 @@ -ifndef CFLAGS -CFLAGS = -O2 -g -endif -INCLUDES=-Iinclude -Iinclude/registerMap \ - -Iinclude/registerMap/APPIA \ - -Iinclude/registerMap/HHD - -all: aq-fw-download - -%.o: %.c - $(CC) $(INCLUDES) $(CFLAGS) -c -o $@ $^ - -aq-fw-download: mdioBootLoadCLD.o src/AQ_PhyInterface.o src/AQ_API.o - $(CC) $(LDFLAGS) -o $@ $^ $(LIBS) diff --git a/qca/aq-fw-download/src/include/AQ_API.h b/qca/aq-fw-download/src/include/AQ_API.h deleted file mode 100644 index 9a0b4c20a..000000000 --- a/qca/aq-fw-download/src/include/AQ_API.h +++ /dev/null @@ -1,246 +0,0 @@ -/* -* Copyright (c) 2015, Aquantia -* -* Permission to use, copy, modify, and/or distribute this software for any -* purpose with or without fee is hereby granted, provided that the above -* copyright notice and this permission notice appear in all copies. -* -* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -*/ - -/*! \file - This file contains the AQ_API function and datatype declarations. */ - - -#ifndef AQ_API_TOKEN -#define AQ_API_TOKEN - -#include - -#include "AQ_User.h" -#include "AQ_ReturnCodes.h" - -/******************************************************************* - General -*******************************************************************/ - -#ifdef __cplusplus -extern "C" { -#endif - -/*! This typedef defines the bool datatype which takes the values -true and false.*/ -typedef enum {False = 0, True = 1} AQ_boolean; - - -/*@}*/ - - -/******************************************************************* - Device Identity -*******************************************************************/ - -/*! \defgroup deviceIdentity Device Identity -All AQ_API functions accept a parameter identifying the target PHY that -should be acted upon. */ -/*@{*/ - - -/*! This enumeration is used to describe the different types of - Aquantia PHY.*/ -typedef enum -{ - /*! 1/2/4-port package, 40nm architechture.*/ - AQ_DEVICE_APPIA, - /*! 1/2/4-port package, 28nm architechture.*/ - AQ_DEVICE_HHD -} AQ_API_Device; - -/*! This structure is used to specify a particular Aquantia PHY port - within the system.*/ -typedef struct -{ - /*! The type of Aquantia PHY*/ - AQ_API_Device device; - /*! Uniquely identifies the port within the system. AQ_Port must be - defined to whatever data type is suitable for the platform. - AQ_API functions will never do anything with PHY_ID other than - pass it down to the platform's PHY register read/write - functions.*/ - AQ_Port PHY_ID; -} AQ_API_Port; - -/*@}*/ - - -/*! This function boot-loads the instruction and data memory (IRAM and - DRAM) of a set of Aquantia PHYs from a .cld format image file (the - same image file used to burn the FLASH). During boot-load of each - Aquantia PHY, the processor is halted, and after programming is - complete the processor is released. Note that calling this - function leaves the daisy-chain disabled to prevent RAM over- - write. To exit MDIO boot-load mode, use the function - AQ_API_EnableDaisyChain. - Unlike most of the other functions in this API, this function can - operate on a group of PHYs simultaneously. This is referred to as - gang-loading. To facilitate this, this function takes as - parameters 3 parallel arrays: PHY_IDs, provisioningAddresses, and - resultCodes. The length of these arrays must be identical, and is - specified by the num_PHY_IDs parameter. - In order to check the integrity of the boot-load operation, a - CRC-16 value is calculated over the IRAM and DRAM. After the image - has been loaded, this value is directly compared against each - PHY's Mailbox CRC-16 in 1E.0201. - The value of register 1E.C441 must be the same for all the boot- - loaded PHYs. This will be checked before the boot-load is - performed, and if a non-uniform value is read from any of the - PHYs, the function will fail before any writes are performed. - A separate result code is returned for each of the boot-loaded - PHYs, in the OUT parameter, resultCodes. - Individual Port Return codes: - AQ_RET_BOOTLOAD_PROVADDR_OOR: The specified provisioning address - was outside of the permitted range. - AQ_RET_BOOTLOAD_NONUNIFORM_REGVALS: The values of the register(s) - that must be uniform across the ports being bootloaded were not - uniform. - AQ_RET_BOOTLOAD_CRC_MISMATCH: The image was completely loaded into - memory, but the after the port exited bootload the running - checksum that was read from the uP memory mailbox was not the - expected value. This indicates that the memory has potentially - been corrupted, and the PHY should be reset before trying the - bootload again. - Overall Return codes (the return value from the function call): - AQ_RET_OK: all ports were successfully bootloaded. - AQ_RET_ERROR: One or more ports were not successfully bootloaded. - */ -AQ_Retcode AQ_API_WriteBootLoadImage -( - /*! An array identifying the target PHY ports.*/ - AQ_API_Port** ports, - /*! The length of the arrays ports, provisioningAddresses, and - resultCodes. These are parallel arrays, and must all be of the - same length.*/ - unsigned int numPorts, - /*! The provisioning addresses of each of the PHYs specified in - ports. This can range from 0 through 47, and is also known as - the daisy-chain address or the hop-count. If the PHYs are - connected to a FLASH using the daisy-chain, this is the distance - from the PHY to the FLASH, and is used to identify customized - provisioning for each PHY from the provisioning data within the - image. Otherwise, it is an arbitrary number. The length of this - array must match the length of ports.*/ - unsigned int* provisioningAddresses, - /*! OUT: The result code indicating success or failure of boot- - loading each of the PHYs specified in ports.*/ - AQ_Retcode* resultCodes, - /*! A pointer to the size of the image (in bytes) that is being - loaded into the Aquantia PHY.*/ - uint32_t* imageSizePointer, - /*! The image being loaded into the Aquantia PHY. This is the same - regardless of whether the target is internal RAM or FLASH.*/ - uint8_t* image, - /*! The 5-bit address to be used during the gang-loading operation. - During the boot-loading process, each of the PHYs specified in - ports will be changed such that they are addressed on the MDIO - bus at gangloadAddress. This allows all the PHYs to be loaded - simultaneously. Before returning, each PHY will be moved back to - its original MDIO address. If ports contains only a single - element, callers will probably want to use the PHY's original - MDIO address for this parameter.*/ - uint8_t gangload_MDIO_address, - /*! The address of the PHYs while in gangload mode. This is - ultimately some combination of the system address and the - gangload MDIO address, specified by gangload_MDIO_address. For - most platforms, gangload_MDIO_address and gangload_PHY_ID should - have the same value.*/ - AQ_API_Port* gangloadPort -); - -/*! This function boot-loads the instruction and data memory (IRAM and - DRAM) of a set of Aquantia PHYs from a .cld format image file (the - same image file used to burn the FLASH), as well as a separately - provided provisioning table image file.The provisioning table - image allows additional provisioning to be provided, beyond what - is built in to the .cld image. If provTableSizePointer or - provTableImage are NULL, this function behaves like - AQ_API_WriteBootLoadImage. - Aside from the additional provisioing table, this function behaves - exactly the same as AQ_API_WriteBootLoadImage. For additional - documentation and information on return codes, refer to - AQ_API_WriteBootLoadImage. - Individual Port Return codes (same as AQ_API_WriteBootLoadImage, - plus): - AQ_RET_BOOTLOAD_PROVTABLE_TOO_LARGE: The supplied provisioning - table image does not fit within the alloted space.*/ -AQ_Retcode AQ_API_WriteBootLoadImageWithProvTable -( - /*! An array identifying the target PHY ports.*/ - AQ_API_Port** ports, - /*! The length of the arrays ports, provisioningAddresses, and - resultCodes. These are parallel arrays, and must all be of the - same length.*/ - unsigned int numPorts, - /*! The provisioning addresses of each of the PHYs specified in - ports. This can range from 0 through 47, and is also known as - the daisy-chain address or the hop-count. If the PHYs are - connected to a FLASH using the daisy-chain, this is the distance - from the PHY to the FLASH, and is used to identify customized - provisioning for each PHY from the provisioning data within the - image. Otherwise, it is an arbitrary number. The length of this - array must match the length of ports.*/ - unsigned int* provisioningAddresses, - /*! OUT: The result code indicating success or failure of boot- - loading each of the PHYs specified in ports.*/ - AQ_Retcode* resultCodes, - /*! A pointer to the size of the image (in bytes) that is being - loaded into the Aquantia PHY.*/ - uint32_t* imageSizePointer, - /*! The image being loaded into the Aquantia PHY. This is the same - regardless of whether the target is internal RAM or FLASH.*/ - uint8_t* image, - /*! The 5-bit address to be used during the gang-loading operation. - During the boot-loading process, each of the PHYs specified in - ports will be changed such that they are addressed on the MDIO - bus at gangloadAddress. This allows all the PHYs to be loaded - simultaneously. Before returning, each PHY will be moved back to - its original MDIO address. If ports contains only a single - element, callers will probably want to use the PHY's original - MDIO address for this parameter.*/ - uint8_t gangload_MDIO_address, - /*! The address of the PHYs while in gangload mode. This is - ultimately some combination of the system address and the - gangload MDIO address, specified by gangload_MDIO_address. For - most platforms, gangload_MDIO_address and gangload_PHY_ID should - have the same value.*/ - AQ_API_Port* gangloadPort, - /*! A pointer to the size of the provTableImage (in bytes) that is - being loaded into the Aquantia PHY.*/ - uint32_t* provTableSizePointer, - /*! The additional provisioning table image being loaded into the - Aquantia PHY.*/ - uint8_t* provTableImage -); - -/*! Calling this function disables boot-loading and enables the daisy- - chain. This would typically be called after using MDIO boot- - loading on a daisy-chain enabled PHY. Re-enabling the daisy-chain - after performing an MDIO bootload will cause the PHY to reboot - from FLASH.*/ -AQ_Retcode AQ_API_EnableDaisyChain -( - /*! The target PHY port.*/ - AQ_API_Port* port -); - - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/qca/aq-fw-download/src/include/AQ_PhyInterface.h b/qca/aq-fw-download/src/include/AQ_PhyInterface.h deleted file mode 100644 index 66eb817be..000000000 --- a/qca/aq-fw-download/src/include/AQ_PhyInterface.h +++ /dev/null @@ -1,171 +0,0 @@ -/* AQ_PhyInterface.h */ - -/*********************************************************************** -* Copyright (c) 2015, Aquantia -* -* Permission to use, copy, modify, and/or distribute this software for any -* purpose with or without fee is hereby granted, provided that the above -* copyright notice and this permission notice appear in all copies. -* -* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -* -* Description: -* -* Declares the base PHY register read and write functions that are -* called by the API functions. The platform integrator must provide -* the implementation of these routines. -* -***********************************************************************/ - - -/*! \file - * Declares the base PHY register read and write functions that are - * called by the API functions. The platform integrator must provide - * the implementation of these routines. */ - - -#ifndef AQ_PHY_INTERFACE_TOKEN -#define AQ_PHY_INTERFACE_TOKEN - - -#include "AQ_API.h" -#include "AQ_User.h" - - -#ifdef __cplusplus -extern "C" { -#endif - - -/******************************************************************* - MDIO Access Functions -*******************************************************************/ - -/*! \defgroup mdioAccessFunctions MDIO Access Functions -The MDIO access functions are required by the API to access the register space -of each Aquantia PHY deployed in a system. The body of these functions needs to -be written by the system designer, as the method of accessing the PHY will -be unique to the target system. They are designed to be generic read and -write access functions, as the MDIO addressing scheme relies on each -MMD to maintain a 16 bit address pointer that determines the register where -the next read or write is coming from. Consequently, various levels of -optimization of the MDIO interface are possible: from re-writing the MMD -address pointer on every transaction, to storing shadow copies of the MMD -address pointers and only updating the MMD address pointer as necessary. -Thus these functions leave the MDIO optimization to the system engineer. - */ -/*@{*/ - - -/*! Provides generic synchronous PHY register write functionality. It is the - * responsibility of the system designer to provide the specific MDIO address - * pointer updates, etc. in order to accomplish this write operation. - * It will be assumed that the write has been completed by the time this - * function returns.*/ -void AQ_API_MDIO_Write -( - /*! Uniquely identifies the port within the system. AQ_Port must be - * defined to a whatever data type is suitable for the platform.*/ - AQ_Port PHY_ID, - /*! The address of the MMD within the target PHY. */ - unsigned int MMD, - /*! The 16-bit address of the PHY register being written. */ - unsigned int address, - /*! The 16-bits of data to write to the specified PHY register. */ - unsigned int data -); - -/*! Provides generic synchronous PHY register read functionality. It is the - * responsibility of the system designer to provide the specific MDIO address - * pointer updates, etc. in order to accomplish this read operation.*/ -unsigned int AQ_API_MDIO_Read -( - /*! Uniquely identifies the port within the system. AQ_Port must be - * defined to a whatever data type is suitable for the platform.*/ - AQ_Port PHY_ID, - /*! The address of the MMD within the target PHY. */ - unsigned int MMD, - /*! The 16-bit address of the PHY register being read. */ - unsigned int address -); - -#ifdef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE - -/*! Provides generic asynchronous/buffered PHY register write functionality. - * It is the responsibility of the system designer to provide the specific - * MDIO address pointer updates, etc. in order to accomplish this write - * operation. The write need not necessarily have been completed by the time - * this function returns. All register reads and writes to a particular PHY_ID - * that are requested by calling AQ_API_MDIO_BlockWrite or AQ_API_MDIO_BlockRead - * MUST be performed in the order that the calls are made. */ -void AQ_API_MDIO_BlockWrite -( - /*! Uniquely identifies the port within the system. AQ_Port must be - * defined to a whatever data type is suitable for the platform.*/ - AQ_Port PHY_ID, - /*! The address of the MMD within the target PHY. */ - unsigned int MMD, - /*! The 16-bit address of the PHY register being written. */ - unsigned int address, - /*! The 16-bits of data to write to the specified PHY register. */ - unsigned int data -); - -/*! Provides generic asynchronous/buffered PHY register read functionality. - * It is the responsibility of the system designer to provide the specific - * MDIO address pointer updates, etc. in order to accomplish this read - * operation. All register reads and writes to a particular PHY_ID that - * are requested by calling AQ_API_MDIO_BlockWrite or AQ_API_MDIO_BlockRead - * MUST be performed in the order that the calls are made. The register value - * may subsequently be fetched by calling AQ_API_MDIO_BlockOperationExecute.*/ -void AQ_API_MDIO_BlockRead -( - /*! Uniquely identifies the port within the system. AQ_Port must be - * defined to a whatever data type is suitable for the platform.*/ - AQ_Port PHY_ID, - /*! The address of the MMD within the target PHY. */ - unsigned int MMD, - /*! The 16-bit address of the PHY register being read. */ - unsigned int address -); - -/* Retrieve the results of all PHY register reads to PHY_ID previously - * requested via calls to AQ_API_MDIO_BlockRead. The read and write - * operations previously performed by calls to AQ_API_MDIO_BlockRead and - * AQ_API_MDIO_BlockRead must have all been completed by the time this - * function returns, in the order that the calls were performed. The - * return value is an array representing the fetched results of all - * pending calls to AQ_API_MDIO_BlockRead, in the order that the calls - * were performed. Callers should track the number of pending block - * reads to determine the size of the returned array. */ -unsigned int * AQ_API_MDIO_BlockOperationExecute -( - /*! Uniquely identifies the port within the system. AQ_Port must be - * defined to a whatever data type is suitable for the platform.*/ - AQ_Port PHY_ID -); - -/* Returns the maximum number of asynchronous/buffered PHY register - * read/write operations. Callers will call AQ_API_MDIO_BlockOperationExecute - * before issuing additional calls to AQ_API_MDIO_BlockWrite or - * AQ_API_MDIO_BlockRead to avoid a buffer overflow. */ -unsigned int AQ_API_MDIO_MaxBlockOperations -( -); - -#endif - -/*@}*/ - - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/qca/aq-fw-download/src/include/AQ_PlatformRoutines.h b/qca/aq-fw-download/src/include/AQ_PlatformRoutines.h deleted file mode 100644 index 9a16d6408..000000000 --- a/qca/aq-fw-download/src/include/AQ_PlatformRoutines.h +++ /dev/null @@ -1,71 +0,0 @@ -/*AQ_PlatformRoutines.h*/ - -/************************************************************************************ -* Copyright (c) 2015, Aquantia -* -* Permission to use, copy, modify, and/or distribute this software for any -* purpose with or without fee is hereby granted, provided that the above -* copyright notice and this permission notice appear in all copies. -* -* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -* -* Description: -* -* Declares the platform interface functions that will be called by AQ_API -* functions. The platform integrator must provide the implementation of -* these functions. -* -************************************************************************************/ - -/*! \file - * Declares the platform interface functions that will be called by AQ_API - * functions. The platform integrator must provide the implementation of - * these functions. */ - - -#ifndef AQ_PHY_PLATFORMROUTINES_TOKEN -#define AQ_PHY_PLATFORMROUTINES_TOKEN - -#include - -#include "AQ_API.h" -#include "AQ_User.h" -#include "AQ_ReturnCodes.h" - -#ifdef __cplusplus -extern "C" { -#endif - - -/******************************************************************* - Time Delay -*******************************************************************/ - -/*! \defgroup delay Time Delay - @{ -*/ - -/*! Returns after at least milliseconds have elapsed. This must be implemented - * in a platform-approriate way. AQ_API functions will call this function to - * block for the specified period of time. If necessary, PHY register reads - * may be performed on port to busy-wait. */ -void AQ_API_Wait -( - uint32_t milliseconds, /*!< The delay in milliseconds */ - AQ_API_Port* port /*!< The PHY to use if delay reads are necessary*/ -); - -/*@}*/ - - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/qca/aq-fw-download/src/include/AQ_RegMacro.h b/qca/aq-fw-download/src/include/AQ_RegMacro.h deleted file mode 100644 index 8dcca522b..000000000 --- a/qca/aq-fw-download/src/include/AQ_RegMacro.h +++ /dev/null @@ -1,323 +0,0 @@ -/* Copyright (c) 2015, Aquantia -* -* Permission to use, copy, modify, and/or distribute this software for any -* purpose with or without fee is hereby granted, provided that the above -* copyright notice and this permission notice appear in all copies. -* -* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -*/ -/*! \file - This file contains macros for accessing the AQ PHYs' registers - using the device-specific register map data structures and definitions. -*/ - -#ifndef AQ_REG_MACRO_TOKEN -#define AQ_REG_MACRO_TOKEN - -#include "AQ_PhyInterface.h" - - -#define AQ_API_ReadRegister(id,reg,wd) AQ_API_ReadRegister_DeviceRestricted(APPIA_HHD,id,reg,wd) - -#define AQ_API_ReadRegister_DeviceRestricted(devices,id,reg,wd) AQ_API_ReadRegister_Devs_ ## devices(id,reg,wd) - -#define AQ_API_ReadRegister_Devs_APPIA(id,reg,wd) \ - ((port->device == AQ_DEVICE_APPIA) ? AQ_API_MDIO_Read (id,reg ## _APPIA_mmdAddress,(reg ## _APPIA_baseRegisterAddress + wd)) : \ - (0)) - -#define AQ_API_ReadRegister_Devs_HHD(id,reg,wd) \ - ((port->device == AQ_DEVICE_HHD) ? AQ_API_MDIO_Read (id,reg ## _HHD_mmdAddress,(reg ## _HHD_baseRegisterAddress + wd)) : \ - (0)) - -#define AQ_API_ReadRegister_Devs_APPIA_HHD(id,reg,wd) \ - ((port->device == AQ_DEVICE_HHD) ? AQ_API_MDIO_Read (id,reg ## _HHD_mmdAddress,(reg ## _HHD_baseRegisterAddress + wd)) : \ - ((port->device == AQ_DEVICE_APPIA) ? AQ_API_MDIO_Read (id,reg ## _APPIA_mmdAddress,(reg ## _APPIA_baseRegisterAddress + wd)) : \ - (0))) - -#define AQ_API_ReadRegister_Devs_HHD_APPIA(id,reg,wd) AQ_API_ReadRegister_Devs_APPIA_HHD(id,reg,wd) - - -#define AQ_API_WriteRegister(id,reg,wd,value) AQ_API_WriteRegister_DeviceRestricted(APPIA_HHD,id,reg,wd,value) - -#define AQ_API_WriteRegister_DeviceRestricted(devices,id,reg,wd,value) AQ_API_WriteRegister_Devs_ ## devices(id,reg,wd,value) - -#define AQ_API_WriteRegister_Devs_APPIA(id,reg,wd,value) \ - ((port->device == AQ_DEVICE_APPIA) ? AQ_API_MDIO_Write (id,reg ## _APPIA_mmdAddress,(reg ## _APPIA_baseRegisterAddress + wd),value) : \ - ((void)0)) - -#define AQ_API_WriteRegister_Devs_HHD(id,reg,wd,value) \ - ((port->device == AQ_DEVICE_HHD) ? AQ_API_MDIO_Write (id,reg ## _HHD_mmdAddress,(reg ## _HHD_baseRegisterAddress + wd),value) : \ - ((void)0)) - -#define AQ_API_WriteRegister_Devs_APPIA_HHD(id,reg,wd,value) \ - ((port->device == AQ_DEVICE_HHD) ? AQ_API_MDIO_Write (id,reg ## _HHD_mmdAddress,(reg ## _HHD_baseRegisterAddress + wd),value) : \ - ((port->device == AQ_DEVICE_APPIA) ? AQ_API_MDIO_Write (id,reg ## _APPIA_mmdAddress,(reg ## _APPIA_baseRegisterAddress + wd),value) : \ - ((void)0))) - -#define AQ_API_WriteRegister_Devs_HHD_APPIA(id,reg,wd,value) AQ_API_WriteRegister_Devs_APPIA_HHD(id,reg,wd,value) - - -#ifdef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE - -#define AQ_API_BlockReadRegister(id,reg,wd) AQ_API_BlockReadRegister_DeviceRestricted(APPIA_HHD,id,reg,wd) - -#define AQ_API_BlockReadRegister_DeviceRestricted(devices,id,reg,wd) AQ_API_BlockReadRegister_Devs_ ## devices(id,reg,wd) - -#define AQ_API_BlockReadRegister_Devs_APPIA(id,reg,wd) \ - ((port->device == AQ_DEVICE_APPIA) ? AQ_API_MDIO_BlockRead (id,reg ## _APPIA_mmdAddress,(reg ## _APPIA_baseRegisterAddress + wd)) : \ - ((void)0)) - -#define AQ_API_BlockReadRegister_Devs_HHD(id,reg,wd) \ - ((port->device == AQ_DEVICE_HHD) ? AQ_API_MDIO_BlockRead (id,reg ## _HHD_mmdAddress,(reg ## _HHD_baseRegisterAddress + wd)) : \ - ((void)0)) - -#define AQ_API_BlockReadRegister_Devs_APPIA_HHD(id,reg,wd) \ - ((port->device == AQ_DEVICE_HHD) ? AQ_API_MDIO_BlockRead (id,reg ## _HHD_mmdAddress,(reg ## _HHD_baseRegisterAddress + wd)) : \ - ((port->device == AQ_DEVICE_APPIA) ? AQ_API_MDIO_BlockRead (id,reg ## _APPIA_mmdAddress,(reg ## _APPIA_baseRegisterAddress + wd)) : \ - ((void)0))) - -#define AQ_API_BlockReadRegister_Devs_HHD_APPIA(id,reg,wd) AQ_API_BlockReadRegister_Devs_APPIA_HHD(id,reg,wd) - - -#define AQ_API_BlockWriteRegister(id,reg,wd,value) AQ_API_BlockWriteRegister_DeviceRestricted(APPIA_HHD,id,reg,wd,value) - -#define AQ_API_BlockWriteRegister_DeviceRestricted(devices,id,reg,wd,value) AQ_API_BlockWriteRegister_Devs_ ## devices(id,reg,wd,value) - -#define AQ_API_BlockWriteRegister_Devs_APPIA(id,reg,wd,value) \ - ((port->device == AQ_DEVICE_APPIA) ? AQ_API_MDIO_BlockWrite (id,reg ## _APPIA_mmdAddress,(reg ## _APPIA_baseRegisterAddress + wd),value) : \ - ((void)0)) - -#define AQ_API_BlockWriteRegister_Devs_HHD(id,reg,wd,value) \ - ((port->device == AQ_DEVICE_HHD) ? AQ_API_MDIO_BlockWrite (id,reg ## _HHD_mmdAddress,(reg ## _HHD_baseRegisterAddress + wd),value) : \ - ((void)0)) - -#define AQ_API_BlockWriteRegister_Devs_APPIA_HHD(id,reg,wd,value) \ - ((port->device == AQ_DEVICE_HHD) ? AQ_API_MDIO_BlockWrite (id,reg ## _HHD_mmdAddress,(reg ## _HHD_baseRegisterAddress + wd),value) : \ - ((port->device == AQ_DEVICE_APPIA) ? AQ_API_MDIO_BlockWrite (id,reg ## _APPIA_mmdAddress,(reg ## _APPIA_baseRegisterAddress + wd),value) : \ - ((void)0))) - -#define AQ_API_BlockWriteRegister_Devs_HHD_APPIA(id,reg,wd,value) AQ_API_BlockWriteRegister_Devs_APPIA_HHD(id,reg,wd,value) - - -#endif - -#define AQ_API_Variable(reg) AQ_API_Variable_DeviceRestricted(APPIA_HHD,reg) - -#define AQ_API_Variable_DeviceRestricted(devices,reg) AQ_API_Variable_Devs_ ## devices(reg) - -#define AQ_API_Variable_Devs_APPIA(reg) uint8_t _local ## reg ## _space[ sizeof(reg ## _BiggestVersion) ];\ - reg ## _APPIA* _local ## reg ## _APPIA = (reg ## _APPIA*) _local ## reg ## _space; \ - -#define AQ_API_Variable_Devs_HHD(reg) uint8_t _local ## reg ## _space[ sizeof(reg ## _BiggestVersion) ];\ - reg ## _HHD* _local ## reg ## _HHD = (reg ## _HHD*) _local ## reg ## _space; \ - -#define AQ_API_Variable_Devs_APPIA_HHD(reg) uint8_t _local ## reg ## _space[ sizeof(reg ## _BiggestVersion) ];\ - reg ## _APPIA* _local ## reg ## _APPIA = (reg ## _APPIA*) _local ## reg ## _space; \ - reg ## _HHD* _local ## reg ## _HHD = (reg ## _HHD*) _local ## reg ## _space; \ - -#define AQ_API_Variable_Devs_HHD_APPIA(reg) AQ_API_Variable_Devs_APPIA_HHD(reg) - - -#define AQ_API_DeclareLocalStruct(reg,localvar) AQ_API_DeclareLocalStruct_DeviceRestricted(APPIA_HHD,reg,localvar) - -#define AQ_API_DeclareLocalStruct_DeviceRestricted(devices,reg,localvar) AQ_API_DeclareLocalStruct_Devs_ ## devices(reg,localvar) - -#define AQ_API_DeclareLocalStruct_Devs_APPIA(reg,localvar) uint8_t localvar ## _space[ sizeof(reg ## _BiggestVersion) ];\ - reg ## _APPIA* localvar ## _APPIA = (reg ## _APPIA*) localvar ## _space; \ - -#define AQ_API_DeclareLocalStruct_Devs_HHD(reg,localvar) uint8_t localvar ## _space[ sizeof(reg ## _BiggestVersion) ];\ - reg ## _HHD* localvar ## _HHD = (reg ## _HHD*) localvar ## _space; \ - -#define AQ_API_DeclareLocalStruct_Devs_APPIA_HHD(reg,localvar) uint8_t localvar ## _space[ sizeof(reg ## _BiggestVersion) ];\ - reg ## _APPIA* localvar ## _APPIA = (reg ## _APPIA*) localvar ## _space; \ - reg ## _HHD* localvar ## _HHD = (reg ## _HHD*) localvar ## _space; \ - -#define AQ_API_DeclareLocalStruct_Devs_HHD_APPIA(reg,localvar) AQ_API_DeclareLocalStruct_Devs_APPIA_HHD(reg,localvar) - - -#define AQ_API_Set(id,reg,field,value) AQ_API_Set_DeviceRestricted(APPIA_HHD,id,reg,field,value) - -#define AQ_API_Set_DeviceRestricted(devices,id,reg,field,value) AQ_API_Set_Devs_ ## devices(id,reg,field,value) - -#define AQ_API_Set_Devs_APPIA(id,reg,field,value) { \ - switch (port->device) { \ - case AQ_DEVICE_APPIA: \ - _local ## reg ## _APPIA->word_ ## reg ## _APPIA_ ## field = AQ_API_ReadRegister_Devs_APPIA(id,reg,reg ## _APPIA_ ## field); \ - if (_local ## reg ## _APPIA->bits_ ## reg ## _APPIA_ ## field.field != value) \ - { \ - _local ## reg ## _APPIA->bits_ ## reg ## _APPIA_ ## field.field = value; \ - AQ_API_WriteRegister_Devs_APPIA(id,reg,reg ## _APPIA_ ## field,_local ## reg ## _APPIA->word_ ## reg ## _APPIA_ ## field); \ - } \ - break; \ - default: break; \ - } \ -} - -#define AQ_API_Set_Devs_HHD(id,reg,field,value) { \ - switch (port->device) { \ - case AQ_DEVICE_HHD: \ - _local ## reg ## _HHD->word_ ## reg ## _HHD_ ## field = AQ_API_ReadRegister_Devs_HHD(id,reg,reg ## _HHD_ ## field); \ - if (_local ## reg ## _HHD->bits_ ## reg ## _HHD_ ## field.field != value) \ - { \ - _local ## reg ## _HHD->bits_ ## reg ## _HHD_ ## field.field = value; \ - AQ_API_WriteRegister_Devs_HHD(id,reg,reg ## _HHD_ ## field,_local ## reg ## _HHD->word_ ## reg ## _HHD_ ## field); \ - } \ - break; \ - default: break; \ - } \ -} - -#define AQ_API_Set_Devs_APPIA_HHD(id,reg,field,value) { \ - switch (port->device) { \ - case AQ_DEVICE_APPIA: \ - _local ## reg ## _APPIA->word_ ## reg ## _APPIA_ ## field = AQ_API_ReadRegister_Devs_APPIA_HHD(id,reg,reg ## _APPIA_ ## field); \ - if (_local ## reg ## _APPIA->bits_ ## reg ## _APPIA_ ## field.field != value) \ - { \ - _local ## reg ## _APPIA->bits_ ## reg ## _APPIA_ ## field.field = value; \ - AQ_API_WriteRegister_Devs_APPIA_HHD(id,reg,reg ## _APPIA_ ## field,_local ## reg ## _APPIA->word_ ## reg ## _APPIA_ ## field); \ - } \ - break; \ - case AQ_DEVICE_HHD: \ - _local ## reg ## _HHD->word_ ## reg ## _HHD_ ## field = AQ_API_ReadRegister_Devs_APPIA_HHD(id,reg,reg ## _HHD_ ## field); \ - if (_local ## reg ## _HHD->bits_ ## reg ## _HHD_ ## field.field != value) \ - { \ - _local ## reg ## _HHD->bits_ ## reg ## _HHD_ ## field.field = value; \ - AQ_API_WriteRegister_Devs_APPIA_HHD(id,reg,reg ## _HHD_ ## field,_local ## reg ## _HHD->word_ ## reg ## _HHD_ ## field); \ - } \ - break; \ - default: break; \ - } \ -} - -#define AQ_API_Set_Devs_HHD_APPIA(id,reg,field,value) AQ_API_Set_Devs_APPIA_HHD(id,reg,field,value) - - -#define AQ_API_Get(id,reg,field,value) AQ_API_Get_DeviceRestricted(APPIA_HHD,id,reg,field,value) - -#define AQ_API_Get_DeviceRestricted(devices,id,reg,field,value) AQ_API_Get_Devs_ ## devices(id,reg,field,value) - -#define AQ_API_Get_Devs_APPIA(id,reg,field,value) { \ - switch (port->device) { \ - case AQ_DEVICE_APPIA: \ - _local ## reg ## _APPIA->word_ ## reg ## _APPIA_ ## field = AQ_API_ReadRegister_Devs_APPIA(id,reg,reg ## _APPIA_ ## field); \ - value = _local ## reg ## _APPIA->bits_ ## reg ## _APPIA_ ## field.field; \ - break; \ - default: value = 0; break; \ - } \ -} - -#define AQ_API_Get_Devs_HHD(id,reg,field,value) { \ - switch (port->device) { \ - case AQ_DEVICE_HHD: \ - _local ## reg ## _HHD->word_ ## reg ## _HHD_ ## field = AQ_API_ReadRegister_Devs_HHD(id,reg,reg ## _HHD_ ## field); \ - value = _local ## reg ## _HHD->bits_ ## reg ## _HHD_ ## field.field; \ - break; \ - default: value = 0; break; \ - } \ -} - -#define AQ_API_Get_Devs_APPIA_HHD(id,reg,field,value) { \ - switch (port->device) { \ - case AQ_DEVICE_APPIA: \ - _local ## reg ## _APPIA->word_ ## reg ## _APPIA_ ## field = AQ_API_ReadRegister_Devs_APPIA_HHD(id,reg,reg ## _APPIA_ ## field); \ - value = _local ## reg ## _APPIA->bits_ ## reg ## _APPIA_ ## field.field; \ - break; \ - case AQ_DEVICE_HHD: \ - _local ## reg ## _HHD->word_ ## reg ## _HHD_ ## field = AQ_API_ReadRegister_Devs_APPIA_HHD(id,reg,reg ## _HHD_ ## field); \ - value = _local ## reg ## _HHD->bits_ ## reg ## _HHD_ ## field.field; \ - break; \ - default: value = 0; break; \ - } \ -} - -#define AQ_API_Get_Devs_HHD_APPIA(id,reg,field,value) AQ_API_Get_Devs_APPIA_HHD(id,reg,field,value) - - -#define AQ_API_BitfieldOfLocalStruct(reg,localvar,field) AQ_API_BitfieldOfLocalStruct_DeviceRestricted(APPIA_HHD,reg,localvar,field) - -#define AQ_API_BitfieldOfLocalStruct_DeviceRestricted(devices,reg,localvar,field) AQ_API_BitfieldOfLocalStruct_Devs_ ## devices(reg,localvar,field) - -#define AQ_API_BitfieldOfLocalStruct_Devs_APPIA(reg,localvar,field) \ - ((port->device == AQ_DEVICE_APPIA) ? ((localvar ## _APPIA)->bits_ ## reg ## _APPIA ## _ ## field.field) : \ - (0)) - -#define AQ_API_BitfieldOfLocalStruct_Devs_HHD(reg,localvar,field) \ - ((port->device == AQ_DEVICE_HHD) ? ((localvar ## _HHD)->bits_ ## reg ## _HHD ## _ ## field.field) : \ - (0)) - -#define AQ_API_BitfieldOfLocalStruct_Devs_APPIA_HHD(reg,localvar,field) \ - ((port->device == AQ_DEVICE_HHD) ? ((localvar ## _HHD)->bits_ ## reg ## _HHD ## _ ## field.field) : \ - ((port->device == AQ_DEVICE_APPIA) ? ((localvar ## _APPIA)->bits_ ## reg ## _APPIA ## _ ## field.field) : \ - (0))) - -#define AQ_API_BitfieldOfLocalStruct_Devs_HHD_APPIA(reg,localvar,field) AQ_API_BitfieldOfLocalStruct_Devs_APPIA_HHD(reg,localvar,field) - - -#define AQ_API_AssignBitfieldOfLocalStruct(reg,localvar,field,value) AQ_API_AssignBitfieldOfLocalStruct_DeviceRestricted(APPIA_HHD,reg,localvar,field,value) - -#define AQ_API_AssignBitfieldOfLocalStruct_DeviceRestricted(devices,reg,localvar,field,value) AQ_API_AssignBitfieldOfLocalStruct_Devs_ ## devices(reg,localvar,field,value) - -#define AQ_API_AssignBitfieldOfLocalStruct_Devs_APPIA(reg,localvar,field,value) \ - ((port->device == AQ_DEVICE_APPIA) ? ((localvar ## _APPIA)->bits_ ## reg ## _APPIA ## _ ## field.field = value) : \ - (0)) - -#define AQ_API_AssignBitfieldOfLocalStruct_Devs_HHD(reg,localvar,field,value) \ - ((port->device == AQ_DEVICE_HHD) ? ((localvar ## _HHD)->bits_ ## reg ## _HHD ## _ ## field.field = value) : \ - (0)) - -#define AQ_API_AssignBitfieldOfLocalStruct_Devs_APPIA_HHD(reg,localvar,field,value) \ - ((port->device == AQ_DEVICE_HHD) ? ((localvar ## _HHD)->bits_ ## reg ## _HHD ## _ ## field.field = value) : \ - ((port->device == AQ_DEVICE_APPIA) ? ((localvar ## _APPIA)->bits_ ## reg ## _APPIA ## _ ## field.field = value) : \ - (0))) - -#define AQ_API_AssignBitfieldOfLocalStruct_Devs_HHD_APPIA(reg,localvar,field,value) AQ_API_AssignBitfieldOfLocalStruct_Devs_APPIA_HHD(reg,localvar,field,value) - - -#define AQ_API_WordOfLocalStruct(localvar,wd) AQ_API_WordOfLocalStruct_DeviceRestricted(APPIA_HHD,localvar,wd) - -#define AQ_API_WordOfLocalStruct_DeviceRestricted(devices,localvar,wd) AQ_API_WordOfLocalStruct_Devs_ ## devices(localvar,wd) - -#define AQ_API_WordOfLocalStruct_Devs_APPIA(localvar,wd) \ - ((port->device == AQ_DEVICE_APPIA) ? ((localvar ## _APPIA)->u ## wd.word_ ## wd) : \ - (0)) - -#define AQ_API_WordOfLocalStruct_Devs_HHD(localvar,wd) \ - ((port->device == AQ_DEVICE_HHD) ? ((localvar ## _HHD)->u ## wd.word_ ## wd) : \ - (0)) - -#define AQ_API_WordOfLocalStruct_Devs_APPIA_HHD(localvar,wd) \ - ((port->device == AQ_DEVICE_HHD) ? ((localvar ## _HHD)->u ## wd.word_ ## wd) : \ - ((port->device == AQ_DEVICE_APPIA) ? ((localvar ## _APPIA)->u ## wd.word_ ## wd) : \ - (0))) - -#define AQ_API_WordOfLocalStruct_Devs_HHD_APPIA(localvar,wd) AQ_API_WordOfLocalStruct_Devs_APPIA_HHD(localvar,wd) - - -#define AQ_API_AssignWordOfLocalStruct(localvar,wd,value) AQ_API_AssignWordOfLocalStruct_DeviceRestricted(APPIA_HHD,localvar,wd,value) - -#define AQ_API_AssignWordOfLocalStruct_DeviceRestricted(devices,localvar,wd,value) AQ_API_AssignWordOfLocalStruct_Devs_ ## devices(localvar,wd,value) - -#define AQ_API_AssignWordOfLocalStruct_Devs_APPIA(localvar,wd,value) \ - ((port->device == AQ_DEVICE_APPIA) ? ((localvar ## _APPIA)->u ## wd.word_ ## wd = value) : \ - (0)) - -#define AQ_API_AssignWordOfLocalStruct_Devs_HHD(localvar,wd,value) \ - ((port->device == AQ_DEVICE_HHD) ? ((localvar ## _HHD)->u ## wd.word_ ## wd = value) : \ - (0)) - -#define AQ_API_AssignWordOfLocalStruct_Devs_APPIA_HHD(localvar,wd,value) \ - ((port->device == AQ_DEVICE_HHD) ? ((localvar ## _HHD)->u ## wd.word_ ## wd = value) : \ - ((port->device == AQ_DEVICE_APPIA) ? ((localvar ## _APPIA)->u ## wd.word_ ## wd = value) : \ - (0))) - -#define AQ_API_AssignWordOfLocalStruct_Devs_HHD_APPIA(localvar,wd,value) AQ_API_AssignWordOfLocalStruct_Devs_APPIA_HHD(localvar,wd,value) - - -#endif - diff --git a/qca/aq-fw-download/src/include/AQ_ReturnCodes.h b/qca/aq-fw-download/src/include/AQ_ReturnCodes.h deleted file mode 100644 index bff083b03..000000000 --- a/qca/aq-fw-download/src/include/AQ_ReturnCodes.h +++ /dev/null @@ -1,113 +0,0 @@ -/* AQ_ReturnCodes.h */ - -/************************************************************************************ -* Copyright (c) 2015, Aquantia -* -* Permission to use, copy, modify, and/or distribute this software for any -* purpose with or without fee is hereby granted, provided that the above -* copyright notice and this permission notice appear in all copies. -* -* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -* -* Description: -* -* This file defines the AQ_API functions' integral return codes. -* -* -************************************************************************************/ - -/*! \file - This file defines the AQ_API functions' integral return codes. -*/ - -#ifndef AQ_RETURNCODES_TOKEN -#define AQ_RETURNCODES_TOKEN - - -/*! \defgroup ReturnCodes - @{ -*/ - -/*! Most AQ_API functions return AQ_Retcode to report success or failure. - * The values used are defined as preprocessor symbols in AQ_ReturnCodes.h. - * Callers should prefer to test the return values by equivalence to these - * symbols, rather than using the integer values directly, as these may - * not be stable across releases. The set of possible return codes that may - * be returned by a particular API function can be found in the function's - * documentation, as well as information on how to interpret each of the - * possible return codes. */ -typedef unsigned int AQ_Retcode; - -/*! \defgroup Success - @{ */ -#define AQ_RET_OK 0 -/*@}*/ - - -/*! \defgroup GeneralErrors - @{ */ -#define AQ_RET_ERROR 100 -#define AQ_RET_UP_BUSY_TIMEOUT 101 -/*@}*/ - -/*! \defgroup FunctionSpecificResults - @{ */ -#define AQ_RET_FLASH_READY 200 -#define AQ_RET_FLASH_READINESS_TIMEOUT 204 - -#define AQ_RET_FLASHINTF_READY 201 -#define AQ_RET_FLASHINTF_NOTREADY 202 -#define AQ_RET_FLASHINTF_READINESS_TIMEOUT 203 - -#define AQ_RET_FLASH_TYPE_UNKNOWN 205 -#define AQ_RET_FLASH_TYPE_BAD 206 - -#define AQ_RET_FLASH_IMAGE_CORRUPT 207 -#define AQ_RET_FLASH_IMAGE_TOO_LARGE 208 -#define AQ_RET_FLASH_IMAGE_MISMATCH 209 - -#define AQ_RET_FLASH_PAGE_SIZE_CHANGED 210 - -#define AQ_RET_BOOTLOAD_PROVADDR_OOR 211 -#define AQ_RET_BOOTLOAD_NONUNIFORM_REGVALS 212 -#define AQ_RET_BOOTLOAD_CRC_MISMATCH 213 -#define AQ_RET_BOOTLOAD_PROVTABLE_TOO_LARGE 228 - -#define AQ_RET_LOOPBACK_BAD_ENTRY_STATE 214 - -#define AQ_RET_DEBUGTRACE_FREEZE_TIMEOUT 215 -#define AQ_RET_DEBUGTRACE_UNFREEZE_TIMEOUT 216 - -#define AQ_RET_CABLEDIAG_ALREADY_RUNNING 217 -#define AQ_RET_CABLEDIAG_STILL_RUNNING 218 -#define AQ_RET_CABLEDIAG_BAD_PAIRSTATUS 219 -#define AQ_RET_CABLEDIAG_RESULTS_ALREDY_COLLECTED 220 -#define AQ_RET_CABLEDIAG_BAD_NUM_SAMPLES 221 -#define AQ_RET_CABLEDIAG_REPORTEDPAIR_MISMATCH 222 -#define AQ_RET_CABLEDIAG_REPORTEDPAIR_OOR 223 -#define AQ_RET_CABLEDIAG_STARTED_PAIR_B 224 -#define AQ_RET_CABLEDIAG_STARTED_PAIR_C 225 -#define AQ_RET_CABLEDIAG_STARTED_PAIR_D 226 -#define AQ_RET_CABLEDIAG_TXENABLE_MISMATCH 227 - -#define AQ_RET_SERDESEYE_BAD_SERDES_MODE 229 -#define AQ_RET_SERDESEYE_BAD_MEAS_COUNT 230 -#define AQ_RET_SERDESEYE_MEAS_TIMEOUT 231 -#define AQ_RET_SERDESEYE_LANE_OOR 232 -#define AQ_RET_SERDESEYE_COORD_OOR 233 - -#define AQ_RET_PIFMAILBOX_ERROR 234 -#define AQ_RET_PIFMAILBOX_TIMEOUT 235 - -#define AQ_RET_SEC_TABLE_INDEX_OOR 236 -/*@}*/ - -/*@}*/ - -#endif diff --git a/qca/aq-fw-download/src/include/AQ_User.h b/qca/aq-fw-download/src/include/AQ_User.h deleted file mode 100644 index c7526a7cb..000000000 --- a/qca/aq-fw-download/src/include/AQ_User.h +++ /dev/null @@ -1,97 +0,0 @@ -/*AQ_User.h*/ - -/************************************************************************************ -* Copyright (c) 2015, Aquantia -* -* Permission to use, copy, modify, and/or distribute this software for any -* purpose with or without fee is hereby granted, provided that the above -* copyright notice and this permission notice appear in all copies. -* -* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -* -* Description: -* -* This file contains preprocessor symbol definitions and type definitions -* for the platform-integrator controlled compile-time AQ_API options. -* -************************************************************************************/ - -/*! \file - This file contains preprocessor symbol definitions and type definitions - for the platform-integrator controlled compile-time AQ_API options. -*/ - -#ifndef AQ_USER_TOKEN -#define AQ_USER_TOKEN - -/*! \defgroup User User Definitions -This module contains the definitions used to configure AQ_API behavior as desired. */ -/*@{*/ - - -/*! Specify the proper data type for AQ_Port. This will depend on the - * platform-specific implementation of the PHY register read/write functions.*/ -typedef unsigned int AQ_Port; - - -/*! If defined, AQ_API functions will print various error and info messages - * to stdout. If not, nothing will be printed and AQ_API.c will NOT include - * stdio.h. */ -#define AQ_VERBOSE - - -/*! If defined, the PHY interface supports block (asynchronous) read/write - * operation. If AQ_PHY_SUPPORTS_BLOCK_READ_WRITE is defined, then - * the API will call the block-operation functions and so implementations - * for each must be provided. If AQ_PHY_SUPPORTS_BLOCK_READ_WRITE is not - * defined, they will not be called, and need not be implemented. */ -#undef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE - - -/*! If defined, time.h exists, and so the associated functions wil be used to - * compute the elapsed time spent in a polling loop, to ensure that the - * maximum time-out period will not be exceeded. If not defined, then - * AQ_MDIO_READS_PER_SECOND will be used to calculate the minimum possible - * elapsed time. */ -#define AQ_TIME_T_EXISTS - - -/*! The maximum number of synchronous PHY register reads that can be performed - * per second. A worst case number can be derived as follows: - * - * AQ_MDIO_READS_PER_SECOND = MDIO Clock Frequency / 64 - * - * If using MDIO preamble suppression, multiply this number by 2 - * - * For instance, if a 5MHz MDIO clock is being used without preamble supression - * AQ_MDIO_READS_PER_SECOND = 78125 - * - * If AQ_TIME_T_EXISTS is defined, this will be ignored and need not be - * defined. If AQ_TIME_T_EXISTS is not defined, this must be defined. */ -#define AQ_MDIO_READS_PER_SECOND 78125 - - -/*! If defined, after writing to one of the registers that can trigger a - * processor-intensive MDIO operation, AQ_API functions will poll the - * the "processor intensive MDIO operation in progress" bit and wait for it - * to be zero before proceeding. */ -#define AQ_ENABLE_UP_BUSY_CHECKS - - -/*! If defined, the register map header files containing reverse-packed - * structs will be included. If not, the register map header files containing - * non-reverse-packed structs will be included. The proper choice is typically - * a function of the endianness of the platform; on big-endian systems the - * reverse-packed structs should be used, and on little-endian systems the - * non-reverse-packed structs should be used. */ -/*#define AQ_REVERSED_BITFIELD_ORDERING*/ - -/*@}*/ -#endif - diff --git a/qca/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers.h b/qca/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers.h deleted file mode 100644 index a9485f5a4..000000000 --- a/qca/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers.h +++ /dev/null @@ -1,5581 +0,0 @@ -/*! \file -* This file contains the data structures and doxygen comments -* for the Global Registers block. - */ - -/*! \addtogroup registerMap - @{ -*/ - -/*! \defgroup Global_registers Global Registers -* This module contains the data structures and doxygen comments -* for the Global Registers block. - */ -/*********************************************************************** -* Copyright (c) 2015, Aquantia -* -* Permission to use, copy, modify, and/or distribute this software for any -* purpose with or without fee is hereby granted, provided that the above -* copyright notice and this permission notice appear in all copies. -* -* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -* -* $Date: 2014/04/08 $ -* -* $Label: $ -* -* Description: -* -* This file contains the c header structures for the registers contained in the Global Registers block. -* -* The bit fields in this structure are from LSbit to MSbit -* -***********************************************************************/ - - -/*@{*/ -#ifndef AQ_APPIA_GLOBAL_REGS_HEADER -#define AQ_APPIA_GLOBAL_REGS_HEADER - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Standard Control 1: 1E.0000 */ -/* Global Standard Control 1: 1E.0000 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Standard Control 1 */ - union - { - struct - { - unsigned int reserved1 : 11; - /*! \brief 1E.0000.B R/WPD Low Power - AQ_GlobalStandardControl_1_APPIA.u0.bits_0.lowPower - - Provisionable Default = 0x0 - - 1 = Low-power mode - 0 = Normal operation - - - Notes: - A one written to this register causes the chip to enter low-power mode. This bit puts the entire chip in low-power mode, with only the MDIO and microprocessor functioning, and turns off the analog front-end: i.e. places it in high-impedance mode. Setting this bit also sets all of the Low Power bits in the other MMDs. */ - unsigned int lowPower : 1; /* 1E.0000.B R/WPD Provisionable Default = 0x0 */ - /* 1 = Low-power mode - 0 = Normal operation - */ - unsigned int reserved0 : 2; - /*! \brief 1E.0000.E R/WSC Hard Reset - AQ_GlobalStandardControl_1_APPIA.u0.bits_0.hardReset - - Default = 0x0 - - 1 = Global hard reset - 0 = Normal operation - - - Notes: - Setting this bit initiates a global hard reset, equivalent to pulling the reset pin low. This is a level sensitive pin that connects into the power-on reset generation circuitry to initiate a complete power-on reset. */ - unsigned int hardReset : 1; /* 1E.0000.E R/WSC Default = 0x0 */ - /* 1 = Global hard reset - 0 = Normal operation - */ - /*! \brief 1E.0000.F R/WSC Soft Reset - AQ_GlobalStandardControl_1_APPIA.u0.bits_0.softReset - - Default = 0x1 - - 1 = Global soft reset - 0 = Normal operation - - - Notes: - Setting this bit initiates a global soft reset on all of the digital logic, including the microprocessor. Upon completion of the reset sequence, this bit is set back to 0. */ - unsigned int softReset : 1; /* 1E.0000.F R/WSC Default = 0x1 */ - /* 1 = Global soft reset - 0 = Normal operation - */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalStandardControl_1_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Standard Device Identifier: 1E.0002 */ -/* Global Standard Device Identifier: 1E.0002 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Standard Device Identifier */ - union - { - struct - { - /*! \brief 1E.0002.F:0 RO Device ID MSW [1F:10] - AQ_GlobalStandardDeviceIdentifier_APPIA.u0.bits_0.deviceIdMSW - - - - Bits 31 - 16 of Device ID - */ - unsigned int deviceIdMSW : 16; /* 1E.0002.F:0 RO */ - /* Bits 31 - 16 of Device ID */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Standard Device Identifier */ - union - { - struct - { - /*! \brief 1E.0003.F:0 RO Device ID LSW [F:0] - AQ_GlobalStandardDeviceIdentifier_APPIA.u1.bits_1.deviceIdLSW - - - - Bits 15 - 0 of Device ID - */ - unsigned int deviceIdLSW : 16; /* 1E.0003.F:0 RO */ - /* Bits 15 - 0 of Device ID */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_GlobalStandardDeviceIdentifier_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Standard Devices in Package: 1E.0005 */ -/* Global Standard Devices in Package: 1E.0005 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Standard Devices in Package */ - union - { - struct - { - /*! \brief 1E.0005.0 ROS Clause 22 Registers Present - AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.clause_22RegistersPresent - - Default = 0x0 - - 1 = Clause 22 registers are present in package - 0 = Clause 22 registers are not present in package - - Notes: - This is always set to 0 in the PHY, as there are no Clause 22 registers in the device. */ - unsigned int clause_22RegistersPresent : 1; /* 1E.0005.0 ROS Default = 0x0 */ - /* 1 = Clause 22 registers are present in package - 0 = Clause 22 registers are not present in package */ - /*! \brief 1E.0005.1 ROS PMA Present - AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.pmaPresent - - Default = 0x1 - - 1 = PMA is present in package - 0 = PMA is not present - - Notes: - This is always set to 1 as there is PMA functionality in the PHY. */ - unsigned int pmaPresent : 1; /* 1E.0005.1 ROS Default = 0x1 */ - /* 1 = PMA is present in package - 0 = PMA is not present */ - /*! \brief 1E.0005.2 ROS WIS Present - AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.wisPresent - - Default = 0x0 - - 1 = WIS is present in package - 0 = WIS is not present in package - - Notes: - This is always set to 0, as there is no WIS functionality in the PHY. */ - unsigned int wisPresent : 1; /* 1E.0005.2 ROS Default = 0x0 */ - /* 1 = WIS is present in package - 0 = WIS is not present in package */ - /*! \brief 1E.0005.3 ROS PCS Present - AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.pcsPresent - - Default = 0x1 - - 1 = PCS is present in package - 0 = PCS is not present in package - - Notes: - This is always set to 1 as there is PCS functionality in the PHY. */ - unsigned int pcsPresent : 1; /* 1E.0005.3 ROS Default = 0x1 */ - /* 1 = PCS is present in package - 0 = PCS is not present in package */ - /*! \brief 1E.0005.4 ROS PHY XS Present - AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.phyXS_Present - - Default = 0x1 - - 1 = PHY XS is present in package - 0 = PHY XS is not present in package - - Notes: - This is always set to 1 as there is a PHY XS interface in the PHY. */ - unsigned int phyXS_Present : 1; /* 1E.0005.4 ROS Default = 0x1 */ - /* 1 = PHY XS is present in package - 0 = PHY XS is not present in package */ - /*! \brief 1E.0005.5 ROS DTE XS Present - AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.dteXsPresent - - Default = 0x0 - - 1 = DTE XS is present in package - 0 = DTE XS is not present in package - - - Notes: - This is always set to 0, as there is no DTE XAUI interface in the PHY. */ - unsigned int dteXsPresent : 1; /* 1E.0005.5 ROS Default = 0x0 */ - /* 1 = DTE XS is present in package - 0 = DTE XS is not present in package - */ - /*! \brief 1E.0005.6 ROS TC Present - AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.tcPresent - - Default = 0x0 - - 1 = TC is present in package - 0 = TC is not present in package - - Notes: - This is always set to 0, as there is no TC functionality in the PHY. */ - unsigned int tcPresent : 1; /* 1E.0005.6 ROS Default = 0x0 */ - /* 1 = TC is present in package - 0 = TC is not present in package */ - /*! \brief 1E.0005.7 ROS Autonegotiation Present - AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.autonegotiationPresent - - Default = 0x1 - - 1 = Autonegotiation is present in package - 0 = Autonegotiation is not present in package - - Notes: - This is always set to 1, as there is Autonegotiation in the PHY. */ - unsigned int autonegotiationPresent : 1; /* 1E.0005.7 ROS Default = 0x1 */ - /* 1 = Autonegotiation is present in package - 0 = Autonegotiation is not present in package */ - unsigned int reserved0 : 8; - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalStandardDevicesInPackage_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Standard Vendor Devices in Package: 1E.0006 */ -/* Global Standard Vendor Devices in Package: 1E.0006 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Standard Vendor Devices in Package */ - union - { - struct - { - unsigned int reserved0 : 13; - /*! \brief 1E.0006.D ROS Clause 22 Extension Present - AQ_GlobalStandardVendorDevicesInPackage_APPIA.u0.bits_0.clause_22ExtensionPresent - - Default = 0x1 - - 1 = Clause 22 Extension is present in package - 0 = Clause 22 Extension is not present in package - - Notes: - This is always set to 1 as the PHY utilizes this device for the GbE registers. */ - unsigned int clause_22ExtensionPresent : 1; /* 1E.0006.D ROS Default = 0x1 */ - /* 1 = Clause 22 Extension is present in package - 0 = Clause 22 Extension is not present in package */ - /*! \brief 1E.0006.E ROS Vendor Specific Device #1 Present - AQ_GlobalStandardVendorDevicesInPackage_APPIA.u0.bits_0.vendorSpecificDevice_1Present - - Default = 0x1 - - 1 = Device #1 is present in package - 0 = Device #1 is not present in package - - Notes: - This is always set to 1 as the PHY utilizes this device for the global control registers. */ - unsigned int vendorSpecificDevice_1Present : 1; /* 1E.0006.E ROS Default = 0x1 */ - /* 1 = Device #1 is present in package - 0 = Device #1 is not present in package */ - /*! \brief 1E.0006.F ROS Vendor Specific Device #2 Present - AQ_GlobalStandardVendorDevicesInPackage_APPIA.u0.bits_0.vendorSpecificDevice_2Present - - Default = 0x1 - - 1 = Device #2 is present in package - 0 = Device #2 is not present in package - - Notes: - This is always set to 1 as the PHY utilizes this device for the DSP PMA registers. */ - unsigned int vendorSpecificDevice_2Present : 1; /* 1E.0006.F ROS Default = 0x1 */ - /* 1 = Device #2 is present in package - 0 = Device #2 is not present in package */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalStandardVendorDevicesInPackage_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Standard Status 2: 1E.0008 */ -/* Global Standard Status 2: 1E.0008 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Standard Status 2 */ - union - { - struct - { - unsigned int reserved0 : 14; - /*! \brief 1E.0008.F:E ROS Device Present [1:0] - AQ_GlobalStandardStatus_2_APPIA.u0.bits_0.devicePresent - - Default = 0x2 - - [F:E] - 0x3 = No device at this address - 0x2 = Device present at this address - 0x1 = No device at this address - 0x0 = No device at this address - - Notes: - This field is always set to 0x2, as the Global MMD resides here in the PHY. */ - unsigned int devicePresent : 2; /* 1E.0008.F:E ROS Default = 0x2 */ - /* [F:E] - 0x3 = No device at this address - 0x2 = Device present at this address - 0x1 = No device at this address - 0x0 = No device at this address */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalStandardStatus_2_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Standard Package Identifier: 1E.000E */ -/* Global Standard Package Identifier: 1E.000E */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Standard Package Identifier */ - union - { - struct - { - /*! \brief 1E.000E.F:0 RO Package ID MSW [1F:10] - AQ_GlobalStandardPackageIdentifier_APPIA.u0.bits_0.packageIdMSW - - - - Bits 31- 16 of Package ID - */ - unsigned int packageIdMSW : 16; /* 1E.000E.F:0 RO */ - /* Bits 31- 16 of Package ID */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Standard Package Identifier */ - union - { - struct - { - /*! \brief 1E.000F.F:0 RO Package ID LSW [F:0] - AQ_GlobalStandardPackageIdentifier_APPIA.u1.bits_1.packageIdLSW - - - - Bits 15 - 0 of Package ID - */ - unsigned int packageIdLSW : 16; /* 1E.000F.F:0 RO */ - /* Bits 15 - 0 of Package ID */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_GlobalStandardPackageIdentifier_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Firmware ID: 1E.0020 */ -/* Global Firmware ID: 1E.0020 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Firmware ID */ - union - { - struct - { - /*! \brief 1E.0020.7:0 RO Firmware Minor Revision Number [7:0] - AQ_GlobalFirmwareID_APPIA.u0.bits_0.firmwareMinorRevisionNumber - - - - [7:0] = Minor revision number - - Notes: - - - The lower six bits of major and minor firmware revision are exchanged in autonegotiation when the PHYID message is sent. */ - unsigned int firmwareMinorRevisionNumber : 8; /* 1E.0020.7:0 RO */ - /* [7:0] = Minor revision number */ - /*! \brief 1E.0020.F:8 RO Firmware Major Revision Number [7:0] - AQ_GlobalFirmwareID_APPIA.u0.bits_0.firmwareMajorRevisionNumber - - - - [F:8] = Major revision number - - Notes: - - - The lower six bits of major and minor firmware revision are exchanged in autonegotiation when the PHYID message is sent. */ - unsigned int firmwareMajorRevisionNumber : 8; /* 1E.0020.F:8 RO */ - /* [F:8] = Major revision number */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalFirmwareID_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Chip Identification: 1E.0021 */ -/* Global Chip Identification: 1E.0021 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Chip Identification */ - union - { - struct - { - /*! \brief 1E.0021.F:0 RO Chip Identification [F:0] - AQ_GlobalChipIdentification_APPIA.u0.bits_0.chipIdentification - - - - Hardware Chip ID - - Notes: - This value is a hard-coded chip ID */ - unsigned int chipIdentification : 16; /* 1E.0021.F:0 RO */ - /* Hardware Chip ID */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalChipIdentification_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Chip Revision: 1E.0022 */ -/* Global Chip Revision: 1E.0022 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Chip Revision */ - union - { - struct - { - /*! \brief 1E.0022.F:0 RO Chip Revision [F:0] - AQ_GlobalChipRevision_APPIA.u0.bits_0.chipRevision - - - - Hardware Chip Revision - - Notes: - This value is a hard-coded chip revision */ - unsigned int chipRevision : 16; /* 1E.0022.F:0 RO */ - /* Hardware Chip Revision */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalChipRevision_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global NVR Interface: 1E.0100 */ -/* Global NVR Interface: 1E.0100 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global NVR Interface */ - union - { - struct - { - /*! \brief 1E.0100.7:0 R/W NVR Opcode [7:0] - AQ_GlobalNvrInterface_APPIA.u0.bits_0.nvrOpcode - - Default = 0x03 - - NVR instruction opcode - - */ - unsigned int nvrOpcode : 8; /* 1E.0100.7:0 R/W Default = 0x03 */ - /* NVR instruction opcode - */ - /*! \brief 1E.0100.8 RO NVR Busy - AQ_GlobalNvrInterface_APPIA.u0.bits_0.nvrBusy - - - - 1 = NVR is busy - 0 = NVR is ready - - - Notes: - When set to 1, the NVR is busy. A new NVR operation should not occur until this bit is 0. If the NVR clock is greater than 64/63 of the MDIO clock, this bit never needs to be polled when operating over the MDIO. */ - unsigned int nvrBusy : 1; /* 1E.0100.8 RO */ - /* 1 = NVR is busy - 0 = NVR is ready - */ - unsigned int reserved1 : 1; - /*! \brief 1E.0100.A R/W NVR Burst - AQ_GlobalNvrInterface_APPIA.u0.bits_0.nvrBurst - - Default = 0x0 - - 0 = Single read or write operation of up to 4 bytes - 1 = Burst operation - - - Notes: - When this bit is set, the operation is a burst operation where more than 32-bits is read from the NVR or written to the NVR. This bit should be set to one until the last burst in the read or write operation, when it should be set to zero. It operates by gating the SPI clock, and not restarting it until new data is ready to be written, or the previous contents have been read. Each burst of data requires the NVR Execute Operation bit to be set to initiate the next phase. */ - unsigned int nvrBurst : 1; /* 1E.0100.A R/W Default = 0x0 */ - /* 0 = Single read or write operation of up to 4 bytes - 1 = Burst operation - */ - unsigned int reserved0 : 1; - /*! \brief 1E.0100.C R/WSC Reset NVR CRC - AQ_GlobalNvrInterface_APPIA.u0.bits_0.resetNvrCrc - - Default = 0x0 - - 1 = Reset NVR Mailbox CRC calculation register - - - Notes: - To prevent an erroneous answer, this bit should not be set at the same time the See NVR Operation Valid bit is set. */ - unsigned int resetNvrCrc : 1; /* 1E.0100.C R/WSC Default = 0x0 */ - /* 1 = Reset NVR Mailbox CRC calculation register - */ - /*! \brief 1E.0100.D R/W Freeze NVR CRC - AQ_GlobalNvrInterface_APPIA.u0.bits_0.freezeNvrCrc - - Default = 0x0 - - 1 = Freeze NVR Mailbox CRC calculation register - - - Notes: - To prevent an erroneous answer, this bit should not be set at the same time the See NVR Operation Valid bit is set. */ - unsigned int freezeNvrCrc : 1; /* 1E.0100.D R/W Default = 0x0 */ - /* 1 = Freeze NVR Mailbox CRC calculation register - */ - /*! \brief 1E.0100.E R/W NVR Write Mode - AQ_GlobalNvrInterface_APPIA.u0.bits_0.nvrWriteMode - - Default = 0x0 - - 1 = Write to NVR - 0 = Read from NVR - - */ - unsigned int nvrWriteMode : 1; /* 1E.0100.E R/W Default = 0x0 */ - /* 1 = Write to NVR - 0 = Read from NVR - */ - /*! \brief 1E.0100.F R/WSC NVR Execute Operation - AQ_GlobalNvrInterface_APPIA.u0.bits_0.nvrExecuteOperation - - Default = 0x0 - - 1 = Start NVR Operation - - - Notes: - When set to 1, the NVR operation will begin. Ensure that the uP is stalled using the See MCP Run Stall bit to ensure no NVR contention. */ - unsigned int nvrExecuteOperation : 1; /* 1E.0100.F R/WSC Default = 0x0 */ - /* 1 = Start NVR Operation - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global NVR Interface */ - union - { - struct - { - /*! \brief 1E.0101.F:0 RO NVR Mailbox CRC [F:0] - AQ_GlobalNvrInterface_APPIA.u1.bits_1.nvrMailboxCrc - - - - The running CRC-16 of everything passing through the NVR interface - - - Notes: - The CRC-16 over all data written or read through the NVR interface. The CRC-16 is calculated by dividing the data by: - x^16 + x^12 + x^5 + 1 */ - unsigned int nvrMailboxCrc : 16; /* 1E.0101.F:0 RO */ - /* The running CRC-16 of everything passing through the NVR interface - */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global NVR Interface */ - union - { - struct - { - /*! \brief 1E.0102.7:0 R/W NVR Address MSW [17:10] - AQ_GlobalNvrInterface_APPIA.u2.bits_2.nvrAddressMSW - - Default = 0x00 - - NVR address MSW bits [17:10] - - - Notes: - The address of where to read and write from in the NVR. This is self-incrementing and will automatically increment after each read or write operation. The increment amount is based on the data length (i.e. increments by 4 if the data length is 4 bytes) */ - unsigned int nvrAddressMSW : 8; /* 1E.0102.7:0 R/W Default = 0x00 */ - /* NVR address MSW bits [17:10] - */ - unsigned int reserved0 : 8; - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global NVR Interface */ - union - { - struct - { - /*! \brief 1E.0103.F:0 R/W NVR Address LSW [F:0] - AQ_GlobalNvrInterface_APPIA.u3.bits_3.nvrAddressLSW - - Default = 0x0000 - - NVR address LSW bits [F:0] - - - Notes: - The address of where to read and write from in the NVR. This is self-incrementing and will automatically increment after each read or write operation. */ - unsigned int nvrAddressLSW : 16; /* 1E.0103.F:0 R/W Default = 0x0000 */ - /* NVR address LSW bits [F:0] - */ - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of Global NVR Interface */ - union - { - struct - { - /*! \brief 1E.0104.F:0 R/W NVR Data MSW [1F:10] - AQ_GlobalNvrInterface_APPIA.u4.bits_4.nvrDataMSW - - Default = 0x0000 - - NVR data MSW bits [1F:10] - - - Notes: - Data is stored and read-out from these registers in little-endian format for operations such as FLASH device ID, and for programming the processor. - - For instance the 64K Atmel device code reads out as two bytes 0x651F into the LSW register, whereas the datasheet indicates that 1F is the first byte read, followed by 65 as the second byte. - - To burst read and write these 4 bytes in the correct order (where DD is written to address x), they should be stored as: - - AA BB in the MSW - CC DD in the LSW. */ - unsigned int nvrDataMSW : 16; /* 1E.0104.F:0 R/W Default = 0x0000 */ - /* NVR data MSW bits [1F:10] - */ - } bits_4; - uint16_t word_4; - } u4; - /*! \brief Union for bit and word level access of word 5 of Global NVR Interface */ - union - { - struct - { - /*! \brief 1E.0105.F:0 R/W NVR Data LSW [F:0] - AQ_GlobalNvrInterface_APPIA.u5.bits_5.nvrDataLSW - - Default = 0x0000 - - NVR data LSW bits [F:0] - - - Notes: - Data is stored and read-out from these registers in little-endian format for operations such as FLASH device ID, and for programming the processor. - - For instance the 64K Atmel device code reads out as two bytes 0x651F into the LSW register, whereas the datasheet indicates that 1F is the first byte read, followed by 65 as the second byte. - To burst read and write these 4 bytes in the correct order (where DD is written to address x), they should be stored as: - - AA BB in the MSW - CC DD in the LSW. */ - unsigned int nvrDataLSW : 16; /* 1E.0105.F:0 R/W Default = 0x0000 */ - /* NVR data LSW bits [F:0] - */ - } bits_5; - uint16_t word_5; - } u5; -} AQ_GlobalNvrInterface_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Mailbox Interface: 1E.0200 */ -/* Global Mailbox Interface: 1E.0200 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Mailbox Interface */ - union - { - struct - { - unsigned int reserved2 : 8; - /*! \brief 1E.0200.8 RO uP Mailbox Busy - AQ_GlobalMailboxInterface_APPIA.u0.bits_0.upMailboxBusy - - - - 1 = uP mailbox busy - 0 = uP mailbox ready - - - Notes: - In general the uP will respond within a few processor cycles to any PIF slave request, much faster than the MDIO. If the busy is asserted over multiple MDIO polling cycles, then a H/W error may have occured and a Global S/W reset or uP reset is required. */ - unsigned int upMailboxBusy : 1; /* 1E.0200.8 RO */ - /* 1 = uP mailbox busy - 0 = uP mailbox ready - */ - unsigned int reserved1 : 3; - /*! \brief 1E.0200.C R/WSC Reset uP Mailbox CRC - AQ_GlobalMailboxInterface_APPIA.u0.bits_0.resetUpMailboxCrc - - Default = 0x0 - - 1 = Reset uP mailbox CRC calculation register - - */ - unsigned int resetUpMailboxCrc : 1; /* 1E.0200.C R/WSC Default = 0x0 */ - /* 1 = Reset uP mailbox CRC calculation register - */ - unsigned int reserved0 : 1; - /*! \brief 1E.0200.E R/W uP Mailbox Write Mode - AQ_GlobalMailboxInterface_APPIA.u0.bits_0.upMailboxWriteMode - - Default = 0x0 - - 1 = Write - 0 = Read - - - Notes: - Mailbox direction */ - unsigned int upMailboxWriteMode : 1; /* 1E.0200.E R/W Default = 0x0 */ - /* 1 = Write - 0 = Read - */ - /*! \brief 1E.0200.F R/WSC uP Mailbox Execute Operation - AQ_GlobalMailboxInterface_APPIA.u0.bits_0.upMailboxExecuteOperation - - Default = 0x0 - - 1 = Start of mailbox Operation - - - Notes: - Indicates mailbox is loaded and ready */ - unsigned int upMailboxExecuteOperation : 1; /* 1E.0200.F R/WSC Default = 0x0 */ - /* 1 = Start of mailbox Operation - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Mailbox Interface */ - union - { - struct - { - /*! \brief 1E.0201.F:0 RO uP Mailbox CRC [F:0] - AQ_GlobalMailboxInterface_APPIA.u1.bits_1.upMailboxCrc - - - - The running CRC-16 of everything passing through the mailbox interface - - */ - unsigned int upMailboxCrc : 16; /* 1E.0201.F:0 RO */ - /* The running CRC-16 of everything passing through the mailbox interface - */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global Mailbox Interface */ - union - { - struct - { - /*! \brief 1E.0202.F:0 R/W uP Mailbox Address MSW [1F:10] - AQ_GlobalMailboxInterface_APPIA.u2.bits_2.upMailboxAddressMSW - - Default = 0x0000 - - uP Mailbox MSW address - - - Notes: - The address of where to read and write from in the Microcontroller Mailbox. This is self-incrementing and automatically increments after each read and write operation.PHY */ - unsigned int upMailboxAddressMSW : 16; /* 1E.0202.F:0 R/W Default = 0x0000 */ - /* uP Mailbox MSW address - */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global Mailbox Interface */ - union - { - struct - { - /*! \brief 1E.0203.1:0 RO uP Mailbox Address LSW Don't Care [1:0] - AQ_GlobalMailboxInterface_APPIA.u3.bits_3.upMailboxAddressLSW_Don_tCare - - - - Least significant uP LSW Mailbox address bits [1:0] - - - Notes: - These bits are always set to 0 since each memory access is on a 4-byte boundary. */ - unsigned int upMailboxAddressLSW_Don_tCare : 2; /* 1E.0203.1:0 RO */ - /* Least significant uP LSW Mailbox address bits [1:0] - */ - /*! \brief 1E.0203.F:2 R/W uP Mailbox Address LSW [F:2] - AQ_GlobalMailboxInterface_APPIA.u3.bits_3.upMailboxAddressLSW - - Default = 0x0000 - - uP LSW Mailbox address [F:2] - - - Notes: - The address of where to read and write from in the Microcontroller Mailbox. This is self-incrementing and automatically increments after each read and write operation.PHY */ - unsigned int upMailboxAddressLSW : 14; /* 1E.0203.F:2 R/W Default = 0x0000 */ - /* uP LSW Mailbox address [F:2] - */ - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of Global Mailbox Interface */ - union - { - struct - { - /*! \brief 1E.0204.F:0 R/W uP Mailbox Data MSW [1F:10] - AQ_GlobalMailboxInterface_APPIA.u4.bits_4.upMailboxDataMSW - - Default = 0x0000 - - uP Mailbox data MSW - - */ - unsigned int upMailboxDataMSW : 16; /* 1E.0204.F:0 R/W Default = 0x0000 */ - /* uP Mailbox data MSW - */ - } bits_4; - uint16_t word_4; - } u4; - /*! \brief Union for bit and word level access of word 5 of Global Mailbox Interface */ - union - { - struct - { - /*! \brief 1E.0205.F:0 R/W uP Mailbox Data LSW [F:0] - AQ_GlobalMailboxInterface_APPIA.u5.bits_5.upMailboxDataLSW - - Default = 0x0000 - - uP Mailbox data LSW - - */ - unsigned int upMailboxDataLSW : 16; /* 1E.0205.F:0 R/W Default = 0x0000 */ - /* uP Mailbox data LSW - */ - } bits_5; - uint16_t word_5; - } u5; -} AQ_GlobalMailboxInterface_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Microprocessor Scratch Pad: 1E.0300 */ -/* Global Microprocessor Scratch Pad: 1E.0300 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Microprocessor Scratch Pad */ - union - { - struct - { - /*! \brief 1E.0300.F:0 R/W Scratch Pad 1[F:0] - AQ_GlobalMicroprocessorScratchPad_APPIA.u0.bits_0.scratchPad_1 - - Default = 0x0000 - - General Purpose Scratch Pad1 - */ - unsigned int scratchPad_1 : 16; /* 1E.0300.F:0 R/W Default = 0x0000 */ - /* General Purpose Scratch Pad1 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Microprocessor Scratch Pad */ - union - { - struct - { - /*! \brief 1E.0301.F:0 R/W Scratch Pad 2 [F:0] - AQ_GlobalMicroprocessorScratchPad_APPIA.u1.bits_1.scratchPad_2 - - Default = 0x0000 - - General Purpose Scratch P - */ - unsigned int scratchPad_2 : 16; /* 1E.0301.F:0 R/W Default = 0x0000 */ - /* General Purpose Scratch P */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_GlobalMicroprocessorScratchPad_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Control: 1E.C000 */ -/* Global Control: 1E.C000 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Control */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Control */ - union - { - struct - { - /*! \brief 1E.C001.0 R/W uP Run Stall - AQ_GlobalControl_APPIA.u1.bits_1.upRunStall - - Default = 0x0 - - 1 = uP Run Stall - 0 = uP normal mode - - - Notes: - Deactivates the uP. The PIF slave bus for inbound requests will still be active. This bit is muliplexed with the "MDIO Boot Load" pin with the See uP Run Stall Override bit as the select. When the "MDIO Boot Load" pin is asserted, the uP will be in Run Stall mode after reset. */ - unsigned int upRunStall : 1; /* 1E.C001.0 R/W Default = 0x0 */ - /* 1 = uP Run Stall - 0 = uP normal mode - */ - unsigned int reserved1 : 5; - /*! \brief 1E.C001.6 R/W uP Run Stall Override - AQ_GlobalControl_APPIA.u1.bits_1.upRunStallOverride - - Default = 0x0 - - 0 = uP Run Stall from "MDIO Boot Load" pin. - 1 = uP Run Stall from See MCP Run Stall bit - - - Notes: - This bit selects the uP Run Stall from either the "MDIO Boot Load" pin or the See MCP Run Stall bit. */ - unsigned int upRunStallOverride : 1; /* 1E.C001.6 R/W Default = 0x0 */ - /* 0 = uP Run Stall from "MDIO Boot Load" pin. - 1 = uP Run Stall from See MCP Run Stall bit - */ - unsigned int reserved0 : 8; - /*! \brief 1E.C001.F R/W uP Reset - AQ_GlobalControl_APPIA.u1.bits_1.upReset - - Default = 0x0 - - 1 = Reset - - - Notes: - Resets the uP and the PIF master and slave bus. Will be active for a minimum of 100 microseconds. */ - unsigned int upReset : 1; /* 1E.C001.F R/W Default = 0x0 */ - /* 1 = Reset - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_GlobalControl_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Reset Control: 1E.C006 */ -/* Global Reset Control: 1E.C006 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Reset Control */ - union - { - struct - { - unsigned int reserved1 : 14; - /*! \brief 1E.C006.E R/WPD Global MMD Reset Disable - AQ_GlobalResetControl_APPIA.u0.bits_0.globalMMD_ResetDisable - - Provisionable Default = 0x0 - - 1 = Disable the S/W reset to the Global MMD registers - 0 = Enable the S/W reset to the Global MMD registers - - - Notes: - Setting this bit prevents a Global S/W reset or Global S/W reset from resetting the Global MMD registers */ - unsigned int globalMMD_ResetDisable : 1; /* 1E.C006.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Disable the S/W reset to the Global MMD registers - 0 = Enable the S/W reset to the Global MMD registers - */ - unsigned int reserved0 : 1; - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalResetControl_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Diagnostic Provisioning: 1E.C400 */ -/* Global Diagnostic Provisioning: 1E.C400 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Diagnostic Provisioning */ - union - { - struct - { - unsigned int reserved0 : 15; - /*! \brief 1E.C400.F R/WPD Enable Diagnostics - AQ_GlobalDiagnosticProvisioning_APPIA.u0.bits_0.enableDiagnostics - - Provisionable Default = 0x1 - - 1 = Chip performs diagnostics on power-up - */ - unsigned int enableDiagnostics : 1; /* 1E.C400.F R/WPD Provisionable Default = 0x1 */ - /* 1 = Chip performs diagnostics on power-up */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalDiagnosticProvisioning_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Thermal Provisioning: 1E.C420 */ -/* Global Thermal Provisioning: 1E.C420 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Thermal Provisioning */ - union - { - struct - { - /*! \brief 1E.C420.F:0 R/WPD Reserved 0 [F:0] - AQ_GlobalThermalProvisioning_APPIA.u0.bits_0.reserved_0 - - Provisionable Default = 0x0000 - - Internal reserved - do not modify - - */ - unsigned int reserved_0 : 16; /* 1E.C420.F:0 R/WPD Provisionable Default = 0x0000 */ - /* Internal reserved - do not modify - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Thermal Provisioning */ - union - { - struct - { - /*! \brief 1E.C421.F:0 R/WPD High Temp Failure Threshold [F:0] - AQ_GlobalThermalProvisioning_APPIA.u1.bits_1.highTempFailureThreshold - - Provisionable Default = 0x4600 - - [F:0] of high temperature failure threshold - - Notes: - 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 70 degreesC. - - In XENPAK mode, F/W will use the XENPAK register 1.A000 - 1.A001: instead of this register. - - NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. - High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ - unsigned int highTempFailureThreshold : 16; /* 1E.C421.F:0 R/WPD Provisionable Default = 0x4600 */ - /* [F:0] of high temperature failure threshold */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global Thermal Provisioning */ - union - { - struct - { - /*! \brief 1E.C422.F:0 R/WPD Low Temp Failure Threshold [F:0] - AQ_GlobalThermalProvisioning_APPIA.u2.bits_2.lowTempFailureThreshold - - Provisionable Default = 0x0000 - - [F:0] of low temperature failure threshold - - Notes: - 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 0 degreesC. - - In XENPAK mode, F/W will use the XENPAK register 1.A002 - 1.A003: instead of this register. - - NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. - High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ - unsigned int lowTempFailureThreshold : 16; /* 1E.C422.F:0 R/WPD Provisionable Default = 0x0000 */ - /* [F:0] of low temperature failure threshold */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global Thermal Provisioning */ - union - { - struct - { - /*! \brief 1E.C423.F:0 R/WPD High Temp Warning Threshold [F:0] - AQ_GlobalThermalProvisioning_APPIA.u3.bits_3.highTempWarningThreshold - - Provisionable Default = 0x3C00 - - [F:0] of high temperature warning threshold - - Notes: - 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD008. Default is 60 degreesC. - - In XENPAK mode, F/W will use the XENPAK register 1.A004 - 1.A005: instead of this register. - - NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. - High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ - unsigned int highTempWarningThreshold : 16; /* 1E.C423.F:0 R/WPD Provisionable Default = 0x3C00 */ - /* [F:0] of high temperature warning threshold */ - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of Global Thermal Provisioning */ - union - { - struct - { - /*! \brief 1E.C424.F:0 R/WPD Low Temp Warning Threshold [F:0] - AQ_GlobalThermalProvisioning_APPIA.u4.bits_4.lowTempWarningThreshold - - Provisionable Default = 0x0A00 - - [F:0] of low temperature warning threshold - - Notes: - 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 10 degreesC. - - In XENPAK mode, F/W will use the XENPAK register 1.A006 - 1.A007: instead of this register. - - NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. - High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ - unsigned int lowTempWarningThreshold : 16; /* 1E.C424.F:0 R/WPD Provisionable Default = 0x0A00 */ - /* [F:0] of low temperature warning threshold */ - } bits_4; - uint16_t word_4; - } u4; -} AQ_GlobalThermalProvisioning_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global LED Provisioning: 1E.C430 */ -/* Global LED Provisioning: 1E.C430 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global LED Provisioning */ - union - { - struct - { - /*! \brief 1E.C430.1:0 R/WPD LED #0 Activity Stretch [1:0] - AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0ActivityStretch - - Provisionable Default = 0x3 - - [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - - */ - unsigned int led_0ActivityStretch : 2; /* 1E.C430.1:0 R/WPD Provisionable Default = 0x3 */ - /* [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - */ - /*! \brief 1E.C430.2 R/WPD LED #0 Transmit Activity - AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0TransmitActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on transmit activity - - */ - unsigned int led_0TransmitActivity : 1; /* 1E.C430.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on transmit activity - */ - /*! \brief 1E.C430.3 R/WPD LED #0 Receive Activity - AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0ReceiveActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on receive activity - - */ - unsigned int led_0ReceiveActivity : 1; /* 1E.C430.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on receive activity - */ - /*! \brief 1E.C430.4 R/WPD LED #0 Connecting - AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0Connecting - - Provisionable Default = 0x0 - - 1 = LED is on when attempting to connect. - - */ - unsigned int led_0Connecting : 1; /* 1E.C430.4 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when attempting to connect. - */ - /*! \brief 1E.C430.5 R/WPD LED #0 100 Mb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0_100Mb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 100 Mb/s - - */ - unsigned int led_0_100Mb_sLinkEstablished : 1; /* 1E.C430.5 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 100 Mb/s - */ - /*! \brief 1E.C430.6 R/WPD LED #0 1 Gb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0_1Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 1 Gb/s - - */ - unsigned int led_0_1Gb_sLinkEstablished : 1; /* 1E.C430.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 1 Gb/s - */ - /*! \brief 1E.C430.7 R/WPD LED #0 10 Gb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0_10Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 10 Gb/s - - */ - unsigned int led_0_10Gb_sLinkEstablished : 1; /* 1E.C430.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 10 Gb/s - */ - /*! \brief 1E.C430.8 R/WPD LED #0 Manual Set - AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0ManualSet - - Provisionable Default = 0x0 - - 1 = LED On - - */ - unsigned int led_0ManualSet : 1; /* 1E.C430.8 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED On - */ - unsigned int reserved0 : 7; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global LED Provisioning */ - union - { - struct - { - /*! \brief 1E.C431.1:0 R/WPD LED #1 Activity Stretch [1:0] - AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1ActivityStretch - - Provisionable Default = 0x3 - - [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - - */ - unsigned int led_1ActivityStretch : 2; /* 1E.C431.1:0 R/WPD Provisionable Default = 0x3 */ - /* [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - */ - /*! \brief 1E.C431.2 R/WPD LED #1 Transmit Activity - AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1TransmitActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on transmit activity - - */ - unsigned int led_1TransmitActivity : 1; /* 1E.C431.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on transmit activity - */ - /*! \brief 1E.C431.3 R/WPD LED #1 Receive Activity - AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1ReceiveActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on receive activity - - */ - unsigned int led_1ReceiveActivity : 1; /* 1E.C431.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on receive activity - */ - /*! \brief 1E.C431.4 R/WPD LED #1 Connecting - AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1Connecting - - Provisionable Default = 0x0 - - 1 = LED is on when attempting to connect. - - */ - unsigned int led_1Connecting : 1; /* 1E.C431.4 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when attempting to connect. - */ - /*! \brief 1E.C431.5 R/WPD LED #1 100 Mb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1_100Mb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 100 Mb/s - - */ - unsigned int led_1_100Mb_sLinkEstablished : 1; /* 1E.C431.5 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 100 Mb/s - */ - /*! \brief 1E.C431.6 R/WPD LED #1 1 Gb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1_1Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 1 Gb/s - - */ - unsigned int led_1_1Gb_sLinkEstablished : 1; /* 1E.C431.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 1 Gb/s - */ - /*! \brief 1E.C431.7 R/WPD LED #1 10 Gb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1_10Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 10 Gb/s - - */ - unsigned int led_1_10Gb_sLinkEstablished : 1; /* 1E.C431.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 10 Gb/s - */ - /*! \brief 1E.C431.8 R/WPD LED #1 Manual Set - AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1ManualSet - - Provisionable Default = 0x0 - - 1 = LED On - - */ - unsigned int led_1ManualSet : 1; /* 1E.C431.8 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED On - */ - unsigned int reserved0 : 7; - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global LED Provisioning */ - union - { - struct - { - /*! \brief 1E.C432.1:0 R/WPD LED #2 Activity Stretch [1:0] - AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2ActivityStretch - - Provisionable Default = 0x3 - - [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - - */ - unsigned int led_2ActivityStretch : 2; /* 1E.C432.1:0 R/WPD Provisionable Default = 0x3 */ - /* [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - */ - /*! \brief 1E.C432.2 R/WPD LED #2 Transmit Activity - AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2TransmitActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on transmit activity - - */ - unsigned int led_2TransmitActivity : 1; /* 1E.C432.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on transmit activity - */ - /*! \brief 1E.C432.3 R/WPD LED #2 Receive Activity - AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2ReceiveActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on receive activity - - */ - unsigned int led_2ReceiveActivity : 1; /* 1E.C432.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on receive activity - */ - /*! \brief 1E.C432.4 R/WPD LED #2 Connecting - AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2Connecting - - Provisionable Default = 0x0 - - 1 = LED is on when attempting to connect. - - */ - unsigned int led_2Connecting : 1; /* 1E.C432.4 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when attempting to connect. - */ - /*! \brief 1E.C432.5 R/WPD LED #2 100 Mb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2_100Mb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 100 Mb/s - - */ - unsigned int led_2_100Mb_sLinkEstablished : 1; /* 1E.C432.5 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 100 Mb/s - */ - /*! \brief 1E.C432.6 R/WPD LED #2 1 Gb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2_1Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 1 Gb/s - - */ - unsigned int led_2_1Gb_sLinkEstablished : 1; /* 1E.C432.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 1 Gb/s - */ - /*! \brief 1E.C432.7 R/WPD LED #2 10 Gb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2_10Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 10 Gb/s - - */ - unsigned int led_2_10Gb_sLinkEstablished : 1; /* 1E.C432.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 10 Gb/s - */ - /*! \brief 1E.C432.8 R/WPD LED #2 Manual Set - AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2ManualSet - - Provisionable Default = 0x0 - - 1 = LED On - - */ - unsigned int led_2ManualSet : 1; /* 1E.C432.8 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED On - */ - unsigned int reserved0 : 7; - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global LED Provisioning */ - union - { - struct - { - /*! \brief 1E.C433.1:0 R/WPD LED #3 Activity Stretch [1:0] - AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3ActivityStretch - - Provisionable Default = 0x3 - - [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - - */ - unsigned int led_3ActivityStretch : 2; /* 1E.C433.1:0 R/WPD Provisionable Default = 0x3 */ - /* [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - */ - /*! \brief 1E.C433.2 R/WPD LED #3 Transmit Activity - AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3TransmitActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on transmit activity - - */ - unsigned int led_3TransmitActivity : 1; /* 1E.C433.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on transmit activity - */ - /*! \brief 1E.C433.3 R/WPD LED #3 Receive Activity - AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3ReceiveActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on receive activity - - */ - unsigned int led_3ReceiveActivity : 1; /* 1E.C433.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on receive activity - */ - /*! \brief 1E.C433.4 R/WPD LED #3 Connecting - AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3Connecting - - Provisionable Default = 0x0 - - 1 = LED is on when attempting to connect. - - */ - unsigned int led_3Connecting : 1; /* 1E.C433.4 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when attempting to connect. - */ - /*! \brief 1E.C433.5 R/WPD LED #3 100 Mb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3_100Mb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 100 Mb/s - - */ - unsigned int led_3_100Mb_sLinkEstablished : 1; /* 1E.C433.5 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 100 Mb/s - */ - /*! \brief 1E.C433.6 R/WPD LED #3 1 Gb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3_1Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 1 Gb/s - - */ - unsigned int led_3_1Gb_sLinkEstablished : 1; /* 1E.C433.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 1 Gb/s - */ - /*! \brief 1E.C433.7 R/WPD LED #3 10 Gb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3_10Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 10 Gb/s - - */ - unsigned int led_3_10Gb_sLinkEstablished : 1; /* 1E.C433.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 10 Gb/s - */ - /*! \brief 1E.C433.8 R/WPD LED #3 Manual Set - AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3ManualSet - - Provisionable Default = 0x0 - - 1 = LED On - - */ - unsigned int led_3ManualSet : 1; /* 1E.C433.8 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED On - */ - unsigned int reserved0 : 7; - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of Global LED Provisioning */ - union - { - struct - { - /*! \brief 1E.C434.1:0 R/WPD LED #4 Activity Stretch [1:0] - AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4ActivityStretch - - Provisionable Default = 0x3 - - [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - - */ - unsigned int led_4ActivityStretch : 2; /* 1E.C434.1:0 R/WPD Provisionable Default = 0x3 */ - /* [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - */ - /*! \brief 1E.C434.2 R/WPD LED #4 Transmit Activity - AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4TransmitActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on transmit activity - - */ - unsigned int led_4TransmitActivity : 1; /* 1E.C434.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on transmit activity - */ - /*! \brief 1E.C434.3 R/WPD LED #4 Receive Activity - AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4ReceiveActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on receive activity - - */ - unsigned int led_4ReceiveActivity : 1; /* 1E.C434.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on receive activity - */ - /*! \brief 1E.C434.4 R/WPD LED #4 Connecting - AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4Connecting - - Provisionable Default = 0x0 - - 1 = LED is on when attempting to connect. - - */ - unsigned int led_4Connecting : 1; /* 1E.C434.4 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when attempting to connect. - */ - /*! \brief 1E.C434.5 R/WPD LED #4 100 Mb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4_100Mb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 100 Mb/s - - */ - unsigned int led_4_100Mb_sLinkEstablished : 1; /* 1E.C434.5 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 100 Mb/s - */ - /*! \brief 1E.C434.6 R/WPD LED #4 1 Gb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4_1Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 1 Gb/s - - */ - unsigned int led_4_1Gb_sLinkEstablished : 1; /* 1E.C434.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 1 Gb/s - */ - /*! \brief 1E.C434.7 R/WPD LED #4 10 Gb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4_10Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 10 Gb/s - - */ - unsigned int led_4_10Gb_sLinkEstablished : 1; /* 1E.C434.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 10 Gb/s - */ - /*! \brief 1E.C434.8 R/WPD LED #4 Manual Set - AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4ManualSet - - Provisionable Default = 0x0 - - 1 = LED On - - */ - unsigned int led_4ManualSet : 1; /* 1E.C434.8 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED On - */ - unsigned int reserved0 : 7; - } bits_4; - uint16_t word_4; - } u4; - /*! \brief Union for bit and word level access of word 5 of Global LED Provisioning */ - union - { - struct - { - /*! \brief 1E.C435.1:0 R/WPD LED #5 Activity Stretch [1:0] - AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5ActivityStretch - - Provisionable Default = 0x3 - - [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - - */ - unsigned int led_5ActivityStretch : 2; /* 1E.C435.1:0 R/WPD Provisionable Default = 0x3 */ - /* [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - */ - /*! \brief 1E.C435.2 R/WPD LED #5 Transmit Activity - AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5TransmitActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on transmit activity - - */ - unsigned int led_5TransmitActivity : 1; /* 1E.C435.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on transmit activity - */ - /*! \brief 1E.C435.3 R/WPD LED #5 Receive Activity - AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5ReceiveActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on receive activity - - */ - unsigned int led_5ReceiveActivity : 1; /* 1E.C435.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on receive activity - */ - /*! \brief 1E.C435.4 R/WPD LED #5 Connecting - AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5Connecting - - Provisionable Default = 0x0 - - 1 = LED is on when attempting to connect. - - */ - unsigned int led_5Connecting : 1; /* 1E.C435.4 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when attempting to connect. - */ - /*! \brief 1E.C435.5 R/WPD LED #5 100 Mb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5_100Mb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 100 Mb/s - - */ - unsigned int led_5_100Mb_sLinkEstablished : 1; /* 1E.C435.5 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 100 Mb/s - */ - /*! \brief 1E.C435.6 R/WPD LED #5 1 Gb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5_1Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 1 Gb/s - - */ - unsigned int led_5_1Gb_sLinkEstablished : 1; /* 1E.C435.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 1 Gb/s - */ - /*! \brief 1E.C435.7 R/WPD LED #5 10 Gb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5_10Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 10 Gb/s - - */ - unsigned int led_5_10Gb_sLinkEstablished : 1; /* 1E.C435.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 10 Gb/s - */ - /*! \brief 1E.C435.8 R/WPD LED #5 Manual Set - AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5ManualSet - - Provisionable Default = 0x0 - - 1 = LED On - - */ - unsigned int led_5ManualSet : 1; /* 1E.C435.8 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED On - */ - unsigned int reserved0 : 7; - } bits_5; - uint16_t word_5; - } u5; - /*! \brief Union for bit and word level access of word 6 of Global LED Provisioning */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_6; - uint16_t word_6; - } u6; - /*! \brief Union for bit and word level access of word 7 of Global LED Provisioning */ - union - { - struct - { - /*! \brief 1E.C437.0 R/WPD LED Operation Mode - AQ_GlobalLedProvisioning_APPIA.u7.bits_7.ledOperationMode - - Provisionable Default = 0x0 - - 1 = LED link activity in Mode #2 - 0 = LED link activity in classic mode - - - Notes: - When set to 1, the LED blinking rate is based on Mode #2 algorithm. When set to 0, the LED blinking rate is based on the classic algorithm. */ - unsigned int ledOperationMode : 1; /* 1E.C437.0 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED link activity in Mode #2 - 0 = LED link activity in classic mode - */ - unsigned int reserved0 : 15; - } bits_7; - uint16_t word_7; - } u7; - /*! \brief Union for bit and word level access of word 8 of Global LED Provisioning */ - union - { - struct - { - /*! \brief 1E.C438.0 R/WPD LED #0 Manual Active Select - AQ_GlobalLedProvisioning_APPIA.u8.bits_8.led_0ManualActiveSelect - - Provisionable Default = 0x0 - - 1 = Manual selection of LED active high or low - 0 = Determine the active high or low based on the external pull-up or pull-down - - */ - unsigned int led_0ManualActiveSelect : 1; /* 1E.C438.0 R/WPD Provisionable Default = 0x0 */ - /* 1 = Manual selection of LED active high or low - 0 = Determine the active high or low based on the external pull-up or pull-down - */ - /*! \brief 1E.C438.1 R/WPD LED #0 Active High Select - AQ_GlobalLedProvisioning_APPIA.u8.bits_8.led_0ActiveHighSelect - - Provisionable Default = 0x0 - - 1 = LED active high - 0 = LED active low - - - Notes: - The See LED #0 Manual Active Select bit must be 1 for this bit to take affect. */ - unsigned int led_0ActiveHighSelect : 1; /* 1E.C438.1 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED active high - 0 = LED active low - */ - /*! \brief 1E.C438.2 R/WPD LED #0 Drive Three State Select - AQ_GlobalLedProvisioning_APPIA.u8.bits_8.led_0DriveThreeStateSelect - - Provisionable Default = 0x0 - - 1 = Drive LED tri-state when not active - 0 = Drive LED opposite of active level when not active - - */ - unsigned int led_0DriveThreeStateSelect : 1; /* 1E.C438.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = Drive LED tri-state when not active - 0 = Drive LED opposite of active level when not active - */ - unsigned int reserved0 : 13; - } bits_8; - uint16_t word_8; - } u8; - /*! \brief Union for bit and word level access of word 9 of Global LED Provisioning */ - union - { - struct - { - /*! \brief 1E.C439.0 R/WPD LED #1 Manual Active Select - AQ_GlobalLedProvisioning_APPIA.u9.bits_9.led_1ManualActiveSelect - - Provisionable Default = 0x0 - - 1 = Manual selection of LED active high or low - 0 = Determine the active high or low based on the external pull-up or pull-down - - */ - unsigned int led_1ManualActiveSelect : 1; /* 1E.C439.0 R/WPD Provisionable Default = 0x0 */ - /* 1 = Manual selection of LED active high or low - 0 = Determine the active high or low based on the external pull-up or pull-down - */ - /*! \brief 1E.C439.1 R/WPD LED #1 Active High Select - AQ_GlobalLedProvisioning_APPIA.u9.bits_9.led_1ActiveHighSelect - - Provisionable Default = 0x0 - - 1 = LED active high - 0 = LED active low - - - Notes: - The See LED #1 Manual Active Select bit must be 1 for this bit to take affect. */ - unsigned int led_1ActiveHighSelect : 1; /* 1E.C439.1 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED active high - 0 = LED active low - */ - /*! \brief 1E.C439.2 R/WPD LED #1 Drive Three State Select - AQ_GlobalLedProvisioning_APPIA.u9.bits_9.led_1DriveThreeStateSelect - - Provisionable Default = 0x0 - - 1 = Drive LED tri-state when not active - 0 = Drive LED opposite of active level when not active - - */ - unsigned int led_1DriveThreeStateSelect : 1; /* 1E.C439.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = Drive LED tri-state when not active - 0 = Drive LED opposite of active level when not active - */ - unsigned int reserved0 : 13; - } bits_9; - uint16_t word_9; - } u9; - /*! \brief Union for bit and word level access of word 10 of Global LED Provisioning */ - union - { - struct - { - /*! \brief 1E.C43A.0 R/WPD LED #2 Manual Active Select - AQ_GlobalLedProvisioning_APPIA.u10.bits_10.led_2ManualActiveSelect - - Provisionable Default = 0x0 - - 1 = Manual selection of LED active high or low - 0 = Determine the active high or low based on the external pull-up or pull-down - - */ - unsigned int led_2ManualActiveSelect : 1; /* 1E.C43A.0 R/WPD Provisionable Default = 0x0 */ - /* 1 = Manual selection of LED active high or low - 0 = Determine the active high or low based on the external pull-up or pull-down - */ - /*! \brief 1E.C43A.1 R/WPD LED #2 Active High Select - AQ_GlobalLedProvisioning_APPIA.u10.bits_10.led_2ActiveHighSelect - - Provisionable Default = 0x0 - - 1 = LED active high - 0 = LED active low - - - Notes: - The See LED #2 Manual Active Select bit must be 1 for this bit to take affect. */ - unsigned int led_2ActiveHighSelect : 1; /* 1E.C43A.1 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED active high - 0 = LED active low - */ - /*! \brief 1E.C43A.2 R/WPD LED #2 Drive Three State Select - AQ_GlobalLedProvisioning_APPIA.u10.bits_10.led_2DriveThreeStateSelect - - Provisionable Default = 0x0 - - 1 = Drive LED tri-state when not active - 0 = Drive LED opposite of active level when not active - - */ - unsigned int led_2DriveThreeStateSelect : 1; /* 1E.C43A.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = Drive LED tri-state when not active - 0 = Drive LED opposite of active level when not active - */ - unsigned int reserved0 : 13; - } bits_10; - uint16_t word_10; - } u10; - /*! \brief Union for bit and word level access of word 11 of Global LED Provisioning */ - union - { - struct - { - /*! \brief 1E.C43B.0 R/WPD LED #3 Manual Active Select - AQ_GlobalLedProvisioning_APPIA.u11.bits_11.led_3ManualActiveSelect - - Provisionable Default = 0x0 - - 1 = Manual selection of LED active high or low - 0 = Determine the active high or low based on the external pull-up or pull-down - - */ - unsigned int led_3ManualActiveSelect : 1; /* 1E.C43B.0 R/WPD Provisionable Default = 0x0 */ - /* 1 = Manual selection of LED active high or low - 0 = Determine the active high or low based on the external pull-up or pull-down - */ - /*! \brief 1E.C43B.1 R/WPD LED #3 Active High Select - AQ_GlobalLedProvisioning_APPIA.u11.bits_11.led_3ActiveHighSelect - - Provisionable Default = 0x0 - - 1 = LED active high - 0 = LED active low - - - Notes: - The See LED #3 Manual Active Select bit must be 1 for this bit to take affect. */ - unsigned int led_3ActiveHighSelect : 1; /* 1E.C43B.1 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED active high - 0 = LED active low - */ - /*! \brief 1E.C43B.2 R/WPD LED #3 Drive Three State Select - AQ_GlobalLedProvisioning_APPIA.u11.bits_11.led_3DriveThreeStateSelect - - Provisionable Default = 0x0 - - 1 = Drive LED tri-state when not active - 0 = Drive LED opposite of active level when not active - - */ - unsigned int led_3DriveThreeStateSelect : 1; /* 1E.C43B.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = Drive LED tri-state when not active - 0 = Drive LED opposite of active level when not active - */ - unsigned int reserved0 : 13; - } bits_11; - uint16_t word_11; - } u11; - /*! \brief Union for bit and word level access of word 12 of Global LED Provisioning */ - union - { - struct - { - /*! \brief 1E.C43C.0 R/WPD LED #4 Manual Active Select - AQ_GlobalLedProvisioning_APPIA.u12.bits_12.led_4ManualActiveSelect - - Provisionable Default = 0x0 - - 1 = Manual selection of LED active high or low - 0 = Determine the active high or low based on the external pull-up or pull-down - - */ - unsigned int led_4ManualActiveSelect : 1; /* 1E.C43C.0 R/WPD Provisionable Default = 0x0 */ - /* 1 = Manual selection of LED active high or low - 0 = Determine the active high or low based on the external pull-up or pull-down - */ - /*! \brief 1E.C43C.1 R/WPD LED #4 Active High Select - AQ_GlobalLedProvisioning_APPIA.u12.bits_12.led_4ActiveHighSelect - - Provisionable Default = 0x0 - - 1 = LED active high - 0 = LED active low - - - Notes: - The See LED #4 Manual Active Select bit must be 1 for this bit to take affect. */ - unsigned int led_4ActiveHighSelect : 1; /* 1E.C43C.1 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED active high - 0 = LED active low - */ - /*! \brief 1E.C43C.2 R/WPD LED #4 Drive Three State Select - AQ_GlobalLedProvisioning_APPIA.u12.bits_12.led_4DriveThreeStateSelect - - Provisionable Default = 0x0 - - 1 = Drive LED tri-state when not active - 0 = Drive LED opposite of active level when not active - - */ - unsigned int led_4DriveThreeStateSelect : 1; /* 1E.C43C.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = Drive LED tri-state when not active - 0 = Drive LED opposite of active level when not active - */ - unsigned int reserved0 : 13; - } bits_12; - uint16_t word_12; - } u12; - /*! \brief Union for bit and word level access of word 13 of Global LED Provisioning */ - union - { - struct - { - /*! \brief 1E.C43D.0 R/WPD LED #5 Manual Active Select - AQ_GlobalLedProvisioning_APPIA.u13.bits_13.led_5ManualActiveSelect - - Provisionable Default = 0x0 - - 1 = Manual selection of LED active high or low - 0 = Determine the active high or low based on the external pull-up or pull-down - - */ - unsigned int led_5ManualActiveSelect : 1; /* 1E.C43D.0 R/WPD Provisionable Default = 0x0 */ - /* 1 = Manual selection of LED active high or low - 0 = Determine the active high or low based on the external pull-up or pull-down - */ - /*! \brief 1E.C43D.1 R/WPD LED #5 Active High Select - AQ_GlobalLedProvisioning_APPIA.u13.bits_13.led_5ActiveHighSelect - - Provisionable Default = 0x0 - - 1 = LED active high - 0 = LED active low - - - Notes: - The See LED #5 Manual Active Select bit must be 1 for this bit to take affect. */ - unsigned int led_5ActiveHighSelect : 1; /* 1E.C43D.1 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED active high - 0 = LED active low - */ - /*! \brief 1E.C43D.2 R/WPD LED #5 Drive Three State Select - AQ_GlobalLedProvisioning_APPIA.u13.bits_13.led_5DriveThreeStateSelect - - Provisionable Default = 0x0 - - 1 = Drive LED tri-state when not active - 0 = Drive LED opposite of active level when not active - - */ - unsigned int led_5DriveThreeStateSelect : 1; /* 1E.C43D.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = Drive LED tri-state when not active - 0 = Drive LED opposite of active level when not active - */ - unsigned int reserved0 : 13; - } bits_13; - uint16_t word_13; - } u13; -} AQ_GlobalLedProvisioning_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global General Provisioning: 1E.C440 */ -/* Global General Provisioning: 1E.C440 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global General Provisioning */ - union - { - struct - { - /*! \brief 1E.C440.0 RO Gang Load MDIO Write Only - AQ_GlobalGeneralProvisioning_APPIA.u0.bits_0.gangLoadMdioWriteOnly - - - - 1 = MDIO gang load enable - - - Notes: - This bit enables gang load operation with the address specified in Bits 8:4. */ - unsigned int gangLoadMdioWriteOnly : 1; /* 1E.C440.0 RO */ - /* 1 = MDIO gang load enable - */ - unsigned int reserved1 : 3; - /*! \brief 1E.C440.8:4 R/WPD Gang Load MDIO Address [4:0] - AQ_GlobalGeneralProvisioning_APPIA.u0.bits_0.gangLoadMdioAddress - - Provisionable Default = 0x00 - - MDIO Address to be used during gang load operation - - - Notes: - Gang load operation is used to load data into multiple PHYs all connected to the same MDIO bus. The address for gang load operation is provided by these bits (8:4), and enabling is done by writing Bit 0. Disabling of gang load mode is done by writing the See MDIO Address Reset (1E.C441.2) bit. These will revert the PHY's MDIO address back to the address provided by the MDIO Address pins. During gang load operation, MDIO reads are disabled to prevent bus contention. */ - unsigned int gangLoadMdioAddress : 5; /* 1E.C440.8:4 R/WPD Provisionable Default = 0x00 */ - /* MDIO Address to be used during gang load operation - */ - unsigned int reserved0 : 7; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global General Provisioning */ - union - { - struct - { - unsigned int reserved2 : 2; - /*! \brief 1E.C441.2 R/WSC MDIO Address Reset - AQ_GlobalGeneralProvisioning_APPIA.u1.bits_1.mdioAddressReset - - Default = 0x0 - - 1 = Load MDIO Address with the address on the MDIO address pins - - - Notes: - Used to reset the address after gang load and enable MDIO reads again. */ - unsigned int mdioAddressReset : 1; /* 1E.C441.2 R/WSC Default = 0x0 */ - /* 1 = Load MDIO Address with the address on the MDIO address pins - */ - /*! \brief 1E.C441.3 R/WPD MDIO Preamble Detection Disable - AQ_GlobalGeneralProvisioning_APPIA.u1.bits_1.mdioPreambleDetectionDisable - - Provisionable Default = 0x0 - - 1 = Suppress preamble detection on MDIO - 0 = Enable preamble detection on MDIO - - */ - unsigned int mdioPreambleDetectionDisable : 1; /* 1E.C441.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = Suppress preamble detection on MDIO - 0 = Enable preamble detection on MDIO - */ - /*! \brief 1E.C441.4 R/WPD MDIO Drive Configuration - AQ_GlobalGeneralProvisioning_APPIA.u1.bits_1.mdioDriveConfiguration - - Provisionable Default = 0x0 - - 0 = MDIO driver is in normal mode - 1 = MDIO driver is in open drain mode - - - Notes: - When the MDIO driver is in open drain mode during a read cycle, "0" data will be actively driven out of the MDIO, "1" data will set the MDIO driver in high impedance state and an external pullup will set the MDIO line to "1". The Turn-Around "0" will also be actively driven out of the MDIO, therefore in open drain mode, the Turn-Around is still "Z0". */ - unsigned int mdioDriveConfiguration : 1; /* 1E.C441.4 R/WPD Provisionable Default = 0x0 */ - /* 0 = MDIO driver is in normal mode - 1 = MDIO driver is in open drain mode - */ - unsigned int reserved1 : 8; - /*! \brief 1E.C441.D R/WPD MDIO Read MSW First Enable - AQ_GlobalGeneralProvisioning_APPIA.u1.bits_1.mdioReadMSW_FirstEnable - - Provisionable Default = 0x0 - - 1 = MSW of counter must be read first - 0 = LSW of counter must be read first - - - Notes: - This bit configures whether the MSW or LSW must be read first for counters greater than 16 bits. */ - unsigned int mdioReadMSW_FirstEnable : 1; /* 1E.C441.D R/WPD Provisionable Default = 0x0 */ - /* 1 = MSW of counter must be read first - 0 = LSW of counter must be read first - */ - /*! \brief 1E.C441.E R/WPD MDIO Broadcast Mode Enable - AQ_GlobalGeneralProvisioning_APPIA.u1.bits_1.mdioBroadcastModeEnable - - Provisionable Default = 0x0 - - 1 = Enable broadcast on Address 0 - 0 = Disable broadcast on Address 0 - - - Notes: - When set, this bit enables gang-load operation on address zero, simultaneous with normal MDIO operation. Obviously, this requires that no PHY use address 0 as its normal operating address. As well, reads on MDIO Address 0 are disabled to prevent bus contention. */ - unsigned int mdioBroadcastModeEnable : 1; /* 1E.C441.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable broadcast on Address 0 - 0 = Disable broadcast on Address 0 - */ - unsigned int reserved0 : 1; - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global General Provisioning */ - union - { - struct - { - /*! \brief 1E.C442.0 R/W Daisy Chain Reset - AQ_GlobalGeneralProvisioning_APPIA.u2.bits_2.daisyChainReset - - Default = 0x0 - - 1 = Reset the daisy chain - - - Notes: - Toggling this bit from 0 to 1 will reload the IRAM and DRAM and reset the uP. The uP will be in uP run stall during the reload process. After the reload process, uP run stall will be de-asserted adn the uP reset will be asserted. Note that before setting this bit, the See Soft Reset bit needs to be de-asserted. */ - unsigned int daisyChainReset : 1; /* 1E.C442.0 R/W Default = 0x0 */ - /* 1 = Reset the daisy chain - */ - unsigned int reserved0 : 15; - } bits_2; - uint16_t word_2; - } u2; -} AQ_GlobalGeneralProvisioning_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global NVR Provisioning: 1E.C450 */ -/* Global NVR Provisioning: 1E.C450 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global NVR Provisioning */ - union - { - struct - { - /*! \brief 1E.C450.1:0 R/WPD NVR Address Length [1:0] - AQ_GlobalNvrProvisioning_APPIA.u0.bits_0.nvrAddressLength - - Provisionable Default = 0x2 - - NVR address length ranges from 0 bytes up to 3 bytes. - - - Notes: - This sets the length of the address field used in read and write operations. Use of this field is enabled via Bit 8 of See Global NVR Provisioning 2: Address 1E.C451 . - */ - unsigned int nvrAddressLength : 2; /* 1E.C450.1:0 R/WPD Provisionable Default = 0x2 */ - /* NVR address length ranges from 0 bytes up to 3 bytes. - */ - unsigned int reserved2 : 2; - /*! \brief 1E.C450.6:4 R/WPD NVR Dummy Length [2:0] - AQ_GlobalNvrProvisioning_APPIA.u0.bits_0.nvrDummyLength - - Provisionable Default = 0x0 - - NVR dummy length ranges from 0 bytes to 4 bytes. - - - Notes: - This sets the length of the dummy field used in some maunfacturer's read status and write status operations. - */ - unsigned int nvrDummyLength : 3; /* 1E.C450.6:4 R/WPD Provisionable Default = 0x0 */ - /* NVR dummy length ranges from 0 bytes to 4 bytes. - */ - unsigned int reserved1 : 1; - /*! \brief 1E.C450.A:8 R/WPD NVR Data Length [2:0] - AQ_GlobalNvrProvisioning_APPIA.u0.bits_0.nvrDataLength - - Provisionable Default = 0x4 - - NVR data length ranges from 0 bytes to 4 bytes - - - Notes: - This sets the length of the data burst used in read and write operations. - */ - unsigned int nvrDataLength : 3; /* 1E.C450.A:8 R/WPD Provisionable Default = 0x4 */ - /* NVR data length ranges from 0 bytes to 4 bytes - */ - unsigned int reserved0 : 5; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global NVR Provisioning */ - union - { - struct - { - /*! \brief 1E.C451.7:0 R/WPD NVR Clock Divide [7:0] - AQ_GlobalNvrProvisioning_APPIA.u1.bits_1.nvrClockDivide - - Provisionable Default = 0xA0 - - NVR clock divide. Clock frequency is divided by the NVR clock divide + 1 - - */ - unsigned int nvrClockDivide : 8; /* 1E.C451.7:0 R/WPD Provisionable Default = 0xA0 */ - /* NVR clock divide. Clock frequency is divided by the NVR clock divide + 1 - */ - /*! \brief 1E.C451.8 R/WPD NVR Address Length Override - AQ_GlobalNvrProvisioning_APPIA.u1.bits_1.nvrAddressLengthOverride - - Provisionable Default = 0x0 - - 0 = NVR address length is based on the "NVR_SIZE" pin. - 1 = NVR address length is based on the See NVR Address Length [1:0] register. - - - Notes: - When the this bit = 0 and NVR_SIZE pin = 0, the NVR address length is 2 bytes. When this bit = 0 and the NVR_SIZE pin = 1, the NVR address length is 3 bytes. When this bit = 1 the NVR address length is from the See NVR Address Length [1:0] */ - unsigned int nvrAddressLengthOverride : 1; /* 1E.C451.8 R/WPD Provisionable Default = 0x0 */ - /* 0 = NVR address length is based on the "NVR_SIZE" pin. - 1 = NVR address length is based on the See NVR Address Length [1:0] register. - */ - unsigned int reserved0 : 7; - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global NVR Provisioning */ - union - { - struct - { - /*! \brief 1E.C452.0 R/W NVR Daisy Chain Disable - AQ_GlobalNvrProvisioning_APPIA.u2.bits_2.nvrDaisyChainDisable - - Default = 0x0 - - 1 = Disable the Daisy Chain - - - Notes: - When in daisy chain master mode, the daisy chain and MDIO can both access the SPI. Setting this bit to 1 will disable the dasiy chain from accessing the SPI and force it into a reset state. */ - unsigned int nvrDaisyChainDisable : 1; /* 1E.C452.0 R/W Default = 0x0 */ - /* 1 = Disable the Daisy Chain - */ - /*! \brief 1E.C452.1 R/W NVR Daisy Chain Clock Divide Override - AQ_GlobalNvrProvisioning_APPIA.u2.bits_2.nvrDaisyChainClockDivideOverride - - Default = 0x0 - - 1 = Override NVR clock divide when in daisy chain master mode - - - - Notes: - When in daisy chain master mode, the clock divide configuration is received from the flash. This bit will override the clock divide configuration from the flash with the See NVR Clock Divide [7:0] . */ - unsigned int nvrDaisyChainClockDivideOverride : 1; /* 1E.C452.1 R/W Default = 0x0 */ - /* 1 = Override NVR clock divide when in daisy chain master mode - - */ - unsigned int reserved0 : 14; - } bits_2; - uint16_t word_2; - } u2; -} AQ_GlobalNvrProvisioning_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Reserved Provisioning: 1E.C470 */ -/* Global Reserved Provisioning: 1E.C470 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Reserved Provisioning */ - union - { - struct - { - unsigned int reserved2 : 4; - /*! \brief 1E.C470.4 R/WSC Initiate Cable Diagnostics - AQ_GlobalReservedProvisioning_APPIA.u0.bits_0.initiateCableDiagnostics - - Default = 0x0 - - 1 = Perform cable diagnostics - - - Notes: - Perform cable diagnostics regardless of link state. If link is up, setting this bit will cause the link to drop while diagnostics are performed. This bit is self-clearing upon completion of the cable diagnostics. Further MDIO writes should be avoided until this bit has self-cleared, indicating completion of the diagnostic routine. */ - unsigned int initiateCableDiagnostics : 1; /* 1E.C470.4 R/WSC Default = 0x0 */ - /* 1 = Perform cable diagnostics - */ - /*! \brief 1E.C470.5 R/WSC Initiate Component Diagnostics - AQ_GlobalReservedProvisioning_APPIA.u0.bits_0.initiateComponentDiagnostics - - Default = 0x0 - - 1 = Perform component diagnostics - - - Notes: - Perform component diagnostics regardless of link state. If link is up, setting this bit will cause the link to drop while diagnostics are performed. This bit is self-clearing upon completion of the component diagnostics. Further MDIO writes should be avoided until this bit has self-cleared, indicating completion of the diagnostic routine. */ - unsigned int initiateComponentDiagnostics : 1; /* 1E.C470.5 R/WSC Default = 0x0 */ - /* 1 = Perform component diagnostics - */ - unsigned int reserved1 : 2; - unsigned int reserved0 : 5; - /*! \brief 1E.C470.E:D R/WPD Extended MDI Diagnostics Select [1:0] - AQ_GlobalReservedProvisioning_APPIA.u0.bits_0.extendedMdiDiagnosticsSelect - - Provisionable Default = 0x0 - - 0x0 = TDR Data - 0x1 = RFI Channel PSD - 0x2 = Noise PSD while the local Tx is Off - 0x3 = Noise PSD while the local Tx is On - - - Notes: - These bits select what sort of cable diagnostics to perform. For regular cable diagnostics, Bit F is set to zero, and the diagnostics are triggered by setting Bit 4. For extended diagnostics, Bit F is set to 1, and the desired extended diagnostics are selected by Bits E:D. The routine is then triggered by setting Bit 4. Each of the extended diagnostic routines present data for all for MDI pairs (A, B, C, D) consecutively, and after the data for each channel is gathered Bits F:D are reset. To get the data for the next pair, Bits F:D must be set back to the desired value (which must be the same as the initial channel). This continues until the data for all channels has been gathered. The address in memory where the data is stored is given in 1E.C802 and 1E.C804. - - For the case of PSD, the structure is as follows: - Int32 info - Int16 data[Len] - Info = Len << 16 | TxEnable << 8 | Pair (0 = A, etc.) - - For TDR: - Int32 info - Int16 tdr_A[Len] - Int16 tdr_B[Len] - Int16 tdr_C[Len] - Int16 tdr_D[Len] - - Info = Len << 16 | Channel - - TDR data is from the current pair to all other pairs. - - At the end of retrieving extended MDI diag data, the part will be reset. Conversly the only way to exit this routine once it starts is to issue a PMA reset. */ - unsigned int extendedMdiDiagnosticsSelect : 2; /* 1E.C470.E:D R/WPD Provisionable Default = 0x0 */ - /* 0x0 = TDR Data - 0x1 = RFI Channel PSD - 0x2 = Noise PSD while the local Tx is Off - 0x3 = Noise PSD while the local Tx is On - */ - /*! \brief 1E.C470.F R/WPD Diagnostics Select - AQ_GlobalReservedProvisioning_APPIA.u0.bits_0.diagnosticsSelect - - Provisionable Default = 0x0 - - 1 = Provide Extended MDI Diagnostics Information. - 0 = Provide normal cable diagnostics - - - Notes: - These bits select what sort of cable diagnostics to perform. For regular cable diagnostics, Bit F is set to zero, and the diagnostics are triggered by setting Bit 4. For extended diagnostics, Bit F is set to 1, and the desired extended diagnostics are selected by Bits E:D. The routine is then triggered by setting Bit 4. Each of the extended diagnostic routines present data for all for MDI pairs (A, B, C, D) consecutively, and after the data for each channel is gathered Bits F:D are reset. To get the data for the next pair, Bits F:D must be set back to the desired value (which must be the same as the initial channel). This continues until the data for all channels has been gathered. The address in memory where the data is stored is given in 1E.C802 and 1E.C804. - - For the case of PSD, the structure is as follows: - Int32 info - Int16 data[Len] - Info = Len << 16 | TxEnable << 8 | Pair (0 = A, etc.) - - For TDR: - Int32 info - Int16 tdr_A[Len] - Int16 tdr_B[Len] - Int16 tdr_C[Len] - Int16 tdr_D[Len] - - Info = Len << 16 | Channel - - TDR data is from the current pair to all other pairs. - - At the end of retrieving extended MDI diag data, the part will be reset. Conversly the only way to exit this routine once it starts is to issue a PMA reset. */ - unsigned int diagnosticsSelect : 1; /* 1E.C470.F R/WPD Provisionable Default = 0x0 */ - /* 1 = Provide Extended MDI Diagnostics Information. - 0 = Provide normal cable diagnostics - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Reserved Provisioning */ - union - { - struct - { - /*! \brief 1E.C471.5:0 R/WuP Daisy-Chain Hop-Count Override Value [5:0] - AQ_GlobalReservedProvisioning_APPIA.u1.bits_1.daisy_chainHop_countOverrideValue - - Default = 0x00 - - The value to use for the PHY's daisy-chain hop-count. Valid values are from 0 -> 47 - - - Notes: - Daisy-Chain Hop-Count Override should be used during MDIO boot-load operation, as the daisy-chain hop-count does not function when the daisy-chain is disabled (1E.C452.0). Setting this bit tells the processor where in the diasy-chain it is, so that the provisioning operation will function correctly. */ - unsigned int daisy_chainHop_countOverrideValue : 6; /* 1E.C471.5:0 R/WuP Default = 0x00 */ - /* The value to use for the PHY's daisy-chain hop-count. Valid values are from 0 -> 47 - */ - /*! \brief 1E.C471.6 R/WuP Enable Daisy-Chain Hop-Count Override - AQ_GlobalReservedProvisioning_APPIA.u1.bits_1.enableDaisy_chainHop_countOverride - - Default = 0x0 - - 1 = Hop-count is set by Bits 5:0 - 0 = Hop-count is determined by the daisy-chain - - - Notes: - Daisy-Chain Hop-Count Override should be used during MDIO boot-load operation, as the daisy-chain hop-count does not function when the daisy-chain is disabled (1E.C452.0). Setting this bit tells the processor where in the diasy-chain it is, so that the provisioning operation will function correctly. */ - unsigned int enableDaisy_chainHop_countOverride : 1; /* 1E.C471.6 R/WuP Default = 0x0 */ - /* 1 = Hop-count is set by Bits 5:0 - 0 = Hop-count is determined by the daisy-chain - */ - /*! \brief 1E.C471.F:7 R/WPD Reserved Provisioning 2 [8:0] - AQ_GlobalReservedProvisioning_APPIA.u1.bits_1.reservedProvisioning_2 - - Provisionable Default = 0x000 - - Reserved for future use - - */ - unsigned int reservedProvisioning_2 : 9; /* 1E.C471.F:7 R/WPD Provisionable Default = 0x000 */ - /* Reserved for future use - */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global Reserved Provisioning */ - union - { - struct - { - /*! \brief 1E.C472.0 R/WPDuP Enable 5th Channel RFI Cancellation - AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.enable_5thChannelRfiCancellation - - Provisionable Default = 0x0 - - 1 = 5th channel and RFI cancellers operation enabled - 0 = 5th channel AFE is powered down, 5th channel digital is clock gated, RFI cancellers are disabled - - - Notes: - Note: The value of this bit at the time of Autonegotiation sets the local PHY behavior until the next time Autonegotiation occurs. */ - unsigned int enable_5thChannelRfiCancellation : 1; /* 1E.C472.0 R/WPDuP Provisionable Default = 0x0 */ - /* 1 = 5th channel and RFI cancellers operation enabled - 0 = 5th channel AFE is powered down, 5th channel digital is clock gated, RFI cancellers are disabled - */ - /*! \brief 1E.C472.1 R/WPDuP Enable XENPAK Register Space - AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.enableXenpakRegisterSpace - - Provisionable Default = 0x0 - - 1 = XENPAK register space enabled - 0 = XENPAK register space disabled - - */ - unsigned int enableXenpakRegisterSpace : 1; /* 1E.C472.1 R/WPDuP Provisionable Default = 0x0 */ - /* 1 = XENPAK register space enabled - 0 = XENPAK register space disabled - */ - unsigned int reserved1 : 4; - /*! \brief 1E.C472.6 R/WPD Tunable External VDD Power Supply Present - AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.tunableExternalVddPowerSupplyPresent - - Provisionable Default = 0x0 - - 1 = Tunable external VDD power supply present - 0 = No tunable external VDD power supply present - - - Notes: - - - - These bits must be set if tuning of external power supplies is desired (see Bits 7:6) */ - unsigned int tunableExternalVddPowerSupplyPresent : 1; /* 1E.C472.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = Tunable external VDD power supply present - 0 = No tunable external VDD power supply present - */ - /*! \brief 1E.C472.7 R/WPD Tunable External LVDD Power Supply Present - AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.tunableExternalLvddPowerSupplyPresent - - Provisionable Default = 0x0 - - 1 = Tunable external LVDD power supply present - 0 = No tunable external LVDD power supply present - - - Notes: - - - - These bits must be set if tuning of external power supplies is desired (see Bits 7:6) */ - unsigned int tunableExternalLvddPowerSupplyPresent : 1; /* 1E.C472.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = Tunable external LVDD power supply present - 0 = No tunable external LVDD power supply present - */ - unsigned int reserved0 : 6; - /*! \brief 1E.C472.E R/WPD Enable VDD Power Supply Tuning - AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.enableVddPowerSupplyTuning - - Provisionable Default = 0x0 - - 1 = Enable external VDD power supply tuning - 0 = Disable external VDD power supply tuning is disabled - - - Notes: - - - - These bits control whether the PHY attempts to tune the external VDD and LVDD power supplies via the PMBus. These bits are only operational if the external supplies are present (see Bits 7:6) */ - unsigned int enableVddPowerSupplyTuning : 1; /* 1E.C472.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable external VDD power supply tuning - 0 = Disable external VDD power supply tuning is disabled - */ - /*! \brief 1E.C472.F R/WPD Enable LVDD Power Supply Tuning - AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.enableLvddPowerSupplyTuning - - Provisionable Default = 0x0 - - 1 = Enable external LVDD power supply tuning - 0 = Disable external LVDD power supply tuning is disabled - - - Notes: - - - - These bits control whether the PHY attempts to tune the external VDD and LVDD power supplies via the PMBus. These bits are only operational if the external supplies are present (see Bits 7:6) */ - unsigned int enableLvddPowerSupplyTuning : 1; /* 1E.C472.F R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable external LVDD power supply tuning - 0 = Disable external LVDD power supply tuning is disabled - */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global Reserved Provisioning */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of Global Reserved Provisioning */ - union - { - struct - { - /*! \brief 1E.C474.7:0 R/WPD Training SNR [7:0] - AQ_GlobalReservedProvisioning_APPIA.u4.bits_4.trainingSNR - - Provisionable Default = 0x00 - - SNR during 10G training on the worst channel. SNR is in steps of 0.1dB - - - Notes: - The SNR margin that is enjoyed by the worst channel, over and above the minimum SNR required to operate at a BER of 10-12. It is reported with 0.1 dB of resolution to an accuracy of 0.5 dB within the range of -12.7 dB to 12.7 dB. The number is in offset binary, with 0.0 dB represented by 0x8000. - */ - unsigned int trainingSNR : 8; /* 1E.C474.7:0 R/WPD Provisionable Default = 0x00 */ - /* SNR during 10G training on the worst channel. SNR is in steps of 0.1dB - */ - unsigned int reserved0 : 8; - } bits_4; - uint16_t word_4; - } u4; - /*! \brief Union for bit and word level access of word 5 of Global Reserved Provisioning */ - union - { - struct - { - unsigned int reserved1 : 2; - /*! \brief 1E.C475.2 R/WPD Smart Power-Down Enable - AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.smartPower_downEnable - - Provisionable Default = 0x0 - - 1 = Enable smart power down mode - 0 = Smart power-down mode disabled - - - Notes: - Smart power down (SPD) is the lowest power mode at which PHY is able to autonegotiate. SPD can be enabled with bit 1E.C475.2 */ - unsigned int smartPower_downEnable : 1; /* 1E.C475.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable smart power down mode - 0 = Smart power-down mode disabled - */ - /*! \brief 1E.C475.3 R/WPD Deadlock Avoidance Enable - AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.deadlockAvoidanceEnable - - Provisionable Default = 0x0 - - 1 = SPD with deadlock avoidance: PHY transmits autonegotiation pulses (FLPs) at a slower rate (~ 1 FLP/ 100ms) than specified by autonegotiation standard (~1 FLP / 8.25ms). Receiver is active and able to detect the pulses. - 0 = SPD without deadlock avoidance: PHY transmitter is shut down, no autonegotiation pulses are sent on the line but the receiver is active and able to detect the pulses - - */ - unsigned int deadlockAvoidanceEnable : 1; /* 1E.C475.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = SPD with deadlock avoidance: PHY transmits autonegotiation pulses (FLPs) at a slower rate (~ 1 FLP/ 100ms) than specified by autonegotiation standard (~1 FLP / 8.25ms). Receiver is active and able to detect the pulses. - 0 = SPD without deadlock avoidance: PHY transmitter is shut down, no autonegotiation pulses are sent on the line but the receiver is active and able to detect the pulses - */ - /*! \brief 1E.C475.4 R/WPD CFR Support - AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrSupport - - Provisionable Default = 0x0 - - 1 = Local PHY supports Cisco Fast Retrain - 0 = Local PHY does support Cisco Fast Retrain - - */ - unsigned int cfrSupport : 1; /* 1E.C475.4 R/WPD Provisionable Default = 0x0 */ - /* 1 = Local PHY supports Cisco Fast Retrain - 0 = Local PHY does support Cisco Fast Retrain - */ - /*! \brief 1E.C475.5 R/WPD CFR THP - AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrTHP - - Provisionable Default = 0x0 - - 1 = Local PHY requires local PHY to enable THP - 0 = Local PHY does not require local PHY to enable THP - - */ - unsigned int cfrTHP : 1; /* 1E.C475.5 R/WPD Provisionable Default = 0x0 */ - /* 1 = Local PHY requires local PHY to enable THP - 0 = Local PHY does not require local PHY to enable THP - */ - /*! \brief 1E.C475.6 R/WPD CFR Extended Maxwait - AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrExtendedMaxwait - - Provisionable Default = 0x0 - - 1 = Local PHY requires extended maxwait - 0 = Local PHY does not require extended maxwait - - */ - unsigned int cfrExtendedMaxwait : 1; /* 1E.C475.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = Local PHY requires extended maxwait - 0 = Local PHY does not require extended maxwait - */ - /*! \brief 1E.C475.7 R/WPD CFR Disable Timer - AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrDisableTimer - - Provisionable Default = 0x0 - - 1 = Local PHY requires cfr_disable timer - 0 = Local PHY does not require cfr_disable timer - - */ - unsigned int cfrDisableTimer : 1; /* 1E.C475.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = Local PHY requires cfr_disable timer - 0 = Local PHY does not require cfr_disable timer - */ - /*! \brief 1E.C475.8 R/WPD CFR LP Support - AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrLpSupport - - Provisionable Default = 0x0 - - 1 = Link partner supports Cisco Fast Retrain - 0 = Link partner does support Cisco Fast Retrain - - */ - unsigned int cfrLpSupport : 1; /* 1E.C475.8 R/WPD Provisionable Default = 0x0 */ - /* 1 = Link partner supports Cisco Fast Retrain - 0 = Link partner does support Cisco Fast Retrain - */ - /*! \brief 1E.C475.9 R/WPD CFR LP THP - AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrLpTHP - - Provisionable Default = 0x0 - - 1 = Link partner requires local PHY to enable THP - 0 = Link partner does not require local PHY to enable THP - - */ - unsigned int cfrLpTHP : 1; /* 1E.C475.9 R/WPD Provisionable Default = 0x0 */ - /* 1 = Link partner requires local PHY to enable THP - 0 = Link partner does not require local PHY to enable THP - */ - /*! \brief 1E.C475.A R/WPD CFR LP Extended Maxwait - AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrLpExtendedMaxwait - - Provisionable Default = 0x0 - - 1 = Link partner requires extended maxwait - 0 = Link partner does not require extended maxwait - - */ - unsigned int cfrLpExtendedMaxwait : 1; /* 1E.C475.A R/WPD Provisionable Default = 0x0 */ - /* 1 = Link partner requires extended maxwait - 0 = Link partner does not require extended maxwait - */ - /*! \brief 1E.C475.B R/WPD CFR LP Disable Timer - AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrLpDisableTimer - - Provisionable Default = 0x0 - - 1 = Link partner requires cfr_disable timer - 0 = Link partner does not require cfr_disable timer - - */ - unsigned int cfrLpDisableTimer : 1; /* 1E.C475.B R/WPD Provisionable Default = 0x0 */ - /* 1 = Link partner requires cfr_disable timer - 0 = Link partner does not require cfr_disable timer - */ - /*! \brief 1E.C475.C R/WPD Reserved Provisioning 6 - AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.reservedProvisioning_6 - - Provisionable Default = 0x0 - - Reserved for future use - - */ - unsigned int reservedProvisioning_6 : 1; /* 1E.C475.C R/WPD Provisionable Default = 0x0 */ - /* Reserved for future use - */ - /*! \brief 1E.C475.D R/WPD Smart Power-Down Status - AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.smartPower_downStatus - - Provisionable Default = 0x0 - - 1 = Smart Power-Down Active - 0 = Smart Power-Down Inactive - - */ - unsigned int smartPower_downStatus : 1; /* 1E.C475.D R/WPD Provisionable Default = 0x0 */ - /* 1 = Smart Power-Down Active - 0 = Smart Power-Down Inactive - */ - unsigned int reserved0 : 2; - } bits_5; - uint16_t word_5; - } u5; -} AQ_GlobalReservedProvisioning_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Cable Diagnostic Status: 1E.C800 */ -/* Global Cable Diagnostic Status: 1E.C800 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C800.2:0 RO Pair D Status [2:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u0.bits_0.pairDStatus - - - - (after running cable diags) - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair C - 010= Connected to Pair B - 001= Connected to Pair A - 000= OK - - OR: - - (after running component diags) - 100 = TX pin open - 011= TX bias open - 010= Capacitor short - 001= Inductor open - 000= OK - - Notes: - This bitfield reports the result, for pair D, of running either cable diagnostics or component diagnostics. */ - unsigned int pairDStatus : 3; /* 1E.C800.2:0 RO */ - /* (after running cable diags) - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair C - 010= Connected to Pair B - 001= Connected to Pair A - 000= OK - - OR: - - (after running component diags) - 100 = TX pin open - 011= TX bias open - 010= Capacitor short - 001= Inductor open - 000= OK */ - unsigned int reserved3 : 1; - /*! \brief 1E.C800.6:4 RO Pair C Status [2:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u0.bits_0.pairCStatus - - - - (after running cable diags) - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair B - 010= Connected to Pair A - 001= Connected to Pair D - 000= OK - - OR: - - (after running component diags) - 100 = TX pin open - 011= TX bias open - 010= Capacitor short - 001= Inductor open - 000= OK - - Notes: - This bitfield reports the result, for pair C, of running either cable diagnostics or component diagnostics. */ - unsigned int pairCStatus : 3; /* 1E.C800.6:4 RO */ - /* (after running cable diags) - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair B - 010= Connected to Pair A - 001= Connected to Pair D - 000= OK - - OR: - - (after running component diags) - 100 = TX pin open - 011= TX bias open - 010= Capacitor short - 001= Inductor open - 000= OK */ - unsigned int reserved2 : 1; - /*! \brief 1E.C800.A:8 RO Pair B Status [2:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u0.bits_0.pairBStatus - - - - (after running cable diags) - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair A - 010= Connected to Pair D - 001= Connected to Pair C - 000= OK - - OR: - - (after running component diags) - 100 = TX pin open - 011= TX bias open - 010= Capacitor short - 001= Inductor open - 000= OK - - Notes: - This bitfield reports the result, for pair B, of running either cable diagnostics or component diagnostics. */ - unsigned int pairBStatus : 3; /* 1E.C800.A:8 RO */ - /* (after running cable diags) - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair A - 010= Connected to Pair D - 001= Connected to Pair C - 000= OK - - OR: - - (after running component diags) - 100 = TX pin open - 011= TX bias open - 010= Capacitor short - 001= Inductor open - 000= OK */ - unsigned int reserved1 : 1; - /*! \brief 1E.C800.E:C RO Pair A Status [2:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u0.bits_0.pairAStatus - - - - (after running cable diags) - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair D - 010= Connected to Pair C - 001= Connected to Pair B - 000= OK - - OR: - - (after running component diags) - 100 = TX pin open - 011= TX bias open - 010= Capacitor short - 001= Inductor open - 000= OK - - Notes: - This bitfield reports the result, for pair A, of running either cable diagnostics or component diagnostics. */ - unsigned int pairAStatus : 3; /* 1E.C800.E:C RO */ - /* (after running cable diags) - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair D - 010= Connected to Pair C - 001= Connected to Pair B - 000= OK - - OR: - - (after running component diags) - 100 = TX pin open - 011= TX bias open - 010= Capacitor short - 001= Inductor open - 000= OK */ - unsigned int reserved0 : 1; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C801.7:0 RO Pair A Reflection #2 [7:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u1.bits_1.pairAReflection_2 - - - - The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair A - - Notes: - The distance to this reflection is given in See Global Reserved Status 1: Address 1E.C870 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairAReflection_2 : 8; /* 1E.C801.7:0 RO */ - /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair A */ - /*! \brief 1E.C801.F:8 RO Pair A Reflection #1 [7:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u1.bits_1.pairAReflection_1 - - - - The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair A - - Notes: - The distance to this reflection is given in See Global Reserved Status 1: Address 1E.C870 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairAReflection_1 : 8; /* 1E.C801.F:8 RO */ - /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair A */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C802.F:0 RO Impulse Response MSW [F:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u2.bits_2.impulseResponseMSW - - - - The MSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type in 1E.C470.E:D - - - Notes: - See 1E.C470 for more information */ - unsigned int impulseResponseMSW : 16; /* 1E.C802.F:0 RO */ - /* The MSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type in 1E.C470.E:D - */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C803.7:0 RO Pair B Reflection #2 [7:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u3.bits_3.pairBReflection_2 - - - - The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair B - - Notes: - The distance to this reflection is given in See Global Reserved Status 2: Address 1E.C871 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairBReflection_2 : 8; /* 1E.C803.7:0 RO */ - /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair B */ - /*! \brief 1E.C803.F:8 RO Pair B Reflection #1 [7:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u3.bits_3.pairBReflection_1 - - - - The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair B - - Notes: - The distance to this reflection is given in See Global Reserved Status 2: Address 1E.C871 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairBReflection_1 : 8; /* 1E.C803.F:8 RO */ - /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair B */ - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C804.F:0 RO Impulse Response LSW [F:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u4.bits_4.impulseResponseLSW - - - - The LSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type specified in 1E.C470.E:D - - - Notes: - See 1E.C470 for more information */ - unsigned int impulseResponseLSW : 16; /* 1E.C804.F:0 RO */ - /* The LSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type specified in 1E.C470.E:D - */ - } bits_4; - uint16_t word_4; - } u4; - /*! \brief Union for bit and word level access of word 5 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C805.7:0 RO Pair C Reflection #2 [7:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u5.bits_5.pairCReflection_2 - - - - The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair C - - Notes: - The distance to this reflection is given in See Global Reserved Status 3: Address 1E.C872 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairCReflection_2 : 8; /* 1E.C805.7:0 RO */ - /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair C */ - /*! \brief 1E.C805.F:8 RO Pair C Reflection #1 [7:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u5.bits_5.pairCReflection_1 - - - - The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair C - - Notes: - The distance to this reflection is given in See Global Reserved Status 3: Address 1E.C872 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairCReflection_1 : 8; /* 1E.C805.F:8 RO */ - /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair C */ - } bits_5; - uint16_t word_5; - } u5; - /*! \brief Union for bit and word level access of word 6 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C806.F:0 RO Reserved 1 [F:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u6.bits_6.reserved_1 - - - - Reserved for future use - - */ - unsigned int reserved_1 : 16; /* 1E.C806.F:0 RO */ - /* Reserved for future use - */ - } bits_6; - uint16_t word_6; - } u6; - /*! \brief Union for bit and word level access of word 7 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C807.7:0 RO Pair D Reflection #2 [7:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u7.bits_7.pairDReflection_2 - - - - The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair D - - Notes: - The distance to this reflection is given in See Global Reserved Status 4: Address 1E.C873 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairDReflection_2 : 8; /* 1E.C807.7:0 RO */ - /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair D */ - /*! \brief 1E.C807.F:8 RO Pair D Reflection #1 [7:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u7.bits_7.pairDReflection_1 - - - - The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair D - - Notes: - The distance to this reflection is given in See Global Reserved Status 4: Address 1E.C873 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairDReflection_1 : 8; /* 1E.C807.F:8 RO */ - /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair D */ - } bits_7; - uint16_t word_7; - } u7; - /*! \brief Union for bit and word level access of word 8 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C808.F:0 RO Reserved 2[F:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u8.bits_8.reserved_2 - - - - Reserved for future use - - */ - unsigned int reserved_2 : 16; /* 1E.C808.F:0 RO */ - /* Reserved for future use - */ - } bits_8; - uint16_t word_8; - } u8; -} AQ_GlobalCableDiagnosticStatus_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Thermal Status: 1E.C820 */ -/* Global Thermal Status: 1E.C820 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Thermal Status */ - union - { - struct - { - /*! \brief 1E.C820.F:0 RO Temperature [F:0] - AQ_GlobalThermalStatus_APPIA.u0.bits_0.temperature - - - - [F:0] of temperature - - - Notes: - 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 70 degreesC. This is a mirror of the XENPAK register 1.A060 - 1.A061. The mirror is performed in H/W. */ - unsigned int temperature : 16; /* 1E.C820.F:0 RO */ - /* [F:0] of temperature - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Thermal Status */ - union - { - struct - { - /*! \brief 1E.C821.0 RO Temperature Ready - AQ_GlobalThermalStatus_APPIA.u1.bits_1.temperatureReady - - - - 1 = Temperature measurement is valid - - - Notes: - This is a mirror of the XENPAK register 1.A06E. */ - unsigned int temperatureReady : 1; /* 1E.C821.0 RO */ - /* 1 = Temperature measurement is valid - */ - unsigned int reserved0 : 15; - } bits_1; - uint16_t word_1; - } u1; -} AQ_GlobalThermalStatus_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global General Status: 1E.C830 */ -/* Global General Status: 1E.C830 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global General Status */ - union - { - struct - { - unsigned int reserved1 : 11; - /*! \brief 1E.C830.B RO Low Temperature Warning State - AQ_GlobalGeneralStatus_APPIA.u0.bits_0.lowTemperatureWarningState - - - - 1 = Low temperature warning threshold has been exceeded - - Notes: - In XENPAK mode, F/W will copy this register to the 1.A074.6 register. - - */ - unsigned int lowTemperatureWarningState : 1; /* 1E.C830.B RO */ - /* 1 = Low temperature warning threshold has been exceeded */ - /*! \brief 1E.C830.C RO High Temperature Warning State - AQ_GlobalGeneralStatus_APPIA.u0.bits_0.highTemperatureWarningState - - - - 1 = High temperature warning threshold has been exceeded - - Notes: - In XENPAK mode, F/W will copy this register to the 1.A074.7 register. - - */ - unsigned int highTemperatureWarningState : 1; /* 1E.C830.C RO */ - /* 1 = High temperature warning threshold has been exceeded */ - /*! \brief 1E.C830.D RO Low Temperature Failure State - AQ_GlobalGeneralStatus_APPIA.u0.bits_0.lowTemperatureFailureState - - - - 1 = Low temperature failure threshold has been exceeded - - Notes: - In XENPAK mode, F/W will copy this register to the 1.A070.6 register. - - */ - unsigned int lowTemperatureFailureState : 1; /* 1E.C830.D RO */ - /* 1 = Low temperature failure threshold has been exceeded */ - /*! \brief 1E.C830.E RO High Temperature Failure State - AQ_GlobalGeneralStatus_APPIA.u0.bits_0.highTemperatureFailureState - - - - 1 = High temperature failure threshold has been exceeded - - Notes: - In XENPAK mode, F/W will copy this register to the 1.A070.7 register. - - */ - unsigned int highTemperatureFailureState : 1; /* 1E.C830.E RO */ - /* 1 = High temperature failure threshold has been exceeded */ - unsigned int reserved0 : 1; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global General Status */ - union - { - struct - { - unsigned int reserved0 : 15; - /*! \brief 1E.C831.F RO Processor Intensive MDIO Operation In- Progress - AQ_GlobalGeneralStatus_APPIA.u1.bits_1.processorIntensiveMdioOperationIn_Progress - - - - 1 = PHY microprocessor is busy with a processor-intensive MDIO operation - 0 = Processor-intensive MDIO operation completed - - - Notes: - This bit should may be used with certain processor-intensive MDIO commands (such as Loopbacks, Test Modes, Low power modes, Tx-Disable, Restart autoneg, Cable Diagnostics, etc.) that take longer than an MDIO cycle to complete. Upon receiving an MDIO command that involves the PHY's microprocessor, this bit is set, and when the command is completed, this bit is cleared. - - NOTE!!! This bit should be checked only after 1 ms of issuing a processor-intensive MDIO operation. - - The list of operations that set this bit are as follows: - - 1.0.0, PMA Loopback - 1.0.B, Low power mode - 1.9.4:0, Tx Disable - 1.84, 10G Test modes - 1.8000.5, XENPAK Control - 1.9000, XENPAK Rx Fault Enable - 1.9002, XENPAK Alarm Enable - 1.E400.F, External loopback - 3.0.B, Low power mode - 3.0.E, System PCS loopback - 3.C471.5, PRBS Test - 3.C471.6, PRBS Test - 3.E471.5, PRBS Test - 3.E471.6, PRBS Test - 4.0.B, Low power mode - 4.0.E, PHY-XS network loopback - 4.C440, Output clock control, Load SERDES parameters - 4.F802.E, System loopback - 4.C444.F:B, Loopback Control - 4.C444.4:2, Packet generation - 4.C445.C, SERDES calibration - 7.0.9, Restart autonegotiation - 1D.C280, 1G/100M Network loopback - 1D.C500, 1G System loopback - 1D.C501, 1G / 100M Test modes */ - unsigned int processorIntensiveMdioOperationIn_Progress : 1; /* 1E.C831.F RO */ - /* 1 = PHY microprocessor is busy with a processor-intensive MDIO operation - 0 = Processor-intensive MDIO operation completed - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_GlobalGeneralStatus_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Pin Status: 1E.C840 */ -/* Global Pin Status: 1E.C840 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Pin Status */ - union - { - struct - { - /*! \brief 1E.C840.5:0 RO LED Pullup State [5:0] - AQ_GlobalPinStatus_APPIA.u0.bits_0.ledPullupState - - - - 1 = LED output pin is pulled high - 0 = LED output pin is pulled low - - */ - unsigned int ledPullupState : 6; /* 1E.C840.5:0 RO */ - /* 1 = LED output pin is pulled high - 0 = LED output pin is pulled low - */ - unsigned int reserved3 : 1; - /*! \brief 1E.C840.7 RO Tx Enable - AQ_GlobalPinStatus_APPIA.u0.bits_0.txEnable - - - - Current Value of Tx Enable pin - - - Notes: - 0 = Disable Transmitter */ - unsigned int txEnable : 1; /* 1E.C840.7 RO */ - /* Current Value of Tx Enable pin - */ - unsigned int reserved2 : 1; - /*! \brief 1E.C840.9 RO Package Connectivity - AQ_GlobalPinStatus_APPIA.u0.bits_0.packageConnectivity - - - - Value of the package connection pin - - */ - unsigned int packageConnectivity : 1; /* 1E.C840.9 RO */ - /* Value of the package connection pin - */ - unsigned int reserved1 : 3; - /*! \brief 1E.C840.E:D RO MDIO Boot Load [1:0] - AQ_GlobalPinStatus_APPIA.u0.bits_0.mdioBootLoad - - - - Value of MDIO Boot Load pins - - 0x3 = PHY #0 Slave Daisy Chain Boot - 0x2 = PHY #0 Master Daisy Chain Boot from Flash - 0x1 = MDIO Boot Load - 0x0 = Boot from Flash (PHY #0 only) - - - Notes: - NOTES: - - PHY #0 is the primary PHY, and PHY #1 is the secondary PHY - - PHY #1 is always in Slave Daisy Chain Boot from Flash when set to 0x2 or 0x3. */ - unsigned int mdioBootLoad : 2; /* 1E.C840.E:D RO */ - /* Value of MDIO Boot Load pins - - 0x3 = PHY #0 Slave Daisy Chain Boot - 0x2 = PHY #0 Master Daisy Chain Boot from Flash - 0x1 = MDIO Boot Load - 0x0 = Boot from Flash (PHY #0 only) - */ - unsigned int reserved0 : 1; - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalPinStatus_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Daisy Chain Status: 1E.C842 */ -/* Global Daisy Chain Status: 1E.C842 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Daisy Chain Status */ - union - { - struct - { - /*! \brief 1E.C842.F:0 RO Rx Daisy Chain Calculated CRC [F:0] - AQ_GlobalDaisyChainStatus_APPIA.u0.bits_0.rxDaisyChainCalculatedCrc - - - - Rx Daisy Chain Calculated CRC - - - Notes: - This is the calculated daisy chain CRC. */ - unsigned int rxDaisyChainCalculatedCrc : 16; /* 1E.C842.F:0 RO */ - /* Rx Daisy Chain Calculated CRC - */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalDaisyChainStatus_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Fault Message: 1E.C850 */ -/* Global Fault Message: 1E.C850 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Fault Message */ - union - { - struct - { - /*! \brief 1E.C850.F:0 RO Message [F:0] - AQ_GlobalFaultMessage_APPIA.u0.bits_0.message - - - - Error code describing fault - - Notes: - Code 0x8001: Firmware not compatible with chip architecture. This fault occurs when firmware compiled for a different Tensilica core is loaded. - Code 0x8002: VCO calibration failed. This occurs when the main PLLs on chip fail to lock: this is not possible to trigger. - Code 0x8003: XAUI calibration failed. This occurs when the XAUI PLLs fail to lock: this is not possible to trigger. - Code 0x8004: Failed to set operating voltages via PMBus. This only occurs when the processor has control over power supply voltage via an attached PMBus device and there is a protocol error on the I2C bus: this is not possible to trigger. - Code 0x8005: Unexpected device ID. This occurs if the device ID programmed into the internal E-Fuse registers in not valid: this is not possible to trigger. - Code 0x8006: Computed checksum does not match expected checksum. This occurs when the FLASH checksum check performed at boot time fails. This only occurs when the system boots from FLASH. - Code 0x8007: Detected a bit error in static memory. To trigger, corrupt one of the static regions. - Code 0xC001: Illegal Instruction exception. This occurs when the processor attempts to execute an illegal instruction. To trigger this, write an illegal instruction to program memory. It's possible that the bit error check will trigger before the illegal instruction is executed. - Code 0xC002 Instruction Fetch Error. Internal physical address or a data error during instruction fetch: this is not possible to trigger. - Code 0xC003 Load Store Error. Internal physical address or data error during load store operation: this is not possible to trigger.. - Code 0xC004 Privileged Instruction. Attempt to execute a privileged operation without sufficient privilege: this is not possible to trigger. - Code 0xC005 Unaligned Load or Store. Attempt to load or store data at an address which cannot be handled due to alignment: this is not possible to trigger. - Code 0xC006 Instruction fetch from prohibited space: this is not possible to trigger. - Code 0xC007 Data load from prohibited space: this is not possible to trigger. - Code 0xC008 Data store into prohibited space: this is not possible to trigger. */ - unsigned int message : 16; /* 1E.C850.F:0 RO */ - /* Error code describing fault */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalFaultMessage_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Primary Status: 1E.C851 */ -/* Global Primary Status: 1E.C851 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Primary Status */ - union - { - struct - { - /*! \brief 1E.C851.0 RO Primary Status - AQ_GlobalPrimaryStatus_APPIA.u0.bits_0.primaryStatus - - - - 1 = PHY is the primary PHY - 0 = PHY is is secondary PHY - - */ - unsigned int primaryStatus : 1; /* 1E.C851.0 RO */ - /* 1 = PHY is the primary PHY - 0 = PHY is is secondary PHY - */ - unsigned int reserved0 : 15; - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalPrimaryStatus_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Cable Diagnostic Impedance: 1E.C880 */ -/* Global Cable Diagnostic Impedance: 1E.C880 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Cable Diagnostic Impedance */ - union - { - struct - { - /*! \brief 1E.C880.2:0 RO Pair A Reflection #4 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.pairAReflection_4 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the fourth worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ - unsigned int pairAReflection_4 : 3; /* 1E.C880.2:0 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C880.3 RO Reserved 4 - AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.reserved_4 - - - - Reserved for future use - - */ - unsigned int reserved_4 : 1; /* 1E.C880.3 RO */ - /* Reserved for future use - */ - /*! \brief 1E.C880.6:4 RO Pair A Reflection #3 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.pairAReflection_3 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the third worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ - unsigned int pairAReflection_3 : 3; /* 1E.C880.6:4 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C880.7 RO Reserved 3 - AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.reserved_3 - - - - Reserved for future use - - */ - unsigned int reserved_3 : 1; /* 1E.C880.7 RO */ - /* Reserved for future use - */ - /*! \brief 1E.C880.A:8 RO Pair A Reflection #2 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.pairAReflection_2 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the second worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ - unsigned int pairAReflection_2 : 3; /* 1E.C880.A:8 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C880.B RO Reserved 2 - AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.reserved_2 - - - - Reserved for future use - - */ - unsigned int reserved_2 : 1; /* 1E.C880.B RO */ - /* Reserved for future use - */ - /*! \brief 1E.C880.E:C RO Pair A Reflection #1 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.pairAReflection_1 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the first worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ - unsigned int pairAReflection_1 : 3; /* 1E.C880.E:C RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C880.F RO Reserved 1 - AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.reserved_1 - - - - Reserved for future use - - */ - unsigned int reserved_1 : 1; /* 1E.C880.F RO */ - /* Reserved for future use - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Cable Diagnostic Impedance */ - union - { - struct - { - /*! \brief 1E.C881.2:0 RO Pair B Reflection #4 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.pairBReflection_4 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the fourth worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ - unsigned int pairBReflection_4 : 3; /* 1E.C881.2:0 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C881.3 RO Reserved 8 - AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.reserved_8 - - - - Reserved for future use - - */ - unsigned int reserved_8 : 1; /* 1E.C881.3 RO */ - /* Reserved for future use - */ - /*! \brief 1E.C881.6:4 RO Pair B Reflection #3 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.pairBReflection_3 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the third worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ - unsigned int pairBReflection_3 : 3; /* 1E.C881.6:4 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C881.7 RO Reserved 7 - AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.reserved_7 - - - - Reserved for future use - - */ - unsigned int reserved_7 : 1; /* 1E.C881.7 RO */ - /* Reserved for future use - */ - /*! \brief 1E.C881.A:8 RO Pair B Reflection #2 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.pairBReflection_2 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the second worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ - unsigned int pairBReflection_2 : 3; /* 1E.C881.A:8 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C881.B RO Reserved 6 - AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.reserved_6 - - - - Reserved for future use - - */ - unsigned int reserved_6 : 1; /* 1E.C881.B RO */ - /* Reserved for future use - */ - /*! \brief 1E.C881.E:C RO Pair B Reflection #1 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.pairBReflection_1 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the first worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ - unsigned int pairBReflection_1 : 3; /* 1E.C881.E:C RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C881.F RO Reserved 5 - AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.reserved_5 - - - - Reserved for future use - - */ - unsigned int reserved_5 : 1; /* 1E.C881.F RO */ - /* Reserved for future use - */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global Cable Diagnostic Impedance */ - union - { - struct - { - /*! \brief 1E.C882.2:0 RO Pair C Reflection #4 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.pairCReflection_4 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the fourth worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ - unsigned int pairCReflection_4 : 3; /* 1E.C882.2:0 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C882.3 RO Reserved 12 - AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.reserved_12 - - - - Reserved for future use - - */ - unsigned int reserved_12 : 1; /* 1E.C882.3 RO */ - /* Reserved for future use - */ - /*! \brief 1E.C882.6:4 RO Pair C Reflection #3 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.pairCReflection_3 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the third worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ - unsigned int pairCReflection_3 : 3; /* 1E.C882.6:4 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C882.7 RO Reserved 11 - AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.reserved_11 - - - - Reserved for future use - - */ - unsigned int reserved_11 : 1; /* 1E.C882.7 RO */ - /* Reserved for future use - */ - /*! \brief 1E.C882.A:8 RO Pair C Reflection #2 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.pairCReflection_2 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the second worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ - unsigned int pairCReflection_2 : 3; /* 1E.C882.A:8 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C882.B RO Reserved 10 - AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.reserved_10 - - - - Reserved for future use - - */ - unsigned int reserved_10 : 1; /* 1E.C882.B RO */ - /* Reserved for future use - */ - /*! \brief 1E.C882.E:C RO Pair C Reflection #1 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.pairCReflection_1 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the first worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ - unsigned int pairCReflection_1 : 3; /* 1E.C882.E:C RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C882.F RO Reserved 9 - AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.reserved_9 - - - - Reserved for future use - - */ - unsigned int reserved_9 : 1; /* 1E.C882.F RO */ - /* Reserved for future use - */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global Cable Diagnostic Impedance */ - union - { - struct - { - /*! \brief 1E.C883.2:0 RO Pair D Reflection #4 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.pairDReflection_4 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the fourth worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ - unsigned int pairDReflection_4 : 3; /* 1E.C883.2:0 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C883.3 RO Reserved 16 - AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.reserved_16 - - - - Reserved for future use - - */ - unsigned int reserved_16 : 1; /* 1E.C883.3 RO */ - /* Reserved for future use - */ - /*! \brief 1E.C883.6:4 RO Pair D Reflection #3 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.pairDReflection_3 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the third worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ - unsigned int pairDReflection_3 : 3; /* 1E.C883.6:4 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C883.7 RO Reserved 15 - AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.reserved_15 - - - - Reserved for future use - - */ - unsigned int reserved_15 : 1; /* 1E.C883.7 RO */ - /* Reserved for future use - */ - /*! \brief 1E.C883.A:8 RO Pair D Reflection #2 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.pairDReflection_2 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the second worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ - unsigned int pairDReflection_2 : 3; /* 1E.C883.A:8 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C883.B RO Reserved 14 - AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.reserved_14 - - - - Reserved for future use - - */ - unsigned int reserved_14 : 1; /* 1E.C883.B RO */ - /* Reserved for future use - */ - /*! \brief 1E.C883.E:C RO Pair D Reflection #1 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.pairDReflection_1 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the first worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ - unsigned int pairDReflection_1 : 3; /* 1E.C883.E:C RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C883.F RO Reserved 13 - AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.reserved_13 - - - - Reserved for future use - - */ - unsigned int reserved_13 : 1; /* 1E.C883.F RO */ - /* Reserved for future use - */ - } bits_3; - uint16_t word_3; - } u3; -} AQ_GlobalCableDiagnosticImpedance_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Status: 1E.C884 */ -/* Global Status: 1E.C884 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Status */ - union - { - struct - { - /*! \brief 1E.C884.7:0 RO Cable Length [7:0] - AQ_GlobalStatus_APPIA.u0.bits_0.cableLength - - - - The estimated length of the cable in meters - - - Notes: - The length of the cable shown here is estimated from the cable diagnostic engine and should be accurate to +/-1m. */ - unsigned int cableLength : 8; /* 1E.C884.7:0 RO */ - /* The estimated length of the cable in meters - */ - /*! \brief 1E.C884.F:8 RO Reserved Status 0 [7:0] - AQ_GlobalStatus_APPIA.u0.bits_0.reservedStatus_0 - - - - Reserved for future use - - */ - unsigned int reservedStatus_0 : 8; /* 1E.C884.F:8 RO */ - /* Reserved for future use - */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalStatus_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Reserved Status: 1E.C885 */ -/* Global Reserved Status: 1E.C885 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Reserved Status */ - union - { - struct - { - /*! \brief 1E.C885.7:0 ROSPD ROM Revision [7:0] - AQ_GlobalReservedStatus_APPIA.u0.bits_0.romRevision - - Provisionable Default = 0x00 - - ROM Revision Number - - - Notes: - Customers may receive multiple ROM images that differ only in their provisioning. This field is used to differentiate those images. This field is used in conjunction with the firmware major and minor revision numbers to uniquely identify ROM images. */ - unsigned int romRevision : 8; /* 1E.C885.7:0 ROSPD Provisionable Default = 0x00 */ - /* ROM Revision Number - */ - /*! \brief 1E.C885.9:8 ROSPD XENPAK NVR Status [1:0] - AQ_GlobalReservedStatus_APPIA.u0.bits_0.xenpakNvrStatus - - Provisionable Default = 0x0 - - Status of XENPAK NVR: - 0: NVR not enabled - 1: Last NVR operation succeeded - 2: Last NVR operation failed - 3: Reserved - - - Notes: - XENPAK register space is mirrored in NVR (SPI ROM). This register indicates the status of the last NVR operation. */ - unsigned int xenpakNvrStatus : 2; /* 1E.C885.9:8 ROSPD Provisionable Default = 0x0 */ - /* Status of XENPAK NVR: - 0: NVR not enabled - 1: Last NVR operation succeeded - 2: Last NVR operation failed - 3: Reserved - */ - /*! \brief 1E.C885.F:A RO Nearly Seconds MSW[5:0] - AQ_GlobalReservedStatus_APPIA.u0.bits_0.nearlySecondsMSW - - - - Bits 16 to 21 of the 22 bit "Nearly Seconds" uptime counter. - - - Notes: - The "Nearly Seconds" counter is incremented every 1024 milliseconds. */ - unsigned int nearlySecondsMSW : 6; /* 1E.C885.F:A RO */ - /* Bits 16 to 21 of the 22 bit "Nearly Seconds" uptime counter. - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Reserved Status */ - union - { - struct - { - /*! \brief 1E.C886.F:0 RO Nearly Seconds LSW[F:0] - AQ_GlobalReservedStatus_APPIA.u1.bits_1.nearlySecondsLSW - - - - Bits 0 to 15 of the 22 bit "Nearly Seconds" uptime counter. - - - Notes: - The "Nearly Seconds" counter is incremented every 1024 milliseconds. */ - unsigned int nearlySecondsLSW : 16; /* 1E.C886.F:0 RO */ - /* Bits 0 to 15 of the 22 bit "Nearly Seconds" uptime counter. - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_GlobalReservedStatus_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Alarms: 1E.CC00 */ -/* Global Alarms: 1E.CC00 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Alarms */ - union - { - struct - { - /*! \brief 1E.CC00.0 LH Reserved Alarm D - AQ_GlobalAlarms_APPIA.u0.bits_0.reservedAlarmD - - - - Reserved for future use - - */ - unsigned int reservedAlarmD : 1; /* 1E.CC00.0 LH */ - /* Reserved for future use - */ - /*! \brief 1E.CC00.1 LH Reserved Alarm C - AQ_GlobalAlarms_APPIA.u0.bits_0.reservedAlarmC - - - - Reserved for future use - - */ - unsigned int reservedAlarmC : 1; /* 1E.CC00.1 LH */ - /* Reserved for future use - */ - /*! \brief 1E.CC00.2 LH Reserved Alarm B - AQ_GlobalAlarms_APPIA.u0.bits_0.reservedAlarmB - - - - Reserved for future use - - */ - unsigned int reservedAlarmB : 1; /* 1E.CC00.2 LH */ - /* Reserved for future use - */ - /*! \brief 1E.CC00.3 LH Reserved Alarm A - AQ_GlobalAlarms_APPIA.u0.bits_0.reservedAlarmA - - - - Reserved for future use - - */ - unsigned int reservedAlarmA : 1; /* 1E.CC00.3 LH */ - /* Reserved for future use - */ - /*! \brief 1E.CC00.4 LH Device Fault - AQ_GlobalAlarms_APPIA.u0.bits_0.deviceFault - - - - 1 = Fault - - Notes: - When set, a fault has been detected by the uP and the associated 16 bit error code is visible in See Global Configuration Fault Message: Address 1E.C850 */ - unsigned int deviceFault : 1; /* 1E.CC00.4 LH */ - /* 1 = Fault */ - unsigned int reserved2 : 1; - /*! \brief 1E.CC00.6 LH Reset completed - AQ_GlobalAlarms_APPIA.u0.bits_0.resetCompleted - - - - 1 = Chip wide reset completed - - Notes: - This bit is set by the microprocessor when it has completed it's initialization sequence. This bit is mirrored in 1.CC02.0 */ - unsigned int resetCompleted : 1; /* 1E.CC00.6 LH */ - /* 1 = Chip wide reset completed */ - unsigned int reserved1 : 4; - /*! \brief 1E.CC00.B LH Low Temperature Warning - AQ_GlobalAlarms_APPIA.u0.bits_0.lowTemperatureWarning - - - - 1 = Low temperature warning threshold has been exceeded - - - Notes: - - - - - These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ - unsigned int lowTemperatureWarning : 1; /* 1E.CC00.B LH */ - /* 1 = Low temperature warning threshold has been exceeded - */ - /*! \brief 1E.CC00.C LH High Temperature Warning - AQ_GlobalAlarms_APPIA.u0.bits_0.highTemperatureWarning - - - - 1 = High temperature warning threshold has been exceeded - - - Notes: - - - - - These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ - unsigned int highTemperatureWarning : 1; /* 1E.CC00.C LH */ - /* 1 = High temperature warning threshold has been exceeded - */ - /*! \brief 1E.CC00.D LH Low Temperature Failure - AQ_GlobalAlarms_APPIA.u0.bits_0.lowTemperatureFailure - - - - 1 = Low temperature failure threshold has been exceeded - - - Notes: - - - - - These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ - unsigned int lowTemperatureFailure : 1; /* 1E.CC00.D LH */ - /* 1 = Low temperature failure threshold has been exceeded - */ - /*! \brief 1E.CC00.E LH High Temperature Failure - AQ_GlobalAlarms_APPIA.u0.bits_0.highTemperatureFailure - - - - 1 = High temperature failure threshold has been exceeded - - - Notes: - - - - - These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ - unsigned int highTemperatureFailure : 1; /* 1E.CC00.E LH */ - /* 1 = High temperature failure threshold has been exceeded - */ - unsigned int reserved0 : 1; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Alarms */ - union - { - struct - { - /*! \brief 1E.CC01.0 LH Diagnostic Alarm - AQ_GlobalAlarms_APPIA.u1.bits_1.diagnosticAlarm - - - - 1 = Alarm triggered by a write to 1E.C470.7 - - - Notes: - A diagnostic alarm use to test system alarm circuitry */ - unsigned int diagnosticAlarm : 1; /* 1E.CC01.0 LH */ - /* 1 = Alarm triggered by a write to 1E.C470.7 - */ - unsigned int reserved1 : 6; - /*! \brief 1E.CC01.7 LH MDIO Command Handling Overflow - AQ_GlobalAlarms_APPIA.u1.bits_1.mdioCommandHandlingOverflow - - - - 1 = PHY was issued more MDIO requests than it could service in it's request buffer - - - Notes: - Assertion of this bit means that more MDIO commands were issued than FW could handle. */ - unsigned int mdioCommandHandlingOverflow : 1; /* 1E.CC01.7 LH */ - /* 1 = PHY was issued more MDIO requests than it could service in it's request buffer - */ - /*! \brief 1E.CC01.C:8 LH Reserved Alarms [4:0] - AQ_GlobalAlarms_APPIA.u1.bits_1.reservedAlarms - - - - Reserved for future use - - */ - unsigned int reservedAlarms : 5; /* 1E.CC01.C:8 LH */ - /* Reserved for future use - */ - /*! \brief 1E.CC01.D RO XENPAK Alarm - AQ_GlobalAlarms_APPIA.u1.bits_1.xenpakAlarm - - - - 1 = XENPAK Alarm - - - Notes: - This alarm is performed by H/W. */ - unsigned int xenpakAlarm : 1; /* 1E.CC01.D RO */ - /* 1 = XENPAK Alarm - */ - /*! \brief 1E.CC01.E LH Smart Power-Down Entered - AQ_GlobalAlarms_APPIA.u1.bits_1.smartPower_downEntered - - - - 1 = Smart Power-Down State Entered - - - Notes: - When this bit is set, it indicates that the Smart Power-Down state was entered */ - unsigned int smartPower_downEntered : 1; /* 1E.CC01.E LH */ - /* 1 = Smart Power-Down State Entered - */ - unsigned int reserved0 : 1; - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global Alarms */ - union - { - struct - { - /*! \brief 1E.CC02.0 LH Watchdog Timer Alarm - AQ_GlobalAlarms_APPIA.u2.bits_2.watchdogTimerAlarm - - - - 1 = Watchdog timer alarm - - */ - unsigned int watchdogTimerAlarm : 1; /* 1E.CC02.0 LH */ - /* 1 = Watchdog timer alarm - */ - /*! \brief 1E.CC02.1 LH MDIO Timeout Error - AQ_GlobalAlarms_APPIA.u2.bits_2.mdioTimeoutError - - - - 1 = MDIO timeout detected - - */ - unsigned int mdioTimeoutError : 1; /* 1E.CC02.1 LH */ - /* 1 = MDIO timeout detected - */ - /*! \brief 1E.CC02.2 LH MDIO MMD Error - AQ_GlobalAlarms_APPIA.u2.bits_2.mdioMMD_Error - - - - 1 = Invalid MMD address detected - - */ - unsigned int mdioMMD_Error : 1; /* 1E.CC02.2 LH */ - /* 1 = Invalid MMD address detected - */ - unsigned int reserved2 : 2; - /*! \brief 1E.CC02.5 LRF Tx Enable State Change - AQ_GlobalAlarms_APPIA.u2.bits_2.txEnableStateChange - - - - 1 = TX_EN pin has changed state - - */ - unsigned int txEnableStateChange : 1; /* 1E.CC02.5 LRF */ - /* 1 = TX_EN pin has changed state - */ - unsigned int reserved1 : 2; - /*! \brief 1E.CC02.9:8 LH uP IRAM Parity Error [1:0] - AQ_GlobalAlarms_APPIA.u2.bits_2.upIramParityError - - - - 1 = Parity error detected in the uP IRAM - - - Notes: - Bit 0 indicates a parity error was detected in the uP IRAM but was corrected. - Bit 1 indicates a multiple parity errors were detected in the uP IRAM and could not be corrected. - The uP IRAM is protected with ECC. */ - unsigned int upIramParityError : 2; /* 1E.CC02.9:8 LH */ - /* 1 = Parity error detected in the uP IRAM - */ - /*! \brief 1E.CC02.A LH uP DRAM Parity Error - AQ_GlobalAlarms_APPIA.u2.bits_2.upDramParityError - - - - 1 = Parity error detected in the uP DRAM - - */ - unsigned int upDramParityError : 1; /* 1E.CC02.A LH */ - /* 1 = Parity error detected in the uP DRAM - */ - unsigned int reserved0 : 3; - /*! \brief 1E.CC02.E LH Mailbox Operation: Complete - AQ_GlobalAlarms_APPIA.u2.bits_2.mailboxOperation_Complete - - - - 1 = Mailbox operation is complete - - - Notes: - Mailbox interface is ready interrupt for registers See Global Vendor Specific Control - Address 1E.C000 - See Global Vendor Specific Provisioning 5 - Address 1E.C404 */ - unsigned int mailboxOperation_Complete : 1; /* 1E.CC02.E LH */ - /* 1 = Mailbox operation is complete - */ - /*! \brief 1E.CC02.F LH NVR Operation Complete - AQ_GlobalAlarms_APPIA.u2.bits_2.nvrOperationComplete - - - - 1 = NVR operation is complete - - - Notes: - NVR interface is ready interrupt for registers See Global NVR Interface 1: Address 1E.100 - See Global NVR Provisioning Data MSW - Address 1E.17 . */ - unsigned int nvrOperationComplete : 1; /* 1E.CC02.F LH */ - /* 1 = NVR operation is complete - */ - } bits_2; - uint16_t word_2; - } u2; -} AQ_GlobalAlarms_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Interrupt Mask: 1E.D400 */ -/* Global Interrupt Mask: 1E.D400 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Interrupt Mask */ - union - { - struct - { - /*! \brief 1E.D400.0 R/WPD Reserved Alarm D Mask - AQ_GlobalInterruptMask_APPIA.u0.bits_0.reservedAlarmDMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int reservedAlarmDMask : 1; /* 1E.D400.0 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - /*! \brief 1E.D400.1 R/WPD Reserved Alarm C Mask - AQ_GlobalInterruptMask_APPIA.u0.bits_0.reservedAlarmCMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int reservedAlarmCMask : 1; /* 1E.D400.1 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - /*! \brief 1E.D400.2 R/WPD Reserved Alarm B Mask - AQ_GlobalInterruptMask_APPIA.u0.bits_0.reservedAlarmBMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int reservedAlarmBMask : 1; /* 1E.D400.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - /*! \brief 1E.D400.3 R/WPD Reserved Alarm A Mask - AQ_GlobalInterruptMask_APPIA.u0.bits_0.reservedAlarmAMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int reservedAlarmAMask : 1; /* 1E.D400.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - /*! \brief 1E.D400.4 R/WPD Device Fault Mask - AQ_GlobalInterruptMask_APPIA.u0.bits_0.deviceFaultMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int deviceFaultMask : 1; /* 1E.D400.4 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - unsigned int reserved2 : 1; - /*! \brief 1E.D400.6 R/WPD Reset completed Mask - AQ_GlobalInterruptMask_APPIA.u0.bits_0.resetCompletedMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int resetCompletedMask : 1; /* 1E.D400.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - unsigned int reserved1 : 4; - /*! \brief 1E.D400.B R/WPD Low Temperature Warning Mask - AQ_GlobalInterruptMask_APPIA.u0.bits_0.lowTemperatureWarningMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int lowTemperatureWarningMask : 1; /* 1E.D400.B R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.D400.C R/WPD High Temperature Warning Mask - AQ_GlobalInterruptMask_APPIA.u0.bits_0.highTemperatureWarningMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int highTemperatureWarningMask : 1; /* 1E.D400.C R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.D400.D R/WPD Low Temperature Failure Mask - AQ_GlobalInterruptMask_APPIA.u0.bits_0.lowTemperatureFailureMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int lowTemperatureFailureMask : 1; /* 1E.D400.D R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.D400.E R/WPD High Temperature Failure Mask - AQ_GlobalInterruptMask_APPIA.u0.bits_0.highTemperatureFailureMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int highTemperatureFailureMask : 1; /* 1E.D400.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - unsigned int reserved0 : 1; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Interrupt Mask */ - union - { - struct - { - /*! \brief 1E.D401.0 R/WPD Diagnostic Alarm Mask - AQ_GlobalInterruptMask_APPIA.u1.bits_1.diagnosticAlarmMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int diagnosticAlarmMask : 1; /* 1E.D401.0 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int reserved1 : 6; - /*! \brief 1E.D401.7 R/WPD MDIO Command Handling Overflow Mask - AQ_GlobalInterruptMask_APPIA.u1.bits_1.mdioCommandHandlingOverflowMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int mdioCommandHandlingOverflowMask : 1; /* 1E.D401.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - /*! \brief 1E.D401.C:8 R/WPD Reserved Alarms Mask [4:0] - AQ_GlobalInterruptMask_APPIA.u1.bits_1.reservedAlarmsMask - - Provisionable Default = 0x00 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int reservedAlarmsMask : 5; /* 1E.D401.C:8 R/WPD Provisionable Default = 0x00 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - /*! \brief 1E.D401.D R/WPD XENPAK Alarm Mask - AQ_GlobalInterruptMask_APPIA.u1.bits_1.xenpakAlarmMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int xenpakAlarmMask : 1; /* 1E.D401.D R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.D401.E R/WPD Smart Power-Down Entered Mask - AQ_GlobalInterruptMask_APPIA.u1.bits_1.smartPower_downEnteredMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int smartPower_downEnteredMask : 1; /* 1E.D401.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int reserved0 : 1; - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global Interrupt Mask */ - union - { - struct - { - /*! \brief 1E.D402.0 R/WPD Watchdog Timer Alarm Mask - AQ_GlobalInterruptMask_APPIA.u2.bits_2.watchdogTimerAlarmMask - - Provisionable Default = 0x1 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int watchdogTimerAlarmMask : 1; /* 1E.D402.0 R/WPD Provisionable Default = 0x1 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.D402.1 R/WPD MDIO Timeout Error Mask - AQ_GlobalInterruptMask_APPIA.u2.bits_2.mdioTimeoutErrorMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int mdioTimeoutErrorMask : 1; /* 1E.D402.1 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.D402.2 R/WPD MDIO MMD Error Mask - AQ_GlobalInterruptMask_APPIA.u2.bits_2.mdioMMD_ErrorMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int mdioMMD_ErrorMask : 1; /* 1E.D402.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - unsigned int reserved2 : 2; - /*! \brief 1E.D402.5 R/WPD Tx Enable State Change Mask - AQ_GlobalInterruptMask_APPIA.u2.bits_2.txEnableStateChangeMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int txEnableStateChangeMask : 1; /* 1E.D402.5 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - unsigned int reserved1 : 2; - /*! \brief 1E.D402.9:8 R/WPD uP IRAM Parity Error Mask [1:0] - AQ_GlobalInterruptMask_APPIA.u2.bits_2.upIramParityErrorMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int upIramParityErrorMask : 2; /* 1E.D402.9:8 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - /*! \brief 1E.D402.A R/WPD uP DRAM Parity Error Mask - AQ_GlobalInterruptMask_APPIA.u2.bits_2.upDramParityErrorMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int upDramParityErrorMask : 1; /* 1E.D402.A R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int reserved0 : 3; - /*! \brief 1E.D402.E R/WPD Mailbox Operation Complete Mask - AQ_GlobalInterruptMask_APPIA.u2.bits_2.mailboxOperationCompleteMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - Notes: - Mailbox interface is ready interrupt for registers See Global Vendor Specific Control - Address 1E.C000 - See Global Vendor Specific Provisioning 5 - Address 1E.C404 */ - unsigned int mailboxOperationCompleteMask : 1; /* 1E.D402.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.D402.F R/WPD NVR Operation Complete Mask - AQ_GlobalInterruptMask_APPIA.u2.bits_2.nvrOperationCompleteMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - Notes: - NVR interface is ready interrupt for registers See Global NVR Interface 1: Address 1E.100 - See Global NVR Provisioning Data MSW - Address 1E.17 */ - unsigned int nvrOperationCompleteMask : 1; /* 1E.D402.F R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - } bits_2; - uint16_t word_2; - } u2; -} AQ_GlobalInterruptMask_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Chip-Wide Standard Interrupt Flags: 1E.FC00 */ -/* Global Chip-Wide Standard Interrupt Flags: 1E.FC00 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Chip-Wide Standard Interrupt Flags */ - union - { - struct - { - /*! \brief 1E.FC00.0 RO All Vendor Alarms Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.allVendorAlarmsInterrupt - - - - 1 = Interrupt in all vendor alarms - - - Notes: - An interrupt was generated from status register ( See Global Chip-Wide LASI Vendor Interrupt Flags: Address 1E.FC01 ) and the corresponding mask register. ( See Global Interrupt LASI Mask: Address 1E.FF01 ) */ - unsigned int allVendorAlarmsInterrupt : 1; /* 1E.FC00.0 RO */ - /* 1 = Interrupt in all vendor alarms - */ - unsigned int reserved0 : 5; - /*! \brief 1E.FC00.6 RO GbE Standard Alarms Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.gbeStandardAlarmsInterrupt - - - - 1 = Interrupt in GbE standard alarms - - - Notes: - An interrupt was generated from the TGE core. */ - unsigned int gbeStandardAlarmsInterrupt : 1; /* 1E.FC00.6 RO */ - /* 1 = Interrupt in GbE standard alarms - */ - /*! \brief 1E.FC00.7 RO Autonegotiation Standard Alarms 2 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.autonegotiationStandardAlarms_2Interrupt - - - - 1 = Interrupt in Autonegotiation standard alarms 2 - - - Notes: - An interrupt was generated from status register ( See Autonegotiation 10GBASE-T Status Register - Address 7.21 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ - unsigned int autonegotiationStandardAlarms_2Interrupt : 1; /* 1E.FC00.7 RO */ - /* 1 = Interrupt in Autonegotiation standard alarms 2 - */ - /*! \brief 1E.FC00.8 RO Autonegotiation Standard Alarms 1 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.autonegotiationStandardAlarms_1Interrupt - - - - 1 = Interrupt in Autonegotiation standard alarms 1 - - - Notes: - An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See Autonegotiation Standard LASI Interrupt Mask 1: Address 7.D000 ) */ - unsigned int autonegotiationStandardAlarms_1Interrupt : 1; /* 1E.FC00.8 RO */ - /* 1 = Interrupt in Autonegotiation standard alarms 1 - */ - /*! \brief 1E.FC00.9 RO PHY XS Standard Alarms 2 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.phyXS_StandardAlarms_2Interrupt - - - - 1 = Interrupt in PHY XS standard alarms 2 - - - Notes: - An interrupt was generated from the status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ - unsigned int phyXS_StandardAlarms_2Interrupt : 1; /* 1E.FC00.9 RO */ - /* 1 = Interrupt in PHY XS standard alarms 2 - */ - /*! \brief 1E.FC00.A RO PHY XS Standard Alarms 1 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.phyXS_StandardAlarms_1Interrupt - - - - 1 = Interrupt in PHY XS standard alarms 1 - - - Notes: - An interrupt was generated from the status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ - unsigned int phyXS_StandardAlarms_1Interrupt : 1; /* 1E.FC00.A RO */ - /* 1 = Interrupt in PHY XS standard alarms 1 - */ - /*! \brief 1E.FC00.B RO PCS Standard Alarm 3 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.pcsStandardAlarm_3Interrupt - - - - 1 = Interrupt in PCS standard alarms 3 - - - Notes: - An interrupt was generated from status register ( See PCS 10GBASE-T Status 2 - Address 3.21 ) and the corresponding mask register. ( See PCS Standard Interrupt Mask 1 - Address 3.E021 ) */ - unsigned int pcsStandardAlarm_3Interrupt : 1; /* 1E.FC00.B RO */ - /* 1 = Interrupt in PCS standard alarms 3 - */ - /*! \brief 1E.FC00.C RO PCS Standard Alarm 2 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.pcsStandardAlarm_2Interrupt - - - - 1 = Interrupt in PCS standard alarms 2 - - - Notes: - An interrupt was generated from status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ - unsigned int pcsStandardAlarm_2Interrupt : 1; /* 1E.FC00.C RO */ - /* 1 = Interrupt in PCS standard alarms 2 - */ - /*! \brief 1E.FC00.D RO PCS Standard Alarm 1 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.pcsStandardAlarm_1Interrupt - - - - 1 = Interrupt in PCS standard alarms 1 - - - Notes: - An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ - unsigned int pcsStandardAlarm_1Interrupt : 1; /* 1E.FC00.D RO */ - /* 1 = Interrupt in PCS standard alarms 1 - */ - /*! \brief 1E.FC00.E RO PMA Standard Alarm 2 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.pmaStandardAlarm_2Interrupt - - - - 1 = Interrupt in PMA standard alarms 2 - - - Notes: - An interrupt was generated from either bit 1.8.B or 1.8.A. - An interrupt was generated from status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ - unsigned int pmaStandardAlarm_2Interrupt : 1; /* 1E.FC00.E RO */ - /* 1 = Interrupt in PMA standard alarms 2 - */ - /*! \brief 1E.FC00.F RO PMA Standard Alarm 1 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.pmaStandardAlarm_1Interrupt - - - - 1 = Interrupt in PMA standard alarms 1 - - - Notes: - An interrupt was generated from bit 1.1.2. - An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ - unsigned int pmaStandardAlarm_1Interrupt : 1; /* 1E.FC00.F RO */ - /* 1 = Interrupt in PMA standard alarms 1 - */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalChip_wideStandardInterruptFlags_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Chip-Wide Vendor Interrupt Flags: 1E.FC01 */ -/* Global Chip-Wide Vendor Interrupt Flags: 1E.FC01 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Chip-Wide Vendor Interrupt Flags */ - union - { - struct - { - /*! \brief 1E.FC01.0 RO Global Alarms 3 Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.globalAlarms_3Interrupt - - - - 1 = Interrupt in Global alarms 3 - - - Notes: - An interrupt was generated from status register ( See Global Vendor Alarms 2: Address 1E.CC01 ) and the corresponding mask register. ( See Global LASI Interrupt Mask 2: Address 1E.D401 ) */ - unsigned int globalAlarms_3Interrupt : 1; /* 1E.FC01.0 RO */ - /* 1 = Interrupt in Global alarms 3 - */ - /*! \brief 1E.FC01.1 RO Global Alarms 2 Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.globalAlarms_2Interrupt - - - - 1 = Interrupt in Global alarms 2 - - - Notes: - An interrupt was generated from status register ( See Global Alarms 2: Address 1E.CC01 ) and the corresponding mask register. ( See Global LASI Interrupt Mask 2: Address 1E.D401 ) */ - unsigned int globalAlarms_2Interrupt : 1; /* 1E.FC01.1 RO */ - /* 1 = Interrupt in Global alarms 2 - */ - /*! \brief 1E.FC01.2 RO Global Alarms 1 Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.globalAlarms_1Interrupt - - - - 1 = Interrupt in Global alarms 1 - - - Notes: - An interrupt was generated from status register ( See Global Vendor Alarms 1 - Address 1E.CC00 ) and the corresponding mask register. ( See Global Vendor Interrupt Mask - Address 1E.D400 ) */ - unsigned int globalAlarms_1Interrupt : 1; /* 1E.FC01.2 RO */ - /* 1 = Interrupt in Global alarms 1 - */ - unsigned int reserved0 : 8; - /*! \brief 1E.FC01.B RO GbE Vendor Alarm Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.gbeVendorAlarmInterrupt - - - - 1 = Interrupt in GbE vendor specific alarm - - - Notes: - A GbE alarm was generated. ( See GbE PHY Vendor Global LASI Interrupt Flags 1: Address 1D.FC00 ) */ - unsigned int gbeVendorAlarmInterrupt : 1; /* 1E.FC01.B RO */ - /* 1 = Interrupt in GbE vendor specific alarm - */ - /*! \brief 1E.FC01.C RO Autonegotiation Vendor Alarm Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.autonegotiationVendorAlarmInterrupt - - - - 1 = Interrupt in Autonegotiation vendor specific alarm - - - Notes: - An Autonegotiation alarm was generated. ( See Autonegotiation Vendor Global LASI Interrupt Flags 1: Address 7.FC00 ) */ - unsigned int autonegotiationVendorAlarmInterrupt : 1; /* 1E.FC01.C RO */ - /* 1 = Interrupt in Autonegotiation vendor specific alarm - */ - /*! \brief 1E.FC01.D RO PHY XS Vendor Alarm Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.phyXS_VendorAlarmInterrupt - - - - 1 = Interrupt in PHY XS vendor specific alarm - - - Notes: - A PHY XS alarm was generated. ( See PHY XS Vendor Global LASI Interrupt Flags 1: Address 4.FC00 ) */ - unsigned int phyXS_VendorAlarmInterrupt : 1; /* 1E.FC01.D RO */ - /* 1 = Interrupt in PHY XS vendor specific alarm - */ - /*! \brief 1E.FC01.E RO PCS Vendor Alarm Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.pcsVendorAlarmInterrupt - - - - 1 = Interrupt in PCS vendor specific alarm - - - Notes: - A PCS alarm was generated. ( See PHY XS Vendor Global Interrupt Flags 1- Address 4.F800 ) */ - unsigned int pcsVendorAlarmInterrupt : 1; /* 1E.FC01.E RO */ - /* 1 = Interrupt in PCS vendor specific alarm - */ - /*! \brief 1E.FC01.F RO PMA Vendor Alarm Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.pmaVendorAlarmInterrupt - - - - 1 = Interrupt in PMA vendor specific alarm - - - Notes: - A PMA alarm was generated. ( See PHY XS Vendor Global Interrupt Flags 1- Address 4.F800 ) */ - unsigned int pmaVendorAlarmInterrupt : 1; /* 1E.FC01.F RO */ - /* 1 = Interrupt in PMA vendor specific alarm - */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalChip_wideVendorInterruptFlags_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Interrupt Chip-Wide Standard Mask: 1E.FF00 */ -/* Global Interrupt Chip-Wide Standard Mask: 1E.FF00 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Interrupt Chip-Wide Standard Mask */ - union - { - struct - { - /*! \brief 1E.FF00.0 R/WPD All Vendor Alarms Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.allVendorAlarmsInterruptMask - - Provisionable Default = 0x1 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int allVendorAlarmsInterruptMask : 1; /* 1E.FF00.0 R/WPD Provisionable Default = 0x1 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - unsigned int reserved0 : 5; - /*! \brief 1E.FF00.6 R/WPD Gbe Standard Alarms Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.gbeStandardAlarmsInterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int gbeStandardAlarmsInterruptMask : 1; /* 1E.FF00.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.7 R/WPD Autonegotiation Standard Alarms 2 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.autonegotiationStandardAlarms_2InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int autonegotiationStandardAlarms_2InterruptMask : 1; /* 1E.FF00.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.8 R/WPD Autonegotiation Standard Alarms 1 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.autonegotiationStandardAlarms_1InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int autonegotiationStandardAlarms_1InterruptMask : 1; /* 1E.FF00.8 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.9 R/WPD PHY XS Standard Alarms 2 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.phyXS_StandardAlarms_2InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int phyXS_StandardAlarms_2InterruptMask : 1; /* 1E.FF00.9 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.A R/WPD PHY XS Standard Alarms 1 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.phyXS_StandardAlarms_1InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int phyXS_StandardAlarms_1InterruptMask : 1; /* 1E.FF00.A R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.B R/WPD PCS Standard Alarm 3 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.pcsStandardAlarm_3InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int pcsStandardAlarm_3InterruptMask : 1; /* 1E.FF00.B R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.C R/WPD PCS Standard Alarm 2 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.pcsStandardAlarm_2InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int pcsStandardAlarm_2InterruptMask : 1; /* 1E.FF00.C R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.D R/WPD PCS Standard Alarm 1 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.pcsStandardAlarm_1InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int pcsStandardAlarm_1InterruptMask : 1; /* 1E.FF00.D R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.E R/WPD PMA Standard Alarm 2 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.pmaStandardAlarm_2InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int pmaStandardAlarm_2InterruptMask : 1; /* 1E.FF00.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.F R/WPD PMA Standard Alarm 1 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.pmaStandardAlarm_1InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int pmaStandardAlarm_1InterruptMask : 1; /* 1E.FF00.F R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalInterruptChip_wideStandardMask_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Interrupt Chip-Wide Vendor Mask: 1E.FF01 */ -/* Global Interrupt Chip-Wide Vendor Mask: 1E.FF01 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Interrupt Chip-Wide Vendor Mask */ - union - { - struct - { - /*! \brief 1E.FF01.0 R/WPD Global Alarms 3 Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.globalAlarms_3InterruptMask - - Provisionable Default = 0x1 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int globalAlarms_3InterruptMask : 1; /* 1E.FF01.0 R/WPD Provisionable Default = 0x1 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF01.1 R/WPD Global Alarms 2 Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.globalAlarms_2InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int globalAlarms_2InterruptMask : 1; /* 1E.FF01.1 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF01.2 R/WPD Global Alarms 1 Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.globalAlarms_1InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int globalAlarms_1InterruptMask : 1; /* 1E.FF01.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - unsigned int reserved0 : 8; - /*! \brief 1E.FF01.B R/WPD GbE Vendor Alarm Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.gbeVendorAlarmInterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int gbeVendorAlarmInterruptMask : 1; /* 1E.FF01.B R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF01.C R/WPD Autonegotiation Vendor Alarm Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.autonegotiationVendorAlarmInterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int autonegotiationVendorAlarmInterruptMask : 1; /* 1E.FF01.C R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF01.D R/WPD PHY XS Vendor Alarm Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.phyXS_VendorAlarmInterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int phyXS_VendorAlarmInterruptMask : 1; /* 1E.FF01.D R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF01.E R/WPD PCS Vendor Alarm Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.pcsVendorAlarmInterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int pcsVendorAlarmInterruptMask : 1; /* 1E.FF01.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF01.F R/WPD PMA Vendor Alarm Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.pmaVendorAlarmInterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int pmaVendorAlarmInterruptMask : 1; /* 1E.FF01.F R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalInterruptChip_wideVendorMask_APPIA; - -#endif -/*@}*/ -/*@}*/ diff --git a/qca/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers_Defines.h b/qca/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers_Defines.h deleted file mode 100644 index 9c7bb5cb5..000000000 --- a/qca/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers_Defines.h +++ /dev/null @@ -1,2134 +0,0 @@ -/*! \file -* This file contains the compiler assist macros and doxygen comments -* for the Global Registers block. -*/ - -/*! \defgroup Global_registers_Defines Global Registers Defines -* This module contains the compiler assist macros and doxygen comments -* for the Global Registers block. -*/ -/*********************************************************************** -* Copyright (c) 2015, Aquantia -* -* Permission to use, copy, modify, and/or distribute this software for any -* purpose with or without fee is hereby granted, provided that the above -* copyright notice and this permission notice appear in all copies. -* -* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -* -* $File: //depot/icm/proj/Dena/rev1.0/c/Systems/tools/windows/regMapParser/src/gencheaders.py $ -* -* $Revision: #10 $ -* -* $DateTime: 2014/04/08 16:55:58 $ -* -* $Author: joshd $ -* -* $Label: $ -* -* Description: -* -* This file contains the compiler assist macros for the registers contained in the Global Registers block. -* -* -***********************************************************************/ - - -/*@{*/ -#ifndef AQ_APPIA_GLOBAL_REGS_DEFINES_HEADER -#define AQ_APPIA_GLOBAL_REGS_DEFINES_HEADER - - -/*-----------------------------------------------------------------------------*/ -/*Access macro definitions */ -/*-----------------------------------------------------------------------------*/ -/*! \brief Base register address of structure AQ_GlobalStandardControl_1_APPIA */ -#define AQ_GlobalStandardControl_1_APPIA_baseRegisterAddress 0x0000 -/*! \brief MMD address of structure AQ_GlobalStandardControl_1_APPIA */ -#define AQ_GlobalStandardControl_1_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure softReset in AQ_GlobalStandardControl_1_APPIA */ -#define AQ_GlobalStandardControl_1_APPIA_softReset 0 -/*! \brief Preprocessor variable to relate field to bit position in structure softReset in AQ_GlobalStandardControl_1_APPIA */ -#define bits_AQ_GlobalStandardControl_1_APPIA_softReset u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure softReset in AQ_GlobalStandardControl_1_APPIA */ -#define word_AQ_GlobalStandardControl_1_APPIA_softReset u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure hardReset in AQ_GlobalStandardControl_1_APPIA */ -#define AQ_GlobalStandardControl_1_APPIA_hardReset 0 -/*! \brief Preprocessor variable to relate field to bit position in structure hardReset in AQ_GlobalStandardControl_1_APPIA */ -#define bits_AQ_GlobalStandardControl_1_APPIA_hardReset u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure hardReset in AQ_GlobalStandardControl_1_APPIA */ -#define word_AQ_GlobalStandardControl_1_APPIA_hardReset u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure lowPower in AQ_GlobalStandardControl_1_APPIA */ -#define AQ_GlobalStandardControl_1_APPIA_lowPower 0 -/*! \brief Preprocessor variable to relate field to bit position in structure lowPower in AQ_GlobalStandardControl_1_APPIA */ -#define bits_AQ_GlobalStandardControl_1_APPIA_lowPower u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure lowPower in AQ_GlobalStandardControl_1_APPIA */ -#define word_AQ_GlobalStandardControl_1_APPIA_lowPower u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalStandardDeviceIdentifier_APPIA */ -#define AQ_GlobalStandardDeviceIdentifier_APPIA_baseRegisterAddress 0x0002 -/*! \brief MMD address of structure AQ_GlobalStandardDeviceIdentifier_APPIA */ -#define AQ_GlobalStandardDeviceIdentifier_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure deviceIdMSW in AQ_GlobalStandardDeviceIdentifier_APPIA */ -#define AQ_GlobalStandardDeviceIdentifier_APPIA_deviceIdMSW 0 -/*! \brief Preprocessor variable to relate field to bit position in structure deviceIdMSW in AQ_GlobalStandardDeviceIdentifier_APPIA */ -#define bits_AQ_GlobalStandardDeviceIdentifier_APPIA_deviceIdMSW u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure deviceIdMSW in AQ_GlobalStandardDeviceIdentifier_APPIA */ -#define word_AQ_GlobalStandardDeviceIdentifier_APPIA_deviceIdMSW u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure deviceIdLSW in AQ_GlobalStandardDeviceIdentifier_APPIA */ -#define AQ_GlobalStandardDeviceIdentifier_APPIA_deviceIdLSW 1 -/*! \brief Preprocessor variable to relate field to bit position in structure deviceIdLSW in AQ_GlobalStandardDeviceIdentifier_APPIA */ -#define bits_AQ_GlobalStandardDeviceIdentifier_APPIA_deviceIdLSW u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure deviceIdLSW in AQ_GlobalStandardDeviceIdentifier_APPIA */ -#define word_AQ_GlobalStandardDeviceIdentifier_APPIA_deviceIdLSW u1.word_1 - -/*! \brief Base register address of structure AQ_GlobalStandardDevicesInPackage_APPIA */ -#define AQ_GlobalStandardDevicesInPackage_APPIA_baseRegisterAddress 0x0005 -/*! \brief MMD address of structure AQ_GlobalStandardDevicesInPackage_APPIA */ -#define AQ_GlobalStandardDevicesInPackage_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ -#define AQ_GlobalStandardDevicesInPackage_APPIA_autonegotiationPresent 0 -/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ -#define bits_AQ_GlobalStandardDevicesInPackage_APPIA_autonegotiationPresent u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ -#define word_AQ_GlobalStandardDevicesInPackage_APPIA_autonegotiationPresent u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure tcPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ -#define AQ_GlobalStandardDevicesInPackage_APPIA_tcPresent 0 -/*! \brief Preprocessor variable to relate field to bit position in structure tcPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ -#define bits_AQ_GlobalStandardDevicesInPackage_APPIA_tcPresent u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure tcPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ -#define word_AQ_GlobalStandardDevicesInPackage_APPIA_tcPresent u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure dteXsPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ -#define AQ_GlobalStandardDevicesInPackage_APPIA_dteXsPresent 0 -/*! \brief Preprocessor variable to relate field to bit position in structure dteXsPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ -#define bits_AQ_GlobalStandardDevicesInPackage_APPIA_dteXsPresent u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure dteXsPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ -#define word_AQ_GlobalStandardDevicesInPackage_APPIA_dteXsPresent u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure phyXS_Present in AQ_GlobalStandardDevicesInPackage_APPIA */ -#define AQ_GlobalStandardDevicesInPackage_APPIA_phyXS_Present 0 -/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_Present in AQ_GlobalStandardDevicesInPackage_APPIA */ -#define bits_AQ_GlobalStandardDevicesInPackage_APPIA_phyXS_Present u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure phyXS_Present in AQ_GlobalStandardDevicesInPackage_APPIA */ -#define word_AQ_GlobalStandardDevicesInPackage_APPIA_phyXS_Present u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pcsPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ -#define AQ_GlobalStandardDevicesInPackage_APPIA_pcsPresent 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pcsPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ -#define bits_AQ_GlobalStandardDevicesInPackage_APPIA_pcsPresent u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pcsPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ -#define word_AQ_GlobalStandardDevicesInPackage_APPIA_pcsPresent u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure wisPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ -#define AQ_GlobalStandardDevicesInPackage_APPIA_wisPresent 0 -/*! \brief Preprocessor variable to relate field to bit position in structure wisPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ -#define bits_AQ_GlobalStandardDevicesInPackage_APPIA_wisPresent u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure wisPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ -#define word_AQ_GlobalStandardDevicesInPackage_APPIA_wisPresent u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pmaPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ -#define AQ_GlobalStandardDevicesInPackage_APPIA_pmaPresent 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pmaPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ -#define bits_AQ_GlobalStandardDevicesInPackage_APPIA_pmaPresent u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pmaPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ -#define word_AQ_GlobalStandardDevicesInPackage_APPIA_pmaPresent u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure clause_22RegistersPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ -#define AQ_GlobalStandardDevicesInPackage_APPIA_clause_22RegistersPresent 0 -/*! \brief Preprocessor variable to relate field to bit position in structure clause_22RegistersPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ -#define bits_AQ_GlobalStandardDevicesInPackage_APPIA_clause_22RegistersPresent u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure clause_22RegistersPresent in AQ_GlobalStandardDevicesInPackage_APPIA */ -#define word_AQ_GlobalStandardDevicesInPackage_APPIA_clause_22RegistersPresent u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalStandardVendorDevicesInPackage_APPIA */ -#define AQ_GlobalStandardVendorDevicesInPackage_APPIA_baseRegisterAddress 0x0006 -/*! \brief MMD address of structure AQ_GlobalStandardVendorDevicesInPackage_APPIA */ -#define AQ_GlobalStandardVendorDevicesInPackage_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure vendorSpecificDevice_2Present in AQ_GlobalStandardVendorDevicesInPackage_APPIA */ -#define AQ_GlobalStandardVendorDevicesInPackage_APPIA_vendorSpecificDevice_2Present 0 -/*! \brief Preprocessor variable to relate field to bit position in structure vendorSpecificDevice_2Present in AQ_GlobalStandardVendorDevicesInPackage_APPIA */ -#define bits_AQ_GlobalStandardVendorDevicesInPackage_APPIA_vendorSpecificDevice_2Present u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure vendorSpecificDevice_2Present in AQ_GlobalStandardVendorDevicesInPackage_APPIA */ -#define word_AQ_GlobalStandardVendorDevicesInPackage_APPIA_vendorSpecificDevice_2Present u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure vendorSpecificDevice_1Present in AQ_GlobalStandardVendorDevicesInPackage_APPIA */ -#define AQ_GlobalStandardVendorDevicesInPackage_APPIA_vendorSpecificDevice_1Present 0 -/*! \brief Preprocessor variable to relate field to bit position in structure vendorSpecificDevice_1Present in AQ_GlobalStandardVendorDevicesInPackage_APPIA */ -#define bits_AQ_GlobalStandardVendorDevicesInPackage_APPIA_vendorSpecificDevice_1Present u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure vendorSpecificDevice_1Present in AQ_GlobalStandardVendorDevicesInPackage_APPIA */ -#define word_AQ_GlobalStandardVendorDevicesInPackage_APPIA_vendorSpecificDevice_1Present u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure clause_22ExtensionPresent in AQ_GlobalStandardVendorDevicesInPackage_APPIA */ -#define AQ_GlobalStandardVendorDevicesInPackage_APPIA_clause_22ExtensionPresent 0 -/*! \brief Preprocessor variable to relate field to bit position in structure clause_22ExtensionPresent in AQ_GlobalStandardVendorDevicesInPackage_APPIA */ -#define bits_AQ_GlobalStandardVendorDevicesInPackage_APPIA_clause_22ExtensionPresent u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure clause_22ExtensionPresent in AQ_GlobalStandardVendorDevicesInPackage_APPIA */ -#define word_AQ_GlobalStandardVendorDevicesInPackage_APPIA_clause_22ExtensionPresent u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalStandardStatus_2_APPIA */ -#define AQ_GlobalStandardStatus_2_APPIA_baseRegisterAddress 0x0008 -/*! \brief MMD address of structure AQ_GlobalStandardStatus_2_APPIA */ -#define AQ_GlobalStandardStatus_2_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure devicePresent in AQ_GlobalStandardStatus_2_APPIA */ -#define AQ_GlobalStandardStatus_2_APPIA_devicePresent 0 -/*! \brief Preprocessor variable to relate field to bit position in structure devicePresent in AQ_GlobalStandardStatus_2_APPIA */ -#define bits_AQ_GlobalStandardStatus_2_APPIA_devicePresent u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure devicePresent in AQ_GlobalStandardStatus_2_APPIA */ -#define word_AQ_GlobalStandardStatus_2_APPIA_devicePresent u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalStandardPackageIdentifier_APPIA */ -#define AQ_GlobalStandardPackageIdentifier_APPIA_baseRegisterAddress 0x000E -/*! \brief MMD address of structure AQ_GlobalStandardPackageIdentifier_APPIA */ -#define AQ_GlobalStandardPackageIdentifier_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure packageIdMSW in AQ_GlobalStandardPackageIdentifier_APPIA */ -#define AQ_GlobalStandardPackageIdentifier_APPIA_packageIdMSW 0 -/*! \brief Preprocessor variable to relate field to bit position in structure packageIdMSW in AQ_GlobalStandardPackageIdentifier_APPIA */ -#define bits_AQ_GlobalStandardPackageIdentifier_APPIA_packageIdMSW u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure packageIdMSW in AQ_GlobalStandardPackageIdentifier_APPIA */ -#define word_AQ_GlobalStandardPackageIdentifier_APPIA_packageIdMSW u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure packageIdLSW in AQ_GlobalStandardPackageIdentifier_APPIA */ -#define AQ_GlobalStandardPackageIdentifier_APPIA_packageIdLSW 1 -/*! \brief Preprocessor variable to relate field to bit position in structure packageIdLSW in AQ_GlobalStandardPackageIdentifier_APPIA */ -#define bits_AQ_GlobalStandardPackageIdentifier_APPIA_packageIdLSW u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure packageIdLSW in AQ_GlobalStandardPackageIdentifier_APPIA */ -#define word_AQ_GlobalStandardPackageIdentifier_APPIA_packageIdLSW u1.word_1 - -/*! \brief Base register address of structure AQ_GlobalFirmwareID_APPIA */ -#define AQ_GlobalFirmwareID_APPIA_baseRegisterAddress 0x0020 -/*! \brief MMD address of structure AQ_GlobalFirmwareID_APPIA */ -#define AQ_GlobalFirmwareID_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure firmwareMajorRevisionNumber in AQ_GlobalFirmwareID_APPIA */ -#define AQ_GlobalFirmwareID_APPIA_firmwareMajorRevisionNumber 0 -/*! \brief Preprocessor variable to relate field to bit position in structure firmwareMajorRevisionNumber in AQ_GlobalFirmwareID_APPIA */ -#define bits_AQ_GlobalFirmwareID_APPIA_firmwareMajorRevisionNumber u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure firmwareMajorRevisionNumber in AQ_GlobalFirmwareID_APPIA */ -#define word_AQ_GlobalFirmwareID_APPIA_firmwareMajorRevisionNumber u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure firmwareMinorRevisionNumber in AQ_GlobalFirmwareID_APPIA */ -#define AQ_GlobalFirmwareID_APPIA_firmwareMinorRevisionNumber 0 -/*! \brief Preprocessor variable to relate field to bit position in structure firmwareMinorRevisionNumber in AQ_GlobalFirmwareID_APPIA */ -#define bits_AQ_GlobalFirmwareID_APPIA_firmwareMinorRevisionNumber u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure firmwareMinorRevisionNumber in AQ_GlobalFirmwareID_APPIA */ -#define word_AQ_GlobalFirmwareID_APPIA_firmwareMinorRevisionNumber u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalChipIdentification_APPIA */ -#define AQ_GlobalChipIdentification_APPIA_baseRegisterAddress 0x0021 -/*! \brief MMD address of structure AQ_GlobalChipIdentification_APPIA */ -#define AQ_GlobalChipIdentification_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure chipIdentification in AQ_GlobalChipIdentification_APPIA */ -#define AQ_GlobalChipIdentification_APPIA_chipIdentification 0 -/*! \brief Preprocessor variable to relate field to bit position in structure chipIdentification in AQ_GlobalChipIdentification_APPIA */ -#define bits_AQ_GlobalChipIdentification_APPIA_chipIdentification u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure chipIdentification in AQ_GlobalChipIdentification_APPIA */ -#define word_AQ_GlobalChipIdentification_APPIA_chipIdentification u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalChipRevision_APPIA */ -#define AQ_GlobalChipRevision_APPIA_baseRegisterAddress 0x0022 -/*! \brief MMD address of structure AQ_GlobalChipRevision_APPIA */ -#define AQ_GlobalChipRevision_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure chipRevision in AQ_GlobalChipRevision_APPIA */ -#define AQ_GlobalChipRevision_APPIA_chipRevision 0 -/*! \brief Preprocessor variable to relate field to bit position in structure chipRevision in AQ_GlobalChipRevision_APPIA */ -#define bits_AQ_GlobalChipRevision_APPIA_chipRevision u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure chipRevision in AQ_GlobalChipRevision_APPIA */ -#define word_AQ_GlobalChipRevision_APPIA_chipRevision u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalNvrInterface_APPIA */ -#define AQ_GlobalNvrInterface_APPIA_baseRegisterAddress 0x0100 -/*! \brief MMD address of structure AQ_GlobalNvrInterface_APPIA */ -#define AQ_GlobalNvrInterface_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure nvrExecuteOperation in AQ_GlobalNvrInterface_APPIA */ -#define AQ_GlobalNvrInterface_APPIA_nvrExecuteOperation 0 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrExecuteOperation in AQ_GlobalNvrInterface_APPIA */ -#define bits_AQ_GlobalNvrInterface_APPIA_nvrExecuteOperation u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure nvrExecuteOperation in AQ_GlobalNvrInterface_APPIA */ -#define word_AQ_GlobalNvrInterface_APPIA_nvrExecuteOperation u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure nvrWriteMode in AQ_GlobalNvrInterface_APPIA */ -#define AQ_GlobalNvrInterface_APPIA_nvrWriteMode 0 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrWriteMode in AQ_GlobalNvrInterface_APPIA */ -#define bits_AQ_GlobalNvrInterface_APPIA_nvrWriteMode u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure nvrWriteMode in AQ_GlobalNvrInterface_APPIA */ -#define word_AQ_GlobalNvrInterface_APPIA_nvrWriteMode u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure freezeNvrCrc in AQ_GlobalNvrInterface_APPIA */ -#define AQ_GlobalNvrInterface_APPIA_freezeNvrCrc 0 -/*! \brief Preprocessor variable to relate field to bit position in structure freezeNvrCrc in AQ_GlobalNvrInterface_APPIA */ -#define bits_AQ_GlobalNvrInterface_APPIA_freezeNvrCrc u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure freezeNvrCrc in AQ_GlobalNvrInterface_APPIA */ -#define word_AQ_GlobalNvrInterface_APPIA_freezeNvrCrc u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure resetNvrCrc in AQ_GlobalNvrInterface_APPIA */ -#define AQ_GlobalNvrInterface_APPIA_resetNvrCrc 0 -/*! \brief Preprocessor variable to relate field to bit position in structure resetNvrCrc in AQ_GlobalNvrInterface_APPIA */ -#define bits_AQ_GlobalNvrInterface_APPIA_resetNvrCrc u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure resetNvrCrc in AQ_GlobalNvrInterface_APPIA */ -#define word_AQ_GlobalNvrInterface_APPIA_resetNvrCrc u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure nvrBurst in AQ_GlobalNvrInterface_APPIA */ -#define AQ_GlobalNvrInterface_APPIA_nvrBurst 0 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrBurst in AQ_GlobalNvrInterface_APPIA */ -#define bits_AQ_GlobalNvrInterface_APPIA_nvrBurst u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure nvrBurst in AQ_GlobalNvrInterface_APPIA */ -#define word_AQ_GlobalNvrInterface_APPIA_nvrBurst u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure nvrBusy in AQ_GlobalNvrInterface_APPIA */ -#define AQ_GlobalNvrInterface_APPIA_nvrBusy 0 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrBusy in AQ_GlobalNvrInterface_APPIA */ -#define bits_AQ_GlobalNvrInterface_APPIA_nvrBusy u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure nvrBusy in AQ_GlobalNvrInterface_APPIA */ -#define word_AQ_GlobalNvrInterface_APPIA_nvrBusy u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure nvrOpcode in AQ_GlobalNvrInterface_APPIA */ -#define AQ_GlobalNvrInterface_APPIA_nvrOpcode 0 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrOpcode in AQ_GlobalNvrInterface_APPIA */ -#define bits_AQ_GlobalNvrInterface_APPIA_nvrOpcode u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure nvrOpcode in AQ_GlobalNvrInterface_APPIA */ -#define word_AQ_GlobalNvrInterface_APPIA_nvrOpcode u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure nvrMailboxCrc in AQ_GlobalNvrInterface_APPIA */ -#define AQ_GlobalNvrInterface_APPIA_nvrMailboxCrc 1 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrMailboxCrc in AQ_GlobalNvrInterface_APPIA */ -#define bits_AQ_GlobalNvrInterface_APPIA_nvrMailboxCrc u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure nvrMailboxCrc in AQ_GlobalNvrInterface_APPIA */ -#define word_AQ_GlobalNvrInterface_APPIA_nvrMailboxCrc u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure nvrAddressMSW in AQ_GlobalNvrInterface_APPIA */ -#define AQ_GlobalNvrInterface_APPIA_nvrAddressMSW 2 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrAddressMSW in AQ_GlobalNvrInterface_APPIA */ -#define bits_AQ_GlobalNvrInterface_APPIA_nvrAddressMSW u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure nvrAddressMSW in AQ_GlobalNvrInterface_APPIA */ -#define word_AQ_GlobalNvrInterface_APPIA_nvrAddressMSW u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure nvrAddressLSW in AQ_GlobalNvrInterface_APPIA */ -#define AQ_GlobalNvrInterface_APPIA_nvrAddressLSW 3 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrAddressLSW in AQ_GlobalNvrInterface_APPIA */ -#define bits_AQ_GlobalNvrInterface_APPIA_nvrAddressLSW u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure nvrAddressLSW in AQ_GlobalNvrInterface_APPIA */ -#define word_AQ_GlobalNvrInterface_APPIA_nvrAddressLSW u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure nvrDataMSW in AQ_GlobalNvrInterface_APPIA */ -#define AQ_GlobalNvrInterface_APPIA_nvrDataMSW 4 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrDataMSW in AQ_GlobalNvrInterface_APPIA */ -#define bits_AQ_GlobalNvrInterface_APPIA_nvrDataMSW u4.bits_4 -/*! \brief Preprocessor variable to relate field to word position in structure nvrDataMSW in AQ_GlobalNvrInterface_APPIA */ -#define word_AQ_GlobalNvrInterface_APPIA_nvrDataMSW u4.word_4 -/*! \brief Preprocessor variable to relate field to word number in structure nvrDataLSW in AQ_GlobalNvrInterface_APPIA */ -#define AQ_GlobalNvrInterface_APPIA_nvrDataLSW 5 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrDataLSW in AQ_GlobalNvrInterface_APPIA */ -#define bits_AQ_GlobalNvrInterface_APPIA_nvrDataLSW u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure nvrDataLSW in AQ_GlobalNvrInterface_APPIA */ -#define word_AQ_GlobalNvrInterface_APPIA_nvrDataLSW u5.word_5 - -/*! \brief Base register address of structure AQ_GlobalMailboxInterface_APPIA */ -#define AQ_GlobalMailboxInterface_APPIA_baseRegisterAddress 0x0200 -/*! \brief MMD address of structure AQ_GlobalMailboxInterface_APPIA */ -#define AQ_GlobalMailboxInterface_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure upMailboxExecuteOperation in AQ_GlobalMailboxInterface_APPIA */ -#define AQ_GlobalMailboxInterface_APPIA_upMailboxExecuteOperation 0 -/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxExecuteOperation in AQ_GlobalMailboxInterface_APPIA */ -#define bits_AQ_GlobalMailboxInterface_APPIA_upMailboxExecuteOperation u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure upMailboxExecuteOperation in AQ_GlobalMailboxInterface_APPIA */ -#define word_AQ_GlobalMailboxInterface_APPIA_upMailboxExecuteOperation u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure upMailboxWriteMode in AQ_GlobalMailboxInterface_APPIA */ -#define AQ_GlobalMailboxInterface_APPIA_upMailboxWriteMode 0 -/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxWriteMode in AQ_GlobalMailboxInterface_APPIA */ -#define bits_AQ_GlobalMailboxInterface_APPIA_upMailboxWriteMode u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure upMailboxWriteMode in AQ_GlobalMailboxInterface_APPIA */ -#define word_AQ_GlobalMailboxInterface_APPIA_upMailboxWriteMode u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure resetUpMailboxCrc in AQ_GlobalMailboxInterface_APPIA */ -#define AQ_GlobalMailboxInterface_APPIA_resetUpMailboxCrc 0 -/*! \brief Preprocessor variable to relate field to bit position in structure resetUpMailboxCrc in AQ_GlobalMailboxInterface_APPIA */ -#define bits_AQ_GlobalMailboxInterface_APPIA_resetUpMailboxCrc u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure resetUpMailboxCrc in AQ_GlobalMailboxInterface_APPIA */ -#define word_AQ_GlobalMailboxInterface_APPIA_resetUpMailboxCrc u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure upMailboxBusy in AQ_GlobalMailboxInterface_APPIA */ -#define AQ_GlobalMailboxInterface_APPIA_upMailboxBusy 0 -/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxBusy in AQ_GlobalMailboxInterface_APPIA */ -#define bits_AQ_GlobalMailboxInterface_APPIA_upMailboxBusy u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure upMailboxBusy in AQ_GlobalMailboxInterface_APPIA */ -#define word_AQ_GlobalMailboxInterface_APPIA_upMailboxBusy u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure upMailboxCrc in AQ_GlobalMailboxInterface_APPIA */ -#define AQ_GlobalMailboxInterface_APPIA_upMailboxCrc 1 -/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxCrc in AQ_GlobalMailboxInterface_APPIA */ -#define bits_AQ_GlobalMailboxInterface_APPIA_upMailboxCrc u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure upMailboxCrc in AQ_GlobalMailboxInterface_APPIA */ -#define word_AQ_GlobalMailboxInterface_APPIA_upMailboxCrc u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure upMailboxAddressMSW in AQ_GlobalMailboxInterface_APPIA */ -#define AQ_GlobalMailboxInterface_APPIA_upMailboxAddressMSW 2 -/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxAddressMSW in AQ_GlobalMailboxInterface_APPIA */ -#define bits_AQ_GlobalMailboxInterface_APPIA_upMailboxAddressMSW u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure upMailboxAddressMSW in AQ_GlobalMailboxInterface_APPIA */ -#define word_AQ_GlobalMailboxInterface_APPIA_upMailboxAddressMSW u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure upMailboxAddressLSW in AQ_GlobalMailboxInterface_APPIA */ -#define AQ_GlobalMailboxInterface_APPIA_upMailboxAddressLSW 3 -/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxAddressLSW in AQ_GlobalMailboxInterface_APPIA */ -#define bits_AQ_GlobalMailboxInterface_APPIA_upMailboxAddressLSW u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure upMailboxAddressLSW in AQ_GlobalMailboxInterface_APPIA */ -#define word_AQ_GlobalMailboxInterface_APPIA_upMailboxAddressLSW u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure upMailboxAddressLSW_Don_tCare in AQ_GlobalMailboxInterface_APPIA */ -#define AQ_GlobalMailboxInterface_APPIA_upMailboxAddressLSW_Don_tCare 3 -/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxAddressLSW_Don_tCare in AQ_GlobalMailboxInterface_APPIA */ -#define bits_AQ_GlobalMailboxInterface_APPIA_upMailboxAddressLSW_Don_tCare u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure upMailboxAddressLSW_Don_tCare in AQ_GlobalMailboxInterface_APPIA */ -#define word_AQ_GlobalMailboxInterface_APPIA_upMailboxAddressLSW_Don_tCare u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure upMailboxDataMSW in AQ_GlobalMailboxInterface_APPIA */ -#define AQ_GlobalMailboxInterface_APPIA_upMailboxDataMSW 4 -/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxDataMSW in AQ_GlobalMailboxInterface_APPIA */ -#define bits_AQ_GlobalMailboxInterface_APPIA_upMailboxDataMSW u4.bits_4 -/*! \brief Preprocessor variable to relate field to word position in structure upMailboxDataMSW in AQ_GlobalMailboxInterface_APPIA */ -#define word_AQ_GlobalMailboxInterface_APPIA_upMailboxDataMSW u4.word_4 -/*! \brief Preprocessor variable to relate field to word number in structure upMailboxDataLSW in AQ_GlobalMailboxInterface_APPIA */ -#define AQ_GlobalMailboxInterface_APPIA_upMailboxDataLSW 5 -/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxDataLSW in AQ_GlobalMailboxInterface_APPIA */ -#define bits_AQ_GlobalMailboxInterface_APPIA_upMailboxDataLSW u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure upMailboxDataLSW in AQ_GlobalMailboxInterface_APPIA */ -#define word_AQ_GlobalMailboxInterface_APPIA_upMailboxDataLSW u5.word_5 - -/*! \brief Base register address of structure AQ_GlobalMicroprocessorScratchPad_APPIA */ -#define AQ_GlobalMicroprocessorScratchPad_APPIA_baseRegisterAddress 0x0300 -/*! \brief MMD address of structure AQ_GlobalMicroprocessorScratchPad_APPIA */ -#define AQ_GlobalMicroprocessorScratchPad_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure scratchPad_1 in AQ_GlobalMicroprocessorScratchPad_APPIA */ -#define AQ_GlobalMicroprocessorScratchPad_APPIA_scratchPad_1 0 -/*! \brief Preprocessor variable to relate field to bit position in structure scratchPad_1 in AQ_GlobalMicroprocessorScratchPad_APPIA */ -#define bits_AQ_GlobalMicroprocessorScratchPad_APPIA_scratchPad_1 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure scratchPad_1 in AQ_GlobalMicroprocessorScratchPad_APPIA */ -#define word_AQ_GlobalMicroprocessorScratchPad_APPIA_scratchPad_1 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure scratchPad_2 in AQ_GlobalMicroprocessorScratchPad_APPIA */ -#define AQ_GlobalMicroprocessorScratchPad_APPIA_scratchPad_2 1 -/*! \brief Preprocessor variable to relate field to bit position in structure scratchPad_2 in AQ_GlobalMicroprocessorScratchPad_APPIA */ -#define bits_AQ_GlobalMicroprocessorScratchPad_APPIA_scratchPad_2 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure scratchPad_2 in AQ_GlobalMicroprocessorScratchPad_APPIA */ -#define word_AQ_GlobalMicroprocessorScratchPad_APPIA_scratchPad_2 u1.word_1 - -/*! \brief Base register address of structure AQ_GlobalControl_APPIA */ -#define AQ_GlobalControl_APPIA_baseRegisterAddress 0xC000 -/*! \brief MMD address of structure AQ_GlobalControl_APPIA */ -#define AQ_GlobalControl_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure upReset in AQ_GlobalControl_APPIA */ -#define AQ_GlobalControl_APPIA_upReset 1 -/*! \brief Preprocessor variable to relate field to bit position in structure upReset in AQ_GlobalControl_APPIA */ -#define bits_AQ_GlobalControl_APPIA_upReset u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure upReset in AQ_GlobalControl_APPIA */ -#define word_AQ_GlobalControl_APPIA_upReset u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure upRunStallOverride in AQ_GlobalControl_APPIA */ -#define AQ_GlobalControl_APPIA_upRunStallOverride 1 -/*! \brief Preprocessor variable to relate field to bit position in structure upRunStallOverride in AQ_GlobalControl_APPIA */ -#define bits_AQ_GlobalControl_APPIA_upRunStallOverride u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure upRunStallOverride in AQ_GlobalControl_APPIA */ -#define word_AQ_GlobalControl_APPIA_upRunStallOverride u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure upRunStall in AQ_GlobalControl_APPIA */ -#define AQ_GlobalControl_APPIA_upRunStall 1 -/*! \brief Preprocessor variable to relate field to bit position in structure upRunStall in AQ_GlobalControl_APPIA */ -#define bits_AQ_GlobalControl_APPIA_upRunStall u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure upRunStall in AQ_GlobalControl_APPIA */ -#define word_AQ_GlobalControl_APPIA_upRunStall u1.word_1 - -/*! \brief Base register address of structure AQ_GlobalResetControl_APPIA */ -#define AQ_GlobalResetControl_APPIA_baseRegisterAddress 0xC006 -/*! \brief MMD address of structure AQ_GlobalResetControl_APPIA */ -#define AQ_GlobalResetControl_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure globalMMD_ResetDisable in AQ_GlobalResetControl_APPIA */ -#define AQ_GlobalResetControl_APPIA_globalMMD_ResetDisable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure globalMMD_ResetDisable in AQ_GlobalResetControl_APPIA */ -#define bits_AQ_GlobalResetControl_APPIA_globalMMD_ResetDisable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure globalMMD_ResetDisable in AQ_GlobalResetControl_APPIA */ -#define word_AQ_GlobalResetControl_APPIA_globalMMD_ResetDisable u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalDiagnosticProvisioning_APPIA */ -#define AQ_GlobalDiagnosticProvisioning_APPIA_baseRegisterAddress 0xC400 -/*! \brief MMD address of structure AQ_GlobalDiagnosticProvisioning_APPIA */ -#define AQ_GlobalDiagnosticProvisioning_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure enableDiagnostics in AQ_GlobalDiagnosticProvisioning_APPIA */ -#define AQ_GlobalDiagnosticProvisioning_APPIA_enableDiagnostics 0 -/*! \brief Preprocessor variable to relate field to bit position in structure enableDiagnostics in AQ_GlobalDiagnosticProvisioning_APPIA */ -#define bits_AQ_GlobalDiagnosticProvisioning_APPIA_enableDiagnostics u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure enableDiagnostics in AQ_GlobalDiagnosticProvisioning_APPIA */ -#define word_AQ_GlobalDiagnosticProvisioning_APPIA_enableDiagnostics u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalThermalProvisioning_APPIA */ -#define AQ_GlobalThermalProvisioning_APPIA_baseRegisterAddress 0xC420 -/*! \brief MMD address of structure AQ_GlobalThermalProvisioning_APPIA */ -#define AQ_GlobalThermalProvisioning_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure reserved_0 in AQ_GlobalThermalProvisioning_APPIA */ -#define AQ_GlobalThermalProvisioning_APPIA_reserved_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_0 in AQ_GlobalThermalProvisioning_APPIA */ -#define bits_AQ_GlobalThermalProvisioning_APPIA_reserved_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_0 in AQ_GlobalThermalProvisioning_APPIA */ -#define word_AQ_GlobalThermalProvisioning_APPIA_reserved_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure highTempFailureThreshold in AQ_GlobalThermalProvisioning_APPIA */ -#define AQ_GlobalThermalProvisioning_APPIA_highTempFailureThreshold 1 -/*! \brief Preprocessor variable to relate field to bit position in structure highTempFailureThreshold in AQ_GlobalThermalProvisioning_APPIA */ -#define bits_AQ_GlobalThermalProvisioning_APPIA_highTempFailureThreshold u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure highTempFailureThreshold in AQ_GlobalThermalProvisioning_APPIA */ -#define word_AQ_GlobalThermalProvisioning_APPIA_highTempFailureThreshold u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure lowTempFailureThreshold in AQ_GlobalThermalProvisioning_APPIA */ -#define AQ_GlobalThermalProvisioning_APPIA_lowTempFailureThreshold 2 -/*! \brief Preprocessor variable to relate field to bit position in structure lowTempFailureThreshold in AQ_GlobalThermalProvisioning_APPIA */ -#define bits_AQ_GlobalThermalProvisioning_APPIA_lowTempFailureThreshold u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure lowTempFailureThreshold in AQ_GlobalThermalProvisioning_APPIA */ -#define word_AQ_GlobalThermalProvisioning_APPIA_lowTempFailureThreshold u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure highTempWarningThreshold in AQ_GlobalThermalProvisioning_APPIA */ -#define AQ_GlobalThermalProvisioning_APPIA_highTempWarningThreshold 3 -/*! \brief Preprocessor variable to relate field to bit position in structure highTempWarningThreshold in AQ_GlobalThermalProvisioning_APPIA */ -#define bits_AQ_GlobalThermalProvisioning_APPIA_highTempWarningThreshold u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure highTempWarningThreshold in AQ_GlobalThermalProvisioning_APPIA */ -#define word_AQ_GlobalThermalProvisioning_APPIA_highTempWarningThreshold u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure lowTempWarningThreshold in AQ_GlobalThermalProvisioning_APPIA */ -#define AQ_GlobalThermalProvisioning_APPIA_lowTempWarningThreshold 4 -/*! \brief Preprocessor variable to relate field to bit position in structure lowTempWarningThreshold in AQ_GlobalThermalProvisioning_APPIA */ -#define bits_AQ_GlobalThermalProvisioning_APPIA_lowTempWarningThreshold u4.bits_4 -/*! \brief Preprocessor variable to relate field to word position in structure lowTempWarningThreshold in AQ_GlobalThermalProvisioning_APPIA */ -#define word_AQ_GlobalThermalProvisioning_APPIA_lowTempWarningThreshold u4.word_4 - -/*! \brief Base register address of structure AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_baseRegisterAddress 0xC430 -/*! \brief MMD address of structure AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure led_0ManualSet in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_0ManualSet 0 -/*! \brief Preprocessor variable to relate field to bit position in structure led_0ManualSet in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_0ManualSet u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure led_0ManualSet in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_0ManualSet u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure led_0_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_0_10Gb_sLinkEstablished 0 -/*! \brief Preprocessor variable to relate field to bit position in structure led_0_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_0_10Gb_sLinkEstablished u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure led_0_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_0_10Gb_sLinkEstablished u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure led_0_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_0_1Gb_sLinkEstablished 0 -/*! \brief Preprocessor variable to relate field to bit position in structure led_0_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_0_1Gb_sLinkEstablished u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure led_0_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_0_1Gb_sLinkEstablished u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure led_0_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_0_100Mb_sLinkEstablished 0 -/*! \brief Preprocessor variable to relate field to bit position in structure led_0_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_0_100Mb_sLinkEstablished u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure led_0_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_0_100Mb_sLinkEstablished u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure led_0Connecting in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_0Connecting 0 -/*! \brief Preprocessor variable to relate field to bit position in structure led_0Connecting in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_0Connecting u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure led_0Connecting in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_0Connecting u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure led_0ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_0ReceiveActivity 0 -/*! \brief Preprocessor variable to relate field to bit position in structure led_0ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_0ReceiveActivity u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure led_0ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_0ReceiveActivity u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure led_0TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_0TransmitActivity 0 -/*! \brief Preprocessor variable to relate field to bit position in structure led_0TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_0TransmitActivity u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure led_0TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_0TransmitActivity u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure led_0ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_0ActivityStretch 0 -/*! \brief Preprocessor variable to relate field to bit position in structure led_0ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_0ActivityStretch u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure led_0ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_0ActivityStretch u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure led_1ManualSet in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_1ManualSet 1 -/*! \brief Preprocessor variable to relate field to bit position in structure led_1ManualSet in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_1ManualSet u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure led_1ManualSet in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_1ManualSet u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure led_1_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_1_10Gb_sLinkEstablished 1 -/*! \brief Preprocessor variable to relate field to bit position in structure led_1_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_1_10Gb_sLinkEstablished u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure led_1_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_1_10Gb_sLinkEstablished u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure led_1_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_1_1Gb_sLinkEstablished 1 -/*! \brief Preprocessor variable to relate field to bit position in structure led_1_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_1_1Gb_sLinkEstablished u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure led_1_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_1_1Gb_sLinkEstablished u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure led_1_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_1_100Mb_sLinkEstablished 1 -/*! \brief Preprocessor variable to relate field to bit position in structure led_1_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_1_100Mb_sLinkEstablished u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure led_1_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_1_100Mb_sLinkEstablished u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure led_1Connecting in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_1Connecting 1 -/*! \brief Preprocessor variable to relate field to bit position in structure led_1Connecting in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_1Connecting u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure led_1Connecting in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_1Connecting u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure led_1ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_1ReceiveActivity 1 -/*! \brief Preprocessor variable to relate field to bit position in structure led_1ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_1ReceiveActivity u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure led_1ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_1ReceiveActivity u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure led_1TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_1TransmitActivity 1 -/*! \brief Preprocessor variable to relate field to bit position in structure led_1TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_1TransmitActivity u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure led_1TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_1TransmitActivity u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure led_1ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_1ActivityStretch 1 -/*! \brief Preprocessor variable to relate field to bit position in structure led_1ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_1ActivityStretch u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure led_1ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_1ActivityStretch u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure led_2ManualSet in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_2ManualSet 2 -/*! \brief Preprocessor variable to relate field to bit position in structure led_2ManualSet in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_2ManualSet u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure led_2ManualSet in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_2ManualSet u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure led_2_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_2_10Gb_sLinkEstablished 2 -/*! \brief Preprocessor variable to relate field to bit position in structure led_2_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_2_10Gb_sLinkEstablished u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure led_2_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_2_10Gb_sLinkEstablished u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure led_2_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_2_1Gb_sLinkEstablished 2 -/*! \brief Preprocessor variable to relate field to bit position in structure led_2_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_2_1Gb_sLinkEstablished u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure led_2_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_2_1Gb_sLinkEstablished u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure led_2_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_2_100Mb_sLinkEstablished 2 -/*! \brief Preprocessor variable to relate field to bit position in structure led_2_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_2_100Mb_sLinkEstablished u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure led_2_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_2_100Mb_sLinkEstablished u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure led_2Connecting in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_2Connecting 2 -/*! \brief Preprocessor variable to relate field to bit position in structure led_2Connecting in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_2Connecting u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure led_2Connecting in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_2Connecting u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure led_2ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_2ReceiveActivity 2 -/*! \brief Preprocessor variable to relate field to bit position in structure led_2ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_2ReceiveActivity u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure led_2ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_2ReceiveActivity u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure led_2TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_2TransmitActivity 2 -/*! \brief Preprocessor variable to relate field to bit position in structure led_2TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_2TransmitActivity u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure led_2TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_2TransmitActivity u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure led_2ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_2ActivityStretch 2 -/*! \brief Preprocessor variable to relate field to bit position in structure led_2ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_2ActivityStretch u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure led_2ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_2ActivityStretch u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure led_3ManualSet in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_3ManualSet 3 -/*! \brief Preprocessor variable to relate field to bit position in structure led_3ManualSet in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_3ManualSet u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure led_3ManualSet in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_3ManualSet u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure led_3_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_3_10Gb_sLinkEstablished 3 -/*! \brief Preprocessor variable to relate field to bit position in structure led_3_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_3_10Gb_sLinkEstablished u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure led_3_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_3_10Gb_sLinkEstablished u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure led_3_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_3_1Gb_sLinkEstablished 3 -/*! \brief Preprocessor variable to relate field to bit position in structure led_3_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_3_1Gb_sLinkEstablished u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure led_3_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_3_1Gb_sLinkEstablished u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure led_3_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_3_100Mb_sLinkEstablished 3 -/*! \brief Preprocessor variable to relate field to bit position in structure led_3_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_3_100Mb_sLinkEstablished u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure led_3_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_3_100Mb_sLinkEstablished u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure led_3Connecting in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_3Connecting 3 -/*! \brief Preprocessor variable to relate field to bit position in structure led_3Connecting in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_3Connecting u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure led_3Connecting in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_3Connecting u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure led_3ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_3ReceiveActivity 3 -/*! \brief Preprocessor variable to relate field to bit position in structure led_3ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_3ReceiveActivity u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure led_3ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_3ReceiveActivity u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure led_3TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_3TransmitActivity 3 -/*! \brief Preprocessor variable to relate field to bit position in structure led_3TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_3TransmitActivity u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure led_3TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_3TransmitActivity u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure led_3ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_3ActivityStretch 3 -/*! \brief Preprocessor variable to relate field to bit position in structure led_3ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_3ActivityStretch u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure led_3ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_3ActivityStretch u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure led_4ManualSet in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_4ManualSet 4 -/*! \brief Preprocessor variable to relate field to bit position in structure led_4ManualSet in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_4ManualSet u4.bits_4 -/*! \brief Preprocessor variable to relate field to word position in structure led_4ManualSet in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_4ManualSet u4.word_4 -/*! \brief Preprocessor variable to relate field to word number in structure led_4_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_4_10Gb_sLinkEstablished 4 -/*! \brief Preprocessor variable to relate field to bit position in structure led_4_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_4_10Gb_sLinkEstablished u4.bits_4 -/*! \brief Preprocessor variable to relate field to word position in structure led_4_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_4_10Gb_sLinkEstablished u4.word_4 -/*! \brief Preprocessor variable to relate field to word number in structure led_4_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_4_1Gb_sLinkEstablished 4 -/*! \brief Preprocessor variable to relate field to bit position in structure led_4_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_4_1Gb_sLinkEstablished u4.bits_4 -/*! \brief Preprocessor variable to relate field to word position in structure led_4_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_4_1Gb_sLinkEstablished u4.word_4 -/*! \brief Preprocessor variable to relate field to word number in structure led_4_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_4_100Mb_sLinkEstablished 4 -/*! \brief Preprocessor variable to relate field to bit position in structure led_4_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_4_100Mb_sLinkEstablished u4.bits_4 -/*! \brief Preprocessor variable to relate field to word position in structure led_4_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_4_100Mb_sLinkEstablished u4.word_4 -/*! \brief Preprocessor variable to relate field to word number in structure led_4Connecting in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_4Connecting 4 -/*! \brief Preprocessor variable to relate field to bit position in structure led_4Connecting in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_4Connecting u4.bits_4 -/*! \brief Preprocessor variable to relate field to word position in structure led_4Connecting in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_4Connecting u4.word_4 -/*! \brief Preprocessor variable to relate field to word number in structure led_4ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_4ReceiveActivity 4 -/*! \brief Preprocessor variable to relate field to bit position in structure led_4ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_4ReceiveActivity u4.bits_4 -/*! \brief Preprocessor variable to relate field to word position in structure led_4ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_4ReceiveActivity u4.word_4 -/*! \brief Preprocessor variable to relate field to word number in structure led_4TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_4TransmitActivity 4 -/*! \brief Preprocessor variable to relate field to bit position in structure led_4TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_4TransmitActivity u4.bits_4 -/*! \brief Preprocessor variable to relate field to word position in structure led_4TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_4TransmitActivity u4.word_4 -/*! \brief Preprocessor variable to relate field to word number in structure led_4ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_4ActivityStretch 4 -/*! \brief Preprocessor variable to relate field to bit position in structure led_4ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_4ActivityStretch u4.bits_4 -/*! \brief Preprocessor variable to relate field to word position in structure led_4ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_4ActivityStretch u4.word_4 -/*! \brief Preprocessor variable to relate field to word number in structure led_5ManualSet in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_5ManualSet 5 -/*! \brief Preprocessor variable to relate field to bit position in structure led_5ManualSet in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_5ManualSet u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure led_5ManualSet in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_5ManualSet u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure led_5_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_5_10Gb_sLinkEstablished 5 -/*! \brief Preprocessor variable to relate field to bit position in structure led_5_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_5_10Gb_sLinkEstablished u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure led_5_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_5_10Gb_sLinkEstablished u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure led_5_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_5_1Gb_sLinkEstablished 5 -/*! \brief Preprocessor variable to relate field to bit position in structure led_5_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_5_1Gb_sLinkEstablished u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure led_5_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_5_1Gb_sLinkEstablished u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure led_5_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_5_100Mb_sLinkEstablished 5 -/*! \brief Preprocessor variable to relate field to bit position in structure led_5_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_5_100Mb_sLinkEstablished u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure led_5_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_5_100Mb_sLinkEstablished u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure led_5Connecting in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_5Connecting 5 -/*! \brief Preprocessor variable to relate field to bit position in structure led_5Connecting in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_5Connecting u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure led_5Connecting in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_5Connecting u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure led_5ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_5ReceiveActivity 5 -/*! \brief Preprocessor variable to relate field to bit position in structure led_5ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_5ReceiveActivity u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure led_5ReceiveActivity in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_5ReceiveActivity u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure led_5TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_5TransmitActivity 5 -/*! \brief Preprocessor variable to relate field to bit position in structure led_5TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_5TransmitActivity u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure led_5TransmitActivity in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_5TransmitActivity u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure led_5ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_5ActivityStretch 5 -/*! \brief Preprocessor variable to relate field to bit position in structure led_5ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_5ActivityStretch u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure led_5ActivityStretch in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_5ActivityStretch u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure ledOperationMode in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_ledOperationMode 7 -/*! \brief Preprocessor variable to relate field to bit position in structure ledOperationMode in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_ledOperationMode u7.bits_7 -/*! \brief Preprocessor variable to relate field to word position in structure ledOperationMode in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_ledOperationMode u7.word_7 -/*! \brief Preprocessor variable to relate field to word number in structure led_0DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_0DriveThreeStateSelect 8 -/*! \brief Preprocessor variable to relate field to bit position in structure led_0DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_0DriveThreeStateSelect u8.bits_8 -/*! \brief Preprocessor variable to relate field to word position in structure led_0DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_0DriveThreeStateSelect u8.word_8 -/*! \brief Preprocessor variable to relate field to word number in structure led_0ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_0ActiveHighSelect 8 -/*! \brief Preprocessor variable to relate field to bit position in structure led_0ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_0ActiveHighSelect u8.bits_8 -/*! \brief Preprocessor variable to relate field to word position in structure led_0ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_0ActiveHighSelect u8.word_8 -/*! \brief Preprocessor variable to relate field to word number in structure led_0ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_0ManualActiveSelect 8 -/*! \brief Preprocessor variable to relate field to bit position in structure led_0ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_0ManualActiveSelect u8.bits_8 -/*! \brief Preprocessor variable to relate field to word position in structure led_0ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_0ManualActiveSelect u8.word_8 -/*! \brief Preprocessor variable to relate field to word number in structure led_1DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_1DriveThreeStateSelect 9 -/*! \brief Preprocessor variable to relate field to bit position in structure led_1DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_1DriveThreeStateSelect u9.bits_9 -/*! \brief Preprocessor variable to relate field to word position in structure led_1DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_1DriveThreeStateSelect u9.word_9 -/*! \brief Preprocessor variable to relate field to word number in structure led_1ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_1ActiveHighSelect 9 -/*! \brief Preprocessor variable to relate field to bit position in structure led_1ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_1ActiveHighSelect u9.bits_9 -/*! \brief Preprocessor variable to relate field to word position in structure led_1ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_1ActiveHighSelect u9.word_9 -/*! \brief Preprocessor variable to relate field to word number in structure led_1ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_1ManualActiveSelect 9 -/*! \brief Preprocessor variable to relate field to bit position in structure led_1ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_1ManualActiveSelect u9.bits_9 -/*! \brief Preprocessor variable to relate field to word position in structure led_1ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_1ManualActiveSelect u9.word_9 -/*! \brief Preprocessor variable to relate field to word number in structure led_2DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_2DriveThreeStateSelect 10 -/*! \brief Preprocessor variable to relate field to bit position in structure led_2DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_2DriveThreeStateSelect u10.bits_10 -/*! \brief Preprocessor variable to relate field to word position in structure led_2DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_2DriveThreeStateSelect u10.word_10 -/*! \brief Preprocessor variable to relate field to word number in structure led_2ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_2ActiveHighSelect 10 -/*! \brief Preprocessor variable to relate field to bit position in structure led_2ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_2ActiveHighSelect u10.bits_10 -/*! \brief Preprocessor variable to relate field to word position in structure led_2ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_2ActiveHighSelect u10.word_10 -/*! \brief Preprocessor variable to relate field to word number in structure led_2ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_2ManualActiveSelect 10 -/*! \brief Preprocessor variable to relate field to bit position in structure led_2ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_2ManualActiveSelect u10.bits_10 -/*! \brief Preprocessor variable to relate field to word position in structure led_2ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_2ManualActiveSelect u10.word_10 -/*! \brief Preprocessor variable to relate field to word number in structure led_3DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_3DriveThreeStateSelect 11 -/*! \brief Preprocessor variable to relate field to bit position in structure led_3DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_3DriveThreeStateSelect u11.bits_11 -/*! \brief Preprocessor variable to relate field to word position in structure led_3DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_3DriveThreeStateSelect u11.word_11 -/*! \brief Preprocessor variable to relate field to word number in structure led_3ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_3ActiveHighSelect 11 -/*! \brief Preprocessor variable to relate field to bit position in structure led_3ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_3ActiveHighSelect u11.bits_11 -/*! \brief Preprocessor variable to relate field to word position in structure led_3ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_3ActiveHighSelect u11.word_11 -/*! \brief Preprocessor variable to relate field to word number in structure led_3ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_3ManualActiveSelect 11 -/*! \brief Preprocessor variable to relate field to bit position in structure led_3ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_3ManualActiveSelect u11.bits_11 -/*! \brief Preprocessor variable to relate field to word position in structure led_3ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_3ManualActiveSelect u11.word_11 -/*! \brief Preprocessor variable to relate field to word number in structure led_4DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_4DriveThreeStateSelect 12 -/*! \brief Preprocessor variable to relate field to bit position in structure led_4DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_4DriveThreeStateSelect u12.bits_12 -/*! \brief Preprocessor variable to relate field to word position in structure led_4DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_4DriveThreeStateSelect u12.word_12 -/*! \brief Preprocessor variable to relate field to word number in structure led_4ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_4ActiveHighSelect 12 -/*! \brief Preprocessor variable to relate field to bit position in structure led_4ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_4ActiveHighSelect u12.bits_12 -/*! \brief Preprocessor variable to relate field to word position in structure led_4ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_4ActiveHighSelect u12.word_12 -/*! \brief Preprocessor variable to relate field to word number in structure led_4ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_4ManualActiveSelect 12 -/*! \brief Preprocessor variable to relate field to bit position in structure led_4ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_4ManualActiveSelect u12.bits_12 -/*! \brief Preprocessor variable to relate field to word position in structure led_4ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_4ManualActiveSelect u12.word_12 -/*! \brief Preprocessor variable to relate field to word number in structure led_5DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_5DriveThreeStateSelect 13 -/*! \brief Preprocessor variable to relate field to bit position in structure led_5DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_5DriveThreeStateSelect u13.bits_13 -/*! \brief Preprocessor variable to relate field to word position in structure led_5DriveThreeStateSelect in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_5DriveThreeStateSelect u13.word_13 -/*! \brief Preprocessor variable to relate field to word number in structure led_5ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_5ActiveHighSelect 13 -/*! \brief Preprocessor variable to relate field to bit position in structure led_5ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_5ActiveHighSelect u13.bits_13 -/*! \brief Preprocessor variable to relate field to word position in structure led_5ActiveHighSelect in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_5ActiveHighSelect u13.word_13 -/*! \brief Preprocessor variable to relate field to word number in structure led_5ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ -#define AQ_GlobalLedProvisioning_APPIA_led_5ManualActiveSelect 13 -/*! \brief Preprocessor variable to relate field to bit position in structure led_5ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ -#define bits_AQ_GlobalLedProvisioning_APPIA_led_5ManualActiveSelect u13.bits_13 -/*! \brief Preprocessor variable to relate field to word position in structure led_5ManualActiveSelect in AQ_GlobalLedProvisioning_APPIA */ -#define word_AQ_GlobalLedProvisioning_APPIA_led_5ManualActiveSelect u13.word_13 - -/*! \brief Base register address of structure AQ_GlobalGeneralProvisioning_APPIA */ -#define AQ_GlobalGeneralProvisioning_APPIA_baseRegisterAddress 0xC440 -/*! \brief MMD address of structure AQ_GlobalGeneralProvisioning_APPIA */ -#define AQ_GlobalGeneralProvisioning_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure gangLoadMdioAddress in AQ_GlobalGeneralProvisioning_APPIA */ -#define AQ_GlobalGeneralProvisioning_APPIA_gangLoadMdioAddress 0 -/*! \brief Preprocessor variable to relate field to bit position in structure gangLoadMdioAddress in AQ_GlobalGeneralProvisioning_APPIA */ -#define bits_AQ_GlobalGeneralProvisioning_APPIA_gangLoadMdioAddress u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure gangLoadMdioAddress in AQ_GlobalGeneralProvisioning_APPIA */ -#define word_AQ_GlobalGeneralProvisioning_APPIA_gangLoadMdioAddress u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure gangLoadMdioWriteOnly in AQ_GlobalGeneralProvisioning_APPIA */ -#define AQ_GlobalGeneralProvisioning_APPIA_gangLoadMdioWriteOnly 0 -/*! \brief Preprocessor variable to relate field to bit position in structure gangLoadMdioWriteOnly in AQ_GlobalGeneralProvisioning_APPIA */ -#define bits_AQ_GlobalGeneralProvisioning_APPIA_gangLoadMdioWriteOnly u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure gangLoadMdioWriteOnly in AQ_GlobalGeneralProvisioning_APPIA */ -#define word_AQ_GlobalGeneralProvisioning_APPIA_gangLoadMdioWriteOnly u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mdioBroadcastModeEnable in AQ_GlobalGeneralProvisioning_APPIA */ -#define AQ_GlobalGeneralProvisioning_APPIA_mdioBroadcastModeEnable 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mdioBroadcastModeEnable in AQ_GlobalGeneralProvisioning_APPIA */ -#define bits_AQ_GlobalGeneralProvisioning_APPIA_mdioBroadcastModeEnable u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mdioBroadcastModeEnable in AQ_GlobalGeneralProvisioning_APPIA */ -#define word_AQ_GlobalGeneralProvisioning_APPIA_mdioBroadcastModeEnable u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure mdioReadMSW_FirstEnable in AQ_GlobalGeneralProvisioning_APPIA */ -#define AQ_GlobalGeneralProvisioning_APPIA_mdioReadMSW_FirstEnable 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mdioReadMSW_FirstEnable in AQ_GlobalGeneralProvisioning_APPIA */ -#define bits_AQ_GlobalGeneralProvisioning_APPIA_mdioReadMSW_FirstEnable u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mdioReadMSW_FirstEnable in AQ_GlobalGeneralProvisioning_APPIA */ -#define word_AQ_GlobalGeneralProvisioning_APPIA_mdioReadMSW_FirstEnable u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure mdioDriveConfiguration in AQ_GlobalGeneralProvisioning_APPIA */ -#define AQ_GlobalGeneralProvisioning_APPIA_mdioDriveConfiguration 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mdioDriveConfiguration in AQ_GlobalGeneralProvisioning_APPIA */ -#define bits_AQ_GlobalGeneralProvisioning_APPIA_mdioDriveConfiguration u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mdioDriveConfiguration in AQ_GlobalGeneralProvisioning_APPIA */ -#define word_AQ_GlobalGeneralProvisioning_APPIA_mdioDriveConfiguration u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure mdioPreambleDetectionDisable in AQ_GlobalGeneralProvisioning_APPIA */ -#define AQ_GlobalGeneralProvisioning_APPIA_mdioPreambleDetectionDisable 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mdioPreambleDetectionDisable in AQ_GlobalGeneralProvisioning_APPIA */ -#define bits_AQ_GlobalGeneralProvisioning_APPIA_mdioPreambleDetectionDisable u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mdioPreambleDetectionDisable in AQ_GlobalGeneralProvisioning_APPIA */ -#define word_AQ_GlobalGeneralProvisioning_APPIA_mdioPreambleDetectionDisable u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure mdioAddressReset in AQ_GlobalGeneralProvisioning_APPIA */ -#define AQ_GlobalGeneralProvisioning_APPIA_mdioAddressReset 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mdioAddressReset in AQ_GlobalGeneralProvisioning_APPIA */ -#define bits_AQ_GlobalGeneralProvisioning_APPIA_mdioAddressReset u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mdioAddressReset in AQ_GlobalGeneralProvisioning_APPIA */ -#define word_AQ_GlobalGeneralProvisioning_APPIA_mdioAddressReset u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure daisyChainReset in AQ_GlobalGeneralProvisioning_APPIA */ -#define AQ_GlobalGeneralProvisioning_APPIA_daisyChainReset 2 -/*! \brief Preprocessor variable to relate field to bit position in structure daisyChainReset in AQ_GlobalGeneralProvisioning_APPIA */ -#define bits_AQ_GlobalGeneralProvisioning_APPIA_daisyChainReset u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure daisyChainReset in AQ_GlobalGeneralProvisioning_APPIA */ -#define word_AQ_GlobalGeneralProvisioning_APPIA_daisyChainReset u2.word_2 - -/*! \brief Base register address of structure AQ_GlobalNvrProvisioning_APPIA */ -#define AQ_GlobalNvrProvisioning_APPIA_baseRegisterAddress 0xC450 -/*! \brief MMD address of structure AQ_GlobalNvrProvisioning_APPIA */ -#define AQ_GlobalNvrProvisioning_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure nvrDataLength in AQ_GlobalNvrProvisioning_APPIA */ -#define AQ_GlobalNvrProvisioning_APPIA_nvrDataLength 0 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrDataLength in AQ_GlobalNvrProvisioning_APPIA */ -#define bits_AQ_GlobalNvrProvisioning_APPIA_nvrDataLength u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure nvrDataLength in AQ_GlobalNvrProvisioning_APPIA */ -#define word_AQ_GlobalNvrProvisioning_APPIA_nvrDataLength u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure nvrDummyLength in AQ_GlobalNvrProvisioning_APPIA */ -#define AQ_GlobalNvrProvisioning_APPIA_nvrDummyLength 0 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrDummyLength in AQ_GlobalNvrProvisioning_APPIA */ -#define bits_AQ_GlobalNvrProvisioning_APPIA_nvrDummyLength u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure nvrDummyLength in AQ_GlobalNvrProvisioning_APPIA */ -#define word_AQ_GlobalNvrProvisioning_APPIA_nvrDummyLength u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure nvrAddressLength in AQ_GlobalNvrProvisioning_APPIA */ -#define AQ_GlobalNvrProvisioning_APPIA_nvrAddressLength 0 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrAddressLength in AQ_GlobalNvrProvisioning_APPIA */ -#define bits_AQ_GlobalNvrProvisioning_APPIA_nvrAddressLength u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure nvrAddressLength in AQ_GlobalNvrProvisioning_APPIA */ -#define word_AQ_GlobalNvrProvisioning_APPIA_nvrAddressLength u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure nvrAddressLengthOverride in AQ_GlobalNvrProvisioning_APPIA */ -#define AQ_GlobalNvrProvisioning_APPIA_nvrAddressLengthOverride 1 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrAddressLengthOverride in AQ_GlobalNvrProvisioning_APPIA */ -#define bits_AQ_GlobalNvrProvisioning_APPIA_nvrAddressLengthOverride u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure nvrAddressLengthOverride in AQ_GlobalNvrProvisioning_APPIA */ -#define word_AQ_GlobalNvrProvisioning_APPIA_nvrAddressLengthOverride u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure nvrClockDivide in AQ_GlobalNvrProvisioning_APPIA */ -#define AQ_GlobalNvrProvisioning_APPIA_nvrClockDivide 1 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrClockDivide in AQ_GlobalNvrProvisioning_APPIA */ -#define bits_AQ_GlobalNvrProvisioning_APPIA_nvrClockDivide u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure nvrClockDivide in AQ_GlobalNvrProvisioning_APPIA */ -#define word_AQ_GlobalNvrProvisioning_APPIA_nvrClockDivide u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure nvrDaisyChainClockDivideOverride in AQ_GlobalNvrProvisioning_APPIA */ -#define AQ_GlobalNvrProvisioning_APPIA_nvrDaisyChainClockDivideOverride 2 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrDaisyChainClockDivideOverride in AQ_GlobalNvrProvisioning_APPIA */ -#define bits_AQ_GlobalNvrProvisioning_APPIA_nvrDaisyChainClockDivideOverride u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure nvrDaisyChainClockDivideOverride in AQ_GlobalNvrProvisioning_APPIA */ -#define word_AQ_GlobalNvrProvisioning_APPIA_nvrDaisyChainClockDivideOverride u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure nvrDaisyChainDisable in AQ_GlobalNvrProvisioning_APPIA */ -#define AQ_GlobalNvrProvisioning_APPIA_nvrDaisyChainDisable 2 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrDaisyChainDisable in AQ_GlobalNvrProvisioning_APPIA */ -#define bits_AQ_GlobalNvrProvisioning_APPIA_nvrDaisyChainDisable u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure nvrDaisyChainDisable in AQ_GlobalNvrProvisioning_APPIA */ -#define word_AQ_GlobalNvrProvisioning_APPIA_nvrDaisyChainDisable u2.word_2 - -/*! \brief Base register address of structure AQ_GlobalReservedProvisioning_APPIA */ -#define AQ_GlobalReservedProvisioning_APPIA_baseRegisterAddress 0xC470 -/*! \brief MMD address of structure AQ_GlobalReservedProvisioning_APPIA */ -#define AQ_GlobalReservedProvisioning_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure diagnosticsSelect in AQ_GlobalReservedProvisioning_APPIA */ -#define AQ_GlobalReservedProvisioning_APPIA_diagnosticsSelect 0 -/*! \brief Preprocessor variable to relate field to bit position in structure diagnosticsSelect in AQ_GlobalReservedProvisioning_APPIA */ -#define bits_AQ_GlobalReservedProvisioning_APPIA_diagnosticsSelect u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure diagnosticsSelect in AQ_GlobalReservedProvisioning_APPIA */ -#define word_AQ_GlobalReservedProvisioning_APPIA_diagnosticsSelect u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure extendedMdiDiagnosticsSelect in AQ_GlobalReservedProvisioning_APPIA */ -#define AQ_GlobalReservedProvisioning_APPIA_extendedMdiDiagnosticsSelect 0 -/*! \brief Preprocessor variable to relate field to bit position in structure extendedMdiDiagnosticsSelect in AQ_GlobalReservedProvisioning_APPIA */ -#define bits_AQ_GlobalReservedProvisioning_APPIA_extendedMdiDiagnosticsSelect u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure extendedMdiDiagnosticsSelect in AQ_GlobalReservedProvisioning_APPIA */ -#define word_AQ_GlobalReservedProvisioning_APPIA_extendedMdiDiagnosticsSelect u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure initiateComponentDiagnostics in AQ_GlobalReservedProvisioning_APPIA */ -#define AQ_GlobalReservedProvisioning_APPIA_initiateComponentDiagnostics 0 -/*! \brief Preprocessor variable to relate field to bit position in structure initiateComponentDiagnostics in AQ_GlobalReservedProvisioning_APPIA */ -#define bits_AQ_GlobalReservedProvisioning_APPIA_initiateComponentDiagnostics u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure initiateComponentDiagnostics in AQ_GlobalReservedProvisioning_APPIA */ -#define word_AQ_GlobalReservedProvisioning_APPIA_initiateComponentDiagnostics u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure initiateCableDiagnostics in AQ_GlobalReservedProvisioning_APPIA */ -#define AQ_GlobalReservedProvisioning_APPIA_initiateCableDiagnostics 0 -/*! \brief Preprocessor variable to relate field to bit position in structure initiateCableDiagnostics in AQ_GlobalReservedProvisioning_APPIA */ -#define bits_AQ_GlobalReservedProvisioning_APPIA_initiateCableDiagnostics u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure initiateCableDiagnostics in AQ_GlobalReservedProvisioning_APPIA */ -#define word_AQ_GlobalReservedProvisioning_APPIA_initiateCableDiagnostics u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioning_2 in AQ_GlobalReservedProvisioning_APPIA */ -#define AQ_GlobalReservedProvisioning_APPIA_reservedProvisioning_2 1 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioning_2 in AQ_GlobalReservedProvisioning_APPIA */ -#define bits_AQ_GlobalReservedProvisioning_APPIA_reservedProvisioning_2 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioning_2 in AQ_GlobalReservedProvisioning_APPIA */ -#define word_AQ_GlobalReservedProvisioning_APPIA_reservedProvisioning_2 u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure enableDaisy_chainHop_countOverride in AQ_GlobalReservedProvisioning_APPIA */ -#define AQ_GlobalReservedProvisioning_APPIA_enableDaisy_chainHop_countOverride 1 -/*! \brief Preprocessor variable to relate field to bit position in structure enableDaisy_chainHop_countOverride in AQ_GlobalReservedProvisioning_APPIA */ -#define bits_AQ_GlobalReservedProvisioning_APPIA_enableDaisy_chainHop_countOverride u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure enableDaisy_chainHop_countOverride in AQ_GlobalReservedProvisioning_APPIA */ -#define word_AQ_GlobalReservedProvisioning_APPIA_enableDaisy_chainHop_countOverride u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure daisy_chainHop_countOverrideValue in AQ_GlobalReservedProvisioning_APPIA */ -#define AQ_GlobalReservedProvisioning_APPIA_daisy_chainHop_countOverrideValue 1 -/*! \brief Preprocessor variable to relate field to bit position in structure daisy_chainHop_countOverrideValue in AQ_GlobalReservedProvisioning_APPIA */ -#define bits_AQ_GlobalReservedProvisioning_APPIA_daisy_chainHop_countOverrideValue u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure daisy_chainHop_countOverrideValue in AQ_GlobalReservedProvisioning_APPIA */ -#define word_AQ_GlobalReservedProvisioning_APPIA_daisy_chainHop_countOverrideValue u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure enableLvddPowerSupplyTuning in AQ_GlobalReservedProvisioning_APPIA */ -#define AQ_GlobalReservedProvisioning_APPIA_enableLvddPowerSupplyTuning 2 -/*! \brief Preprocessor variable to relate field to bit position in structure enableLvddPowerSupplyTuning in AQ_GlobalReservedProvisioning_APPIA */ -#define bits_AQ_GlobalReservedProvisioning_APPIA_enableLvddPowerSupplyTuning u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure enableLvddPowerSupplyTuning in AQ_GlobalReservedProvisioning_APPIA */ -#define word_AQ_GlobalReservedProvisioning_APPIA_enableLvddPowerSupplyTuning u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure enableVddPowerSupplyTuning in AQ_GlobalReservedProvisioning_APPIA */ -#define AQ_GlobalReservedProvisioning_APPIA_enableVddPowerSupplyTuning 2 -/*! \brief Preprocessor variable to relate field to bit position in structure enableVddPowerSupplyTuning in AQ_GlobalReservedProvisioning_APPIA */ -#define bits_AQ_GlobalReservedProvisioning_APPIA_enableVddPowerSupplyTuning u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure enableVddPowerSupplyTuning in AQ_GlobalReservedProvisioning_APPIA */ -#define word_AQ_GlobalReservedProvisioning_APPIA_enableVddPowerSupplyTuning u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure tunableExternalLvddPowerSupplyPresent in AQ_GlobalReservedProvisioning_APPIA */ -#define AQ_GlobalReservedProvisioning_APPIA_tunableExternalLvddPowerSupplyPresent 2 -/*! \brief Preprocessor variable to relate field to bit position in structure tunableExternalLvddPowerSupplyPresent in AQ_GlobalReservedProvisioning_APPIA */ -#define bits_AQ_GlobalReservedProvisioning_APPIA_tunableExternalLvddPowerSupplyPresent u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure tunableExternalLvddPowerSupplyPresent in AQ_GlobalReservedProvisioning_APPIA */ -#define word_AQ_GlobalReservedProvisioning_APPIA_tunableExternalLvddPowerSupplyPresent u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure tunableExternalVddPowerSupplyPresent in AQ_GlobalReservedProvisioning_APPIA */ -#define AQ_GlobalReservedProvisioning_APPIA_tunableExternalVddPowerSupplyPresent 2 -/*! \brief Preprocessor variable to relate field to bit position in structure tunableExternalVddPowerSupplyPresent in AQ_GlobalReservedProvisioning_APPIA */ -#define bits_AQ_GlobalReservedProvisioning_APPIA_tunableExternalVddPowerSupplyPresent u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure tunableExternalVddPowerSupplyPresent in AQ_GlobalReservedProvisioning_APPIA */ -#define word_AQ_GlobalReservedProvisioning_APPIA_tunableExternalVddPowerSupplyPresent u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure enableXenpakRegisterSpace in AQ_GlobalReservedProvisioning_APPIA */ -#define AQ_GlobalReservedProvisioning_APPIA_enableXenpakRegisterSpace 2 -/*! \brief Preprocessor variable to relate field to bit position in structure enableXenpakRegisterSpace in AQ_GlobalReservedProvisioning_APPIA */ -#define bits_AQ_GlobalReservedProvisioning_APPIA_enableXenpakRegisterSpace u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure enableXenpakRegisterSpace in AQ_GlobalReservedProvisioning_APPIA */ -#define word_AQ_GlobalReservedProvisioning_APPIA_enableXenpakRegisterSpace u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure enable_5thChannelRfiCancellation in AQ_GlobalReservedProvisioning_APPIA */ -#define AQ_GlobalReservedProvisioning_APPIA_enable_5thChannelRfiCancellation 2 -/*! \brief Preprocessor variable to relate field to bit position in structure enable_5thChannelRfiCancellation in AQ_GlobalReservedProvisioning_APPIA */ -#define bits_AQ_GlobalReservedProvisioning_APPIA_enable_5thChannelRfiCancellation u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure enable_5thChannelRfiCancellation in AQ_GlobalReservedProvisioning_APPIA */ -#define word_AQ_GlobalReservedProvisioning_APPIA_enable_5thChannelRfiCancellation u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure trainingSNR in AQ_GlobalReservedProvisioning_APPIA */ -#define AQ_GlobalReservedProvisioning_APPIA_trainingSNR 4 -/*! \brief Preprocessor variable to relate field to bit position in structure trainingSNR in AQ_GlobalReservedProvisioning_APPIA */ -#define bits_AQ_GlobalReservedProvisioning_APPIA_trainingSNR u4.bits_4 -/*! \brief Preprocessor variable to relate field to word position in structure trainingSNR in AQ_GlobalReservedProvisioning_APPIA */ -#define word_AQ_GlobalReservedProvisioning_APPIA_trainingSNR u4.word_4 -/*! \brief Preprocessor variable to relate field to word number in structure smartPower_downStatus in AQ_GlobalReservedProvisioning_APPIA */ -#define AQ_GlobalReservedProvisioning_APPIA_smartPower_downStatus 5 -/*! \brief Preprocessor variable to relate field to bit position in structure smartPower_downStatus in AQ_GlobalReservedProvisioning_APPIA */ -#define bits_AQ_GlobalReservedProvisioning_APPIA_smartPower_downStatus u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure smartPower_downStatus in AQ_GlobalReservedProvisioning_APPIA */ -#define word_AQ_GlobalReservedProvisioning_APPIA_smartPower_downStatus u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioning_6 in AQ_GlobalReservedProvisioning_APPIA */ -#define AQ_GlobalReservedProvisioning_APPIA_reservedProvisioning_6 5 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioning_6 in AQ_GlobalReservedProvisioning_APPIA */ -#define bits_AQ_GlobalReservedProvisioning_APPIA_reservedProvisioning_6 u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioning_6 in AQ_GlobalReservedProvisioning_APPIA */ -#define word_AQ_GlobalReservedProvisioning_APPIA_reservedProvisioning_6 u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure cfrLpDisableTimer in AQ_GlobalReservedProvisioning_APPIA */ -#define AQ_GlobalReservedProvisioning_APPIA_cfrLpDisableTimer 5 -/*! \brief Preprocessor variable to relate field to bit position in structure cfrLpDisableTimer in AQ_GlobalReservedProvisioning_APPIA */ -#define bits_AQ_GlobalReservedProvisioning_APPIA_cfrLpDisableTimer u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure cfrLpDisableTimer in AQ_GlobalReservedProvisioning_APPIA */ -#define word_AQ_GlobalReservedProvisioning_APPIA_cfrLpDisableTimer u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure cfrLpExtendedMaxwait in AQ_GlobalReservedProvisioning_APPIA */ -#define AQ_GlobalReservedProvisioning_APPIA_cfrLpExtendedMaxwait 5 -/*! \brief Preprocessor variable to relate field to bit position in structure cfrLpExtendedMaxwait in AQ_GlobalReservedProvisioning_APPIA */ -#define bits_AQ_GlobalReservedProvisioning_APPIA_cfrLpExtendedMaxwait u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure cfrLpExtendedMaxwait in AQ_GlobalReservedProvisioning_APPIA */ -#define word_AQ_GlobalReservedProvisioning_APPIA_cfrLpExtendedMaxwait u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure cfrLpTHP in AQ_GlobalReservedProvisioning_APPIA */ -#define AQ_GlobalReservedProvisioning_APPIA_cfrLpTHP 5 -/*! \brief Preprocessor variable to relate field to bit position in structure cfrLpTHP in AQ_GlobalReservedProvisioning_APPIA */ -#define bits_AQ_GlobalReservedProvisioning_APPIA_cfrLpTHP u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure cfrLpTHP in AQ_GlobalReservedProvisioning_APPIA */ -#define word_AQ_GlobalReservedProvisioning_APPIA_cfrLpTHP u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure cfrLpSupport in AQ_GlobalReservedProvisioning_APPIA */ -#define AQ_GlobalReservedProvisioning_APPIA_cfrLpSupport 5 -/*! \brief Preprocessor variable to relate field to bit position in structure cfrLpSupport in AQ_GlobalReservedProvisioning_APPIA */ -#define bits_AQ_GlobalReservedProvisioning_APPIA_cfrLpSupport u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure cfrLpSupport in AQ_GlobalReservedProvisioning_APPIA */ -#define word_AQ_GlobalReservedProvisioning_APPIA_cfrLpSupport u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure cfrDisableTimer in AQ_GlobalReservedProvisioning_APPIA */ -#define AQ_GlobalReservedProvisioning_APPIA_cfrDisableTimer 5 -/*! \brief Preprocessor variable to relate field to bit position in structure cfrDisableTimer in AQ_GlobalReservedProvisioning_APPIA */ -#define bits_AQ_GlobalReservedProvisioning_APPIA_cfrDisableTimer u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure cfrDisableTimer in AQ_GlobalReservedProvisioning_APPIA */ -#define word_AQ_GlobalReservedProvisioning_APPIA_cfrDisableTimer u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure cfrExtendedMaxwait in AQ_GlobalReservedProvisioning_APPIA */ -#define AQ_GlobalReservedProvisioning_APPIA_cfrExtendedMaxwait 5 -/*! \brief Preprocessor variable to relate field to bit position in structure cfrExtendedMaxwait in AQ_GlobalReservedProvisioning_APPIA */ -#define bits_AQ_GlobalReservedProvisioning_APPIA_cfrExtendedMaxwait u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure cfrExtendedMaxwait in AQ_GlobalReservedProvisioning_APPIA */ -#define word_AQ_GlobalReservedProvisioning_APPIA_cfrExtendedMaxwait u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure cfrTHP in AQ_GlobalReservedProvisioning_APPIA */ -#define AQ_GlobalReservedProvisioning_APPIA_cfrTHP 5 -/*! \brief Preprocessor variable to relate field to bit position in structure cfrTHP in AQ_GlobalReservedProvisioning_APPIA */ -#define bits_AQ_GlobalReservedProvisioning_APPIA_cfrTHP u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure cfrTHP in AQ_GlobalReservedProvisioning_APPIA */ -#define word_AQ_GlobalReservedProvisioning_APPIA_cfrTHP u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure cfrSupport in AQ_GlobalReservedProvisioning_APPIA */ -#define AQ_GlobalReservedProvisioning_APPIA_cfrSupport 5 -/*! \brief Preprocessor variable to relate field to bit position in structure cfrSupport in AQ_GlobalReservedProvisioning_APPIA */ -#define bits_AQ_GlobalReservedProvisioning_APPIA_cfrSupport u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure cfrSupport in AQ_GlobalReservedProvisioning_APPIA */ -#define word_AQ_GlobalReservedProvisioning_APPIA_cfrSupport u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure deadlockAvoidanceEnable in AQ_GlobalReservedProvisioning_APPIA */ -#define AQ_GlobalReservedProvisioning_APPIA_deadlockAvoidanceEnable 5 -/*! \brief Preprocessor variable to relate field to bit position in structure deadlockAvoidanceEnable in AQ_GlobalReservedProvisioning_APPIA */ -#define bits_AQ_GlobalReservedProvisioning_APPIA_deadlockAvoidanceEnable u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure deadlockAvoidanceEnable in AQ_GlobalReservedProvisioning_APPIA */ -#define word_AQ_GlobalReservedProvisioning_APPIA_deadlockAvoidanceEnable u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure smartPower_downEnable in AQ_GlobalReservedProvisioning_APPIA */ -#define AQ_GlobalReservedProvisioning_APPIA_smartPower_downEnable 5 -/*! \brief Preprocessor variable to relate field to bit position in structure smartPower_downEnable in AQ_GlobalReservedProvisioning_APPIA */ -#define bits_AQ_GlobalReservedProvisioning_APPIA_smartPower_downEnable u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure smartPower_downEnable in AQ_GlobalReservedProvisioning_APPIA */ -#define word_AQ_GlobalReservedProvisioning_APPIA_smartPower_downEnable u5.word_5 - -/*! \brief Base register address of structure AQ_GlobalCableDiagnosticStatus_APPIA */ -#define AQ_GlobalCableDiagnosticStatus_APPIA_baseRegisterAddress 0xC800 -/*! \brief MMD address of structure AQ_GlobalCableDiagnosticStatus_APPIA */ -#define AQ_GlobalCableDiagnosticStatus_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure pairAStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define AQ_GlobalCableDiagnosticStatus_APPIA_pairAStatus 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pairAStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairAStatus u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pairAStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairAStatus u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pairBStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define AQ_GlobalCableDiagnosticStatus_APPIA_pairBStatus 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pairBStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairBStatus u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pairBStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairBStatus u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pairCStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define AQ_GlobalCableDiagnosticStatus_APPIA_pairCStatus 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pairCStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairCStatus u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pairCStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairCStatus u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pairDStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define AQ_GlobalCableDiagnosticStatus_APPIA_pairDStatus 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pairDStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairDStatus u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pairDStatus in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairDStatus u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define AQ_GlobalCableDiagnosticStatus_APPIA_pairAReflection_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairAReflection_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairAReflection_1 u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define AQ_GlobalCableDiagnosticStatus_APPIA_pairAReflection_2 1 -/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairAReflection_2 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairAReflection_2 u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure impulseResponseMSW in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define AQ_GlobalCableDiagnosticStatus_APPIA_impulseResponseMSW 2 -/*! \brief Preprocessor variable to relate field to bit position in structure impulseResponseMSW in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_impulseResponseMSW u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure impulseResponseMSW in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define word_AQ_GlobalCableDiagnosticStatus_APPIA_impulseResponseMSW u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define AQ_GlobalCableDiagnosticStatus_APPIA_pairBReflection_1 3 -/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairBReflection_1 u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairBReflection_1 u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define AQ_GlobalCableDiagnosticStatus_APPIA_pairBReflection_2 3 -/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairBReflection_2 u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairBReflection_2 u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure impulseResponseLSW in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define AQ_GlobalCableDiagnosticStatus_APPIA_impulseResponseLSW 4 -/*! \brief Preprocessor variable to relate field to bit position in structure impulseResponseLSW in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_impulseResponseLSW u4.bits_4 -/*! \brief Preprocessor variable to relate field to word position in structure impulseResponseLSW in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define word_AQ_GlobalCableDiagnosticStatus_APPIA_impulseResponseLSW u4.word_4 -/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define AQ_GlobalCableDiagnosticStatus_APPIA_pairCReflection_1 5 -/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairCReflection_1 u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairCReflection_1 u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define AQ_GlobalCableDiagnosticStatus_APPIA_pairCReflection_2 5 -/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairCReflection_2 u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairCReflection_2 u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define AQ_GlobalCableDiagnosticStatus_APPIA_reserved_1 6 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_reserved_1 u6.bits_6 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define word_AQ_GlobalCableDiagnosticStatus_APPIA_reserved_1 u6.word_6 -/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define AQ_GlobalCableDiagnosticStatus_APPIA_pairDReflection_1 7 -/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairDReflection_1 u7.bits_7 -/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_1 in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairDReflection_1 u7.word_7 -/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define AQ_GlobalCableDiagnosticStatus_APPIA_pairDReflection_2 7 -/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_pairDReflection_2 u7.bits_7 -/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define word_AQ_GlobalCableDiagnosticStatus_APPIA_pairDReflection_2 u7.word_7 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define AQ_GlobalCableDiagnosticStatus_APPIA_reserved_2 8 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define bits_AQ_GlobalCableDiagnosticStatus_APPIA_reserved_2 u8.bits_8 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_2 in AQ_GlobalCableDiagnosticStatus_APPIA */ -#define word_AQ_GlobalCableDiagnosticStatus_APPIA_reserved_2 u8.word_8 - -/*! \brief Base register address of structure AQ_GlobalThermalStatus_APPIA */ -#define AQ_GlobalThermalStatus_APPIA_baseRegisterAddress 0xC820 -/*! \brief MMD address of structure AQ_GlobalThermalStatus_APPIA */ -#define AQ_GlobalThermalStatus_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure temperature in AQ_GlobalThermalStatus_APPIA */ -#define AQ_GlobalThermalStatus_APPIA_temperature 0 -/*! \brief Preprocessor variable to relate field to bit position in structure temperature in AQ_GlobalThermalStatus_APPIA */ -#define bits_AQ_GlobalThermalStatus_APPIA_temperature u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure temperature in AQ_GlobalThermalStatus_APPIA */ -#define word_AQ_GlobalThermalStatus_APPIA_temperature u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure temperatureReady in AQ_GlobalThermalStatus_APPIA */ -#define AQ_GlobalThermalStatus_APPIA_temperatureReady 1 -/*! \brief Preprocessor variable to relate field to bit position in structure temperatureReady in AQ_GlobalThermalStatus_APPIA */ -#define bits_AQ_GlobalThermalStatus_APPIA_temperatureReady u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure temperatureReady in AQ_GlobalThermalStatus_APPIA */ -#define word_AQ_GlobalThermalStatus_APPIA_temperatureReady u1.word_1 - -/*! \brief Base register address of structure AQ_GlobalGeneralStatus_APPIA */ -#define AQ_GlobalGeneralStatus_APPIA_baseRegisterAddress 0xC830 -/*! \brief MMD address of structure AQ_GlobalGeneralStatus_APPIA */ -#define AQ_GlobalGeneralStatus_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureFailureState in AQ_GlobalGeneralStatus_APPIA */ -#define AQ_GlobalGeneralStatus_APPIA_highTemperatureFailureState 0 -/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureFailureState in AQ_GlobalGeneralStatus_APPIA */ -#define bits_AQ_GlobalGeneralStatus_APPIA_highTemperatureFailureState u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureFailureState in AQ_GlobalGeneralStatus_APPIA */ -#define word_AQ_GlobalGeneralStatus_APPIA_highTemperatureFailureState u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureFailureState in AQ_GlobalGeneralStatus_APPIA */ -#define AQ_GlobalGeneralStatus_APPIA_lowTemperatureFailureState 0 -/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureFailureState in AQ_GlobalGeneralStatus_APPIA */ -#define bits_AQ_GlobalGeneralStatus_APPIA_lowTemperatureFailureState u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureFailureState in AQ_GlobalGeneralStatus_APPIA */ -#define word_AQ_GlobalGeneralStatus_APPIA_lowTemperatureFailureState u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureWarningState in AQ_GlobalGeneralStatus_APPIA */ -#define AQ_GlobalGeneralStatus_APPIA_highTemperatureWarningState 0 -/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureWarningState in AQ_GlobalGeneralStatus_APPIA */ -#define bits_AQ_GlobalGeneralStatus_APPIA_highTemperatureWarningState u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureWarningState in AQ_GlobalGeneralStatus_APPIA */ -#define word_AQ_GlobalGeneralStatus_APPIA_highTemperatureWarningState u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureWarningState in AQ_GlobalGeneralStatus_APPIA */ -#define AQ_GlobalGeneralStatus_APPIA_lowTemperatureWarningState 0 -/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureWarningState in AQ_GlobalGeneralStatus_APPIA */ -#define bits_AQ_GlobalGeneralStatus_APPIA_lowTemperatureWarningState u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureWarningState in AQ_GlobalGeneralStatus_APPIA */ -#define word_AQ_GlobalGeneralStatus_APPIA_lowTemperatureWarningState u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure processorIntensiveMdioOperationIn_Progress in AQ_GlobalGeneralStatus_APPIA */ -#define AQ_GlobalGeneralStatus_APPIA_processorIntensiveMdioOperationIn_Progress 1 -/*! \brief Preprocessor variable to relate field to bit position in structure processorIntensiveMdioOperationIn_Progress in AQ_GlobalGeneralStatus_APPIA */ -#define bits_AQ_GlobalGeneralStatus_APPIA_processorIntensiveMdioOperationIn_Progress u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure processorIntensiveMdioOperationIn_Progress in AQ_GlobalGeneralStatus_APPIA */ -#define word_AQ_GlobalGeneralStatus_APPIA_processorIntensiveMdioOperationIn_Progress u1.word_1 - -/*! \brief Base register address of structure AQ_GlobalPinStatus_APPIA */ -#define AQ_GlobalPinStatus_APPIA_baseRegisterAddress 0xC840 -/*! \brief MMD address of structure AQ_GlobalPinStatus_APPIA */ -#define AQ_GlobalPinStatus_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mdioBootLoad in AQ_GlobalPinStatus_APPIA */ -#define AQ_GlobalPinStatus_APPIA_mdioBootLoad 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mdioBootLoad in AQ_GlobalPinStatus_APPIA */ -#define bits_AQ_GlobalPinStatus_APPIA_mdioBootLoad u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mdioBootLoad in AQ_GlobalPinStatus_APPIA */ -#define word_AQ_GlobalPinStatus_APPIA_mdioBootLoad u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure packageConnectivity in AQ_GlobalPinStatus_APPIA */ -#define AQ_GlobalPinStatus_APPIA_packageConnectivity 0 -/*! \brief Preprocessor variable to relate field to bit position in structure packageConnectivity in AQ_GlobalPinStatus_APPIA */ -#define bits_AQ_GlobalPinStatus_APPIA_packageConnectivity u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure packageConnectivity in AQ_GlobalPinStatus_APPIA */ -#define word_AQ_GlobalPinStatus_APPIA_packageConnectivity u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure txEnable in AQ_GlobalPinStatus_APPIA */ -#define AQ_GlobalPinStatus_APPIA_txEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure txEnable in AQ_GlobalPinStatus_APPIA */ -#define bits_AQ_GlobalPinStatus_APPIA_txEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure txEnable in AQ_GlobalPinStatus_APPIA */ -#define word_AQ_GlobalPinStatus_APPIA_txEnable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure ledPullupState in AQ_GlobalPinStatus_APPIA */ -#define AQ_GlobalPinStatus_APPIA_ledPullupState 0 -/*! \brief Preprocessor variable to relate field to bit position in structure ledPullupState in AQ_GlobalPinStatus_APPIA */ -#define bits_AQ_GlobalPinStatus_APPIA_ledPullupState u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure ledPullupState in AQ_GlobalPinStatus_APPIA */ -#define word_AQ_GlobalPinStatus_APPIA_ledPullupState u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalDaisyChainStatus_APPIA */ -#define AQ_GlobalDaisyChainStatus_APPIA_baseRegisterAddress 0xC842 -/*! \brief MMD address of structure AQ_GlobalDaisyChainStatus_APPIA */ -#define AQ_GlobalDaisyChainStatus_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure rxDaisyChainCalculatedCrc in AQ_GlobalDaisyChainStatus_APPIA */ -#define AQ_GlobalDaisyChainStatus_APPIA_rxDaisyChainCalculatedCrc 0 -/*! \brief Preprocessor variable to relate field to bit position in structure rxDaisyChainCalculatedCrc in AQ_GlobalDaisyChainStatus_APPIA */ -#define bits_AQ_GlobalDaisyChainStatus_APPIA_rxDaisyChainCalculatedCrc u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure rxDaisyChainCalculatedCrc in AQ_GlobalDaisyChainStatus_APPIA */ -#define word_AQ_GlobalDaisyChainStatus_APPIA_rxDaisyChainCalculatedCrc u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalFaultMessage_APPIA */ -#define AQ_GlobalFaultMessage_APPIA_baseRegisterAddress 0xC850 -/*! \brief MMD address of structure AQ_GlobalFaultMessage_APPIA */ -#define AQ_GlobalFaultMessage_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure message in AQ_GlobalFaultMessage_APPIA */ -#define AQ_GlobalFaultMessage_APPIA_message 0 -/*! \brief Preprocessor variable to relate field to bit position in structure message in AQ_GlobalFaultMessage_APPIA */ -#define bits_AQ_GlobalFaultMessage_APPIA_message u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure message in AQ_GlobalFaultMessage_APPIA */ -#define word_AQ_GlobalFaultMessage_APPIA_message u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalPrimaryStatus_APPIA */ -#define AQ_GlobalPrimaryStatus_APPIA_baseRegisterAddress 0xC851 -/*! \brief MMD address of structure AQ_GlobalPrimaryStatus_APPIA */ -#define AQ_GlobalPrimaryStatus_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure primaryStatus in AQ_GlobalPrimaryStatus_APPIA */ -#define AQ_GlobalPrimaryStatus_APPIA_primaryStatus 0 -/*! \brief Preprocessor variable to relate field to bit position in structure primaryStatus in AQ_GlobalPrimaryStatus_APPIA */ -#define bits_AQ_GlobalPrimaryStatus_APPIA_primaryStatus u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure primaryStatus in AQ_GlobalPrimaryStatus_APPIA */ -#define word_AQ_GlobalPrimaryStatus_APPIA_primaryStatus u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_baseRegisterAddress 0xC880 -/*! \brief MMD address of structure AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure reserved_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_1 0 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_1 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_1 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_1 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_1 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_1 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_2 0 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_2 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_2 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_2 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_2 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_2 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_3 0 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_3 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_3 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_3 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_3 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_3 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_4 0 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_4 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_4 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_4 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_4 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairAReflection_4 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_5 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_5 1 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_5 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_5 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_5 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_5 u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_1 u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_6 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_6 1 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_6 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_6 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_6 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_6 u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_2 1 -/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_2 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_2 u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_7 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_7 1 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_7 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_7 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_7 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_7 u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_3 1 -/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_3 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_3 u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_8 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_8 1 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_8 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_8 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_8 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_8 u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_4 1 -/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_4 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairBReflection_4 u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_9 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_9 2 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_9 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_9 u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_9 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_9 u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_1 2 -/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_1 u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_1 u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_10 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_10 2 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_10 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_10 u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_10 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_10 u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_2 2 -/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_2 u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_2 u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_11 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_11 2 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_11 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_11 u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_11 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_11 u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_3 2 -/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_3 u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_3 u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_12 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_12 2 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_12 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_12 u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_12 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_12 u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_4 2 -/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_4 u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairCReflection_4 u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_13 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_13 3 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_13 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_13 u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_13 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_13 u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_1 3 -/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_1 u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_1 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_1 u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_14 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_14 3 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_14 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_14 u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_14 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_14 u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_2 3 -/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_2 u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_2 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_2 u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_15 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_15 3 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_15 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_15 u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_15 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_15 u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_3 3 -/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_3 u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_3 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_3 u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_16 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_16 3 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_16 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_16 u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_16 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_reserved_16 u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_4 3 -/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define bits_AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_4 u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_4 in AQ_GlobalCableDiagnosticImpedance_APPIA */ -#define word_AQ_GlobalCableDiagnosticImpedance_APPIA_pairDReflection_4 u3.word_3 - -/*! \brief Base register address of structure AQ_GlobalStatus_APPIA */ -#define AQ_GlobalStatus_APPIA_baseRegisterAddress 0xC884 -/*! \brief MMD address of structure AQ_GlobalStatus_APPIA */ -#define AQ_GlobalStatus_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure reservedStatus_0 in AQ_GlobalStatus_APPIA */ -#define AQ_GlobalStatus_APPIA_reservedStatus_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedStatus_0 in AQ_GlobalStatus_APPIA */ -#define bits_AQ_GlobalStatus_APPIA_reservedStatus_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure reservedStatus_0 in AQ_GlobalStatus_APPIA */ -#define word_AQ_GlobalStatus_APPIA_reservedStatus_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure cableLength in AQ_GlobalStatus_APPIA */ -#define AQ_GlobalStatus_APPIA_cableLength 0 -/*! \brief Preprocessor variable to relate field to bit position in structure cableLength in AQ_GlobalStatus_APPIA */ -#define bits_AQ_GlobalStatus_APPIA_cableLength u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure cableLength in AQ_GlobalStatus_APPIA */ -#define word_AQ_GlobalStatus_APPIA_cableLength u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalReservedStatus_APPIA */ -#define AQ_GlobalReservedStatus_APPIA_baseRegisterAddress 0xC885 -/*! \brief MMD address of structure AQ_GlobalReservedStatus_APPIA */ -#define AQ_GlobalReservedStatus_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure nearlySecondsMSW in AQ_GlobalReservedStatus_APPIA */ -#define AQ_GlobalReservedStatus_APPIA_nearlySecondsMSW 0 -/*! \brief Preprocessor variable to relate field to bit position in structure nearlySecondsMSW in AQ_GlobalReservedStatus_APPIA */ -#define bits_AQ_GlobalReservedStatus_APPIA_nearlySecondsMSW u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure nearlySecondsMSW in AQ_GlobalReservedStatus_APPIA */ -#define word_AQ_GlobalReservedStatus_APPIA_nearlySecondsMSW u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure xenpakNvrStatus in AQ_GlobalReservedStatus_APPIA */ -#define AQ_GlobalReservedStatus_APPIA_xenpakNvrStatus 0 -/*! \brief Preprocessor variable to relate field to bit position in structure xenpakNvrStatus in AQ_GlobalReservedStatus_APPIA */ -#define bits_AQ_GlobalReservedStatus_APPIA_xenpakNvrStatus u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure xenpakNvrStatus in AQ_GlobalReservedStatus_APPIA */ -#define word_AQ_GlobalReservedStatus_APPIA_xenpakNvrStatus u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure romRevision in AQ_GlobalReservedStatus_APPIA */ -#define AQ_GlobalReservedStatus_APPIA_romRevision 0 -/*! \brief Preprocessor variable to relate field to bit position in structure romRevision in AQ_GlobalReservedStatus_APPIA */ -#define bits_AQ_GlobalReservedStatus_APPIA_romRevision u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure romRevision in AQ_GlobalReservedStatus_APPIA */ -#define word_AQ_GlobalReservedStatus_APPIA_romRevision u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure nearlySecondsLSW in AQ_GlobalReservedStatus_APPIA */ -#define AQ_GlobalReservedStatus_APPIA_nearlySecondsLSW 1 -/*! \brief Preprocessor variable to relate field to bit position in structure nearlySecondsLSW in AQ_GlobalReservedStatus_APPIA */ -#define bits_AQ_GlobalReservedStatus_APPIA_nearlySecondsLSW u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure nearlySecondsLSW in AQ_GlobalReservedStatus_APPIA */ -#define word_AQ_GlobalReservedStatus_APPIA_nearlySecondsLSW u1.word_1 - -/*! \brief Base register address of structure AQ_GlobalAlarms_APPIA */ -#define AQ_GlobalAlarms_APPIA_baseRegisterAddress 0xCC00 -/*! \brief MMD address of structure AQ_GlobalAlarms_APPIA */ -#define AQ_GlobalAlarms_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureFailure in AQ_GlobalAlarms_APPIA */ -#define AQ_GlobalAlarms_APPIA_highTemperatureFailure 0 -/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureFailure in AQ_GlobalAlarms_APPIA */ -#define bits_AQ_GlobalAlarms_APPIA_highTemperatureFailure u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureFailure in AQ_GlobalAlarms_APPIA */ -#define word_AQ_GlobalAlarms_APPIA_highTemperatureFailure u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureFailure in AQ_GlobalAlarms_APPIA */ -#define AQ_GlobalAlarms_APPIA_lowTemperatureFailure 0 -/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureFailure in AQ_GlobalAlarms_APPIA */ -#define bits_AQ_GlobalAlarms_APPIA_lowTemperatureFailure u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureFailure in AQ_GlobalAlarms_APPIA */ -#define word_AQ_GlobalAlarms_APPIA_lowTemperatureFailure u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureWarning in AQ_GlobalAlarms_APPIA */ -#define AQ_GlobalAlarms_APPIA_highTemperatureWarning 0 -/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureWarning in AQ_GlobalAlarms_APPIA */ -#define bits_AQ_GlobalAlarms_APPIA_highTemperatureWarning u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureWarning in AQ_GlobalAlarms_APPIA */ -#define word_AQ_GlobalAlarms_APPIA_highTemperatureWarning u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureWarning in AQ_GlobalAlarms_APPIA */ -#define AQ_GlobalAlarms_APPIA_lowTemperatureWarning 0 -/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureWarning in AQ_GlobalAlarms_APPIA */ -#define bits_AQ_GlobalAlarms_APPIA_lowTemperatureWarning u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureWarning in AQ_GlobalAlarms_APPIA */ -#define word_AQ_GlobalAlarms_APPIA_lowTemperatureWarning u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure resetCompleted in AQ_GlobalAlarms_APPIA */ -#define AQ_GlobalAlarms_APPIA_resetCompleted 0 -/*! \brief Preprocessor variable to relate field to bit position in structure resetCompleted in AQ_GlobalAlarms_APPIA */ -#define bits_AQ_GlobalAlarms_APPIA_resetCompleted u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure resetCompleted in AQ_GlobalAlarms_APPIA */ -#define word_AQ_GlobalAlarms_APPIA_resetCompleted u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure deviceFault in AQ_GlobalAlarms_APPIA */ -#define AQ_GlobalAlarms_APPIA_deviceFault 0 -/*! \brief Preprocessor variable to relate field to bit position in structure deviceFault in AQ_GlobalAlarms_APPIA */ -#define bits_AQ_GlobalAlarms_APPIA_deviceFault u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure deviceFault in AQ_GlobalAlarms_APPIA */ -#define word_AQ_GlobalAlarms_APPIA_deviceFault u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmA in AQ_GlobalAlarms_APPIA */ -#define AQ_GlobalAlarms_APPIA_reservedAlarmA 0 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmA in AQ_GlobalAlarms_APPIA */ -#define bits_AQ_GlobalAlarms_APPIA_reservedAlarmA u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmA in AQ_GlobalAlarms_APPIA */ -#define word_AQ_GlobalAlarms_APPIA_reservedAlarmA u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmB in AQ_GlobalAlarms_APPIA */ -#define AQ_GlobalAlarms_APPIA_reservedAlarmB 0 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmB in AQ_GlobalAlarms_APPIA */ -#define bits_AQ_GlobalAlarms_APPIA_reservedAlarmB u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmB in AQ_GlobalAlarms_APPIA */ -#define word_AQ_GlobalAlarms_APPIA_reservedAlarmB u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmC in AQ_GlobalAlarms_APPIA */ -#define AQ_GlobalAlarms_APPIA_reservedAlarmC 0 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmC in AQ_GlobalAlarms_APPIA */ -#define bits_AQ_GlobalAlarms_APPIA_reservedAlarmC u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmC in AQ_GlobalAlarms_APPIA */ -#define word_AQ_GlobalAlarms_APPIA_reservedAlarmC u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmD in AQ_GlobalAlarms_APPIA */ -#define AQ_GlobalAlarms_APPIA_reservedAlarmD 0 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmD in AQ_GlobalAlarms_APPIA */ -#define bits_AQ_GlobalAlarms_APPIA_reservedAlarmD u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmD in AQ_GlobalAlarms_APPIA */ -#define word_AQ_GlobalAlarms_APPIA_reservedAlarmD u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure smartPower_downEntered in AQ_GlobalAlarms_APPIA */ -#define AQ_GlobalAlarms_APPIA_smartPower_downEntered 1 -/*! \brief Preprocessor variable to relate field to bit position in structure smartPower_downEntered in AQ_GlobalAlarms_APPIA */ -#define bits_AQ_GlobalAlarms_APPIA_smartPower_downEntered u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure smartPower_downEntered in AQ_GlobalAlarms_APPIA */ -#define word_AQ_GlobalAlarms_APPIA_smartPower_downEntered u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure xenpakAlarm in AQ_GlobalAlarms_APPIA */ -#define AQ_GlobalAlarms_APPIA_xenpakAlarm 1 -/*! \brief Preprocessor variable to relate field to bit position in structure xenpakAlarm in AQ_GlobalAlarms_APPIA */ -#define bits_AQ_GlobalAlarms_APPIA_xenpakAlarm u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure xenpakAlarm in AQ_GlobalAlarms_APPIA */ -#define word_AQ_GlobalAlarms_APPIA_xenpakAlarm u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarms in AQ_GlobalAlarms_APPIA */ -#define AQ_GlobalAlarms_APPIA_reservedAlarms 1 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarms in AQ_GlobalAlarms_APPIA */ -#define bits_AQ_GlobalAlarms_APPIA_reservedAlarms u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarms in AQ_GlobalAlarms_APPIA */ -#define word_AQ_GlobalAlarms_APPIA_reservedAlarms u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure mdioCommandHandlingOverflow in AQ_GlobalAlarms_APPIA */ -#define AQ_GlobalAlarms_APPIA_mdioCommandHandlingOverflow 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mdioCommandHandlingOverflow in AQ_GlobalAlarms_APPIA */ -#define bits_AQ_GlobalAlarms_APPIA_mdioCommandHandlingOverflow u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mdioCommandHandlingOverflow in AQ_GlobalAlarms_APPIA */ -#define word_AQ_GlobalAlarms_APPIA_mdioCommandHandlingOverflow u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure diagnosticAlarm in AQ_GlobalAlarms_APPIA */ -#define AQ_GlobalAlarms_APPIA_diagnosticAlarm 1 -/*! \brief Preprocessor variable to relate field to bit position in structure diagnosticAlarm in AQ_GlobalAlarms_APPIA */ -#define bits_AQ_GlobalAlarms_APPIA_diagnosticAlarm u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure diagnosticAlarm in AQ_GlobalAlarms_APPIA */ -#define word_AQ_GlobalAlarms_APPIA_diagnosticAlarm u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure nvrOperationComplete in AQ_GlobalAlarms_APPIA */ -#define AQ_GlobalAlarms_APPIA_nvrOperationComplete 2 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrOperationComplete in AQ_GlobalAlarms_APPIA */ -#define bits_AQ_GlobalAlarms_APPIA_nvrOperationComplete u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure nvrOperationComplete in AQ_GlobalAlarms_APPIA */ -#define word_AQ_GlobalAlarms_APPIA_nvrOperationComplete u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure mailboxOperation_Complete in AQ_GlobalAlarms_APPIA */ -#define AQ_GlobalAlarms_APPIA_mailboxOperation_Complete 2 -/*! \brief Preprocessor variable to relate field to bit position in structure mailboxOperation_Complete in AQ_GlobalAlarms_APPIA */ -#define bits_AQ_GlobalAlarms_APPIA_mailboxOperation_Complete u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure mailboxOperation_Complete in AQ_GlobalAlarms_APPIA */ -#define word_AQ_GlobalAlarms_APPIA_mailboxOperation_Complete u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure upDramParityError in AQ_GlobalAlarms_APPIA */ -#define AQ_GlobalAlarms_APPIA_upDramParityError 2 -/*! \brief Preprocessor variable to relate field to bit position in structure upDramParityError in AQ_GlobalAlarms_APPIA */ -#define bits_AQ_GlobalAlarms_APPIA_upDramParityError u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure upDramParityError in AQ_GlobalAlarms_APPIA */ -#define word_AQ_GlobalAlarms_APPIA_upDramParityError u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure upIramParityError in AQ_GlobalAlarms_APPIA */ -#define AQ_GlobalAlarms_APPIA_upIramParityError 2 -/*! \brief Preprocessor variable to relate field to bit position in structure upIramParityError in AQ_GlobalAlarms_APPIA */ -#define bits_AQ_GlobalAlarms_APPIA_upIramParityError u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure upIramParityError in AQ_GlobalAlarms_APPIA */ -#define word_AQ_GlobalAlarms_APPIA_upIramParityError u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure txEnableStateChange in AQ_GlobalAlarms_APPIA */ -#define AQ_GlobalAlarms_APPIA_txEnableStateChange 2 -/*! \brief Preprocessor variable to relate field to bit position in structure txEnableStateChange in AQ_GlobalAlarms_APPIA */ -#define bits_AQ_GlobalAlarms_APPIA_txEnableStateChange u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure txEnableStateChange in AQ_GlobalAlarms_APPIA */ -#define word_AQ_GlobalAlarms_APPIA_txEnableStateChange u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure mdioMMD_Error in AQ_GlobalAlarms_APPIA */ -#define AQ_GlobalAlarms_APPIA_mdioMMD_Error 2 -/*! \brief Preprocessor variable to relate field to bit position in structure mdioMMD_Error in AQ_GlobalAlarms_APPIA */ -#define bits_AQ_GlobalAlarms_APPIA_mdioMMD_Error u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure mdioMMD_Error in AQ_GlobalAlarms_APPIA */ -#define word_AQ_GlobalAlarms_APPIA_mdioMMD_Error u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure mdioTimeoutError in AQ_GlobalAlarms_APPIA */ -#define AQ_GlobalAlarms_APPIA_mdioTimeoutError 2 -/*! \brief Preprocessor variable to relate field to bit position in structure mdioTimeoutError in AQ_GlobalAlarms_APPIA */ -#define bits_AQ_GlobalAlarms_APPIA_mdioTimeoutError u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure mdioTimeoutError in AQ_GlobalAlarms_APPIA */ -#define word_AQ_GlobalAlarms_APPIA_mdioTimeoutError u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure watchdogTimerAlarm in AQ_GlobalAlarms_APPIA */ -#define AQ_GlobalAlarms_APPIA_watchdogTimerAlarm 2 -/*! \brief Preprocessor variable to relate field to bit position in structure watchdogTimerAlarm in AQ_GlobalAlarms_APPIA */ -#define bits_AQ_GlobalAlarms_APPIA_watchdogTimerAlarm u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure watchdogTimerAlarm in AQ_GlobalAlarms_APPIA */ -#define word_AQ_GlobalAlarms_APPIA_watchdogTimerAlarm u2.word_2 - -/*! \brief Base register address of structure AQ_GlobalInterruptMask_APPIA */ -#define AQ_GlobalInterruptMask_APPIA_baseRegisterAddress 0xD400 -/*! \brief MMD address of structure AQ_GlobalInterruptMask_APPIA */ -#define AQ_GlobalInterruptMask_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureFailureMask in AQ_GlobalInterruptMask_APPIA */ -#define AQ_GlobalInterruptMask_APPIA_highTemperatureFailureMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureFailureMask in AQ_GlobalInterruptMask_APPIA */ -#define bits_AQ_GlobalInterruptMask_APPIA_highTemperatureFailureMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureFailureMask in AQ_GlobalInterruptMask_APPIA */ -#define word_AQ_GlobalInterruptMask_APPIA_highTemperatureFailureMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureFailureMask in AQ_GlobalInterruptMask_APPIA */ -#define AQ_GlobalInterruptMask_APPIA_lowTemperatureFailureMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureFailureMask in AQ_GlobalInterruptMask_APPIA */ -#define bits_AQ_GlobalInterruptMask_APPIA_lowTemperatureFailureMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureFailureMask in AQ_GlobalInterruptMask_APPIA */ -#define word_AQ_GlobalInterruptMask_APPIA_lowTemperatureFailureMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureWarningMask in AQ_GlobalInterruptMask_APPIA */ -#define AQ_GlobalInterruptMask_APPIA_highTemperatureWarningMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureWarningMask in AQ_GlobalInterruptMask_APPIA */ -#define bits_AQ_GlobalInterruptMask_APPIA_highTemperatureWarningMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureWarningMask in AQ_GlobalInterruptMask_APPIA */ -#define word_AQ_GlobalInterruptMask_APPIA_highTemperatureWarningMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureWarningMask in AQ_GlobalInterruptMask_APPIA */ -#define AQ_GlobalInterruptMask_APPIA_lowTemperatureWarningMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureWarningMask in AQ_GlobalInterruptMask_APPIA */ -#define bits_AQ_GlobalInterruptMask_APPIA_lowTemperatureWarningMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureWarningMask in AQ_GlobalInterruptMask_APPIA */ -#define word_AQ_GlobalInterruptMask_APPIA_lowTemperatureWarningMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure resetCompletedMask in AQ_GlobalInterruptMask_APPIA */ -#define AQ_GlobalInterruptMask_APPIA_resetCompletedMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure resetCompletedMask in AQ_GlobalInterruptMask_APPIA */ -#define bits_AQ_GlobalInterruptMask_APPIA_resetCompletedMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure resetCompletedMask in AQ_GlobalInterruptMask_APPIA */ -#define word_AQ_GlobalInterruptMask_APPIA_resetCompletedMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure deviceFaultMask in AQ_GlobalInterruptMask_APPIA */ -#define AQ_GlobalInterruptMask_APPIA_deviceFaultMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure deviceFaultMask in AQ_GlobalInterruptMask_APPIA */ -#define bits_AQ_GlobalInterruptMask_APPIA_deviceFaultMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure deviceFaultMask in AQ_GlobalInterruptMask_APPIA */ -#define word_AQ_GlobalInterruptMask_APPIA_deviceFaultMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmAMask in AQ_GlobalInterruptMask_APPIA */ -#define AQ_GlobalInterruptMask_APPIA_reservedAlarmAMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmAMask in AQ_GlobalInterruptMask_APPIA */ -#define bits_AQ_GlobalInterruptMask_APPIA_reservedAlarmAMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmAMask in AQ_GlobalInterruptMask_APPIA */ -#define word_AQ_GlobalInterruptMask_APPIA_reservedAlarmAMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmBMask in AQ_GlobalInterruptMask_APPIA */ -#define AQ_GlobalInterruptMask_APPIA_reservedAlarmBMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmBMask in AQ_GlobalInterruptMask_APPIA */ -#define bits_AQ_GlobalInterruptMask_APPIA_reservedAlarmBMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmBMask in AQ_GlobalInterruptMask_APPIA */ -#define word_AQ_GlobalInterruptMask_APPIA_reservedAlarmBMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmCMask in AQ_GlobalInterruptMask_APPIA */ -#define AQ_GlobalInterruptMask_APPIA_reservedAlarmCMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmCMask in AQ_GlobalInterruptMask_APPIA */ -#define bits_AQ_GlobalInterruptMask_APPIA_reservedAlarmCMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmCMask in AQ_GlobalInterruptMask_APPIA */ -#define word_AQ_GlobalInterruptMask_APPIA_reservedAlarmCMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmDMask in AQ_GlobalInterruptMask_APPIA */ -#define AQ_GlobalInterruptMask_APPIA_reservedAlarmDMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmDMask in AQ_GlobalInterruptMask_APPIA */ -#define bits_AQ_GlobalInterruptMask_APPIA_reservedAlarmDMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmDMask in AQ_GlobalInterruptMask_APPIA */ -#define word_AQ_GlobalInterruptMask_APPIA_reservedAlarmDMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure smartPower_downEnteredMask in AQ_GlobalInterruptMask_APPIA */ -#define AQ_GlobalInterruptMask_APPIA_smartPower_downEnteredMask 1 -/*! \brief Preprocessor variable to relate field to bit position in structure smartPower_downEnteredMask in AQ_GlobalInterruptMask_APPIA */ -#define bits_AQ_GlobalInterruptMask_APPIA_smartPower_downEnteredMask u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure smartPower_downEnteredMask in AQ_GlobalInterruptMask_APPIA */ -#define word_AQ_GlobalInterruptMask_APPIA_smartPower_downEnteredMask u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure xenpakAlarmMask in AQ_GlobalInterruptMask_APPIA */ -#define AQ_GlobalInterruptMask_APPIA_xenpakAlarmMask 1 -/*! \brief Preprocessor variable to relate field to bit position in structure xenpakAlarmMask in AQ_GlobalInterruptMask_APPIA */ -#define bits_AQ_GlobalInterruptMask_APPIA_xenpakAlarmMask u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure xenpakAlarmMask in AQ_GlobalInterruptMask_APPIA */ -#define word_AQ_GlobalInterruptMask_APPIA_xenpakAlarmMask u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmsMask in AQ_GlobalInterruptMask_APPIA */ -#define AQ_GlobalInterruptMask_APPIA_reservedAlarmsMask 1 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmsMask in AQ_GlobalInterruptMask_APPIA */ -#define bits_AQ_GlobalInterruptMask_APPIA_reservedAlarmsMask u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmsMask in AQ_GlobalInterruptMask_APPIA */ -#define word_AQ_GlobalInterruptMask_APPIA_reservedAlarmsMask u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure mdioCommandHandlingOverflowMask in AQ_GlobalInterruptMask_APPIA */ -#define AQ_GlobalInterruptMask_APPIA_mdioCommandHandlingOverflowMask 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mdioCommandHandlingOverflowMask in AQ_GlobalInterruptMask_APPIA */ -#define bits_AQ_GlobalInterruptMask_APPIA_mdioCommandHandlingOverflowMask u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mdioCommandHandlingOverflowMask in AQ_GlobalInterruptMask_APPIA */ -#define word_AQ_GlobalInterruptMask_APPIA_mdioCommandHandlingOverflowMask u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure diagnosticAlarmMask in AQ_GlobalInterruptMask_APPIA */ -#define AQ_GlobalInterruptMask_APPIA_diagnosticAlarmMask 1 -/*! \brief Preprocessor variable to relate field to bit position in structure diagnosticAlarmMask in AQ_GlobalInterruptMask_APPIA */ -#define bits_AQ_GlobalInterruptMask_APPIA_diagnosticAlarmMask u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure diagnosticAlarmMask in AQ_GlobalInterruptMask_APPIA */ -#define word_AQ_GlobalInterruptMask_APPIA_diagnosticAlarmMask u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure nvrOperationCompleteMask in AQ_GlobalInterruptMask_APPIA */ -#define AQ_GlobalInterruptMask_APPIA_nvrOperationCompleteMask 2 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrOperationCompleteMask in AQ_GlobalInterruptMask_APPIA */ -#define bits_AQ_GlobalInterruptMask_APPIA_nvrOperationCompleteMask u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure nvrOperationCompleteMask in AQ_GlobalInterruptMask_APPIA */ -#define word_AQ_GlobalInterruptMask_APPIA_nvrOperationCompleteMask u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure mailboxOperationCompleteMask in AQ_GlobalInterruptMask_APPIA */ -#define AQ_GlobalInterruptMask_APPIA_mailboxOperationCompleteMask 2 -/*! \brief Preprocessor variable to relate field to bit position in structure mailboxOperationCompleteMask in AQ_GlobalInterruptMask_APPIA */ -#define bits_AQ_GlobalInterruptMask_APPIA_mailboxOperationCompleteMask u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure mailboxOperationCompleteMask in AQ_GlobalInterruptMask_APPIA */ -#define word_AQ_GlobalInterruptMask_APPIA_mailboxOperationCompleteMask u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure upDramParityErrorMask in AQ_GlobalInterruptMask_APPIA */ -#define AQ_GlobalInterruptMask_APPIA_upDramParityErrorMask 2 -/*! \brief Preprocessor variable to relate field to bit position in structure upDramParityErrorMask in AQ_GlobalInterruptMask_APPIA */ -#define bits_AQ_GlobalInterruptMask_APPIA_upDramParityErrorMask u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure upDramParityErrorMask in AQ_GlobalInterruptMask_APPIA */ -#define word_AQ_GlobalInterruptMask_APPIA_upDramParityErrorMask u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure upIramParityErrorMask in AQ_GlobalInterruptMask_APPIA */ -#define AQ_GlobalInterruptMask_APPIA_upIramParityErrorMask 2 -/*! \brief Preprocessor variable to relate field to bit position in structure upIramParityErrorMask in AQ_GlobalInterruptMask_APPIA */ -#define bits_AQ_GlobalInterruptMask_APPIA_upIramParityErrorMask u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure upIramParityErrorMask in AQ_GlobalInterruptMask_APPIA */ -#define word_AQ_GlobalInterruptMask_APPIA_upIramParityErrorMask u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure txEnableStateChangeMask in AQ_GlobalInterruptMask_APPIA */ -#define AQ_GlobalInterruptMask_APPIA_txEnableStateChangeMask 2 -/*! \brief Preprocessor variable to relate field to bit position in structure txEnableStateChangeMask in AQ_GlobalInterruptMask_APPIA */ -#define bits_AQ_GlobalInterruptMask_APPIA_txEnableStateChangeMask u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure txEnableStateChangeMask in AQ_GlobalInterruptMask_APPIA */ -#define word_AQ_GlobalInterruptMask_APPIA_txEnableStateChangeMask u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure mdioMMD_ErrorMask in AQ_GlobalInterruptMask_APPIA */ -#define AQ_GlobalInterruptMask_APPIA_mdioMMD_ErrorMask 2 -/*! \brief Preprocessor variable to relate field to bit position in structure mdioMMD_ErrorMask in AQ_GlobalInterruptMask_APPIA */ -#define bits_AQ_GlobalInterruptMask_APPIA_mdioMMD_ErrorMask u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure mdioMMD_ErrorMask in AQ_GlobalInterruptMask_APPIA */ -#define word_AQ_GlobalInterruptMask_APPIA_mdioMMD_ErrorMask u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure mdioTimeoutErrorMask in AQ_GlobalInterruptMask_APPIA */ -#define AQ_GlobalInterruptMask_APPIA_mdioTimeoutErrorMask 2 -/*! \brief Preprocessor variable to relate field to bit position in structure mdioTimeoutErrorMask in AQ_GlobalInterruptMask_APPIA */ -#define bits_AQ_GlobalInterruptMask_APPIA_mdioTimeoutErrorMask u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure mdioTimeoutErrorMask in AQ_GlobalInterruptMask_APPIA */ -#define word_AQ_GlobalInterruptMask_APPIA_mdioTimeoutErrorMask u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure watchdogTimerAlarmMask in AQ_GlobalInterruptMask_APPIA */ -#define AQ_GlobalInterruptMask_APPIA_watchdogTimerAlarmMask 2 -/*! \brief Preprocessor variable to relate field to bit position in structure watchdogTimerAlarmMask in AQ_GlobalInterruptMask_APPIA */ -#define bits_AQ_GlobalInterruptMask_APPIA_watchdogTimerAlarmMask u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure watchdogTimerAlarmMask in AQ_GlobalInterruptMask_APPIA */ -#define word_AQ_GlobalInterruptMask_APPIA_watchdogTimerAlarmMask u2.word_2 - -/*! \brief Base register address of structure AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_baseRegisterAddress 0xFC00 -/*! \brief MMD address of structure AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure pmaStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pmaStandardAlarm_1Interrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pmaStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pmaStandardAlarm_1Interrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pmaStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pmaStandardAlarm_1Interrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pmaStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pmaStandardAlarm_2Interrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pmaStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pmaStandardAlarm_2Interrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pmaStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pmaStandardAlarm_2Interrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pcsStandardAlarm_1Interrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pcsStandardAlarm_1Interrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pcsStandardAlarm_1Interrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pcsStandardAlarm_2Interrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pcsStandardAlarm_2Interrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pcsStandardAlarm_2Interrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_3Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pcsStandardAlarm_3Interrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_3Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pcsStandardAlarm_3Interrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_3Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_pcsStandardAlarm_3Interrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure phyXS_StandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_phyXS_StandardAlarms_1Interrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_StandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_phyXS_StandardAlarms_1Interrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure phyXS_StandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_phyXS_StandardAlarms_1Interrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure phyXS_StandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_phyXS_StandardAlarms_2Interrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_StandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_phyXS_StandardAlarms_2Interrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure phyXS_StandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_phyXS_StandardAlarms_2Interrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationStandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_autonegotiationStandardAlarms_1Interrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationStandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_autonegotiationStandardAlarms_1Interrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationStandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_autonegotiationStandardAlarms_1Interrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationStandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_autonegotiationStandardAlarms_2Interrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationStandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_autonegotiationStandardAlarms_2Interrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationStandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_autonegotiationStandardAlarms_2Interrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure gbeStandardAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_gbeStandardAlarmsInterrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure gbeStandardAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_gbeStandardAlarmsInterrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure gbeStandardAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_gbeStandardAlarmsInterrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure allVendorAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define AQ_GlobalChip_wideStandardInterruptFlags_APPIA_allVendorAlarmsInterrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure allVendorAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define bits_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_allVendorAlarmsInterrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure allVendorAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_APPIA */ -#define word_AQ_GlobalChip_wideStandardInterruptFlags_APPIA_allVendorAlarmsInterrupt u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ -#define AQ_GlobalChip_wideVendorInterruptFlags_APPIA_baseRegisterAddress 0xFC01 -/*! \brief MMD address of structure AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ -#define AQ_GlobalChip_wideVendorInterruptFlags_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure pmaVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ -#define AQ_GlobalChip_wideVendorInterruptFlags_APPIA_pmaVendorAlarmInterrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pmaVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ -#define bits_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_pmaVendorAlarmInterrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pmaVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ -#define word_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_pmaVendorAlarmInterrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pcsVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ -#define AQ_GlobalChip_wideVendorInterruptFlags_APPIA_pcsVendorAlarmInterrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pcsVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ -#define bits_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_pcsVendorAlarmInterrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pcsVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ -#define word_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_pcsVendorAlarmInterrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure phyXS_VendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ -#define AQ_GlobalChip_wideVendorInterruptFlags_APPIA_phyXS_VendorAlarmInterrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_VendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ -#define bits_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_phyXS_VendorAlarmInterrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure phyXS_VendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ -#define word_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_phyXS_VendorAlarmInterrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ -#define AQ_GlobalChip_wideVendorInterruptFlags_APPIA_autonegotiationVendorAlarmInterrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ -#define bits_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_autonegotiationVendorAlarmInterrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ -#define word_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_autonegotiationVendorAlarmInterrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure gbeVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ -#define AQ_GlobalChip_wideVendorInterruptFlags_APPIA_gbeVendorAlarmInterrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure gbeVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ -#define bits_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_gbeVendorAlarmInterrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure gbeVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ -#define word_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_gbeVendorAlarmInterrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_1Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ -#define AQ_GlobalChip_wideVendorInterruptFlags_APPIA_globalAlarms_1Interrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_1Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ -#define bits_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_globalAlarms_1Interrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_1Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ -#define word_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_globalAlarms_1Interrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_2Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ -#define AQ_GlobalChip_wideVendorInterruptFlags_APPIA_globalAlarms_2Interrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_2Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ -#define bits_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_globalAlarms_2Interrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_2Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ -#define word_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_globalAlarms_2Interrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_3Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ -#define AQ_GlobalChip_wideVendorInterruptFlags_APPIA_globalAlarms_3Interrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_3Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ -#define bits_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_globalAlarms_3Interrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_3Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_APPIA */ -#define word_AQ_GlobalChip_wideVendorInterruptFlags_APPIA_globalAlarms_3Interrupt u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_baseRegisterAddress 0xFF00 -/*! \brief MMD address of structure AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure pmaStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_pmaStandardAlarm_1InterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pmaStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_pmaStandardAlarm_1InterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pmaStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_pmaStandardAlarm_1InterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pmaStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_pmaStandardAlarm_2InterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pmaStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_pmaStandardAlarm_2InterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pmaStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_pmaStandardAlarm_2InterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_pcsStandardAlarm_1InterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_pcsStandardAlarm_1InterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_pcsStandardAlarm_1InterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_pcsStandardAlarm_2InterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_pcsStandardAlarm_2InterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_pcsStandardAlarm_2InterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_3InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_pcsStandardAlarm_3InterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_3InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_pcsStandardAlarm_3InterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_3InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_pcsStandardAlarm_3InterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure phyXS_StandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_phyXS_StandardAlarms_1InterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_StandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_phyXS_StandardAlarms_1InterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure phyXS_StandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_phyXS_StandardAlarms_1InterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure phyXS_StandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_phyXS_StandardAlarms_2InterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_StandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_phyXS_StandardAlarms_2InterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure phyXS_StandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_phyXS_StandardAlarms_2InterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationStandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_autonegotiationStandardAlarms_1InterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationStandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_autonegotiationStandardAlarms_1InterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationStandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_autonegotiationStandardAlarms_1InterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationStandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_autonegotiationStandardAlarms_2InterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationStandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_autonegotiationStandardAlarms_2InterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationStandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_autonegotiationStandardAlarms_2InterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure gbeStandardAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_gbeStandardAlarmsInterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure gbeStandardAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_gbeStandardAlarmsInterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure gbeStandardAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_gbeStandardAlarmsInterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure allVendorAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define AQ_GlobalInterruptChip_wideStandardMask_APPIA_allVendorAlarmsInterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure allVendorAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define bits_AQ_GlobalInterruptChip_wideStandardMask_APPIA_allVendorAlarmsInterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure allVendorAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_APPIA */ -#define word_AQ_GlobalInterruptChip_wideStandardMask_APPIA_allVendorAlarmsInterruptMask u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalInterruptChip_wideVendorMask_APPIA */ -#define AQ_GlobalInterruptChip_wideVendorMask_APPIA_baseRegisterAddress 0xFF01 -/*! \brief MMD address of structure AQ_GlobalInterruptChip_wideVendorMask_APPIA */ -#define AQ_GlobalInterruptChip_wideVendorMask_APPIA_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure pmaVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ -#define AQ_GlobalInterruptChip_wideVendorMask_APPIA_pmaVendorAlarmInterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pmaVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ -#define bits_AQ_GlobalInterruptChip_wideVendorMask_APPIA_pmaVendorAlarmInterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pmaVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ -#define word_AQ_GlobalInterruptChip_wideVendorMask_APPIA_pmaVendorAlarmInterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pcsVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ -#define AQ_GlobalInterruptChip_wideVendorMask_APPIA_pcsVendorAlarmInterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pcsVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ -#define bits_AQ_GlobalInterruptChip_wideVendorMask_APPIA_pcsVendorAlarmInterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pcsVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ -#define word_AQ_GlobalInterruptChip_wideVendorMask_APPIA_pcsVendorAlarmInterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure phyXS_VendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ -#define AQ_GlobalInterruptChip_wideVendorMask_APPIA_phyXS_VendorAlarmInterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_VendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ -#define bits_AQ_GlobalInterruptChip_wideVendorMask_APPIA_phyXS_VendorAlarmInterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure phyXS_VendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ -#define word_AQ_GlobalInterruptChip_wideVendorMask_APPIA_phyXS_VendorAlarmInterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ -#define AQ_GlobalInterruptChip_wideVendorMask_APPIA_autonegotiationVendorAlarmInterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ -#define bits_AQ_GlobalInterruptChip_wideVendorMask_APPIA_autonegotiationVendorAlarmInterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ -#define word_AQ_GlobalInterruptChip_wideVendorMask_APPIA_autonegotiationVendorAlarmInterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure gbeVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ -#define AQ_GlobalInterruptChip_wideVendorMask_APPIA_gbeVendorAlarmInterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure gbeVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ -#define bits_AQ_GlobalInterruptChip_wideVendorMask_APPIA_gbeVendorAlarmInterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure gbeVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ -#define word_AQ_GlobalInterruptChip_wideVendorMask_APPIA_gbeVendorAlarmInterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ -#define AQ_GlobalInterruptChip_wideVendorMask_APPIA_globalAlarms_1InterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ -#define bits_AQ_GlobalInterruptChip_wideVendorMask_APPIA_globalAlarms_1InterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ -#define word_AQ_GlobalInterruptChip_wideVendorMask_APPIA_globalAlarms_1InterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ -#define AQ_GlobalInterruptChip_wideVendorMask_APPIA_globalAlarms_2InterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ -#define bits_AQ_GlobalInterruptChip_wideVendorMask_APPIA_globalAlarms_2InterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ -#define word_AQ_GlobalInterruptChip_wideVendorMask_APPIA_globalAlarms_2InterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_3InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ -#define AQ_GlobalInterruptChip_wideVendorMask_APPIA_globalAlarms_3InterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_3InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ -#define bits_AQ_GlobalInterruptChip_wideVendorMask_APPIA_globalAlarms_3InterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_3InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_APPIA */ -#define word_AQ_GlobalInterruptChip_wideVendorMask_APPIA_globalAlarms_3InterruptMask u0.word_0 -#endif -/*@}*/ -/*@}*/ diff --git a/qca/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers_reversed.h b/qca/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers_reversed.h deleted file mode 100644 index 89e02c325..000000000 --- a/qca/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers_reversed.h +++ /dev/null @@ -1,5581 +0,0 @@ -/*! \file -* This file contains the data structures and doxygen comments -* for the Global Registers block. - */ - -/*! \addtogroup registerMap - @{ -*/ - -/*! \defgroup Global_registers Global Registers -* This module contains the data structures and doxygen comments -* for the Global Registers block. - */ -/*********************************************************************** -* Copyright (c) 2015, Aquantia -* -* Permission to use, copy, modify, and/or distribute this software for any -* purpose with or without fee is hereby granted, provided that the above -* copyright notice and this permission notice appear in all copies. -* -* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -* -* $Date: 2014/04/08 $ -* -* $Label: $ -* -* Description: -* -* This file contains the c header structures for the registers contained in the Global Registers block. -* -* The bit fields in this structure are from MSbit to LSbit -* -***********************************************************************/ - - -/*@{*/ -#ifndef AQ_APPIA_GLOBAL_REGS_HEADER -#define AQ_APPIA_GLOBAL_REGS_HEADER - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Standard Control 1: 1E.0000 */ -/* Global Standard Control 1: 1E.0000 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Standard Control 1 */ - union - { - struct - { - /*! \brief 1E.0000.F R/WSC Soft Reset - AQ_GlobalStandardControl_1_APPIA.u0.bits_0.softReset - - Default = 0x1 - - 1 = Global soft reset - 0 = Normal operation - - - Notes: - Setting this bit initiates a global soft reset on all of the digital logic, including the microprocessor. Upon completion of the reset sequence, this bit is set back to 0. */ - unsigned int softReset : 1; /* 1E.0000.F R/WSC Default = 0x1 */ - /* 1 = Global soft reset - 0 = Normal operation - */ - /*! \brief 1E.0000.E R/WSC Hard Reset - AQ_GlobalStandardControl_1_APPIA.u0.bits_0.hardReset - - Default = 0x0 - - 1 = Global hard reset - 0 = Normal operation - - - Notes: - Setting this bit initiates a global hard reset, equivalent to pulling the reset pin low. This is a level sensitive pin that connects into the power-on reset generation circuitry to initiate a complete power-on reset. */ - unsigned int hardReset : 1; /* 1E.0000.E R/WSC Default = 0x0 */ - /* 1 = Global hard reset - 0 = Normal operation - */ - unsigned int reserved0 : 2; - /*! \brief 1E.0000.B R/WPD Low Power - AQ_GlobalStandardControl_1_APPIA.u0.bits_0.lowPower - - Provisionable Default = 0x0 - - 1 = Low-power mode - 0 = Normal operation - - - Notes: - A one written to this register causes the chip to enter low-power mode. This bit puts the entire chip in low-power mode, with only the MDIO and microprocessor functioning, and turns off the analog front-end: i.e. places it in high-impedance mode. Setting this bit also sets all of the Low Power bits in the other MMDs. */ - unsigned int lowPower : 1; /* 1E.0000.B R/WPD Provisionable Default = 0x0 */ - /* 1 = Low-power mode - 0 = Normal operation - */ - unsigned int reserved1 : 11; - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalStandardControl_1_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Standard Device Identifier: 1E.0002 */ -/* Global Standard Device Identifier: 1E.0002 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Standard Device Identifier */ - union - { - struct - { - /*! \brief 1E.0002.F:0 RO Device ID MSW [1F:10] - AQ_GlobalStandardDeviceIdentifier_APPIA.u0.bits_0.deviceIdMSW - - - - Bits 31 - 16 of Device ID - */ - unsigned int deviceIdMSW : 16; /* 1E.0002.F:0 RO */ - /* Bits 31 - 16 of Device ID */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Standard Device Identifier */ - union - { - struct - { - /*! \brief 1E.0003.F:0 RO Device ID LSW [F:0] - AQ_GlobalStandardDeviceIdentifier_APPIA.u1.bits_1.deviceIdLSW - - - - Bits 15 - 0 of Device ID - */ - unsigned int deviceIdLSW : 16; /* 1E.0003.F:0 RO */ - /* Bits 15 - 0 of Device ID */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_GlobalStandardDeviceIdentifier_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Standard Devices in Package: 1E.0005 */ -/* Global Standard Devices in Package: 1E.0005 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Standard Devices in Package */ - union - { - struct - { - unsigned int reserved0 : 8; - /*! \brief 1E.0005.7 ROS Autonegotiation Present - AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.autonegotiationPresent - - Default = 0x1 - - 1 = Autonegotiation is present in package - 0 = Autonegotiation is not present in package - - Notes: - This is always set to 1, as there is Autonegotiation in the PHY. */ - unsigned int autonegotiationPresent : 1; /* 1E.0005.7 ROS Default = 0x1 */ - /* 1 = Autonegotiation is present in package - 0 = Autonegotiation is not present in package */ - /*! \brief 1E.0005.6 ROS TC Present - AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.tcPresent - - Default = 0x0 - - 1 = TC is present in package - 0 = TC is not present in package - - Notes: - This is always set to 0, as there is no TC functionality in the PHY. */ - unsigned int tcPresent : 1; /* 1E.0005.6 ROS Default = 0x0 */ - /* 1 = TC is present in package - 0 = TC is not present in package */ - /*! \brief 1E.0005.5 ROS DTE XS Present - AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.dteXsPresent - - Default = 0x0 - - 1 = DTE XS is present in package - 0 = DTE XS is not present in package - - - Notes: - This is always set to 0, as there is no DTE XAUI interface in the PHY. */ - unsigned int dteXsPresent : 1; /* 1E.0005.5 ROS Default = 0x0 */ - /* 1 = DTE XS is present in package - 0 = DTE XS is not present in package - */ - /*! \brief 1E.0005.4 ROS PHY XS Present - AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.phyXS_Present - - Default = 0x1 - - 1 = PHY XS is present in package - 0 = PHY XS is not present in package - - Notes: - This is always set to 1 as there is a PHY XS interface in the PHY. */ - unsigned int phyXS_Present : 1; /* 1E.0005.4 ROS Default = 0x1 */ - /* 1 = PHY XS is present in package - 0 = PHY XS is not present in package */ - /*! \brief 1E.0005.3 ROS PCS Present - AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.pcsPresent - - Default = 0x1 - - 1 = PCS is present in package - 0 = PCS is not present in package - - Notes: - This is always set to 1 as there is PCS functionality in the PHY. */ - unsigned int pcsPresent : 1; /* 1E.0005.3 ROS Default = 0x1 */ - /* 1 = PCS is present in package - 0 = PCS is not present in package */ - /*! \brief 1E.0005.2 ROS WIS Present - AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.wisPresent - - Default = 0x0 - - 1 = WIS is present in package - 0 = WIS is not present in package - - Notes: - This is always set to 0, as there is no WIS functionality in the PHY. */ - unsigned int wisPresent : 1; /* 1E.0005.2 ROS Default = 0x0 */ - /* 1 = WIS is present in package - 0 = WIS is not present in package */ - /*! \brief 1E.0005.1 ROS PMA Present - AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.pmaPresent - - Default = 0x1 - - 1 = PMA is present in package - 0 = PMA is not present - - Notes: - This is always set to 1 as there is PMA functionality in the PHY. */ - unsigned int pmaPresent : 1; /* 1E.0005.1 ROS Default = 0x1 */ - /* 1 = PMA is present in package - 0 = PMA is not present */ - /*! \brief 1E.0005.0 ROS Clause 22 Registers Present - AQ_GlobalStandardDevicesInPackage_APPIA.u0.bits_0.clause_22RegistersPresent - - Default = 0x0 - - 1 = Clause 22 registers are present in package - 0 = Clause 22 registers are not present in package - - Notes: - This is always set to 0 in the PHY, as there are no Clause 22 registers in the device. */ - unsigned int clause_22RegistersPresent : 1; /* 1E.0005.0 ROS Default = 0x0 */ - /* 1 = Clause 22 registers are present in package - 0 = Clause 22 registers are not present in package */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalStandardDevicesInPackage_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Standard Vendor Devices in Package: 1E.0006 */ -/* Global Standard Vendor Devices in Package: 1E.0006 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Standard Vendor Devices in Package */ - union - { - struct - { - /*! \brief 1E.0006.F ROS Vendor Specific Device #2 Present - AQ_GlobalStandardVendorDevicesInPackage_APPIA.u0.bits_0.vendorSpecificDevice_2Present - - Default = 0x1 - - 1 = Device #2 is present in package - 0 = Device #2 is not present in package - - Notes: - This is always set to 1 as the PHY utilizes this device for the DSP PMA registers. */ - unsigned int vendorSpecificDevice_2Present : 1; /* 1E.0006.F ROS Default = 0x1 */ - /* 1 = Device #2 is present in package - 0 = Device #2 is not present in package */ - /*! \brief 1E.0006.E ROS Vendor Specific Device #1 Present - AQ_GlobalStandardVendorDevicesInPackage_APPIA.u0.bits_0.vendorSpecificDevice_1Present - - Default = 0x1 - - 1 = Device #1 is present in package - 0 = Device #1 is not present in package - - Notes: - This is always set to 1 as the PHY utilizes this device for the global control registers. */ - unsigned int vendorSpecificDevice_1Present : 1; /* 1E.0006.E ROS Default = 0x1 */ - /* 1 = Device #1 is present in package - 0 = Device #1 is not present in package */ - /*! \brief 1E.0006.D ROS Clause 22 Extension Present - AQ_GlobalStandardVendorDevicesInPackage_APPIA.u0.bits_0.clause_22ExtensionPresent - - Default = 0x1 - - 1 = Clause 22 Extension is present in package - 0 = Clause 22 Extension is not present in package - - Notes: - This is always set to 1 as the PHY utilizes this device for the GbE registers. */ - unsigned int clause_22ExtensionPresent : 1; /* 1E.0006.D ROS Default = 0x1 */ - /* 1 = Clause 22 Extension is present in package - 0 = Clause 22 Extension is not present in package */ - unsigned int reserved0 : 13; - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalStandardVendorDevicesInPackage_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Standard Status 2: 1E.0008 */ -/* Global Standard Status 2: 1E.0008 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Standard Status 2 */ - union - { - struct - { - /*! \brief 1E.0008.F:E ROS Device Present [1:0] - AQ_GlobalStandardStatus_2_APPIA.u0.bits_0.devicePresent - - Default = 0x2 - - [F:E] - 0x3 = No device at this address - 0x2 = Device present at this address - 0x1 = No device at this address - 0x0 = No device at this address - - Notes: - This field is always set to 0x2, as the Global MMD resides here in the PHY. */ - unsigned int devicePresent : 2; /* 1E.0008.F:E ROS Default = 0x2 */ - /* [F:E] - 0x3 = No device at this address - 0x2 = Device present at this address - 0x1 = No device at this address - 0x0 = No device at this address */ - unsigned int reserved0 : 14; - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalStandardStatus_2_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Standard Package Identifier: 1E.000E */ -/* Global Standard Package Identifier: 1E.000E */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Standard Package Identifier */ - union - { - struct - { - /*! \brief 1E.000E.F:0 RO Package ID MSW [1F:10] - AQ_GlobalStandardPackageIdentifier_APPIA.u0.bits_0.packageIdMSW - - - - Bits 31- 16 of Package ID - */ - unsigned int packageIdMSW : 16; /* 1E.000E.F:0 RO */ - /* Bits 31- 16 of Package ID */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Standard Package Identifier */ - union - { - struct - { - /*! \brief 1E.000F.F:0 RO Package ID LSW [F:0] - AQ_GlobalStandardPackageIdentifier_APPIA.u1.bits_1.packageIdLSW - - - - Bits 15 - 0 of Package ID - */ - unsigned int packageIdLSW : 16; /* 1E.000F.F:0 RO */ - /* Bits 15 - 0 of Package ID */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_GlobalStandardPackageIdentifier_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Firmware ID: 1E.0020 */ -/* Global Firmware ID: 1E.0020 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Firmware ID */ - union - { - struct - { - /*! \brief 1E.0020.F:8 RO Firmware Major Revision Number [7:0] - AQ_GlobalFirmwareID_APPIA.u0.bits_0.firmwareMajorRevisionNumber - - - - [F:8] = Major revision number - - Notes: - - - The lower six bits of major and minor firmware revision are exchanged in autonegotiation when the PHYID message is sent. */ - unsigned int firmwareMajorRevisionNumber : 8; /* 1E.0020.F:8 RO */ - /* [F:8] = Major revision number */ - /*! \brief 1E.0020.7:0 RO Firmware Minor Revision Number [7:0] - AQ_GlobalFirmwareID_APPIA.u0.bits_0.firmwareMinorRevisionNumber - - - - [7:0] = Minor revision number - - Notes: - - - The lower six bits of major and minor firmware revision are exchanged in autonegotiation when the PHYID message is sent. */ - unsigned int firmwareMinorRevisionNumber : 8; /* 1E.0020.7:0 RO */ - /* [7:0] = Minor revision number */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalFirmwareID_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Chip Identification: 1E.0021 */ -/* Global Chip Identification: 1E.0021 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Chip Identification */ - union - { - struct - { - /*! \brief 1E.0021.F:0 RO Chip Identification [F:0] - AQ_GlobalChipIdentification_APPIA.u0.bits_0.chipIdentification - - - - Hardware Chip ID - - Notes: - This value is a hard-coded chip ID */ - unsigned int chipIdentification : 16; /* 1E.0021.F:0 RO */ - /* Hardware Chip ID */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalChipIdentification_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Chip Revision: 1E.0022 */ -/* Global Chip Revision: 1E.0022 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Chip Revision */ - union - { - struct - { - /*! \brief 1E.0022.F:0 RO Chip Revision [F:0] - AQ_GlobalChipRevision_APPIA.u0.bits_0.chipRevision - - - - Hardware Chip Revision - - Notes: - This value is a hard-coded chip revision */ - unsigned int chipRevision : 16; /* 1E.0022.F:0 RO */ - /* Hardware Chip Revision */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalChipRevision_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global NVR Interface: 1E.0100 */ -/* Global NVR Interface: 1E.0100 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global NVR Interface */ - union - { - struct - { - /*! \brief 1E.0100.F R/WSC NVR Execute Operation - AQ_GlobalNvrInterface_APPIA.u0.bits_0.nvrExecuteOperation - - Default = 0x0 - - 1 = Start NVR Operation - - - Notes: - When set to 1, the NVR operation will begin. Ensure that the uP is stalled using the See MCP Run Stall bit to ensure no NVR contention. */ - unsigned int nvrExecuteOperation : 1; /* 1E.0100.F R/WSC Default = 0x0 */ - /* 1 = Start NVR Operation - */ - /*! \brief 1E.0100.E R/W NVR Write Mode - AQ_GlobalNvrInterface_APPIA.u0.bits_0.nvrWriteMode - - Default = 0x0 - - 1 = Write to NVR - 0 = Read from NVR - - */ - unsigned int nvrWriteMode : 1; /* 1E.0100.E R/W Default = 0x0 */ - /* 1 = Write to NVR - 0 = Read from NVR - */ - /*! \brief 1E.0100.D R/W Freeze NVR CRC - AQ_GlobalNvrInterface_APPIA.u0.bits_0.freezeNvrCrc - - Default = 0x0 - - 1 = Freeze NVR Mailbox CRC calculation register - - - Notes: - To prevent an erroneous answer, this bit should not be set at the same time the See NVR Operation Valid bit is set. */ - unsigned int freezeNvrCrc : 1; /* 1E.0100.D R/W Default = 0x0 */ - /* 1 = Freeze NVR Mailbox CRC calculation register - */ - /*! \brief 1E.0100.C R/WSC Reset NVR CRC - AQ_GlobalNvrInterface_APPIA.u0.bits_0.resetNvrCrc - - Default = 0x0 - - 1 = Reset NVR Mailbox CRC calculation register - - - Notes: - To prevent an erroneous answer, this bit should not be set at the same time the See NVR Operation Valid bit is set. */ - unsigned int resetNvrCrc : 1; /* 1E.0100.C R/WSC Default = 0x0 */ - /* 1 = Reset NVR Mailbox CRC calculation register - */ - unsigned int reserved0 : 1; - /*! \brief 1E.0100.A R/W NVR Burst - AQ_GlobalNvrInterface_APPIA.u0.bits_0.nvrBurst - - Default = 0x0 - - 0 = Single read or write operation of up to 4 bytes - 1 = Burst operation - - - Notes: - When this bit is set, the operation is a burst operation where more than 32-bits is read from the NVR or written to the NVR. This bit should be set to one until the last burst in the read or write operation, when it should be set to zero. It operates by gating the SPI clock, and not restarting it until new data is ready to be written, or the previous contents have been read. Each burst of data requires the NVR Execute Operation bit to be set to initiate the next phase. */ - unsigned int nvrBurst : 1; /* 1E.0100.A R/W Default = 0x0 */ - /* 0 = Single read or write operation of up to 4 bytes - 1 = Burst operation - */ - unsigned int reserved1 : 1; - /*! \brief 1E.0100.8 RO NVR Busy - AQ_GlobalNvrInterface_APPIA.u0.bits_0.nvrBusy - - - - 1 = NVR is busy - 0 = NVR is ready - - - Notes: - When set to 1, the NVR is busy. A new NVR operation should not occur until this bit is 0. If the NVR clock is greater than 64/63 of the MDIO clock, this bit never needs to be polled when operating over the MDIO. */ - unsigned int nvrBusy : 1; /* 1E.0100.8 RO */ - /* 1 = NVR is busy - 0 = NVR is ready - */ - /*! \brief 1E.0100.7:0 R/W NVR Opcode [7:0] - AQ_GlobalNvrInterface_APPIA.u0.bits_0.nvrOpcode - - Default = 0x03 - - NVR instruction opcode - - */ - unsigned int nvrOpcode : 8; /* 1E.0100.7:0 R/W Default = 0x03 */ - /* NVR instruction opcode - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global NVR Interface */ - union - { - struct - { - /*! \brief 1E.0101.F:0 RO NVR Mailbox CRC [F:0] - AQ_GlobalNvrInterface_APPIA.u1.bits_1.nvrMailboxCrc - - - - The running CRC-16 of everything passing through the NVR interface - - - Notes: - The CRC-16 over all data written or read through the NVR interface. The CRC-16 is calculated by dividing the data by: - x^16 + x^12 + x^5 + 1 */ - unsigned int nvrMailboxCrc : 16; /* 1E.0101.F:0 RO */ - /* The running CRC-16 of everything passing through the NVR interface - */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global NVR Interface */ - union - { - struct - { - unsigned int reserved0 : 8; - /*! \brief 1E.0102.7:0 R/W NVR Address MSW [17:10] - AQ_GlobalNvrInterface_APPIA.u2.bits_2.nvrAddressMSW - - Default = 0x00 - - NVR address MSW bits [17:10] - - - Notes: - The address of where to read and write from in the NVR. This is self-incrementing and will automatically increment after each read or write operation. The increment amount is based on the data length (i.e. increments by 4 if the data length is 4 bytes) */ - unsigned int nvrAddressMSW : 8; /* 1E.0102.7:0 R/W Default = 0x00 */ - /* NVR address MSW bits [17:10] - */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global NVR Interface */ - union - { - struct - { - /*! \brief 1E.0103.F:0 R/W NVR Address LSW [F:0] - AQ_GlobalNvrInterface_APPIA.u3.bits_3.nvrAddressLSW - - Default = 0x0000 - - NVR address LSW bits [F:0] - - - Notes: - The address of where to read and write from in the NVR. This is self-incrementing and will automatically increment after each read or write operation. */ - unsigned int nvrAddressLSW : 16; /* 1E.0103.F:0 R/W Default = 0x0000 */ - /* NVR address LSW bits [F:0] - */ - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of Global NVR Interface */ - union - { - struct - { - /*! \brief 1E.0104.F:0 R/W NVR Data MSW [1F:10] - AQ_GlobalNvrInterface_APPIA.u4.bits_4.nvrDataMSW - - Default = 0x0000 - - NVR data MSW bits [1F:10] - - - Notes: - Data is stored and read-out from these registers in little-endian format for operations such as FLASH device ID, and for programming the processor. - - For instance the 64K Atmel device code reads out as two bytes 0x651F into the LSW register, whereas the datasheet indicates that 1F is the first byte read, followed by 65 as the second byte. - - To burst read and write these 4 bytes in the correct order (where DD is written to address x), they should be stored as: - - AA BB in the MSW - CC DD in the LSW. */ - unsigned int nvrDataMSW : 16; /* 1E.0104.F:0 R/W Default = 0x0000 */ - /* NVR data MSW bits [1F:10] - */ - } bits_4; - uint16_t word_4; - } u4; - /*! \brief Union for bit and word level access of word 5 of Global NVR Interface */ - union - { - struct - { - /*! \brief 1E.0105.F:0 R/W NVR Data LSW [F:0] - AQ_GlobalNvrInterface_APPIA.u5.bits_5.nvrDataLSW - - Default = 0x0000 - - NVR data LSW bits [F:0] - - - Notes: - Data is stored and read-out from these registers in little-endian format for operations such as FLASH device ID, and for programming the processor. - - For instance the 64K Atmel device code reads out as two bytes 0x651F into the LSW register, whereas the datasheet indicates that 1F is the first byte read, followed by 65 as the second byte. - To burst read and write these 4 bytes in the correct order (where DD is written to address x), they should be stored as: - - AA BB in the MSW - CC DD in the LSW. */ - unsigned int nvrDataLSW : 16; /* 1E.0105.F:0 R/W Default = 0x0000 */ - /* NVR data LSW bits [F:0] - */ - } bits_5; - uint16_t word_5; - } u5; -} AQ_GlobalNvrInterface_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Mailbox Interface: 1E.0200 */ -/* Global Mailbox Interface: 1E.0200 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Mailbox Interface */ - union - { - struct - { - /*! \brief 1E.0200.F R/WSC uP Mailbox Execute Operation - AQ_GlobalMailboxInterface_APPIA.u0.bits_0.upMailboxExecuteOperation - - Default = 0x0 - - 1 = Start of mailbox Operation - - - Notes: - Indicates mailbox is loaded and ready */ - unsigned int upMailboxExecuteOperation : 1; /* 1E.0200.F R/WSC Default = 0x0 */ - /* 1 = Start of mailbox Operation - */ - /*! \brief 1E.0200.E R/W uP Mailbox Write Mode - AQ_GlobalMailboxInterface_APPIA.u0.bits_0.upMailboxWriteMode - - Default = 0x0 - - 1 = Write - 0 = Read - - - Notes: - Mailbox direction */ - unsigned int upMailboxWriteMode : 1; /* 1E.0200.E R/W Default = 0x0 */ - /* 1 = Write - 0 = Read - */ - unsigned int reserved0 : 1; - /*! \brief 1E.0200.C R/WSC Reset uP Mailbox CRC - AQ_GlobalMailboxInterface_APPIA.u0.bits_0.resetUpMailboxCrc - - Default = 0x0 - - 1 = Reset uP mailbox CRC calculation register - - */ - unsigned int resetUpMailboxCrc : 1; /* 1E.0200.C R/WSC Default = 0x0 */ - /* 1 = Reset uP mailbox CRC calculation register - */ - unsigned int reserved1 : 3; - /*! \brief 1E.0200.8 RO uP Mailbox Busy - AQ_GlobalMailboxInterface_APPIA.u0.bits_0.upMailboxBusy - - - - 1 = uP mailbox busy - 0 = uP mailbox ready - - - Notes: - In general the uP will respond within a few processor cycles to any PIF slave request, much faster than the MDIO. If the busy is asserted over multiple MDIO polling cycles, then a H/W error may have occured and a Global S/W reset or uP reset is required. */ - unsigned int upMailboxBusy : 1; /* 1E.0200.8 RO */ - /* 1 = uP mailbox busy - 0 = uP mailbox ready - */ - unsigned int reserved2 : 8; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Mailbox Interface */ - union - { - struct - { - /*! \brief 1E.0201.F:0 RO uP Mailbox CRC [F:0] - AQ_GlobalMailboxInterface_APPIA.u1.bits_1.upMailboxCrc - - - - The running CRC-16 of everything passing through the mailbox interface - - */ - unsigned int upMailboxCrc : 16; /* 1E.0201.F:0 RO */ - /* The running CRC-16 of everything passing through the mailbox interface - */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global Mailbox Interface */ - union - { - struct - { - /*! \brief 1E.0202.F:0 R/W uP Mailbox Address MSW [1F:10] - AQ_GlobalMailboxInterface_APPIA.u2.bits_2.upMailboxAddressMSW - - Default = 0x0000 - - uP Mailbox MSW address - - - Notes: - The address of where to read and write from in the Microcontroller Mailbox. This is self-incrementing and automatically increments after each read and write operation.PHY */ - unsigned int upMailboxAddressMSW : 16; /* 1E.0202.F:0 R/W Default = 0x0000 */ - /* uP Mailbox MSW address - */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global Mailbox Interface */ - union - { - struct - { - /*! \brief 1E.0203.F:2 R/W uP Mailbox Address LSW [F:2] - AQ_GlobalMailboxInterface_APPIA.u3.bits_3.upMailboxAddressLSW - - Default = 0x0000 - - uP LSW Mailbox address [F:2] - - - Notes: - The address of where to read and write from in the Microcontroller Mailbox. This is self-incrementing and automatically increments after each read and write operation.PHY */ - unsigned int upMailboxAddressLSW : 14; /* 1E.0203.F:2 R/W Default = 0x0000 */ - /* uP LSW Mailbox address [F:2] - */ - /*! \brief 1E.0203.1:0 RO uP Mailbox Address LSW Don't Care [1:0] - AQ_GlobalMailboxInterface_APPIA.u3.bits_3.upMailboxAddressLSW_Don_tCare - - - - Least significant uP LSW Mailbox address bits [1:0] - - - Notes: - These bits are always set to 0 since each memory access is on a 4-byte boundary. */ - unsigned int upMailboxAddressLSW_Don_tCare : 2; /* 1E.0203.1:0 RO */ - /* Least significant uP LSW Mailbox address bits [1:0] - */ - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of Global Mailbox Interface */ - union - { - struct - { - /*! \brief 1E.0204.F:0 R/W uP Mailbox Data MSW [1F:10] - AQ_GlobalMailboxInterface_APPIA.u4.bits_4.upMailboxDataMSW - - Default = 0x0000 - - uP Mailbox data MSW - - */ - unsigned int upMailboxDataMSW : 16; /* 1E.0204.F:0 R/W Default = 0x0000 */ - /* uP Mailbox data MSW - */ - } bits_4; - uint16_t word_4; - } u4; - /*! \brief Union for bit and word level access of word 5 of Global Mailbox Interface */ - union - { - struct - { - /*! \brief 1E.0205.F:0 R/W uP Mailbox Data LSW [F:0] - AQ_GlobalMailboxInterface_APPIA.u5.bits_5.upMailboxDataLSW - - Default = 0x0000 - - uP Mailbox data LSW - - */ - unsigned int upMailboxDataLSW : 16; /* 1E.0205.F:0 R/W Default = 0x0000 */ - /* uP Mailbox data LSW - */ - } bits_5; - uint16_t word_5; - } u5; -} AQ_GlobalMailboxInterface_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Microprocessor Scratch Pad: 1E.0300 */ -/* Global Microprocessor Scratch Pad: 1E.0300 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Microprocessor Scratch Pad */ - union - { - struct - { - /*! \brief 1E.0300.F:0 R/W Scratch Pad 1[F:0] - AQ_GlobalMicroprocessorScratchPad_APPIA.u0.bits_0.scratchPad_1 - - Default = 0x0000 - - General Purpose Scratch Pad1 - */ - unsigned int scratchPad_1 : 16; /* 1E.0300.F:0 R/W Default = 0x0000 */ - /* General Purpose Scratch Pad1 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Microprocessor Scratch Pad */ - union - { - struct - { - /*! \brief 1E.0301.F:0 R/W Scratch Pad 2 [F:0] - AQ_GlobalMicroprocessorScratchPad_APPIA.u1.bits_1.scratchPad_2 - - Default = 0x0000 - - General Purpose Scratch P - */ - unsigned int scratchPad_2 : 16; /* 1E.0301.F:0 R/W Default = 0x0000 */ - /* General Purpose Scratch P */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_GlobalMicroprocessorScratchPad_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Control: 1E.C000 */ -/* Global Control: 1E.C000 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Control */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Control */ - union - { - struct - { - /*! \brief 1E.C001.F R/W uP Reset - AQ_GlobalControl_APPIA.u1.bits_1.upReset - - Default = 0x0 - - 1 = Reset - - - Notes: - Resets the uP and the PIF master and slave bus. Will be active for a minimum of 100 microseconds. */ - unsigned int upReset : 1; /* 1E.C001.F R/W Default = 0x0 */ - /* 1 = Reset - */ - unsigned int reserved0 : 8; - /*! \brief 1E.C001.6 R/W uP Run Stall Override - AQ_GlobalControl_APPIA.u1.bits_1.upRunStallOverride - - Default = 0x0 - - 0 = uP Run Stall from "MDIO Boot Load" pin. - 1 = uP Run Stall from See MCP Run Stall bit - - - Notes: - This bit selects the uP Run Stall from either the "MDIO Boot Load" pin or the See MCP Run Stall bit. */ - unsigned int upRunStallOverride : 1; /* 1E.C001.6 R/W Default = 0x0 */ - /* 0 = uP Run Stall from "MDIO Boot Load" pin. - 1 = uP Run Stall from See MCP Run Stall bit - */ - unsigned int reserved1 : 5; - /*! \brief 1E.C001.0 R/W uP Run Stall - AQ_GlobalControl_APPIA.u1.bits_1.upRunStall - - Default = 0x0 - - 1 = uP Run Stall - 0 = uP normal mode - - - Notes: - Deactivates the uP. The PIF slave bus for inbound requests will still be active. This bit is muliplexed with the "MDIO Boot Load" pin with the See uP Run Stall Override bit as the select. When the "MDIO Boot Load" pin is asserted, the uP will be in Run Stall mode after reset. */ - unsigned int upRunStall : 1; /* 1E.C001.0 R/W Default = 0x0 */ - /* 1 = uP Run Stall - 0 = uP normal mode - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_GlobalControl_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Reset Control: 1E.C006 */ -/* Global Reset Control: 1E.C006 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Reset Control */ - union - { - struct - { - unsigned int reserved0 : 1; - /*! \brief 1E.C006.E R/WPD Global MMD Reset Disable - AQ_GlobalResetControl_APPIA.u0.bits_0.globalMMD_ResetDisable - - Provisionable Default = 0x0 - - 1 = Disable the S/W reset to the Global MMD registers - 0 = Enable the S/W reset to the Global MMD registers - - - Notes: - Setting this bit prevents a Global S/W reset or Global S/W reset from resetting the Global MMD registers */ - unsigned int globalMMD_ResetDisable : 1; /* 1E.C006.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Disable the S/W reset to the Global MMD registers - 0 = Enable the S/W reset to the Global MMD registers - */ - unsigned int reserved1 : 14; - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalResetControl_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Diagnostic Provisioning: 1E.C400 */ -/* Global Diagnostic Provisioning: 1E.C400 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Diagnostic Provisioning */ - union - { - struct - { - /*! \brief 1E.C400.F R/WPD Enable Diagnostics - AQ_GlobalDiagnosticProvisioning_APPIA.u0.bits_0.enableDiagnostics - - Provisionable Default = 0x1 - - 1 = Chip performs diagnostics on power-up - */ - unsigned int enableDiagnostics : 1; /* 1E.C400.F R/WPD Provisionable Default = 0x1 */ - /* 1 = Chip performs diagnostics on power-up */ - unsigned int reserved0 : 15; - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalDiagnosticProvisioning_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Thermal Provisioning: 1E.C420 */ -/* Global Thermal Provisioning: 1E.C420 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Thermal Provisioning */ - union - { - struct - { - /*! \brief 1E.C420.F:0 R/WPD Reserved 0 [F:0] - AQ_GlobalThermalProvisioning_APPIA.u0.bits_0.reserved_0 - - Provisionable Default = 0x0000 - - Internal reserved - do not modify - - */ - unsigned int reserved_0 : 16; /* 1E.C420.F:0 R/WPD Provisionable Default = 0x0000 */ - /* Internal reserved - do not modify - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Thermal Provisioning */ - union - { - struct - { - /*! \brief 1E.C421.F:0 R/WPD High Temp Failure Threshold [F:0] - AQ_GlobalThermalProvisioning_APPIA.u1.bits_1.highTempFailureThreshold - - Provisionable Default = 0x4600 - - [F:0] of high temperature failure threshold - - Notes: - 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 70 degreesC. - - In XENPAK mode, F/W will use the XENPAK register 1.A000 - 1.A001: instead of this register. - - NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. - High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ - unsigned int highTempFailureThreshold : 16; /* 1E.C421.F:0 R/WPD Provisionable Default = 0x4600 */ - /* [F:0] of high temperature failure threshold */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global Thermal Provisioning */ - union - { - struct - { - /*! \brief 1E.C422.F:0 R/WPD Low Temp Failure Threshold [F:0] - AQ_GlobalThermalProvisioning_APPIA.u2.bits_2.lowTempFailureThreshold - - Provisionable Default = 0x0000 - - [F:0] of low temperature failure threshold - - Notes: - 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 0 degreesC. - - In XENPAK mode, F/W will use the XENPAK register 1.A002 - 1.A003: instead of this register. - - NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. - High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ - unsigned int lowTempFailureThreshold : 16; /* 1E.C422.F:0 R/WPD Provisionable Default = 0x0000 */ - /* [F:0] of low temperature failure threshold */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global Thermal Provisioning */ - union - { - struct - { - /*! \brief 1E.C423.F:0 R/WPD High Temp Warning Threshold [F:0] - AQ_GlobalThermalProvisioning_APPIA.u3.bits_3.highTempWarningThreshold - - Provisionable Default = 0x3C00 - - [F:0] of high temperature warning threshold - - Notes: - 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD008. Default is 60 degreesC. - - In XENPAK mode, F/W will use the XENPAK register 1.A004 - 1.A005: instead of this register. - - NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. - High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ - unsigned int highTempWarningThreshold : 16; /* 1E.C423.F:0 R/WPD Provisionable Default = 0x3C00 */ - /* [F:0] of high temperature warning threshold */ - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of Global Thermal Provisioning */ - union - { - struct - { - /*! \brief 1E.C424.F:0 R/WPD Low Temp Warning Threshold [F:0] - AQ_GlobalThermalProvisioning_APPIA.u4.bits_4.lowTempWarningThreshold - - Provisionable Default = 0x0A00 - - [F:0] of low temperature warning threshold - - Notes: - 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 10 degreesC. - - In XENPAK mode, F/W will use the XENPAK register 1.A006 - 1.A007: instead of this register. - - NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. - High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ - unsigned int lowTempWarningThreshold : 16; /* 1E.C424.F:0 R/WPD Provisionable Default = 0x0A00 */ - /* [F:0] of low temperature warning threshold */ - } bits_4; - uint16_t word_4; - } u4; -} AQ_GlobalThermalProvisioning_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global LED Provisioning: 1E.C430 */ -/* Global LED Provisioning: 1E.C430 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global LED Provisioning */ - union - { - struct - { - unsigned int reserved0 : 7; - /*! \brief 1E.C430.8 R/WPD LED #0 Manual Set - AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0ManualSet - - Provisionable Default = 0x0 - - 1 = LED On - - */ - unsigned int led_0ManualSet : 1; /* 1E.C430.8 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED On - */ - /*! \brief 1E.C430.7 R/WPD LED #0 10 Gb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0_10Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 10 Gb/s - - */ - unsigned int led_0_10Gb_sLinkEstablished : 1; /* 1E.C430.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 10 Gb/s - */ - /*! \brief 1E.C430.6 R/WPD LED #0 1 Gb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0_1Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 1 Gb/s - - */ - unsigned int led_0_1Gb_sLinkEstablished : 1; /* 1E.C430.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 1 Gb/s - */ - /*! \brief 1E.C430.5 R/WPD LED #0 100 Mb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0_100Mb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 100 Mb/s - - */ - unsigned int led_0_100Mb_sLinkEstablished : 1; /* 1E.C430.5 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 100 Mb/s - */ - /*! \brief 1E.C430.4 R/WPD LED #0 Connecting - AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0Connecting - - Provisionable Default = 0x0 - - 1 = LED is on when attempting to connect. - - */ - unsigned int led_0Connecting : 1; /* 1E.C430.4 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when attempting to connect. - */ - /*! \brief 1E.C430.3 R/WPD LED #0 Receive Activity - AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0ReceiveActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on receive activity - - */ - unsigned int led_0ReceiveActivity : 1; /* 1E.C430.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on receive activity - */ - /*! \brief 1E.C430.2 R/WPD LED #0 Transmit Activity - AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0TransmitActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on transmit activity - - */ - unsigned int led_0TransmitActivity : 1; /* 1E.C430.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on transmit activity - */ - /*! \brief 1E.C430.1:0 R/WPD LED #0 Activity Stretch [1:0] - AQ_GlobalLedProvisioning_APPIA.u0.bits_0.led_0ActivityStretch - - Provisionable Default = 0x3 - - [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - - */ - unsigned int led_0ActivityStretch : 2; /* 1E.C430.1:0 R/WPD Provisionable Default = 0x3 */ - /* [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global LED Provisioning */ - union - { - struct - { - unsigned int reserved0 : 7; - /*! \brief 1E.C431.8 R/WPD LED #1 Manual Set - AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1ManualSet - - Provisionable Default = 0x0 - - 1 = LED On - - */ - unsigned int led_1ManualSet : 1; /* 1E.C431.8 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED On - */ - /*! \brief 1E.C431.7 R/WPD LED #1 10 Gb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1_10Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 10 Gb/s - - */ - unsigned int led_1_10Gb_sLinkEstablished : 1; /* 1E.C431.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 10 Gb/s - */ - /*! \brief 1E.C431.6 R/WPD LED #1 1 Gb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1_1Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 1 Gb/s - - */ - unsigned int led_1_1Gb_sLinkEstablished : 1; /* 1E.C431.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 1 Gb/s - */ - /*! \brief 1E.C431.5 R/WPD LED #1 100 Mb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1_100Mb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 100 Mb/s - - */ - unsigned int led_1_100Mb_sLinkEstablished : 1; /* 1E.C431.5 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 100 Mb/s - */ - /*! \brief 1E.C431.4 R/WPD LED #1 Connecting - AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1Connecting - - Provisionable Default = 0x0 - - 1 = LED is on when attempting to connect. - - */ - unsigned int led_1Connecting : 1; /* 1E.C431.4 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when attempting to connect. - */ - /*! \brief 1E.C431.3 R/WPD LED #1 Receive Activity - AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1ReceiveActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on receive activity - - */ - unsigned int led_1ReceiveActivity : 1; /* 1E.C431.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on receive activity - */ - /*! \brief 1E.C431.2 R/WPD LED #1 Transmit Activity - AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1TransmitActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on transmit activity - - */ - unsigned int led_1TransmitActivity : 1; /* 1E.C431.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on transmit activity - */ - /*! \brief 1E.C431.1:0 R/WPD LED #1 Activity Stretch [1:0] - AQ_GlobalLedProvisioning_APPIA.u1.bits_1.led_1ActivityStretch - - Provisionable Default = 0x3 - - [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - - */ - unsigned int led_1ActivityStretch : 2; /* 1E.C431.1:0 R/WPD Provisionable Default = 0x3 */ - /* [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global LED Provisioning */ - union - { - struct - { - unsigned int reserved0 : 7; - /*! \brief 1E.C432.8 R/WPD LED #2 Manual Set - AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2ManualSet - - Provisionable Default = 0x0 - - 1 = LED On - - */ - unsigned int led_2ManualSet : 1; /* 1E.C432.8 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED On - */ - /*! \brief 1E.C432.7 R/WPD LED #2 10 Gb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2_10Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 10 Gb/s - - */ - unsigned int led_2_10Gb_sLinkEstablished : 1; /* 1E.C432.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 10 Gb/s - */ - /*! \brief 1E.C432.6 R/WPD LED #2 1 Gb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2_1Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 1 Gb/s - - */ - unsigned int led_2_1Gb_sLinkEstablished : 1; /* 1E.C432.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 1 Gb/s - */ - /*! \brief 1E.C432.5 R/WPD LED #2 100 Mb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2_100Mb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 100 Mb/s - - */ - unsigned int led_2_100Mb_sLinkEstablished : 1; /* 1E.C432.5 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 100 Mb/s - */ - /*! \brief 1E.C432.4 R/WPD LED #2 Connecting - AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2Connecting - - Provisionable Default = 0x0 - - 1 = LED is on when attempting to connect. - - */ - unsigned int led_2Connecting : 1; /* 1E.C432.4 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when attempting to connect. - */ - /*! \brief 1E.C432.3 R/WPD LED #2 Receive Activity - AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2ReceiveActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on receive activity - - */ - unsigned int led_2ReceiveActivity : 1; /* 1E.C432.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on receive activity - */ - /*! \brief 1E.C432.2 R/WPD LED #2 Transmit Activity - AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2TransmitActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on transmit activity - - */ - unsigned int led_2TransmitActivity : 1; /* 1E.C432.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on transmit activity - */ - /*! \brief 1E.C432.1:0 R/WPD LED #2 Activity Stretch [1:0] - AQ_GlobalLedProvisioning_APPIA.u2.bits_2.led_2ActivityStretch - - Provisionable Default = 0x3 - - [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - - */ - unsigned int led_2ActivityStretch : 2; /* 1E.C432.1:0 R/WPD Provisionable Default = 0x3 */ - /* [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global LED Provisioning */ - union - { - struct - { - unsigned int reserved0 : 7; - /*! \brief 1E.C433.8 R/WPD LED #3 Manual Set - AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3ManualSet - - Provisionable Default = 0x0 - - 1 = LED On - - */ - unsigned int led_3ManualSet : 1; /* 1E.C433.8 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED On - */ - /*! \brief 1E.C433.7 R/WPD LED #3 10 Gb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3_10Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 10 Gb/s - - */ - unsigned int led_3_10Gb_sLinkEstablished : 1; /* 1E.C433.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 10 Gb/s - */ - /*! \brief 1E.C433.6 R/WPD LED #3 1 Gb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3_1Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 1 Gb/s - - */ - unsigned int led_3_1Gb_sLinkEstablished : 1; /* 1E.C433.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 1 Gb/s - */ - /*! \brief 1E.C433.5 R/WPD LED #3 100 Mb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3_100Mb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 100 Mb/s - - */ - unsigned int led_3_100Mb_sLinkEstablished : 1; /* 1E.C433.5 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 100 Mb/s - */ - /*! \brief 1E.C433.4 R/WPD LED #3 Connecting - AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3Connecting - - Provisionable Default = 0x0 - - 1 = LED is on when attempting to connect. - - */ - unsigned int led_3Connecting : 1; /* 1E.C433.4 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when attempting to connect. - */ - /*! \brief 1E.C433.3 R/WPD LED #3 Receive Activity - AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3ReceiveActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on receive activity - - */ - unsigned int led_3ReceiveActivity : 1; /* 1E.C433.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on receive activity - */ - /*! \brief 1E.C433.2 R/WPD LED #3 Transmit Activity - AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3TransmitActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on transmit activity - - */ - unsigned int led_3TransmitActivity : 1; /* 1E.C433.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on transmit activity - */ - /*! \brief 1E.C433.1:0 R/WPD LED #3 Activity Stretch [1:0] - AQ_GlobalLedProvisioning_APPIA.u3.bits_3.led_3ActivityStretch - - Provisionable Default = 0x3 - - [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - - */ - unsigned int led_3ActivityStretch : 2; /* 1E.C433.1:0 R/WPD Provisionable Default = 0x3 */ - /* [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - */ - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of Global LED Provisioning */ - union - { - struct - { - unsigned int reserved0 : 7; - /*! \brief 1E.C434.8 R/WPD LED #4 Manual Set - AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4ManualSet - - Provisionable Default = 0x0 - - 1 = LED On - - */ - unsigned int led_4ManualSet : 1; /* 1E.C434.8 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED On - */ - /*! \brief 1E.C434.7 R/WPD LED #4 10 Gb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4_10Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 10 Gb/s - - */ - unsigned int led_4_10Gb_sLinkEstablished : 1; /* 1E.C434.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 10 Gb/s - */ - /*! \brief 1E.C434.6 R/WPD LED #4 1 Gb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4_1Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 1 Gb/s - - */ - unsigned int led_4_1Gb_sLinkEstablished : 1; /* 1E.C434.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 1 Gb/s - */ - /*! \brief 1E.C434.5 R/WPD LED #4 100 Mb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4_100Mb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 100 Mb/s - - */ - unsigned int led_4_100Mb_sLinkEstablished : 1; /* 1E.C434.5 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 100 Mb/s - */ - /*! \brief 1E.C434.4 R/WPD LED #4 Connecting - AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4Connecting - - Provisionable Default = 0x0 - - 1 = LED is on when attempting to connect. - - */ - unsigned int led_4Connecting : 1; /* 1E.C434.4 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when attempting to connect. - */ - /*! \brief 1E.C434.3 R/WPD LED #4 Receive Activity - AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4ReceiveActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on receive activity - - */ - unsigned int led_4ReceiveActivity : 1; /* 1E.C434.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on receive activity - */ - /*! \brief 1E.C434.2 R/WPD LED #4 Transmit Activity - AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4TransmitActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on transmit activity - - */ - unsigned int led_4TransmitActivity : 1; /* 1E.C434.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on transmit activity - */ - /*! \brief 1E.C434.1:0 R/WPD LED #4 Activity Stretch [1:0] - AQ_GlobalLedProvisioning_APPIA.u4.bits_4.led_4ActivityStretch - - Provisionable Default = 0x3 - - [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - - */ - unsigned int led_4ActivityStretch : 2; /* 1E.C434.1:0 R/WPD Provisionable Default = 0x3 */ - /* [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - */ - } bits_4; - uint16_t word_4; - } u4; - /*! \brief Union for bit and word level access of word 5 of Global LED Provisioning */ - union - { - struct - { - unsigned int reserved0 : 7; - /*! \brief 1E.C435.8 R/WPD LED #5 Manual Set - AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5ManualSet - - Provisionable Default = 0x0 - - 1 = LED On - - */ - unsigned int led_5ManualSet : 1; /* 1E.C435.8 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED On - */ - /*! \brief 1E.C435.7 R/WPD LED #5 10 Gb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5_10Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 10 Gb/s - - */ - unsigned int led_5_10Gb_sLinkEstablished : 1; /* 1E.C435.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 10 Gb/s - */ - /*! \brief 1E.C435.6 R/WPD LED #5 1 Gb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5_1Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 1 Gb/s - - */ - unsigned int led_5_1Gb_sLinkEstablished : 1; /* 1E.C435.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 1 Gb/s - */ - /*! \brief 1E.C435.5 R/WPD LED #5 100 Mb/s Link Established - AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5_100Mb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 100 Mb/s - - */ - unsigned int led_5_100Mb_sLinkEstablished : 1; /* 1E.C435.5 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 100 Mb/s - */ - /*! \brief 1E.C435.4 R/WPD LED #5 Connecting - AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5Connecting - - Provisionable Default = 0x0 - - 1 = LED is on when attempting to connect. - - */ - unsigned int led_5Connecting : 1; /* 1E.C435.4 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when attempting to connect. - */ - /*! \brief 1E.C435.3 R/WPD LED #5 Receive Activity - AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5ReceiveActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on receive activity - - */ - unsigned int led_5ReceiveActivity : 1; /* 1E.C435.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on receive activity - */ - /*! \brief 1E.C435.2 R/WPD LED #5 Transmit Activity - AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5TransmitActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on transmit activity - - */ - unsigned int led_5TransmitActivity : 1; /* 1E.C435.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on transmit activity - */ - /*! \brief 1E.C435.1:0 R/WPD LED #5 Activity Stretch [1:0] - AQ_GlobalLedProvisioning_APPIA.u5.bits_5.led_5ActivityStretch - - Provisionable Default = 0x3 - - [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - - */ - unsigned int led_5ActivityStretch : 2; /* 1E.C435.1:0 R/WPD Provisionable Default = 0x3 */ - /* [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - */ - } bits_5; - uint16_t word_5; - } u5; - /*! \brief Union for bit and word level access of word 6 of Global LED Provisioning */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_6; - uint16_t word_6; - } u6; - /*! \brief Union for bit and word level access of word 7 of Global LED Provisioning */ - union - { - struct - { - unsigned int reserved0 : 15; - /*! \brief 1E.C437.0 R/WPD LED Operation Mode - AQ_GlobalLedProvisioning_APPIA.u7.bits_7.ledOperationMode - - Provisionable Default = 0x0 - - 1 = LED link activity in Mode #2 - 0 = LED link activity in classic mode - - - Notes: - When set to 1, the LED blinking rate is based on Mode #2 algorithm. When set to 0, the LED blinking rate is based on the classic algorithm. */ - unsigned int ledOperationMode : 1; /* 1E.C437.0 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED link activity in Mode #2 - 0 = LED link activity in classic mode - */ - } bits_7; - uint16_t word_7; - } u7; - /*! \brief Union for bit and word level access of word 8 of Global LED Provisioning */ - union - { - struct - { - unsigned int reserved0 : 13; - /*! \brief 1E.C438.2 R/WPD LED #0 Drive Three State Select - AQ_GlobalLedProvisioning_APPIA.u8.bits_8.led_0DriveThreeStateSelect - - Provisionable Default = 0x0 - - 1 = Drive LED tri-state when not active - 0 = Drive LED opposite of active level when not active - - */ - unsigned int led_0DriveThreeStateSelect : 1; /* 1E.C438.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = Drive LED tri-state when not active - 0 = Drive LED opposite of active level when not active - */ - /*! \brief 1E.C438.1 R/WPD LED #0 Active High Select - AQ_GlobalLedProvisioning_APPIA.u8.bits_8.led_0ActiveHighSelect - - Provisionable Default = 0x0 - - 1 = LED active high - 0 = LED active low - - - Notes: - The See LED #0 Manual Active Select bit must be 1 for this bit to take affect. */ - unsigned int led_0ActiveHighSelect : 1; /* 1E.C438.1 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED active high - 0 = LED active low - */ - /*! \brief 1E.C438.0 R/WPD LED #0 Manual Active Select - AQ_GlobalLedProvisioning_APPIA.u8.bits_8.led_0ManualActiveSelect - - Provisionable Default = 0x0 - - 1 = Manual selection of LED active high or low - 0 = Determine the active high or low based on the external pull-up or pull-down - - */ - unsigned int led_0ManualActiveSelect : 1; /* 1E.C438.0 R/WPD Provisionable Default = 0x0 */ - /* 1 = Manual selection of LED active high or low - 0 = Determine the active high or low based on the external pull-up or pull-down - */ - } bits_8; - uint16_t word_8; - } u8; - /*! \brief Union for bit and word level access of word 9 of Global LED Provisioning */ - union - { - struct - { - unsigned int reserved0 : 13; - /*! \brief 1E.C439.2 R/WPD LED #1 Drive Three State Select - AQ_GlobalLedProvisioning_APPIA.u9.bits_9.led_1DriveThreeStateSelect - - Provisionable Default = 0x0 - - 1 = Drive LED tri-state when not active - 0 = Drive LED opposite of active level when not active - - */ - unsigned int led_1DriveThreeStateSelect : 1; /* 1E.C439.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = Drive LED tri-state when not active - 0 = Drive LED opposite of active level when not active - */ - /*! \brief 1E.C439.1 R/WPD LED #1 Active High Select - AQ_GlobalLedProvisioning_APPIA.u9.bits_9.led_1ActiveHighSelect - - Provisionable Default = 0x0 - - 1 = LED active high - 0 = LED active low - - - Notes: - The See LED #1 Manual Active Select bit must be 1 for this bit to take affect. */ - unsigned int led_1ActiveHighSelect : 1; /* 1E.C439.1 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED active high - 0 = LED active low - */ - /*! \brief 1E.C439.0 R/WPD LED #1 Manual Active Select - AQ_GlobalLedProvisioning_APPIA.u9.bits_9.led_1ManualActiveSelect - - Provisionable Default = 0x0 - - 1 = Manual selection of LED active high or low - 0 = Determine the active high or low based on the external pull-up or pull-down - - */ - unsigned int led_1ManualActiveSelect : 1; /* 1E.C439.0 R/WPD Provisionable Default = 0x0 */ - /* 1 = Manual selection of LED active high or low - 0 = Determine the active high or low based on the external pull-up or pull-down - */ - } bits_9; - uint16_t word_9; - } u9; - /*! \brief Union for bit and word level access of word 10 of Global LED Provisioning */ - union - { - struct - { - unsigned int reserved0 : 13; - /*! \brief 1E.C43A.2 R/WPD LED #2 Drive Three State Select - AQ_GlobalLedProvisioning_APPIA.u10.bits_10.led_2DriveThreeStateSelect - - Provisionable Default = 0x0 - - 1 = Drive LED tri-state when not active - 0 = Drive LED opposite of active level when not active - - */ - unsigned int led_2DriveThreeStateSelect : 1; /* 1E.C43A.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = Drive LED tri-state when not active - 0 = Drive LED opposite of active level when not active - */ - /*! \brief 1E.C43A.1 R/WPD LED #2 Active High Select - AQ_GlobalLedProvisioning_APPIA.u10.bits_10.led_2ActiveHighSelect - - Provisionable Default = 0x0 - - 1 = LED active high - 0 = LED active low - - - Notes: - The See LED #2 Manual Active Select bit must be 1 for this bit to take affect. */ - unsigned int led_2ActiveHighSelect : 1; /* 1E.C43A.1 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED active high - 0 = LED active low - */ - /*! \brief 1E.C43A.0 R/WPD LED #2 Manual Active Select - AQ_GlobalLedProvisioning_APPIA.u10.bits_10.led_2ManualActiveSelect - - Provisionable Default = 0x0 - - 1 = Manual selection of LED active high or low - 0 = Determine the active high or low based on the external pull-up or pull-down - - */ - unsigned int led_2ManualActiveSelect : 1; /* 1E.C43A.0 R/WPD Provisionable Default = 0x0 */ - /* 1 = Manual selection of LED active high or low - 0 = Determine the active high or low based on the external pull-up or pull-down - */ - } bits_10; - uint16_t word_10; - } u10; - /*! \brief Union for bit and word level access of word 11 of Global LED Provisioning */ - union - { - struct - { - unsigned int reserved0 : 13; - /*! \brief 1E.C43B.2 R/WPD LED #3 Drive Three State Select - AQ_GlobalLedProvisioning_APPIA.u11.bits_11.led_3DriveThreeStateSelect - - Provisionable Default = 0x0 - - 1 = Drive LED tri-state when not active - 0 = Drive LED opposite of active level when not active - - */ - unsigned int led_3DriveThreeStateSelect : 1; /* 1E.C43B.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = Drive LED tri-state when not active - 0 = Drive LED opposite of active level when not active - */ - /*! \brief 1E.C43B.1 R/WPD LED #3 Active High Select - AQ_GlobalLedProvisioning_APPIA.u11.bits_11.led_3ActiveHighSelect - - Provisionable Default = 0x0 - - 1 = LED active high - 0 = LED active low - - - Notes: - The See LED #3 Manual Active Select bit must be 1 for this bit to take affect. */ - unsigned int led_3ActiveHighSelect : 1; /* 1E.C43B.1 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED active high - 0 = LED active low - */ - /*! \brief 1E.C43B.0 R/WPD LED #3 Manual Active Select - AQ_GlobalLedProvisioning_APPIA.u11.bits_11.led_3ManualActiveSelect - - Provisionable Default = 0x0 - - 1 = Manual selection of LED active high or low - 0 = Determine the active high or low based on the external pull-up or pull-down - - */ - unsigned int led_3ManualActiveSelect : 1; /* 1E.C43B.0 R/WPD Provisionable Default = 0x0 */ - /* 1 = Manual selection of LED active high or low - 0 = Determine the active high or low based on the external pull-up or pull-down - */ - } bits_11; - uint16_t word_11; - } u11; - /*! \brief Union for bit and word level access of word 12 of Global LED Provisioning */ - union - { - struct - { - unsigned int reserved0 : 13; - /*! \brief 1E.C43C.2 R/WPD LED #4 Drive Three State Select - AQ_GlobalLedProvisioning_APPIA.u12.bits_12.led_4DriveThreeStateSelect - - Provisionable Default = 0x0 - - 1 = Drive LED tri-state when not active - 0 = Drive LED opposite of active level when not active - - */ - unsigned int led_4DriveThreeStateSelect : 1; /* 1E.C43C.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = Drive LED tri-state when not active - 0 = Drive LED opposite of active level when not active - */ - /*! \brief 1E.C43C.1 R/WPD LED #4 Active High Select - AQ_GlobalLedProvisioning_APPIA.u12.bits_12.led_4ActiveHighSelect - - Provisionable Default = 0x0 - - 1 = LED active high - 0 = LED active low - - - Notes: - The See LED #4 Manual Active Select bit must be 1 for this bit to take affect. */ - unsigned int led_4ActiveHighSelect : 1; /* 1E.C43C.1 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED active high - 0 = LED active low - */ - /*! \brief 1E.C43C.0 R/WPD LED #4 Manual Active Select - AQ_GlobalLedProvisioning_APPIA.u12.bits_12.led_4ManualActiveSelect - - Provisionable Default = 0x0 - - 1 = Manual selection of LED active high or low - 0 = Determine the active high or low based on the external pull-up or pull-down - - */ - unsigned int led_4ManualActiveSelect : 1; /* 1E.C43C.0 R/WPD Provisionable Default = 0x0 */ - /* 1 = Manual selection of LED active high or low - 0 = Determine the active high or low based on the external pull-up or pull-down - */ - } bits_12; - uint16_t word_12; - } u12; - /*! \brief Union for bit and word level access of word 13 of Global LED Provisioning */ - union - { - struct - { - unsigned int reserved0 : 13; - /*! \brief 1E.C43D.2 R/WPD LED #5 Drive Three State Select - AQ_GlobalLedProvisioning_APPIA.u13.bits_13.led_5DriveThreeStateSelect - - Provisionable Default = 0x0 - - 1 = Drive LED tri-state when not active - 0 = Drive LED opposite of active level when not active - - */ - unsigned int led_5DriveThreeStateSelect : 1; /* 1E.C43D.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = Drive LED tri-state when not active - 0 = Drive LED opposite of active level when not active - */ - /*! \brief 1E.C43D.1 R/WPD LED #5 Active High Select - AQ_GlobalLedProvisioning_APPIA.u13.bits_13.led_5ActiveHighSelect - - Provisionable Default = 0x0 - - 1 = LED active high - 0 = LED active low - - - Notes: - The See LED #5 Manual Active Select bit must be 1 for this bit to take affect. */ - unsigned int led_5ActiveHighSelect : 1; /* 1E.C43D.1 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED active high - 0 = LED active low - */ - /*! \brief 1E.C43D.0 R/WPD LED #5 Manual Active Select - AQ_GlobalLedProvisioning_APPIA.u13.bits_13.led_5ManualActiveSelect - - Provisionable Default = 0x0 - - 1 = Manual selection of LED active high or low - 0 = Determine the active high or low based on the external pull-up or pull-down - - */ - unsigned int led_5ManualActiveSelect : 1; /* 1E.C43D.0 R/WPD Provisionable Default = 0x0 */ - /* 1 = Manual selection of LED active high or low - 0 = Determine the active high or low based on the external pull-up or pull-down - */ - } bits_13; - uint16_t word_13; - } u13; -} AQ_GlobalLedProvisioning_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global General Provisioning: 1E.C440 */ -/* Global General Provisioning: 1E.C440 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global General Provisioning */ - union - { - struct - { - unsigned int reserved0 : 7; - /*! \brief 1E.C440.8:4 R/WPD Gang Load MDIO Address [4:0] - AQ_GlobalGeneralProvisioning_APPIA.u0.bits_0.gangLoadMdioAddress - - Provisionable Default = 0x00 - - MDIO Address to be used during gang load operation - - - Notes: - Gang load operation is used to load data into multiple PHYs all connected to the same MDIO bus. The address for gang load operation is provided by these bits (8:4), and enabling is done by writing Bit 0. Disabling of gang load mode is done by writing the See MDIO Address Reset (1E.C441.2) bit. These will revert the PHY's MDIO address back to the address provided by the MDIO Address pins. During gang load operation, MDIO reads are disabled to prevent bus contention. */ - unsigned int gangLoadMdioAddress : 5; /* 1E.C440.8:4 R/WPD Provisionable Default = 0x00 */ - /* MDIO Address to be used during gang load operation - */ - unsigned int reserved1 : 3; - /*! \brief 1E.C440.0 RO Gang Load MDIO Write Only - AQ_GlobalGeneralProvisioning_APPIA.u0.bits_0.gangLoadMdioWriteOnly - - - - 1 = MDIO gang load enable - - - Notes: - This bit enables gang load operation with the address specified in Bits 8:4. */ - unsigned int gangLoadMdioWriteOnly : 1; /* 1E.C440.0 RO */ - /* 1 = MDIO gang load enable - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global General Provisioning */ - union - { - struct - { - unsigned int reserved0 : 1; - /*! \brief 1E.C441.E R/WPD MDIO Broadcast Mode Enable - AQ_GlobalGeneralProvisioning_APPIA.u1.bits_1.mdioBroadcastModeEnable - - Provisionable Default = 0x0 - - 1 = Enable broadcast on Address 0 - 0 = Disable broadcast on Address 0 - - - Notes: - When set, this bit enables gang-load operation on address zero, simultaneous with normal MDIO operation. Obviously, this requires that no PHY use address 0 as its normal operating address. As well, reads on MDIO Address 0 are disabled to prevent bus contention. */ - unsigned int mdioBroadcastModeEnable : 1; /* 1E.C441.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable broadcast on Address 0 - 0 = Disable broadcast on Address 0 - */ - /*! \brief 1E.C441.D R/WPD MDIO Read MSW First Enable - AQ_GlobalGeneralProvisioning_APPIA.u1.bits_1.mdioReadMSW_FirstEnable - - Provisionable Default = 0x0 - - 1 = MSW of counter must be read first - 0 = LSW of counter must be read first - - - Notes: - This bit configures whether the MSW or LSW must be read first for counters greater than 16 bits. */ - unsigned int mdioReadMSW_FirstEnable : 1; /* 1E.C441.D R/WPD Provisionable Default = 0x0 */ - /* 1 = MSW of counter must be read first - 0 = LSW of counter must be read first - */ - unsigned int reserved1 : 8; - /*! \brief 1E.C441.4 R/WPD MDIO Drive Configuration - AQ_GlobalGeneralProvisioning_APPIA.u1.bits_1.mdioDriveConfiguration - - Provisionable Default = 0x0 - - 0 = MDIO driver is in normal mode - 1 = MDIO driver is in open drain mode - - - Notes: - When the MDIO driver is in open drain mode during a read cycle, "0" data will be actively driven out of the MDIO, "1" data will set the MDIO driver in high impedance state and an external pullup will set the MDIO line to "1". The Turn-Around "0" will also be actively driven out of the MDIO, therefore in open drain mode, the Turn-Around is still "Z0". */ - unsigned int mdioDriveConfiguration : 1; /* 1E.C441.4 R/WPD Provisionable Default = 0x0 */ - /* 0 = MDIO driver is in normal mode - 1 = MDIO driver is in open drain mode - */ - /*! \brief 1E.C441.3 R/WPD MDIO Preamble Detection Disable - AQ_GlobalGeneralProvisioning_APPIA.u1.bits_1.mdioPreambleDetectionDisable - - Provisionable Default = 0x0 - - 1 = Suppress preamble detection on MDIO - 0 = Enable preamble detection on MDIO - - */ - unsigned int mdioPreambleDetectionDisable : 1; /* 1E.C441.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = Suppress preamble detection on MDIO - 0 = Enable preamble detection on MDIO - */ - /*! \brief 1E.C441.2 R/WSC MDIO Address Reset - AQ_GlobalGeneralProvisioning_APPIA.u1.bits_1.mdioAddressReset - - Default = 0x0 - - 1 = Load MDIO Address with the address on the MDIO address pins - - - Notes: - Used to reset the address after gang load and enable MDIO reads again. */ - unsigned int mdioAddressReset : 1; /* 1E.C441.2 R/WSC Default = 0x0 */ - /* 1 = Load MDIO Address with the address on the MDIO address pins - */ - unsigned int reserved2 : 2; - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global General Provisioning */ - union - { - struct - { - unsigned int reserved0 : 15; - /*! \brief 1E.C442.0 R/W Daisy Chain Reset - AQ_GlobalGeneralProvisioning_APPIA.u2.bits_2.daisyChainReset - - Default = 0x0 - - 1 = Reset the daisy chain - - - Notes: - Toggling this bit from 0 to 1 will reload the IRAM and DRAM and reset the uP. The uP will be in uP run stall during the reload process. After the reload process, uP run stall will be de-asserted adn the uP reset will be asserted. Note that before setting this bit, the See Soft Reset bit needs to be de-asserted. */ - unsigned int daisyChainReset : 1; /* 1E.C442.0 R/W Default = 0x0 */ - /* 1 = Reset the daisy chain - */ - } bits_2; - uint16_t word_2; - } u2; -} AQ_GlobalGeneralProvisioning_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global NVR Provisioning: 1E.C450 */ -/* Global NVR Provisioning: 1E.C450 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global NVR Provisioning */ - union - { - struct - { - unsigned int reserved0 : 5; - /*! \brief 1E.C450.A:8 R/WPD NVR Data Length [2:0] - AQ_GlobalNvrProvisioning_APPIA.u0.bits_0.nvrDataLength - - Provisionable Default = 0x4 - - NVR data length ranges from 0 bytes to 4 bytes - - - Notes: - This sets the length of the data burst used in read and write operations. - */ - unsigned int nvrDataLength : 3; /* 1E.C450.A:8 R/WPD Provisionable Default = 0x4 */ - /* NVR data length ranges from 0 bytes to 4 bytes - */ - unsigned int reserved1 : 1; - /*! \brief 1E.C450.6:4 R/WPD NVR Dummy Length [2:0] - AQ_GlobalNvrProvisioning_APPIA.u0.bits_0.nvrDummyLength - - Provisionable Default = 0x0 - - NVR dummy length ranges from 0 bytes to 4 bytes. - - - Notes: - This sets the length of the dummy field used in some maunfacturer's read status and write status operations. - */ - unsigned int nvrDummyLength : 3; /* 1E.C450.6:4 R/WPD Provisionable Default = 0x0 */ - /* NVR dummy length ranges from 0 bytes to 4 bytes. - */ - unsigned int reserved2 : 2; - /*! \brief 1E.C450.1:0 R/WPD NVR Address Length [1:0] - AQ_GlobalNvrProvisioning_APPIA.u0.bits_0.nvrAddressLength - - Provisionable Default = 0x2 - - NVR address length ranges from 0 bytes up to 3 bytes. - - - Notes: - This sets the length of the address field used in read and write operations. Use of this field is enabled via Bit 8 of See Global NVR Provisioning 2: Address 1E.C451 . - */ - unsigned int nvrAddressLength : 2; /* 1E.C450.1:0 R/WPD Provisionable Default = 0x2 */ - /* NVR address length ranges from 0 bytes up to 3 bytes. - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global NVR Provisioning */ - union - { - struct - { - unsigned int reserved0 : 7; - /*! \brief 1E.C451.8 R/WPD NVR Address Length Override - AQ_GlobalNvrProvisioning_APPIA.u1.bits_1.nvrAddressLengthOverride - - Provisionable Default = 0x0 - - 0 = NVR address length is based on the "NVR_SIZE" pin. - 1 = NVR address length is based on the See NVR Address Length [1:0] register. - - - Notes: - When the this bit = 0 and NVR_SIZE pin = 0, the NVR address length is 2 bytes. When this bit = 0 and the NVR_SIZE pin = 1, the NVR address length is 3 bytes. When this bit = 1 the NVR address length is from the See NVR Address Length [1:0] */ - unsigned int nvrAddressLengthOverride : 1; /* 1E.C451.8 R/WPD Provisionable Default = 0x0 */ - /* 0 = NVR address length is based on the "NVR_SIZE" pin. - 1 = NVR address length is based on the See NVR Address Length [1:0] register. - */ - /*! \brief 1E.C451.7:0 R/WPD NVR Clock Divide [7:0] - AQ_GlobalNvrProvisioning_APPIA.u1.bits_1.nvrClockDivide - - Provisionable Default = 0xA0 - - NVR clock divide. Clock frequency is divided by the NVR clock divide + 1 - - */ - unsigned int nvrClockDivide : 8; /* 1E.C451.7:0 R/WPD Provisionable Default = 0xA0 */ - /* NVR clock divide. Clock frequency is divided by the NVR clock divide + 1 - */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global NVR Provisioning */ - union - { - struct - { - unsigned int reserved0 : 14; - /*! \brief 1E.C452.1 R/W NVR Daisy Chain Clock Divide Override - AQ_GlobalNvrProvisioning_APPIA.u2.bits_2.nvrDaisyChainClockDivideOverride - - Default = 0x0 - - 1 = Override NVR clock divide when in daisy chain master mode - - - - Notes: - When in daisy chain master mode, the clock divide configuration is received from the flash. This bit will override the clock divide configuration from the flash with the See NVR Clock Divide [7:0] . */ - unsigned int nvrDaisyChainClockDivideOverride : 1; /* 1E.C452.1 R/W Default = 0x0 */ - /* 1 = Override NVR clock divide when in daisy chain master mode - - */ - /*! \brief 1E.C452.0 R/W NVR Daisy Chain Disable - AQ_GlobalNvrProvisioning_APPIA.u2.bits_2.nvrDaisyChainDisable - - Default = 0x0 - - 1 = Disable the Daisy Chain - - - Notes: - When in daisy chain master mode, the daisy chain and MDIO can both access the SPI. Setting this bit to 1 will disable the dasiy chain from accessing the SPI and force it into a reset state. */ - unsigned int nvrDaisyChainDisable : 1; /* 1E.C452.0 R/W Default = 0x0 */ - /* 1 = Disable the Daisy Chain - */ - } bits_2; - uint16_t word_2; - } u2; -} AQ_GlobalNvrProvisioning_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Reserved Provisioning: 1E.C470 */ -/* Global Reserved Provisioning: 1E.C470 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Reserved Provisioning */ - union - { - struct - { - /*! \brief 1E.C470.F R/WPD Diagnostics Select - AQ_GlobalReservedProvisioning_APPIA.u0.bits_0.diagnosticsSelect - - Provisionable Default = 0x0 - - 1 = Provide Extended MDI Diagnostics Information. - 0 = Provide normal cable diagnostics - - - Notes: - These bits select what sort of cable diagnostics to perform. For regular cable diagnostics, Bit F is set to zero, and the diagnostics are triggered by setting Bit 4. For extended diagnostics, Bit F is set to 1, and the desired extended diagnostics are selected by Bits E:D. The routine is then triggered by setting Bit 4. Each of the extended diagnostic routines present data for all for MDI pairs (A, B, C, D) consecutively, and after the data for each channel is gathered Bits F:D are reset. To get the data for the next pair, Bits F:D must be set back to the desired value (which must be the same as the initial channel). This continues until the data for all channels has been gathered. The address in memory where the data is stored is given in 1E.C802 and 1E.C804. - - For the case of PSD, the structure is as follows: - Int32 info - Int16 data[Len] - Info = Len << 16 | TxEnable << 8 | Pair (0 = A, etc.) - - For TDR: - Int32 info - Int16 tdr_A[Len] - Int16 tdr_B[Len] - Int16 tdr_C[Len] - Int16 tdr_D[Len] - - Info = Len << 16 | Channel - - TDR data is from the current pair to all other pairs. - - At the end of retrieving extended MDI diag data, the part will be reset. Conversly the only way to exit this routine once it starts is to issue a PMA reset. */ - unsigned int diagnosticsSelect : 1; /* 1E.C470.F R/WPD Provisionable Default = 0x0 */ - /* 1 = Provide Extended MDI Diagnostics Information. - 0 = Provide normal cable diagnostics - */ - /*! \brief 1E.C470.E:D R/WPD Extended MDI Diagnostics Select [1:0] - AQ_GlobalReservedProvisioning_APPIA.u0.bits_0.extendedMdiDiagnosticsSelect - - Provisionable Default = 0x0 - - 0x0 = TDR Data - 0x1 = RFI Channel PSD - 0x2 = Noise PSD while the local Tx is Off - 0x3 = Noise PSD while the local Tx is On - - - Notes: - These bits select what sort of cable diagnostics to perform. For regular cable diagnostics, Bit F is set to zero, and the diagnostics are triggered by setting Bit 4. For extended diagnostics, Bit F is set to 1, and the desired extended diagnostics are selected by Bits E:D. The routine is then triggered by setting Bit 4. Each of the extended diagnostic routines present data for all for MDI pairs (A, B, C, D) consecutively, and after the data for each channel is gathered Bits F:D are reset. To get the data for the next pair, Bits F:D must be set back to the desired value (which must be the same as the initial channel). This continues until the data for all channels has been gathered. The address in memory where the data is stored is given in 1E.C802 and 1E.C804. - - For the case of PSD, the structure is as follows: - Int32 info - Int16 data[Len] - Info = Len << 16 | TxEnable << 8 | Pair (0 = A, etc.) - - For TDR: - Int32 info - Int16 tdr_A[Len] - Int16 tdr_B[Len] - Int16 tdr_C[Len] - Int16 tdr_D[Len] - - Info = Len << 16 | Channel - - TDR data is from the current pair to all other pairs. - - At the end of retrieving extended MDI diag data, the part will be reset. Conversly the only way to exit this routine once it starts is to issue a PMA reset. */ - unsigned int extendedMdiDiagnosticsSelect : 2; /* 1E.C470.E:D R/WPD Provisionable Default = 0x0 */ - /* 0x0 = TDR Data - 0x1 = RFI Channel PSD - 0x2 = Noise PSD while the local Tx is Off - 0x3 = Noise PSD while the local Tx is On - */ - unsigned int reserved0 : 5; - unsigned int reserved1 : 2; - /*! \brief 1E.C470.5 R/WSC Initiate Component Diagnostics - AQ_GlobalReservedProvisioning_APPIA.u0.bits_0.initiateComponentDiagnostics - - Default = 0x0 - - 1 = Perform component diagnostics - - - Notes: - Perform component diagnostics regardless of link state. If link is up, setting this bit will cause the link to drop while diagnostics are performed. This bit is self-clearing upon completion of the component diagnostics. Further MDIO writes should be avoided until this bit has self-cleared, indicating completion of the diagnostic routine. */ - unsigned int initiateComponentDiagnostics : 1; /* 1E.C470.5 R/WSC Default = 0x0 */ - /* 1 = Perform component diagnostics - */ - /*! \brief 1E.C470.4 R/WSC Initiate Cable Diagnostics - AQ_GlobalReservedProvisioning_APPIA.u0.bits_0.initiateCableDiagnostics - - Default = 0x0 - - 1 = Perform cable diagnostics - - - Notes: - Perform cable diagnostics regardless of link state. If link is up, setting this bit will cause the link to drop while diagnostics are performed. This bit is self-clearing upon completion of the cable diagnostics. Further MDIO writes should be avoided until this bit has self-cleared, indicating completion of the diagnostic routine. */ - unsigned int initiateCableDiagnostics : 1; /* 1E.C470.4 R/WSC Default = 0x0 */ - /* 1 = Perform cable diagnostics - */ - unsigned int reserved2 : 4; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Reserved Provisioning */ - union - { - struct - { - /*! \brief 1E.C471.F:7 R/WPD Reserved Provisioning 2 [8:0] - AQ_GlobalReservedProvisioning_APPIA.u1.bits_1.reservedProvisioning_2 - - Provisionable Default = 0x000 - - Reserved for future use - - */ - unsigned int reservedProvisioning_2 : 9; /* 1E.C471.F:7 R/WPD Provisionable Default = 0x000 */ - /* Reserved for future use - */ - /*! \brief 1E.C471.6 R/WuP Enable Daisy-Chain Hop-Count Override - AQ_GlobalReservedProvisioning_APPIA.u1.bits_1.enableDaisy_chainHop_countOverride - - Default = 0x0 - - 1 = Hop-count is set by Bits 5:0 - 0 = Hop-count is determined by the daisy-chain - - - Notes: - Daisy-Chain Hop-Count Override should be used during MDIO boot-load operation, as the daisy-chain hop-count does not function when the daisy-chain is disabled (1E.C452.0). Setting this bit tells the processor where in the diasy-chain it is, so that the provisioning operation will function correctly. */ - unsigned int enableDaisy_chainHop_countOverride : 1; /* 1E.C471.6 R/WuP Default = 0x0 */ - /* 1 = Hop-count is set by Bits 5:0 - 0 = Hop-count is determined by the daisy-chain - */ - /*! \brief 1E.C471.5:0 R/WuP Daisy-Chain Hop-Count Override Value [5:0] - AQ_GlobalReservedProvisioning_APPIA.u1.bits_1.daisy_chainHop_countOverrideValue - - Default = 0x00 - - The value to use for the PHY's daisy-chain hop-count. Valid values are from 0 -> 47 - - - Notes: - Daisy-Chain Hop-Count Override should be used during MDIO boot-load operation, as the daisy-chain hop-count does not function when the daisy-chain is disabled (1E.C452.0). Setting this bit tells the processor where in the diasy-chain it is, so that the provisioning operation will function correctly. */ - unsigned int daisy_chainHop_countOverrideValue : 6; /* 1E.C471.5:0 R/WuP Default = 0x00 */ - /* The value to use for the PHY's daisy-chain hop-count. Valid values are from 0 -> 47 - */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global Reserved Provisioning */ - union - { - struct - { - /*! \brief 1E.C472.F R/WPD Enable LVDD Power Supply Tuning - AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.enableLvddPowerSupplyTuning - - Provisionable Default = 0x0 - - 1 = Enable external LVDD power supply tuning - 0 = Disable external LVDD power supply tuning is disabled - - - Notes: - - - - These bits control whether the PHY attempts to tune the external VDD and LVDD power supplies via the PMBus. These bits are only operational if the external supplies are present (see Bits 7:6) */ - unsigned int enableLvddPowerSupplyTuning : 1; /* 1E.C472.F R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable external LVDD power supply tuning - 0 = Disable external LVDD power supply tuning is disabled - */ - /*! \brief 1E.C472.E R/WPD Enable VDD Power Supply Tuning - AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.enableVddPowerSupplyTuning - - Provisionable Default = 0x0 - - 1 = Enable external VDD power supply tuning - 0 = Disable external VDD power supply tuning is disabled - - - Notes: - - - - These bits control whether the PHY attempts to tune the external VDD and LVDD power supplies via the PMBus. These bits are only operational if the external supplies are present (see Bits 7:6) */ - unsigned int enableVddPowerSupplyTuning : 1; /* 1E.C472.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable external VDD power supply tuning - 0 = Disable external VDD power supply tuning is disabled - */ - unsigned int reserved0 : 6; - /*! \brief 1E.C472.7 R/WPD Tunable External LVDD Power Supply Present - AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.tunableExternalLvddPowerSupplyPresent - - Provisionable Default = 0x0 - - 1 = Tunable external LVDD power supply present - 0 = No tunable external LVDD power supply present - - - Notes: - - - - These bits must be set if tuning of external power supplies is desired (see Bits 7:6) */ - unsigned int tunableExternalLvddPowerSupplyPresent : 1; /* 1E.C472.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = Tunable external LVDD power supply present - 0 = No tunable external LVDD power supply present - */ - /*! \brief 1E.C472.6 R/WPD Tunable External VDD Power Supply Present - AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.tunableExternalVddPowerSupplyPresent - - Provisionable Default = 0x0 - - 1 = Tunable external VDD power supply present - 0 = No tunable external VDD power supply present - - - Notes: - - - - These bits must be set if tuning of external power supplies is desired (see Bits 7:6) */ - unsigned int tunableExternalVddPowerSupplyPresent : 1; /* 1E.C472.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = Tunable external VDD power supply present - 0 = No tunable external VDD power supply present - */ - unsigned int reserved1 : 4; - /*! \brief 1E.C472.1 R/WPDuP Enable XENPAK Register Space - AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.enableXenpakRegisterSpace - - Provisionable Default = 0x0 - - 1 = XENPAK register space enabled - 0 = XENPAK register space disabled - - */ - unsigned int enableXenpakRegisterSpace : 1; /* 1E.C472.1 R/WPDuP Provisionable Default = 0x0 */ - /* 1 = XENPAK register space enabled - 0 = XENPAK register space disabled - */ - /*! \brief 1E.C472.0 R/WPDuP Enable 5th Channel RFI Cancellation - AQ_GlobalReservedProvisioning_APPIA.u2.bits_2.enable_5thChannelRfiCancellation - - Provisionable Default = 0x0 - - 1 = 5th channel and RFI cancellers operation enabled - 0 = 5th channel AFE is powered down, 5th channel digital is clock gated, RFI cancellers are disabled - - - Notes: - Note: The value of this bit at the time of Autonegotiation sets the local PHY behavior until the next time Autonegotiation occurs. */ - unsigned int enable_5thChannelRfiCancellation : 1; /* 1E.C472.0 R/WPDuP Provisionable Default = 0x0 */ - /* 1 = 5th channel and RFI cancellers operation enabled - 0 = 5th channel AFE is powered down, 5th channel digital is clock gated, RFI cancellers are disabled - */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global Reserved Provisioning */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of Global Reserved Provisioning */ - union - { - struct - { - unsigned int reserved0 : 8; - /*! \brief 1E.C474.7:0 R/WPD Training SNR [7:0] - AQ_GlobalReservedProvisioning_APPIA.u4.bits_4.trainingSNR - - Provisionable Default = 0x00 - - SNR during 10G training on the worst channel. SNR is in steps of 0.1dB - - - Notes: - The SNR margin that is enjoyed by the worst channel, over and above the minimum SNR required to operate at a BER of 10-12. It is reported with 0.1 dB of resolution to an accuracy of 0.5 dB within the range of -12.7 dB to 12.7 dB. The number is in offset binary, with 0.0 dB represented by 0x8000. - */ - unsigned int trainingSNR : 8; /* 1E.C474.7:0 R/WPD Provisionable Default = 0x00 */ - /* SNR during 10G training on the worst channel. SNR is in steps of 0.1dB - */ - } bits_4; - uint16_t word_4; - } u4; - /*! \brief Union for bit and word level access of word 5 of Global Reserved Provisioning */ - union - { - struct - { - unsigned int reserved0 : 2; - /*! \brief 1E.C475.D R/WPD Smart Power-Down Status - AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.smartPower_downStatus - - Provisionable Default = 0x0 - - 1 = Smart Power-Down Active - 0 = Smart Power-Down Inactive - - */ - unsigned int smartPower_downStatus : 1; /* 1E.C475.D R/WPD Provisionable Default = 0x0 */ - /* 1 = Smart Power-Down Active - 0 = Smart Power-Down Inactive - */ - /*! \brief 1E.C475.C R/WPD Reserved Provisioning 6 - AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.reservedProvisioning_6 - - Provisionable Default = 0x0 - - Reserved for future use - - */ - unsigned int reservedProvisioning_6 : 1; /* 1E.C475.C R/WPD Provisionable Default = 0x0 */ - /* Reserved for future use - */ - /*! \brief 1E.C475.B R/WPD CFR LP Disable Timer - AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrLpDisableTimer - - Provisionable Default = 0x0 - - 1 = Link partner requires cfr_disable timer - 0 = Link partner does not require cfr_disable timer - - */ - unsigned int cfrLpDisableTimer : 1; /* 1E.C475.B R/WPD Provisionable Default = 0x0 */ - /* 1 = Link partner requires cfr_disable timer - 0 = Link partner does not require cfr_disable timer - */ - /*! \brief 1E.C475.A R/WPD CFR LP Extended Maxwait - AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrLpExtendedMaxwait - - Provisionable Default = 0x0 - - 1 = Link partner requires extended maxwait - 0 = Link partner does not require extended maxwait - - */ - unsigned int cfrLpExtendedMaxwait : 1; /* 1E.C475.A R/WPD Provisionable Default = 0x0 */ - /* 1 = Link partner requires extended maxwait - 0 = Link partner does not require extended maxwait - */ - /*! \brief 1E.C475.9 R/WPD CFR LP THP - AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrLpTHP - - Provisionable Default = 0x0 - - 1 = Link partner requires local PHY to enable THP - 0 = Link partner does not require local PHY to enable THP - - */ - unsigned int cfrLpTHP : 1; /* 1E.C475.9 R/WPD Provisionable Default = 0x0 */ - /* 1 = Link partner requires local PHY to enable THP - 0 = Link partner does not require local PHY to enable THP - */ - /*! \brief 1E.C475.8 R/WPD CFR LP Support - AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrLpSupport - - Provisionable Default = 0x0 - - 1 = Link partner supports Cisco Fast Retrain - 0 = Link partner does support Cisco Fast Retrain - - */ - unsigned int cfrLpSupport : 1; /* 1E.C475.8 R/WPD Provisionable Default = 0x0 */ - /* 1 = Link partner supports Cisco Fast Retrain - 0 = Link partner does support Cisco Fast Retrain - */ - /*! \brief 1E.C475.7 R/WPD CFR Disable Timer - AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrDisableTimer - - Provisionable Default = 0x0 - - 1 = Local PHY requires cfr_disable timer - 0 = Local PHY does not require cfr_disable timer - - */ - unsigned int cfrDisableTimer : 1; /* 1E.C475.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = Local PHY requires cfr_disable timer - 0 = Local PHY does not require cfr_disable timer - */ - /*! \brief 1E.C475.6 R/WPD CFR Extended Maxwait - AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrExtendedMaxwait - - Provisionable Default = 0x0 - - 1 = Local PHY requires extended maxwait - 0 = Local PHY does not require extended maxwait - - */ - unsigned int cfrExtendedMaxwait : 1; /* 1E.C475.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = Local PHY requires extended maxwait - 0 = Local PHY does not require extended maxwait - */ - /*! \brief 1E.C475.5 R/WPD CFR THP - AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrTHP - - Provisionable Default = 0x0 - - 1 = Local PHY requires local PHY to enable THP - 0 = Local PHY does not require local PHY to enable THP - - */ - unsigned int cfrTHP : 1; /* 1E.C475.5 R/WPD Provisionable Default = 0x0 */ - /* 1 = Local PHY requires local PHY to enable THP - 0 = Local PHY does not require local PHY to enable THP - */ - /*! \brief 1E.C475.4 R/WPD CFR Support - AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.cfrSupport - - Provisionable Default = 0x0 - - 1 = Local PHY supports Cisco Fast Retrain - 0 = Local PHY does support Cisco Fast Retrain - - */ - unsigned int cfrSupport : 1; /* 1E.C475.4 R/WPD Provisionable Default = 0x0 */ - /* 1 = Local PHY supports Cisco Fast Retrain - 0 = Local PHY does support Cisco Fast Retrain - */ - /*! \brief 1E.C475.3 R/WPD Deadlock Avoidance Enable - AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.deadlockAvoidanceEnable - - Provisionable Default = 0x0 - - 1 = SPD with deadlock avoidance: PHY transmits autonegotiation pulses (FLPs) at a slower rate (~ 1 FLP/ 100ms) than specified by autonegotiation standard (~1 FLP / 8.25ms). Receiver is active and able to detect the pulses. - 0 = SPD without deadlock avoidance: PHY transmitter is shut down, no autonegotiation pulses are sent on the line but the receiver is active and able to detect the pulses - - */ - unsigned int deadlockAvoidanceEnable : 1; /* 1E.C475.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = SPD with deadlock avoidance: PHY transmits autonegotiation pulses (FLPs) at a slower rate (~ 1 FLP/ 100ms) than specified by autonegotiation standard (~1 FLP / 8.25ms). Receiver is active and able to detect the pulses. - 0 = SPD without deadlock avoidance: PHY transmitter is shut down, no autonegotiation pulses are sent on the line but the receiver is active and able to detect the pulses - */ - /*! \brief 1E.C475.2 R/WPD Smart Power-Down Enable - AQ_GlobalReservedProvisioning_APPIA.u5.bits_5.smartPower_downEnable - - Provisionable Default = 0x0 - - 1 = Enable smart power down mode - 0 = Smart power-down mode disabled - - - Notes: - Smart power down (SPD) is the lowest power mode at which PHY is able to autonegotiate. SPD can be enabled with bit 1E.C475.2 */ - unsigned int smartPower_downEnable : 1; /* 1E.C475.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable smart power down mode - 0 = Smart power-down mode disabled - */ - unsigned int reserved1 : 2; - } bits_5; - uint16_t word_5; - } u5; -} AQ_GlobalReservedProvisioning_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Cable Diagnostic Status: 1E.C800 */ -/* Global Cable Diagnostic Status: 1E.C800 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Cable Diagnostic Status */ - union - { - struct - { - unsigned int reserved0 : 1; - /*! \brief 1E.C800.E:C RO Pair A Status [2:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u0.bits_0.pairAStatus - - - - (after running cable diags) - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair D - 010= Connected to Pair C - 001= Connected to Pair B - 000= OK - - OR: - - (after running component diags) - 100 = TX pin open - 011= TX bias open - 010= Capacitor short - 001= Inductor open - 000= OK - - Notes: - This bitfield reports the result, for pair A, of running either cable diagnostics or component diagnostics. */ - unsigned int pairAStatus : 3; /* 1E.C800.E:C RO */ - /* (after running cable diags) - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair D - 010= Connected to Pair C - 001= Connected to Pair B - 000= OK - - OR: - - (after running component diags) - 100 = TX pin open - 011= TX bias open - 010= Capacitor short - 001= Inductor open - 000= OK */ - unsigned int reserved1 : 1; - /*! \brief 1E.C800.A:8 RO Pair B Status [2:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u0.bits_0.pairBStatus - - - - (after running cable diags) - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair A - 010= Connected to Pair D - 001= Connected to Pair C - 000= OK - - OR: - - (after running component diags) - 100 = TX pin open - 011= TX bias open - 010= Capacitor short - 001= Inductor open - 000= OK - - Notes: - This bitfield reports the result, for pair B, of running either cable diagnostics or component diagnostics. */ - unsigned int pairBStatus : 3; /* 1E.C800.A:8 RO */ - /* (after running cable diags) - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair A - 010= Connected to Pair D - 001= Connected to Pair C - 000= OK - - OR: - - (after running component diags) - 100 = TX pin open - 011= TX bias open - 010= Capacitor short - 001= Inductor open - 000= OK */ - unsigned int reserved2 : 1; - /*! \brief 1E.C800.6:4 RO Pair C Status [2:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u0.bits_0.pairCStatus - - - - (after running cable diags) - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair B - 010= Connected to Pair A - 001= Connected to Pair D - 000= OK - - OR: - - (after running component diags) - 100 = TX pin open - 011= TX bias open - 010= Capacitor short - 001= Inductor open - 000= OK - - Notes: - This bitfield reports the result, for pair C, of running either cable diagnostics or component diagnostics. */ - unsigned int pairCStatus : 3; /* 1E.C800.6:4 RO */ - /* (after running cable diags) - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair B - 010= Connected to Pair A - 001= Connected to Pair D - 000= OK - - OR: - - (after running component diags) - 100 = TX pin open - 011= TX bias open - 010= Capacitor short - 001= Inductor open - 000= OK */ - unsigned int reserved3 : 1; - /*! \brief 1E.C800.2:0 RO Pair D Status [2:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u0.bits_0.pairDStatus - - - - (after running cable diags) - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair C - 010= Connected to Pair B - 001= Connected to Pair A - 000= OK - - OR: - - (after running component diags) - 100 = TX pin open - 011= TX bias open - 010= Capacitor short - 001= Inductor open - 000= OK - - Notes: - This bitfield reports the result, for pair D, of running either cable diagnostics or component diagnostics. */ - unsigned int pairDStatus : 3; /* 1E.C800.2:0 RO */ - /* (after running cable diags) - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair C - 010= Connected to Pair B - 001= Connected to Pair A - 000= OK - - OR: - - (after running component diags) - 100 = TX pin open - 011= TX bias open - 010= Capacitor short - 001= Inductor open - 000= OK */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C801.F:8 RO Pair A Reflection #1 [7:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u1.bits_1.pairAReflection_1 - - - - The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair A - - Notes: - The distance to this reflection is given in See Global Reserved Status 1: Address 1E.C870 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairAReflection_1 : 8; /* 1E.C801.F:8 RO */ - /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair A */ - /*! \brief 1E.C801.7:0 RO Pair A Reflection #2 [7:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u1.bits_1.pairAReflection_2 - - - - The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair A - - Notes: - The distance to this reflection is given in See Global Reserved Status 1: Address 1E.C870 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairAReflection_2 : 8; /* 1E.C801.7:0 RO */ - /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair A */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C802.F:0 RO Impulse Response MSW [F:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u2.bits_2.impulseResponseMSW - - - - The MSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type in 1E.C470.E:D - - - Notes: - See 1E.C470 for more information */ - unsigned int impulseResponseMSW : 16; /* 1E.C802.F:0 RO */ - /* The MSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type in 1E.C470.E:D - */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C803.F:8 RO Pair B Reflection #1 [7:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u3.bits_3.pairBReflection_1 - - - - The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair B - - Notes: - The distance to this reflection is given in See Global Reserved Status 2: Address 1E.C871 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairBReflection_1 : 8; /* 1E.C803.F:8 RO */ - /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair B */ - /*! \brief 1E.C803.7:0 RO Pair B Reflection #2 [7:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u3.bits_3.pairBReflection_2 - - - - The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair B - - Notes: - The distance to this reflection is given in See Global Reserved Status 2: Address 1E.C871 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairBReflection_2 : 8; /* 1E.C803.7:0 RO */ - /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair B */ - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C804.F:0 RO Impulse Response LSW [F:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u4.bits_4.impulseResponseLSW - - - - The LSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type specified in 1E.C470.E:D - - - Notes: - See 1E.C470 for more information */ - unsigned int impulseResponseLSW : 16; /* 1E.C804.F:0 RO */ - /* The LSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type specified in 1E.C470.E:D - */ - } bits_4; - uint16_t word_4; - } u4; - /*! \brief Union for bit and word level access of word 5 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C805.F:8 RO Pair C Reflection #1 [7:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u5.bits_5.pairCReflection_1 - - - - The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair C - - Notes: - The distance to this reflection is given in See Global Reserved Status 3: Address 1E.C872 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairCReflection_1 : 8; /* 1E.C805.F:8 RO */ - /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair C */ - /*! \brief 1E.C805.7:0 RO Pair C Reflection #2 [7:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u5.bits_5.pairCReflection_2 - - - - The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair C - - Notes: - The distance to this reflection is given in See Global Reserved Status 3: Address 1E.C872 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairCReflection_2 : 8; /* 1E.C805.7:0 RO */ - /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair C */ - } bits_5; - uint16_t word_5; - } u5; - /*! \brief Union for bit and word level access of word 6 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C806.F:0 RO Reserved 1 [F:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u6.bits_6.reserved_1 - - - - Reserved for future use - - */ - unsigned int reserved_1 : 16; /* 1E.C806.F:0 RO */ - /* Reserved for future use - */ - } bits_6; - uint16_t word_6; - } u6; - /*! \brief Union for bit and word level access of word 7 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C807.F:8 RO Pair D Reflection #1 [7:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u7.bits_7.pairDReflection_1 - - - - The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair D - - Notes: - The distance to this reflection is given in See Global Reserved Status 4: Address 1E.C873 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairDReflection_1 : 8; /* 1E.C807.F:8 RO */ - /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair D */ - /*! \brief 1E.C807.7:0 RO Pair D Reflection #2 [7:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u7.bits_7.pairDReflection_2 - - - - The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair D - - Notes: - The distance to this reflection is given in See Global Reserved Status 4: Address 1E.C873 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairDReflection_2 : 8; /* 1E.C807.7:0 RO */ - /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair D */ - } bits_7; - uint16_t word_7; - } u7; - /*! \brief Union for bit and word level access of word 8 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C808.F:0 RO Reserved 2[F:0] - AQ_GlobalCableDiagnosticStatus_APPIA.u8.bits_8.reserved_2 - - - - Reserved for future use - - */ - unsigned int reserved_2 : 16; /* 1E.C808.F:0 RO */ - /* Reserved for future use - */ - } bits_8; - uint16_t word_8; - } u8; -} AQ_GlobalCableDiagnosticStatus_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Thermal Status: 1E.C820 */ -/* Global Thermal Status: 1E.C820 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Thermal Status */ - union - { - struct - { - /*! \brief 1E.C820.F:0 RO Temperature [F:0] - AQ_GlobalThermalStatus_APPIA.u0.bits_0.temperature - - - - [F:0] of temperature - - - Notes: - 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 70 degreesC. This is a mirror of the XENPAK register 1.A060 - 1.A061. The mirror is performed in H/W. */ - unsigned int temperature : 16; /* 1E.C820.F:0 RO */ - /* [F:0] of temperature - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Thermal Status */ - union - { - struct - { - unsigned int reserved0 : 15; - /*! \brief 1E.C821.0 RO Temperature Ready - AQ_GlobalThermalStatus_APPIA.u1.bits_1.temperatureReady - - - - 1 = Temperature measurement is valid - - - Notes: - This is a mirror of the XENPAK register 1.A06E. */ - unsigned int temperatureReady : 1; /* 1E.C821.0 RO */ - /* 1 = Temperature measurement is valid - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_GlobalThermalStatus_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global General Status: 1E.C830 */ -/* Global General Status: 1E.C830 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global General Status */ - union - { - struct - { - unsigned int reserved0 : 1; - /*! \brief 1E.C830.E RO High Temperature Failure State - AQ_GlobalGeneralStatus_APPIA.u0.bits_0.highTemperatureFailureState - - - - 1 = High temperature failure threshold has been exceeded - - Notes: - In XENPAK mode, F/W will copy this register to the 1.A070.7 register. - - */ - unsigned int highTemperatureFailureState : 1; /* 1E.C830.E RO */ - /* 1 = High temperature failure threshold has been exceeded */ - /*! \brief 1E.C830.D RO Low Temperature Failure State - AQ_GlobalGeneralStatus_APPIA.u0.bits_0.lowTemperatureFailureState - - - - 1 = Low temperature failure threshold has been exceeded - - Notes: - In XENPAK mode, F/W will copy this register to the 1.A070.6 register. - - */ - unsigned int lowTemperatureFailureState : 1; /* 1E.C830.D RO */ - /* 1 = Low temperature failure threshold has been exceeded */ - /*! \brief 1E.C830.C RO High Temperature Warning State - AQ_GlobalGeneralStatus_APPIA.u0.bits_0.highTemperatureWarningState - - - - 1 = High temperature warning threshold has been exceeded - - Notes: - In XENPAK mode, F/W will copy this register to the 1.A074.7 register. - - */ - unsigned int highTemperatureWarningState : 1; /* 1E.C830.C RO */ - /* 1 = High temperature warning threshold has been exceeded */ - /*! \brief 1E.C830.B RO Low Temperature Warning State - AQ_GlobalGeneralStatus_APPIA.u0.bits_0.lowTemperatureWarningState - - - - 1 = Low temperature warning threshold has been exceeded - - Notes: - In XENPAK mode, F/W will copy this register to the 1.A074.6 register. - - */ - unsigned int lowTemperatureWarningState : 1; /* 1E.C830.B RO */ - /* 1 = Low temperature warning threshold has been exceeded */ - unsigned int reserved1 : 11; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global General Status */ - union - { - struct - { - /*! \brief 1E.C831.F RO Processor Intensive MDIO Operation In- Progress - AQ_GlobalGeneralStatus_APPIA.u1.bits_1.processorIntensiveMdioOperationIn_Progress - - - - 1 = PHY microprocessor is busy with a processor-intensive MDIO operation - 0 = Processor-intensive MDIO operation completed - - - Notes: - This bit should may be used with certain processor-intensive MDIO commands (such as Loopbacks, Test Modes, Low power modes, Tx-Disable, Restart autoneg, Cable Diagnostics, etc.) that take longer than an MDIO cycle to complete. Upon receiving an MDIO command that involves the PHY's microprocessor, this bit is set, and when the command is completed, this bit is cleared. - - NOTE!!! This bit should be checked only after 1 ms of issuing a processor-intensive MDIO operation. - - The list of operations that set this bit are as follows: - - 1.0.0, PMA Loopback - 1.0.B, Low power mode - 1.9.4:0, Tx Disable - 1.84, 10G Test modes - 1.8000.5, XENPAK Control - 1.9000, XENPAK Rx Fault Enable - 1.9002, XENPAK Alarm Enable - 1.E400.F, External loopback - 3.0.B, Low power mode - 3.0.E, System PCS loopback - 3.C471.5, PRBS Test - 3.C471.6, PRBS Test - 3.E471.5, PRBS Test - 3.E471.6, PRBS Test - 4.0.B, Low power mode - 4.0.E, PHY-XS network loopback - 4.C440, Output clock control, Load SERDES parameters - 4.F802.E, System loopback - 4.C444.F:B, Loopback Control - 4.C444.4:2, Packet generation - 4.C445.C, SERDES calibration - 7.0.9, Restart autonegotiation - 1D.C280, 1G/100M Network loopback - 1D.C500, 1G System loopback - 1D.C501, 1G / 100M Test modes */ - unsigned int processorIntensiveMdioOperationIn_Progress : 1; /* 1E.C831.F RO */ - /* 1 = PHY microprocessor is busy with a processor-intensive MDIO operation - 0 = Processor-intensive MDIO operation completed - */ - unsigned int reserved0 : 15; - } bits_1; - uint16_t word_1; - } u1; -} AQ_GlobalGeneralStatus_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Pin Status: 1E.C840 */ -/* Global Pin Status: 1E.C840 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Pin Status */ - union - { - struct - { - unsigned int reserved0 : 1; - /*! \brief 1E.C840.E:D RO MDIO Boot Load [1:0] - AQ_GlobalPinStatus_APPIA.u0.bits_0.mdioBootLoad - - - - Value of MDIO Boot Load pins - - 0x3 = PHY #0 Slave Daisy Chain Boot - 0x2 = PHY #0 Master Daisy Chain Boot from Flash - 0x1 = MDIO Boot Load - 0x0 = Boot from Flash (PHY #0 only) - - - Notes: - NOTES: - - PHY #0 is the primary PHY, and PHY #1 is the secondary PHY - - PHY #1 is always in Slave Daisy Chain Boot from Flash when set to 0x2 or 0x3. */ - unsigned int mdioBootLoad : 2; /* 1E.C840.E:D RO */ - /* Value of MDIO Boot Load pins - - 0x3 = PHY #0 Slave Daisy Chain Boot - 0x2 = PHY #0 Master Daisy Chain Boot from Flash - 0x1 = MDIO Boot Load - 0x0 = Boot from Flash (PHY #0 only) - */ - unsigned int reserved1 : 3; - /*! \brief 1E.C840.9 RO Package Connectivity - AQ_GlobalPinStatus_APPIA.u0.bits_0.packageConnectivity - - - - Value of the package connection pin - - */ - unsigned int packageConnectivity : 1; /* 1E.C840.9 RO */ - /* Value of the package connection pin - */ - unsigned int reserved2 : 1; - /*! \brief 1E.C840.7 RO Tx Enable - AQ_GlobalPinStatus_APPIA.u0.bits_0.txEnable - - - - Current Value of Tx Enable pin - - - Notes: - 0 = Disable Transmitter */ - unsigned int txEnable : 1; /* 1E.C840.7 RO */ - /* Current Value of Tx Enable pin - */ - unsigned int reserved3 : 1; - /*! \brief 1E.C840.5:0 RO LED Pullup State [5:0] - AQ_GlobalPinStatus_APPIA.u0.bits_0.ledPullupState - - - - 1 = LED output pin is pulled high - 0 = LED output pin is pulled low - - */ - unsigned int ledPullupState : 6; /* 1E.C840.5:0 RO */ - /* 1 = LED output pin is pulled high - 0 = LED output pin is pulled low - */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalPinStatus_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Daisy Chain Status: 1E.C842 */ -/* Global Daisy Chain Status: 1E.C842 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Daisy Chain Status */ - union - { - struct - { - /*! \brief 1E.C842.F:0 RO Rx Daisy Chain Calculated CRC [F:0] - AQ_GlobalDaisyChainStatus_APPIA.u0.bits_0.rxDaisyChainCalculatedCrc - - - - Rx Daisy Chain Calculated CRC - - - Notes: - This is the calculated daisy chain CRC. */ - unsigned int rxDaisyChainCalculatedCrc : 16; /* 1E.C842.F:0 RO */ - /* Rx Daisy Chain Calculated CRC - */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalDaisyChainStatus_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Fault Message: 1E.C850 */ -/* Global Fault Message: 1E.C850 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Fault Message */ - union - { - struct - { - /*! \brief 1E.C850.F:0 RO Message [F:0] - AQ_GlobalFaultMessage_APPIA.u0.bits_0.message - - - - Error code describing fault - - Notes: - Code 0x8001: Firmware not compatible with chip architecture. This fault occurs when firmware compiled for a different Tensilica core is loaded. - Code 0x8002: VCO calibration failed. This occurs when the main PLLs on chip fail to lock: this is not possible to trigger. - Code 0x8003: XAUI calibration failed. This occurs when the XAUI PLLs fail to lock: this is not possible to trigger. - Code 0x8004: Failed to set operating voltages via PMBus. This only occurs when the processor has control over power supply voltage via an attached PMBus device and there is a protocol error on the I2C bus: this is not possible to trigger. - Code 0x8005: Unexpected device ID. This occurs if the device ID programmed into the internal E-Fuse registers in not valid: this is not possible to trigger. - Code 0x8006: Computed checksum does not match expected checksum. This occurs when the FLASH checksum check performed at boot time fails. This only occurs when the system boots from FLASH. - Code 0x8007: Detected a bit error in static memory. To trigger, corrupt one of the static regions. - Code 0xC001: Illegal Instruction exception. This occurs when the processor attempts to execute an illegal instruction. To trigger this, write an illegal instruction to program memory. It's possible that the bit error check will trigger before the illegal instruction is executed. - Code 0xC002 Instruction Fetch Error. Internal physical address or a data error during instruction fetch: this is not possible to trigger. - Code 0xC003 Load Store Error. Internal physical address or data error during load store operation: this is not possible to trigger.. - Code 0xC004 Privileged Instruction. Attempt to execute a privileged operation without sufficient privilege: this is not possible to trigger. - Code 0xC005 Unaligned Load or Store. Attempt to load or store data at an address which cannot be handled due to alignment: this is not possible to trigger. - Code 0xC006 Instruction fetch from prohibited space: this is not possible to trigger. - Code 0xC007 Data load from prohibited space: this is not possible to trigger. - Code 0xC008 Data store into prohibited space: this is not possible to trigger. */ - unsigned int message : 16; /* 1E.C850.F:0 RO */ - /* Error code describing fault */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalFaultMessage_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Primary Status: 1E.C851 */ -/* Global Primary Status: 1E.C851 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Primary Status */ - union - { - struct - { - unsigned int reserved0 : 15; - /*! \brief 1E.C851.0 RO Primary Status - AQ_GlobalPrimaryStatus_APPIA.u0.bits_0.primaryStatus - - - - 1 = PHY is the primary PHY - 0 = PHY is is secondary PHY - - */ - unsigned int primaryStatus : 1; /* 1E.C851.0 RO */ - /* 1 = PHY is the primary PHY - 0 = PHY is is secondary PHY - */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalPrimaryStatus_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Cable Diagnostic Impedance: 1E.C880 */ -/* Global Cable Diagnostic Impedance: 1E.C880 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Cable Diagnostic Impedance */ - union - { - struct - { - /*! \brief 1E.C880.F RO Reserved 1 - AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.reserved_1 - - - - Reserved for future use - - */ - unsigned int reserved_1 : 1; /* 1E.C880.F RO */ - /* Reserved for future use - */ - /*! \brief 1E.C880.E:C RO Pair A Reflection #1 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.pairAReflection_1 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the first worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ - unsigned int pairAReflection_1 : 3; /* 1E.C880.E:C RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C880.B RO Reserved 2 - AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.reserved_2 - - - - Reserved for future use - - */ - unsigned int reserved_2 : 1; /* 1E.C880.B RO */ - /* Reserved for future use - */ - /*! \brief 1E.C880.A:8 RO Pair A Reflection #2 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.pairAReflection_2 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the second worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ - unsigned int pairAReflection_2 : 3; /* 1E.C880.A:8 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C880.7 RO Reserved 3 - AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.reserved_3 - - - - Reserved for future use - - */ - unsigned int reserved_3 : 1; /* 1E.C880.7 RO */ - /* Reserved for future use - */ - /*! \brief 1E.C880.6:4 RO Pair A Reflection #3 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.pairAReflection_3 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the third worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ - unsigned int pairAReflection_3 : 3; /* 1E.C880.6:4 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C880.3 RO Reserved 4 - AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.reserved_4 - - - - Reserved for future use - - */ - unsigned int reserved_4 : 1; /* 1E.C880.3 RO */ - /* Reserved for future use - */ - /*! \brief 1E.C880.2:0 RO Pair A Reflection #4 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u0.bits_0.pairAReflection_4 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the fourth worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ - unsigned int pairAReflection_4 : 3; /* 1E.C880.2:0 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Cable Diagnostic Impedance */ - union - { - struct - { - /*! \brief 1E.C881.F RO Reserved 5 - AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.reserved_5 - - - - Reserved for future use - - */ - unsigned int reserved_5 : 1; /* 1E.C881.F RO */ - /* Reserved for future use - */ - /*! \brief 1E.C881.E:C RO Pair B Reflection #1 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.pairBReflection_1 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the first worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ - unsigned int pairBReflection_1 : 3; /* 1E.C881.E:C RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C881.B RO Reserved 6 - AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.reserved_6 - - - - Reserved for future use - - */ - unsigned int reserved_6 : 1; /* 1E.C881.B RO */ - /* Reserved for future use - */ - /*! \brief 1E.C881.A:8 RO Pair B Reflection #2 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.pairBReflection_2 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the second worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ - unsigned int pairBReflection_2 : 3; /* 1E.C881.A:8 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C881.7 RO Reserved 7 - AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.reserved_7 - - - - Reserved for future use - - */ - unsigned int reserved_7 : 1; /* 1E.C881.7 RO */ - /* Reserved for future use - */ - /*! \brief 1E.C881.6:4 RO Pair B Reflection #3 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.pairBReflection_3 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the third worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ - unsigned int pairBReflection_3 : 3; /* 1E.C881.6:4 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C881.3 RO Reserved 8 - AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.reserved_8 - - - - Reserved for future use - - */ - unsigned int reserved_8 : 1; /* 1E.C881.3 RO */ - /* Reserved for future use - */ - /*! \brief 1E.C881.2:0 RO Pair B Reflection #4 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u1.bits_1.pairBReflection_4 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the fourth worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ - unsigned int pairBReflection_4 : 3; /* 1E.C881.2:0 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global Cable Diagnostic Impedance */ - union - { - struct - { - /*! \brief 1E.C882.F RO Reserved 9 - AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.reserved_9 - - - - Reserved for future use - - */ - unsigned int reserved_9 : 1; /* 1E.C882.F RO */ - /* Reserved for future use - */ - /*! \brief 1E.C882.E:C RO Pair C Reflection #1 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.pairCReflection_1 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the first worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ - unsigned int pairCReflection_1 : 3; /* 1E.C882.E:C RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C882.B RO Reserved 10 - AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.reserved_10 - - - - Reserved for future use - - */ - unsigned int reserved_10 : 1; /* 1E.C882.B RO */ - /* Reserved for future use - */ - /*! \brief 1E.C882.A:8 RO Pair C Reflection #2 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.pairCReflection_2 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the second worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ - unsigned int pairCReflection_2 : 3; /* 1E.C882.A:8 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C882.7 RO Reserved 11 - AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.reserved_11 - - - - Reserved for future use - - */ - unsigned int reserved_11 : 1; /* 1E.C882.7 RO */ - /* Reserved for future use - */ - /*! \brief 1E.C882.6:4 RO Pair C Reflection #3 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.pairCReflection_3 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the third worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ - unsigned int pairCReflection_3 : 3; /* 1E.C882.6:4 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C882.3 RO Reserved 12 - AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.reserved_12 - - - - Reserved for future use - - */ - unsigned int reserved_12 : 1; /* 1E.C882.3 RO */ - /* Reserved for future use - */ - /*! \brief 1E.C882.2:0 RO Pair C Reflection #4 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u2.bits_2.pairCReflection_4 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the fourth worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ - unsigned int pairCReflection_4 : 3; /* 1E.C882.2:0 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global Cable Diagnostic Impedance */ - union - { - struct - { - /*! \brief 1E.C883.F RO Reserved 13 - AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.reserved_13 - - - - Reserved for future use - - */ - unsigned int reserved_13 : 1; /* 1E.C883.F RO */ - /* Reserved for future use - */ - /*! \brief 1E.C883.E:C RO Pair D Reflection #1 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.pairDReflection_1 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the first worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ - unsigned int pairDReflection_1 : 3; /* 1E.C883.E:C RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C883.B RO Reserved 14 - AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.reserved_14 - - - - Reserved for future use - - */ - unsigned int reserved_14 : 1; /* 1E.C883.B RO */ - /* Reserved for future use - */ - /*! \brief 1E.C883.A:8 RO Pair D Reflection #2 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.pairDReflection_2 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the second worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ - unsigned int pairDReflection_2 : 3; /* 1E.C883.A:8 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C883.7 RO Reserved 15 - AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.reserved_15 - - - - Reserved for future use - - */ - unsigned int reserved_15 : 1; /* 1E.C883.7 RO */ - /* Reserved for future use - */ - /*! \brief 1E.C883.6:4 RO Pair D Reflection #3 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.pairDReflection_3 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the third worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ - unsigned int pairDReflection_3 : 3; /* 1E.C883.6:4 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C883.3 RO Reserved 16 - AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.reserved_16 - - - - Reserved for future use - - */ - unsigned int reserved_16 : 1; /* 1E.C883.3 RO */ - /* Reserved for future use - */ - /*! \brief 1E.C883.2:0 RO Pair D Reflection #4 [2:0] - AQ_GlobalCableDiagnosticImpedance_APPIA.u3.bits_3.pairDReflection_4 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the fourth worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ - unsigned int pairDReflection_4 : 3; /* 1E.C883.2:0 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - } bits_3; - uint16_t word_3; - } u3; -} AQ_GlobalCableDiagnosticImpedance_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Status: 1E.C884 */ -/* Global Status: 1E.C884 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Status */ - union - { - struct - { - /*! \brief 1E.C884.F:8 RO Reserved Status 0 [7:0] - AQ_GlobalStatus_APPIA.u0.bits_0.reservedStatus_0 - - - - Reserved for future use - - */ - unsigned int reservedStatus_0 : 8; /* 1E.C884.F:8 RO */ - /* Reserved for future use - */ - /*! \brief 1E.C884.7:0 RO Cable Length [7:0] - AQ_GlobalStatus_APPIA.u0.bits_0.cableLength - - - - The estimated length of the cable in meters - - - Notes: - The length of the cable shown here is estimated from the cable diagnostic engine and should be accurate to +/-1m. */ - unsigned int cableLength : 8; /* 1E.C884.7:0 RO */ - /* The estimated length of the cable in meters - */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalStatus_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Reserved Status: 1E.C885 */ -/* Global Reserved Status: 1E.C885 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Reserved Status */ - union - { - struct - { - /*! \brief 1E.C885.F:A RO Nearly Seconds MSW[5:0] - AQ_GlobalReservedStatus_APPIA.u0.bits_0.nearlySecondsMSW - - - - Bits 16 to 21 of the 22 bit "Nearly Seconds" uptime counter. - - - Notes: - The "Nearly Seconds" counter is incremented every 1024 milliseconds. */ - unsigned int nearlySecondsMSW : 6; /* 1E.C885.F:A RO */ - /* Bits 16 to 21 of the 22 bit "Nearly Seconds" uptime counter. - */ - /*! \brief 1E.C885.9:8 ROSPD XENPAK NVR Status [1:0] - AQ_GlobalReservedStatus_APPIA.u0.bits_0.xenpakNvrStatus - - Provisionable Default = 0x0 - - Status of XENPAK NVR: - 0: NVR not enabled - 1: Last NVR operation succeeded - 2: Last NVR operation failed - 3: Reserved - - - Notes: - XENPAK register space is mirrored in NVR (SPI ROM). This register indicates the status of the last NVR operation. */ - unsigned int xenpakNvrStatus : 2; /* 1E.C885.9:8 ROSPD Provisionable Default = 0x0 */ - /* Status of XENPAK NVR: - 0: NVR not enabled - 1: Last NVR operation succeeded - 2: Last NVR operation failed - 3: Reserved - */ - /*! \brief 1E.C885.7:0 ROSPD ROM Revision [7:0] - AQ_GlobalReservedStatus_APPIA.u0.bits_0.romRevision - - Provisionable Default = 0x00 - - ROM Revision Number - - - Notes: - Customers may receive multiple ROM images that differ only in their provisioning. This field is used to differentiate those images. This field is used in conjunction with the firmware major and minor revision numbers to uniquely identify ROM images. */ - unsigned int romRevision : 8; /* 1E.C885.7:0 ROSPD Provisionable Default = 0x00 */ - /* ROM Revision Number - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Reserved Status */ - union - { - struct - { - /*! \brief 1E.C886.F:0 RO Nearly Seconds LSW[F:0] - AQ_GlobalReservedStatus_APPIA.u1.bits_1.nearlySecondsLSW - - - - Bits 0 to 15 of the 22 bit "Nearly Seconds" uptime counter. - - - Notes: - The "Nearly Seconds" counter is incremented every 1024 milliseconds. */ - unsigned int nearlySecondsLSW : 16; /* 1E.C886.F:0 RO */ - /* Bits 0 to 15 of the 22 bit "Nearly Seconds" uptime counter. - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_GlobalReservedStatus_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Alarms: 1E.CC00 */ -/* Global Alarms: 1E.CC00 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Alarms */ - union - { - struct - { - unsigned int reserved0 : 1; - /*! \brief 1E.CC00.E LH High Temperature Failure - AQ_GlobalAlarms_APPIA.u0.bits_0.highTemperatureFailure - - - - 1 = High temperature failure threshold has been exceeded - - - Notes: - - - - - These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ - unsigned int highTemperatureFailure : 1; /* 1E.CC00.E LH */ - /* 1 = High temperature failure threshold has been exceeded - */ - /*! \brief 1E.CC00.D LH Low Temperature Failure - AQ_GlobalAlarms_APPIA.u0.bits_0.lowTemperatureFailure - - - - 1 = Low temperature failure threshold has been exceeded - - - Notes: - - - - - These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ - unsigned int lowTemperatureFailure : 1; /* 1E.CC00.D LH */ - /* 1 = Low temperature failure threshold has been exceeded - */ - /*! \brief 1E.CC00.C LH High Temperature Warning - AQ_GlobalAlarms_APPIA.u0.bits_0.highTemperatureWarning - - - - 1 = High temperature warning threshold has been exceeded - - - Notes: - - - - - These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ - unsigned int highTemperatureWarning : 1; /* 1E.CC00.C LH */ - /* 1 = High temperature warning threshold has been exceeded - */ - /*! \brief 1E.CC00.B LH Low Temperature Warning - AQ_GlobalAlarms_APPIA.u0.bits_0.lowTemperatureWarning - - - - 1 = Low temperature warning threshold has been exceeded - - - Notes: - - - - - These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ - unsigned int lowTemperatureWarning : 1; /* 1E.CC00.B LH */ - /* 1 = Low temperature warning threshold has been exceeded - */ - unsigned int reserved1 : 4; - /*! \brief 1E.CC00.6 LH Reset completed - AQ_GlobalAlarms_APPIA.u0.bits_0.resetCompleted - - - - 1 = Chip wide reset completed - - Notes: - This bit is set by the microprocessor when it has completed it's initialization sequence. This bit is mirrored in 1.CC02.0 */ - unsigned int resetCompleted : 1; /* 1E.CC00.6 LH */ - /* 1 = Chip wide reset completed */ - unsigned int reserved2 : 1; - /*! \brief 1E.CC00.4 LH Device Fault - AQ_GlobalAlarms_APPIA.u0.bits_0.deviceFault - - - - 1 = Fault - - Notes: - When set, a fault has been detected by the uP and the associated 16 bit error code is visible in See Global Configuration Fault Message: Address 1E.C850 */ - unsigned int deviceFault : 1; /* 1E.CC00.4 LH */ - /* 1 = Fault */ - /*! \brief 1E.CC00.3 LH Reserved Alarm A - AQ_GlobalAlarms_APPIA.u0.bits_0.reservedAlarmA - - - - Reserved for future use - - */ - unsigned int reservedAlarmA : 1; /* 1E.CC00.3 LH */ - /* Reserved for future use - */ - /*! \brief 1E.CC00.2 LH Reserved Alarm B - AQ_GlobalAlarms_APPIA.u0.bits_0.reservedAlarmB - - - - Reserved for future use - - */ - unsigned int reservedAlarmB : 1; /* 1E.CC00.2 LH */ - /* Reserved for future use - */ - /*! \brief 1E.CC00.1 LH Reserved Alarm C - AQ_GlobalAlarms_APPIA.u0.bits_0.reservedAlarmC - - - - Reserved for future use - - */ - unsigned int reservedAlarmC : 1; /* 1E.CC00.1 LH */ - /* Reserved for future use - */ - /*! \brief 1E.CC00.0 LH Reserved Alarm D - AQ_GlobalAlarms_APPIA.u0.bits_0.reservedAlarmD - - - - Reserved for future use - - */ - unsigned int reservedAlarmD : 1; /* 1E.CC00.0 LH */ - /* Reserved for future use - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Alarms */ - union - { - struct - { - unsigned int reserved0 : 1; - /*! \brief 1E.CC01.E LH Smart Power-Down Entered - AQ_GlobalAlarms_APPIA.u1.bits_1.smartPower_downEntered - - - - 1 = Smart Power-Down State Entered - - - Notes: - When this bit is set, it indicates that the Smart Power-Down state was entered */ - unsigned int smartPower_downEntered : 1; /* 1E.CC01.E LH */ - /* 1 = Smart Power-Down State Entered - */ - /*! \brief 1E.CC01.D RO XENPAK Alarm - AQ_GlobalAlarms_APPIA.u1.bits_1.xenpakAlarm - - - - 1 = XENPAK Alarm - - - Notes: - This alarm is performed by H/W. */ - unsigned int xenpakAlarm : 1; /* 1E.CC01.D RO */ - /* 1 = XENPAK Alarm - */ - /*! \brief 1E.CC01.C:8 LH Reserved Alarms [4:0] - AQ_GlobalAlarms_APPIA.u1.bits_1.reservedAlarms - - - - Reserved for future use - - */ - unsigned int reservedAlarms : 5; /* 1E.CC01.C:8 LH */ - /* Reserved for future use - */ - /*! \brief 1E.CC01.7 LH MDIO Command Handling Overflow - AQ_GlobalAlarms_APPIA.u1.bits_1.mdioCommandHandlingOverflow - - - - 1 = PHY was issued more MDIO requests than it could service in it's request buffer - - - Notes: - Assertion of this bit means that more MDIO commands were issued than FW could handle. */ - unsigned int mdioCommandHandlingOverflow : 1; /* 1E.CC01.7 LH */ - /* 1 = PHY was issued more MDIO requests than it could service in it's request buffer - */ - unsigned int reserved1 : 6; - /*! \brief 1E.CC01.0 LH Diagnostic Alarm - AQ_GlobalAlarms_APPIA.u1.bits_1.diagnosticAlarm - - - - 1 = Alarm triggered by a write to 1E.C470.7 - - - Notes: - A diagnostic alarm use to test system alarm circuitry */ - unsigned int diagnosticAlarm : 1; /* 1E.CC01.0 LH */ - /* 1 = Alarm triggered by a write to 1E.C470.7 - */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global Alarms */ - union - { - struct - { - /*! \brief 1E.CC02.F LH NVR Operation Complete - AQ_GlobalAlarms_APPIA.u2.bits_2.nvrOperationComplete - - - - 1 = NVR operation is complete - - - Notes: - NVR interface is ready interrupt for registers See Global NVR Interface 1: Address 1E.100 - See Global NVR Provisioning Data MSW - Address 1E.17 . */ - unsigned int nvrOperationComplete : 1; /* 1E.CC02.F LH */ - /* 1 = NVR operation is complete - */ - /*! \brief 1E.CC02.E LH Mailbox Operation: Complete - AQ_GlobalAlarms_APPIA.u2.bits_2.mailboxOperation_Complete - - - - 1 = Mailbox operation is complete - - - Notes: - Mailbox interface is ready interrupt for registers See Global Vendor Specific Control - Address 1E.C000 - See Global Vendor Specific Provisioning 5 - Address 1E.C404 */ - unsigned int mailboxOperation_Complete : 1; /* 1E.CC02.E LH */ - /* 1 = Mailbox operation is complete - */ - unsigned int reserved0 : 3; - /*! \brief 1E.CC02.A LH uP DRAM Parity Error - AQ_GlobalAlarms_APPIA.u2.bits_2.upDramParityError - - - - 1 = Parity error detected in the uP DRAM - - */ - unsigned int upDramParityError : 1; /* 1E.CC02.A LH */ - /* 1 = Parity error detected in the uP DRAM - */ - /*! \brief 1E.CC02.9:8 LH uP IRAM Parity Error [1:0] - AQ_GlobalAlarms_APPIA.u2.bits_2.upIramParityError - - - - 1 = Parity error detected in the uP IRAM - - - Notes: - Bit 0 indicates a parity error was detected in the uP IRAM but was corrected. - Bit 1 indicates a multiple parity errors were detected in the uP IRAM and could not be corrected. - The uP IRAM is protected with ECC. */ - unsigned int upIramParityError : 2; /* 1E.CC02.9:8 LH */ - /* 1 = Parity error detected in the uP IRAM - */ - unsigned int reserved1 : 2; - /*! \brief 1E.CC02.5 LRF Tx Enable State Change - AQ_GlobalAlarms_APPIA.u2.bits_2.txEnableStateChange - - - - 1 = TX_EN pin has changed state - - */ - unsigned int txEnableStateChange : 1; /* 1E.CC02.5 LRF */ - /* 1 = TX_EN pin has changed state - */ - unsigned int reserved2 : 2; - /*! \brief 1E.CC02.2 LH MDIO MMD Error - AQ_GlobalAlarms_APPIA.u2.bits_2.mdioMMD_Error - - - - 1 = Invalid MMD address detected - - */ - unsigned int mdioMMD_Error : 1; /* 1E.CC02.2 LH */ - /* 1 = Invalid MMD address detected - */ - /*! \brief 1E.CC02.1 LH MDIO Timeout Error - AQ_GlobalAlarms_APPIA.u2.bits_2.mdioTimeoutError - - - - 1 = MDIO timeout detected - - */ - unsigned int mdioTimeoutError : 1; /* 1E.CC02.1 LH */ - /* 1 = MDIO timeout detected - */ - /*! \brief 1E.CC02.0 LH Watchdog Timer Alarm - AQ_GlobalAlarms_APPIA.u2.bits_2.watchdogTimerAlarm - - - - 1 = Watchdog timer alarm - - */ - unsigned int watchdogTimerAlarm : 1; /* 1E.CC02.0 LH */ - /* 1 = Watchdog timer alarm - */ - } bits_2; - uint16_t word_2; - } u2; -} AQ_GlobalAlarms_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Interrupt Mask: 1E.D400 */ -/* Global Interrupt Mask: 1E.D400 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Interrupt Mask */ - union - { - struct - { - unsigned int reserved0 : 1; - /*! \brief 1E.D400.E R/WPD High Temperature Failure Mask - AQ_GlobalInterruptMask_APPIA.u0.bits_0.highTemperatureFailureMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int highTemperatureFailureMask : 1; /* 1E.D400.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.D400.D R/WPD Low Temperature Failure Mask - AQ_GlobalInterruptMask_APPIA.u0.bits_0.lowTemperatureFailureMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int lowTemperatureFailureMask : 1; /* 1E.D400.D R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.D400.C R/WPD High Temperature Warning Mask - AQ_GlobalInterruptMask_APPIA.u0.bits_0.highTemperatureWarningMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int highTemperatureWarningMask : 1; /* 1E.D400.C R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.D400.B R/WPD Low Temperature Warning Mask - AQ_GlobalInterruptMask_APPIA.u0.bits_0.lowTemperatureWarningMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int lowTemperatureWarningMask : 1; /* 1E.D400.B R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - unsigned int reserved1 : 4; - /*! \brief 1E.D400.6 R/WPD Reset completed Mask - AQ_GlobalInterruptMask_APPIA.u0.bits_0.resetCompletedMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int resetCompletedMask : 1; /* 1E.D400.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - unsigned int reserved2 : 1; - /*! \brief 1E.D400.4 R/WPD Device Fault Mask - AQ_GlobalInterruptMask_APPIA.u0.bits_0.deviceFaultMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int deviceFaultMask : 1; /* 1E.D400.4 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.D400.3 R/WPD Reserved Alarm A Mask - AQ_GlobalInterruptMask_APPIA.u0.bits_0.reservedAlarmAMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int reservedAlarmAMask : 1; /* 1E.D400.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - /*! \brief 1E.D400.2 R/WPD Reserved Alarm B Mask - AQ_GlobalInterruptMask_APPIA.u0.bits_0.reservedAlarmBMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int reservedAlarmBMask : 1; /* 1E.D400.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - /*! \brief 1E.D400.1 R/WPD Reserved Alarm C Mask - AQ_GlobalInterruptMask_APPIA.u0.bits_0.reservedAlarmCMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int reservedAlarmCMask : 1; /* 1E.D400.1 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - /*! \brief 1E.D400.0 R/WPD Reserved Alarm D Mask - AQ_GlobalInterruptMask_APPIA.u0.bits_0.reservedAlarmDMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int reservedAlarmDMask : 1; /* 1E.D400.0 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Interrupt Mask */ - union - { - struct - { - unsigned int reserved0 : 1; - /*! \brief 1E.D401.E R/WPD Smart Power-Down Entered Mask - AQ_GlobalInterruptMask_APPIA.u1.bits_1.smartPower_downEnteredMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int smartPower_downEnteredMask : 1; /* 1E.D401.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - /*! \brief 1E.D401.D R/WPD XENPAK Alarm Mask - AQ_GlobalInterruptMask_APPIA.u1.bits_1.xenpakAlarmMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int xenpakAlarmMask : 1; /* 1E.D401.D R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.D401.C:8 R/WPD Reserved Alarms Mask [4:0] - AQ_GlobalInterruptMask_APPIA.u1.bits_1.reservedAlarmsMask - - Provisionable Default = 0x00 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int reservedAlarmsMask : 5; /* 1E.D401.C:8 R/WPD Provisionable Default = 0x00 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - /*! \brief 1E.D401.7 R/WPD MDIO Command Handling Overflow Mask - AQ_GlobalInterruptMask_APPIA.u1.bits_1.mdioCommandHandlingOverflowMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int mdioCommandHandlingOverflowMask : 1; /* 1E.D401.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int reserved1 : 6; - /*! \brief 1E.D401.0 R/WPD Diagnostic Alarm Mask - AQ_GlobalInterruptMask_APPIA.u1.bits_1.diagnosticAlarmMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int diagnosticAlarmMask : 1; /* 1E.D401.0 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global Interrupt Mask */ - union - { - struct - { - /*! \brief 1E.D402.F R/WPD NVR Operation Complete Mask - AQ_GlobalInterruptMask_APPIA.u2.bits_2.nvrOperationCompleteMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - Notes: - NVR interface is ready interrupt for registers See Global NVR Interface 1: Address 1E.100 - See Global NVR Provisioning Data MSW - Address 1E.17 */ - unsigned int nvrOperationCompleteMask : 1; /* 1E.D402.F R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.D402.E R/WPD Mailbox Operation Complete Mask - AQ_GlobalInterruptMask_APPIA.u2.bits_2.mailboxOperationCompleteMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - Notes: - Mailbox interface is ready interrupt for registers See Global Vendor Specific Control - Address 1E.C000 - See Global Vendor Specific Provisioning 5 - Address 1E.C404 */ - unsigned int mailboxOperationCompleteMask : 1; /* 1E.D402.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - unsigned int reserved0 : 3; - /*! \brief 1E.D402.A R/WPD uP DRAM Parity Error Mask - AQ_GlobalInterruptMask_APPIA.u2.bits_2.upDramParityErrorMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int upDramParityErrorMask : 1; /* 1E.D402.A R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - /*! \brief 1E.D402.9:8 R/WPD uP IRAM Parity Error Mask [1:0] - AQ_GlobalInterruptMask_APPIA.u2.bits_2.upIramParityErrorMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int upIramParityErrorMask : 2; /* 1E.D402.9:8 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int reserved1 : 2; - /*! \brief 1E.D402.5 R/WPD Tx Enable State Change Mask - AQ_GlobalInterruptMask_APPIA.u2.bits_2.txEnableStateChangeMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int txEnableStateChangeMask : 1; /* 1E.D402.5 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - unsigned int reserved2 : 2; - /*! \brief 1E.D402.2 R/WPD MDIO MMD Error Mask - AQ_GlobalInterruptMask_APPIA.u2.bits_2.mdioMMD_ErrorMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int mdioMMD_ErrorMask : 1; /* 1E.D402.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.D402.1 R/WPD MDIO Timeout Error Mask - AQ_GlobalInterruptMask_APPIA.u2.bits_2.mdioTimeoutErrorMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int mdioTimeoutErrorMask : 1; /* 1E.D402.1 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.D402.0 R/WPD Watchdog Timer Alarm Mask - AQ_GlobalInterruptMask_APPIA.u2.bits_2.watchdogTimerAlarmMask - - Provisionable Default = 0x1 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int watchdogTimerAlarmMask : 1; /* 1E.D402.0 R/WPD Provisionable Default = 0x1 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - } bits_2; - uint16_t word_2; - } u2; -} AQ_GlobalInterruptMask_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Chip-Wide Standard Interrupt Flags: 1E.FC00 */ -/* Global Chip-Wide Standard Interrupt Flags: 1E.FC00 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Chip-Wide Standard Interrupt Flags */ - union - { - struct - { - /*! \brief 1E.FC00.F RO PMA Standard Alarm 1 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.pmaStandardAlarm_1Interrupt - - - - 1 = Interrupt in PMA standard alarms 1 - - - Notes: - An interrupt was generated from bit 1.1.2. - An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ - unsigned int pmaStandardAlarm_1Interrupt : 1; /* 1E.FC00.F RO */ - /* 1 = Interrupt in PMA standard alarms 1 - */ - /*! \brief 1E.FC00.E RO PMA Standard Alarm 2 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.pmaStandardAlarm_2Interrupt - - - - 1 = Interrupt in PMA standard alarms 2 - - - Notes: - An interrupt was generated from either bit 1.8.B or 1.8.A. - An interrupt was generated from status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ - unsigned int pmaStandardAlarm_2Interrupt : 1; /* 1E.FC00.E RO */ - /* 1 = Interrupt in PMA standard alarms 2 - */ - /*! \brief 1E.FC00.D RO PCS Standard Alarm 1 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.pcsStandardAlarm_1Interrupt - - - - 1 = Interrupt in PCS standard alarms 1 - - - Notes: - An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ - unsigned int pcsStandardAlarm_1Interrupt : 1; /* 1E.FC00.D RO */ - /* 1 = Interrupt in PCS standard alarms 1 - */ - /*! \brief 1E.FC00.C RO PCS Standard Alarm 2 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.pcsStandardAlarm_2Interrupt - - - - 1 = Interrupt in PCS standard alarms 2 - - - Notes: - An interrupt was generated from status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ - unsigned int pcsStandardAlarm_2Interrupt : 1; /* 1E.FC00.C RO */ - /* 1 = Interrupt in PCS standard alarms 2 - */ - /*! \brief 1E.FC00.B RO PCS Standard Alarm 3 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.pcsStandardAlarm_3Interrupt - - - - 1 = Interrupt in PCS standard alarms 3 - - - Notes: - An interrupt was generated from status register ( See PCS 10GBASE-T Status 2 - Address 3.21 ) and the corresponding mask register. ( See PCS Standard Interrupt Mask 1 - Address 3.E021 ) */ - unsigned int pcsStandardAlarm_3Interrupt : 1; /* 1E.FC00.B RO */ - /* 1 = Interrupt in PCS standard alarms 3 - */ - /*! \brief 1E.FC00.A RO PHY XS Standard Alarms 1 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.phyXS_StandardAlarms_1Interrupt - - - - 1 = Interrupt in PHY XS standard alarms 1 - - - Notes: - An interrupt was generated from the status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ - unsigned int phyXS_StandardAlarms_1Interrupt : 1; /* 1E.FC00.A RO */ - /* 1 = Interrupt in PHY XS standard alarms 1 - */ - /*! \brief 1E.FC00.9 RO PHY XS Standard Alarms 2 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.phyXS_StandardAlarms_2Interrupt - - - - 1 = Interrupt in PHY XS standard alarms 2 - - - Notes: - An interrupt was generated from the status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ - unsigned int phyXS_StandardAlarms_2Interrupt : 1; /* 1E.FC00.9 RO */ - /* 1 = Interrupt in PHY XS standard alarms 2 - */ - /*! \brief 1E.FC00.8 RO Autonegotiation Standard Alarms 1 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.autonegotiationStandardAlarms_1Interrupt - - - - 1 = Interrupt in Autonegotiation standard alarms 1 - - - Notes: - An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See Autonegotiation Standard LASI Interrupt Mask 1: Address 7.D000 ) */ - unsigned int autonegotiationStandardAlarms_1Interrupt : 1; /* 1E.FC00.8 RO */ - /* 1 = Interrupt in Autonegotiation standard alarms 1 - */ - /*! \brief 1E.FC00.7 RO Autonegotiation Standard Alarms 2 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.autonegotiationStandardAlarms_2Interrupt - - - - 1 = Interrupt in Autonegotiation standard alarms 2 - - - Notes: - An interrupt was generated from status register ( See Autonegotiation 10GBASE-T Status Register - Address 7.21 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ - unsigned int autonegotiationStandardAlarms_2Interrupt : 1; /* 1E.FC00.7 RO */ - /* 1 = Interrupt in Autonegotiation standard alarms 2 - */ - /*! \brief 1E.FC00.6 RO GbE Standard Alarms Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.gbeStandardAlarmsInterrupt - - - - 1 = Interrupt in GbE standard alarms - - - Notes: - An interrupt was generated from the TGE core. */ - unsigned int gbeStandardAlarmsInterrupt : 1; /* 1E.FC00.6 RO */ - /* 1 = Interrupt in GbE standard alarms - */ - unsigned int reserved0 : 5; - /*! \brief 1E.FC00.0 RO All Vendor Alarms Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_APPIA.u0.bits_0.allVendorAlarmsInterrupt - - - - 1 = Interrupt in all vendor alarms - - - Notes: - An interrupt was generated from status register ( See Global Chip-Wide LASI Vendor Interrupt Flags: Address 1E.FC01 ) and the corresponding mask register. ( See Global Interrupt LASI Mask: Address 1E.FF01 ) */ - unsigned int allVendorAlarmsInterrupt : 1; /* 1E.FC00.0 RO */ - /* 1 = Interrupt in all vendor alarms - */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalChip_wideStandardInterruptFlags_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Chip-Wide Vendor Interrupt Flags: 1E.FC01 */ -/* Global Chip-Wide Vendor Interrupt Flags: 1E.FC01 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Chip-Wide Vendor Interrupt Flags */ - union - { - struct - { - /*! \brief 1E.FC01.F RO PMA Vendor Alarm Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.pmaVendorAlarmInterrupt - - - - 1 = Interrupt in PMA vendor specific alarm - - - Notes: - A PMA alarm was generated. ( See PHY XS Vendor Global Interrupt Flags 1- Address 4.F800 ) */ - unsigned int pmaVendorAlarmInterrupt : 1; /* 1E.FC01.F RO */ - /* 1 = Interrupt in PMA vendor specific alarm - */ - /*! \brief 1E.FC01.E RO PCS Vendor Alarm Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.pcsVendorAlarmInterrupt - - - - 1 = Interrupt in PCS vendor specific alarm - - - Notes: - A PCS alarm was generated. ( See PHY XS Vendor Global Interrupt Flags 1- Address 4.F800 ) */ - unsigned int pcsVendorAlarmInterrupt : 1; /* 1E.FC01.E RO */ - /* 1 = Interrupt in PCS vendor specific alarm - */ - /*! \brief 1E.FC01.D RO PHY XS Vendor Alarm Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.phyXS_VendorAlarmInterrupt - - - - 1 = Interrupt in PHY XS vendor specific alarm - - - Notes: - A PHY XS alarm was generated. ( See PHY XS Vendor Global LASI Interrupt Flags 1: Address 4.FC00 ) */ - unsigned int phyXS_VendorAlarmInterrupt : 1; /* 1E.FC01.D RO */ - /* 1 = Interrupt in PHY XS vendor specific alarm - */ - /*! \brief 1E.FC01.C RO Autonegotiation Vendor Alarm Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.autonegotiationVendorAlarmInterrupt - - - - 1 = Interrupt in Autonegotiation vendor specific alarm - - - Notes: - An Autonegotiation alarm was generated. ( See Autonegotiation Vendor Global LASI Interrupt Flags 1: Address 7.FC00 ) */ - unsigned int autonegotiationVendorAlarmInterrupt : 1; /* 1E.FC01.C RO */ - /* 1 = Interrupt in Autonegotiation vendor specific alarm - */ - /*! \brief 1E.FC01.B RO GbE Vendor Alarm Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.gbeVendorAlarmInterrupt - - - - 1 = Interrupt in GbE vendor specific alarm - - - Notes: - A GbE alarm was generated. ( See GbE PHY Vendor Global LASI Interrupt Flags 1: Address 1D.FC00 ) */ - unsigned int gbeVendorAlarmInterrupt : 1; /* 1E.FC01.B RO */ - /* 1 = Interrupt in GbE vendor specific alarm - */ - unsigned int reserved0 : 8; - /*! \brief 1E.FC01.2 RO Global Alarms 1 Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.globalAlarms_1Interrupt - - - - 1 = Interrupt in Global alarms 1 - - - Notes: - An interrupt was generated from status register ( See Global Vendor Alarms 1 - Address 1E.CC00 ) and the corresponding mask register. ( See Global Vendor Interrupt Mask - Address 1E.D400 ) */ - unsigned int globalAlarms_1Interrupt : 1; /* 1E.FC01.2 RO */ - /* 1 = Interrupt in Global alarms 1 - */ - /*! \brief 1E.FC01.1 RO Global Alarms 2 Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.globalAlarms_2Interrupt - - - - 1 = Interrupt in Global alarms 2 - - - Notes: - An interrupt was generated from status register ( See Global Alarms 2: Address 1E.CC01 ) and the corresponding mask register. ( See Global LASI Interrupt Mask 2: Address 1E.D401 ) */ - unsigned int globalAlarms_2Interrupt : 1; /* 1E.FC01.1 RO */ - /* 1 = Interrupt in Global alarms 2 - */ - /*! \brief 1E.FC01.0 RO Global Alarms 3 Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_APPIA.u0.bits_0.globalAlarms_3Interrupt - - - - 1 = Interrupt in Global alarms 3 - - - Notes: - An interrupt was generated from status register ( See Global Vendor Alarms 2: Address 1E.CC01 ) and the corresponding mask register. ( See Global LASI Interrupt Mask 2: Address 1E.D401 ) */ - unsigned int globalAlarms_3Interrupt : 1; /* 1E.FC01.0 RO */ - /* 1 = Interrupt in Global alarms 3 - */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalChip_wideVendorInterruptFlags_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Interrupt Chip-Wide Standard Mask: 1E.FF00 */ -/* Global Interrupt Chip-Wide Standard Mask: 1E.FF00 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Interrupt Chip-Wide Standard Mask */ - union - { - struct - { - /*! \brief 1E.FF00.F R/WPD PMA Standard Alarm 1 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.pmaStandardAlarm_1InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int pmaStandardAlarm_1InterruptMask : 1; /* 1E.FF00.F R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.E R/WPD PMA Standard Alarm 2 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.pmaStandardAlarm_2InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int pmaStandardAlarm_2InterruptMask : 1; /* 1E.FF00.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.D R/WPD PCS Standard Alarm 1 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.pcsStandardAlarm_1InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int pcsStandardAlarm_1InterruptMask : 1; /* 1E.FF00.D R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.C R/WPD PCS Standard Alarm 2 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.pcsStandardAlarm_2InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int pcsStandardAlarm_2InterruptMask : 1; /* 1E.FF00.C R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.B R/WPD PCS Standard Alarm 3 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.pcsStandardAlarm_3InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int pcsStandardAlarm_3InterruptMask : 1; /* 1E.FF00.B R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.A R/WPD PHY XS Standard Alarms 1 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.phyXS_StandardAlarms_1InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int phyXS_StandardAlarms_1InterruptMask : 1; /* 1E.FF00.A R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.9 R/WPD PHY XS Standard Alarms 2 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.phyXS_StandardAlarms_2InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int phyXS_StandardAlarms_2InterruptMask : 1; /* 1E.FF00.9 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.8 R/WPD Autonegotiation Standard Alarms 1 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.autonegotiationStandardAlarms_1InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int autonegotiationStandardAlarms_1InterruptMask : 1; /* 1E.FF00.8 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.7 R/WPD Autonegotiation Standard Alarms 2 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.autonegotiationStandardAlarms_2InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int autonegotiationStandardAlarms_2InterruptMask : 1; /* 1E.FF00.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.6 R/WPD Gbe Standard Alarms Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.gbeStandardAlarmsInterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int gbeStandardAlarmsInterruptMask : 1; /* 1E.FF00.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - unsigned int reserved0 : 5; - /*! \brief 1E.FF00.0 R/WPD All Vendor Alarms Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_APPIA.u0.bits_0.allVendorAlarmsInterruptMask - - Provisionable Default = 0x1 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int allVendorAlarmsInterruptMask : 1; /* 1E.FF00.0 R/WPD Provisionable Default = 0x1 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalInterruptChip_wideStandardMask_APPIA; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Interrupt Chip-Wide Vendor Mask: 1E.FF01 */ -/* Global Interrupt Chip-Wide Vendor Mask: 1E.FF01 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Interrupt Chip-Wide Vendor Mask */ - union - { - struct - { - /*! \brief 1E.FF01.F R/WPD PMA Vendor Alarm Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.pmaVendorAlarmInterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int pmaVendorAlarmInterruptMask : 1; /* 1E.FF01.F R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF01.E R/WPD PCS Vendor Alarm Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.pcsVendorAlarmInterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int pcsVendorAlarmInterruptMask : 1; /* 1E.FF01.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF01.D R/WPD PHY XS Vendor Alarm Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.phyXS_VendorAlarmInterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int phyXS_VendorAlarmInterruptMask : 1; /* 1E.FF01.D R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF01.C R/WPD Autonegotiation Vendor Alarm Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.autonegotiationVendorAlarmInterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int autonegotiationVendorAlarmInterruptMask : 1; /* 1E.FF01.C R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF01.B R/WPD GbE Vendor Alarm Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.gbeVendorAlarmInterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int gbeVendorAlarmInterruptMask : 1; /* 1E.FF01.B R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - unsigned int reserved0 : 8; - /*! \brief 1E.FF01.2 R/WPD Global Alarms 1 Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.globalAlarms_1InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int globalAlarms_1InterruptMask : 1; /* 1E.FF01.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF01.1 R/WPD Global Alarms 2 Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.globalAlarms_2InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int globalAlarms_2InterruptMask : 1; /* 1E.FF01.1 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF01.0 R/WPD Global Alarms 3 Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_APPIA.u0.bits_0.globalAlarms_3InterruptMask - - Provisionable Default = 0x1 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int globalAlarms_3InterruptMask : 1; /* 1E.FF01.0 R/WPD Provisionable Default = 0x1 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalInterruptChip_wideVendorMask_APPIA; - -#endif -/*@}*/ -/*@}*/ diff --git a/qca/aq-fw-download/src/include/registerMap/AQ_RegGroupMaxSizes.h b/qca/aq-fw-download/src/include/registerMap/AQ_RegGroupMaxSizes.h deleted file mode 100644 index 08e255860..000000000 --- a/qca/aq-fw-download/src/include/registerMap/AQ_RegGroupMaxSizes.h +++ /dev/null @@ -1,387 +0,0 @@ -/* Copyright (c) 2015, Aquantia -* -* Permission to use, copy, modify, and/or distribute this software for any -* purpose with or without fee is hereby granted, provided that the above -* copyright notice and this permission notice appear in all copies. -* -* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -*/ -#ifndef AQ_REG_GROUP_MAX_SIZES -#define AQ_REG_GROUP_MAX_SIZES - -#define AQ_Autonegotiation10GBaseT_ControlRegister_BiggestVersion AQ_Autonegotiation10GBaseT_ControlRegister_HHD -#define AQ_Autonegotiation10GBaseT_StatusRegister_BiggestVersion AQ_Autonegotiation10GBaseT_StatusRegister_HHD -#define AQ_AutonegotiationAdvertisementRegister_BiggestVersion AQ_AutonegotiationAdvertisementRegister_HHD -#define AQ_AutonegotiationEeeAdvertisementRegister_BiggestVersion AQ_AutonegotiationEeeAdvertisementRegister_HHD -#define AQ_AutonegotiationEeeLinkPartnerAbilityRegister_BiggestVersion AQ_AutonegotiationEeeLinkPartnerAbilityRegister_HHD -#define AQ_AutonegotiationExtendedNextPageTransmitRegister_BiggestVersion AQ_AutonegotiationExtendedNextPageTransmitRegister_HHD -#define AQ_AutonegotiationExtendedNextPageUnformattedCodeRegister_BiggestVersion AQ_AutonegotiationExtendedNextPageUnformattedCodeRegister_HHD -#define AQ_AutonegotiationLinkPartnerBasePageAbilityRegister_BiggestVersion AQ_AutonegotiationLinkPartnerBasePageAbilityRegister_HHD -#define AQ_AutonegotiationLinkPartnerExtendedNextPageAbilityRegister_BiggestVersion AQ_AutonegotiationLinkPartnerExtendedNextPageAbilityRegister_HHD -#define AQ_AutonegotiationLinkPartnerExtendedNextPageUnformattedCodeRegister_BiggestVersion AQ_AutonegotiationLinkPartnerExtendedNextPageUnformattedCodeRegister_HHD -#define AQ_AutonegotiationReceiveLinkPartnerStatus_BiggestVersion AQ_AutonegotiationReceiveLinkPartnerStatus_HHD -#define AQ_AutonegotiationReceiveReservedVendorProvisioning_BiggestVersion AQ_AutonegotiationReceiveReservedVendorProvisioning_APPIA -#define AQ_AutonegotiationReceiveReservedVendorStatus_BiggestVersion AQ_AutonegotiationReceiveReservedVendorStatus_HHD -#define AQ_AutonegotiationReceiveVendorAlarms_BiggestVersion AQ_AutonegotiationReceiveVendorAlarms_HHD -#define AQ_AutonegotiationReceiveVendorInterruptMask_BiggestVersion AQ_AutonegotiationReceiveVendorInterruptMask_HHD -#define AQ_AutonegotiationReservedVendorProvisioning_BiggestVersion AQ_AutonegotiationReservedVendorProvisioning_HHD -#define AQ_AutonegotiationReservedVendorStatus_BiggestVersion AQ_AutonegotiationReservedVendorStatus_HHD -#define AQ_AutonegotiationStandardControl_1_BiggestVersion AQ_AutonegotiationStandardControl_1_HHD -#define AQ_AutonegotiationStandardDeviceIdentifier_BiggestVersion AQ_AutonegotiationStandardDeviceIdentifier_HHD -#define AQ_AutonegotiationStandardDevicesInPackage_BiggestVersion AQ_AutonegotiationStandardDevicesInPackage_HHD -#define AQ_AutonegotiationStandardInterruptMask_BiggestVersion AQ_AutonegotiationStandardInterruptMask_HHD -#define AQ_AutonegotiationStandardPackageIdentifier_BiggestVersion AQ_AutonegotiationStandardPackageIdentifier_HHD -#define AQ_AutonegotiationStandardStatus_1_BiggestVersion AQ_AutonegotiationStandardStatus_1_HHD -#define AQ_AutonegotiationStandardStatus_2_BiggestVersion AQ_AutonegotiationStandardStatus_2_HHD -#define AQ_AutonegotiationTransmitVendorAlarms_BiggestVersion AQ_AutonegotiationTransmitVendorAlarms_APPIA -#define AQ_AutonegotiationTransmitVendorInterruptMask_BiggestVersion AQ_AutonegotiationTransmitVendorInterruptMask_HHD -#define AQ_AutonegotiationVendorGlobalInterruptFlags_BiggestVersion AQ_AutonegotiationVendorGlobalInterruptFlags_HHD -#define AQ_AutonegotiationVendorProvisioning_BiggestVersion AQ_AutonegotiationVendorProvisioning_HHD -#define AQ_AutonegotiationVendorStatus_BiggestVersion AQ_AutonegotiationVendorStatus_HHD -#define AQ_GbePhyExtendedWolControl_BiggestVersion AQ_GbePhyExtendedWolControl_HHD -#define AQ_GbePhySgmii0RxStatus_BiggestVersion AQ_GbePhySgmii0RxStatus_HHD -#define AQ_GbePhySgmii0TxStatus_BiggestVersion AQ_GbePhySgmii0TxStatus_HHD -#define AQ_GbePhySgmii1RxStatus_BiggestVersion AQ_GbePhySgmii1RxStatus_HHD -#define AQ_GbePhySgmii1TxStatus_BiggestVersion AQ_GbePhySgmii1TxStatus_HHD -#define AQ_GbePhySgmii1WolStatus_BiggestVersion AQ_GbePhySgmii1WolStatus_HHD -#define AQ_GbePhySgmiiRxAlarms_BiggestVersion AQ_GbePhySgmiiRxAlarms_HHD -#define AQ_GbePhySgmiiRxInterruptMask_BiggestVersion AQ_GbePhySgmiiRxInterruptMask_HHD -#define AQ_GbePhySgmiiTestControl_BiggestVersion AQ_GbePhySgmiiTestControl_HHD -#define AQ_GbePhySgmiiTxAlarms_BiggestVersion AQ_GbePhySgmiiTxAlarms_HHD -#define AQ_GbePhySgmiiTxInterruptMask_BiggestVersion AQ_GbePhySgmiiTxInterruptMask_HHD -#define AQ_GbePhySgmiiWolStatus_BiggestVersion AQ_GbePhySgmiiWolStatus_HHD -#define AQ_GbePhyVendorGlobalInterruptFlags_BiggestVersion AQ_GbePhyVendorGlobalInterruptFlags_HHD -#define AQ_GbePhyWolControl_BiggestVersion AQ_GbePhyWolControl_HHD -#define AQ_GbePhysgmii1WolStatus_BiggestVersion AQ_GbePhysgmii1WolStatus_APPIA -#define AQ_GbeReservedProvisioning_BiggestVersion AQ_GbeReservedProvisioning_HHD -#define AQ_GbeStandardDeviceIdentifier_BiggestVersion AQ_GbeStandardDeviceIdentifier_HHD -#define AQ_GbeStandardDevicesInPackage_BiggestVersion AQ_GbeStandardDevicesInPackage_HHD -#define AQ_GbeStandardPackageIdentifier_BiggestVersion AQ_GbeStandardPackageIdentifier_HHD -#define AQ_GbeStandardStatus_2_BiggestVersion AQ_GbeStandardStatus_2_HHD -#define AQ_GbeStandardVendorDevicesInPackage_BiggestVersion AQ_GbeStandardVendorDevicesInPackage_HHD -#define AQ_GlobalAlarms_BiggestVersion AQ_GlobalAlarms_HHD -#define AQ_GlobalCableDiagnosticImpedance_BiggestVersion AQ_GlobalCableDiagnosticImpedance_HHD -#define AQ_GlobalCableDiagnosticStatus_BiggestVersion AQ_GlobalCableDiagnosticStatus_APPIA -#define AQ_GlobalChipIdentification_BiggestVersion AQ_GlobalChipIdentification_APPIA -#define AQ_GlobalChipRevision_BiggestVersion AQ_GlobalChipRevision_APPIA -#define AQ_GlobalChip_wideStandardInterruptFlags_BiggestVersion AQ_GlobalChip_wideStandardInterruptFlags_HHD -#define AQ_GlobalChip_wideVendorInterruptFlags_BiggestVersion AQ_GlobalChip_wideVendorInterruptFlags_HHD -#define AQ_GlobalControl_BiggestVersion AQ_GlobalControl_HHD -#define AQ_GlobalDaisyChainStatus_BiggestVersion AQ_GlobalDaisyChainStatus_HHD -#define AQ_GlobalDiagnosticProvisioning_BiggestVersion AQ_GlobalDiagnosticProvisioning_HHD -#define AQ_GlobalEeeProvisioning_BiggestVersion AQ_GlobalEeeProvisioning_HHD -#define AQ_GlobalFaultMessage_BiggestVersion AQ_GlobalFaultMessage_HHD -#define AQ_GlobalFirmwareID_BiggestVersion AQ_GlobalFirmwareID_HHD -#define AQ_GlobalGeneralProvisioning_BiggestVersion AQ_GlobalGeneralProvisioning_HHD -#define AQ_GlobalGeneralStatus_BiggestVersion AQ_GlobalGeneralStatus_HHD -#define AQ_GlobalInterruptChip_wideStandardMask_BiggestVersion AQ_GlobalInterruptChip_wideStandardMask_HHD -#define AQ_GlobalInterruptChip_wideVendorMask_BiggestVersion AQ_GlobalInterruptChip_wideVendorMask_HHD -#define AQ_GlobalInterruptMask_BiggestVersion AQ_GlobalInterruptMask_HHD -#define AQ_GlobalLedProvisioning_BiggestVersion AQ_GlobalLedProvisioning_HHD -#define AQ_GlobalMailboxInterface_BiggestVersion AQ_GlobalMailboxInterface_HHD -#define AQ_GlobalMicroprocessorScratchPad_BiggestVersion AQ_GlobalMicroprocessorScratchPad_HHD -#define AQ_GlobalNvrInterface_BiggestVersion AQ_GlobalNvrInterface_HHD -#define AQ_GlobalNvrProvisioning_BiggestVersion AQ_GlobalNvrProvisioning_HHD -#define AQ_GlobalPinStatus_BiggestVersion AQ_GlobalPinStatus_HHD -#define AQ_GlobalPrimaryStatus_BiggestVersion AQ_GlobalPrimaryStatus_APPIA -#define AQ_GlobalReservedProvisioning_BiggestVersion AQ_GlobalReservedProvisioning_HHD -#define AQ_GlobalReservedStatus_BiggestVersion AQ_GlobalReservedStatus_HHD -#define AQ_GlobalResetControl_BiggestVersion AQ_GlobalResetControl_HHD -#define AQ_GlobalSmbus_0Provisioning_BiggestVersion AQ_GlobalSmbus_0Provisioning_HHD -#define AQ_GlobalSmbus_1Provisioning_BiggestVersion AQ_GlobalSmbus_1Provisioning_HHD -#define AQ_GlobalStandardControl_1_BiggestVersion AQ_GlobalStandardControl_1_HHD -#define AQ_GlobalStandardDeviceIdentifier_BiggestVersion AQ_GlobalStandardDeviceIdentifier_HHD -#define AQ_GlobalStandardDevicesInPackage_BiggestVersion AQ_GlobalStandardDevicesInPackage_HHD -#define AQ_GlobalStandardPackageIdentifier_BiggestVersion AQ_GlobalStandardPackageIdentifier_HHD -#define AQ_GlobalStandardStatus_2_BiggestVersion AQ_GlobalStandardStatus_2_HHD -#define AQ_GlobalStandardVendorDevicesInPackage_BiggestVersion AQ_GlobalStandardVendorDevicesInPackage_HHD -#define AQ_GlobalStatus_BiggestVersion AQ_GlobalStatus_HHD -#define AQ_GlobalThermalProvisioning_BiggestVersion AQ_GlobalThermalProvisioning_HHD -#define AQ_GlobalThermalStatus_BiggestVersion AQ_GlobalThermalStatus_HHD -#define AQ_Kr0AutonegotiationAdvertisementWord_BiggestVersion AQ_Kr0AutonegotiationAdvertisementWord_HHD -#define AQ_Kr0AutonegotiationControl_BiggestVersion AQ_Kr0AutonegotiationControl_HHD -#define AQ_Kr0AutonegotiationExtendedNextPageAdvertisementWord_BiggestVersion AQ_Kr0AutonegotiationExtendedNextPageAdvertisementWord_HHD -#define AQ_Kr0AutonegotiationStatus_BiggestVersion AQ_Kr0AutonegotiationStatus_HHD -#define AQ_Kr0LinkPartnerAutonegotiationAdvertisementWord_BiggestVersion AQ_Kr0LinkPartnerAutonegotiationAdvertisementWord_HHD -#define AQ_Kr0LinkPartnerAutonegotiationExtendedNextPageAdvertisementWord_BiggestVersion AQ_Kr0LinkPartnerAutonegotiationExtendedNextPageAdvertisementWord_HHD -#define AQ_Kr1AutonegotiationAdvertisementWord_BiggestVersion AQ_Kr1AutonegotiationAdvertisementWord_HHD -#define AQ_Kr1AutonegotiationControl_BiggestVersion AQ_Kr1AutonegotiationControl_HHD -#define AQ_Kr1AutonegotiationExtendedNextPageAdvertisementWord_BiggestVersion AQ_Kr1AutonegotiationExtendedNextPageAdvertisementWord_HHD -#define AQ_Kr1AutonegotiationStatus_BiggestVersion AQ_Kr1AutonegotiationStatus_HHD -#define AQ_Kr1LinkPartnerAutonegotiationAdvertisementWord_BiggestVersion AQ_Kr1LinkPartnerAutonegotiationAdvertisementWord_HHD -#define AQ_Kr1LinkPartnerAutonegotiationExtendedNextPageAdvertisementWord_BiggestVersion AQ_Kr1LinkPartnerAutonegotiationExtendedNextPageAdvertisementWord_HHD -#define AQ_MsmLineFifoControlRegister_BiggestVersion AQ_MsmLineFifoControlRegister_HHD -#define AQ_MsmLineGeneralControlRegister_BiggestVersion AQ_MsmLineGeneralControlRegister_HHD -#define AQ_MsmLineGeneralStatusRegister_BiggestVersion AQ_MsmLineGeneralStatusRegister_HHD -#define AQ_MsmLineRxAlignmentErrorsCounterRegister_BiggestVersion AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD -#define AQ_MsmLineRxBroadcastFramesCounterRegister_BiggestVersion AQ_MsmLineRxBroadcastFramesCounterRegister_HHD -#define AQ_MsmLineRxErrorsCounterRegister_BiggestVersion AQ_MsmLineRxErrorsCounterRegister_HHD -#define AQ_MsmLineRxFcsErrorsCounterRegister_BiggestVersion AQ_MsmLineRxFcsErrorsCounterRegister_HHD -#define AQ_MsmLineRxGoodFramesCounterRegister_BiggestVersion AQ_MsmLineRxGoodFramesCounterRegister_HHD -#define AQ_MsmLineRxInRangeLengthErrorsCounterRegister_BiggestVersion AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD -#define AQ_MsmLineRxMulticastFramesCounterRegister_BiggestVersion AQ_MsmLineRxMulticastFramesCounterRegister_HHD -#define AQ_MsmLineRxOctetsCounterRegister_BiggestVersion AQ_MsmLineRxOctetsCounterRegister_HHD -#define AQ_MsmLineRxPauseFramesCounterRegister_BiggestVersion AQ_MsmLineRxPauseFramesCounterRegister_HHD -#define AQ_MsmLineRxTooLongErrorsCounterRegister_BiggestVersion AQ_MsmLineRxTooLongErrorsCounterRegister_HHD -#define AQ_MsmLineRxUnicastFramesCounterRegister_BiggestVersion AQ_MsmLineRxUnicastFramesCounterRegister_HHD -#define AQ_MsmLineRxVlanFramesCounterRegister_BiggestVersion AQ_MsmLineRxVlanFramesCounterRegister_HHD -#define AQ_MsmLineTxBroadcastFramesCounterRegister_BiggestVersion AQ_MsmLineTxBroadcastFramesCounterRegister_HHD -#define AQ_MsmLineTxErrorsCounterRegister_BiggestVersion AQ_MsmLineTxErrorsCounterRegister_HHD -#define AQ_MsmLineTxGoodFramesCounterRegister_BiggestVersion AQ_MsmLineTxGoodFramesCounterRegister_HHD -#define AQ_MsmLineTxIpgControlRegister_BiggestVersion AQ_MsmLineTxIpgControlRegister_HHD -#define AQ_MsmLineTxMulticastFramesCounterRegister_BiggestVersion AQ_MsmLineTxMulticastFramesCounterRegister_HHD -#define AQ_MsmLineTxOctetsCounterRegister_BiggestVersion AQ_MsmLineTxOctetsCounterRegister_HHD -#define AQ_MsmLineTxPauseFramesCounterRegister_BiggestVersion AQ_MsmLineTxPauseFramesCounterRegister_HHD -#define AQ_MsmLineTxUnicastFramesCounterRegister_BiggestVersion AQ_MsmLineTxUnicastFramesCounterRegister_HHD -#define AQ_MsmLineTxVlanFramesCounterRegister_BiggestVersion AQ_MsmLineTxVlanFramesCounterRegister_HHD -#define AQ_MsmSystemFifoControlRegister_BiggestVersion AQ_MsmSystemFifoControlRegister_HHD -#define AQ_MsmSystemGeneralControlRegister_BiggestVersion AQ_MsmSystemGeneralControlRegister_HHD -#define AQ_MsmSystemGeneralStatusRegister_BiggestVersion AQ_MsmSystemGeneralStatusRegister_HHD -#define AQ_MsmSystemRxAlignmentErrorsCounterRegister_BiggestVersion AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD -#define AQ_MsmSystemRxBroadcastFramesCounterRegister_BiggestVersion AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD -#define AQ_MsmSystemRxErrorsCounterRegister_BiggestVersion AQ_MsmSystemRxErrorsCounterRegister_HHD -#define AQ_MsmSystemRxFcsErrorsCounterRegister_BiggestVersion AQ_MsmSystemRxFcsErrorsCounterRegister_HHD -#define AQ_MsmSystemRxGoodFramesCounterRegister_BiggestVersion AQ_MsmSystemRxGoodFramesCounterRegister_HHD -#define AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_BiggestVersion AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD -#define AQ_MsmSystemRxMulticastFramesCounterRegister_BiggestVersion AQ_MsmSystemRxMulticastFramesCounterRegister_HHD -#define AQ_MsmSystemRxOctetsCounterRegister_BiggestVersion AQ_MsmSystemRxOctetsCounterRegister_HHD -#define AQ_MsmSystemRxPauseFramesCounterRegister_BiggestVersion AQ_MsmSystemRxPauseFramesCounterRegister_HHD -#define AQ_MsmSystemRxTooLongErrorsCounterRegister_BiggestVersion AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD -#define AQ_MsmSystemRxUnicastFramesCounterRegister_BiggestVersion AQ_MsmSystemRxUnicastFramesCounterRegister_HHD -#define AQ_MsmSystemRxVlanFramesCounterRegister_BiggestVersion AQ_MsmSystemRxVlanFramesCounterRegister_HHD -#define AQ_MsmSystemTxBroadcastFramesCounterRegister_BiggestVersion AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD -#define AQ_MsmSystemTxErrorsCounterRegister_BiggestVersion AQ_MsmSystemTxErrorsCounterRegister_HHD -#define AQ_MsmSystemTxGoodFramesCounterRegister_BiggestVersion AQ_MsmSystemTxGoodFramesCounterRegister_HHD -#define AQ_MsmSystemTxIpgControlRegister_BiggestVersion AQ_MsmSystemTxIpgControlRegister_HHD -#define AQ_MsmSystemTxMulticastFramesCounterRegister_BiggestVersion AQ_MsmSystemTxMulticastFramesCounterRegister_HHD -#define AQ_MsmSystemTxOctetsCounterRegister_BiggestVersion AQ_MsmSystemTxOctetsCounterRegister_HHD -#define AQ_MsmSystemTxPauseFramesCounterRegister_BiggestVersion AQ_MsmSystemTxPauseFramesCounterRegister_HHD -#define AQ_MsmSystemTxUnicastFramesCounterRegister_BiggestVersion AQ_MsmSystemTxUnicastFramesCounterRegister_HHD -#define AQ_MsmSystemTxVlanFramesCounterRegister_BiggestVersion AQ_MsmSystemTxVlanFramesCounterRegister_HHD -#define AQ_MssEgressControlRegister_BiggestVersion AQ_MssEgressControlRegister_HHD -#define AQ_MssEgressEccInterruptStatusRegister_BiggestVersion AQ_MssEgressEccInterruptStatusRegister_HHD -#define AQ_MssEgressInterruptMaskRegister_BiggestVersion AQ_MssEgressInterruptMaskRegister_HHD -#define AQ_MssEgressInterruptStatusRegister_BiggestVersion AQ_MssEgressInterruptStatusRegister_HHD -#define AQ_MssEgressLutAddressControlRegister_BiggestVersion AQ_MssEgressLutAddressControlRegister_HHD -#define AQ_MssEgressLutControlRegister_BiggestVersion AQ_MssEgressLutControlRegister_HHD -#define AQ_MssEgressLutDataControlRegister_BiggestVersion AQ_MssEgressLutDataControlRegister_HHD -#define AQ_MssEgressMtuSizeControlRegister_BiggestVersion AQ_MssEgressMtuSizeControlRegister_HHD -#define AQ_MssEgressPnControlRegister_BiggestVersion AQ_MssEgressPnControlRegister_HHD -#define AQ_MssEgressSaExpiredStatusRegister_BiggestVersion AQ_MssEgressSaExpiredStatusRegister_HHD -#define AQ_MssEgressSaThresholdExpiredStatusRegister_BiggestVersion AQ_MssEgressSaThresholdExpiredStatusRegister_HHD -#define AQ_MssEgressVlanControlRegister_BiggestVersion AQ_MssEgressVlanControlRegister_HHD -#define AQ_MssEgressVlanTpid_0Register_BiggestVersion AQ_MssEgressVlanTpid_0Register_HHD -#define AQ_MssEgressVlanTpid_1Register_BiggestVersion AQ_MssEgressVlanTpid_1Register_HHD -#define AQ_MssIngressControlRegister_BiggestVersion AQ_MssIngressControlRegister_HHD -#define AQ_MssIngressEccInterruptStatusRegister_BiggestVersion AQ_MssIngressEccInterruptStatusRegister_HHD -#define AQ_MssIngressInterruptMaskRegister_BiggestVersion AQ_MssIngressInterruptMaskRegister_HHD -#define AQ_MssIngressInterruptStatusRegister_BiggestVersion AQ_MssIngressInterruptStatusRegister_HHD -#define AQ_MssIngressLutAddressControlRegister_BiggestVersion AQ_MssIngressLutAddressControlRegister_HHD -#define AQ_MssIngressLutControlRegister_BiggestVersion AQ_MssIngressLutControlRegister_HHD -#define AQ_MssIngressLutDataControlRegister_BiggestVersion AQ_MssIngressLutDataControlRegister_HHD -#define AQ_MssIngressMtuSizeControlRegister_BiggestVersion AQ_MssIngressMtuSizeControlRegister_HHD -#define AQ_MssIngressSaControlRegister_BiggestVersion AQ_MssIngressSaControlRegister_HHD -#define AQ_MssIngressSaExpiredStatusRegister_BiggestVersion AQ_MssIngressSaExpiredStatusRegister_HHD -#define AQ_MssIngressSaIcvErrorStatusRegister_BiggestVersion AQ_MssIngressSaIcvErrorStatusRegister_HHD -#define AQ_MssIngressSaReplayErrorStatusRegister_BiggestVersion AQ_MssIngressSaReplayErrorStatusRegister_HHD -#define AQ_MssIngressSaThresholdExpiredStatusRegister_BiggestVersion AQ_MssIngressSaThresholdExpiredStatusRegister_HHD -#define AQ_MssIngressVlanControlRegister_BiggestVersion AQ_MssIngressVlanControlRegister_HHD -#define AQ_MssIngressVlanTpid_0Register_BiggestVersion AQ_MssIngressVlanTpid_0Register_HHD -#define AQ_MssIngressVlanTpid_1Register_BiggestVersion AQ_MssIngressVlanTpid_1Register_HHD -#define AQ_Pcs10GBaseT_Status_BiggestVersion AQ_Pcs10GBaseT_Status_APPIA -#define AQ_Pcs10G_Status_BiggestVersion AQ_Pcs10G_Status_HHD -#define AQ_Pcs10G_base_rPcsTest_patternControl_BiggestVersion AQ_Pcs10G_base_rPcsTest_patternControl_HHD -#define AQ_Pcs10G_base_rPcsTest_patternErrorCounter_BiggestVersion AQ_Pcs10G_base_rPcsTest_patternErrorCounter_HHD -#define AQ_Pcs10G_base_rTestPatternSeedA_BiggestVersion AQ_Pcs10G_base_rTestPatternSeedA_HHD -#define AQ_Pcs10G_base_rTestPatternSeedB_BiggestVersion AQ_Pcs10G_base_rTestPatternSeedB_HHD -#define AQ_PcsEeeCapabilityRegister_BiggestVersion AQ_PcsEeeCapabilityRegister_HHD -#define AQ_PcsEeeWakeErrorCounter_BiggestVersion AQ_PcsEeeWakeErrorCounter_HHD -#define AQ_PcsReceiveStandardInterruptMask_BiggestVersion AQ_PcsReceiveStandardInterruptMask_APPIA -#define AQ_PcsReceiveVendorAlarms_BiggestVersion AQ_PcsReceiveVendorAlarms_HHD -#define AQ_PcsReceiveVendorCorrectedFrame_1IterationCounter_BiggestVersion AQ_PcsReceiveVendorCorrectedFrame_1IterationCounter_HHD -#define AQ_PcsReceiveVendorCorrectedFrame_2IterationCounter_BiggestVersion AQ_PcsReceiveVendorCorrectedFrame_2IterationCounter_HHD -#define AQ_PcsReceiveVendorCorrectedFrame_3IterationCounter_BiggestVersion AQ_PcsReceiveVendorCorrectedFrame_3IterationCounter_HHD -#define AQ_PcsReceiveVendorCorrectedFrame_4IterationCounter_BiggestVersion AQ_PcsReceiveVendorCorrectedFrame_4IterationCounter_HHD -#define AQ_PcsReceiveVendorCorrectedFrame_5IterationCounter_BiggestVersion AQ_PcsReceiveVendorCorrectedFrame_5IterationCounter_HHD -#define AQ_PcsReceiveVendorCorrectedFrame_6IterationCounter_BiggestVersion AQ_PcsReceiveVendorCorrectedFrame_6IterationCounter_HHD -#define AQ_PcsReceiveVendorCorrectedFrame_7IterationCounter_BiggestVersion AQ_PcsReceiveVendorCorrectedFrame_7IterationCounter_HHD -#define AQ_PcsReceiveVendorCorrectedFrame_8IterationCounter_BiggestVersion AQ_PcsReceiveVendorCorrectedFrame_8IterationCounter_HHD -#define AQ_PcsReceiveVendorCrc_8ErrorCounter_BiggestVersion AQ_PcsReceiveVendorCrc_8ErrorCounter_HHD -#define AQ_PcsReceiveVendorDebug_BiggestVersion AQ_PcsReceiveVendorDebug_HHD -#define AQ_PcsReceiveVendorFcsErrorFrameCounter_BiggestVersion AQ_PcsReceiveVendorFcsErrorFrameCounter_HHD -#define AQ_PcsReceiveVendorFcsNoErrorFrameCounter_BiggestVersion AQ_PcsReceiveVendorFcsNoErrorFrameCounter_HHD -#define AQ_PcsReceiveVendorInterruptMask_BiggestVersion AQ_PcsReceiveVendorInterruptMask_HHD -#define AQ_PcsReceiveVendorProvisioning_BiggestVersion AQ_PcsReceiveVendorProvisioning_HHD -#define AQ_PcsReceiveVendorState_BiggestVersion AQ_PcsReceiveVendorState_HHD -#define AQ_PcsReceiveVendorUncorrectedFrameCounter_BiggestVersion AQ_PcsReceiveVendorUncorrectedFrameCounter_HHD -#define AQ_PcsReceiveXfi0Provisioning_BiggestVersion AQ_PcsReceiveXfi0Provisioning_HHD -#define AQ_PcsReceiveXfi0VendorState_BiggestVersion AQ_PcsReceiveXfi0VendorState_HHD -#define AQ_PcsReceiveXfi1Provisioning_BiggestVersion AQ_PcsReceiveXfi1Provisioning_HHD -#define AQ_PcsReceiveXfi1VendorState_BiggestVersion AQ_PcsReceiveXfi1VendorState_HHD -#define AQ_PcsSerdesMuxSwapTxrxRegister_BiggestVersion AQ_PcsSerdesMuxSwapTxrxRegister_HHD -#define AQ_PcsStandardControl_1_BiggestVersion AQ_PcsStandardControl_1_HHD -#define AQ_PcsStandardControl_2_BiggestVersion AQ_PcsStandardControl_2_HHD -#define AQ_PcsStandardDeviceIdentifier_BiggestVersion AQ_PcsStandardDeviceIdentifier_HHD -#define AQ_PcsStandardDevicesInPackage_BiggestVersion AQ_PcsStandardDevicesInPackage_HHD -#define AQ_PcsStandardInterruptMask_BiggestVersion AQ_PcsStandardInterruptMask_HHD -#define AQ_PcsStandardPackageIdentifier_BiggestVersion AQ_PcsStandardPackageIdentifier_HHD -#define AQ_PcsStandardSpeedAbility_BiggestVersion AQ_PcsStandardSpeedAbility_HHD -#define AQ_PcsStandardStatus_1_BiggestVersion AQ_PcsStandardStatus_1_HHD -#define AQ_PcsStandardStatus_2_BiggestVersion AQ_PcsStandardStatus_2_HHD -#define AQ_PcsTransmitReservedVendorProvisioning_BiggestVersion AQ_PcsTransmitReservedVendorProvisioning_HHD -#define AQ_PcsTransmitVendorAlarms_BiggestVersion AQ_PcsTransmitVendorAlarms_APPIA -#define AQ_PcsTransmitVendorDebug_BiggestVersion AQ_PcsTransmitVendorDebug_HHD -#define AQ_PcsTransmitVendorFcsErrorFrameCounter_BiggestVersion AQ_PcsTransmitVendorFcsErrorFrameCounter_HHD -#define AQ_PcsTransmitVendorFcsNoErrorFrameCounter_BiggestVersion AQ_PcsTransmitVendorFcsNoErrorFrameCounter_HHD -#define AQ_PcsTransmitVendorInterruptMask_BiggestVersion AQ_PcsTransmitVendorInterruptMask_APPIA -#define AQ_PcsTransmitVendorProvisioning_BiggestVersion AQ_PcsTransmitVendorProvisioning_HHD -#define AQ_PcsTransmitXfi0VendorProvisioning_BiggestVersion AQ_PcsTransmitXfi0VendorProvisioning_HHD -#define AQ_PcsTransmitXfi0VendorState_BiggestVersion AQ_PcsTransmitXfi0VendorState_HHD -#define AQ_PcsTransmitXfi1VendorProvisioning_BiggestVersion AQ_PcsTransmitXfi1VendorProvisioning_HHD -#define AQ_PcsTransmitXfi1VendorState_BiggestVersion AQ_PcsTransmitXfi1VendorState_HHD -#define AQ_PcsTransmitXfiVendorProvisioning_BiggestVersion AQ_PcsTransmitXfiVendorProvisioning_HHD -#define AQ_PcsTransmitXgsVendorState_BiggestVersion AQ_PcsTransmitXgsVendorState_HHD -#define AQ_PcsVendorGlobalInterruptFlags_BiggestVersion AQ_PcsVendorGlobalInterruptFlags_HHD -#define AQ_PhyXS_EeeCapabilityRegister_BiggestVersion AQ_PhyXS_EeeCapabilityRegister_HHD -#define AQ_PhyXS_EeeWakeErrorCounter_BiggestVersion AQ_PhyXS_EeeWakeErrorCounter_HHD -#define AQ_PhyXS_Receive_xauiTx_PcsStatus_BiggestVersion AQ_PhyXS_Receive_xauiTx_PcsStatus_HHD -#define AQ_PhyXS_Receive_xauiTx_ReservedVendorProvisioning_BiggestVersion AQ_PhyXS_Receive_xauiTx_ReservedVendorProvisioning_HHD -#define AQ_PhyXS_Receive_xauiTx_VendorAlarms_BiggestVersion AQ_PhyXS_Receive_xauiTx_VendorAlarms_HHD -#define AQ_PhyXS_Receive_xauiTx_VendorDebug_BiggestVersion AQ_PhyXS_Receive_xauiTx_VendorDebug_HHD -#define AQ_PhyXS_Receive_xauiTx_VendorInterruptMask_BiggestVersion AQ_PhyXS_Receive_xauiTx_VendorInterruptMask_HHD -#define AQ_PhyXS_SerdesConfiguration_BiggestVersion AQ_PhyXS_SerdesConfiguration_HHD -#define AQ_PhyXS_SerdesLane_0Configuration_BiggestVersion AQ_PhyXS_SerdesLane_0Configuration_HHD -#define AQ_PhyXS_SerdesLane_1Configuration_BiggestVersion AQ_PhyXS_SerdesLane_1Configuration_HHD -#define AQ_PhyXS_SerdesLane_2Configuration_BiggestVersion AQ_PhyXS_SerdesLane_2Configuration_HHD -#define AQ_PhyXS_SerdesLane_3Configuration_BiggestVersion AQ_PhyXS_SerdesLane_3Configuration_HHD -#define AQ_PhyXS_SerdesLut_BiggestVersion AQ_PhyXS_SerdesLut_HHD -#define AQ_PhyXS_StandardControl_1_BiggestVersion AQ_PhyXS_StandardControl_1_HHD -#define AQ_PhyXS_StandardDeviceIdentifier_BiggestVersion AQ_PhyXS_StandardDeviceIdentifier_HHD -#define AQ_PhyXS_StandardDevicesInPackage_BiggestVersion AQ_PhyXS_StandardDevicesInPackage_HHD -#define AQ_PhyXS_StandardPackageIdentifier_BiggestVersion AQ_PhyXS_StandardPackageIdentifier_HHD -#define AQ_PhyXS_StandardSpeedAbility_BiggestVersion AQ_PhyXS_StandardSpeedAbility_HHD -#define AQ_PhyXS_StandardStatus_1_BiggestVersion AQ_PhyXS_StandardStatus_1_HHD -#define AQ_PhyXS_StandardStatus_2_BiggestVersion AQ_PhyXS_StandardStatus_2_HHD -#define AQ_PhyXS_StandardXGXS_LaneStatus_BiggestVersion AQ_PhyXS_StandardXGXS_LaneStatus_HHD -#define AQ_PhyXS_StandardXGXS_TestControl_BiggestVersion AQ_PhyXS_StandardXGXS_TestControl_HHD -#define AQ_PhyXS_SystemInterfaceConnectionStatus_BiggestVersion AQ_PhyXS_SystemInterfaceConnectionStatus_HHD -#define AQ_PhyXS_Transmit_xauiRx_PcsStatus_BiggestVersion AQ_PhyXS_Transmit_xauiRx_PcsStatus_HHD -#define AQ_PhyXS_Transmit_xauiRx_ReservedVendorProvisioning_BiggestVersion AQ_PhyXS_Transmit_xauiRx_ReservedVendorProvisioning_HHD -#define AQ_PhyXS_Transmit_xauiRx_ReservedVendorState_BiggestVersion AQ_PhyXS_Transmit_xauiRx_ReservedVendorState_HHD -#define AQ_PhyXS_Transmit_xauiRx_StandardInterruptMask_BiggestVersion AQ_PhyXS_Transmit_xauiRx_StandardInterruptMask_HHD -#define AQ_PhyXS_Transmit_xauiRx_TestPatternErrorCounter_BiggestVersion AQ_PhyXS_Transmit_xauiRx_TestPatternErrorCounter_HHD -#define AQ_PhyXS_Transmit_xauiRx_VendorAlarms_BiggestVersion AQ_PhyXS_Transmit_xauiRx_VendorAlarms_HHD -#define AQ_PhyXS_Transmit_xauiRx_VendorDebug_BiggestVersion AQ_PhyXS_Transmit_xauiRx_VendorDebug_HHD -#define AQ_PhyXS_Transmit_xauiRx_VendorInterruptMask_BiggestVersion AQ_PhyXS_Transmit_xauiRx_VendorInterruptMask_HHD -#define AQ_PhyXS_VendorGlobalInterruptFlags_BiggestVersion AQ_PhyXS_VendorGlobalInterruptFlags_HHD -#define AQ_PifMailboxControl_BiggestVersion AQ_PifMailboxControl_HHD -#define AQ_Pma10GBaseT_FastRetrainStatusAndControl_BiggestVersion AQ_Pma10GBaseT_FastRetrainStatusAndControl_HHD -#define AQ_Pma10GBaseT_PairSwapAndPolarityStatus_BiggestVersion AQ_Pma10GBaseT_PairSwapAndPolarityStatus_HHD -#define AQ_Pma10GBaseT_ReceiveSignalPowerChannelA_BiggestVersion AQ_Pma10GBaseT_ReceiveSignalPowerChannelA_HHD -#define AQ_Pma10GBaseT_ReceiveSignalPowerChannelB_BiggestVersion AQ_Pma10GBaseT_ReceiveSignalPowerChannelB_HHD -#define AQ_Pma10GBaseT_ReceiveSignalPowerChannelC_BiggestVersion AQ_Pma10GBaseT_ReceiveSignalPowerChannelC_HHD -#define AQ_Pma10GBaseT_ReceiveSignalPowerChannelD_BiggestVersion AQ_Pma10GBaseT_ReceiveSignalPowerChannelD_HHD -#define AQ_Pma10GBaseT_SNR_MinimumOperatingMarginChannelA_BiggestVersion AQ_Pma10GBaseT_SNR_MinimumOperatingMarginChannelA_HHD -#define AQ_Pma10GBaseT_SNR_MinimumOperatingMarginChannelB_BiggestVersion AQ_Pma10GBaseT_SNR_MinimumOperatingMarginChannelB_HHD -#define AQ_Pma10GBaseT_SNR_MinimumOperatingMarginChannelC_BiggestVersion AQ_Pma10GBaseT_SNR_MinimumOperatingMarginChannelC_HHD -#define AQ_Pma10GBaseT_SNR_MinimumOperatingMarginChannelD_BiggestVersion AQ_Pma10GBaseT_SNR_MinimumOperatingMarginChannelD_HHD -#define AQ_Pma10GBaseT_SNR_OperatingMarginChannelA_BiggestVersion AQ_Pma10GBaseT_SNR_OperatingMarginChannelA_HHD -#define AQ_Pma10GBaseT_SNR_OperatingMarginChannelB_BiggestVersion AQ_Pma10GBaseT_SNR_OperatingMarginChannelB_HHD -#define AQ_Pma10GBaseT_SNR_OperatingMarginChannelC_BiggestVersion AQ_Pma10GBaseT_SNR_OperatingMarginChannelC_HHD -#define AQ_Pma10GBaseT_SNR_OperatingMarginChannelD_BiggestVersion AQ_Pma10GBaseT_SNR_OperatingMarginChannelD_HHD -#define AQ_Pma10GBaseT_SkewDelay_BiggestVersion AQ_Pma10GBaseT_SkewDelay_HHD -#define AQ_Pma10GBaseT_Status_BiggestVersion AQ_Pma10GBaseT_Status_HHD -#define AQ_Pma10GBaseT_TestModes_BiggestVersion AQ_Pma10GBaseT_TestModes_HHD -#define AQ_Pma10GBaseT_TxPowerBackoffAndShortReachSetting_BiggestVersion AQ_Pma10GBaseT_TxPowerBackoffAndShortReachSetting_HHD -#define AQ_PmaReceiveReservedVendorProvisioning_BiggestVersion AQ_PmaReceiveReservedVendorProvisioning_HHD -#define AQ_PmaReceiveReservedVendorState_BiggestVersion AQ_PmaReceiveReservedVendorState_HHD -#define AQ_PmaReceiveVendorState_BiggestVersion AQ_PmaReceiveVendorState_HHD -#define AQ_PmaStandardControl_1_BiggestVersion AQ_PmaStandardControl_1_HHD -#define AQ_PmaStandardControl_2_BiggestVersion AQ_PmaStandardControl_2_HHD -#define AQ_PmaStandardDeviceIdentifier_BiggestVersion AQ_PmaStandardDeviceIdentifier_HHD -#define AQ_PmaStandardDevicesInPackage_BiggestVersion AQ_PmaStandardDevicesInPackage_HHD -#define AQ_PmaStandardPackageIdentifier_BiggestVersion AQ_PmaStandardPackageIdentifier_HHD -#define AQ_PmaStandardSpeedAbility_BiggestVersion AQ_PmaStandardSpeedAbility_HHD -#define AQ_PmaStandardStatus_1_BiggestVersion AQ_PmaStandardStatus_1_HHD -#define AQ_PmaStandardStatus_2_BiggestVersion AQ_PmaStandardStatus_2_HHD -#define AQ_PmaTransmitReservedVendorProvisioning_BiggestVersion AQ_PmaTransmitReservedVendorProvisioning_HHD -#define AQ_PmaTransmitStandardInterruptMask_BiggestVersion AQ_PmaTransmitStandardInterruptMask_HHD -#define AQ_PmaTransmitVendorAlarms_BiggestVersion AQ_PmaTransmitVendorAlarms_HHD -#define AQ_PmaTransmitVendorDebug_BiggestVersion AQ_PmaTransmitVendorDebug_HHD -#define AQ_PmaTransmitVendorLASI_InterruptMask_BiggestVersion AQ_PmaTransmitVendorLASI_InterruptMask_HHD -#define AQ_PmaVendorGlobalInterruptFlags_BiggestVersion AQ_PmaVendorGlobalInterruptFlags_HHD -#define AQ_PmdStandard10G_ExtendedAbilityRegister_BiggestVersion AQ_PmdStandard10G_ExtendedAbilityRegister_HHD -#define AQ_PmdStandardSignalDetect_BiggestVersion AQ_PmdStandardSignalDetect_HHD -#define AQ_PmdStandardTransmitDisableControl_BiggestVersion AQ_PmdStandardTransmitDisableControl_HHD -#define AQ_Sgmii0WolStatus_BiggestVersion AQ_Sgmii0WolStatus_HHD -#define AQ_TimesyncPcsCapability_BiggestVersion AQ_TimesyncPcsCapability_HHD -#define AQ_TimesyncPcsReceivePathDataDelay_BiggestVersion AQ_TimesyncPcsReceivePathDataDelay_HHD -#define AQ_TimesyncPcsTransmitPathDataDelay_BiggestVersion AQ_TimesyncPcsTransmitPathDataDelay_HHD -#define AQ_TimesyncPhyXsCapability_BiggestVersion AQ_TimesyncPhyXsCapability_HHD -#define AQ_TimesyncPhyXsReceivePathDataDelay_BiggestVersion AQ_TimesyncPhyXsReceivePathDataDelay_HHD -#define AQ_TimesyncPhyXsTransmitPathDataDelay_BiggestVersion AQ_TimesyncPhyXsTransmitPathDataDelay_HHD -#define AQ_TimesyncPmaCapability_BiggestVersion AQ_TimesyncPmaCapability_HHD -#define AQ_TimesyncPmaReceivePathDataDelay_BiggestVersion AQ_TimesyncPmaReceivePathDataDelay_HHD -#define AQ_TimesyncPmaTransmitPathDataDelay_BiggestVersion AQ_TimesyncPmaTransmitPathDataDelay_HHD -#define AQ_XenpakBasic_ApsLoading_BiggestVersion AQ_XenpakBasic_ApsLoading_HHD -#define AQ_XenpakBasic_ApsVoltage_BiggestVersion AQ_XenpakBasic_ApsVoltage_HHD -#define AQ_XenpakBasic_BitRate_BiggestVersion AQ_XenpakBasic_BitRate_HHD -#define AQ_XenpakBasic_Checksum_BiggestVersion AQ_XenpakBasic_Checksum_HHD -#define AQ_XenpakBasic_ConnectorType_BiggestVersion AQ_XenpakBasic_ConnectorType_HHD -#define AQ_XenpakBasic_DomCapability_BiggestVersion AQ_XenpakBasic_DomCapability_HHD -#define AQ_XenpakBasic_Encoding_BiggestVersion AQ_XenpakBasic_Encoding_HHD -#define AQ_XenpakBasic_Low_powerStartupCapability_BiggestVersion AQ_XenpakBasic_Low_powerStartupCapability_HHD -#define AQ_XenpakBasic_PackageIdentifier_BiggestVersion AQ_XenpakBasic_PackageIdentifier_HHD -#define AQ_XenpakBasic_Protocol_BiggestVersion AQ_XenpakBasic_Protocol_HHD -#define AQ_XenpakBasic_Reserved_0x11_BiggestVersion AQ_XenpakBasic_Reserved_0x11_HHD -#define AQ_XenpakBasic_Reserved_0x19_BiggestVersion AQ_XenpakBasic_Reserved_0x19_HHD -#define AQ_XenpakBasic_Reserved_0x7c_BiggestVersion AQ_XenpakBasic_Reserved_0x7c_HHD -#define AQ_XenpakBasic_StandardsComplianceCodes_BiggestVersion AQ_XenpakBasic_StandardsComplianceCodes_HHD -#define AQ_XenpakBasic_TransceiverType_BiggestVersion AQ_XenpakBasic_TransceiverType_HHD -#define AQ_XenpakBasic_VendorDateCode_BiggestVersion AQ_XenpakBasic_VendorDateCode_HHD -#define AQ_XenpakBasic_VendorIdentifier_BiggestVersion AQ_XenpakBasic_VendorIdentifier_HHD -#define AQ_XenpakBasic_VendorName_BiggestVersion AQ_XenpakBasic_VendorName_HHD -#define AQ_XenpakBasic_VendorPartNumber_BiggestVersion AQ_XenpakBasic_VendorPartNumber_HHD -#define AQ_XenpakBasic_VendorPartRevisionNumber_BiggestVersion AQ_XenpakBasic_VendorPartRevisionNumber_HHD -#define AQ_XenpakBasic_VendorSerialNumber_BiggestVersion AQ_XenpakBasic_VendorSerialNumber_HHD -#define AQ_XenpakBasic__3_3vLoading_BiggestVersion AQ_XenpakBasic__3_3vLoading_HHD -#define AQ_XenpakBasic__5vLoading_BiggestVersion AQ_XenpakBasic__5vLoading_HHD -#define AQ_XenpakControl_BiggestVersion AQ_XenpakControl_HHD -#define AQ_XenpakCustomer_Reserved_0x7e_BiggestVersion AQ_XenpakCustomer_Reserved_0x7e_HHD -#define AQ_XenpakDom_Alarms_BiggestVersion AQ_XenpakDom_Alarms_HHD -#define AQ_XenpakDom_Capability_BiggestVersion AQ_XenpakDom_Capability_HHD -#define AQ_XenpakDom_ControlAndStatus_BiggestVersion AQ_XenpakDom_ControlAndStatus_HHD -#define AQ_XenpakDom_HighTemperatureAlarmThresholdLSW_BiggestVersion AQ_XenpakDom_HighTemperatureAlarmThresholdLSW_HHD -#define AQ_XenpakDom_HighTemperatureAlarmThresholdMSW_BiggestVersion AQ_XenpakDom_HighTemperatureAlarmThresholdMSW_HHD -#define AQ_XenpakDom_HighTemperatureWarningThresholdLSW_BiggestVersion AQ_XenpakDom_HighTemperatureWarningThresholdLSW_HHD -#define AQ_XenpakDom_HighTemperatureWarningThresholdMSW_BiggestVersion AQ_XenpakDom_HighTemperatureWarningThresholdMSW_HHD -#define AQ_XenpakDom_LowTemperatureAlarmThresholdLSW_BiggestVersion AQ_XenpakDom_LowTemperatureAlarmThresholdLSW_HHD -#define AQ_XenpakDom_LowTemperatureAlarmThresholdMSW_BiggestVersion AQ_XenpakDom_LowTemperatureAlarmThresholdMSW_HHD -#define AQ_XenpakDom_LowTemperatureWarningThresholdLSW_BiggestVersion AQ_XenpakDom_LowTemperatureWarningThresholdLSW_HHD -#define AQ_XenpakDom_LowTemperatureWarningThresholdMSW_BiggestVersion AQ_XenpakDom_LowTemperatureWarningThresholdMSW_HHD -#define AQ_XenpakDom_Status_BiggestVersion AQ_XenpakDom_Status_HHD -#define AQ_XenpakDom_TemperatureLSW_BiggestVersion AQ_XenpakDom_TemperatureLSW_HHD -#define AQ_XenpakDom_TemperatureMSW_BiggestVersion AQ_XenpakDom_TemperatureMSW_HHD -#define AQ_XenpakDom_TxControl_BiggestVersion AQ_XenpakDom_TxControl_HHD -#define AQ_XenpakHeader_BasicMemoryStartAddress_BiggestVersion AQ_XenpakHeader_BasicMemoryStartAddress_HHD -#define AQ_XenpakHeader_CustomerMemoryOffset_BiggestVersion AQ_XenpakHeader_CustomerMemoryOffset_HHD -#define AQ_XenpakHeader_ExtendedVendorMemoryOffset_BiggestVersion AQ_XenpakHeader_ExtendedVendorMemoryOffset_HHD -#define AQ_XenpakHeader_MemoryUsed_BiggestVersion AQ_XenpakHeader_MemoryUsed_HHD -#define AQ_XenpakHeader_NvrSize_BiggestVersion AQ_XenpakHeader_NvrSize_HHD -#define AQ_XenpakHeader_VendorMemoryStartAddress_BiggestVersion AQ_XenpakHeader_VendorMemoryStartAddress_HHD -#define AQ_XenpakHeader_XenpakMsaVersionSupported_BiggestVersion AQ_XenpakHeader_XenpakMsaVersionSupported_HHD -#define AQ_XenpakLASI__Control_BiggestVersion AQ_XenpakLASI__Control_HHD -#define AQ_XenpakLASI__Status_BiggestVersion AQ_XenpakLASI__Status_HHD -#define AQ_XenpakRxAlarm_Control_BiggestVersion AQ_XenpakRxAlarm_Control_HHD -#define AQ_XenpakRxAlarm_Status_BiggestVersion AQ_XenpakRxAlarm_Status_HHD -#define AQ_XenpakTxAlarm_Control_BiggestVersion AQ_XenpakTxAlarm_Control_HHD -#define AQ_XenpakTxAlarm_Status_BiggestVersion AQ_XenpakTxAlarm_Status_HHD -#define AQ_XenpakVendor_Reserved_0xae_BiggestVersion AQ_XenpakVendor_Reserved_0xae_HHD - -#endif diff --git a/qca/aq-fw-download/src/include/registerMap/AQ_RegMaps.h b/qca/aq-fw-download/src/include/registerMap/AQ_RegMaps.h deleted file mode 100644 index 52a24e385..000000000 --- a/qca/aq-fw-download/src/include/registerMap/AQ_RegMaps.h +++ /dev/null @@ -1,69 +0,0 @@ -/*AQ_RegMaps.h*/ - -/************************************************************************************ -* Copyright (c) 2015, Aquantia -* -* Permission to use, copy, modify, and/or distribute this software for any -* purpose with or without fee is hereby granted, provided that the above -* copyright notice and this permission notice appear in all copies. -* -* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -* -* Description: -* -* This file contains includes all appropriate Aquantia PHY device-specific -* register map headers. -* -************************************************************************************/ - -/*! \file -* This file contains includes all appropriate Aquantia PHY device-specific -* register map headers. - */ - -#ifndef AQ_REGISTERMAPS_HEADER -#define AQ_REGISTERMAPS_HEADER - -#include "AQ_User.h" -#include "AQ_RegGroupMaxSizes.h" - - -#ifndef AQ_REVERSED_BITFIELD_ORDERING -/* - * Include non-reversed header files (bitfields ordered from LSbit to MSbit) - */ - -/* APPIA */ -#include "AQ_APPIA_Global_registers.h" - -#include "AQ_APPIA_Global_registers_Defines.h" - -/* HHD */ -#include "AQ_HHD_Global_registers.h" - -#include "AQ_HHD_Global_registers_Defines.h" - -#else -/* - * Include reversed header files (bitfields ordered from MSbit to LSbit) - */ - -/* APPIA */ -#include "AQ_APPIA_Global_registers_reversed.h" - -#include "AQ_APPIA_Global_registers_Defines.h" - -/* HHD */ -#include "AQ_HHD_Global_registers_reversed.h" - -#include "AQ_HHD_Global_registers_Defines.h" - -#endif - -#endif diff --git a/qca/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers.h b/qca/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers.h deleted file mode 100644 index e0a2fa27b..000000000 --- a/qca/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers.h +++ /dev/null @@ -1,12123 +0,0 @@ -/*! \file -* This file contains the data structures and doxygen comments -* for the Global Registers block. - */ - -/*! \addtogroup registerMap - @{ -*/ - -/*! \defgroup Global_registers Global Registers -* This module contains the data structures and doxygen comments -* for the Global Registers block. - */ -/*********************************************************************** -* Copyright (c) 2015, Aquantia -* -* Permission to use, copy, modify, and/or distribute this software for any -* purpose with or without fee is hereby granted, provided that the above -* copyright notice and this permission notice appear in all copies. -* -* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -* -* $Date: 2014/04/08 $ -* -* $Label: $ -* -* Description: -* -* This file contains the c header structures for the registers contained in the Global Registers block. -* -* The bit fields in this structure are from LSbit to MSbit -* -***********************************************************************/ - - -/*@{*/ -#ifndef AQ_HHD_GLOBAL_REGS_HEADER -#define AQ_HHD_GLOBAL_REGS_HEADER - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Standard Control 1: 1E.0000 */ -/* Global Standard Control 1: 1E.0000 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Standard Control 1 */ - union - { - struct - { - unsigned int reserved1 : 11; - /*! \brief 1E.0000.B R/WPD Low Power - AQ_GlobalStandardControl_1_HHD.u0.bits_0.lowPower - - Provisionable Default = 0x0 - - 1 = Low-power mode - 0 = Normal operation - - - Notes: - A one written to this register causes the chip to enter low-power mode. This bit puts the entire chip in low-power mode, with only the MDIO and microprocessor functioning, and turns off the analog front-end: i.e. places it in high-impedance mode. Setting this bit also sets all of the Low Power bits in the other MMDs. */ - unsigned int lowPower : 1; /* 1E.0000.B R/WPD Provisionable Default = 0x0 */ - /* 1 = Low-power mode - 0 = Normal operation - */ - unsigned int reserved0 : 3; - /*! \brief 1E.0000.F R/WSC Soft Reset - AQ_GlobalStandardControl_1_HHD.u0.bits_0.softReset - - Default = 0x1 - - 1 = Global soft reset - 0 = Normal operation - - - Notes: - Resets the entire PHY. - Setting this bit initiates a global soft reset on all of the digital logic not including the microprocessor (i.e. microprocessor is not reset). Upon completion of the reset sequence, this bit is set back to 0by the microprocessor. Note this bit is OR'ed with the individual MMD resets. This bit should be set to 0 before setting the individual MMD resets. */ - unsigned int softReset : 1; /* 1E.0000.F R/WSC Default = 0x1 */ - /* 1 = Global soft reset - 0 = Normal operation - */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalStandardControl_1_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Standard Device Identifier: 1E.0002 */ -/* Global Standard Device Identifier: 1E.0002 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Standard Device Identifier */ - union - { - struct - { - /*! \brief 1E.0002.F:0 RO Device ID MSW [1F:10] - AQ_GlobalStandardDeviceIdentifier_HHD.u0.bits_0.deviceIdMSW - - - - Bits 31 - 16 of Device ID - */ - unsigned int deviceIdMSW : 16; /* 1E.0002.F:0 RO */ - /* Bits 31 - 16 of Device ID */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Standard Device Identifier */ - union - { - struct - { - /*! \brief 1E.0003.F:0 RO Device ID LSW [F:0] - AQ_GlobalStandardDeviceIdentifier_HHD.u1.bits_1.deviceIdLSW - - - - Bits 15 - 0 of Device ID - */ - unsigned int deviceIdLSW : 16; /* 1E.0003.F:0 RO */ - /* Bits 15 - 0 of Device ID */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_GlobalStandardDeviceIdentifier_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Standard Devices in Package: 1E.0005 */ -/* Global Standard Devices in Package: 1E.0005 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Standard Devices in Package */ - union - { - struct - { - /*! \brief 1E.0005.0 ROS Clause 22 Registers Present - AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.clause_22RegistersPresent - - Default = 0x0 - - 1 = Clause 22 registers are present in package - 0 = Clause 22 registers are not present in package - - Notes: - This is always set to 0 in the PHY, as there are no Clause 22 registers in the device. */ - unsigned int clause_22RegistersPresent : 1; /* 1E.0005.0 ROS Default = 0x0 */ - /* 1 = Clause 22 registers are present in package - 0 = Clause 22 registers are not present in package */ - /*! \brief 1E.0005.1 ROS PMA Present - AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.pmaPresent - - Default = 0x1 - - 1 = PMA is present in package - 0 = PMA is not present - - Notes: - This is always set to 1 as there is PMA functionality in the PHY. */ - unsigned int pmaPresent : 1; /* 1E.0005.1 ROS Default = 0x1 */ - /* 1 = PMA is present in package - 0 = PMA is not present */ - /*! \brief 1E.0005.2 ROS WIS Present - AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.wisPresent - - Default = 0x0 - - 1 = WIS is present in package - 0 = WIS is not present in package - - Notes: - This is always set to 0, as there is no WIS functionality in the PHY. */ - unsigned int wisPresent : 1; /* 1E.0005.2 ROS Default = 0x0 */ - /* 1 = WIS is present in package - 0 = WIS is not present in package */ - /*! \brief 1E.0005.3 ROS PCS Present - AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.pcsPresent - - Default = 0x1 - - 1 = PCS is present in package - 0 = PCS is not present in package - - Notes: - This is always set to 1 as there is PCS functionality in the PHY. */ - unsigned int pcsPresent : 1; /* 1E.0005.3 ROS Default = 0x1 */ - /* 1 = PCS is present in package - 0 = PCS is not present in package */ - /*! \brief 1E.0005.4 ROS PHY XS Present - AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.phyXS_Present - - Default = 0x1 - - 1 = PHY XS is present in package - 0 = PHY XS is not present in package - - Notes: - This is always set to 1 as there is a PHY XS interface in the PHY. */ - unsigned int phyXS_Present : 1; /* 1E.0005.4 ROS Default = 0x1 */ - /* 1 = PHY XS is present in package - 0 = PHY XS is not present in package */ - /*! \brief 1E.0005.5 ROS DTE XS Present - AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.dteXsPresent - - Default = 0x0 - - 1 = DTE XS is present in package - 0 = DTE XS is not present in package - - - Notes: - This is always set to 0, as there is no DTE XAUI interface in the PHY. */ - unsigned int dteXsPresent : 1; /* 1E.0005.5 ROS Default = 0x0 */ - /* 1 = DTE XS is present in package - 0 = DTE XS is not present in package - */ - /*! \brief 1E.0005.6 ROS TC Present - AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.tcPresent - - Default = 0x0 - - 1 = TC is present in package - 0 = TC is not present in package - - Notes: - This is always set to 0, as there is no TC functionality in the PHY. */ - unsigned int tcPresent : 1; /* 1E.0005.6 ROS Default = 0x0 */ - /* 1 = TC is present in package - 0 = TC is not present in package */ - /*! \brief 1E.0005.7 ROS Autonegotiation Present - AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.autonegotiationPresent - - Default = 0x1 - - 1 = Autonegotiation is present in package - 0 = Autonegotiation is not present in package - - Notes: - This is always set to 1, as there is Autonegotiation in the PHY. */ - unsigned int autonegotiationPresent : 1; /* 1E.0005.7 ROS Default = 0x1 */ - /* 1 = Autonegotiation is present in package - 0 = Autonegotiation is not present in package */ - unsigned int reserved0 : 8; - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalStandardDevicesInPackage_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Standard Vendor Devices in Package: 1E.0006 */ -/* Global Standard Vendor Devices in Package: 1E.0006 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Standard Vendor Devices in Package */ - union - { - struct - { - unsigned int reserved0 : 13; - /*! \brief 1E.0006.D ROS Clause 22 Extension Present - AQ_GlobalStandardVendorDevicesInPackage_HHD.u0.bits_0.clause_22ExtensionPresent - - Default = 0x1 - - 1 = Clause 22 Extension is present in package - 0 = Clause 22 Extension is not present in package - - Notes: - This is always set to 1 as the PHY utilizes this device for the GbE registers. */ - unsigned int clause_22ExtensionPresent : 1; /* 1E.0006.D ROS Default = 0x1 */ - /* 1 = Clause 22 Extension is present in package - 0 = Clause 22 Extension is not present in package */ - /*! \brief 1E.0006.E ROS Vendor Specific Device #1 Present - AQ_GlobalStandardVendorDevicesInPackage_HHD.u0.bits_0.vendorSpecificDevice_1Present - - Default = 0x1 - - 1 = Device #1 is present in package - 0 = Device #1 is not present in package - - Notes: - This is always set to 1 as the PHY utilizes this device for the global control registers. */ - unsigned int vendorSpecificDevice_1Present : 1; /* 1E.0006.E ROS Default = 0x1 */ - /* 1 = Device #1 is present in package - 0 = Device #1 is not present in package */ - /*! \brief 1E.0006.F ROS Vendor Specific Device #2 Present - AQ_GlobalStandardVendorDevicesInPackage_HHD.u0.bits_0.vendorSpecificDevice_2Present - - Default = 0x1 - - 1 = Device #2 is present in package - 0 = Device #2 is not present in package - - Notes: - This is always set to 1 as the PHY utilizes this device for the DSP PMA registers. */ - unsigned int vendorSpecificDevice_2Present : 1; /* 1E.0006.F ROS Default = 0x1 */ - /* 1 = Device #2 is present in package - 0 = Device #2 is not present in package */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalStandardVendorDevicesInPackage_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Standard Status 2: 1E.0008 */ -/* Global Standard Status 2: 1E.0008 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Standard Status 2 */ - union - { - struct - { - unsigned int reserved0 : 14; - /*! \brief 1E.0008.F:E ROS Device Present [1:0] - AQ_GlobalStandardStatus_2_HHD.u0.bits_0.devicePresent - - Default = 0x2 - - [F:E] - 0x3 = No device at this address - 0x2 = Device present at this address - 0x1 = No device at this address - 0x0 = No device at this address - - Notes: - This field is always set to 0x2, as the Global MMD resides here in the PHY. */ - unsigned int devicePresent : 2; /* 1E.0008.F:E ROS Default = 0x2 */ - /* [F:E] - 0x3 = No device at this address - 0x2 = Device present at this address - 0x1 = No device at this address - 0x0 = No device at this address */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalStandardStatus_2_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Standard Package Identifier: 1E.000E */ -/* Global Standard Package Identifier: 1E.000E */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Standard Package Identifier */ - union - { - struct - { - /*! \brief 1E.000E.F:0 RO Package ID MSW [1F:10] - AQ_GlobalStandardPackageIdentifier_HHD.u0.bits_0.packageIdMSW - - - - Bits 31- 16 of Package ID - */ - unsigned int packageIdMSW : 16; /* 1E.000E.F:0 RO */ - /* Bits 31- 16 of Package ID */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Standard Package Identifier */ - union - { - struct - { - /*! \brief 1E.000F.F:0 RO Package ID LSW [F:0] - AQ_GlobalStandardPackageIdentifier_HHD.u1.bits_1.packageIdLSW - - - - Bits 15 - 0 of Package ID - */ - unsigned int packageIdLSW : 16; /* 1E.000F.F:0 RO */ - /* Bits 15 - 0 of Package ID */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_GlobalStandardPackageIdentifier_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Firmware ID: 1E.0020 */ -/* Global Firmware ID: 1E.0020 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Firmware ID */ - union - { - struct - { - /*! \brief 1E.0020.7:0 RO Firmware Minor Revision Number [7:0] - AQ_GlobalFirmwareID_HHD.u0.bits_0.firmwareMinorRevisionNumber - - - - [7:0] = Minor revision number - - Notes: - - - The lower six bits of major and minor firmware revision are exchanged in autonegotiation when the PHYID message is sent. */ - unsigned int firmwareMinorRevisionNumber : 8; /* 1E.0020.7:0 RO */ - /* [7:0] = Minor revision number */ - /*! \brief 1E.0020.F:8 RO Firmware Major Revision Number [7:0] - AQ_GlobalFirmwareID_HHD.u0.bits_0.firmwareMajorRevisionNumber - - - - [F:8] = Major revision number - - Notes: - - - The lower six bits of major and minor firmware revision are exchanged in autonegotiation when the PHYID message is sent. */ - unsigned int firmwareMajorRevisionNumber : 8; /* 1E.0020.F:8 RO */ - /* [F:8] = Major revision number */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalFirmwareID_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global NVR Interface: 1E.0100 */ -/* Global NVR Interface: 1E.0100 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global NVR Interface */ - union - { - struct - { - /*! \brief 1E.0100.7:0 R/W NVR Opcode [7:0] - AQ_GlobalNvrInterface_HHD.u0.bits_0.nvrOpcode - - Default = 0x03 - - NVR instruction opcode - - */ - unsigned int nvrOpcode : 8; /* 1E.0100.7:0 R/W Default = 0x03 */ - /* NVR instruction opcode - */ - /*! \brief 1E.0100.8 RO NVR Busy - AQ_GlobalNvrInterface_HHD.u0.bits_0.nvrBusy - - - - 1 = NVR is busy - 0 = NVR is ready - - - Notes: - When set to 1, the NVR is busy. A new NVR operation should not occur until this bit is 0. If the NVR clock is greater than 64/63 of the MDIO clock, this bit never needs to be polled when operating over the MDIO. */ - unsigned int nvrBusy : 1; /* 1E.0100.8 RO */ - /* 1 = NVR is busy - 0 = NVR is ready - */ - unsigned int reserved1 : 1; - /*! \brief 1E.0100.A R/W NVR Burst - AQ_GlobalNvrInterface_HHD.u0.bits_0.nvrBurst - - Default = 0x0 - - 0 = Single read or write operation of up to 4 bytes - 1 = Burst operation - - - Notes: - When this bit is set, the operation is a burst operation where more than 32-bits is read from the NVR or written to the NVR. This bit should be set to one until the last burst in the read or write operation, when it should be set to zero. It operates by gating the SPI clock, and not restarting it until new data is ready to be written, or the previous contents have been read. Each burst of data requires the NVR Execute Operation bit to be set to initiate the next phase. */ - unsigned int nvrBurst : 1; /* 1E.0100.A R/W Default = 0x0 */ - /* 0 = Single read or write operation of up to 4 bytes - 1 = Burst operation - */ - unsigned int reserved0 : 1; - /*! \brief 1E.0100.C R/WSC Reset NVR CRC - AQ_GlobalNvrInterface_HHD.u0.bits_0.resetNvrCrc - - Default = 0x0 - - 1 = Reset NVR Mailbox CRC calculation register - - - - Notes: - To prevent an erroneous answer, this bit should not be set at the same time the See NVR Operation Valid bit is set. */ - unsigned int resetNvrCrc : 1; /* 1E.0100.C R/WSC Default = 0x0 */ - /* 1 = Reset NVR Mailbox CRC calculation register - - */ - /*! \brief 1E.0100.D R/W Freeze NVR CRC - AQ_GlobalNvrInterface_HHD.u0.bits_0.freezeNvrCrc - - Default = 0x0 - - 1 = Freeze NVR Mailbox CRC calculation register - - - Notes: - To prevent an erroneous answer, this bit should not be set at the same time the See NVR Operation Valid bit is set. */ - unsigned int freezeNvrCrc : 1; /* 1E.0100.D R/W Default = 0x0 */ - /* 1 = Freeze NVR Mailbox CRC calculation register - */ - /*! \brief 1E.0100.E R/W NVR Write Mode - AQ_GlobalNvrInterface_HHD.u0.bits_0.nvrWriteMode - - Default = 0x0 - - 1 = Write to NVR - 0 = Read from NVR - - */ - unsigned int nvrWriteMode : 1; /* 1E.0100.E R/W Default = 0x0 */ - /* 1 = Write to NVR - 0 = Read from NVR - */ - /*! \brief 1E.0100.F R/WSC NVR Execute Operation - AQ_GlobalNvrInterface_HHD.u0.bits_0.nvrExecuteOperation - - Default = 0x0 - - 1 = Start NVR Operation - - - - Notes: - When set to 1, the NVR operation will begin. Ensure that the uP is stalled using the See MCP Run Stall bit to ensure no NVR contention. */ - unsigned int nvrExecuteOperation : 1; /* 1E.0100.F R/WSC Default = 0x0 */ - /* 1 = Start NVR Operation - - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global NVR Interface */ - union - { - struct - { - /*! \brief 1E.0101.F:0 RO NVR Mailbox CRC [F:0] - AQ_GlobalNvrInterface_HHD.u1.bits_1.nvrMailboxCrc - - - - The running CRC-16 of everything passing through the NVR interface - - - Notes: - The CRC-16 over all data written or read through the NVR interface. The CRC-16 is calculated by dividing the data by: - x^16 + x^12 + x^5 + 1 */ - unsigned int nvrMailboxCrc : 16; /* 1E.0101.F:0 RO */ - /* The running CRC-16 of everything passing through the NVR interface - */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global NVR Interface */ - union - { - struct - { - /*! \brief 1E.0102.7:0 R/W NVR Address MSW [17:10] - AQ_GlobalNvrInterface_HHD.u2.bits_2.nvrAddressMSW - - Default = 0x00 - - NVR address MSW bits [17:10] - - - Notes: - The address of where to read and write from in the NVR. This is self-incrementing and will automatically increment after each read or write operation. The increment amount is based on the data length (i.e. increments by 4 if the data length is 4 bytes) */ - unsigned int nvrAddressMSW : 8; /* 1E.0102.7:0 R/W Default = 0x00 */ - /* NVR address MSW bits [17:10] - */ - unsigned int reserved0 : 8; - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global NVR Interface */ - union - { - struct - { - /*! \brief 1E.0103.F:0 R/W NVR Address LSW [F:0] - AQ_GlobalNvrInterface_HHD.u3.bits_3.nvrAddressLSW - - Default = 0x0000 - - NVR address LSW bits [F:0] - - - Notes: - The address of where to read and write from in the NVR. This is self-incrementing and will automatically increment after each read or write operation. */ - unsigned int nvrAddressLSW : 16; /* 1E.0103.F:0 R/W Default = 0x0000 */ - /* NVR address LSW bits [F:0] - */ - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of Global NVR Interface */ - union - { - struct - { - /*! \brief 1E.0104.F:0 R/W NVR Data MSW [1F:10] - AQ_GlobalNvrInterface_HHD.u4.bits_4.nvrDataMSW - - Default = 0x0000 - - NVR data MSW bits [1F:10] - - - Notes: - Data is stored and read-out from these registers in little-endian format for operations such as FLASH device ID, and for programming the processor. - - For instance the 64K Atmel device code reads out as two bytes 0x651F into the LSW register, whereas the datasheet indicates that 1F is the first byte read, followed by 65 as the second byte. - - To burst read and write these 4 bytes in the correct order (where DD is written to address x), they should be stored as: - - AA BB in the MSW - CC DD in the LSW. */ - unsigned int nvrDataMSW : 16; /* 1E.0104.F:0 R/W Default = 0x0000 */ - /* NVR data MSW bits [1F:10] - */ - } bits_4; - uint16_t word_4; - } u4; - /*! \brief Union for bit and word level access of word 5 of Global NVR Interface */ - union - { - struct - { - /*! \brief 1E.0105.F:0 R/W NVR Data LSW [F:0] - AQ_GlobalNvrInterface_HHD.u5.bits_5.nvrDataLSW - - Default = 0x0000 - - NVR data LSW bits [F:0] - - - Notes: - Data is stored and read-out from these registers in little-endian format for operations such as FLASH device ID, and for programming the processor. - - For instance the 64K Atmel device code reads out as two bytes 0x651F into the LSW register, whereas the datasheet indicates that 1F is the first byte read, followed by 65 as the second byte. - To burst read and write these 4 bytes in the correct order (where DD is written to address x), they should be stored as: - - AA BB in the MSW - CC DD in the LSW. */ - unsigned int nvrDataLSW : 16; /* 1E.0105.F:0 R/W Default = 0x0000 */ - /* NVR data LSW bits [F:0] - */ - } bits_5; - uint16_t word_5; - } u5; -} AQ_GlobalNvrInterface_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Mailbox Interface: 1E.0200 */ -/* Global Mailbox Interface: 1E.0200 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Mailbox Interface */ - union - { - struct - { - unsigned int reserved2 : 8; - /*! \brief 1E.0200.8 RO uP Mailbox Busy - AQ_GlobalMailboxInterface_HHD.u0.bits_0.upMailboxBusy - - - - 1 = uP mailbox busy - 0 = uP mailbox ready - - - Notes: - In general the uP will respond within a few processor cycles to any PIF slave request, much faster than the MDIO. If the busy is asserted over multiple MDIO polling cycles, then a H/W error may have occurred and a Global S/W reset or uP reset is required. */ - unsigned int upMailboxBusy : 1; /* 1E.0200.8 RO */ - /* 1 = uP mailbox busy - 0 = uP mailbox ready - */ - unsigned int reserved1 : 3; - /*! \brief 1E.0200.C R/WSC Reset uP Mailbox CRC - AQ_GlobalMailboxInterface_HHD.u0.bits_0.resetUpMailboxCrc - - Default = 0x0 - - 1 = Reset uP mailbox CRC calculation register - - - */ - unsigned int resetUpMailboxCrc : 1; /* 1E.0200.C R/WSC Default = 0x0 */ - /* 1 = Reset uP mailbox CRC calculation register - - */ - unsigned int reserved0 : 1; - /*! \brief 1E.0200.E R/W uP Mailbox Write Mode - AQ_GlobalMailboxInterface_HHD.u0.bits_0.upMailboxWriteMode - - Default = 0x0 - - 1 = Write - 0 = Read - - - Notes: - Mailbox direction */ - unsigned int upMailboxWriteMode : 1; /* 1E.0200.E R/W Default = 0x0 */ - /* 1 = Write - 0 = Read - */ - /*! \brief 1E.0200.F R/WSC uP Mailbox Execute Operation - AQ_GlobalMailboxInterface_HHD.u0.bits_0.upMailboxExecuteOperation - - Default = 0x0 - - 1 = Start of mailbox Operation - - - - Notes: - Indicates mailbox is loaded and ready */ - unsigned int upMailboxExecuteOperation : 1; /* 1E.0200.F R/WSC Default = 0x0 */ - /* 1 = Start of mailbox Operation - - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Mailbox Interface */ - union - { - struct - { - /*! \brief 1E.0201.F:0 RO uP Mailbox CRC [F:0] - AQ_GlobalMailboxInterface_HHD.u1.bits_1.upMailboxCrc - - - - The running CRC-16 of everything passing through the mailbox interface - - */ - unsigned int upMailboxCrc : 16; /* 1E.0201.F:0 RO */ - /* The running CRC-16 of everything passing through the mailbox interface - */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global Mailbox Interface */ - union - { - struct - { - /*! \brief 1E.0202.F:0 R/W uP Mailbox Address MSW [1F:10] - AQ_GlobalMailboxInterface_HHD.u2.bits_2.upMailboxAddressMSW - - Default = 0x0000 - - uP Mailbox MSW address - - - Notes: - The address of where to read and write from in the Microcontroller Mailbox. This is self-incrementing and automatically increments after each read and write operation.PHY */ - unsigned int upMailboxAddressMSW : 16; /* 1E.0202.F:0 R/W Default = 0x0000 */ - /* uP Mailbox MSW address - */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global Mailbox Interface */ - union - { - struct - { - /*! \brief 1E.0203.1:0 RO uP Mailbox Address LSW Don't Care [1:0] - AQ_GlobalMailboxInterface_HHD.u3.bits_3.upMailboxAddressLSW_Don_tCare - - - - Least significant uP LSW Mailbox address bits [1:0] - - - Notes: - These bits are always set to 0 since each memory access is on a 4-byte boundary. */ - unsigned int upMailboxAddressLSW_Don_tCare : 2; /* 1E.0203.1:0 RO */ - /* Least significant uP LSW Mailbox address bits [1:0] - */ - /*! \brief 1E.0203.F:2 R/W uP Mailbox Address LSW [F:2] - AQ_GlobalMailboxInterface_HHD.u3.bits_3.upMailboxAddressLSW - - Default = 0x0000 - - uP LSW Mailbox address [F:2] - - - Notes: - The address of where to read and write from in the Microcontroller Mailbox. This is self-incrementing and automatically increments after each read and write operation.PHY */ - unsigned int upMailboxAddressLSW : 14; /* 1E.0203.F:2 R/W Default = 0x0000 */ - /* uP LSW Mailbox address [F:2] - */ - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of Global Mailbox Interface */ - union - { - struct - { - /*! \brief 1E.0204.F:0 R/W uP Mailbox Data MSW [1F:10] - AQ_GlobalMailboxInterface_HHD.u4.bits_4.upMailboxDataMSW - - Default = 0x0000 - - uP Mailbox data MSW - - */ - unsigned int upMailboxDataMSW : 16; /* 1E.0204.F:0 R/W Default = 0x0000 */ - /* uP Mailbox data MSW - */ - } bits_4; - uint16_t word_4; - } u4; - /*! \brief Union for bit and word level access of word 5 of Global Mailbox Interface */ - union - { - struct - { - /*! \brief 1E.0205.F:0 R/W uP Mailbox Data LSW [F:0] - AQ_GlobalMailboxInterface_HHD.u5.bits_5.upMailboxDataLSW - - Default = 0x0000 - - uP Mailbox data LSW - - */ - unsigned int upMailboxDataLSW : 16; /* 1E.0205.F:0 R/W Default = 0x0000 */ - /* uP Mailbox data LSW - */ - } bits_5; - uint16_t word_5; - } u5; - /*! \brief Union for bit and word level access of word 6 of Global Mailbox Interface */ - union - { - struct - { - unsigned int reserved1 : 1; - /*! \brief 1E.0206.1 R/W uP Mailbox CRC Read Enable - AQ_GlobalMailboxInterface_HHD.u6.bits_6.upMailboxCrcReadEnable - - Default = 0x0 - - 1 = Update uP mailbox CRC on read - - */ - unsigned int upMailboxCrcReadEnable : 1; /* 1E.0206.1 R/W Default = 0x0 */ - /* 1 = Update uP mailbox CRC on read - */ - unsigned int reserved0 : 14; - } bits_6; - uint16_t word_6; - } u6; -} AQ_GlobalMailboxInterface_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Microprocessor Scratch Pad: 1E.0300 */ -/* Global Microprocessor Scratch Pad: 1E.0300 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Microprocessor Scratch Pad */ - union - { - struct - { - /*! \brief 1E.0300.F:0 R/W Scratch Pad 1[F:0] - AQ_GlobalMicroprocessorScratchPad_HHD.u0.bits_0.scratchPad_1 - - Default = 0x0000 - - General Purpose Scratch Pad - */ - unsigned int scratchPad_1 : 16; /* 1E.0300.F:0 R/W Default = 0x0000 */ - /* General Purpose Scratch Pad */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Microprocessor Scratch Pad */ - union - { - struct - { - /*! \brief 1E.0301.F:0 R/W Scratch Pad 2 [F:0] - AQ_GlobalMicroprocessorScratchPad_HHD.u1.bits_1.scratchPad_2 - - Default = 0x0000 - - General Purpose Scratch Pad - */ - unsigned int scratchPad_2 : 16; /* 1E.0301.F:0 R/W Default = 0x0000 */ - /* General Purpose Scratch Pad */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_GlobalMicroprocessorScratchPad_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Egress Control Register: 1E.5002 */ -/* MSS Egress Control Register: 1E.5002 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Egress Control Register */ - union - { - struct - { - /*! \brief 1E.5002.0 R/W MSS Egress Soft Reset - AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressSoftReset - - Default = 0x0 - - 1 = Soft reset - - - Notes: - S/W reset */ - unsigned int mssEgressSoftReset : 1; /* 1E.5002.0 R/W Default = 0x0 */ - /* 1 = Soft reset - */ - /*! \brief 1E.5002.1 R/W MSS Egress Drop KAY Packet - AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressDropKayPacket - - Default = 0x0 - - 1 = Drop KAY packet - - - Notes: - Decides whether KAY packets have to be dropped */ - unsigned int mssEgressDropKayPacket : 1; /* 1E.5002.1 R/W Default = 0x0 */ - /* 1 = Drop KAY packet - */ - /*! \brief 1E.5002.2 R/W MSS Egress Drop EGPRC LUT Miss - AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressDropEgprcLutMiss - - Default = 0x0 - - 1 = Drop Egress Classification LUT miss packets - - - - Notes: - Decides whether Egress Pre-Security Classification (EGPRC) LUT miss packets are to be dropped */ - unsigned int mssEgressDropEgprcLutMiss : 1; /* 1E.5002.2 R/W Default = 0x0 */ - /* 1 = Drop Egress Classification LUT miss packets - - */ - /*! \brief 1E.5002.3 R/W MSS Egress GCM Start - AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressGcmStart - - Default = 0x0 - - 1 = Start GCM - - - - Notes: - Indicates GCM to start */ - unsigned int mssEgressGcmStart : 1; /* 1E.5002.3 R/W Default = 0x0 */ - /* 1 = Start GCM - - */ - /*! \brief 1E.5002.4 R/W MSS Egresss GCM Test Mode - AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgresssGcmTestMode - - Default = 0x0 - - 1 = Enable GCM test mode - - - - Notes: - Enables GCM test mode */ - unsigned int mssEgresssGcmTestMode : 1; /* 1E.5002.4 R/W Default = 0x0 */ - /* 1 = Enable GCM test mode - - */ - /*! \brief 1E.5002.5 R/W MSS Egress Unmatched Use SC 0 - AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressUnmatchedUseSc_0 - - Default = 0x0 - - 1 = Use SC 0 for unmatched packets - 0 = Unmatched packets are uncontrolled packets - - - - Notes: - Use SC-Index 0 as default SC for unmatched packets. Otherwise the packets are treated as uncontrolled packets. */ - unsigned int mssEgressUnmatchedUseSc_0 : 1; /* 1E.5002.5 R/W Default = 0x0 */ - /* 1 = Use SC 0 for unmatched packets - 0 = Unmatched packets are uncontrolled packets - - */ - /*! \brief 1E.5002.6 R/W MSS Egress Drop Invalid SA/SC Packets - AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressDropInvalidSa_scPackets - - Default = 0x0 - - 1 = Drop invalid SA/SC packets - - - - Notes: - Enables dropping of invalid SA/SC packets. */ - unsigned int mssEgressDropInvalidSa_scPackets : 1; /* 1E.5002.6 R/W Default = 0x0 */ - /* 1 = Drop invalid SA/SC packets - - */ - /*! \brief 1E.5002.7 R/W MSS Egress Explicit SECTag Report Short Length - AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressExplicitSectagReportShortLength - - Default = 0x0 - - Reserved - - - - Notes: - Unused. */ - unsigned int mssEgressExplicitSectagReportShortLength : 1; /* 1E.5002.7 R/W Default = 0x0 */ - /* Reserved - - */ - /*! \brief 1E.5002.8 R/W MSS Egress External Classification Enable - AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressExternalClassificationEnable - - Default = 0x0 - - 1 = Drop EGPRC miss packets - - - - Notes: - If set, internal classification is bypassed. Should always be set to 0. */ - unsigned int mssEgressExternalClassificationEnable : 1; /* 1E.5002.8 R/W Default = 0x0 */ - /* 1 = Drop EGPRC miss packets - - */ - /*! \brief 1E.5002.9 R/W MSS Egress ICV LSB 8 Bytes Enable - AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressIcvLsb_8BytesEnable - - Default = 0x0 - - 1 = Use LSB - 0 = Use MSB - - - - Notes: - This bit selects MSB or LSB 8 bytes selection in the case where the ICV is 8 bytes. - 0 = MSB is used. */ - unsigned int mssEgressIcvLsb_8BytesEnable : 1; /* 1E.5002.9 R/W Default = 0x0 */ - /* 1 = Use LSB - 0 = Use MSB - - */ - /*! \brief 1E.5002.A R/W MSS Egress High Priority - AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressHighPriority - - Default = 0x0 - - 1 = MIB counter clear on read enable - - - - Notes: - If this bit is set to 1, read is given high priority and the MIB count value becomes 0 after read. */ - unsigned int mssEgressHighPriority : 1; /* 1E.5002.A R/W Default = 0x0 */ - /* 1 = MIB counter clear on read enable - - */ - /*! \brief 1E.5002.B R/W MSS Egress Clear Counter - AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressClearCounter - - Default = 0x0 - - 1 = Clear all MIB counters - - - - Notes: - If this bit is set to 1, all MIB counters will be cleared. */ - unsigned int mssEgressClearCounter : 1; /* 1E.5002.B R/W Default = 0x0 */ - /* 1 = Clear all MIB counters - - */ - /*! \brief 1E.5002.C R/W MSS Egress Clear Global Time - AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressClearGlobalTime - - Default = 0x0 - - 1 = Clear global time - - - - Notes: - Clear global time. */ - unsigned int mssEgressClearGlobalTime : 1; /* 1E.5002.C R/W Default = 0x0 */ - /* 1 = Clear global time - - */ - /*! \brief 1E.5002.F:D R/W MSS Egress Ethertype Explicit SECTag LSB [2:0] - AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressEthertypeExplicitSectagLsb - - Default = 0x0 - - Ethertype for explicit SECTag bits 2:0. - - - Notes: - Ethertype for explicity SECTag. */ - unsigned int mssEgressEthertypeExplicitSectagLsb : 3; /* 1E.5002.F:D R/W Default = 0x0 */ - /* Ethertype for explicit SECTag bits 2:0. - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Egress Control Register */ - union - { - struct - { - /*! \brief 1E.5003.C:0 R/W MSS Egress Ethertype Explicit SECTag MSB [F:3] - AQ_MssEgressControlRegister_HHD.u1.bits_1.mssEgressEthertypeExplicitSectagMsb - - Default = 0x0000 - - Ethertype for explicit SECTag bits 15:3. - - - Notes: - Ethertype for explicity SECTag. */ - unsigned int mssEgressEthertypeExplicitSectagMsb : 13; /* 1E.5003.C:0 R/W Default = 0x0000 */ - /* Ethertype for explicit SECTag bits 15:3. - */ - unsigned int reserved0 : 3; - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssEgressControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Egress VLAN TPID 0 Register: 1E.5008 */ -/* MSS Egress VLAN TPID 0 Register: 1E.5008 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Egress VLAN TPID 0 Register */ - union - { - struct - { - /*! \brief 1E.5008.F:0 R/W MSS Egress VLAN STag TPID [F:0] - AQ_MssEgressVlanTpid_0Register_HHD.u0.bits_0.mssEgressVlanStagTpid - - Default = 0x0000 - - STag TPID - - - Notes: - Service Tag Protocol Identifier (TPID) values to identify a VLAN tag. The " See SEC Egress VLAN CP Tag Parse STag " bit must be set to 1 for the incoming packet's TPID to be parsed. */ - unsigned int mssEgressVlanStagTpid : 16; /* 1E.5008.F:0 R/W Default = 0x0000 */ - /* STag TPID - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Egress VLAN TPID 0 Register */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssEgressVlanTpid_0Register_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Egress VLAN TPID 1 Register: 1E.500A */ -/* MSS Egress VLAN TPID 1 Register: 1E.500A */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Egress VLAN TPID 1 Register */ - union - { - struct - { - /*! \brief 1E.500A.F:0 R/W MSS Egress VLAN QTag TPID [F:0] - AQ_MssEgressVlanTpid_1Register_HHD.u0.bits_0.mssEgressVlanQtagTpid - - Default = 0x0000 - - QTag TPID - - - Notes: - Customer Tag Protocol Identifier (TPID) values to identify a VLAN tag. The " See SEC Egress VLAN CP Tag Parse QTag " bit must be set to 1 for the incoming packet's TPID to be parsed. */ - unsigned int mssEgressVlanQtagTpid : 16; /* 1E.500A.F:0 R/W Default = 0x0000 */ - /* QTag TPID - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Egress VLAN TPID 1 Register */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssEgressVlanTpid_1Register_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Egress VLAN Control Register: 1E.500C */ -/* MSS Egress VLAN Control Register: 1E.500C */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Egress VLAN Control Register */ - union - { - struct - { - /*! \brief 1E.500C.F:0 R/W MSS Egress VLAN UP Map Table [F:0] - AQ_MssEgressVlanControlRegister_HHD.u0.bits_0.mssEgressVlanUpMapTable - - Default = 0x0000 - - UP Map table bits 15:0 - - - Notes: - If there is a customer TPID Tag match and no service TPID Tag match or the service TPID Tag match is disabled, the outer TAG's PCP is used to index into this map table to generate the packets user priority. - 2:0 : UP value for customer Tag PCP 0x0 - 5:3: UP value for customer Tag PCP 0x0 - 8:6 : UP value for customer Tag PCP 0x0 - 11:9 : UP value for customer Tag PCP 0x0 - 14:12 : UP value for customer Tag PCP 0x0 - 17:15 : UP value for customer Tag PCP 0x0 - 20:18 : UP value for customer Tag PCP 0x0 - 23:21 : UP value for customer Tag PCP 0x0 */ - unsigned int mssEgressVlanUpMapTable : 16; /* 1E.500C.F:0 R/W Default = 0x0000 */ - /* UP Map table bits 15:0 - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Egress VLAN Control Register */ - union - { - struct - { - /*! \brief 1E.500D.7:0 R/W MSS Egress VLAN UP Map Table MSW [17:10] - AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanUpMapTableMSW - - Default = 0x00 - - UP Map table bits 23:16 - - - Notes: - If there is a customer TPID Tag match and no service TPID Tag match or the service TPID Tag match is disabled, the outer TAG's PCP is used to index into this map table to generate the packets user priority. - 2:0 : UP value for customer Tag PCP 0x0 - 5:3: UP value for customer Tag PCP 0x0 - 8:6 : UP value for customer Tag PCP 0x0 - 11:9 : UP value for customer Tag PCP 0x0 - 14:12 : UP value for customer Tag PCP 0x0 - 17:15 : UP value for customer Tag PCP 0x0 - 20:18 : UP value for customer Tag PCP 0x0 - 23:21 : UP value for customer Tag PCP 0x0 */ - unsigned int mssEgressVlanUpMapTableMSW : 8; /* 1E.500D.7:0 R/W Default = 0x00 */ - /* UP Map table bits 23:16 - */ - /*! \brief 1E.500D.A:8 R/W MSS Egress VLAN UP Default [2:0] - AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanUpDefault - - Default = 0x0 - - UP default - - - Notes: - User priority default */ - unsigned int mssEgressVlanUpDefault : 3; /* 1E.500D.A:8 R/W Default = 0x0 */ - /* UP default - */ - /*! \brief 1E.500D.B R/W MSS Egress VLAN STag UP Parse Enable - AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanStagUpParseEnable - - Default = 0x0 - - VLAN CP Tag STag UP enable - - - Notes: - Enable controlled port service VLAN service Tag user priority field parsing. */ - unsigned int mssEgressVlanStagUpParseEnable : 1; /* 1E.500D.B R/W Default = 0x0 */ - /* VLAN CP Tag STag UP enable - */ - /*! \brief 1E.500D.C R/W MSS Egress VLAN QTag UP Parse Enable - AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanQtagUpParseEnable - - Default = 0x0 - - VLAN CP Tag QTag UP enable - - - Notes: - Enable controlled port customer VLAN customer Tag user priority field parsing. */ - unsigned int mssEgressVlanQtagUpParseEnable : 1; /* 1E.500D.C R/W Default = 0x0 */ - /* VLAN CP Tag QTag UP enable - */ - /*! \brief 1E.500D.D R/W MSS Egress VLAN QinQ Parse Enable - AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanQinqParseEnable - - Default = 0x0 - - VLAN CP Tag Parse QinQ - - - Notes: - Enable controlled port VLAN QinQ Tag parsing. When this bit is set to 1 both the outer and inner VLAN Tags will be parsed. */ - unsigned int mssEgressVlanQinqParseEnable : 1; /* 1E.500D.D R/W Default = 0x0 */ - /* VLAN CP Tag Parse QinQ - */ - /*! \brief 1E.500D.E R/W MSS Egress VLAN STag Parse Enable - AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanStagParseEnable - - Default = 0x0 - - 1 = Enable VLAN STag parsing - - - Notes: - Enable controlled port VLAN service Tag parsing. When this bit is set to 1, the incoming packets outer TPID will be compared with the configured " See SEC Egress TPID 0 [F:0] " for matching. If the " See SEC Egress VLAN CP Tag Parse QinQ " bit is set to1, this will also be used to compare the incoming packet's inner TPID. */ - unsigned int mssEgressVlanStagParseEnable : 1; /* 1E.500D.E R/W Default = 0x0 */ - /* 1 = Enable VLAN STag parsing - */ - /*! \brief 1E.500D.F R/W MSS Egress VLAN QTag Parse Enable - AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanQtagParseEnable - - Default = 0x0 - - 1 = Enable VLAN QTag parsing - - - Notes: - Enable controlled port VLAN customer Tag parsing. When this bit is set to 1, the incoming packet's outer TPID will be compared with the configured " See SEC Egress TPID 1 [F:0] " for matching. If the " See SEC Egress VLAN CP Tag Parse QinQ " bit is set to1, this will also be used to compare the incoming packet's inner TPID. */ - unsigned int mssEgressVlanQtagParseEnable : 1; /* 1E.500D.F R/W Default = 0x0 */ - /* 1 = Enable VLAN QTag parsing - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssEgressVlanControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Egress PN Control Register: 1E.500E */ -/* MSS Egress PN Control Register: 1E.500E */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Egress PN Control Register */ - union - { - struct - { - /*! \brief 1E.500E.F:0 R/W MSS Egress SA PN Threshold LSW [F:0] - AQ_MssEgressPnControlRegister_HHD.u0.bits_0.mssEgressSaPnThresholdLSW - - Default = 0x0000 - - PN threshold bits 15:0 - - - Notes: - Egress PN threshold to generate SA threshold interrupt. */ - unsigned int mssEgressSaPnThresholdLSW : 16; /* 1E.500E.F:0 R/W Default = 0x0000 */ - /* PN threshold bits 15:0 - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Egress PN Control Register */ - union - { - struct - { - /*! \brief 1E.500F.F:0 R/W MSS Egress SA PN Threshold MSW [1F:10] - AQ_MssEgressPnControlRegister_HHD.u1.bits_1.mssEgressSaPnThresholdMSW - - Default = 0x0000 - - PN threshold bits 31:16 - - - Notes: - Egress PN threshold to generate SA threshold interrupt. */ - unsigned int mssEgressSaPnThresholdMSW : 16; /* 1E.500F.F:0 R/W Default = 0x0000 */ - /* PN threshold bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssEgressPnControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Egress MTU Size Control Register: 1E.5010 */ -/* MSS Egress MTU Size Control Register: 1E.5010 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Egress MTU Size Control Register */ - union - { - struct - { - /*! \brief 1E.5010.F:0 R/W MSS Egress Controlled Packet MTU Size [F:0] - AQ_MssEgressMtuSizeControlRegister_HHD.u0.bits_0.mssEgressControlledPacketMtuSize - - Default = 0x05DC - - Maximum transmission unit for controlled packet - - - Notes: - Maximum transmission unit of controlled packet */ - unsigned int mssEgressControlledPacketMtuSize : 16; /* 1E.5010.F:0 R/W Default = 0x05DC */ - /* Maximum transmission unit for controlled packet - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Egress MTU Size Control Register */ - union - { - struct - { - /*! \brief 1E.5011.F:0 R/W MSS Egress Uncontrolled Packet MTU Size [F:0] - AQ_MssEgressMtuSizeControlRegister_HHD.u1.bits_1.mssEgressUncontrolledPacketMtuSize - - Default = 0x05DC - - Maximum transmission unit for uncontrolled packet - - - Notes: - Maximum transmission unit of uncontrolled packet */ - unsigned int mssEgressUncontrolledPacketMtuSize : 16; /* 1E.5011.F:0 R/W Default = 0x05DC */ - /* Maximum transmission unit for uncontrolled packet - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssEgressMtuSizeControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Egress Interrupt Status Register: 1E.505C */ -/* MSS Egress Interrupt Status Register: 1E.505C */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Egress Interrupt Status Register */ - union - { - struct - { - /*! \brief 1E.505C.0 COW MSS Egress Master Interrupt - AQ_MssEgressInterruptStatusRegister_HHD.u0.bits_0.mssEgressMasterInterrupt - - Default = 0x0 - - 1 = Interrupt - - - Notes: - Write to 1 to clear. This bit is set when any one of the above interrupt and the corresponding interrupt enable are both set. The interrupt enable for this bit must also be set for this bit to be set. */ - unsigned int mssEgressMasterInterrupt : 1; /* 1E.505C.0 COW Default = 0x0 */ - /* 1 = Interrupt - */ - /*! \brief 1E.505C.1 COW MSS Egress SA Expired Interrupt - AQ_MssEgressInterruptStatusRegister_HHD.u0.bits_0.mssEgressSaExpiredInterrupt - - Default = 0x0 - - 1 = Interrupt - - - Notes: - Write to 1 to clear. This bit is set when the SA PN reaches all ones saturation. */ - unsigned int mssEgressSaExpiredInterrupt : 1; /* 1E.505C.1 COW Default = 0x0 */ - /* 1 = Interrupt - */ - /*! \brief 1E.505C.2 COW MSS Egress SA Threshold Expired Interrupt - AQ_MssEgressInterruptStatusRegister_HHD.u0.bits_0.mssEgressSaThresholdExpiredInterrupt - - Default = 0x0 - - 1 = Interrupt - - - Notes: - Write to 1 to clear. This bit is set when the SA PN reaches the See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . */ - unsigned int mssEgressSaThresholdExpiredInterrupt : 1; /* 1E.505C.2 COW Default = 0x0 */ - /* 1 = Interrupt - */ - /*! \brief 1E.505C.3 COW MSS Egress MIB Saturation Interrupt - AQ_MssEgressInterruptStatusRegister_HHD.u0.bits_0.mssEgressMibSaturationInterrupt - - Default = 0x0 - - 1 = Interrupt - - - Notes: - Write to 1 to clear. This bit is set when the MIB counters reaches all ones saturation. */ - unsigned int mssEgressMibSaturationInterrupt : 1; /* 1E.505C.3 COW Default = 0x0 */ - /* 1 = Interrupt - */ - /*! \brief 1E.505C.4 COW MSS Egress ECC Error Interrupt - AQ_MssEgressInterruptStatusRegister_HHD.u0.bits_0.mssEgressEccErrorInterrupt - - Default = 0x0 - - 1 = Interrupt - - - Notes: - Write to 1 to clear. This bit is set when anyone of the memories detects an ECC error. */ - unsigned int mssEgressEccErrorInterrupt : 1; /* 1E.505C.4 COW Default = 0x0 */ - /* 1 = Interrupt - */ - unsigned int reserved0 : 11; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Egress Interrupt Status Register */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssEgressInterruptStatusRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Egress Interrupt Mask Register: 1E.505E */ -/* MSS Egress Interrupt Mask Register: 1E.505E */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Egress Interrupt Mask Register */ - union - { - struct - { - /*! \brief 1E.505E.0 COW MSS Egress Master Interrupt Enable - AQ_MssEgressInterruptMaskRegister_HHD.u0.bits_0.mssEgressMasterInterruptEnable - - Default = 0x0 - - 1 = Interrupt enabled - - - Notes: - Write to 1 to clear. */ - unsigned int mssEgressMasterInterruptEnable : 1; /* 1E.505E.0 COW Default = 0x0 */ - /* 1 = Interrupt enabled - */ - /*! \brief 1E.505E.1 COW MSS Egress SA Expired Interrupt Enable - AQ_MssEgressInterruptMaskRegister_HHD.u0.bits_0.mssEgressSaExpiredInterruptEnable - - Default = 0x0 - - 1 = Interrupt enabled - - - Notes: - Write to 1 to clear. This bit is set when the SA PN reaches all ones saturation. */ - unsigned int mssEgressSaExpiredInterruptEnable : 1; /* 1E.505E.1 COW Default = 0x0 */ - /* 1 = Interrupt enabled - */ - /*! \brief 1E.505E.2 COW MSS Egress SA Expired Threshold Interrupt Enable - AQ_MssEgressInterruptMaskRegister_HHD.u0.bits_0.mssEgressSaExpiredThresholdInterruptEnable - - Default = 0x0 - - 1 = Interrupt enabled - - - Notes: - Write to 1 to clear. This bit is set when the SA PN reaches the configured threshold See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . */ - unsigned int mssEgressSaExpiredThresholdInterruptEnable : 1; /* 1E.505E.2 COW Default = 0x0 */ - /* 1 = Interrupt enabled - */ - /*! \brief 1E.505E.3 COW MSS Egress MIB Saturation Interrupt Enable - AQ_MssEgressInterruptMaskRegister_HHD.u0.bits_0.mssEgressMibSaturationInterruptEnable - - Default = 0x0 - - 1 = Interrupt enabled - - - Notes: - Write to 1 to clear. This bit is set when the MIB counters reaches all ones saturation. */ - unsigned int mssEgressMibSaturationInterruptEnable : 1; /* 1E.505E.3 COW Default = 0x0 */ - /* 1 = Interrupt enabled - */ - /*! \brief 1E.505E.4 COW MSS Egress ECC Error Interrupt Enable - AQ_MssEgressInterruptMaskRegister_HHD.u0.bits_0.mssEgressEccErrorInterruptEnable - - Default = 0x0 - - 1 = Interrupt enabled - - - Notes: - Write to 1 to clear. This bit is set when anyone of the memories detects an ECC error. */ - unsigned int mssEgressEccErrorInterruptEnable : 1; /* 1E.505E.4 COW Default = 0x0 */ - /* 1 = Interrupt enabled - */ - unsigned int reserved0 : 11; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Egress Interrupt Mask Register */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssEgressInterruptMaskRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Egress SA Expired Status Register: 1E.5060 */ -/* MSS Egress SA Expired Status Register: 1E.5060 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Egress SA Expired Status Register */ - union - { - struct - { - /*! \brief 1E.5060.F:0 COW MSS Egress SA Expired LSW [F:0] - AQ_MssEgressSaExpiredStatusRegister_HHD.u0.bits_0.mssEgressSaExpiredLSW - - Default = 0x0000 - - SA expired bits 15:0 - - - Notes: - Write these bits to 1 to clear. - When set, these bits identify the SA that has expired when the SA PN reaches all-ones saturation. */ - unsigned int mssEgressSaExpiredLSW : 16; /* 1E.5060.F:0 COW Default = 0x0000 */ - /* SA expired bits 15:0 - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Egress SA Expired Status Register */ - union - { - struct - { - /*! \brief 1E.5061.F:0 COW MSS Egress SA Expired MSW [1F:10] - AQ_MssEgressSaExpiredStatusRegister_HHD.u1.bits_1.mssEgressSaExpiredMSW - - Default = 0x0000 - - SA expired bits 31:16 - - - Notes: - Write these bits to 1 to clear. - When set, these bits identify the SA that has expired when the SA PN reaches all-ones saturation. */ - unsigned int mssEgressSaExpiredMSW : 16; /* 1E.5061.F:0 COW Default = 0x0000 */ - /* SA expired bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssEgressSaExpiredStatusRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Egress SA Threshold Expired Status Register: 1E.5062 */ -/* MSS Egress SA Threshold Expired Status Register: 1E.5062 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Egress SA Threshold Expired Status Register */ - union - { - struct - { - /*! \brief 1E.5062.F:0 COW MSS Egress SA Threshold Expired LSW [F:0] - AQ_MssEgressSaThresholdExpiredStatusRegister_HHD.u0.bits_0.mssEgressSaThresholdExpiredLSW - - Default = 0x0000 - - SA threshold expired bits 15:0 - - - Notes: - Write these bits to 1 to clear. - When set, these bits identify the SA that has expired when the SA PN has reached the configured threshold See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . */ - unsigned int mssEgressSaThresholdExpiredLSW : 16; /* 1E.5062.F:0 COW Default = 0x0000 */ - /* SA threshold expired bits 15:0 - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Egress SA Threshold Expired Status Register */ - union - { - struct - { - /*! \brief 1E.5063.F:0 COW MSS Egress SA Threshold Expired MSW [1F:10] - AQ_MssEgressSaThresholdExpiredStatusRegister_HHD.u1.bits_1.mssEgressSaThresholdExpiredMSW - - Default = 0x0000 - - SA threshold expired bits 31:16 - - - Notes: - Write these bits to 1 to clear. - When set, these bits identify the SA that has expired when the SA PN has reached the configured threshold See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . */ - unsigned int mssEgressSaThresholdExpiredMSW : 16; /* 1E.5063.F:0 COW Default = 0x0000 */ - /* SA threshold expired bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssEgressSaThresholdExpiredStatusRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Egress ECC Interrupt Status Register: 1E.5064 */ -/* MSS Egress ECC Interrupt Status Register: 1E.5064 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Egress ECC Interrupt Status Register */ - union - { - struct - { - /*! \brief 1E.5064.F:0 COW MSS Egress SA ECC Error Interrupt LSW [F:0] - AQ_MssEgressEccInterruptStatusRegister_HHD.u0.bits_0.mssEgressSaEccErrorInterruptLSW - - Default = 0x0000 - - SA ECC error interrupt bits 15:0 - - - Notes: - Write these bits to 1 to clear. - When set to 1, indicates that an ECC error occured for the SA. */ - unsigned int mssEgressSaEccErrorInterruptLSW : 16; /* 1E.5064.F:0 COW Default = 0x0000 */ - /* SA ECC error interrupt bits 15:0 - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Egress ECC Interrupt Status Register */ - union - { - struct - { - /*! \brief 1E.5065.F:0 COW MSS Egress SA ECC Error Interrupt MSW [1F:10] - AQ_MssEgressEccInterruptStatusRegister_HHD.u1.bits_1.mssEgressSaEccErrorInterruptMSW - - Default = 0x0000 - - SA ECC error interrupt bits 31:16 - - - Notes: - Write these bits to 1 to clear. - When set to 1, indicates that an ECC error occured for the SA. */ - unsigned int mssEgressSaEccErrorInterruptMSW : 16; /* 1E.5065.F:0 COW Default = 0x0000 */ - /* SA ECC error interrupt bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssEgressEccInterruptStatusRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Egress LUT Address Control Register: 1E.5080 */ -/* MSS Egress LUT Address Control Register: 1E.5080 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Egress LUT Address Control Register */ - union - { - struct - { - /*! \brief 1E.5080.8:0 R/W MSS Egress LUT Address [8:0] - AQ_MssEgressLutAddressControlRegister_HHD.u0.bits_0.mssEgressLutAddress - - Default = 0x000 - - LUT address - - */ - unsigned int mssEgressLutAddress : 9; /* 1E.5080.8:0 R/W Default = 0x000 */ - /* LUT address - */ - unsigned int reserved0 : 3; - /*! \brief 1E.5080.F:C R/W MSS Egress LUT Select [3:0] - AQ_MssEgressLutAddressControlRegister_HHD.u0.bits_0.mssEgressLutSelect - - Default = 0x0 - - LUT select - - - Notes: - 0x0 : Egress MAC Control FIlter (CTLF) LUT - 0x1 : Egress Classification LUT - 0x2 : Egress SC/SA LUT - 0x3 : Egress SMIB */ - unsigned int mssEgressLutSelect : 4; /* 1E.5080.F:C R/W Default = 0x0 */ - /* LUT select - */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_MssEgressLutAddressControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Egress LUT Control Register: 1E.5081 */ -/* MSS Egress LUT Control Register: 1E.5081 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Egress LUT Control Register */ - union - { - struct - { - unsigned int reserved0 : 14; - /*! \brief 1E.5081.E R/W MSS Egress LUT Read - AQ_MssEgressLutControlRegister_HHD.u0.bits_0.mssEgressLutRead - - Default = 0x0 - - 1 = LUT read - - - Notes: - Setting this bit to 1, will read the LUT. This bit will automatically clear to 0. */ - unsigned int mssEgressLutRead : 1; /* 1E.5081.E R/W Default = 0x0 */ - /* 1 = LUT read - */ - /*! \brief 1E.5081.F R/W MSS Egress LUT Write - AQ_MssEgressLutControlRegister_HHD.u0.bits_0.mssEgressLutWrite - - Default = 0x0 - - 1 = LUT write - - - Notes: - Setting this bit to 1, will write the LUT. This bit will automatically clear to 0. */ - unsigned int mssEgressLutWrite : 1; /* 1E.5081.F R/W Default = 0x0 */ - /* 1 = LUT write - */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_MssEgressLutControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Egress LUT Data Control Register: 1E.50A0 */ -/* MSS Egress LUT Data Control Register: 1E.50A0 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50A0.F:0 R/W MSS Egress LUT Data 0 [F:0] - AQ_MssEgressLutDataControlRegister_HHD.u0.bits_0.mssEgressLutData_0 - - Default = 0x0000 - - LUT data bits 15:0 - - */ - unsigned int mssEgressLutData_0 : 16; /* 1E.50A0.F:0 R/W Default = 0x0000 */ - /* LUT data bits 15:0 - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50A1.F:0 R/W MSS Egress LUT Data 1 [1F:10] - AQ_MssEgressLutDataControlRegister_HHD.u1.bits_1.mssEgressLutData_1 - - Default = 0x0000 - - LUT data bits 31:16 - - */ - unsigned int mssEgressLutData_1 : 16; /* 1E.50A1.F:0 R/W Default = 0x0000 */ - /* LUT data bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50A2.F:0 R/W MSS Egress LUT Data 2 [2F:20] - AQ_MssEgressLutDataControlRegister_HHD.u2.bits_2.mssEgressLutData_2 - - Default = 0x0000 - - LUT data bits 47:32 - - */ - unsigned int mssEgressLutData_2 : 16; /* 1E.50A2.F:0 R/W Default = 0x0000 */ - /* LUT data bits 47:32 - */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50A3.F:0 R/W MSS Egress LUT Data 3 [3F:30] - AQ_MssEgressLutDataControlRegister_HHD.u3.bits_3.mssEgressLutData_3 - - Default = 0x0000 - - LUT data bits 63:48 - - */ - unsigned int mssEgressLutData_3 : 16; /* 1E.50A3.F:0 R/W Default = 0x0000 */ - /* LUT data bits 63:48 - */ - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50A4.F:0 R/W MSS Egress LUT Data 4 [4F:40] - AQ_MssEgressLutDataControlRegister_HHD.u4.bits_4.mssEgressLutData_4 - - Default = 0x0000 - - LUT data bits 79:64 - - */ - unsigned int mssEgressLutData_4 : 16; /* 1E.50A4.F:0 R/W Default = 0x0000 */ - /* LUT data bits 79:64 - */ - } bits_4; - uint16_t word_4; - } u4; - /*! \brief Union for bit and word level access of word 5 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50A5.F:0 R/W MSS Egress LUT Data 5 [5F:50] - AQ_MssEgressLutDataControlRegister_HHD.u5.bits_5.mssEgressLutData_5 - - Default = 0x0000 - - LUT data bits 95:80 - - */ - unsigned int mssEgressLutData_5 : 16; /* 1E.50A5.F:0 R/W Default = 0x0000 */ - /* LUT data bits 95:80 - */ - } bits_5; - uint16_t word_5; - } u5; - /*! \brief Union for bit and word level access of word 6 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50A6.F:0 R/W MSS Egress LUT Data 6 [6F:60] - AQ_MssEgressLutDataControlRegister_HHD.u6.bits_6.mssEgressLutData_6 - - Default = 0x0000 - - LUT data bits 111:96 - - */ - unsigned int mssEgressLutData_6 : 16; /* 1E.50A6.F:0 R/W Default = 0x0000 */ - /* LUT data bits 111:96 - */ - } bits_6; - uint16_t word_6; - } u6; - /*! \brief Union for bit and word level access of word 7 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50A7.F:0 R/W MSS Egress LUT Data 7 [7F:70] - AQ_MssEgressLutDataControlRegister_HHD.u7.bits_7.mssEgressLutData_7 - - Default = 0x0000 - - LUT data bits 127:112 - - */ - unsigned int mssEgressLutData_7 : 16; /* 1E.50A7.F:0 R/W Default = 0x0000 */ - /* LUT data bits 127:112 - */ - } bits_7; - uint16_t word_7; - } u7; - /*! \brief Union for bit and word level access of word 8 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50A8.F:0 R/W MSS Egress LUT Data 8 [8F:80] - AQ_MssEgressLutDataControlRegister_HHD.u8.bits_8.mssEgressLutData_8 - - Default = 0x0000 - - LUT data bits 143:128 - - */ - unsigned int mssEgressLutData_8 : 16; /* 1E.50A8.F:0 R/W Default = 0x0000 */ - /* LUT data bits 143:128 - */ - } bits_8; - uint16_t word_8; - } u8; - /*! \brief Union for bit and word level access of word 9 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50A9.F:0 R/W MSS Egress LUT Data 9 [9F:90] - AQ_MssEgressLutDataControlRegister_HHD.u9.bits_9.mssEgressLutData_9 - - Default = 0x0000 - - LUT data bits 159:144 - - */ - unsigned int mssEgressLutData_9 : 16; /* 1E.50A9.F:0 R/W Default = 0x0000 */ - /* LUT data bits 159:144 - */ - } bits_9; - uint16_t word_9; - } u9; - /*! \brief Union for bit and word level access of word 10 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50AA.F:0 R/W MSS Egress LUT Data 10 [AF:A0] - AQ_MssEgressLutDataControlRegister_HHD.u10.bits_10.mssEgressLutData_10 - - Default = 0x0000 - - LUT data bits 175:160 - - */ - unsigned int mssEgressLutData_10 : 16; /* 1E.50AA.F:0 R/W Default = 0x0000 */ - /* LUT data bits 175:160 - */ - } bits_10; - uint16_t word_10; - } u10; - /*! \brief Union for bit and word level access of word 11 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50AB.F:0 R/W MSS Egress LUT Data 11 [BF:B0] - AQ_MssEgressLutDataControlRegister_HHD.u11.bits_11.mssEgressLutData_11 - - Default = 0x0000 - - LUT data bits 191:176 - - */ - unsigned int mssEgressLutData_11 : 16; /* 1E.50AB.F:0 R/W Default = 0x0000 */ - /* LUT data bits 191:176 - */ - } bits_11; - uint16_t word_11; - } u11; - /*! \brief Union for bit and word level access of word 12 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50AC.F:0 R/W MSS Egress LUT Data 12 [CF:C0] - AQ_MssEgressLutDataControlRegister_HHD.u12.bits_12.mssEgressLutData_12 - - Default = 0x0000 - - LUT data bits 207:192 - - */ - unsigned int mssEgressLutData_12 : 16; /* 1E.50AC.F:0 R/W Default = 0x0000 */ - /* LUT data bits 207:192 - */ - } bits_12; - uint16_t word_12; - } u12; - /*! \brief Union for bit and word level access of word 13 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50AD.F:0 R/W MSS Egress LUT Data 13 [DF:D0] - AQ_MssEgressLutDataControlRegister_HHD.u13.bits_13.mssEgressLutData_13 - - Default = 0x0000 - - LUT data bits 223:208 - - */ - unsigned int mssEgressLutData_13 : 16; /* 1E.50AD.F:0 R/W Default = 0x0000 */ - /* LUT data bits 223:208 - */ - } bits_13; - uint16_t word_13; - } u13; - /*! \brief Union for bit and word level access of word 14 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50AE.F:0 R/W MSS Egress LUT Data 14 [EF:E0] - AQ_MssEgressLutDataControlRegister_HHD.u14.bits_14.mssEgressLutData_14 - - Default = 0x0000 - - LUT data bits 239:224 - - */ - unsigned int mssEgressLutData_14 : 16; /* 1E.50AE.F:0 R/W Default = 0x0000 */ - /* LUT data bits 239:224 - */ - } bits_14; - uint16_t word_14; - } u14; - /*! \brief Union for bit and word level access of word 15 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50AF.F:0 R/W MSS Egress LUT Data 15 [FF:F0] - AQ_MssEgressLutDataControlRegister_HHD.u15.bits_15.mssEgressLutData_15 - - Default = 0x0000 - - LUT data bits 255:240 - - */ - unsigned int mssEgressLutData_15 : 16; /* 1E.50AF.F:0 R/W Default = 0x0000 */ - /* LUT data bits 255:240 - */ - } bits_15; - uint16_t word_15; - } u15; - /*! \brief Union for bit and word level access of word 16 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50B0.F:0 R/W MSS Egress LUT Data 16 [10F:100] - AQ_MssEgressLutDataControlRegister_HHD.u16.bits_16.mssEgressLutData_16 - - Default = 0x0000 - - LUT data bits 271:256 - - */ - unsigned int mssEgressLutData_16 : 16; /* 1E.50B0.F:0 R/W Default = 0x0000 */ - /* LUT data bits 271:256 - */ - } bits_16; - uint16_t word_16; - } u16; - /*! \brief Union for bit and word level access of word 17 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50B1.F:0 R/W MSS Egress LUT Data 17 [11F:110] - AQ_MssEgressLutDataControlRegister_HHD.u17.bits_17.mssEgressLutData_17 - - Default = 0x0000 - - LUT data bits 287:272 - - */ - unsigned int mssEgressLutData_17 : 16; /* 1E.50B1.F:0 R/W Default = 0x0000 */ - /* LUT data bits 287:272 - */ - } bits_17; - uint16_t word_17; - } u17; - /*! \brief Union for bit and word level access of word 18 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50B2.F:0 R/W MSS Egress LUT Data 18 [12F:120] - AQ_MssEgressLutDataControlRegister_HHD.u18.bits_18.mssEgressLutData_18 - - Default = 0x0000 - - LUT data bits 303:288 - - */ - unsigned int mssEgressLutData_18 : 16; /* 1E.50B2.F:0 R/W Default = 0x0000 */ - /* LUT data bits 303:288 - */ - } bits_18; - uint16_t word_18; - } u18; - /*! \brief Union for bit and word level access of word 19 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50B3.F:0 R/W MSS Egress LUT Data 19 [13F:130] - AQ_MssEgressLutDataControlRegister_HHD.u19.bits_19.mssEgressLutData_19 - - Default = 0x0000 - - LUT data bits 319:304 - - */ - unsigned int mssEgressLutData_19 : 16; /* 1E.50B3.F:0 R/W Default = 0x0000 */ - /* LUT data bits 319:304 - */ - } bits_19; - uint16_t word_19; - } u19; - /*! \brief Union for bit and word level access of word 20 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50B4.F:0 R/W MSS Egress LUT Data 20 [14F:140] - AQ_MssEgressLutDataControlRegister_HHD.u20.bits_20.mssEgressLutData_20 - - Default = 0x0000 - - LUT data bits 335:320 - - */ - unsigned int mssEgressLutData_20 : 16; /* 1E.50B4.F:0 R/W Default = 0x0000 */ - /* LUT data bits 335:320 - */ - } bits_20; - uint16_t word_20; - } u20; - /*! \brief Union for bit and word level access of word 21 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50B5.F:0 R/W MSS Egress LUT Data 21 [15F:150] - AQ_MssEgressLutDataControlRegister_HHD.u21.bits_21.mssEgressLutData_21 - - Default = 0x0000 - - LUT data bits 351:336 - - */ - unsigned int mssEgressLutData_21 : 16; /* 1E.50B5.F:0 R/W Default = 0x0000 */ - /* LUT data bits 351:336 - */ - } bits_21; - uint16_t word_21; - } u21; - /*! \brief Union for bit and word level access of word 22 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50B6.F:0 R/W MSS Egress LUT Data 22 [16F:160] - AQ_MssEgressLutDataControlRegister_HHD.u22.bits_22.mssEgressLutData_22 - - Default = 0x0000 - - LUT data bits 367:352 - - */ - unsigned int mssEgressLutData_22 : 16; /* 1E.50B6.F:0 R/W Default = 0x0000 */ - /* LUT data bits 367:352 - */ - } bits_22; - uint16_t word_22; - } u22; - /*! \brief Union for bit and word level access of word 23 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50B7.F:0 R/W MSS Egress LUT Data 23 [17F:170] - AQ_MssEgressLutDataControlRegister_HHD.u23.bits_23.mssEgressLutData_23 - - Default = 0x0000 - - LUT data bits 383:368 - - */ - unsigned int mssEgressLutData_23 : 16; /* 1E.50B7.F:0 R/W Default = 0x0000 */ - /* LUT data bits 383:368 - */ - } bits_23; - uint16_t word_23; - } u23; - /*! \brief Union for bit and word level access of word 24 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50B8.F:0 R/W MSS Egress LUT Data 24 [18F:180] - AQ_MssEgressLutDataControlRegister_HHD.u24.bits_24.mssEgressLutData_24 - - Default = 0x0000 - - LUT data bits 399:384 - - */ - unsigned int mssEgressLutData_24 : 16; /* 1E.50B8.F:0 R/W Default = 0x0000 */ - /* LUT data bits 399:384 - */ - } bits_24; - uint16_t word_24; - } u24; - /*! \brief Union for bit and word level access of word 25 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50B9.F:0 R/W MSS Egress LUT Data 25 [19F:190] - AQ_MssEgressLutDataControlRegister_HHD.u25.bits_25.mssEgressLutData_25 - - Default = 0x0000 - - LUT data bits 415:400 - - */ - unsigned int mssEgressLutData_25 : 16; /* 1E.50B9.F:0 R/W Default = 0x0000 */ - /* LUT data bits 415:400 - */ - } bits_25; - uint16_t word_25; - } u25; - /*! \brief Union for bit and word level access of word 26 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50BA.F:0 R/W MSS Egress LUT Data 26 [1AF:1A0] - AQ_MssEgressLutDataControlRegister_HHD.u26.bits_26.mssEgressLutData_26 - - Default = 0x0000 - - LUT data bits 431:416 - - */ - unsigned int mssEgressLutData_26 : 16; /* 1E.50BA.F:0 R/W Default = 0x0000 */ - /* LUT data bits 431:416 - */ - } bits_26; - uint16_t word_26; - } u26; - /*! \brief Union for bit and word level access of word 27 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50BB.F:0 R/W MSS Egress LUT Data 27 [1BF:1B0] - AQ_MssEgressLutDataControlRegister_HHD.u27.bits_27.mssEgressLutData_27 - - Default = 0x0000 - - LUT data bits 447:432 - - */ - unsigned int mssEgressLutData_27 : 16; /* 1E.50BB.F:0 R/W Default = 0x0000 */ - /* LUT data bits 447:432 - */ - } bits_27; - uint16_t word_27; - } u27; -} AQ_MssEgressLutDataControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System General Control Register: 1E.6004 */ -/* MSM System General Control Register: 1E.6004 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System General Control Register */ - union - { - struct - { - /*! \brief 1E.6004.0 R/W MSM System Tx Enable - AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemTxEnable - - Default = 0x0 - - 1 = Tx enable - - Notes: - MAC Rx path enable. Should be set to 1 to enable the MAC Rx path. Should be set to 0 to disable the MAC Rx path. */ - unsigned int msmSystemTxEnable : 1; /* 1E.6004.0 R/W Default = 0x0 */ - /* 1 = Tx enable */ - /*! \brief 1E.6004.1 R/W MSM System Rx Enable - AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemRxEnable - - Default = 0x0 - - 1 = Rx enable - - Notes: - MAC Tx path enable. Should be set to 1 to enable the MAC Tx path. Should be set to 0 to disable the MAC Tx path. */ - unsigned int msmSystemRxEnable : 1; /* 1E.6004.1 R/W Default = 0x0 */ - /* 1 = Rx enable */ - unsigned int reserved0 : 1; - /*! \brief 1E.6004.3 R/W MSM System WAN Mode - AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemWanMode - - Default = 0x0 - - 1 = WAN mode - 0 = LAN mode - - - Notes: - WAN mode enable. Sets WAN mode when set to 1 and LAN mode when set to 0. Note: When changing the mode, verifiy correct setting of the Tx IPG. */ - unsigned int msmSystemWanMode : 1; /* 1E.6004.3 R/W Default = 0x0 */ - /* 1 = WAN mode - 0 = LAN mode - */ - /*! \brief 1E.6004.4 R/W MSM System Promiscuous Mode - AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemPromiscuousMode - - Default = 0x0 - - 1 = Promiscuous mode - - - Notes: - When set to 1, all frames are received without any MAC address filtering. */ - unsigned int msmSystemPromiscuousMode : 1; /* 1E.6004.4 R/W Default = 0x0 */ - /* 1 = Promiscuous mode - */ - /*! \brief 1E.6004.5 R/W MSM System PAD Enable - AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemPadEnable - - Default = 0x0 - - 1 = Enable frame padding removal on Rx - - - Notes: - When set to 1, enable frame padding removal on the Rx path. If enabled, padding is removed before the frame is transferred to the MAC client application. If disabled, no padding is removed on the Rx by the MAC. - Note : On Tx, the MAC always adds padding as required. */ - unsigned int msmSystemPadEnable : 1; /* 1E.6004.5 R/W Default = 0x0 */ - /* 1 = Enable frame padding removal on Rx - */ - /*! \brief 1E.6004.6 R/W MSM System CRC Forward - AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemCrcForward - - Default = 0x0 - - 1 = Enable CRC forwarding - - - Notes: - When set to 1, the CRC field of the received frames is forwarded with the frame to the user application. If disabled, the CRC field is stripped from the frame. - Note : If padding is enabled ( See MAC PAD Enable set to 1), this bit is ignored. */ - unsigned int msmSystemCrcForward : 1; /* 1E.6004.6 R/W Default = 0x0 */ - /* 1 = Enable CRC forwarding - */ - /*! \brief 1E.6004.7 R/W MSM System Pause Forward - AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemPauseForward - - Default = 0x0 - - 1 = Enable Pause forwarding - - - Notes: - Terminate or forward pause frames. If set to 1, pause frames are forwarded to the user application. In normal mode, when set to 0, pause frames are terminated and discarded within the MAC. */ - unsigned int msmSystemPauseForward : 1; /* 1E.6004.7 R/W Default = 0x0 */ - /* 1 = Enable Pause forwarding - */ - /*! \brief 1E.6004.8 R/W MSM System Pause Ignore - AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemPauseIgnore - - Default = 0x0 - - 1 = Ignore pause frames - - - Notes: - Ignore pause frame quanta. If set to 1, received pause frames are ignored by the MAC. When set to 0, the Tx is stopped for the amount of time specified in the pause quanta received within the pause frame. */ - unsigned int msmSystemPauseIgnore : 1; /* 1E.6004.8 R/W Default = 0x0 */ - /* 1 = Ignore pause frames - */ - /*! \brief 1E.6004.9 R/W MSM System Tx Address Insert Enable - AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemTxAddressInsertEnable - - Default = 0x0 - - 1 = Insert Tx MAC source address - - - Notes: - Set the source MAC address on transmit. If set to 1, the MAC overwrites the source MAC address with the MAC programmed address in all transmitted frames. When set to 0, the source MAC address is transmitted unmodified from the MAC Tx client application. */ - unsigned int msmSystemTxAddressInsertEnable : 1; /* 1E.6004.9 R/W Default = 0x0 */ - /* 1 = Insert Tx MAC source address - */ - /*! \brief 1E.6004.A R/W MSM System Tx CRC Append - AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemTxCrcAppend - - Default = 0x0 - - 1 = Append Tx CRC - - - Notes: - Permanently enable CRC append on transmit. If set to 1, the Tx will append a CRC to all transmitted frames. If set to 0, CRC append can be controlled on a per frame basis using the pin ff_tx_crc. - This configuration bit is OR'ed with the external ff_tx_crc pin to instruct the Tx to append a CRC to transmitted frames. The ff_tx_crc pin is tied to 0. */ - unsigned int msmSystemTxCrcAppend : 1; /* 1E.6004.A R/W Default = 0x0 */ - /* 1 = Append Tx CRC - */ - /*! \brief 1E.6004.B R/W MSM System Tx Pad Enable - AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemTxPadEnable - - Default = 0x1 - - 1 = Enable Tx padding - - - Notes: - When set to 1, enable padding of frames in the Tx direction. When set to 0, the MAC will not extend frames from the application to a minimum of 64 bytes, allowing to transmit short frames (violating the Ethernet mimimum size requirements). Must be set to 1 for normal operation. */ - unsigned int msmSystemTxPadEnable : 1; /* 1E.6004.B R/W Default = 0x1 */ - /* 1 = Enable Tx padding - */ - /*! \brief 1E.6004.C R/WSC MSM System Soft Reset - AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemSoftReset - - Default = 0x0 - - 1 = Soft reset - - - Notes: - Software reset. Self clearing bit. When set to 1, resets all statistic counters as well as the Tx and Rx FIFOs. It should be issued after all traffic has been stopped as a result of clearing the Rx/Tx enable bits ( See MAC Rx Enable set to 0 and See MAC Tx Enable set to 0). - Note : Can lead to an Rx interface (ff_rx_xxx) violations to the application if the reset is issued in the middle of a receive frame transfer. Then the end of packet (assertion of ff_rx_eop) is lost and the application should be prepeared to handle this exception. */ - unsigned int msmSystemSoftReset : 1; /* 1E.6004.C R/WSC Default = 0x0 */ - /* 1 = Soft reset - */ - /*! \brief 1E.6004.D R/W MSM System Control Frame Enable - AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemControlFrameEnable - - Default = 0x0 - - 1 = Control frame enabled - - - Notes: - MAC control frame enable. When set to 1, the MAC control frames with any Opcode other than 0x0001 are accepted and forwarded to the client interface. When set to 0, MAC control frames with any opcode other than 0x0001 are silently discarded. */ - unsigned int msmSystemControlFrameEnable : 1; /* 1E.6004.D R/W Default = 0x0 */ - /* 1 = Control frame enabled - */ - /*! \brief 1E.6004.E R/W MSM System Rx Error Discard - AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemRxErrorDiscard - - Default = 0x0 - - 1 = Enable discard of received errored frames - - - Notes: - Rx errored frame discard enable. When set to 1, any frame received with an error is discarded and not forwarded to the client interface. When set to 0, errored frames are forwarded to the client interface with ff_rx_err asserted. - Note : It is recommended to set this bit to 1 only when store and forward operation is enabled (RX_SECTION_FULL TBD). */ - unsigned int msmSystemRxErrorDiscard : 1; /* 1E.6004.E R/W Default = 0x0 */ - /* 1 = Enable discard of received errored frames - */ - /*! \brief 1E.6004.F R/W MSM System PHY Tx Enable - AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemPhyTxEnable - - Default = 0x0 - - 1 = Enable PHY Tx - - - Notes: - Directly controls the phy_tx_ena pin. */ - unsigned int msmSystemPhyTxEnable : 1; /* 1E.6004.F R/W Default = 0x0 */ - /* 1 = Enable PHY Tx - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System General Control Register */ - union - { - struct - { - /*! \brief 1E.6005.0 R/W MSM System Force Send IDLE - AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemForceSendIdle - - Default = 0x0 - - 1 = Force send idle - - Notes: - When set to 1, suppress any frame transmissions and forces IDLE n the Tx interface instead of frames. This control affects the MAC reconciliation layer (RS) which acts after all MAC datapath has processed the frame. - Note : Does not have an effect on fault handling (i.e. reception of local fault will still cause transmit of remote fault). - Must be 0 for normal operation. */ - unsigned int msmSystemForceSendIdle : 1; /* 1E.6005.0 R/W Default = 0x0 */ - /* 1 = Force send idle */ - /*! \brief 1E.6005.1 R/W MSM System Length Check Disable - AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemLengthCheckDisable - - Default = 0x0 - - 1 = Disable length check - - Notes: - Payload length check disable. When set to 0, the MAC checks the frames payload length with the frame length/type field. When set to 1, the payload length check is disabled. */ - unsigned int msmSystemLengthCheckDisable : 1; /* 1E.6005.1 R/W Default = 0x0 */ - /* 1 = Disable length check */ - /*! \brief 1E.6005.2 R/W MSM System IDLE Column Count Extend - AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemIdleColumnCountExtend - - Default = 0x0 - - 1 = Extend IDLE column count - - Notes: - When set to 1, extends the RS layer IDLE column counter by 2x. The IEEE 802.3ae defines the fault condition to be cleared after 128 columns of IDLE have been received. If the MAC operates together with a WAN mode PCS (WIS) it may may happen (depending on PCS) that this period is too short to bridge the IDLE stuffing occurring in this mode, leading to a toggling fault indication. In this case, extending the counter helps to aoivd toggling fault indications. */ - unsigned int msmSystemIdleColumnCountExtend : 1; /* 1E.6005.2 R/W Default = 0x0 */ - /* 1 = Extend IDLE column count */ - /*! \brief 1E.6005.3 R/W MSM System Priority Flow Control Enable - AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemPriorityFlowControlEnable - - Default = 0x0 - - 1 = Enable priority flow control - 0 = Enable link flow control - - - Notes: - Enable priority flow control (PFC) mode of operation. When set to 0, the MAC uses standard link pause frames. When set to 1, the MAC will transmit and accept PFC frames. */ - unsigned int msmSystemPriorityFlowControlEnable : 1; /* 1E.6005.3 R/W Default = 0x0 */ - /* 1 = Enable priority flow control - 0 = Enable link flow control - */ - unsigned int reserved2 : 1; - /*! \brief 1E.6005.5 R/W MSM System SFD Check Disable - AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemSfdCheckDisable - - Default = 0x0 - - 1 = Disable SFD check - - - Notes: - Disable check of SFD (0xD5) character at frame start. When set to 1, the frame is accepted even if the SFD byte following the preamble is not 0xD5. When set to 0, a frame is accepted only if the SFD byte is found with the value 0xD5. */ - unsigned int msmSystemSfdCheckDisable : 1; /* 1E.6005.5 R/W Default = 0x0 */ - /* 1 = Disable SFD check - */ - unsigned int reserved1 : 1; - /*! \brief 1E.6005.7 R/W MSM System Tx Low Power IDLE Enable - AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemTxLowPowerIdleEnable - - Default = 0x0 - - 1 = Transmit LPI enable - - - Notes: - Transmit low power IDLE enable. When set to 1, the MAC completes the transmission of the current frame and generates low power IDLE sequences (LPI) to the XGMII/SGMII. When set to 0, the MAC operates in normal mode. This bit is OR'ed with the reg_lowp_ena pin. */ - unsigned int msmSystemTxLowPowerIdleEnable : 1; /* 1E.6005.7 R/W Default = 0x0 */ - /* 1 = Transmit LPI enable - */ - unsigned int reserved0 : 8; - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemGeneralControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System FIFO Control Register: 1E.600E */ -/* MSM System FIFO Control Register: 1E.600E */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System FIFO Control Register */ - union - { - struct - { - /*! \brief 1E.600E.7:0 R/W MSM System Rx FIFO Full Threshold [7:0] - AQ_MsmSystemFifoControlRegister_HHD.u0.bits_0.msmSystemRxFifoFullThreshold - - Default = 0x08 - - Rx FIFO full threshold - - Notes: - All threshold values are in steps of FIFO words. */ - unsigned int msmSystemRxFifoFullThreshold : 8; /* 1E.600E.7:0 R/W Default = 0x08 */ - /* Rx FIFO full threshold */ - unsigned int reserved0 : 8; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System FIFO Control Register */ - union - { - struct - { - /*! \brief 1E.600F.7:0 R/W MSM System Rx FIFO Empty Threshold [7:0] - AQ_MsmSystemFifoControlRegister_HHD.u1.bits_1.msmSystemRxFifoEmptyThreshold - - Default = 0x00 - - Rx FIFO empty threshold - - Notes: - All threshold values are in steps of FIFO words. */ - unsigned int msmSystemRxFifoEmptyThreshold : 8; /* 1E.600F.7:0 R/W Default = 0x00 */ - /* Rx FIFO empty threshold */ - unsigned int reserved0 : 8; - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of MSM System FIFO Control Register */ - union - { - struct - { - /*! \brief 1E.6010.5:0 R/W MSM System Tx FIFO Full Threshold [5:0] - AQ_MsmSystemFifoControlRegister_HHD.u2.bits_2.msmSystemTxFifoFullThreshold - - Default = 0x08 - - Tx FIFO full threshold - - Notes: - All threshold values are in steps of FIFO words. */ - unsigned int msmSystemTxFifoFullThreshold : 6; /* 1E.6010.5:0 R/W Default = 0x08 */ - /* Tx FIFO full threshold */ - unsigned int reserved0 : 10; - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of MSM System FIFO Control Register */ - union - { - struct - { - /*! \brief 1E.6011.5:0 R/W MSM System Tx FIFO Empty Threshold [5:0] - AQ_MsmSystemFifoControlRegister_HHD.u3.bits_3.msmSystemTxFifoEmptyThreshold - - Default = 0x00 - - Tx FIFO empty threshold - - Notes: - All threshold values are in steps of FIFO words. */ - unsigned int msmSystemTxFifoEmptyThreshold : 6; /* 1E.6011.5:0 R/W Default = 0x00 */ - /* Tx FIFO empty threshold */ - unsigned int reserved0 : 10; - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of MSM System FIFO Control Register */ - union - { - struct - { - /*! \brief 1E.6012.7:0 ROS MSM System Rx FIFO Almost Full Threshold [7:0] - AQ_MsmSystemFifoControlRegister_HHD.u4.bits_4.msmSystemRxFifoAlmostFullThreshold - - Default = 0x00 - - Rx FIFO almost full threshold - - Notes: - Unused. */ - unsigned int msmSystemRxFifoAlmostFullThreshold : 8; /* 1E.6012.7:0 ROS Default = 0x00 */ - /* Rx FIFO almost full threshold */ - unsigned int reserved0 : 8; - } bits_4; - uint16_t word_4; - } u4; - /*! \brief Union for bit and word level access of word 5 of MSM System FIFO Control Register */ - union - { - struct - { - /*! \brief 1E.6013.7:0 ROS MSM System Rx FIFO Almost Empty Threshold [7:0] - AQ_MsmSystemFifoControlRegister_HHD.u5.bits_5.msmSystemRxFifoAlmostEmptyThreshold - - Default = 0x00 - - Rx FIFO almost empty threshold - - Notes: - Unused. */ - unsigned int msmSystemRxFifoAlmostEmptyThreshold : 8; /* 1E.6013.7:0 ROS Default = 0x00 */ - /* Rx FIFO almost empty threshold */ - unsigned int reserved0 : 8; - } bits_5; - uint16_t word_5; - } u5; - /*! \brief Union for bit and word level access of word 6 of MSM System FIFO Control Register */ - union - { - struct - { - /*! \brief 1E.6014.7:0 ROS MSM System Tx FIFO Almost Full Threshold [7:0] - AQ_MsmSystemFifoControlRegister_HHD.u6.bits_6.msmSystemTxFifoAlmostFullThreshold - - Default = 0x00 - - Tx FIFO almost full threshold - - Notes: - Unused. */ - unsigned int msmSystemTxFifoAlmostFullThreshold : 8; /* 1E.6014.7:0 ROS Default = 0x00 */ - /* Tx FIFO almost full threshold */ - unsigned int reserved0 : 8; - } bits_6; - uint16_t word_6; - } u6; - /*! \brief Union for bit and word level access of word 7 of MSM System FIFO Control Register */ - union - { - struct - { - /*! \brief 1E.6015.7:0 ROS MSM System Tx FIFO Almost Empty Threshold [7:0] - AQ_MsmSystemFifoControlRegister_HHD.u7.bits_7.msmSystemTxFifoAlmostEmptyThreshold - - Default = 0x00 - - Tx FIFO almost empty threshold - - Notes: - Unused. */ - unsigned int msmSystemTxFifoAlmostEmptyThreshold : 8; /* 1E.6015.7:0 ROS Default = 0x00 */ - /* Tx FIFO almost empty threshold */ - unsigned int reserved0 : 8; - } bits_7; - uint16_t word_7; - } u7; -} AQ_MsmSystemFifoControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System General Status Register: 1E.6020 */ -/* MSM System General Status Register: 1E.6020 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System General Status Register */ - union - { - struct - { - /*! \brief 1E.6020.0 BLH MSM System Rx Local Fault - AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemRxLocalFault - - - - Rx local fault detected - - Notes: - Latch high local fault status. Set to 1, whent he MAC detects Rx local fault sequences on the Rx interface. Reset to 0 after read and after reset. */ - unsigned int msmSystemRxLocalFault : 1; /* 1E.6020.0 BLH */ - /* Rx local fault detected */ - /*! \brief 1E.6020.1 BLH MSM System Rx Remote Fault - AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemRxRemoteFault - - - - Rx remote fault detected - - Notes: - Latch high local fault status. Set to 1, whent he MAC detects Rx local fault sequences on the Rx interface. Reset to 0 after read and after reset. */ - unsigned int msmSystemRxRemoteFault : 1; /* 1E.6020.1 BLH */ - /* Rx remote fault detected */ - /*! \brief 1E.6020.2 RO MSM System PHY Loss of Signal - AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemPhyLossOfSignal - - - - PHY loss of signal - - Notes: - PHY indicates loss of signal. This is the value of pin phy_los which is tied to 0. */ - unsigned int msmSystemPhyLossOfSignal : 1; /* 1E.6020.2 RO */ - /* PHY loss of signal */ - /*! \brief 1E.6020.3 R/W MSM System Timestamp Available - AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemTimestampAvailable - - Default = 0x0 - - Timestamp available - - Notes: - Transmit timestamp available. Indicates that the timestamp of the last transmitted event frame (which had ff_tx_ts_frm=1) is available in the register See MAC Time Stamp Status 0 [F:0] and See MAC Time Stamp Status 1 [F:0] . To clear this bit, the bit must be written with a 1. - */ - unsigned int msmSystemTimestampAvailable : 1; /* 1E.6020.3 R/W Default = 0x0 */ - /* Timestamp available */ - /*! \brief 1E.6020.4 RO MSM System Rx Low Power IDLE - AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemRxLowPowerIdle - - - - Rx LPI detected - - Notes: - Receive low power IDLE (LPI). Set to 1 when LPI is currently detected on the MAC Rx interface. Set to 0, when the MAC currently operates in normal mode. */ - unsigned int msmSystemRxLowPowerIdle : 1; /* 1E.6020.4 RO */ - /* Rx LPI detected */ - /*! \brief 1E.6020.5 RO MSM System Tx FIFO Empty - AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemTxFifoEmpty - - - - Tx FIFO empty - - Notes: - When set to 1, indicates the Tx FIFO is empty. When set to 0, Tx FIFO is non-empty. */ - unsigned int msmSystemTxFifoEmpty : 1; /* 1E.6020.5 RO */ - /* Tx FIFO empty */ - unsigned int reserved0 : 10; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System General Status Register */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemGeneralStatusRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Tx IPG Control Register: 1E.6022 */ -/* MSM System Tx IPG Control Register: 1E.6022 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Tx IPG Control Register */ - union - { - struct - { - /*! \brief 1E.6022.5:0 R/W MSM System Tx IPG Length [5:0] - AQ_MsmSystemTxIpgControlRegister_HHD.u0.bits_0.msmSystemTxIpgLength - - Default = 0x0C - - Tx IPG length - - Notes: - Tx inter-packet gap (IPG) value. Depending on LAN or WAN mode of operation. - LAN Mode : Number of octets in steps of 4. Valid values are 8, 12, 16,..., 100. DIC is supported for any setting > 8. A default of 12 must be set to conform to IEEE802.3ae. - WAN Mode : Stretch factor. Valid values are 4 ... 15. The stretch factor is calculated as (value+1)*8. A default of 12 must be set to conform to IEEE802.3ae (i.e. 13*8=104). A larger value shrinks the IPG (increasing bandwidth). - The reset value of 12 leads to IEEE802.3ae conformant behavior in both modes. - Note : WAN mode is only available in 10G mode of operation. */ - unsigned int msmSystemTxIpgLength : 6; /* 1E.6022.5:0 R/W Default = 0x0C */ - /* Tx IPG length */ - unsigned int reserved0 : 10; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Tx IPG Control Register */ - union - { - struct - { - /*! \brief 1E.6023.F:0 MSM System Tx IPG Reserved - AQ_MsmSystemTxIpgControlRegister_HHD.u1.bits_1.msmSystemTxIpgReserved - - - - Value always 0, writes ignored - */ - unsigned int msmSystemTxIpgReserved : 16; /* 1E.6023.F:0 */ - /* Value always 0, writes ignored */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemTxIpgControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Tx Good Frames Counter Register: 1E.6040 */ -/* MSM System Tx Good Frames Counter Register: 1E.6040 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Tx Good Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6040.F:0 ROS MSM System Tx Good Frames Counter 0 [F:0] - AQ_MsmSystemTxGoodFramesCounterRegister_HHD.u0.bits_0.msmSystemTxGoodFramesCounter_0 - - Default = 0x0000 - - Tx good frame counter bits 15:0 - - Notes: - Count of frames transmitted without error (Including pause frames). */ - unsigned int msmSystemTxGoodFramesCounter_0 : 16; /* 1E.6040.F:0 ROS Default = 0x0000 */ - /* Tx good frame counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Tx Good Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6041.F:0 ROS MSM System Tx Good Frames Counter 1 [F:0] - AQ_MsmSystemTxGoodFramesCounterRegister_HHD.u1.bits_1.msmSystemTxGoodFramesCounter_1 - - Default = 0x0000 - - Tx good frame counter bits 31:16 - - - Notes: - Count of frames transmitted without error (Including pause frames). */ - unsigned int msmSystemTxGoodFramesCounter_1 : 16; /* 1E.6041.F:0 ROS Default = 0x0000 */ - /* Tx good frame counter bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemTxGoodFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Rx Good Frames Counter Register: 1E.6044 */ -/* MSM System Rx Good Frames Counter Register: 1E.6044 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Rx Good Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6044.F:0 ROS MSM System Rx Good Frames Counter 0 [F:0] - AQ_MsmSystemRxGoodFramesCounterRegister_HHD.u0.bits_0.msmSystemRxGoodFramesCounter_0 - - Default = 0x0000 - - Rx good frame counter bits 15:0 - - Notes: - Count of frames received without error (Including pause frames). */ - unsigned int msmSystemRxGoodFramesCounter_0 : 16; /* 1E.6044.F:0 ROS Default = 0x0000 */ - /* Rx good frame counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Rx Good Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6045.F:0 ROS MSM System Rx Good Frames Counter 1 [F:0] - AQ_MsmSystemRxGoodFramesCounterRegister_HHD.u1.bits_1.msmSystemRxGoodFramesCounter_1 - - Default = 0x0000 - - Rx good frame counter bits 31:16 - - Notes: - Count of frames received without error (Including pause frames). */ - unsigned int msmSystemRxGoodFramesCounter_1 : 16; /* 1E.6045.F:0 ROS Default = 0x0000 */ - /* Rx good frame counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemRxGoodFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Rx FCS Errors Counter Register: 1E.6048 */ -/* MSM System Rx FCS Errors Counter Register: 1E.6048 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Rx FCS Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.6048.F:0 ROS MSM System FCS Error Counter 0 [F:0] - AQ_MsmSystemRxFcsErrorsCounterRegister_HHD.u0.bits_0.msmSystemFcsErrorCounter_0 - - Default = 0x0000 - - Frame check sequence error counter bits 15:0 - - Notes: - Count of frames for which a CRC-32 Error is detected but the frame is otherwise of correct length. */ - unsigned int msmSystemFcsErrorCounter_0 : 16; /* 1E.6048.F:0 ROS Default = 0x0000 */ - /* Frame check sequence error counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Rx FCS Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.6049.F:0 ROS MSM System FCS Error Counter 1 [F:0] - AQ_MsmSystemRxFcsErrorsCounterRegister_HHD.u1.bits_1.msmSystemFcsErrorCounter_1 - - Default = 0x0000 - - Frame check sequence error counter bits 31:16 - - Notes: - Count of frames for which a CRC-32 Error is detected but the frame is otherwise of correct length. */ - unsigned int msmSystemFcsErrorCounter_1 : 16; /* 1E.6049.F:0 ROS Default = 0x0000 */ - /* Frame check sequence error counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemRxFcsErrorsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Rx Alignment Errors Counter Register: 1E.604C */ -/* MSM System Rx Alignment Errors Counter Register: 1E.604C */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Rx Alignment Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.604C.F:0 ROS MSM System Alignment Error Counter 0 [F:0] - AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD.u0.bits_0.msmSystemAlignmentErrorCounter_0 - - Default = 0x0000 - - Alignment error counter bits 15:0 - - Notes: - Count of frames received with an alignment error. */ - unsigned int msmSystemAlignmentErrorCounter_0 : 16; /* 1E.604C.F:0 ROS Default = 0x0000 */ - /* Alignment error counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Rx Alignment Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.604D.F:0 ROS MSM System Alignment Error Counter 1 [F:0] - AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD.u1.bits_1.msmSystemAlignmentErrorCounter_1 - - Default = 0x0000 - - Alignment error counter bits 31:16 - - Notes: - Count of frames received with an alignment error. */ - unsigned int msmSystemAlignmentErrorCounter_1 : 16; /* 1E.604D.F:0 ROS Default = 0x0000 */ - /* Alignment error counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Tx Pause Frames Counter Register: 1E.6050 */ -/* MSM System Tx Pause Frames Counter Register: 1E.6050 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Tx Pause Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6050.F:0 ROS MSM System Tx Pause Frames Counter 0 [F:0] - AQ_MsmSystemTxPauseFramesCounterRegister_HHD.u0.bits_0.msmSystemTxPauseFramesCounter_0 - - Default = 0x0000 - - Tx pause frame counter bits 15:0 - - Notes: - Valid pause frames transmitted. */ - unsigned int msmSystemTxPauseFramesCounter_0 : 16; /* 1E.6050.F:0 ROS Default = 0x0000 */ - /* Tx pause frame counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Tx Pause Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6051.F:0 ROS MSM System Tx Pause Frames Counter 1 [F:0] - AQ_MsmSystemTxPauseFramesCounterRegister_HHD.u1.bits_1.msmSystemTxPauseFramesCounter_1 - - Default = 0x0000 - - Tx pause frame counter bits 31:16 - - - Notes: - Valid pause frames transmitted. */ - unsigned int msmSystemTxPauseFramesCounter_1 : 16; /* 1E.6051.F:0 ROS Default = 0x0000 */ - /* Tx pause frame counter bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemTxPauseFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Rx Pause Frames Counter Register: 1E.6054 */ -/* MSM System Rx Pause Frames Counter Register: 1E.6054 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Rx Pause Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6054.F:0 ROS MSM System Rx Pause Frames Counter 0 [F:0] - AQ_MsmSystemRxPauseFramesCounterRegister_HHD.u0.bits_0.msmSystemRxPauseFramesCounter_0 - - Default = 0x0000 - - Rx pause frame counter bits 15:0 - - Notes: - Valid pause frames received. */ - unsigned int msmSystemRxPauseFramesCounter_0 : 16; /* 1E.6054.F:0 ROS Default = 0x0000 */ - /* Rx pause frame counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Rx Pause Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6055.F:0 ROS MSM System Rx Pause Frames Counter 1 [F:0] - AQ_MsmSystemRxPauseFramesCounterRegister_HHD.u1.bits_1.msmSystemRxPauseFramesCounter_1 - - Default = 0x0000 - - Rx pause frame counter bits 31:16 - - Notes: - Valid pause frames received. */ - unsigned int msmSystemRxPauseFramesCounter_1 : 16; /* 1E.6055.F:0 ROS Default = 0x0000 */ - /* Rx pause frame counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemRxPauseFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Rx Too Long Errors Counter Register: 1E.6058 */ -/* MSM System Rx Too Long Errors Counter Register: 1E.6058 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Rx Too Long Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.6058.F:0 ROS MSM System Rx Too Long Errors Counter 0 [F:0] - AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD.u0.bits_0.msmSystemRxTooLongErrorsCounter_0 - - Default = 0x0000 - - Too-long errors counter bits 15:0 - - Notes: - Frame received exceeded the maximum length programmed with register FRM_LGTH. */ - unsigned int msmSystemRxTooLongErrorsCounter_0 : 16; /* 1E.6058.F:0 ROS Default = 0x0000 */ - /* Too-long errors counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Rx Too Long Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.6059.F:0 ROS MSM System Rx Too Long Errors Counter 1 [F:0] - AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD.u1.bits_1.msmSystemRxTooLongErrorsCounter_1 - - Default = 0x0000 - - Too-long errors counter bits 31:16 - - Notes: - Frame received exceeded the maximum length programmed with register FRM_LGTH. */ - unsigned int msmSystemRxTooLongErrorsCounter_1 : 16; /* 1E.6059.F:0 ROS Default = 0x0000 */ - /* Too-long errors counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Rx In Range Length Errors Counter Register: 1E.605C */ -/* MSM System Rx In Range Length Errors Counter Register: 1E.605C */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Rx In Range Length Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.605C.F:0 ROS MSM System Rx In Range Length Errors Counter 0 [F:0] - AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD.u0.bits_0.msmSystemRxInRangeLengthErrorsCounter_0 - - Default = 0x0000 - - In-range-length errors counter bits 15:0 - - Notes: - A count of frames with a length/type field value between 46 (VLAN: 42) and less than 0x0600, that does not match the number of payload data octets received. Should count also if length/type field is less than 46 (VLAN: 42) and the frame is longer than 64 bytes. */ - unsigned int msmSystemRxInRangeLengthErrorsCounter_0 : 16; /* 1E.605C.F:0 ROS Default = 0x0000 */ - /* In-range-length errors counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Rx In Range Length Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.605D.F:0 ROS MSM System Rx In Range Length Errors Counter 1 [F:0] - AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD.u1.bits_1.msmSystemRxInRangeLengthErrorsCounter_1 - - Default = 0x0000 - - In-range-length errors counter bits 31:16 - - Notes: - A count of frames with a length/type field value between 46 (VLAN: 42) and less than 0x0600, that does not match the number of payload data octets received. Should count also if length/type field is less than 46 (VLAN: 42) and the frame is longer than 64 bytes. */ - unsigned int msmSystemRxInRangeLengthErrorsCounter_1 : 16; /* 1E.605D.F:0 ROS Default = 0x0000 */ - /* In-range-length errors counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Tx VLAN Frames Counter Register: 1E.6060 */ -/* MSM System Tx VLAN Frames Counter Register: 1E.6060 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Tx VLAN Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6060.F:0 ROS MSM System Tx VLAN Frames Counter 0 [F:0] - AQ_MsmSystemTxVlanFramesCounterRegister_HHD.u0.bits_0.msmSystemTxVlanFramesCounter_0 - - Default = 0x0000 - - Tx VLAN frames counter bits 15:0 - - Notes: - Valid VLAN tagged frames transmitted. */ - unsigned int msmSystemTxVlanFramesCounter_0 : 16; /* 1E.6060.F:0 ROS Default = 0x0000 */ - /* Tx VLAN frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Tx VLAN Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6061.F:0 ROS MSM System Tx VLAN Frames Counter 1 [F:0] - AQ_MsmSystemTxVlanFramesCounterRegister_HHD.u1.bits_1.msmSystemTxVlanFramesCounter_1 - - Default = 0x0000 - - Tx VLAN frames counter bits 31:16 - - Notes: - Valid VLAN tagged frames transmitted. */ - unsigned int msmSystemTxVlanFramesCounter_1 : 16; /* 1E.6061.F:0 ROS Default = 0x0000 */ - /* Tx VLAN frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemTxVlanFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Rx VLAN Frames Counter Register: 1E.6064 */ -/* MSM System Rx VLAN Frames Counter Register: 1E.6064 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Rx VLAN Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6064.F:0 ROS MSM System Rx VLAN Frames Counter 0 [F:0] - AQ_MsmSystemRxVlanFramesCounterRegister_HHD.u0.bits_0.msmSystemRxVlanFramesCounter_0 - - Default = 0x0000 - - Rx VLAN frames counter bits 15:0 - - Notes: - Valid VLAN tagged frames received. */ - unsigned int msmSystemRxVlanFramesCounter_0 : 16; /* 1E.6064.F:0 ROS Default = 0x0000 */ - /* Rx VLAN frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Rx VLAN Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6065.F:0 ROS MSM System Rx VLAN Frames Counter 1 [F:0] - AQ_MsmSystemRxVlanFramesCounterRegister_HHD.u1.bits_1.msmSystemRxVlanFramesCounter_1 - - Default = 0x0000 - - Rx VLAN frames counter bits 31:16 - - Notes: - Valid VLAN tagged frames received. */ - unsigned int msmSystemRxVlanFramesCounter_1 : 16; /* 1E.6065.F:0 ROS Default = 0x0000 */ - /* Rx VLAN frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemRxVlanFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Tx Octets Counter Register: 1E.6068 */ -/* MSM System Tx Octets Counter Register: 1E.6068 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Tx Octets Counter Register */ - union - { - struct - { - /*! \brief 1E.6068.F:0 ROS MSM System Tx Octets Counter 0 [F:0] - AQ_MsmSystemTxOctetsCounterRegister_HHD.u0.bits_0.msmSystemTxOctetsCounter_0 - - Default = 0x0000 - - Tx octets counter bits 15:0 - - Notes: - All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ - unsigned int msmSystemTxOctetsCounter_0 : 16; /* 1E.6068.F:0 ROS Default = 0x0000 */ - /* Tx octets counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Tx Octets Counter Register */ - union - { - struct - { - /*! \brief 1E.6069.F:0 ROS MSM System Tx Octets Counter 1 [F:0] - AQ_MsmSystemTxOctetsCounterRegister_HHD.u1.bits_1.msmSystemTxOctetsCounter_1 - - Default = 0x0000 - - Tx octets counter bits 31:16 - - Notes: - All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ - unsigned int msmSystemTxOctetsCounter_1 : 16; /* 1E.6069.F:0 ROS Default = 0x0000 */ - /* Tx octets counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of MSM System Tx Octets Counter Register */ - union - { - struct - { - /*! \brief 1E.606A.F:0 ROS MSM System Tx Octets Counter 2 [F:0] - AQ_MsmSystemTxOctetsCounterRegister_HHD.u2.bits_2.msmSystemTxOctetsCounter_2 - - Default = 0x0000 - - Tx octets counter bits 47:32 - - Notes: - All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ - unsigned int msmSystemTxOctetsCounter_2 : 16; /* 1E.606A.F:0 ROS Default = 0x0000 */ - /* Tx octets counter bits 47:32 */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of MSM System Tx Octets Counter Register */ - union - { - struct - { - /*! \brief 1E.606B.F:0 ROS MSM System Tx Octets Counter 3 [F:0] - AQ_MsmSystemTxOctetsCounterRegister_HHD.u3.bits_3.msmSystemTxOctetsCounter_3 - - Default = 0x0000 - - Tx octets counter bits 63:48 - - Notes: - All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ - unsigned int msmSystemTxOctetsCounter_3 : 16; /* 1E.606B.F:0 ROS Default = 0x0000 */ - /* Tx octets counter bits 63:48 */ - } bits_3; - uint16_t word_3; - } u3; -} AQ_MsmSystemTxOctetsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Rx Octets Counter Register: 1E.606C */ -/* MSM System Rx Octets Counter Register: 1E.606C */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Rx Octets Counter Register */ - union - { - struct - { - /*! \brief 1E.606C.F:0 ROS MSM System Rx Octets Counter 0 [F:0] - AQ_MsmSystemRxOctetsCounterRegister_HHD.u0.bits_0.msmSystemRxOctetsCounter_0 - - Default = 0x0000 - - Rx octets counter bits 15:0 - - Notes: - All octets received except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames received. */ - unsigned int msmSystemRxOctetsCounter_0 : 16; /* 1E.606C.F:0 ROS Default = 0x0000 */ - /* Rx octets counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Rx Octets Counter Register */ - union - { - struct - { - /*! \brief 1E.606D.F:0 ROS MSM System Rx Octets Counter 1 [F:0] - AQ_MsmSystemRxOctetsCounterRegister_HHD.u1.bits_1.msmSystemRxOctetsCounter_1 - - Default = 0x0000 - - Rx octets counter bits 31:16 - - Notes: - All octets received except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames received. */ - unsigned int msmSystemRxOctetsCounter_1 : 16; /* 1E.606D.F:0 ROS Default = 0x0000 */ - /* Rx octets counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemRxOctetsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Rx Unicast Frames Counter Register: 1E.6070 */ -/* MSM System Rx Unicast Frames Counter Register: 1E.6070 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Rx Unicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6070.F:0 ROS MSM System Rx Unicast Frames Counter 0 [F:0] - AQ_MsmSystemRxUnicastFramesCounterRegister_HHD.u0.bits_0.msmSystemRxUnicastFramesCounter_0 - - Default = 0x0000 - - Rx unicast frames counter bits 15:0 - - Notes: - Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '0'. */ - unsigned int msmSystemRxUnicastFramesCounter_0 : 16; /* 1E.6070.F:0 ROS Default = 0x0000 */ - /* Rx unicast frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Rx Unicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6071.F:0 ROS MSM System Rx Unicast Frames Counter 1 [F:0] - AQ_MsmSystemRxUnicastFramesCounterRegister_HHD.u1.bits_1.msmSystemRxUnicastFramesCounter_1 - - Default = 0x0000 - - Rx unicast frames counter bits 31:16 - - Notes: - Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '0'. */ - unsigned int msmSystemRxUnicastFramesCounter_1 : 16; /* 1E.6071.F:0 ROS Default = 0x0000 */ - /* Rx unicast frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemRxUnicastFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Rx Multicast Frames Counter Register: 1E.6074 */ -/* MSM System Rx Multicast Frames Counter Register: 1E.6074 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Rx Multicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6074.F:0 ROS MSM System Rx Multicast Frames Counter 0 [F:0] - AQ_MsmSystemRxMulticastFramesCounterRegister_HHD.u0.bits_0.msmSystemRxMulticastFramesCounter_0 - - Default = 0x0000 - - Rx multicast frames counter bits 15:0 - - Notes: - Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '1' but not the broadcast address (all bits set '1' ). Pause frames are not counted. */ - unsigned int msmSystemRxMulticastFramesCounter_0 : 16; /* 1E.6074.F:0 ROS Default = 0x0000 */ - /* Rx multicast frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Rx Multicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6075.F:0 ROS MSM System Rx Multicast Frames Counter 1 [F:0] - AQ_MsmSystemRxMulticastFramesCounterRegister_HHD.u1.bits_1.msmSystemRxMulticastFramesCounter_1 - - Default = 0x0000 - - Rx multicast frames counter bits 31:16 - - Notes: - Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '1' but not the broadcast address (all bits set '1' ). Pause frames are not counted. */ - unsigned int msmSystemRxMulticastFramesCounter_1 : 16; /* 1E.6075.F:0 ROS Default = 0x0000 */ - /* Rx multicast frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemRxMulticastFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Rx Broadcast Frames Counter Register: 1E.6078 */ -/* MSM System Rx Broadcast Frames Counter Register: 1E.6078 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Rx Broadcast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6078.F:0 ROS MSM System Rx Broadcast Frames Counter 0 [F:0] - AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD.u0.bits_0.msmSystemRxBroadcastFramesCounter_0 - - Default = 0x0000 - - Rx broadcast frames counter bits 15:0 - - Notes: - Incremented with each valid frame received on the receive FIFO interface (FIFO) and all bits of the destination address were set '1'. */ - unsigned int msmSystemRxBroadcastFramesCounter_0 : 16; /* 1E.6078.F:0 ROS Default = 0x0000 */ - /* Rx broadcast frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Rx Broadcast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6079.F:0 ROS MSM System Rx Broadcast Frames Counter 1 [F:0] - AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD.u1.bits_1.msmSystemRxBroadcastFramesCounter_1 - - Default = 0x0000 - - Rx broadcast frames counter bits 31:16 - - Notes: - Incremented with each valid frame received on the receive FIFO interface (FIFO) and all bits of the destination address were set '1'. */ - unsigned int msmSystemRxBroadcastFramesCounter_1 : 16; /* 1E.6079.F:0 ROS Default = 0x0000 */ - /* Rx broadcast frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Tx Errors Counter Register: 1E.607C */ -/* MSM System Tx Errors Counter Register: 1E.607C */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Tx Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.607C.F:0 ROS MSM System Tx Errors Counter 0 [F:0] - AQ_MsmSystemTxErrorsCounterRegister_HHD.u0.bits_0.msmSystemTxErrorsCounter_0 - - Default = 0x0000 - - Rx errors counter bits 15:0 - - Notes: - Number of frames transmitted with error: - - FIFO Overflow Errors - - FIFO Underflow Errors */ - unsigned int msmSystemTxErrorsCounter_0 : 16; /* 1E.607C.F:0 ROS Default = 0x0000 */ - /* Rx errors counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Tx Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.607D.F:0 ROS MSM System Tx Errors Counter 1 [F:0] - AQ_MsmSystemTxErrorsCounterRegister_HHD.u1.bits_1.msmSystemTxErrorsCounter_1 - - Default = 0x0000 - - Tx errors counter bits 31:16 - - Notes: - Number of frames transmitted with error: - - FIFO Overflow Errors - - FIFO Underflow Errors */ - unsigned int msmSystemTxErrorsCounter_1 : 16; /* 1E.607D.F:0 ROS Default = 0x0000 */ - /* Tx errors counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemTxErrorsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Tx Unicast Frames Counter Register: 1E.6084 */ -/* MSM System Tx Unicast Frames Counter Register: 1E.6084 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Tx Unicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6084.F:0 ROS MSM System Tx Unicast Frames Counter 0 [F:0] - AQ_MsmSystemTxUnicastFramesCounterRegister_HHD.u0.bits_0.msmSystemTxUnicastFramesCounter_0 - - Default = 0x0000 - - Tx unicast frames counter bits 15:0 - - Notes: - Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '0'. */ - unsigned int msmSystemTxUnicastFramesCounter_0 : 16; /* 1E.6084.F:0 ROS Default = 0x0000 */ - /* Tx unicast frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Tx Unicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6085.F:0 ROS MSM System Tx Unicast Frames Counter 1 [F:0] - AQ_MsmSystemTxUnicastFramesCounterRegister_HHD.u1.bits_1.msmSystemTxUnicastFramesCounter_1 - - Default = 0x0000 - - Tx unicast frames counter bits 31:16 - - Notes: - Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '0'. */ - unsigned int msmSystemTxUnicastFramesCounter_1 : 16; /* 1E.6085.F:0 ROS Default = 0x0000 */ - /* Tx unicast frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemTxUnicastFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Tx Multicast Frames Counter Register: 1E.6088 */ -/* MSM System Tx Multicast Frames Counter Register: 1E.6088 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Tx Multicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6088.F:0 ROS MSM System Tx Multicast Frames Counter 0 [F:0] - AQ_MsmSystemTxMulticastFramesCounterRegister_HHD.u0.bits_0.msmSystemTxMulticastFramesCounter_0 - - Default = 0x0000 - - Tx multicast frames counter bits 15:0 - - Notes: - Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '1' but not the broadcast address (all bits '1'). */ - unsigned int msmSystemTxMulticastFramesCounter_0 : 16; /* 1E.6088.F:0 ROS Default = 0x0000 */ - /* Tx multicast frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Tx Multicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6089.F:0 ROS MSM System Tx Multicast Frames Counter 1 [F:0] - AQ_MsmSystemTxMulticastFramesCounterRegister_HHD.u1.bits_1.msmSystemTxMulticastFramesCounter_1 - - Default = 0x0000 - - Tx multicast frames counter bits 31:16 - - Notes: - Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '1' but not the broadcast address (all bits '1'). */ - unsigned int msmSystemTxMulticastFramesCounter_1 : 16; /* 1E.6089.F:0 ROS Default = 0x0000 */ - /* Tx multicast frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemTxMulticastFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Tx Broadcast Frames Counter Register: 1E.608C */ -/* MSM System Tx Broadcast Frames Counter Register: 1E.608C */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Tx Broadcast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.608C.F:0 ROS MSM System Tx Broadcast Frames Counter 0 [F:0] - AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD.u0.bits_0.msmSystemTxBroadcastFramesCounter_0 - - Default = 0x0000 - - Tx broadcast frames counter bits 15:0 - - Notes: - Incremented with each frame written to the FIFO interface and all bits of the destination address set to '1'. */ - unsigned int msmSystemTxBroadcastFramesCounter_0 : 16; /* 1E.608C.F:0 ROS Default = 0x0000 */ - /* Tx broadcast frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Tx Broadcast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.608D.F:0 ROS MSM System Tx Broadcast Frames Counter 1 [F:0] - AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD.u1.bits_1.msmSystemTxBroadcastFramesCounter_1 - - Default = 0x0000 - - Tx broadcast frames counter bits 31:16 - - Notes: - Incremented with each frame written to the FIFO interface and all bits of the destination address set to '1'. */ - unsigned int msmSystemTxBroadcastFramesCounter_1 : 16; /* 1E.608D.F:0 ROS Default = 0x0000 */ - /* Tx broadcast frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Rx Errors Counter Register: 1E.60C8 */ -/* MSM System Rx Errors Counter Register: 1E.60C8 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Rx Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.60C8.F:0 ROS MSM System Rx Errors Counter 0 [F:0] - AQ_MsmSystemRxErrorsCounterRegister_HHD.u0.bits_0.msmSystemRxErrorsCounter_0 - - Default = 0x0000 - - Rx errors counter bits 15:0 - - Notes: - Number of frames received with error: - - FIFO Overflow Errors - - CRC Errors - - Payload Length Errors - - Jabber and Oversized Errors - - Alignment Errors - - The dedicated Error Code (0xfe, not a code error) was received */ - unsigned int msmSystemRxErrorsCounter_0 : 16; /* 1E.60C8.F:0 ROS Default = 0x0000 */ - /* Rx errors counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Rx Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.60C9.F:0 ROS MSM System Rx Errors Counter 1 [F:0] - AQ_MsmSystemRxErrorsCounterRegister_HHD.u1.bits_1.msmSystemRxErrorsCounter_1 - - Default = 0x0000 - - Rx errors counter bits 31:16 - - Notes: - Number of frames received with error: - - FIFO Overflow Errors - - CRC Errors - - Payload Length Errors - - Jabber and Oversized Errors - - Alignment Errors - - The dedicated Error Code (0xfe, not a code error) was received */ - unsigned int msmSystemRxErrorsCounter_1 : 16; /* 1E.60C9.F:0 ROS Default = 0x0000 */ - /* Rx errors counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemRxErrorsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress VLAN TPID 0 Register: 1E.8006 */ -/* MSS Ingress VLAN TPID 0 Register: 1E.8006 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress VLAN TPID 0 Register */ - union - { - struct - { - /*! \brief 1E.8006.F:0 R/W MSS Ingress VLAN STag [F:0] - AQ_MssIngressVlanTpid_0Register_HHD.u0.bits_0.mssIngressVlanStag - - Default = 0x0000 - - STag TPID - - - Notes: - Service Tag Protocol Identifier (TPID) values to identify a VLAN tag. The " See SEC Egress VLAN CP Tag Parse STag " bit must be set to 1 for the incoming packet's TPID to be parsed. */ - unsigned int mssIngressVlanStag : 16; /* 1E.8006.F:0 R/W Default = 0x0000 */ - /* STag TPID - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Ingress VLAN TPID 0 Register */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssIngressVlanTpid_0Register_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress VLAN TPID 1 Register: 1E.8008 */ -/* MSS Ingress VLAN TPID 1 Register: 1E.8008 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress VLAN TPID 1 Register */ - union - { - struct - { - /*! \brief 1E.8008.F:0 R/W MSS Ingress VLAN QTag [F:0] - AQ_MssIngressVlanTpid_1Register_HHD.u0.bits_0.mssIngressVlanQtag - - Default = 0x0000 - - QTag TPID - - - Notes: - Customer Tag Protocol Identifier (TPID) values to identify a VLAN tag. The " See SEC Egress VLAN CP Tag Parse QTag " bit must be set to 1 for the incoming packet's TPID to be parsed. */ - unsigned int mssIngressVlanQtag : 16; /* 1E.8008.F:0 R/W Default = 0x0000 */ - /* QTag TPID - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Ingress VLAN TPID 1 Register */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssIngressVlanTpid_1Register_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress VLAN Control Register: 1E.800A */ -/* MSS Ingress VLAN Control Register: 1E.800A */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress VLAN Control Register */ - union - { - struct - { - /*! \brief 1E.800A.F:0 R/W MSS Ingress VLAN UP Map Table LSW [F:0] - AQ_MssIngressVlanControlRegister_HHD.u0.bits_0.mssIngressVlanUpMapTableLSW - - Default = 0x0000 - - Map table bits 15:0 - - - Notes: - If there is a customer TPID Tag match and no service TPID Tag match or the service TPID Tag match is disabled, the outer TAG's PCP is used to index into this map table to generate the packets user priority. - 2:0 : UP value for customer Tag PCP 0x0 - 5:3: UP value for customer Tag PCP 0x0 - 8:6 : UP value for customer Tag PCP 0x0 - 11:9 : UP value for customer Tag PCP 0x0 - 14:12 : UP value for customer Tag PCP 0x0 - 17:15 : UP value for customer Tag PCP 0x0 */ - unsigned int mssIngressVlanUpMapTableLSW : 16; /* 1E.800A.F:0 R/W Default = 0x0000 */ - /* Map table bits 15:0 - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Ingress VLAN Control Register */ - union - { - struct - { - /*! \brief 1E.800B.7:0 R/W MSS Ingress VLAN UP Map Table MSW [17:10] - AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanUpMapTableMSW - - Default = 0x00 - - UP Map table bits 23:16 - - - Notes: - If there is a customer TPID Tag match and no service TPID Tag match or the service TPID Tag match is disabled, the outer TAG's PCP is used to index into this map table to generate the packets user priority. - 2:0 : UP value for customer Tag PCP 0x0 - 5:3: UP value for customer Tag PCP 0x0 - 8:6 : UP value for customer Tag PCP 0x0 - 11:9 : UP value for customer Tag PCP 0x0 - 14:12 : UP value for customer Tag PCP 0x0 - 17:15 : UP value for customer Tag PCP 0x0 - 20:18 : UP value for customer Tag PCP 0x0 - 23:21 : UP value for customer Tag PCP 0x0 */ - unsigned int mssIngressVlanUpMapTableMSW : 8; /* 1E.800B.7:0 R/W Default = 0x00 */ - /* UP Map table bits 23:16 - */ - /*! \brief 1E.800B.A:8 R/W MSS Ingress VLAN UP Default [2:0] - AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanUpDefault - - Default = 0x0 - - UP default - - - Notes: - User priority default */ - unsigned int mssIngressVlanUpDefault : 3; /* 1E.800B.A:8 R/W Default = 0x0 */ - /* UP default - */ - /*! \brief 1E.800B.B R/W MSS Ingress VLAN STag UP Parse Enable - AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanStagUpParseEnable - - Default = 0x0 - - VLAN CP Tag STag UP enable - - - Notes: - Enable controlled port service VLAN service Tag user priority field parsing. */ - unsigned int mssIngressVlanStagUpParseEnable : 1; /* 1E.800B.B R/W Default = 0x0 */ - /* VLAN CP Tag STag UP enable - */ - /*! \brief 1E.800B.C R/W MSS Ingress VLAN QTag UP Parse Enable - AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanQtagUpParseEnable - - Default = 0x0 - - VLAN CP Tag QTag UP enable - - - Notes: - Enable controlled port customer VLAN customer Tag user priority field parsing. */ - unsigned int mssIngressVlanQtagUpParseEnable : 1; /* 1E.800B.C R/W Default = 0x0 */ - /* VLAN CP Tag QTag UP enable - */ - /*! \brief 1E.800B.D R/W MSS Ingress VLAN QinQ Parse Enable - AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanQinqParseEnable - - Default = 0x0 - - VLAN CP Tag Parse QinQ - - - Notes: - Enable controlled port VLAN QinQ Tag parsing. When this bit is set to 1 both the outer and inner VLAN Tags will be parsed. */ - unsigned int mssIngressVlanQinqParseEnable : 1; /* 1E.800B.D R/W Default = 0x0 */ - /* VLAN CP Tag Parse QinQ - */ - /*! \brief 1E.800B.E R/W MSS Ingress VLAN STag Parse Enable - AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanStagParseEnable - - Default = 0x0 - - 1 = Enable VLAN STag parsing - - - Notes: - Enable controlled port VLAN service Tag parsing. When this bit is set to 1, the incoming packets outer TPID will be compared with the configured " See MSS Ingress VLAN Stag [F:0] " for matching. If the " See SEC Egress VLAN CP Tag Parse QinQ " bit is set to1, this will also be used to compare the incoming packet's inner TPID. */ - unsigned int mssIngressVlanStagParseEnable : 1; /* 1E.800B.E R/W Default = 0x0 */ - /* 1 = Enable VLAN STag parsing - */ - /*! \brief 1E.800B.F R/W MSS Ingress VLAN QTag Parse Enable - AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanQtagParseEnable - - Default = 0x0 - - 1 = Enable VLAN QTag parsing - - - Notes: - Enable controlled port VLAN customer Tag parsing. When this bit is set to 1, the incoming packet's outer TPID will be compared with the configured " See MSS Ingress VLAN QTag [F:0] " for matching. If the " See SEC Egress VLAN CP Tag Parse QinQ " bit is set to1, this will also be used to compare the incoming packet's inner TPID. */ - unsigned int mssIngressVlanQtagParseEnable : 1; /* 1E.800B.F R/W Default = 0x0 */ - /* 1 = Enable VLAN QTag parsing - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssIngressVlanControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress MTU Size Control Register: 1E.800C */ -/* MSS Ingress MTU Size Control Register: 1E.800C */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress MTU Size Control Register */ - union - { - struct - { - /*! \brief 1E.800C.F:0 R/W MSS Ingress Controlled Packet MTU Size [F:0] - AQ_MssIngressMtuSizeControlRegister_HHD.u0.bits_0.mssIngressControlledPacketMtuSize - - Default = 0x05DC - - Maximum transmission unit for controlled packet - - - Notes: - Maximum transmission unit of controlled packet */ - unsigned int mssIngressControlledPacketMtuSize : 16; /* 1E.800C.F:0 R/W Default = 0x05DC */ - /* Maximum transmission unit for controlled packet - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Ingress MTU Size Control Register */ - union - { - struct - { - /*! \brief 1E.800D.F:0 R/W MSS Ingress Uncontrolled Packet MTU Size [F:0] - AQ_MssIngressMtuSizeControlRegister_HHD.u1.bits_1.mssIngressUncontrolledPacketMtuSize - - Default = 0x05DC - - Maximum transmission unit for uncontrolled packet - - - Notes: - Maximum transmission unit of uncontrolled packet */ - unsigned int mssIngressUncontrolledPacketMtuSize : 16; /* 1E.800D.F:0 R/W Default = 0x05DC */ - /* Maximum transmission unit for uncontrolled packet - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssIngressMtuSizeControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress Control Register: 1E.800E */ -/* MSS Ingress Control Register: 1E.800E */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress Control Register */ - union - { - struct - { - /*! \brief 1E.800E.0 R/W MSS Ingress Soft Reset - AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressSoftReset - - Default = 0x0 - - 1 = Soft reset - - - Notes: - S/W reset */ - unsigned int mssIngressSoftReset : 1; /* 1E.800E.0 R/W Default = 0x0 */ - /* 1 = Soft reset - */ - /*! \brief 1E.800E.1 R/W MSS Ingress Operation Point To Point - AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressOperationPointToPoint - - Default = 0x0 - - 1 = Enable the SCI for authorization default - - - Notes: - The default SCI for authorization is configured in See MSS Ingress SCI Default [F:0] See MSS Ingress SCI Default [1F:10] , See MSS Ingress SCI Default [2F:20] , and See MSS Ingress SCI Default [3F:30] . */ - unsigned int mssIngressOperationPointToPoint : 1; /* 1E.800E.1 R/W Default = 0x0 */ - /* 1 = Enable the SCI for authorization default - */ - /*! \brief 1E.800E.2 R/W MSS Ingress Create SCI - AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressCreateSci - - Default = 0x0 - - 0 = SCI from IGPRC LUT - - - Notes: - If the SCI is not in the packet and this bit is set to 0, the SCI will be taken from the IGPRC LUT. */ - unsigned int mssIngressCreateSci : 1; /* 1E.800E.2 R/W Default = 0x0 */ - /* 0 = SCI from IGPRC LUT - */ - /*! \brief 1E.800E.3 R/W MSS Ingress Mask Short Length Error - AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressMaskShortLengthError - - Default = 0x0 - - Unused - - - Notes: - Unused */ - unsigned int mssIngressMaskShortLengthError : 1; /* 1E.800E.3 R/W Default = 0x0 */ - /* Unused - */ - /*! \brief 1E.800E.4 R/W MSS Ingress Drop Kay Packet - AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressDropKayPacket - - Default = 0x0 - - 1 = Drop KaY packets - - - Notes: - Decides whether KaY packets have to be dropped */ - unsigned int mssIngressDropKayPacket : 1; /* 1E.800E.4 R/W Default = 0x0 */ - /* 1 = Drop KaY packets - */ - /*! \brief 1E.800E.5 R/W MSS Ingress Drop IGPRC Miss - AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressDropIgprcMiss - - Default = 0x0 - - 1 = Drop IGPRC miss packets - - - Notes: - Decides whether Ingress Pre-Security Classification (IGPRC) LUT miss packets are to be dropped */ - unsigned int mssIngressDropIgprcMiss : 1; /* 1E.800E.5 R/W Default = 0x0 */ - /* 1 = Drop IGPRC miss packets - */ - /*! \brief 1E.800E.6 R/W MSS Ingress Check ICV - AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressCheckIcv - - Default = 0x0 - - Unused - - - Notes: - Unused */ - unsigned int mssIngressCheckIcv : 1; /* 1E.800E.6 R/W Default = 0x0 */ - /* Unused - */ - /*! \brief 1E.800E.7 R/W MSS Ingress Clear Global Time - AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressClearGlobalTime - - Default = 0x0 - - 1 = Clear global time - - - Notes: - Clear global time */ - unsigned int mssIngressClearGlobalTime : 1; /* 1E.800E.7 R/W Default = 0x0 */ - /* 1 = Clear global time - */ - /*! \brief 1E.800E.8 R/W MSS Ingress Clear Count - AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressClearCount - - Default = 0x0 - - 1 = Clear all MIB counters - - - Notes: - If this bit is set to 1, all MIB counters will be cleared. */ - unsigned int mssIngressClearCount : 1; /* 1E.800E.8 R/W Default = 0x0 */ - /* 1 = Clear all MIB counters - */ - /*! \brief 1E.800E.9 R/W MSS Ingress High Priority - AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressHighPriority - - Default = 0x0 - - 1 = MIB counter clear on read enable - - - Notes: - If this bit is set to 1, read is given high priority and the MIB count value becomes 0 after read. */ - unsigned int mssIngressHighPriority : 1; /* 1E.800E.9 R/W Default = 0x0 */ - /* 1 = MIB counter clear on read enable - */ - /*! \brief 1E.800E.A R/W MSS Ingress Remove SECTag - AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressRemoveSectag - - Default = 0x0 - - 1 = Enable removal of SECTag - - - Notes: - If this bit is set and either of the following two conditions occurs, the SECTag will be removed. - Controlled packet and either the SA or SC is invalid. - IGPRC miss. */ - unsigned int mssIngressRemoveSectag : 1; /* 1E.800E.A R/W Default = 0x0 */ - /* 1 = Enable removal of SECTag - */ - /*! \brief 1E.800E.C:B R/W MSS Ingress Global Validate Frames [1:0] - AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressGlobalValidateFrames - - Default = 0x0 - - Default validate frames configuration - - - Notes: - If the SC is invalid or if an IGPRC miss packet condition occurs, this default will be used for the validate frames configuration instead of the validate frame entry in the Ingress SC Table (IGSCT). */ - unsigned int mssIngressGlobalValidateFrames : 2; /* 1E.800E.C:B R/W Default = 0x0 */ - /* Default validate frames configuration - */ - /*! \brief 1E.800E.D R/W MSS Ingress ICV LSB 8 Bytes Enable - AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressIcvLsb_8BytesEnable - - Default = 0x0 - - 1 = Use LSB - 0 = Use MSB - - - - Notes: - This bit selects MSB or LSB 8 bytes selection in the case where the ICV is 8 bytes. - 0 = MSB is used. */ - unsigned int mssIngressIcvLsb_8BytesEnable : 1; /* 1E.800E.D R/W Default = 0x0 */ - /* 1 = Use LSB - 0 = Use MSB - - */ - unsigned int reserved0 : 2; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Ingress Control Register */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssIngressControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress SA Control Register: 1E.8010 */ -/* MSS Ingress SA Control Register: 1E.8010 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress SA Control Register */ - union - { - struct - { - /*! \brief 1E.8010.F:0 R/W MSS Ingress SA Threshold LSW [F:0] - AQ_MssIngressSaControlRegister_HHD.u0.bits_0.mssIngressSaThresholdLSW - - Default = 0x0000 - - SA threshold bits 15:0 - - - Notes: - Ingress PN threshold to generate SA threshold interrupt. */ - unsigned int mssIngressSaThresholdLSW : 16; /* 1E.8010.F:0 R/W Default = 0x0000 */ - /* SA threshold bits 15:0 - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Ingress SA Control Register */ - union - { - struct - { - /*! \brief 1E.8011.F:0 R/W MSS Ingress SA Threshold MSW [1F:10] - AQ_MssIngressSaControlRegister_HHD.u1.bits_1.mssIngressSaThresholdMSW - - Default = 0x0000 - - SA threshold bits 31:16 - - - Notes: - Ingress PN threshold to generate SA threshold interrupt. */ - unsigned int mssIngressSaThresholdMSW : 16; /* 1E.8011.F:0 R/W Default = 0x0000 */ - /* SA threshold bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssIngressSaControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress Interrupt Status Register: 1E.802E */ -/* MSS Ingress Interrupt Status Register: 1E.802E */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress Interrupt Status Register */ - union - { - struct - { - /*! \brief 1E.802E.0 COW MSS Master Ingress Interrupt - AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssMasterIngressInterrupt - - Default = 0x0 - - 1 = Interrupt - - - Notes: - Write to 1 to clear. This bit is set when any one of the above interrupt and the corresponding interrupt enable are both set. The interrupt enable for this bit must also be set for this bit to be set. */ - unsigned int mssMasterIngressInterrupt : 1; /* 1E.802E.0 COW Default = 0x0 */ - /* 1 = Interrupt - */ - /*! \brief 1E.802E.1 COW MSS Ingress SA Expired Interrupt - AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressSaExpiredInterrupt - - Default = 0x0 - - 1 = Interrupt - - - Notes: - Write to 1 to clear. This bit is set when the SA PN reaches all ones saturation. */ - unsigned int mssIngressSaExpiredInterrupt : 1; /* 1E.802E.1 COW Default = 0x0 */ - /* 1 = Interrupt - */ - /*! \brief 1E.802E.2 COW MSS Ingress SA Threshold Expired Interrupt - AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressSaThresholdExpiredInterrupt - - Default = 0x0 - - 1 = Interrupt - - - Notes: - Write to 1 to clear. This bit is set when the SA PN reaches the See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . */ - unsigned int mssIngressSaThresholdExpiredInterrupt : 1; /* 1E.802E.2 COW Default = 0x0 */ - /* 1 = Interrupt - */ - /*! \brief 1E.802E.3 COW MSS Ingress ICV Error Interrupt - AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressIcvErrorInterrupt - - Default = 0x0 - - 1 = Interrupt - - - Notes: - Write to 1 to clear. */ - unsigned int mssIngressIcvErrorInterrupt : 1; /* 1E.802E.3 COW Default = 0x0 */ - /* 1 = Interrupt - */ - /*! \brief 1E.802E.4 COW MSS Ingress Replay Error Interrupt - AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressReplayErrorInterrupt - - Default = 0x0 - - 1 = Interrupt - - - Notes: - Write to 1 to clear. */ - unsigned int mssIngressReplayErrorInterrupt : 1; /* 1E.802E.4 COW Default = 0x0 */ - /* 1 = Interrupt - */ - /*! \brief 1E.802E.5 COW MSS Ingress MIB Saturation Interrupt - AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressMibSaturationInterrupt - - Default = 0x0 - - 1 = Interrupt - - - Notes: - Write to 1 to clear. This bit is set when the MIB counters reaches all ones saturation. */ - unsigned int mssIngressMibSaturationInterrupt : 1; /* 1E.802E.5 COW Default = 0x0 */ - /* 1 = Interrupt - */ - /*! \brief 1E.802E.6 COW MSS Ingress ECC Error Interrupt - AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressEccErrorInterrupt - - Default = 0x0 - - 1 = Interrupt - - - Notes: - Write to 1 to clear. */ - unsigned int mssIngressEccErrorInterrupt : 1; /* 1E.802E.6 COW Default = 0x0 */ - /* 1 = Interrupt - */ - /*! \brief 1E.802E.7 COW MSS Ingress TCI E/C Error Interrupt - AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressTciE_cErrorInterrupt - - Default = 0x0 - - 1 = Interrupt - - - Notes: - Write to 1 to clear. This error occurs when the TCI E bit is 1 and the TCI C bit is 0. The packet is not dropped, uncontrolled, or untagged. */ - unsigned int mssIngressTciE_cErrorInterrupt : 1; /* 1E.802E.7 COW Default = 0x0 */ - /* 1 = Interrupt - */ - /*! \brief 1E.802E.8 COW MSS Ingress IGPOC Miss Interrupt - AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressIgpocMissInterrupt - - Default = 0x0 - - 1 = Interrupt - - */ - unsigned int mssIngressIgpocMissInterrupt : 1; /* 1E.802E.8 COW Default = 0x0 */ - /* 1 = Interrupt - */ - unsigned int reserved0 : 7; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Ingress Interrupt Status Register */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssIngressInterruptStatusRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress Interrupt Mask Register: 1E.8030 */ -/* MSS Ingress Interrupt Mask Register: 1E.8030 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress Interrupt Mask Register */ - union - { - struct - { - /*! \brief 1E.8030.0 R/W MSS Ingress Master Interrupt Enable - AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressMasterInterruptEnable - - Default = 0x0 - - 1 = Interrupt enabled - - */ - unsigned int mssIngressMasterInterruptEnable : 1; /* 1E.8030.0 R/W Default = 0x0 */ - /* 1 = Interrupt enabled - */ - /*! \brief 1E.8030.1 R/W MSS Ingress SA Expired Interrupt Enable - AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressSaExpiredInterruptEnable - - Default = 0x0 - - 1 = Interrupt enabled - - */ - unsigned int mssIngressSaExpiredInterruptEnable : 1; /* 1E.8030.1 R/W Default = 0x0 */ - /* 1 = Interrupt enabled - */ - /*! \brief 1E.8030.2 R/W MSS Ingress SA Threshold Expired Interrupt Enable - AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressSaThresholdExpiredInterruptEnable - - Default = 0x0 - - 1 = Interrupt enabled - - */ - unsigned int mssIngressSaThresholdExpiredInterruptEnable : 1; /* 1E.8030.2 R/W Default = 0x0 */ - /* 1 = Interrupt enabled - */ - /*! \brief 1E.8030.3 R/W MSS Ingress ICV Error Interrupt Enable - AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressIcvErrorInterruptEnable - - Default = 0x0 - - 1 = Interrupt enabled - - */ - unsigned int mssIngressIcvErrorInterruptEnable : 1; /* 1E.8030.3 R/W Default = 0x0 */ - /* 1 = Interrupt enabled - */ - /*! \brief 1E.8030.4 R/W MSS Ingress Replay Error Interrupt Enable - AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressReplayErrorInterruptEnable - - Default = 0x0 - - 1 = Interrupt enabled - - */ - unsigned int mssIngressReplayErrorInterruptEnable : 1; /* 1E.8030.4 R/W Default = 0x0 */ - /* 1 = Interrupt enabled - */ - /*! \brief 1E.8030.5 R/W MSS Ingress MIB Saturation Interrupt Enable - AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressMibSaturationInterruptEnable - - Default = 0x0 - - 1 = Interrupt enabled - - */ - unsigned int mssIngressMibSaturationInterruptEnable : 1; /* 1E.8030.5 R/W Default = 0x0 */ - /* 1 = Interrupt enabled - */ - /*! \brief 1E.8030.6 R/W MSS Ingress ECC Error Interrupt Enable - AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressEccErrorInterruptEnable - - Default = 0x0 - - 1 = Interrupt enabled - - */ - unsigned int mssIngressEccErrorInterruptEnable : 1; /* 1E.8030.6 R/W Default = 0x0 */ - /* 1 = Interrupt enabled - */ - /*! \brief 1E.8030.7 R/W MSS Ingress TCI E/C Error Interrupt Enable - AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressTciE_cErrorInterruptEnable - - Default = 0x0 - - 1 = Interrupt enabled - - */ - unsigned int mssIngressTciE_cErrorInterruptEnable : 1; /* 1E.8030.7 R/W Default = 0x0 */ - /* 1 = Interrupt enabled - */ - /*! \brief 1E.8030.8 R/W MSS Ingress IGPOC Miss Interrupt Enable - AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressIgpocMissInterruptEnable - - Default = 0x0 - - 1 = Interrupt enabled - - */ - unsigned int mssIngressIgpocMissInterruptEnable : 1; /* 1E.8030.8 R/W Default = 0x0 */ - /* 1 = Interrupt enabled - */ - unsigned int reserved0 : 7; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Ingress Interrupt Mask Register */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssIngressInterruptMaskRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress SA ICV Error Status Register: 1E.8032 */ -/* MSS Ingress SA ICV Error Status Register: 1E.8032 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress SA ICV Error Status Register */ - union - { - struct - { - /*! \brief 1E.8032.F:0 COW MSS Ingress SA ICV Error LSW [F:0] - AQ_MssIngressSaIcvErrorStatusRegister_HHD.u0.bits_0.mssIngressSaIcvErrorLSW - - Default = 0x0000 - - SA ICV error bits 15:0 - - - Notes: - When set, these bits identify the SA that has an ICV error. Write these bits to 1 to clear. */ - unsigned int mssIngressSaIcvErrorLSW : 16; /* 1E.8032.F:0 COW Default = 0x0000 */ - /* SA ICV error bits 15:0 - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Ingress SA ICV Error Status Register */ - union - { - struct - { - /*! \brief 1E.8033.F:0 COW MSS Ingress SA ICV Error MSW [1F:10] - AQ_MssIngressSaIcvErrorStatusRegister_HHD.u1.bits_1.mssIngressSaIcvErrorMSW - - Default = 0x0000 - - SA ICV error bits 31:16 - - - Notes: - When set, these bits identify the SA that has an ICV error. Write these bits to 1 to clear. */ - unsigned int mssIngressSaIcvErrorMSW : 16; /* 1E.8033.F:0 COW Default = 0x0000 */ - /* SA ICV error bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssIngressSaIcvErrorStatusRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress SA Replay Error Status Register: 1E.8034 */ -/* MSS Ingress SA Replay Error Status Register: 1E.8034 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress SA Replay Error Status Register */ - union - { - struct - { - /*! \brief 1E.8034.F:0 COW MSS Ingress SA Replay Error LSW [F:0] - AQ_MssIngressSaReplayErrorStatusRegister_HHD.u0.bits_0.mssIngressSaReplayErrorLSW - - Default = 0x0000 - - SA replay error bits 15:0 - - - Notes: - When set, these bits identify the SA that has a replay error. Write these bits to 1 to clear. */ - unsigned int mssIngressSaReplayErrorLSW : 16; /* 1E.8034.F:0 COW Default = 0x0000 */ - /* SA replay error bits 15:0 - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Ingress SA Replay Error Status Register */ - union - { - struct - { - /*! \brief 1E.8035.F:0 COW MSS Ingress SA Replay Error MSW [1F:10] - AQ_MssIngressSaReplayErrorStatusRegister_HHD.u1.bits_1.mssIngressSaReplayErrorMSW - - Default = 0x0000 - - SA replay error bits 31:16 - - - Notes: - When set, these bits identify the SA that has a replay error. Write these bits to 1 to clear. */ - unsigned int mssIngressSaReplayErrorMSW : 16; /* 1E.8035.F:0 COW Default = 0x0000 */ - /* SA replay error bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssIngressSaReplayErrorStatusRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress SA Expired Status Register: 1E.8036 */ -/* MSS Ingress SA Expired Status Register: 1E.8036 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress SA Expired Status Register */ - union - { - struct - { - /*! \brief 1E.8036.F:0 ROS MSS Ingress SA Expired LSW [F:0] - AQ_MssIngressSaExpiredStatusRegister_HHD.u0.bits_0.mssIngressSaExpiredLSW - - Default = 0x0000 - - SA expired bits 15:0 - - - Notes: - When set, these bits identify the SA that has expired when the SA PN reaches all-ones saturation. Write these bits to 1 to clear. */ - unsigned int mssIngressSaExpiredLSW : 16; /* 1E.8036.F:0 ROS Default = 0x0000 */ - /* SA expired bits 15:0 - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Ingress SA Expired Status Register */ - union - { - struct - { - /*! \brief 1E.8037.F:0 ROS MSS Ingress SA Expired MSW [1F:10] - AQ_MssIngressSaExpiredStatusRegister_HHD.u1.bits_1.mssIngressSaExpiredMSW - - Default = 0x0000 - - SA expired bits 31:16 - - - Notes: - When set, these bits identify the SA that has expired when the SA PN reaches all-ones saturation. Write these bits to 1 to clear. */ - unsigned int mssIngressSaExpiredMSW : 16; /* 1E.8037.F:0 ROS Default = 0x0000 */ - /* SA expired bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssIngressSaExpiredStatusRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress SA Threshold Expired Status Register: 1E.8038 */ -/* MSS Ingress SA Threshold Expired Status Register: 1E.8038 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress SA Threshold Expired Status Register */ - union - { - struct - { - /*! \brief 1E.8038.F:0 ROS MSS Ingress SA Threshold Expired LSW [F:0] - AQ_MssIngressSaThresholdExpiredStatusRegister_HHD.u0.bits_0.mssIngressSaThresholdExpiredLSW - - Default = 0x0000 - - SA threshold expired bits 15:0 - - - Notes: - When set, these bits identify the SA that has expired when the SA PN has reached the configured threshold See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . Write these bits to 1 to clear. */ - unsigned int mssIngressSaThresholdExpiredLSW : 16; /* 1E.8038.F:0 ROS Default = 0x0000 */ - /* SA threshold expired bits 15:0 - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Ingress SA Threshold Expired Status Register */ - union - { - struct - { - /*! \brief 1E.8039.F:0 ROS MSS Ingress SA Threshold Expired MSW [1F:10] - AQ_MssIngressSaThresholdExpiredStatusRegister_HHD.u1.bits_1.mssIngressSaThresholdExpiredMSW - - Default = 0x0000 - - SA threshold expired bits 31:16 - - - Notes: - When set, these bits identify the SA that has expired when the SA PN has reached the configured threshold See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . Write these bits to 1 to clear. */ - unsigned int mssIngressSaThresholdExpiredMSW : 16; /* 1E.8039.F:0 ROS Default = 0x0000 */ - /* SA threshold expired bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssIngressSaThresholdExpiredStatusRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress ECC Interrupt Status Register: 1E.803A */ -/* MSS Ingress ECC Interrupt Status Register: 1E.803A */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress ECC Interrupt Status Register */ - union - { - struct - { - /*! \brief 1E.803A.F:0 R/W MSS Ingress SA ECC Error Interrupt LSW [F:0] - AQ_MssIngressEccInterruptStatusRegister_HHD.u0.bits_0.mssIngressSaEccErrorInterruptLSW - - Default = 0x0000 - - SA ECC error interrupt bits 15:0 - - - Notes: - When set to 1, indicates that an ECC error occured for the SA. */ - unsigned int mssIngressSaEccErrorInterruptLSW : 16; /* 1E.803A.F:0 R/W Default = 0x0000 */ - /* SA ECC error interrupt bits 15:0 - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Ingress ECC Interrupt Status Register */ - union - { - struct - { - /*! \brief 1E.803B.F:0 R/W MSS Ingress SA ECC Error Interrupt MSW [1F:10] - AQ_MssIngressEccInterruptStatusRegister_HHD.u1.bits_1.mssIngressSaEccErrorInterruptMSW - - Default = 0x0000 - - SA ECC error interrupt bits 31:16 - - - Notes: - When set to 1, indicates that an ECC error occured for the SA. */ - unsigned int mssIngressSaEccErrorInterruptMSW : 16; /* 1E.803B.F:0 R/W Default = 0x0000 */ - /* SA ECC error interrupt bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssIngressEccInterruptStatusRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress LUT Address Control Register: 1E.8080 */ -/* MSS Ingress LUT Address Control Register: 1E.8080 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress LUT Address Control Register */ - union - { - struct - { - /*! \brief 1E.8080.8:0 R/W MSS Ingress LUT Address [8:0] - AQ_MssIngressLutAddressControlRegister_HHD.u0.bits_0.mssIngressLutAddress - - Default = 0x000 - - LUT address - - */ - unsigned int mssIngressLutAddress : 9; /* 1E.8080.8:0 R/W Default = 0x000 */ - /* LUT address - */ - unsigned int reserved0 : 3; - /*! \brief 1E.8080.F:C R/W MSS Ingress LUT Select [3:0] - AQ_MssIngressLutAddressControlRegister_HHD.u0.bits_0.mssIngressLutSelect - - Default = 0x0 - - LUT select - - - Notes: - 0x0 : Ingress Pre-Security MAC Control FIlter (IGPRCTLF) LUT - 0x1 : Ingress Pre-Security Classification LUT (IGPRC) - 0x2 : Ingress Packet Format (IGPFMT) SAKey LUT - 0x3 : Ingress Packet Format (IGPFMT) SC/SA LUT - 0x4 : Ingress Post-Security Classification LUT (IGPOC) - 0x5 : Ingress Post-Security MAC Control Filter (IGPOCTLF) LUT - 0x6 : Ingress MIB (IGMIB) */ - unsigned int mssIngressLutSelect : 4; /* 1E.8080.F:C R/W Default = 0x0 */ - /* LUT select - */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_MssIngressLutAddressControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress LUT Control Register: 1E.8081 */ -/* MSS Ingress LUT Control Register: 1E.8081 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress LUT Control Register */ - union - { - struct - { - unsigned int reserved0 : 14; - /*! \brief 1E.8081.E R/W MSS Ingress LUT Read - AQ_MssIngressLutControlRegister_HHD.u0.bits_0.mssIngressLutRead - - Default = 0x0 - - 1 = LUT read - - - Notes: - Setting this bit to 1, will read the LUT. This bit will automatically clear to 0. */ - unsigned int mssIngressLutRead : 1; /* 1E.8081.E R/W Default = 0x0 */ - /* 1 = LUT read - */ - /*! \brief 1E.8081.F R/W MSS Ingress LUT Write - AQ_MssIngressLutControlRegister_HHD.u0.bits_0.mssIngressLutWrite - - Default = 0x0 - - 1 = LUT write - - - Notes: - Setting this bit to 1, will write the LUT. This bit will automatically clear to 0. */ - unsigned int mssIngressLutWrite : 1; /* 1E.8081.F R/W Default = 0x0 */ - /* 1 = LUT write - */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_MssIngressLutControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress LUT Data Control Register: 1E.80A0 */ -/* MSS Ingress LUT Data Control Register: 1E.80A0 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80A0.F:0 R/W MSS Ingress LUT Data 0 [F:0] - AQ_MssIngressLutDataControlRegister_HHD.u0.bits_0.mssIngressLutData_0 - - Default = 0x0000 - - LUT data bits 15:0 - - */ - unsigned int mssIngressLutData_0 : 16; /* 1E.80A0.F:0 R/W Default = 0x0000 */ - /* LUT data bits 15:0 - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80A1.F:0 R/W MSS Ingress LUT Data 1 [1F:10] - AQ_MssIngressLutDataControlRegister_HHD.u1.bits_1.mssIngressLutData_1 - - Default = 0x0000 - - LUT data bits 31:16 - - */ - unsigned int mssIngressLutData_1 : 16; /* 1E.80A1.F:0 R/W Default = 0x0000 */ - /* LUT data bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80A2.F:0 R/W MSS Ingress LUT Data 2 [2F:20] - AQ_MssIngressLutDataControlRegister_HHD.u2.bits_2.mssIngressLutData_2 - - Default = 0x0000 - - LUT data bits 47:32 - - */ - unsigned int mssIngressLutData_2 : 16; /* 1E.80A2.F:0 R/W Default = 0x0000 */ - /* LUT data bits 47:32 - */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80A3.F:0 R/W MSS Ingress LUT Data 3 [3F:30] - AQ_MssIngressLutDataControlRegister_HHD.u3.bits_3.mssIngressLutData_3 - - Default = 0x0000 - - LUT data bits 63:48 - - */ - unsigned int mssIngressLutData_3 : 16; /* 1E.80A3.F:0 R/W Default = 0x0000 */ - /* LUT data bits 63:48 - */ - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80A4.F:0 R/W MSS Ingress LUT Data 4 [4F:40] - AQ_MssIngressLutDataControlRegister_HHD.u4.bits_4.mssIngressLutData_4 - - Default = 0x0000 - - LUT data bits 79:64 - - */ - unsigned int mssIngressLutData_4 : 16; /* 1E.80A4.F:0 R/W Default = 0x0000 */ - /* LUT data bits 79:64 - */ - } bits_4; - uint16_t word_4; - } u4; - /*! \brief Union for bit and word level access of word 5 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80A5.F:0 R/W MSS Ingress LUT Data 5 [5F:50] - AQ_MssIngressLutDataControlRegister_HHD.u5.bits_5.mssIngressLutData_5 - - Default = 0x0000 - - LUT data bits 95:80 - - */ - unsigned int mssIngressLutData_5 : 16; /* 1E.80A5.F:0 R/W Default = 0x0000 */ - /* LUT data bits 95:80 - */ - } bits_5; - uint16_t word_5; - } u5; - /*! \brief Union for bit and word level access of word 6 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80A6.F:0 R/W MSS Ingress LUT Data 6 [6F:60] - AQ_MssIngressLutDataControlRegister_HHD.u6.bits_6.mssIngressLutData_6 - - Default = 0x0000 - - LUT data bits 111:96 - - */ - unsigned int mssIngressLutData_6 : 16; /* 1E.80A6.F:0 R/W Default = 0x0000 */ - /* LUT data bits 111:96 - */ - } bits_6; - uint16_t word_6; - } u6; - /*! \brief Union for bit and word level access of word 7 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80A7.F:0 R/W MSS Ingress LUT Data 7 [7F:70] - AQ_MssIngressLutDataControlRegister_HHD.u7.bits_7.mssIngressLutData_7 - - Default = 0x0000 - - LUT data bits 127:112 - - */ - unsigned int mssIngressLutData_7 : 16; /* 1E.80A7.F:0 R/W Default = 0x0000 */ - /* LUT data bits 127:112 - */ - } bits_7; - uint16_t word_7; - } u7; - /*! \brief Union for bit and word level access of word 8 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80A8.F:0 R/W MSS Ingress LUT Data 8 [8F:80] - AQ_MssIngressLutDataControlRegister_HHD.u8.bits_8.mssIngressLutData_8 - - Default = 0x0000 - - LUT data bits 143:128 - - */ - unsigned int mssIngressLutData_8 : 16; /* 1E.80A8.F:0 R/W Default = 0x0000 */ - /* LUT data bits 143:128 - */ - } bits_8; - uint16_t word_8; - } u8; - /*! \brief Union for bit and word level access of word 9 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80A9.F:0 R/W MSS Ingress LUT Data 9 [9F:90] - AQ_MssIngressLutDataControlRegister_HHD.u9.bits_9.mssIngressLutData_9 - - Default = 0x0000 - - LUT data bits 159:144 - - */ - unsigned int mssIngressLutData_9 : 16; /* 1E.80A9.F:0 R/W Default = 0x0000 */ - /* LUT data bits 159:144 - */ - } bits_9; - uint16_t word_9; - } u9; - /*! \brief Union for bit and word level access of word 10 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80AA.F:0 R/W MSS Ingress LUT Data 10 [AF:A0] - AQ_MssIngressLutDataControlRegister_HHD.u10.bits_10.mssIngressLutData_10 - - Default = 0x0000 - - LUT data bits 175:160 - - */ - unsigned int mssIngressLutData_10 : 16; /* 1E.80AA.F:0 R/W Default = 0x0000 */ - /* LUT data bits 175:160 - */ - } bits_10; - uint16_t word_10; - } u10; - /*! \brief Union for bit and word level access of word 11 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80AB.F:0 R/W MSS Ingress LUT Data 11 [BF:B0] - AQ_MssIngressLutDataControlRegister_HHD.u11.bits_11.mssIngressLutData_11 - - Default = 0x0000 - - LUT data bits 191:176 - - */ - unsigned int mssIngressLutData_11 : 16; /* 1E.80AB.F:0 R/W Default = 0x0000 */ - /* LUT data bits 191:176 - */ - } bits_11; - uint16_t word_11; - } u11; - /*! \brief Union for bit and word level access of word 12 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80AC.F:0 R/W MSS Ingress LUT Data 12 [CF:C0] - AQ_MssIngressLutDataControlRegister_HHD.u12.bits_12.mssIngressLutData_12 - - Default = 0x0000 - - LUT data bits 207:192 - - */ - unsigned int mssIngressLutData_12 : 16; /* 1E.80AC.F:0 R/W Default = 0x0000 */ - /* LUT data bits 207:192 - */ - } bits_12; - uint16_t word_12; - } u12; - /*! \brief Union for bit and word level access of word 13 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80AD.F:0 R/W MSS Ingress LUT Data 13 [DF:D0] - AQ_MssIngressLutDataControlRegister_HHD.u13.bits_13.mssIngressLutData_13 - - Default = 0x0000 - - LUT data bits 223:208 - - */ - unsigned int mssIngressLutData_13 : 16; /* 1E.80AD.F:0 R/W Default = 0x0000 */ - /* LUT data bits 223:208 - */ - } bits_13; - uint16_t word_13; - } u13; - /*! \brief Union for bit and word level access of word 14 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80AE.F:0 R/W MSS Ingress LUT Data 14 [EF:E0] - AQ_MssIngressLutDataControlRegister_HHD.u14.bits_14.mssIngressLutData_14 - - Default = 0x0000 - - LUT data bits 239:224 - - */ - unsigned int mssIngressLutData_14 : 16; /* 1E.80AE.F:0 R/W Default = 0x0000 */ - /* LUT data bits 239:224 - */ - } bits_14; - uint16_t word_14; - } u14; - /*! \brief Union for bit and word level access of word 15 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80AF.F:0 R/W MSS Ingress LUT Data 15 [FF:F0] - AQ_MssIngressLutDataControlRegister_HHD.u15.bits_15.mssIngressLutData_15 - - Default = 0x0000 - - LUT data bits 255:240 - - */ - unsigned int mssIngressLutData_15 : 16; /* 1E.80AF.F:0 R/W Default = 0x0000 */ - /* LUT data bits 255:240 - */ - } bits_15; - uint16_t word_15; - } u15; - /*! \brief Union for bit and word level access of word 16 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80B0.F:0 R/W MSS Ingress LUT Data 16 [10F:100] - AQ_MssIngressLutDataControlRegister_HHD.u16.bits_16.mssIngressLutData_16 - - Default = 0x0000 - - LUT data bits 271:256 - - */ - unsigned int mssIngressLutData_16 : 16; /* 1E.80B0.F:0 R/W Default = 0x0000 */ - /* LUT data bits 271:256 - */ - } bits_16; - uint16_t word_16; - } u16; - /*! \brief Union for bit and word level access of word 17 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80B1.F:0 R/W MSS Ingress LUT Data 17 [11F:110] - AQ_MssIngressLutDataControlRegister_HHD.u17.bits_17.mssIngressLutData_17 - - Default = 0x0000 - - LUT data bits 287:272 - - */ - unsigned int mssIngressLutData_17 : 16; /* 1E.80B1.F:0 R/W Default = 0x0000 */ - /* LUT data bits 287:272 - */ - } bits_17; - uint16_t word_17; - } u17; - /*! \brief Union for bit and word level access of word 18 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80B2.F:0 R/W MSS Ingress LUT Data 18 [12F:120] - AQ_MssIngressLutDataControlRegister_HHD.u18.bits_18.mssIngressLutData_18 - - Default = 0x0000 - - LUT data bits 303:288 - - */ - unsigned int mssIngressLutData_18 : 16; /* 1E.80B2.F:0 R/W Default = 0x0000 */ - /* LUT data bits 303:288 - */ - } bits_18; - uint16_t word_18; - } u18; - /*! \brief Union for bit and word level access of word 19 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80B3.F:0 R/W MSS Ingress LUT Data 19 [13F:130] - AQ_MssIngressLutDataControlRegister_HHD.u19.bits_19.mssIngressLutData_19 - - Default = 0x0000 - - LUT data bits 319:304 - - */ - unsigned int mssIngressLutData_19 : 16; /* 1E.80B3.F:0 R/W Default = 0x0000 */ - /* LUT data bits 319:304 - */ - } bits_19; - uint16_t word_19; - } u19; - /*! \brief Union for bit and word level access of word 20 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80B4.F:0 R/W MSS Ingress LUT Data 20 [14F:140] - AQ_MssIngressLutDataControlRegister_HHD.u20.bits_20.mssIngressLutData_20 - - Default = 0x0000 - - LUT data bits 335:320 - - */ - unsigned int mssIngressLutData_20 : 16; /* 1E.80B4.F:0 R/W Default = 0x0000 */ - /* LUT data bits 335:320 - */ - } bits_20; - uint16_t word_20; - } u20; - /*! \brief Union for bit and word level access of word 21 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80B5.F:0 R/W MSS Ingress LUT Data 21 [15F:150] - AQ_MssIngressLutDataControlRegister_HHD.u21.bits_21.mssIngressLutData_21 - - Default = 0x0000 - - LUT data bits 351:336 - - */ - unsigned int mssIngressLutData_21 : 16; /* 1E.80B5.F:0 R/W Default = 0x0000 */ - /* LUT data bits 351:336 - */ - } bits_21; - uint16_t word_21; - } u21; - /*! \brief Union for bit and word level access of word 22 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80B6.F:0 R/W MSS Ingress LUT Data 22 [16F:160] - AQ_MssIngressLutDataControlRegister_HHD.u22.bits_22.mssIngressLutData_22 - - Default = 0x0000 - - LUT data bits 367:352 - - */ - unsigned int mssIngressLutData_22 : 16; /* 1E.80B6.F:0 R/W Default = 0x0000 */ - /* LUT data bits 367:352 - */ - } bits_22; - uint16_t word_22; - } u22; - /*! \brief Union for bit and word level access of word 23 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80B7.F:0 R/W MSS Ingress LUT Data 23 [17F:170] - AQ_MssIngressLutDataControlRegister_HHD.u23.bits_23.mssIngressLutData_23 - - Default = 0x0000 - - LUT data bits 383:368 - - */ - unsigned int mssIngressLutData_23 : 16; /* 1E.80B7.F:0 R/W Default = 0x0000 */ - /* LUT data bits 383:368 - */ - } bits_23; - uint16_t word_23; - } u23; -} AQ_MssIngressLutDataControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line General Control Register: 1E.9004 */ -/* MSM Line General Control Register: 1E.9004 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line General Control Register */ - union - { - struct - { - /*! \brief 1E.9004.0 R/W MSM Line Tx Enable - AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineTxEnable - - Default = 0x0 - - 1 = Tx enable - - Notes: - MAC Rx path enable. Should be set to 1 to enable the MAC Rx path. Should be set to 0 to disable the MAC Rx path. */ - unsigned int msmLineTxEnable : 1; /* 1E.9004.0 R/W Default = 0x0 */ - /* 1 = Tx enable */ - /*! \brief 1E.9004.1 R/W MSM Line Rx Enable - AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineRxEnable - - Default = 0x0 - - 1 = Rx enable - - Notes: - MAC Tx path enable. Should be set to 1 to enable the MAC Tx path. Should be set to 0 to disable the MAC Tx path. */ - unsigned int msmLineRxEnable : 1; /* 1E.9004.1 R/W Default = 0x0 */ - /* 1 = Rx enable */ - unsigned int reserved0 : 1; - /*! \brief 1E.9004.3 R/W MSM Line WAN Mode - AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineWanMode - - Default = 0x0 - - 1 = WAN mode - 0 = LAN mode - - - Notes: - WAN mode enable. Sets WAN mode when set to 1 and LAN mode when set to 0. Note: When changing the mode, verifiy correct setting of the Tx IPG. */ - unsigned int msmLineWanMode : 1; /* 1E.9004.3 R/W Default = 0x0 */ - /* 1 = WAN mode - 0 = LAN mode - */ - /*! \brief 1E.9004.4 R/W MSM Line Promiscuous Mode - AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLinePromiscuousMode - - Default = 0x0 - - 1 = Promiscuous mode - - - Notes: - When set to 1, all frames are received without any MAC address filtering. */ - unsigned int msmLinePromiscuousMode : 1; /* 1E.9004.4 R/W Default = 0x0 */ - /* 1 = Promiscuous mode - */ - /*! \brief 1E.9004.5 R/W MSM Line PAD Enable - AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLinePadEnable - - Default = 0x0 - - 1 = Enable frame padding removal on Rx - - - Notes: - When set to 1, enable frame padding removal on the Rx path. If enabled, padding is removed before the frame is transferred to the MAC client application. If disabled, no padding is removed on the Rx by the MAC. - Note : On Tx, the MAC always adds padding as required. */ - unsigned int msmLinePadEnable : 1; /* 1E.9004.5 R/W Default = 0x0 */ - /* 1 = Enable frame padding removal on Rx - */ - /*! \brief 1E.9004.6 R/W MSM Line CRC Forward - AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineCrcForward - - Default = 0x0 - - 1 = Enable CRC forwarding - - - Notes: - When set to 1, the CRC field of the received frames is forwarded with the frame to the user application. If disabled, the CRC field is stripped from the frame. - Note : If padding is enabled ( See MAC PAD Enable set to 1), this bit is ignored. */ - unsigned int msmLineCrcForward : 1; /* 1E.9004.6 R/W Default = 0x0 */ - /* 1 = Enable CRC forwarding - */ - /*! \brief 1E.9004.7 R/W MSM Line Pause Forward - AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLinePauseForward - - Default = 0x0 - - 1 = Enable Pause forwarding - - - Notes: - Terminate or forward pause frames. If set to 1, pause frames are forwarded to the user application. In normal mode, when set to 0, pause frames are terminated and discarded within the MAC. */ - unsigned int msmLinePauseForward : 1; /* 1E.9004.7 R/W Default = 0x0 */ - /* 1 = Enable Pause forwarding - */ - /*! \brief 1E.9004.8 R/W MSM Line Pause Ignore - AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLinePauseIgnore - - Default = 0x0 - - 1 = Ignore pause frames - - - Notes: - Ignore pause frame quanta. If set to 1, received pause frames are ignored by the MAC. When set to 0, the Tx is stopped for the amount of time specified in the pause quanta received within the pause frame. */ - unsigned int msmLinePauseIgnore : 1; /* 1E.9004.8 R/W Default = 0x0 */ - /* 1 = Ignore pause frames - */ - /*! \brief 1E.9004.9 R/W MSM Line Tx Address Insert Enable - AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineTxAddressInsertEnable - - Default = 0x0 - - 1 = Insert Tx MAC source address - - - Notes: - Set the source MAC address on transmit. If set to 1, the MAC overwrites the source MAC address with the MAC programmed address in all transmitted frames. When set to 0, the source MAC address is transmitted unmodified from the MAC Tx client application. */ - unsigned int msmLineTxAddressInsertEnable : 1; /* 1E.9004.9 R/W Default = 0x0 */ - /* 1 = Insert Tx MAC source address - */ - /*! \brief 1E.9004.A R/W MSM Line Tx CRC Append - AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineTxCrcAppend - - Default = 0x0 - - 1 = Append Tx CRC - - - Notes: - Permanently enable CRC append on transmit. If set to 1, the Tx will append a CRC to all transmitted frames. If set to 0, CRC append can be controlled on a per frame basis using the pin ff_tx_crc. - This configuration bit is OR'ed with the external ff_tx_crc pin to instruct the Tx to append a CRC to transmitted frames. The ff_tx_crc pin is tied to 0. */ - unsigned int msmLineTxCrcAppend : 1; /* 1E.9004.A R/W Default = 0x0 */ - /* 1 = Append Tx CRC - */ - /*! \brief 1E.9004.B R/W MSM Line Tx Pad Enable - AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineTxPadEnable - - Default = 0x1 - - 1 = Enable Tx padding - - - Notes: - When set to 1, enable padding of frames in the Tx direction. When set to 0, the MAC will not extend frames from the application to a minimum of 64 bytes, allowing to transmit short frames (violating the Ethernet mimimum size requirements). Must be set to 1 for normal operation. */ - unsigned int msmLineTxPadEnable : 1; /* 1E.9004.B R/W Default = 0x1 */ - /* 1 = Enable Tx padding - */ - /*! \brief 1E.9004.C R/WSC MSM Line Soft Reset - AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineSoftReset - - Default = 0x0 - - 1 = Soft reset - - - Notes: - Software reset. Self clearing bit. When set to 1, resets all statistic counters as well as the Tx and Rx FIFOs. It should be issued after all traffic has been stopped as a result of clearing the Rx/Tx enable bits ( See MAC Rx Enable set to 0 and See MAC Tx Enable set to 0). - Note : Can lead to an Rx interface (ff_rx_xxx) violations to the application if the reset is issued in the middle of a receive frame transfer. Then the end of packet (assertion of ff_rx_eop) is lost and the application should be prepeared to handle this exception. */ - unsigned int msmLineSoftReset : 1; /* 1E.9004.C R/WSC Default = 0x0 */ - /* 1 = Soft reset - */ - /*! \brief 1E.9004.D R/W MSM Line Control Frame Enable - AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineControlFrameEnable - - Default = 0x0 - - 1 = Control frame enabled - - - Notes: - MAC control frame enable. When set to 1, the MAC control frames with any Opcode other than 0x0001 are accepted and forwarded to the client interface. When set to 0, MAC control frames with any opcode other than 0x0001 are silently discarded. */ - unsigned int msmLineControlFrameEnable : 1; /* 1E.9004.D R/W Default = 0x0 */ - /* 1 = Control frame enabled - */ - /*! \brief 1E.9004.E R/W MSM Line Rx Error Discard - AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineRxErrorDiscard - - Default = 0x0 - - 1 = Enable discard of received errored frames - - - Notes: - Rx errored frame discard enable. When set to 1, any frame received with an error is discarded and not forwarded to the client interface. When set to 0, errored frames are forwarded to the client interface with ff_rx_err asserted. - Note : It is recommended to set this bit to 1 only when store and forward operation is enabled (RX_SECTION_FULL TBD). */ - unsigned int msmLineRxErrorDiscard : 1; /* 1E.9004.E R/W Default = 0x0 */ - /* 1 = Enable discard of received errored frames - */ - /*! \brief 1E.9004.F R/W MSM Line PHY Tx Enable - AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLinePhyTxEnable - - Default = 0x0 - - 1 = Enable PHY Tx - - - Notes: - Directly controls the phy_tx_ena pin. */ - unsigned int msmLinePhyTxEnable : 1; /* 1E.9004.F R/W Default = 0x0 */ - /* 1 = Enable PHY Tx - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line General Control Register */ - union - { - struct - { - /*! \brief 1E.9005.0 R/W MSM Line Force Send IDLE - AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLineForceSendIdle - - Default = 0x0 - - 1 = Force send idle - - Notes: - When set to 1, suppress any frame transmissions and forces IDLE n the Tx interface instead of frames. This control affects the MAC reconciliation layer (RS) which acts after all MAC datapath has processed the frame. - Note : Does not have an effect on fault handling (i.e. reception of local fault will still cause transmit of remote fault). - Must be 0 for normal operation. */ - unsigned int msmLineForceSendIdle : 1; /* 1E.9005.0 R/W Default = 0x0 */ - /* 1 = Force send idle */ - /*! \brief 1E.9005.1 R/W MSM Line Length Check Disable - AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLineLengthCheckDisable - - Default = 0x0 - - 1 = Disable length check - - Notes: - Payload length check disable. When set to 0, the MAC checks the frames payload length with the frame length/type field. When set to 1, the payload length check is disabled. */ - unsigned int msmLineLengthCheckDisable : 1; /* 1E.9005.1 R/W Default = 0x0 */ - /* 1 = Disable length check */ - /*! \brief 1E.9005.2 R/W MSM Line IDLE Column Count Extend - AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLineIdleColumnCountExtend - - Default = 0x0 - - 1 = Extend IDLE column count - - Notes: - When set to 1, extends the RS layer IDLE column counter by 2x. The IEEE 802.3ae defines the fault condition to be cleared after 128 columns of IDLE have been received. If the MAC operates together with a WAN mode PCS (WIS) it may may happen (depending on PCS) that this period is too short to bridge the IDLE stuffing occurring in this mode, leading to a toggling fault indication. In this case, extending the counter helps to aoivd toggling fault indications. */ - unsigned int msmLineIdleColumnCountExtend : 1; /* 1E.9005.2 R/W Default = 0x0 */ - /* 1 = Extend IDLE column count */ - /*! \brief 1E.9005.3 R/W MSM Line Priority Flow Control Enable - AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLinePriorityFlowControlEnable - - Default = 0x0 - - 1 = Enable priority flow control - 0 = Enable link flow control - - - Notes: - Enable priority flow control (PFC) mode of operation. When set to 0, the MAC uses standard link pause frames. When set to 1, the MAC will transmit and accept PFC frames. */ - unsigned int msmLinePriorityFlowControlEnable : 1; /* 1E.9005.3 R/W Default = 0x0 */ - /* 1 = Enable priority flow control - 0 = Enable link flow control - */ - unsigned int reserved2 : 1; - /*! \brief 1E.9005.5 R/W MSM Line SFD Check Disable - AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLineSfdCheckDisable - - Default = 0x0 - - 1 = Disable SFD check - - - Notes: - Disable check of SFD (0xD5) character at frame start. When set to 1, the frame is accepted even if the SFD byte following the preamble is not 0xD5. When set to 0, a frame is accepted only if the SFD byte is found with the value 0xD5. */ - unsigned int msmLineSfdCheckDisable : 1; /* 1E.9005.5 R/W Default = 0x0 */ - /* 1 = Disable SFD check - */ - unsigned int reserved1 : 1; - /*! \brief 1E.9005.7 R/W MSM Line Tx Low Power IDLE Enable - AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLineTxLowPowerIdleEnable - - Default = 0x0 - - 1 = Transmit LPI enable - - - Notes: - Transmit low power IDLE enable. When set to 1, the MAC completes the transmission of the current frame and generates low power IDLE sequences (LPI) to the XGMII/SGMII. When set to 0, the MAC operates in normal mode. This bit is OR'ed with the reg_lowp_ena pin. */ - unsigned int msmLineTxLowPowerIdleEnable : 1; /* 1E.9005.7 R/W Default = 0x0 */ - /* 1 = Transmit LPI enable - */ - unsigned int reserved0 : 8; - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineGeneralControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line FIFO Control Register: 1E.900E */ -/* MSM Line FIFO Control Register: 1E.900E */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line FIFO Control Register */ - union - { - struct - { - /*! \brief 1E.900E.7:0 R/W MSM Line Rx FIFO Full Threshold [7:0] - AQ_MsmLineFifoControlRegister_HHD.u0.bits_0.msmLineRxFifoFullThreshold - - Default = 0x08 - - Rx FIFO full threshold - - Notes: - All threshold values are in steps of FIFO words. */ - unsigned int msmLineRxFifoFullThreshold : 8; /* 1E.900E.7:0 R/W Default = 0x08 */ - /* Rx FIFO full threshold */ - unsigned int reserved0 : 8; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line FIFO Control Register */ - union - { - struct - { - /*! \brief 1E.900F.7:0 R/W MSM Line Rx FIFO Empty Threshold [7:0] - AQ_MsmLineFifoControlRegister_HHD.u1.bits_1.msmLineRxFifoEmptyThreshold - - Default = 0x00 - - Rx FIFO empty threshold - - Notes: - All threshold values are in steps of FIFO words. */ - unsigned int msmLineRxFifoEmptyThreshold : 8; /* 1E.900F.7:0 R/W Default = 0x00 */ - /* Rx FIFO empty threshold */ - unsigned int reserved0 : 8; - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of MSM Line FIFO Control Register */ - union - { - struct - { - /*! \brief 1E.9010.5:0 R/W MSM Line Tx FIFO Full Threshold [5:0] - AQ_MsmLineFifoControlRegister_HHD.u2.bits_2.msmLineTxFifoFullThreshold - - Default = 0x08 - - Tx FIFO full threshold - - Notes: - All threshold values are in steps of FIFO words. */ - unsigned int msmLineTxFifoFullThreshold : 6; /* 1E.9010.5:0 R/W Default = 0x08 */ - /* Tx FIFO full threshold */ - unsigned int reserved0 : 10; - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of MSM Line FIFO Control Register */ - union - { - struct - { - /*! \brief 1E.9011.5:0 R/W MSM Line Tx FIFO Empty Threshold [5:0] - AQ_MsmLineFifoControlRegister_HHD.u3.bits_3.msmLineTxFifoEmptyThreshold - - Default = 0x00 - - Tx FIFO empty threshold - - Notes: - All threshold values are in steps of FIFO words. */ - unsigned int msmLineTxFifoEmptyThreshold : 6; /* 1E.9011.5:0 R/W Default = 0x00 */ - /* Tx FIFO empty threshold */ - unsigned int reserved0 : 10; - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of MSM Line FIFO Control Register */ - union - { - struct - { - /*! \brief 1E.9012.7:0 ROS MSM Line Rx FIFO Almost Full Threshold [7:0] - AQ_MsmLineFifoControlRegister_HHD.u4.bits_4.msmLineRxFifoAlmostFullThreshold - - Default = 0x00 - - Rx FIFO almost full threshold - - Notes: - Unused. */ - unsigned int msmLineRxFifoAlmostFullThreshold : 8; /* 1E.9012.7:0 ROS Default = 0x00 */ - /* Rx FIFO almost full threshold */ - unsigned int reserved0 : 8; - } bits_4; - uint16_t word_4; - } u4; - /*! \brief Union for bit and word level access of word 5 of MSM Line FIFO Control Register */ - union - { - struct - { - /*! \brief 1E.9013.7:0 ROS MSM Line Rx FIFO Almost Empty Threshold [7:0] - AQ_MsmLineFifoControlRegister_HHD.u5.bits_5.msmLineRxFifoAlmostEmptyThreshold - - Default = 0x00 - - Rx FIFO almost empty threshold - - Notes: - Unused. */ - unsigned int msmLineRxFifoAlmostEmptyThreshold : 8; /* 1E.9013.7:0 ROS Default = 0x00 */ - /* Rx FIFO almost empty threshold */ - unsigned int reserved0 : 8; - } bits_5; - uint16_t word_5; - } u5; - /*! \brief Union for bit and word level access of word 6 of MSM Line FIFO Control Register */ - union - { - struct - { - /*! \brief 1E.9014.7:0 ROS MSM Line Tx FIFO Almost Full Threshold [7:0] - AQ_MsmLineFifoControlRegister_HHD.u6.bits_6.msmLineTxFifoAlmostFullThreshold - - Default = 0x00 - - Tx FIFO almost full threshold - - Notes: - Unused. */ - unsigned int msmLineTxFifoAlmostFullThreshold : 8; /* 1E.9014.7:0 ROS Default = 0x00 */ - /* Tx FIFO almost full threshold */ - unsigned int reserved0 : 8; - } bits_6; - uint16_t word_6; - } u6; - /*! \brief Union for bit and word level access of word 7 of MSM Line FIFO Control Register */ - union - { - struct - { - /*! \brief 1E.9015.7:0 ROS MSM Line Tx FIFO Almost Empty Threshold [7:0] - AQ_MsmLineFifoControlRegister_HHD.u7.bits_7.msmLineTxFifoAlmostEmptyThreshold - - Default = 0x00 - - Tx FIFO almost empty threshold - - Notes: - Unused. */ - unsigned int msmLineTxFifoAlmostEmptyThreshold : 8; /* 1E.9015.7:0 ROS Default = 0x00 */ - /* Tx FIFO almost empty threshold */ - unsigned int reserved0 : 8; - } bits_7; - uint16_t word_7; - } u7; -} AQ_MsmLineFifoControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line General Status Register: 1E.9020 */ -/* MSM Line General Status Register: 1E.9020 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line General Status Register */ - union - { - struct - { - /*! \brief 1E.9020.0 BLH MSM Line Rx Local Fault - AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLineRxLocalFault - - - - Rx local fault detected - - Notes: - Latch high local fault status. Set to 1, whent he MAC detects Rx local fault sequences on the Rx interface. Reset to 0 after read and after reset. */ - unsigned int msmLineRxLocalFault : 1; /* 1E.9020.0 BLH */ - /* Rx local fault detected */ - /*! \brief 1E.9020.1 BLH MSM Line Rx Remote Fault - AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLineRxRemoteFault - - - - Rx remote fault detected - - Notes: - Latch high local fault status. Set to 1, whent he MAC detects Rx local fault sequences on the Rx interface. Reset to 0 after read and after reset. */ - unsigned int msmLineRxRemoteFault : 1; /* 1E.9020.1 BLH */ - /* Rx remote fault detected */ - /*! \brief 1E.9020.2 RO MSM Line PHY Loss of Signal - AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLinePhyLossOfSignal - - - - PHY loss of signal - - Notes: - PHY indicates loss of signal. This is the value of pin phy_los which is tied to 0. */ - unsigned int msmLinePhyLossOfSignal : 1; /* 1E.9020.2 RO */ - /* PHY loss of signal */ - /*! \brief 1E.9020.3 R/W MSM Line Timestamp Available - AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLineTimestampAvailable - - Default = 0x0 - - Timestamp available - - Notes: - Transmit timestamp available. Indicates that the timestamp of the last transmitted event frame (which had ff_tx_ts_frm=1) is available in the register See MAC Time Stamp Status 0 [F:0] and See MAC Time Stamp Status 1 [F:0] . To clear this bit, the bit must be written with a 1. - */ - unsigned int msmLineTimestampAvailable : 1; /* 1E.9020.3 R/W Default = 0x0 */ - /* Timestamp available */ - /*! \brief 1E.9020.4 RO MSM Line Rx Low Power IDLE - AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLineRxLowPowerIdle - - - - Rx LPI detected - - Notes: - Receive low power IDLE (LPI). Set to 1 when LPI is currently detected on the MAC Rx interface. Set to 0, when the MAC currently operates in normal mode. */ - unsigned int msmLineRxLowPowerIdle : 1; /* 1E.9020.4 RO */ - /* Rx LPI detected */ - /*! \brief 1E.9020.5 RO MSM Line Tx FIFO Empty - AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLineTxFifoEmpty - - - - Tx FIFO empty - - Notes: - When set to 1, indicates the Tx FIFO is empty. When set to 0, Tx FIFO is non-empty. */ - unsigned int msmLineTxFifoEmpty : 1; /* 1E.9020.5 RO */ - /* Tx FIFO empty */ - unsigned int reserved0 : 10; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line General Status Register */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineGeneralStatusRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Tx IPG Control Register: 1E.9022 */ -/* MSM Line Tx IPG Control Register: 1E.9022 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Tx IPG Control Register */ - union - { - struct - { - /*! \brief 1E.9022.5:0 R/W MSM Line Tx IPG Length [5:0] - AQ_MsmLineTxIpgControlRegister_HHD.u0.bits_0.msmLineTxIpgLength - - Default = 0x0C - - Tx IPG length - - Notes: - Tx inter-packet gap (IPG) value. Depending on LAN or WAN mode of operation. - LAN Mode : Number of octets in steps of 4. Valid values are 8, 12, 16,..., 100. DIC is supported for any setting > 8. A default of 12 must be set to conform to IEEE802.3ae. - WAN Mode : Stretch factor. Valid values are 4 ... 15. The stretch factor is calculated as (value+1)*8. A default of 12 must be set to conform to IEEE802.3ae (i.e. 13*8=104). A larger value shrinks the IPG (increasing bandwidth). - The reset value of 12 leads to IEEE802.3ae conformant behavior in both modes. - Note : WAN mode is only available in 10G mode of operation. */ - unsigned int msmLineTxIpgLength : 6; /* 1E.9022.5:0 R/W Default = 0x0C */ - /* Tx IPG length */ - unsigned int reserved0 : 10; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Tx IPG Control Register */ - union - { - struct - { - /*! \brief 1E.9023.F:0 MSM Line Tx IPG Reserved - AQ_MsmLineTxIpgControlRegister_HHD.u1.bits_1.msmLineTxIpgReserved - - - - Value always 0, writes ignored - */ - unsigned int msmLineTxIpgReserved : 16; /* 1E.9023.F:0 */ - /* Value always 0, writes ignored */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineTxIpgControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Tx Good Frames Counter Register: 1E.9040 */ -/* MSM Line Tx Good Frames Counter Register: 1E.9040 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Good Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9040.F:0 ROS MSM Line Tx Good Frames Counter 0 [F:0] - AQ_MsmLineTxGoodFramesCounterRegister_HHD.u0.bits_0.msmLineTxGoodFramesCounter_0 - - Default = 0x0000 - - Tx good frame counter bits 15:0 - - Notes: - Count of frames transmitted without error (Including pause frames). */ - unsigned int msmLineTxGoodFramesCounter_0 : 16; /* 1E.9040.F:0 ROS Default = 0x0000 */ - /* Tx good frame counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Good Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9041.F:0 ROS MSM Line Tx Good Frames Counter 1 [F:0] - AQ_MsmLineTxGoodFramesCounterRegister_HHD.u1.bits_1.msmLineTxGoodFramesCounter_1 - - Default = 0x0000 - - Tx good frame counter bits 31:16 - - - Notes: - Count of frames transmitted without error (Including pause frames). */ - unsigned int msmLineTxGoodFramesCounter_1 : 16; /* 1E.9041.F:0 ROS Default = 0x0000 */ - /* Tx good frame counter bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineTxGoodFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Rx Good Frames Counter Register: 1E.9044 */ -/* MSM Line Rx Good Frames Counter Register: 1E.9044 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Good Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9044.F:0 ROS MSM Line Rx Good Frames Counter 0 [F:0] - AQ_MsmLineRxGoodFramesCounterRegister_HHD.u0.bits_0.msmLineRxGoodFramesCounter_0 - - Default = 0x0000 - - Rx good frame counter bits 15:0 - - Notes: - Count of frames received without error (Including pause frames). */ - unsigned int msmLineRxGoodFramesCounter_0 : 16; /* 1E.9044.F:0 ROS Default = 0x0000 */ - /* Rx good frame counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Good Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9045.F:0 ROS MSM Line Rx Good Frames Counter 1 [F:0] - AQ_MsmLineRxGoodFramesCounterRegister_HHD.u1.bits_1.msmLineRxGoodFramesCounter_1 - - Default = 0x0000 - - Rx good frame counter bits 31:16 - - Notes: - Count of frames received without error (Including pause frames). */ - unsigned int msmLineRxGoodFramesCounter_1 : 16; /* 1E.9045.F:0 ROS Default = 0x0000 */ - /* Rx good frame counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineRxGoodFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Rx FCS Errors Counter Register: 1E.9048 */ -/* MSM Line Rx FCS Errors Counter Register: 1E.9048 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Rx FCS Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.9048.F:0 ROS MSM Line FCS Error Counter 0 [F:0] - AQ_MsmLineRxFcsErrorsCounterRegister_HHD.u0.bits_0.msmLineFcsErrorCounter_0 - - Default = 0x0000 - - Frame check sequence error counter bits 15:0 - - Notes: - Count of frames for which a CRC-32 Error is detected but the frame is otherwise of correct length. */ - unsigned int msmLineFcsErrorCounter_0 : 16; /* 1E.9048.F:0 ROS Default = 0x0000 */ - /* Frame check sequence error counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Rx FCS Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.9049.F:0 ROS MSM Line FCS Error Counter 1 [F:0] - AQ_MsmLineRxFcsErrorsCounterRegister_HHD.u1.bits_1.msmLineFcsErrorCounter_1 - - Default = 0x0000 - - Frame check sequence error counter bits 31:16 - - Notes: - Count of frames for which a CRC-32 Error is detected but the frame is otherwise of correct length. */ - unsigned int msmLineFcsErrorCounter_1 : 16; /* 1E.9049.F:0 ROS Default = 0x0000 */ - /* Frame check sequence error counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineRxFcsErrorsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Rx Alignment Errors Counter Register: 1E.904C */ -/* MSM Line Rx Alignment Errors Counter Register: 1E.904C */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Alignment Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.904C.F:0 ROS MSM Line Alignment Error Counter 0 [F:0] - AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD.u0.bits_0.msmLineAlignmentErrorCounter_0 - - Default = 0x0000 - - Alignment error counter bits 15:0 - - Notes: - Count of frames received with an alignment error. */ - unsigned int msmLineAlignmentErrorCounter_0 : 16; /* 1E.904C.F:0 ROS Default = 0x0000 */ - /* Alignment error counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Alignment Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.904D.F:0 ROS MSM Line Alignment Error Counter 1 [F:0] - AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD.u1.bits_1.msmLineAlignmentErrorCounter_1 - - Default = 0x0000 - - Alignment error counter bits 31:16 - - Notes: - Count of frames received with an alignment error. */ - unsigned int msmLineAlignmentErrorCounter_1 : 16; /* 1E.904D.F:0 ROS Default = 0x0000 */ - /* Alignment error counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Tx Pause Frames Counter Register: 1E.9050 */ -/* MSM Line Tx Pause Frames Counter Register: 1E.9050 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Pause Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9050.F:0 ROS MSM Line Tx Pause Frames Counter 0 [F:0] - AQ_MsmLineTxPauseFramesCounterRegister_HHD.u0.bits_0.msmLineTxPauseFramesCounter_0 - - Default = 0x0000 - - Tx pause frame counter bits 15:0 - - Notes: - Valid pause frames transmitted. */ - unsigned int msmLineTxPauseFramesCounter_0 : 16; /* 1E.9050.F:0 ROS Default = 0x0000 */ - /* Tx pause frame counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Pause Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9051.F:0 ROS MSM Line Tx Pause Frames Counter 1 [F:0] - AQ_MsmLineTxPauseFramesCounterRegister_HHD.u1.bits_1.msmLineTxPauseFramesCounter_1 - - Default = 0x0000 - - Tx pause frame counter bits 31:16 - - - Notes: - Valid pause frames transmitted. */ - unsigned int msmLineTxPauseFramesCounter_1 : 16; /* 1E.9051.F:0 ROS Default = 0x0000 */ - /* Tx pause frame counter bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineTxPauseFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Rx Pause Frames Counter Register: 1E.9054 */ -/* MSM Line Rx Pause Frames Counter Register: 1E.9054 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Pause Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9054.F:0 ROS MSM Line Rx Pause Frames Counter 0 [F:0] - AQ_MsmLineRxPauseFramesCounterRegister_HHD.u0.bits_0.msmLineRxPauseFramesCounter_0 - - Default = 0x0000 - - Rx pause frame counter bits 15:0 - - Notes: - Valid pause frames received. */ - unsigned int msmLineRxPauseFramesCounter_0 : 16; /* 1E.9054.F:0 ROS Default = 0x0000 */ - /* Rx pause frame counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Pause Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9055.F:0 ROS MSM Line Rx Pause Frames Counter 1 [F:0] - AQ_MsmLineRxPauseFramesCounterRegister_HHD.u1.bits_1.msmLineRxPauseFramesCounter_1 - - Default = 0x0000 - - Rx pause frame counter bits 31:16 - - Notes: - Valid pause frames received. */ - unsigned int msmLineRxPauseFramesCounter_1 : 16; /* 1E.9055.F:0 ROS Default = 0x0000 */ - /* Rx pause frame counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineRxPauseFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Rx Too Long Errors Counter Register: 1E.9058 */ -/* MSM Line Rx Too Long Errors Counter Register: 1E.9058 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Too Long Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.9058.F:0 ROS MSM Line Rx Too Long Errors Counter 0 [F:0] - AQ_MsmLineRxTooLongErrorsCounterRegister_HHD.u0.bits_0.msmLineRxTooLongErrorsCounter_0 - - Default = 0x0000 - - Too-long errors counter bits 15:0 - - Notes: - Frame received exceeded the maximum length programmed with register FRM_LGTH. */ - unsigned int msmLineRxTooLongErrorsCounter_0 : 16; /* 1E.9058.F:0 ROS Default = 0x0000 */ - /* Too-long errors counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Too Long Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.9059.F:0 ROS MSM Line Rx Too Long Errors Counter 1 [F:0] - AQ_MsmLineRxTooLongErrorsCounterRegister_HHD.u1.bits_1.msmLineRxTooLongErrorsCounter_1 - - Default = 0x0000 - - Too-long errors counter bits 31:16 - - Notes: - Frame received exceeded the maximum length programmed with register FRM_LGTH. */ - unsigned int msmLineRxTooLongErrorsCounter_1 : 16; /* 1E.9059.F:0 ROS Default = 0x0000 */ - /* Too-long errors counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineRxTooLongErrorsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Rx In Range Length Errors Counter Register: 1E.905C */ -/* MSM Line Rx In Range Length Errors Counter Register: 1E.905C */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Rx In Range Length Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.905C.F:0 ROS MSM Line Rx In Range Length Errors Counter 0 [F:0] - AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD.u0.bits_0.msmLineRxInRangeLengthErrorsCounter_0 - - Default = 0x0000 - - In-range-length errors counter bits 15:0 - - Notes: - A count of frames with a length/type field value between 46 (VLAN: 42) and less than 0x0600, that does not match the number of payload data octets received. Should count also if length/type field is less than 46 (VLAN: 42) and the frame is longer than 64 bytes. */ - unsigned int msmLineRxInRangeLengthErrorsCounter_0 : 16; /* 1E.905C.F:0 ROS Default = 0x0000 */ - /* In-range-length errors counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Rx In Range Length Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.905D.F:0 ROS MSM Line Rx In Range Length Errors Counter 1 [F:0] - AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD.u1.bits_1.msmLineRxInRangeLengthErrorsCounter_1 - - Default = 0x0000 - - In-range-length errors counter bits 31:16 - - Notes: - A count of frames with a length/type field value between 46 (VLAN: 42) and less than 0x0600, that does not match the number of payload data octets received. Should count also if length/type field is less than 46 (VLAN: 42) and the frame is longer than 64 bytes. */ - unsigned int msmLineRxInRangeLengthErrorsCounter_1 : 16; /* 1E.905D.F:0 ROS Default = 0x0000 */ - /* In-range-length errors counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Tx VLAN Frames Counter Register: 1E.9060 */ -/* MSM Line Tx VLAN Frames Counter Register: 1E.9060 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Tx VLAN Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9060.F:0 ROS MSM Line Tx VLAN Frames Counter 0 [F:0] - AQ_MsmLineTxVlanFramesCounterRegister_HHD.u0.bits_0.msmLineTxVlanFramesCounter_0 - - Default = 0x0000 - - Tx VLAN frames counter bits 15:0 - - Notes: - Valid VLAN tagged frames transmitted. */ - unsigned int msmLineTxVlanFramesCounter_0 : 16; /* 1E.9060.F:0 ROS Default = 0x0000 */ - /* Tx VLAN frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Tx VLAN Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9061.F:0 ROS MSM Line Tx VLAN Frames Counter 1 [F:0] - AQ_MsmLineTxVlanFramesCounterRegister_HHD.u1.bits_1.msmLineTxVlanFramesCounter_1 - - Default = 0x0000 - - Tx VLAN frames counter bits 31:16 - - Notes: - Valid VLAN tagged frames transmitted. */ - unsigned int msmLineTxVlanFramesCounter_1 : 16; /* 1E.9061.F:0 ROS Default = 0x0000 */ - /* Tx VLAN frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineTxVlanFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Rx VLAN Frames Counter Register: 1E.9064 */ -/* MSM Line Rx VLAN Frames Counter Register: 1E.9064 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Rx VLAN Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9064.F:0 ROS MSM Line Rx VLAN Frames Counter 0 [F:0] - AQ_MsmLineRxVlanFramesCounterRegister_HHD.u0.bits_0.msmLineRxVlanFramesCounter_0 - - Default = 0x0000 - - Rx VLAN frames counter bits 15:0 - - Notes: - Valid VLAN tagged frames received. */ - unsigned int msmLineRxVlanFramesCounter_0 : 16; /* 1E.9064.F:0 ROS Default = 0x0000 */ - /* Rx VLAN frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Rx VLAN Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9065.F:0 ROS MSM Line Rx VLAN Frames Counter 1 [F:0] - AQ_MsmLineRxVlanFramesCounterRegister_HHD.u1.bits_1.msmLineRxVlanFramesCounter_1 - - Default = 0x0000 - - Rx VLAN frames counter bits 31:16 - - Notes: - Valid VLAN tagged frames received. */ - unsigned int msmLineRxVlanFramesCounter_1 : 16; /* 1E.9065.F:0 ROS Default = 0x0000 */ - /* Rx VLAN frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineRxVlanFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Tx Octets Counter Register: 1E.9068 */ -/* MSM Line Tx Octets Counter Register: 1E.9068 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Octets Counter Register */ - union - { - struct - { - /*! \brief 1E.9068.F:0 ROS MSM Line Tx Octets Counter 0 [F:0] - AQ_MsmLineTxOctetsCounterRegister_HHD.u0.bits_0.msmLineTxOctetsCounter_0 - - Default = 0x0000 - - Tx octets counter bits 15:0 - - Notes: - All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ - unsigned int msmLineTxOctetsCounter_0 : 16; /* 1E.9068.F:0 ROS Default = 0x0000 */ - /* Tx octets counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Octets Counter Register */ - union - { - struct - { - /*! \brief 1E.9069.F:0 ROS MSM Line Tx Octets Counter 1 [F:0] - AQ_MsmLineTxOctetsCounterRegister_HHD.u1.bits_1.msmLineTxOctetsCounter_1 - - Default = 0x0000 - - Tx octets counter bits 31:16 - - Notes: - All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ - unsigned int msmLineTxOctetsCounter_1 : 16; /* 1E.9069.F:0 ROS Default = 0x0000 */ - /* Tx octets counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of MSM Line Tx Octets Counter Register */ - union - { - struct - { - /*! \brief 1E.906A.F:0 ROS MSM Line Tx Octets Counter 2 [F:0] - AQ_MsmLineTxOctetsCounterRegister_HHD.u2.bits_2.msmLineTxOctetsCounter_2 - - Default = 0x0000 - - Tx octets counter bits 47:32 - - Notes: - All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ - unsigned int msmLineTxOctetsCounter_2 : 16; /* 1E.906A.F:0 ROS Default = 0x0000 */ - /* Tx octets counter bits 47:32 */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of MSM Line Tx Octets Counter Register */ - union - { - struct - { - /*! \brief 1E.906B.F:0 ROS MSM Line Tx Octets Counter 3 [F:0] - AQ_MsmLineTxOctetsCounterRegister_HHD.u3.bits_3.msmLineTxOctetsCounter_3 - - Default = 0x0000 - - Tx octets counter bits 63:48 - - Notes: - All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ - unsigned int msmLineTxOctetsCounter_3 : 16; /* 1E.906B.F:0 ROS Default = 0x0000 */ - /* Tx octets counter bits 63:48 */ - } bits_3; - uint16_t word_3; - } u3; -} AQ_MsmLineTxOctetsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Rx Octets Counter Register: 1E.906C */ -/* MSM Line Rx Octets Counter Register: 1E.906C */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Octets Counter Register */ - union - { - struct - { - /*! \brief 1E.906C.F:0 ROS MSM Line Rx Octets Counter 0 [F:0] - AQ_MsmLineRxOctetsCounterRegister_HHD.u0.bits_0.msmLineRxOctetsCounter_0 - - Default = 0x0000 - - Rx octets counter bits 15:0 - - Notes: - All octets received except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames received. */ - unsigned int msmLineRxOctetsCounter_0 : 16; /* 1E.906C.F:0 ROS Default = 0x0000 */ - /* Rx octets counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Octets Counter Register */ - union - { - struct - { - /*! \brief 1E.906D.F:0 ROS MSM Line Rx Octets Counter 1 [F:0] - AQ_MsmLineRxOctetsCounterRegister_HHD.u1.bits_1.msmLineRxOctetsCounter_1 - - Default = 0x0000 - - Rx octets counter bits 31:16 - - Notes: - All octets received except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames received. */ - unsigned int msmLineRxOctetsCounter_1 : 16; /* 1E.906D.F:0 ROS Default = 0x0000 */ - /* Rx octets counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineRxOctetsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Rx Unicast Frames Counter Register: 1E.9070 */ -/* MSM Line Rx Unicast Frames Counter Register: 1E.9070 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Unicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9070.F:0 ROS MSM Line Rx Unicast Frames Counter 0 [F:0] - AQ_MsmLineRxUnicastFramesCounterRegister_HHD.u0.bits_0.msmLineRxUnicastFramesCounter_0 - - Default = 0x0000 - - Rx unicast frames counter bits 15:0 - - Notes: - Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '0'. */ - unsigned int msmLineRxUnicastFramesCounter_0 : 16; /* 1E.9070.F:0 ROS Default = 0x0000 */ - /* Rx unicast frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Unicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9071.F:0 ROS MSM Line Rx Unicast Frames Counter 1 [F:0] - AQ_MsmLineRxUnicastFramesCounterRegister_HHD.u1.bits_1.msmLineRxUnicastFramesCounter_1 - - Default = 0x0000 - - Rx unicast frames counter bits 31:16 - - Notes: - Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '0'. */ - unsigned int msmLineRxUnicastFramesCounter_1 : 16; /* 1E.9071.F:0 ROS Default = 0x0000 */ - /* Rx unicast frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineRxUnicastFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Rx Multicast Frames Counter Register: 1E.9074 */ -/* MSM Line Rx Multicast Frames Counter Register: 1E.9074 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Multicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9074.F:0 ROS MSM Line Rx Multicast Frames Counter 0 [F:0] - AQ_MsmLineRxMulticastFramesCounterRegister_HHD.u0.bits_0.msmLineRxMulticastFramesCounter_0 - - Default = 0x0000 - - Rx multicast frames counter bits 15:0 - - Notes: - Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '1' but not the broadcast address (all bits set '1' ). Pause frames are not counted. */ - unsigned int msmLineRxMulticastFramesCounter_0 : 16; /* 1E.9074.F:0 ROS Default = 0x0000 */ - /* Rx multicast frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Multicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9075.F:0 ROS MSM Line Rx Multicast Frames Counter 1 [F:0] - AQ_MsmLineRxMulticastFramesCounterRegister_HHD.u1.bits_1.msmLineRxMulticastFramesCounter_1 - - Default = 0x0000 - - Rx multicast frames counter bits 31:16 - - Notes: - Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '1' but not the broadcast address (all bits set '1' ). Pause frames are not counted. */ - unsigned int msmLineRxMulticastFramesCounter_1 : 16; /* 1E.9075.F:0 ROS Default = 0x0000 */ - /* Rx multicast frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineRxMulticastFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Rx Broadcast Frames Counter Register: 1E.9078 */ -/* MSM Line Rx Broadcast Frames Counter Register: 1E.9078 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Broadcast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9078.F:0 ROS MSM Line Rx Broadcast Frames Counter 0 [F:0] - AQ_MsmLineRxBroadcastFramesCounterRegister_HHD.u0.bits_0.msmLineRxBroadcastFramesCounter_0 - - Default = 0x0000 - - Rx broadcast frames counter bits 15:0 - - Notes: - Incremented with each valid frame received on the receive FIFO interface (FIFO) and all bits of the destination address were set '1'. */ - unsigned int msmLineRxBroadcastFramesCounter_0 : 16; /* 1E.9078.F:0 ROS Default = 0x0000 */ - /* Rx broadcast frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Broadcast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9079.F:0 ROS MSM Line Rx Broadcast Frames Counter 1 [F:0] - AQ_MsmLineRxBroadcastFramesCounterRegister_HHD.u1.bits_1.msmLineRxBroadcastFramesCounter_1 - - Default = 0x0000 - - Rx broadcast frames counter bits 31:16 - - Notes: - Incremented with each valid frame received on the receive FIFO interface (FIFO) and all bits of the destination address were set '1'. */ - unsigned int msmLineRxBroadcastFramesCounter_1 : 16; /* 1E.9079.F:0 ROS Default = 0x0000 */ - /* Rx broadcast frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineRxBroadcastFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Tx Errors Counter Register: 1E.907C */ -/* MSM Line Tx Errors Counter Register: 1E.907C */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.907C.F:0 ROS MSM Line Tx Errors Counter 0 [F:0] - AQ_MsmLineTxErrorsCounterRegister_HHD.u0.bits_0.msmLineTxErrorsCounter_0 - - Default = 0x0000 - - Rx errors counter bits 15:0 - - Notes: - Number of frames transmitted with error: - - FIFO Overflow Errors - - FIFO Underflow Errors */ - unsigned int msmLineTxErrorsCounter_0 : 16; /* 1E.907C.F:0 ROS Default = 0x0000 */ - /* Rx errors counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.907D.F:0 ROS MSM Line Tx Errors Counter 1 [F:0] - AQ_MsmLineTxErrorsCounterRegister_HHD.u1.bits_1.msmLineTxErrorsCounter_1 - - Default = 0x0000 - - Tx errors counter bits 31:16 - - Notes: - Number of frames transmitted with error: - - FIFO Overflow Errors - - FIFO Underflow Errors */ - unsigned int msmLineTxErrorsCounter_1 : 16; /* 1E.907D.F:0 ROS Default = 0x0000 */ - /* Tx errors counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineTxErrorsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Tx Unicast Frames Counter Register: 1E.9084 */ -/* MSM Line Tx Unicast Frames Counter Register: 1E.9084 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Unicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9084.F:0 ROS MSM Line Tx Unicast Frames Counter 0 [F:0] - AQ_MsmLineTxUnicastFramesCounterRegister_HHD.u0.bits_0.msmLineTxUnicastFramesCounter_0 - - Default = 0x0000 - - Tx unicast frames counter bits 15:0 - - Notes: - Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '0'. */ - unsigned int msmLineTxUnicastFramesCounter_0 : 16; /* 1E.9084.F:0 ROS Default = 0x0000 */ - /* Tx unicast frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Unicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9085.F:0 ROS MSM Line Tx Unicast Frames Counter 1 [F:0] - AQ_MsmLineTxUnicastFramesCounterRegister_HHD.u1.bits_1.msmLineTxUnicastFramesCounter_1 - - Default = 0x0000 - - Tx unicast frames counter bits 31:16 - - Notes: - Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '0'. */ - unsigned int msmLineTxUnicastFramesCounter_1 : 16; /* 1E.9085.F:0 ROS Default = 0x0000 */ - /* Tx unicast frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineTxUnicastFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Tx Multicast Frames Counter Register: 1E.9088 */ -/* MSM Line Tx Multicast Frames Counter Register: 1E.9088 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Multicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9088.F:0 ROS MSM Line Tx Multicast Frames Counter 0 [F:0] - AQ_MsmLineTxMulticastFramesCounterRegister_HHD.u0.bits_0.msmLineTxMulticastFramesCounter_0 - - Default = 0x0000 - - Tx multicast frames counter bits 15:0 - - Notes: - Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '1' but not the broadcast address (all bits '1'). */ - unsigned int msmLineTxMulticastFramesCounter_0 : 16; /* 1E.9088.F:0 ROS Default = 0x0000 */ - /* Tx multicast frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Multicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9089.F:0 ROS MSM Line Tx Multicast Frames Counter 1 [F:0] - AQ_MsmLineTxMulticastFramesCounterRegister_HHD.u1.bits_1.msmLineTxMulticastFramesCounter_1 - - Default = 0x0000 - - Tx multicast frames counter bits 31:16 - - Notes: - Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '1' but not the broadcast address (all bits '1'). */ - unsigned int msmLineTxMulticastFramesCounter_1 : 16; /* 1E.9089.F:0 ROS Default = 0x0000 */ - /* Tx multicast frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineTxMulticastFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Tx Broadcast Frames Counter Register: 1E.908C */ -/* MSM Line Tx Broadcast Frames Counter Register: 1E.908C */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Broadcast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.908C.F:0 ROS MSM Line Tx Broadcast Frames Counter 0 [F:0] - AQ_MsmLineTxBroadcastFramesCounterRegister_HHD.u0.bits_0.msmLineTxBroadcastFramesCounter_0 - - Default = 0x0000 - - Tx broadcast frames counter bits 15:0 - - Notes: - Incremented with each frame written to the FIFO interface and all bits of the destination address set to '1'. */ - unsigned int msmLineTxBroadcastFramesCounter_0 : 16; /* 1E.908C.F:0 ROS Default = 0x0000 */ - /* Tx broadcast frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Broadcast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.908D.F:0 ROS MSM Line Tx Broadcast Frames Counter 1 [F:0] - AQ_MsmLineTxBroadcastFramesCounterRegister_HHD.u1.bits_1.msmLineTxBroadcastFramesCounter_1 - - Default = 0x0000 - - Tx broadcast frames counter bits 31:16 - - Notes: - Incremented with each frame written to the FIFO interface and all bits of the destination address set to '1'. */ - unsigned int msmLineTxBroadcastFramesCounter_1 : 16; /* 1E.908D.F:0 ROS Default = 0x0000 */ - /* Tx broadcast frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineTxBroadcastFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Rx Errors Counter Register: 1E.90C8 */ -/* MSM Line Rx Errors Counter Register: 1E.90C8 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.90C8.F:0 ROS MSM Line Rx Errors Counter 0 [F:0] - AQ_MsmLineRxErrorsCounterRegister_HHD.u0.bits_0.msmLineRxErrorsCounter_0 - - Default = 0x0000 - - Rx errors counter bits 15:0 - - Notes: - Number of frames received with error: - - FIFO Overflow Errors - - CRC Errors - - Payload Length Errors - - Jabber and Oversized Errors - - Alignment Errors - - The dedicated Error Code (0xfe, not a code error) was received */ - unsigned int msmLineRxErrorsCounter_0 : 16; /* 1E.90C8.F:0 ROS Default = 0x0000 */ - /* Rx errors counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.90C9.F:0 ROS MSM Line Rx Errors Counter 1 [F:0] - AQ_MsmLineRxErrorsCounterRegister_HHD.u1.bits_1.msmLineRxErrorsCounter_1 - - Default = 0x0000 - - Rx errors counter bits 31:16 - - Notes: - Number of frames received with error: - - FIFO Overflow Errors - - CRC Errors - - Payload Length Errors - - Jabber and Oversized Errors - - Alignment Errors - - The dedicated Error Code (0xfe, not a code error) was received */ - unsigned int msmLineRxErrorsCounter_1 : 16; /* 1E.90C9.F:0 ROS Default = 0x0000 */ - /* Rx errors counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineRxErrorsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Control: 1E.C000 */ -/* Global Control: 1E.C000 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Control */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Control */ - union - { - struct - { - /*! \brief 1E.C001.0 R/W uP Run Stall - AQ_GlobalControl_HHD.u1.bits_1.upRunStall - - Default = 0x0 - - 1 = uP Run Stall - 0 = uP normal mode - - - Notes: - Deactivates the uP. */ - unsigned int upRunStall : 1; /* 1E.C001.0 R/W Default = 0x0 */ - /* 1 = uP Run Stall - 0 = uP normal mode - */ - unsigned int reserved1 : 5; - /*! \brief 1E.C001.6 R/W uP Run Stall Override - AQ_GlobalControl_HHD.u1.bits_1.upRunStallOverride - - Default = 0x0 - - 0 = uP Run Stall from "MDIO Boot Load" pin. - 1 = uP Run Stall from See MCP Run Stall bit - - - - Notes: - This bit selects the uP Run Stall from either the "MDIO Boot Load" pin or the See MCP Run Stall bit. Pin no longer brought out as deprecated. */ - unsigned int upRunStallOverride : 1; /* 1E.C001.6 R/W Default = 0x0 */ - /* 0 = uP Run Stall from "MDIO Boot Load" pin. - 1 = uP Run Stall from See MCP Run Stall bit - - */ - unsigned int reserved0 : 8; - /*! \brief 1E.C001.F R/W uP Reset - AQ_GlobalControl_HHD.u1.bits_1.upReset - - Default = 0x0 - - 1 = Reset - - - Notes: - Resets the uP and the PIF master and slave bus. Will be active for a minimum of 100 microseconds. */ - unsigned int upReset : 1; /* 1E.C001.F R/W Default = 0x0 */ - /* 1 = Reset - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_GlobalControl_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Reset Control: 1E.C006 */ -/* Global Reset Control: 1E.C006 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Reset Control */ - union - { - struct - { - unsigned int reserved1 : 14; - /*! \brief 1E.C006.E R/WPD Global MMD Reset Disable - AQ_GlobalResetControl_HHD.u0.bits_0.globalMMD_ResetDisable - - Provisionable Default = 0x0 - - 1 = Disable the S/W reset to the Global MMD registers - 0 = Enable the S/W reset to the Global MMD registers - - - Notes: - Setting this bit prevents a Global S/W reset or Global S/W reset from resetting the Global MMD registers */ - unsigned int globalMMD_ResetDisable : 1; /* 1E.C006.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Disable the S/W reset to the Global MMD registers - 0 = Enable the S/W reset to the Global MMD registers - */ - unsigned int reserved0 : 1; - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalResetControl_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Diagnostic Provisioning: 1E.C400 */ -/* Global Diagnostic Provisioning: 1E.C400 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Diagnostic Provisioning */ - union - { - struct - { - unsigned int reserved0 : 15; - /*! \brief 1E.C400.F R/WPD Enable Diagnostics - AQ_GlobalDiagnosticProvisioning_HHD.u0.bits_0.enableDiagnostics - - Provisionable Default = 0x1 - - 1 = Chip performs diagnostics on power-up - */ - unsigned int enableDiagnostics : 1; /* 1E.C400.F R/WPD Provisionable Default = 0x1 */ - /* 1 = Chip performs diagnostics on power-up */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalDiagnosticProvisioning_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Thermal Provisioning: 1E.C420 */ -/* Global Thermal Provisioning: 1E.C420 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Thermal Provisioning */ - union - { - struct - { - /*! \brief 1E.C420.F:0 R/WPD Reserved 0 [F:0] - AQ_GlobalThermalProvisioning_HHD.u0.bits_0.reserved_0 - - Provisionable Default = 0x0000 - - Internal reserved - do not modify - - */ - unsigned int reserved_0 : 16; /* 1E.C420.F:0 R/WPD Provisionable Default = 0x0000 */ - /* Internal reserved - do not modify - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Thermal Provisioning */ - union - { - struct - { - /*! \brief 1E.C421.F:0 R/WPD High Temp Failure Threshold [F:0] - AQ_GlobalThermalProvisioning_HHD.u1.bits_1.highTempFailureThreshold - - Provisionable Default = 0x4600 - - [F:0] of high temperature failure threshold - - Notes: - 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 70 degreesC. - - In XENPAK mode, F/W will use the XENPAK register 1.A000 - 1.A001: instead of this register. - - NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ - unsigned int highTempFailureThreshold : 16; /* 1E.C421.F:0 R/WPD Provisionable Default = 0x4600 */ - /* [F:0] of high temperature failure threshold */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global Thermal Provisioning */ - union - { - struct - { - /*! \brief 1E.C422.F:0 R/WPD Low Temp Failure Threshold [F:0] - AQ_GlobalThermalProvisioning_HHD.u2.bits_2.lowTempFailureThreshold - - Provisionable Default = 0x0000 - - [F:0] of low temperature failure threshold - - Notes: - 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 0 degreesC. - - In XENPAK mode, F/W will use the XENPAK register 1.A002 - 1.A003: instead of this register. - - NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ - unsigned int lowTempFailureThreshold : 16; /* 1E.C422.F:0 R/WPD Provisionable Default = 0x0000 */ - /* [F:0] of low temperature failure threshold */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global Thermal Provisioning */ - union - { - struct - { - /*! \brief 1E.C423.F:0 R/WPD High Temp Warning Threshold [F:0] - AQ_GlobalThermalProvisioning_HHD.u3.bits_3.highTempWarningThreshold - - Provisionable Default = 0x3C00 - - [F:0] of high temperature warning threshold - - Notes: - 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD008. Default is 60 degreesC. - - In XENPAK mode, F/W will use the XENPAK register 1.A004 - 1.A005: instead of this register. - - NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ - unsigned int highTempWarningThreshold : 16; /* 1E.C423.F:0 R/WPD Provisionable Default = 0x3C00 */ - /* [F:0] of high temperature warning threshold */ - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of Global Thermal Provisioning */ - union - { - struct - { - /*! \brief 1E.C424.F:0 R/WPD Low Temp Warning Threshold [F:0] - AQ_GlobalThermalProvisioning_HHD.u4.bits_4.lowTempWarningThreshold - - Provisionable Default = 0x0A00 - - [F:0] of low temperature warning threshold - - Notes: - 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 10 degreesC. - - In XENPAK mode, F/W will use the XENPAK register 1.A006 - 1.A007: instead of this register. - - NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ - unsigned int lowTempWarningThreshold : 16; /* 1E.C424.F:0 R/WPD Provisionable Default = 0x0A00 */ - /* [F:0] of low temperature warning threshold */ - } bits_4; - uint16_t word_4; - } u4; -} AQ_GlobalThermalProvisioning_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global LED Provisioning: 1E.C430 */ -/* Global LED Provisioning: 1E.C430 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global LED Provisioning */ - union - { - struct - { - /*! \brief 1E.C430.1:0 R/WPD LED #0 Activity Stretch [1:0] - AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0ActivityStretch - - Provisionable Default = 0x3 - - [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - - */ - unsigned int led_0ActivityStretch : 2; /* 1E.C430.1:0 R/WPD Provisionable Default = 0x3 */ - /* [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - */ - /*! \brief 1E.C430.2 R/WPD LED #0 Transmit Activity - AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0TransmitActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on transmit activity - - */ - unsigned int led_0TransmitActivity : 1; /* 1E.C430.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on transmit activity - */ - /*! \brief 1E.C430.3 R/WPD LED #0 Receive Activity - AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0ReceiveActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on receive activity - - */ - unsigned int led_0ReceiveActivity : 1; /* 1E.C430.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on receive activity - */ - /*! \brief 1E.C430.4 R/WPD LED #0 Connecting - AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0Connecting - - Provisionable Default = 0x0 - - 1 = LED is on when attempting to connect. - - */ - unsigned int led_0Connecting : 1; /* 1E.C430.4 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when attempting to connect. - */ - /*! \brief 1E.C430.5 R/WPD LED #0 100 Mb/s Link Established - AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0_100Mb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 100 Mb/s. - - */ - unsigned int led_0_100Mb_sLinkEstablished : 1; /* 1E.C430.5 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 100 Mb/s. - */ - /*! \brief 1E.C430.6 R/WPD LED #0 1 Gb/s Link Established - AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0_1Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 1 Gb/s - - */ - unsigned int led_0_1Gb_sLinkEstablished : 1; /* 1E.C430.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 1 Gb/s - */ - /*! \brief 1E.C430.7 R/WPD LED #0 10 Gb/s Link Established - AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0_10Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 10 Gb/s - - */ - unsigned int led_0_10Gb_sLinkEstablished : 1; /* 1E.C430.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 10 Gb/s - */ - /*! \brief 1E.C430.8 R/WPD LED #0 Manual Set - AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0ManualSet - - Provisionable Default = 0x0 - - 1 = LED On - - */ - unsigned int led_0ManualSet : 1; /* 1E.C430.8 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED On - */ - /*! \brief 1E.C430.D:9 R/WPD Reserved Provisioning C430 [4:0] - AQ_GlobalLedProvisioning_HHD.u0.bits_0.reservedProvisioningC430 - - Provisionable Default = 0x00 - - Reserved for future use - */ - unsigned int reservedProvisioningC430 : 5; /* 1E.C430.D:9 R/WPD Provisionable Default = 0x00 */ - /* Reserved for future use */ - unsigned int reserved0 : 2; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global LED Provisioning */ - union - { - struct - { - /*! \brief 1E.C431.1:0 R/WPD LED #1 Activity Stretch [1:0] - AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1ActivityStretch - - Provisionable Default = 0x3 - - [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - - */ - unsigned int led_1ActivityStretch : 2; /* 1E.C431.1:0 R/WPD Provisionable Default = 0x3 */ - /* [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - */ - /*! \brief 1E.C431.2 R/WPD LED #1 Transmit Activity - AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1TransmitActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on transmit activity - - */ - unsigned int led_1TransmitActivity : 1; /* 1E.C431.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on transmit activity - */ - /*! \brief 1E.C431.3 R/WPD LED #1 Receive Activity - AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1ReceiveActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on receive activity - - */ - unsigned int led_1ReceiveActivity : 1; /* 1E.C431.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on receive activity - */ - /*! \brief 1E.C431.4 R/WPD LED #1 Connecting - AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1Connecting - - Provisionable Default = 0x0 - - 1 = LED is on when attempting to connect. - - */ - unsigned int led_1Connecting : 1; /* 1E.C431.4 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when attempting to connect. - */ - /*! \brief 1E.C431.5 R/WPD LED #1 100 Mb/s Link Established - AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1_100Mb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 100 Mb/s. - - */ - unsigned int led_1_100Mb_sLinkEstablished : 1; /* 1E.C431.5 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 100 Mb/s. - */ - /*! \brief 1E.C431.6 R/WPD LED #1 1 Gb/s Link Established - AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1_1Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 1 Gb/s - - */ - unsigned int led_1_1Gb_sLinkEstablished : 1; /* 1E.C431.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 1 Gb/s - */ - /*! \brief 1E.C431.7 R/WPD LED #1 10 Gb/s Link Established - AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1_10Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 10 Gb/s - - */ - unsigned int led_1_10Gb_sLinkEstablished : 1; /* 1E.C431.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 10 Gb/s - */ - /*! \brief 1E.C431.8 R/WPD LED #1 Manual Set - AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1ManualSet - - Provisionable Default = 0x0 - - 1 = LED On - - */ - unsigned int led_1ManualSet : 1; /* 1E.C431.8 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED On - */ - /*! \brief 1E.C431.D:9 R/WPD Reserved Provisioning C431 [4:0] - AQ_GlobalLedProvisioning_HHD.u1.bits_1.reservedProvisioningC431 - - Provisionable Default = 0x00 - - Reserved for future use - */ - unsigned int reservedProvisioningC431 : 5; /* 1E.C431.D:9 R/WPD Provisionable Default = 0x00 */ - /* Reserved for future use */ - unsigned int reserved0 : 2; - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global LED Provisioning */ - union - { - struct - { - /*! \brief 1E.C432.1:0 R/WPD LED #2 Activity Stretch [1:0] - AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2ActivityStretch - - Provisionable Default = 0x3 - - [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - - */ - unsigned int led_2ActivityStretch : 2; /* 1E.C432.1:0 R/WPD Provisionable Default = 0x3 */ - /* [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - */ - /*! \brief 1E.C432.2 R/WPD LED #2 Transmit Activity - AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2TransmitActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on transmit activity - - */ - unsigned int led_2TransmitActivity : 1; /* 1E.C432.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on transmit activity - */ - /*! \brief 1E.C432.3 R/WPD LED #2 Receive Activity - AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2ReceiveActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on receive activity - - */ - unsigned int led_2ReceiveActivity : 1; /* 1E.C432.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on receive activity - */ - /*! \brief 1E.C432.4 R/WPD LED #2 Connecting - AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2Connecting - - Provisionable Default = 0x0 - - 1 = LED is on when attempting to connect. - - */ - unsigned int led_2Connecting : 1; /* 1E.C432.4 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when attempting to connect. - */ - /*! \brief 1E.C432.5 R/WPD LED #2 100 Mb/s Link Established - AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2_100Mb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 100 Mb/s. - */ - unsigned int led_2_100Mb_sLinkEstablished : 1; /* 1E.C432.5 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 100 Mb/s. */ - /*! \brief 1E.C432.6 R/WPD LED #2 1 Gb/s Link Established - AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2_1Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 1 Gb/s - - */ - unsigned int led_2_1Gb_sLinkEstablished : 1; /* 1E.C432.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 1 Gb/s - */ - /*! \brief 1E.C432.7 R/WPD LED #2 10 Gb/s Link Established - AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2_10Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 10 Gb/s - - */ - unsigned int led_2_10Gb_sLinkEstablished : 1; /* 1E.C432.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 10 Gb/s - */ - /*! \brief 1E.C432.8 R/WPD LED #2 Manual Set - AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2ManualSet - - Provisionable Default = 0x0 - - 1 = LED On - - */ - unsigned int led_2ManualSet : 1; /* 1E.C432.8 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED On - */ - /*! \brief 1E.C432.D:9 R/WPD Reserved Provisioning C432 [4:0] - AQ_GlobalLedProvisioning_HHD.u2.bits_2.reservedProvisioningC432 - - Provisionable Default = 0x00 - - Reserved for future use - */ - unsigned int reservedProvisioningC432 : 5; /* 1E.C432.D:9 R/WPD Provisionable Default = 0x00 */ - /* Reserved for future use */ - unsigned int reserved0 : 2; - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global LED Provisioning */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of Global LED Provisioning */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_4; - uint16_t word_4; - } u4; - /*! \brief Union for bit and word level access of word 5 of Global LED Provisioning */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_5; - uint16_t word_5; - } u5; - /*! \brief Union for bit and word level access of word 6 of Global LED Provisioning */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_6; - uint16_t word_6; - } u6; - /*! \brief Union for bit and word level access of word 7 of Global LED Provisioning */ - union - { - struct - { - /*! \brief 1E.C437.0 R/WPD LED Operation Mode - AQ_GlobalLedProvisioning_HHD.u7.bits_7.ledOperationMode - - Provisionable Default = 0x0 - - 1 = LED link activity in Mode #2 - 0 = LED link activity in Aquantia classic mode - - - Notes: - When set to 1, the LED blinking rate is based on Mode #2 algorithm. When set to 0, the LED blinking rate is based on the classic Aquantia algorithm. */ - unsigned int ledOperationMode : 1; /* 1E.C437.0 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED link activity in Mode #2 - 0 = LED link activity in Aquantia classic mode - */ - unsigned int reserved0 : 15; - } bits_7; - uint16_t word_7; - } u7; - /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ - union - { - struct - { - unsigned int reserved : 16; - } bits_8; - uint16_t word_8; - } u8; - /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ - union - { - struct - { - unsigned int reserved : 16; - } bits_9; - uint16_t word_9; - } u9; - /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ - union - { - struct - { - unsigned int reserved : 16; - } bits_10; - uint16_t word_10; - } u10; - /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ - union - { - struct - { - unsigned int reserved : 16; - } bits_11; - uint16_t word_11; - } u11; - /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ - union - { - struct - { - unsigned int reserved : 16; - } bits_12; - uint16_t word_12; - } u12; - /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ - union - { - struct - { - unsigned int reserved : 16; - } bits_13; - uint16_t word_13; - } u13; - /*! \brief Union for bit and word level access of word 14 of Global LED Provisioning */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_14; - uint16_t word_14; - } u14; -} AQ_GlobalLedProvisioning_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global General Provisioning: 1E.C440 */ -/* Global General Provisioning: 1E.C440 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global General Provisioning */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global General Provisioning */ - union - { - struct - { - unsigned int reserved3 : 2; - unsigned int reserved2 : 1; - /*! \brief 1E.C441.3 R/WPD MDIO Preamble Detection Disable - AQ_GlobalGeneralProvisioning_HHD.u1.bits_1.mdioPreambleDetectionDisable - - Provisionable Default = 0x0 - - 1 = Suppress preamble detection on MDIO - 0 = Enable preamble detection on MDIO - - */ - unsigned int mdioPreambleDetectionDisable : 1; /* 1E.C441.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = Suppress preamble detection on MDIO - 0 = Enable preamble detection on MDIO - */ - /*! \brief 1E.C441.4 R/WPD MDIO Drive Configuration - AQ_GlobalGeneralProvisioning_HHD.u1.bits_1.mdioDriveConfiguration - - Provisionable Default = 0x0 - - 0 = MDIO driver is in normal mode - 1 = MDIO driver is in open drain mode - - - Notes: - When the MDIO driver is in open drain mode during a read cycle, "0" data will be actively driven out of the MDIO, "1" data will set the MDIO driver in high impedance state and an external pullup will set the MDIO line to "1". The Turn-Around "0" will also be actively driven out of the MDIO, therefore in open drain mode, the Turn-Around is still "Z0". */ - unsigned int mdioDriveConfiguration : 1; /* 1E.C441.4 R/WPD Provisionable Default = 0x0 */ - /* 0 = MDIO driver is in normal mode - 1 = MDIO driver is in open drain mode - */ - unsigned int reserved1 : 8; - /*! \brief 1E.C441.D R/WPD MDIO Read MSW First Enable - AQ_GlobalGeneralProvisioning_HHD.u1.bits_1.mdioReadMSW_FirstEnable - - Provisionable Default = 0x0 - - 1 = MSW of counter must be read first - 0 = LSW of counter must be read first - - - Notes: - This bit configures whether the MSW or LSW must be read first for counters greater than 16 bits. */ - unsigned int mdioReadMSW_FirstEnable : 1; /* 1E.C441.D R/WPD Provisionable Default = 0x0 */ - /* 1 = MSW of counter must be read first - 0 = LSW of counter must be read first - */ - /*! \brief 1E.C441.E R/WPD MDIO Broadcast Mode Enable - AQ_GlobalGeneralProvisioning_HHD.u1.bits_1.mdioBroadcastModeEnable - - Provisionable Default = 0x0 - - 1 = Enable broadcast on address set in 1E.C446 - 0 = Disable broadcast on n address set in 1E.C446 - - - Notes: - When enabled, writes and load MMD address opcodes are supported. Read opcodes are ignored. */ - unsigned int mdioBroadcastModeEnable : 1; /* 1E.C441.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable broadcast on address set in 1E.C446 - 0 = Disable broadcast on n address set in 1E.C446 - */ - unsigned int reserved0 : 1; - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global General Provisioning */ - union - { - struct - { - /*! \brief 1E.C442.0 R/W Daisy Chain Reset - AQ_GlobalGeneralProvisioning_HHD.u2.bits_2.daisyChainReset - - Default = 0x0 - - 1 = Reset the daisy chain - - - Notes: - Toggling this bit from 0 to 1 will reload the IRAM and DRAM and reset the uP. The uP will be in uP run stall during the reload process. After the reload process, uP run stall will be de-asserted and the uP reset will be asserted. Note that before setting this bit, the See Soft Reset bit needs to be de-asserted. */ - unsigned int daisyChainReset : 1; /* 1E.C442.0 R/W Default = 0x0 */ - /* 1 = Reset the daisy chain - */ - unsigned int reserved0 : 15; - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global General Provisioning */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of Global General Provisioning */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_4; - uint16_t word_4; - } u4; - /*! \brief Union for bit and word level access of word 5 of Global General Provisioning */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_5; - uint16_t word_5; - } u5; - /*! \brief Union for bit and word level access of word 6 of Global General Provisioning */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_6; - uint16_t word_6; - } u6; - /*! \brief Union for bit and word level access of word 7 of Global General Provisioning */ - union - { - struct - { - /*! \brief 1E.C447.4:0 R/WPD MDIO Broadcast Address Configuration [4:0] - AQ_GlobalGeneralProvisioning_HHD.u7.bits_7.mdioBroadcastAddressConfiguration - - Provisionable Default = 0x1F - - Broadcast address - - - Notes: - Allows setting the broadcast address. By default this is set to 0x1F */ - unsigned int mdioBroadcastAddressConfiguration : 5; /* 1E.C447.4:0 R/WPD Provisionable Default = 0x1F */ - /* Broadcast address - */ - unsigned int reserved0 : 11; - } bits_7; - uint16_t word_7; - } u7; - /*! \brief Union for bit and word level access of word 8 of Global General Provisioning */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_8; - uint16_t word_8; - } u8; - /*! \brief Union for bit and word level access of word 9 of Global General Provisioning */ - union - { - struct - { - /*! \brief 1E.C449.6:0 R/W MDIO Preamble Length [6:0] - AQ_GlobalGeneralProvisioning_HHD.u9.bits_9.mdioPreambleLength - - Default = 0x02 - - MDIO Preamble Length - - */ - unsigned int mdioPreambleLength : 7; /* 1E.C449.6:0 R/W Default = 0x02 */ - /* MDIO Preamble Length - */ - unsigned int reserved0 : 9; - } bits_9; - uint16_t word_9; - } u9; -} AQ_GlobalGeneralProvisioning_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global NVR Provisioning: 1E.C450 */ -/* Global NVR Provisioning: 1E.C450 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global NVR Provisioning */ - union - { - struct - { - /*! \brief 1E.C450.1:0 R/WPD NVR Address Length [1:0] - AQ_GlobalNvrProvisioning_HHD.u0.bits_0.nvrAddressLength - - Provisionable Default = 0x2 - - NVR address length ranges from 0 bytes up to 3 bytes - - - Notes: - This sets the length of the address field used in read and write operations. Use of this field is enabled via Bit 8 of See Global NVR Provisioning 2: Address 1E.C451 . - */ - unsigned int nvrAddressLength : 2; /* 1E.C450.1:0 R/WPD Provisionable Default = 0x2 */ - /* NVR address length ranges from 0 bytes up to 3 bytes - */ - unsigned int reserved2 : 2; - /*! \brief 1E.C450.6:4 R/WPD NVR Dummy Length [2:0] - AQ_GlobalNvrProvisioning_HHD.u0.bits_0.nvrDummyLength - - Provisionable Default = 0x0 - - NVR dummy length ranges from 0 bytes to 4 bytes - - - Notes: - This sets the length of the dummy field used in some manufacturer's read status and write status operations. - */ - unsigned int nvrDummyLength : 3; /* 1E.C450.6:4 R/WPD Provisionable Default = 0x0 */ - /* NVR dummy length ranges from 0 bytes to 4 bytes - */ - unsigned int reserved1 : 1; - /*! \brief 1E.C450.A:8 R/WPD NVR Data Length [2:0] - AQ_GlobalNvrProvisioning_HHD.u0.bits_0.nvrDataLength - - Provisionable Default = 0x4 - - NVR data length ranges from 0 bytes to 4 bytes - - - Notes: - This sets the length of the data burst used in read and write operations. - */ - unsigned int nvrDataLength : 3; /* 1E.C450.A:8 R/WPD Provisionable Default = 0x4 */ - /* NVR data length ranges from 0 bytes to 4 bytes - */ - unsigned int reserved0 : 5; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global NVR Provisioning */ - union - { - struct - { - /*! \brief 1E.C451.7:0 R/WPD NVR Clock Divide [7:0] - AQ_GlobalNvrProvisioning_HHD.u1.bits_1.nvrClockDivide - - Provisionable Default = 0xA0 - - NVR clock divide. Clock frequency is divided by the NVR clock divide + 1 - - */ - unsigned int nvrClockDivide : 8; /* 1E.C451.7:0 R/WPD Provisionable Default = 0xA0 */ - /* NVR clock divide. Clock frequency is divided by the NVR clock divide + 1 - */ - /*! \brief 1E.C451.8 R/WPD NVR Address Length Override - AQ_GlobalNvrProvisioning_HHD.u1.bits_1.nvrAddressLengthOverride - - Provisionable Default = 0x0 - - 0 = NVR address length is based on the "NVR_SIZE" pin. - 1 = NVR address length is based on the See NVR Address Length [1:0] register - - - Notes: - When this bit = 0 and NVR_SIZE pin = 0, the NVR address length is 2 bytes. When this bit = 0 and the NVR_SIZE pin = 1, the NVR address length is 3 bytes. When this bit = 1 the NVR address length is from the See NVR Address Length [1:0] */ - unsigned int nvrAddressLengthOverride : 1; /* 1E.C451.8 R/WPD Provisionable Default = 0x0 */ - /* 0 = NVR address length is based on the "NVR_SIZE" pin. - 1 = NVR address length is based on the See NVR Address Length [1:0] register - */ - unsigned int reserved0 : 7; - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global NVR Provisioning */ - union - { - struct - { - /*! \brief 1E.C452.0 R/W NVR Daisy Chain Disable - AQ_GlobalNvrProvisioning_HHD.u2.bits_2.nvrDaisyChainDisable - - Default = 0x0 - - 1 = Disable the Daisy Chain - - - Notes: - When in daisy chain master mode, the daisy chain and MDIO can both access the SPI. Setting this bit to 1 will disable the daisy chain from accessing the SPI and force it into a reset state. */ - unsigned int nvrDaisyChainDisable : 1; /* 1E.C452.0 R/W Default = 0x0 */ - /* 1 = Disable the Daisy Chain - */ - /*! \brief 1E.C452.1 R/W NVR Daisy Chain Clock Divide Override - AQ_GlobalNvrProvisioning_HHD.u2.bits_2.nvrDaisyChainClockDivideOverride - - Default = 0x0 - - 1 = Override NVR clock divide when in daisy chain master mode - - - Notes: - When in daisy chain master mode, the clock divide configuration is received from the FLASH. This bit will override the clock divide configuration from the FLASH with the See NVR Clock Divide [7:0] . */ - unsigned int nvrDaisyChainClockDivideOverride : 1; /* 1E.C452.1 R/W Default = 0x0 */ - /* 1 = Override NVR clock divide when in daisy chain master mode - */ - unsigned int reserved0 : 14; - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global NVR Provisioning */ - union - { - struct - { - unsigned int reserved1 : 4; - /*! \brief 1E.C453.4 R/W NVR Reset - AQ_GlobalNvrProvisioning_HHD.u3.bits_3.nvrReset - - Default = 0x0 - - 1 = Reset SPI - - */ - unsigned int nvrReset : 1; /* 1E.C453.4 R/W Default = 0x0 */ - /* 1 = Reset SPI - */ - unsigned int reserved0 : 11; - } bits_3; - uint16_t word_3; - } u3; -} AQ_GlobalNvrProvisioning_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Reserved Provisioning: 1E.C470 */ -/* Global Reserved Provisioning: 1E.C470 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Reserved Provisioning */ - union - { - struct - { - unsigned int reserved2 : 4; - /*! \brief 1E.C470.4 R/WSC Initiate Cable Diagnostics - AQ_GlobalReservedProvisioning_HHD.u0.bits_0.initiateCableDiagnostics - - Default = 0x0 - - 1 = Perform cable diagnostics - - - Notes: - Perform cable diagnostics regardless of link state. If link is up, setting this bit will cause the link to drop while diagnostics are performed. This bit is self-clearing upon completion of the cable diagnostics. - - NOTE!! This is a processor intensive operation. Completion of this operation can also be monitored via 1E.C831.F */ - unsigned int initiateCableDiagnostics : 1; /* 1E.C470.4 R/WSC Default = 0x0 */ - /* 1 = Perform cable diagnostics - */ - unsigned int reserved1 : 3; - unsigned int reserved0 : 5; - /*! \brief 1E.C470.E:D R/WPD Extended MDI Diagnostics Select [1:0] - AQ_GlobalReservedProvisioning_HHD.u0.bits_0.extendedMdiDiagnosticsSelect - - Provisionable Default = 0x0 - - 0x0 = TDR Data - 0x1 = RFI Channel PSD - 0x2 = Noise PSD while the local Tx is Off - 0x3 = Noise PSD while the local Tx is On - - - Notes: - These bits select what sort of cable diagnostics to perform. For regular cable diagnostics, Bit F is set to zero, and the diagnostics are triggered by setting Bit 4. For extended diagnostics, Bit F is set to 1, and the desired extended diagnostics are selected by Bits E:D. The routine is then triggered by setting Bit 4. Each of the extended diagnostic routines present data for all for MDI pairs (A, B, C, D) consecutively, and after the data for each channel is gathered Bits F:D are reset. To get the data for the next pair, Bits F:D must be set back to the desired value (which must be the same as the initial channel). This continues until the data for all channels has been gathered. The address in memory where the data is stored is given in 1E.C802 and 1E.C804. - - For the case of PSD, the structure is as follows: - Int32 info - Int16 data[Len] - Info = Len << 16 | TxEnable << 8 | Pair (0 = A, etc.) - - For TDR: - Int32 info - Int16 tdr_A[Len] - Int16 tdr_B[Len] - Int16 tdr_C[Len] - Int16 tdr_D[Len] - - Info = Len << 16 | Channel - - TDR data is from the current pair to all other pairs. - - At the end of retrieving extended MDI diag data, the part will be reset. Conversely the only way to exit this routine once it starts is to issue a PMA reset. */ - unsigned int extendedMdiDiagnosticsSelect : 2; /* 1E.C470.E:D R/WPD Provisionable Default = 0x0 */ - /* 0x0 = TDR Data - 0x1 = RFI Channel PSD - 0x2 = Noise PSD while the local Tx is Off - 0x3 = Noise PSD while the local Tx is On - */ - /*! \brief 1E.C470.F R/WPD Diagnostics Select - AQ_GlobalReservedProvisioning_HHD.u0.bits_0.diagnosticsSelect - - Provisionable Default = 0x0 - - 1 = Provide Extended MDI Diagnostics Information. - 0 = Provide normal cable diagnostics - - - Notes: - These bits select what sort of cable diagnostics to perform. For regular cable diagnostics, Bit F is set to zero, and the diagnostics are triggered by setting Bit 4. For extended diagnostics, Bit F is set to 1, and the desired extended diagnostics are selected by Bits E:D. The routine is then triggered by setting Bit 4. Each of the extended diagnostic routines present data for all for MDI pairs (A, B, C, D) consecutively, and after the data for each channel is gathered Bits F:D are reset. To get the data for the next pair, Bits F:D must be set back to the desired value (which must be the same as the initial channel). This continues until the data for all channels has been gathered. The address in memory where the data is stored is given in 1E.C802 and 1E.C804. - - For the case of PSD, the structure is as follows: - Int32 info - Int16 data[Len] - Info = Len << 16 | TxEnable << 8 | Pair (0 = A, etc.) - - For TDR: - Int32 info - Int16 tdr_A[Len] - Int16 tdr_B[Len] - Int16 tdr_C[Len] - Int16 tdr_D[Len] - - Info = Len << 16 | Channel - - TDR data is from the current pair to all other pairs. - - At the end of retrieving extended MDI diag data, the part will be reset. Conversely the only way to exit this routine once it starts is to issue a PMA reset. */ - unsigned int diagnosticsSelect : 1; /* 1E.C470.F R/WPD Provisionable Default = 0x0 */ - /* 1 = Provide Extended MDI Diagnostics Information. - 0 = Provide normal cable diagnostics - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Reserved Provisioning */ - union - { - struct - { - /*! \brief 1E.C471.5:0 R/WuP Daisy-Chain Hop-Count Override Value [5:0] - AQ_GlobalReservedProvisioning_HHD.u1.bits_1.daisy_chainHop_countOverrideValue - - Default = 0x00 - - The value to use for the PHY's daisy-chain hop-count. Valid values are from 0 -> 47 - - - Notes: - Daisy-Chain Hop-Count Override should be used during MDIO boot-load operation, as the daisy-chain hop-count does not function when the daisy-chain is disabled (1E.C452.0). Setting this bit tells the processor where in the daisy-chain it is, so that the provisioning operation will function correctly. */ - unsigned int daisy_chainHop_countOverrideValue : 6; /* 1E.C471.5:0 R/WuP Default = 0x00 */ - /* The value to use for the PHY's daisy-chain hop-count. Valid values are from 0 -> 47 - */ - /*! \brief 1E.C471.6 R/WuP Enable Daisy-Chain Hop-Count Override - AQ_GlobalReservedProvisioning_HHD.u1.bits_1.enableDaisy_chainHop_countOverride - - Default = 0x0 - - 1 = Hop-count is set by Bits 5:0 - 0 = Hop-count is determined by the daisy-chain - - - Notes: - Daisy-Chain Hop-Count Override should be used during MDIO boot-load operation, as the daisy-chain hop-count does not function when the daisy-chain is disabled (1E.C452.0). Setting this bit tells the processor where in the daisy-chain it is, so that the provisioning operation will function correctly. */ - unsigned int enableDaisy_chainHop_countOverride : 1; /* 1E.C471.6 R/WuP Default = 0x0 */ - /* 1 = Hop-count is set by Bits 5:0 - 0 = Hop-count is determined by the daisy-chain - */ - unsigned int reserved0 : 9; - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global Reserved Provisioning */ - union - { - struct - { - /*! \brief 1E.C472.0 R/WPDuP Enable 5th Channel RFI Cancellation - AQ_GlobalReservedProvisioning_HHD.u2.bits_2.enable_5thChannelRfiCancellation - - Provisionable Default = 0x0 - - 1 = 5th channel and RFI cancellers operation enabled - 0 = 5th channel AFE is powered down, 5th channel digital is clock gated, RFI cancellers are disabled - - - Notes: - Note: The value of this bit at the time of Autonegotiation sets the local PHY behavior until the next time Autonegotiation occurs. */ - unsigned int enable_5thChannelRfiCancellation : 1; /* 1E.C472.0 R/WPDuP Provisionable Default = 0x0 */ - /* 1 = 5th channel and RFI cancellers operation enabled - 0 = 5th channel AFE is powered down, 5th channel digital is clock gated, RFI cancellers are disabled - */ - /*! \brief 1E.C472.1 R/WPDuP Enable XENPAK Register Space - AQ_GlobalReservedProvisioning_HHD.u2.bits_2.enableXenpakRegisterSpace - - Provisionable Default = 0x0 - - 1 = XENPAK register space enabled - 0 = XENPAK register space disabled - - */ - unsigned int enableXenpakRegisterSpace : 1; /* 1E.C472.1 R/WPDuP Provisionable Default = 0x0 */ - /* 1 = XENPAK register space enabled - 0 = XENPAK register space disabled - */ - /*! \brief 1E.C472.5:2 R/WPD External VDD Change Request [3:0] - AQ_GlobalReservedProvisioning_HHD.u2.bits_2.externalVddChangeRequest - - Provisionable Default = 0x0 - - The amount of VDD change requested by firmware, in mV (2's complement value). - - */ - unsigned int externalVddChangeRequest : 4; /* 1E.C472.5:2 R/WPD Provisionable Default = 0x0 */ - /* The amount of VDD change requested by firmware, in mV (2's complement value). - */ - /*! \brief 1E.C472.6 R/WPD Tunable External VDD Power Supply Present - AQ_GlobalReservedProvisioning_HHD.u2.bits_2.tunableExternalVddPowerSupplyPresent - - Provisionable Default = 0x0 - - 1 = Tunable external VDD power supply present - 0 = No tunable external VDD power supply present - - - Notes: - This bit must be set if tuning of external power supply is desired. */ - unsigned int tunableExternalVddPowerSupplyPresent : 1; /* 1E.C472.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = Tunable external VDD power supply present - 0 = No tunable external VDD power supply present - */ - unsigned int reserved1 : 7; - /*! \brief 1E.C472.E R/WPD Enable VDD Power Supply Tuning - AQ_GlobalReservedProvisioning_HHD.u2.bits_2.enableVddPowerSupplyTuning - - Provisionable Default = 0x0 - - 1 = Enable external VDD power supply tuning - 0 = Disable external VDD power supply tuning is disabled - - - Notes: - This bit controls whether the PHY attempts to tune the external VDD power supply via the SMBus. This bit is only operational if the external supply is present. (See 1E.C472.6) */ - unsigned int enableVddPowerSupplyTuning : 1; /* 1E.C472.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable external VDD power supply tuning - 0 = Disable external VDD power supply tuning is disabled - */ - unsigned int reserved0 : 1; - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global Reserved Provisioning */ - union - { - struct - { - /*! \brief 1E.C473.7:0 R/WPD Training SNR [7:0] - AQ_GlobalReservedProvisioning_HHD.u3.bits_3.trainingSNR - - Provisionable Default = 0x00 - - SNR during 10G training on the worst channel. SNR is in steps of 0.1dB - - - Notes: - The SNR margin that is enjoyed by the worst channel, over and above the minimum SNR required to operate at a BER of 10-12. It is reported with 0.1 dB of resolution to an accuracy of 0.5 dB within the range of -12.7 dB to 12.7 dB. The number is in offset binary, with 0.0 dB represented by 0x8000. */ - unsigned int trainingSNR : 8; /* 1E.C473.7:0 R/WPD Provisionable Default = 0x00 */ - /* SNR during 10G training on the worst channel. SNR is in steps of 0.1dB - */ - /*! \brief 1E.C473.A:8 R/WPD Rate Transition Request [2:0] - AQ_GlobalReservedProvisioning_HHD.u3.bits_3.rateTransitionRequest - - Provisionable Default = 0x0 - - 0 = No Transition - 1 = Reserved - 2 = Reserved - 3 = Retrain at 10G - 4 = Retrain at 5G - 5 = Retrain at 2.5G - 6 = Retrain at 1G - 7 = Reserved - - */ - unsigned int rateTransitionRequest : 3; /* 1E.C473.A:8 R/WPD Provisionable Default = 0x0 */ - /* 0 = No Transition - 1 = Reserved - 2 = Reserved - 3 = Retrain at 10G - 4 = Retrain at 5G - 5 = Retrain at 2.5G - 6 = Retrain at 1G - 7 = Reserved - */ - unsigned int reserved0 : 5; - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of Global Reserved Provisioning */ - union - { - struct - { - /*! \brief 1E.C474.0 R/W NVR Daisy Chain Kickstart - AQ_GlobalReservedProvisioning_HHD.u4.bits_4.nvrDaisyChainKickstart - - Default = 0x0 - - 1 = Kickstart the Daisy Chain - - - Notes: - When in daisy chain master mode, the PHY0 can kickstart the daisy chain. The kickstart will not reload the IRAM/DRAM or reset the uP for PHY0. It will just read the FLASH and transfer the FLASH data to the daisy chain. */ - unsigned int nvrDaisyChainKickstart : 1; /* 1E.C474.0 R/W Default = 0x0 */ - /* 1 = Kickstart the Daisy Chain - */ - /*! \brief 1E.C474.F:1 R/WPD Reserved Provisioning 5 [F:1] - AQ_GlobalReservedProvisioning_HHD.u4.bits_4.reservedProvisioning_5 - - Provisionable Default = 0x0000 - - Reserved for future use - - */ - unsigned int reservedProvisioning_5 : 15; /* 1E.C474.F:1 R/WPD Provisionable Default = 0x0000 */ - /* Reserved for future use - */ - } bits_4; - uint16_t word_4; - } u4; - /*! \brief Union for bit and word level access of word 5 of Global Reserved Provisioning */ - union - { - struct - { - unsigned int reserved1 : 2; - /*! \brief 1E.C475.2 R/WPD Smart Power-Down Enable - AQ_GlobalReservedProvisioning_HHD.u5.bits_5.smartPower_downEnable - - Provisionable Default = 0x0 - - 1 = Enable smart power down mode - 0 = Smart power-down mode disabled - - - Notes: - Smart power down (SPD) is the lowest power mode at which PHY is able to autonegotiate. SPD can be enabled with bit 1E.C475.2 */ - unsigned int smartPower_downEnable : 1; /* 1E.C475.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable smart power down mode - 0 = Smart power-down mode disabled - */ - /*! \brief 1E.C475.3 R/WPD Deadlock Avoidance Enable - AQ_GlobalReservedProvisioning_HHD.u5.bits_5.deadlockAvoidanceEnable - - Provisionable Default = 0x0 - - 1 = SPD with deadlock avoidance: PHY transmits autonegotiation pulses (FLPs) at a slower rate (~ 1 FLP/ 100ms) than specified by autonegotiation standard (~1 FLP / 8.25ms). Receiver is active and able to detect the pulses. - 0 = SPD without deadlock avoidance: PHY transmitter is shut down, no autonegotiation pulses are sent on the line but the receiver is active and able to detect the pulses - - */ - unsigned int deadlockAvoidanceEnable : 1; /* 1E.C475.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = SPD with deadlock avoidance: PHY transmits autonegotiation pulses (FLPs) at a slower rate (~ 1 FLP/ 100ms) than specified by autonegotiation standard (~1 FLP / 8.25ms). Receiver is active and able to detect the pulses. - 0 = SPD without deadlock avoidance: PHY transmitter is shut down, no autonegotiation pulses are sent on the line but the receiver is active and able to detect the pulses - */ - /*! \brief 1E.C475.4 R/WPD CFR Support - AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrSupport - - Provisionable Default = 0x0 - - 1 = Local PHY supports Cisco Fast Retrain - 0 = Local PHY does support Cisco Fast Retrain - - */ - unsigned int cfrSupport : 1; /* 1E.C475.4 R/WPD Provisionable Default = 0x0 */ - /* 1 = Local PHY supports Cisco Fast Retrain - 0 = Local PHY does support Cisco Fast Retrain - */ - /*! \brief 1E.C475.5 R/WPD CFR THP - AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrTHP - - Provisionable Default = 0x0 - - 1 = Local PHY requires local PHY to enable THP - 0 = Local PHY does not require local PHY to enable THP - - */ - unsigned int cfrTHP : 1; /* 1E.C475.5 R/WPD Provisionable Default = 0x0 */ - /* 1 = Local PHY requires local PHY to enable THP - 0 = Local PHY does not require local PHY to enable THP - */ - /*! \brief 1E.C475.6 R/WPD CFR Extended Maxwait - AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrExtendedMaxwait - - Provisionable Default = 0x0 - - 1 = Local PHY requires extended maxwait - 0 = Local PHY does not require extended maxwait - - */ - unsigned int cfrExtendedMaxwait : 1; /* 1E.C475.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = Local PHY requires extended maxwait - 0 = Local PHY does not require extended maxwait - */ - /*! \brief 1E.C475.7 R/WPD CFR Disable Timer - AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrDisableTimer - - Provisionable Default = 0x0 - - 1 = Local PHY requires cfr_disable timer - 0 = Local PHY does not require cfr_disable timer - - */ - unsigned int cfrDisableTimer : 1; /* 1E.C475.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = Local PHY requires cfr_disable timer - 0 = Local PHY does not require cfr_disable timer - */ - /*! \brief 1E.C475.8 R/WPD CFR LP Support - AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrLpSupport - - Provisionable Default = 0x0 - - 1 = Link partner supports Cisco Fast Retrain - 0 = Link partner does support Cisco Fast Retrain - - */ - unsigned int cfrLpSupport : 1; /* 1E.C475.8 R/WPD Provisionable Default = 0x0 */ - /* 1 = Link partner supports Cisco Fast Retrain - 0 = Link partner does support Cisco Fast Retrain - */ - /*! \brief 1E.C475.9 R/WPD CFR LP THP - AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrLpTHP - - Provisionable Default = 0x0 - - 1 = Link partner requires local PHY to enable THP - 0 = Link partner does not require local PHY to enable THP - - */ - unsigned int cfrLpTHP : 1; /* 1E.C475.9 R/WPD Provisionable Default = 0x0 */ - /* 1 = Link partner requires local PHY to enable THP - 0 = Link partner does not require local PHY to enable THP - */ - /*! \brief 1E.C475.A R/WPD CFR LP Extended Maxwait - AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrLpExtendedMaxwait - - Provisionable Default = 0x0 - - 1 = Link partner requires extended maxwait - 0 = Link partner does not require extended maxwait - - */ - unsigned int cfrLpExtendedMaxwait : 1; /* 1E.C475.A R/WPD Provisionable Default = 0x0 */ - /* 1 = Link partner requires extended maxwait - 0 = Link partner does not require extended maxwait - */ - /*! \brief 1E.C475.B R/WPD CFR LP Disable Timer - AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrLpDisableTimer - - Provisionable Default = 0x0 - - 1 = Link partner requires cfr_disable timer - 0 = Link partner does not require cfr_disable timer - - */ - unsigned int cfrLpDisableTimer : 1; /* 1E.C475.B R/WPD Provisionable Default = 0x0 */ - /* 1 = Link partner requires cfr_disable timer - 0 = Link partner does not require cfr_disable timer - */ - /*! \brief 1E.C475.C R/WPD Reserved Provisioning 6 - AQ_GlobalReservedProvisioning_HHD.u5.bits_5.reservedProvisioning_6 - - Provisionable Default = 0x0 - - Internal reserved - do not modify - - */ - unsigned int reservedProvisioning_6 : 1; /* 1E.C475.C R/WPD Provisionable Default = 0x0 */ - /* Internal reserved - do not modify - */ - /*! \brief 1E.C475.D R/WPD Smart Power-Down Status - AQ_GlobalReservedProvisioning_HHD.u5.bits_5.smartPower_downStatus - - Provisionable Default = 0x0 - - 1 = Smart Power-Down Active - 0 = Smart Power-Down Inactive - - */ - unsigned int smartPower_downStatus : 1; /* 1E.C475.D R/WPD Provisionable Default = 0x0 */ - /* 1 = Smart Power-Down Active - 0 = Smart Power-Down Inactive - */ - unsigned int reserved0 : 2; - } bits_5; - uint16_t word_5; - } u5; - /*! \brief Dummy union to fill space in the structure Global Reserved Provisioning */ - union - { - struct - { - unsigned int reserved : 16; - } bits_6; - uint16_t word_6; - } u6; - /*! \brief Dummy union to fill space in the structure Global Reserved Provisioning */ - union - { - struct - { - unsigned int reserved : 16; - } bits_7; - uint16_t word_7; - } u7; - /*! \brief Union for bit and word level access of word 8 of Global Reserved Provisioning */ - union - { - struct - { - /*! \brief 1E.C478.A:0 R/WPD Reserved Provisioning 9 [A:0] - AQ_GlobalReservedProvisioning_HHD.u8.bits_8.reservedProvisioning_9 - - Provisionable Default = 0x000 - - Reserved for future use - - */ - unsigned int reservedProvisioning_9 : 11; /* 1E.C478.A:0 R/WPD Provisionable Default = 0x000 */ - /* Reserved for future use - */ - /*! \brief 1E.C478.E:B R/WPD DTE Drop Reporting Timer [3:0] - AQ_GlobalReservedProvisioning_HHD.u8.bits_8.dteDropReportingTimer - - Provisionable Default = 0x0 - - Number of seconds between loss of link partner filter and assertion of no-power-needed state, in 5 second increments (e.g. 0x4 = 20 seconds). - - - Notes: - These bits are used to set how long the PHY waits after it no longer detects the link partner filter before declaring that power is not needed. */ - unsigned int dteDropReportingTimer : 4; /* 1E.C478.E:B R/WPD Provisionable Default = 0x0 */ - /* Number of seconds between loss of link partner filter and assertion of no-power-needed state, in 5 second increments (e.g. 0x4 = 20 seconds). - */ - /*! \brief 1E.C478.F R/WPD DTE Enable - AQ_GlobalReservedProvisioning_HHD.u8.bits_8.dteEnable - - Provisionable Default = 0x0 - - 1 = Enable DTE - 0 = Disable DTE - - */ - unsigned int dteEnable : 1; /* 1E.C478.F R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable DTE - 0 = Disable DTE - */ - } bits_8; - uint16_t word_8; - } u8; - /*! \brief Union for bit and word level access of word 9 of Global Reserved Provisioning */ - union - { - struct - { - /*! \brief 1E.C479.E:0 R/WPD Reserved Provisioning 10 [E:0] - AQ_GlobalReservedProvisioning_HHD.u9.bits_9.reservedProvisioning_10 - - Provisionable Default = 0x0000 - - Reserved for future use - - */ - unsigned int reservedProvisioning_10 : 15; /* 1E.C479.E:0 R/WPD Provisionable Default = 0x0000 */ - /* Reserved for future use - */ - /*! \brief 1E.C479.F R/WPD Power Up Stall - AQ_GlobalReservedProvisioning_HHD.u9.bits_9.powerUpStall - - Provisionable Default = 0x0 - - 1 = Stall FW at Power Up - 0 = Unstall the FW - - - Notes: - This bit needs to be provisioned in Power Up Init for firmware to stall. */ - unsigned int powerUpStall : 1; /* 1E.C479.F R/WPD Provisionable Default = 0x0 */ - /* 1 = Stall FW at Power Up - 0 = Unstall the FW - */ - } bits_9; - uint16_t word_9; - } u9; - /*! \brief Union for bit and word level access of word 10 of Global Reserved Provisioning */ - union - { - struct - { - /*! \brief 1E.C47A.1:0 R/WPD Rate [1:0] - AQ_GlobalReservedProvisioning_HHD.u10.bits_10.rate - - Provisionable Default = 0x0 - - 0x3 = 10G - 0x2 = 1G - 0x1 = 100M - 0x0 = reserved - - - Notes: - These bits select the rate for the loopback and packet generation. SERDES configuration, as well autonegotiation is controlled accordingly when a loopback is selected. For instance, if 100M system loopback on the network interface is selected, SGMII on the system interface is enabled to connect at 100M, and if passthrough is enabled 100BASE-TX will be the only advertised rate and will force a re-autonegotiation if not already connected at 100M. - - NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F - - The controls in this register are identical to, and mirrored with, the controls in 4.C444. */ - unsigned int rate : 2; /* 1E.C47A.1:0 R/WPD Provisionable Default = 0x0 */ - /* 0x3 = 10G - 0x2 = 1G - 0x1 = 100M - 0x0 = reserved - */ - /*! \brief 1E.C47A.2 R/WPD Reserved Provisioning 11a - AQ_GlobalReservedProvisioning_HHD.u10.bits_10.reservedProvisioning_11a - - Provisionable Default = 0x0 - - Reserved for future use - - */ - unsigned int reservedProvisioning_11a : 1; /* 1E.C47A.2 R/WPD Provisionable Default = 0x0 */ - /* Reserved for future use - */ - /*! \brief 1E.C47A.3 R/WPD System I/F Packet Generation - AQ_GlobalReservedProvisioning_HHD.u10.bits_10.systemI_fPacketGeneration - - Provisionable Default = 0x0 - - 1 = CRPAT packet generation out 10G system interface - 0 = No CRPAT packet generation out 10G system interface - - - Notes: - Selecting this mode of operation causes the CRPAT packet generator in the PHY to output CRPAT packets on the selected 10G system interface (4.C441.F:E) - - NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F - - The controls in this register are identical to, and mirrored with, the controls in 4.C444. */ - unsigned int systemI_fPacketGeneration : 1; /* 1E.C47A.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = CRPAT packet generation out 10G system interface - 0 = No CRPAT packet generation out 10G system interface - */ - /*! \brief 1E.C47A.4 R/WPD Look-Aside Port Packet Generation - AQ_GlobalReservedProvisioning_HHD.u10.bits_10.look_asidePortPacketGeneration - - Provisionable Default = 0x0 - - 1 = CRPAT packet generation out 10G look-aside interface (KR0) - 0 = No CRPAT packet generation out 10G look-aside interface (KR0) - - - Notes: - Selecting this mode of operation causes the CRPAT packet generator in the PHY to output on KR0. - - NOTE!! This only functions if KR1 (SERDES2) is selected as the system interface in (4.C441.F:E). - - NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F - - The controls in this register are identical to, and mirrored with, the controls in 4.C444. */ - unsigned int look_asidePortPacketGeneration : 1; /* 1E.C47A.4 R/WPD Provisionable Default = 0x0 */ - /* 1 = CRPAT packet generation out 10G look-aside interface (KR0) - 0 = No CRPAT packet generation out 10G look-aside interface (KR0) - */ - /*! \brief 1E.C47A.5 R/WPD MDI Packet Generation - AQ_GlobalReservedProvisioning_HHD.u10.bits_10.mdiPacketGeneration - - Provisionable Default = 0x0 - - 1 = CRPAT packet generation out MDI interface - 0 = No CRPAT packet generation out MDI interface - - - Notes: - Selecting this mode of operation causes the CRPAT packet generator in the PHY to output on the MDI interface at the selected rate. - - NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F - - The controls in this register are identical to, and mirrored with, the controls in 4.C444. */ - unsigned int mdiPacketGeneration : 1; /* 1E.C47A.5 R/WPD Provisionable Default = 0x0 */ - /* 1 = CRPAT packet generation out MDI interface - 0 = No CRPAT packet generation out MDI interface - */ - /*! \brief 1E.C47A.A:6 R/WPD Reserved Provisioning 11 [4:0] - AQ_GlobalReservedProvisioning_HHD.u10.bits_10.reservedProvisioning_11 - - Provisionable Default = 0x00 - - Reserved for future use - - */ - unsigned int reservedProvisioning_11 : 5; /* 1E.C47A.A:6 R/WPD Provisionable Default = 0x00 */ - /* Reserved for future use - */ - /*! \brief 1E.C47A.F:B R/WPD Loopback Control [4:0] - AQ_GlobalReservedProvisioning_HHD.u10.bits_10.loopbackControl - - Provisionable Default = 0x00 - - 0x00 = No loopback - 0x01 = System Interface - System Loopback - 0x02 = System Interface - System Loopback with Passthrough - 0x03 = System Interface - Network Loopback - 0x04 = System Interface - Network Loopback with Passthrough - 0x05 = System Interface - Network Loopback with Passthrough and Merge - 0x06 = System Interface - Peer-to-peer loopback - 0x07 - 0x08 = Reserved - 0x09 = Network Interface - System Loopback - 0x0A = Network Interface - System Loopback with Passthrough - 0x0B = Network Interface - Network Loopback - 0x0C = Network Interface - Network Loopback with Passthrough - 0x0D = Network Interface - Peer-to-peer loopback - 0x0E - 0x0F = Reserved - 0x10 = Cross-connect System Loopback - 0x11 = Cross-connect Network Loopback - 0x12 - 0x13 = Reserved - 0x14 = Network Interface - System Loopback via Loopback Plug - 0x15 - 0x1F = Reserved - - - Notes: - These bits, in conjunction with the chip configuration and the rate (Bits 1:0), select the loopback to configure for the chip. Setting one of these loopbacks provisions the chip for the specified loopback. Upon clearing the loopback, the chip returns to it's configuration prior to entering loopback (irregardless of whether other loopbacks were selected after the initial loopback). - - NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F. - - The controls in this register are identical to, and mirrored with, the controls in 4.C444. - */ - unsigned int loopbackControl : 5; /* 1E.C47A.F:B R/WPD Provisionable Default = 0x00 */ - /* 0x00 = No loopback - 0x01 = System Interface - System Loopback - 0x02 = System Interface - System Loopback with Passthrough - 0x03 = System Interface - Network Loopback - 0x04 = System Interface - Network Loopback with Passthrough - 0x05 = System Interface - Network Loopback with Passthrough and Merge - 0x06 = System Interface - Peer-to-peer loopback - 0x07 - 0x08 = Reserved - 0x09 = Network Interface - System Loopback - 0x0A = Network Interface - System Loopback with Passthrough - 0x0B = Network Interface - Network Loopback - 0x0C = Network Interface - Network Loopback with Passthrough - 0x0D = Network Interface - Peer-to-peer loopback - 0x0E - 0x0F = Reserved - 0x10 = Cross-connect System Loopback - 0x11 = Cross-connect Network Loopback - 0x12 - 0x13 = Reserved - 0x14 = Network Interface - System Loopback via Loopback Plug - 0x15 - 0x1F = Reserved - */ - } bits_10; - uint16_t word_10; - } u10; - /*! \brief Union for bit and word level access of word 11 of Global Reserved Provisioning */ - union - { - struct - { - /*! \brief 1E.C47B.0 R/WPD Enable PTP - AQ_GlobalReservedProvisioning_HHD.u11.bits_11.enablePtp - - Provisionable Default = 0x0 - - 1 = PTP functionality is enabled - 0 = PTP functionality is disabled - - - Notes: - If this bit is 1, the PTP/SEC block will be included in the data path, regardless of operating mode. */ - unsigned int enablePtp : 1; /* 1E.C47B.0 R/WPD Provisionable Default = 0x0 */ - /* 1 = PTP functionality is enabled - 0 = PTP functionality is disabled - */ - /*! \brief 1E.C47B.1 R/WPD Enable MACSec - AQ_GlobalReservedProvisioning_HHD.u11.bits_11.enableMacsec - - Provisionable Default = 0x0 - - 1 = MACSec functionality is enabled - 0 = MACSec functionality is disabled - - - Notes: - If this bit is 1, the PTP/SEC block will be included in the data path, regardless of operating mode. */ - unsigned int enableMacsec : 1; /* 1E.C47B.1 R/WPD Provisionable Default = 0x0 */ - /* 1 = MACSec functionality is enabled - 0 = MACSec functionality is disabled - */ - /*! \brief 1E.C47B.F:2 R/WPD Reserved Provisioning 12 [D:0] - AQ_GlobalReservedProvisioning_HHD.u11.bits_11.reservedProvisioning_12 - - Provisionable Default = 0x0000 - - Reserved for future use - - */ - unsigned int reservedProvisioning_12 : 14; /* 1E.C47B.F:2 R/WPD Provisionable Default = 0x0000 */ - /* Reserved for future use - */ - } bits_11; - uint16_t word_11; - } u11; -} AQ_GlobalReservedProvisioning_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief PIF Mailbox Control: 1E.C47C */ -/* PIF Mailbox Control: 1E.C47C */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of PIF Mailbox Control */ - union - { - struct - { - /*! \brief 1E.C47C.F:0 R/WPDuP PIF Mailbox Address [F:0] - AQ_PifMailboxControl_HHD.u0.bits_0.pifMailboxAddress - - Provisionable Default = 0x0000 - - The least 16 bits of the PIF address to read or write. - - */ - unsigned int pifMailboxAddress : 16; /* 1E.C47C.F:0 R/WPDuP Provisionable Default = 0x0000 */ - /* The least 16 bits of the PIF address to read or write. - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of PIF Mailbox Control */ - union - { - struct - { - /*! \brief 1E.C47D.F:0 R/WPDuP PIF Mailbox Data [F:0] - AQ_PifMailboxControl_HHD.u1.bits_1.pifMailboxData - - Provisionable Default = 0x0000 - - The data to be written, or that had been read. - - */ - unsigned int pifMailboxData : 16; /* 1E.C47D.F:0 R/WPDuP Provisionable Default = 0x0000 */ - /* The data to be written, or that had been read. - */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of PIF Mailbox Control */ - union - { - struct - { - /*! \brief 1E.C47E.7:0 R/WPDuP PIF Mailbox MMD [7:0] - AQ_PifMailboxControl_HHD.u2.bits_2.pifMailboxMMD - - Provisionable Default = 0x00 - - MMD (upper 8 bits) of the PID address to read or write. - - */ - unsigned int pifMailboxMMD : 8; /* 1E.C47E.7:0 R/WPDuP Provisionable Default = 0x00 */ - /* MMD (upper 8 bits) of the PID address to read or write. - */ - /*! \brief 1E.C47E.B:8 R/WPDuP PIF Mailbox Command Type [3:0] - AQ_PifMailboxControl_HHD.u2.bits_2.pifMailboxCommandType - - Provisionable Default = 0x0 - - 0 = No Action - 1 = Read - 2 = Write - - - Notes: - System SW writes non-zero value to start a PIF command. */ - unsigned int pifMailboxCommandType : 4; /* 1E.C47E.B:8 R/WPDuP Provisionable Default = 0x0 */ - /* 0 = No Action - 1 = Read - 2 = Write - */ - /*! \brief 1E.C47E.F:C R/WPD Reserved PIF Mailbox Control 3 [3:0] - AQ_PifMailboxControl_HHD.u2.bits_2.reservedPifMailboxControl_3 - - Provisionable Default = 0x0 - - Reserved for future use - - */ - unsigned int reservedPifMailboxControl_3 : 4; /* 1E.C47E.F:C R/WPD Provisionable Default = 0x0 */ - /* Reserved for future use - */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of PIF Mailbox Control */ - union - { - struct - { - /*! \brief 1E.C47F.3:0 R/WPDuP PIF Mailbox Command Status [3:0] - AQ_PifMailboxControl_HHD.u3.bits_3.pifMailboxCommandStatus - - Provisionable Default = 0x0 - - 0 = Idle - 1 = Command completed - 2 = Command did not complete - - - Notes: - System SW should write 0 before writing Command Type to clear completion status */ - unsigned int pifMailboxCommandStatus : 4; /* 1E.C47F.3:0 R/WPDuP Provisionable Default = 0x0 */ - /* 0 = Idle - 1 = Command completed - 2 = Command did not complete - */ - /*! \brief 1E.C47F.F:4 R/WPD Reserved PIF Mailbox Control 4 [B:0] - AQ_PifMailboxControl_HHD.u3.bits_3.reservedPifMailboxControl_4 - - Provisionable Default = 0x000 - - Reserved for future use - - */ - unsigned int reservedPifMailboxControl_4 : 12; /* 1E.C47F.F:4 R/WPD Provisionable Default = 0x000 */ - /* Reserved for future use - */ - } bits_3; - uint16_t word_3; - } u3; -} AQ_PifMailboxControl_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global SMBus 0 Provisioning: 1E.C485 */ -/* Global SMBus 0 Provisioning: 1E.C485 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global SMBus 0 Provisioning */ - union - { - struct - { - unsigned int reserved1 : 1; - /*! \brief 1E.C485.7:1 R/W SMB 0 Slave Address [7:1] - AQ_GlobalSmbus_0Provisioning_HHD.u0.bits_0.smb_0SlaveAddress - - Default = 0x00 - - SMB slave address configuration - - */ - unsigned int smb_0SlaveAddress : 7; /* 1E.C485.7:1 R/W Default = 0x00 */ - /* SMB slave address configuration - */ - unsigned int reserved0 : 8; - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalSmbus_0Provisioning_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global SMBus 1 Provisioning: 1E.C495 */ -/* Global SMBus 1 Provisioning: 1E.C495 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global SMBus 1 Provisioning */ - union - { - struct - { - unsigned int reserved1 : 1; - /*! \brief 1E.C495.7:1 R/W SMB 1 Slave Address [7:1] - AQ_GlobalSmbus_1Provisioning_HHD.u0.bits_0.smb_1SlaveAddress - - Default = 0x00 - - SMB slave address configuration - - */ - unsigned int smb_1SlaveAddress : 7; /* 1E.C495.7:1 R/W Default = 0x00 */ - /* SMB slave address configuration - */ - unsigned int reserved0 : 8; - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalSmbus_1Provisioning_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global EEE Provisioning: 1E.C4A0 */ -/* Global EEE Provisioning: 1E.C4A0 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global EEE Provisioning */ - union - { - struct - { - /*! \brief 1E.C4A0.0 R/WPD EEE Mode - AQ_GlobalEeeProvisioning_HHD.u0.bits_0.eeeMode - - Provisionable Default = 0x0 - - 1 = EEE mode of operation - - - Notes: - EEE mode of operation (0=disable, 1=enable, default:0) */ - unsigned int eeeMode : 1; /* 1E.C4A0.0 R/WPD Provisionable Default = 0x0 */ - /* 1 = EEE mode of operation - */ - unsigned int reserved0 : 15; - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalEeeProvisioning_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Cable Diagnostic Status: 1E.C800 */ -/* Global Cable Diagnostic Status: 1E.C800 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C800.2:0 RO Pair D Status [2:0] - AQ_GlobalCableDiagnosticStatus_HHD.u0.bits_0.pairDStatus - - - - [6:4] - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair C - 010= Connected to Pair B - 001= Connected to Pair A - 000= OK - - Notes: - This register summarizes the worst impairment on Pair D. */ - unsigned int pairDStatus : 3; /* 1E.C800.2:0 RO */ - /* [6:4] - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair C - 010= Connected to Pair B - 001= Connected to Pair A - 000= OK */ - unsigned int reserved3 : 1; - /*! \brief 1E.C800.6:4 RO Pair C Status [2:0] - AQ_GlobalCableDiagnosticStatus_HHD.u0.bits_0.pairCStatus - - - - [9:7] - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair B - 010= Connected to Pair A - 001= Connected to Pair D - 000= OK - - Notes: - This register summarizes the worst impairment on Pair C. */ - unsigned int pairCStatus : 3; /* 1E.C800.6:4 RO */ - /* [9:7] - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair B - 010= Connected to Pair A - 001= Connected to Pair D - 000= OK */ - unsigned int reserved2 : 1; - /*! \brief 1E.C800.A:8 RO Pair B Status [2:0] - AQ_GlobalCableDiagnosticStatus_HHD.u0.bits_0.pairBStatus - - - - [C:A] - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair A - 010= Connected to Pair D - 001= Connected to Pair C - 000= OK - - Notes: - This register summarizes the worst impairment on Pair B. */ - unsigned int pairBStatus : 3; /* 1E.C800.A:8 RO */ - /* [C:A] - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair A - 010= Connected to Pair D - 001= Connected to Pair C - 000= OK */ - unsigned int reserved1 : 1; - /*! \brief 1E.C800.E:C RO Pair A Status [2:0] - AQ_GlobalCableDiagnosticStatus_HHD.u0.bits_0.pairAStatus - - - - [F:D] - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair D - 010= Connected to Pair C - 001= Connected to Pair B - 000= OK - - Notes: - This register summarizes the worst impairment on Pair A. */ - unsigned int pairAStatus : 3; /* 1E.C800.E:C RO */ - /* [F:D] - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair D - 010= Connected to Pair C - 001= Connected to Pair B - 000= OK */ - unsigned int reserved0 : 1; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C801.7:0 RO Pair A Reflection #2 [7:0] - AQ_GlobalCableDiagnosticStatus_HHD.u1.bits_1.pairAReflection_2 - - - - The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair A - - Notes: - The distance to this reflection is given in See Global Reserved Status 1: Address 1E.C870 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairAReflection_2 : 8; /* 1E.C801.7:0 RO */ - /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair A */ - /*! \brief 1E.C801.F:8 RO Pair A Reflection #1 [7:0] - AQ_GlobalCableDiagnosticStatus_HHD.u1.bits_1.pairAReflection_1 - - - - The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair A - - Notes: - The distance to this reflection is given in See Global Reserved Status 1: Address 1E.C870 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairAReflection_1 : 8; /* 1E.C801.F:8 RO */ - /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair A */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C802.F:0 RO Impulse Response MSW [F:0] - AQ_GlobalCableDiagnosticStatus_HHD.u2.bits_2.impulseResponseMSW - - - - The MSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type in 1E.C470.E:D - - Notes: - See 1E.C470 for more information */ - unsigned int impulseResponseMSW : 16; /* 1E.C802.F:0 RO */ - /* The MSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type in 1E.C470.E:D */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C803.7:0 RO Pair B Reflection #2 [7:0] - AQ_GlobalCableDiagnosticStatus_HHD.u3.bits_3.pairBReflection_2 - - - - The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair B - - Notes: - The distance to this reflection is given in See Global Reserved Status 2: Address 1E.C871 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairBReflection_2 : 8; /* 1E.C803.7:0 RO */ - /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair B */ - /*! \brief 1E.C803.F:8 RO Pair B Reflection #1 [7:0] - AQ_GlobalCableDiagnosticStatus_HHD.u3.bits_3.pairBReflection_1 - - - - The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair B - - Notes: - The distance to this reflection is given in See Global Reserved Status 2: Address 1E.C871 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairBReflection_1 : 8; /* 1E.C803.F:8 RO */ - /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair B */ - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C804.F:0 RO Impulse Response LSW [F:0] - AQ_GlobalCableDiagnosticStatus_HHD.u4.bits_4.impulseResponseLSW - - - - The LSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type specified in 1E.C470.E:D - - Notes: - See 1E.C470 for more information */ - unsigned int impulseResponseLSW : 16; /* 1E.C804.F:0 RO */ - /* The LSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type specified in 1E.C470.E:D */ - } bits_4; - uint16_t word_4; - } u4; - /*! \brief Union for bit and word level access of word 5 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C805.7:0 RO Pair C Reflection #2 [7:0] - AQ_GlobalCableDiagnosticStatus_HHD.u5.bits_5.pairCReflection_2 - - - - The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair C - - Notes: - The distance to this reflection is given in See Global Reserved Status 3: Address 1E.C872 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairCReflection_2 : 8; /* 1E.C805.7:0 RO */ - /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair C */ - /*! \brief 1E.C805.F:8 RO Pair C Reflection #1 [7:0] - AQ_GlobalCableDiagnosticStatus_HHD.u5.bits_5.pairCReflection_1 - - - - The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair C - - Notes: - The distance to this reflection is given in See Global Reserved Status 3: Address 1E.C872 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairCReflection_1 : 8; /* 1E.C805.F:8 RO */ - /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair C */ - } bits_5; - uint16_t word_5; - } u5; - /*! \brief Union for bit and word level access of word 6 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C806.F:0 RO Reserved 1 [F:0] - AQ_GlobalCableDiagnosticStatus_HHD.u6.bits_6.reserved_1 - - - - Reserved for future use - */ - unsigned int reserved_1 : 16; /* 1E.C806.F:0 RO */ - /* Reserved for future use */ - } bits_6; - uint16_t word_6; - } u6; - /*! \brief Union for bit and word level access of word 7 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C807.7:0 RO Pair D Reflection #2 [7:0] - AQ_GlobalCableDiagnosticStatus_HHD.u7.bits_7.pairDReflection_2 - - - - The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair D - - Notes: - The distance to this reflection is given in See Global Reserved Status 4: Address 1E.C873 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairDReflection_2 : 8; /* 1E.C807.7:0 RO */ - /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair D */ - /*! \brief 1E.C807.F:8 RO Pair D Reflection #1 [7:0] - AQ_GlobalCableDiagnosticStatus_HHD.u7.bits_7.pairDReflection_1 - - - - The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair D - - Notes: - The distance to this reflection is given in See Global Reserved Status 4: Address 1E.C873 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairDReflection_1 : 8; /* 1E.C807.F:8 RO */ - /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair D */ - } bits_7; - uint16_t word_7; - } u7; -} AQ_GlobalCableDiagnosticStatus_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Thermal Status: 1E.C820 */ -/* Global Thermal Status: 1E.C820 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Thermal Status */ - union - { - struct - { - /*! \brief 1E.C820.F:0 RO Temperature [F:0] - AQ_GlobalThermalStatus_HHD.u0.bits_0.temperature - - - - [F:0] of temperature - - - Notes: - 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 70 degreesC. This is a mirror of the XENPAK register 1.A060 - 1.A061. The mirror is performed in H/W. */ - unsigned int temperature : 16; /* 1E.C820.F:0 RO */ - /* [F:0] of temperature - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Thermal Status */ - union - { - struct - { - /*! \brief 1E.C821.0 RO Temperature Ready - AQ_GlobalThermalStatus_HHD.u1.bits_1.temperatureReady - - - - 1 = Temperature measurement is valid - - - Notes: - This is a mirror of the XENPAK register 1.A06E. */ - unsigned int temperatureReady : 1; /* 1E.C821.0 RO */ - /* 1 = Temperature measurement is valid - */ - unsigned int reserved0 : 15; - } bits_1; - uint16_t word_1; - } u1; -} AQ_GlobalThermalStatus_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global General Status: 1E.C830 */ -/* Global General Status: 1E.C830 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global General Status */ - union - { - struct - { - unsigned int reserved1 : 11; - /*! \brief 1E.C830.B RO Low Temperature Warning State - AQ_GlobalGeneralStatus_HHD.u0.bits_0.lowTemperatureWarningState - - - - 1 = Low temperature warning threshold has been exceeded - - Notes: - In XENPAK mode, F/W will copy this register to the 1.A074.6 register. - - */ - unsigned int lowTemperatureWarningState : 1; /* 1E.C830.B RO */ - /* 1 = Low temperature warning threshold has been exceeded */ - /*! \brief 1E.C830.C RO High Temperature Warning State - AQ_GlobalGeneralStatus_HHD.u0.bits_0.highTemperatureWarningState - - - - 1 = High temperature warning threshold has been exceeded - - Notes: - In XENPAK mode, F/W will copy this register to the 1.A074.7 register. - - */ - unsigned int highTemperatureWarningState : 1; /* 1E.C830.C RO */ - /* 1 = High temperature warning threshold has been exceeded */ - /*! \brief 1E.C830.D RO Low Temperature Failure State - AQ_GlobalGeneralStatus_HHD.u0.bits_0.lowTemperatureFailureState - - - - 1 = Low temperature failure threshold has been exceeded - - Notes: - In XENPAK mode, F/W will copy this register to the 1.A070.6 register. - - */ - unsigned int lowTemperatureFailureState : 1; /* 1E.C830.D RO */ - /* 1 = Low temperature failure threshold has been exceeded */ - /*! \brief 1E.C830.E RO High Temperature Failure State - AQ_GlobalGeneralStatus_HHD.u0.bits_0.highTemperatureFailureState - - - - 1 = High temperature failure threshold has been exceeded - - Notes: - In XENPAK mode, F/W will copy this register to the 1.A070.7 register. - - */ - unsigned int highTemperatureFailureState : 1; /* 1E.C830.E RO */ - /* 1 = High temperature failure threshold has been exceeded */ - unsigned int reserved0 : 1; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global General Status */ - union - { - struct - { - unsigned int reserved0 : 15; - /*! \brief 1E.C831.F RO Processor Intensive MDIO Operation In- Progress - AQ_GlobalGeneralStatus_HHD.u1.bits_1.processorIntensiveMdioOperationIn_Progress - - - - 1 = PHY microprocessor is busy with a processor-intensive MDIO operation - 0 = Processor-intensive MDIO operation completed - - - Notes: - This bit should may be used with certain processor-intensive MDIO commands (such as Loopbacks, Test Modes, Low power modes, Tx-Disable, Restart autonegotiation, Cable Diagnostics, etc.) that take longer than an MDIO cycle to complete. Upon receiving an MDIO command that involves the PHY's microprocessor, this bit is set, and when the command is completed, this bit is cleared. - - NOTE!!! This bit should be checked only after 1 ms of issuing a processor-intensive MDIO operation. - - The list of operations that set this bit are as follows: - - 1.0.0, PMA Loopback - 1.0.B, Low power mode - 1.9.4:0, Tx Disable - 1.84, 10G Test modes - 1.8000.5, XENPAK Control - 1.9000, XENPAK Rx Fault Enable - 1.9002, XENPAK Alarm Enable - 1.E400.F, External loopback - 3.0.B, Low power mode - 3.0.E, System PCS loopback - 3.C471.5, PRBS Test - 3.C471.6, PRBS Test - 3.E471.5, PRBS Test - 3.E471.6, PRBS Test - 4.0.B, Low power mode - 4.0.E, PHY-XS network loopback - 4.C440, Output clock control, Load SERDES parameters - 4.F802.E, System loopback - 4.C444.F:B, Loopback Control - 4.C444.4:2, Packet generation - 4.C445.C, SERDES calibration - 7.0.9, Restart autonegotiation - 1D.C280, 1G/100M Network loopback - 1D.C500, 1G System loopback - 1D.C501, 1G / 100M Test modes - 1E.C470.4, Cable diagnostics - 1E.C47A.F:B, Loopback Control - 1E.C47A.4:2, Packet generation */ - unsigned int processorIntensiveMdioOperationIn_Progress : 1; /* 1E.C831.F RO */ - /* 1 = PHY microprocessor is busy with a processor-intensive MDIO operation - 0 = Processor-intensive MDIO operation completed - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_GlobalGeneralStatus_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Pin Status: 1E.C840 */ -/* Global Pin Status: 1E.C840 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Pin Status */ - union - { - struct - { - /*! \brief 1E.C840.5:0 RO LED Pullup State [5:0] - AQ_GlobalPinStatus_HHD.u0.bits_0.ledPullupState - - - - 1 = LED output pin is pulled high - 0 = LED output pin is pulled low - - */ - unsigned int ledPullupState : 6; /* 1E.C840.5:0 RO */ - /* 1 = LED output pin is pulled high - 0 = LED output pin is pulled low - */ - unsigned int reserved4 : 1; - /*! \brief 1E.C840.7 RO Tx Enable - AQ_GlobalPinStatus_HHD.u0.bits_0.txEnable - - - - Current Value of Tx Enable pin - - - Notes: - 0 = Disable Transmitter */ - unsigned int txEnable : 1; /* 1E.C840.7 RO */ - /* Current Value of Tx Enable pin - */ - unsigned int reserved3 : 1; - /*! \brief 1E.C840.9 RO Package Connectivity - AQ_GlobalPinStatus_HHD.u0.bits_0.packageConnectivity - - - - Value of the package connection pin - - */ - unsigned int packageConnectivity : 1; /* 1E.C840.9 RO */ - /* Value of the package connection pin - */ - unsigned int reserved2 : 3; - /*! \brief 1E.C840.D RO DC_MASTER_N - AQ_GlobalPinStatus_HHD.u0.bits_0.dcMasterN - - - - Value of DC_MASTER_N pin: - - 0x1 = PHY Slave Daisy Chain Boot - 0x0 = PHY Master Daisy Chain Boot from FLASH - */ - unsigned int dcMasterN : 1; /* 1E.C840.D RO */ - /* Value of DC_MASTER_N pin: - - 0x1 = PHY Slave Daisy Chain Boot - 0x0 = PHY Master Daisy Chain Boot from FLASH */ - unsigned int reserved1 : 1; - unsigned int reserved0 : 1; - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalPinStatus_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Daisy Chain Status: 1E.C842 */ -/* Global Daisy Chain Status: 1E.C842 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Daisy Chain Status */ - union - { - struct - { - /*! \brief 1E.C842.F:0 RO Rx Daisy Chain Calculated CRC [F:0] - AQ_GlobalDaisyChainStatus_HHD.u0.bits_0.rxDaisyChainCalculatedCrc - - - - Rx Daisy Chain Calculated CRC - - - Notes: - This is the calculated daisy chain CRC. */ - unsigned int rxDaisyChainCalculatedCrc : 16; /* 1E.C842.F:0 RO */ - /* Rx Daisy Chain Calculated CRC - */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalDaisyChainStatus_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Fault Message: 1E.C850 */ -/* Global Fault Message: 1E.C850 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Fault Message */ - union - { - struct - { - /*! \brief 1E.C850.F:0 RO Message [F:0] - AQ_GlobalFaultMessage_HHD.u0.bits_0.message - - - - Error code describing fault - - Notes: - Code 0x8001: Firmware not compatible with chip architecture. This fault occurs when firmware compiled for a different microprocessor core is loaded. - Code 0x8002: VCO calibration failed. This occurs when the main PLLs on chip fail to lock: this is not possible to trigger. - Code 0x8003: XAUI calibration failed. This occurs when the XAUI PLLs fail to lock: this is not possible to trigger. - Code 0x8005: Unexpected device ID. This occurs if the device ID programmed into the internal E-Fuse registers in not valid: this is not possible to trigger. - Code 0x8006: Computed checksum does not match expected checksum. This occurs when the FLASH checksum check performed at boot time fails. This only occurs when the system boots from FLASH. - Code 0x8007: Detected a bit error in static memory. To trigger, corrupt one of the static regions. - Code 0xC001: Illegal Instruction exception. This occurs when the processor attempts to execute an illegal instruction. To trigger this, write an illegal instruction to program memory. It's possible that the bit error check will trigger before the illegal instruction is executed. - Code 0xC002 Instruction Fetch Error. Internal physical address or a data error during instruction fetch: this is not possible to trigger. - Code 0xC003 Load Store Error. Internal physical address or data error during load store operation: this is not possible to trigger.. - Code 0xC004 Privileged Instruction. Attempt to execute a privileged operation without sufficient privilege: this is not possible to trigger. - Code 0xC005 Unaligned Load or Store. Attempt to load or store data at an address which cannot be handled due to alignment: this is not possible to trigger. - Code 0xC006 Instruction fetch from prohibited space: this is not possible to trigger. - Code 0xC007 Data load from prohibited space: this is not possible to trigger. - Code 0xC008 Data store into prohibited space: this is not possible to trigger. */ - unsigned int message : 16; /* 1E.C850.F:0 RO */ - /* Error code describing fault */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalFaultMessage_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Cable Diagnostic Impedance: 1E.C880 */ -/* Global Cable Diagnostic Impedance: 1E.C880 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Cable Diagnostic Impedance */ - union - { - struct - { - /*! \brief 1E.C880.2:0 RO Pair A Reflection #4 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.pairAReflection_4 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the fourth worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ - unsigned int pairAReflection_4 : 3; /* 1E.C880.2:0 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C880.3 RO Reserved 4 - AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.reserved_4 - - - - Reserved - - */ - unsigned int reserved_4 : 1; /* 1E.C880.3 RO */ - /* Reserved - */ - /*! \brief 1E.C880.6:4 RO Pair A Reflection #3 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.pairAReflection_3 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the third worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ - unsigned int pairAReflection_3 : 3; /* 1E.C880.6:4 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C880.7 RO Reserved 3 - AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.reserved_3 - - - - Reserved - - */ - unsigned int reserved_3 : 1; /* 1E.C880.7 RO */ - /* Reserved - */ - /*! \brief 1E.C880.A:8 RO Pair A Reflection #2 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.pairAReflection_2 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the second worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ - unsigned int pairAReflection_2 : 3; /* 1E.C880.A:8 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C880.B RO Reserved 2 - AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.reserved_2 - - - - Reserved - - */ - unsigned int reserved_2 : 1; /* 1E.C880.B RO */ - /* Reserved - */ - /*! \brief 1E.C880.E:C RO Pair A Reflection #1 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.pairAReflection_1 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the first worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ - unsigned int pairAReflection_1 : 3; /* 1E.C880.E:C RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C880.F RO Reserved 1 - AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.reserved_1 - - - - Reserved - - */ - unsigned int reserved_1 : 1; /* 1E.C880.F RO */ - /* Reserved - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Cable Diagnostic Impedance */ - union - { - struct - { - /*! \brief 1E.C881.2:0 RO Pair B Reflection #4 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.pairBReflection_4 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the fourth worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ - unsigned int pairBReflection_4 : 3; /* 1E.C881.2:0 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C881.3 RO Reserved 8 - AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.reserved_8 - - - - Reserved - - */ - unsigned int reserved_8 : 1; /* 1E.C881.3 RO */ - /* Reserved - */ - /*! \brief 1E.C881.6:4 RO Pair B Reflection #3 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.pairBReflection_3 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the third worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ - unsigned int pairBReflection_3 : 3; /* 1E.C881.6:4 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C881.7 RO Reserved 7 - AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.reserved_7 - - - - Reserved - - */ - unsigned int reserved_7 : 1; /* 1E.C881.7 RO */ - /* Reserved - */ - /*! \brief 1E.C881.A:8 RO Pair B Reflection #2 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.pairBReflection_2 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the second worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ - unsigned int pairBReflection_2 : 3; /* 1E.C881.A:8 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C881.B RO Reserved 6 - AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.reserved_6 - - - - Reserved - - */ - unsigned int reserved_6 : 1; /* 1E.C881.B RO */ - /* Reserved - */ - /*! \brief 1E.C881.E:C RO Pair B Reflection #1 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.pairBReflection_1 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the first worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ - unsigned int pairBReflection_1 : 3; /* 1E.C881.E:C RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C881.F RO Reserved 5 - AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.reserved_5 - - - - Reserved - - */ - unsigned int reserved_5 : 1; /* 1E.C881.F RO */ - /* Reserved - */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global Cable Diagnostic Impedance */ - union - { - struct - { - /*! \brief 1E.C882.2:0 RO Pair C Reflection #4 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.pairCReflection_4 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the fourth worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ - unsigned int pairCReflection_4 : 3; /* 1E.C882.2:0 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C882.3 RO Reserved 12 - AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.reserved_12 - - - - Reserved - - */ - unsigned int reserved_12 : 1; /* 1E.C882.3 RO */ - /* Reserved - */ - /*! \brief 1E.C882.6:4 RO Pair C Reflection #3 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.pairCReflection_3 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the third worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ - unsigned int pairCReflection_3 : 3; /* 1E.C882.6:4 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C882.7 RO Reserved 11 - AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.reserved_11 - - - - Reserved - - */ - unsigned int reserved_11 : 1; /* 1E.C882.7 RO */ - /* Reserved - */ - /*! \brief 1E.C882.A:8 RO Pair C Reflection #2 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.pairCReflection_2 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the second worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ - unsigned int pairCReflection_2 : 3; /* 1E.C882.A:8 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C882.B RO Reserved 10 - AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.reserved_10 - - - - Reserved - - */ - unsigned int reserved_10 : 1; /* 1E.C882.B RO */ - /* Reserved - */ - /*! \brief 1E.C882.E:C RO Pair C Reflection #1 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.pairCReflection_1 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the first worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ - unsigned int pairCReflection_1 : 3; /* 1E.C882.E:C RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C882.F RO Reserved 9 - AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.reserved_9 - - - - Reserved - - */ - unsigned int reserved_9 : 1; /* 1E.C882.F RO */ - /* Reserved - */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global Cable Diagnostic Impedance */ - union - { - struct - { - /*! \brief 1E.C883.2:0 RO Pair D Reflection #4 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.pairDReflection_4 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the fourth worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ - unsigned int pairDReflection_4 : 3; /* 1E.C883.2:0 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C883.3 RO Reserved 16 - AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.reserved_16 - - - - Reserved - - */ - unsigned int reserved_16 : 1; /* 1E.C883.3 RO */ - /* Reserved - */ - /*! \brief 1E.C883.6:4 RO Pair D Reflection #3 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.pairDReflection_3 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the third worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ - unsigned int pairDReflection_3 : 3; /* 1E.C883.6:4 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C883.7 RO Reserved 15 - AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.reserved_15 - - - - Reserved - - */ - unsigned int reserved_15 : 1; /* 1E.C883.7 RO */ - /* Reserved - */ - /*! \brief 1E.C883.A:8 RO Pair D Reflection #2 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.pairDReflection_2 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the second worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ - unsigned int pairDReflection_2 : 3; /* 1E.C883.A:8 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C883.B RO Reserved 14 - AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.reserved_14 - - - - Reserved - - */ - unsigned int reserved_14 : 1; /* 1E.C883.B RO */ - /* Reserved - */ - /*! \brief 1E.C883.E:C RO Pair D Reflection #1 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.pairDReflection_1 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the first worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ - unsigned int pairDReflection_1 : 3; /* 1E.C883.E:C RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C883.F RO Reserved 13 - AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.reserved_13 - - - - Reserved - - */ - unsigned int reserved_13 : 1; /* 1E.C883.F RO */ - /* Reserved - */ - } bits_3; - uint16_t word_3; - } u3; -} AQ_GlobalCableDiagnosticImpedance_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Status: 1E.C884 */ -/* Global Status: 1E.C884 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Status */ - union - { - struct - { - /*! \brief 1E.C884.7:0 RO Cable Length [7:0] - AQ_GlobalStatus_HHD.u0.bits_0.cableLength - - - - The estimated length of the cable in meters - - - Notes: - The length of the cable shown here is estimated from the cable diagnostic engine and should be accurate to +/-1m. */ - unsigned int cableLength : 8; /* 1E.C884.7:0 RO */ - /* The estimated length of the cable in meters - */ - /*! \brief 1E.C884.F:8 RO Reserved Status 0 [7:0] - AQ_GlobalStatus_HHD.u0.bits_0.reservedStatus_0 - - - - Reserved - - */ - unsigned int reservedStatus_0 : 8; /* 1E.C884.F:8 RO */ - /* Reserved - */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalStatus_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Reserved Status: 1E.C885 */ -/* Global Reserved Status: 1E.C885 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Reserved Status */ - union - { - struct - { - /*! \brief 1E.C885.3:0 ROSPD Provisioning ID [3:0] - AQ_GlobalReservedStatus_HHD.u0.bits_0.provisioningID - - Provisionable Default = 0x0 - - Provisioning ID - - - Notes: - Customers may receive multiple ROM images that differ only in their provisioning. This field is used to differentiate those images. This field is used in conjunction with the firmware major and minor revision numbers to uniquely identify ROM images. */ - unsigned int provisioningID : 4; /* 1E.C885.3:0 ROSPD Provisionable Default = 0x0 */ - /* Provisioning ID - */ - /*! \brief 1E.C885.7:4 ROSPD Firmware Build ID [3:0] - AQ_GlobalReservedStatus_HHD.u0.bits_0.firmwareBuildID - - Provisionable Default = 0x0 - - Firmware Build ID - - - Notes: - Customers may receive multiple ROM images that differ only in their provisioning. This field is used to differentiate those images. This field is used in conjunction with the firmware major and minor revision numbers to uniquely identify ROM images. */ - unsigned int firmwareBuildID : 4; /* 1E.C885.7:4 ROSPD Provisionable Default = 0x0 */ - /* Firmware Build ID - */ - /*! \brief 1E.C885.9:8 ROSPD XENPAK NVR Status [1:0] - AQ_GlobalReservedStatus_HHD.u0.bits_0.xenpakNvrStatus - - Provisionable Default = 0x0 - - Status of XENPAK NVR: - 0: NVR not enabled - 1: Last NVR operation succeeded - 2: Last NVR operation failed - 3: Reserved - - - Notes: - XENPAK register space is mirrored in NVR (SPI ROM). This register indicates the status of the last NVR operation. */ - unsigned int xenpakNvrStatus : 2; /* 1E.C885.9:8 ROSPD Provisionable Default = 0x0 */ - /* Status of XENPAK NVR: - 0: NVR not enabled - 1: Last NVR operation succeeded - 2: Last NVR operation failed - 3: Reserved - */ - /*! \brief 1E.C885.F:A RO Nearly Seconds MSW[5:0] - AQ_GlobalReservedStatus_HHD.u0.bits_0.nearlySecondsMSW - - - - Bits 16 to 21 of the 22 bit "Nearly Seconds" uptime counter. - - - Notes: - The "Nearly Seconds" counter is incremented every 1024 milliseconds. */ - unsigned int nearlySecondsMSW : 6; /* 1E.C885.F:A RO */ - /* Bits 16 to 21 of the 22 bit "Nearly Seconds" uptime counter. - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Reserved Status */ - union - { - struct - { - /*! \brief 1E.C886.F:0 RO Nearly Seconds LSW [F:0] - AQ_GlobalReservedStatus_HHD.u1.bits_1.nearlySecondsLSW - - - - Bits 0 to 15 of the 22 bit "Nearly Seconds" uptime counter - - - Notes: - The "Nearly Seconds" counter is incremented every 1024 milliseconds. */ - unsigned int nearlySecondsLSW : 16; /* 1E.C886.F:0 RO */ - /* Bits 0 to 15 of the 22 bit "Nearly Seconds" uptime counter - */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global Reserved Status */ - union - { - struct - { - /*! \brief 1E.C887.D:0 RO Reserved Status 3 [D:0] - AQ_GlobalReservedStatus_HHD.u2.bits_2.reservedStatus_3 - - - - Reserved for future use - - */ - unsigned int reservedStatus_3 : 14; /* 1E.C887.D:0 RO */ - /* Reserved for future use - */ - /*! \brief 1E.C887.E ROS Power Up Stall Status - AQ_GlobalReservedStatus_HHD.u2.bits_2.powerUpStallStatus - - Default = 0x0 - - 1 = FW is stalled at power up - 0 = Firmware is unstalled - - */ - unsigned int powerUpStallStatus : 1; /* 1E.C887.E ROS Default = 0x0 */ - /* 1 = FW is stalled at power up - 0 = Firmware is unstalled - */ - /*! \brief 1E.C887.F ROS DTE Status - AQ_GlobalReservedStatus_HHD.u2.bits_2.dteStatus - - Default = 0x0 - - 1 = Need power - 0 = Don't need power - - */ - unsigned int dteStatus : 1; /* 1E.C887.F ROS Default = 0x0 */ - /* 1 = Need power - 0 = Don't need power - */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global Reserved Status */ - union - { - struct - { - /*! \brief 1E.C888.1:0 RO Rate [1:0] - AQ_GlobalReservedStatus_HHD.u3.bits_3.rate - - Default = 0x0 - - 0x3 = 10G - 0x2 = 1G - 0x1 = 100M - 0x0 = invalid - - - Notes: - These bits report the selected rate for the loopback and packet generation. */ - unsigned int rate : 2; /* 1E.C888.1:0 RO Default = 0x0 */ - /* 0x3 = 10G - 0x2 = 1G - 0x1 = 100M - 0x0 = invalid - */ - /*! \brief 1E.C888.2 RO Reserved Status 4a - AQ_GlobalReservedStatus_HHD.u3.bits_3.reservedStatus_4a - - Default = 0x0 - - Reserved for future use - - */ - unsigned int reservedStatus_4a : 1; /* 1E.C888.2 RO Default = 0x0 */ - /* Reserved for future use - */ - /*! \brief 1E.C888.3 RO System I/F Packet Generation Status - AQ_GlobalReservedStatus_HHD.u3.bits_3.systemI_fPacketGenerationStatus - - Default = 0x0 - - 1 = CRPAT packet generation out 10G system interface - 0 = No CRPAT packet generation out 10G system interface - - - Notes: - Reports whether the CRPAT packet generator in the PHY outputs on the selected system interface at the selected rate. */ - unsigned int systemI_fPacketGenerationStatus : 1; /* 1E.C888.3 RO Default = 0x0 */ - /* 1 = CRPAT packet generation out 10G system interface - 0 = No CRPAT packet generation out 10G system interface - */ - /*! \brief 1E.C888.4 RO Look-Aside Port Packet Generation Status - AQ_GlobalReservedStatus_HHD.u3.bits_3.look_asidePortPacketGenerationStatus - - Default = 0x0 - - 1 = CRPAT packet generation out 10G look-aside interface (KR0) - 0 = No CRPAT packet generation out 10G look-aside interface (KR0) - - - Notes: - Reports whether the CRPAT packet generator in the PHY outputs on the KR0 interface at the selected rate. */ - unsigned int look_asidePortPacketGenerationStatus : 1; /* 1E.C888.4 RO Default = 0x0 */ - /* 1 = CRPAT packet generation out 10G look-aside interface (KR0) - 0 = No CRPAT packet generation out 10G look-aside interface (KR0) - */ - /*! \brief 1E.C888.5 RO MDI Packet Generation Status - AQ_GlobalReservedStatus_HHD.u3.bits_3.mdiPacketGenerationStatus - - Default = 0x0 - - 1 = CRPAT packet generation out MDI interface - 0 = No CRPAT packet generation out MDI interface - - - Notes: - Reports whether the CRPAT packet generator in the PHY outputs on the MDI interface at the selected rate. */ - unsigned int mdiPacketGenerationStatus : 1; /* 1E.C888.5 RO Default = 0x0 */ - /* 1 = CRPAT packet generation out MDI interface - 0 = No CRPAT packet generation out MDI interface - */ - /*! \brief 1E.C888.A:6 RO Reserved Status 4 [4:0] - AQ_GlobalReservedStatus_HHD.u3.bits_3.reservedStatus_4 - - Default = 0x00 - - Reserved for future use - - */ - unsigned int reservedStatus_4 : 5; /* 1E.C888.A:6 RO Default = 0x00 */ - /* Reserved for future use - */ - /*! \brief 1E.C888.F:B RO Loopback Status [4:0] - AQ_GlobalReservedStatus_HHD.u3.bits_3.loopbackStatus - - Default = 0x00 - - 0x00 = No loopback - 0x01 = System Interface - System Loopback - 0x02 = System Interface - System Loopback with Passthrough - 0x03 = System Interface - Network Loopback - 0x04 = System Interface - Network Loopback with Passthrough - 0x05 = System Interface - Network Loopback with Passthrough and Merge - 0x06 = System Interface - Peer-to-peer loopback - 0x07 - 0x08 = Reserved - 0x09 = Network Interface - System Loopback - 0x0A = Network Interface - System Loopback with Passthrough - 0x0B = Network Interface - Network Loopback - 0x0C = Network Interface - Network Loopback with Passthrough - 0x0D = Network Interface - Peer-to-peer loopback - 0x0E - 0x0F = Reserved - 0x10 = Cross-connect System Loopback - 0x11 = Cross-connect Network Loopback - 0x12 - 0x13 = Reserved - 0x14 = Network Interface - System Loopback via Loopback Plug - 0x15 - 0x1F = Reserved - - - Notes: - These bits, in conjunction with the chip configuration and the rate (Bits 1:0), report the selected loopback. - - */ - unsigned int loopbackStatus : 5; /* 1E.C888.F:B RO Default = 0x00 */ - /* 0x00 = No loopback - 0x01 = System Interface - System Loopback - 0x02 = System Interface - System Loopback with Passthrough - 0x03 = System Interface - Network Loopback - 0x04 = System Interface - Network Loopback with Passthrough - 0x05 = System Interface - Network Loopback with Passthrough and Merge - 0x06 = System Interface - Peer-to-peer loopback - 0x07 - 0x08 = Reserved - 0x09 = Network Interface - System Loopback - 0x0A = Network Interface - System Loopback with Passthrough - 0x0B = Network Interface - Network Loopback - 0x0C = Network Interface - Network Loopback with Passthrough - 0x0D = Network Interface - Peer-to-peer loopback - 0x0E - 0x0F = Reserved - 0x10 = Cross-connect System Loopback - 0x11 = Cross-connect Network Loopback - 0x12 - 0x13 = Reserved - 0x14 = Network Interface - System Loopback via Loopback Plug - 0x15 - 0x1F = Reserved - */ - } bits_3; - uint16_t word_3; - } u3; -} AQ_GlobalReservedStatus_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Alarms: 1E.CC00 */ -/* Global Alarms: 1E.CC00 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Alarms */ - union - { - struct - { - /*! \brief 1E.CC00.0 LH Reserved Alarm D - AQ_GlobalAlarms_HHD.u0.bits_0.reservedAlarmD - - - - Reserved for future use - - */ - unsigned int reservedAlarmD : 1; /* 1E.CC00.0 LH */ - /* Reserved for future use - */ - /*! \brief 1E.CC00.1 LH Reserved Alarm C - AQ_GlobalAlarms_HHD.u0.bits_0.reservedAlarmC - - - - Reserved for future use - - */ - unsigned int reservedAlarmC : 1; /* 1E.CC00.1 LH */ - /* Reserved for future use - */ - /*! \brief 1E.CC00.2 LH Reserved Alarm B - AQ_GlobalAlarms_HHD.u0.bits_0.reservedAlarmB - - - - Reserved for future use - - */ - unsigned int reservedAlarmB : 1; /* 1E.CC00.2 LH */ - /* Reserved for future use - */ - /*! \brief 1E.CC00.3 LH Reserved Alarm A - AQ_GlobalAlarms_HHD.u0.bits_0.reservedAlarmA - - - - Reserved for future use - - */ - unsigned int reservedAlarmA : 1; /* 1E.CC00.3 LH */ - /* Reserved for future use - */ - /*! \brief 1E.CC00.4 LH Device Fault - AQ_GlobalAlarms_HHD.u0.bits_0.deviceFault - - - - 1 = Fault - - Notes: - When set, a fault has been detected by the uP and the associated 16 bit error code is visible in See Global Configuration Fault Message: Address 1E.C850 */ - unsigned int deviceFault : 1; /* 1E.CC00.4 LH */ - /* 1 = Fault */ - unsigned int reserved2 : 1; - /*! \brief 1E.CC00.6 LH Reset completed - AQ_GlobalAlarms_HHD.u0.bits_0.resetCompleted - - - - 1 = Chip wide reset completed - - Notes: - This bit is set by the microprocessor when it has completed it's initialization sequence. This bit is mirrored in 1.CC02.0 */ - unsigned int resetCompleted : 1; /* 1E.CC00.6 LH */ - /* 1 = Chip wide reset completed */ - unsigned int reserved1 : 4; - /*! \brief 1E.CC00.B LH Low Temperature Warning - AQ_GlobalAlarms_HHD.u0.bits_0.lowTemperatureWarning - - - - 1 = Low temperature warning threshold has been exceeded - - - Notes: - - - - - These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ - unsigned int lowTemperatureWarning : 1; /* 1E.CC00.B LH */ - /* 1 = Low temperature warning threshold has been exceeded - */ - /*! \brief 1E.CC00.C LH High Temperature Warning - AQ_GlobalAlarms_HHD.u0.bits_0.highTemperatureWarning - - - - 1 = High temperature warning threshold has been exceeded - - - Notes: - - - - - These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ - unsigned int highTemperatureWarning : 1; /* 1E.CC00.C LH */ - /* 1 = High temperature warning threshold has been exceeded - */ - /*! \brief 1E.CC00.D LH Low Temperature Failure - AQ_GlobalAlarms_HHD.u0.bits_0.lowTemperatureFailure - - - - 1 = Low temperature failure threshold has been exceeded - - - Notes: - - - - - These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ - unsigned int lowTemperatureFailure : 1; /* 1E.CC00.D LH */ - /* 1 = Low temperature failure threshold has been exceeded - */ - /*! \brief 1E.CC00.E LH High Temperature Failure - AQ_GlobalAlarms_HHD.u0.bits_0.highTemperatureFailure - - - - 1 = High temperature failure threshold has been exceeded - - - Notes: - - - - - These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ - unsigned int highTemperatureFailure : 1; /* 1E.CC00.E LH */ - /* 1 = High temperature failure threshold has been exceeded - */ - unsigned int reserved0 : 1; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Alarms */ - union - { - struct - { - unsigned int reserved2 : 1; - unsigned int reserved1 : 6; - /*! \brief 1E.CC01.7 LH MDIO Command Handling Overflow - AQ_GlobalAlarms_HHD.u1.bits_1.mdioCommandHandlingOverflow - - - - 1 = PHY was issued more MDIO requests than it could service in it's request buffer - - - Notes: - Assertion of this bit means that more MDIO commands were issued than FW could handle. */ - unsigned int mdioCommandHandlingOverflow : 1; /* 1E.CC01.7 LH */ - /* 1 = PHY was issued more MDIO requests than it could service in it's request buffer - */ - /*! \brief 1E.CC01.A:8 LH Reserved Alarms [2:0] - AQ_GlobalAlarms_HHD.u1.bits_1.reservedAlarms - - - - Reserved - - - */ - unsigned int reservedAlarms : 3; /* 1E.CC01.A:8 LH */ - /* Reserved - - */ - /*! \brief 1E.CC01.B LH DTE Status Change - AQ_GlobalAlarms_HHD.u1.bits_1.dteStatusChange - - - - 1 = DTE status change - - - Notes: - Change in 1E.C887[F]. */ - unsigned int dteStatusChange : 1; /* 1E.CC01.B LH */ - /* 1 = DTE status change - */ - /*! \brief 1E.CC01.C LH IP Phone Detect - AQ_GlobalAlarms_HHD.u1.bits_1.ipPhoneDetect - - - - 1 = IP Phone Detect - - - Notes: - Assertion of this bit means that the presence of an IP Phone has been detected. */ - unsigned int ipPhoneDetect : 1; /* 1E.CC01.C LH */ - /* 1 = IP Phone Detect - */ - /*! \brief 1E.CC01.D RO XENPAK Alarm - AQ_GlobalAlarms_HHD.u1.bits_1.xenpakAlarm - - - - 1 = XENPAK Alarm - - */ - unsigned int xenpakAlarm : 1; /* 1E.CC01.D RO */ - /* 1 = XENPAK Alarm - */ - /*! \brief 1E.CC01.E LH Smart Power-Down Entered - AQ_GlobalAlarms_HHD.u1.bits_1.smartPower_downEntered - - - - 1 = Smart Power-Down State Entered - - - Notes: - When this bit is set, it indicates that the Smart Power-Down state was entered */ - unsigned int smartPower_downEntered : 1; /* 1E.CC01.E LH */ - /* 1 = Smart Power-Down State Entered - */ - unsigned int reserved0 : 1; - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global Alarms */ - union - { - struct - { - /*! \brief 1E.CC02.0 LH Watchdog Timer Alarm - AQ_GlobalAlarms_HHD.u2.bits_2.watchdogTimerAlarm - - - - 1 = Watchdog timer alarm - - */ - unsigned int watchdogTimerAlarm : 1; /* 1E.CC02.0 LH */ - /* 1 = Watchdog timer alarm - */ - /*! \brief 1E.CC02.1 LH MDIO Timeout Error - AQ_GlobalAlarms_HHD.u2.bits_2.mdioTimeoutError - - - - 1 = MDIO timeout detected - - */ - unsigned int mdioTimeoutError : 1; /* 1E.CC02.1 LH */ - /* 1 = MDIO timeout detected - */ - /*! \brief 1E.CC02.2 LH MDIO MMD Error - AQ_GlobalAlarms_HHD.u2.bits_2.mdioMMD_Error - - - - 1 = Invalid MMD address detected - - */ - unsigned int mdioMMD_Error : 1; /* 1E.CC02.2 LH */ - /* 1 = Invalid MMD address detected - */ - unsigned int reserved2 : 2; - /*! \brief 1E.CC02.5 LRF Tx Enable State Change - AQ_GlobalAlarms_HHD.u2.bits_2.txEnableStateChange - - - - 1 = TX_EN pin has changed state - - */ - unsigned int txEnableStateChange : 1; /* 1E.CC02.5 LRF */ - /* 1 = TX_EN pin has changed state - */ - unsigned int reserved1 : 2; - /*! \brief 1E.CC02.9:8 LH uP IRAM Parity Error [1:0] - AQ_GlobalAlarms_HHD.u2.bits_2.upIramParityError - - - - 1 = Parity error detected in the uP IRAM - - - Notes: - Bit 0 indicates a parity error was detected in the uP IRAM but was corrected. - Bit 1 indicates a multiple parity errors were detected in the uP IRAM and could not be corrected. - The uP IRAM is protected with ECC. */ - unsigned int upIramParityError : 2; /* 1E.CC02.9:8 LH */ - /* 1 = Parity error detected in the uP IRAM - */ - /*! \brief 1E.CC02.A LH uP DRAM Parity Error - AQ_GlobalAlarms_HHD.u2.bits_2.upDramParityError - - - - 1 = Parity error detected in the uP DRAM - - */ - unsigned int upDramParityError : 1; /* 1E.CC02.A LH */ - /* 1 = Parity error detected in the uP DRAM - */ - unsigned int reserved0 : 3; - /*! \brief 1E.CC02.E LH Mailbox Operation: Complete - AQ_GlobalAlarms_HHD.u2.bits_2.mailboxOperation_Complete - - - - 1 = Mailbox operation is complete - - - Notes: - Mailbox interface is ready interrupt for registers See Global Vendor Specific Control - Address 1E.C000 - See Global Vendor Specific Provisioning 5 - Address 1E.C404 */ - unsigned int mailboxOperation_Complete : 1; /* 1E.CC02.E LH */ - /* 1 = Mailbox operation is complete - */ - /*! \brief 1E.CC02.F LH NVR Operation Complete - AQ_GlobalAlarms_HHD.u2.bits_2.nvrOperationComplete - - - - 1 = NVR operation is complete - - - Notes: - NVR interface is ready interrupt for registers See Global NVR Interface 1: Address 1E.100 - See Global NVR Provisioning Data MSW - Address 1E.17 . */ - unsigned int nvrOperationComplete : 1; /* 1E.CC02.F LH */ - /* 1 = NVR operation is complete - */ - } bits_2; - uint16_t word_2; - } u2; -} AQ_GlobalAlarms_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Interrupt Mask: 1E.D400 */ -/* Global Interrupt Mask: 1E.D400 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Interrupt Mask */ - union - { - struct - { - /*! \brief 1E.D400.0 R/WPD Reserved Alarm D Mask - AQ_GlobalInterruptMask_HHD.u0.bits_0.reservedAlarmDMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int reservedAlarmDMask : 1; /* 1E.D400.0 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - /*! \brief 1E.D400.1 R/WPD Reserved Alarm C Mask - AQ_GlobalInterruptMask_HHD.u0.bits_0.reservedAlarmCMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int reservedAlarmCMask : 1; /* 1E.D400.1 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - /*! \brief 1E.D400.2 R/WPD Reserved Alarm B Mask - AQ_GlobalInterruptMask_HHD.u0.bits_0.reservedAlarmBMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int reservedAlarmBMask : 1; /* 1E.D400.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - /*! \brief 1E.D400.3 R/WPD Reserved Alarm A Mask - AQ_GlobalInterruptMask_HHD.u0.bits_0.reservedAlarmAMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int reservedAlarmAMask : 1; /* 1E.D400.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - /*! \brief 1E.D400.4 R/WPD Device Fault Mask - AQ_GlobalInterruptMask_HHD.u0.bits_0.deviceFaultMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int deviceFaultMask : 1; /* 1E.D400.4 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - unsigned int reserved2 : 1; - /*! \brief 1E.D400.6 R/WPD Reset completed Mask - AQ_GlobalInterruptMask_HHD.u0.bits_0.resetCompletedMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int resetCompletedMask : 1; /* 1E.D400.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - unsigned int reserved1 : 4; - /*! \brief 1E.D400.B R/WPD Low Temperature Warning Mask - AQ_GlobalInterruptMask_HHD.u0.bits_0.lowTemperatureWarningMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int lowTemperatureWarningMask : 1; /* 1E.D400.B R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.D400.C R/WPD High Temperature Warning Mask - AQ_GlobalInterruptMask_HHD.u0.bits_0.highTemperatureWarningMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int highTemperatureWarningMask : 1; /* 1E.D400.C R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.D400.D R/WPD Low Temperature Failure Mask - AQ_GlobalInterruptMask_HHD.u0.bits_0.lowTemperatureFailureMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int lowTemperatureFailureMask : 1; /* 1E.D400.D R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.D400.E R/WPD High Temperature Failure Mask - AQ_GlobalInterruptMask_HHD.u0.bits_0.highTemperatureFailureMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int highTemperatureFailureMask : 1; /* 1E.D400.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - unsigned int reserved0 : 1; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Interrupt Mask */ - union - { - struct - { - /*! \brief 1E.D401.0 R/WPD Diagnostic Alarm Mask - AQ_GlobalInterruptMask_HHD.u1.bits_1.diagnosticAlarmMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int diagnosticAlarmMask : 1; /* 1E.D401.0 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int reserved1 : 6; - /*! \brief 1E.D401.7 R/WPD MDIO Command Handling Overflow Mask - AQ_GlobalInterruptMask_HHD.u1.bits_1.mdioCommandHandlingOverflowMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int mdioCommandHandlingOverflowMask : 1; /* 1E.D401.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - /*! \brief 1E.D401.A:8 R/WPD Reserved Alarms Mask [2:0] - AQ_GlobalInterruptMask_HHD.u1.bits_1.reservedAlarmsMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int reservedAlarmsMask : 3; /* 1E.D401.A:8 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - /*! \brief 1E.D401.B R/WPD DTE Status Change Mask - AQ_GlobalInterruptMask_HHD.u1.bits_1.dteStatusChangeMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int dteStatusChangeMask : 1; /* 1E.D401.B R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - /*! \brief 1E.D401.C R/WPD IP Phone Detect Mask - AQ_GlobalInterruptMask_HHD.u1.bits_1.ipPhoneDetectMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int ipPhoneDetectMask : 1; /* 1E.D401.C R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - /*! \brief 1E.D401.D R/WPD XENPAK Alarm Mask - AQ_GlobalInterruptMask_HHD.u1.bits_1.xenpakAlarmMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int xenpakAlarmMask : 1; /* 1E.D401.D R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.D401.E R/WPD Smart Power-Down Entered Mask - AQ_GlobalInterruptMask_HHD.u1.bits_1.smartPower_downEnteredMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int smartPower_downEnteredMask : 1; /* 1E.D401.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int reserved0 : 1; - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global Interrupt Mask */ - union - { - struct - { - /*! \brief 1E.D402.0 R/WPD Watchdog Timer Alarm Mask - AQ_GlobalInterruptMask_HHD.u2.bits_2.watchdogTimerAlarmMask - - Provisionable Default = 0x1 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int watchdogTimerAlarmMask : 1; /* 1E.D402.0 R/WPD Provisionable Default = 0x1 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.D402.1 R/WPD MDIO Timeout Error Mask - AQ_GlobalInterruptMask_HHD.u2.bits_2.mdioTimeoutErrorMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int mdioTimeoutErrorMask : 1; /* 1E.D402.1 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.D402.2 R/WPD MDIO MMD Error Mask - AQ_GlobalInterruptMask_HHD.u2.bits_2.mdioMMD_ErrorMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int mdioMMD_ErrorMask : 1; /* 1E.D402.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - unsigned int reserved2 : 2; - /*! \brief 1E.D402.5 R/WPD Tx Enable State Change Mask - AQ_GlobalInterruptMask_HHD.u2.bits_2.txEnableStateChangeMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int txEnableStateChangeMask : 1; /* 1E.D402.5 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - unsigned int reserved1 : 2; - /*! \brief 1E.D402.9:8 R/WPD uP IRAM Parity Error Mask [1:0] - AQ_GlobalInterruptMask_HHD.u2.bits_2.upIramParityErrorMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int upIramParityErrorMask : 2; /* 1E.D402.9:8 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - /*! \brief 1E.D402.A R/WPD uP DRAM Parity Error Mask - AQ_GlobalInterruptMask_HHD.u2.bits_2.upDramParityErrorMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int upDramParityErrorMask : 1; /* 1E.D402.A R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int reserved0 : 3; - /*! \brief 1E.D402.E R/WPD Mailbox Operation Complete Mask - AQ_GlobalInterruptMask_HHD.u2.bits_2.mailboxOperationCompleteMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - Notes: - Mailbox interface is ready interrupt for registers See Global Vendor Specific Control - Address 1E.C000 - See Global Vendor Specific Provisioning 5 - Address 1E.C404 */ - unsigned int mailboxOperationCompleteMask : 1; /* 1E.D402.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.D402.F R/WPD NVR Operation Complete Mask - AQ_GlobalInterruptMask_HHD.u2.bits_2.nvrOperationCompleteMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - Notes: - NVR interface is ready interrupt for registers See Global NVR Interface 1: Address 1E.100 - See Global NVR Provisioning Data MSW - Address 1E.17 */ - unsigned int nvrOperationCompleteMask : 1; /* 1E.D402.F R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - } bits_2; - uint16_t word_2; - } u2; -} AQ_GlobalInterruptMask_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Chip-Wide Standard Interrupt Flags: 1E.FC00 */ -/* Global Chip-Wide Standard Interrupt Flags: 1E.FC00 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Chip-Wide Standard Interrupt Flags */ - union - { - struct - { - /*! \brief 1E.FC00.0 RO All Vendor Alarms Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.allVendorAlarmsInterrupt - - - - 1 = Interrupt in all vendor alarms - - - Notes: - An interrupt was generated from status register ( See Global Chip-Wide LASI Vendor Interrupt Flags: Address 1E.FC01 ) and the corresponding mask register. ( See Global Interrupt LASI Mask: Address 1E.FF01 ) */ - unsigned int allVendorAlarmsInterrupt : 1; /* 1E.FC00.0 RO */ - /* 1 = Interrupt in all vendor alarms - */ - unsigned int reserved0 : 5; - /*! \brief 1E.FC00.6 RO GbE Standard Alarms Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.gbeStandardAlarmsInterrupt - - - - 1 = Interrupt in GbE standard alarms - - - Notes: - An interrupt was generated from the TGE core. */ - unsigned int gbeStandardAlarmsInterrupt : 1; /* 1E.FC00.6 RO */ - /* 1 = Interrupt in GbE standard alarms - */ - /*! \brief 1E.FC00.7 RO Autonegotiation Standard Alarms 2 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.autonegotiationStandardAlarms_2Interrupt - - - - 1 = Interrupt in Autonegotiation standard alarms 2 - - - Notes: - An interrupt was generated from status register ( See Autonegotiation 10GBASE-T Status Register - Address 7.21 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ - unsigned int autonegotiationStandardAlarms_2Interrupt : 1; /* 1E.FC00.7 RO */ - /* 1 = Interrupt in Autonegotiation standard alarms 2 - */ - /*! \brief 1E.FC00.8 RO Autonegotiation Standard Alarms 1 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.autonegotiationStandardAlarms_1Interrupt - - - - 1 = Interrupt in Autonegotiation standard alarms 1 - - - Notes: - An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See Autonegotiation Standard LASI Interrupt Mask 1: Address 7.D000 ) */ - unsigned int autonegotiationStandardAlarms_1Interrupt : 1; /* 1E.FC00.8 RO */ - /* 1 = Interrupt in Autonegotiation standard alarms 1 - */ - /*! \brief 1E.FC00.9 RO PHY XS Standard Alarms 2 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.phyXS_StandardAlarms_2Interrupt - - - - 1 = Interrupt in PHY XS standard alarms 2 - - - Notes: - An interrupt was generated from the status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ - unsigned int phyXS_StandardAlarms_2Interrupt : 1; /* 1E.FC00.9 RO */ - /* 1 = Interrupt in PHY XS standard alarms 2 - */ - /*! \brief 1E.FC00.A RO PHY XS Standard Alarms 1 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.phyXS_StandardAlarms_1Interrupt - - - - 1 = Interrupt in PHY XS standard alarms 1 - - - Notes: - An interrupt was generated from the status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ - unsigned int phyXS_StandardAlarms_1Interrupt : 1; /* 1E.FC00.A RO */ - /* 1 = Interrupt in PHY XS standard alarms 1 - */ - /*! \brief 1E.FC00.B RO PCS Standard Alarm 3 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.pcsStandardAlarm_3Interrupt - - - - 1 = Interrupt in PCS standard alarms 3 - - - Notes: - An interrupt was generated from status register ( See PCS 10GBASE-T Status 2 - Address 3.21 ) and the corresponding mask register. ( See PCS Standard Interrupt Mask 1 - Address 3.E021 ) */ - unsigned int pcsStandardAlarm_3Interrupt : 1; /* 1E.FC00.B RO */ - /* 1 = Interrupt in PCS standard alarms 3 - */ - /*! \brief 1E.FC00.C RO PCS Standard Alarm 2 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.pcsStandardAlarm_2Interrupt - - - - 1 = Interrupt in PCS standard alarms 2 - - - Notes: - An interrupt was generated from status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ - unsigned int pcsStandardAlarm_2Interrupt : 1; /* 1E.FC00.C RO */ - /* 1 = Interrupt in PCS standard alarms 2 - */ - /*! \brief 1E.FC00.D RO PCS Standard Alarm 1 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.pcsStandardAlarm_1Interrupt - - - - 1 = Interrupt in PCS standard alarms 1 - - - Notes: - An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ - unsigned int pcsStandardAlarm_1Interrupt : 1; /* 1E.FC00.D RO */ - /* 1 = Interrupt in PCS standard alarms 1 - */ - /*! \brief 1E.FC00.E RO PMA Standard Alarm 2 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.pmaStandardAlarm_2Interrupt - - - - 1 = Interrupt in PMA standard alarms 2 - - - Notes: - An interrupt was generated from either bit 1.8.B or 1.8.A. - An interrupt was generated from status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ - unsigned int pmaStandardAlarm_2Interrupt : 1; /* 1E.FC00.E RO */ - /* 1 = Interrupt in PMA standard alarms 2 - */ - /*! \brief 1E.FC00.F RO PMA Standard Alarm 1 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.pmaStandardAlarm_1Interrupt - - - - 1 = Interrupt in PMA standard alarms 1 - - - Notes: - An interrupt was generated from bit 1.1.2. - An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ - unsigned int pmaStandardAlarm_1Interrupt : 1; /* 1E.FC00.F RO */ - /* 1 = Interrupt in PMA standard alarms 1 - */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalChip_wideStandardInterruptFlags_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Chip-Wide Vendor Interrupt Flags: 1E.FC01 */ -/* Global Chip-Wide Vendor Interrupt Flags: 1E.FC01 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Chip-Wide Vendor Interrupt Flags */ - union - { - struct - { - /*! \brief 1E.FC01.0 RO Global Alarms 3 Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.globalAlarms_3Interrupt - - - - 1 = Interrupt in Global alarms 3 - - - Notes: - An interrupt was generated from status register ( See Global Vendor Alarms 2: Address 1E.CC01 ) and the corresponding mask register. ( See Global LASI Interrupt Mask 2: Address 1E.D401 ) */ - unsigned int globalAlarms_3Interrupt : 1; /* 1E.FC01.0 RO */ - /* 1 = Interrupt in Global alarms 3 - */ - /*! \brief 1E.FC01.1 RO Global Alarms 2 Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.globalAlarms_2Interrupt - - - - 1 = Interrupt in Global alarms 2 - - - Notes: - An interrupt was generated from status register ( See Global Alarms 2: Address 1E.CC01 ) and the corresponding mask register. ( See Global LASI Interrupt Mask 2: Address 1E.D401 ) */ - unsigned int globalAlarms_2Interrupt : 1; /* 1E.FC01.1 RO */ - /* 1 = Interrupt in Global alarms 2 - */ - /*! \brief 1E.FC01.2 RO Global Alarms 1 Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.globalAlarms_1Interrupt - - - - 1 = Interrupt in Global alarms 1 - - - Notes: - An interrupt was generated from status register ( See Global Vendor Alarms 1 - Address 1E.CC00 ) and the corresponding mask register. ( See Global Vendor Interrupt Mask - Address 1E.D400 ) */ - unsigned int globalAlarms_1Interrupt : 1; /* 1E.FC01.2 RO */ - /* 1 = Interrupt in Global alarms 1 - */ - unsigned int reserved0 : 8; - /*! \brief 1E.FC01.B RO GbE Vendor Alarm Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.gbeVendorAlarmInterrupt - - - - 1 = Interrupt in GbE vendor specific alarm - - - Notes: - A GbE alarm was generated. ( See GbE PHY Vendor Global LASI Interrupt Flags 1: Address 1D.FC00 ) */ - unsigned int gbeVendorAlarmInterrupt : 1; /* 1E.FC01.B RO */ - /* 1 = Interrupt in GbE vendor specific alarm - */ - /*! \brief 1E.FC01.C RO Autonegotiation Vendor Alarm Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.autonegotiationVendorAlarmInterrupt - - - - 1 = Interrupt in Autonegotiation vendor specific alarm - - - Notes: - An Autonegotiation alarm was generated. ( See Autonegotiation Vendor Global LASI Interrupt Flags 1: Address 7.FC00 ) */ - unsigned int autonegotiationVendorAlarmInterrupt : 1; /* 1E.FC01.C RO */ - /* 1 = Interrupt in Autonegotiation vendor specific alarm - */ - /*! \brief 1E.FC01.D RO PHY XS Vendor Alarm Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.phyXS_VendorAlarmInterrupt - - - - 1 = Interrupt in PHY XS vendor specific alarm - - - Notes: - A PHY XS alarm was generated. ( See PHY XS Vendor Global LASI Interrupt Flags 1: Address 4.FC00 ) */ - unsigned int phyXS_VendorAlarmInterrupt : 1; /* 1E.FC01.D RO */ - /* 1 = Interrupt in PHY XS vendor specific alarm - */ - /*! \brief 1E.FC01.E RO PCS Vendor Alarm Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.pcsVendorAlarmInterrupt - - - - 1 = Interrupt in PCS vendor specific alarm - - - Notes: - A PCS alarm was generated. ( See PHY XS Vendor Global Interrupt Flags 1- Address 4.F800 ) */ - unsigned int pcsVendorAlarmInterrupt : 1; /* 1E.FC01.E RO */ - /* 1 = Interrupt in PCS vendor specific alarm - */ - /*! \brief 1E.FC01.F RO PMA Vendor Alarm Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.pmaVendorAlarmInterrupt - - - - 1 = Interrupt in PMA vendor specific alarm - - - Notes: - A PMA alarm was generated. ( See PHY XS Vendor Global Interrupt Flags 1- Address 4.F800 ) */ - unsigned int pmaVendorAlarmInterrupt : 1; /* 1E.FC01.F RO */ - /* 1 = Interrupt in PMA vendor specific alarm - */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalChip_wideVendorInterruptFlags_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Interrupt Chip-Wide Standard Mask: 1E.FF00 */ -/* Global Interrupt Chip-Wide Standard Mask: 1E.FF00 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Interrupt Chip-Wide Standard Mask */ - union - { - struct - { - /*! \brief 1E.FF00.0 R/WPD All Vendor Alarms Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.allVendorAlarmsInterruptMask - - Provisionable Default = 0x1 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int allVendorAlarmsInterruptMask : 1; /* 1E.FF00.0 R/WPD Provisionable Default = 0x1 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - unsigned int reserved0 : 5; - /*! \brief 1E.FF00.6 R/WPD Gbe Standard Alarms Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.gbeStandardAlarmsInterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int gbeStandardAlarmsInterruptMask : 1; /* 1E.FF00.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.7 R/WPD Autonegotiation Standard Alarms 2 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.autonegotiationStandardAlarms_2InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int autonegotiationStandardAlarms_2InterruptMask : 1; /* 1E.FF00.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.8 R/WPD Autonegotiation Standard Alarms 1 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.autonegotiationStandardAlarms_1InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int autonegotiationStandardAlarms_1InterruptMask : 1; /* 1E.FF00.8 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.9 R/WPD PHY XS Standard Alarms 2 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.phyXS_StandardAlarms_2InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int phyXS_StandardAlarms_2InterruptMask : 1; /* 1E.FF00.9 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.A R/WPD PHY XS Standard Alarms 1 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.phyXS_StandardAlarms_1InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int phyXS_StandardAlarms_1InterruptMask : 1; /* 1E.FF00.A R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.B R/WPD PCS Standard Alarm 3 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.pcsStandardAlarm_3InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int pcsStandardAlarm_3InterruptMask : 1; /* 1E.FF00.B R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.C R/WPD PCS Standard Alarm 2 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.pcsStandardAlarm_2InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int pcsStandardAlarm_2InterruptMask : 1; /* 1E.FF00.C R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.D R/WPD PCS Standard Alarm 1 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.pcsStandardAlarm_1InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int pcsStandardAlarm_1InterruptMask : 1; /* 1E.FF00.D R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.E R/WPD PMA Standard Alarm 2 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.pmaStandardAlarm_2InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int pmaStandardAlarm_2InterruptMask : 1; /* 1E.FF00.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.F R/WPD PMA Standard Alarm 1 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.pmaStandardAlarm_1InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int pmaStandardAlarm_1InterruptMask : 1; /* 1E.FF00.F R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalInterruptChip_wideStandardMask_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Interrupt Chip-Wide Vendor Mask: 1E.FF01 */ -/* Global Interrupt Chip-Wide Vendor Mask: 1E.FF01 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Interrupt Chip-Wide Vendor Mask */ - union - { - struct - { - /*! \brief 1E.FF01.0 R/WPD Global Alarms 3 Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.globalAlarms_3InterruptMask - - Provisionable Default = 0x1 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int globalAlarms_3InterruptMask : 1; /* 1E.FF01.0 R/WPD Provisionable Default = 0x1 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF01.1 R/WPD Global Alarms 2 Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.globalAlarms_2InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int globalAlarms_2InterruptMask : 1; /* 1E.FF01.1 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF01.2 R/WPD Global Alarms 1 Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.globalAlarms_1InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int globalAlarms_1InterruptMask : 1; /* 1E.FF01.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - unsigned int reserved0 : 8; - /*! \brief 1E.FF01.B R/WPD GbE Vendor Alarm Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.gbeVendorAlarmInterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int gbeVendorAlarmInterruptMask : 1; /* 1E.FF01.B R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF01.C R/WPD Autonegotiation Vendor Alarm Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.autonegotiationVendorAlarmInterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int autonegotiationVendorAlarmInterruptMask : 1; /* 1E.FF01.C R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF01.D R/WPD PHY XS Vendor Alarm Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.phyXS_VendorAlarmInterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int phyXS_VendorAlarmInterruptMask : 1; /* 1E.FF01.D R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF01.E R/WPD PCS Vendor Alarm Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.pcsVendorAlarmInterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int pcsVendorAlarmInterruptMask : 1; /* 1E.FF01.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF01.F R/WPD PMA Vendor Alarm Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.pmaVendorAlarmInterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int pmaVendorAlarmInterruptMask : 1; /* 1E.FF01.F R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalInterruptChip_wideVendorMask_HHD; - -#endif -/*@}*/ -/*@}*/ diff --git a/qca/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers_Defines.h b/qca/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers_Defines.h deleted file mode 100644 index d9a4429d5..000000000 --- a/qca/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers_Defines.h +++ /dev/null @@ -1,4413 +0,0 @@ -/*! \file -* This file contains the compiler assist macros and doxygen comments -* for the Global Registers block. -*/ - -/*! \defgroup Global_registers_Defines Global Registers Defines -* This module contains the compiler assist macros and doxygen comments -* for the Global Registers block. -*/ -/*********************************************************************** -* Copyright (c) 2015, Aquantia -* -* Permission to use, copy, modify, and/or distribute this software for any -* purpose with or without fee is hereby granted, provided that the above -* copyright notice and this permission notice appear in all copies. -* -* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -* -* $File: //depot/icm/proj/Dena/rev1.0/c/Systems/tools/windows/regMapParser/src/gencheaders.py $ -* -* $Revision: #10 $ -* -* $DateTime: 2014/04/08 16:55:58 $ -* -* $Author: joshd $ -* -* $Label: $ -* -* Description: -* -* This file contains the compiler assist macros for the registers contained in the Global Registers block. -* -* -***********************************************************************/ - - -/*@{*/ -#ifndef AQ_HHD_GLOBAL_REGS_DEFINES_HEADER -#define AQ_HHD_GLOBAL_REGS_DEFINES_HEADER - - -/*-----------------------------------------------------------------------------*/ -/*Access macro definitions */ -/*-----------------------------------------------------------------------------*/ -/*! \brief Base register address of structure AQ_GlobalStandardControl_1_HHD */ -#define AQ_GlobalStandardControl_1_HHD_baseRegisterAddress 0x0000 -/*! \brief MMD address of structure AQ_GlobalStandardControl_1_HHD */ -#define AQ_GlobalStandardControl_1_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure softReset in AQ_GlobalStandardControl_1_HHD */ -#define AQ_GlobalStandardControl_1_HHD_softReset 0 -/*! \brief Preprocessor variable to relate field to bit position in structure softReset in AQ_GlobalStandardControl_1_HHD */ -#define bits_AQ_GlobalStandardControl_1_HHD_softReset u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure softReset in AQ_GlobalStandardControl_1_HHD */ -#define word_AQ_GlobalStandardControl_1_HHD_softReset u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure lowPower in AQ_GlobalStandardControl_1_HHD */ -#define AQ_GlobalStandardControl_1_HHD_lowPower 0 -/*! \brief Preprocessor variable to relate field to bit position in structure lowPower in AQ_GlobalStandardControl_1_HHD */ -#define bits_AQ_GlobalStandardControl_1_HHD_lowPower u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure lowPower in AQ_GlobalStandardControl_1_HHD */ -#define word_AQ_GlobalStandardControl_1_HHD_lowPower u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalStandardDeviceIdentifier_HHD */ -#define AQ_GlobalStandardDeviceIdentifier_HHD_baseRegisterAddress 0x0002 -/*! \brief MMD address of structure AQ_GlobalStandardDeviceIdentifier_HHD */ -#define AQ_GlobalStandardDeviceIdentifier_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure deviceIdMSW in AQ_GlobalStandardDeviceIdentifier_HHD */ -#define AQ_GlobalStandardDeviceIdentifier_HHD_deviceIdMSW 0 -/*! \brief Preprocessor variable to relate field to bit position in structure deviceIdMSW in AQ_GlobalStandardDeviceIdentifier_HHD */ -#define bits_AQ_GlobalStandardDeviceIdentifier_HHD_deviceIdMSW u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure deviceIdMSW in AQ_GlobalStandardDeviceIdentifier_HHD */ -#define word_AQ_GlobalStandardDeviceIdentifier_HHD_deviceIdMSW u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure deviceIdLSW in AQ_GlobalStandardDeviceIdentifier_HHD */ -#define AQ_GlobalStandardDeviceIdentifier_HHD_deviceIdLSW 1 -/*! \brief Preprocessor variable to relate field to bit position in structure deviceIdLSW in AQ_GlobalStandardDeviceIdentifier_HHD */ -#define bits_AQ_GlobalStandardDeviceIdentifier_HHD_deviceIdLSW u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure deviceIdLSW in AQ_GlobalStandardDeviceIdentifier_HHD */ -#define word_AQ_GlobalStandardDeviceIdentifier_HHD_deviceIdLSW u1.word_1 - -/*! \brief Base register address of structure AQ_GlobalStandardDevicesInPackage_HHD */ -#define AQ_GlobalStandardDevicesInPackage_HHD_baseRegisterAddress 0x0005 -/*! \brief MMD address of structure AQ_GlobalStandardDevicesInPackage_HHD */ -#define AQ_GlobalStandardDevicesInPackage_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationPresent in AQ_GlobalStandardDevicesInPackage_HHD */ -#define AQ_GlobalStandardDevicesInPackage_HHD_autonegotiationPresent 0 -/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationPresent in AQ_GlobalStandardDevicesInPackage_HHD */ -#define bits_AQ_GlobalStandardDevicesInPackage_HHD_autonegotiationPresent u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationPresent in AQ_GlobalStandardDevicesInPackage_HHD */ -#define word_AQ_GlobalStandardDevicesInPackage_HHD_autonegotiationPresent u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure tcPresent in AQ_GlobalStandardDevicesInPackage_HHD */ -#define AQ_GlobalStandardDevicesInPackage_HHD_tcPresent 0 -/*! \brief Preprocessor variable to relate field to bit position in structure tcPresent in AQ_GlobalStandardDevicesInPackage_HHD */ -#define bits_AQ_GlobalStandardDevicesInPackage_HHD_tcPresent u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure tcPresent in AQ_GlobalStandardDevicesInPackage_HHD */ -#define word_AQ_GlobalStandardDevicesInPackage_HHD_tcPresent u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure dteXsPresent in AQ_GlobalStandardDevicesInPackage_HHD */ -#define AQ_GlobalStandardDevicesInPackage_HHD_dteXsPresent 0 -/*! \brief Preprocessor variable to relate field to bit position in structure dteXsPresent in AQ_GlobalStandardDevicesInPackage_HHD */ -#define bits_AQ_GlobalStandardDevicesInPackage_HHD_dteXsPresent u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure dteXsPresent in AQ_GlobalStandardDevicesInPackage_HHD */ -#define word_AQ_GlobalStandardDevicesInPackage_HHD_dteXsPresent u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure phyXS_Present in AQ_GlobalStandardDevicesInPackage_HHD */ -#define AQ_GlobalStandardDevicesInPackage_HHD_phyXS_Present 0 -/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_Present in AQ_GlobalStandardDevicesInPackage_HHD */ -#define bits_AQ_GlobalStandardDevicesInPackage_HHD_phyXS_Present u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure phyXS_Present in AQ_GlobalStandardDevicesInPackage_HHD */ -#define word_AQ_GlobalStandardDevicesInPackage_HHD_phyXS_Present u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pcsPresent in AQ_GlobalStandardDevicesInPackage_HHD */ -#define AQ_GlobalStandardDevicesInPackage_HHD_pcsPresent 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pcsPresent in AQ_GlobalStandardDevicesInPackage_HHD */ -#define bits_AQ_GlobalStandardDevicesInPackage_HHD_pcsPresent u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pcsPresent in AQ_GlobalStandardDevicesInPackage_HHD */ -#define word_AQ_GlobalStandardDevicesInPackage_HHD_pcsPresent u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure wisPresent in AQ_GlobalStandardDevicesInPackage_HHD */ -#define AQ_GlobalStandardDevicesInPackage_HHD_wisPresent 0 -/*! \brief Preprocessor variable to relate field to bit position in structure wisPresent in AQ_GlobalStandardDevicesInPackage_HHD */ -#define bits_AQ_GlobalStandardDevicesInPackage_HHD_wisPresent u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure wisPresent in AQ_GlobalStandardDevicesInPackage_HHD */ -#define word_AQ_GlobalStandardDevicesInPackage_HHD_wisPresent u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pmaPresent in AQ_GlobalStandardDevicesInPackage_HHD */ -#define AQ_GlobalStandardDevicesInPackage_HHD_pmaPresent 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pmaPresent in AQ_GlobalStandardDevicesInPackage_HHD */ -#define bits_AQ_GlobalStandardDevicesInPackage_HHD_pmaPresent u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pmaPresent in AQ_GlobalStandardDevicesInPackage_HHD */ -#define word_AQ_GlobalStandardDevicesInPackage_HHD_pmaPresent u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure clause_22RegistersPresent in AQ_GlobalStandardDevicesInPackage_HHD */ -#define AQ_GlobalStandardDevicesInPackage_HHD_clause_22RegistersPresent 0 -/*! \brief Preprocessor variable to relate field to bit position in structure clause_22RegistersPresent in AQ_GlobalStandardDevicesInPackage_HHD */ -#define bits_AQ_GlobalStandardDevicesInPackage_HHD_clause_22RegistersPresent u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure clause_22RegistersPresent in AQ_GlobalStandardDevicesInPackage_HHD */ -#define word_AQ_GlobalStandardDevicesInPackage_HHD_clause_22RegistersPresent u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalStandardVendorDevicesInPackage_HHD */ -#define AQ_GlobalStandardVendorDevicesInPackage_HHD_baseRegisterAddress 0x0006 -/*! \brief MMD address of structure AQ_GlobalStandardVendorDevicesInPackage_HHD */ -#define AQ_GlobalStandardVendorDevicesInPackage_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure vendorSpecificDevice_2Present in AQ_GlobalStandardVendorDevicesInPackage_HHD */ -#define AQ_GlobalStandardVendorDevicesInPackage_HHD_vendorSpecificDevice_2Present 0 -/*! \brief Preprocessor variable to relate field to bit position in structure vendorSpecificDevice_2Present in AQ_GlobalStandardVendorDevicesInPackage_HHD */ -#define bits_AQ_GlobalStandardVendorDevicesInPackage_HHD_vendorSpecificDevice_2Present u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure vendorSpecificDevice_2Present in AQ_GlobalStandardVendorDevicesInPackage_HHD */ -#define word_AQ_GlobalStandardVendorDevicesInPackage_HHD_vendorSpecificDevice_2Present u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure vendorSpecificDevice_1Present in AQ_GlobalStandardVendorDevicesInPackage_HHD */ -#define AQ_GlobalStandardVendorDevicesInPackage_HHD_vendorSpecificDevice_1Present 0 -/*! \brief Preprocessor variable to relate field to bit position in structure vendorSpecificDevice_1Present in AQ_GlobalStandardVendorDevicesInPackage_HHD */ -#define bits_AQ_GlobalStandardVendorDevicesInPackage_HHD_vendorSpecificDevice_1Present u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure vendorSpecificDevice_1Present in AQ_GlobalStandardVendorDevicesInPackage_HHD */ -#define word_AQ_GlobalStandardVendorDevicesInPackage_HHD_vendorSpecificDevice_1Present u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure clause_22ExtensionPresent in AQ_GlobalStandardVendorDevicesInPackage_HHD */ -#define AQ_GlobalStandardVendorDevicesInPackage_HHD_clause_22ExtensionPresent 0 -/*! \brief Preprocessor variable to relate field to bit position in structure clause_22ExtensionPresent in AQ_GlobalStandardVendorDevicesInPackage_HHD */ -#define bits_AQ_GlobalStandardVendorDevicesInPackage_HHD_clause_22ExtensionPresent u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure clause_22ExtensionPresent in AQ_GlobalStandardVendorDevicesInPackage_HHD */ -#define word_AQ_GlobalStandardVendorDevicesInPackage_HHD_clause_22ExtensionPresent u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalStandardStatus_2_HHD */ -#define AQ_GlobalStandardStatus_2_HHD_baseRegisterAddress 0x0008 -/*! \brief MMD address of structure AQ_GlobalStandardStatus_2_HHD */ -#define AQ_GlobalStandardStatus_2_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure devicePresent in AQ_GlobalStandardStatus_2_HHD */ -#define AQ_GlobalStandardStatus_2_HHD_devicePresent 0 -/*! \brief Preprocessor variable to relate field to bit position in structure devicePresent in AQ_GlobalStandardStatus_2_HHD */ -#define bits_AQ_GlobalStandardStatus_2_HHD_devicePresent u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure devicePresent in AQ_GlobalStandardStatus_2_HHD */ -#define word_AQ_GlobalStandardStatus_2_HHD_devicePresent u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalStandardPackageIdentifier_HHD */ -#define AQ_GlobalStandardPackageIdentifier_HHD_baseRegisterAddress 0x000E -/*! \brief MMD address of structure AQ_GlobalStandardPackageIdentifier_HHD */ -#define AQ_GlobalStandardPackageIdentifier_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure packageIdMSW in AQ_GlobalStandardPackageIdentifier_HHD */ -#define AQ_GlobalStandardPackageIdentifier_HHD_packageIdMSW 0 -/*! \brief Preprocessor variable to relate field to bit position in structure packageIdMSW in AQ_GlobalStandardPackageIdentifier_HHD */ -#define bits_AQ_GlobalStandardPackageIdentifier_HHD_packageIdMSW u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure packageIdMSW in AQ_GlobalStandardPackageIdentifier_HHD */ -#define word_AQ_GlobalStandardPackageIdentifier_HHD_packageIdMSW u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure packageIdLSW in AQ_GlobalStandardPackageIdentifier_HHD */ -#define AQ_GlobalStandardPackageIdentifier_HHD_packageIdLSW 1 -/*! \brief Preprocessor variable to relate field to bit position in structure packageIdLSW in AQ_GlobalStandardPackageIdentifier_HHD */ -#define bits_AQ_GlobalStandardPackageIdentifier_HHD_packageIdLSW u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure packageIdLSW in AQ_GlobalStandardPackageIdentifier_HHD */ -#define word_AQ_GlobalStandardPackageIdentifier_HHD_packageIdLSW u1.word_1 - -/*! \brief Base register address of structure AQ_GlobalFirmwareID_HHD */ -#define AQ_GlobalFirmwareID_HHD_baseRegisterAddress 0x0020 -/*! \brief MMD address of structure AQ_GlobalFirmwareID_HHD */ -#define AQ_GlobalFirmwareID_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure firmwareMajorRevisionNumber in AQ_GlobalFirmwareID_HHD */ -#define AQ_GlobalFirmwareID_HHD_firmwareMajorRevisionNumber 0 -/*! \brief Preprocessor variable to relate field to bit position in structure firmwareMajorRevisionNumber in AQ_GlobalFirmwareID_HHD */ -#define bits_AQ_GlobalFirmwareID_HHD_firmwareMajorRevisionNumber u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure firmwareMajorRevisionNumber in AQ_GlobalFirmwareID_HHD */ -#define word_AQ_GlobalFirmwareID_HHD_firmwareMajorRevisionNumber u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure firmwareMinorRevisionNumber in AQ_GlobalFirmwareID_HHD */ -#define AQ_GlobalFirmwareID_HHD_firmwareMinorRevisionNumber 0 -/*! \brief Preprocessor variable to relate field to bit position in structure firmwareMinorRevisionNumber in AQ_GlobalFirmwareID_HHD */ -#define bits_AQ_GlobalFirmwareID_HHD_firmwareMinorRevisionNumber u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure firmwareMinorRevisionNumber in AQ_GlobalFirmwareID_HHD */ -#define word_AQ_GlobalFirmwareID_HHD_firmwareMinorRevisionNumber u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalNvrInterface_HHD */ -#define AQ_GlobalNvrInterface_HHD_baseRegisterAddress 0x0100 -/*! \brief MMD address of structure AQ_GlobalNvrInterface_HHD */ -#define AQ_GlobalNvrInterface_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure nvrExecuteOperation in AQ_GlobalNvrInterface_HHD */ -#define AQ_GlobalNvrInterface_HHD_nvrExecuteOperation 0 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrExecuteOperation in AQ_GlobalNvrInterface_HHD */ -#define bits_AQ_GlobalNvrInterface_HHD_nvrExecuteOperation u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure nvrExecuteOperation in AQ_GlobalNvrInterface_HHD */ -#define word_AQ_GlobalNvrInterface_HHD_nvrExecuteOperation u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure nvrWriteMode in AQ_GlobalNvrInterface_HHD */ -#define AQ_GlobalNvrInterface_HHD_nvrWriteMode 0 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrWriteMode in AQ_GlobalNvrInterface_HHD */ -#define bits_AQ_GlobalNvrInterface_HHD_nvrWriteMode u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure nvrWriteMode in AQ_GlobalNvrInterface_HHD */ -#define word_AQ_GlobalNvrInterface_HHD_nvrWriteMode u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure freezeNvrCrc in AQ_GlobalNvrInterface_HHD */ -#define AQ_GlobalNvrInterface_HHD_freezeNvrCrc 0 -/*! \brief Preprocessor variable to relate field to bit position in structure freezeNvrCrc in AQ_GlobalNvrInterface_HHD */ -#define bits_AQ_GlobalNvrInterface_HHD_freezeNvrCrc u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure freezeNvrCrc in AQ_GlobalNvrInterface_HHD */ -#define word_AQ_GlobalNvrInterface_HHD_freezeNvrCrc u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure resetNvrCrc in AQ_GlobalNvrInterface_HHD */ -#define AQ_GlobalNvrInterface_HHD_resetNvrCrc 0 -/*! \brief Preprocessor variable to relate field to bit position in structure resetNvrCrc in AQ_GlobalNvrInterface_HHD */ -#define bits_AQ_GlobalNvrInterface_HHD_resetNvrCrc u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure resetNvrCrc in AQ_GlobalNvrInterface_HHD */ -#define word_AQ_GlobalNvrInterface_HHD_resetNvrCrc u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure nvrBurst in AQ_GlobalNvrInterface_HHD */ -#define AQ_GlobalNvrInterface_HHD_nvrBurst 0 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrBurst in AQ_GlobalNvrInterface_HHD */ -#define bits_AQ_GlobalNvrInterface_HHD_nvrBurst u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure nvrBurst in AQ_GlobalNvrInterface_HHD */ -#define word_AQ_GlobalNvrInterface_HHD_nvrBurst u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure nvrBusy in AQ_GlobalNvrInterface_HHD */ -#define AQ_GlobalNvrInterface_HHD_nvrBusy 0 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrBusy in AQ_GlobalNvrInterface_HHD */ -#define bits_AQ_GlobalNvrInterface_HHD_nvrBusy u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure nvrBusy in AQ_GlobalNvrInterface_HHD */ -#define word_AQ_GlobalNvrInterface_HHD_nvrBusy u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure nvrOpcode in AQ_GlobalNvrInterface_HHD */ -#define AQ_GlobalNvrInterface_HHD_nvrOpcode 0 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrOpcode in AQ_GlobalNvrInterface_HHD */ -#define bits_AQ_GlobalNvrInterface_HHD_nvrOpcode u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure nvrOpcode in AQ_GlobalNvrInterface_HHD */ -#define word_AQ_GlobalNvrInterface_HHD_nvrOpcode u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure nvrMailboxCrc in AQ_GlobalNvrInterface_HHD */ -#define AQ_GlobalNvrInterface_HHD_nvrMailboxCrc 1 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrMailboxCrc in AQ_GlobalNvrInterface_HHD */ -#define bits_AQ_GlobalNvrInterface_HHD_nvrMailboxCrc u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure nvrMailboxCrc in AQ_GlobalNvrInterface_HHD */ -#define word_AQ_GlobalNvrInterface_HHD_nvrMailboxCrc u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure nvrAddressMSW in AQ_GlobalNvrInterface_HHD */ -#define AQ_GlobalNvrInterface_HHD_nvrAddressMSW 2 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrAddressMSW in AQ_GlobalNvrInterface_HHD */ -#define bits_AQ_GlobalNvrInterface_HHD_nvrAddressMSW u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure nvrAddressMSW in AQ_GlobalNvrInterface_HHD */ -#define word_AQ_GlobalNvrInterface_HHD_nvrAddressMSW u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure nvrAddressLSW in AQ_GlobalNvrInterface_HHD */ -#define AQ_GlobalNvrInterface_HHD_nvrAddressLSW 3 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrAddressLSW in AQ_GlobalNvrInterface_HHD */ -#define bits_AQ_GlobalNvrInterface_HHD_nvrAddressLSW u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure nvrAddressLSW in AQ_GlobalNvrInterface_HHD */ -#define word_AQ_GlobalNvrInterface_HHD_nvrAddressLSW u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure nvrDataMSW in AQ_GlobalNvrInterface_HHD */ -#define AQ_GlobalNvrInterface_HHD_nvrDataMSW 4 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrDataMSW in AQ_GlobalNvrInterface_HHD */ -#define bits_AQ_GlobalNvrInterface_HHD_nvrDataMSW u4.bits_4 -/*! \brief Preprocessor variable to relate field to word position in structure nvrDataMSW in AQ_GlobalNvrInterface_HHD */ -#define word_AQ_GlobalNvrInterface_HHD_nvrDataMSW u4.word_4 -/*! \brief Preprocessor variable to relate field to word number in structure nvrDataLSW in AQ_GlobalNvrInterface_HHD */ -#define AQ_GlobalNvrInterface_HHD_nvrDataLSW 5 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrDataLSW in AQ_GlobalNvrInterface_HHD */ -#define bits_AQ_GlobalNvrInterface_HHD_nvrDataLSW u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure nvrDataLSW in AQ_GlobalNvrInterface_HHD */ -#define word_AQ_GlobalNvrInterface_HHD_nvrDataLSW u5.word_5 - -/*! \brief Base register address of structure AQ_GlobalMailboxInterface_HHD */ -#define AQ_GlobalMailboxInterface_HHD_baseRegisterAddress 0x0200 -/*! \brief MMD address of structure AQ_GlobalMailboxInterface_HHD */ -#define AQ_GlobalMailboxInterface_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure upMailboxExecuteOperation in AQ_GlobalMailboxInterface_HHD */ -#define AQ_GlobalMailboxInterface_HHD_upMailboxExecuteOperation 0 -/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxExecuteOperation in AQ_GlobalMailboxInterface_HHD */ -#define bits_AQ_GlobalMailboxInterface_HHD_upMailboxExecuteOperation u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure upMailboxExecuteOperation in AQ_GlobalMailboxInterface_HHD */ -#define word_AQ_GlobalMailboxInterface_HHD_upMailboxExecuteOperation u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure upMailboxWriteMode in AQ_GlobalMailboxInterface_HHD */ -#define AQ_GlobalMailboxInterface_HHD_upMailboxWriteMode 0 -/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxWriteMode in AQ_GlobalMailboxInterface_HHD */ -#define bits_AQ_GlobalMailboxInterface_HHD_upMailboxWriteMode u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure upMailboxWriteMode in AQ_GlobalMailboxInterface_HHD */ -#define word_AQ_GlobalMailboxInterface_HHD_upMailboxWriteMode u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure resetUpMailboxCrc in AQ_GlobalMailboxInterface_HHD */ -#define AQ_GlobalMailboxInterface_HHD_resetUpMailboxCrc 0 -/*! \brief Preprocessor variable to relate field to bit position in structure resetUpMailboxCrc in AQ_GlobalMailboxInterface_HHD */ -#define bits_AQ_GlobalMailboxInterface_HHD_resetUpMailboxCrc u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure resetUpMailboxCrc in AQ_GlobalMailboxInterface_HHD */ -#define word_AQ_GlobalMailboxInterface_HHD_resetUpMailboxCrc u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure upMailboxBusy in AQ_GlobalMailboxInterface_HHD */ -#define AQ_GlobalMailboxInterface_HHD_upMailboxBusy 0 -/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxBusy in AQ_GlobalMailboxInterface_HHD */ -#define bits_AQ_GlobalMailboxInterface_HHD_upMailboxBusy u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure upMailboxBusy in AQ_GlobalMailboxInterface_HHD */ -#define word_AQ_GlobalMailboxInterface_HHD_upMailboxBusy u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure upMailboxCrc in AQ_GlobalMailboxInterface_HHD */ -#define AQ_GlobalMailboxInterface_HHD_upMailboxCrc 1 -/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxCrc in AQ_GlobalMailboxInterface_HHD */ -#define bits_AQ_GlobalMailboxInterface_HHD_upMailboxCrc u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure upMailboxCrc in AQ_GlobalMailboxInterface_HHD */ -#define word_AQ_GlobalMailboxInterface_HHD_upMailboxCrc u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure upMailboxAddressMSW in AQ_GlobalMailboxInterface_HHD */ -#define AQ_GlobalMailboxInterface_HHD_upMailboxAddressMSW 2 -/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxAddressMSW in AQ_GlobalMailboxInterface_HHD */ -#define bits_AQ_GlobalMailboxInterface_HHD_upMailboxAddressMSW u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure upMailboxAddressMSW in AQ_GlobalMailboxInterface_HHD */ -#define word_AQ_GlobalMailboxInterface_HHD_upMailboxAddressMSW u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure upMailboxAddressLSW in AQ_GlobalMailboxInterface_HHD */ -#define AQ_GlobalMailboxInterface_HHD_upMailboxAddressLSW 3 -/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxAddressLSW in AQ_GlobalMailboxInterface_HHD */ -#define bits_AQ_GlobalMailboxInterface_HHD_upMailboxAddressLSW u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure upMailboxAddressLSW in AQ_GlobalMailboxInterface_HHD */ -#define word_AQ_GlobalMailboxInterface_HHD_upMailboxAddressLSW u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure upMailboxAddressLSW_Don_tCare in AQ_GlobalMailboxInterface_HHD */ -#define AQ_GlobalMailboxInterface_HHD_upMailboxAddressLSW_Don_tCare 3 -/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxAddressLSW_Don_tCare in AQ_GlobalMailboxInterface_HHD */ -#define bits_AQ_GlobalMailboxInterface_HHD_upMailboxAddressLSW_Don_tCare u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure upMailboxAddressLSW_Don_tCare in AQ_GlobalMailboxInterface_HHD */ -#define word_AQ_GlobalMailboxInterface_HHD_upMailboxAddressLSW_Don_tCare u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure upMailboxDataMSW in AQ_GlobalMailboxInterface_HHD */ -#define AQ_GlobalMailboxInterface_HHD_upMailboxDataMSW 4 -/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxDataMSW in AQ_GlobalMailboxInterface_HHD */ -#define bits_AQ_GlobalMailboxInterface_HHD_upMailboxDataMSW u4.bits_4 -/*! \brief Preprocessor variable to relate field to word position in structure upMailboxDataMSW in AQ_GlobalMailboxInterface_HHD */ -#define word_AQ_GlobalMailboxInterface_HHD_upMailboxDataMSW u4.word_4 -/*! \brief Preprocessor variable to relate field to word number in structure upMailboxDataLSW in AQ_GlobalMailboxInterface_HHD */ -#define AQ_GlobalMailboxInterface_HHD_upMailboxDataLSW 5 -/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxDataLSW in AQ_GlobalMailboxInterface_HHD */ -#define bits_AQ_GlobalMailboxInterface_HHD_upMailboxDataLSW u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure upMailboxDataLSW in AQ_GlobalMailboxInterface_HHD */ -#define word_AQ_GlobalMailboxInterface_HHD_upMailboxDataLSW u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure upMailboxCrcReadEnable in AQ_GlobalMailboxInterface_HHD */ -#define AQ_GlobalMailboxInterface_HHD_upMailboxCrcReadEnable 6 -/*! \brief Preprocessor variable to relate field to bit position in structure upMailboxCrcReadEnable in AQ_GlobalMailboxInterface_HHD */ -#define bits_AQ_GlobalMailboxInterface_HHD_upMailboxCrcReadEnable u6.bits_6 -/*! \brief Preprocessor variable to relate field to word position in structure upMailboxCrcReadEnable in AQ_GlobalMailboxInterface_HHD */ -#define word_AQ_GlobalMailboxInterface_HHD_upMailboxCrcReadEnable u6.word_6 - -/*! \brief Base register address of structure AQ_GlobalMicroprocessorScratchPad_HHD */ -#define AQ_GlobalMicroprocessorScratchPad_HHD_baseRegisterAddress 0x0300 -/*! \brief MMD address of structure AQ_GlobalMicroprocessorScratchPad_HHD */ -#define AQ_GlobalMicroprocessorScratchPad_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure scratchPad_1 in AQ_GlobalMicroprocessorScratchPad_HHD */ -#define AQ_GlobalMicroprocessorScratchPad_HHD_scratchPad_1 0 -/*! \brief Preprocessor variable to relate field to bit position in structure scratchPad_1 in AQ_GlobalMicroprocessorScratchPad_HHD */ -#define bits_AQ_GlobalMicroprocessorScratchPad_HHD_scratchPad_1 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure scratchPad_1 in AQ_GlobalMicroprocessorScratchPad_HHD */ -#define word_AQ_GlobalMicroprocessorScratchPad_HHD_scratchPad_1 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure scratchPad_2 in AQ_GlobalMicroprocessorScratchPad_HHD */ -#define AQ_GlobalMicroprocessorScratchPad_HHD_scratchPad_2 1 -/*! \brief Preprocessor variable to relate field to bit position in structure scratchPad_2 in AQ_GlobalMicroprocessorScratchPad_HHD */ -#define bits_AQ_GlobalMicroprocessorScratchPad_HHD_scratchPad_2 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure scratchPad_2 in AQ_GlobalMicroprocessorScratchPad_HHD */ -#define word_AQ_GlobalMicroprocessorScratchPad_HHD_scratchPad_2 u1.word_1 - -/*! \brief Base register address of structure AQ_MssEgressControlRegister_HHD */ -#define AQ_MssEgressControlRegister_HHD_baseRegisterAddress 0x5002 -/*! \brief MMD address of structure AQ_MssEgressControlRegister_HHD */ -#define AQ_MssEgressControlRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressEthertypeExplicitSectagLsb in AQ_MssEgressControlRegister_HHD */ -#define AQ_MssEgressControlRegister_HHD_mssEgressEthertypeExplicitSectagLsb 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressEthertypeExplicitSectagLsb in AQ_MssEgressControlRegister_HHD */ -#define bits_AQ_MssEgressControlRegister_HHD_mssEgressEthertypeExplicitSectagLsb u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressEthertypeExplicitSectagLsb in AQ_MssEgressControlRegister_HHD */ -#define word_AQ_MssEgressControlRegister_HHD_mssEgressEthertypeExplicitSectagLsb u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressClearGlobalTime in AQ_MssEgressControlRegister_HHD */ -#define AQ_MssEgressControlRegister_HHD_mssEgressClearGlobalTime 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressClearGlobalTime in AQ_MssEgressControlRegister_HHD */ -#define bits_AQ_MssEgressControlRegister_HHD_mssEgressClearGlobalTime u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressClearGlobalTime in AQ_MssEgressControlRegister_HHD */ -#define word_AQ_MssEgressControlRegister_HHD_mssEgressClearGlobalTime u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressClearCounter in AQ_MssEgressControlRegister_HHD */ -#define AQ_MssEgressControlRegister_HHD_mssEgressClearCounter 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressClearCounter in AQ_MssEgressControlRegister_HHD */ -#define bits_AQ_MssEgressControlRegister_HHD_mssEgressClearCounter u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressClearCounter in AQ_MssEgressControlRegister_HHD */ -#define word_AQ_MssEgressControlRegister_HHD_mssEgressClearCounter u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressHighPriority in AQ_MssEgressControlRegister_HHD */ -#define AQ_MssEgressControlRegister_HHD_mssEgressHighPriority 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressHighPriority in AQ_MssEgressControlRegister_HHD */ -#define bits_AQ_MssEgressControlRegister_HHD_mssEgressHighPriority u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressHighPriority in AQ_MssEgressControlRegister_HHD */ -#define word_AQ_MssEgressControlRegister_HHD_mssEgressHighPriority u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressIcvLsb_8BytesEnable in AQ_MssEgressControlRegister_HHD */ -#define AQ_MssEgressControlRegister_HHD_mssEgressIcvLsb_8BytesEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressIcvLsb_8BytesEnable in AQ_MssEgressControlRegister_HHD */ -#define bits_AQ_MssEgressControlRegister_HHD_mssEgressIcvLsb_8BytesEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressIcvLsb_8BytesEnable in AQ_MssEgressControlRegister_HHD */ -#define word_AQ_MssEgressControlRegister_HHD_mssEgressIcvLsb_8BytesEnable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressExternalClassificationEnable in AQ_MssEgressControlRegister_HHD */ -#define AQ_MssEgressControlRegister_HHD_mssEgressExternalClassificationEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressExternalClassificationEnable in AQ_MssEgressControlRegister_HHD */ -#define bits_AQ_MssEgressControlRegister_HHD_mssEgressExternalClassificationEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressExternalClassificationEnable in AQ_MssEgressControlRegister_HHD */ -#define word_AQ_MssEgressControlRegister_HHD_mssEgressExternalClassificationEnable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressExplicitSectagReportShortLength in AQ_MssEgressControlRegister_HHD */ -#define AQ_MssEgressControlRegister_HHD_mssEgressExplicitSectagReportShortLength 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressExplicitSectagReportShortLength in AQ_MssEgressControlRegister_HHD */ -#define bits_AQ_MssEgressControlRegister_HHD_mssEgressExplicitSectagReportShortLength u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressExplicitSectagReportShortLength in AQ_MssEgressControlRegister_HHD */ -#define word_AQ_MssEgressControlRegister_HHD_mssEgressExplicitSectagReportShortLength u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressDropInvalidSa_scPackets in AQ_MssEgressControlRegister_HHD */ -#define AQ_MssEgressControlRegister_HHD_mssEgressDropInvalidSa_scPackets 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressDropInvalidSa_scPackets in AQ_MssEgressControlRegister_HHD */ -#define bits_AQ_MssEgressControlRegister_HHD_mssEgressDropInvalidSa_scPackets u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressDropInvalidSa_scPackets in AQ_MssEgressControlRegister_HHD */ -#define word_AQ_MssEgressControlRegister_HHD_mssEgressDropInvalidSa_scPackets u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressUnmatchedUseSc_0 in AQ_MssEgressControlRegister_HHD */ -#define AQ_MssEgressControlRegister_HHD_mssEgressUnmatchedUseSc_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressUnmatchedUseSc_0 in AQ_MssEgressControlRegister_HHD */ -#define bits_AQ_MssEgressControlRegister_HHD_mssEgressUnmatchedUseSc_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressUnmatchedUseSc_0 in AQ_MssEgressControlRegister_HHD */ -#define word_AQ_MssEgressControlRegister_HHD_mssEgressUnmatchedUseSc_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgresssGcmTestMode in AQ_MssEgressControlRegister_HHD */ -#define AQ_MssEgressControlRegister_HHD_mssEgresssGcmTestMode 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgresssGcmTestMode in AQ_MssEgressControlRegister_HHD */ -#define bits_AQ_MssEgressControlRegister_HHD_mssEgresssGcmTestMode u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgresssGcmTestMode in AQ_MssEgressControlRegister_HHD */ -#define word_AQ_MssEgressControlRegister_HHD_mssEgresssGcmTestMode u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressGcmStart in AQ_MssEgressControlRegister_HHD */ -#define AQ_MssEgressControlRegister_HHD_mssEgressGcmStart 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressGcmStart in AQ_MssEgressControlRegister_HHD */ -#define bits_AQ_MssEgressControlRegister_HHD_mssEgressGcmStart u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressGcmStart in AQ_MssEgressControlRegister_HHD */ -#define word_AQ_MssEgressControlRegister_HHD_mssEgressGcmStart u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressDropEgprcLutMiss in AQ_MssEgressControlRegister_HHD */ -#define AQ_MssEgressControlRegister_HHD_mssEgressDropEgprcLutMiss 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressDropEgprcLutMiss in AQ_MssEgressControlRegister_HHD */ -#define bits_AQ_MssEgressControlRegister_HHD_mssEgressDropEgprcLutMiss u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressDropEgprcLutMiss in AQ_MssEgressControlRegister_HHD */ -#define word_AQ_MssEgressControlRegister_HHD_mssEgressDropEgprcLutMiss u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressDropKayPacket in AQ_MssEgressControlRegister_HHD */ -#define AQ_MssEgressControlRegister_HHD_mssEgressDropKayPacket 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressDropKayPacket in AQ_MssEgressControlRegister_HHD */ -#define bits_AQ_MssEgressControlRegister_HHD_mssEgressDropKayPacket u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressDropKayPacket in AQ_MssEgressControlRegister_HHD */ -#define word_AQ_MssEgressControlRegister_HHD_mssEgressDropKayPacket u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSoftReset in AQ_MssEgressControlRegister_HHD */ -#define AQ_MssEgressControlRegister_HHD_mssEgressSoftReset 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSoftReset in AQ_MssEgressControlRegister_HHD */ -#define bits_AQ_MssEgressControlRegister_HHD_mssEgressSoftReset u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSoftReset in AQ_MssEgressControlRegister_HHD */ -#define word_AQ_MssEgressControlRegister_HHD_mssEgressSoftReset u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressEthertypeExplicitSectagMsb in AQ_MssEgressControlRegister_HHD */ -#define AQ_MssEgressControlRegister_HHD_mssEgressEthertypeExplicitSectagMsb 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressEthertypeExplicitSectagMsb in AQ_MssEgressControlRegister_HHD */ -#define bits_AQ_MssEgressControlRegister_HHD_mssEgressEthertypeExplicitSectagMsb u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressEthertypeExplicitSectagMsb in AQ_MssEgressControlRegister_HHD */ -#define word_AQ_MssEgressControlRegister_HHD_mssEgressEthertypeExplicitSectagMsb u1.word_1 - -/*! \brief Base register address of structure AQ_MssEgressVlanTpid_0Register_HHD */ -#define AQ_MssEgressVlanTpid_0Register_HHD_baseRegisterAddress 0x5008 -/*! \brief MMD address of structure AQ_MssEgressVlanTpid_0Register_HHD */ -#define AQ_MssEgressVlanTpid_0Register_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressVlanStagTpid in AQ_MssEgressVlanTpid_0Register_HHD */ -#define AQ_MssEgressVlanTpid_0Register_HHD_mssEgressVlanStagTpid 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressVlanStagTpid in AQ_MssEgressVlanTpid_0Register_HHD */ -#define bits_AQ_MssEgressVlanTpid_0Register_HHD_mssEgressVlanStagTpid u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressVlanStagTpid in AQ_MssEgressVlanTpid_0Register_HHD */ -#define word_AQ_MssEgressVlanTpid_0Register_HHD_mssEgressVlanStagTpid u0.word_0 - -/*! \brief Base register address of structure AQ_MssEgressVlanTpid_1Register_HHD */ -#define AQ_MssEgressVlanTpid_1Register_HHD_baseRegisterAddress 0x500A -/*! \brief MMD address of structure AQ_MssEgressVlanTpid_1Register_HHD */ -#define AQ_MssEgressVlanTpid_1Register_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressVlanQtagTpid in AQ_MssEgressVlanTpid_1Register_HHD */ -#define AQ_MssEgressVlanTpid_1Register_HHD_mssEgressVlanQtagTpid 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressVlanQtagTpid in AQ_MssEgressVlanTpid_1Register_HHD */ -#define bits_AQ_MssEgressVlanTpid_1Register_HHD_mssEgressVlanQtagTpid u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressVlanQtagTpid in AQ_MssEgressVlanTpid_1Register_HHD */ -#define word_AQ_MssEgressVlanTpid_1Register_HHD_mssEgressVlanQtagTpid u0.word_0 - -/*! \brief Base register address of structure AQ_MssEgressVlanControlRegister_HHD */ -#define AQ_MssEgressVlanControlRegister_HHD_baseRegisterAddress 0x500C -/*! \brief MMD address of structure AQ_MssEgressVlanControlRegister_HHD */ -#define AQ_MssEgressVlanControlRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressVlanUpMapTable in AQ_MssEgressVlanControlRegister_HHD */ -#define AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanUpMapTable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressVlanUpMapTable in AQ_MssEgressVlanControlRegister_HHD */ -#define bits_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanUpMapTable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressVlanUpMapTable in AQ_MssEgressVlanControlRegister_HHD */ -#define word_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanUpMapTable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressVlanQtagParseEnable in AQ_MssEgressVlanControlRegister_HHD */ -#define AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanQtagParseEnable 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressVlanQtagParseEnable in AQ_MssEgressVlanControlRegister_HHD */ -#define bits_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanQtagParseEnable u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressVlanQtagParseEnable in AQ_MssEgressVlanControlRegister_HHD */ -#define word_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanQtagParseEnable u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressVlanStagParseEnable in AQ_MssEgressVlanControlRegister_HHD */ -#define AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanStagParseEnable 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressVlanStagParseEnable in AQ_MssEgressVlanControlRegister_HHD */ -#define bits_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanStagParseEnable u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressVlanStagParseEnable in AQ_MssEgressVlanControlRegister_HHD */ -#define word_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanStagParseEnable u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressVlanQinqParseEnable in AQ_MssEgressVlanControlRegister_HHD */ -#define AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanQinqParseEnable 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressVlanQinqParseEnable in AQ_MssEgressVlanControlRegister_HHD */ -#define bits_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanQinqParseEnable u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressVlanQinqParseEnable in AQ_MssEgressVlanControlRegister_HHD */ -#define word_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanQinqParseEnable u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressVlanQtagUpParseEnable in AQ_MssEgressVlanControlRegister_HHD */ -#define AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanQtagUpParseEnable 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressVlanQtagUpParseEnable in AQ_MssEgressVlanControlRegister_HHD */ -#define bits_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanQtagUpParseEnable u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressVlanQtagUpParseEnable in AQ_MssEgressVlanControlRegister_HHD */ -#define word_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanQtagUpParseEnable u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressVlanStagUpParseEnable in AQ_MssEgressVlanControlRegister_HHD */ -#define AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanStagUpParseEnable 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressVlanStagUpParseEnable in AQ_MssEgressVlanControlRegister_HHD */ -#define bits_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanStagUpParseEnable u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressVlanStagUpParseEnable in AQ_MssEgressVlanControlRegister_HHD */ -#define word_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanStagUpParseEnable u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressVlanUpDefault in AQ_MssEgressVlanControlRegister_HHD */ -#define AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanUpDefault 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressVlanUpDefault in AQ_MssEgressVlanControlRegister_HHD */ -#define bits_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanUpDefault u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressVlanUpDefault in AQ_MssEgressVlanControlRegister_HHD */ -#define word_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanUpDefault u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressVlanUpMapTableMSW in AQ_MssEgressVlanControlRegister_HHD */ -#define AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanUpMapTableMSW 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressVlanUpMapTableMSW in AQ_MssEgressVlanControlRegister_HHD */ -#define bits_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanUpMapTableMSW u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressVlanUpMapTableMSW in AQ_MssEgressVlanControlRegister_HHD */ -#define word_AQ_MssEgressVlanControlRegister_HHD_mssEgressVlanUpMapTableMSW u1.word_1 - -/*! \brief Base register address of structure AQ_MssEgressPnControlRegister_HHD */ -#define AQ_MssEgressPnControlRegister_HHD_baseRegisterAddress 0x500E -/*! \brief MMD address of structure AQ_MssEgressPnControlRegister_HHD */ -#define AQ_MssEgressPnControlRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaPnThresholdLSW in AQ_MssEgressPnControlRegister_HHD */ -#define AQ_MssEgressPnControlRegister_HHD_mssEgressSaPnThresholdLSW 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaPnThresholdLSW in AQ_MssEgressPnControlRegister_HHD */ -#define bits_AQ_MssEgressPnControlRegister_HHD_mssEgressSaPnThresholdLSW u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaPnThresholdLSW in AQ_MssEgressPnControlRegister_HHD */ -#define word_AQ_MssEgressPnControlRegister_HHD_mssEgressSaPnThresholdLSW u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaPnThresholdMSW in AQ_MssEgressPnControlRegister_HHD */ -#define AQ_MssEgressPnControlRegister_HHD_mssEgressSaPnThresholdMSW 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaPnThresholdMSW in AQ_MssEgressPnControlRegister_HHD */ -#define bits_AQ_MssEgressPnControlRegister_HHD_mssEgressSaPnThresholdMSW u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaPnThresholdMSW in AQ_MssEgressPnControlRegister_HHD */ -#define word_AQ_MssEgressPnControlRegister_HHD_mssEgressSaPnThresholdMSW u1.word_1 - -/*! \brief Base register address of structure AQ_MssEgressMtuSizeControlRegister_HHD */ -#define AQ_MssEgressMtuSizeControlRegister_HHD_baseRegisterAddress 0x5010 -/*! \brief MMD address of structure AQ_MssEgressMtuSizeControlRegister_HHD */ -#define AQ_MssEgressMtuSizeControlRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressControlledPacketMtuSize in AQ_MssEgressMtuSizeControlRegister_HHD */ -#define AQ_MssEgressMtuSizeControlRegister_HHD_mssEgressControlledPacketMtuSize 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressControlledPacketMtuSize in AQ_MssEgressMtuSizeControlRegister_HHD */ -#define bits_AQ_MssEgressMtuSizeControlRegister_HHD_mssEgressControlledPacketMtuSize u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressControlledPacketMtuSize in AQ_MssEgressMtuSizeControlRegister_HHD */ -#define word_AQ_MssEgressMtuSizeControlRegister_HHD_mssEgressControlledPacketMtuSize u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressUncontrolledPacketMtuSize in AQ_MssEgressMtuSizeControlRegister_HHD */ -#define AQ_MssEgressMtuSizeControlRegister_HHD_mssEgressUncontrolledPacketMtuSize 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressUncontrolledPacketMtuSize in AQ_MssEgressMtuSizeControlRegister_HHD */ -#define bits_AQ_MssEgressMtuSizeControlRegister_HHD_mssEgressUncontrolledPacketMtuSize u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressUncontrolledPacketMtuSize in AQ_MssEgressMtuSizeControlRegister_HHD */ -#define word_AQ_MssEgressMtuSizeControlRegister_HHD_mssEgressUncontrolledPacketMtuSize u1.word_1 - -/*! \brief Base register address of structure AQ_MssEgressInterruptStatusRegister_HHD */ -#define AQ_MssEgressInterruptStatusRegister_HHD_baseRegisterAddress 0x505C -/*! \brief MMD address of structure AQ_MssEgressInterruptStatusRegister_HHD */ -#define AQ_MssEgressInterruptStatusRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressEccErrorInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ -#define AQ_MssEgressInterruptStatusRegister_HHD_mssEgressEccErrorInterrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressEccErrorInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ -#define bits_AQ_MssEgressInterruptStatusRegister_HHD_mssEgressEccErrorInterrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressEccErrorInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ -#define word_AQ_MssEgressInterruptStatusRegister_HHD_mssEgressEccErrorInterrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressMibSaturationInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ -#define AQ_MssEgressInterruptStatusRegister_HHD_mssEgressMibSaturationInterrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressMibSaturationInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ -#define bits_AQ_MssEgressInterruptStatusRegister_HHD_mssEgressMibSaturationInterrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressMibSaturationInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ -#define word_AQ_MssEgressInterruptStatusRegister_HHD_mssEgressMibSaturationInterrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaThresholdExpiredInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ -#define AQ_MssEgressInterruptStatusRegister_HHD_mssEgressSaThresholdExpiredInterrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaThresholdExpiredInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ -#define bits_AQ_MssEgressInterruptStatusRegister_HHD_mssEgressSaThresholdExpiredInterrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaThresholdExpiredInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ -#define word_AQ_MssEgressInterruptStatusRegister_HHD_mssEgressSaThresholdExpiredInterrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaExpiredInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ -#define AQ_MssEgressInterruptStatusRegister_HHD_mssEgressSaExpiredInterrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaExpiredInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ -#define bits_AQ_MssEgressInterruptStatusRegister_HHD_mssEgressSaExpiredInterrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaExpiredInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ -#define word_AQ_MssEgressInterruptStatusRegister_HHD_mssEgressSaExpiredInterrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressMasterInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ -#define AQ_MssEgressInterruptStatusRegister_HHD_mssEgressMasterInterrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressMasterInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ -#define bits_AQ_MssEgressInterruptStatusRegister_HHD_mssEgressMasterInterrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressMasterInterrupt in AQ_MssEgressInterruptStatusRegister_HHD */ -#define word_AQ_MssEgressInterruptStatusRegister_HHD_mssEgressMasterInterrupt u0.word_0 - -/*! \brief Base register address of structure AQ_MssEgressInterruptMaskRegister_HHD */ -#define AQ_MssEgressInterruptMaskRegister_HHD_baseRegisterAddress 0x505E -/*! \brief MMD address of structure AQ_MssEgressInterruptMaskRegister_HHD */ -#define AQ_MssEgressInterruptMaskRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressEccErrorInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ -#define AQ_MssEgressInterruptMaskRegister_HHD_mssEgressEccErrorInterruptEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressEccErrorInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ -#define bits_AQ_MssEgressInterruptMaskRegister_HHD_mssEgressEccErrorInterruptEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressEccErrorInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ -#define word_AQ_MssEgressInterruptMaskRegister_HHD_mssEgressEccErrorInterruptEnable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressMibSaturationInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ -#define AQ_MssEgressInterruptMaskRegister_HHD_mssEgressMibSaturationInterruptEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressMibSaturationInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ -#define bits_AQ_MssEgressInterruptMaskRegister_HHD_mssEgressMibSaturationInterruptEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressMibSaturationInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ -#define word_AQ_MssEgressInterruptMaskRegister_HHD_mssEgressMibSaturationInterruptEnable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaExpiredThresholdInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ -#define AQ_MssEgressInterruptMaskRegister_HHD_mssEgressSaExpiredThresholdInterruptEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaExpiredThresholdInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ -#define bits_AQ_MssEgressInterruptMaskRegister_HHD_mssEgressSaExpiredThresholdInterruptEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaExpiredThresholdInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ -#define word_AQ_MssEgressInterruptMaskRegister_HHD_mssEgressSaExpiredThresholdInterruptEnable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaExpiredInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ -#define AQ_MssEgressInterruptMaskRegister_HHD_mssEgressSaExpiredInterruptEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaExpiredInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ -#define bits_AQ_MssEgressInterruptMaskRegister_HHD_mssEgressSaExpiredInterruptEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaExpiredInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ -#define word_AQ_MssEgressInterruptMaskRegister_HHD_mssEgressSaExpiredInterruptEnable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressMasterInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ -#define AQ_MssEgressInterruptMaskRegister_HHD_mssEgressMasterInterruptEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressMasterInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ -#define bits_AQ_MssEgressInterruptMaskRegister_HHD_mssEgressMasterInterruptEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressMasterInterruptEnable in AQ_MssEgressInterruptMaskRegister_HHD */ -#define word_AQ_MssEgressInterruptMaskRegister_HHD_mssEgressMasterInterruptEnable u0.word_0 - -/*! \brief Base register address of structure AQ_MssEgressSaExpiredStatusRegister_HHD */ -#define AQ_MssEgressSaExpiredStatusRegister_HHD_baseRegisterAddress 0x5060 -/*! \brief MMD address of structure AQ_MssEgressSaExpiredStatusRegister_HHD */ -#define AQ_MssEgressSaExpiredStatusRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaExpiredLSW in AQ_MssEgressSaExpiredStatusRegister_HHD */ -#define AQ_MssEgressSaExpiredStatusRegister_HHD_mssEgressSaExpiredLSW 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaExpiredLSW in AQ_MssEgressSaExpiredStatusRegister_HHD */ -#define bits_AQ_MssEgressSaExpiredStatusRegister_HHD_mssEgressSaExpiredLSW u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaExpiredLSW in AQ_MssEgressSaExpiredStatusRegister_HHD */ -#define word_AQ_MssEgressSaExpiredStatusRegister_HHD_mssEgressSaExpiredLSW u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaExpiredMSW in AQ_MssEgressSaExpiredStatusRegister_HHD */ -#define AQ_MssEgressSaExpiredStatusRegister_HHD_mssEgressSaExpiredMSW 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaExpiredMSW in AQ_MssEgressSaExpiredStatusRegister_HHD */ -#define bits_AQ_MssEgressSaExpiredStatusRegister_HHD_mssEgressSaExpiredMSW u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaExpiredMSW in AQ_MssEgressSaExpiredStatusRegister_HHD */ -#define word_AQ_MssEgressSaExpiredStatusRegister_HHD_mssEgressSaExpiredMSW u1.word_1 - -/*! \brief Base register address of structure AQ_MssEgressSaThresholdExpiredStatusRegister_HHD */ -#define AQ_MssEgressSaThresholdExpiredStatusRegister_HHD_baseRegisterAddress 0x5062 -/*! \brief MMD address of structure AQ_MssEgressSaThresholdExpiredStatusRegister_HHD */ -#define AQ_MssEgressSaThresholdExpiredStatusRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaThresholdExpiredLSW in AQ_MssEgressSaThresholdExpiredStatusRegister_HHD */ -#define AQ_MssEgressSaThresholdExpiredStatusRegister_HHD_mssEgressSaThresholdExpiredLSW 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaThresholdExpiredLSW in AQ_MssEgressSaThresholdExpiredStatusRegister_HHD */ -#define bits_AQ_MssEgressSaThresholdExpiredStatusRegister_HHD_mssEgressSaThresholdExpiredLSW u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaThresholdExpiredLSW in AQ_MssEgressSaThresholdExpiredStatusRegister_HHD */ -#define word_AQ_MssEgressSaThresholdExpiredStatusRegister_HHD_mssEgressSaThresholdExpiredLSW u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaThresholdExpiredMSW in AQ_MssEgressSaThresholdExpiredStatusRegister_HHD */ -#define AQ_MssEgressSaThresholdExpiredStatusRegister_HHD_mssEgressSaThresholdExpiredMSW 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaThresholdExpiredMSW in AQ_MssEgressSaThresholdExpiredStatusRegister_HHD */ -#define bits_AQ_MssEgressSaThresholdExpiredStatusRegister_HHD_mssEgressSaThresholdExpiredMSW u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaThresholdExpiredMSW in AQ_MssEgressSaThresholdExpiredStatusRegister_HHD */ -#define word_AQ_MssEgressSaThresholdExpiredStatusRegister_HHD_mssEgressSaThresholdExpiredMSW u1.word_1 - -/*! \brief Base register address of structure AQ_MssEgressEccInterruptStatusRegister_HHD */ -#define AQ_MssEgressEccInterruptStatusRegister_HHD_baseRegisterAddress 0x5064 -/*! \brief MMD address of structure AQ_MssEgressEccInterruptStatusRegister_HHD */ -#define AQ_MssEgressEccInterruptStatusRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaEccErrorInterruptLSW in AQ_MssEgressEccInterruptStatusRegister_HHD */ -#define AQ_MssEgressEccInterruptStatusRegister_HHD_mssEgressSaEccErrorInterruptLSW 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaEccErrorInterruptLSW in AQ_MssEgressEccInterruptStatusRegister_HHD */ -#define bits_AQ_MssEgressEccInterruptStatusRegister_HHD_mssEgressSaEccErrorInterruptLSW u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaEccErrorInterruptLSW in AQ_MssEgressEccInterruptStatusRegister_HHD */ -#define word_AQ_MssEgressEccInterruptStatusRegister_HHD_mssEgressSaEccErrorInterruptLSW u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressSaEccErrorInterruptMSW in AQ_MssEgressEccInterruptStatusRegister_HHD */ -#define AQ_MssEgressEccInterruptStatusRegister_HHD_mssEgressSaEccErrorInterruptMSW 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressSaEccErrorInterruptMSW in AQ_MssEgressEccInterruptStatusRegister_HHD */ -#define bits_AQ_MssEgressEccInterruptStatusRegister_HHD_mssEgressSaEccErrorInterruptMSW u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressSaEccErrorInterruptMSW in AQ_MssEgressEccInterruptStatusRegister_HHD */ -#define word_AQ_MssEgressEccInterruptStatusRegister_HHD_mssEgressSaEccErrorInterruptMSW u1.word_1 - -/*! \brief Base register address of structure AQ_MssEgressLutAddressControlRegister_HHD */ -#define AQ_MssEgressLutAddressControlRegister_HHD_baseRegisterAddress 0x5080 -/*! \brief MMD address of structure AQ_MssEgressLutAddressControlRegister_HHD */ -#define AQ_MssEgressLutAddressControlRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutSelect in AQ_MssEgressLutAddressControlRegister_HHD */ -#define AQ_MssEgressLutAddressControlRegister_HHD_mssEgressLutSelect 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutSelect in AQ_MssEgressLutAddressControlRegister_HHD */ -#define bits_AQ_MssEgressLutAddressControlRegister_HHD_mssEgressLutSelect u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutSelect in AQ_MssEgressLutAddressControlRegister_HHD */ -#define word_AQ_MssEgressLutAddressControlRegister_HHD_mssEgressLutSelect u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutAddress in AQ_MssEgressLutAddressControlRegister_HHD */ -#define AQ_MssEgressLutAddressControlRegister_HHD_mssEgressLutAddress 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutAddress in AQ_MssEgressLutAddressControlRegister_HHD */ -#define bits_AQ_MssEgressLutAddressControlRegister_HHD_mssEgressLutAddress u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutAddress in AQ_MssEgressLutAddressControlRegister_HHD */ -#define word_AQ_MssEgressLutAddressControlRegister_HHD_mssEgressLutAddress u0.word_0 - -/*! \brief Base register address of structure AQ_MssEgressLutControlRegister_HHD */ -#define AQ_MssEgressLutControlRegister_HHD_baseRegisterAddress 0x5081 -/*! \brief MMD address of structure AQ_MssEgressLutControlRegister_HHD */ -#define AQ_MssEgressLutControlRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutWrite in AQ_MssEgressLutControlRegister_HHD */ -#define AQ_MssEgressLutControlRegister_HHD_mssEgressLutWrite 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutWrite in AQ_MssEgressLutControlRegister_HHD */ -#define bits_AQ_MssEgressLutControlRegister_HHD_mssEgressLutWrite u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutWrite in AQ_MssEgressLutControlRegister_HHD */ -#define word_AQ_MssEgressLutControlRegister_HHD_mssEgressLutWrite u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutRead in AQ_MssEgressLutControlRegister_HHD */ -#define AQ_MssEgressLutControlRegister_HHD_mssEgressLutRead 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutRead in AQ_MssEgressLutControlRegister_HHD */ -#define bits_AQ_MssEgressLutControlRegister_HHD_mssEgressLutRead u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutRead in AQ_MssEgressLutControlRegister_HHD */ -#define word_AQ_MssEgressLutControlRegister_HHD_mssEgressLutRead u0.word_0 - -/*! \brief Base register address of structure AQ_MssEgressLutDataControlRegister_HHD */ -#define AQ_MssEgressLutDataControlRegister_HHD_baseRegisterAddress 0x50A0 -/*! \brief MMD address of structure AQ_MssEgressLutDataControlRegister_HHD */ -#define AQ_MssEgressLutDataControlRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_0 in AQ_MssEgressLutDataControlRegister_HHD */ -#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_0 in AQ_MssEgressLutDataControlRegister_HHD */ -#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_0 in AQ_MssEgressLutDataControlRegister_HHD */ -#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_1 in AQ_MssEgressLutDataControlRegister_HHD */ -#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_1 in AQ_MssEgressLutDataControlRegister_HHD */ -#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_1 in AQ_MssEgressLutDataControlRegister_HHD */ -#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_1 u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_2 in AQ_MssEgressLutDataControlRegister_HHD */ -#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_2 2 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_2 in AQ_MssEgressLutDataControlRegister_HHD */ -#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_2 u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_2 in AQ_MssEgressLutDataControlRegister_HHD */ -#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_2 u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_3 in AQ_MssEgressLutDataControlRegister_HHD */ -#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_3 3 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_3 in AQ_MssEgressLutDataControlRegister_HHD */ -#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_3 u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_3 in AQ_MssEgressLutDataControlRegister_HHD */ -#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_3 u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_4 in AQ_MssEgressLutDataControlRegister_HHD */ -#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_4 4 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_4 in AQ_MssEgressLutDataControlRegister_HHD */ -#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_4 u4.bits_4 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_4 in AQ_MssEgressLutDataControlRegister_HHD */ -#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_4 u4.word_4 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_5 in AQ_MssEgressLutDataControlRegister_HHD */ -#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_5 5 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_5 in AQ_MssEgressLutDataControlRegister_HHD */ -#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_5 u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_5 in AQ_MssEgressLutDataControlRegister_HHD */ -#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_5 u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_6 in AQ_MssEgressLutDataControlRegister_HHD */ -#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_6 6 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_6 in AQ_MssEgressLutDataControlRegister_HHD */ -#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_6 u6.bits_6 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_6 in AQ_MssEgressLutDataControlRegister_HHD */ -#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_6 u6.word_6 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_7 in AQ_MssEgressLutDataControlRegister_HHD */ -#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_7 7 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_7 in AQ_MssEgressLutDataControlRegister_HHD */ -#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_7 u7.bits_7 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_7 in AQ_MssEgressLutDataControlRegister_HHD */ -#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_7 u7.word_7 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_8 in AQ_MssEgressLutDataControlRegister_HHD */ -#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_8 8 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_8 in AQ_MssEgressLutDataControlRegister_HHD */ -#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_8 u8.bits_8 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_8 in AQ_MssEgressLutDataControlRegister_HHD */ -#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_8 u8.word_8 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_9 in AQ_MssEgressLutDataControlRegister_HHD */ -#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_9 9 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_9 in AQ_MssEgressLutDataControlRegister_HHD */ -#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_9 u9.bits_9 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_9 in AQ_MssEgressLutDataControlRegister_HHD */ -#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_9 u9.word_9 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_10 in AQ_MssEgressLutDataControlRegister_HHD */ -#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_10 10 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_10 in AQ_MssEgressLutDataControlRegister_HHD */ -#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_10 u10.bits_10 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_10 in AQ_MssEgressLutDataControlRegister_HHD */ -#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_10 u10.word_10 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_11 in AQ_MssEgressLutDataControlRegister_HHD */ -#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_11 11 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_11 in AQ_MssEgressLutDataControlRegister_HHD */ -#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_11 u11.bits_11 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_11 in AQ_MssEgressLutDataControlRegister_HHD */ -#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_11 u11.word_11 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_12 in AQ_MssEgressLutDataControlRegister_HHD */ -#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_12 12 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_12 in AQ_MssEgressLutDataControlRegister_HHD */ -#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_12 u12.bits_12 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_12 in AQ_MssEgressLutDataControlRegister_HHD */ -#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_12 u12.word_12 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_13 in AQ_MssEgressLutDataControlRegister_HHD */ -#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_13 13 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_13 in AQ_MssEgressLutDataControlRegister_HHD */ -#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_13 u13.bits_13 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_13 in AQ_MssEgressLutDataControlRegister_HHD */ -#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_13 u13.word_13 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_14 in AQ_MssEgressLutDataControlRegister_HHD */ -#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_14 14 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_14 in AQ_MssEgressLutDataControlRegister_HHD */ -#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_14 u14.bits_14 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_14 in AQ_MssEgressLutDataControlRegister_HHD */ -#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_14 u14.word_14 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_15 in AQ_MssEgressLutDataControlRegister_HHD */ -#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_15 15 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_15 in AQ_MssEgressLutDataControlRegister_HHD */ -#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_15 u15.bits_15 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_15 in AQ_MssEgressLutDataControlRegister_HHD */ -#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_15 u15.word_15 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_16 in AQ_MssEgressLutDataControlRegister_HHD */ -#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_16 16 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_16 in AQ_MssEgressLutDataControlRegister_HHD */ -#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_16 u16.bits_16 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_16 in AQ_MssEgressLutDataControlRegister_HHD */ -#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_16 u16.word_16 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_17 in AQ_MssEgressLutDataControlRegister_HHD */ -#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_17 17 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_17 in AQ_MssEgressLutDataControlRegister_HHD */ -#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_17 u17.bits_17 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_17 in AQ_MssEgressLutDataControlRegister_HHD */ -#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_17 u17.word_17 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_18 in AQ_MssEgressLutDataControlRegister_HHD */ -#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_18 18 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_18 in AQ_MssEgressLutDataControlRegister_HHD */ -#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_18 u18.bits_18 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_18 in AQ_MssEgressLutDataControlRegister_HHD */ -#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_18 u18.word_18 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_19 in AQ_MssEgressLutDataControlRegister_HHD */ -#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_19 19 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_19 in AQ_MssEgressLutDataControlRegister_HHD */ -#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_19 u19.bits_19 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_19 in AQ_MssEgressLutDataControlRegister_HHD */ -#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_19 u19.word_19 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_20 in AQ_MssEgressLutDataControlRegister_HHD */ -#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_20 20 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_20 in AQ_MssEgressLutDataControlRegister_HHD */ -#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_20 u20.bits_20 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_20 in AQ_MssEgressLutDataControlRegister_HHD */ -#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_20 u20.word_20 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_21 in AQ_MssEgressLutDataControlRegister_HHD */ -#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_21 21 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_21 in AQ_MssEgressLutDataControlRegister_HHD */ -#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_21 u21.bits_21 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_21 in AQ_MssEgressLutDataControlRegister_HHD */ -#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_21 u21.word_21 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_22 in AQ_MssEgressLutDataControlRegister_HHD */ -#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_22 22 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_22 in AQ_MssEgressLutDataControlRegister_HHD */ -#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_22 u22.bits_22 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_22 in AQ_MssEgressLutDataControlRegister_HHD */ -#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_22 u22.word_22 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_23 in AQ_MssEgressLutDataControlRegister_HHD */ -#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_23 23 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_23 in AQ_MssEgressLutDataControlRegister_HHD */ -#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_23 u23.bits_23 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_23 in AQ_MssEgressLutDataControlRegister_HHD */ -#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_23 u23.word_23 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_24 in AQ_MssEgressLutDataControlRegister_HHD */ -#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_24 24 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_24 in AQ_MssEgressLutDataControlRegister_HHD */ -#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_24 u24.bits_24 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_24 in AQ_MssEgressLutDataControlRegister_HHD */ -#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_24 u24.word_24 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_25 in AQ_MssEgressLutDataControlRegister_HHD */ -#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_25 25 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_25 in AQ_MssEgressLutDataControlRegister_HHD */ -#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_25 u25.bits_25 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_25 in AQ_MssEgressLutDataControlRegister_HHD */ -#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_25 u25.word_25 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_26 in AQ_MssEgressLutDataControlRegister_HHD */ -#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_26 26 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_26 in AQ_MssEgressLutDataControlRegister_HHD */ -#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_26 u26.bits_26 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_26 in AQ_MssEgressLutDataControlRegister_HHD */ -#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_26 u26.word_26 -/*! \brief Preprocessor variable to relate field to word number in structure mssEgressLutData_27 in AQ_MssEgressLutDataControlRegister_HHD */ -#define AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_27 27 -/*! \brief Preprocessor variable to relate field to bit position in structure mssEgressLutData_27 in AQ_MssEgressLutDataControlRegister_HHD */ -#define bits_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_27 u27.bits_27 -/*! \brief Preprocessor variable to relate field to word position in structure mssEgressLutData_27 in AQ_MssEgressLutDataControlRegister_HHD */ -#define word_AQ_MssEgressLutDataControlRegister_HHD_mssEgressLutData_27 u27.word_27 - -/*! \brief Base register address of structure AQ_MsmSystemGeneralControlRegister_HHD */ -#define AQ_MsmSystemGeneralControlRegister_HHD_baseRegisterAddress 0x6004 -/*! \brief MMD address of structure AQ_MsmSystemGeneralControlRegister_HHD */ -#define AQ_MsmSystemGeneralControlRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemPhyTxEnable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPhyTxEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemPhyTxEnable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPhyTxEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemPhyTxEnable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPhyTxEnable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxErrorDiscard in AQ_MsmSystemGeneralControlRegister_HHD */ -#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemRxErrorDiscard 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxErrorDiscard in AQ_MsmSystemGeneralControlRegister_HHD */ -#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemRxErrorDiscard u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxErrorDiscard in AQ_MsmSystemGeneralControlRegister_HHD */ -#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemRxErrorDiscard u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemControlFrameEnable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemControlFrameEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemControlFrameEnable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemControlFrameEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemControlFrameEnable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemControlFrameEnable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemSoftReset in AQ_MsmSystemGeneralControlRegister_HHD */ -#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemSoftReset 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemSoftReset in AQ_MsmSystemGeneralControlRegister_HHD */ -#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemSoftReset u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemSoftReset in AQ_MsmSystemGeneralControlRegister_HHD */ -#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemSoftReset u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxPadEnable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxPadEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxPadEnable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxPadEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxPadEnable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxPadEnable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxCrcAppend in AQ_MsmSystemGeneralControlRegister_HHD */ -#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxCrcAppend 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxCrcAppend in AQ_MsmSystemGeneralControlRegister_HHD */ -#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxCrcAppend u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxCrcAppend in AQ_MsmSystemGeneralControlRegister_HHD */ -#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxCrcAppend u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxAddressInsertEnable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxAddressInsertEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxAddressInsertEnable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxAddressInsertEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxAddressInsertEnable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxAddressInsertEnable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemPauseIgnore in AQ_MsmSystemGeneralControlRegister_HHD */ -#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPauseIgnore 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemPauseIgnore in AQ_MsmSystemGeneralControlRegister_HHD */ -#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPauseIgnore u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemPauseIgnore in AQ_MsmSystemGeneralControlRegister_HHD */ -#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPauseIgnore u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemPauseForward in AQ_MsmSystemGeneralControlRegister_HHD */ -#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPauseForward 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemPauseForward in AQ_MsmSystemGeneralControlRegister_HHD */ -#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPauseForward u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemPauseForward in AQ_MsmSystemGeneralControlRegister_HHD */ -#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPauseForward u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemCrcForward in AQ_MsmSystemGeneralControlRegister_HHD */ -#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemCrcForward 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemCrcForward in AQ_MsmSystemGeneralControlRegister_HHD */ -#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemCrcForward u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemCrcForward in AQ_MsmSystemGeneralControlRegister_HHD */ -#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemCrcForward u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemPadEnable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPadEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemPadEnable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPadEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemPadEnable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPadEnable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemPromiscuousMode in AQ_MsmSystemGeneralControlRegister_HHD */ -#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPromiscuousMode 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemPromiscuousMode in AQ_MsmSystemGeneralControlRegister_HHD */ -#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPromiscuousMode u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemPromiscuousMode in AQ_MsmSystemGeneralControlRegister_HHD */ -#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPromiscuousMode u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemWanMode in AQ_MsmSystemGeneralControlRegister_HHD */ -#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemWanMode 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemWanMode in AQ_MsmSystemGeneralControlRegister_HHD */ -#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemWanMode u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemWanMode in AQ_MsmSystemGeneralControlRegister_HHD */ -#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemWanMode u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxEnable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemRxEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxEnable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemRxEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxEnable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemRxEnable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxEnable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxEnable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxEnable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxEnable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxLowPowerIdleEnable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxLowPowerIdleEnable 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxLowPowerIdleEnable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxLowPowerIdleEnable u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxLowPowerIdleEnable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemTxLowPowerIdleEnable u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemSfdCheckDisable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemSfdCheckDisable 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemSfdCheckDisable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemSfdCheckDisable u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemSfdCheckDisable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemSfdCheckDisable u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemPriorityFlowControlEnable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPriorityFlowControlEnable 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemPriorityFlowControlEnable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPriorityFlowControlEnable u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemPriorityFlowControlEnable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemPriorityFlowControlEnable u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemIdleColumnCountExtend in AQ_MsmSystemGeneralControlRegister_HHD */ -#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemIdleColumnCountExtend 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemIdleColumnCountExtend in AQ_MsmSystemGeneralControlRegister_HHD */ -#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemIdleColumnCountExtend u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemIdleColumnCountExtend in AQ_MsmSystemGeneralControlRegister_HHD */ -#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemIdleColumnCountExtend u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemLengthCheckDisable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemLengthCheckDisable 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemLengthCheckDisable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemLengthCheckDisable u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemLengthCheckDisable in AQ_MsmSystemGeneralControlRegister_HHD */ -#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemLengthCheckDisable u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemForceSendIdle in AQ_MsmSystemGeneralControlRegister_HHD */ -#define AQ_MsmSystemGeneralControlRegister_HHD_msmSystemForceSendIdle 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemForceSendIdle in AQ_MsmSystemGeneralControlRegister_HHD */ -#define bits_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemForceSendIdle u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemForceSendIdle in AQ_MsmSystemGeneralControlRegister_HHD */ -#define word_AQ_MsmSystemGeneralControlRegister_HHD_msmSystemForceSendIdle u1.word_1 - -/*! \brief Base register address of structure AQ_MsmSystemFifoControlRegister_HHD */ -#define AQ_MsmSystemFifoControlRegister_HHD_baseRegisterAddress 0x600E -/*! \brief MMD address of structure AQ_MsmSystemFifoControlRegister_HHD */ -#define AQ_MsmSystemFifoControlRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxFifoFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ -#define AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoFullThreshold 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxFifoFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ -#define bits_AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoFullThreshold u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxFifoFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ -#define word_AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoFullThreshold u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxFifoEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ -#define AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoEmptyThreshold 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxFifoEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ -#define bits_AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoEmptyThreshold u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxFifoEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ -#define word_AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoEmptyThreshold u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxFifoFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ -#define AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoFullThreshold 2 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxFifoFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ -#define bits_AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoFullThreshold u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxFifoFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ -#define word_AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoFullThreshold u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxFifoEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ -#define AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoEmptyThreshold 3 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxFifoEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ -#define bits_AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoEmptyThreshold u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxFifoEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ -#define word_AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoEmptyThreshold u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxFifoAlmostFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ -#define AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoAlmostFullThreshold 4 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxFifoAlmostFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ -#define bits_AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoAlmostFullThreshold u4.bits_4 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxFifoAlmostFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ -#define word_AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoAlmostFullThreshold u4.word_4 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxFifoAlmostEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ -#define AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoAlmostEmptyThreshold 5 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxFifoAlmostEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ -#define bits_AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoAlmostEmptyThreshold u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxFifoAlmostEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ -#define word_AQ_MsmSystemFifoControlRegister_HHD_msmSystemRxFifoAlmostEmptyThreshold u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxFifoAlmostFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ -#define AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoAlmostFullThreshold 6 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxFifoAlmostFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ -#define bits_AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoAlmostFullThreshold u6.bits_6 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxFifoAlmostFullThreshold in AQ_MsmSystemFifoControlRegister_HHD */ -#define word_AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoAlmostFullThreshold u6.word_6 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxFifoAlmostEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ -#define AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoAlmostEmptyThreshold 7 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxFifoAlmostEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ -#define bits_AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoAlmostEmptyThreshold u7.bits_7 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxFifoAlmostEmptyThreshold in AQ_MsmSystemFifoControlRegister_HHD */ -#define word_AQ_MsmSystemFifoControlRegister_HHD_msmSystemTxFifoAlmostEmptyThreshold u7.word_7 - -/*! \brief Base register address of structure AQ_MsmSystemGeneralStatusRegister_HHD */ -#define AQ_MsmSystemGeneralStatusRegister_HHD_baseRegisterAddress 0x6020 -/*! \brief MMD address of structure AQ_MsmSystemGeneralStatusRegister_HHD */ -#define AQ_MsmSystemGeneralStatusRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxFifoEmpty in AQ_MsmSystemGeneralStatusRegister_HHD */ -#define AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemTxFifoEmpty 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxFifoEmpty in AQ_MsmSystemGeneralStatusRegister_HHD */ -#define bits_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemTxFifoEmpty u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxFifoEmpty in AQ_MsmSystemGeneralStatusRegister_HHD */ -#define word_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemTxFifoEmpty u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxLowPowerIdle in AQ_MsmSystemGeneralStatusRegister_HHD */ -#define AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemRxLowPowerIdle 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxLowPowerIdle in AQ_MsmSystemGeneralStatusRegister_HHD */ -#define bits_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemRxLowPowerIdle u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxLowPowerIdle in AQ_MsmSystemGeneralStatusRegister_HHD */ -#define word_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemRxLowPowerIdle u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTimestampAvailable in AQ_MsmSystemGeneralStatusRegister_HHD */ -#define AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemTimestampAvailable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTimestampAvailable in AQ_MsmSystemGeneralStatusRegister_HHD */ -#define bits_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemTimestampAvailable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTimestampAvailable in AQ_MsmSystemGeneralStatusRegister_HHD */ -#define word_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemTimestampAvailable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemPhyLossOfSignal in AQ_MsmSystemGeneralStatusRegister_HHD */ -#define AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemPhyLossOfSignal 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemPhyLossOfSignal in AQ_MsmSystemGeneralStatusRegister_HHD */ -#define bits_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemPhyLossOfSignal u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemPhyLossOfSignal in AQ_MsmSystemGeneralStatusRegister_HHD */ -#define word_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemPhyLossOfSignal u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxRemoteFault in AQ_MsmSystemGeneralStatusRegister_HHD */ -#define AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemRxRemoteFault 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxRemoteFault in AQ_MsmSystemGeneralStatusRegister_HHD */ -#define bits_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemRxRemoteFault u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxRemoteFault in AQ_MsmSystemGeneralStatusRegister_HHD */ -#define word_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemRxRemoteFault u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxLocalFault in AQ_MsmSystemGeneralStatusRegister_HHD */ -#define AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemRxLocalFault 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxLocalFault in AQ_MsmSystemGeneralStatusRegister_HHD */ -#define bits_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemRxLocalFault u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxLocalFault in AQ_MsmSystemGeneralStatusRegister_HHD */ -#define word_AQ_MsmSystemGeneralStatusRegister_HHD_msmSystemRxLocalFault u0.word_0 - -/*! \brief Base register address of structure AQ_MsmSystemTxIpgControlRegister_HHD */ -#define AQ_MsmSystemTxIpgControlRegister_HHD_baseRegisterAddress 0x6022 -/*! \brief MMD address of structure AQ_MsmSystemTxIpgControlRegister_HHD */ -#define AQ_MsmSystemTxIpgControlRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxIpgLength in AQ_MsmSystemTxIpgControlRegister_HHD */ -#define AQ_MsmSystemTxIpgControlRegister_HHD_msmSystemTxIpgLength 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxIpgLength in AQ_MsmSystemTxIpgControlRegister_HHD */ -#define bits_AQ_MsmSystemTxIpgControlRegister_HHD_msmSystemTxIpgLength u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxIpgLength in AQ_MsmSystemTxIpgControlRegister_HHD */ -#define word_AQ_MsmSystemTxIpgControlRegister_HHD_msmSystemTxIpgLength u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxIpgReserved in AQ_MsmSystemTxIpgControlRegister_HHD */ -#define AQ_MsmSystemTxIpgControlRegister_HHD_msmSystemTxIpgReserved 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxIpgReserved in AQ_MsmSystemTxIpgControlRegister_HHD */ -#define bits_AQ_MsmSystemTxIpgControlRegister_HHD_msmSystemTxIpgReserved u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxIpgReserved in AQ_MsmSystemTxIpgControlRegister_HHD */ -#define word_AQ_MsmSystemTxIpgControlRegister_HHD_msmSystemTxIpgReserved u1.word_1 - -/*! \brief Base register address of structure AQ_MsmSystemTxGoodFramesCounterRegister_HHD */ -#define AQ_MsmSystemTxGoodFramesCounterRegister_HHD_baseRegisterAddress 0x6040 -/*! \brief MMD address of structure AQ_MsmSystemTxGoodFramesCounterRegister_HHD */ -#define AQ_MsmSystemTxGoodFramesCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxGoodFramesCounter_0 in AQ_MsmSystemTxGoodFramesCounterRegister_HHD */ -#define AQ_MsmSystemTxGoodFramesCounterRegister_HHD_msmSystemTxGoodFramesCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxGoodFramesCounter_0 in AQ_MsmSystemTxGoodFramesCounterRegister_HHD */ -#define bits_AQ_MsmSystemTxGoodFramesCounterRegister_HHD_msmSystemTxGoodFramesCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxGoodFramesCounter_0 in AQ_MsmSystemTxGoodFramesCounterRegister_HHD */ -#define word_AQ_MsmSystemTxGoodFramesCounterRegister_HHD_msmSystemTxGoodFramesCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxGoodFramesCounter_1 in AQ_MsmSystemTxGoodFramesCounterRegister_HHD */ -#define AQ_MsmSystemTxGoodFramesCounterRegister_HHD_msmSystemTxGoodFramesCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxGoodFramesCounter_1 in AQ_MsmSystemTxGoodFramesCounterRegister_HHD */ -#define bits_AQ_MsmSystemTxGoodFramesCounterRegister_HHD_msmSystemTxGoodFramesCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxGoodFramesCounter_1 in AQ_MsmSystemTxGoodFramesCounterRegister_HHD */ -#define word_AQ_MsmSystemTxGoodFramesCounterRegister_HHD_msmSystemTxGoodFramesCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmSystemRxGoodFramesCounterRegister_HHD */ -#define AQ_MsmSystemRxGoodFramesCounterRegister_HHD_baseRegisterAddress 0x6044 -/*! \brief MMD address of structure AQ_MsmSystemRxGoodFramesCounterRegister_HHD */ -#define AQ_MsmSystemRxGoodFramesCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxGoodFramesCounter_0 in AQ_MsmSystemRxGoodFramesCounterRegister_HHD */ -#define AQ_MsmSystemRxGoodFramesCounterRegister_HHD_msmSystemRxGoodFramesCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxGoodFramesCounter_0 in AQ_MsmSystemRxGoodFramesCounterRegister_HHD */ -#define bits_AQ_MsmSystemRxGoodFramesCounterRegister_HHD_msmSystemRxGoodFramesCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxGoodFramesCounter_0 in AQ_MsmSystemRxGoodFramesCounterRegister_HHD */ -#define word_AQ_MsmSystemRxGoodFramesCounterRegister_HHD_msmSystemRxGoodFramesCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxGoodFramesCounter_1 in AQ_MsmSystemRxGoodFramesCounterRegister_HHD */ -#define AQ_MsmSystemRxGoodFramesCounterRegister_HHD_msmSystemRxGoodFramesCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxGoodFramesCounter_1 in AQ_MsmSystemRxGoodFramesCounterRegister_HHD */ -#define bits_AQ_MsmSystemRxGoodFramesCounterRegister_HHD_msmSystemRxGoodFramesCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxGoodFramesCounter_1 in AQ_MsmSystemRxGoodFramesCounterRegister_HHD */ -#define word_AQ_MsmSystemRxGoodFramesCounterRegister_HHD_msmSystemRxGoodFramesCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmSystemRxFcsErrorsCounterRegister_HHD */ -#define AQ_MsmSystemRxFcsErrorsCounterRegister_HHD_baseRegisterAddress 0x6048 -/*! \brief MMD address of structure AQ_MsmSystemRxFcsErrorsCounterRegister_HHD */ -#define AQ_MsmSystemRxFcsErrorsCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemFcsErrorCounter_0 in AQ_MsmSystemRxFcsErrorsCounterRegister_HHD */ -#define AQ_MsmSystemRxFcsErrorsCounterRegister_HHD_msmSystemFcsErrorCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemFcsErrorCounter_0 in AQ_MsmSystemRxFcsErrorsCounterRegister_HHD */ -#define bits_AQ_MsmSystemRxFcsErrorsCounterRegister_HHD_msmSystemFcsErrorCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemFcsErrorCounter_0 in AQ_MsmSystemRxFcsErrorsCounterRegister_HHD */ -#define word_AQ_MsmSystemRxFcsErrorsCounterRegister_HHD_msmSystemFcsErrorCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemFcsErrorCounter_1 in AQ_MsmSystemRxFcsErrorsCounterRegister_HHD */ -#define AQ_MsmSystemRxFcsErrorsCounterRegister_HHD_msmSystemFcsErrorCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemFcsErrorCounter_1 in AQ_MsmSystemRxFcsErrorsCounterRegister_HHD */ -#define bits_AQ_MsmSystemRxFcsErrorsCounterRegister_HHD_msmSystemFcsErrorCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemFcsErrorCounter_1 in AQ_MsmSystemRxFcsErrorsCounterRegister_HHD */ -#define word_AQ_MsmSystemRxFcsErrorsCounterRegister_HHD_msmSystemFcsErrorCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD */ -#define AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD_baseRegisterAddress 0x604C -/*! \brief MMD address of structure AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD */ -#define AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemAlignmentErrorCounter_0 in AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD */ -#define AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD_msmSystemAlignmentErrorCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemAlignmentErrorCounter_0 in AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD */ -#define bits_AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD_msmSystemAlignmentErrorCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemAlignmentErrorCounter_0 in AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD */ -#define word_AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD_msmSystemAlignmentErrorCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemAlignmentErrorCounter_1 in AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD */ -#define AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD_msmSystemAlignmentErrorCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemAlignmentErrorCounter_1 in AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD */ -#define bits_AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD_msmSystemAlignmentErrorCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemAlignmentErrorCounter_1 in AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD */ -#define word_AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD_msmSystemAlignmentErrorCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmSystemTxPauseFramesCounterRegister_HHD */ -#define AQ_MsmSystemTxPauseFramesCounterRegister_HHD_baseRegisterAddress 0x6050 -/*! \brief MMD address of structure AQ_MsmSystemTxPauseFramesCounterRegister_HHD */ -#define AQ_MsmSystemTxPauseFramesCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxPauseFramesCounter_0 in AQ_MsmSystemTxPauseFramesCounterRegister_HHD */ -#define AQ_MsmSystemTxPauseFramesCounterRegister_HHD_msmSystemTxPauseFramesCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxPauseFramesCounter_0 in AQ_MsmSystemTxPauseFramesCounterRegister_HHD */ -#define bits_AQ_MsmSystemTxPauseFramesCounterRegister_HHD_msmSystemTxPauseFramesCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxPauseFramesCounter_0 in AQ_MsmSystemTxPauseFramesCounterRegister_HHD */ -#define word_AQ_MsmSystemTxPauseFramesCounterRegister_HHD_msmSystemTxPauseFramesCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxPauseFramesCounter_1 in AQ_MsmSystemTxPauseFramesCounterRegister_HHD */ -#define AQ_MsmSystemTxPauseFramesCounterRegister_HHD_msmSystemTxPauseFramesCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxPauseFramesCounter_1 in AQ_MsmSystemTxPauseFramesCounterRegister_HHD */ -#define bits_AQ_MsmSystemTxPauseFramesCounterRegister_HHD_msmSystemTxPauseFramesCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxPauseFramesCounter_1 in AQ_MsmSystemTxPauseFramesCounterRegister_HHD */ -#define word_AQ_MsmSystemTxPauseFramesCounterRegister_HHD_msmSystemTxPauseFramesCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmSystemRxPauseFramesCounterRegister_HHD */ -#define AQ_MsmSystemRxPauseFramesCounterRegister_HHD_baseRegisterAddress 0x6054 -/*! \brief MMD address of structure AQ_MsmSystemRxPauseFramesCounterRegister_HHD */ -#define AQ_MsmSystemRxPauseFramesCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxPauseFramesCounter_0 in AQ_MsmSystemRxPauseFramesCounterRegister_HHD */ -#define AQ_MsmSystemRxPauseFramesCounterRegister_HHD_msmSystemRxPauseFramesCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxPauseFramesCounter_0 in AQ_MsmSystemRxPauseFramesCounterRegister_HHD */ -#define bits_AQ_MsmSystemRxPauseFramesCounterRegister_HHD_msmSystemRxPauseFramesCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxPauseFramesCounter_0 in AQ_MsmSystemRxPauseFramesCounterRegister_HHD */ -#define word_AQ_MsmSystemRxPauseFramesCounterRegister_HHD_msmSystemRxPauseFramesCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxPauseFramesCounter_1 in AQ_MsmSystemRxPauseFramesCounterRegister_HHD */ -#define AQ_MsmSystemRxPauseFramesCounterRegister_HHD_msmSystemRxPauseFramesCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxPauseFramesCounter_1 in AQ_MsmSystemRxPauseFramesCounterRegister_HHD */ -#define bits_AQ_MsmSystemRxPauseFramesCounterRegister_HHD_msmSystemRxPauseFramesCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxPauseFramesCounter_1 in AQ_MsmSystemRxPauseFramesCounterRegister_HHD */ -#define word_AQ_MsmSystemRxPauseFramesCounterRegister_HHD_msmSystemRxPauseFramesCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD */ -#define AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD_baseRegisterAddress 0x6058 -/*! \brief MMD address of structure AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD */ -#define AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxTooLongErrorsCounter_0 in AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD */ -#define AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD_msmSystemRxTooLongErrorsCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxTooLongErrorsCounter_0 in AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD */ -#define bits_AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD_msmSystemRxTooLongErrorsCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxTooLongErrorsCounter_0 in AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD */ -#define word_AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD_msmSystemRxTooLongErrorsCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxTooLongErrorsCounter_1 in AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD */ -#define AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD_msmSystemRxTooLongErrorsCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxTooLongErrorsCounter_1 in AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD */ -#define bits_AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD_msmSystemRxTooLongErrorsCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxTooLongErrorsCounter_1 in AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD */ -#define word_AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD_msmSystemRxTooLongErrorsCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD */ -#define AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD_baseRegisterAddress 0x605C -/*! \brief MMD address of structure AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD */ -#define AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxInRangeLengthErrorsCounter_0 in AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD */ -#define AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD_msmSystemRxInRangeLengthErrorsCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxInRangeLengthErrorsCounter_0 in AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD */ -#define bits_AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD_msmSystemRxInRangeLengthErrorsCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxInRangeLengthErrorsCounter_0 in AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD */ -#define word_AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD_msmSystemRxInRangeLengthErrorsCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxInRangeLengthErrorsCounter_1 in AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD */ -#define AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD_msmSystemRxInRangeLengthErrorsCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxInRangeLengthErrorsCounter_1 in AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD */ -#define bits_AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD_msmSystemRxInRangeLengthErrorsCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxInRangeLengthErrorsCounter_1 in AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD */ -#define word_AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD_msmSystemRxInRangeLengthErrorsCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmSystemTxVlanFramesCounterRegister_HHD */ -#define AQ_MsmSystemTxVlanFramesCounterRegister_HHD_baseRegisterAddress 0x6060 -/*! \brief MMD address of structure AQ_MsmSystemTxVlanFramesCounterRegister_HHD */ -#define AQ_MsmSystemTxVlanFramesCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxVlanFramesCounter_0 in AQ_MsmSystemTxVlanFramesCounterRegister_HHD */ -#define AQ_MsmSystemTxVlanFramesCounterRegister_HHD_msmSystemTxVlanFramesCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxVlanFramesCounter_0 in AQ_MsmSystemTxVlanFramesCounterRegister_HHD */ -#define bits_AQ_MsmSystemTxVlanFramesCounterRegister_HHD_msmSystemTxVlanFramesCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxVlanFramesCounter_0 in AQ_MsmSystemTxVlanFramesCounterRegister_HHD */ -#define word_AQ_MsmSystemTxVlanFramesCounterRegister_HHD_msmSystemTxVlanFramesCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxVlanFramesCounter_1 in AQ_MsmSystemTxVlanFramesCounterRegister_HHD */ -#define AQ_MsmSystemTxVlanFramesCounterRegister_HHD_msmSystemTxVlanFramesCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxVlanFramesCounter_1 in AQ_MsmSystemTxVlanFramesCounterRegister_HHD */ -#define bits_AQ_MsmSystemTxVlanFramesCounterRegister_HHD_msmSystemTxVlanFramesCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxVlanFramesCounter_1 in AQ_MsmSystemTxVlanFramesCounterRegister_HHD */ -#define word_AQ_MsmSystemTxVlanFramesCounterRegister_HHD_msmSystemTxVlanFramesCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmSystemRxVlanFramesCounterRegister_HHD */ -#define AQ_MsmSystemRxVlanFramesCounterRegister_HHD_baseRegisterAddress 0x6064 -/*! \brief MMD address of structure AQ_MsmSystemRxVlanFramesCounterRegister_HHD */ -#define AQ_MsmSystemRxVlanFramesCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxVlanFramesCounter_0 in AQ_MsmSystemRxVlanFramesCounterRegister_HHD */ -#define AQ_MsmSystemRxVlanFramesCounterRegister_HHD_msmSystemRxVlanFramesCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxVlanFramesCounter_0 in AQ_MsmSystemRxVlanFramesCounterRegister_HHD */ -#define bits_AQ_MsmSystemRxVlanFramesCounterRegister_HHD_msmSystemRxVlanFramesCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxVlanFramesCounter_0 in AQ_MsmSystemRxVlanFramesCounterRegister_HHD */ -#define word_AQ_MsmSystemRxVlanFramesCounterRegister_HHD_msmSystemRxVlanFramesCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxVlanFramesCounter_1 in AQ_MsmSystemRxVlanFramesCounterRegister_HHD */ -#define AQ_MsmSystemRxVlanFramesCounterRegister_HHD_msmSystemRxVlanFramesCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxVlanFramesCounter_1 in AQ_MsmSystemRxVlanFramesCounterRegister_HHD */ -#define bits_AQ_MsmSystemRxVlanFramesCounterRegister_HHD_msmSystemRxVlanFramesCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxVlanFramesCounter_1 in AQ_MsmSystemRxVlanFramesCounterRegister_HHD */ -#define word_AQ_MsmSystemRxVlanFramesCounterRegister_HHD_msmSystemRxVlanFramesCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmSystemTxOctetsCounterRegister_HHD */ -#define AQ_MsmSystemTxOctetsCounterRegister_HHD_baseRegisterAddress 0x6068 -/*! \brief MMD address of structure AQ_MsmSystemTxOctetsCounterRegister_HHD */ -#define AQ_MsmSystemTxOctetsCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxOctetsCounter_0 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ -#define AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxOctetsCounter_0 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ -#define bits_AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxOctetsCounter_0 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ -#define word_AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxOctetsCounter_1 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ -#define AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxOctetsCounter_1 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ -#define bits_AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxOctetsCounter_1 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ -#define word_AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_1 u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxOctetsCounter_2 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ -#define AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_2 2 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxOctetsCounter_2 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ -#define bits_AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_2 u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxOctetsCounter_2 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ -#define word_AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_2 u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxOctetsCounter_3 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ -#define AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_3 3 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxOctetsCounter_3 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ -#define bits_AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_3 u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxOctetsCounter_3 in AQ_MsmSystemTxOctetsCounterRegister_HHD */ -#define word_AQ_MsmSystemTxOctetsCounterRegister_HHD_msmSystemTxOctetsCounter_3 u3.word_3 - -/*! \brief Base register address of structure AQ_MsmSystemRxOctetsCounterRegister_HHD */ -#define AQ_MsmSystemRxOctetsCounterRegister_HHD_baseRegisterAddress 0x606C -/*! \brief MMD address of structure AQ_MsmSystemRxOctetsCounterRegister_HHD */ -#define AQ_MsmSystemRxOctetsCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxOctetsCounter_0 in AQ_MsmSystemRxOctetsCounterRegister_HHD */ -#define AQ_MsmSystemRxOctetsCounterRegister_HHD_msmSystemRxOctetsCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxOctetsCounter_0 in AQ_MsmSystemRxOctetsCounterRegister_HHD */ -#define bits_AQ_MsmSystemRxOctetsCounterRegister_HHD_msmSystemRxOctetsCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxOctetsCounter_0 in AQ_MsmSystemRxOctetsCounterRegister_HHD */ -#define word_AQ_MsmSystemRxOctetsCounterRegister_HHD_msmSystemRxOctetsCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxOctetsCounter_1 in AQ_MsmSystemRxOctetsCounterRegister_HHD */ -#define AQ_MsmSystemRxOctetsCounterRegister_HHD_msmSystemRxOctetsCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxOctetsCounter_1 in AQ_MsmSystemRxOctetsCounterRegister_HHD */ -#define bits_AQ_MsmSystemRxOctetsCounterRegister_HHD_msmSystemRxOctetsCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxOctetsCounter_1 in AQ_MsmSystemRxOctetsCounterRegister_HHD */ -#define word_AQ_MsmSystemRxOctetsCounterRegister_HHD_msmSystemRxOctetsCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmSystemRxUnicastFramesCounterRegister_HHD */ -#define AQ_MsmSystemRxUnicastFramesCounterRegister_HHD_baseRegisterAddress 0x6070 -/*! \brief MMD address of structure AQ_MsmSystemRxUnicastFramesCounterRegister_HHD */ -#define AQ_MsmSystemRxUnicastFramesCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxUnicastFramesCounter_0 in AQ_MsmSystemRxUnicastFramesCounterRegister_HHD */ -#define AQ_MsmSystemRxUnicastFramesCounterRegister_HHD_msmSystemRxUnicastFramesCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxUnicastFramesCounter_0 in AQ_MsmSystemRxUnicastFramesCounterRegister_HHD */ -#define bits_AQ_MsmSystemRxUnicastFramesCounterRegister_HHD_msmSystemRxUnicastFramesCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxUnicastFramesCounter_0 in AQ_MsmSystemRxUnicastFramesCounterRegister_HHD */ -#define word_AQ_MsmSystemRxUnicastFramesCounterRegister_HHD_msmSystemRxUnicastFramesCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxUnicastFramesCounter_1 in AQ_MsmSystemRxUnicastFramesCounterRegister_HHD */ -#define AQ_MsmSystemRxUnicastFramesCounterRegister_HHD_msmSystemRxUnicastFramesCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxUnicastFramesCounter_1 in AQ_MsmSystemRxUnicastFramesCounterRegister_HHD */ -#define bits_AQ_MsmSystemRxUnicastFramesCounterRegister_HHD_msmSystemRxUnicastFramesCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxUnicastFramesCounter_1 in AQ_MsmSystemRxUnicastFramesCounterRegister_HHD */ -#define word_AQ_MsmSystemRxUnicastFramesCounterRegister_HHD_msmSystemRxUnicastFramesCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmSystemRxMulticastFramesCounterRegister_HHD */ -#define AQ_MsmSystemRxMulticastFramesCounterRegister_HHD_baseRegisterAddress 0x6074 -/*! \brief MMD address of structure AQ_MsmSystemRxMulticastFramesCounterRegister_HHD */ -#define AQ_MsmSystemRxMulticastFramesCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxMulticastFramesCounter_0 in AQ_MsmSystemRxMulticastFramesCounterRegister_HHD */ -#define AQ_MsmSystemRxMulticastFramesCounterRegister_HHD_msmSystemRxMulticastFramesCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxMulticastFramesCounter_0 in AQ_MsmSystemRxMulticastFramesCounterRegister_HHD */ -#define bits_AQ_MsmSystemRxMulticastFramesCounterRegister_HHD_msmSystemRxMulticastFramesCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxMulticastFramesCounter_0 in AQ_MsmSystemRxMulticastFramesCounterRegister_HHD */ -#define word_AQ_MsmSystemRxMulticastFramesCounterRegister_HHD_msmSystemRxMulticastFramesCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxMulticastFramesCounter_1 in AQ_MsmSystemRxMulticastFramesCounterRegister_HHD */ -#define AQ_MsmSystemRxMulticastFramesCounterRegister_HHD_msmSystemRxMulticastFramesCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxMulticastFramesCounter_1 in AQ_MsmSystemRxMulticastFramesCounterRegister_HHD */ -#define bits_AQ_MsmSystemRxMulticastFramesCounterRegister_HHD_msmSystemRxMulticastFramesCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxMulticastFramesCounter_1 in AQ_MsmSystemRxMulticastFramesCounterRegister_HHD */ -#define word_AQ_MsmSystemRxMulticastFramesCounterRegister_HHD_msmSystemRxMulticastFramesCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD */ -#define AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD_baseRegisterAddress 0x6078 -/*! \brief MMD address of structure AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD */ -#define AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxBroadcastFramesCounter_0 in AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD */ -#define AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD_msmSystemRxBroadcastFramesCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxBroadcastFramesCounter_0 in AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD */ -#define bits_AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD_msmSystemRxBroadcastFramesCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxBroadcastFramesCounter_0 in AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD */ -#define word_AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD_msmSystemRxBroadcastFramesCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxBroadcastFramesCounter_1 in AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD */ -#define AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD_msmSystemRxBroadcastFramesCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxBroadcastFramesCounter_1 in AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD */ -#define bits_AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD_msmSystemRxBroadcastFramesCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxBroadcastFramesCounter_1 in AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD */ -#define word_AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD_msmSystemRxBroadcastFramesCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmSystemTxErrorsCounterRegister_HHD */ -#define AQ_MsmSystemTxErrorsCounterRegister_HHD_baseRegisterAddress 0x607C -/*! \brief MMD address of structure AQ_MsmSystemTxErrorsCounterRegister_HHD */ -#define AQ_MsmSystemTxErrorsCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxErrorsCounter_0 in AQ_MsmSystemTxErrorsCounterRegister_HHD */ -#define AQ_MsmSystemTxErrorsCounterRegister_HHD_msmSystemTxErrorsCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxErrorsCounter_0 in AQ_MsmSystemTxErrorsCounterRegister_HHD */ -#define bits_AQ_MsmSystemTxErrorsCounterRegister_HHD_msmSystemTxErrorsCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxErrorsCounter_0 in AQ_MsmSystemTxErrorsCounterRegister_HHD */ -#define word_AQ_MsmSystemTxErrorsCounterRegister_HHD_msmSystemTxErrorsCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxErrorsCounter_1 in AQ_MsmSystemTxErrorsCounterRegister_HHD */ -#define AQ_MsmSystemTxErrorsCounterRegister_HHD_msmSystemTxErrorsCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxErrorsCounter_1 in AQ_MsmSystemTxErrorsCounterRegister_HHD */ -#define bits_AQ_MsmSystemTxErrorsCounterRegister_HHD_msmSystemTxErrorsCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxErrorsCounter_1 in AQ_MsmSystemTxErrorsCounterRegister_HHD */ -#define word_AQ_MsmSystemTxErrorsCounterRegister_HHD_msmSystemTxErrorsCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmSystemTxUnicastFramesCounterRegister_HHD */ -#define AQ_MsmSystemTxUnicastFramesCounterRegister_HHD_baseRegisterAddress 0x6084 -/*! \brief MMD address of structure AQ_MsmSystemTxUnicastFramesCounterRegister_HHD */ -#define AQ_MsmSystemTxUnicastFramesCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxUnicastFramesCounter_0 in AQ_MsmSystemTxUnicastFramesCounterRegister_HHD */ -#define AQ_MsmSystemTxUnicastFramesCounterRegister_HHD_msmSystemTxUnicastFramesCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxUnicastFramesCounter_0 in AQ_MsmSystemTxUnicastFramesCounterRegister_HHD */ -#define bits_AQ_MsmSystemTxUnicastFramesCounterRegister_HHD_msmSystemTxUnicastFramesCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxUnicastFramesCounter_0 in AQ_MsmSystemTxUnicastFramesCounterRegister_HHD */ -#define word_AQ_MsmSystemTxUnicastFramesCounterRegister_HHD_msmSystemTxUnicastFramesCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxUnicastFramesCounter_1 in AQ_MsmSystemTxUnicastFramesCounterRegister_HHD */ -#define AQ_MsmSystemTxUnicastFramesCounterRegister_HHD_msmSystemTxUnicastFramesCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxUnicastFramesCounter_1 in AQ_MsmSystemTxUnicastFramesCounterRegister_HHD */ -#define bits_AQ_MsmSystemTxUnicastFramesCounterRegister_HHD_msmSystemTxUnicastFramesCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxUnicastFramesCounter_1 in AQ_MsmSystemTxUnicastFramesCounterRegister_HHD */ -#define word_AQ_MsmSystemTxUnicastFramesCounterRegister_HHD_msmSystemTxUnicastFramesCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmSystemTxMulticastFramesCounterRegister_HHD */ -#define AQ_MsmSystemTxMulticastFramesCounterRegister_HHD_baseRegisterAddress 0x6088 -/*! \brief MMD address of structure AQ_MsmSystemTxMulticastFramesCounterRegister_HHD */ -#define AQ_MsmSystemTxMulticastFramesCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxMulticastFramesCounter_0 in AQ_MsmSystemTxMulticastFramesCounterRegister_HHD */ -#define AQ_MsmSystemTxMulticastFramesCounterRegister_HHD_msmSystemTxMulticastFramesCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxMulticastFramesCounter_0 in AQ_MsmSystemTxMulticastFramesCounterRegister_HHD */ -#define bits_AQ_MsmSystemTxMulticastFramesCounterRegister_HHD_msmSystemTxMulticastFramesCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxMulticastFramesCounter_0 in AQ_MsmSystemTxMulticastFramesCounterRegister_HHD */ -#define word_AQ_MsmSystemTxMulticastFramesCounterRegister_HHD_msmSystemTxMulticastFramesCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxMulticastFramesCounter_1 in AQ_MsmSystemTxMulticastFramesCounterRegister_HHD */ -#define AQ_MsmSystemTxMulticastFramesCounterRegister_HHD_msmSystemTxMulticastFramesCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxMulticastFramesCounter_1 in AQ_MsmSystemTxMulticastFramesCounterRegister_HHD */ -#define bits_AQ_MsmSystemTxMulticastFramesCounterRegister_HHD_msmSystemTxMulticastFramesCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxMulticastFramesCounter_1 in AQ_MsmSystemTxMulticastFramesCounterRegister_HHD */ -#define word_AQ_MsmSystemTxMulticastFramesCounterRegister_HHD_msmSystemTxMulticastFramesCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD */ -#define AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD_baseRegisterAddress 0x608C -/*! \brief MMD address of structure AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD */ -#define AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxBroadcastFramesCounter_0 in AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD */ -#define AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD_msmSystemTxBroadcastFramesCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxBroadcastFramesCounter_0 in AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD */ -#define bits_AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD_msmSystemTxBroadcastFramesCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxBroadcastFramesCounter_0 in AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD */ -#define word_AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD_msmSystemTxBroadcastFramesCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemTxBroadcastFramesCounter_1 in AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD */ -#define AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD_msmSystemTxBroadcastFramesCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemTxBroadcastFramesCounter_1 in AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD */ -#define bits_AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD_msmSystemTxBroadcastFramesCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemTxBroadcastFramesCounter_1 in AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD */ -#define word_AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD_msmSystemTxBroadcastFramesCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmSystemRxErrorsCounterRegister_HHD */ -#define AQ_MsmSystemRxErrorsCounterRegister_HHD_baseRegisterAddress 0x60C8 -/*! \brief MMD address of structure AQ_MsmSystemRxErrorsCounterRegister_HHD */ -#define AQ_MsmSystemRxErrorsCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxErrorsCounter_0 in AQ_MsmSystemRxErrorsCounterRegister_HHD */ -#define AQ_MsmSystemRxErrorsCounterRegister_HHD_msmSystemRxErrorsCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxErrorsCounter_0 in AQ_MsmSystemRxErrorsCounterRegister_HHD */ -#define bits_AQ_MsmSystemRxErrorsCounterRegister_HHD_msmSystemRxErrorsCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxErrorsCounter_0 in AQ_MsmSystemRxErrorsCounterRegister_HHD */ -#define word_AQ_MsmSystemRxErrorsCounterRegister_HHD_msmSystemRxErrorsCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmSystemRxErrorsCounter_1 in AQ_MsmSystemRxErrorsCounterRegister_HHD */ -#define AQ_MsmSystemRxErrorsCounterRegister_HHD_msmSystemRxErrorsCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmSystemRxErrorsCounter_1 in AQ_MsmSystemRxErrorsCounterRegister_HHD */ -#define bits_AQ_MsmSystemRxErrorsCounterRegister_HHD_msmSystemRxErrorsCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmSystemRxErrorsCounter_1 in AQ_MsmSystemRxErrorsCounterRegister_HHD */ -#define word_AQ_MsmSystemRxErrorsCounterRegister_HHD_msmSystemRxErrorsCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MssIngressVlanTpid_0Register_HHD */ -#define AQ_MssIngressVlanTpid_0Register_HHD_baseRegisterAddress 0x8006 -/*! \brief MMD address of structure AQ_MssIngressVlanTpid_0Register_HHD */ -#define AQ_MssIngressVlanTpid_0Register_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressVlanStag in AQ_MssIngressVlanTpid_0Register_HHD */ -#define AQ_MssIngressVlanTpid_0Register_HHD_mssIngressVlanStag 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressVlanStag in AQ_MssIngressVlanTpid_0Register_HHD */ -#define bits_AQ_MssIngressVlanTpid_0Register_HHD_mssIngressVlanStag u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressVlanStag in AQ_MssIngressVlanTpid_0Register_HHD */ -#define word_AQ_MssIngressVlanTpid_0Register_HHD_mssIngressVlanStag u0.word_0 - -/*! \brief Base register address of structure AQ_MssIngressVlanTpid_1Register_HHD */ -#define AQ_MssIngressVlanTpid_1Register_HHD_baseRegisterAddress 0x8008 -/*! \brief MMD address of structure AQ_MssIngressVlanTpid_1Register_HHD */ -#define AQ_MssIngressVlanTpid_1Register_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressVlanQtag in AQ_MssIngressVlanTpid_1Register_HHD */ -#define AQ_MssIngressVlanTpid_1Register_HHD_mssIngressVlanQtag 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressVlanQtag in AQ_MssIngressVlanTpid_1Register_HHD */ -#define bits_AQ_MssIngressVlanTpid_1Register_HHD_mssIngressVlanQtag u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressVlanQtag in AQ_MssIngressVlanTpid_1Register_HHD */ -#define word_AQ_MssIngressVlanTpid_1Register_HHD_mssIngressVlanQtag u0.word_0 - -/*! \brief Base register address of structure AQ_MssIngressVlanControlRegister_HHD */ -#define AQ_MssIngressVlanControlRegister_HHD_baseRegisterAddress 0x800A -/*! \brief MMD address of structure AQ_MssIngressVlanControlRegister_HHD */ -#define AQ_MssIngressVlanControlRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressVlanUpMapTableLSW in AQ_MssIngressVlanControlRegister_HHD */ -#define AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanUpMapTableLSW 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressVlanUpMapTableLSW in AQ_MssIngressVlanControlRegister_HHD */ -#define bits_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanUpMapTableLSW u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressVlanUpMapTableLSW in AQ_MssIngressVlanControlRegister_HHD */ -#define word_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanUpMapTableLSW u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressVlanQtagParseEnable in AQ_MssIngressVlanControlRegister_HHD */ -#define AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanQtagParseEnable 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressVlanQtagParseEnable in AQ_MssIngressVlanControlRegister_HHD */ -#define bits_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanQtagParseEnable u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressVlanQtagParseEnable in AQ_MssIngressVlanControlRegister_HHD */ -#define word_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanQtagParseEnable u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressVlanStagParseEnable in AQ_MssIngressVlanControlRegister_HHD */ -#define AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanStagParseEnable 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressVlanStagParseEnable in AQ_MssIngressVlanControlRegister_HHD */ -#define bits_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanStagParseEnable u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressVlanStagParseEnable in AQ_MssIngressVlanControlRegister_HHD */ -#define word_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanStagParseEnable u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressVlanQinqParseEnable in AQ_MssIngressVlanControlRegister_HHD */ -#define AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanQinqParseEnable 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressVlanQinqParseEnable in AQ_MssIngressVlanControlRegister_HHD */ -#define bits_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanQinqParseEnable u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressVlanQinqParseEnable in AQ_MssIngressVlanControlRegister_HHD */ -#define word_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanQinqParseEnable u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressVlanQtagUpParseEnable in AQ_MssIngressVlanControlRegister_HHD */ -#define AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanQtagUpParseEnable 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressVlanQtagUpParseEnable in AQ_MssIngressVlanControlRegister_HHD */ -#define bits_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanQtagUpParseEnable u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressVlanQtagUpParseEnable in AQ_MssIngressVlanControlRegister_HHD */ -#define word_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanQtagUpParseEnable u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressVlanStagUpParseEnable in AQ_MssIngressVlanControlRegister_HHD */ -#define AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanStagUpParseEnable 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressVlanStagUpParseEnable in AQ_MssIngressVlanControlRegister_HHD */ -#define bits_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanStagUpParseEnable u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressVlanStagUpParseEnable in AQ_MssIngressVlanControlRegister_HHD */ -#define word_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanStagUpParseEnable u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressVlanUpDefault in AQ_MssIngressVlanControlRegister_HHD */ -#define AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanUpDefault 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressVlanUpDefault in AQ_MssIngressVlanControlRegister_HHD */ -#define bits_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanUpDefault u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressVlanUpDefault in AQ_MssIngressVlanControlRegister_HHD */ -#define word_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanUpDefault u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressVlanUpMapTableMSW in AQ_MssIngressVlanControlRegister_HHD */ -#define AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanUpMapTableMSW 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressVlanUpMapTableMSW in AQ_MssIngressVlanControlRegister_HHD */ -#define bits_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanUpMapTableMSW u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressVlanUpMapTableMSW in AQ_MssIngressVlanControlRegister_HHD */ -#define word_AQ_MssIngressVlanControlRegister_HHD_mssIngressVlanUpMapTableMSW u1.word_1 - -/*! \brief Base register address of structure AQ_MssIngressMtuSizeControlRegister_HHD */ -#define AQ_MssIngressMtuSizeControlRegister_HHD_baseRegisterAddress 0x800C -/*! \brief MMD address of structure AQ_MssIngressMtuSizeControlRegister_HHD */ -#define AQ_MssIngressMtuSizeControlRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressControlledPacketMtuSize in AQ_MssIngressMtuSizeControlRegister_HHD */ -#define AQ_MssIngressMtuSizeControlRegister_HHD_mssIngressControlledPacketMtuSize 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressControlledPacketMtuSize in AQ_MssIngressMtuSizeControlRegister_HHD */ -#define bits_AQ_MssIngressMtuSizeControlRegister_HHD_mssIngressControlledPacketMtuSize u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressControlledPacketMtuSize in AQ_MssIngressMtuSizeControlRegister_HHD */ -#define word_AQ_MssIngressMtuSizeControlRegister_HHD_mssIngressControlledPacketMtuSize u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressUncontrolledPacketMtuSize in AQ_MssIngressMtuSizeControlRegister_HHD */ -#define AQ_MssIngressMtuSizeControlRegister_HHD_mssIngressUncontrolledPacketMtuSize 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressUncontrolledPacketMtuSize in AQ_MssIngressMtuSizeControlRegister_HHD */ -#define bits_AQ_MssIngressMtuSizeControlRegister_HHD_mssIngressUncontrolledPacketMtuSize u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressUncontrolledPacketMtuSize in AQ_MssIngressMtuSizeControlRegister_HHD */ -#define word_AQ_MssIngressMtuSizeControlRegister_HHD_mssIngressUncontrolledPacketMtuSize u1.word_1 - -/*! \brief Base register address of structure AQ_MssIngressControlRegister_HHD */ -#define AQ_MssIngressControlRegister_HHD_baseRegisterAddress 0x800E -/*! \brief MMD address of structure AQ_MssIngressControlRegister_HHD */ -#define AQ_MssIngressControlRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressIcvLsb_8BytesEnable in AQ_MssIngressControlRegister_HHD */ -#define AQ_MssIngressControlRegister_HHD_mssIngressIcvLsb_8BytesEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressIcvLsb_8BytesEnable in AQ_MssIngressControlRegister_HHD */ -#define bits_AQ_MssIngressControlRegister_HHD_mssIngressIcvLsb_8BytesEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressIcvLsb_8BytesEnable in AQ_MssIngressControlRegister_HHD */ -#define word_AQ_MssIngressControlRegister_HHD_mssIngressIcvLsb_8BytesEnable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressGlobalValidateFrames in AQ_MssIngressControlRegister_HHD */ -#define AQ_MssIngressControlRegister_HHD_mssIngressGlobalValidateFrames 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressGlobalValidateFrames in AQ_MssIngressControlRegister_HHD */ -#define bits_AQ_MssIngressControlRegister_HHD_mssIngressGlobalValidateFrames u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressGlobalValidateFrames in AQ_MssIngressControlRegister_HHD */ -#define word_AQ_MssIngressControlRegister_HHD_mssIngressGlobalValidateFrames u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressRemoveSectag in AQ_MssIngressControlRegister_HHD */ -#define AQ_MssIngressControlRegister_HHD_mssIngressRemoveSectag 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressRemoveSectag in AQ_MssIngressControlRegister_HHD */ -#define bits_AQ_MssIngressControlRegister_HHD_mssIngressRemoveSectag u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressRemoveSectag in AQ_MssIngressControlRegister_HHD */ -#define word_AQ_MssIngressControlRegister_HHD_mssIngressRemoveSectag u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressHighPriority in AQ_MssIngressControlRegister_HHD */ -#define AQ_MssIngressControlRegister_HHD_mssIngressHighPriority 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressHighPriority in AQ_MssIngressControlRegister_HHD */ -#define bits_AQ_MssIngressControlRegister_HHD_mssIngressHighPriority u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressHighPriority in AQ_MssIngressControlRegister_HHD */ -#define word_AQ_MssIngressControlRegister_HHD_mssIngressHighPriority u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressClearCount in AQ_MssIngressControlRegister_HHD */ -#define AQ_MssIngressControlRegister_HHD_mssIngressClearCount 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressClearCount in AQ_MssIngressControlRegister_HHD */ -#define bits_AQ_MssIngressControlRegister_HHD_mssIngressClearCount u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressClearCount in AQ_MssIngressControlRegister_HHD */ -#define word_AQ_MssIngressControlRegister_HHD_mssIngressClearCount u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressClearGlobalTime in AQ_MssIngressControlRegister_HHD */ -#define AQ_MssIngressControlRegister_HHD_mssIngressClearGlobalTime 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressClearGlobalTime in AQ_MssIngressControlRegister_HHD */ -#define bits_AQ_MssIngressControlRegister_HHD_mssIngressClearGlobalTime u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressClearGlobalTime in AQ_MssIngressControlRegister_HHD */ -#define word_AQ_MssIngressControlRegister_HHD_mssIngressClearGlobalTime u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressCheckIcv in AQ_MssIngressControlRegister_HHD */ -#define AQ_MssIngressControlRegister_HHD_mssIngressCheckIcv 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressCheckIcv in AQ_MssIngressControlRegister_HHD */ -#define bits_AQ_MssIngressControlRegister_HHD_mssIngressCheckIcv u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressCheckIcv in AQ_MssIngressControlRegister_HHD */ -#define word_AQ_MssIngressControlRegister_HHD_mssIngressCheckIcv u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressDropIgprcMiss in AQ_MssIngressControlRegister_HHD */ -#define AQ_MssIngressControlRegister_HHD_mssIngressDropIgprcMiss 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressDropIgprcMiss in AQ_MssIngressControlRegister_HHD */ -#define bits_AQ_MssIngressControlRegister_HHD_mssIngressDropIgprcMiss u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressDropIgprcMiss in AQ_MssIngressControlRegister_HHD */ -#define word_AQ_MssIngressControlRegister_HHD_mssIngressDropIgprcMiss u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressDropKayPacket in AQ_MssIngressControlRegister_HHD */ -#define AQ_MssIngressControlRegister_HHD_mssIngressDropKayPacket 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressDropKayPacket in AQ_MssIngressControlRegister_HHD */ -#define bits_AQ_MssIngressControlRegister_HHD_mssIngressDropKayPacket u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressDropKayPacket in AQ_MssIngressControlRegister_HHD */ -#define word_AQ_MssIngressControlRegister_HHD_mssIngressDropKayPacket u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressMaskShortLengthError in AQ_MssIngressControlRegister_HHD */ -#define AQ_MssIngressControlRegister_HHD_mssIngressMaskShortLengthError 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressMaskShortLengthError in AQ_MssIngressControlRegister_HHD */ -#define bits_AQ_MssIngressControlRegister_HHD_mssIngressMaskShortLengthError u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressMaskShortLengthError in AQ_MssIngressControlRegister_HHD */ -#define word_AQ_MssIngressControlRegister_HHD_mssIngressMaskShortLengthError u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressCreateSci in AQ_MssIngressControlRegister_HHD */ -#define AQ_MssIngressControlRegister_HHD_mssIngressCreateSci 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressCreateSci in AQ_MssIngressControlRegister_HHD */ -#define bits_AQ_MssIngressControlRegister_HHD_mssIngressCreateSci u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressCreateSci in AQ_MssIngressControlRegister_HHD */ -#define word_AQ_MssIngressControlRegister_HHD_mssIngressCreateSci u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressOperationPointToPoint in AQ_MssIngressControlRegister_HHD */ -#define AQ_MssIngressControlRegister_HHD_mssIngressOperationPointToPoint 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressOperationPointToPoint in AQ_MssIngressControlRegister_HHD */ -#define bits_AQ_MssIngressControlRegister_HHD_mssIngressOperationPointToPoint u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressOperationPointToPoint in AQ_MssIngressControlRegister_HHD */ -#define word_AQ_MssIngressControlRegister_HHD_mssIngressOperationPointToPoint u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSoftReset in AQ_MssIngressControlRegister_HHD */ -#define AQ_MssIngressControlRegister_HHD_mssIngressSoftReset 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSoftReset in AQ_MssIngressControlRegister_HHD */ -#define bits_AQ_MssIngressControlRegister_HHD_mssIngressSoftReset u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSoftReset in AQ_MssIngressControlRegister_HHD */ -#define word_AQ_MssIngressControlRegister_HHD_mssIngressSoftReset u0.word_0 - -/*! \brief Base register address of structure AQ_MssIngressSaControlRegister_HHD */ -#define AQ_MssIngressSaControlRegister_HHD_baseRegisterAddress 0x8010 -/*! \brief MMD address of structure AQ_MssIngressSaControlRegister_HHD */ -#define AQ_MssIngressSaControlRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaThresholdLSW in AQ_MssIngressSaControlRegister_HHD */ -#define AQ_MssIngressSaControlRegister_HHD_mssIngressSaThresholdLSW 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaThresholdLSW in AQ_MssIngressSaControlRegister_HHD */ -#define bits_AQ_MssIngressSaControlRegister_HHD_mssIngressSaThresholdLSW u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaThresholdLSW in AQ_MssIngressSaControlRegister_HHD */ -#define word_AQ_MssIngressSaControlRegister_HHD_mssIngressSaThresholdLSW u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaThresholdMSW in AQ_MssIngressSaControlRegister_HHD */ -#define AQ_MssIngressSaControlRegister_HHD_mssIngressSaThresholdMSW 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaThresholdMSW in AQ_MssIngressSaControlRegister_HHD */ -#define bits_AQ_MssIngressSaControlRegister_HHD_mssIngressSaThresholdMSW u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaThresholdMSW in AQ_MssIngressSaControlRegister_HHD */ -#define word_AQ_MssIngressSaControlRegister_HHD_mssIngressSaThresholdMSW u1.word_1 - -/*! \brief Base register address of structure AQ_MssIngressInterruptStatusRegister_HHD */ -#define AQ_MssIngressInterruptStatusRegister_HHD_baseRegisterAddress 0x802E -/*! \brief MMD address of structure AQ_MssIngressInterruptStatusRegister_HHD */ -#define AQ_MssIngressInterruptStatusRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressIgpocMissInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ -#define AQ_MssIngressInterruptStatusRegister_HHD_mssIngressIgpocMissInterrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressIgpocMissInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ -#define bits_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressIgpocMissInterrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressIgpocMissInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ -#define word_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressIgpocMissInterrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressTciE_cErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ -#define AQ_MssIngressInterruptStatusRegister_HHD_mssIngressTciE_cErrorInterrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressTciE_cErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ -#define bits_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressTciE_cErrorInterrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressTciE_cErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ -#define word_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressTciE_cErrorInterrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressEccErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ -#define AQ_MssIngressInterruptStatusRegister_HHD_mssIngressEccErrorInterrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressEccErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ -#define bits_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressEccErrorInterrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressEccErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ -#define word_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressEccErrorInterrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressMibSaturationInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ -#define AQ_MssIngressInterruptStatusRegister_HHD_mssIngressMibSaturationInterrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressMibSaturationInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ -#define bits_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressMibSaturationInterrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressMibSaturationInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ -#define word_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressMibSaturationInterrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressReplayErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ -#define AQ_MssIngressInterruptStatusRegister_HHD_mssIngressReplayErrorInterrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressReplayErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ -#define bits_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressReplayErrorInterrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressReplayErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ -#define word_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressReplayErrorInterrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressIcvErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ -#define AQ_MssIngressInterruptStatusRegister_HHD_mssIngressIcvErrorInterrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressIcvErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ -#define bits_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressIcvErrorInterrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressIcvErrorInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ -#define word_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressIcvErrorInterrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaThresholdExpiredInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ -#define AQ_MssIngressInterruptStatusRegister_HHD_mssIngressSaThresholdExpiredInterrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaThresholdExpiredInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ -#define bits_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressSaThresholdExpiredInterrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaThresholdExpiredInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ -#define word_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressSaThresholdExpiredInterrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaExpiredInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ -#define AQ_MssIngressInterruptStatusRegister_HHD_mssIngressSaExpiredInterrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaExpiredInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ -#define bits_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressSaExpiredInterrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaExpiredInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ -#define word_AQ_MssIngressInterruptStatusRegister_HHD_mssIngressSaExpiredInterrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssMasterIngressInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ -#define AQ_MssIngressInterruptStatusRegister_HHD_mssMasterIngressInterrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssMasterIngressInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ -#define bits_AQ_MssIngressInterruptStatusRegister_HHD_mssMasterIngressInterrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssMasterIngressInterrupt in AQ_MssIngressInterruptStatusRegister_HHD */ -#define word_AQ_MssIngressInterruptStatusRegister_HHD_mssMasterIngressInterrupt u0.word_0 - -/*! \brief Base register address of structure AQ_MssIngressInterruptMaskRegister_HHD */ -#define AQ_MssIngressInterruptMaskRegister_HHD_baseRegisterAddress 0x8030 -/*! \brief MMD address of structure AQ_MssIngressInterruptMaskRegister_HHD */ -#define AQ_MssIngressInterruptMaskRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressIgpocMissInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ -#define AQ_MssIngressInterruptMaskRegister_HHD_mssIngressIgpocMissInterruptEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressIgpocMissInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ -#define bits_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressIgpocMissInterruptEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressIgpocMissInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ -#define word_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressIgpocMissInterruptEnable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressTciE_cErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ -#define AQ_MssIngressInterruptMaskRegister_HHD_mssIngressTciE_cErrorInterruptEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressTciE_cErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ -#define bits_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressTciE_cErrorInterruptEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressTciE_cErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ -#define word_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressTciE_cErrorInterruptEnable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressEccErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ -#define AQ_MssIngressInterruptMaskRegister_HHD_mssIngressEccErrorInterruptEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressEccErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ -#define bits_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressEccErrorInterruptEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressEccErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ -#define word_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressEccErrorInterruptEnable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressMibSaturationInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ -#define AQ_MssIngressInterruptMaskRegister_HHD_mssIngressMibSaturationInterruptEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressMibSaturationInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ -#define bits_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressMibSaturationInterruptEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressMibSaturationInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ -#define word_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressMibSaturationInterruptEnable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressReplayErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ -#define AQ_MssIngressInterruptMaskRegister_HHD_mssIngressReplayErrorInterruptEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressReplayErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ -#define bits_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressReplayErrorInterruptEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressReplayErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ -#define word_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressReplayErrorInterruptEnable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressIcvErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ -#define AQ_MssIngressInterruptMaskRegister_HHD_mssIngressIcvErrorInterruptEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressIcvErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ -#define bits_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressIcvErrorInterruptEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressIcvErrorInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ -#define word_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressIcvErrorInterruptEnable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaThresholdExpiredInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ -#define AQ_MssIngressInterruptMaskRegister_HHD_mssIngressSaThresholdExpiredInterruptEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaThresholdExpiredInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ -#define bits_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressSaThresholdExpiredInterruptEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaThresholdExpiredInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ -#define word_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressSaThresholdExpiredInterruptEnable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaExpiredInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ -#define AQ_MssIngressInterruptMaskRegister_HHD_mssIngressSaExpiredInterruptEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaExpiredInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ -#define bits_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressSaExpiredInterruptEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaExpiredInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ -#define word_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressSaExpiredInterruptEnable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressMasterInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ -#define AQ_MssIngressInterruptMaskRegister_HHD_mssIngressMasterInterruptEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressMasterInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ -#define bits_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressMasterInterruptEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressMasterInterruptEnable in AQ_MssIngressInterruptMaskRegister_HHD */ -#define word_AQ_MssIngressInterruptMaskRegister_HHD_mssIngressMasterInterruptEnable u0.word_0 - -/*! \brief Base register address of structure AQ_MssIngressSaIcvErrorStatusRegister_HHD */ -#define AQ_MssIngressSaIcvErrorStatusRegister_HHD_baseRegisterAddress 0x8032 -/*! \brief MMD address of structure AQ_MssIngressSaIcvErrorStatusRegister_HHD */ -#define AQ_MssIngressSaIcvErrorStatusRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaIcvErrorLSW in AQ_MssIngressSaIcvErrorStatusRegister_HHD */ -#define AQ_MssIngressSaIcvErrorStatusRegister_HHD_mssIngressSaIcvErrorLSW 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaIcvErrorLSW in AQ_MssIngressSaIcvErrorStatusRegister_HHD */ -#define bits_AQ_MssIngressSaIcvErrorStatusRegister_HHD_mssIngressSaIcvErrorLSW u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaIcvErrorLSW in AQ_MssIngressSaIcvErrorStatusRegister_HHD */ -#define word_AQ_MssIngressSaIcvErrorStatusRegister_HHD_mssIngressSaIcvErrorLSW u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaIcvErrorMSW in AQ_MssIngressSaIcvErrorStatusRegister_HHD */ -#define AQ_MssIngressSaIcvErrorStatusRegister_HHD_mssIngressSaIcvErrorMSW 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaIcvErrorMSW in AQ_MssIngressSaIcvErrorStatusRegister_HHD */ -#define bits_AQ_MssIngressSaIcvErrorStatusRegister_HHD_mssIngressSaIcvErrorMSW u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaIcvErrorMSW in AQ_MssIngressSaIcvErrorStatusRegister_HHD */ -#define word_AQ_MssIngressSaIcvErrorStatusRegister_HHD_mssIngressSaIcvErrorMSW u1.word_1 - -/*! \brief Base register address of structure AQ_MssIngressSaReplayErrorStatusRegister_HHD */ -#define AQ_MssIngressSaReplayErrorStatusRegister_HHD_baseRegisterAddress 0x8034 -/*! \brief MMD address of structure AQ_MssIngressSaReplayErrorStatusRegister_HHD */ -#define AQ_MssIngressSaReplayErrorStatusRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaReplayErrorLSW in AQ_MssIngressSaReplayErrorStatusRegister_HHD */ -#define AQ_MssIngressSaReplayErrorStatusRegister_HHD_mssIngressSaReplayErrorLSW 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaReplayErrorLSW in AQ_MssIngressSaReplayErrorStatusRegister_HHD */ -#define bits_AQ_MssIngressSaReplayErrorStatusRegister_HHD_mssIngressSaReplayErrorLSW u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaReplayErrorLSW in AQ_MssIngressSaReplayErrorStatusRegister_HHD */ -#define word_AQ_MssIngressSaReplayErrorStatusRegister_HHD_mssIngressSaReplayErrorLSW u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaReplayErrorMSW in AQ_MssIngressSaReplayErrorStatusRegister_HHD */ -#define AQ_MssIngressSaReplayErrorStatusRegister_HHD_mssIngressSaReplayErrorMSW 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaReplayErrorMSW in AQ_MssIngressSaReplayErrorStatusRegister_HHD */ -#define bits_AQ_MssIngressSaReplayErrorStatusRegister_HHD_mssIngressSaReplayErrorMSW u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaReplayErrorMSW in AQ_MssIngressSaReplayErrorStatusRegister_HHD */ -#define word_AQ_MssIngressSaReplayErrorStatusRegister_HHD_mssIngressSaReplayErrorMSW u1.word_1 - -/*! \brief Base register address of structure AQ_MssIngressSaExpiredStatusRegister_HHD */ -#define AQ_MssIngressSaExpiredStatusRegister_HHD_baseRegisterAddress 0x8036 -/*! \brief MMD address of structure AQ_MssIngressSaExpiredStatusRegister_HHD */ -#define AQ_MssIngressSaExpiredStatusRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaExpiredLSW in AQ_MssIngressSaExpiredStatusRegister_HHD */ -#define AQ_MssIngressSaExpiredStatusRegister_HHD_mssIngressSaExpiredLSW 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaExpiredLSW in AQ_MssIngressSaExpiredStatusRegister_HHD */ -#define bits_AQ_MssIngressSaExpiredStatusRegister_HHD_mssIngressSaExpiredLSW u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaExpiredLSW in AQ_MssIngressSaExpiredStatusRegister_HHD */ -#define word_AQ_MssIngressSaExpiredStatusRegister_HHD_mssIngressSaExpiredLSW u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaExpiredMSW in AQ_MssIngressSaExpiredStatusRegister_HHD */ -#define AQ_MssIngressSaExpiredStatusRegister_HHD_mssIngressSaExpiredMSW 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaExpiredMSW in AQ_MssIngressSaExpiredStatusRegister_HHD */ -#define bits_AQ_MssIngressSaExpiredStatusRegister_HHD_mssIngressSaExpiredMSW u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaExpiredMSW in AQ_MssIngressSaExpiredStatusRegister_HHD */ -#define word_AQ_MssIngressSaExpiredStatusRegister_HHD_mssIngressSaExpiredMSW u1.word_1 - -/*! \brief Base register address of structure AQ_MssIngressSaThresholdExpiredStatusRegister_HHD */ -#define AQ_MssIngressSaThresholdExpiredStatusRegister_HHD_baseRegisterAddress 0x8038 -/*! \brief MMD address of structure AQ_MssIngressSaThresholdExpiredStatusRegister_HHD */ -#define AQ_MssIngressSaThresholdExpiredStatusRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaThresholdExpiredLSW in AQ_MssIngressSaThresholdExpiredStatusRegister_HHD */ -#define AQ_MssIngressSaThresholdExpiredStatusRegister_HHD_mssIngressSaThresholdExpiredLSW 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaThresholdExpiredLSW in AQ_MssIngressSaThresholdExpiredStatusRegister_HHD */ -#define bits_AQ_MssIngressSaThresholdExpiredStatusRegister_HHD_mssIngressSaThresholdExpiredLSW u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaThresholdExpiredLSW in AQ_MssIngressSaThresholdExpiredStatusRegister_HHD */ -#define word_AQ_MssIngressSaThresholdExpiredStatusRegister_HHD_mssIngressSaThresholdExpiredLSW u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaThresholdExpiredMSW in AQ_MssIngressSaThresholdExpiredStatusRegister_HHD */ -#define AQ_MssIngressSaThresholdExpiredStatusRegister_HHD_mssIngressSaThresholdExpiredMSW 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaThresholdExpiredMSW in AQ_MssIngressSaThresholdExpiredStatusRegister_HHD */ -#define bits_AQ_MssIngressSaThresholdExpiredStatusRegister_HHD_mssIngressSaThresholdExpiredMSW u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaThresholdExpiredMSW in AQ_MssIngressSaThresholdExpiredStatusRegister_HHD */ -#define word_AQ_MssIngressSaThresholdExpiredStatusRegister_HHD_mssIngressSaThresholdExpiredMSW u1.word_1 - -/*! \brief Base register address of structure AQ_MssIngressEccInterruptStatusRegister_HHD */ -#define AQ_MssIngressEccInterruptStatusRegister_HHD_baseRegisterAddress 0x803A -/*! \brief MMD address of structure AQ_MssIngressEccInterruptStatusRegister_HHD */ -#define AQ_MssIngressEccInterruptStatusRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaEccErrorInterruptLSW in AQ_MssIngressEccInterruptStatusRegister_HHD */ -#define AQ_MssIngressEccInterruptStatusRegister_HHD_mssIngressSaEccErrorInterruptLSW 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaEccErrorInterruptLSW in AQ_MssIngressEccInterruptStatusRegister_HHD */ -#define bits_AQ_MssIngressEccInterruptStatusRegister_HHD_mssIngressSaEccErrorInterruptLSW u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaEccErrorInterruptLSW in AQ_MssIngressEccInterruptStatusRegister_HHD */ -#define word_AQ_MssIngressEccInterruptStatusRegister_HHD_mssIngressSaEccErrorInterruptLSW u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressSaEccErrorInterruptMSW in AQ_MssIngressEccInterruptStatusRegister_HHD */ -#define AQ_MssIngressEccInterruptStatusRegister_HHD_mssIngressSaEccErrorInterruptMSW 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressSaEccErrorInterruptMSW in AQ_MssIngressEccInterruptStatusRegister_HHD */ -#define bits_AQ_MssIngressEccInterruptStatusRegister_HHD_mssIngressSaEccErrorInterruptMSW u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressSaEccErrorInterruptMSW in AQ_MssIngressEccInterruptStatusRegister_HHD */ -#define word_AQ_MssIngressEccInterruptStatusRegister_HHD_mssIngressSaEccErrorInterruptMSW u1.word_1 - -/*! \brief Base register address of structure AQ_MssIngressLutAddressControlRegister_HHD */ -#define AQ_MssIngressLutAddressControlRegister_HHD_baseRegisterAddress 0x8080 -/*! \brief MMD address of structure AQ_MssIngressLutAddressControlRegister_HHD */ -#define AQ_MssIngressLutAddressControlRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutSelect in AQ_MssIngressLutAddressControlRegister_HHD */ -#define AQ_MssIngressLutAddressControlRegister_HHD_mssIngressLutSelect 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutSelect in AQ_MssIngressLutAddressControlRegister_HHD */ -#define bits_AQ_MssIngressLutAddressControlRegister_HHD_mssIngressLutSelect u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutSelect in AQ_MssIngressLutAddressControlRegister_HHD */ -#define word_AQ_MssIngressLutAddressControlRegister_HHD_mssIngressLutSelect u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutAddress in AQ_MssIngressLutAddressControlRegister_HHD */ -#define AQ_MssIngressLutAddressControlRegister_HHD_mssIngressLutAddress 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutAddress in AQ_MssIngressLutAddressControlRegister_HHD */ -#define bits_AQ_MssIngressLutAddressControlRegister_HHD_mssIngressLutAddress u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutAddress in AQ_MssIngressLutAddressControlRegister_HHD */ -#define word_AQ_MssIngressLutAddressControlRegister_HHD_mssIngressLutAddress u0.word_0 - -/*! \brief Base register address of structure AQ_MssIngressLutControlRegister_HHD */ -#define AQ_MssIngressLutControlRegister_HHD_baseRegisterAddress 0x8081 -/*! \brief MMD address of structure AQ_MssIngressLutControlRegister_HHD */ -#define AQ_MssIngressLutControlRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutWrite in AQ_MssIngressLutControlRegister_HHD */ -#define AQ_MssIngressLutControlRegister_HHD_mssIngressLutWrite 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutWrite in AQ_MssIngressLutControlRegister_HHD */ -#define bits_AQ_MssIngressLutControlRegister_HHD_mssIngressLutWrite u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutWrite in AQ_MssIngressLutControlRegister_HHD */ -#define word_AQ_MssIngressLutControlRegister_HHD_mssIngressLutWrite u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutRead in AQ_MssIngressLutControlRegister_HHD */ -#define AQ_MssIngressLutControlRegister_HHD_mssIngressLutRead 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutRead in AQ_MssIngressLutControlRegister_HHD */ -#define bits_AQ_MssIngressLutControlRegister_HHD_mssIngressLutRead u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutRead in AQ_MssIngressLutControlRegister_HHD */ -#define word_AQ_MssIngressLutControlRegister_HHD_mssIngressLutRead u0.word_0 - -/*! \brief Base register address of structure AQ_MssIngressLutDataControlRegister_HHD */ -#define AQ_MssIngressLutDataControlRegister_HHD_baseRegisterAddress 0x80A0 -/*! \brief MMD address of structure AQ_MssIngressLutDataControlRegister_HHD */ -#define AQ_MssIngressLutDataControlRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_0 in AQ_MssIngressLutDataControlRegister_HHD */ -#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_0 in AQ_MssIngressLutDataControlRegister_HHD */ -#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_0 in AQ_MssIngressLutDataControlRegister_HHD */ -#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_1 in AQ_MssIngressLutDataControlRegister_HHD */ -#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_1 in AQ_MssIngressLutDataControlRegister_HHD */ -#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_1 in AQ_MssIngressLutDataControlRegister_HHD */ -#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_1 u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_2 in AQ_MssIngressLutDataControlRegister_HHD */ -#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_2 2 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_2 in AQ_MssIngressLutDataControlRegister_HHD */ -#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_2 u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_2 in AQ_MssIngressLutDataControlRegister_HHD */ -#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_2 u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_3 in AQ_MssIngressLutDataControlRegister_HHD */ -#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_3 3 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_3 in AQ_MssIngressLutDataControlRegister_HHD */ -#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_3 u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_3 in AQ_MssIngressLutDataControlRegister_HHD */ -#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_3 u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_4 in AQ_MssIngressLutDataControlRegister_HHD */ -#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_4 4 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_4 in AQ_MssIngressLutDataControlRegister_HHD */ -#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_4 u4.bits_4 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_4 in AQ_MssIngressLutDataControlRegister_HHD */ -#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_4 u4.word_4 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_5 in AQ_MssIngressLutDataControlRegister_HHD */ -#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_5 5 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_5 in AQ_MssIngressLutDataControlRegister_HHD */ -#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_5 u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_5 in AQ_MssIngressLutDataControlRegister_HHD */ -#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_5 u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_6 in AQ_MssIngressLutDataControlRegister_HHD */ -#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_6 6 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_6 in AQ_MssIngressLutDataControlRegister_HHD */ -#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_6 u6.bits_6 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_6 in AQ_MssIngressLutDataControlRegister_HHD */ -#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_6 u6.word_6 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_7 in AQ_MssIngressLutDataControlRegister_HHD */ -#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_7 7 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_7 in AQ_MssIngressLutDataControlRegister_HHD */ -#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_7 u7.bits_7 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_7 in AQ_MssIngressLutDataControlRegister_HHD */ -#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_7 u7.word_7 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_8 in AQ_MssIngressLutDataControlRegister_HHD */ -#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_8 8 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_8 in AQ_MssIngressLutDataControlRegister_HHD */ -#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_8 u8.bits_8 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_8 in AQ_MssIngressLutDataControlRegister_HHD */ -#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_8 u8.word_8 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_9 in AQ_MssIngressLutDataControlRegister_HHD */ -#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_9 9 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_9 in AQ_MssIngressLutDataControlRegister_HHD */ -#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_9 u9.bits_9 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_9 in AQ_MssIngressLutDataControlRegister_HHD */ -#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_9 u9.word_9 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_10 in AQ_MssIngressLutDataControlRegister_HHD */ -#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_10 10 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_10 in AQ_MssIngressLutDataControlRegister_HHD */ -#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_10 u10.bits_10 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_10 in AQ_MssIngressLutDataControlRegister_HHD */ -#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_10 u10.word_10 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_11 in AQ_MssIngressLutDataControlRegister_HHD */ -#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_11 11 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_11 in AQ_MssIngressLutDataControlRegister_HHD */ -#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_11 u11.bits_11 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_11 in AQ_MssIngressLutDataControlRegister_HHD */ -#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_11 u11.word_11 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_12 in AQ_MssIngressLutDataControlRegister_HHD */ -#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_12 12 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_12 in AQ_MssIngressLutDataControlRegister_HHD */ -#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_12 u12.bits_12 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_12 in AQ_MssIngressLutDataControlRegister_HHD */ -#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_12 u12.word_12 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_13 in AQ_MssIngressLutDataControlRegister_HHD */ -#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_13 13 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_13 in AQ_MssIngressLutDataControlRegister_HHD */ -#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_13 u13.bits_13 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_13 in AQ_MssIngressLutDataControlRegister_HHD */ -#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_13 u13.word_13 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_14 in AQ_MssIngressLutDataControlRegister_HHD */ -#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_14 14 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_14 in AQ_MssIngressLutDataControlRegister_HHD */ -#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_14 u14.bits_14 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_14 in AQ_MssIngressLutDataControlRegister_HHD */ -#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_14 u14.word_14 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_15 in AQ_MssIngressLutDataControlRegister_HHD */ -#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_15 15 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_15 in AQ_MssIngressLutDataControlRegister_HHD */ -#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_15 u15.bits_15 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_15 in AQ_MssIngressLutDataControlRegister_HHD */ -#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_15 u15.word_15 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_16 in AQ_MssIngressLutDataControlRegister_HHD */ -#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_16 16 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_16 in AQ_MssIngressLutDataControlRegister_HHD */ -#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_16 u16.bits_16 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_16 in AQ_MssIngressLutDataControlRegister_HHD */ -#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_16 u16.word_16 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_17 in AQ_MssIngressLutDataControlRegister_HHD */ -#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_17 17 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_17 in AQ_MssIngressLutDataControlRegister_HHD */ -#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_17 u17.bits_17 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_17 in AQ_MssIngressLutDataControlRegister_HHD */ -#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_17 u17.word_17 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_18 in AQ_MssIngressLutDataControlRegister_HHD */ -#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_18 18 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_18 in AQ_MssIngressLutDataControlRegister_HHD */ -#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_18 u18.bits_18 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_18 in AQ_MssIngressLutDataControlRegister_HHD */ -#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_18 u18.word_18 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_19 in AQ_MssIngressLutDataControlRegister_HHD */ -#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_19 19 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_19 in AQ_MssIngressLutDataControlRegister_HHD */ -#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_19 u19.bits_19 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_19 in AQ_MssIngressLutDataControlRegister_HHD */ -#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_19 u19.word_19 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_20 in AQ_MssIngressLutDataControlRegister_HHD */ -#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_20 20 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_20 in AQ_MssIngressLutDataControlRegister_HHD */ -#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_20 u20.bits_20 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_20 in AQ_MssIngressLutDataControlRegister_HHD */ -#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_20 u20.word_20 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_21 in AQ_MssIngressLutDataControlRegister_HHD */ -#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_21 21 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_21 in AQ_MssIngressLutDataControlRegister_HHD */ -#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_21 u21.bits_21 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_21 in AQ_MssIngressLutDataControlRegister_HHD */ -#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_21 u21.word_21 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_22 in AQ_MssIngressLutDataControlRegister_HHD */ -#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_22 22 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_22 in AQ_MssIngressLutDataControlRegister_HHD */ -#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_22 u22.bits_22 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_22 in AQ_MssIngressLutDataControlRegister_HHD */ -#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_22 u22.word_22 -/*! \brief Preprocessor variable to relate field to word number in structure mssIngressLutData_23 in AQ_MssIngressLutDataControlRegister_HHD */ -#define AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_23 23 -/*! \brief Preprocessor variable to relate field to bit position in structure mssIngressLutData_23 in AQ_MssIngressLutDataControlRegister_HHD */ -#define bits_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_23 u23.bits_23 -/*! \brief Preprocessor variable to relate field to word position in structure mssIngressLutData_23 in AQ_MssIngressLutDataControlRegister_HHD */ -#define word_AQ_MssIngressLutDataControlRegister_HHD_mssIngressLutData_23 u23.word_23 - -/*! \brief Base register address of structure AQ_MsmLineGeneralControlRegister_HHD */ -#define AQ_MsmLineGeneralControlRegister_HHD_baseRegisterAddress 0x9004 -/*! \brief MMD address of structure AQ_MsmLineGeneralControlRegister_HHD */ -#define AQ_MsmLineGeneralControlRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmLinePhyTxEnable in AQ_MsmLineGeneralControlRegister_HHD */ -#define AQ_MsmLineGeneralControlRegister_HHD_msmLinePhyTxEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLinePhyTxEnable in AQ_MsmLineGeneralControlRegister_HHD */ -#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLinePhyTxEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLinePhyTxEnable in AQ_MsmLineGeneralControlRegister_HHD */ -#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLinePhyTxEnable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxErrorDiscard in AQ_MsmLineGeneralControlRegister_HHD */ -#define AQ_MsmLineGeneralControlRegister_HHD_msmLineRxErrorDiscard 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxErrorDiscard in AQ_MsmLineGeneralControlRegister_HHD */ -#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineRxErrorDiscard u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxErrorDiscard in AQ_MsmLineGeneralControlRegister_HHD */ -#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineRxErrorDiscard u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineControlFrameEnable in AQ_MsmLineGeneralControlRegister_HHD */ -#define AQ_MsmLineGeneralControlRegister_HHD_msmLineControlFrameEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineControlFrameEnable in AQ_MsmLineGeneralControlRegister_HHD */ -#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineControlFrameEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineControlFrameEnable in AQ_MsmLineGeneralControlRegister_HHD */ -#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineControlFrameEnable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineSoftReset in AQ_MsmLineGeneralControlRegister_HHD */ -#define AQ_MsmLineGeneralControlRegister_HHD_msmLineSoftReset 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineSoftReset in AQ_MsmLineGeneralControlRegister_HHD */ -#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineSoftReset u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineSoftReset in AQ_MsmLineGeneralControlRegister_HHD */ -#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineSoftReset u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxPadEnable in AQ_MsmLineGeneralControlRegister_HHD */ -#define AQ_MsmLineGeneralControlRegister_HHD_msmLineTxPadEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxPadEnable in AQ_MsmLineGeneralControlRegister_HHD */ -#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineTxPadEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxPadEnable in AQ_MsmLineGeneralControlRegister_HHD */ -#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineTxPadEnable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxCrcAppend in AQ_MsmLineGeneralControlRegister_HHD */ -#define AQ_MsmLineGeneralControlRegister_HHD_msmLineTxCrcAppend 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxCrcAppend in AQ_MsmLineGeneralControlRegister_HHD */ -#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineTxCrcAppend u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxCrcAppend in AQ_MsmLineGeneralControlRegister_HHD */ -#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineTxCrcAppend u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxAddressInsertEnable in AQ_MsmLineGeneralControlRegister_HHD */ -#define AQ_MsmLineGeneralControlRegister_HHD_msmLineTxAddressInsertEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxAddressInsertEnable in AQ_MsmLineGeneralControlRegister_HHD */ -#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineTxAddressInsertEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxAddressInsertEnable in AQ_MsmLineGeneralControlRegister_HHD */ -#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineTxAddressInsertEnable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLinePauseIgnore in AQ_MsmLineGeneralControlRegister_HHD */ -#define AQ_MsmLineGeneralControlRegister_HHD_msmLinePauseIgnore 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLinePauseIgnore in AQ_MsmLineGeneralControlRegister_HHD */ -#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLinePauseIgnore u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLinePauseIgnore in AQ_MsmLineGeneralControlRegister_HHD */ -#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLinePauseIgnore u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLinePauseForward in AQ_MsmLineGeneralControlRegister_HHD */ -#define AQ_MsmLineGeneralControlRegister_HHD_msmLinePauseForward 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLinePauseForward in AQ_MsmLineGeneralControlRegister_HHD */ -#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLinePauseForward u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLinePauseForward in AQ_MsmLineGeneralControlRegister_HHD */ -#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLinePauseForward u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineCrcForward in AQ_MsmLineGeneralControlRegister_HHD */ -#define AQ_MsmLineGeneralControlRegister_HHD_msmLineCrcForward 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineCrcForward in AQ_MsmLineGeneralControlRegister_HHD */ -#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineCrcForward u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineCrcForward in AQ_MsmLineGeneralControlRegister_HHD */ -#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineCrcForward u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLinePadEnable in AQ_MsmLineGeneralControlRegister_HHD */ -#define AQ_MsmLineGeneralControlRegister_HHD_msmLinePadEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLinePadEnable in AQ_MsmLineGeneralControlRegister_HHD */ -#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLinePadEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLinePadEnable in AQ_MsmLineGeneralControlRegister_HHD */ -#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLinePadEnable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLinePromiscuousMode in AQ_MsmLineGeneralControlRegister_HHD */ -#define AQ_MsmLineGeneralControlRegister_HHD_msmLinePromiscuousMode 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLinePromiscuousMode in AQ_MsmLineGeneralControlRegister_HHD */ -#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLinePromiscuousMode u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLinePromiscuousMode in AQ_MsmLineGeneralControlRegister_HHD */ -#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLinePromiscuousMode u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineWanMode in AQ_MsmLineGeneralControlRegister_HHD */ -#define AQ_MsmLineGeneralControlRegister_HHD_msmLineWanMode 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineWanMode in AQ_MsmLineGeneralControlRegister_HHD */ -#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineWanMode u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineWanMode in AQ_MsmLineGeneralControlRegister_HHD */ -#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineWanMode u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxEnable in AQ_MsmLineGeneralControlRegister_HHD */ -#define AQ_MsmLineGeneralControlRegister_HHD_msmLineRxEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxEnable in AQ_MsmLineGeneralControlRegister_HHD */ -#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineRxEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxEnable in AQ_MsmLineGeneralControlRegister_HHD */ -#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineRxEnable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxEnable in AQ_MsmLineGeneralControlRegister_HHD */ -#define AQ_MsmLineGeneralControlRegister_HHD_msmLineTxEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxEnable in AQ_MsmLineGeneralControlRegister_HHD */ -#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineTxEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxEnable in AQ_MsmLineGeneralControlRegister_HHD */ -#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineTxEnable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxLowPowerIdleEnable in AQ_MsmLineGeneralControlRegister_HHD */ -#define AQ_MsmLineGeneralControlRegister_HHD_msmLineTxLowPowerIdleEnable 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxLowPowerIdleEnable in AQ_MsmLineGeneralControlRegister_HHD */ -#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineTxLowPowerIdleEnable u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxLowPowerIdleEnable in AQ_MsmLineGeneralControlRegister_HHD */ -#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineTxLowPowerIdleEnable u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineSfdCheckDisable in AQ_MsmLineGeneralControlRegister_HHD */ -#define AQ_MsmLineGeneralControlRegister_HHD_msmLineSfdCheckDisable 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineSfdCheckDisable in AQ_MsmLineGeneralControlRegister_HHD */ -#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineSfdCheckDisable u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineSfdCheckDisable in AQ_MsmLineGeneralControlRegister_HHD */ -#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineSfdCheckDisable u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure msmLinePriorityFlowControlEnable in AQ_MsmLineGeneralControlRegister_HHD */ -#define AQ_MsmLineGeneralControlRegister_HHD_msmLinePriorityFlowControlEnable 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLinePriorityFlowControlEnable in AQ_MsmLineGeneralControlRegister_HHD */ -#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLinePriorityFlowControlEnable u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmLinePriorityFlowControlEnable in AQ_MsmLineGeneralControlRegister_HHD */ -#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLinePriorityFlowControlEnable u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineIdleColumnCountExtend in AQ_MsmLineGeneralControlRegister_HHD */ -#define AQ_MsmLineGeneralControlRegister_HHD_msmLineIdleColumnCountExtend 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineIdleColumnCountExtend in AQ_MsmLineGeneralControlRegister_HHD */ -#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineIdleColumnCountExtend u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineIdleColumnCountExtend in AQ_MsmLineGeneralControlRegister_HHD */ -#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineIdleColumnCountExtend u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineLengthCheckDisable in AQ_MsmLineGeneralControlRegister_HHD */ -#define AQ_MsmLineGeneralControlRegister_HHD_msmLineLengthCheckDisable 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineLengthCheckDisable in AQ_MsmLineGeneralControlRegister_HHD */ -#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineLengthCheckDisable u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineLengthCheckDisable in AQ_MsmLineGeneralControlRegister_HHD */ -#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineLengthCheckDisable u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineForceSendIdle in AQ_MsmLineGeneralControlRegister_HHD */ -#define AQ_MsmLineGeneralControlRegister_HHD_msmLineForceSendIdle 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineForceSendIdle in AQ_MsmLineGeneralControlRegister_HHD */ -#define bits_AQ_MsmLineGeneralControlRegister_HHD_msmLineForceSendIdle u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineForceSendIdle in AQ_MsmLineGeneralControlRegister_HHD */ -#define word_AQ_MsmLineGeneralControlRegister_HHD_msmLineForceSendIdle u1.word_1 - -/*! \brief Base register address of structure AQ_MsmLineFifoControlRegister_HHD */ -#define AQ_MsmLineFifoControlRegister_HHD_baseRegisterAddress 0x900E -/*! \brief MMD address of structure AQ_MsmLineFifoControlRegister_HHD */ -#define AQ_MsmLineFifoControlRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxFifoFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ -#define AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoFullThreshold 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxFifoFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ -#define bits_AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoFullThreshold u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxFifoFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ -#define word_AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoFullThreshold u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxFifoEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ -#define AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoEmptyThreshold 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxFifoEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ -#define bits_AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoEmptyThreshold u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxFifoEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ -#define word_AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoEmptyThreshold u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxFifoFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ -#define AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoFullThreshold 2 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxFifoFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ -#define bits_AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoFullThreshold u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxFifoFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ -#define word_AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoFullThreshold u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxFifoEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ -#define AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoEmptyThreshold 3 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxFifoEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ -#define bits_AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoEmptyThreshold u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxFifoEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ -#define word_AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoEmptyThreshold u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxFifoAlmostFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ -#define AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoAlmostFullThreshold 4 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxFifoAlmostFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ -#define bits_AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoAlmostFullThreshold u4.bits_4 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxFifoAlmostFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ -#define word_AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoAlmostFullThreshold u4.word_4 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxFifoAlmostEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ -#define AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoAlmostEmptyThreshold 5 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxFifoAlmostEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ -#define bits_AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoAlmostEmptyThreshold u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxFifoAlmostEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ -#define word_AQ_MsmLineFifoControlRegister_HHD_msmLineRxFifoAlmostEmptyThreshold u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxFifoAlmostFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ -#define AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoAlmostFullThreshold 6 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxFifoAlmostFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ -#define bits_AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoAlmostFullThreshold u6.bits_6 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxFifoAlmostFullThreshold in AQ_MsmLineFifoControlRegister_HHD */ -#define word_AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoAlmostFullThreshold u6.word_6 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxFifoAlmostEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ -#define AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoAlmostEmptyThreshold 7 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxFifoAlmostEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ -#define bits_AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoAlmostEmptyThreshold u7.bits_7 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxFifoAlmostEmptyThreshold in AQ_MsmLineFifoControlRegister_HHD */ -#define word_AQ_MsmLineFifoControlRegister_HHD_msmLineTxFifoAlmostEmptyThreshold u7.word_7 - -/*! \brief Base register address of structure AQ_MsmLineGeneralStatusRegister_HHD */ -#define AQ_MsmLineGeneralStatusRegister_HHD_baseRegisterAddress 0x9020 -/*! \brief MMD address of structure AQ_MsmLineGeneralStatusRegister_HHD */ -#define AQ_MsmLineGeneralStatusRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxFifoEmpty in AQ_MsmLineGeneralStatusRegister_HHD */ -#define AQ_MsmLineGeneralStatusRegister_HHD_msmLineTxFifoEmpty 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxFifoEmpty in AQ_MsmLineGeneralStatusRegister_HHD */ -#define bits_AQ_MsmLineGeneralStatusRegister_HHD_msmLineTxFifoEmpty u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxFifoEmpty in AQ_MsmLineGeneralStatusRegister_HHD */ -#define word_AQ_MsmLineGeneralStatusRegister_HHD_msmLineTxFifoEmpty u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxLowPowerIdle in AQ_MsmLineGeneralStatusRegister_HHD */ -#define AQ_MsmLineGeneralStatusRegister_HHD_msmLineRxLowPowerIdle 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxLowPowerIdle in AQ_MsmLineGeneralStatusRegister_HHD */ -#define bits_AQ_MsmLineGeneralStatusRegister_HHD_msmLineRxLowPowerIdle u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxLowPowerIdle in AQ_MsmLineGeneralStatusRegister_HHD */ -#define word_AQ_MsmLineGeneralStatusRegister_HHD_msmLineRxLowPowerIdle u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineTimestampAvailable in AQ_MsmLineGeneralStatusRegister_HHD */ -#define AQ_MsmLineGeneralStatusRegister_HHD_msmLineTimestampAvailable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTimestampAvailable in AQ_MsmLineGeneralStatusRegister_HHD */ -#define bits_AQ_MsmLineGeneralStatusRegister_HHD_msmLineTimestampAvailable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineTimestampAvailable in AQ_MsmLineGeneralStatusRegister_HHD */ -#define word_AQ_MsmLineGeneralStatusRegister_HHD_msmLineTimestampAvailable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLinePhyLossOfSignal in AQ_MsmLineGeneralStatusRegister_HHD */ -#define AQ_MsmLineGeneralStatusRegister_HHD_msmLinePhyLossOfSignal 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLinePhyLossOfSignal in AQ_MsmLineGeneralStatusRegister_HHD */ -#define bits_AQ_MsmLineGeneralStatusRegister_HHD_msmLinePhyLossOfSignal u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLinePhyLossOfSignal in AQ_MsmLineGeneralStatusRegister_HHD */ -#define word_AQ_MsmLineGeneralStatusRegister_HHD_msmLinePhyLossOfSignal u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxRemoteFault in AQ_MsmLineGeneralStatusRegister_HHD */ -#define AQ_MsmLineGeneralStatusRegister_HHD_msmLineRxRemoteFault 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxRemoteFault in AQ_MsmLineGeneralStatusRegister_HHD */ -#define bits_AQ_MsmLineGeneralStatusRegister_HHD_msmLineRxRemoteFault u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxRemoteFault in AQ_MsmLineGeneralStatusRegister_HHD */ -#define word_AQ_MsmLineGeneralStatusRegister_HHD_msmLineRxRemoteFault u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxLocalFault in AQ_MsmLineGeneralStatusRegister_HHD */ -#define AQ_MsmLineGeneralStatusRegister_HHD_msmLineRxLocalFault 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxLocalFault in AQ_MsmLineGeneralStatusRegister_HHD */ -#define bits_AQ_MsmLineGeneralStatusRegister_HHD_msmLineRxLocalFault u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxLocalFault in AQ_MsmLineGeneralStatusRegister_HHD */ -#define word_AQ_MsmLineGeneralStatusRegister_HHD_msmLineRxLocalFault u0.word_0 - -/*! \brief Base register address of structure AQ_MsmLineTxIpgControlRegister_HHD */ -#define AQ_MsmLineTxIpgControlRegister_HHD_baseRegisterAddress 0x9022 -/*! \brief MMD address of structure AQ_MsmLineTxIpgControlRegister_HHD */ -#define AQ_MsmLineTxIpgControlRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxIpgLength in AQ_MsmLineTxIpgControlRegister_HHD */ -#define AQ_MsmLineTxIpgControlRegister_HHD_msmLineTxIpgLength 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxIpgLength in AQ_MsmLineTxIpgControlRegister_HHD */ -#define bits_AQ_MsmLineTxIpgControlRegister_HHD_msmLineTxIpgLength u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxIpgLength in AQ_MsmLineTxIpgControlRegister_HHD */ -#define word_AQ_MsmLineTxIpgControlRegister_HHD_msmLineTxIpgLength u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxIpgReserved in AQ_MsmLineTxIpgControlRegister_HHD */ -#define AQ_MsmLineTxIpgControlRegister_HHD_msmLineTxIpgReserved 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxIpgReserved in AQ_MsmLineTxIpgControlRegister_HHD */ -#define bits_AQ_MsmLineTxIpgControlRegister_HHD_msmLineTxIpgReserved u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxIpgReserved in AQ_MsmLineTxIpgControlRegister_HHD */ -#define word_AQ_MsmLineTxIpgControlRegister_HHD_msmLineTxIpgReserved u1.word_1 - -/*! \brief Base register address of structure AQ_MsmLineTxGoodFramesCounterRegister_HHD */ -#define AQ_MsmLineTxGoodFramesCounterRegister_HHD_baseRegisterAddress 0x9040 -/*! \brief MMD address of structure AQ_MsmLineTxGoodFramesCounterRegister_HHD */ -#define AQ_MsmLineTxGoodFramesCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxGoodFramesCounter_0 in AQ_MsmLineTxGoodFramesCounterRegister_HHD */ -#define AQ_MsmLineTxGoodFramesCounterRegister_HHD_msmLineTxGoodFramesCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxGoodFramesCounter_0 in AQ_MsmLineTxGoodFramesCounterRegister_HHD */ -#define bits_AQ_MsmLineTxGoodFramesCounterRegister_HHD_msmLineTxGoodFramesCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxGoodFramesCounter_0 in AQ_MsmLineTxGoodFramesCounterRegister_HHD */ -#define word_AQ_MsmLineTxGoodFramesCounterRegister_HHD_msmLineTxGoodFramesCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxGoodFramesCounter_1 in AQ_MsmLineTxGoodFramesCounterRegister_HHD */ -#define AQ_MsmLineTxGoodFramesCounterRegister_HHD_msmLineTxGoodFramesCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxGoodFramesCounter_1 in AQ_MsmLineTxGoodFramesCounterRegister_HHD */ -#define bits_AQ_MsmLineTxGoodFramesCounterRegister_HHD_msmLineTxGoodFramesCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxGoodFramesCounter_1 in AQ_MsmLineTxGoodFramesCounterRegister_HHD */ -#define word_AQ_MsmLineTxGoodFramesCounterRegister_HHD_msmLineTxGoodFramesCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmLineRxGoodFramesCounterRegister_HHD */ -#define AQ_MsmLineRxGoodFramesCounterRegister_HHD_baseRegisterAddress 0x9044 -/*! \brief MMD address of structure AQ_MsmLineRxGoodFramesCounterRegister_HHD */ -#define AQ_MsmLineRxGoodFramesCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxGoodFramesCounter_0 in AQ_MsmLineRxGoodFramesCounterRegister_HHD */ -#define AQ_MsmLineRxGoodFramesCounterRegister_HHD_msmLineRxGoodFramesCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxGoodFramesCounter_0 in AQ_MsmLineRxGoodFramesCounterRegister_HHD */ -#define bits_AQ_MsmLineRxGoodFramesCounterRegister_HHD_msmLineRxGoodFramesCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxGoodFramesCounter_0 in AQ_MsmLineRxGoodFramesCounterRegister_HHD */ -#define word_AQ_MsmLineRxGoodFramesCounterRegister_HHD_msmLineRxGoodFramesCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxGoodFramesCounter_1 in AQ_MsmLineRxGoodFramesCounterRegister_HHD */ -#define AQ_MsmLineRxGoodFramesCounterRegister_HHD_msmLineRxGoodFramesCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxGoodFramesCounter_1 in AQ_MsmLineRxGoodFramesCounterRegister_HHD */ -#define bits_AQ_MsmLineRxGoodFramesCounterRegister_HHD_msmLineRxGoodFramesCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxGoodFramesCounter_1 in AQ_MsmLineRxGoodFramesCounterRegister_HHD */ -#define word_AQ_MsmLineRxGoodFramesCounterRegister_HHD_msmLineRxGoodFramesCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmLineRxFcsErrorsCounterRegister_HHD */ -#define AQ_MsmLineRxFcsErrorsCounterRegister_HHD_baseRegisterAddress 0x9048 -/*! \brief MMD address of structure AQ_MsmLineRxFcsErrorsCounterRegister_HHD */ -#define AQ_MsmLineRxFcsErrorsCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmLineFcsErrorCounter_0 in AQ_MsmLineRxFcsErrorsCounterRegister_HHD */ -#define AQ_MsmLineRxFcsErrorsCounterRegister_HHD_msmLineFcsErrorCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineFcsErrorCounter_0 in AQ_MsmLineRxFcsErrorsCounterRegister_HHD */ -#define bits_AQ_MsmLineRxFcsErrorsCounterRegister_HHD_msmLineFcsErrorCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineFcsErrorCounter_0 in AQ_MsmLineRxFcsErrorsCounterRegister_HHD */ -#define word_AQ_MsmLineRxFcsErrorsCounterRegister_HHD_msmLineFcsErrorCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineFcsErrorCounter_1 in AQ_MsmLineRxFcsErrorsCounterRegister_HHD */ -#define AQ_MsmLineRxFcsErrorsCounterRegister_HHD_msmLineFcsErrorCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineFcsErrorCounter_1 in AQ_MsmLineRxFcsErrorsCounterRegister_HHD */ -#define bits_AQ_MsmLineRxFcsErrorsCounterRegister_HHD_msmLineFcsErrorCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineFcsErrorCounter_1 in AQ_MsmLineRxFcsErrorsCounterRegister_HHD */ -#define word_AQ_MsmLineRxFcsErrorsCounterRegister_HHD_msmLineFcsErrorCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD */ -#define AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD_baseRegisterAddress 0x904C -/*! \brief MMD address of structure AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD */ -#define AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmLineAlignmentErrorCounter_0 in AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD */ -#define AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD_msmLineAlignmentErrorCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineAlignmentErrorCounter_0 in AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD */ -#define bits_AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD_msmLineAlignmentErrorCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineAlignmentErrorCounter_0 in AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD */ -#define word_AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD_msmLineAlignmentErrorCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineAlignmentErrorCounter_1 in AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD */ -#define AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD_msmLineAlignmentErrorCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineAlignmentErrorCounter_1 in AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD */ -#define bits_AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD_msmLineAlignmentErrorCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineAlignmentErrorCounter_1 in AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD */ -#define word_AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD_msmLineAlignmentErrorCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmLineTxPauseFramesCounterRegister_HHD */ -#define AQ_MsmLineTxPauseFramesCounterRegister_HHD_baseRegisterAddress 0x9050 -/*! \brief MMD address of structure AQ_MsmLineTxPauseFramesCounterRegister_HHD */ -#define AQ_MsmLineTxPauseFramesCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxPauseFramesCounter_0 in AQ_MsmLineTxPauseFramesCounterRegister_HHD */ -#define AQ_MsmLineTxPauseFramesCounterRegister_HHD_msmLineTxPauseFramesCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxPauseFramesCounter_0 in AQ_MsmLineTxPauseFramesCounterRegister_HHD */ -#define bits_AQ_MsmLineTxPauseFramesCounterRegister_HHD_msmLineTxPauseFramesCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxPauseFramesCounter_0 in AQ_MsmLineTxPauseFramesCounterRegister_HHD */ -#define word_AQ_MsmLineTxPauseFramesCounterRegister_HHD_msmLineTxPauseFramesCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxPauseFramesCounter_1 in AQ_MsmLineTxPauseFramesCounterRegister_HHD */ -#define AQ_MsmLineTxPauseFramesCounterRegister_HHD_msmLineTxPauseFramesCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxPauseFramesCounter_1 in AQ_MsmLineTxPauseFramesCounterRegister_HHD */ -#define bits_AQ_MsmLineTxPauseFramesCounterRegister_HHD_msmLineTxPauseFramesCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxPauseFramesCounter_1 in AQ_MsmLineTxPauseFramesCounterRegister_HHD */ -#define word_AQ_MsmLineTxPauseFramesCounterRegister_HHD_msmLineTxPauseFramesCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmLineRxPauseFramesCounterRegister_HHD */ -#define AQ_MsmLineRxPauseFramesCounterRegister_HHD_baseRegisterAddress 0x9054 -/*! \brief MMD address of structure AQ_MsmLineRxPauseFramesCounterRegister_HHD */ -#define AQ_MsmLineRxPauseFramesCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxPauseFramesCounter_0 in AQ_MsmLineRxPauseFramesCounterRegister_HHD */ -#define AQ_MsmLineRxPauseFramesCounterRegister_HHD_msmLineRxPauseFramesCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxPauseFramesCounter_0 in AQ_MsmLineRxPauseFramesCounterRegister_HHD */ -#define bits_AQ_MsmLineRxPauseFramesCounterRegister_HHD_msmLineRxPauseFramesCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxPauseFramesCounter_0 in AQ_MsmLineRxPauseFramesCounterRegister_HHD */ -#define word_AQ_MsmLineRxPauseFramesCounterRegister_HHD_msmLineRxPauseFramesCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxPauseFramesCounter_1 in AQ_MsmLineRxPauseFramesCounterRegister_HHD */ -#define AQ_MsmLineRxPauseFramesCounterRegister_HHD_msmLineRxPauseFramesCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxPauseFramesCounter_1 in AQ_MsmLineRxPauseFramesCounterRegister_HHD */ -#define bits_AQ_MsmLineRxPauseFramesCounterRegister_HHD_msmLineRxPauseFramesCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxPauseFramesCounter_1 in AQ_MsmLineRxPauseFramesCounterRegister_HHD */ -#define word_AQ_MsmLineRxPauseFramesCounterRegister_HHD_msmLineRxPauseFramesCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmLineRxTooLongErrorsCounterRegister_HHD */ -#define AQ_MsmLineRxTooLongErrorsCounterRegister_HHD_baseRegisterAddress 0x9058 -/*! \brief MMD address of structure AQ_MsmLineRxTooLongErrorsCounterRegister_HHD */ -#define AQ_MsmLineRxTooLongErrorsCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxTooLongErrorsCounter_0 in AQ_MsmLineRxTooLongErrorsCounterRegister_HHD */ -#define AQ_MsmLineRxTooLongErrorsCounterRegister_HHD_msmLineRxTooLongErrorsCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxTooLongErrorsCounter_0 in AQ_MsmLineRxTooLongErrorsCounterRegister_HHD */ -#define bits_AQ_MsmLineRxTooLongErrorsCounterRegister_HHD_msmLineRxTooLongErrorsCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxTooLongErrorsCounter_0 in AQ_MsmLineRxTooLongErrorsCounterRegister_HHD */ -#define word_AQ_MsmLineRxTooLongErrorsCounterRegister_HHD_msmLineRxTooLongErrorsCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxTooLongErrorsCounter_1 in AQ_MsmLineRxTooLongErrorsCounterRegister_HHD */ -#define AQ_MsmLineRxTooLongErrorsCounterRegister_HHD_msmLineRxTooLongErrorsCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxTooLongErrorsCounter_1 in AQ_MsmLineRxTooLongErrorsCounterRegister_HHD */ -#define bits_AQ_MsmLineRxTooLongErrorsCounterRegister_HHD_msmLineRxTooLongErrorsCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxTooLongErrorsCounter_1 in AQ_MsmLineRxTooLongErrorsCounterRegister_HHD */ -#define word_AQ_MsmLineRxTooLongErrorsCounterRegister_HHD_msmLineRxTooLongErrorsCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD */ -#define AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD_baseRegisterAddress 0x905C -/*! \brief MMD address of structure AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD */ -#define AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxInRangeLengthErrorsCounter_0 in AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD */ -#define AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD_msmLineRxInRangeLengthErrorsCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxInRangeLengthErrorsCounter_0 in AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD */ -#define bits_AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD_msmLineRxInRangeLengthErrorsCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxInRangeLengthErrorsCounter_0 in AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD */ -#define word_AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD_msmLineRxInRangeLengthErrorsCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxInRangeLengthErrorsCounter_1 in AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD */ -#define AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD_msmLineRxInRangeLengthErrorsCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxInRangeLengthErrorsCounter_1 in AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD */ -#define bits_AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD_msmLineRxInRangeLengthErrorsCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxInRangeLengthErrorsCounter_1 in AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD */ -#define word_AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD_msmLineRxInRangeLengthErrorsCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmLineTxVlanFramesCounterRegister_HHD */ -#define AQ_MsmLineTxVlanFramesCounterRegister_HHD_baseRegisterAddress 0x9060 -/*! \brief MMD address of structure AQ_MsmLineTxVlanFramesCounterRegister_HHD */ -#define AQ_MsmLineTxVlanFramesCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxVlanFramesCounter_0 in AQ_MsmLineTxVlanFramesCounterRegister_HHD */ -#define AQ_MsmLineTxVlanFramesCounterRegister_HHD_msmLineTxVlanFramesCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxVlanFramesCounter_0 in AQ_MsmLineTxVlanFramesCounterRegister_HHD */ -#define bits_AQ_MsmLineTxVlanFramesCounterRegister_HHD_msmLineTxVlanFramesCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxVlanFramesCounter_0 in AQ_MsmLineTxVlanFramesCounterRegister_HHD */ -#define word_AQ_MsmLineTxVlanFramesCounterRegister_HHD_msmLineTxVlanFramesCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxVlanFramesCounter_1 in AQ_MsmLineTxVlanFramesCounterRegister_HHD */ -#define AQ_MsmLineTxVlanFramesCounterRegister_HHD_msmLineTxVlanFramesCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxVlanFramesCounter_1 in AQ_MsmLineTxVlanFramesCounterRegister_HHD */ -#define bits_AQ_MsmLineTxVlanFramesCounterRegister_HHD_msmLineTxVlanFramesCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxVlanFramesCounter_1 in AQ_MsmLineTxVlanFramesCounterRegister_HHD */ -#define word_AQ_MsmLineTxVlanFramesCounterRegister_HHD_msmLineTxVlanFramesCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmLineRxVlanFramesCounterRegister_HHD */ -#define AQ_MsmLineRxVlanFramesCounterRegister_HHD_baseRegisterAddress 0x9064 -/*! \brief MMD address of structure AQ_MsmLineRxVlanFramesCounterRegister_HHD */ -#define AQ_MsmLineRxVlanFramesCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxVlanFramesCounter_0 in AQ_MsmLineRxVlanFramesCounterRegister_HHD */ -#define AQ_MsmLineRxVlanFramesCounterRegister_HHD_msmLineRxVlanFramesCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxVlanFramesCounter_0 in AQ_MsmLineRxVlanFramesCounterRegister_HHD */ -#define bits_AQ_MsmLineRxVlanFramesCounterRegister_HHD_msmLineRxVlanFramesCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxVlanFramesCounter_0 in AQ_MsmLineRxVlanFramesCounterRegister_HHD */ -#define word_AQ_MsmLineRxVlanFramesCounterRegister_HHD_msmLineRxVlanFramesCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxVlanFramesCounter_1 in AQ_MsmLineRxVlanFramesCounterRegister_HHD */ -#define AQ_MsmLineRxVlanFramesCounterRegister_HHD_msmLineRxVlanFramesCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxVlanFramesCounter_1 in AQ_MsmLineRxVlanFramesCounterRegister_HHD */ -#define bits_AQ_MsmLineRxVlanFramesCounterRegister_HHD_msmLineRxVlanFramesCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxVlanFramesCounter_1 in AQ_MsmLineRxVlanFramesCounterRegister_HHD */ -#define word_AQ_MsmLineRxVlanFramesCounterRegister_HHD_msmLineRxVlanFramesCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmLineTxOctetsCounterRegister_HHD */ -#define AQ_MsmLineTxOctetsCounterRegister_HHD_baseRegisterAddress 0x9068 -/*! \brief MMD address of structure AQ_MsmLineTxOctetsCounterRegister_HHD */ -#define AQ_MsmLineTxOctetsCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxOctetsCounter_0 in AQ_MsmLineTxOctetsCounterRegister_HHD */ -#define AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxOctetsCounter_0 in AQ_MsmLineTxOctetsCounterRegister_HHD */ -#define bits_AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxOctetsCounter_0 in AQ_MsmLineTxOctetsCounterRegister_HHD */ -#define word_AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxOctetsCounter_1 in AQ_MsmLineTxOctetsCounterRegister_HHD */ -#define AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxOctetsCounter_1 in AQ_MsmLineTxOctetsCounterRegister_HHD */ -#define bits_AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxOctetsCounter_1 in AQ_MsmLineTxOctetsCounterRegister_HHD */ -#define word_AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_1 u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxOctetsCounter_2 in AQ_MsmLineTxOctetsCounterRegister_HHD */ -#define AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_2 2 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxOctetsCounter_2 in AQ_MsmLineTxOctetsCounterRegister_HHD */ -#define bits_AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_2 u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxOctetsCounter_2 in AQ_MsmLineTxOctetsCounterRegister_HHD */ -#define word_AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_2 u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxOctetsCounter_3 in AQ_MsmLineTxOctetsCounterRegister_HHD */ -#define AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_3 3 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxOctetsCounter_3 in AQ_MsmLineTxOctetsCounterRegister_HHD */ -#define bits_AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_3 u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxOctetsCounter_3 in AQ_MsmLineTxOctetsCounterRegister_HHD */ -#define word_AQ_MsmLineTxOctetsCounterRegister_HHD_msmLineTxOctetsCounter_3 u3.word_3 - -/*! \brief Base register address of structure AQ_MsmLineRxOctetsCounterRegister_HHD */ -#define AQ_MsmLineRxOctetsCounterRegister_HHD_baseRegisterAddress 0x906C -/*! \brief MMD address of structure AQ_MsmLineRxOctetsCounterRegister_HHD */ -#define AQ_MsmLineRxOctetsCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxOctetsCounter_0 in AQ_MsmLineRxOctetsCounterRegister_HHD */ -#define AQ_MsmLineRxOctetsCounterRegister_HHD_msmLineRxOctetsCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxOctetsCounter_0 in AQ_MsmLineRxOctetsCounterRegister_HHD */ -#define bits_AQ_MsmLineRxOctetsCounterRegister_HHD_msmLineRxOctetsCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxOctetsCounter_0 in AQ_MsmLineRxOctetsCounterRegister_HHD */ -#define word_AQ_MsmLineRxOctetsCounterRegister_HHD_msmLineRxOctetsCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxOctetsCounter_1 in AQ_MsmLineRxOctetsCounterRegister_HHD */ -#define AQ_MsmLineRxOctetsCounterRegister_HHD_msmLineRxOctetsCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxOctetsCounter_1 in AQ_MsmLineRxOctetsCounterRegister_HHD */ -#define bits_AQ_MsmLineRxOctetsCounterRegister_HHD_msmLineRxOctetsCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxOctetsCounter_1 in AQ_MsmLineRxOctetsCounterRegister_HHD */ -#define word_AQ_MsmLineRxOctetsCounterRegister_HHD_msmLineRxOctetsCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmLineRxUnicastFramesCounterRegister_HHD */ -#define AQ_MsmLineRxUnicastFramesCounterRegister_HHD_baseRegisterAddress 0x9070 -/*! \brief MMD address of structure AQ_MsmLineRxUnicastFramesCounterRegister_HHD */ -#define AQ_MsmLineRxUnicastFramesCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxUnicastFramesCounter_0 in AQ_MsmLineRxUnicastFramesCounterRegister_HHD */ -#define AQ_MsmLineRxUnicastFramesCounterRegister_HHD_msmLineRxUnicastFramesCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxUnicastFramesCounter_0 in AQ_MsmLineRxUnicastFramesCounterRegister_HHD */ -#define bits_AQ_MsmLineRxUnicastFramesCounterRegister_HHD_msmLineRxUnicastFramesCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxUnicastFramesCounter_0 in AQ_MsmLineRxUnicastFramesCounterRegister_HHD */ -#define word_AQ_MsmLineRxUnicastFramesCounterRegister_HHD_msmLineRxUnicastFramesCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxUnicastFramesCounter_1 in AQ_MsmLineRxUnicastFramesCounterRegister_HHD */ -#define AQ_MsmLineRxUnicastFramesCounterRegister_HHD_msmLineRxUnicastFramesCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxUnicastFramesCounter_1 in AQ_MsmLineRxUnicastFramesCounterRegister_HHD */ -#define bits_AQ_MsmLineRxUnicastFramesCounterRegister_HHD_msmLineRxUnicastFramesCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxUnicastFramesCounter_1 in AQ_MsmLineRxUnicastFramesCounterRegister_HHD */ -#define word_AQ_MsmLineRxUnicastFramesCounterRegister_HHD_msmLineRxUnicastFramesCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmLineRxMulticastFramesCounterRegister_HHD */ -#define AQ_MsmLineRxMulticastFramesCounterRegister_HHD_baseRegisterAddress 0x9074 -/*! \brief MMD address of structure AQ_MsmLineRxMulticastFramesCounterRegister_HHD */ -#define AQ_MsmLineRxMulticastFramesCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxMulticastFramesCounter_0 in AQ_MsmLineRxMulticastFramesCounterRegister_HHD */ -#define AQ_MsmLineRxMulticastFramesCounterRegister_HHD_msmLineRxMulticastFramesCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxMulticastFramesCounter_0 in AQ_MsmLineRxMulticastFramesCounterRegister_HHD */ -#define bits_AQ_MsmLineRxMulticastFramesCounterRegister_HHD_msmLineRxMulticastFramesCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxMulticastFramesCounter_0 in AQ_MsmLineRxMulticastFramesCounterRegister_HHD */ -#define word_AQ_MsmLineRxMulticastFramesCounterRegister_HHD_msmLineRxMulticastFramesCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxMulticastFramesCounter_1 in AQ_MsmLineRxMulticastFramesCounterRegister_HHD */ -#define AQ_MsmLineRxMulticastFramesCounterRegister_HHD_msmLineRxMulticastFramesCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxMulticastFramesCounter_1 in AQ_MsmLineRxMulticastFramesCounterRegister_HHD */ -#define bits_AQ_MsmLineRxMulticastFramesCounterRegister_HHD_msmLineRxMulticastFramesCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxMulticastFramesCounter_1 in AQ_MsmLineRxMulticastFramesCounterRegister_HHD */ -#define word_AQ_MsmLineRxMulticastFramesCounterRegister_HHD_msmLineRxMulticastFramesCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmLineRxBroadcastFramesCounterRegister_HHD */ -#define AQ_MsmLineRxBroadcastFramesCounterRegister_HHD_baseRegisterAddress 0x9078 -/*! \brief MMD address of structure AQ_MsmLineRxBroadcastFramesCounterRegister_HHD */ -#define AQ_MsmLineRxBroadcastFramesCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxBroadcastFramesCounter_0 in AQ_MsmLineRxBroadcastFramesCounterRegister_HHD */ -#define AQ_MsmLineRxBroadcastFramesCounterRegister_HHD_msmLineRxBroadcastFramesCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxBroadcastFramesCounter_0 in AQ_MsmLineRxBroadcastFramesCounterRegister_HHD */ -#define bits_AQ_MsmLineRxBroadcastFramesCounterRegister_HHD_msmLineRxBroadcastFramesCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxBroadcastFramesCounter_0 in AQ_MsmLineRxBroadcastFramesCounterRegister_HHD */ -#define word_AQ_MsmLineRxBroadcastFramesCounterRegister_HHD_msmLineRxBroadcastFramesCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxBroadcastFramesCounter_1 in AQ_MsmLineRxBroadcastFramesCounterRegister_HHD */ -#define AQ_MsmLineRxBroadcastFramesCounterRegister_HHD_msmLineRxBroadcastFramesCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxBroadcastFramesCounter_1 in AQ_MsmLineRxBroadcastFramesCounterRegister_HHD */ -#define bits_AQ_MsmLineRxBroadcastFramesCounterRegister_HHD_msmLineRxBroadcastFramesCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxBroadcastFramesCounter_1 in AQ_MsmLineRxBroadcastFramesCounterRegister_HHD */ -#define word_AQ_MsmLineRxBroadcastFramesCounterRegister_HHD_msmLineRxBroadcastFramesCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmLineTxErrorsCounterRegister_HHD */ -#define AQ_MsmLineTxErrorsCounterRegister_HHD_baseRegisterAddress 0x907C -/*! \brief MMD address of structure AQ_MsmLineTxErrorsCounterRegister_HHD */ -#define AQ_MsmLineTxErrorsCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxErrorsCounter_0 in AQ_MsmLineTxErrorsCounterRegister_HHD */ -#define AQ_MsmLineTxErrorsCounterRegister_HHD_msmLineTxErrorsCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxErrorsCounter_0 in AQ_MsmLineTxErrorsCounterRegister_HHD */ -#define bits_AQ_MsmLineTxErrorsCounterRegister_HHD_msmLineTxErrorsCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxErrorsCounter_0 in AQ_MsmLineTxErrorsCounterRegister_HHD */ -#define word_AQ_MsmLineTxErrorsCounterRegister_HHD_msmLineTxErrorsCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxErrorsCounter_1 in AQ_MsmLineTxErrorsCounterRegister_HHD */ -#define AQ_MsmLineTxErrorsCounterRegister_HHD_msmLineTxErrorsCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxErrorsCounter_1 in AQ_MsmLineTxErrorsCounterRegister_HHD */ -#define bits_AQ_MsmLineTxErrorsCounterRegister_HHD_msmLineTxErrorsCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxErrorsCounter_1 in AQ_MsmLineTxErrorsCounterRegister_HHD */ -#define word_AQ_MsmLineTxErrorsCounterRegister_HHD_msmLineTxErrorsCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmLineTxUnicastFramesCounterRegister_HHD */ -#define AQ_MsmLineTxUnicastFramesCounterRegister_HHD_baseRegisterAddress 0x9084 -/*! \brief MMD address of structure AQ_MsmLineTxUnicastFramesCounterRegister_HHD */ -#define AQ_MsmLineTxUnicastFramesCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxUnicastFramesCounter_0 in AQ_MsmLineTxUnicastFramesCounterRegister_HHD */ -#define AQ_MsmLineTxUnicastFramesCounterRegister_HHD_msmLineTxUnicastFramesCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxUnicastFramesCounter_0 in AQ_MsmLineTxUnicastFramesCounterRegister_HHD */ -#define bits_AQ_MsmLineTxUnicastFramesCounterRegister_HHD_msmLineTxUnicastFramesCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxUnicastFramesCounter_0 in AQ_MsmLineTxUnicastFramesCounterRegister_HHD */ -#define word_AQ_MsmLineTxUnicastFramesCounterRegister_HHD_msmLineTxUnicastFramesCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxUnicastFramesCounter_1 in AQ_MsmLineTxUnicastFramesCounterRegister_HHD */ -#define AQ_MsmLineTxUnicastFramesCounterRegister_HHD_msmLineTxUnicastFramesCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxUnicastFramesCounter_1 in AQ_MsmLineTxUnicastFramesCounterRegister_HHD */ -#define bits_AQ_MsmLineTxUnicastFramesCounterRegister_HHD_msmLineTxUnicastFramesCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxUnicastFramesCounter_1 in AQ_MsmLineTxUnicastFramesCounterRegister_HHD */ -#define word_AQ_MsmLineTxUnicastFramesCounterRegister_HHD_msmLineTxUnicastFramesCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmLineTxMulticastFramesCounterRegister_HHD */ -#define AQ_MsmLineTxMulticastFramesCounterRegister_HHD_baseRegisterAddress 0x9088 -/*! \brief MMD address of structure AQ_MsmLineTxMulticastFramesCounterRegister_HHD */ -#define AQ_MsmLineTxMulticastFramesCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxMulticastFramesCounter_0 in AQ_MsmLineTxMulticastFramesCounterRegister_HHD */ -#define AQ_MsmLineTxMulticastFramesCounterRegister_HHD_msmLineTxMulticastFramesCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxMulticastFramesCounter_0 in AQ_MsmLineTxMulticastFramesCounterRegister_HHD */ -#define bits_AQ_MsmLineTxMulticastFramesCounterRegister_HHD_msmLineTxMulticastFramesCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxMulticastFramesCounter_0 in AQ_MsmLineTxMulticastFramesCounterRegister_HHD */ -#define word_AQ_MsmLineTxMulticastFramesCounterRegister_HHD_msmLineTxMulticastFramesCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxMulticastFramesCounter_1 in AQ_MsmLineTxMulticastFramesCounterRegister_HHD */ -#define AQ_MsmLineTxMulticastFramesCounterRegister_HHD_msmLineTxMulticastFramesCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxMulticastFramesCounter_1 in AQ_MsmLineTxMulticastFramesCounterRegister_HHD */ -#define bits_AQ_MsmLineTxMulticastFramesCounterRegister_HHD_msmLineTxMulticastFramesCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxMulticastFramesCounter_1 in AQ_MsmLineTxMulticastFramesCounterRegister_HHD */ -#define word_AQ_MsmLineTxMulticastFramesCounterRegister_HHD_msmLineTxMulticastFramesCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmLineTxBroadcastFramesCounterRegister_HHD */ -#define AQ_MsmLineTxBroadcastFramesCounterRegister_HHD_baseRegisterAddress 0x908C -/*! \brief MMD address of structure AQ_MsmLineTxBroadcastFramesCounterRegister_HHD */ -#define AQ_MsmLineTxBroadcastFramesCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxBroadcastFramesCounter_0 in AQ_MsmLineTxBroadcastFramesCounterRegister_HHD */ -#define AQ_MsmLineTxBroadcastFramesCounterRegister_HHD_msmLineTxBroadcastFramesCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxBroadcastFramesCounter_0 in AQ_MsmLineTxBroadcastFramesCounterRegister_HHD */ -#define bits_AQ_MsmLineTxBroadcastFramesCounterRegister_HHD_msmLineTxBroadcastFramesCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxBroadcastFramesCounter_0 in AQ_MsmLineTxBroadcastFramesCounterRegister_HHD */ -#define word_AQ_MsmLineTxBroadcastFramesCounterRegister_HHD_msmLineTxBroadcastFramesCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineTxBroadcastFramesCounter_1 in AQ_MsmLineTxBroadcastFramesCounterRegister_HHD */ -#define AQ_MsmLineTxBroadcastFramesCounterRegister_HHD_msmLineTxBroadcastFramesCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineTxBroadcastFramesCounter_1 in AQ_MsmLineTxBroadcastFramesCounterRegister_HHD */ -#define bits_AQ_MsmLineTxBroadcastFramesCounterRegister_HHD_msmLineTxBroadcastFramesCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineTxBroadcastFramesCounter_1 in AQ_MsmLineTxBroadcastFramesCounterRegister_HHD */ -#define word_AQ_MsmLineTxBroadcastFramesCounterRegister_HHD_msmLineTxBroadcastFramesCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_MsmLineRxErrorsCounterRegister_HHD */ -#define AQ_MsmLineRxErrorsCounterRegister_HHD_baseRegisterAddress 0x90C8 -/*! \brief MMD address of structure AQ_MsmLineRxErrorsCounterRegister_HHD */ -#define AQ_MsmLineRxErrorsCounterRegister_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxErrorsCounter_0 in AQ_MsmLineRxErrorsCounterRegister_HHD */ -#define AQ_MsmLineRxErrorsCounterRegister_HHD_msmLineRxErrorsCounter_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxErrorsCounter_0 in AQ_MsmLineRxErrorsCounterRegister_HHD */ -#define bits_AQ_MsmLineRxErrorsCounterRegister_HHD_msmLineRxErrorsCounter_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxErrorsCounter_0 in AQ_MsmLineRxErrorsCounterRegister_HHD */ -#define word_AQ_MsmLineRxErrorsCounterRegister_HHD_msmLineRxErrorsCounter_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure msmLineRxErrorsCounter_1 in AQ_MsmLineRxErrorsCounterRegister_HHD */ -#define AQ_MsmLineRxErrorsCounterRegister_HHD_msmLineRxErrorsCounter_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure msmLineRxErrorsCounter_1 in AQ_MsmLineRxErrorsCounterRegister_HHD */ -#define bits_AQ_MsmLineRxErrorsCounterRegister_HHD_msmLineRxErrorsCounter_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure msmLineRxErrorsCounter_1 in AQ_MsmLineRxErrorsCounterRegister_HHD */ -#define word_AQ_MsmLineRxErrorsCounterRegister_HHD_msmLineRxErrorsCounter_1 u1.word_1 - -/*! \brief Base register address of structure AQ_GlobalControl_HHD */ -#define AQ_GlobalControl_HHD_baseRegisterAddress 0xC000 -/*! \brief MMD address of structure AQ_GlobalControl_HHD */ -#define AQ_GlobalControl_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure upReset in AQ_GlobalControl_HHD */ -#define AQ_GlobalControl_HHD_upReset 1 -/*! \brief Preprocessor variable to relate field to bit position in structure upReset in AQ_GlobalControl_HHD */ -#define bits_AQ_GlobalControl_HHD_upReset u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure upReset in AQ_GlobalControl_HHD */ -#define word_AQ_GlobalControl_HHD_upReset u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure upRunStallOverride in AQ_GlobalControl_HHD */ -#define AQ_GlobalControl_HHD_upRunStallOverride 1 -/*! \brief Preprocessor variable to relate field to bit position in structure upRunStallOverride in AQ_GlobalControl_HHD */ -#define bits_AQ_GlobalControl_HHD_upRunStallOverride u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure upRunStallOverride in AQ_GlobalControl_HHD */ -#define word_AQ_GlobalControl_HHD_upRunStallOverride u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure upRunStall in AQ_GlobalControl_HHD */ -#define AQ_GlobalControl_HHD_upRunStall 1 -/*! \brief Preprocessor variable to relate field to bit position in structure upRunStall in AQ_GlobalControl_HHD */ -#define bits_AQ_GlobalControl_HHD_upRunStall u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure upRunStall in AQ_GlobalControl_HHD */ -#define word_AQ_GlobalControl_HHD_upRunStall u1.word_1 - -/*! \brief Base register address of structure AQ_GlobalResetControl_HHD */ -#define AQ_GlobalResetControl_HHD_baseRegisterAddress 0xC006 -/*! \brief MMD address of structure AQ_GlobalResetControl_HHD */ -#define AQ_GlobalResetControl_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure globalMMD_ResetDisable in AQ_GlobalResetControl_HHD */ -#define AQ_GlobalResetControl_HHD_globalMMD_ResetDisable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure globalMMD_ResetDisable in AQ_GlobalResetControl_HHD */ -#define bits_AQ_GlobalResetControl_HHD_globalMMD_ResetDisable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure globalMMD_ResetDisable in AQ_GlobalResetControl_HHD */ -#define word_AQ_GlobalResetControl_HHD_globalMMD_ResetDisable u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalDiagnosticProvisioning_HHD */ -#define AQ_GlobalDiagnosticProvisioning_HHD_baseRegisterAddress 0xC400 -/*! \brief MMD address of structure AQ_GlobalDiagnosticProvisioning_HHD */ -#define AQ_GlobalDiagnosticProvisioning_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure enableDiagnostics in AQ_GlobalDiagnosticProvisioning_HHD */ -#define AQ_GlobalDiagnosticProvisioning_HHD_enableDiagnostics 0 -/*! \brief Preprocessor variable to relate field to bit position in structure enableDiagnostics in AQ_GlobalDiagnosticProvisioning_HHD */ -#define bits_AQ_GlobalDiagnosticProvisioning_HHD_enableDiagnostics u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure enableDiagnostics in AQ_GlobalDiagnosticProvisioning_HHD */ -#define word_AQ_GlobalDiagnosticProvisioning_HHD_enableDiagnostics u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalThermalProvisioning_HHD */ -#define AQ_GlobalThermalProvisioning_HHD_baseRegisterAddress 0xC420 -/*! \brief MMD address of structure AQ_GlobalThermalProvisioning_HHD */ -#define AQ_GlobalThermalProvisioning_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure reserved_0 in AQ_GlobalThermalProvisioning_HHD */ -#define AQ_GlobalThermalProvisioning_HHD_reserved_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_0 in AQ_GlobalThermalProvisioning_HHD */ -#define bits_AQ_GlobalThermalProvisioning_HHD_reserved_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_0 in AQ_GlobalThermalProvisioning_HHD */ -#define word_AQ_GlobalThermalProvisioning_HHD_reserved_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure highTempFailureThreshold in AQ_GlobalThermalProvisioning_HHD */ -#define AQ_GlobalThermalProvisioning_HHD_highTempFailureThreshold 1 -/*! \brief Preprocessor variable to relate field to bit position in structure highTempFailureThreshold in AQ_GlobalThermalProvisioning_HHD */ -#define bits_AQ_GlobalThermalProvisioning_HHD_highTempFailureThreshold u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure highTempFailureThreshold in AQ_GlobalThermalProvisioning_HHD */ -#define word_AQ_GlobalThermalProvisioning_HHD_highTempFailureThreshold u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure lowTempFailureThreshold in AQ_GlobalThermalProvisioning_HHD */ -#define AQ_GlobalThermalProvisioning_HHD_lowTempFailureThreshold 2 -/*! \brief Preprocessor variable to relate field to bit position in structure lowTempFailureThreshold in AQ_GlobalThermalProvisioning_HHD */ -#define bits_AQ_GlobalThermalProvisioning_HHD_lowTempFailureThreshold u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure lowTempFailureThreshold in AQ_GlobalThermalProvisioning_HHD */ -#define word_AQ_GlobalThermalProvisioning_HHD_lowTempFailureThreshold u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure highTempWarningThreshold in AQ_GlobalThermalProvisioning_HHD */ -#define AQ_GlobalThermalProvisioning_HHD_highTempWarningThreshold 3 -/*! \brief Preprocessor variable to relate field to bit position in structure highTempWarningThreshold in AQ_GlobalThermalProvisioning_HHD */ -#define bits_AQ_GlobalThermalProvisioning_HHD_highTempWarningThreshold u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure highTempWarningThreshold in AQ_GlobalThermalProvisioning_HHD */ -#define word_AQ_GlobalThermalProvisioning_HHD_highTempWarningThreshold u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure lowTempWarningThreshold in AQ_GlobalThermalProvisioning_HHD */ -#define AQ_GlobalThermalProvisioning_HHD_lowTempWarningThreshold 4 -/*! \brief Preprocessor variable to relate field to bit position in structure lowTempWarningThreshold in AQ_GlobalThermalProvisioning_HHD */ -#define bits_AQ_GlobalThermalProvisioning_HHD_lowTempWarningThreshold u4.bits_4 -/*! \brief Preprocessor variable to relate field to word position in structure lowTempWarningThreshold in AQ_GlobalThermalProvisioning_HHD */ -#define word_AQ_GlobalThermalProvisioning_HHD_lowTempWarningThreshold u4.word_4 - -/*! \brief Base register address of structure AQ_GlobalLedProvisioning_HHD */ -#define AQ_GlobalLedProvisioning_HHD_baseRegisterAddress 0xC430 -/*! \brief MMD address of structure AQ_GlobalLedProvisioning_HHD */ -#define AQ_GlobalLedProvisioning_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioningC430 in AQ_GlobalLedProvisioning_HHD */ -#define AQ_GlobalLedProvisioning_HHD_reservedProvisioningC430 0 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioningC430 in AQ_GlobalLedProvisioning_HHD */ -#define bits_AQ_GlobalLedProvisioning_HHD_reservedProvisioningC430 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioningC430 in AQ_GlobalLedProvisioning_HHD */ -#define word_AQ_GlobalLedProvisioning_HHD_reservedProvisioningC430 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure led_0ManualSet in AQ_GlobalLedProvisioning_HHD */ -#define AQ_GlobalLedProvisioning_HHD_led_0ManualSet 0 -/*! \brief Preprocessor variable to relate field to bit position in structure led_0ManualSet in AQ_GlobalLedProvisioning_HHD */ -#define bits_AQ_GlobalLedProvisioning_HHD_led_0ManualSet u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure led_0ManualSet in AQ_GlobalLedProvisioning_HHD */ -#define word_AQ_GlobalLedProvisioning_HHD_led_0ManualSet u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure led_0_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ -#define AQ_GlobalLedProvisioning_HHD_led_0_10Gb_sLinkEstablished 0 -/*! \brief Preprocessor variable to relate field to bit position in structure led_0_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ -#define bits_AQ_GlobalLedProvisioning_HHD_led_0_10Gb_sLinkEstablished u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure led_0_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ -#define word_AQ_GlobalLedProvisioning_HHD_led_0_10Gb_sLinkEstablished u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure led_0_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ -#define AQ_GlobalLedProvisioning_HHD_led_0_1Gb_sLinkEstablished 0 -/*! \brief Preprocessor variable to relate field to bit position in structure led_0_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ -#define bits_AQ_GlobalLedProvisioning_HHD_led_0_1Gb_sLinkEstablished u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure led_0_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ -#define word_AQ_GlobalLedProvisioning_HHD_led_0_1Gb_sLinkEstablished u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure led_0_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ -#define AQ_GlobalLedProvisioning_HHD_led_0_100Mb_sLinkEstablished 0 -/*! \brief Preprocessor variable to relate field to bit position in structure led_0_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ -#define bits_AQ_GlobalLedProvisioning_HHD_led_0_100Mb_sLinkEstablished u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure led_0_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ -#define word_AQ_GlobalLedProvisioning_HHD_led_0_100Mb_sLinkEstablished u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure led_0Connecting in AQ_GlobalLedProvisioning_HHD */ -#define AQ_GlobalLedProvisioning_HHD_led_0Connecting 0 -/*! \brief Preprocessor variable to relate field to bit position in structure led_0Connecting in AQ_GlobalLedProvisioning_HHD */ -#define bits_AQ_GlobalLedProvisioning_HHD_led_0Connecting u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure led_0Connecting in AQ_GlobalLedProvisioning_HHD */ -#define word_AQ_GlobalLedProvisioning_HHD_led_0Connecting u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure led_0ReceiveActivity in AQ_GlobalLedProvisioning_HHD */ -#define AQ_GlobalLedProvisioning_HHD_led_0ReceiveActivity 0 -/*! \brief Preprocessor variable to relate field to bit position in structure led_0ReceiveActivity in AQ_GlobalLedProvisioning_HHD */ -#define bits_AQ_GlobalLedProvisioning_HHD_led_0ReceiveActivity u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure led_0ReceiveActivity in AQ_GlobalLedProvisioning_HHD */ -#define word_AQ_GlobalLedProvisioning_HHD_led_0ReceiveActivity u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure led_0TransmitActivity in AQ_GlobalLedProvisioning_HHD */ -#define AQ_GlobalLedProvisioning_HHD_led_0TransmitActivity 0 -/*! \brief Preprocessor variable to relate field to bit position in structure led_0TransmitActivity in AQ_GlobalLedProvisioning_HHD */ -#define bits_AQ_GlobalLedProvisioning_HHD_led_0TransmitActivity u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure led_0TransmitActivity in AQ_GlobalLedProvisioning_HHD */ -#define word_AQ_GlobalLedProvisioning_HHD_led_0TransmitActivity u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure led_0ActivityStretch in AQ_GlobalLedProvisioning_HHD */ -#define AQ_GlobalLedProvisioning_HHD_led_0ActivityStretch 0 -/*! \brief Preprocessor variable to relate field to bit position in structure led_0ActivityStretch in AQ_GlobalLedProvisioning_HHD */ -#define bits_AQ_GlobalLedProvisioning_HHD_led_0ActivityStretch u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure led_0ActivityStretch in AQ_GlobalLedProvisioning_HHD */ -#define word_AQ_GlobalLedProvisioning_HHD_led_0ActivityStretch u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioningC431 in AQ_GlobalLedProvisioning_HHD */ -#define AQ_GlobalLedProvisioning_HHD_reservedProvisioningC431 1 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioningC431 in AQ_GlobalLedProvisioning_HHD */ -#define bits_AQ_GlobalLedProvisioning_HHD_reservedProvisioningC431 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioningC431 in AQ_GlobalLedProvisioning_HHD */ -#define word_AQ_GlobalLedProvisioning_HHD_reservedProvisioningC431 u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure led_1ManualSet in AQ_GlobalLedProvisioning_HHD */ -#define AQ_GlobalLedProvisioning_HHD_led_1ManualSet 1 -/*! \brief Preprocessor variable to relate field to bit position in structure led_1ManualSet in AQ_GlobalLedProvisioning_HHD */ -#define bits_AQ_GlobalLedProvisioning_HHD_led_1ManualSet u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure led_1ManualSet in AQ_GlobalLedProvisioning_HHD */ -#define word_AQ_GlobalLedProvisioning_HHD_led_1ManualSet u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure led_1_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ -#define AQ_GlobalLedProvisioning_HHD_led_1_10Gb_sLinkEstablished 1 -/*! \brief Preprocessor variable to relate field to bit position in structure led_1_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ -#define bits_AQ_GlobalLedProvisioning_HHD_led_1_10Gb_sLinkEstablished u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure led_1_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ -#define word_AQ_GlobalLedProvisioning_HHD_led_1_10Gb_sLinkEstablished u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure led_1_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ -#define AQ_GlobalLedProvisioning_HHD_led_1_1Gb_sLinkEstablished 1 -/*! \brief Preprocessor variable to relate field to bit position in structure led_1_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ -#define bits_AQ_GlobalLedProvisioning_HHD_led_1_1Gb_sLinkEstablished u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure led_1_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ -#define word_AQ_GlobalLedProvisioning_HHD_led_1_1Gb_sLinkEstablished u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure led_1_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ -#define AQ_GlobalLedProvisioning_HHD_led_1_100Mb_sLinkEstablished 1 -/*! \brief Preprocessor variable to relate field to bit position in structure led_1_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ -#define bits_AQ_GlobalLedProvisioning_HHD_led_1_100Mb_sLinkEstablished u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure led_1_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ -#define word_AQ_GlobalLedProvisioning_HHD_led_1_100Mb_sLinkEstablished u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure led_1Connecting in AQ_GlobalLedProvisioning_HHD */ -#define AQ_GlobalLedProvisioning_HHD_led_1Connecting 1 -/*! \brief Preprocessor variable to relate field to bit position in structure led_1Connecting in AQ_GlobalLedProvisioning_HHD */ -#define bits_AQ_GlobalLedProvisioning_HHD_led_1Connecting u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure led_1Connecting in AQ_GlobalLedProvisioning_HHD */ -#define word_AQ_GlobalLedProvisioning_HHD_led_1Connecting u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure led_1ReceiveActivity in AQ_GlobalLedProvisioning_HHD */ -#define AQ_GlobalLedProvisioning_HHD_led_1ReceiveActivity 1 -/*! \brief Preprocessor variable to relate field to bit position in structure led_1ReceiveActivity in AQ_GlobalLedProvisioning_HHD */ -#define bits_AQ_GlobalLedProvisioning_HHD_led_1ReceiveActivity u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure led_1ReceiveActivity in AQ_GlobalLedProvisioning_HHD */ -#define word_AQ_GlobalLedProvisioning_HHD_led_1ReceiveActivity u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure led_1TransmitActivity in AQ_GlobalLedProvisioning_HHD */ -#define AQ_GlobalLedProvisioning_HHD_led_1TransmitActivity 1 -/*! \brief Preprocessor variable to relate field to bit position in structure led_1TransmitActivity in AQ_GlobalLedProvisioning_HHD */ -#define bits_AQ_GlobalLedProvisioning_HHD_led_1TransmitActivity u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure led_1TransmitActivity in AQ_GlobalLedProvisioning_HHD */ -#define word_AQ_GlobalLedProvisioning_HHD_led_1TransmitActivity u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure led_1ActivityStretch in AQ_GlobalLedProvisioning_HHD */ -#define AQ_GlobalLedProvisioning_HHD_led_1ActivityStretch 1 -/*! \brief Preprocessor variable to relate field to bit position in structure led_1ActivityStretch in AQ_GlobalLedProvisioning_HHD */ -#define bits_AQ_GlobalLedProvisioning_HHD_led_1ActivityStretch u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure led_1ActivityStretch in AQ_GlobalLedProvisioning_HHD */ -#define word_AQ_GlobalLedProvisioning_HHD_led_1ActivityStretch u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioningC432 in AQ_GlobalLedProvisioning_HHD */ -#define AQ_GlobalLedProvisioning_HHD_reservedProvisioningC432 2 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioningC432 in AQ_GlobalLedProvisioning_HHD */ -#define bits_AQ_GlobalLedProvisioning_HHD_reservedProvisioningC432 u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioningC432 in AQ_GlobalLedProvisioning_HHD */ -#define word_AQ_GlobalLedProvisioning_HHD_reservedProvisioningC432 u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure led_2ManualSet in AQ_GlobalLedProvisioning_HHD */ -#define AQ_GlobalLedProvisioning_HHD_led_2ManualSet 2 -/*! \brief Preprocessor variable to relate field to bit position in structure led_2ManualSet in AQ_GlobalLedProvisioning_HHD */ -#define bits_AQ_GlobalLedProvisioning_HHD_led_2ManualSet u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure led_2ManualSet in AQ_GlobalLedProvisioning_HHD */ -#define word_AQ_GlobalLedProvisioning_HHD_led_2ManualSet u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure led_2_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ -#define AQ_GlobalLedProvisioning_HHD_led_2_10Gb_sLinkEstablished 2 -/*! \brief Preprocessor variable to relate field to bit position in structure led_2_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ -#define bits_AQ_GlobalLedProvisioning_HHD_led_2_10Gb_sLinkEstablished u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure led_2_10Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ -#define word_AQ_GlobalLedProvisioning_HHD_led_2_10Gb_sLinkEstablished u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure led_2_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ -#define AQ_GlobalLedProvisioning_HHD_led_2_1Gb_sLinkEstablished 2 -/*! \brief Preprocessor variable to relate field to bit position in structure led_2_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ -#define bits_AQ_GlobalLedProvisioning_HHD_led_2_1Gb_sLinkEstablished u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure led_2_1Gb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ -#define word_AQ_GlobalLedProvisioning_HHD_led_2_1Gb_sLinkEstablished u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure led_2_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ -#define AQ_GlobalLedProvisioning_HHD_led_2_100Mb_sLinkEstablished 2 -/*! \brief Preprocessor variable to relate field to bit position in structure led_2_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ -#define bits_AQ_GlobalLedProvisioning_HHD_led_2_100Mb_sLinkEstablished u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure led_2_100Mb_sLinkEstablished in AQ_GlobalLedProvisioning_HHD */ -#define word_AQ_GlobalLedProvisioning_HHD_led_2_100Mb_sLinkEstablished u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure led_2Connecting in AQ_GlobalLedProvisioning_HHD */ -#define AQ_GlobalLedProvisioning_HHD_led_2Connecting 2 -/*! \brief Preprocessor variable to relate field to bit position in structure led_2Connecting in AQ_GlobalLedProvisioning_HHD */ -#define bits_AQ_GlobalLedProvisioning_HHD_led_2Connecting u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure led_2Connecting in AQ_GlobalLedProvisioning_HHD */ -#define word_AQ_GlobalLedProvisioning_HHD_led_2Connecting u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure led_2ReceiveActivity in AQ_GlobalLedProvisioning_HHD */ -#define AQ_GlobalLedProvisioning_HHD_led_2ReceiveActivity 2 -/*! \brief Preprocessor variable to relate field to bit position in structure led_2ReceiveActivity in AQ_GlobalLedProvisioning_HHD */ -#define bits_AQ_GlobalLedProvisioning_HHD_led_2ReceiveActivity u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure led_2ReceiveActivity in AQ_GlobalLedProvisioning_HHD */ -#define word_AQ_GlobalLedProvisioning_HHD_led_2ReceiveActivity u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure led_2TransmitActivity in AQ_GlobalLedProvisioning_HHD */ -#define AQ_GlobalLedProvisioning_HHD_led_2TransmitActivity 2 -/*! \brief Preprocessor variable to relate field to bit position in structure led_2TransmitActivity in AQ_GlobalLedProvisioning_HHD */ -#define bits_AQ_GlobalLedProvisioning_HHD_led_2TransmitActivity u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure led_2TransmitActivity in AQ_GlobalLedProvisioning_HHD */ -#define word_AQ_GlobalLedProvisioning_HHD_led_2TransmitActivity u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure led_2ActivityStretch in AQ_GlobalLedProvisioning_HHD */ -#define AQ_GlobalLedProvisioning_HHD_led_2ActivityStretch 2 -/*! \brief Preprocessor variable to relate field to bit position in structure led_2ActivityStretch in AQ_GlobalLedProvisioning_HHD */ -#define bits_AQ_GlobalLedProvisioning_HHD_led_2ActivityStretch u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure led_2ActivityStretch in AQ_GlobalLedProvisioning_HHD */ -#define word_AQ_GlobalLedProvisioning_HHD_led_2ActivityStretch u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure ledOperationMode in AQ_GlobalLedProvisioning_HHD */ -#define AQ_GlobalLedProvisioning_HHD_ledOperationMode 7 -/*! \brief Preprocessor variable to relate field to bit position in structure ledOperationMode in AQ_GlobalLedProvisioning_HHD */ -#define bits_AQ_GlobalLedProvisioning_HHD_ledOperationMode u7.bits_7 -/*! \brief Preprocessor variable to relate field to word position in structure ledOperationMode in AQ_GlobalLedProvisioning_HHD */ -#define word_AQ_GlobalLedProvisioning_HHD_ledOperationMode u7.word_7 - -/*! \brief Base register address of structure AQ_GlobalGeneralProvisioning_HHD */ -#define AQ_GlobalGeneralProvisioning_HHD_baseRegisterAddress 0xC440 -/*! \brief MMD address of structure AQ_GlobalGeneralProvisioning_HHD */ -#define AQ_GlobalGeneralProvisioning_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure mdioBroadcastModeEnable in AQ_GlobalGeneralProvisioning_HHD */ -#define AQ_GlobalGeneralProvisioning_HHD_mdioBroadcastModeEnable 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mdioBroadcastModeEnable in AQ_GlobalGeneralProvisioning_HHD */ -#define bits_AQ_GlobalGeneralProvisioning_HHD_mdioBroadcastModeEnable u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mdioBroadcastModeEnable in AQ_GlobalGeneralProvisioning_HHD */ -#define word_AQ_GlobalGeneralProvisioning_HHD_mdioBroadcastModeEnable u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure mdioReadMSW_FirstEnable in AQ_GlobalGeneralProvisioning_HHD */ -#define AQ_GlobalGeneralProvisioning_HHD_mdioReadMSW_FirstEnable 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mdioReadMSW_FirstEnable in AQ_GlobalGeneralProvisioning_HHD */ -#define bits_AQ_GlobalGeneralProvisioning_HHD_mdioReadMSW_FirstEnable u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mdioReadMSW_FirstEnable in AQ_GlobalGeneralProvisioning_HHD */ -#define word_AQ_GlobalGeneralProvisioning_HHD_mdioReadMSW_FirstEnable u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure mdioDriveConfiguration in AQ_GlobalGeneralProvisioning_HHD */ -#define AQ_GlobalGeneralProvisioning_HHD_mdioDriveConfiguration 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mdioDriveConfiguration in AQ_GlobalGeneralProvisioning_HHD */ -#define bits_AQ_GlobalGeneralProvisioning_HHD_mdioDriveConfiguration u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mdioDriveConfiguration in AQ_GlobalGeneralProvisioning_HHD */ -#define word_AQ_GlobalGeneralProvisioning_HHD_mdioDriveConfiguration u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure mdioPreambleDetectionDisable in AQ_GlobalGeneralProvisioning_HHD */ -#define AQ_GlobalGeneralProvisioning_HHD_mdioPreambleDetectionDisable 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mdioPreambleDetectionDisable in AQ_GlobalGeneralProvisioning_HHD */ -#define bits_AQ_GlobalGeneralProvisioning_HHD_mdioPreambleDetectionDisable u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mdioPreambleDetectionDisable in AQ_GlobalGeneralProvisioning_HHD */ -#define word_AQ_GlobalGeneralProvisioning_HHD_mdioPreambleDetectionDisable u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure daisyChainReset in AQ_GlobalGeneralProvisioning_HHD */ -#define AQ_GlobalGeneralProvisioning_HHD_daisyChainReset 2 -/*! \brief Preprocessor variable to relate field to bit position in structure daisyChainReset in AQ_GlobalGeneralProvisioning_HHD */ -#define bits_AQ_GlobalGeneralProvisioning_HHD_daisyChainReset u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure daisyChainReset in AQ_GlobalGeneralProvisioning_HHD */ -#define word_AQ_GlobalGeneralProvisioning_HHD_daisyChainReset u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure mdioBroadcastAddressConfiguration in AQ_GlobalGeneralProvisioning_HHD */ -#define AQ_GlobalGeneralProvisioning_HHD_mdioBroadcastAddressConfiguration 7 -/*! \brief Preprocessor variable to relate field to bit position in structure mdioBroadcastAddressConfiguration in AQ_GlobalGeneralProvisioning_HHD */ -#define bits_AQ_GlobalGeneralProvisioning_HHD_mdioBroadcastAddressConfiguration u7.bits_7 -/*! \brief Preprocessor variable to relate field to word position in structure mdioBroadcastAddressConfiguration in AQ_GlobalGeneralProvisioning_HHD */ -#define word_AQ_GlobalGeneralProvisioning_HHD_mdioBroadcastAddressConfiguration u7.word_7 -/*! \brief Preprocessor variable to relate field to word number in structure mdioPreambleLength in AQ_GlobalGeneralProvisioning_HHD */ -#define AQ_GlobalGeneralProvisioning_HHD_mdioPreambleLength 9 -/*! \brief Preprocessor variable to relate field to bit position in structure mdioPreambleLength in AQ_GlobalGeneralProvisioning_HHD */ -#define bits_AQ_GlobalGeneralProvisioning_HHD_mdioPreambleLength u9.bits_9 -/*! \brief Preprocessor variable to relate field to word position in structure mdioPreambleLength in AQ_GlobalGeneralProvisioning_HHD */ -#define word_AQ_GlobalGeneralProvisioning_HHD_mdioPreambleLength u9.word_9 - -/*! \brief Base register address of structure AQ_GlobalNvrProvisioning_HHD */ -#define AQ_GlobalNvrProvisioning_HHD_baseRegisterAddress 0xC450 -/*! \brief MMD address of structure AQ_GlobalNvrProvisioning_HHD */ -#define AQ_GlobalNvrProvisioning_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure nvrDataLength in AQ_GlobalNvrProvisioning_HHD */ -#define AQ_GlobalNvrProvisioning_HHD_nvrDataLength 0 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrDataLength in AQ_GlobalNvrProvisioning_HHD */ -#define bits_AQ_GlobalNvrProvisioning_HHD_nvrDataLength u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure nvrDataLength in AQ_GlobalNvrProvisioning_HHD */ -#define word_AQ_GlobalNvrProvisioning_HHD_nvrDataLength u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure nvrDummyLength in AQ_GlobalNvrProvisioning_HHD */ -#define AQ_GlobalNvrProvisioning_HHD_nvrDummyLength 0 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrDummyLength in AQ_GlobalNvrProvisioning_HHD */ -#define bits_AQ_GlobalNvrProvisioning_HHD_nvrDummyLength u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure nvrDummyLength in AQ_GlobalNvrProvisioning_HHD */ -#define word_AQ_GlobalNvrProvisioning_HHD_nvrDummyLength u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure nvrAddressLength in AQ_GlobalNvrProvisioning_HHD */ -#define AQ_GlobalNvrProvisioning_HHD_nvrAddressLength 0 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrAddressLength in AQ_GlobalNvrProvisioning_HHD */ -#define bits_AQ_GlobalNvrProvisioning_HHD_nvrAddressLength u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure nvrAddressLength in AQ_GlobalNvrProvisioning_HHD */ -#define word_AQ_GlobalNvrProvisioning_HHD_nvrAddressLength u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure nvrAddressLengthOverride in AQ_GlobalNvrProvisioning_HHD */ -#define AQ_GlobalNvrProvisioning_HHD_nvrAddressLengthOverride 1 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrAddressLengthOverride in AQ_GlobalNvrProvisioning_HHD */ -#define bits_AQ_GlobalNvrProvisioning_HHD_nvrAddressLengthOverride u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure nvrAddressLengthOverride in AQ_GlobalNvrProvisioning_HHD */ -#define word_AQ_GlobalNvrProvisioning_HHD_nvrAddressLengthOverride u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure nvrClockDivide in AQ_GlobalNvrProvisioning_HHD */ -#define AQ_GlobalNvrProvisioning_HHD_nvrClockDivide 1 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrClockDivide in AQ_GlobalNvrProvisioning_HHD */ -#define bits_AQ_GlobalNvrProvisioning_HHD_nvrClockDivide u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure nvrClockDivide in AQ_GlobalNvrProvisioning_HHD */ -#define word_AQ_GlobalNvrProvisioning_HHD_nvrClockDivide u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure nvrDaisyChainClockDivideOverride in AQ_GlobalNvrProvisioning_HHD */ -#define AQ_GlobalNvrProvisioning_HHD_nvrDaisyChainClockDivideOverride 2 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrDaisyChainClockDivideOverride in AQ_GlobalNvrProvisioning_HHD */ -#define bits_AQ_GlobalNvrProvisioning_HHD_nvrDaisyChainClockDivideOverride u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure nvrDaisyChainClockDivideOverride in AQ_GlobalNvrProvisioning_HHD */ -#define word_AQ_GlobalNvrProvisioning_HHD_nvrDaisyChainClockDivideOverride u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure nvrDaisyChainDisable in AQ_GlobalNvrProvisioning_HHD */ -#define AQ_GlobalNvrProvisioning_HHD_nvrDaisyChainDisable 2 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrDaisyChainDisable in AQ_GlobalNvrProvisioning_HHD */ -#define bits_AQ_GlobalNvrProvisioning_HHD_nvrDaisyChainDisable u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure nvrDaisyChainDisable in AQ_GlobalNvrProvisioning_HHD */ -#define word_AQ_GlobalNvrProvisioning_HHD_nvrDaisyChainDisable u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure nvrReset in AQ_GlobalNvrProvisioning_HHD */ -#define AQ_GlobalNvrProvisioning_HHD_nvrReset 3 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrReset in AQ_GlobalNvrProvisioning_HHD */ -#define bits_AQ_GlobalNvrProvisioning_HHD_nvrReset u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure nvrReset in AQ_GlobalNvrProvisioning_HHD */ -#define word_AQ_GlobalNvrProvisioning_HHD_nvrReset u3.word_3 - -/*! \brief Base register address of structure AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_baseRegisterAddress 0xC470 -/*! \brief MMD address of structure AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure diagnosticsSelect in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_diagnosticsSelect 0 -/*! \brief Preprocessor variable to relate field to bit position in structure diagnosticsSelect in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_diagnosticsSelect u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure diagnosticsSelect in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_diagnosticsSelect u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure extendedMdiDiagnosticsSelect in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_extendedMdiDiagnosticsSelect 0 -/*! \brief Preprocessor variable to relate field to bit position in structure extendedMdiDiagnosticsSelect in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_extendedMdiDiagnosticsSelect u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure extendedMdiDiagnosticsSelect in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_extendedMdiDiagnosticsSelect u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure initiateCableDiagnostics in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_initiateCableDiagnostics 0 -/*! \brief Preprocessor variable to relate field to bit position in structure initiateCableDiagnostics in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_initiateCableDiagnostics u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure initiateCableDiagnostics in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_initiateCableDiagnostics u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure enableDaisy_chainHop_countOverride in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_enableDaisy_chainHop_countOverride 1 -/*! \brief Preprocessor variable to relate field to bit position in structure enableDaisy_chainHop_countOverride in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_enableDaisy_chainHop_countOverride u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure enableDaisy_chainHop_countOverride in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_enableDaisy_chainHop_countOverride u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure daisy_chainHop_countOverrideValue in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_daisy_chainHop_countOverrideValue 1 -/*! \brief Preprocessor variable to relate field to bit position in structure daisy_chainHop_countOverrideValue in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_daisy_chainHop_countOverrideValue u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure daisy_chainHop_countOverrideValue in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_daisy_chainHop_countOverrideValue u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure enableVddPowerSupplyTuning in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_enableVddPowerSupplyTuning 2 -/*! \brief Preprocessor variable to relate field to bit position in structure enableVddPowerSupplyTuning in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_enableVddPowerSupplyTuning u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure enableVddPowerSupplyTuning in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_enableVddPowerSupplyTuning u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure tunableExternalVddPowerSupplyPresent in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_tunableExternalVddPowerSupplyPresent 2 -/*! \brief Preprocessor variable to relate field to bit position in structure tunableExternalVddPowerSupplyPresent in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_tunableExternalVddPowerSupplyPresent u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure tunableExternalVddPowerSupplyPresent in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_tunableExternalVddPowerSupplyPresent u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure externalVddChangeRequest in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_externalVddChangeRequest 2 -/*! \brief Preprocessor variable to relate field to bit position in structure externalVddChangeRequest in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_externalVddChangeRequest u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure externalVddChangeRequest in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_externalVddChangeRequest u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure enableXenpakRegisterSpace in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_enableXenpakRegisterSpace 2 -/*! \brief Preprocessor variable to relate field to bit position in structure enableXenpakRegisterSpace in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_enableXenpakRegisterSpace u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure enableXenpakRegisterSpace in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_enableXenpakRegisterSpace u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure enable_5thChannelRfiCancellation in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_enable_5thChannelRfiCancellation 2 -/*! \brief Preprocessor variable to relate field to bit position in structure enable_5thChannelRfiCancellation in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_enable_5thChannelRfiCancellation u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure enable_5thChannelRfiCancellation in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_enable_5thChannelRfiCancellation u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure rateTransitionRequest in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_rateTransitionRequest 3 -/*! \brief Preprocessor variable to relate field to bit position in structure rateTransitionRequest in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_rateTransitionRequest u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure rateTransitionRequest in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_rateTransitionRequest u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure trainingSNR in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_trainingSNR 3 -/*! \brief Preprocessor variable to relate field to bit position in structure trainingSNR in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_trainingSNR u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure trainingSNR in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_trainingSNR u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioning_5 in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_5 4 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioning_5 in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_5 u4.bits_4 -/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioning_5 in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_5 u4.word_4 -/*! \brief Preprocessor variable to relate field to word number in structure nvrDaisyChainKickstart in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_nvrDaisyChainKickstart 4 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrDaisyChainKickstart in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_nvrDaisyChainKickstart u4.bits_4 -/*! \brief Preprocessor variable to relate field to word position in structure nvrDaisyChainKickstart in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_nvrDaisyChainKickstart u4.word_4 -/*! \brief Preprocessor variable to relate field to word number in structure smartPower_downStatus in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_smartPower_downStatus 5 -/*! \brief Preprocessor variable to relate field to bit position in structure smartPower_downStatus in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_smartPower_downStatus u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure smartPower_downStatus in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_smartPower_downStatus u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioning_6 in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_6 5 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioning_6 in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_6 u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioning_6 in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_6 u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure cfrLpDisableTimer in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_cfrLpDisableTimer 5 -/*! \brief Preprocessor variable to relate field to bit position in structure cfrLpDisableTimer in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_cfrLpDisableTimer u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure cfrLpDisableTimer in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_cfrLpDisableTimer u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure cfrLpExtendedMaxwait in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_cfrLpExtendedMaxwait 5 -/*! \brief Preprocessor variable to relate field to bit position in structure cfrLpExtendedMaxwait in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_cfrLpExtendedMaxwait u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure cfrLpExtendedMaxwait in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_cfrLpExtendedMaxwait u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure cfrLpTHP in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_cfrLpTHP 5 -/*! \brief Preprocessor variable to relate field to bit position in structure cfrLpTHP in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_cfrLpTHP u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure cfrLpTHP in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_cfrLpTHP u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure cfrLpSupport in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_cfrLpSupport 5 -/*! \brief Preprocessor variable to relate field to bit position in structure cfrLpSupport in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_cfrLpSupport u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure cfrLpSupport in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_cfrLpSupport u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure cfrDisableTimer in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_cfrDisableTimer 5 -/*! \brief Preprocessor variable to relate field to bit position in structure cfrDisableTimer in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_cfrDisableTimer u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure cfrDisableTimer in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_cfrDisableTimer u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure cfrExtendedMaxwait in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_cfrExtendedMaxwait 5 -/*! \brief Preprocessor variable to relate field to bit position in structure cfrExtendedMaxwait in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_cfrExtendedMaxwait u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure cfrExtendedMaxwait in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_cfrExtendedMaxwait u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure cfrTHP in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_cfrTHP 5 -/*! \brief Preprocessor variable to relate field to bit position in structure cfrTHP in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_cfrTHP u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure cfrTHP in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_cfrTHP u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure cfrSupport in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_cfrSupport 5 -/*! \brief Preprocessor variable to relate field to bit position in structure cfrSupport in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_cfrSupport u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure cfrSupport in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_cfrSupport u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure deadlockAvoidanceEnable in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_deadlockAvoidanceEnable 5 -/*! \brief Preprocessor variable to relate field to bit position in structure deadlockAvoidanceEnable in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_deadlockAvoidanceEnable u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure deadlockAvoidanceEnable in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_deadlockAvoidanceEnable u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure smartPower_downEnable in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_smartPower_downEnable 5 -/*! \brief Preprocessor variable to relate field to bit position in structure smartPower_downEnable in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_smartPower_downEnable u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure smartPower_downEnable in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_smartPower_downEnable u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure dteEnable in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_dteEnable 8 -/*! \brief Preprocessor variable to relate field to bit position in structure dteEnable in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_dteEnable u8.bits_8 -/*! \brief Preprocessor variable to relate field to word position in structure dteEnable in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_dteEnable u8.word_8 -/*! \brief Preprocessor variable to relate field to word number in structure dteDropReportingTimer in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_dteDropReportingTimer 8 -/*! \brief Preprocessor variable to relate field to bit position in structure dteDropReportingTimer in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_dteDropReportingTimer u8.bits_8 -/*! \brief Preprocessor variable to relate field to word position in structure dteDropReportingTimer in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_dteDropReportingTimer u8.word_8 -/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioning_9 in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_9 8 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioning_9 in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_9 u8.bits_8 -/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioning_9 in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_9 u8.word_8 -/*! \brief Preprocessor variable to relate field to word number in structure powerUpStall in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_powerUpStall 9 -/*! \brief Preprocessor variable to relate field to bit position in structure powerUpStall in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_powerUpStall u9.bits_9 -/*! \brief Preprocessor variable to relate field to word position in structure powerUpStall in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_powerUpStall u9.word_9 -/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioning_10 in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_10 9 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioning_10 in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_10 u9.bits_9 -/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioning_10 in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_10 u9.word_9 -/*! \brief Preprocessor variable to relate field to word number in structure loopbackControl in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_loopbackControl 10 -/*! \brief Preprocessor variable to relate field to bit position in structure loopbackControl in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_loopbackControl u10.bits_10 -/*! \brief Preprocessor variable to relate field to word position in structure loopbackControl in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_loopbackControl u10.word_10 -/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioning_11 in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_11 10 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioning_11 in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_11 u10.bits_10 -/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioning_11 in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_11 u10.word_10 -/*! \brief Preprocessor variable to relate field to word number in structure mdiPacketGeneration in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_mdiPacketGeneration 10 -/*! \brief Preprocessor variable to relate field to bit position in structure mdiPacketGeneration in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_mdiPacketGeneration u10.bits_10 -/*! \brief Preprocessor variable to relate field to word position in structure mdiPacketGeneration in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_mdiPacketGeneration u10.word_10 -/*! \brief Preprocessor variable to relate field to word number in structure look_asidePortPacketGeneration in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_look_asidePortPacketGeneration 10 -/*! \brief Preprocessor variable to relate field to bit position in structure look_asidePortPacketGeneration in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_look_asidePortPacketGeneration u10.bits_10 -/*! \brief Preprocessor variable to relate field to word position in structure look_asidePortPacketGeneration in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_look_asidePortPacketGeneration u10.word_10 -/*! \brief Preprocessor variable to relate field to word number in structure systemI_fPacketGeneration in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_systemI_fPacketGeneration 10 -/*! \brief Preprocessor variable to relate field to bit position in structure systemI_fPacketGeneration in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_systemI_fPacketGeneration u10.bits_10 -/*! \brief Preprocessor variable to relate field to word position in structure systemI_fPacketGeneration in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_systemI_fPacketGeneration u10.word_10 -/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioning_11a in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_11a 10 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioning_11a in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_11a u10.bits_10 -/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioning_11a in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_11a u10.word_10 -/*! \brief Preprocessor variable to relate field to word number in structure rate in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_rate 10 -/*! \brief Preprocessor variable to relate field to bit position in structure rate in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_rate u10.bits_10 -/*! \brief Preprocessor variable to relate field to word position in structure rate in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_rate u10.word_10 -/*! \brief Preprocessor variable to relate field to word number in structure reservedProvisioning_12 in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_12 11 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedProvisioning_12 in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_12 u11.bits_11 -/*! \brief Preprocessor variable to relate field to word position in structure reservedProvisioning_12 in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_reservedProvisioning_12 u11.word_11 -/*! \brief Preprocessor variable to relate field to word number in structure enableMacsec in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_enableMacsec 11 -/*! \brief Preprocessor variable to relate field to bit position in structure enableMacsec in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_enableMacsec u11.bits_11 -/*! \brief Preprocessor variable to relate field to word position in structure enableMacsec in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_enableMacsec u11.word_11 -/*! \brief Preprocessor variable to relate field to word number in structure enablePtp in AQ_GlobalReservedProvisioning_HHD */ -#define AQ_GlobalReservedProvisioning_HHD_enablePtp 11 -/*! \brief Preprocessor variable to relate field to bit position in structure enablePtp in AQ_GlobalReservedProvisioning_HHD */ -#define bits_AQ_GlobalReservedProvisioning_HHD_enablePtp u11.bits_11 -/*! \brief Preprocessor variable to relate field to word position in structure enablePtp in AQ_GlobalReservedProvisioning_HHD */ -#define word_AQ_GlobalReservedProvisioning_HHD_enablePtp u11.word_11 - -/*! \brief Base register address of structure AQ_PifMailboxControl_HHD */ -#define AQ_PifMailboxControl_HHD_baseRegisterAddress 0xC47C -/*! \brief MMD address of structure AQ_PifMailboxControl_HHD */ -#define AQ_PifMailboxControl_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure pifMailboxAddress in AQ_PifMailboxControl_HHD */ -#define AQ_PifMailboxControl_HHD_pifMailboxAddress 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pifMailboxAddress in AQ_PifMailboxControl_HHD */ -#define bits_AQ_PifMailboxControl_HHD_pifMailboxAddress u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pifMailboxAddress in AQ_PifMailboxControl_HHD */ -#define word_AQ_PifMailboxControl_HHD_pifMailboxAddress u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pifMailboxData in AQ_PifMailboxControl_HHD */ -#define AQ_PifMailboxControl_HHD_pifMailboxData 1 -/*! \brief Preprocessor variable to relate field to bit position in structure pifMailboxData in AQ_PifMailboxControl_HHD */ -#define bits_AQ_PifMailboxControl_HHD_pifMailboxData u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure pifMailboxData in AQ_PifMailboxControl_HHD */ -#define word_AQ_PifMailboxControl_HHD_pifMailboxData u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure reservedPifMailboxControl_3 in AQ_PifMailboxControl_HHD */ -#define AQ_PifMailboxControl_HHD_reservedPifMailboxControl_3 2 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedPifMailboxControl_3 in AQ_PifMailboxControl_HHD */ -#define bits_AQ_PifMailboxControl_HHD_reservedPifMailboxControl_3 u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure reservedPifMailboxControl_3 in AQ_PifMailboxControl_HHD */ -#define word_AQ_PifMailboxControl_HHD_reservedPifMailboxControl_3 u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure pifMailboxCommandType in AQ_PifMailboxControl_HHD */ -#define AQ_PifMailboxControl_HHD_pifMailboxCommandType 2 -/*! \brief Preprocessor variable to relate field to bit position in structure pifMailboxCommandType in AQ_PifMailboxControl_HHD */ -#define bits_AQ_PifMailboxControl_HHD_pifMailboxCommandType u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure pifMailboxCommandType in AQ_PifMailboxControl_HHD */ -#define word_AQ_PifMailboxControl_HHD_pifMailboxCommandType u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure pifMailboxMMD in AQ_PifMailboxControl_HHD */ -#define AQ_PifMailboxControl_HHD_pifMailboxMMD 2 -/*! \brief Preprocessor variable to relate field to bit position in structure pifMailboxMMD in AQ_PifMailboxControl_HHD */ -#define bits_AQ_PifMailboxControl_HHD_pifMailboxMMD u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure pifMailboxMMD in AQ_PifMailboxControl_HHD */ -#define word_AQ_PifMailboxControl_HHD_pifMailboxMMD u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure reservedPifMailboxControl_4 in AQ_PifMailboxControl_HHD */ -#define AQ_PifMailboxControl_HHD_reservedPifMailboxControl_4 3 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedPifMailboxControl_4 in AQ_PifMailboxControl_HHD */ -#define bits_AQ_PifMailboxControl_HHD_reservedPifMailboxControl_4 u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure reservedPifMailboxControl_4 in AQ_PifMailboxControl_HHD */ -#define word_AQ_PifMailboxControl_HHD_reservedPifMailboxControl_4 u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure pifMailboxCommandStatus in AQ_PifMailboxControl_HHD */ -#define AQ_PifMailboxControl_HHD_pifMailboxCommandStatus 3 -/*! \brief Preprocessor variable to relate field to bit position in structure pifMailboxCommandStatus in AQ_PifMailboxControl_HHD */ -#define bits_AQ_PifMailboxControl_HHD_pifMailboxCommandStatus u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure pifMailboxCommandStatus in AQ_PifMailboxControl_HHD */ -#define word_AQ_PifMailboxControl_HHD_pifMailboxCommandStatus u3.word_3 - -/*! \brief Base register address of structure AQ_GlobalSmbus_0Provisioning_HHD */ -#define AQ_GlobalSmbus_0Provisioning_HHD_baseRegisterAddress 0xC485 -/*! \brief MMD address of structure AQ_GlobalSmbus_0Provisioning_HHD */ -#define AQ_GlobalSmbus_0Provisioning_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure smb_0SlaveAddress in AQ_GlobalSmbus_0Provisioning_HHD */ -#define AQ_GlobalSmbus_0Provisioning_HHD_smb_0SlaveAddress 0 -/*! \brief Preprocessor variable to relate field to bit position in structure smb_0SlaveAddress in AQ_GlobalSmbus_0Provisioning_HHD */ -#define bits_AQ_GlobalSmbus_0Provisioning_HHD_smb_0SlaveAddress u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure smb_0SlaveAddress in AQ_GlobalSmbus_0Provisioning_HHD */ -#define word_AQ_GlobalSmbus_0Provisioning_HHD_smb_0SlaveAddress u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalSmbus_1Provisioning_HHD */ -#define AQ_GlobalSmbus_1Provisioning_HHD_baseRegisterAddress 0xC495 -/*! \brief MMD address of structure AQ_GlobalSmbus_1Provisioning_HHD */ -#define AQ_GlobalSmbus_1Provisioning_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure smb_1SlaveAddress in AQ_GlobalSmbus_1Provisioning_HHD */ -#define AQ_GlobalSmbus_1Provisioning_HHD_smb_1SlaveAddress 0 -/*! \brief Preprocessor variable to relate field to bit position in structure smb_1SlaveAddress in AQ_GlobalSmbus_1Provisioning_HHD */ -#define bits_AQ_GlobalSmbus_1Provisioning_HHD_smb_1SlaveAddress u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure smb_1SlaveAddress in AQ_GlobalSmbus_1Provisioning_HHD */ -#define word_AQ_GlobalSmbus_1Provisioning_HHD_smb_1SlaveAddress u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalEeeProvisioning_HHD */ -#define AQ_GlobalEeeProvisioning_HHD_baseRegisterAddress 0xC4A0 -/*! \brief MMD address of structure AQ_GlobalEeeProvisioning_HHD */ -#define AQ_GlobalEeeProvisioning_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure eeeMode in AQ_GlobalEeeProvisioning_HHD */ -#define AQ_GlobalEeeProvisioning_HHD_eeeMode 0 -/*! \brief Preprocessor variable to relate field to bit position in structure eeeMode in AQ_GlobalEeeProvisioning_HHD */ -#define bits_AQ_GlobalEeeProvisioning_HHD_eeeMode u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure eeeMode in AQ_GlobalEeeProvisioning_HHD */ -#define word_AQ_GlobalEeeProvisioning_HHD_eeeMode u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalCableDiagnosticStatus_HHD */ -#define AQ_GlobalCableDiagnosticStatus_HHD_baseRegisterAddress 0xC800 -/*! \brief MMD address of structure AQ_GlobalCableDiagnosticStatus_HHD */ -#define AQ_GlobalCableDiagnosticStatus_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure pairAStatus in AQ_GlobalCableDiagnosticStatus_HHD */ -#define AQ_GlobalCableDiagnosticStatus_HHD_pairAStatus 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pairAStatus in AQ_GlobalCableDiagnosticStatus_HHD */ -#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairAStatus u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pairAStatus in AQ_GlobalCableDiagnosticStatus_HHD */ -#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairAStatus u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pairBStatus in AQ_GlobalCableDiagnosticStatus_HHD */ -#define AQ_GlobalCableDiagnosticStatus_HHD_pairBStatus 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pairBStatus in AQ_GlobalCableDiagnosticStatus_HHD */ -#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairBStatus u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pairBStatus in AQ_GlobalCableDiagnosticStatus_HHD */ -#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairBStatus u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pairCStatus in AQ_GlobalCableDiagnosticStatus_HHD */ -#define AQ_GlobalCableDiagnosticStatus_HHD_pairCStatus 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pairCStatus in AQ_GlobalCableDiagnosticStatus_HHD */ -#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairCStatus u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pairCStatus in AQ_GlobalCableDiagnosticStatus_HHD */ -#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairCStatus u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pairDStatus in AQ_GlobalCableDiagnosticStatus_HHD */ -#define AQ_GlobalCableDiagnosticStatus_HHD_pairDStatus 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pairDStatus in AQ_GlobalCableDiagnosticStatus_HHD */ -#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairDStatus u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pairDStatus in AQ_GlobalCableDiagnosticStatus_HHD */ -#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairDStatus u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ -#define AQ_GlobalCableDiagnosticStatus_HHD_pairAReflection_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ -#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairAReflection_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ -#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairAReflection_1 u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ -#define AQ_GlobalCableDiagnosticStatus_HHD_pairAReflection_2 1 -/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ -#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairAReflection_2 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ -#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairAReflection_2 u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure impulseResponseMSW in AQ_GlobalCableDiagnosticStatus_HHD */ -#define AQ_GlobalCableDiagnosticStatus_HHD_impulseResponseMSW 2 -/*! \brief Preprocessor variable to relate field to bit position in structure impulseResponseMSW in AQ_GlobalCableDiagnosticStatus_HHD */ -#define bits_AQ_GlobalCableDiagnosticStatus_HHD_impulseResponseMSW u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure impulseResponseMSW in AQ_GlobalCableDiagnosticStatus_HHD */ -#define word_AQ_GlobalCableDiagnosticStatus_HHD_impulseResponseMSW u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ -#define AQ_GlobalCableDiagnosticStatus_HHD_pairBReflection_1 3 -/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ -#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairBReflection_1 u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ -#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairBReflection_1 u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ -#define AQ_GlobalCableDiagnosticStatus_HHD_pairBReflection_2 3 -/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ -#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairBReflection_2 u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ -#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairBReflection_2 u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure impulseResponseLSW in AQ_GlobalCableDiagnosticStatus_HHD */ -#define AQ_GlobalCableDiagnosticStatus_HHD_impulseResponseLSW 4 -/*! \brief Preprocessor variable to relate field to bit position in structure impulseResponseLSW in AQ_GlobalCableDiagnosticStatus_HHD */ -#define bits_AQ_GlobalCableDiagnosticStatus_HHD_impulseResponseLSW u4.bits_4 -/*! \brief Preprocessor variable to relate field to word position in structure impulseResponseLSW in AQ_GlobalCableDiagnosticStatus_HHD */ -#define word_AQ_GlobalCableDiagnosticStatus_HHD_impulseResponseLSW u4.word_4 -/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ -#define AQ_GlobalCableDiagnosticStatus_HHD_pairCReflection_1 5 -/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ -#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairCReflection_1 u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ -#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairCReflection_1 u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ -#define AQ_GlobalCableDiagnosticStatus_HHD_pairCReflection_2 5 -/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ -#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairCReflection_2 u5.bits_5 -/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ -#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairCReflection_2 u5.word_5 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_1 in AQ_GlobalCableDiagnosticStatus_HHD */ -#define AQ_GlobalCableDiagnosticStatus_HHD_reserved_1 6 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_1 in AQ_GlobalCableDiagnosticStatus_HHD */ -#define bits_AQ_GlobalCableDiagnosticStatus_HHD_reserved_1 u6.bits_6 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_1 in AQ_GlobalCableDiagnosticStatus_HHD */ -#define word_AQ_GlobalCableDiagnosticStatus_HHD_reserved_1 u6.word_6 -/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ -#define AQ_GlobalCableDiagnosticStatus_HHD_pairDReflection_1 7 -/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ -#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairDReflection_1 u7.bits_7 -/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_1 in AQ_GlobalCableDiagnosticStatus_HHD */ -#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairDReflection_1 u7.word_7 -/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ -#define AQ_GlobalCableDiagnosticStatus_HHD_pairDReflection_2 7 -/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ -#define bits_AQ_GlobalCableDiagnosticStatus_HHD_pairDReflection_2 u7.bits_7 -/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_2 in AQ_GlobalCableDiagnosticStatus_HHD */ -#define word_AQ_GlobalCableDiagnosticStatus_HHD_pairDReflection_2 u7.word_7 - -/*! \brief Base register address of structure AQ_GlobalThermalStatus_HHD */ -#define AQ_GlobalThermalStatus_HHD_baseRegisterAddress 0xC820 -/*! \brief MMD address of structure AQ_GlobalThermalStatus_HHD */ -#define AQ_GlobalThermalStatus_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure temperature in AQ_GlobalThermalStatus_HHD */ -#define AQ_GlobalThermalStatus_HHD_temperature 0 -/*! \brief Preprocessor variable to relate field to bit position in structure temperature in AQ_GlobalThermalStatus_HHD */ -#define bits_AQ_GlobalThermalStatus_HHD_temperature u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure temperature in AQ_GlobalThermalStatus_HHD */ -#define word_AQ_GlobalThermalStatus_HHD_temperature u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure temperatureReady in AQ_GlobalThermalStatus_HHD */ -#define AQ_GlobalThermalStatus_HHD_temperatureReady 1 -/*! \brief Preprocessor variable to relate field to bit position in structure temperatureReady in AQ_GlobalThermalStatus_HHD */ -#define bits_AQ_GlobalThermalStatus_HHD_temperatureReady u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure temperatureReady in AQ_GlobalThermalStatus_HHD */ -#define word_AQ_GlobalThermalStatus_HHD_temperatureReady u1.word_1 - -/*! \brief Base register address of structure AQ_GlobalGeneralStatus_HHD */ -#define AQ_GlobalGeneralStatus_HHD_baseRegisterAddress 0xC830 -/*! \brief MMD address of structure AQ_GlobalGeneralStatus_HHD */ -#define AQ_GlobalGeneralStatus_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureFailureState in AQ_GlobalGeneralStatus_HHD */ -#define AQ_GlobalGeneralStatus_HHD_highTemperatureFailureState 0 -/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureFailureState in AQ_GlobalGeneralStatus_HHD */ -#define bits_AQ_GlobalGeneralStatus_HHD_highTemperatureFailureState u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureFailureState in AQ_GlobalGeneralStatus_HHD */ -#define word_AQ_GlobalGeneralStatus_HHD_highTemperatureFailureState u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureFailureState in AQ_GlobalGeneralStatus_HHD */ -#define AQ_GlobalGeneralStatus_HHD_lowTemperatureFailureState 0 -/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureFailureState in AQ_GlobalGeneralStatus_HHD */ -#define bits_AQ_GlobalGeneralStatus_HHD_lowTemperatureFailureState u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureFailureState in AQ_GlobalGeneralStatus_HHD */ -#define word_AQ_GlobalGeneralStatus_HHD_lowTemperatureFailureState u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureWarningState in AQ_GlobalGeneralStatus_HHD */ -#define AQ_GlobalGeneralStatus_HHD_highTemperatureWarningState 0 -/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureWarningState in AQ_GlobalGeneralStatus_HHD */ -#define bits_AQ_GlobalGeneralStatus_HHD_highTemperatureWarningState u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureWarningState in AQ_GlobalGeneralStatus_HHD */ -#define word_AQ_GlobalGeneralStatus_HHD_highTemperatureWarningState u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureWarningState in AQ_GlobalGeneralStatus_HHD */ -#define AQ_GlobalGeneralStatus_HHD_lowTemperatureWarningState 0 -/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureWarningState in AQ_GlobalGeneralStatus_HHD */ -#define bits_AQ_GlobalGeneralStatus_HHD_lowTemperatureWarningState u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureWarningState in AQ_GlobalGeneralStatus_HHD */ -#define word_AQ_GlobalGeneralStatus_HHD_lowTemperatureWarningState u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure processorIntensiveMdioOperationIn_Progress in AQ_GlobalGeneralStatus_HHD */ -#define AQ_GlobalGeneralStatus_HHD_processorIntensiveMdioOperationIn_Progress 1 -/*! \brief Preprocessor variable to relate field to bit position in structure processorIntensiveMdioOperationIn_Progress in AQ_GlobalGeneralStatus_HHD */ -#define bits_AQ_GlobalGeneralStatus_HHD_processorIntensiveMdioOperationIn_Progress u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure processorIntensiveMdioOperationIn_Progress in AQ_GlobalGeneralStatus_HHD */ -#define word_AQ_GlobalGeneralStatus_HHD_processorIntensiveMdioOperationIn_Progress u1.word_1 - -/*! \brief Base register address of structure AQ_GlobalPinStatus_HHD */ -#define AQ_GlobalPinStatus_HHD_baseRegisterAddress 0xC840 -/*! \brief MMD address of structure AQ_GlobalPinStatus_HHD */ -#define AQ_GlobalPinStatus_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure dcMasterN in AQ_GlobalPinStatus_HHD */ -#define AQ_GlobalPinStatus_HHD_dcMasterN 0 -/*! \brief Preprocessor variable to relate field to bit position in structure dcMasterN in AQ_GlobalPinStatus_HHD */ -#define bits_AQ_GlobalPinStatus_HHD_dcMasterN u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure dcMasterN in AQ_GlobalPinStatus_HHD */ -#define word_AQ_GlobalPinStatus_HHD_dcMasterN u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure packageConnectivity in AQ_GlobalPinStatus_HHD */ -#define AQ_GlobalPinStatus_HHD_packageConnectivity 0 -/*! \brief Preprocessor variable to relate field to bit position in structure packageConnectivity in AQ_GlobalPinStatus_HHD */ -#define bits_AQ_GlobalPinStatus_HHD_packageConnectivity u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure packageConnectivity in AQ_GlobalPinStatus_HHD */ -#define word_AQ_GlobalPinStatus_HHD_packageConnectivity u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure txEnable in AQ_GlobalPinStatus_HHD */ -#define AQ_GlobalPinStatus_HHD_txEnable 0 -/*! \brief Preprocessor variable to relate field to bit position in structure txEnable in AQ_GlobalPinStatus_HHD */ -#define bits_AQ_GlobalPinStatus_HHD_txEnable u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure txEnable in AQ_GlobalPinStatus_HHD */ -#define word_AQ_GlobalPinStatus_HHD_txEnable u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure ledPullupState in AQ_GlobalPinStatus_HHD */ -#define AQ_GlobalPinStatus_HHD_ledPullupState 0 -/*! \brief Preprocessor variable to relate field to bit position in structure ledPullupState in AQ_GlobalPinStatus_HHD */ -#define bits_AQ_GlobalPinStatus_HHD_ledPullupState u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure ledPullupState in AQ_GlobalPinStatus_HHD */ -#define word_AQ_GlobalPinStatus_HHD_ledPullupState u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalDaisyChainStatus_HHD */ -#define AQ_GlobalDaisyChainStatus_HHD_baseRegisterAddress 0xC842 -/*! \brief MMD address of structure AQ_GlobalDaisyChainStatus_HHD */ -#define AQ_GlobalDaisyChainStatus_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure rxDaisyChainCalculatedCrc in AQ_GlobalDaisyChainStatus_HHD */ -#define AQ_GlobalDaisyChainStatus_HHD_rxDaisyChainCalculatedCrc 0 -/*! \brief Preprocessor variable to relate field to bit position in structure rxDaisyChainCalculatedCrc in AQ_GlobalDaisyChainStatus_HHD */ -#define bits_AQ_GlobalDaisyChainStatus_HHD_rxDaisyChainCalculatedCrc u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure rxDaisyChainCalculatedCrc in AQ_GlobalDaisyChainStatus_HHD */ -#define word_AQ_GlobalDaisyChainStatus_HHD_rxDaisyChainCalculatedCrc u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalFaultMessage_HHD */ -#define AQ_GlobalFaultMessage_HHD_baseRegisterAddress 0xC850 -/*! \brief MMD address of structure AQ_GlobalFaultMessage_HHD */ -#define AQ_GlobalFaultMessage_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure message in AQ_GlobalFaultMessage_HHD */ -#define AQ_GlobalFaultMessage_HHD_message 0 -/*! \brief Preprocessor variable to relate field to bit position in structure message in AQ_GlobalFaultMessage_HHD */ -#define bits_AQ_GlobalFaultMessage_HHD_message u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure message in AQ_GlobalFaultMessage_HHD */ -#define word_AQ_GlobalFaultMessage_HHD_message u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_baseRegisterAddress 0xC880 -/*! \brief MMD address of structure AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure reserved_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_1 0 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_1 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_1 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_1 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_1 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_1 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_2 0 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_2 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_2 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_2 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_2 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_2 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_3 0 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_3 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_3 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_3 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_3 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_3 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_4 0 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_4 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_4 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pairAReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_4 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pairAReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_4 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pairAReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairAReflection_4 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_5 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_5 1 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_5 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_5 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_5 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_5 u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_1 1 -/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_1 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_1 u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_6 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_6 1 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_6 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_6 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_6 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_6 u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_2 1 -/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_2 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_2 u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_7 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_7 1 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_7 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_7 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_7 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_7 u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_3 1 -/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_3 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_3 u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_8 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_8 1 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_8 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_8 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_8 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_8 u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure pairBReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_4 1 -/*! \brief Preprocessor variable to relate field to bit position in structure pairBReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_4 u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure pairBReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairBReflection_4 u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_9 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_9 2 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_9 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_9 u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_9 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_9 u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_1 2 -/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_1 u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_1 u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_10 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_10 2 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_10 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_10 u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_10 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_10 u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_2 2 -/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_2 u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_2 u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_11 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_11 2 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_11 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_11 u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_11 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_11 u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_3 2 -/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_3 u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_3 u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_12 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_12 2 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_12 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_12 u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_12 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_12 u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure pairCReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_4 2 -/*! \brief Preprocessor variable to relate field to bit position in structure pairCReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_4 u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure pairCReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairCReflection_4 u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_13 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_13 3 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_13 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_13 u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_13 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_13 u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_1 3 -/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_1 u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_1 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_1 u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_14 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_14 3 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_14 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_14 u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_14 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_14 u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_2 3 -/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_2 u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_2 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_2 u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_15 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_15 3 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_15 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_15 u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_15 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_15 u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_3 3 -/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_3 u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_3 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_3 u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure reserved_16 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_reserved_16 3 -/*! \brief Preprocessor variable to relate field to bit position in structure reserved_16 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_16 u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure reserved_16 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_reserved_16 u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure pairDReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_4 3 -/*! \brief Preprocessor variable to relate field to bit position in structure pairDReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define bits_AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_4 u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure pairDReflection_4 in AQ_GlobalCableDiagnosticImpedance_HHD */ -#define word_AQ_GlobalCableDiagnosticImpedance_HHD_pairDReflection_4 u3.word_3 - -/*! \brief Base register address of structure AQ_GlobalStatus_HHD */ -#define AQ_GlobalStatus_HHD_baseRegisterAddress 0xC884 -/*! \brief MMD address of structure AQ_GlobalStatus_HHD */ -#define AQ_GlobalStatus_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure reservedStatus_0 in AQ_GlobalStatus_HHD */ -#define AQ_GlobalStatus_HHD_reservedStatus_0 0 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedStatus_0 in AQ_GlobalStatus_HHD */ -#define bits_AQ_GlobalStatus_HHD_reservedStatus_0 u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure reservedStatus_0 in AQ_GlobalStatus_HHD */ -#define word_AQ_GlobalStatus_HHD_reservedStatus_0 u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure cableLength in AQ_GlobalStatus_HHD */ -#define AQ_GlobalStatus_HHD_cableLength 0 -/*! \brief Preprocessor variable to relate field to bit position in structure cableLength in AQ_GlobalStatus_HHD */ -#define bits_AQ_GlobalStatus_HHD_cableLength u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure cableLength in AQ_GlobalStatus_HHD */ -#define word_AQ_GlobalStatus_HHD_cableLength u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalReservedStatus_HHD */ -#define AQ_GlobalReservedStatus_HHD_baseRegisterAddress 0xC885 -/*! \brief MMD address of structure AQ_GlobalReservedStatus_HHD */ -#define AQ_GlobalReservedStatus_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure nearlySecondsMSW in AQ_GlobalReservedStatus_HHD */ -#define AQ_GlobalReservedStatus_HHD_nearlySecondsMSW 0 -/*! \brief Preprocessor variable to relate field to bit position in structure nearlySecondsMSW in AQ_GlobalReservedStatus_HHD */ -#define bits_AQ_GlobalReservedStatus_HHD_nearlySecondsMSW u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure nearlySecondsMSW in AQ_GlobalReservedStatus_HHD */ -#define word_AQ_GlobalReservedStatus_HHD_nearlySecondsMSW u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure xenpakNvrStatus in AQ_GlobalReservedStatus_HHD */ -#define AQ_GlobalReservedStatus_HHD_xenpakNvrStatus 0 -/*! \brief Preprocessor variable to relate field to bit position in structure xenpakNvrStatus in AQ_GlobalReservedStatus_HHD */ -#define bits_AQ_GlobalReservedStatus_HHD_xenpakNvrStatus u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure xenpakNvrStatus in AQ_GlobalReservedStatus_HHD */ -#define word_AQ_GlobalReservedStatus_HHD_xenpakNvrStatus u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure firmwareBuildID in AQ_GlobalReservedStatus_HHD */ -#define AQ_GlobalReservedStatus_HHD_firmwareBuildID 0 -/*! \brief Preprocessor variable to relate field to bit position in structure firmwareBuildID in AQ_GlobalReservedStatus_HHD */ -#define bits_AQ_GlobalReservedStatus_HHD_firmwareBuildID u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure firmwareBuildID in AQ_GlobalReservedStatus_HHD */ -#define word_AQ_GlobalReservedStatus_HHD_firmwareBuildID u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure provisioningID in AQ_GlobalReservedStatus_HHD */ -#define AQ_GlobalReservedStatus_HHD_provisioningID 0 -/*! \brief Preprocessor variable to relate field to bit position in structure provisioningID in AQ_GlobalReservedStatus_HHD */ -#define bits_AQ_GlobalReservedStatus_HHD_provisioningID u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure provisioningID in AQ_GlobalReservedStatus_HHD */ -#define word_AQ_GlobalReservedStatus_HHD_provisioningID u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure nearlySecondsLSW in AQ_GlobalReservedStatus_HHD */ -#define AQ_GlobalReservedStatus_HHD_nearlySecondsLSW 1 -/*! \brief Preprocessor variable to relate field to bit position in structure nearlySecondsLSW in AQ_GlobalReservedStatus_HHD */ -#define bits_AQ_GlobalReservedStatus_HHD_nearlySecondsLSW u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure nearlySecondsLSW in AQ_GlobalReservedStatus_HHD */ -#define word_AQ_GlobalReservedStatus_HHD_nearlySecondsLSW u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure dteStatus in AQ_GlobalReservedStatus_HHD */ -#define AQ_GlobalReservedStatus_HHD_dteStatus 2 -/*! \brief Preprocessor variable to relate field to bit position in structure dteStatus in AQ_GlobalReservedStatus_HHD */ -#define bits_AQ_GlobalReservedStatus_HHD_dteStatus u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure dteStatus in AQ_GlobalReservedStatus_HHD */ -#define word_AQ_GlobalReservedStatus_HHD_dteStatus u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure powerUpStallStatus in AQ_GlobalReservedStatus_HHD */ -#define AQ_GlobalReservedStatus_HHD_powerUpStallStatus 2 -/*! \brief Preprocessor variable to relate field to bit position in structure powerUpStallStatus in AQ_GlobalReservedStatus_HHD */ -#define bits_AQ_GlobalReservedStatus_HHD_powerUpStallStatus u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure powerUpStallStatus in AQ_GlobalReservedStatus_HHD */ -#define word_AQ_GlobalReservedStatus_HHD_powerUpStallStatus u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure reservedStatus_3 in AQ_GlobalReservedStatus_HHD */ -#define AQ_GlobalReservedStatus_HHD_reservedStatus_3 2 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedStatus_3 in AQ_GlobalReservedStatus_HHD */ -#define bits_AQ_GlobalReservedStatus_HHD_reservedStatus_3 u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure reservedStatus_3 in AQ_GlobalReservedStatus_HHD */ -#define word_AQ_GlobalReservedStatus_HHD_reservedStatus_3 u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure loopbackStatus in AQ_GlobalReservedStatus_HHD */ -#define AQ_GlobalReservedStatus_HHD_loopbackStatus 3 -/*! \brief Preprocessor variable to relate field to bit position in structure loopbackStatus in AQ_GlobalReservedStatus_HHD */ -#define bits_AQ_GlobalReservedStatus_HHD_loopbackStatus u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure loopbackStatus in AQ_GlobalReservedStatus_HHD */ -#define word_AQ_GlobalReservedStatus_HHD_loopbackStatus u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure reservedStatus_4 in AQ_GlobalReservedStatus_HHD */ -#define AQ_GlobalReservedStatus_HHD_reservedStatus_4 3 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedStatus_4 in AQ_GlobalReservedStatus_HHD */ -#define bits_AQ_GlobalReservedStatus_HHD_reservedStatus_4 u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure reservedStatus_4 in AQ_GlobalReservedStatus_HHD */ -#define word_AQ_GlobalReservedStatus_HHD_reservedStatus_4 u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure mdiPacketGenerationStatus in AQ_GlobalReservedStatus_HHD */ -#define AQ_GlobalReservedStatus_HHD_mdiPacketGenerationStatus 3 -/*! \brief Preprocessor variable to relate field to bit position in structure mdiPacketGenerationStatus in AQ_GlobalReservedStatus_HHD */ -#define bits_AQ_GlobalReservedStatus_HHD_mdiPacketGenerationStatus u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure mdiPacketGenerationStatus in AQ_GlobalReservedStatus_HHD */ -#define word_AQ_GlobalReservedStatus_HHD_mdiPacketGenerationStatus u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure look_asidePortPacketGenerationStatus in AQ_GlobalReservedStatus_HHD */ -#define AQ_GlobalReservedStatus_HHD_look_asidePortPacketGenerationStatus 3 -/*! \brief Preprocessor variable to relate field to bit position in structure look_asidePortPacketGenerationStatus in AQ_GlobalReservedStatus_HHD */ -#define bits_AQ_GlobalReservedStatus_HHD_look_asidePortPacketGenerationStatus u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure look_asidePortPacketGenerationStatus in AQ_GlobalReservedStatus_HHD */ -#define word_AQ_GlobalReservedStatus_HHD_look_asidePortPacketGenerationStatus u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure systemI_fPacketGenerationStatus in AQ_GlobalReservedStatus_HHD */ -#define AQ_GlobalReservedStatus_HHD_systemI_fPacketGenerationStatus 3 -/*! \brief Preprocessor variable to relate field to bit position in structure systemI_fPacketGenerationStatus in AQ_GlobalReservedStatus_HHD */ -#define bits_AQ_GlobalReservedStatus_HHD_systemI_fPacketGenerationStatus u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure systemI_fPacketGenerationStatus in AQ_GlobalReservedStatus_HHD */ -#define word_AQ_GlobalReservedStatus_HHD_systemI_fPacketGenerationStatus u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure reservedStatus_4a in AQ_GlobalReservedStatus_HHD */ -#define AQ_GlobalReservedStatus_HHD_reservedStatus_4a 3 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedStatus_4a in AQ_GlobalReservedStatus_HHD */ -#define bits_AQ_GlobalReservedStatus_HHD_reservedStatus_4a u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure reservedStatus_4a in AQ_GlobalReservedStatus_HHD */ -#define word_AQ_GlobalReservedStatus_HHD_reservedStatus_4a u3.word_3 -/*! \brief Preprocessor variable to relate field to word number in structure rate in AQ_GlobalReservedStatus_HHD */ -#define AQ_GlobalReservedStatus_HHD_rate 3 -/*! \brief Preprocessor variable to relate field to bit position in structure rate in AQ_GlobalReservedStatus_HHD */ -#define bits_AQ_GlobalReservedStatus_HHD_rate u3.bits_3 -/*! \brief Preprocessor variable to relate field to word position in structure rate in AQ_GlobalReservedStatus_HHD */ -#define word_AQ_GlobalReservedStatus_HHD_rate u3.word_3 - -/*! \brief Base register address of structure AQ_GlobalAlarms_HHD */ -#define AQ_GlobalAlarms_HHD_baseRegisterAddress 0xCC00 -/*! \brief MMD address of structure AQ_GlobalAlarms_HHD */ -#define AQ_GlobalAlarms_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureFailure in AQ_GlobalAlarms_HHD */ -#define AQ_GlobalAlarms_HHD_highTemperatureFailure 0 -/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureFailure in AQ_GlobalAlarms_HHD */ -#define bits_AQ_GlobalAlarms_HHD_highTemperatureFailure u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureFailure in AQ_GlobalAlarms_HHD */ -#define word_AQ_GlobalAlarms_HHD_highTemperatureFailure u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureFailure in AQ_GlobalAlarms_HHD */ -#define AQ_GlobalAlarms_HHD_lowTemperatureFailure 0 -/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureFailure in AQ_GlobalAlarms_HHD */ -#define bits_AQ_GlobalAlarms_HHD_lowTemperatureFailure u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureFailure in AQ_GlobalAlarms_HHD */ -#define word_AQ_GlobalAlarms_HHD_lowTemperatureFailure u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureWarning in AQ_GlobalAlarms_HHD */ -#define AQ_GlobalAlarms_HHD_highTemperatureWarning 0 -/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureWarning in AQ_GlobalAlarms_HHD */ -#define bits_AQ_GlobalAlarms_HHD_highTemperatureWarning u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureWarning in AQ_GlobalAlarms_HHD */ -#define word_AQ_GlobalAlarms_HHD_highTemperatureWarning u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureWarning in AQ_GlobalAlarms_HHD */ -#define AQ_GlobalAlarms_HHD_lowTemperatureWarning 0 -/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureWarning in AQ_GlobalAlarms_HHD */ -#define bits_AQ_GlobalAlarms_HHD_lowTemperatureWarning u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureWarning in AQ_GlobalAlarms_HHD */ -#define word_AQ_GlobalAlarms_HHD_lowTemperatureWarning u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure resetCompleted in AQ_GlobalAlarms_HHD */ -#define AQ_GlobalAlarms_HHD_resetCompleted 0 -/*! \brief Preprocessor variable to relate field to bit position in structure resetCompleted in AQ_GlobalAlarms_HHD */ -#define bits_AQ_GlobalAlarms_HHD_resetCompleted u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure resetCompleted in AQ_GlobalAlarms_HHD */ -#define word_AQ_GlobalAlarms_HHD_resetCompleted u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure deviceFault in AQ_GlobalAlarms_HHD */ -#define AQ_GlobalAlarms_HHD_deviceFault 0 -/*! \brief Preprocessor variable to relate field to bit position in structure deviceFault in AQ_GlobalAlarms_HHD */ -#define bits_AQ_GlobalAlarms_HHD_deviceFault u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure deviceFault in AQ_GlobalAlarms_HHD */ -#define word_AQ_GlobalAlarms_HHD_deviceFault u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmA in AQ_GlobalAlarms_HHD */ -#define AQ_GlobalAlarms_HHD_reservedAlarmA 0 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmA in AQ_GlobalAlarms_HHD */ -#define bits_AQ_GlobalAlarms_HHD_reservedAlarmA u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmA in AQ_GlobalAlarms_HHD */ -#define word_AQ_GlobalAlarms_HHD_reservedAlarmA u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmB in AQ_GlobalAlarms_HHD */ -#define AQ_GlobalAlarms_HHD_reservedAlarmB 0 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmB in AQ_GlobalAlarms_HHD */ -#define bits_AQ_GlobalAlarms_HHD_reservedAlarmB u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmB in AQ_GlobalAlarms_HHD */ -#define word_AQ_GlobalAlarms_HHD_reservedAlarmB u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmC in AQ_GlobalAlarms_HHD */ -#define AQ_GlobalAlarms_HHD_reservedAlarmC 0 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmC in AQ_GlobalAlarms_HHD */ -#define bits_AQ_GlobalAlarms_HHD_reservedAlarmC u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmC in AQ_GlobalAlarms_HHD */ -#define word_AQ_GlobalAlarms_HHD_reservedAlarmC u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmD in AQ_GlobalAlarms_HHD */ -#define AQ_GlobalAlarms_HHD_reservedAlarmD 0 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmD in AQ_GlobalAlarms_HHD */ -#define bits_AQ_GlobalAlarms_HHD_reservedAlarmD u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmD in AQ_GlobalAlarms_HHD */ -#define word_AQ_GlobalAlarms_HHD_reservedAlarmD u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure smartPower_downEntered in AQ_GlobalAlarms_HHD */ -#define AQ_GlobalAlarms_HHD_smartPower_downEntered 1 -/*! \brief Preprocessor variable to relate field to bit position in structure smartPower_downEntered in AQ_GlobalAlarms_HHD */ -#define bits_AQ_GlobalAlarms_HHD_smartPower_downEntered u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure smartPower_downEntered in AQ_GlobalAlarms_HHD */ -#define word_AQ_GlobalAlarms_HHD_smartPower_downEntered u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure xenpakAlarm in AQ_GlobalAlarms_HHD */ -#define AQ_GlobalAlarms_HHD_xenpakAlarm 1 -/*! \brief Preprocessor variable to relate field to bit position in structure xenpakAlarm in AQ_GlobalAlarms_HHD */ -#define bits_AQ_GlobalAlarms_HHD_xenpakAlarm u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure xenpakAlarm in AQ_GlobalAlarms_HHD */ -#define word_AQ_GlobalAlarms_HHD_xenpakAlarm u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure ipPhoneDetect in AQ_GlobalAlarms_HHD */ -#define AQ_GlobalAlarms_HHD_ipPhoneDetect 1 -/*! \brief Preprocessor variable to relate field to bit position in structure ipPhoneDetect in AQ_GlobalAlarms_HHD */ -#define bits_AQ_GlobalAlarms_HHD_ipPhoneDetect u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure ipPhoneDetect in AQ_GlobalAlarms_HHD */ -#define word_AQ_GlobalAlarms_HHD_ipPhoneDetect u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure dteStatusChange in AQ_GlobalAlarms_HHD */ -#define AQ_GlobalAlarms_HHD_dteStatusChange 1 -/*! \brief Preprocessor variable to relate field to bit position in structure dteStatusChange in AQ_GlobalAlarms_HHD */ -#define bits_AQ_GlobalAlarms_HHD_dteStatusChange u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure dteStatusChange in AQ_GlobalAlarms_HHD */ -#define word_AQ_GlobalAlarms_HHD_dteStatusChange u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarms in AQ_GlobalAlarms_HHD */ -#define AQ_GlobalAlarms_HHD_reservedAlarms 1 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarms in AQ_GlobalAlarms_HHD */ -#define bits_AQ_GlobalAlarms_HHD_reservedAlarms u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarms in AQ_GlobalAlarms_HHD */ -#define word_AQ_GlobalAlarms_HHD_reservedAlarms u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure mdioCommandHandlingOverflow in AQ_GlobalAlarms_HHD */ -#define AQ_GlobalAlarms_HHD_mdioCommandHandlingOverflow 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mdioCommandHandlingOverflow in AQ_GlobalAlarms_HHD */ -#define bits_AQ_GlobalAlarms_HHD_mdioCommandHandlingOverflow u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mdioCommandHandlingOverflow in AQ_GlobalAlarms_HHD */ -#define word_AQ_GlobalAlarms_HHD_mdioCommandHandlingOverflow u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure nvrOperationComplete in AQ_GlobalAlarms_HHD */ -#define AQ_GlobalAlarms_HHD_nvrOperationComplete 2 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrOperationComplete in AQ_GlobalAlarms_HHD */ -#define bits_AQ_GlobalAlarms_HHD_nvrOperationComplete u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure nvrOperationComplete in AQ_GlobalAlarms_HHD */ -#define word_AQ_GlobalAlarms_HHD_nvrOperationComplete u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure mailboxOperation_Complete in AQ_GlobalAlarms_HHD */ -#define AQ_GlobalAlarms_HHD_mailboxOperation_Complete 2 -/*! \brief Preprocessor variable to relate field to bit position in structure mailboxOperation_Complete in AQ_GlobalAlarms_HHD */ -#define bits_AQ_GlobalAlarms_HHD_mailboxOperation_Complete u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure mailboxOperation_Complete in AQ_GlobalAlarms_HHD */ -#define word_AQ_GlobalAlarms_HHD_mailboxOperation_Complete u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure upDramParityError in AQ_GlobalAlarms_HHD */ -#define AQ_GlobalAlarms_HHD_upDramParityError 2 -/*! \brief Preprocessor variable to relate field to bit position in structure upDramParityError in AQ_GlobalAlarms_HHD */ -#define bits_AQ_GlobalAlarms_HHD_upDramParityError u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure upDramParityError in AQ_GlobalAlarms_HHD */ -#define word_AQ_GlobalAlarms_HHD_upDramParityError u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure upIramParityError in AQ_GlobalAlarms_HHD */ -#define AQ_GlobalAlarms_HHD_upIramParityError 2 -/*! \brief Preprocessor variable to relate field to bit position in structure upIramParityError in AQ_GlobalAlarms_HHD */ -#define bits_AQ_GlobalAlarms_HHD_upIramParityError u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure upIramParityError in AQ_GlobalAlarms_HHD */ -#define word_AQ_GlobalAlarms_HHD_upIramParityError u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure txEnableStateChange in AQ_GlobalAlarms_HHD */ -#define AQ_GlobalAlarms_HHD_txEnableStateChange 2 -/*! \brief Preprocessor variable to relate field to bit position in structure txEnableStateChange in AQ_GlobalAlarms_HHD */ -#define bits_AQ_GlobalAlarms_HHD_txEnableStateChange u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure txEnableStateChange in AQ_GlobalAlarms_HHD */ -#define word_AQ_GlobalAlarms_HHD_txEnableStateChange u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure mdioMMD_Error in AQ_GlobalAlarms_HHD */ -#define AQ_GlobalAlarms_HHD_mdioMMD_Error 2 -/*! \brief Preprocessor variable to relate field to bit position in structure mdioMMD_Error in AQ_GlobalAlarms_HHD */ -#define bits_AQ_GlobalAlarms_HHD_mdioMMD_Error u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure mdioMMD_Error in AQ_GlobalAlarms_HHD */ -#define word_AQ_GlobalAlarms_HHD_mdioMMD_Error u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure mdioTimeoutError in AQ_GlobalAlarms_HHD */ -#define AQ_GlobalAlarms_HHD_mdioTimeoutError 2 -/*! \brief Preprocessor variable to relate field to bit position in structure mdioTimeoutError in AQ_GlobalAlarms_HHD */ -#define bits_AQ_GlobalAlarms_HHD_mdioTimeoutError u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure mdioTimeoutError in AQ_GlobalAlarms_HHD */ -#define word_AQ_GlobalAlarms_HHD_mdioTimeoutError u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure watchdogTimerAlarm in AQ_GlobalAlarms_HHD */ -#define AQ_GlobalAlarms_HHD_watchdogTimerAlarm 2 -/*! \brief Preprocessor variable to relate field to bit position in structure watchdogTimerAlarm in AQ_GlobalAlarms_HHD */ -#define bits_AQ_GlobalAlarms_HHD_watchdogTimerAlarm u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure watchdogTimerAlarm in AQ_GlobalAlarms_HHD */ -#define word_AQ_GlobalAlarms_HHD_watchdogTimerAlarm u2.word_2 - -/*! \brief Base register address of structure AQ_GlobalInterruptMask_HHD */ -#define AQ_GlobalInterruptMask_HHD_baseRegisterAddress 0xD400 -/*! \brief MMD address of structure AQ_GlobalInterruptMask_HHD */ -#define AQ_GlobalInterruptMask_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureFailureMask in AQ_GlobalInterruptMask_HHD */ -#define AQ_GlobalInterruptMask_HHD_highTemperatureFailureMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureFailureMask in AQ_GlobalInterruptMask_HHD */ -#define bits_AQ_GlobalInterruptMask_HHD_highTemperatureFailureMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureFailureMask in AQ_GlobalInterruptMask_HHD */ -#define word_AQ_GlobalInterruptMask_HHD_highTemperatureFailureMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureFailureMask in AQ_GlobalInterruptMask_HHD */ -#define AQ_GlobalInterruptMask_HHD_lowTemperatureFailureMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureFailureMask in AQ_GlobalInterruptMask_HHD */ -#define bits_AQ_GlobalInterruptMask_HHD_lowTemperatureFailureMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureFailureMask in AQ_GlobalInterruptMask_HHD */ -#define word_AQ_GlobalInterruptMask_HHD_lowTemperatureFailureMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure highTemperatureWarningMask in AQ_GlobalInterruptMask_HHD */ -#define AQ_GlobalInterruptMask_HHD_highTemperatureWarningMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure highTemperatureWarningMask in AQ_GlobalInterruptMask_HHD */ -#define bits_AQ_GlobalInterruptMask_HHD_highTemperatureWarningMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure highTemperatureWarningMask in AQ_GlobalInterruptMask_HHD */ -#define word_AQ_GlobalInterruptMask_HHD_highTemperatureWarningMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure lowTemperatureWarningMask in AQ_GlobalInterruptMask_HHD */ -#define AQ_GlobalInterruptMask_HHD_lowTemperatureWarningMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure lowTemperatureWarningMask in AQ_GlobalInterruptMask_HHD */ -#define bits_AQ_GlobalInterruptMask_HHD_lowTemperatureWarningMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure lowTemperatureWarningMask in AQ_GlobalInterruptMask_HHD */ -#define word_AQ_GlobalInterruptMask_HHD_lowTemperatureWarningMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure resetCompletedMask in AQ_GlobalInterruptMask_HHD */ -#define AQ_GlobalInterruptMask_HHD_resetCompletedMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure resetCompletedMask in AQ_GlobalInterruptMask_HHD */ -#define bits_AQ_GlobalInterruptMask_HHD_resetCompletedMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure resetCompletedMask in AQ_GlobalInterruptMask_HHD */ -#define word_AQ_GlobalInterruptMask_HHD_resetCompletedMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure deviceFaultMask in AQ_GlobalInterruptMask_HHD */ -#define AQ_GlobalInterruptMask_HHD_deviceFaultMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure deviceFaultMask in AQ_GlobalInterruptMask_HHD */ -#define bits_AQ_GlobalInterruptMask_HHD_deviceFaultMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure deviceFaultMask in AQ_GlobalInterruptMask_HHD */ -#define word_AQ_GlobalInterruptMask_HHD_deviceFaultMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmAMask in AQ_GlobalInterruptMask_HHD */ -#define AQ_GlobalInterruptMask_HHD_reservedAlarmAMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmAMask in AQ_GlobalInterruptMask_HHD */ -#define bits_AQ_GlobalInterruptMask_HHD_reservedAlarmAMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmAMask in AQ_GlobalInterruptMask_HHD */ -#define word_AQ_GlobalInterruptMask_HHD_reservedAlarmAMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmBMask in AQ_GlobalInterruptMask_HHD */ -#define AQ_GlobalInterruptMask_HHD_reservedAlarmBMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmBMask in AQ_GlobalInterruptMask_HHD */ -#define bits_AQ_GlobalInterruptMask_HHD_reservedAlarmBMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmBMask in AQ_GlobalInterruptMask_HHD */ -#define word_AQ_GlobalInterruptMask_HHD_reservedAlarmBMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmCMask in AQ_GlobalInterruptMask_HHD */ -#define AQ_GlobalInterruptMask_HHD_reservedAlarmCMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmCMask in AQ_GlobalInterruptMask_HHD */ -#define bits_AQ_GlobalInterruptMask_HHD_reservedAlarmCMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmCMask in AQ_GlobalInterruptMask_HHD */ -#define word_AQ_GlobalInterruptMask_HHD_reservedAlarmCMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmDMask in AQ_GlobalInterruptMask_HHD */ -#define AQ_GlobalInterruptMask_HHD_reservedAlarmDMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmDMask in AQ_GlobalInterruptMask_HHD */ -#define bits_AQ_GlobalInterruptMask_HHD_reservedAlarmDMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmDMask in AQ_GlobalInterruptMask_HHD */ -#define word_AQ_GlobalInterruptMask_HHD_reservedAlarmDMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure smartPower_downEnteredMask in AQ_GlobalInterruptMask_HHD */ -#define AQ_GlobalInterruptMask_HHD_smartPower_downEnteredMask 1 -/*! \brief Preprocessor variable to relate field to bit position in structure smartPower_downEnteredMask in AQ_GlobalInterruptMask_HHD */ -#define bits_AQ_GlobalInterruptMask_HHD_smartPower_downEnteredMask u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure smartPower_downEnteredMask in AQ_GlobalInterruptMask_HHD */ -#define word_AQ_GlobalInterruptMask_HHD_smartPower_downEnteredMask u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure xenpakAlarmMask in AQ_GlobalInterruptMask_HHD */ -#define AQ_GlobalInterruptMask_HHD_xenpakAlarmMask 1 -/*! \brief Preprocessor variable to relate field to bit position in structure xenpakAlarmMask in AQ_GlobalInterruptMask_HHD */ -#define bits_AQ_GlobalInterruptMask_HHD_xenpakAlarmMask u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure xenpakAlarmMask in AQ_GlobalInterruptMask_HHD */ -#define word_AQ_GlobalInterruptMask_HHD_xenpakAlarmMask u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure ipPhoneDetectMask in AQ_GlobalInterruptMask_HHD */ -#define AQ_GlobalInterruptMask_HHD_ipPhoneDetectMask 1 -/*! \brief Preprocessor variable to relate field to bit position in structure ipPhoneDetectMask in AQ_GlobalInterruptMask_HHD */ -#define bits_AQ_GlobalInterruptMask_HHD_ipPhoneDetectMask u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure ipPhoneDetectMask in AQ_GlobalInterruptMask_HHD */ -#define word_AQ_GlobalInterruptMask_HHD_ipPhoneDetectMask u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure dteStatusChangeMask in AQ_GlobalInterruptMask_HHD */ -#define AQ_GlobalInterruptMask_HHD_dteStatusChangeMask 1 -/*! \brief Preprocessor variable to relate field to bit position in structure dteStatusChangeMask in AQ_GlobalInterruptMask_HHD */ -#define bits_AQ_GlobalInterruptMask_HHD_dteStatusChangeMask u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure dteStatusChangeMask in AQ_GlobalInterruptMask_HHD */ -#define word_AQ_GlobalInterruptMask_HHD_dteStatusChangeMask u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure reservedAlarmsMask in AQ_GlobalInterruptMask_HHD */ -#define AQ_GlobalInterruptMask_HHD_reservedAlarmsMask 1 -/*! \brief Preprocessor variable to relate field to bit position in structure reservedAlarmsMask in AQ_GlobalInterruptMask_HHD */ -#define bits_AQ_GlobalInterruptMask_HHD_reservedAlarmsMask u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure reservedAlarmsMask in AQ_GlobalInterruptMask_HHD */ -#define word_AQ_GlobalInterruptMask_HHD_reservedAlarmsMask u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure mdioCommandHandlingOverflowMask in AQ_GlobalInterruptMask_HHD */ -#define AQ_GlobalInterruptMask_HHD_mdioCommandHandlingOverflowMask 1 -/*! \brief Preprocessor variable to relate field to bit position in structure mdioCommandHandlingOverflowMask in AQ_GlobalInterruptMask_HHD */ -#define bits_AQ_GlobalInterruptMask_HHD_mdioCommandHandlingOverflowMask u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure mdioCommandHandlingOverflowMask in AQ_GlobalInterruptMask_HHD */ -#define word_AQ_GlobalInterruptMask_HHD_mdioCommandHandlingOverflowMask u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure diagnosticAlarmMask in AQ_GlobalInterruptMask_HHD */ -#define AQ_GlobalInterruptMask_HHD_diagnosticAlarmMask 1 -/*! \brief Preprocessor variable to relate field to bit position in structure diagnosticAlarmMask in AQ_GlobalInterruptMask_HHD */ -#define bits_AQ_GlobalInterruptMask_HHD_diagnosticAlarmMask u1.bits_1 -/*! \brief Preprocessor variable to relate field to word position in structure diagnosticAlarmMask in AQ_GlobalInterruptMask_HHD */ -#define word_AQ_GlobalInterruptMask_HHD_diagnosticAlarmMask u1.word_1 -/*! \brief Preprocessor variable to relate field to word number in structure nvrOperationCompleteMask in AQ_GlobalInterruptMask_HHD */ -#define AQ_GlobalInterruptMask_HHD_nvrOperationCompleteMask 2 -/*! \brief Preprocessor variable to relate field to bit position in structure nvrOperationCompleteMask in AQ_GlobalInterruptMask_HHD */ -#define bits_AQ_GlobalInterruptMask_HHD_nvrOperationCompleteMask u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure nvrOperationCompleteMask in AQ_GlobalInterruptMask_HHD */ -#define word_AQ_GlobalInterruptMask_HHD_nvrOperationCompleteMask u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure mailboxOperationCompleteMask in AQ_GlobalInterruptMask_HHD */ -#define AQ_GlobalInterruptMask_HHD_mailboxOperationCompleteMask 2 -/*! \brief Preprocessor variable to relate field to bit position in structure mailboxOperationCompleteMask in AQ_GlobalInterruptMask_HHD */ -#define bits_AQ_GlobalInterruptMask_HHD_mailboxOperationCompleteMask u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure mailboxOperationCompleteMask in AQ_GlobalInterruptMask_HHD */ -#define word_AQ_GlobalInterruptMask_HHD_mailboxOperationCompleteMask u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure upDramParityErrorMask in AQ_GlobalInterruptMask_HHD */ -#define AQ_GlobalInterruptMask_HHD_upDramParityErrorMask 2 -/*! \brief Preprocessor variable to relate field to bit position in structure upDramParityErrorMask in AQ_GlobalInterruptMask_HHD */ -#define bits_AQ_GlobalInterruptMask_HHD_upDramParityErrorMask u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure upDramParityErrorMask in AQ_GlobalInterruptMask_HHD */ -#define word_AQ_GlobalInterruptMask_HHD_upDramParityErrorMask u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure upIramParityErrorMask in AQ_GlobalInterruptMask_HHD */ -#define AQ_GlobalInterruptMask_HHD_upIramParityErrorMask 2 -/*! \brief Preprocessor variable to relate field to bit position in structure upIramParityErrorMask in AQ_GlobalInterruptMask_HHD */ -#define bits_AQ_GlobalInterruptMask_HHD_upIramParityErrorMask u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure upIramParityErrorMask in AQ_GlobalInterruptMask_HHD */ -#define word_AQ_GlobalInterruptMask_HHD_upIramParityErrorMask u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure txEnableStateChangeMask in AQ_GlobalInterruptMask_HHD */ -#define AQ_GlobalInterruptMask_HHD_txEnableStateChangeMask 2 -/*! \brief Preprocessor variable to relate field to bit position in structure txEnableStateChangeMask in AQ_GlobalInterruptMask_HHD */ -#define bits_AQ_GlobalInterruptMask_HHD_txEnableStateChangeMask u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure txEnableStateChangeMask in AQ_GlobalInterruptMask_HHD */ -#define word_AQ_GlobalInterruptMask_HHD_txEnableStateChangeMask u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure mdioMMD_ErrorMask in AQ_GlobalInterruptMask_HHD */ -#define AQ_GlobalInterruptMask_HHD_mdioMMD_ErrorMask 2 -/*! \brief Preprocessor variable to relate field to bit position in structure mdioMMD_ErrorMask in AQ_GlobalInterruptMask_HHD */ -#define bits_AQ_GlobalInterruptMask_HHD_mdioMMD_ErrorMask u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure mdioMMD_ErrorMask in AQ_GlobalInterruptMask_HHD */ -#define word_AQ_GlobalInterruptMask_HHD_mdioMMD_ErrorMask u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure mdioTimeoutErrorMask in AQ_GlobalInterruptMask_HHD */ -#define AQ_GlobalInterruptMask_HHD_mdioTimeoutErrorMask 2 -/*! \brief Preprocessor variable to relate field to bit position in structure mdioTimeoutErrorMask in AQ_GlobalInterruptMask_HHD */ -#define bits_AQ_GlobalInterruptMask_HHD_mdioTimeoutErrorMask u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure mdioTimeoutErrorMask in AQ_GlobalInterruptMask_HHD */ -#define word_AQ_GlobalInterruptMask_HHD_mdioTimeoutErrorMask u2.word_2 -/*! \brief Preprocessor variable to relate field to word number in structure watchdogTimerAlarmMask in AQ_GlobalInterruptMask_HHD */ -#define AQ_GlobalInterruptMask_HHD_watchdogTimerAlarmMask 2 -/*! \brief Preprocessor variable to relate field to bit position in structure watchdogTimerAlarmMask in AQ_GlobalInterruptMask_HHD */ -#define bits_AQ_GlobalInterruptMask_HHD_watchdogTimerAlarmMask u2.bits_2 -/*! \brief Preprocessor variable to relate field to word position in structure watchdogTimerAlarmMask in AQ_GlobalInterruptMask_HHD */ -#define word_AQ_GlobalInterruptMask_HHD_watchdogTimerAlarmMask u2.word_2 - -/*! \brief Base register address of structure AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_baseRegisterAddress 0xFC00 -/*! \brief MMD address of structure AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure pmaStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_pmaStandardAlarm_1Interrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pmaStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_pmaStandardAlarm_1Interrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pmaStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_pmaStandardAlarm_1Interrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pmaStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_pmaStandardAlarm_2Interrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pmaStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_pmaStandardAlarm_2Interrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pmaStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_pmaStandardAlarm_2Interrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_pcsStandardAlarm_1Interrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_pcsStandardAlarm_1Interrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_pcsStandardAlarm_1Interrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_pcsStandardAlarm_2Interrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_pcsStandardAlarm_2Interrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_pcsStandardAlarm_2Interrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_3Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_pcsStandardAlarm_3Interrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_3Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_pcsStandardAlarm_3Interrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_3Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_pcsStandardAlarm_3Interrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure phyXS_StandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_phyXS_StandardAlarms_1Interrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_StandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_phyXS_StandardAlarms_1Interrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure phyXS_StandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_phyXS_StandardAlarms_1Interrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure phyXS_StandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_phyXS_StandardAlarms_2Interrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_StandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_phyXS_StandardAlarms_2Interrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure phyXS_StandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_phyXS_StandardAlarms_2Interrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationStandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_autonegotiationStandardAlarms_1Interrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationStandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_autonegotiationStandardAlarms_1Interrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationStandardAlarms_1Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_autonegotiationStandardAlarms_1Interrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationStandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_autonegotiationStandardAlarms_2Interrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationStandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_autonegotiationStandardAlarms_2Interrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationStandardAlarms_2Interrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_autonegotiationStandardAlarms_2Interrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure gbeStandardAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_gbeStandardAlarmsInterrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure gbeStandardAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_gbeStandardAlarmsInterrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure gbeStandardAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_gbeStandardAlarmsInterrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure allVendorAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define AQ_GlobalChip_wideStandardInterruptFlags_HHD_allVendorAlarmsInterrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure allVendorAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define bits_AQ_GlobalChip_wideStandardInterruptFlags_HHD_allVendorAlarmsInterrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure allVendorAlarmsInterrupt in AQ_GlobalChip_wideStandardInterruptFlags_HHD */ -#define word_AQ_GlobalChip_wideStandardInterruptFlags_HHD_allVendorAlarmsInterrupt u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalChip_wideVendorInterruptFlags_HHD */ -#define AQ_GlobalChip_wideVendorInterruptFlags_HHD_baseRegisterAddress 0xFC01 -/*! \brief MMD address of structure AQ_GlobalChip_wideVendorInterruptFlags_HHD */ -#define AQ_GlobalChip_wideVendorInterruptFlags_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure pmaVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ -#define AQ_GlobalChip_wideVendorInterruptFlags_HHD_pmaVendorAlarmInterrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pmaVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ -#define bits_AQ_GlobalChip_wideVendorInterruptFlags_HHD_pmaVendorAlarmInterrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pmaVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ -#define word_AQ_GlobalChip_wideVendorInterruptFlags_HHD_pmaVendorAlarmInterrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pcsVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ -#define AQ_GlobalChip_wideVendorInterruptFlags_HHD_pcsVendorAlarmInterrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pcsVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ -#define bits_AQ_GlobalChip_wideVendorInterruptFlags_HHD_pcsVendorAlarmInterrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pcsVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ -#define word_AQ_GlobalChip_wideVendorInterruptFlags_HHD_pcsVendorAlarmInterrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure phyXS_VendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ -#define AQ_GlobalChip_wideVendorInterruptFlags_HHD_phyXS_VendorAlarmInterrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_VendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ -#define bits_AQ_GlobalChip_wideVendorInterruptFlags_HHD_phyXS_VendorAlarmInterrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure phyXS_VendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ -#define word_AQ_GlobalChip_wideVendorInterruptFlags_HHD_phyXS_VendorAlarmInterrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ -#define AQ_GlobalChip_wideVendorInterruptFlags_HHD_autonegotiationVendorAlarmInterrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ -#define bits_AQ_GlobalChip_wideVendorInterruptFlags_HHD_autonegotiationVendorAlarmInterrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ -#define word_AQ_GlobalChip_wideVendorInterruptFlags_HHD_autonegotiationVendorAlarmInterrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure gbeVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ -#define AQ_GlobalChip_wideVendorInterruptFlags_HHD_gbeVendorAlarmInterrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure gbeVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ -#define bits_AQ_GlobalChip_wideVendorInterruptFlags_HHD_gbeVendorAlarmInterrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure gbeVendorAlarmInterrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ -#define word_AQ_GlobalChip_wideVendorInterruptFlags_HHD_gbeVendorAlarmInterrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_1Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ -#define AQ_GlobalChip_wideVendorInterruptFlags_HHD_globalAlarms_1Interrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_1Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ -#define bits_AQ_GlobalChip_wideVendorInterruptFlags_HHD_globalAlarms_1Interrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_1Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ -#define word_AQ_GlobalChip_wideVendorInterruptFlags_HHD_globalAlarms_1Interrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_2Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ -#define AQ_GlobalChip_wideVendorInterruptFlags_HHD_globalAlarms_2Interrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_2Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ -#define bits_AQ_GlobalChip_wideVendorInterruptFlags_HHD_globalAlarms_2Interrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_2Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ -#define word_AQ_GlobalChip_wideVendorInterruptFlags_HHD_globalAlarms_2Interrupt u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_3Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ -#define AQ_GlobalChip_wideVendorInterruptFlags_HHD_globalAlarms_3Interrupt 0 -/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_3Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ -#define bits_AQ_GlobalChip_wideVendorInterruptFlags_HHD_globalAlarms_3Interrupt u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_3Interrupt in AQ_GlobalChip_wideVendorInterruptFlags_HHD */ -#define word_AQ_GlobalChip_wideVendorInterruptFlags_HHD_globalAlarms_3Interrupt u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define AQ_GlobalInterruptChip_wideStandardMask_HHD_baseRegisterAddress 0xFF00 -/*! \brief MMD address of structure AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define AQ_GlobalInterruptChip_wideStandardMask_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure pmaStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define AQ_GlobalInterruptChip_wideStandardMask_HHD_pmaStandardAlarm_1InterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pmaStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_pmaStandardAlarm_1InterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pmaStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_pmaStandardAlarm_1InterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pmaStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define AQ_GlobalInterruptChip_wideStandardMask_HHD_pmaStandardAlarm_2InterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pmaStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_pmaStandardAlarm_2InterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pmaStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_pmaStandardAlarm_2InterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define AQ_GlobalInterruptChip_wideStandardMask_HHD_pcsStandardAlarm_1InterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_pcsStandardAlarm_1InterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_pcsStandardAlarm_1InterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define AQ_GlobalInterruptChip_wideStandardMask_HHD_pcsStandardAlarm_2InterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_pcsStandardAlarm_2InterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_pcsStandardAlarm_2InterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pcsStandardAlarm_3InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define AQ_GlobalInterruptChip_wideStandardMask_HHD_pcsStandardAlarm_3InterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pcsStandardAlarm_3InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_pcsStandardAlarm_3InterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pcsStandardAlarm_3InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_pcsStandardAlarm_3InterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure phyXS_StandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define AQ_GlobalInterruptChip_wideStandardMask_HHD_phyXS_StandardAlarms_1InterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_StandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_phyXS_StandardAlarms_1InterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure phyXS_StandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_phyXS_StandardAlarms_1InterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure phyXS_StandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define AQ_GlobalInterruptChip_wideStandardMask_HHD_phyXS_StandardAlarms_2InterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_StandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_phyXS_StandardAlarms_2InterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure phyXS_StandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_phyXS_StandardAlarms_2InterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationStandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define AQ_GlobalInterruptChip_wideStandardMask_HHD_autonegotiationStandardAlarms_1InterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationStandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_autonegotiationStandardAlarms_1InterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationStandardAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_autonegotiationStandardAlarms_1InterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationStandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define AQ_GlobalInterruptChip_wideStandardMask_HHD_autonegotiationStandardAlarms_2InterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationStandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_autonegotiationStandardAlarms_2InterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationStandardAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_autonegotiationStandardAlarms_2InterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure gbeStandardAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define AQ_GlobalInterruptChip_wideStandardMask_HHD_gbeStandardAlarmsInterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure gbeStandardAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_gbeStandardAlarmsInterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure gbeStandardAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_gbeStandardAlarmsInterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure allVendorAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define AQ_GlobalInterruptChip_wideStandardMask_HHD_allVendorAlarmsInterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure allVendorAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define bits_AQ_GlobalInterruptChip_wideStandardMask_HHD_allVendorAlarmsInterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure allVendorAlarmsInterruptMask in AQ_GlobalInterruptChip_wideStandardMask_HHD */ -#define word_AQ_GlobalInterruptChip_wideStandardMask_HHD_allVendorAlarmsInterruptMask u0.word_0 - -/*! \brief Base register address of structure AQ_GlobalInterruptChip_wideVendorMask_HHD */ -#define AQ_GlobalInterruptChip_wideVendorMask_HHD_baseRegisterAddress 0xFF01 -/*! \brief MMD address of structure AQ_GlobalInterruptChip_wideVendorMask_HHD */ -#define AQ_GlobalInterruptChip_wideVendorMask_HHD_mmdAddress 0x1E -/*! \brief Preprocessor variable to relate field to word number in structure pmaVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ -#define AQ_GlobalInterruptChip_wideVendorMask_HHD_pmaVendorAlarmInterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pmaVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ -#define bits_AQ_GlobalInterruptChip_wideVendorMask_HHD_pmaVendorAlarmInterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pmaVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ -#define word_AQ_GlobalInterruptChip_wideVendorMask_HHD_pmaVendorAlarmInterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure pcsVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ -#define AQ_GlobalInterruptChip_wideVendorMask_HHD_pcsVendorAlarmInterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure pcsVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ -#define bits_AQ_GlobalInterruptChip_wideVendorMask_HHD_pcsVendorAlarmInterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure pcsVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ -#define word_AQ_GlobalInterruptChip_wideVendorMask_HHD_pcsVendorAlarmInterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure phyXS_VendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ -#define AQ_GlobalInterruptChip_wideVendorMask_HHD_phyXS_VendorAlarmInterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure phyXS_VendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ -#define bits_AQ_GlobalInterruptChip_wideVendorMask_HHD_phyXS_VendorAlarmInterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure phyXS_VendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ -#define word_AQ_GlobalInterruptChip_wideVendorMask_HHD_phyXS_VendorAlarmInterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure autonegotiationVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ -#define AQ_GlobalInterruptChip_wideVendorMask_HHD_autonegotiationVendorAlarmInterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure autonegotiationVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ -#define bits_AQ_GlobalInterruptChip_wideVendorMask_HHD_autonegotiationVendorAlarmInterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure autonegotiationVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ -#define word_AQ_GlobalInterruptChip_wideVendorMask_HHD_autonegotiationVendorAlarmInterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure gbeVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ -#define AQ_GlobalInterruptChip_wideVendorMask_HHD_gbeVendorAlarmInterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure gbeVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ -#define bits_AQ_GlobalInterruptChip_wideVendorMask_HHD_gbeVendorAlarmInterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure gbeVendorAlarmInterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ -#define word_AQ_GlobalInterruptChip_wideVendorMask_HHD_gbeVendorAlarmInterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ -#define AQ_GlobalInterruptChip_wideVendorMask_HHD_globalAlarms_1InterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ -#define bits_AQ_GlobalInterruptChip_wideVendorMask_HHD_globalAlarms_1InterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_1InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ -#define word_AQ_GlobalInterruptChip_wideVendorMask_HHD_globalAlarms_1InterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ -#define AQ_GlobalInterruptChip_wideVendorMask_HHD_globalAlarms_2InterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ -#define bits_AQ_GlobalInterruptChip_wideVendorMask_HHD_globalAlarms_2InterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_2InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ -#define word_AQ_GlobalInterruptChip_wideVendorMask_HHD_globalAlarms_2InterruptMask u0.word_0 -/*! \brief Preprocessor variable to relate field to word number in structure globalAlarms_3InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ -#define AQ_GlobalInterruptChip_wideVendorMask_HHD_globalAlarms_3InterruptMask 0 -/*! \brief Preprocessor variable to relate field to bit position in structure globalAlarms_3InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ -#define bits_AQ_GlobalInterruptChip_wideVendorMask_HHD_globalAlarms_3InterruptMask u0.bits_0 -/*! \brief Preprocessor variable to relate field to word position in structure globalAlarms_3InterruptMask in AQ_GlobalInterruptChip_wideVendorMask_HHD */ -#define word_AQ_GlobalInterruptChip_wideVendorMask_HHD_globalAlarms_3InterruptMask u0.word_0 -#endif -/*@}*/ -/*@}*/ diff --git a/qca/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers_reversed.h b/qca/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers_reversed.h deleted file mode 100644 index f6fe99831..000000000 --- a/qca/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers_reversed.h +++ /dev/null @@ -1,12123 +0,0 @@ -/*! \file -* This file contains the data structures and doxygen comments -* for the Global Registers block. - */ - -/*! \addtogroup registerMap - @{ -*/ - -/*! \defgroup Global_registers Global Registers -* This module contains the data structures and doxygen comments -* for the Global Registers block. - */ -/*********************************************************************** -* Copyright (c) 2015, Aquantia -* -* Permission to use, copy, modify, and/or distribute this software for any -* purpose with or without fee is hereby granted, provided that the above -* copyright notice and this permission notice appear in all copies. -* -* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -* -* $Date: 2014/04/08 $ -* -* $Label: $ -* -* Description: -* -* This file contains the c header structures for the registers contained in the Global Registers block. -* -* The bit fields in this structure are from MSbit to LSbit -* -***********************************************************************/ - - -/*@{*/ -#ifndef AQ_HHD_GLOBAL_REGS_HEADER -#define AQ_HHD_GLOBAL_REGS_HEADER - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Standard Control 1: 1E.0000 */ -/* Global Standard Control 1: 1E.0000 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Standard Control 1 */ - union - { - struct - { - /*! \brief 1E.0000.F R/WSC Soft Reset - AQ_GlobalStandardControl_1_HHD.u0.bits_0.softReset - - Default = 0x1 - - 1 = Global soft reset - 0 = Normal operation - - - Notes: - Resets the entire PHY. - Setting this bit initiates a global soft reset on all of the digital logic not including the microprocessor (i.e. microprocessor is not reset). Upon completion of the reset sequence, this bit is set back to 0by the microprocessor. Note this bit is OR'ed with the individual MMD resets. This bit should be set to 0 before setting the individual MMD resets. */ - unsigned int softReset : 1; /* 1E.0000.F R/WSC Default = 0x1 */ - /* 1 = Global soft reset - 0 = Normal operation - */ - unsigned int reserved0 : 3; - /*! \brief 1E.0000.B R/WPD Low Power - AQ_GlobalStandardControl_1_HHD.u0.bits_0.lowPower - - Provisionable Default = 0x0 - - 1 = Low-power mode - 0 = Normal operation - - - Notes: - A one written to this register causes the chip to enter low-power mode. This bit puts the entire chip in low-power mode, with only the MDIO and microprocessor functioning, and turns off the analog front-end: i.e. places it in high-impedance mode. Setting this bit also sets all of the Low Power bits in the other MMDs. */ - unsigned int lowPower : 1; /* 1E.0000.B R/WPD Provisionable Default = 0x0 */ - /* 1 = Low-power mode - 0 = Normal operation - */ - unsigned int reserved1 : 11; - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalStandardControl_1_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Standard Device Identifier: 1E.0002 */ -/* Global Standard Device Identifier: 1E.0002 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Standard Device Identifier */ - union - { - struct - { - /*! \brief 1E.0002.F:0 RO Device ID MSW [1F:10] - AQ_GlobalStandardDeviceIdentifier_HHD.u0.bits_0.deviceIdMSW - - - - Bits 31 - 16 of Device ID - */ - unsigned int deviceIdMSW : 16; /* 1E.0002.F:0 RO */ - /* Bits 31 - 16 of Device ID */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Standard Device Identifier */ - union - { - struct - { - /*! \brief 1E.0003.F:0 RO Device ID LSW [F:0] - AQ_GlobalStandardDeviceIdentifier_HHD.u1.bits_1.deviceIdLSW - - - - Bits 15 - 0 of Device ID - */ - unsigned int deviceIdLSW : 16; /* 1E.0003.F:0 RO */ - /* Bits 15 - 0 of Device ID */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_GlobalStandardDeviceIdentifier_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Standard Devices in Package: 1E.0005 */ -/* Global Standard Devices in Package: 1E.0005 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Standard Devices in Package */ - union - { - struct - { - unsigned int reserved0 : 8; - /*! \brief 1E.0005.7 ROS Autonegotiation Present - AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.autonegotiationPresent - - Default = 0x1 - - 1 = Autonegotiation is present in package - 0 = Autonegotiation is not present in package - - Notes: - This is always set to 1, as there is Autonegotiation in the PHY. */ - unsigned int autonegotiationPresent : 1; /* 1E.0005.7 ROS Default = 0x1 */ - /* 1 = Autonegotiation is present in package - 0 = Autonegotiation is not present in package */ - /*! \brief 1E.0005.6 ROS TC Present - AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.tcPresent - - Default = 0x0 - - 1 = TC is present in package - 0 = TC is not present in package - - Notes: - This is always set to 0, as there is no TC functionality in the PHY. */ - unsigned int tcPresent : 1; /* 1E.0005.6 ROS Default = 0x0 */ - /* 1 = TC is present in package - 0 = TC is not present in package */ - /*! \brief 1E.0005.5 ROS DTE XS Present - AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.dteXsPresent - - Default = 0x0 - - 1 = DTE XS is present in package - 0 = DTE XS is not present in package - - - Notes: - This is always set to 0, as there is no DTE XAUI interface in the PHY. */ - unsigned int dteXsPresent : 1; /* 1E.0005.5 ROS Default = 0x0 */ - /* 1 = DTE XS is present in package - 0 = DTE XS is not present in package - */ - /*! \brief 1E.0005.4 ROS PHY XS Present - AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.phyXS_Present - - Default = 0x1 - - 1 = PHY XS is present in package - 0 = PHY XS is not present in package - - Notes: - This is always set to 1 as there is a PHY XS interface in the PHY. */ - unsigned int phyXS_Present : 1; /* 1E.0005.4 ROS Default = 0x1 */ - /* 1 = PHY XS is present in package - 0 = PHY XS is not present in package */ - /*! \brief 1E.0005.3 ROS PCS Present - AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.pcsPresent - - Default = 0x1 - - 1 = PCS is present in package - 0 = PCS is not present in package - - Notes: - This is always set to 1 as there is PCS functionality in the PHY. */ - unsigned int pcsPresent : 1; /* 1E.0005.3 ROS Default = 0x1 */ - /* 1 = PCS is present in package - 0 = PCS is not present in package */ - /*! \brief 1E.0005.2 ROS WIS Present - AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.wisPresent - - Default = 0x0 - - 1 = WIS is present in package - 0 = WIS is not present in package - - Notes: - This is always set to 0, as there is no WIS functionality in the PHY. */ - unsigned int wisPresent : 1; /* 1E.0005.2 ROS Default = 0x0 */ - /* 1 = WIS is present in package - 0 = WIS is not present in package */ - /*! \brief 1E.0005.1 ROS PMA Present - AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.pmaPresent - - Default = 0x1 - - 1 = PMA is present in package - 0 = PMA is not present - - Notes: - This is always set to 1 as there is PMA functionality in the PHY. */ - unsigned int pmaPresent : 1; /* 1E.0005.1 ROS Default = 0x1 */ - /* 1 = PMA is present in package - 0 = PMA is not present */ - /*! \brief 1E.0005.0 ROS Clause 22 Registers Present - AQ_GlobalStandardDevicesInPackage_HHD.u0.bits_0.clause_22RegistersPresent - - Default = 0x0 - - 1 = Clause 22 registers are present in package - 0 = Clause 22 registers are not present in package - - Notes: - This is always set to 0 in the PHY, as there are no Clause 22 registers in the device. */ - unsigned int clause_22RegistersPresent : 1; /* 1E.0005.0 ROS Default = 0x0 */ - /* 1 = Clause 22 registers are present in package - 0 = Clause 22 registers are not present in package */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalStandardDevicesInPackage_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Standard Vendor Devices in Package: 1E.0006 */ -/* Global Standard Vendor Devices in Package: 1E.0006 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Standard Vendor Devices in Package */ - union - { - struct - { - /*! \brief 1E.0006.F ROS Vendor Specific Device #2 Present - AQ_GlobalStandardVendorDevicesInPackage_HHD.u0.bits_0.vendorSpecificDevice_2Present - - Default = 0x1 - - 1 = Device #2 is present in package - 0 = Device #2 is not present in package - - Notes: - This is always set to 1 as the PHY utilizes this device for the DSP PMA registers. */ - unsigned int vendorSpecificDevice_2Present : 1; /* 1E.0006.F ROS Default = 0x1 */ - /* 1 = Device #2 is present in package - 0 = Device #2 is not present in package */ - /*! \brief 1E.0006.E ROS Vendor Specific Device #1 Present - AQ_GlobalStandardVendorDevicesInPackage_HHD.u0.bits_0.vendorSpecificDevice_1Present - - Default = 0x1 - - 1 = Device #1 is present in package - 0 = Device #1 is not present in package - - Notes: - This is always set to 1 as the PHY utilizes this device for the global control registers. */ - unsigned int vendorSpecificDevice_1Present : 1; /* 1E.0006.E ROS Default = 0x1 */ - /* 1 = Device #1 is present in package - 0 = Device #1 is not present in package */ - /*! \brief 1E.0006.D ROS Clause 22 Extension Present - AQ_GlobalStandardVendorDevicesInPackage_HHD.u0.bits_0.clause_22ExtensionPresent - - Default = 0x1 - - 1 = Clause 22 Extension is present in package - 0 = Clause 22 Extension is not present in package - - Notes: - This is always set to 1 as the PHY utilizes this device for the GbE registers. */ - unsigned int clause_22ExtensionPresent : 1; /* 1E.0006.D ROS Default = 0x1 */ - /* 1 = Clause 22 Extension is present in package - 0 = Clause 22 Extension is not present in package */ - unsigned int reserved0 : 13; - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalStandardVendorDevicesInPackage_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Standard Status 2: 1E.0008 */ -/* Global Standard Status 2: 1E.0008 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Standard Status 2 */ - union - { - struct - { - /*! \brief 1E.0008.F:E ROS Device Present [1:0] - AQ_GlobalStandardStatus_2_HHD.u0.bits_0.devicePresent - - Default = 0x2 - - [F:E] - 0x3 = No device at this address - 0x2 = Device present at this address - 0x1 = No device at this address - 0x0 = No device at this address - - Notes: - This field is always set to 0x2, as the Global MMD resides here in the PHY. */ - unsigned int devicePresent : 2; /* 1E.0008.F:E ROS Default = 0x2 */ - /* [F:E] - 0x3 = No device at this address - 0x2 = Device present at this address - 0x1 = No device at this address - 0x0 = No device at this address */ - unsigned int reserved0 : 14; - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalStandardStatus_2_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Standard Package Identifier: 1E.000E */ -/* Global Standard Package Identifier: 1E.000E */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Standard Package Identifier */ - union - { - struct - { - /*! \brief 1E.000E.F:0 RO Package ID MSW [1F:10] - AQ_GlobalStandardPackageIdentifier_HHD.u0.bits_0.packageIdMSW - - - - Bits 31- 16 of Package ID - */ - unsigned int packageIdMSW : 16; /* 1E.000E.F:0 RO */ - /* Bits 31- 16 of Package ID */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Standard Package Identifier */ - union - { - struct - { - /*! \brief 1E.000F.F:0 RO Package ID LSW [F:0] - AQ_GlobalStandardPackageIdentifier_HHD.u1.bits_1.packageIdLSW - - - - Bits 15 - 0 of Package ID - */ - unsigned int packageIdLSW : 16; /* 1E.000F.F:0 RO */ - /* Bits 15 - 0 of Package ID */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_GlobalStandardPackageIdentifier_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Firmware ID: 1E.0020 */ -/* Global Firmware ID: 1E.0020 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Firmware ID */ - union - { - struct - { - /*! \brief 1E.0020.F:8 RO Firmware Major Revision Number [7:0] - AQ_GlobalFirmwareID_HHD.u0.bits_0.firmwareMajorRevisionNumber - - - - [F:8] = Major revision number - - Notes: - - - The lower six bits of major and minor firmware revision are exchanged in autonegotiation when the PHYID message is sent. */ - unsigned int firmwareMajorRevisionNumber : 8; /* 1E.0020.F:8 RO */ - /* [F:8] = Major revision number */ - /*! \brief 1E.0020.7:0 RO Firmware Minor Revision Number [7:0] - AQ_GlobalFirmwareID_HHD.u0.bits_0.firmwareMinorRevisionNumber - - - - [7:0] = Minor revision number - - Notes: - - - The lower six bits of major and minor firmware revision are exchanged in autonegotiation when the PHYID message is sent. */ - unsigned int firmwareMinorRevisionNumber : 8; /* 1E.0020.7:0 RO */ - /* [7:0] = Minor revision number */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalFirmwareID_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global NVR Interface: 1E.0100 */ -/* Global NVR Interface: 1E.0100 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global NVR Interface */ - union - { - struct - { - /*! \brief 1E.0100.F R/WSC NVR Execute Operation - AQ_GlobalNvrInterface_HHD.u0.bits_0.nvrExecuteOperation - - Default = 0x0 - - 1 = Start NVR Operation - - - - Notes: - When set to 1, the NVR operation will begin. Ensure that the uP is stalled using the See MCP Run Stall bit to ensure no NVR contention. */ - unsigned int nvrExecuteOperation : 1; /* 1E.0100.F R/WSC Default = 0x0 */ - /* 1 = Start NVR Operation - - */ - /*! \brief 1E.0100.E R/W NVR Write Mode - AQ_GlobalNvrInterface_HHD.u0.bits_0.nvrWriteMode - - Default = 0x0 - - 1 = Write to NVR - 0 = Read from NVR - - */ - unsigned int nvrWriteMode : 1; /* 1E.0100.E R/W Default = 0x0 */ - /* 1 = Write to NVR - 0 = Read from NVR - */ - /*! \brief 1E.0100.D R/W Freeze NVR CRC - AQ_GlobalNvrInterface_HHD.u0.bits_0.freezeNvrCrc - - Default = 0x0 - - 1 = Freeze NVR Mailbox CRC calculation register - - - Notes: - To prevent an erroneous answer, this bit should not be set at the same time the See NVR Operation Valid bit is set. */ - unsigned int freezeNvrCrc : 1; /* 1E.0100.D R/W Default = 0x0 */ - /* 1 = Freeze NVR Mailbox CRC calculation register - */ - /*! \brief 1E.0100.C R/WSC Reset NVR CRC - AQ_GlobalNvrInterface_HHD.u0.bits_0.resetNvrCrc - - Default = 0x0 - - 1 = Reset NVR Mailbox CRC calculation register - - - - Notes: - To prevent an erroneous answer, this bit should not be set at the same time the See NVR Operation Valid bit is set. */ - unsigned int resetNvrCrc : 1; /* 1E.0100.C R/WSC Default = 0x0 */ - /* 1 = Reset NVR Mailbox CRC calculation register - - */ - unsigned int reserved0 : 1; - /*! \brief 1E.0100.A R/W NVR Burst - AQ_GlobalNvrInterface_HHD.u0.bits_0.nvrBurst - - Default = 0x0 - - 0 = Single read or write operation of up to 4 bytes - 1 = Burst operation - - - Notes: - When this bit is set, the operation is a burst operation where more than 32-bits is read from the NVR or written to the NVR. This bit should be set to one until the last burst in the read or write operation, when it should be set to zero. It operates by gating the SPI clock, and not restarting it until new data is ready to be written, or the previous contents have been read. Each burst of data requires the NVR Execute Operation bit to be set to initiate the next phase. */ - unsigned int nvrBurst : 1; /* 1E.0100.A R/W Default = 0x0 */ - /* 0 = Single read or write operation of up to 4 bytes - 1 = Burst operation - */ - unsigned int reserved1 : 1; - /*! \brief 1E.0100.8 RO NVR Busy - AQ_GlobalNvrInterface_HHD.u0.bits_0.nvrBusy - - - - 1 = NVR is busy - 0 = NVR is ready - - - Notes: - When set to 1, the NVR is busy. A new NVR operation should not occur until this bit is 0. If the NVR clock is greater than 64/63 of the MDIO clock, this bit never needs to be polled when operating over the MDIO. */ - unsigned int nvrBusy : 1; /* 1E.0100.8 RO */ - /* 1 = NVR is busy - 0 = NVR is ready - */ - /*! \brief 1E.0100.7:0 R/W NVR Opcode [7:0] - AQ_GlobalNvrInterface_HHD.u0.bits_0.nvrOpcode - - Default = 0x03 - - NVR instruction opcode - - */ - unsigned int nvrOpcode : 8; /* 1E.0100.7:0 R/W Default = 0x03 */ - /* NVR instruction opcode - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global NVR Interface */ - union - { - struct - { - /*! \brief 1E.0101.F:0 RO NVR Mailbox CRC [F:0] - AQ_GlobalNvrInterface_HHD.u1.bits_1.nvrMailboxCrc - - - - The running CRC-16 of everything passing through the NVR interface - - - Notes: - The CRC-16 over all data written or read through the NVR interface. The CRC-16 is calculated by dividing the data by: - x^16 + x^12 + x^5 + 1 */ - unsigned int nvrMailboxCrc : 16; /* 1E.0101.F:0 RO */ - /* The running CRC-16 of everything passing through the NVR interface - */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global NVR Interface */ - union - { - struct - { - unsigned int reserved0 : 8; - /*! \brief 1E.0102.7:0 R/W NVR Address MSW [17:10] - AQ_GlobalNvrInterface_HHD.u2.bits_2.nvrAddressMSW - - Default = 0x00 - - NVR address MSW bits [17:10] - - - Notes: - The address of where to read and write from in the NVR. This is self-incrementing and will automatically increment after each read or write operation. The increment amount is based on the data length (i.e. increments by 4 if the data length is 4 bytes) */ - unsigned int nvrAddressMSW : 8; /* 1E.0102.7:0 R/W Default = 0x00 */ - /* NVR address MSW bits [17:10] - */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global NVR Interface */ - union - { - struct - { - /*! \brief 1E.0103.F:0 R/W NVR Address LSW [F:0] - AQ_GlobalNvrInterface_HHD.u3.bits_3.nvrAddressLSW - - Default = 0x0000 - - NVR address LSW bits [F:0] - - - Notes: - The address of where to read and write from in the NVR. This is self-incrementing and will automatically increment after each read or write operation. */ - unsigned int nvrAddressLSW : 16; /* 1E.0103.F:0 R/W Default = 0x0000 */ - /* NVR address LSW bits [F:0] - */ - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of Global NVR Interface */ - union - { - struct - { - /*! \brief 1E.0104.F:0 R/W NVR Data MSW [1F:10] - AQ_GlobalNvrInterface_HHD.u4.bits_4.nvrDataMSW - - Default = 0x0000 - - NVR data MSW bits [1F:10] - - - Notes: - Data is stored and read-out from these registers in little-endian format for operations such as FLASH device ID, and for programming the processor. - - For instance the 64K Atmel device code reads out as two bytes 0x651F into the LSW register, whereas the datasheet indicates that 1F is the first byte read, followed by 65 as the second byte. - - To burst read and write these 4 bytes in the correct order (where DD is written to address x), they should be stored as: - - AA BB in the MSW - CC DD in the LSW. */ - unsigned int nvrDataMSW : 16; /* 1E.0104.F:0 R/W Default = 0x0000 */ - /* NVR data MSW bits [1F:10] - */ - } bits_4; - uint16_t word_4; - } u4; - /*! \brief Union for bit and word level access of word 5 of Global NVR Interface */ - union - { - struct - { - /*! \brief 1E.0105.F:0 R/W NVR Data LSW [F:0] - AQ_GlobalNvrInterface_HHD.u5.bits_5.nvrDataLSW - - Default = 0x0000 - - NVR data LSW bits [F:0] - - - Notes: - Data is stored and read-out from these registers in little-endian format for operations such as FLASH device ID, and for programming the processor. - - For instance the 64K Atmel device code reads out as two bytes 0x651F into the LSW register, whereas the datasheet indicates that 1F is the first byte read, followed by 65 as the second byte. - To burst read and write these 4 bytes in the correct order (where DD is written to address x), they should be stored as: - - AA BB in the MSW - CC DD in the LSW. */ - unsigned int nvrDataLSW : 16; /* 1E.0105.F:0 R/W Default = 0x0000 */ - /* NVR data LSW bits [F:0] - */ - } bits_5; - uint16_t word_5; - } u5; -} AQ_GlobalNvrInterface_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Mailbox Interface: 1E.0200 */ -/* Global Mailbox Interface: 1E.0200 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Mailbox Interface */ - union - { - struct - { - /*! \brief 1E.0200.F R/WSC uP Mailbox Execute Operation - AQ_GlobalMailboxInterface_HHD.u0.bits_0.upMailboxExecuteOperation - - Default = 0x0 - - 1 = Start of mailbox Operation - - - - Notes: - Indicates mailbox is loaded and ready */ - unsigned int upMailboxExecuteOperation : 1; /* 1E.0200.F R/WSC Default = 0x0 */ - /* 1 = Start of mailbox Operation - - */ - /*! \brief 1E.0200.E R/W uP Mailbox Write Mode - AQ_GlobalMailboxInterface_HHD.u0.bits_0.upMailboxWriteMode - - Default = 0x0 - - 1 = Write - 0 = Read - - - Notes: - Mailbox direction */ - unsigned int upMailboxWriteMode : 1; /* 1E.0200.E R/W Default = 0x0 */ - /* 1 = Write - 0 = Read - */ - unsigned int reserved0 : 1; - /*! \brief 1E.0200.C R/WSC Reset uP Mailbox CRC - AQ_GlobalMailboxInterface_HHD.u0.bits_0.resetUpMailboxCrc - - Default = 0x0 - - 1 = Reset uP mailbox CRC calculation register - - - */ - unsigned int resetUpMailboxCrc : 1; /* 1E.0200.C R/WSC Default = 0x0 */ - /* 1 = Reset uP mailbox CRC calculation register - - */ - unsigned int reserved1 : 3; - /*! \brief 1E.0200.8 RO uP Mailbox Busy - AQ_GlobalMailboxInterface_HHD.u0.bits_0.upMailboxBusy - - - - 1 = uP mailbox busy - 0 = uP mailbox ready - - - Notes: - In general the uP will respond within a few processor cycles to any PIF slave request, much faster than the MDIO. If the busy is asserted over multiple MDIO polling cycles, then a H/W error may have occurred and a Global S/W reset or uP reset is required. */ - unsigned int upMailboxBusy : 1; /* 1E.0200.8 RO */ - /* 1 = uP mailbox busy - 0 = uP mailbox ready - */ - unsigned int reserved2 : 8; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Mailbox Interface */ - union - { - struct - { - /*! \brief 1E.0201.F:0 RO uP Mailbox CRC [F:0] - AQ_GlobalMailboxInterface_HHD.u1.bits_1.upMailboxCrc - - - - The running CRC-16 of everything passing through the mailbox interface - - */ - unsigned int upMailboxCrc : 16; /* 1E.0201.F:0 RO */ - /* The running CRC-16 of everything passing through the mailbox interface - */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global Mailbox Interface */ - union - { - struct - { - /*! \brief 1E.0202.F:0 R/W uP Mailbox Address MSW [1F:10] - AQ_GlobalMailboxInterface_HHD.u2.bits_2.upMailboxAddressMSW - - Default = 0x0000 - - uP Mailbox MSW address - - - Notes: - The address of where to read and write from in the Microcontroller Mailbox. This is self-incrementing and automatically increments after each read and write operation.PHY */ - unsigned int upMailboxAddressMSW : 16; /* 1E.0202.F:0 R/W Default = 0x0000 */ - /* uP Mailbox MSW address - */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global Mailbox Interface */ - union - { - struct - { - /*! \brief 1E.0203.F:2 R/W uP Mailbox Address LSW [F:2] - AQ_GlobalMailboxInterface_HHD.u3.bits_3.upMailboxAddressLSW - - Default = 0x0000 - - uP LSW Mailbox address [F:2] - - - Notes: - The address of where to read and write from in the Microcontroller Mailbox. This is self-incrementing and automatically increments after each read and write operation.PHY */ - unsigned int upMailboxAddressLSW : 14; /* 1E.0203.F:2 R/W Default = 0x0000 */ - /* uP LSW Mailbox address [F:2] - */ - /*! \brief 1E.0203.1:0 RO uP Mailbox Address LSW Don't Care [1:0] - AQ_GlobalMailboxInterface_HHD.u3.bits_3.upMailboxAddressLSW_Don_tCare - - - - Least significant uP LSW Mailbox address bits [1:0] - - - Notes: - These bits are always set to 0 since each memory access is on a 4-byte boundary. */ - unsigned int upMailboxAddressLSW_Don_tCare : 2; /* 1E.0203.1:0 RO */ - /* Least significant uP LSW Mailbox address bits [1:0] - */ - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of Global Mailbox Interface */ - union - { - struct - { - /*! \brief 1E.0204.F:0 R/W uP Mailbox Data MSW [1F:10] - AQ_GlobalMailboxInterface_HHD.u4.bits_4.upMailboxDataMSW - - Default = 0x0000 - - uP Mailbox data MSW - - */ - unsigned int upMailboxDataMSW : 16; /* 1E.0204.F:0 R/W Default = 0x0000 */ - /* uP Mailbox data MSW - */ - } bits_4; - uint16_t word_4; - } u4; - /*! \brief Union for bit and word level access of word 5 of Global Mailbox Interface */ - union - { - struct - { - /*! \brief 1E.0205.F:0 R/W uP Mailbox Data LSW [F:0] - AQ_GlobalMailboxInterface_HHD.u5.bits_5.upMailboxDataLSW - - Default = 0x0000 - - uP Mailbox data LSW - - */ - unsigned int upMailboxDataLSW : 16; /* 1E.0205.F:0 R/W Default = 0x0000 */ - /* uP Mailbox data LSW - */ - } bits_5; - uint16_t word_5; - } u5; - /*! \brief Union for bit and word level access of word 6 of Global Mailbox Interface */ - union - { - struct - { - unsigned int reserved0 : 14; - /*! \brief 1E.0206.1 R/W uP Mailbox CRC Read Enable - AQ_GlobalMailboxInterface_HHD.u6.bits_6.upMailboxCrcReadEnable - - Default = 0x0 - - 1 = Update uP mailbox CRC on read - - */ - unsigned int upMailboxCrcReadEnable : 1; /* 1E.0206.1 R/W Default = 0x0 */ - /* 1 = Update uP mailbox CRC on read - */ - unsigned int reserved1 : 1; - } bits_6; - uint16_t word_6; - } u6; -} AQ_GlobalMailboxInterface_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Microprocessor Scratch Pad: 1E.0300 */ -/* Global Microprocessor Scratch Pad: 1E.0300 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Microprocessor Scratch Pad */ - union - { - struct - { - /*! \brief 1E.0300.F:0 R/W Scratch Pad 1[F:0] - AQ_GlobalMicroprocessorScratchPad_HHD.u0.bits_0.scratchPad_1 - - Default = 0x0000 - - General Purpose Scratch Pad - */ - unsigned int scratchPad_1 : 16; /* 1E.0300.F:0 R/W Default = 0x0000 */ - /* General Purpose Scratch Pad */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Microprocessor Scratch Pad */ - union - { - struct - { - /*! \brief 1E.0301.F:0 R/W Scratch Pad 2 [F:0] - AQ_GlobalMicroprocessorScratchPad_HHD.u1.bits_1.scratchPad_2 - - Default = 0x0000 - - General Purpose Scratch Pad - */ - unsigned int scratchPad_2 : 16; /* 1E.0301.F:0 R/W Default = 0x0000 */ - /* General Purpose Scratch Pad */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_GlobalMicroprocessorScratchPad_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Egress Control Register: 1E.5002 */ -/* MSS Egress Control Register: 1E.5002 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Egress Control Register */ - union - { - struct - { - /*! \brief 1E.5002.F:D R/W MSS Egress Ethertype Explicit SECTag LSB [2:0] - AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressEthertypeExplicitSectagLsb - - Default = 0x0 - - Ethertype for explicit SECTag bits 2:0. - - - Notes: - Ethertype for explicity SECTag. */ - unsigned int mssEgressEthertypeExplicitSectagLsb : 3; /* 1E.5002.F:D R/W Default = 0x0 */ - /* Ethertype for explicit SECTag bits 2:0. - */ - /*! \brief 1E.5002.C R/W MSS Egress Clear Global Time - AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressClearGlobalTime - - Default = 0x0 - - 1 = Clear global time - - - - Notes: - Clear global time. */ - unsigned int mssEgressClearGlobalTime : 1; /* 1E.5002.C R/W Default = 0x0 */ - /* 1 = Clear global time - - */ - /*! \brief 1E.5002.B R/W MSS Egress Clear Counter - AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressClearCounter - - Default = 0x0 - - 1 = Clear all MIB counters - - - - Notes: - If this bit is set to 1, all MIB counters will be cleared. */ - unsigned int mssEgressClearCounter : 1; /* 1E.5002.B R/W Default = 0x0 */ - /* 1 = Clear all MIB counters - - */ - /*! \brief 1E.5002.A R/W MSS Egress High Priority - AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressHighPriority - - Default = 0x0 - - 1 = MIB counter clear on read enable - - - - Notes: - If this bit is set to 1, read is given high priority and the MIB count value becomes 0 after read. */ - unsigned int mssEgressHighPriority : 1; /* 1E.5002.A R/W Default = 0x0 */ - /* 1 = MIB counter clear on read enable - - */ - /*! \brief 1E.5002.9 R/W MSS Egress ICV LSB 8 Bytes Enable - AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressIcvLsb_8BytesEnable - - Default = 0x0 - - 1 = Use LSB - 0 = Use MSB - - - - Notes: - This bit selects MSB or LSB 8 bytes selection in the case where the ICV is 8 bytes. - 0 = MSB is used. */ - unsigned int mssEgressIcvLsb_8BytesEnable : 1; /* 1E.5002.9 R/W Default = 0x0 */ - /* 1 = Use LSB - 0 = Use MSB - - */ - /*! \brief 1E.5002.8 R/W MSS Egress External Classification Enable - AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressExternalClassificationEnable - - Default = 0x0 - - 1 = Drop EGPRC miss packets - - - - Notes: - If set, internal classification is bypassed. Should always be set to 0. */ - unsigned int mssEgressExternalClassificationEnable : 1; /* 1E.5002.8 R/W Default = 0x0 */ - /* 1 = Drop EGPRC miss packets - - */ - /*! \brief 1E.5002.7 R/W MSS Egress Explicit SECTag Report Short Length - AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressExplicitSectagReportShortLength - - Default = 0x0 - - Reserved - - - - Notes: - Unused. */ - unsigned int mssEgressExplicitSectagReportShortLength : 1; /* 1E.5002.7 R/W Default = 0x0 */ - /* Reserved - - */ - /*! \brief 1E.5002.6 R/W MSS Egress Drop Invalid SA/SC Packets - AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressDropInvalidSa_scPackets - - Default = 0x0 - - 1 = Drop invalid SA/SC packets - - - - Notes: - Enables dropping of invalid SA/SC packets. */ - unsigned int mssEgressDropInvalidSa_scPackets : 1; /* 1E.5002.6 R/W Default = 0x0 */ - /* 1 = Drop invalid SA/SC packets - - */ - /*! \brief 1E.5002.5 R/W MSS Egress Unmatched Use SC 0 - AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressUnmatchedUseSc_0 - - Default = 0x0 - - 1 = Use SC 0 for unmatched packets - 0 = Unmatched packets are uncontrolled packets - - - - Notes: - Use SC-Index 0 as default SC for unmatched packets. Otherwise the packets are treated as uncontrolled packets. */ - unsigned int mssEgressUnmatchedUseSc_0 : 1; /* 1E.5002.5 R/W Default = 0x0 */ - /* 1 = Use SC 0 for unmatched packets - 0 = Unmatched packets are uncontrolled packets - - */ - /*! \brief 1E.5002.4 R/W MSS Egresss GCM Test Mode - AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgresssGcmTestMode - - Default = 0x0 - - 1 = Enable GCM test mode - - - - Notes: - Enables GCM test mode */ - unsigned int mssEgresssGcmTestMode : 1; /* 1E.5002.4 R/W Default = 0x0 */ - /* 1 = Enable GCM test mode - - */ - /*! \brief 1E.5002.3 R/W MSS Egress GCM Start - AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressGcmStart - - Default = 0x0 - - 1 = Start GCM - - - - Notes: - Indicates GCM to start */ - unsigned int mssEgressGcmStart : 1; /* 1E.5002.3 R/W Default = 0x0 */ - /* 1 = Start GCM - - */ - /*! \brief 1E.5002.2 R/W MSS Egress Drop EGPRC LUT Miss - AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressDropEgprcLutMiss - - Default = 0x0 - - 1 = Drop Egress Classification LUT miss packets - - - - Notes: - Decides whether Egress Pre-Security Classification (EGPRC) LUT miss packets are to be dropped */ - unsigned int mssEgressDropEgprcLutMiss : 1; /* 1E.5002.2 R/W Default = 0x0 */ - /* 1 = Drop Egress Classification LUT miss packets - - */ - /*! \brief 1E.5002.1 R/W MSS Egress Drop KAY Packet - AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressDropKayPacket - - Default = 0x0 - - 1 = Drop KAY packet - - - Notes: - Decides whether KAY packets have to be dropped */ - unsigned int mssEgressDropKayPacket : 1; /* 1E.5002.1 R/W Default = 0x0 */ - /* 1 = Drop KAY packet - */ - /*! \brief 1E.5002.0 R/W MSS Egress Soft Reset - AQ_MssEgressControlRegister_HHD.u0.bits_0.mssEgressSoftReset - - Default = 0x0 - - 1 = Soft reset - - - Notes: - S/W reset */ - unsigned int mssEgressSoftReset : 1; /* 1E.5002.0 R/W Default = 0x0 */ - /* 1 = Soft reset - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Egress Control Register */ - union - { - struct - { - unsigned int reserved0 : 3; - /*! \brief 1E.5003.C:0 R/W MSS Egress Ethertype Explicit SECTag MSB [F:3] - AQ_MssEgressControlRegister_HHD.u1.bits_1.mssEgressEthertypeExplicitSectagMsb - - Default = 0x0000 - - Ethertype for explicit SECTag bits 15:3. - - - Notes: - Ethertype for explicity SECTag. */ - unsigned int mssEgressEthertypeExplicitSectagMsb : 13; /* 1E.5003.C:0 R/W Default = 0x0000 */ - /* Ethertype for explicit SECTag bits 15:3. - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssEgressControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Egress VLAN TPID 0 Register: 1E.5008 */ -/* MSS Egress VLAN TPID 0 Register: 1E.5008 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Egress VLAN TPID 0 Register */ - union - { - struct - { - /*! \brief 1E.5008.F:0 R/W MSS Egress VLAN STag TPID [F:0] - AQ_MssEgressVlanTpid_0Register_HHD.u0.bits_0.mssEgressVlanStagTpid - - Default = 0x0000 - - STag TPID - - - Notes: - Service Tag Protocol Identifier (TPID) values to identify a VLAN tag. The " See SEC Egress VLAN CP Tag Parse STag " bit must be set to 1 for the incoming packet's TPID to be parsed. */ - unsigned int mssEgressVlanStagTpid : 16; /* 1E.5008.F:0 R/W Default = 0x0000 */ - /* STag TPID - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Egress VLAN TPID 0 Register */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssEgressVlanTpid_0Register_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Egress VLAN TPID 1 Register: 1E.500A */ -/* MSS Egress VLAN TPID 1 Register: 1E.500A */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Egress VLAN TPID 1 Register */ - union - { - struct - { - /*! \brief 1E.500A.F:0 R/W MSS Egress VLAN QTag TPID [F:0] - AQ_MssEgressVlanTpid_1Register_HHD.u0.bits_0.mssEgressVlanQtagTpid - - Default = 0x0000 - - QTag TPID - - - Notes: - Customer Tag Protocol Identifier (TPID) values to identify a VLAN tag. The " See SEC Egress VLAN CP Tag Parse QTag " bit must be set to 1 for the incoming packet's TPID to be parsed. */ - unsigned int mssEgressVlanQtagTpid : 16; /* 1E.500A.F:0 R/W Default = 0x0000 */ - /* QTag TPID - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Egress VLAN TPID 1 Register */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssEgressVlanTpid_1Register_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Egress VLAN Control Register: 1E.500C */ -/* MSS Egress VLAN Control Register: 1E.500C */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Egress VLAN Control Register */ - union - { - struct - { - /*! \brief 1E.500C.F:0 R/W MSS Egress VLAN UP Map Table [F:0] - AQ_MssEgressVlanControlRegister_HHD.u0.bits_0.mssEgressVlanUpMapTable - - Default = 0x0000 - - UP Map table bits 15:0 - - - Notes: - If there is a customer TPID Tag match and no service TPID Tag match or the service TPID Tag match is disabled, the outer TAG's PCP is used to index into this map table to generate the packets user priority. - 2:0 : UP value for customer Tag PCP 0x0 - 5:3: UP value for customer Tag PCP 0x0 - 8:6 : UP value for customer Tag PCP 0x0 - 11:9 : UP value for customer Tag PCP 0x0 - 14:12 : UP value for customer Tag PCP 0x0 - 17:15 : UP value for customer Tag PCP 0x0 - 20:18 : UP value for customer Tag PCP 0x0 - 23:21 : UP value for customer Tag PCP 0x0 */ - unsigned int mssEgressVlanUpMapTable : 16; /* 1E.500C.F:0 R/W Default = 0x0000 */ - /* UP Map table bits 15:0 - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Egress VLAN Control Register */ - union - { - struct - { - /*! \brief 1E.500D.F R/W MSS Egress VLAN QTag Parse Enable - AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanQtagParseEnable - - Default = 0x0 - - 1 = Enable VLAN QTag parsing - - - Notes: - Enable controlled port VLAN customer Tag parsing. When this bit is set to 1, the incoming packet's outer TPID will be compared with the configured " See SEC Egress TPID 1 [F:0] " for matching. If the " See SEC Egress VLAN CP Tag Parse QinQ " bit is set to1, this will also be used to compare the incoming packet's inner TPID. */ - unsigned int mssEgressVlanQtagParseEnable : 1; /* 1E.500D.F R/W Default = 0x0 */ - /* 1 = Enable VLAN QTag parsing - */ - /*! \brief 1E.500D.E R/W MSS Egress VLAN STag Parse Enable - AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanStagParseEnable - - Default = 0x0 - - 1 = Enable VLAN STag parsing - - - Notes: - Enable controlled port VLAN service Tag parsing. When this bit is set to 1, the incoming packets outer TPID will be compared with the configured " See SEC Egress TPID 0 [F:0] " for matching. If the " See SEC Egress VLAN CP Tag Parse QinQ " bit is set to1, this will also be used to compare the incoming packet's inner TPID. */ - unsigned int mssEgressVlanStagParseEnable : 1; /* 1E.500D.E R/W Default = 0x0 */ - /* 1 = Enable VLAN STag parsing - */ - /*! \brief 1E.500D.D R/W MSS Egress VLAN QinQ Parse Enable - AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanQinqParseEnable - - Default = 0x0 - - VLAN CP Tag Parse QinQ - - - Notes: - Enable controlled port VLAN QinQ Tag parsing. When this bit is set to 1 both the outer and inner VLAN Tags will be parsed. */ - unsigned int mssEgressVlanQinqParseEnable : 1; /* 1E.500D.D R/W Default = 0x0 */ - /* VLAN CP Tag Parse QinQ - */ - /*! \brief 1E.500D.C R/W MSS Egress VLAN QTag UP Parse Enable - AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanQtagUpParseEnable - - Default = 0x0 - - VLAN CP Tag QTag UP enable - - - Notes: - Enable controlled port customer VLAN customer Tag user priority field parsing. */ - unsigned int mssEgressVlanQtagUpParseEnable : 1; /* 1E.500D.C R/W Default = 0x0 */ - /* VLAN CP Tag QTag UP enable - */ - /*! \brief 1E.500D.B R/W MSS Egress VLAN STag UP Parse Enable - AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanStagUpParseEnable - - Default = 0x0 - - VLAN CP Tag STag UP enable - - - Notes: - Enable controlled port service VLAN service Tag user priority field parsing. */ - unsigned int mssEgressVlanStagUpParseEnable : 1; /* 1E.500D.B R/W Default = 0x0 */ - /* VLAN CP Tag STag UP enable - */ - /*! \brief 1E.500D.A:8 R/W MSS Egress VLAN UP Default [2:0] - AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanUpDefault - - Default = 0x0 - - UP default - - - Notes: - User priority default */ - unsigned int mssEgressVlanUpDefault : 3; /* 1E.500D.A:8 R/W Default = 0x0 */ - /* UP default - */ - /*! \brief 1E.500D.7:0 R/W MSS Egress VLAN UP Map Table MSW [17:10] - AQ_MssEgressVlanControlRegister_HHD.u1.bits_1.mssEgressVlanUpMapTableMSW - - Default = 0x00 - - UP Map table bits 23:16 - - - Notes: - If there is a customer TPID Tag match and no service TPID Tag match or the service TPID Tag match is disabled, the outer TAG's PCP is used to index into this map table to generate the packets user priority. - 2:0 : UP value for customer Tag PCP 0x0 - 5:3: UP value for customer Tag PCP 0x0 - 8:6 : UP value for customer Tag PCP 0x0 - 11:9 : UP value for customer Tag PCP 0x0 - 14:12 : UP value for customer Tag PCP 0x0 - 17:15 : UP value for customer Tag PCP 0x0 - 20:18 : UP value for customer Tag PCP 0x0 - 23:21 : UP value for customer Tag PCP 0x0 */ - unsigned int mssEgressVlanUpMapTableMSW : 8; /* 1E.500D.7:0 R/W Default = 0x00 */ - /* UP Map table bits 23:16 - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssEgressVlanControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Egress PN Control Register: 1E.500E */ -/* MSS Egress PN Control Register: 1E.500E */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Egress PN Control Register */ - union - { - struct - { - /*! \brief 1E.500E.F:0 R/W MSS Egress SA PN Threshold LSW [F:0] - AQ_MssEgressPnControlRegister_HHD.u0.bits_0.mssEgressSaPnThresholdLSW - - Default = 0x0000 - - PN threshold bits 15:0 - - - Notes: - Egress PN threshold to generate SA threshold interrupt. */ - unsigned int mssEgressSaPnThresholdLSW : 16; /* 1E.500E.F:0 R/W Default = 0x0000 */ - /* PN threshold bits 15:0 - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Egress PN Control Register */ - union - { - struct - { - /*! \brief 1E.500F.F:0 R/W MSS Egress SA PN Threshold MSW [1F:10] - AQ_MssEgressPnControlRegister_HHD.u1.bits_1.mssEgressSaPnThresholdMSW - - Default = 0x0000 - - PN threshold bits 31:16 - - - Notes: - Egress PN threshold to generate SA threshold interrupt. */ - unsigned int mssEgressSaPnThresholdMSW : 16; /* 1E.500F.F:0 R/W Default = 0x0000 */ - /* PN threshold bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssEgressPnControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Egress MTU Size Control Register: 1E.5010 */ -/* MSS Egress MTU Size Control Register: 1E.5010 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Egress MTU Size Control Register */ - union - { - struct - { - /*! \brief 1E.5010.F:0 R/W MSS Egress Controlled Packet MTU Size [F:0] - AQ_MssEgressMtuSizeControlRegister_HHD.u0.bits_0.mssEgressControlledPacketMtuSize - - Default = 0x05DC - - Maximum transmission unit for controlled packet - - - Notes: - Maximum transmission unit of controlled packet */ - unsigned int mssEgressControlledPacketMtuSize : 16; /* 1E.5010.F:0 R/W Default = 0x05DC */ - /* Maximum transmission unit for controlled packet - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Egress MTU Size Control Register */ - union - { - struct - { - /*! \brief 1E.5011.F:0 R/W MSS Egress Uncontrolled Packet MTU Size [F:0] - AQ_MssEgressMtuSizeControlRegister_HHD.u1.bits_1.mssEgressUncontrolledPacketMtuSize - - Default = 0x05DC - - Maximum transmission unit for uncontrolled packet - - - Notes: - Maximum transmission unit of uncontrolled packet */ - unsigned int mssEgressUncontrolledPacketMtuSize : 16; /* 1E.5011.F:0 R/W Default = 0x05DC */ - /* Maximum transmission unit for uncontrolled packet - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssEgressMtuSizeControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Egress Interrupt Status Register: 1E.505C */ -/* MSS Egress Interrupt Status Register: 1E.505C */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Egress Interrupt Status Register */ - union - { - struct - { - unsigned int reserved0 : 11; - /*! \brief 1E.505C.4 COW MSS Egress ECC Error Interrupt - AQ_MssEgressInterruptStatusRegister_HHD.u0.bits_0.mssEgressEccErrorInterrupt - - Default = 0x0 - - 1 = Interrupt - - - Notes: - Write to 1 to clear. This bit is set when anyone of the memories detects an ECC error. */ - unsigned int mssEgressEccErrorInterrupt : 1; /* 1E.505C.4 COW Default = 0x0 */ - /* 1 = Interrupt - */ - /*! \brief 1E.505C.3 COW MSS Egress MIB Saturation Interrupt - AQ_MssEgressInterruptStatusRegister_HHD.u0.bits_0.mssEgressMibSaturationInterrupt - - Default = 0x0 - - 1 = Interrupt - - - Notes: - Write to 1 to clear. This bit is set when the MIB counters reaches all ones saturation. */ - unsigned int mssEgressMibSaturationInterrupt : 1; /* 1E.505C.3 COW Default = 0x0 */ - /* 1 = Interrupt - */ - /*! \brief 1E.505C.2 COW MSS Egress SA Threshold Expired Interrupt - AQ_MssEgressInterruptStatusRegister_HHD.u0.bits_0.mssEgressSaThresholdExpiredInterrupt - - Default = 0x0 - - 1 = Interrupt - - - Notes: - Write to 1 to clear. This bit is set when the SA PN reaches the See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . */ - unsigned int mssEgressSaThresholdExpiredInterrupt : 1; /* 1E.505C.2 COW Default = 0x0 */ - /* 1 = Interrupt - */ - /*! \brief 1E.505C.1 COW MSS Egress SA Expired Interrupt - AQ_MssEgressInterruptStatusRegister_HHD.u0.bits_0.mssEgressSaExpiredInterrupt - - Default = 0x0 - - 1 = Interrupt - - - Notes: - Write to 1 to clear. This bit is set when the SA PN reaches all ones saturation. */ - unsigned int mssEgressSaExpiredInterrupt : 1; /* 1E.505C.1 COW Default = 0x0 */ - /* 1 = Interrupt - */ - /*! \brief 1E.505C.0 COW MSS Egress Master Interrupt - AQ_MssEgressInterruptStatusRegister_HHD.u0.bits_0.mssEgressMasterInterrupt - - Default = 0x0 - - 1 = Interrupt - - - Notes: - Write to 1 to clear. This bit is set when any one of the above interrupt and the corresponding interrupt enable are both set. The interrupt enable for this bit must also be set for this bit to be set. */ - unsigned int mssEgressMasterInterrupt : 1; /* 1E.505C.0 COW Default = 0x0 */ - /* 1 = Interrupt - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Egress Interrupt Status Register */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssEgressInterruptStatusRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Egress Interrupt Mask Register: 1E.505E */ -/* MSS Egress Interrupt Mask Register: 1E.505E */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Egress Interrupt Mask Register */ - union - { - struct - { - unsigned int reserved0 : 11; - /*! \brief 1E.505E.4 COW MSS Egress ECC Error Interrupt Enable - AQ_MssEgressInterruptMaskRegister_HHD.u0.bits_0.mssEgressEccErrorInterruptEnable - - Default = 0x0 - - 1 = Interrupt enabled - - - Notes: - Write to 1 to clear. This bit is set when anyone of the memories detects an ECC error. */ - unsigned int mssEgressEccErrorInterruptEnable : 1; /* 1E.505E.4 COW Default = 0x0 */ - /* 1 = Interrupt enabled - */ - /*! \brief 1E.505E.3 COW MSS Egress MIB Saturation Interrupt Enable - AQ_MssEgressInterruptMaskRegister_HHD.u0.bits_0.mssEgressMibSaturationInterruptEnable - - Default = 0x0 - - 1 = Interrupt enabled - - - Notes: - Write to 1 to clear. This bit is set when the MIB counters reaches all ones saturation. */ - unsigned int mssEgressMibSaturationInterruptEnable : 1; /* 1E.505E.3 COW Default = 0x0 */ - /* 1 = Interrupt enabled - */ - /*! \brief 1E.505E.2 COW MSS Egress SA Expired Threshold Interrupt Enable - AQ_MssEgressInterruptMaskRegister_HHD.u0.bits_0.mssEgressSaExpiredThresholdInterruptEnable - - Default = 0x0 - - 1 = Interrupt enabled - - - Notes: - Write to 1 to clear. This bit is set when the SA PN reaches the configured threshold See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . */ - unsigned int mssEgressSaExpiredThresholdInterruptEnable : 1; /* 1E.505E.2 COW Default = 0x0 */ - /* 1 = Interrupt enabled - */ - /*! \brief 1E.505E.1 COW MSS Egress SA Expired Interrupt Enable - AQ_MssEgressInterruptMaskRegister_HHD.u0.bits_0.mssEgressSaExpiredInterruptEnable - - Default = 0x0 - - 1 = Interrupt enabled - - - Notes: - Write to 1 to clear. This bit is set when the SA PN reaches all ones saturation. */ - unsigned int mssEgressSaExpiredInterruptEnable : 1; /* 1E.505E.1 COW Default = 0x0 */ - /* 1 = Interrupt enabled - */ - /*! \brief 1E.505E.0 COW MSS Egress Master Interrupt Enable - AQ_MssEgressInterruptMaskRegister_HHD.u0.bits_0.mssEgressMasterInterruptEnable - - Default = 0x0 - - 1 = Interrupt enabled - - - Notes: - Write to 1 to clear. */ - unsigned int mssEgressMasterInterruptEnable : 1; /* 1E.505E.0 COW Default = 0x0 */ - /* 1 = Interrupt enabled - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Egress Interrupt Mask Register */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssEgressInterruptMaskRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Egress SA Expired Status Register: 1E.5060 */ -/* MSS Egress SA Expired Status Register: 1E.5060 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Egress SA Expired Status Register */ - union - { - struct - { - /*! \brief 1E.5060.F:0 COW MSS Egress SA Expired LSW [F:0] - AQ_MssEgressSaExpiredStatusRegister_HHD.u0.bits_0.mssEgressSaExpiredLSW - - Default = 0x0000 - - SA expired bits 15:0 - - - Notes: - Write these bits to 1 to clear. - When set, these bits identify the SA that has expired when the SA PN reaches all-ones saturation. */ - unsigned int mssEgressSaExpiredLSW : 16; /* 1E.5060.F:0 COW Default = 0x0000 */ - /* SA expired bits 15:0 - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Egress SA Expired Status Register */ - union - { - struct - { - /*! \brief 1E.5061.F:0 COW MSS Egress SA Expired MSW [1F:10] - AQ_MssEgressSaExpiredStatusRegister_HHD.u1.bits_1.mssEgressSaExpiredMSW - - Default = 0x0000 - - SA expired bits 31:16 - - - Notes: - Write these bits to 1 to clear. - When set, these bits identify the SA that has expired when the SA PN reaches all-ones saturation. */ - unsigned int mssEgressSaExpiredMSW : 16; /* 1E.5061.F:0 COW Default = 0x0000 */ - /* SA expired bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssEgressSaExpiredStatusRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Egress SA Threshold Expired Status Register: 1E.5062 */ -/* MSS Egress SA Threshold Expired Status Register: 1E.5062 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Egress SA Threshold Expired Status Register */ - union - { - struct - { - /*! \brief 1E.5062.F:0 COW MSS Egress SA Threshold Expired LSW [F:0] - AQ_MssEgressSaThresholdExpiredStatusRegister_HHD.u0.bits_0.mssEgressSaThresholdExpiredLSW - - Default = 0x0000 - - SA threshold expired bits 15:0 - - - Notes: - Write these bits to 1 to clear. - When set, these bits identify the SA that has expired when the SA PN has reached the configured threshold See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . */ - unsigned int mssEgressSaThresholdExpiredLSW : 16; /* 1E.5062.F:0 COW Default = 0x0000 */ - /* SA threshold expired bits 15:0 - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Egress SA Threshold Expired Status Register */ - union - { - struct - { - /*! \brief 1E.5063.F:0 COW MSS Egress SA Threshold Expired MSW [1F:10] - AQ_MssEgressSaThresholdExpiredStatusRegister_HHD.u1.bits_1.mssEgressSaThresholdExpiredMSW - - Default = 0x0000 - - SA threshold expired bits 31:16 - - - Notes: - Write these bits to 1 to clear. - When set, these bits identify the SA that has expired when the SA PN has reached the configured threshold See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . */ - unsigned int mssEgressSaThresholdExpiredMSW : 16; /* 1E.5063.F:0 COW Default = 0x0000 */ - /* SA threshold expired bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssEgressSaThresholdExpiredStatusRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Egress ECC Interrupt Status Register: 1E.5064 */ -/* MSS Egress ECC Interrupt Status Register: 1E.5064 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Egress ECC Interrupt Status Register */ - union - { - struct - { - /*! \brief 1E.5064.F:0 COW MSS Egress SA ECC Error Interrupt LSW [F:0] - AQ_MssEgressEccInterruptStatusRegister_HHD.u0.bits_0.mssEgressSaEccErrorInterruptLSW - - Default = 0x0000 - - SA ECC error interrupt bits 15:0 - - - Notes: - Write these bits to 1 to clear. - When set to 1, indicates that an ECC error occured for the SA. */ - unsigned int mssEgressSaEccErrorInterruptLSW : 16; /* 1E.5064.F:0 COW Default = 0x0000 */ - /* SA ECC error interrupt bits 15:0 - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Egress ECC Interrupt Status Register */ - union - { - struct - { - /*! \brief 1E.5065.F:0 COW MSS Egress SA ECC Error Interrupt MSW [1F:10] - AQ_MssEgressEccInterruptStatusRegister_HHD.u1.bits_1.mssEgressSaEccErrorInterruptMSW - - Default = 0x0000 - - SA ECC error interrupt bits 31:16 - - - Notes: - Write these bits to 1 to clear. - When set to 1, indicates that an ECC error occured for the SA. */ - unsigned int mssEgressSaEccErrorInterruptMSW : 16; /* 1E.5065.F:0 COW Default = 0x0000 */ - /* SA ECC error interrupt bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssEgressEccInterruptStatusRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Egress LUT Address Control Register: 1E.5080 */ -/* MSS Egress LUT Address Control Register: 1E.5080 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Egress LUT Address Control Register */ - union - { - struct - { - /*! \brief 1E.5080.F:C R/W MSS Egress LUT Select [3:0] - AQ_MssEgressLutAddressControlRegister_HHD.u0.bits_0.mssEgressLutSelect - - Default = 0x0 - - LUT select - - - Notes: - 0x0 : Egress MAC Control FIlter (CTLF) LUT - 0x1 : Egress Classification LUT - 0x2 : Egress SC/SA LUT - 0x3 : Egress SMIB */ - unsigned int mssEgressLutSelect : 4; /* 1E.5080.F:C R/W Default = 0x0 */ - /* LUT select - */ - unsigned int reserved0 : 3; - /*! \brief 1E.5080.8:0 R/W MSS Egress LUT Address [8:0] - AQ_MssEgressLutAddressControlRegister_HHD.u0.bits_0.mssEgressLutAddress - - Default = 0x000 - - LUT address - - */ - unsigned int mssEgressLutAddress : 9; /* 1E.5080.8:0 R/W Default = 0x000 */ - /* LUT address - */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_MssEgressLutAddressControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Egress LUT Control Register: 1E.5081 */ -/* MSS Egress LUT Control Register: 1E.5081 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Egress LUT Control Register */ - union - { - struct - { - /*! \brief 1E.5081.F R/W MSS Egress LUT Write - AQ_MssEgressLutControlRegister_HHD.u0.bits_0.mssEgressLutWrite - - Default = 0x0 - - 1 = LUT write - - - Notes: - Setting this bit to 1, will write the LUT. This bit will automatically clear to 0. */ - unsigned int mssEgressLutWrite : 1; /* 1E.5081.F R/W Default = 0x0 */ - /* 1 = LUT write - */ - /*! \brief 1E.5081.E R/W MSS Egress LUT Read - AQ_MssEgressLutControlRegister_HHD.u0.bits_0.mssEgressLutRead - - Default = 0x0 - - 1 = LUT read - - - Notes: - Setting this bit to 1, will read the LUT. This bit will automatically clear to 0. */ - unsigned int mssEgressLutRead : 1; /* 1E.5081.E R/W Default = 0x0 */ - /* 1 = LUT read - */ - unsigned int reserved0 : 14; - } bits_0; - uint16_t word_0; - } u0; -} AQ_MssEgressLutControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Egress LUT Data Control Register: 1E.50A0 */ -/* MSS Egress LUT Data Control Register: 1E.50A0 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50A0.F:0 R/W MSS Egress LUT Data 0 [F:0] - AQ_MssEgressLutDataControlRegister_HHD.u0.bits_0.mssEgressLutData_0 - - Default = 0x0000 - - LUT data bits 15:0 - - */ - unsigned int mssEgressLutData_0 : 16; /* 1E.50A0.F:0 R/W Default = 0x0000 */ - /* LUT data bits 15:0 - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50A1.F:0 R/W MSS Egress LUT Data 1 [1F:10] - AQ_MssEgressLutDataControlRegister_HHD.u1.bits_1.mssEgressLutData_1 - - Default = 0x0000 - - LUT data bits 31:16 - - */ - unsigned int mssEgressLutData_1 : 16; /* 1E.50A1.F:0 R/W Default = 0x0000 */ - /* LUT data bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50A2.F:0 R/W MSS Egress LUT Data 2 [2F:20] - AQ_MssEgressLutDataControlRegister_HHD.u2.bits_2.mssEgressLutData_2 - - Default = 0x0000 - - LUT data bits 47:32 - - */ - unsigned int mssEgressLutData_2 : 16; /* 1E.50A2.F:0 R/W Default = 0x0000 */ - /* LUT data bits 47:32 - */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50A3.F:0 R/W MSS Egress LUT Data 3 [3F:30] - AQ_MssEgressLutDataControlRegister_HHD.u3.bits_3.mssEgressLutData_3 - - Default = 0x0000 - - LUT data bits 63:48 - - */ - unsigned int mssEgressLutData_3 : 16; /* 1E.50A3.F:0 R/W Default = 0x0000 */ - /* LUT data bits 63:48 - */ - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50A4.F:0 R/W MSS Egress LUT Data 4 [4F:40] - AQ_MssEgressLutDataControlRegister_HHD.u4.bits_4.mssEgressLutData_4 - - Default = 0x0000 - - LUT data bits 79:64 - - */ - unsigned int mssEgressLutData_4 : 16; /* 1E.50A4.F:0 R/W Default = 0x0000 */ - /* LUT data bits 79:64 - */ - } bits_4; - uint16_t word_4; - } u4; - /*! \brief Union for bit and word level access of word 5 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50A5.F:0 R/W MSS Egress LUT Data 5 [5F:50] - AQ_MssEgressLutDataControlRegister_HHD.u5.bits_5.mssEgressLutData_5 - - Default = 0x0000 - - LUT data bits 95:80 - - */ - unsigned int mssEgressLutData_5 : 16; /* 1E.50A5.F:0 R/W Default = 0x0000 */ - /* LUT data bits 95:80 - */ - } bits_5; - uint16_t word_5; - } u5; - /*! \brief Union for bit and word level access of word 6 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50A6.F:0 R/W MSS Egress LUT Data 6 [6F:60] - AQ_MssEgressLutDataControlRegister_HHD.u6.bits_6.mssEgressLutData_6 - - Default = 0x0000 - - LUT data bits 111:96 - - */ - unsigned int mssEgressLutData_6 : 16; /* 1E.50A6.F:0 R/W Default = 0x0000 */ - /* LUT data bits 111:96 - */ - } bits_6; - uint16_t word_6; - } u6; - /*! \brief Union for bit and word level access of word 7 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50A7.F:0 R/W MSS Egress LUT Data 7 [7F:70] - AQ_MssEgressLutDataControlRegister_HHD.u7.bits_7.mssEgressLutData_7 - - Default = 0x0000 - - LUT data bits 127:112 - - */ - unsigned int mssEgressLutData_7 : 16; /* 1E.50A7.F:0 R/W Default = 0x0000 */ - /* LUT data bits 127:112 - */ - } bits_7; - uint16_t word_7; - } u7; - /*! \brief Union for bit and word level access of word 8 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50A8.F:0 R/W MSS Egress LUT Data 8 [8F:80] - AQ_MssEgressLutDataControlRegister_HHD.u8.bits_8.mssEgressLutData_8 - - Default = 0x0000 - - LUT data bits 143:128 - - */ - unsigned int mssEgressLutData_8 : 16; /* 1E.50A8.F:0 R/W Default = 0x0000 */ - /* LUT data bits 143:128 - */ - } bits_8; - uint16_t word_8; - } u8; - /*! \brief Union for bit and word level access of word 9 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50A9.F:0 R/W MSS Egress LUT Data 9 [9F:90] - AQ_MssEgressLutDataControlRegister_HHD.u9.bits_9.mssEgressLutData_9 - - Default = 0x0000 - - LUT data bits 159:144 - - */ - unsigned int mssEgressLutData_9 : 16; /* 1E.50A9.F:0 R/W Default = 0x0000 */ - /* LUT data bits 159:144 - */ - } bits_9; - uint16_t word_9; - } u9; - /*! \brief Union for bit and word level access of word 10 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50AA.F:0 R/W MSS Egress LUT Data 10 [AF:A0] - AQ_MssEgressLutDataControlRegister_HHD.u10.bits_10.mssEgressLutData_10 - - Default = 0x0000 - - LUT data bits 175:160 - - */ - unsigned int mssEgressLutData_10 : 16; /* 1E.50AA.F:0 R/W Default = 0x0000 */ - /* LUT data bits 175:160 - */ - } bits_10; - uint16_t word_10; - } u10; - /*! \brief Union for bit and word level access of word 11 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50AB.F:0 R/W MSS Egress LUT Data 11 [BF:B0] - AQ_MssEgressLutDataControlRegister_HHD.u11.bits_11.mssEgressLutData_11 - - Default = 0x0000 - - LUT data bits 191:176 - - */ - unsigned int mssEgressLutData_11 : 16; /* 1E.50AB.F:0 R/W Default = 0x0000 */ - /* LUT data bits 191:176 - */ - } bits_11; - uint16_t word_11; - } u11; - /*! \brief Union for bit and word level access of word 12 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50AC.F:0 R/W MSS Egress LUT Data 12 [CF:C0] - AQ_MssEgressLutDataControlRegister_HHD.u12.bits_12.mssEgressLutData_12 - - Default = 0x0000 - - LUT data bits 207:192 - - */ - unsigned int mssEgressLutData_12 : 16; /* 1E.50AC.F:0 R/W Default = 0x0000 */ - /* LUT data bits 207:192 - */ - } bits_12; - uint16_t word_12; - } u12; - /*! \brief Union for bit and word level access of word 13 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50AD.F:0 R/W MSS Egress LUT Data 13 [DF:D0] - AQ_MssEgressLutDataControlRegister_HHD.u13.bits_13.mssEgressLutData_13 - - Default = 0x0000 - - LUT data bits 223:208 - - */ - unsigned int mssEgressLutData_13 : 16; /* 1E.50AD.F:0 R/W Default = 0x0000 */ - /* LUT data bits 223:208 - */ - } bits_13; - uint16_t word_13; - } u13; - /*! \brief Union for bit and word level access of word 14 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50AE.F:0 R/W MSS Egress LUT Data 14 [EF:E0] - AQ_MssEgressLutDataControlRegister_HHD.u14.bits_14.mssEgressLutData_14 - - Default = 0x0000 - - LUT data bits 239:224 - - */ - unsigned int mssEgressLutData_14 : 16; /* 1E.50AE.F:0 R/W Default = 0x0000 */ - /* LUT data bits 239:224 - */ - } bits_14; - uint16_t word_14; - } u14; - /*! \brief Union for bit and word level access of word 15 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50AF.F:0 R/W MSS Egress LUT Data 15 [FF:F0] - AQ_MssEgressLutDataControlRegister_HHD.u15.bits_15.mssEgressLutData_15 - - Default = 0x0000 - - LUT data bits 255:240 - - */ - unsigned int mssEgressLutData_15 : 16; /* 1E.50AF.F:0 R/W Default = 0x0000 */ - /* LUT data bits 255:240 - */ - } bits_15; - uint16_t word_15; - } u15; - /*! \brief Union for bit and word level access of word 16 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50B0.F:0 R/W MSS Egress LUT Data 16 [10F:100] - AQ_MssEgressLutDataControlRegister_HHD.u16.bits_16.mssEgressLutData_16 - - Default = 0x0000 - - LUT data bits 271:256 - - */ - unsigned int mssEgressLutData_16 : 16; /* 1E.50B0.F:0 R/W Default = 0x0000 */ - /* LUT data bits 271:256 - */ - } bits_16; - uint16_t word_16; - } u16; - /*! \brief Union for bit and word level access of word 17 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50B1.F:0 R/W MSS Egress LUT Data 17 [11F:110] - AQ_MssEgressLutDataControlRegister_HHD.u17.bits_17.mssEgressLutData_17 - - Default = 0x0000 - - LUT data bits 287:272 - - */ - unsigned int mssEgressLutData_17 : 16; /* 1E.50B1.F:0 R/W Default = 0x0000 */ - /* LUT data bits 287:272 - */ - } bits_17; - uint16_t word_17; - } u17; - /*! \brief Union for bit and word level access of word 18 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50B2.F:0 R/W MSS Egress LUT Data 18 [12F:120] - AQ_MssEgressLutDataControlRegister_HHD.u18.bits_18.mssEgressLutData_18 - - Default = 0x0000 - - LUT data bits 303:288 - - */ - unsigned int mssEgressLutData_18 : 16; /* 1E.50B2.F:0 R/W Default = 0x0000 */ - /* LUT data bits 303:288 - */ - } bits_18; - uint16_t word_18; - } u18; - /*! \brief Union for bit and word level access of word 19 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50B3.F:0 R/W MSS Egress LUT Data 19 [13F:130] - AQ_MssEgressLutDataControlRegister_HHD.u19.bits_19.mssEgressLutData_19 - - Default = 0x0000 - - LUT data bits 319:304 - - */ - unsigned int mssEgressLutData_19 : 16; /* 1E.50B3.F:0 R/W Default = 0x0000 */ - /* LUT data bits 319:304 - */ - } bits_19; - uint16_t word_19; - } u19; - /*! \brief Union for bit and word level access of word 20 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50B4.F:0 R/W MSS Egress LUT Data 20 [14F:140] - AQ_MssEgressLutDataControlRegister_HHD.u20.bits_20.mssEgressLutData_20 - - Default = 0x0000 - - LUT data bits 335:320 - - */ - unsigned int mssEgressLutData_20 : 16; /* 1E.50B4.F:0 R/W Default = 0x0000 */ - /* LUT data bits 335:320 - */ - } bits_20; - uint16_t word_20; - } u20; - /*! \brief Union for bit and word level access of word 21 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50B5.F:0 R/W MSS Egress LUT Data 21 [15F:150] - AQ_MssEgressLutDataControlRegister_HHD.u21.bits_21.mssEgressLutData_21 - - Default = 0x0000 - - LUT data bits 351:336 - - */ - unsigned int mssEgressLutData_21 : 16; /* 1E.50B5.F:0 R/W Default = 0x0000 */ - /* LUT data bits 351:336 - */ - } bits_21; - uint16_t word_21; - } u21; - /*! \brief Union for bit and word level access of word 22 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50B6.F:0 R/W MSS Egress LUT Data 22 [16F:160] - AQ_MssEgressLutDataControlRegister_HHD.u22.bits_22.mssEgressLutData_22 - - Default = 0x0000 - - LUT data bits 367:352 - - */ - unsigned int mssEgressLutData_22 : 16; /* 1E.50B6.F:0 R/W Default = 0x0000 */ - /* LUT data bits 367:352 - */ - } bits_22; - uint16_t word_22; - } u22; - /*! \brief Union for bit and word level access of word 23 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50B7.F:0 R/W MSS Egress LUT Data 23 [17F:170] - AQ_MssEgressLutDataControlRegister_HHD.u23.bits_23.mssEgressLutData_23 - - Default = 0x0000 - - LUT data bits 383:368 - - */ - unsigned int mssEgressLutData_23 : 16; /* 1E.50B7.F:0 R/W Default = 0x0000 */ - /* LUT data bits 383:368 - */ - } bits_23; - uint16_t word_23; - } u23; - /*! \brief Union for bit and word level access of word 24 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50B8.F:0 R/W MSS Egress LUT Data 24 [18F:180] - AQ_MssEgressLutDataControlRegister_HHD.u24.bits_24.mssEgressLutData_24 - - Default = 0x0000 - - LUT data bits 399:384 - - */ - unsigned int mssEgressLutData_24 : 16; /* 1E.50B8.F:0 R/W Default = 0x0000 */ - /* LUT data bits 399:384 - */ - } bits_24; - uint16_t word_24; - } u24; - /*! \brief Union for bit and word level access of word 25 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50B9.F:0 R/W MSS Egress LUT Data 25 [19F:190] - AQ_MssEgressLutDataControlRegister_HHD.u25.bits_25.mssEgressLutData_25 - - Default = 0x0000 - - LUT data bits 415:400 - - */ - unsigned int mssEgressLutData_25 : 16; /* 1E.50B9.F:0 R/W Default = 0x0000 */ - /* LUT data bits 415:400 - */ - } bits_25; - uint16_t word_25; - } u25; - /*! \brief Union for bit and word level access of word 26 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50BA.F:0 R/W MSS Egress LUT Data 26 [1AF:1A0] - AQ_MssEgressLutDataControlRegister_HHD.u26.bits_26.mssEgressLutData_26 - - Default = 0x0000 - - LUT data bits 431:416 - - */ - unsigned int mssEgressLutData_26 : 16; /* 1E.50BA.F:0 R/W Default = 0x0000 */ - /* LUT data bits 431:416 - */ - } bits_26; - uint16_t word_26; - } u26; - /*! \brief Union for bit and word level access of word 27 of MSS Egress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.50BB.F:0 R/W MSS Egress LUT Data 27 [1BF:1B0] - AQ_MssEgressLutDataControlRegister_HHD.u27.bits_27.mssEgressLutData_27 - - Default = 0x0000 - - LUT data bits 447:432 - - */ - unsigned int mssEgressLutData_27 : 16; /* 1E.50BB.F:0 R/W Default = 0x0000 */ - /* LUT data bits 447:432 - */ - } bits_27; - uint16_t word_27; - } u27; -} AQ_MssEgressLutDataControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System General Control Register: 1E.6004 */ -/* MSM System General Control Register: 1E.6004 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System General Control Register */ - union - { - struct - { - /*! \brief 1E.6004.F R/W MSM System PHY Tx Enable - AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemPhyTxEnable - - Default = 0x0 - - 1 = Enable PHY Tx - - - Notes: - Directly controls the phy_tx_ena pin. */ - unsigned int msmSystemPhyTxEnable : 1; /* 1E.6004.F R/W Default = 0x0 */ - /* 1 = Enable PHY Tx - */ - /*! \brief 1E.6004.E R/W MSM System Rx Error Discard - AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemRxErrorDiscard - - Default = 0x0 - - 1 = Enable discard of received errored frames - - - Notes: - Rx errored frame discard enable. When set to 1, any frame received with an error is discarded and not forwarded to the client interface. When set to 0, errored frames are forwarded to the client interface with ff_rx_err asserted. - Note : It is recommended to set this bit to 1 only when store and forward operation is enabled (RX_SECTION_FULL TBD). */ - unsigned int msmSystemRxErrorDiscard : 1; /* 1E.6004.E R/W Default = 0x0 */ - /* 1 = Enable discard of received errored frames - */ - /*! \brief 1E.6004.D R/W MSM System Control Frame Enable - AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemControlFrameEnable - - Default = 0x0 - - 1 = Control frame enabled - - - Notes: - MAC control frame enable. When set to 1, the MAC control frames with any Opcode other than 0x0001 are accepted and forwarded to the client interface. When set to 0, MAC control frames with any opcode other than 0x0001 are silently discarded. */ - unsigned int msmSystemControlFrameEnable : 1; /* 1E.6004.D R/W Default = 0x0 */ - /* 1 = Control frame enabled - */ - /*! \brief 1E.6004.C R/WSC MSM System Soft Reset - AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemSoftReset - - Default = 0x0 - - 1 = Soft reset - - - Notes: - Software reset. Self clearing bit. When set to 1, resets all statistic counters as well as the Tx and Rx FIFOs. It should be issued after all traffic has been stopped as a result of clearing the Rx/Tx enable bits ( See MAC Rx Enable set to 0 and See MAC Tx Enable set to 0). - Note : Can lead to an Rx interface (ff_rx_xxx) violations to the application if the reset is issued in the middle of a receive frame transfer. Then the end of packet (assertion of ff_rx_eop) is lost and the application should be prepeared to handle this exception. */ - unsigned int msmSystemSoftReset : 1; /* 1E.6004.C R/WSC Default = 0x0 */ - /* 1 = Soft reset - */ - /*! \brief 1E.6004.B R/W MSM System Tx Pad Enable - AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemTxPadEnable - - Default = 0x1 - - 1 = Enable Tx padding - - - Notes: - When set to 1, enable padding of frames in the Tx direction. When set to 0, the MAC will not extend frames from the application to a minimum of 64 bytes, allowing to transmit short frames (violating the Ethernet mimimum size requirements). Must be set to 1 for normal operation. */ - unsigned int msmSystemTxPadEnable : 1; /* 1E.6004.B R/W Default = 0x1 */ - /* 1 = Enable Tx padding - */ - /*! \brief 1E.6004.A R/W MSM System Tx CRC Append - AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemTxCrcAppend - - Default = 0x0 - - 1 = Append Tx CRC - - - Notes: - Permanently enable CRC append on transmit. If set to 1, the Tx will append a CRC to all transmitted frames. If set to 0, CRC append can be controlled on a per frame basis using the pin ff_tx_crc. - This configuration bit is OR'ed with the external ff_tx_crc pin to instruct the Tx to append a CRC to transmitted frames. The ff_tx_crc pin is tied to 0. */ - unsigned int msmSystemTxCrcAppend : 1; /* 1E.6004.A R/W Default = 0x0 */ - /* 1 = Append Tx CRC - */ - /*! \brief 1E.6004.9 R/W MSM System Tx Address Insert Enable - AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemTxAddressInsertEnable - - Default = 0x0 - - 1 = Insert Tx MAC source address - - - Notes: - Set the source MAC address on transmit. If set to 1, the MAC overwrites the source MAC address with the MAC programmed address in all transmitted frames. When set to 0, the source MAC address is transmitted unmodified from the MAC Tx client application. */ - unsigned int msmSystemTxAddressInsertEnable : 1; /* 1E.6004.9 R/W Default = 0x0 */ - /* 1 = Insert Tx MAC source address - */ - /*! \brief 1E.6004.8 R/W MSM System Pause Ignore - AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemPauseIgnore - - Default = 0x0 - - 1 = Ignore pause frames - - - Notes: - Ignore pause frame quanta. If set to 1, received pause frames are ignored by the MAC. When set to 0, the Tx is stopped for the amount of time specified in the pause quanta received within the pause frame. */ - unsigned int msmSystemPauseIgnore : 1; /* 1E.6004.8 R/W Default = 0x0 */ - /* 1 = Ignore pause frames - */ - /*! \brief 1E.6004.7 R/W MSM System Pause Forward - AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemPauseForward - - Default = 0x0 - - 1 = Enable Pause forwarding - - - Notes: - Terminate or forward pause frames. If set to 1, pause frames are forwarded to the user application. In normal mode, when set to 0, pause frames are terminated and discarded within the MAC. */ - unsigned int msmSystemPauseForward : 1; /* 1E.6004.7 R/W Default = 0x0 */ - /* 1 = Enable Pause forwarding - */ - /*! \brief 1E.6004.6 R/W MSM System CRC Forward - AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemCrcForward - - Default = 0x0 - - 1 = Enable CRC forwarding - - - Notes: - When set to 1, the CRC field of the received frames is forwarded with the frame to the user application. If disabled, the CRC field is stripped from the frame. - Note : If padding is enabled ( See MAC PAD Enable set to 1), this bit is ignored. */ - unsigned int msmSystemCrcForward : 1; /* 1E.6004.6 R/W Default = 0x0 */ - /* 1 = Enable CRC forwarding - */ - /*! \brief 1E.6004.5 R/W MSM System PAD Enable - AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemPadEnable - - Default = 0x0 - - 1 = Enable frame padding removal on Rx - - - Notes: - When set to 1, enable frame padding removal on the Rx path. If enabled, padding is removed before the frame is transferred to the MAC client application. If disabled, no padding is removed on the Rx by the MAC. - Note : On Tx, the MAC always adds padding as required. */ - unsigned int msmSystemPadEnable : 1; /* 1E.6004.5 R/W Default = 0x0 */ - /* 1 = Enable frame padding removal on Rx - */ - /*! \brief 1E.6004.4 R/W MSM System Promiscuous Mode - AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemPromiscuousMode - - Default = 0x0 - - 1 = Promiscuous mode - - - Notes: - When set to 1, all frames are received without any MAC address filtering. */ - unsigned int msmSystemPromiscuousMode : 1; /* 1E.6004.4 R/W Default = 0x0 */ - /* 1 = Promiscuous mode - */ - /*! \brief 1E.6004.3 R/W MSM System WAN Mode - AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemWanMode - - Default = 0x0 - - 1 = WAN mode - 0 = LAN mode - - - Notes: - WAN mode enable. Sets WAN mode when set to 1 and LAN mode when set to 0. Note: When changing the mode, verifiy correct setting of the Tx IPG. */ - unsigned int msmSystemWanMode : 1; /* 1E.6004.3 R/W Default = 0x0 */ - /* 1 = WAN mode - 0 = LAN mode - */ - unsigned int reserved0 : 1; - /*! \brief 1E.6004.1 R/W MSM System Rx Enable - AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemRxEnable - - Default = 0x0 - - 1 = Rx enable - - Notes: - MAC Tx path enable. Should be set to 1 to enable the MAC Tx path. Should be set to 0 to disable the MAC Tx path. */ - unsigned int msmSystemRxEnable : 1; /* 1E.6004.1 R/W Default = 0x0 */ - /* 1 = Rx enable */ - /*! \brief 1E.6004.0 R/W MSM System Tx Enable - AQ_MsmSystemGeneralControlRegister_HHD.u0.bits_0.msmSystemTxEnable - - Default = 0x0 - - 1 = Tx enable - - Notes: - MAC Rx path enable. Should be set to 1 to enable the MAC Rx path. Should be set to 0 to disable the MAC Rx path. */ - unsigned int msmSystemTxEnable : 1; /* 1E.6004.0 R/W Default = 0x0 */ - /* 1 = Tx enable */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System General Control Register */ - union - { - struct - { - unsigned int reserved0 : 8; - /*! \brief 1E.6005.7 R/W MSM System Tx Low Power IDLE Enable - AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemTxLowPowerIdleEnable - - Default = 0x0 - - 1 = Transmit LPI enable - - - Notes: - Transmit low power IDLE enable. When set to 1, the MAC completes the transmission of the current frame and generates low power IDLE sequences (LPI) to the XGMII/SGMII. When set to 0, the MAC operates in normal mode. This bit is OR'ed with the reg_lowp_ena pin. */ - unsigned int msmSystemTxLowPowerIdleEnable : 1; /* 1E.6005.7 R/W Default = 0x0 */ - /* 1 = Transmit LPI enable - */ - unsigned int reserved1 : 1; - /*! \brief 1E.6005.5 R/W MSM System SFD Check Disable - AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemSfdCheckDisable - - Default = 0x0 - - 1 = Disable SFD check - - - Notes: - Disable check of SFD (0xD5) character at frame start. When set to 1, the frame is accepted even if the SFD byte following the preamble is not 0xD5. When set to 0, a frame is accepted only if the SFD byte is found with the value 0xD5. */ - unsigned int msmSystemSfdCheckDisable : 1; /* 1E.6005.5 R/W Default = 0x0 */ - /* 1 = Disable SFD check - */ - unsigned int reserved2 : 1; - /*! \brief 1E.6005.3 R/W MSM System Priority Flow Control Enable - AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemPriorityFlowControlEnable - - Default = 0x0 - - 1 = Enable priority flow control - 0 = Enable link flow control - - - Notes: - Enable priority flow control (PFC) mode of operation. When set to 0, the MAC uses standard link pause frames. When set to 1, the MAC will transmit and accept PFC frames. */ - unsigned int msmSystemPriorityFlowControlEnable : 1; /* 1E.6005.3 R/W Default = 0x0 */ - /* 1 = Enable priority flow control - 0 = Enable link flow control - */ - /*! \brief 1E.6005.2 R/W MSM System IDLE Column Count Extend - AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemIdleColumnCountExtend - - Default = 0x0 - - 1 = Extend IDLE column count - - Notes: - When set to 1, extends the RS layer IDLE column counter by 2x. The IEEE 802.3ae defines the fault condition to be cleared after 128 columns of IDLE have been received. If the MAC operates together with a WAN mode PCS (WIS) it may may happen (depending on PCS) that this period is too short to bridge the IDLE stuffing occurring in this mode, leading to a toggling fault indication. In this case, extending the counter helps to aoivd toggling fault indications. */ - unsigned int msmSystemIdleColumnCountExtend : 1; /* 1E.6005.2 R/W Default = 0x0 */ - /* 1 = Extend IDLE column count */ - /*! \brief 1E.6005.1 R/W MSM System Length Check Disable - AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemLengthCheckDisable - - Default = 0x0 - - 1 = Disable length check - - Notes: - Payload length check disable. When set to 0, the MAC checks the frames payload length with the frame length/type field. When set to 1, the payload length check is disabled. */ - unsigned int msmSystemLengthCheckDisable : 1; /* 1E.6005.1 R/W Default = 0x0 */ - /* 1 = Disable length check */ - /*! \brief 1E.6005.0 R/W MSM System Force Send IDLE - AQ_MsmSystemGeneralControlRegister_HHD.u1.bits_1.msmSystemForceSendIdle - - Default = 0x0 - - 1 = Force send idle - - Notes: - When set to 1, suppress any frame transmissions and forces IDLE n the Tx interface instead of frames. This control affects the MAC reconciliation layer (RS) which acts after all MAC datapath has processed the frame. - Note : Does not have an effect on fault handling (i.e. reception of local fault will still cause transmit of remote fault). - Must be 0 for normal operation. */ - unsigned int msmSystemForceSendIdle : 1; /* 1E.6005.0 R/W Default = 0x0 */ - /* 1 = Force send idle */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemGeneralControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System FIFO Control Register: 1E.600E */ -/* MSM System FIFO Control Register: 1E.600E */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System FIFO Control Register */ - union - { - struct - { - unsigned int reserved0 : 8; - /*! \brief 1E.600E.7:0 R/W MSM System Rx FIFO Full Threshold [7:0] - AQ_MsmSystemFifoControlRegister_HHD.u0.bits_0.msmSystemRxFifoFullThreshold - - Default = 0x08 - - Rx FIFO full threshold - - Notes: - All threshold values are in steps of FIFO words. */ - unsigned int msmSystemRxFifoFullThreshold : 8; /* 1E.600E.7:0 R/W Default = 0x08 */ - /* Rx FIFO full threshold */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System FIFO Control Register */ - union - { - struct - { - unsigned int reserved0 : 8; - /*! \brief 1E.600F.7:0 R/W MSM System Rx FIFO Empty Threshold [7:0] - AQ_MsmSystemFifoControlRegister_HHD.u1.bits_1.msmSystemRxFifoEmptyThreshold - - Default = 0x00 - - Rx FIFO empty threshold - - Notes: - All threshold values are in steps of FIFO words. */ - unsigned int msmSystemRxFifoEmptyThreshold : 8; /* 1E.600F.7:0 R/W Default = 0x00 */ - /* Rx FIFO empty threshold */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of MSM System FIFO Control Register */ - union - { - struct - { - unsigned int reserved0 : 10; - /*! \brief 1E.6010.5:0 R/W MSM System Tx FIFO Full Threshold [5:0] - AQ_MsmSystemFifoControlRegister_HHD.u2.bits_2.msmSystemTxFifoFullThreshold - - Default = 0x08 - - Tx FIFO full threshold - - Notes: - All threshold values are in steps of FIFO words. */ - unsigned int msmSystemTxFifoFullThreshold : 6; /* 1E.6010.5:0 R/W Default = 0x08 */ - /* Tx FIFO full threshold */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of MSM System FIFO Control Register */ - union - { - struct - { - unsigned int reserved0 : 10; - /*! \brief 1E.6011.5:0 R/W MSM System Tx FIFO Empty Threshold [5:0] - AQ_MsmSystemFifoControlRegister_HHD.u3.bits_3.msmSystemTxFifoEmptyThreshold - - Default = 0x00 - - Tx FIFO empty threshold - - Notes: - All threshold values are in steps of FIFO words. */ - unsigned int msmSystemTxFifoEmptyThreshold : 6; /* 1E.6011.5:0 R/W Default = 0x00 */ - /* Tx FIFO empty threshold */ - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of MSM System FIFO Control Register */ - union - { - struct - { - unsigned int reserved0 : 8; - /*! \brief 1E.6012.7:0 ROS MSM System Rx FIFO Almost Full Threshold [7:0] - AQ_MsmSystemFifoControlRegister_HHD.u4.bits_4.msmSystemRxFifoAlmostFullThreshold - - Default = 0x00 - - Rx FIFO almost full threshold - - Notes: - Unused. */ - unsigned int msmSystemRxFifoAlmostFullThreshold : 8; /* 1E.6012.7:0 ROS Default = 0x00 */ - /* Rx FIFO almost full threshold */ - } bits_4; - uint16_t word_4; - } u4; - /*! \brief Union for bit and word level access of word 5 of MSM System FIFO Control Register */ - union - { - struct - { - unsigned int reserved0 : 8; - /*! \brief 1E.6013.7:0 ROS MSM System Rx FIFO Almost Empty Threshold [7:0] - AQ_MsmSystemFifoControlRegister_HHD.u5.bits_5.msmSystemRxFifoAlmostEmptyThreshold - - Default = 0x00 - - Rx FIFO almost empty threshold - - Notes: - Unused. */ - unsigned int msmSystemRxFifoAlmostEmptyThreshold : 8; /* 1E.6013.7:0 ROS Default = 0x00 */ - /* Rx FIFO almost empty threshold */ - } bits_5; - uint16_t word_5; - } u5; - /*! \brief Union for bit and word level access of word 6 of MSM System FIFO Control Register */ - union - { - struct - { - unsigned int reserved0 : 8; - /*! \brief 1E.6014.7:0 ROS MSM System Tx FIFO Almost Full Threshold [7:0] - AQ_MsmSystemFifoControlRegister_HHD.u6.bits_6.msmSystemTxFifoAlmostFullThreshold - - Default = 0x00 - - Tx FIFO almost full threshold - - Notes: - Unused. */ - unsigned int msmSystemTxFifoAlmostFullThreshold : 8; /* 1E.6014.7:0 ROS Default = 0x00 */ - /* Tx FIFO almost full threshold */ - } bits_6; - uint16_t word_6; - } u6; - /*! \brief Union for bit and word level access of word 7 of MSM System FIFO Control Register */ - union - { - struct - { - unsigned int reserved0 : 8; - /*! \brief 1E.6015.7:0 ROS MSM System Tx FIFO Almost Empty Threshold [7:0] - AQ_MsmSystemFifoControlRegister_HHD.u7.bits_7.msmSystemTxFifoAlmostEmptyThreshold - - Default = 0x00 - - Tx FIFO almost empty threshold - - Notes: - Unused. */ - unsigned int msmSystemTxFifoAlmostEmptyThreshold : 8; /* 1E.6015.7:0 ROS Default = 0x00 */ - /* Tx FIFO almost empty threshold */ - } bits_7; - uint16_t word_7; - } u7; -} AQ_MsmSystemFifoControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System General Status Register: 1E.6020 */ -/* MSM System General Status Register: 1E.6020 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System General Status Register */ - union - { - struct - { - unsigned int reserved0 : 10; - /*! \brief 1E.6020.5 RO MSM System Tx FIFO Empty - AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemTxFifoEmpty - - - - Tx FIFO empty - - Notes: - When set to 1, indicates the Tx FIFO is empty. When set to 0, Tx FIFO is non-empty. */ - unsigned int msmSystemTxFifoEmpty : 1; /* 1E.6020.5 RO */ - /* Tx FIFO empty */ - /*! \brief 1E.6020.4 RO MSM System Rx Low Power IDLE - AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemRxLowPowerIdle - - - - Rx LPI detected - - Notes: - Receive low power IDLE (LPI). Set to 1 when LPI is currently detected on the MAC Rx interface. Set to 0, when the MAC currently operates in normal mode. */ - unsigned int msmSystemRxLowPowerIdle : 1; /* 1E.6020.4 RO */ - /* Rx LPI detected */ - /*! \brief 1E.6020.3 R/W MSM System Timestamp Available - AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemTimestampAvailable - - Default = 0x0 - - Timestamp available - - Notes: - Transmit timestamp available. Indicates that the timestamp of the last transmitted event frame (which had ff_tx_ts_frm=1) is available in the register See MAC Time Stamp Status 0 [F:0] and See MAC Time Stamp Status 1 [F:0] . To clear this bit, the bit must be written with a 1. - */ - unsigned int msmSystemTimestampAvailable : 1; /* 1E.6020.3 R/W Default = 0x0 */ - /* Timestamp available */ - /*! \brief 1E.6020.2 RO MSM System PHY Loss of Signal - AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemPhyLossOfSignal - - - - PHY loss of signal - - Notes: - PHY indicates loss of signal. This is the value of pin phy_los which is tied to 0. */ - unsigned int msmSystemPhyLossOfSignal : 1; /* 1E.6020.2 RO */ - /* PHY loss of signal */ - /*! \brief 1E.6020.1 BLH MSM System Rx Remote Fault - AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemRxRemoteFault - - - - Rx remote fault detected - - Notes: - Latch high local fault status. Set to 1, whent he MAC detects Rx local fault sequences on the Rx interface. Reset to 0 after read and after reset. */ - unsigned int msmSystemRxRemoteFault : 1; /* 1E.6020.1 BLH */ - /* Rx remote fault detected */ - /*! \brief 1E.6020.0 BLH MSM System Rx Local Fault - AQ_MsmSystemGeneralStatusRegister_HHD.u0.bits_0.msmSystemRxLocalFault - - - - Rx local fault detected - - Notes: - Latch high local fault status. Set to 1, whent he MAC detects Rx local fault sequences on the Rx interface. Reset to 0 after read and after reset. */ - unsigned int msmSystemRxLocalFault : 1; /* 1E.6020.0 BLH */ - /* Rx local fault detected */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System General Status Register */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemGeneralStatusRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Tx IPG Control Register: 1E.6022 */ -/* MSM System Tx IPG Control Register: 1E.6022 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Tx IPG Control Register */ - union - { - struct - { - unsigned int reserved0 : 10; - /*! \brief 1E.6022.5:0 R/W MSM System Tx IPG Length [5:0] - AQ_MsmSystemTxIpgControlRegister_HHD.u0.bits_0.msmSystemTxIpgLength - - Default = 0x0C - - Tx IPG length - - Notes: - Tx inter-packet gap (IPG) value. Depending on LAN or WAN mode of operation. - LAN Mode : Number of octets in steps of 4. Valid values are 8, 12, 16,..., 100. DIC is supported for any setting > 8. A default of 12 must be set to conform to IEEE802.3ae. - WAN Mode : Stretch factor. Valid values are 4 ... 15. The stretch factor is calculated as (value+1)*8. A default of 12 must be set to conform to IEEE802.3ae (i.e. 13*8=104). A larger value shrinks the IPG (increasing bandwidth). - The reset value of 12 leads to IEEE802.3ae conformant behavior in both modes. - Note : WAN mode is only available in 10G mode of operation. */ - unsigned int msmSystemTxIpgLength : 6; /* 1E.6022.5:0 R/W Default = 0x0C */ - /* Tx IPG length */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Tx IPG Control Register */ - union - { - struct - { - /*! \brief 1E.6023.F:0 MSM System Tx IPG Reserved - AQ_MsmSystemTxIpgControlRegister_HHD.u1.bits_1.msmSystemTxIpgReserved - - - - Value always 0, writes ignored - */ - unsigned int msmSystemTxIpgReserved : 16; /* 1E.6023.F:0 */ - /* Value always 0, writes ignored */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemTxIpgControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Tx Good Frames Counter Register: 1E.6040 */ -/* MSM System Tx Good Frames Counter Register: 1E.6040 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Tx Good Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6040.F:0 ROS MSM System Tx Good Frames Counter 0 [F:0] - AQ_MsmSystemTxGoodFramesCounterRegister_HHD.u0.bits_0.msmSystemTxGoodFramesCounter_0 - - Default = 0x0000 - - Tx good frame counter bits 15:0 - - Notes: - Count of frames transmitted without error (Including pause frames). */ - unsigned int msmSystemTxGoodFramesCounter_0 : 16; /* 1E.6040.F:0 ROS Default = 0x0000 */ - /* Tx good frame counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Tx Good Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6041.F:0 ROS MSM System Tx Good Frames Counter 1 [F:0] - AQ_MsmSystemTxGoodFramesCounterRegister_HHD.u1.bits_1.msmSystemTxGoodFramesCounter_1 - - Default = 0x0000 - - Tx good frame counter bits 31:16 - - - Notes: - Count of frames transmitted without error (Including pause frames). */ - unsigned int msmSystemTxGoodFramesCounter_1 : 16; /* 1E.6041.F:0 ROS Default = 0x0000 */ - /* Tx good frame counter bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemTxGoodFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Rx Good Frames Counter Register: 1E.6044 */ -/* MSM System Rx Good Frames Counter Register: 1E.6044 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Rx Good Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6044.F:0 ROS MSM System Rx Good Frames Counter 0 [F:0] - AQ_MsmSystemRxGoodFramesCounterRegister_HHD.u0.bits_0.msmSystemRxGoodFramesCounter_0 - - Default = 0x0000 - - Rx good frame counter bits 15:0 - - Notes: - Count of frames received without error (Including pause frames). */ - unsigned int msmSystemRxGoodFramesCounter_0 : 16; /* 1E.6044.F:0 ROS Default = 0x0000 */ - /* Rx good frame counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Rx Good Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6045.F:0 ROS MSM System Rx Good Frames Counter 1 [F:0] - AQ_MsmSystemRxGoodFramesCounterRegister_HHD.u1.bits_1.msmSystemRxGoodFramesCounter_1 - - Default = 0x0000 - - Rx good frame counter bits 31:16 - - Notes: - Count of frames received without error (Including pause frames). */ - unsigned int msmSystemRxGoodFramesCounter_1 : 16; /* 1E.6045.F:0 ROS Default = 0x0000 */ - /* Rx good frame counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemRxGoodFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Rx FCS Errors Counter Register: 1E.6048 */ -/* MSM System Rx FCS Errors Counter Register: 1E.6048 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Rx FCS Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.6048.F:0 ROS MSM System FCS Error Counter 0 [F:0] - AQ_MsmSystemRxFcsErrorsCounterRegister_HHD.u0.bits_0.msmSystemFcsErrorCounter_0 - - Default = 0x0000 - - Frame check sequence error counter bits 15:0 - - Notes: - Count of frames for which a CRC-32 Error is detected but the frame is otherwise of correct length. */ - unsigned int msmSystemFcsErrorCounter_0 : 16; /* 1E.6048.F:0 ROS Default = 0x0000 */ - /* Frame check sequence error counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Rx FCS Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.6049.F:0 ROS MSM System FCS Error Counter 1 [F:0] - AQ_MsmSystemRxFcsErrorsCounterRegister_HHD.u1.bits_1.msmSystemFcsErrorCounter_1 - - Default = 0x0000 - - Frame check sequence error counter bits 31:16 - - Notes: - Count of frames for which a CRC-32 Error is detected but the frame is otherwise of correct length. */ - unsigned int msmSystemFcsErrorCounter_1 : 16; /* 1E.6049.F:0 ROS Default = 0x0000 */ - /* Frame check sequence error counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemRxFcsErrorsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Rx Alignment Errors Counter Register: 1E.604C */ -/* MSM System Rx Alignment Errors Counter Register: 1E.604C */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Rx Alignment Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.604C.F:0 ROS MSM System Alignment Error Counter 0 [F:0] - AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD.u0.bits_0.msmSystemAlignmentErrorCounter_0 - - Default = 0x0000 - - Alignment error counter bits 15:0 - - Notes: - Count of frames received with an alignment error. */ - unsigned int msmSystemAlignmentErrorCounter_0 : 16; /* 1E.604C.F:0 ROS Default = 0x0000 */ - /* Alignment error counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Rx Alignment Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.604D.F:0 ROS MSM System Alignment Error Counter 1 [F:0] - AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD.u1.bits_1.msmSystemAlignmentErrorCounter_1 - - Default = 0x0000 - - Alignment error counter bits 31:16 - - Notes: - Count of frames received with an alignment error. */ - unsigned int msmSystemAlignmentErrorCounter_1 : 16; /* 1E.604D.F:0 ROS Default = 0x0000 */ - /* Alignment error counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Tx Pause Frames Counter Register: 1E.6050 */ -/* MSM System Tx Pause Frames Counter Register: 1E.6050 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Tx Pause Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6050.F:0 ROS MSM System Tx Pause Frames Counter 0 [F:0] - AQ_MsmSystemTxPauseFramesCounterRegister_HHD.u0.bits_0.msmSystemTxPauseFramesCounter_0 - - Default = 0x0000 - - Tx pause frame counter bits 15:0 - - Notes: - Valid pause frames transmitted. */ - unsigned int msmSystemTxPauseFramesCounter_0 : 16; /* 1E.6050.F:0 ROS Default = 0x0000 */ - /* Tx pause frame counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Tx Pause Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6051.F:0 ROS MSM System Tx Pause Frames Counter 1 [F:0] - AQ_MsmSystemTxPauseFramesCounterRegister_HHD.u1.bits_1.msmSystemTxPauseFramesCounter_1 - - Default = 0x0000 - - Tx pause frame counter bits 31:16 - - - Notes: - Valid pause frames transmitted. */ - unsigned int msmSystemTxPauseFramesCounter_1 : 16; /* 1E.6051.F:0 ROS Default = 0x0000 */ - /* Tx pause frame counter bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemTxPauseFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Rx Pause Frames Counter Register: 1E.6054 */ -/* MSM System Rx Pause Frames Counter Register: 1E.6054 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Rx Pause Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6054.F:0 ROS MSM System Rx Pause Frames Counter 0 [F:0] - AQ_MsmSystemRxPauseFramesCounterRegister_HHD.u0.bits_0.msmSystemRxPauseFramesCounter_0 - - Default = 0x0000 - - Rx pause frame counter bits 15:0 - - Notes: - Valid pause frames received. */ - unsigned int msmSystemRxPauseFramesCounter_0 : 16; /* 1E.6054.F:0 ROS Default = 0x0000 */ - /* Rx pause frame counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Rx Pause Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6055.F:0 ROS MSM System Rx Pause Frames Counter 1 [F:0] - AQ_MsmSystemRxPauseFramesCounterRegister_HHD.u1.bits_1.msmSystemRxPauseFramesCounter_1 - - Default = 0x0000 - - Rx pause frame counter bits 31:16 - - Notes: - Valid pause frames received. */ - unsigned int msmSystemRxPauseFramesCounter_1 : 16; /* 1E.6055.F:0 ROS Default = 0x0000 */ - /* Rx pause frame counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemRxPauseFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Rx Too Long Errors Counter Register: 1E.6058 */ -/* MSM System Rx Too Long Errors Counter Register: 1E.6058 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Rx Too Long Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.6058.F:0 ROS MSM System Rx Too Long Errors Counter 0 [F:0] - AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD.u0.bits_0.msmSystemRxTooLongErrorsCounter_0 - - Default = 0x0000 - - Too-long errors counter bits 15:0 - - Notes: - Frame received exceeded the maximum length programmed with register FRM_LGTH. */ - unsigned int msmSystemRxTooLongErrorsCounter_0 : 16; /* 1E.6058.F:0 ROS Default = 0x0000 */ - /* Too-long errors counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Rx Too Long Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.6059.F:0 ROS MSM System Rx Too Long Errors Counter 1 [F:0] - AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD.u1.bits_1.msmSystemRxTooLongErrorsCounter_1 - - Default = 0x0000 - - Too-long errors counter bits 31:16 - - Notes: - Frame received exceeded the maximum length programmed with register FRM_LGTH. */ - unsigned int msmSystemRxTooLongErrorsCounter_1 : 16; /* 1E.6059.F:0 ROS Default = 0x0000 */ - /* Too-long errors counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Rx In Range Length Errors Counter Register: 1E.605C */ -/* MSM System Rx In Range Length Errors Counter Register: 1E.605C */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Rx In Range Length Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.605C.F:0 ROS MSM System Rx In Range Length Errors Counter 0 [F:0] - AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD.u0.bits_0.msmSystemRxInRangeLengthErrorsCounter_0 - - Default = 0x0000 - - In-range-length errors counter bits 15:0 - - Notes: - A count of frames with a length/type field value between 46 (VLAN: 42) and less than 0x0600, that does not match the number of payload data octets received. Should count also if length/type field is less than 46 (VLAN: 42) and the frame is longer than 64 bytes. */ - unsigned int msmSystemRxInRangeLengthErrorsCounter_0 : 16; /* 1E.605C.F:0 ROS Default = 0x0000 */ - /* In-range-length errors counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Rx In Range Length Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.605D.F:0 ROS MSM System Rx In Range Length Errors Counter 1 [F:0] - AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD.u1.bits_1.msmSystemRxInRangeLengthErrorsCounter_1 - - Default = 0x0000 - - In-range-length errors counter bits 31:16 - - Notes: - A count of frames with a length/type field value between 46 (VLAN: 42) and less than 0x0600, that does not match the number of payload data octets received. Should count also if length/type field is less than 46 (VLAN: 42) and the frame is longer than 64 bytes. */ - unsigned int msmSystemRxInRangeLengthErrorsCounter_1 : 16; /* 1E.605D.F:0 ROS Default = 0x0000 */ - /* In-range-length errors counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Tx VLAN Frames Counter Register: 1E.6060 */ -/* MSM System Tx VLAN Frames Counter Register: 1E.6060 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Tx VLAN Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6060.F:0 ROS MSM System Tx VLAN Frames Counter 0 [F:0] - AQ_MsmSystemTxVlanFramesCounterRegister_HHD.u0.bits_0.msmSystemTxVlanFramesCounter_0 - - Default = 0x0000 - - Tx VLAN frames counter bits 15:0 - - Notes: - Valid VLAN tagged frames transmitted. */ - unsigned int msmSystemTxVlanFramesCounter_0 : 16; /* 1E.6060.F:0 ROS Default = 0x0000 */ - /* Tx VLAN frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Tx VLAN Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6061.F:0 ROS MSM System Tx VLAN Frames Counter 1 [F:0] - AQ_MsmSystemTxVlanFramesCounterRegister_HHD.u1.bits_1.msmSystemTxVlanFramesCounter_1 - - Default = 0x0000 - - Tx VLAN frames counter bits 31:16 - - Notes: - Valid VLAN tagged frames transmitted. */ - unsigned int msmSystemTxVlanFramesCounter_1 : 16; /* 1E.6061.F:0 ROS Default = 0x0000 */ - /* Tx VLAN frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemTxVlanFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Rx VLAN Frames Counter Register: 1E.6064 */ -/* MSM System Rx VLAN Frames Counter Register: 1E.6064 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Rx VLAN Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6064.F:0 ROS MSM System Rx VLAN Frames Counter 0 [F:0] - AQ_MsmSystemRxVlanFramesCounterRegister_HHD.u0.bits_0.msmSystemRxVlanFramesCounter_0 - - Default = 0x0000 - - Rx VLAN frames counter bits 15:0 - - Notes: - Valid VLAN tagged frames received. */ - unsigned int msmSystemRxVlanFramesCounter_0 : 16; /* 1E.6064.F:0 ROS Default = 0x0000 */ - /* Rx VLAN frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Rx VLAN Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6065.F:0 ROS MSM System Rx VLAN Frames Counter 1 [F:0] - AQ_MsmSystemRxVlanFramesCounterRegister_HHD.u1.bits_1.msmSystemRxVlanFramesCounter_1 - - Default = 0x0000 - - Rx VLAN frames counter bits 31:16 - - Notes: - Valid VLAN tagged frames received. */ - unsigned int msmSystemRxVlanFramesCounter_1 : 16; /* 1E.6065.F:0 ROS Default = 0x0000 */ - /* Rx VLAN frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemRxVlanFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Tx Octets Counter Register: 1E.6068 */ -/* MSM System Tx Octets Counter Register: 1E.6068 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Tx Octets Counter Register */ - union - { - struct - { - /*! \brief 1E.6068.F:0 ROS MSM System Tx Octets Counter 0 [F:0] - AQ_MsmSystemTxOctetsCounterRegister_HHD.u0.bits_0.msmSystemTxOctetsCounter_0 - - Default = 0x0000 - - Tx octets counter bits 15:0 - - Notes: - All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ - unsigned int msmSystemTxOctetsCounter_0 : 16; /* 1E.6068.F:0 ROS Default = 0x0000 */ - /* Tx octets counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Tx Octets Counter Register */ - union - { - struct - { - /*! \brief 1E.6069.F:0 ROS MSM System Tx Octets Counter 1 [F:0] - AQ_MsmSystemTxOctetsCounterRegister_HHD.u1.bits_1.msmSystemTxOctetsCounter_1 - - Default = 0x0000 - - Tx octets counter bits 31:16 - - Notes: - All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ - unsigned int msmSystemTxOctetsCounter_1 : 16; /* 1E.6069.F:0 ROS Default = 0x0000 */ - /* Tx octets counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of MSM System Tx Octets Counter Register */ - union - { - struct - { - /*! \brief 1E.606A.F:0 ROS MSM System Tx Octets Counter 2 [F:0] - AQ_MsmSystemTxOctetsCounterRegister_HHD.u2.bits_2.msmSystemTxOctetsCounter_2 - - Default = 0x0000 - - Tx octets counter bits 47:32 - - Notes: - All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ - unsigned int msmSystemTxOctetsCounter_2 : 16; /* 1E.606A.F:0 ROS Default = 0x0000 */ - /* Tx octets counter bits 47:32 */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of MSM System Tx Octets Counter Register */ - union - { - struct - { - /*! \brief 1E.606B.F:0 ROS MSM System Tx Octets Counter 3 [F:0] - AQ_MsmSystemTxOctetsCounterRegister_HHD.u3.bits_3.msmSystemTxOctetsCounter_3 - - Default = 0x0000 - - Tx octets counter bits 63:48 - - Notes: - All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ - unsigned int msmSystemTxOctetsCounter_3 : 16; /* 1E.606B.F:0 ROS Default = 0x0000 */ - /* Tx octets counter bits 63:48 */ - } bits_3; - uint16_t word_3; - } u3; -} AQ_MsmSystemTxOctetsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Rx Octets Counter Register: 1E.606C */ -/* MSM System Rx Octets Counter Register: 1E.606C */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Rx Octets Counter Register */ - union - { - struct - { - /*! \brief 1E.606C.F:0 ROS MSM System Rx Octets Counter 0 [F:0] - AQ_MsmSystemRxOctetsCounterRegister_HHD.u0.bits_0.msmSystemRxOctetsCounter_0 - - Default = 0x0000 - - Rx octets counter bits 15:0 - - Notes: - All octets received except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames received. */ - unsigned int msmSystemRxOctetsCounter_0 : 16; /* 1E.606C.F:0 ROS Default = 0x0000 */ - /* Rx octets counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Rx Octets Counter Register */ - union - { - struct - { - /*! \brief 1E.606D.F:0 ROS MSM System Rx Octets Counter 1 [F:0] - AQ_MsmSystemRxOctetsCounterRegister_HHD.u1.bits_1.msmSystemRxOctetsCounter_1 - - Default = 0x0000 - - Rx octets counter bits 31:16 - - Notes: - All octets received except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames received. */ - unsigned int msmSystemRxOctetsCounter_1 : 16; /* 1E.606D.F:0 ROS Default = 0x0000 */ - /* Rx octets counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemRxOctetsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Rx Unicast Frames Counter Register: 1E.6070 */ -/* MSM System Rx Unicast Frames Counter Register: 1E.6070 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Rx Unicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6070.F:0 ROS MSM System Rx Unicast Frames Counter 0 [F:0] - AQ_MsmSystemRxUnicastFramesCounterRegister_HHD.u0.bits_0.msmSystemRxUnicastFramesCounter_0 - - Default = 0x0000 - - Rx unicast frames counter bits 15:0 - - Notes: - Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '0'. */ - unsigned int msmSystemRxUnicastFramesCounter_0 : 16; /* 1E.6070.F:0 ROS Default = 0x0000 */ - /* Rx unicast frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Rx Unicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6071.F:0 ROS MSM System Rx Unicast Frames Counter 1 [F:0] - AQ_MsmSystemRxUnicastFramesCounterRegister_HHD.u1.bits_1.msmSystemRxUnicastFramesCounter_1 - - Default = 0x0000 - - Rx unicast frames counter bits 31:16 - - Notes: - Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '0'. */ - unsigned int msmSystemRxUnicastFramesCounter_1 : 16; /* 1E.6071.F:0 ROS Default = 0x0000 */ - /* Rx unicast frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemRxUnicastFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Rx Multicast Frames Counter Register: 1E.6074 */ -/* MSM System Rx Multicast Frames Counter Register: 1E.6074 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Rx Multicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6074.F:0 ROS MSM System Rx Multicast Frames Counter 0 [F:0] - AQ_MsmSystemRxMulticastFramesCounterRegister_HHD.u0.bits_0.msmSystemRxMulticastFramesCounter_0 - - Default = 0x0000 - - Rx multicast frames counter bits 15:0 - - Notes: - Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '1' but not the broadcast address (all bits set '1' ). Pause frames are not counted. */ - unsigned int msmSystemRxMulticastFramesCounter_0 : 16; /* 1E.6074.F:0 ROS Default = 0x0000 */ - /* Rx multicast frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Rx Multicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6075.F:0 ROS MSM System Rx Multicast Frames Counter 1 [F:0] - AQ_MsmSystemRxMulticastFramesCounterRegister_HHD.u1.bits_1.msmSystemRxMulticastFramesCounter_1 - - Default = 0x0000 - - Rx multicast frames counter bits 31:16 - - Notes: - Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '1' but not the broadcast address (all bits set '1' ). Pause frames are not counted. */ - unsigned int msmSystemRxMulticastFramesCounter_1 : 16; /* 1E.6075.F:0 ROS Default = 0x0000 */ - /* Rx multicast frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemRxMulticastFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Rx Broadcast Frames Counter Register: 1E.6078 */ -/* MSM System Rx Broadcast Frames Counter Register: 1E.6078 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Rx Broadcast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6078.F:0 ROS MSM System Rx Broadcast Frames Counter 0 [F:0] - AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD.u0.bits_0.msmSystemRxBroadcastFramesCounter_0 - - Default = 0x0000 - - Rx broadcast frames counter bits 15:0 - - Notes: - Incremented with each valid frame received on the receive FIFO interface (FIFO) and all bits of the destination address were set '1'. */ - unsigned int msmSystemRxBroadcastFramesCounter_0 : 16; /* 1E.6078.F:0 ROS Default = 0x0000 */ - /* Rx broadcast frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Rx Broadcast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6079.F:0 ROS MSM System Rx Broadcast Frames Counter 1 [F:0] - AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD.u1.bits_1.msmSystemRxBroadcastFramesCounter_1 - - Default = 0x0000 - - Rx broadcast frames counter bits 31:16 - - Notes: - Incremented with each valid frame received on the receive FIFO interface (FIFO) and all bits of the destination address were set '1'. */ - unsigned int msmSystemRxBroadcastFramesCounter_1 : 16; /* 1E.6079.F:0 ROS Default = 0x0000 */ - /* Rx broadcast frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Tx Errors Counter Register: 1E.607C */ -/* MSM System Tx Errors Counter Register: 1E.607C */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Tx Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.607C.F:0 ROS MSM System Tx Errors Counter 0 [F:0] - AQ_MsmSystemTxErrorsCounterRegister_HHD.u0.bits_0.msmSystemTxErrorsCounter_0 - - Default = 0x0000 - - Rx errors counter bits 15:0 - - Notes: - Number of frames transmitted with error: - - FIFO Overflow Errors - - FIFO Underflow Errors */ - unsigned int msmSystemTxErrorsCounter_0 : 16; /* 1E.607C.F:0 ROS Default = 0x0000 */ - /* Rx errors counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Tx Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.607D.F:0 ROS MSM System Tx Errors Counter 1 [F:0] - AQ_MsmSystemTxErrorsCounterRegister_HHD.u1.bits_1.msmSystemTxErrorsCounter_1 - - Default = 0x0000 - - Tx errors counter bits 31:16 - - Notes: - Number of frames transmitted with error: - - FIFO Overflow Errors - - FIFO Underflow Errors */ - unsigned int msmSystemTxErrorsCounter_1 : 16; /* 1E.607D.F:0 ROS Default = 0x0000 */ - /* Tx errors counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemTxErrorsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Tx Unicast Frames Counter Register: 1E.6084 */ -/* MSM System Tx Unicast Frames Counter Register: 1E.6084 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Tx Unicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6084.F:0 ROS MSM System Tx Unicast Frames Counter 0 [F:0] - AQ_MsmSystemTxUnicastFramesCounterRegister_HHD.u0.bits_0.msmSystemTxUnicastFramesCounter_0 - - Default = 0x0000 - - Tx unicast frames counter bits 15:0 - - Notes: - Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '0'. */ - unsigned int msmSystemTxUnicastFramesCounter_0 : 16; /* 1E.6084.F:0 ROS Default = 0x0000 */ - /* Tx unicast frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Tx Unicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6085.F:0 ROS MSM System Tx Unicast Frames Counter 1 [F:0] - AQ_MsmSystemTxUnicastFramesCounterRegister_HHD.u1.bits_1.msmSystemTxUnicastFramesCounter_1 - - Default = 0x0000 - - Tx unicast frames counter bits 31:16 - - Notes: - Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '0'. */ - unsigned int msmSystemTxUnicastFramesCounter_1 : 16; /* 1E.6085.F:0 ROS Default = 0x0000 */ - /* Tx unicast frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemTxUnicastFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Tx Multicast Frames Counter Register: 1E.6088 */ -/* MSM System Tx Multicast Frames Counter Register: 1E.6088 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Tx Multicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6088.F:0 ROS MSM System Tx Multicast Frames Counter 0 [F:0] - AQ_MsmSystemTxMulticastFramesCounterRegister_HHD.u0.bits_0.msmSystemTxMulticastFramesCounter_0 - - Default = 0x0000 - - Tx multicast frames counter bits 15:0 - - Notes: - Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '1' but not the broadcast address (all bits '1'). */ - unsigned int msmSystemTxMulticastFramesCounter_0 : 16; /* 1E.6088.F:0 ROS Default = 0x0000 */ - /* Tx multicast frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Tx Multicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.6089.F:0 ROS MSM System Tx Multicast Frames Counter 1 [F:0] - AQ_MsmSystemTxMulticastFramesCounterRegister_HHD.u1.bits_1.msmSystemTxMulticastFramesCounter_1 - - Default = 0x0000 - - Tx multicast frames counter bits 31:16 - - Notes: - Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '1' but not the broadcast address (all bits '1'). */ - unsigned int msmSystemTxMulticastFramesCounter_1 : 16; /* 1E.6089.F:0 ROS Default = 0x0000 */ - /* Tx multicast frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemTxMulticastFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Tx Broadcast Frames Counter Register: 1E.608C */ -/* MSM System Tx Broadcast Frames Counter Register: 1E.608C */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Tx Broadcast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.608C.F:0 ROS MSM System Tx Broadcast Frames Counter 0 [F:0] - AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD.u0.bits_0.msmSystemTxBroadcastFramesCounter_0 - - Default = 0x0000 - - Tx broadcast frames counter bits 15:0 - - Notes: - Incremented with each frame written to the FIFO interface and all bits of the destination address set to '1'. */ - unsigned int msmSystemTxBroadcastFramesCounter_0 : 16; /* 1E.608C.F:0 ROS Default = 0x0000 */ - /* Tx broadcast frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Tx Broadcast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.608D.F:0 ROS MSM System Tx Broadcast Frames Counter 1 [F:0] - AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD.u1.bits_1.msmSystemTxBroadcastFramesCounter_1 - - Default = 0x0000 - - Tx broadcast frames counter bits 31:16 - - Notes: - Incremented with each frame written to the FIFO interface and all bits of the destination address set to '1'. */ - unsigned int msmSystemTxBroadcastFramesCounter_1 : 16; /* 1E.608D.F:0 ROS Default = 0x0000 */ - /* Tx broadcast frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM System Rx Errors Counter Register: 1E.60C8 */ -/* MSM System Rx Errors Counter Register: 1E.60C8 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM System Rx Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.60C8.F:0 ROS MSM System Rx Errors Counter 0 [F:0] - AQ_MsmSystemRxErrorsCounterRegister_HHD.u0.bits_0.msmSystemRxErrorsCounter_0 - - Default = 0x0000 - - Rx errors counter bits 15:0 - - Notes: - Number of frames received with error: - - FIFO Overflow Errors - - CRC Errors - - Payload Length Errors - - Jabber and Oversized Errors - - Alignment Errors - - The dedicated Error Code (0xfe, not a code error) was received */ - unsigned int msmSystemRxErrorsCounter_0 : 16; /* 1E.60C8.F:0 ROS Default = 0x0000 */ - /* Rx errors counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM System Rx Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.60C9.F:0 ROS MSM System Rx Errors Counter 1 [F:0] - AQ_MsmSystemRxErrorsCounterRegister_HHD.u1.bits_1.msmSystemRxErrorsCounter_1 - - Default = 0x0000 - - Rx errors counter bits 31:16 - - Notes: - Number of frames received with error: - - FIFO Overflow Errors - - CRC Errors - - Payload Length Errors - - Jabber and Oversized Errors - - Alignment Errors - - The dedicated Error Code (0xfe, not a code error) was received */ - unsigned int msmSystemRxErrorsCounter_1 : 16; /* 1E.60C9.F:0 ROS Default = 0x0000 */ - /* Rx errors counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmSystemRxErrorsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress VLAN TPID 0 Register: 1E.8006 */ -/* MSS Ingress VLAN TPID 0 Register: 1E.8006 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress VLAN TPID 0 Register */ - union - { - struct - { - /*! \brief 1E.8006.F:0 R/W MSS Ingress VLAN STag [F:0] - AQ_MssIngressVlanTpid_0Register_HHD.u0.bits_0.mssIngressVlanStag - - Default = 0x0000 - - STag TPID - - - Notes: - Service Tag Protocol Identifier (TPID) values to identify a VLAN tag. The " See SEC Egress VLAN CP Tag Parse STag " bit must be set to 1 for the incoming packet's TPID to be parsed. */ - unsigned int mssIngressVlanStag : 16; /* 1E.8006.F:0 R/W Default = 0x0000 */ - /* STag TPID - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Ingress VLAN TPID 0 Register */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssIngressVlanTpid_0Register_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress VLAN TPID 1 Register: 1E.8008 */ -/* MSS Ingress VLAN TPID 1 Register: 1E.8008 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress VLAN TPID 1 Register */ - union - { - struct - { - /*! \brief 1E.8008.F:0 R/W MSS Ingress VLAN QTag [F:0] - AQ_MssIngressVlanTpid_1Register_HHD.u0.bits_0.mssIngressVlanQtag - - Default = 0x0000 - - QTag TPID - - - Notes: - Customer Tag Protocol Identifier (TPID) values to identify a VLAN tag. The " See SEC Egress VLAN CP Tag Parse QTag " bit must be set to 1 for the incoming packet's TPID to be parsed. */ - unsigned int mssIngressVlanQtag : 16; /* 1E.8008.F:0 R/W Default = 0x0000 */ - /* QTag TPID - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Ingress VLAN TPID 1 Register */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssIngressVlanTpid_1Register_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress VLAN Control Register: 1E.800A */ -/* MSS Ingress VLAN Control Register: 1E.800A */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress VLAN Control Register */ - union - { - struct - { - /*! \brief 1E.800A.F:0 R/W MSS Ingress VLAN UP Map Table LSW [F:0] - AQ_MssIngressVlanControlRegister_HHD.u0.bits_0.mssIngressVlanUpMapTableLSW - - Default = 0x0000 - - Map table bits 15:0 - - - Notes: - If there is a customer TPID Tag match and no service TPID Tag match or the service TPID Tag match is disabled, the outer TAG's PCP is used to index into this map table to generate the packets user priority. - 2:0 : UP value for customer Tag PCP 0x0 - 5:3: UP value for customer Tag PCP 0x0 - 8:6 : UP value for customer Tag PCP 0x0 - 11:9 : UP value for customer Tag PCP 0x0 - 14:12 : UP value for customer Tag PCP 0x0 - 17:15 : UP value for customer Tag PCP 0x0 */ - unsigned int mssIngressVlanUpMapTableLSW : 16; /* 1E.800A.F:0 R/W Default = 0x0000 */ - /* Map table bits 15:0 - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Ingress VLAN Control Register */ - union - { - struct - { - /*! \brief 1E.800B.F R/W MSS Ingress VLAN QTag Parse Enable - AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanQtagParseEnable - - Default = 0x0 - - 1 = Enable VLAN QTag parsing - - - Notes: - Enable controlled port VLAN customer Tag parsing. When this bit is set to 1, the incoming packet's outer TPID will be compared with the configured " See MSS Ingress VLAN QTag [F:0] " for matching. If the " See SEC Egress VLAN CP Tag Parse QinQ " bit is set to1, this will also be used to compare the incoming packet's inner TPID. */ - unsigned int mssIngressVlanQtagParseEnable : 1; /* 1E.800B.F R/W Default = 0x0 */ - /* 1 = Enable VLAN QTag parsing - */ - /*! \brief 1E.800B.E R/W MSS Ingress VLAN STag Parse Enable - AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanStagParseEnable - - Default = 0x0 - - 1 = Enable VLAN STag parsing - - - Notes: - Enable controlled port VLAN service Tag parsing. When this bit is set to 1, the incoming packets outer TPID will be compared with the configured " See MSS Ingress VLAN Stag [F:0] " for matching. If the " See SEC Egress VLAN CP Tag Parse QinQ " bit is set to1, this will also be used to compare the incoming packet's inner TPID. */ - unsigned int mssIngressVlanStagParseEnable : 1; /* 1E.800B.E R/W Default = 0x0 */ - /* 1 = Enable VLAN STag parsing - */ - /*! \brief 1E.800B.D R/W MSS Ingress VLAN QinQ Parse Enable - AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanQinqParseEnable - - Default = 0x0 - - VLAN CP Tag Parse QinQ - - - Notes: - Enable controlled port VLAN QinQ Tag parsing. When this bit is set to 1 both the outer and inner VLAN Tags will be parsed. */ - unsigned int mssIngressVlanQinqParseEnable : 1; /* 1E.800B.D R/W Default = 0x0 */ - /* VLAN CP Tag Parse QinQ - */ - /*! \brief 1E.800B.C R/W MSS Ingress VLAN QTag UP Parse Enable - AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanQtagUpParseEnable - - Default = 0x0 - - VLAN CP Tag QTag UP enable - - - Notes: - Enable controlled port customer VLAN customer Tag user priority field parsing. */ - unsigned int mssIngressVlanQtagUpParseEnable : 1; /* 1E.800B.C R/W Default = 0x0 */ - /* VLAN CP Tag QTag UP enable - */ - /*! \brief 1E.800B.B R/W MSS Ingress VLAN STag UP Parse Enable - AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanStagUpParseEnable - - Default = 0x0 - - VLAN CP Tag STag UP enable - - - Notes: - Enable controlled port service VLAN service Tag user priority field parsing. */ - unsigned int mssIngressVlanStagUpParseEnable : 1; /* 1E.800B.B R/W Default = 0x0 */ - /* VLAN CP Tag STag UP enable - */ - /*! \brief 1E.800B.A:8 R/W MSS Ingress VLAN UP Default [2:0] - AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanUpDefault - - Default = 0x0 - - UP default - - - Notes: - User priority default */ - unsigned int mssIngressVlanUpDefault : 3; /* 1E.800B.A:8 R/W Default = 0x0 */ - /* UP default - */ - /*! \brief 1E.800B.7:0 R/W MSS Ingress VLAN UP Map Table MSW [17:10] - AQ_MssIngressVlanControlRegister_HHD.u1.bits_1.mssIngressVlanUpMapTableMSW - - Default = 0x00 - - UP Map table bits 23:16 - - - Notes: - If there is a customer TPID Tag match and no service TPID Tag match or the service TPID Tag match is disabled, the outer TAG's PCP is used to index into this map table to generate the packets user priority. - 2:0 : UP value for customer Tag PCP 0x0 - 5:3: UP value for customer Tag PCP 0x0 - 8:6 : UP value for customer Tag PCP 0x0 - 11:9 : UP value for customer Tag PCP 0x0 - 14:12 : UP value for customer Tag PCP 0x0 - 17:15 : UP value for customer Tag PCP 0x0 - 20:18 : UP value for customer Tag PCP 0x0 - 23:21 : UP value for customer Tag PCP 0x0 */ - unsigned int mssIngressVlanUpMapTableMSW : 8; /* 1E.800B.7:0 R/W Default = 0x00 */ - /* UP Map table bits 23:16 - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssIngressVlanControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress MTU Size Control Register: 1E.800C */ -/* MSS Ingress MTU Size Control Register: 1E.800C */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress MTU Size Control Register */ - union - { - struct - { - /*! \brief 1E.800C.F:0 R/W MSS Ingress Controlled Packet MTU Size [F:0] - AQ_MssIngressMtuSizeControlRegister_HHD.u0.bits_0.mssIngressControlledPacketMtuSize - - Default = 0x05DC - - Maximum transmission unit for controlled packet - - - Notes: - Maximum transmission unit of controlled packet */ - unsigned int mssIngressControlledPacketMtuSize : 16; /* 1E.800C.F:0 R/W Default = 0x05DC */ - /* Maximum transmission unit for controlled packet - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Ingress MTU Size Control Register */ - union - { - struct - { - /*! \brief 1E.800D.F:0 R/W MSS Ingress Uncontrolled Packet MTU Size [F:0] - AQ_MssIngressMtuSizeControlRegister_HHD.u1.bits_1.mssIngressUncontrolledPacketMtuSize - - Default = 0x05DC - - Maximum transmission unit for uncontrolled packet - - - Notes: - Maximum transmission unit of uncontrolled packet */ - unsigned int mssIngressUncontrolledPacketMtuSize : 16; /* 1E.800D.F:0 R/W Default = 0x05DC */ - /* Maximum transmission unit for uncontrolled packet - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssIngressMtuSizeControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress Control Register: 1E.800E */ -/* MSS Ingress Control Register: 1E.800E */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress Control Register */ - union - { - struct - { - unsigned int reserved0 : 2; - /*! \brief 1E.800E.D R/W MSS Ingress ICV LSB 8 Bytes Enable - AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressIcvLsb_8BytesEnable - - Default = 0x0 - - 1 = Use LSB - 0 = Use MSB - - - - Notes: - This bit selects MSB or LSB 8 bytes selection in the case where the ICV is 8 bytes. - 0 = MSB is used. */ - unsigned int mssIngressIcvLsb_8BytesEnable : 1; /* 1E.800E.D R/W Default = 0x0 */ - /* 1 = Use LSB - 0 = Use MSB - - */ - /*! \brief 1E.800E.C:B R/W MSS Ingress Global Validate Frames [1:0] - AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressGlobalValidateFrames - - Default = 0x0 - - Default validate frames configuration - - - Notes: - If the SC is invalid or if an IGPRC miss packet condition occurs, this default will be used for the validate frames configuration instead of the validate frame entry in the Ingress SC Table (IGSCT). */ - unsigned int mssIngressGlobalValidateFrames : 2; /* 1E.800E.C:B R/W Default = 0x0 */ - /* Default validate frames configuration - */ - /*! \brief 1E.800E.A R/W MSS Ingress Remove SECTag - AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressRemoveSectag - - Default = 0x0 - - 1 = Enable removal of SECTag - - - Notes: - If this bit is set and either of the following two conditions occurs, the SECTag will be removed. - Controlled packet and either the SA or SC is invalid. - IGPRC miss. */ - unsigned int mssIngressRemoveSectag : 1; /* 1E.800E.A R/W Default = 0x0 */ - /* 1 = Enable removal of SECTag - */ - /*! \brief 1E.800E.9 R/W MSS Ingress High Priority - AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressHighPriority - - Default = 0x0 - - 1 = MIB counter clear on read enable - - - Notes: - If this bit is set to 1, read is given high priority and the MIB count value becomes 0 after read. */ - unsigned int mssIngressHighPriority : 1; /* 1E.800E.9 R/W Default = 0x0 */ - /* 1 = MIB counter clear on read enable - */ - /*! \brief 1E.800E.8 R/W MSS Ingress Clear Count - AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressClearCount - - Default = 0x0 - - 1 = Clear all MIB counters - - - Notes: - If this bit is set to 1, all MIB counters will be cleared. */ - unsigned int mssIngressClearCount : 1; /* 1E.800E.8 R/W Default = 0x0 */ - /* 1 = Clear all MIB counters - */ - /*! \brief 1E.800E.7 R/W MSS Ingress Clear Global Time - AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressClearGlobalTime - - Default = 0x0 - - 1 = Clear global time - - - Notes: - Clear global time */ - unsigned int mssIngressClearGlobalTime : 1; /* 1E.800E.7 R/W Default = 0x0 */ - /* 1 = Clear global time - */ - /*! \brief 1E.800E.6 R/W MSS Ingress Check ICV - AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressCheckIcv - - Default = 0x0 - - Unused - - - Notes: - Unused */ - unsigned int mssIngressCheckIcv : 1; /* 1E.800E.6 R/W Default = 0x0 */ - /* Unused - */ - /*! \brief 1E.800E.5 R/W MSS Ingress Drop IGPRC Miss - AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressDropIgprcMiss - - Default = 0x0 - - 1 = Drop IGPRC miss packets - - - Notes: - Decides whether Ingress Pre-Security Classification (IGPRC) LUT miss packets are to be dropped */ - unsigned int mssIngressDropIgprcMiss : 1; /* 1E.800E.5 R/W Default = 0x0 */ - /* 1 = Drop IGPRC miss packets - */ - /*! \brief 1E.800E.4 R/W MSS Ingress Drop Kay Packet - AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressDropKayPacket - - Default = 0x0 - - 1 = Drop KaY packets - - - Notes: - Decides whether KaY packets have to be dropped */ - unsigned int mssIngressDropKayPacket : 1; /* 1E.800E.4 R/W Default = 0x0 */ - /* 1 = Drop KaY packets - */ - /*! \brief 1E.800E.3 R/W MSS Ingress Mask Short Length Error - AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressMaskShortLengthError - - Default = 0x0 - - Unused - - - Notes: - Unused */ - unsigned int mssIngressMaskShortLengthError : 1; /* 1E.800E.3 R/W Default = 0x0 */ - /* Unused - */ - /*! \brief 1E.800E.2 R/W MSS Ingress Create SCI - AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressCreateSci - - Default = 0x0 - - 0 = SCI from IGPRC LUT - - - Notes: - If the SCI is not in the packet and this bit is set to 0, the SCI will be taken from the IGPRC LUT. */ - unsigned int mssIngressCreateSci : 1; /* 1E.800E.2 R/W Default = 0x0 */ - /* 0 = SCI from IGPRC LUT - */ - /*! \brief 1E.800E.1 R/W MSS Ingress Operation Point To Point - AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressOperationPointToPoint - - Default = 0x0 - - 1 = Enable the SCI for authorization default - - - Notes: - The default SCI for authorization is configured in See MSS Ingress SCI Default [F:0] See MSS Ingress SCI Default [1F:10] , See MSS Ingress SCI Default [2F:20] , and See MSS Ingress SCI Default [3F:30] . */ - unsigned int mssIngressOperationPointToPoint : 1; /* 1E.800E.1 R/W Default = 0x0 */ - /* 1 = Enable the SCI for authorization default - */ - /*! \brief 1E.800E.0 R/W MSS Ingress Soft Reset - AQ_MssIngressControlRegister_HHD.u0.bits_0.mssIngressSoftReset - - Default = 0x0 - - 1 = Soft reset - - - Notes: - S/W reset */ - unsigned int mssIngressSoftReset : 1; /* 1E.800E.0 R/W Default = 0x0 */ - /* 1 = Soft reset - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Ingress Control Register */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssIngressControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress SA Control Register: 1E.8010 */ -/* MSS Ingress SA Control Register: 1E.8010 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress SA Control Register */ - union - { - struct - { - /*! \brief 1E.8010.F:0 R/W MSS Ingress SA Threshold LSW [F:0] - AQ_MssIngressSaControlRegister_HHD.u0.bits_0.mssIngressSaThresholdLSW - - Default = 0x0000 - - SA threshold bits 15:0 - - - Notes: - Ingress PN threshold to generate SA threshold interrupt. */ - unsigned int mssIngressSaThresholdLSW : 16; /* 1E.8010.F:0 R/W Default = 0x0000 */ - /* SA threshold bits 15:0 - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Ingress SA Control Register */ - union - { - struct - { - /*! \brief 1E.8011.F:0 R/W MSS Ingress SA Threshold MSW [1F:10] - AQ_MssIngressSaControlRegister_HHD.u1.bits_1.mssIngressSaThresholdMSW - - Default = 0x0000 - - SA threshold bits 31:16 - - - Notes: - Ingress PN threshold to generate SA threshold interrupt. */ - unsigned int mssIngressSaThresholdMSW : 16; /* 1E.8011.F:0 R/W Default = 0x0000 */ - /* SA threshold bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssIngressSaControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress Interrupt Status Register: 1E.802E */ -/* MSS Ingress Interrupt Status Register: 1E.802E */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress Interrupt Status Register */ - union - { - struct - { - unsigned int reserved0 : 7; - /*! \brief 1E.802E.8 COW MSS Ingress IGPOC Miss Interrupt - AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressIgpocMissInterrupt - - Default = 0x0 - - 1 = Interrupt - - */ - unsigned int mssIngressIgpocMissInterrupt : 1; /* 1E.802E.8 COW Default = 0x0 */ - /* 1 = Interrupt - */ - /*! \brief 1E.802E.7 COW MSS Ingress TCI E/C Error Interrupt - AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressTciE_cErrorInterrupt - - Default = 0x0 - - 1 = Interrupt - - - Notes: - Write to 1 to clear. This error occurs when the TCI E bit is 1 and the TCI C bit is 0. The packet is not dropped, uncontrolled, or untagged. */ - unsigned int mssIngressTciE_cErrorInterrupt : 1; /* 1E.802E.7 COW Default = 0x0 */ - /* 1 = Interrupt - */ - /*! \brief 1E.802E.6 COW MSS Ingress ECC Error Interrupt - AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressEccErrorInterrupt - - Default = 0x0 - - 1 = Interrupt - - - Notes: - Write to 1 to clear. */ - unsigned int mssIngressEccErrorInterrupt : 1; /* 1E.802E.6 COW Default = 0x0 */ - /* 1 = Interrupt - */ - /*! \brief 1E.802E.5 COW MSS Ingress MIB Saturation Interrupt - AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressMibSaturationInterrupt - - Default = 0x0 - - 1 = Interrupt - - - Notes: - Write to 1 to clear. This bit is set when the MIB counters reaches all ones saturation. */ - unsigned int mssIngressMibSaturationInterrupt : 1; /* 1E.802E.5 COW Default = 0x0 */ - /* 1 = Interrupt - */ - /*! \brief 1E.802E.4 COW MSS Ingress Replay Error Interrupt - AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressReplayErrorInterrupt - - Default = 0x0 - - 1 = Interrupt - - - Notes: - Write to 1 to clear. */ - unsigned int mssIngressReplayErrorInterrupt : 1; /* 1E.802E.4 COW Default = 0x0 */ - /* 1 = Interrupt - */ - /*! \brief 1E.802E.3 COW MSS Ingress ICV Error Interrupt - AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressIcvErrorInterrupt - - Default = 0x0 - - 1 = Interrupt - - - Notes: - Write to 1 to clear. */ - unsigned int mssIngressIcvErrorInterrupt : 1; /* 1E.802E.3 COW Default = 0x0 */ - /* 1 = Interrupt - */ - /*! \brief 1E.802E.2 COW MSS Ingress SA Threshold Expired Interrupt - AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressSaThresholdExpiredInterrupt - - Default = 0x0 - - 1 = Interrupt - - - Notes: - Write to 1 to clear. This bit is set when the SA PN reaches the See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . */ - unsigned int mssIngressSaThresholdExpiredInterrupt : 1; /* 1E.802E.2 COW Default = 0x0 */ - /* 1 = Interrupt - */ - /*! \brief 1E.802E.1 COW MSS Ingress SA Expired Interrupt - AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssIngressSaExpiredInterrupt - - Default = 0x0 - - 1 = Interrupt - - - Notes: - Write to 1 to clear. This bit is set when the SA PN reaches all ones saturation. */ - unsigned int mssIngressSaExpiredInterrupt : 1; /* 1E.802E.1 COW Default = 0x0 */ - /* 1 = Interrupt - */ - /*! \brief 1E.802E.0 COW MSS Master Ingress Interrupt - AQ_MssIngressInterruptStatusRegister_HHD.u0.bits_0.mssMasterIngressInterrupt - - Default = 0x0 - - 1 = Interrupt - - - Notes: - Write to 1 to clear. This bit is set when any one of the above interrupt and the corresponding interrupt enable are both set. The interrupt enable for this bit must also be set for this bit to be set. */ - unsigned int mssMasterIngressInterrupt : 1; /* 1E.802E.0 COW Default = 0x0 */ - /* 1 = Interrupt - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Ingress Interrupt Status Register */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssIngressInterruptStatusRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress Interrupt Mask Register: 1E.8030 */ -/* MSS Ingress Interrupt Mask Register: 1E.8030 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress Interrupt Mask Register */ - union - { - struct - { - unsigned int reserved0 : 7; - /*! \brief 1E.8030.8 R/W MSS Ingress IGPOC Miss Interrupt Enable - AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressIgpocMissInterruptEnable - - Default = 0x0 - - 1 = Interrupt enabled - - */ - unsigned int mssIngressIgpocMissInterruptEnable : 1; /* 1E.8030.8 R/W Default = 0x0 */ - /* 1 = Interrupt enabled - */ - /*! \brief 1E.8030.7 R/W MSS Ingress TCI E/C Error Interrupt Enable - AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressTciE_cErrorInterruptEnable - - Default = 0x0 - - 1 = Interrupt enabled - - */ - unsigned int mssIngressTciE_cErrorInterruptEnable : 1; /* 1E.8030.7 R/W Default = 0x0 */ - /* 1 = Interrupt enabled - */ - /*! \brief 1E.8030.6 R/W MSS Ingress ECC Error Interrupt Enable - AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressEccErrorInterruptEnable - - Default = 0x0 - - 1 = Interrupt enabled - - */ - unsigned int mssIngressEccErrorInterruptEnable : 1; /* 1E.8030.6 R/W Default = 0x0 */ - /* 1 = Interrupt enabled - */ - /*! \brief 1E.8030.5 R/W MSS Ingress MIB Saturation Interrupt Enable - AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressMibSaturationInterruptEnable - - Default = 0x0 - - 1 = Interrupt enabled - - */ - unsigned int mssIngressMibSaturationInterruptEnable : 1; /* 1E.8030.5 R/W Default = 0x0 */ - /* 1 = Interrupt enabled - */ - /*! \brief 1E.8030.4 R/W MSS Ingress Replay Error Interrupt Enable - AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressReplayErrorInterruptEnable - - Default = 0x0 - - 1 = Interrupt enabled - - */ - unsigned int mssIngressReplayErrorInterruptEnable : 1; /* 1E.8030.4 R/W Default = 0x0 */ - /* 1 = Interrupt enabled - */ - /*! \brief 1E.8030.3 R/W MSS Ingress ICV Error Interrupt Enable - AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressIcvErrorInterruptEnable - - Default = 0x0 - - 1 = Interrupt enabled - - */ - unsigned int mssIngressIcvErrorInterruptEnable : 1; /* 1E.8030.3 R/W Default = 0x0 */ - /* 1 = Interrupt enabled - */ - /*! \brief 1E.8030.2 R/W MSS Ingress SA Threshold Expired Interrupt Enable - AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressSaThresholdExpiredInterruptEnable - - Default = 0x0 - - 1 = Interrupt enabled - - */ - unsigned int mssIngressSaThresholdExpiredInterruptEnable : 1; /* 1E.8030.2 R/W Default = 0x0 */ - /* 1 = Interrupt enabled - */ - /*! \brief 1E.8030.1 R/W MSS Ingress SA Expired Interrupt Enable - AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressSaExpiredInterruptEnable - - Default = 0x0 - - 1 = Interrupt enabled - - */ - unsigned int mssIngressSaExpiredInterruptEnable : 1; /* 1E.8030.1 R/W Default = 0x0 */ - /* 1 = Interrupt enabled - */ - /*! \brief 1E.8030.0 R/W MSS Ingress Master Interrupt Enable - AQ_MssIngressInterruptMaskRegister_HHD.u0.bits_0.mssIngressMasterInterruptEnable - - Default = 0x0 - - 1 = Interrupt enabled - - */ - unsigned int mssIngressMasterInterruptEnable : 1; /* 1E.8030.0 R/W Default = 0x0 */ - /* 1 = Interrupt enabled - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Ingress Interrupt Mask Register */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssIngressInterruptMaskRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress SA ICV Error Status Register: 1E.8032 */ -/* MSS Ingress SA ICV Error Status Register: 1E.8032 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress SA ICV Error Status Register */ - union - { - struct - { - /*! \brief 1E.8032.F:0 COW MSS Ingress SA ICV Error LSW [F:0] - AQ_MssIngressSaIcvErrorStatusRegister_HHD.u0.bits_0.mssIngressSaIcvErrorLSW - - Default = 0x0000 - - SA ICV error bits 15:0 - - - Notes: - When set, these bits identify the SA that has an ICV error. Write these bits to 1 to clear. */ - unsigned int mssIngressSaIcvErrorLSW : 16; /* 1E.8032.F:0 COW Default = 0x0000 */ - /* SA ICV error bits 15:0 - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Ingress SA ICV Error Status Register */ - union - { - struct - { - /*! \brief 1E.8033.F:0 COW MSS Ingress SA ICV Error MSW [1F:10] - AQ_MssIngressSaIcvErrorStatusRegister_HHD.u1.bits_1.mssIngressSaIcvErrorMSW - - Default = 0x0000 - - SA ICV error bits 31:16 - - - Notes: - When set, these bits identify the SA that has an ICV error. Write these bits to 1 to clear. */ - unsigned int mssIngressSaIcvErrorMSW : 16; /* 1E.8033.F:0 COW Default = 0x0000 */ - /* SA ICV error bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssIngressSaIcvErrorStatusRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress SA Replay Error Status Register: 1E.8034 */ -/* MSS Ingress SA Replay Error Status Register: 1E.8034 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress SA Replay Error Status Register */ - union - { - struct - { - /*! \brief 1E.8034.F:0 COW MSS Ingress SA Replay Error LSW [F:0] - AQ_MssIngressSaReplayErrorStatusRegister_HHD.u0.bits_0.mssIngressSaReplayErrorLSW - - Default = 0x0000 - - SA replay error bits 15:0 - - - Notes: - When set, these bits identify the SA that has a replay error. Write these bits to 1 to clear. */ - unsigned int mssIngressSaReplayErrorLSW : 16; /* 1E.8034.F:0 COW Default = 0x0000 */ - /* SA replay error bits 15:0 - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Ingress SA Replay Error Status Register */ - union - { - struct - { - /*! \brief 1E.8035.F:0 COW MSS Ingress SA Replay Error MSW [1F:10] - AQ_MssIngressSaReplayErrorStatusRegister_HHD.u1.bits_1.mssIngressSaReplayErrorMSW - - Default = 0x0000 - - SA replay error bits 31:16 - - - Notes: - When set, these bits identify the SA that has a replay error. Write these bits to 1 to clear. */ - unsigned int mssIngressSaReplayErrorMSW : 16; /* 1E.8035.F:0 COW Default = 0x0000 */ - /* SA replay error bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssIngressSaReplayErrorStatusRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress SA Expired Status Register: 1E.8036 */ -/* MSS Ingress SA Expired Status Register: 1E.8036 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress SA Expired Status Register */ - union - { - struct - { - /*! \brief 1E.8036.F:0 ROS MSS Ingress SA Expired LSW [F:0] - AQ_MssIngressSaExpiredStatusRegister_HHD.u0.bits_0.mssIngressSaExpiredLSW - - Default = 0x0000 - - SA expired bits 15:0 - - - Notes: - When set, these bits identify the SA that has expired when the SA PN reaches all-ones saturation. Write these bits to 1 to clear. */ - unsigned int mssIngressSaExpiredLSW : 16; /* 1E.8036.F:0 ROS Default = 0x0000 */ - /* SA expired bits 15:0 - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Ingress SA Expired Status Register */ - union - { - struct - { - /*! \brief 1E.8037.F:0 ROS MSS Ingress SA Expired MSW [1F:10] - AQ_MssIngressSaExpiredStatusRegister_HHD.u1.bits_1.mssIngressSaExpiredMSW - - Default = 0x0000 - - SA expired bits 31:16 - - - Notes: - When set, these bits identify the SA that has expired when the SA PN reaches all-ones saturation. Write these bits to 1 to clear. */ - unsigned int mssIngressSaExpiredMSW : 16; /* 1E.8037.F:0 ROS Default = 0x0000 */ - /* SA expired bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssIngressSaExpiredStatusRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress SA Threshold Expired Status Register: 1E.8038 */ -/* MSS Ingress SA Threshold Expired Status Register: 1E.8038 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress SA Threshold Expired Status Register */ - union - { - struct - { - /*! \brief 1E.8038.F:0 ROS MSS Ingress SA Threshold Expired LSW [F:0] - AQ_MssIngressSaThresholdExpiredStatusRegister_HHD.u0.bits_0.mssIngressSaThresholdExpiredLSW - - Default = 0x0000 - - SA threshold expired bits 15:0 - - - Notes: - When set, these bits identify the SA that has expired when the SA PN has reached the configured threshold See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . Write these bits to 1 to clear. */ - unsigned int mssIngressSaThresholdExpiredLSW : 16; /* 1E.8038.F:0 ROS Default = 0x0000 */ - /* SA threshold expired bits 15:0 - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Ingress SA Threshold Expired Status Register */ - union - { - struct - { - /*! \brief 1E.8039.F:0 ROS MSS Ingress SA Threshold Expired MSW [1F:10] - AQ_MssIngressSaThresholdExpiredStatusRegister_HHD.u1.bits_1.mssIngressSaThresholdExpiredMSW - - Default = 0x0000 - - SA threshold expired bits 31:16 - - - Notes: - When set, these bits identify the SA that has expired when the SA PN has reached the configured threshold See SEC Egress PN Threshold [F:0] and See SEC Egress PN Threshold [1F:10] . Write these bits to 1 to clear. */ - unsigned int mssIngressSaThresholdExpiredMSW : 16; /* 1E.8039.F:0 ROS Default = 0x0000 */ - /* SA threshold expired bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssIngressSaThresholdExpiredStatusRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress ECC Interrupt Status Register: 1E.803A */ -/* MSS Ingress ECC Interrupt Status Register: 1E.803A */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress ECC Interrupt Status Register */ - union - { - struct - { - /*! \brief 1E.803A.F:0 R/W MSS Ingress SA ECC Error Interrupt LSW [F:0] - AQ_MssIngressEccInterruptStatusRegister_HHD.u0.bits_0.mssIngressSaEccErrorInterruptLSW - - Default = 0x0000 - - SA ECC error interrupt bits 15:0 - - - Notes: - When set to 1, indicates that an ECC error occured for the SA. */ - unsigned int mssIngressSaEccErrorInterruptLSW : 16; /* 1E.803A.F:0 R/W Default = 0x0000 */ - /* SA ECC error interrupt bits 15:0 - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Ingress ECC Interrupt Status Register */ - union - { - struct - { - /*! \brief 1E.803B.F:0 R/W MSS Ingress SA ECC Error Interrupt MSW [1F:10] - AQ_MssIngressEccInterruptStatusRegister_HHD.u1.bits_1.mssIngressSaEccErrorInterruptMSW - - Default = 0x0000 - - SA ECC error interrupt bits 31:16 - - - Notes: - When set to 1, indicates that an ECC error occured for the SA. */ - unsigned int mssIngressSaEccErrorInterruptMSW : 16; /* 1E.803B.F:0 R/W Default = 0x0000 */ - /* SA ECC error interrupt bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MssIngressEccInterruptStatusRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress LUT Address Control Register: 1E.8080 */ -/* MSS Ingress LUT Address Control Register: 1E.8080 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress LUT Address Control Register */ - union - { - struct - { - /*! \brief 1E.8080.F:C R/W MSS Ingress LUT Select [3:0] - AQ_MssIngressLutAddressControlRegister_HHD.u0.bits_0.mssIngressLutSelect - - Default = 0x0 - - LUT select - - - Notes: - 0x0 : Ingress Pre-Security MAC Control FIlter (IGPRCTLF) LUT - 0x1 : Ingress Pre-Security Classification LUT (IGPRC) - 0x2 : Ingress Packet Format (IGPFMT) SAKey LUT - 0x3 : Ingress Packet Format (IGPFMT) SC/SA LUT - 0x4 : Ingress Post-Security Classification LUT (IGPOC) - 0x5 : Ingress Post-Security MAC Control Filter (IGPOCTLF) LUT - 0x6 : Ingress MIB (IGMIB) */ - unsigned int mssIngressLutSelect : 4; /* 1E.8080.F:C R/W Default = 0x0 */ - /* LUT select - */ - unsigned int reserved0 : 3; - /*! \brief 1E.8080.8:0 R/W MSS Ingress LUT Address [8:0] - AQ_MssIngressLutAddressControlRegister_HHD.u0.bits_0.mssIngressLutAddress - - Default = 0x000 - - LUT address - - */ - unsigned int mssIngressLutAddress : 9; /* 1E.8080.8:0 R/W Default = 0x000 */ - /* LUT address - */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_MssIngressLutAddressControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress LUT Control Register: 1E.8081 */ -/* MSS Ingress LUT Control Register: 1E.8081 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress LUT Control Register */ - union - { - struct - { - /*! \brief 1E.8081.F R/W MSS Ingress LUT Write - AQ_MssIngressLutControlRegister_HHD.u0.bits_0.mssIngressLutWrite - - Default = 0x0 - - 1 = LUT write - - - Notes: - Setting this bit to 1, will write the LUT. This bit will automatically clear to 0. */ - unsigned int mssIngressLutWrite : 1; /* 1E.8081.F R/W Default = 0x0 */ - /* 1 = LUT write - */ - /*! \brief 1E.8081.E R/W MSS Ingress LUT Read - AQ_MssIngressLutControlRegister_HHD.u0.bits_0.mssIngressLutRead - - Default = 0x0 - - 1 = LUT read - - - Notes: - Setting this bit to 1, will read the LUT. This bit will automatically clear to 0. */ - unsigned int mssIngressLutRead : 1; /* 1E.8081.E R/W Default = 0x0 */ - /* 1 = LUT read - */ - unsigned int reserved0 : 14; - } bits_0; - uint16_t word_0; - } u0; -} AQ_MssIngressLutControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSS Ingress LUT Data Control Register: 1E.80A0 */ -/* MSS Ingress LUT Data Control Register: 1E.80A0 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80A0.F:0 R/W MSS Ingress LUT Data 0 [F:0] - AQ_MssIngressLutDataControlRegister_HHD.u0.bits_0.mssIngressLutData_0 - - Default = 0x0000 - - LUT data bits 15:0 - - */ - unsigned int mssIngressLutData_0 : 16; /* 1E.80A0.F:0 R/W Default = 0x0000 */ - /* LUT data bits 15:0 - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80A1.F:0 R/W MSS Ingress LUT Data 1 [1F:10] - AQ_MssIngressLutDataControlRegister_HHD.u1.bits_1.mssIngressLutData_1 - - Default = 0x0000 - - LUT data bits 31:16 - - */ - unsigned int mssIngressLutData_1 : 16; /* 1E.80A1.F:0 R/W Default = 0x0000 */ - /* LUT data bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80A2.F:0 R/W MSS Ingress LUT Data 2 [2F:20] - AQ_MssIngressLutDataControlRegister_HHD.u2.bits_2.mssIngressLutData_2 - - Default = 0x0000 - - LUT data bits 47:32 - - */ - unsigned int mssIngressLutData_2 : 16; /* 1E.80A2.F:0 R/W Default = 0x0000 */ - /* LUT data bits 47:32 - */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80A3.F:0 R/W MSS Ingress LUT Data 3 [3F:30] - AQ_MssIngressLutDataControlRegister_HHD.u3.bits_3.mssIngressLutData_3 - - Default = 0x0000 - - LUT data bits 63:48 - - */ - unsigned int mssIngressLutData_3 : 16; /* 1E.80A3.F:0 R/W Default = 0x0000 */ - /* LUT data bits 63:48 - */ - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80A4.F:0 R/W MSS Ingress LUT Data 4 [4F:40] - AQ_MssIngressLutDataControlRegister_HHD.u4.bits_4.mssIngressLutData_4 - - Default = 0x0000 - - LUT data bits 79:64 - - */ - unsigned int mssIngressLutData_4 : 16; /* 1E.80A4.F:0 R/W Default = 0x0000 */ - /* LUT data bits 79:64 - */ - } bits_4; - uint16_t word_4; - } u4; - /*! \brief Union for bit and word level access of word 5 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80A5.F:0 R/W MSS Ingress LUT Data 5 [5F:50] - AQ_MssIngressLutDataControlRegister_HHD.u5.bits_5.mssIngressLutData_5 - - Default = 0x0000 - - LUT data bits 95:80 - - */ - unsigned int mssIngressLutData_5 : 16; /* 1E.80A5.F:0 R/W Default = 0x0000 */ - /* LUT data bits 95:80 - */ - } bits_5; - uint16_t word_5; - } u5; - /*! \brief Union for bit and word level access of word 6 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80A6.F:0 R/W MSS Ingress LUT Data 6 [6F:60] - AQ_MssIngressLutDataControlRegister_HHD.u6.bits_6.mssIngressLutData_6 - - Default = 0x0000 - - LUT data bits 111:96 - - */ - unsigned int mssIngressLutData_6 : 16; /* 1E.80A6.F:0 R/W Default = 0x0000 */ - /* LUT data bits 111:96 - */ - } bits_6; - uint16_t word_6; - } u6; - /*! \brief Union for bit and word level access of word 7 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80A7.F:0 R/W MSS Ingress LUT Data 7 [7F:70] - AQ_MssIngressLutDataControlRegister_HHD.u7.bits_7.mssIngressLutData_7 - - Default = 0x0000 - - LUT data bits 127:112 - - */ - unsigned int mssIngressLutData_7 : 16; /* 1E.80A7.F:0 R/W Default = 0x0000 */ - /* LUT data bits 127:112 - */ - } bits_7; - uint16_t word_7; - } u7; - /*! \brief Union for bit and word level access of word 8 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80A8.F:0 R/W MSS Ingress LUT Data 8 [8F:80] - AQ_MssIngressLutDataControlRegister_HHD.u8.bits_8.mssIngressLutData_8 - - Default = 0x0000 - - LUT data bits 143:128 - - */ - unsigned int mssIngressLutData_8 : 16; /* 1E.80A8.F:0 R/W Default = 0x0000 */ - /* LUT data bits 143:128 - */ - } bits_8; - uint16_t word_8; - } u8; - /*! \brief Union for bit and word level access of word 9 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80A9.F:0 R/W MSS Ingress LUT Data 9 [9F:90] - AQ_MssIngressLutDataControlRegister_HHD.u9.bits_9.mssIngressLutData_9 - - Default = 0x0000 - - LUT data bits 159:144 - - */ - unsigned int mssIngressLutData_9 : 16; /* 1E.80A9.F:0 R/W Default = 0x0000 */ - /* LUT data bits 159:144 - */ - } bits_9; - uint16_t word_9; - } u9; - /*! \brief Union for bit and word level access of word 10 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80AA.F:0 R/W MSS Ingress LUT Data 10 [AF:A0] - AQ_MssIngressLutDataControlRegister_HHD.u10.bits_10.mssIngressLutData_10 - - Default = 0x0000 - - LUT data bits 175:160 - - */ - unsigned int mssIngressLutData_10 : 16; /* 1E.80AA.F:0 R/W Default = 0x0000 */ - /* LUT data bits 175:160 - */ - } bits_10; - uint16_t word_10; - } u10; - /*! \brief Union for bit and word level access of word 11 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80AB.F:0 R/W MSS Ingress LUT Data 11 [BF:B0] - AQ_MssIngressLutDataControlRegister_HHD.u11.bits_11.mssIngressLutData_11 - - Default = 0x0000 - - LUT data bits 191:176 - - */ - unsigned int mssIngressLutData_11 : 16; /* 1E.80AB.F:0 R/W Default = 0x0000 */ - /* LUT data bits 191:176 - */ - } bits_11; - uint16_t word_11; - } u11; - /*! \brief Union for bit and word level access of word 12 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80AC.F:0 R/W MSS Ingress LUT Data 12 [CF:C0] - AQ_MssIngressLutDataControlRegister_HHD.u12.bits_12.mssIngressLutData_12 - - Default = 0x0000 - - LUT data bits 207:192 - - */ - unsigned int mssIngressLutData_12 : 16; /* 1E.80AC.F:0 R/W Default = 0x0000 */ - /* LUT data bits 207:192 - */ - } bits_12; - uint16_t word_12; - } u12; - /*! \brief Union for bit and word level access of word 13 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80AD.F:0 R/W MSS Ingress LUT Data 13 [DF:D0] - AQ_MssIngressLutDataControlRegister_HHD.u13.bits_13.mssIngressLutData_13 - - Default = 0x0000 - - LUT data bits 223:208 - - */ - unsigned int mssIngressLutData_13 : 16; /* 1E.80AD.F:0 R/W Default = 0x0000 */ - /* LUT data bits 223:208 - */ - } bits_13; - uint16_t word_13; - } u13; - /*! \brief Union for bit and word level access of word 14 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80AE.F:0 R/W MSS Ingress LUT Data 14 [EF:E0] - AQ_MssIngressLutDataControlRegister_HHD.u14.bits_14.mssIngressLutData_14 - - Default = 0x0000 - - LUT data bits 239:224 - - */ - unsigned int mssIngressLutData_14 : 16; /* 1E.80AE.F:0 R/W Default = 0x0000 */ - /* LUT data bits 239:224 - */ - } bits_14; - uint16_t word_14; - } u14; - /*! \brief Union for bit and word level access of word 15 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80AF.F:0 R/W MSS Ingress LUT Data 15 [FF:F0] - AQ_MssIngressLutDataControlRegister_HHD.u15.bits_15.mssIngressLutData_15 - - Default = 0x0000 - - LUT data bits 255:240 - - */ - unsigned int mssIngressLutData_15 : 16; /* 1E.80AF.F:0 R/W Default = 0x0000 */ - /* LUT data bits 255:240 - */ - } bits_15; - uint16_t word_15; - } u15; - /*! \brief Union for bit and word level access of word 16 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80B0.F:0 R/W MSS Ingress LUT Data 16 [10F:100] - AQ_MssIngressLutDataControlRegister_HHD.u16.bits_16.mssIngressLutData_16 - - Default = 0x0000 - - LUT data bits 271:256 - - */ - unsigned int mssIngressLutData_16 : 16; /* 1E.80B0.F:0 R/W Default = 0x0000 */ - /* LUT data bits 271:256 - */ - } bits_16; - uint16_t word_16; - } u16; - /*! \brief Union for bit and word level access of word 17 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80B1.F:0 R/W MSS Ingress LUT Data 17 [11F:110] - AQ_MssIngressLutDataControlRegister_HHD.u17.bits_17.mssIngressLutData_17 - - Default = 0x0000 - - LUT data bits 287:272 - - */ - unsigned int mssIngressLutData_17 : 16; /* 1E.80B1.F:0 R/W Default = 0x0000 */ - /* LUT data bits 287:272 - */ - } bits_17; - uint16_t word_17; - } u17; - /*! \brief Union for bit and word level access of word 18 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80B2.F:0 R/W MSS Ingress LUT Data 18 [12F:120] - AQ_MssIngressLutDataControlRegister_HHD.u18.bits_18.mssIngressLutData_18 - - Default = 0x0000 - - LUT data bits 303:288 - - */ - unsigned int mssIngressLutData_18 : 16; /* 1E.80B2.F:0 R/W Default = 0x0000 */ - /* LUT data bits 303:288 - */ - } bits_18; - uint16_t word_18; - } u18; - /*! \brief Union for bit and word level access of word 19 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80B3.F:0 R/W MSS Ingress LUT Data 19 [13F:130] - AQ_MssIngressLutDataControlRegister_HHD.u19.bits_19.mssIngressLutData_19 - - Default = 0x0000 - - LUT data bits 319:304 - - */ - unsigned int mssIngressLutData_19 : 16; /* 1E.80B3.F:0 R/W Default = 0x0000 */ - /* LUT data bits 319:304 - */ - } bits_19; - uint16_t word_19; - } u19; - /*! \brief Union for bit and word level access of word 20 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80B4.F:0 R/W MSS Ingress LUT Data 20 [14F:140] - AQ_MssIngressLutDataControlRegister_HHD.u20.bits_20.mssIngressLutData_20 - - Default = 0x0000 - - LUT data bits 335:320 - - */ - unsigned int mssIngressLutData_20 : 16; /* 1E.80B4.F:0 R/W Default = 0x0000 */ - /* LUT data bits 335:320 - */ - } bits_20; - uint16_t word_20; - } u20; - /*! \brief Union for bit and word level access of word 21 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80B5.F:0 R/W MSS Ingress LUT Data 21 [15F:150] - AQ_MssIngressLutDataControlRegister_HHD.u21.bits_21.mssIngressLutData_21 - - Default = 0x0000 - - LUT data bits 351:336 - - */ - unsigned int mssIngressLutData_21 : 16; /* 1E.80B5.F:0 R/W Default = 0x0000 */ - /* LUT data bits 351:336 - */ - } bits_21; - uint16_t word_21; - } u21; - /*! \brief Union for bit and word level access of word 22 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80B6.F:0 R/W MSS Ingress LUT Data 22 [16F:160] - AQ_MssIngressLutDataControlRegister_HHD.u22.bits_22.mssIngressLutData_22 - - Default = 0x0000 - - LUT data bits 367:352 - - */ - unsigned int mssIngressLutData_22 : 16; /* 1E.80B6.F:0 R/W Default = 0x0000 */ - /* LUT data bits 367:352 - */ - } bits_22; - uint16_t word_22; - } u22; - /*! \brief Union for bit and word level access of word 23 of MSS Ingress LUT Data Control Register */ - union - { - struct - { - /*! \brief 1E.80B7.F:0 R/W MSS Ingress LUT Data 23 [17F:170] - AQ_MssIngressLutDataControlRegister_HHD.u23.bits_23.mssIngressLutData_23 - - Default = 0x0000 - - LUT data bits 383:368 - - */ - unsigned int mssIngressLutData_23 : 16; /* 1E.80B7.F:0 R/W Default = 0x0000 */ - /* LUT data bits 383:368 - */ - } bits_23; - uint16_t word_23; - } u23; -} AQ_MssIngressLutDataControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line General Control Register: 1E.9004 */ -/* MSM Line General Control Register: 1E.9004 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line General Control Register */ - union - { - struct - { - /*! \brief 1E.9004.F R/W MSM Line PHY Tx Enable - AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLinePhyTxEnable - - Default = 0x0 - - 1 = Enable PHY Tx - - - Notes: - Directly controls the phy_tx_ena pin. */ - unsigned int msmLinePhyTxEnable : 1; /* 1E.9004.F R/W Default = 0x0 */ - /* 1 = Enable PHY Tx - */ - /*! \brief 1E.9004.E R/W MSM Line Rx Error Discard - AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineRxErrorDiscard - - Default = 0x0 - - 1 = Enable discard of received errored frames - - - Notes: - Rx errored frame discard enable. When set to 1, any frame received with an error is discarded and not forwarded to the client interface. When set to 0, errored frames are forwarded to the client interface with ff_rx_err asserted. - Note : It is recommended to set this bit to 1 only when store and forward operation is enabled (RX_SECTION_FULL TBD). */ - unsigned int msmLineRxErrorDiscard : 1; /* 1E.9004.E R/W Default = 0x0 */ - /* 1 = Enable discard of received errored frames - */ - /*! \brief 1E.9004.D R/W MSM Line Control Frame Enable - AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineControlFrameEnable - - Default = 0x0 - - 1 = Control frame enabled - - - Notes: - MAC control frame enable. When set to 1, the MAC control frames with any Opcode other than 0x0001 are accepted and forwarded to the client interface. When set to 0, MAC control frames with any opcode other than 0x0001 are silently discarded. */ - unsigned int msmLineControlFrameEnable : 1; /* 1E.9004.D R/W Default = 0x0 */ - /* 1 = Control frame enabled - */ - /*! \brief 1E.9004.C R/WSC MSM Line Soft Reset - AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineSoftReset - - Default = 0x0 - - 1 = Soft reset - - - Notes: - Software reset. Self clearing bit. When set to 1, resets all statistic counters as well as the Tx and Rx FIFOs. It should be issued after all traffic has been stopped as a result of clearing the Rx/Tx enable bits ( See MAC Rx Enable set to 0 and See MAC Tx Enable set to 0). - Note : Can lead to an Rx interface (ff_rx_xxx) violations to the application if the reset is issued in the middle of a receive frame transfer. Then the end of packet (assertion of ff_rx_eop) is lost and the application should be prepeared to handle this exception. */ - unsigned int msmLineSoftReset : 1; /* 1E.9004.C R/WSC Default = 0x0 */ - /* 1 = Soft reset - */ - /*! \brief 1E.9004.B R/W MSM Line Tx Pad Enable - AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineTxPadEnable - - Default = 0x1 - - 1 = Enable Tx padding - - - Notes: - When set to 1, enable padding of frames in the Tx direction. When set to 0, the MAC will not extend frames from the application to a minimum of 64 bytes, allowing to transmit short frames (violating the Ethernet mimimum size requirements). Must be set to 1 for normal operation. */ - unsigned int msmLineTxPadEnable : 1; /* 1E.9004.B R/W Default = 0x1 */ - /* 1 = Enable Tx padding - */ - /*! \brief 1E.9004.A R/W MSM Line Tx CRC Append - AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineTxCrcAppend - - Default = 0x0 - - 1 = Append Tx CRC - - - Notes: - Permanently enable CRC append on transmit. If set to 1, the Tx will append a CRC to all transmitted frames. If set to 0, CRC append can be controlled on a per frame basis using the pin ff_tx_crc. - This configuration bit is OR'ed with the external ff_tx_crc pin to instruct the Tx to append a CRC to transmitted frames. The ff_tx_crc pin is tied to 0. */ - unsigned int msmLineTxCrcAppend : 1; /* 1E.9004.A R/W Default = 0x0 */ - /* 1 = Append Tx CRC - */ - /*! \brief 1E.9004.9 R/W MSM Line Tx Address Insert Enable - AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineTxAddressInsertEnable - - Default = 0x0 - - 1 = Insert Tx MAC source address - - - Notes: - Set the source MAC address on transmit. If set to 1, the MAC overwrites the source MAC address with the MAC programmed address in all transmitted frames. When set to 0, the source MAC address is transmitted unmodified from the MAC Tx client application. */ - unsigned int msmLineTxAddressInsertEnable : 1; /* 1E.9004.9 R/W Default = 0x0 */ - /* 1 = Insert Tx MAC source address - */ - /*! \brief 1E.9004.8 R/W MSM Line Pause Ignore - AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLinePauseIgnore - - Default = 0x0 - - 1 = Ignore pause frames - - - Notes: - Ignore pause frame quanta. If set to 1, received pause frames are ignored by the MAC. When set to 0, the Tx is stopped for the amount of time specified in the pause quanta received within the pause frame. */ - unsigned int msmLinePauseIgnore : 1; /* 1E.9004.8 R/W Default = 0x0 */ - /* 1 = Ignore pause frames - */ - /*! \brief 1E.9004.7 R/W MSM Line Pause Forward - AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLinePauseForward - - Default = 0x0 - - 1 = Enable Pause forwarding - - - Notes: - Terminate or forward pause frames. If set to 1, pause frames are forwarded to the user application. In normal mode, when set to 0, pause frames are terminated and discarded within the MAC. */ - unsigned int msmLinePauseForward : 1; /* 1E.9004.7 R/W Default = 0x0 */ - /* 1 = Enable Pause forwarding - */ - /*! \brief 1E.9004.6 R/W MSM Line CRC Forward - AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineCrcForward - - Default = 0x0 - - 1 = Enable CRC forwarding - - - Notes: - When set to 1, the CRC field of the received frames is forwarded with the frame to the user application. If disabled, the CRC field is stripped from the frame. - Note : If padding is enabled ( See MAC PAD Enable set to 1), this bit is ignored. */ - unsigned int msmLineCrcForward : 1; /* 1E.9004.6 R/W Default = 0x0 */ - /* 1 = Enable CRC forwarding - */ - /*! \brief 1E.9004.5 R/W MSM Line PAD Enable - AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLinePadEnable - - Default = 0x0 - - 1 = Enable frame padding removal on Rx - - - Notes: - When set to 1, enable frame padding removal on the Rx path. If enabled, padding is removed before the frame is transferred to the MAC client application. If disabled, no padding is removed on the Rx by the MAC. - Note : On Tx, the MAC always adds padding as required. */ - unsigned int msmLinePadEnable : 1; /* 1E.9004.5 R/W Default = 0x0 */ - /* 1 = Enable frame padding removal on Rx - */ - /*! \brief 1E.9004.4 R/W MSM Line Promiscuous Mode - AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLinePromiscuousMode - - Default = 0x0 - - 1 = Promiscuous mode - - - Notes: - When set to 1, all frames are received without any MAC address filtering. */ - unsigned int msmLinePromiscuousMode : 1; /* 1E.9004.4 R/W Default = 0x0 */ - /* 1 = Promiscuous mode - */ - /*! \brief 1E.9004.3 R/W MSM Line WAN Mode - AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineWanMode - - Default = 0x0 - - 1 = WAN mode - 0 = LAN mode - - - Notes: - WAN mode enable. Sets WAN mode when set to 1 and LAN mode when set to 0. Note: When changing the mode, verifiy correct setting of the Tx IPG. */ - unsigned int msmLineWanMode : 1; /* 1E.9004.3 R/W Default = 0x0 */ - /* 1 = WAN mode - 0 = LAN mode - */ - unsigned int reserved0 : 1; - /*! \brief 1E.9004.1 R/W MSM Line Rx Enable - AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineRxEnable - - Default = 0x0 - - 1 = Rx enable - - Notes: - MAC Tx path enable. Should be set to 1 to enable the MAC Tx path. Should be set to 0 to disable the MAC Tx path. */ - unsigned int msmLineRxEnable : 1; /* 1E.9004.1 R/W Default = 0x0 */ - /* 1 = Rx enable */ - /*! \brief 1E.9004.0 R/W MSM Line Tx Enable - AQ_MsmLineGeneralControlRegister_HHD.u0.bits_0.msmLineTxEnable - - Default = 0x0 - - 1 = Tx enable - - Notes: - MAC Rx path enable. Should be set to 1 to enable the MAC Rx path. Should be set to 0 to disable the MAC Rx path. */ - unsigned int msmLineTxEnable : 1; /* 1E.9004.0 R/W Default = 0x0 */ - /* 1 = Tx enable */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line General Control Register */ - union - { - struct - { - unsigned int reserved0 : 8; - /*! \brief 1E.9005.7 R/W MSM Line Tx Low Power IDLE Enable - AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLineTxLowPowerIdleEnable - - Default = 0x0 - - 1 = Transmit LPI enable - - - Notes: - Transmit low power IDLE enable. When set to 1, the MAC completes the transmission of the current frame and generates low power IDLE sequences (LPI) to the XGMII/SGMII. When set to 0, the MAC operates in normal mode. This bit is OR'ed with the reg_lowp_ena pin. */ - unsigned int msmLineTxLowPowerIdleEnable : 1; /* 1E.9005.7 R/W Default = 0x0 */ - /* 1 = Transmit LPI enable - */ - unsigned int reserved1 : 1; - /*! \brief 1E.9005.5 R/W MSM Line SFD Check Disable - AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLineSfdCheckDisable - - Default = 0x0 - - 1 = Disable SFD check - - - Notes: - Disable check of SFD (0xD5) character at frame start. When set to 1, the frame is accepted even if the SFD byte following the preamble is not 0xD5. When set to 0, a frame is accepted only if the SFD byte is found with the value 0xD5. */ - unsigned int msmLineSfdCheckDisable : 1; /* 1E.9005.5 R/W Default = 0x0 */ - /* 1 = Disable SFD check - */ - unsigned int reserved2 : 1; - /*! \brief 1E.9005.3 R/W MSM Line Priority Flow Control Enable - AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLinePriorityFlowControlEnable - - Default = 0x0 - - 1 = Enable priority flow control - 0 = Enable link flow control - - - Notes: - Enable priority flow control (PFC) mode of operation. When set to 0, the MAC uses standard link pause frames. When set to 1, the MAC will transmit and accept PFC frames. */ - unsigned int msmLinePriorityFlowControlEnable : 1; /* 1E.9005.3 R/W Default = 0x0 */ - /* 1 = Enable priority flow control - 0 = Enable link flow control - */ - /*! \brief 1E.9005.2 R/W MSM Line IDLE Column Count Extend - AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLineIdleColumnCountExtend - - Default = 0x0 - - 1 = Extend IDLE column count - - Notes: - When set to 1, extends the RS layer IDLE column counter by 2x. The IEEE 802.3ae defines the fault condition to be cleared after 128 columns of IDLE have been received. If the MAC operates together with a WAN mode PCS (WIS) it may may happen (depending on PCS) that this period is too short to bridge the IDLE stuffing occurring in this mode, leading to a toggling fault indication. In this case, extending the counter helps to aoivd toggling fault indications. */ - unsigned int msmLineIdleColumnCountExtend : 1; /* 1E.9005.2 R/W Default = 0x0 */ - /* 1 = Extend IDLE column count */ - /*! \brief 1E.9005.1 R/W MSM Line Length Check Disable - AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLineLengthCheckDisable - - Default = 0x0 - - 1 = Disable length check - - Notes: - Payload length check disable. When set to 0, the MAC checks the frames payload length with the frame length/type field. When set to 1, the payload length check is disabled. */ - unsigned int msmLineLengthCheckDisable : 1; /* 1E.9005.1 R/W Default = 0x0 */ - /* 1 = Disable length check */ - /*! \brief 1E.9005.0 R/W MSM Line Force Send IDLE - AQ_MsmLineGeneralControlRegister_HHD.u1.bits_1.msmLineForceSendIdle - - Default = 0x0 - - 1 = Force send idle - - Notes: - When set to 1, suppress any frame transmissions and forces IDLE n the Tx interface instead of frames. This control affects the MAC reconciliation layer (RS) which acts after all MAC datapath has processed the frame. - Note : Does not have an effect on fault handling (i.e. reception of local fault will still cause transmit of remote fault). - Must be 0 for normal operation. */ - unsigned int msmLineForceSendIdle : 1; /* 1E.9005.0 R/W Default = 0x0 */ - /* 1 = Force send idle */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineGeneralControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line FIFO Control Register: 1E.900E */ -/* MSM Line FIFO Control Register: 1E.900E */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line FIFO Control Register */ - union - { - struct - { - unsigned int reserved0 : 8; - /*! \brief 1E.900E.7:0 R/W MSM Line Rx FIFO Full Threshold [7:0] - AQ_MsmLineFifoControlRegister_HHD.u0.bits_0.msmLineRxFifoFullThreshold - - Default = 0x08 - - Rx FIFO full threshold - - Notes: - All threshold values are in steps of FIFO words. */ - unsigned int msmLineRxFifoFullThreshold : 8; /* 1E.900E.7:0 R/W Default = 0x08 */ - /* Rx FIFO full threshold */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line FIFO Control Register */ - union - { - struct - { - unsigned int reserved0 : 8; - /*! \brief 1E.900F.7:0 R/W MSM Line Rx FIFO Empty Threshold [7:0] - AQ_MsmLineFifoControlRegister_HHD.u1.bits_1.msmLineRxFifoEmptyThreshold - - Default = 0x00 - - Rx FIFO empty threshold - - Notes: - All threshold values are in steps of FIFO words. */ - unsigned int msmLineRxFifoEmptyThreshold : 8; /* 1E.900F.7:0 R/W Default = 0x00 */ - /* Rx FIFO empty threshold */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of MSM Line FIFO Control Register */ - union - { - struct - { - unsigned int reserved0 : 10; - /*! \brief 1E.9010.5:0 R/W MSM Line Tx FIFO Full Threshold [5:0] - AQ_MsmLineFifoControlRegister_HHD.u2.bits_2.msmLineTxFifoFullThreshold - - Default = 0x08 - - Tx FIFO full threshold - - Notes: - All threshold values are in steps of FIFO words. */ - unsigned int msmLineTxFifoFullThreshold : 6; /* 1E.9010.5:0 R/W Default = 0x08 */ - /* Tx FIFO full threshold */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of MSM Line FIFO Control Register */ - union - { - struct - { - unsigned int reserved0 : 10; - /*! \brief 1E.9011.5:0 R/W MSM Line Tx FIFO Empty Threshold [5:0] - AQ_MsmLineFifoControlRegister_HHD.u3.bits_3.msmLineTxFifoEmptyThreshold - - Default = 0x00 - - Tx FIFO empty threshold - - Notes: - All threshold values are in steps of FIFO words. */ - unsigned int msmLineTxFifoEmptyThreshold : 6; /* 1E.9011.5:0 R/W Default = 0x00 */ - /* Tx FIFO empty threshold */ - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of MSM Line FIFO Control Register */ - union - { - struct - { - unsigned int reserved0 : 8; - /*! \brief 1E.9012.7:0 ROS MSM Line Rx FIFO Almost Full Threshold [7:0] - AQ_MsmLineFifoControlRegister_HHD.u4.bits_4.msmLineRxFifoAlmostFullThreshold - - Default = 0x00 - - Rx FIFO almost full threshold - - Notes: - Unused. */ - unsigned int msmLineRxFifoAlmostFullThreshold : 8; /* 1E.9012.7:0 ROS Default = 0x00 */ - /* Rx FIFO almost full threshold */ - } bits_4; - uint16_t word_4; - } u4; - /*! \brief Union for bit and word level access of word 5 of MSM Line FIFO Control Register */ - union - { - struct - { - unsigned int reserved0 : 8; - /*! \brief 1E.9013.7:0 ROS MSM Line Rx FIFO Almost Empty Threshold [7:0] - AQ_MsmLineFifoControlRegister_HHD.u5.bits_5.msmLineRxFifoAlmostEmptyThreshold - - Default = 0x00 - - Rx FIFO almost empty threshold - - Notes: - Unused. */ - unsigned int msmLineRxFifoAlmostEmptyThreshold : 8; /* 1E.9013.7:0 ROS Default = 0x00 */ - /* Rx FIFO almost empty threshold */ - } bits_5; - uint16_t word_5; - } u5; - /*! \brief Union for bit and word level access of word 6 of MSM Line FIFO Control Register */ - union - { - struct - { - unsigned int reserved0 : 8; - /*! \brief 1E.9014.7:0 ROS MSM Line Tx FIFO Almost Full Threshold [7:0] - AQ_MsmLineFifoControlRegister_HHD.u6.bits_6.msmLineTxFifoAlmostFullThreshold - - Default = 0x00 - - Tx FIFO almost full threshold - - Notes: - Unused. */ - unsigned int msmLineTxFifoAlmostFullThreshold : 8; /* 1E.9014.7:0 ROS Default = 0x00 */ - /* Tx FIFO almost full threshold */ - } bits_6; - uint16_t word_6; - } u6; - /*! \brief Union for bit and word level access of word 7 of MSM Line FIFO Control Register */ - union - { - struct - { - unsigned int reserved0 : 8; - /*! \brief 1E.9015.7:0 ROS MSM Line Tx FIFO Almost Empty Threshold [7:0] - AQ_MsmLineFifoControlRegister_HHD.u7.bits_7.msmLineTxFifoAlmostEmptyThreshold - - Default = 0x00 - - Tx FIFO almost empty threshold - - Notes: - Unused. */ - unsigned int msmLineTxFifoAlmostEmptyThreshold : 8; /* 1E.9015.7:0 ROS Default = 0x00 */ - /* Tx FIFO almost empty threshold */ - } bits_7; - uint16_t word_7; - } u7; -} AQ_MsmLineFifoControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line General Status Register: 1E.9020 */ -/* MSM Line General Status Register: 1E.9020 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line General Status Register */ - union - { - struct - { - unsigned int reserved0 : 10; - /*! \brief 1E.9020.5 RO MSM Line Tx FIFO Empty - AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLineTxFifoEmpty - - - - Tx FIFO empty - - Notes: - When set to 1, indicates the Tx FIFO is empty. When set to 0, Tx FIFO is non-empty. */ - unsigned int msmLineTxFifoEmpty : 1; /* 1E.9020.5 RO */ - /* Tx FIFO empty */ - /*! \brief 1E.9020.4 RO MSM Line Rx Low Power IDLE - AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLineRxLowPowerIdle - - - - Rx LPI detected - - Notes: - Receive low power IDLE (LPI). Set to 1 when LPI is currently detected on the MAC Rx interface. Set to 0, when the MAC currently operates in normal mode. */ - unsigned int msmLineRxLowPowerIdle : 1; /* 1E.9020.4 RO */ - /* Rx LPI detected */ - /*! \brief 1E.9020.3 R/W MSM Line Timestamp Available - AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLineTimestampAvailable - - Default = 0x0 - - Timestamp available - - Notes: - Transmit timestamp available. Indicates that the timestamp of the last transmitted event frame (which had ff_tx_ts_frm=1) is available in the register See MAC Time Stamp Status 0 [F:0] and See MAC Time Stamp Status 1 [F:0] . To clear this bit, the bit must be written with a 1. - */ - unsigned int msmLineTimestampAvailable : 1; /* 1E.9020.3 R/W Default = 0x0 */ - /* Timestamp available */ - /*! \brief 1E.9020.2 RO MSM Line PHY Loss of Signal - AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLinePhyLossOfSignal - - - - PHY loss of signal - - Notes: - PHY indicates loss of signal. This is the value of pin phy_los which is tied to 0. */ - unsigned int msmLinePhyLossOfSignal : 1; /* 1E.9020.2 RO */ - /* PHY loss of signal */ - /*! \brief 1E.9020.1 BLH MSM Line Rx Remote Fault - AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLineRxRemoteFault - - - - Rx remote fault detected - - Notes: - Latch high local fault status. Set to 1, whent he MAC detects Rx local fault sequences on the Rx interface. Reset to 0 after read and after reset. */ - unsigned int msmLineRxRemoteFault : 1; /* 1E.9020.1 BLH */ - /* Rx remote fault detected */ - /*! \brief 1E.9020.0 BLH MSM Line Rx Local Fault - AQ_MsmLineGeneralStatusRegister_HHD.u0.bits_0.msmLineRxLocalFault - - - - Rx local fault detected - - Notes: - Latch high local fault status. Set to 1, whent he MAC detects Rx local fault sequences on the Rx interface. Reset to 0 after read and after reset. */ - unsigned int msmLineRxLocalFault : 1; /* 1E.9020.0 BLH */ - /* Rx local fault detected */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line General Status Register */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineGeneralStatusRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Tx IPG Control Register: 1E.9022 */ -/* MSM Line Tx IPG Control Register: 1E.9022 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Tx IPG Control Register */ - union - { - struct - { - unsigned int reserved0 : 10; - /*! \brief 1E.9022.5:0 R/W MSM Line Tx IPG Length [5:0] - AQ_MsmLineTxIpgControlRegister_HHD.u0.bits_0.msmLineTxIpgLength - - Default = 0x0C - - Tx IPG length - - Notes: - Tx inter-packet gap (IPG) value. Depending on LAN or WAN mode of operation. - LAN Mode : Number of octets in steps of 4. Valid values are 8, 12, 16,..., 100. DIC is supported for any setting > 8. A default of 12 must be set to conform to IEEE802.3ae. - WAN Mode : Stretch factor. Valid values are 4 ... 15. The stretch factor is calculated as (value+1)*8. A default of 12 must be set to conform to IEEE802.3ae (i.e. 13*8=104). A larger value shrinks the IPG (increasing bandwidth). - The reset value of 12 leads to IEEE802.3ae conformant behavior in both modes. - Note : WAN mode is only available in 10G mode of operation. */ - unsigned int msmLineTxIpgLength : 6; /* 1E.9022.5:0 R/W Default = 0x0C */ - /* Tx IPG length */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Tx IPG Control Register */ - union - { - struct - { - /*! \brief 1E.9023.F:0 MSM Line Tx IPG Reserved - AQ_MsmLineTxIpgControlRegister_HHD.u1.bits_1.msmLineTxIpgReserved - - - - Value always 0, writes ignored - */ - unsigned int msmLineTxIpgReserved : 16; /* 1E.9023.F:0 */ - /* Value always 0, writes ignored */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineTxIpgControlRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Tx Good Frames Counter Register: 1E.9040 */ -/* MSM Line Tx Good Frames Counter Register: 1E.9040 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Good Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9040.F:0 ROS MSM Line Tx Good Frames Counter 0 [F:0] - AQ_MsmLineTxGoodFramesCounterRegister_HHD.u0.bits_0.msmLineTxGoodFramesCounter_0 - - Default = 0x0000 - - Tx good frame counter bits 15:0 - - Notes: - Count of frames transmitted without error (Including pause frames). */ - unsigned int msmLineTxGoodFramesCounter_0 : 16; /* 1E.9040.F:0 ROS Default = 0x0000 */ - /* Tx good frame counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Good Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9041.F:0 ROS MSM Line Tx Good Frames Counter 1 [F:0] - AQ_MsmLineTxGoodFramesCounterRegister_HHD.u1.bits_1.msmLineTxGoodFramesCounter_1 - - Default = 0x0000 - - Tx good frame counter bits 31:16 - - - Notes: - Count of frames transmitted without error (Including pause frames). */ - unsigned int msmLineTxGoodFramesCounter_1 : 16; /* 1E.9041.F:0 ROS Default = 0x0000 */ - /* Tx good frame counter bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineTxGoodFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Rx Good Frames Counter Register: 1E.9044 */ -/* MSM Line Rx Good Frames Counter Register: 1E.9044 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Good Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9044.F:0 ROS MSM Line Rx Good Frames Counter 0 [F:0] - AQ_MsmLineRxGoodFramesCounterRegister_HHD.u0.bits_0.msmLineRxGoodFramesCounter_0 - - Default = 0x0000 - - Rx good frame counter bits 15:0 - - Notes: - Count of frames received without error (Including pause frames). */ - unsigned int msmLineRxGoodFramesCounter_0 : 16; /* 1E.9044.F:0 ROS Default = 0x0000 */ - /* Rx good frame counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Good Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9045.F:0 ROS MSM Line Rx Good Frames Counter 1 [F:0] - AQ_MsmLineRxGoodFramesCounterRegister_HHD.u1.bits_1.msmLineRxGoodFramesCounter_1 - - Default = 0x0000 - - Rx good frame counter bits 31:16 - - Notes: - Count of frames received without error (Including pause frames). */ - unsigned int msmLineRxGoodFramesCounter_1 : 16; /* 1E.9045.F:0 ROS Default = 0x0000 */ - /* Rx good frame counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineRxGoodFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Rx FCS Errors Counter Register: 1E.9048 */ -/* MSM Line Rx FCS Errors Counter Register: 1E.9048 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Rx FCS Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.9048.F:0 ROS MSM Line FCS Error Counter 0 [F:0] - AQ_MsmLineRxFcsErrorsCounterRegister_HHD.u0.bits_0.msmLineFcsErrorCounter_0 - - Default = 0x0000 - - Frame check sequence error counter bits 15:0 - - Notes: - Count of frames for which a CRC-32 Error is detected but the frame is otherwise of correct length. */ - unsigned int msmLineFcsErrorCounter_0 : 16; /* 1E.9048.F:0 ROS Default = 0x0000 */ - /* Frame check sequence error counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Rx FCS Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.9049.F:0 ROS MSM Line FCS Error Counter 1 [F:0] - AQ_MsmLineRxFcsErrorsCounterRegister_HHD.u1.bits_1.msmLineFcsErrorCounter_1 - - Default = 0x0000 - - Frame check sequence error counter bits 31:16 - - Notes: - Count of frames for which a CRC-32 Error is detected but the frame is otherwise of correct length. */ - unsigned int msmLineFcsErrorCounter_1 : 16; /* 1E.9049.F:0 ROS Default = 0x0000 */ - /* Frame check sequence error counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineRxFcsErrorsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Rx Alignment Errors Counter Register: 1E.904C */ -/* MSM Line Rx Alignment Errors Counter Register: 1E.904C */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Alignment Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.904C.F:0 ROS MSM Line Alignment Error Counter 0 [F:0] - AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD.u0.bits_0.msmLineAlignmentErrorCounter_0 - - Default = 0x0000 - - Alignment error counter bits 15:0 - - Notes: - Count of frames received with an alignment error. */ - unsigned int msmLineAlignmentErrorCounter_0 : 16; /* 1E.904C.F:0 ROS Default = 0x0000 */ - /* Alignment error counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Alignment Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.904D.F:0 ROS MSM Line Alignment Error Counter 1 [F:0] - AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD.u1.bits_1.msmLineAlignmentErrorCounter_1 - - Default = 0x0000 - - Alignment error counter bits 31:16 - - Notes: - Count of frames received with an alignment error. */ - unsigned int msmLineAlignmentErrorCounter_1 : 16; /* 1E.904D.F:0 ROS Default = 0x0000 */ - /* Alignment error counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Tx Pause Frames Counter Register: 1E.9050 */ -/* MSM Line Tx Pause Frames Counter Register: 1E.9050 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Pause Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9050.F:0 ROS MSM Line Tx Pause Frames Counter 0 [F:0] - AQ_MsmLineTxPauseFramesCounterRegister_HHD.u0.bits_0.msmLineTxPauseFramesCounter_0 - - Default = 0x0000 - - Tx pause frame counter bits 15:0 - - Notes: - Valid pause frames transmitted. */ - unsigned int msmLineTxPauseFramesCounter_0 : 16; /* 1E.9050.F:0 ROS Default = 0x0000 */ - /* Tx pause frame counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Pause Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9051.F:0 ROS MSM Line Tx Pause Frames Counter 1 [F:0] - AQ_MsmLineTxPauseFramesCounterRegister_HHD.u1.bits_1.msmLineTxPauseFramesCounter_1 - - Default = 0x0000 - - Tx pause frame counter bits 31:16 - - - Notes: - Valid pause frames transmitted. */ - unsigned int msmLineTxPauseFramesCounter_1 : 16; /* 1E.9051.F:0 ROS Default = 0x0000 */ - /* Tx pause frame counter bits 31:16 - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineTxPauseFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Rx Pause Frames Counter Register: 1E.9054 */ -/* MSM Line Rx Pause Frames Counter Register: 1E.9054 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Pause Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9054.F:0 ROS MSM Line Rx Pause Frames Counter 0 [F:0] - AQ_MsmLineRxPauseFramesCounterRegister_HHD.u0.bits_0.msmLineRxPauseFramesCounter_0 - - Default = 0x0000 - - Rx pause frame counter bits 15:0 - - Notes: - Valid pause frames received. */ - unsigned int msmLineRxPauseFramesCounter_0 : 16; /* 1E.9054.F:0 ROS Default = 0x0000 */ - /* Rx pause frame counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Pause Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9055.F:0 ROS MSM Line Rx Pause Frames Counter 1 [F:0] - AQ_MsmLineRxPauseFramesCounterRegister_HHD.u1.bits_1.msmLineRxPauseFramesCounter_1 - - Default = 0x0000 - - Rx pause frame counter bits 31:16 - - Notes: - Valid pause frames received. */ - unsigned int msmLineRxPauseFramesCounter_1 : 16; /* 1E.9055.F:0 ROS Default = 0x0000 */ - /* Rx pause frame counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineRxPauseFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Rx Too Long Errors Counter Register: 1E.9058 */ -/* MSM Line Rx Too Long Errors Counter Register: 1E.9058 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Too Long Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.9058.F:0 ROS MSM Line Rx Too Long Errors Counter 0 [F:0] - AQ_MsmLineRxTooLongErrorsCounterRegister_HHD.u0.bits_0.msmLineRxTooLongErrorsCounter_0 - - Default = 0x0000 - - Too-long errors counter bits 15:0 - - Notes: - Frame received exceeded the maximum length programmed with register FRM_LGTH. */ - unsigned int msmLineRxTooLongErrorsCounter_0 : 16; /* 1E.9058.F:0 ROS Default = 0x0000 */ - /* Too-long errors counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Too Long Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.9059.F:0 ROS MSM Line Rx Too Long Errors Counter 1 [F:0] - AQ_MsmLineRxTooLongErrorsCounterRegister_HHD.u1.bits_1.msmLineRxTooLongErrorsCounter_1 - - Default = 0x0000 - - Too-long errors counter bits 31:16 - - Notes: - Frame received exceeded the maximum length programmed with register FRM_LGTH. */ - unsigned int msmLineRxTooLongErrorsCounter_1 : 16; /* 1E.9059.F:0 ROS Default = 0x0000 */ - /* Too-long errors counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineRxTooLongErrorsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Rx In Range Length Errors Counter Register: 1E.905C */ -/* MSM Line Rx In Range Length Errors Counter Register: 1E.905C */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Rx In Range Length Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.905C.F:0 ROS MSM Line Rx In Range Length Errors Counter 0 [F:0] - AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD.u0.bits_0.msmLineRxInRangeLengthErrorsCounter_0 - - Default = 0x0000 - - In-range-length errors counter bits 15:0 - - Notes: - A count of frames with a length/type field value between 46 (VLAN: 42) and less than 0x0600, that does not match the number of payload data octets received. Should count also if length/type field is less than 46 (VLAN: 42) and the frame is longer than 64 bytes. */ - unsigned int msmLineRxInRangeLengthErrorsCounter_0 : 16; /* 1E.905C.F:0 ROS Default = 0x0000 */ - /* In-range-length errors counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Rx In Range Length Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.905D.F:0 ROS MSM Line Rx In Range Length Errors Counter 1 [F:0] - AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD.u1.bits_1.msmLineRxInRangeLengthErrorsCounter_1 - - Default = 0x0000 - - In-range-length errors counter bits 31:16 - - Notes: - A count of frames with a length/type field value between 46 (VLAN: 42) and less than 0x0600, that does not match the number of payload data octets received. Should count also if length/type field is less than 46 (VLAN: 42) and the frame is longer than 64 bytes. */ - unsigned int msmLineRxInRangeLengthErrorsCounter_1 : 16; /* 1E.905D.F:0 ROS Default = 0x0000 */ - /* In-range-length errors counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Tx VLAN Frames Counter Register: 1E.9060 */ -/* MSM Line Tx VLAN Frames Counter Register: 1E.9060 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Tx VLAN Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9060.F:0 ROS MSM Line Tx VLAN Frames Counter 0 [F:0] - AQ_MsmLineTxVlanFramesCounterRegister_HHD.u0.bits_0.msmLineTxVlanFramesCounter_0 - - Default = 0x0000 - - Tx VLAN frames counter bits 15:0 - - Notes: - Valid VLAN tagged frames transmitted. */ - unsigned int msmLineTxVlanFramesCounter_0 : 16; /* 1E.9060.F:0 ROS Default = 0x0000 */ - /* Tx VLAN frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Tx VLAN Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9061.F:0 ROS MSM Line Tx VLAN Frames Counter 1 [F:0] - AQ_MsmLineTxVlanFramesCounterRegister_HHD.u1.bits_1.msmLineTxVlanFramesCounter_1 - - Default = 0x0000 - - Tx VLAN frames counter bits 31:16 - - Notes: - Valid VLAN tagged frames transmitted. */ - unsigned int msmLineTxVlanFramesCounter_1 : 16; /* 1E.9061.F:0 ROS Default = 0x0000 */ - /* Tx VLAN frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineTxVlanFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Rx VLAN Frames Counter Register: 1E.9064 */ -/* MSM Line Rx VLAN Frames Counter Register: 1E.9064 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Rx VLAN Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9064.F:0 ROS MSM Line Rx VLAN Frames Counter 0 [F:0] - AQ_MsmLineRxVlanFramesCounterRegister_HHD.u0.bits_0.msmLineRxVlanFramesCounter_0 - - Default = 0x0000 - - Rx VLAN frames counter bits 15:0 - - Notes: - Valid VLAN tagged frames received. */ - unsigned int msmLineRxVlanFramesCounter_0 : 16; /* 1E.9064.F:0 ROS Default = 0x0000 */ - /* Rx VLAN frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Rx VLAN Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9065.F:0 ROS MSM Line Rx VLAN Frames Counter 1 [F:0] - AQ_MsmLineRxVlanFramesCounterRegister_HHD.u1.bits_1.msmLineRxVlanFramesCounter_1 - - Default = 0x0000 - - Rx VLAN frames counter bits 31:16 - - Notes: - Valid VLAN tagged frames received. */ - unsigned int msmLineRxVlanFramesCounter_1 : 16; /* 1E.9065.F:0 ROS Default = 0x0000 */ - /* Rx VLAN frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineRxVlanFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Tx Octets Counter Register: 1E.9068 */ -/* MSM Line Tx Octets Counter Register: 1E.9068 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Octets Counter Register */ - union - { - struct - { - /*! \brief 1E.9068.F:0 ROS MSM Line Tx Octets Counter 0 [F:0] - AQ_MsmLineTxOctetsCounterRegister_HHD.u0.bits_0.msmLineTxOctetsCounter_0 - - Default = 0x0000 - - Tx octets counter bits 15:0 - - Notes: - All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ - unsigned int msmLineTxOctetsCounter_0 : 16; /* 1E.9068.F:0 ROS Default = 0x0000 */ - /* Tx octets counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Octets Counter Register */ - union - { - struct - { - /*! \brief 1E.9069.F:0 ROS MSM Line Tx Octets Counter 1 [F:0] - AQ_MsmLineTxOctetsCounterRegister_HHD.u1.bits_1.msmLineTxOctetsCounter_1 - - Default = 0x0000 - - Tx octets counter bits 31:16 - - Notes: - All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ - unsigned int msmLineTxOctetsCounter_1 : 16; /* 1E.9069.F:0 ROS Default = 0x0000 */ - /* Tx octets counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of MSM Line Tx Octets Counter Register */ - union - { - struct - { - /*! \brief 1E.906A.F:0 ROS MSM Line Tx Octets Counter 2 [F:0] - AQ_MsmLineTxOctetsCounterRegister_HHD.u2.bits_2.msmLineTxOctetsCounter_2 - - Default = 0x0000 - - Tx octets counter bits 47:32 - - Notes: - All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ - unsigned int msmLineTxOctetsCounter_2 : 16; /* 1E.906A.F:0 ROS Default = 0x0000 */ - /* Tx octets counter bits 47:32 */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of MSM Line Tx Octets Counter Register */ - union - { - struct - { - /*! \brief 1E.906B.F:0 ROS MSM Line Tx Octets Counter 3 [F:0] - AQ_MsmLineTxOctetsCounterRegister_HHD.u3.bits_3.msmLineTxOctetsCounter_3 - - Default = 0x0000 - - Tx octets counter bits 63:48 - - Notes: - All octets transmitted except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames transmitted. */ - unsigned int msmLineTxOctetsCounter_3 : 16; /* 1E.906B.F:0 ROS Default = 0x0000 */ - /* Tx octets counter bits 63:48 */ - } bits_3; - uint16_t word_3; - } u3; -} AQ_MsmLineTxOctetsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Rx Octets Counter Register: 1E.906C */ -/* MSM Line Rx Octets Counter Register: 1E.906C */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Octets Counter Register */ - union - { - struct - { - /*! \brief 1E.906C.F:0 ROS MSM Line Rx Octets Counter 0 [F:0] - AQ_MsmLineRxOctetsCounterRegister_HHD.u0.bits_0.msmLineRxOctetsCounter_0 - - Default = 0x0000 - - Rx octets counter bits 15:0 - - Notes: - All octets received except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames received. */ - unsigned int msmLineRxOctetsCounter_0 : 16; /* 1E.906C.F:0 ROS Default = 0x0000 */ - /* Rx octets counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Octets Counter Register */ - union - { - struct - { - /*! \brief 1E.906D.F:0 ROS MSM Line Rx Octets Counter 1 [F:0] - AQ_MsmLineRxOctetsCounterRegister_HHD.u1.bits_1.msmLineRxOctetsCounter_1 - - Default = 0x0000 - - Rx octets counter bits 31:16 - - Notes: - All octets received except preamble (i.e. Header, Payload, Pad and FCS) for all valid frames and valid pause frames received. */ - unsigned int msmLineRxOctetsCounter_1 : 16; /* 1E.906D.F:0 ROS Default = 0x0000 */ - /* Rx octets counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineRxOctetsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Rx Unicast Frames Counter Register: 1E.9070 */ -/* MSM Line Rx Unicast Frames Counter Register: 1E.9070 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Unicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9070.F:0 ROS MSM Line Rx Unicast Frames Counter 0 [F:0] - AQ_MsmLineRxUnicastFramesCounterRegister_HHD.u0.bits_0.msmLineRxUnicastFramesCounter_0 - - Default = 0x0000 - - Rx unicast frames counter bits 15:0 - - Notes: - Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '0'. */ - unsigned int msmLineRxUnicastFramesCounter_0 : 16; /* 1E.9070.F:0 ROS Default = 0x0000 */ - /* Rx unicast frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Unicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9071.F:0 ROS MSM Line Rx Unicast Frames Counter 1 [F:0] - AQ_MsmLineRxUnicastFramesCounterRegister_HHD.u1.bits_1.msmLineRxUnicastFramesCounter_1 - - Default = 0x0000 - - Rx unicast frames counter bits 31:16 - - Notes: - Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '0'. */ - unsigned int msmLineRxUnicastFramesCounter_1 : 16; /* 1E.9071.F:0 ROS Default = 0x0000 */ - /* Rx unicast frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineRxUnicastFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Rx Multicast Frames Counter Register: 1E.9074 */ -/* MSM Line Rx Multicast Frames Counter Register: 1E.9074 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Multicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9074.F:0 ROS MSM Line Rx Multicast Frames Counter 0 [F:0] - AQ_MsmLineRxMulticastFramesCounterRegister_HHD.u0.bits_0.msmLineRxMulticastFramesCounter_0 - - Default = 0x0000 - - Rx multicast frames counter bits 15:0 - - Notes: - Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '1' but not the broadcast address (all bits set '1' ). Pause frames are not counted. */ - unsigned int msmLineRxMulticastFramesCounter_0 : 16; /* 1E.9074.F:0 ROS Default = 0x0000 */ - /* Rx multicast frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Multicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9075.F:0 ROS MSM Line Rx Multicast Frames Counter 1 [F:0] - AQ_MsmLineRxMulticastFramesCounterRegister_HHD.u1.bits_1.msmLineRxMulticastFramesCounter_1 - - Default = 0x0000 - - Rx multicast frames counter bits 31:16 - - Notes: - Incremented with each valid frame received on the receive FIFO interface and bit 0 of the destination address was '1' but not the broadcast address (all bits set '1' ). Pause frames are not counted. */ - unsigned int msmLineRxMulticastFramesCounter_1 : 16; /* 1E.9075.F:0 ROS Default = 0x0000 */ - /* Rx multicast frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineRxMulticastFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Rx Broadcast Frames Counter Register: 1E.9078 */ -/* MSM Line Rx Broadcast Frames Counter Register: 1E.9078 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Broadcast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9078.F:0 ROS MSM Line Rx Broadcast Frames Counter 0 [F:0] - AQ_MsmLineRxBroadcastFramesCounterRegister_HHD.u0.bits_0.msmLineRxBroadcastFramesCounter_0 - - Default = 0x0000 - - Rx broadcast frames counter bits 15:0 - - Notes: - Incremented with each valid frame received on the receive FIFO interface (FIFO) and all bits of the destination address were set '1'. */ - unsigned int msmLineRxBroadcastFramesCounter_0 : 16; /* 1E.9078.F:0 ROS Default = 0x0000 */ - /* Rx broadcast frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Broadcast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9079.F:0 ROS MSM Line Rx Broadcast Frames Counter 1 [F:0] - AQ_MsmLineRxBroadcastFramesCounterRegister_HHD.u1.bits_1.msmLineRxBroadcastFramesCounter_1 - - Default = 0x0000 - - Rx broadcast frames counter bits 31:16 - - Notes: - Incremented with each valid frame received on the receive FIFO interface (FIFO) and all bits of the destination address were set '1'. */ - unsigned int msmLineRxBroadcastFramesCounter_1 : 16; /* 1E.9079.F:0 ROS Default = 0x0000 */ - /* Rx broadcast frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineRxBroadcastFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Tx Errors Counter Register: 1E.907C */ -/* MSM Line Tx Errors Counter Register: 1E.907C */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.907C.F:0 ROS MSM Line Tx Errors Counter 0 [F:0] - AQ_MsmLineTxErrorsCounterRegister_HHD.u0.bits_0.msmLineTxErrorsCounter_0 - - Default = 0x0000 - - Rx errors counter bits 15:0 - - Notes: - Number of frames transmitted with error: - - FIFO Overflow Errors - - FIFO Underflow Errors */ - unsigned int msmLineTxErrorsCounter_0 : 16; /* 1E.907C.F:0 ROS Default = 0x0000 */ - /* Rx errors counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.907D.F:0 ROS MSM Line Tx Errors Counter 1 [F:0] - AQ_MsmLineTxErrorsCounterRegister_HHD.u1.bits_1.msmLineTxErrorsCounter_1 - - Default = 0x0000 - - Tx errors counter bits 31:16 - - Notes: - Number of frames transmitted with error: - - FIFO Overflow Errors - - FIFO Underflow Errors */ - unsigned int msmLineTxErrorsCounter_1 : 16; /* 1E.907D.F:0 ROS Default = 0x0000 */ - /* Tx errors counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineTxErrorsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Tx Unicast Frames Counter Register: 1E.9084 */ -/* MSM Line Tx Unicast Frames Counter Register: 1E.9084 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Unicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9084.F:0 ROS MSM Line Tx Unicast Frames Counter 0 [F:0] - AQ_MsmLineTxUnicastFramesCounterRegister_HHD.u0.bits_0.msmLineTxUnicastFramesCounter_0 - - Default = 0x0000 - - Tx unicast frames counter bits 15:0 - - Notes: - Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '0'. */ - unsigned int msmLineTxUnicastFramesCounter_0 : 16; /* 1E.9084.F:0 ROS Default = 0x0000 */ - /* Tx unicast frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Unicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9085.F:0 ROS MSM Line Tx Unicast Frames Counter 1 [F:0] - AQ_MsmLineTxUnicastFramesCounterRegister_HHD.u1.bits_1.msmLineTxUnicastFramesCounter_1 - - Default = 0x0000 - - Tx unicast frames counter bits 31:16 - - Notes: - Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '0'. */ - unsigned int msmLineTxUnicastFramesCounter_1 : 16; /* 1E.9085.F:0 ROS Default = 0x0000 */ - /* Tx unicast frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineTxUnicastFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Tx Multicast Frames Counter Register: 1E.9088 */ -/* MSM Line Tx Multicast Frames Counter Register: 1E.9088 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Multicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9088.F:0 ROS MSM Line Tx Multicast Frames Counter 0 [F:0] - AQ_MsmLineTxMulticastFramesCounterRegister_HHD.u0.bits_0.msmLineTxMulticastFramesCounter_0 - - Default = 0x0000 - - Tx multicast frames counter bits 15:0 - - Notes: - Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '1' but not the broadcast address (all bits '1'). */ - unsigned int msmLineTxMulticastFramesCounter_0 : 16; /* 1E.9088.F:0 ROS Default = 0x0000 */ - /* Tx multicast frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Multicast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.9089.F:0 ROS MSM Line Tx Multicast Frames Counter 1 [F:0] - AQ_MsmLineTxMulticastFramesCounterRegister_HHD.u1.bits_1.msmLineTxMulticastFramesCounter_1 - - Default = 0x0000 - - Tx multicast frames counter bits 31:16 - - Notes: - Incremented with each frame written to the FIFO interface and bit 0 of the destination address set to '1' but not the broadcast address (all bits '1'). */ - unsigned int msmLineTxMulticastFramesCounter_1 : 16; /* 1E.9089.F:0 ROS Default = 0x0000 */ - /* Tx multicast frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineTxMulticastFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Tx Broadcast Frames Counter Register: 1E.908C */ -/* MSM Line Tx Broadcast Frames Counter Register: 1E.908C */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Tx Broadcast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.908C.F:0 ROS MSM Line Tx Broadcast Frames Counter 0 [F:0] - AQ_MsmLineTxBroadcastFramesCounterRegister_HHD.u0.bits_0.msmLineTxBroadcastFramesCounter_0 - - Default = 0x0000 - - Tx broadcast frames counter bits 15:0 - - Notes: - Incremented with each frame written to the FIFO interface and all bits of the destination address set to '1'. */ - unsigned int msmLineTxBroadcastFramesCounter_0 : 16; /* 1E.908C.F:0 ROS Default = 0x0000 */ - /* Tx broadcast frames counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Tx Broadcast Frames Counter Register */ - union - { - struct - { - /*! \brief 1E.908D.F:0 ROS MSM Line Tx Broadcast Frames Counter 1 [F:0] - AQ_MsmLineTxBroadcastFramesCounterRegister_HHD.u1.bits_1.msmLineTxBroadcastFramesCounter_1 - - Default = 0x0000 - - Tx broadcast frames counter bits 31:16 - - Notes: - Incremented with each frame written to the FIFO interface and all bits of the destination address set to '1'. */ - unsigned int msmLineTxBroadcastFramesCounter_1 : 16; /* 1E.908D.F:0 ROS Default = 0x0000 */ - /* Tx broadcast frames counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineTxBroadcastFramesCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief MSM Line Rx Errors Counter Register: 1E.90C8 */ -/* MSM Line Rx Errors Counter Register: 1E.90C8 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of MSM Line Rx Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.90C8.F:0 ROS MSM Line Rx Errors Counter 0 [F:0] - AQ_MsmLineRxErrorsCounterRegister_HHD.u0.bits_0.msmLineRxErrorsCounter_0 - - Default = 0x0000 - - Rx errors counter bits 15:0 - - Notes: - Number of frames received with error: - - FIFO Overflow Errors - - CRC Errors - - Payload Length Errors - - Jabber and Oversized Errors - - Alignment Errors - - The dedicated Error Code (0xfe, not a code error) was received */ - unsigned int msmLineRxErrorsCounter_0 : 16; /* 1E.90C8.F:0 ROS Default = 0x0000 */ - /* Rx errors counter bits 15:0 */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of MSM Line Rx Errors Counter Register */ - union - { - struct - { - /*! \brief 1E.90C9.F:0 ROS MSM Line Rx Errors Counter 1 [F:0] - AQ_MsmLineRxErrorsCounterRegister_HHD.u1.bits_1.msmLineRxErrorsCounter_1 - - Default = 0x0000 - - Rx errors counter bits 31:16 - - Notes: - Number of frames received with error: - - FIFO Overflow Errors - - CRC Errors - - Payload Length Errors - - Jabber and Oversized Errors - - Alignment Errors - - The dedicated Error Code (0xfe, not a code error) was received */ - unsigned int msmLineRxErrorsCounter_1 : 16; /* 1E.90C9.F:0 ROS Default = 0x0000 */ - /* Rx errors counter bits 31:16 */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_MsmLineRxErrorsCounterRegister_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Control: 1E.C000 */ -/* Global Control: 1E.C000 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Control */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Control */ - union - { - struct - { - /*! \brief 1E.C001.F R/W uP Reset - AQ_GlobalControl_HHD.u1.bits_1.upReset - - Default = 0x0 - - 1 = Reset - - - Notes: - Resets the uP and the PIF master and slave bus. Will be active for a minimum of 100 microseconds. */ - unsigned int upReset : 1; /* 1E.C001.F R/W Default = 0x0 */ - /* 1 = Reset - */ - unsigned int reserved0 : 8; - /*! \brief 1E.C001.6 R/W uP Run Stall Override - AQ_GlobalControl_HHD.u1.bits_1.upRunStallOverride - - Default = 0x0 - - 0 = uP Run Stall from "MDIO Boot Load" pin. - 1 = uP Run Stall from See MCP Run Stall bit - - - - Notes: - This bit selects the uP Run Stall from either the "MDIO Boot Load" pin or the See MCP Run Stall bit. Pin no longer brought out as deprecated. */ - unsigned int upRunStallOverride : 1; /* 1E.C001.6 R/W Default = 0x0 */ - /* 0 = uP Run Stall from "MDIO Boot Load" pin. - 1 = uP Run Stall from See MCP Run Stall bit - - */ - unsigned int reserved1 : 5; - /*! \brief 1E.C001.0 R/W uP Run Stall - AQ_GlobalControl_HHD.u1.bits_1.upRunStall - - Default = 0x0 - - 1 = uP Run Stall - 0 = uP normal mode - - - Notes: - Deactivates the uP. */ - unsigned int upRunStall : 1; /* 1E.C001.0 R/W Default = 0x0 */ - /* 1 = uP Run Stall - 0 = uP normal mode - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_GlobalControl_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Reset Control: 1E.C006 */ -/* Global Reset Control: 1E.C006 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Reset Control */ - union - { - struct - { - unsigned int reserved0 : 1; - /*! \brief 1E.C006.E R/WPD Global MMD Reset Disable - AQ_GlobalResetControl_HHD.u0.bits_0.globalMMD_ResetDisable - - Provisionable Default = 0x0 - - 1 = Disable the S/W reset to the Global MMD registers - 0 = Enable the S/W reset to the Global MMD registers - - - Notes: - Setting this bit prevents a Global S/W reset or Global S/W reset from resetting the Global MMD registers */ - unsigned int globalMMD_ResetDisable : 1; /* 1E.C006.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Disable the S/W reset to the Global MMD registers - 0 = Enable the S/W reset to the Global MMD registers - */ - unsigned int reserved1 : 14; - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalResetControl_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Diagnostic Provisioning: 1E.C400 */ -/* Global Diagnostic Provisioning: 1E.C400 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Diagnostic Provisioning */ - union - { - struct - { - /*! \brief 1E.C400.F R/WPD Enable Diagnostics - AQ_GlobalDiagnosticProvisioning_HHD.u0.bits_0.enableDiagnostics - - Provisionable Default = 0x1 - - 1 = Chip performs diagnostics on power-up - */ - unsigned int enableDiagnostics : 1; /* 1E.C400.F R/WPD Provisionable Default = 0x1 */ - /* 1 = Chip performs diagnostics on power-up */ - unsigned int reserved0 : 15; - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalDiagnosticProvisioning_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Thermal Provisioning: 1E.C420 */ -/* Global Thermal Provisioning: 1E.C420 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Thermal Provisioning */ - union - { - struct - { - /*! \brief 1E.C420.F:0 R/WPD Reserved 0 [F:0] - AQ_GlobalThermalProvisioning_HHD.u0.bits_0.reserved_0 - - Provisionable Default = 0x0000 - - Internal reserved - do not modify - - */ - unsigned int reserved_0 : 16; /* 1E.C420.F:0 R/WPD Provisionable Default = 0x0000 */ - /* Internal reserved - do not modify - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Thermal Provisioning */ - union - { - struct - { - /*! \brief 1E.C421.F:0 R/WPD High Temp Failure Threshold [F:0] - AQ_GlobalThermalProvisioning_HHD.u1.bits_1.highTempFailureThreshold - - Provisionable Default = 0x4600 - - [F:0] of high temperature failure threshold - - Notes: - 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 70 degreesC. - - In XENPAK mode, F/W will use the XENPAK register 1.A000 - 1.A001: instead of this register. - - NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ - unsigned int highTempFailureThreshold : 16; /* 1E.C421.F:0 R/WPD Provisionable Default = 0x4600 */ - /* [F:0] of high temperature failure threshold */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global Thermal Provisioning */ - union - { - struct - { - /*! \brief 1E.C422.F:0 R/WPD Low Temp Failure Threshold [F:0] - AQ_GlobalThermalProvisioning_HHD.u2.bits_2.lowTempFailureThreshold - - Provisionable Default = 0x0000 - - [F:0] of low temperature failure threshold - - Notes: - 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 0 degreesC. - - In XENPAK mode, F/W will use the XENPAK register 1.A002 - 1.A003: instead of this register. - - NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ - unsigned int lowTempFailureThreshold : 16; /* 1E.C422.F:0 R/WPD Provisionable Default = 0x0000 */ - /* [F:0] of low temperature failure threshold */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global Thermal Provisioning */ - union - { - struct - { - /*! \brief 1E.C423.F:0 R/WPD High Temp Warning Threshold [F:0] - AQ_GlobalThermalProvisioning_HHD.u3.bits_3.highTempWarningThreshold - - Provisionable Default = 0x3C00 - - [F:0] of high temperature warning threshold - - Notes: - 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD008. Default is 60 degreesC. - - In XENPAK mode, F/W will use the XENPAK register 1.A004 - 1.A005: instead of this register. - - NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ - unsigned int highTempWarningThreshold : 16; /* 1E.C423.F:0 R/WPD Provisionable Default = 0x3C00 */ - /* [F:0] of high temperature warning threshold */ - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of Global Thermal Provisioning */ - union - { - struct - { - /*! \brief 1E.C424.F:0 R/WPD Low Temp Warning Threshold [F:0] - AQ_GlobalThermalProvisioning_HHD.u4.bits_4.lowTempWarningThreshold - - Provisionable Default = 0x0A00 - - [F:0] of low temperature warning threshold - - Notes: - 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 10 degreesC. - - In XENPAK mode, F/W will use the XENPAK register 1.A006 - 1.A007: instead of this register. - - NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). */ - unsigned int lowTempWarningThreshold : 16; /* 1E.C424.F:0 R/WPD Provisionable Default = 0x0A00 */ - /* [F:0] of low temperature warning threshold */ - } bits_4; - uint16_t word_4; - } u4; -} AQ_GlobalThermalProvisioning_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global LED Provisioning: 1E.C430 */ -/* Global LED Provisioning: 1E.C430 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global LED Provisioning */ - union - { - struct - { - unsigned int reserved0 : 2; - /*! \brief 1E.C430.D:9 R/WPD Reserved Provisioning C430 [4:0] - AQ_GlobalLedProvisioning_HHD.u0.bits_0.reservedProvisioningC430 - - Provisionable Default = 0x00 - - Reserved for future use - */ - unsigned int reservedProvisioningC430 : 5; /* 1E.C430.D:9 R/WPD Provisionable Default = 0x00 */ - /* Reserved for future use */ - /*! \brief 1E.C430.8 R/WPD LED #0 Manual Set - AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0ManualSet - - Provisionable Default = 0x0 - - 1 = LED On - - */ - unsigned int led_0ManualSet : 1; /* 1E.C430.8 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED On - */ - /*! \brief 1E.C430.7 R/WPD LED #0 10 Gb/s Link Established - AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0_10Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 10 Gb/s - - */ - unsigned int led_0_10Gb_sLinkEstablished : 1; /* 1E.C430.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 10 Gb/s - */ - /*! \brief 1E.C430.6 R/WPD LED #0 1 Gb/s Link Established - AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0_1Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 1 Gb/s - - */ - unsigned int led_0_1Gb_sLinkEstablished : 1; /* 1E.C430.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 1 Gb/s - */ - /*! \brief 1E.C430.5 R/WPD LED #0 100 Mb/s Link Established - AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0_100Mb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 100 Mb/s. - - */ - unsigned int led_0_100Mb_sLinkEstablished : 1; /* 1E.C430.5 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 100 Mb/s. - */ - /*! \brief 1E.C430.4 R/WPD LED #0 Connecting - AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0Connecting - - Provisionable Default = 0x0 - - 1 = LED is on when attempting to connect. - - */ - unsigned int led_0Connecting : 1; /* 1E.C430.4 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when attempting to connect. - */ - /*! \brief 1E.C430.3 R/WPD LED #0 Receive Activity - AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0ReceiveActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on receive activity - - */ - unsigned int led_0ReceiveActivity : 1; /* 1E.C430.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on receive activity - */ - /*! \brief 1E.C430.2 R/WPD LED #0 Transmit Activity - AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0TransmitActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on transmit activity - - */ - unsigned int led_0TransmitActivity : 1; /* 1E.C430.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on transmit activity - */ - /*! \brief 1E.C430.1:0 R/WPD LED #0 Activity Stretch [1:0] - AQ_GlobalLedProvisioning_HHD.u0.bits_0.led_0ActivityStretch - - Provisionable Default = 0x3 - - [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - - */ - unsigned int led_0ActivityStretch : 2; /* 1E.C430.1:0 R/WPD Provisionable Default = 0x3 */ - /* [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global LED Provisioning */ - union - { - struct - { - unsigned int reserved0 : 2; - /*! \brief 1E.C431.D:9 R/WPD Reserved Provisioning C431 [4:0] - AQ_GlobalLedProvisioning_HHD.u1.bits_1.reservedProvisioningC431 - - Provisionable Default = 0x00 - - Reserved for future use - */ - unsigned int reservedProvisioningC431 : 5; /* 1E.C431.D:9 R/WPD Provisionable Default = 0x00 */ - /* Reserved for future use */ - /*! \brief 1E.C431.8 R/WPD LED #1 Manual Set - AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1ManualSet - - Provisionable Default = 0x0 - - 1 = LED On - - */ - unsigned int led_1ManualSet : 1; /* 1E.C431.8 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED On - */ - /*! \brief 1E.C431.7 R/WPD LED #1 10 Gb/s Link Established - AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1_10Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 10 Gb/s - - */ - unsigned int led_1_10Gb_sLinkEstablished : 1; /* 1E.C431.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 10 Gb/s - */ - /*! \brief 1E.C431.6 R/WPD LED #1 1 Gb/s Link Established - AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1_1Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 1 Gb/s - - */ - unsigned int led_1_1Gb_sLinkEstablished : 1; /* 1E.C431.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 1 Gb/s - */ - /*! \brief 1E.C431.5 R/WPD LED #1 100 Mb/s Link Established - AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1_100Mb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 100 Mb/s. - - */ - unsigned int led_1_100Mb_sLinkEstablished : 1; /* 1E.C431.5 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 100 Mb/s. - */ - /*! \brief 1E.C431.4 R/WPD LED #1 Connecting - AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1Connecting - - Provisionable Default = 0x0 - - 1 = LED is on when attempting to connect. - - */ - unsigned int led_1Connecting : 1; /* 1E.C431.4 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when attempting to connect. - */ - /*! \brief 1E.C431.3 R/WPD LED #1 Receive Activity - AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1ReceiveActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on receive activity - - */ - unsigned int led_1ReceiveActivity : 1; /* 1E.C431.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on receive activity - */ - /*! \brief 1E.C431.2 R/WPD LED #1 Transmit Activity - AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1TransmitActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on transmit activity - - */ - unsigned int led_1TransmitActivity : 1; /* 1E.C431.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on transmit activity - */ - /*! \brief 1E.C431.1:0 R/WPD LED #1 Activity Stretch [1:0] - AQ_GlobalLedProvisioning_HHD.u1.bits_1.led_1ActivityStretch - - Provisionable Default = 0x3 - - [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - - */ - unsigned int led_1ActivityStretch : 2; /* 1E.C431.1:0 R/WPD Provisionable Default = 0x3 */ - /* [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global LED Provisioning */ - union - { - struct - { - unsigned int reserved0 : 2; - /*! \brief 1E.C432.D:9 R/WPD Reserved Provisioning C432 [4:0] - AQ_GlobalLedProvisioning_HHD.u2.bits_2.reservedProvisioningC432 - - Provisionable Default = 0x00 - - Reserved for future use - */ - unsigned int reservedProvisioningC432 : 5; /* 1E.C432.D:9 R/WPD Provisionable Default = 0x00 */ - /* Reserved for future use */ - /*! \brief 1E.C432.8 R/WPD LED #2 Manual Set - AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2ManualSet - - Provisionable Default = 0x0 - - 1 = LED On - - */ - unsigned int led_2ManualSet : 1; /* 1E.C432.8 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED On - */ - /*! \brief 1E.C432.7 R/WPD LED #2 10 Gb/s Link Established - AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2_10Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 10 Gb/s - - */ - unsigned int led_2_10Gb_sLinkEstablished : 1; /* 1E.C432.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 10 Gb/s - */ - /*! \brief 1E.C432.6 R/WPD LED #2 1 Gb/s Link Established - AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2_1Gb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 1 Gb/s - - */ - unsigned int led_2_1Gb_sLinkEstablished : 1; /* 1E.C432.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 1 Gb/s - */ - /*! \brief 1E.C432.5 R/WPD LED #2 100 Mb/s Link Established - AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2_100Mb_sLinkEstablished - - Provisionable Default = 0x0 - - 1 = LED is on when link connects at 100 Mb/s. - */ - unsigned int led_2_100Mb_sLinkEstablished : 1; /* 1E.C432.5 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when link connects at 100 Mb/s. */ - /*! \brief 1E.C432.4 R/WPD LED #2 Connecting - AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2Connecting - - Provisionable Default = 0x0 - - 1 = LED is on when attempting to connect. - - */ - unsigned int led_2Connecting : 1; /* 1E.C432.4 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED is on when attempting to connect. - */ - /*! \brief 1E.C432.3 R/WPD LED #2 Receive Activity - AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2ReceiveActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on receive activity - - */ - unsigned int led_2ReceiveActivity : 1; /* 1E.C432.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on receive activity - */ - /*! \brief 1E.C432.2 R/WPD LED #2 Transmit Activity - AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2TransmitActivity - - Provisionable Default = 0x0 - - 1 = LED toggles on transmit activity - - */ - unsigned int led_2TransmitActivity : 1; /* 1E.C432.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED toggles on transmit activity - */ - /*! \brief 1E.C432.1:0 R/WPD LED #2 Activity Stretch [1:0] - AQ_GlobalLedProvisioning_HHD.u2.bits_2.led_2ActivityStretch - - Provisionable Default = 0x3 - - [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - - */ - unsigned int led_2ActivityStretch : 2; /* 1E.C432.1:0 R/WPD Provisionable Default = 0x3 */ - /* [1:0] - 0x3 = stretch activity by 100 ms - 0x2 = stretch activity by 60 ms - 0x1 = stretch activity by 28 ms - 0x0 = no stretching - */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global LED Provisioning */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of Global LED Provisioning */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_4; - uint16_t word_4; - } u4; - /*! \brief Union for bit and word level access of word 5 of Global LED Provisioning */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_5; - uint16_t word_5; - } u5; - /*! \brief Union for bit and word level access of word 6 of Global LED Provisioning */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_6; - uint16_t word_6; - } u6; - /*! \brief Union for bit and word level access of word 7 of Global LED Provisioning */ - union - { - struct - { - unsigned int reserved0 : 15; - /*! \brief 1E.C437.0 R/WPD LED Operation Mode - AQ_GlobalLedProvisioning_HHD.u7.bits_7.ledOperationMode - - Provisionable Default = 0x0 - - 1 = LED link activity in Mode #2 - 0 = LED link activity in Aquantia classic mode - - - Notes: - When set to 1, the LED blinking rate is based on Mode #2 algorithm. When set to 0, the LED blinking rate is based on the classic Aquantia algorithm. */ - unsigned int ledOperationMode : 1; /* 1E.C437.0 R/WPD Provisionable Default = 0x0 */ - /* 1 = LED link activity in Mode #2 - 0 = LED link activity in Aquantia classic mode - */ - } bits_7; - uint16_t word_7; - } u7; - /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ - union - { - struct - { - unsigned int reserved : 16; - } bits_8; - uint16_t word_8; - } u8; - /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ - union - { - struct - { - unsigned int reserved : 16; - } bits_9; - uint16_t word_9; - } u9; - /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ - union - { - struct - { - unsigned int reserved : 16; - } bits_10; - uint16_t word_10; - } u10; - /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ - union - { - struct - { - unsigned int reserved : 16; - } bits_11; - uint16_t word_11; - } u11; - /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ - union - { - struct - { - unsigned int reserved : 16; - } bits_12; - uint16_t word_12; - } u12; - /*! \brief Dummy union to fill space in the structure Global LED Provisioning */ - union - { - struct - { - unsigned int reserved : 16; - } bits_13; - uint16_t word_13; - } u13; - /*! \brief Union for bit and word level access of word 14 of Global LED Provisioning */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_14; - uint16_t word_14; - } u14; -} AQ_GlobalLedProvisioning_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global General Provisioning: 1E.C440 */ -/* Global General Provisioning: 1E.C440 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global General Provisioning */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global General Provisioning */ - union - { - struct - { - unsigned int reserved0 : 1; - /*! \brief 1E.C441.E R/WPD MDIO Broadcast Mode Enable - AQ_GlobalGeneralProvisioning_HHD.u1.bits_1.mdioBroadcastModeEnable - - Provisionable Default = 0x0 - - 1 = Enable broadcast on address set in 1E.C446 - 0 = Disable broadcast on n address set in 1E.C446 - - - Notes: - When enabled, writes and load MMD address opcodes are supported. Read opcodes are ignored. */ - unsigned int mdioBroadcastModeEnable : 1; /* 1E.C441.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable broadcast on address set in 1E.C446 - 0 = Disable broadcast on n address set in 1E.C446 - */ - /*! \brief 1E.C441.D R/WPD MDIO Read MSW First Enable - AQ_GlobalGeneralProvisioning_HHD.u1.bits_1.mdioReadMSW_FirstEnable - - Provisionable Default = 0x0 - - 1 = MSW of counter must be read first - 0 = LSW of counter must be read first - - - Notes: - This bit configures whether the MSW or LSW must be read first for counters greater than 16 bits. */ - unsigned int mdioReadMSW_FirstEnable : 1; /* 1E.C441.D R/WPD Provisionable Default = 0x0 */ - /* 1 = MSW of counter must be read first - 0 = LSW of counter must be read first - */ - unsigned int reserved1 : 8; - /*! \brief 1E.C441.4 R/WPD MDIO Drive Configuration - AQ_GlobalGeneralProvisioning_HHD.u1.bits_1.mdioDriveConfiguration - - Provisionable Default = 0x0 - - 0 = MDIO driver is in normal mode - 1 = MDIO driver is in open drain mode - - - Notes: - When the MDIO driver is in open drain mode during a read cycle, "0" data will be actively driven out of the MDIO, "1" data will set the MDIO driver in high impedance state and an external pullup will set the MDIO line to "1". The Turn-Around "0" will also be actively driven out of the MDIO, therefore in open drain mode, the Turn-Around is still "Z0". */ - unsigned int mdioDriveConfiguration : 1; /* 1E.C441.4 R/WPD Provisionable Default = 0x0 */ - /* 0 = MDIO driver is in normal mode - 1 = MDIO driver is in open drain mode - */ - /*! \brief 1E.C441.3 R/WPD MDIO Preamble Detection Disable - AQ_GlobalGeneralProvisioning_HHD.u1.bits_1.mdioPreambleDetectionDisable - - Provisionable Default = 0x0 - - 1 = Suppress preamble detection on MDIO - 0 = Enable preamble detection on MDIO - - */ - unsigned int mdioPreambleDetectionDisable : 1; /* 1E.C441.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = Suppress preamble detection on MDIO - 0 = Enable preamble detection on MDIO - */ - unsigned int reserved2 : 1; - unsigned int reserved3 : 2; - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global General Provisioning */ - union - { - struct - { - unsigned int reserved0 : 15; - /*! \brief 1E.C442.0 R/W Daisy Chain Reset - AQ_GlobalGeneralProvisioning_HHD.u2.bits_2.daisyChainReset - - Default = 0x0 - - 1 = Reset the daisy chain - - - Notes: - Toggling this bit from 0 to 1 will reload the IRAM and DRAM and reset the uP. The uP will be in uP run stall during the reload process. After the reload process, uP run stall will be de-asserted and the uP reset will be asserted. Note that before setting this bit, the See Soft Reset bit needs to be de-asserted. */ - unsigned int daisyChainReset : 1; /* 1E.C442.0 R/W Default = 0x0 */ - /* 1 = Reset the daisy chain - */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global General Provisioning */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of Global General Provisioning */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_4; - uint16_t word_4; - } u4; - /*! \brief Union for bit and word level access of word 5 of Global General Provisioning */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_5; - uint16_t word_5; - } u5; - /*! \brief Union for bit and word level access of word 6 of Global General Provisioning */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_6; - uint16_t word_6; - } u6; - /*! \brief Union for bit and word level access of word 7 of Global General Provisioning */ - union - { - struct - { - unsigned int reserved0 : 11; - /*! \brief 1E.C447.4:0 R/WPD MDIO Broadcast Address Configuration [4:0] - AQ_GlobalGeneralProvisioning_HHD.u7.bits_7.mdioBroadcastAddressConfiguration - - Provisionable Default = 0x1F - - Broadcast address - - - Notes: - Allows setting the broadcast address. By default this is set to 0x1F */ - unsigned int mdioBroadcastAddressConfiguration : 5; /* 1E.C447.4:0 R/WPD Provisionable Default = 0x1F */ - /* Broadcast address - */ - } bits_7; - uint16_t word_7; - } u7; - /*! \brief Union for bit and word level access of word 8 of Global General Provisioning */ - union - { - struct - { - unsigned int reserved0 : 16; - } bits_8; - uint16_t word_8; - } u8; - /*! \brief Union for bit and word level access of word 9 of Global General Provisioning */ - union - { - struct - { - unsigned int reserved0 : 9; - /*! \brief 1E.C449.6:0 R/W MDIO Preamble Length [6:0] - AQ_GlobalGeneralProvisioning_HHD.u9.bits_9.mdioPreambleLength - - Default = 0x02 - - MDIO Preamble Length - - */ - unsigned int mdioPreambleLength : 7; /* 1E.C449.6:0 R/W Default = 0x02 */ - /* MDIO Preamble Length - */ - } bits_9; - uint16_t word_9; - } u9; -} AQ_GlobalGeneralProvisioning_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global NVR Provisioning: 1E.C450 */ -/* Global NVR Provisioning: 1E.C450 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global NVR Provisioning */ - union - { - struct - { - unsigned int reserved0 : 5; - /*! \brief 1E.C450.A:8 R/WPD NVR Data Length [2:0] - AQ_GlobalNvrProvisioning_HHD.u0.bits_0.nvrDataLength - - Provisionable Default = 0x4 - - NVR data length ranges from 0 bytes to 4 bytes - - - Notes: - This sets the length of the data burst used in read and write operations. - */ - unsigned int nvrDataLength : 3; /* 1E.C450.A:8 R/WPD Provisionable Default = 0x4 */ - /* NVR data length ranges from 0 bytes to 4 bytes - */ - unsigned int reserved1 : 1; - /*! \brief 1E.C450.6:4 R/WPD NVR Dummy Length [2:0] - AQ_GlobalNvrProvisioning_HHD.u0.bits_0.nvrDummyLength - - Provisionable Default = 0x0 - - NVR dummy length ranges from 0 bytes to 4 bytes - - - Notes: - This sets the length of the dummy field used in some manufacturer's read status and write status operations. - */ - unsigned int nvrDummyLength : 3; /* 1E.C450.6:4 R/WPD Provisionable Default = 0x0 */ - /* NVR dummy length ranges from 0 bytes to 4 bytes - */ - unsigned int reserved2 : 2; - /*! \brief 1E.C450.1:0 R/WPD NVR Address Length [1:0] - AQ_GlobalNvrProvisioning_HHD.u0.bits_0.nvrAddressLength - - Provisionable Default = 0x2 - - NVR address length ranges from 0 bytes up to 3 bytes - - - Notes: - This sets the length of the address field used in read and write operations. Use of this field is enabled via Bit 8 of See Global NVR Provisioning 2: Address 1E.C451 . - */ - unsigned int nvrAddressLength : 2; /* 1E.C450.1:0 R/WPD Provisionable Default = 0x2 */ - /* NVR address length ranges from 0 bytes up to 3 bytes - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global NVR Provisioning */ - union - { - struct - { - unsigned int reserved0 : 7; - /*! \brief 1E.C451.8 R/WPD NVR Address Length Override - AQ_GlobalNvrProvisioning_HHD.u1.bits_1.nvrAddressLengthOverride - - Provisionable Default = 0x0 - - 0 = NVR address length is based on the "NVR_SIZE" pin. - 1 = NVR address length is based on the See NVR Address Length [1:0] register - - - Notes: - When this bit = 0 and NVR_SIZE pin = 0, the NVR address length is 2 bytes. When this bit = 0 and the NVR_SIZE pin = 1, the NVR address length is 3 bytes. When this bit = 1 the NVR address length is from the See NVR Address Length [1:0] */ - unsigned int nvrAddressLengthOverride : 1; /* 1E.C451.8 R/WPD Provisionable Default = 0x0 */ - /* 0 = NVR address length is based on the "NVR_SIZE" pin. - 1 = NVR address length is based on the See NVR Address Length [1:0] register - */ - /*! \brief 1E.C451.7:0 R/WPD NVR Clock Divide [7:0] - AQ_GlobalNvrProvisioning_HHD.u1.bits_1.nvrClockDivide - - Provisionable Default = 0xA0 - - NVR clock divide. Clock frequency is divided by the NVR clock divide + 1 - - */ - unsigned int nvrClockDivide : 8; /* 1E.C451.7:0 R/WPD Provisionable Default = 0xA0 */ - /* NVR clock divide. Clock frequency is divided by the NVR clock divide + 1 - */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global NVR Provisioning */ - union - { - struct - { - unsigned int reserved0 : 14; - /*! \brief 1E.C452.1 R/W NVR Daisy Chain Clock Divide Override - AQ_GlobalNvrProvisioning_HHD.u2.bits_2.nvrDaisyChainClockDivideOverride - - Default = 0x0 - - 1 = Override NVR clock divide when in daisy chain master mode - - - Notes: - When in daisy chain master mode, the clock divide configuration is received from the FLASH. This bit will override the clock divide configuration from the FLASH with the See NVR Clock Divide [7:0] . */ - unsigned int nvrDaisyChainClockDivideOverride : 1; /* 1E.C452.1 R/W Default = 0x0 */ - /* 1 = Override NVR clock divide when in daisy chain master mode - */ - /*! \brief 1E.C452.0 R/W NVR Daisy Chain Disable - AQ_GlobalNvrProvisioning_HHD.u2.bits_2.nvrDaisyChainDisable - - Default = 0x0 - - 1 = Disable the Daisy Chain - - - Notes: - When in daisy chain master mode, the daisy chain and MDIO can both access the SPI. Setting this bit to 1 will disable the daisy chain from accessing the SPI and force it into a reset state. */ - unsigned int nvrDaisyChainDisable : 1; /* 1E.C452.0 R/W Default = 0x0 */ - /* 1 = Disable the Daisy Chain - */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global NVR Provisioning */ - union - { - struct - { - unsigned int reserved0 : 11; - /*! \brief 1E.C453.4 R/W NVR Reset - AQ_GlobalNvrProvisioning_HHD.u3.bits_3.nvrReset - - Default = 0x0 - - 1 = Reset SPI - - */ - unsigned int nvrReset : 1; /* 1E.C453.4 R/W Default = 0x0 */ - /* 1 = Reset SPI - */ - unsigned int reserved1 : 4; - } bits_3; - uint16_t word_3; - } u3; -} AQ_GlobalNvrProvisioning_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Reserved Provisioning: 1E.C470 */ -/* Global Reserved Provisioning: 1E.C470 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Reserved Provisioning */ - union - { - struct - { - /*! \brief 1E.C470.F R/WPD Diagnostics Select - AQ_GlobalReservedProvisioning_HHD.u0.bits_0.diagnosticsSelect - - Provisionable Default = 0x0 - - 1 = Provide Extended MDI Diagnostics Information. - 0 = Provide normal cable diagnostics - - - Notes: - These bits select what sort of cable diagnostics to perform. For regular cable diagnostics, Bit F is set to zero, and the diagnostics are triggered by setting Bit 4. For extended diagnostics, Bit F is set to 1, and the desired extended diagnostics are selected by Bits E:D. The routine is then triggered by setting Bit 4. Each of the extended diagnostic routines present data for all for MDI pairs (A, B, C, D) consecutively, and after the data for each channel is gathered Bits F:D are reset. To get the data for the next pair, Bits F:D must be set back to the desired value (which must be the same as the initial channel). This continues until the data for all channels has been gathered. The address in memory where the data is stored is given in 1E.C802 and 1E.C804. - - For the case of PSD, the structure is as follows: - Int32 info - Int16 data[Len] - Info = Len << 16 | TxEnable << 8 | Pair (0 = A, etc.) - - For TDR: - Int32 info - Int16 tdr_A[Len] - Int16 tdr_B[Len] - Int16 tdr_C[Len] - Int16 tdr_D[Len] - - Info = Len << 16 | Channel - - TDR data is from the current pair to all other pairs. - - At the end of retrieving extended MDI diag data, the part will be reset. Conversely the only way to exit this routine once it starts is to issue a PMA reset. */ - unsigned int diagnosticsSelect : 1; /* 1E.C470.F R/WPD Provisionable Default = 0x0 */ - /* 1 = Provide Extended MDI Diagnostics Information. - 0 = Provide normal cable diagnostics - */ - /*! \brief 1E.C470.E:D R/WPD Extended MDI Diagnostics Select [1:0] - AQ_GlobalReservedProvisioning_HHD.u0.bits_0.extendedMdiDiagnosticsSelect - - Provisionable Default = 0x0 - - 0x0 = TDR Data - 0x1 = RFI Channel PSD - 0x2 = Noise PSD while the local Tx is Off - 0x3 = Noise PSD while the local Tx is On - - - Notes: - These bits select what sort of cable diagnostics to perform. For regular cable diagnostics, Bit F is set to zero, and the diagnostics are triggered by setting Bit 4. For extended diagnostics, Bit F is set to 1, and the desired extended diagnostics are selected by Bits E:D. The routine is then triggered by setting Bit 4. Each of the extended diagnostic routines present data for all for MDI pairs (A, B, C, D) consecutively, and after the data for each channel is gathered Bits F:D are reset. To get the data for the next pair, Bits F:D must be set back to the desired value (which must be the same as the initial channel). This continues until the data for all channels has been gathered. The address in memory where the data is stored is given in 1E.C802 and 1E.C804. - - For the case of PSD, the structure is as follows: - Int32 info - Int16 data[Len] - Info = Len << 16 | TxEnable << 8 | Pair (0 = A, etc.) - - For TDR: - Int32 info - Int16 tdr_A[Len] - Int16 tdr_B[Len] - Int16 tdr_C[Len] - Int16 tdr_D[Len] - - Info = Len << 16 | Channel - - TDR data is from the current pair to all other pairs. - - At the end of retrieving extended MDI diag data, the part will be reset. Conversely the only way to exit this routine once it starts is to issue a PMA reset. */ - unsigned int extendedMdiDiagnosticsSelect : 2; /* 1E.C470.E:D R/WPD Provisionable Default = 0x0 */ - /* 0x0 = TDR Data - 0x1 = RFI Channel PSD - 0x2 = Noise PSD while the local Tx is Off - 0x3 = Noise PSD while the local Tx is On - */ - unsigned int reserved0 : 5; - unsigned int reserved1 : 3; - /*! \brief 1E.C470.4 R/WSC Initiate Cable Diagnostics - AQ_GlobalReservedProvisioning_HHD.u0.bits_0.initiateCableDiagnostics - - Default = 0x0 - - 1 = Perform cable diagnostics - - - Notes: - Perform cable diagnostics regardless of link state. If link is up, setting this bit will cause the link to drop while diagnostics are performed. This bit is self-clearing upon completion of the cable diagnostics. - - NOTE!! This is a processor intensive operation. Completion of this operation can also be monitored via 1E.C831.F */ - unsigned int initiateCableDiagnostics : 1; /* 1E.C470.4 R/WSC Default = 0x0 */ - /* 1 = Perform cable diagnostics - */ - unsigned int reserved2 : 4; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Reserved Provisioning */ - union - { - struct - { - unsigned int reserved0 : 9; - /*! \brief 1E.C471.6 R/WuP Enable Daisy-Chain Hop-Count Override - AQ_GlobalReservedProvisioning_HHD.u1.bits_1.enableDaisy_chainHop_countOverride - - Default = 0x0 - - 1 = Hop-count is set by Bits 5:0 - 0 = Hop-count is determined by the daisy-chain - - - Notes: - Daisy-Chain Hop-Count Override should be used during MDIO boot-load operation, as the daisy-chain hop-count does not function when the daisy-chain is disabled (1E.C452.0). Setting this bit tells the processor where in the daisy-chain it is, so that the provisioning operation will function correctly. */ - unsigned int enableDaisy_chainHop_countOverride : 1; /* 1E.C471.6 R/WuP Default = 0x0 */ - /* 1 = Hop-count is set by Bits 5:0 - 0 = Hop-count is determined by the daisy-chain - */ - /*! \brief 1E.C471.5:0 R/WuP Daisy-Chain Hop-Count Override Value [5:0] - AQ_GlobalReservedProvisioning_HHD.u1.bits_1.daisy_chainHop_countOverrideValue - - Default = 0x00 - - The value to use for the PHY's daisy-chain hop-count. Valid values are from 0 -> 47 - - - Notes: - Daisy-Chain Hop-Count Override should be used during MDIO boot-load operation, as the daisy-chain hop-count does not function when the daisy-chain is disabled (1E.C452.0). Setting this bit tells the processor where in the daisy-chain it is, so that the provisioning operation will function correctly. */ - unsigned int daisy_chainHop_countOverrideValue : 6; /* 1E.C471.5:0 R/WuP Default = 0x00 */ - /* The value to use for the PHY's daisy-chain hop-count. Valid values are from 0 -> 47 - */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global Reserved Provisioning */ - union - { - struct - { - unsigned int reserved0 : 1; - /*! \brief 1E.C472.E R/WPD Enable VDD Power Supply Tuning - AQ_GlobalReservedProvisioning_HHD.u2.bits_2.enableVddPowerSupplyTuning - - Provisionable Default = 0x0 - - 1 = Enable external VDD power supply tuning - 0 = Disable external VDD power supply tuning is disabled - - - Notes: - This bit controls whether the PHY attempts to tune the external VDD power supply via the SMBus. This bit is only operational if the external supply is present. (See 1E.C472.6) */ - unsigned int enableVddPowerSupplyTuning : 1; /* 1E.C472.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable external VDD power supply tuning - 0 = Disable external VDD power supply tuning is disabled - */ - unsigned int reserved1 : 7; - /*! \brief 1E.C472.6 R/WPD Tunable External VDD Power Supply Present - AQ_GlobalReservedProvisioning_HHD.u2.bits_2.tunableExternalVddPowerSupplyPresent - - Provisionable Default = 0x0 - - 1 = Tunable external VDD power supply present - 0 = No tunable external VDD power supply present - - - Notes: - This bit must be set if tuning of external power supply is desired. */ - unsigned int tunableExternalVddPowerSupplyPresent : 1; /* 1E.C472.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = Tunable external VDD power supply present - 0 = No tunable external VDD power supply present - */ - /*! \brief 1E.C472.5:2 R/WPD External VDD Change Request [3:0] - AQ_GlobalReservedProvisioning_HHD.u2.bits_2.externalVddChangeRequest - - Provisionable Default = 0x0 - - The amount of VDD change requested by firmware, in mV (2's complement value). - - */ - unsigned int externalVddChangeRequest : 4; /* 1E.C472.5:2 R/WPD Provisionable Default = 0x0 */ - /* The amount of VDD change requested by firmware, in mV (2's complement value). - */ - /*! \brief 1E.C472.1 R/WPDuP Enable XENPAK Register Space - AQ_GlobalReservedProvisioning_HHD.u2.bits_2.enableXenpakRegisterSpace - - Provisionable Default = 0x0 - - 1 = XENPAK register space enabled - 0 = XENPAK register space disabled - - */ - unsigned int enableXenpakRegisterSpace : 1; /* 1E.C472.1 R/WPDuP Provisionable Default = 0x0 */ - /* 1 = XENPAK register space enabled - 0 = XENPAK register space disabled - */ - /*! \brief 1E.C472.0 R/WPDuP Enable 5th Channel RFI Cancellation - AQ_GlobalReservedProvisioning_HHD.u2.bits_2.enable_5thChannelRfiCancellation - - Provisionable Default = 0x0 - - 1 = 5th channel and RFI cancellers operation enabled - 0 = 5th channel AFE is powered down, 5th channel digital is clock gated, RFI cancellers are disabled - - - Notes: - Note: The value of this bit at the time of Autonegotiation sets the local PHY behavior until the next time Autonegotiation occurs. */ - unsigned int enable_5thChannelRfiCancellation : 1; /* 1E.C472.0 R/WPDuP Provisionable Default = 0x0 */ - /* 1 = 5th channel and RFI cancellers operation enabled - 0 = 5th channel AFE is powered down, 5th channel digital is clock gated, RFI cancellers are disabled - */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global Reserved Provisioning */ - union - { - struct - { - unsigned int reserved0 : 5; - /*! \brief 1E.C473.A:8 R/WPD Rate Transition Request [2:0] - AQ_GlobalReservedProvisioning_HHD.u3.bits_3.rateTransitionRequest - - Provisionable Default = 0x0 - - 0 = No Transition - 1 = Reserved - 2 = Reserved - 3 = Retrain at 10G - 4 = Retrain at 5G - 5 = Retrain at 2.5G - 6 = Retrain at 1G - 7 = Reserved - - */ - unsigned int rateTransitionRequest : 3; /* 1E.C473.A:8 R/WPD Provisionable Default = 0x0 */ - /* 0 = No Transition - 1 = Reserved - 2 = Reserved - 3 = Retrain at 10G - 4 = Retrain at 5G - 5 = Retrain at 2.5G - 6 = Retrain at 1G - 7 = Reserved - */ - /*! \brief 1E.C473.7:0 R/WPD Training SNR [7:0] - AQ_GlobalReservedProvisioning_HHD.u3.bits_3.trainingSNR - - Provisionable Default = 0x00 - - SNR during 10G training on the worst channel. SNR is in steps of 0.1dB - - - Notes: - The SNR margin that is enjoyed by the worst channel, over and above the minimum SNR required to operate at a BER of 10-12. It is reported with 0.1 dB of resolution to an accuracy of 0.5 dB within the range of -12.7 dB to 12.7 dB. The number is in offset binary, with 0.0 dB represented by 0x8000. */ - unsigned int trainingSNR : 8; /* 1E.C473.7:0 R/WPD Provisionable Default = 0x00 */ - /* SNR during 10G training on the worst channel. SNR is in steps of 0.1dB - */ - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of Global Reserved Provisioning */ - union - { - struct - { - /*! \brief 1E.C474.F:1 R/WPD Reserved Provisioning 5 [F:1] - AQ_GlobalReservedProvisioning_HHD.u4.bits_4.reservedProvisioning_5 - - Provisionable Default = 0x0000 - - Reserved for future use - - */ - unsigned int reservedProvisioning_5 : 15; /* 1E.C474.F:1 R/WPD Provisionable Default = 0x0000 */ - /* Reserved for future use - */ - /*! \brief 1E.C474.0 R/W NVR Daisy Chain Kickstart - AQ_GlobalReservedProvisioning_HHD.u4.bits_4.nvrDaisyChainKickstart - - Default = 0x0 - - 1 = Kickstart the Daisy Chain - - - Notes: - When in daisy chain master mode, the PHY0 can kickstart the daisy chain. The kickstart will not reload the IRAM/DRAM or reset the uP for PHY0. It will just read the FLASH and transfer the FLASH data to the daisy chain. */ - unsigned int nvrDaisyChainKickstart : 1; /* 1E.C474.0 R/W Default = 0x0 */ - /* 1 = Kickstart the Daisy Chain - */ - } bits_4; - uint16_t word_4; - } u4; - /*! \brief Union for bit and word level access of word 5 of Global Reserved Provisioning */ - union - { - struct - { - unsigned int reserved0 : 2; - /*! \brief 1E.C475.D R/WPD Smart Power-Down Status - AQ_GlobalReservedProvisioning_HHD.u5.bits_5.smartPower_downStatus - - Provisionable Default = 0x0 - - 1 = Smart Power-Down Active - 0 = Smart Power-Down Inactive - - */ - unsigned int smartPower_downStatus : 1; /* 1E.C475.D R/WPD Provisionable Default = 0x0 */ - /* 1 = Smart Power-Down Active - 0 = Smart Power-Down Inactive - */ - /*! \brief 1E.C475.C R/WPD Reserved Provisioning 6 - AQ_GlobalReservedProvisioning_HHD.u5.bits_5.reservedProvisioning_6 - - Provisionable Default = 0x0 - - Internal reserved - do not modify - - */ - unsigned int reservedProvisioning_6 : 1; /* 1E.C475.C R/WPD Provisionable Default = 0x0 */ - /* Internal reserved - do not modify - */ - /*! \brief 1E.C475.B R/WPD CFR LP Disable Timer - AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrLpDisableTimer - - Provisionable Default = 0x0 - - 1 = Link partner requires cfr_disable timer - 0 = Link partner does not require cfr_disable timer - - */ - unsigned int cfrLpDisableTimer : 1; /* 1E.C475.B R/WPD Provisionable Default = 0x0 */ - /* 1 = Link partner requires cfr_disable timer - 0 = Link partner does not require cfr_disable timer - */ - /*! \brief 1E.C475.A R/WPD CFR LP Extended Maxwait - AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrLpExtendedMaxwait - - Provisionable Default = 0x0 - - 1 = Link partner requires extended maxwait - 0 = Link partner does not require extended maxwait - - */ - unsigned int cfrLpExtendedMaxwait : 1; /* 1E.C475.A R/WPD Provisionable Default = 0x0 */ - /* 1 = Link partner requires extended maxwait - 0 = Link partner does not require extended maxwait - */ - /*! \brief 1E.C475.9 R/WPD CFR LP THP - AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrLpTHP - - Provisionable Default = 0x0 - - 1 = Link partner requires local PHY to enable THP - 0 = Link partner does not require local PHY to enable THP - - */ - unsigned int cfrLpTHP : 1; /* 1E.C475.9 R/WPD Provisionable Default = 0x0 */ - /* 1 = Link partner requires local PHY to enable THP - 0 = Link partner does not require local PHY to enable THP - */ - /*! \brief 1E.C475.8 R/WPD CFR LP Support - AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrLpSupport - - Provisionable Default = 0x0 - - 1 = Link partner supports Cisco Fast Retrain - 0 = Link partner does support Cisco Fast Retrain - - */ - unsigned int cfrLpSupport : 1; /* 1E.C475.8 R/WPD Provisionable Default = 0x0 */ - /* 1 = Link partner supports Cisco Fast Retrain - 0 = Link partner does support Cisco Fast Retrain - */ - /*! \brief 1E.C475.7 R/WPD CFR Disable Timer - AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrDisableTimer - - Provisionable Default = 0x0 - - 1 = Local PHY requires cfr_disable timer - 0 = Local PHY does not require cfr_disable timer - - */ - unsigned int cfrDisableTimer : 1; /* 1E.C475.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = Local PHY requires cfr_disable timer - 0 = Local PHY does not require cfr_disable timer - */ - /*! \brief 1E.C475.6 R/WPD CFR Extended Maxwait - AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrExtendedMaxwait - - Provisionable Default = 0x0 - - 1 = Local PHY requires extended maxwait - 0 = Local PHY does not require extended maxwait - - */ - unsigned int cfrExtendedMaxwait : 1; /* 1E.C475.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = Local PHY requires extended maxwait - 0 = Local PHY does not require extended maxwait - */ - /*! \brief 1E.C475.5 R/WPD CFR THP - AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrTHP - - Provisionable Default = 0x0 - - 1 = Local PHY requires local PHY to enable THP - 0 = Local PHY does not require local PHY to enable THP - - */ - unsigned int cfrTHP : 1; /* 1E.C475.5 R/WPD Provisionable Default = 0x0 */ - /* 1 = Local PHY requires local PHY to enable THP - 0 = Local PHY does not require local PHY to enable THP - */ - /*! \brief 1E.C475.4 R/WPD CFR Support - AQ_GlobalReservedProvisioning_HHD.u5.bits_5.cfrSupport - - Provisionable Default = 0x0 - - 1 = Local PHY supports Cisco Fast Retrain - 0 = Local PHY does support Cisco Fast Retrain - - */ - unsigned int cfrSupport : 1; /* 1E.C475.4 R/WPD Provisionable Default = 0x0 */ - /* 1 = Local PHY supports Cisco Fast Retrain - 0 = Local PHY does support Cisco Fast Retrain - */ - /*! \brief 1E.C475.3 R/WPD Deadlock Avoidance Enable - AQ_GlobalReservedProvisioning_HHD.u5.bits_5.deadlockAvoidanceEnable - - Provisionable Default = 0x0 - - 1 = SPD with deadlock avoidance: PHY transmits autonegotiation pulses (FLPs) at a slower rate (~ 1 FLP/ 100ms) than specified by autonegotiation standard (~1 FLP / 8.25ms). Receiver is active and able to detect the pulses. - 0 = SPD without deadlock avoidance: PHY transmitter is shut down, no autonegotiation pulses are sent on the line but the receiver is active and able to detect the pulses - - */ - unsigned int deadlockAvoidanceEnable : 1; /* 1E.C475.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = SPD with deadlock avoidance: PHY transmits autonegotiation pulses (FLPs) at a slower rate (~ 1 FLP/ 100ms) than specified by autonegotiation standard (~1 FLP / 8.25ms). Receiver is active and able to detect the pulses. - 0 = SPD without deadlock avoidance: PHY transmitter is shut down, no autonegotiation pulses are sent on the line but the receiver is active and able to detect the pulses - */ - /*! \brief 1E.C475.2 R/WPD Smart Power-Down Enable - AQ_GlobalReservedProvisioning_HHD.u5.bits_5.smartPower_downEnable - - Provisionable Default = 0x0 - - 1 = Enable smart power down mode - 0 = Smart power-down mode disabled - - - Notes: - Smart power down (SPD) is the lowest power mode at which PHY is able to autonegotiate. SPD can be enabled with bit 1E.C475.2 */ - unsigned int smartPower_downEnable : 1; /* 1E.C475.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable smart power down mode - 0 = Smart power-down mode disabled - */ - unsigned int reserved1 : 2; - } bits_5; - uint16_t word_5; - } u5; - /*! \brief Dummy union to fill space in the structure Global Reserved Provisioning */ - union - { - struct - { - unsigned int reserved : 16; - } bits_6; - uint16_t word_6; - } u6; - /*! \brief Dummy union to fill space in the structure Global Reserved Provisioning */ - union - { - struct - { - unsigned int reserved : 16; - } bits_7; - uint16_t word_7; - } u7; - /*! \brief Union for bit and word level access of word 8 of Global Reserved Provisioning */ - union - { - struct - { - /*! \brief 1E.C478.F R/WPD DTE Enable - AQ_GlobalReservedProvisioning_HHD.u8.bits_8.dteEnable - - Provisionable Default = 0x0 - - 1 = Enable DTE - 0 = Disable DTE - - */ - unsigned int dteEnable : 1; /* 1E.C478.F R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable DTE - 0 = Disable DTE - */ - /*! \brief 1E.C478.E:B R/WPD DTE Drop Reporting Timer [3:0] - AQ_GlobalReservedProvisioning_HHD.u8.bits_8.dteDropReportingTimer - - Provisionable Default = 0x0 - - Number of seconds between loss of link partner filter and assertion of no-power-needed state, in 5 second increments (e.g. 0x4 = 20 seconds). - - - Notes: - These bits are used to set how long the PHY waits after it no longer detects the link partner filter before declaring that power is not needed. */ - unsigned int dteDropReportingTimer : 4; /* 1E.C478.E:B R/WPD Provisionable Default = 0x0 */ - /* Number of seconds between loss of link partner filter and assertion of no-power-needed state, in 5 second increments (e.g. 0x4 = 20 seconds). - */ - /*! \brief 1E.C478.A:0 R/WPD Reserved Provisioning 9 [A:0] - AQ_GlobalReservedProvisioning_HHD.u8.bits_8.reservedProvisioning_9 - - Provisionable Default = 0x000 - - Reserved for future use - - */ - unsigned int reservedProvisioning_9 : 11; /* 1E.C478.A:0 R/WPD Provisionable Default = 0x000 */ - /* Reserved for future use - */ - } bits_8; - uint16_t word_8; - } u8; - /*! \brief Union for bit and word level access of word 9 of Global Reserved Provisioning */ - union - { - struct - { - /*! \brief 1E.C479.F R/WPD Power Up Stall - AQ_GlobalReservedProvisioning_HHD.u9.bits_9.powerUpStall - - Provisionable Default = 0x0 - - 1 = Stall FW at Power Up - 0 = Unstall the FW - - - Notes: - This bit needs to be provisioned in Power Up Init for firmware to stall. */ - unsigned int powerUpStall : 1; /* 1E.C479.F R/WPD Provisionable Default = 0x0 */ - /* 1 = Stall FW at Power Up - 0 = Unstall the FW - */ - /*! \brief 1E.C479.E:0 R/WPD Reserved Provisioning 10 [E:0] - AQ_GlobalReservedProvisioning_HHD.u9.bits_9.reservedProvisioning_10 - - Provisionable Default = 0x0000 - - Reserved for future use - - */ - unsigned int reservedProvisioning_10 : 15; /* 1E.C479.E:0 R/WPD Provisionable Default = 0x0000 */ - /* Reserved for future use - */ - } bits_9; - uint16_t word_9; - } u9; - /*! \brief Union for bit and word level access of word 10 of Global Reserved Provisioning */ - union - { - struct - { - /*! \brief 1E.C47A.F:B R/WPD Loopback Control [4:0] - AQ_GlobalReservedProvisioning_HHD.u10.bits_10.loopbackControl - - Provisionable Default = 0x00 - - 0x00 = No loopback - 0x01 = System Interface - System Loopback - 0x02 = System Interface - System Loopback with Passthrough - 0x03 = System Interface - Network Loopback - 0x04 = System Interface - Network Loopback with Passthrough - 0x05 = System Interface - Network Loopback with Passthrough and Merge - 0x06 = System Interface - Peer-to-peer loopback - 0x07 - 0x08 = Reserved - 0x09 = Network Interface - System Loopback - 0x0A = Network Interface - System Loopback with Passthrough - 0x0B = Network Interface - Network Loopback - 0x0C = Network Interface - Network Loopback with Passthrough - 0x0D = Network Interface - Peer-to-peer loopback - 0x0E - 0x0F = Reserved - 0x10 = Cross-connect System Loopback - 0x11 = Cross-connect Network Loopback - 0x12 - 0x13 = Reserved - 0x14 = Network Interface - System Loopback via Loopback Plug - 0x15 - 0x1F = Reserved - - - Notes: - These bits, in conjunction with the chip configuration and the rate (Bits 1:0), select the loopback to configure for the chip. Setting one of these loopbacks provisions the chip for the specified loopback. Upon clearing the loopback, the chip returns to it's configuration prior to entering loopback (irregardless of whether other loopbacks were selected after the initial loopback). - - NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F. - - The controls in this register are identical to, and mirrored with, the controls in 4.C444. - */ - unsigned int loopbackControl : 5; /* 1E.C47A.F:B R/WPD Provisionable Default = 0x00 */ - /* 0x00 = No loopback - 0x01 = System Interface - System Loopback - 0x02 = System Interface - System Loopback with Passthrough - 0x03 = System Interface - Network Loopback - 0x04 = System Interface - Network Loopback with Passthrough - 0x05 = System Interface - Network Loopback with Passthrough and Merge - 0x06 = System Interface - Peer-to-peer loopback - 0x07 - 0x08 = Reserved - 0x09 = Network Interface - System Loopback - 0x0A = Network Interface - System Loopback with Passthrough - 0x0B = Network Interface - Network Loopback - 0x0C = Network Interface - Network Loopback with Passthrough - 0x0D = Network Interface - Peer-to-peer loopback - 0x0E - 0x0F = Reserved - 0x10 = Cross-connect System Loopback - 0x11 = Cross-connect Network Loopback - 0x12 - 0x13 = Reserved - 0x14 = Network Interface - System Loopback via Loopback Plug - 0x15 - 0x1F = Reserved - */ - /*! \brief 1E.C47A.A:6 R/WPD Reserved Provisioning 11 [4:0] - AQ_GlobalReservedProvisioning_HHD.u10.bits_10.reservedProvisioning_11 - - Provisionable Default = 0x00 - - Reserved for future use - - */ - unsigned int reservedProvisioning_11 : 5; /* 1E.C47A.A:6 R/WPD Provisionable Default = 0x00 */ - /* Reserved for future use - */ - /*! \brief 1E.C47A.5 R/WPD MDI Packet Generation - AQ_GlobalReservedProvisioning_HHD.u10.bits_10.mdiPacketGeneration - - Provisionable Default = 0x0 - - 1 = CRPAT packet generation out MDI interface - 0 = No CRPAT packet generation out MDI interface - - - Notes: - Selecting this mode of operation causes the CRPAT packet generator in the PHY to output on the MDI interface at the selected rate. - - NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F - - The controls in this register are identical to, and mirrored with, the controls in 4.C444. */ - unsigned int mdiPacketGeneration : 1; /* 1E.C47A.5 R/WPD Provisionable Default = 0x0 */ - /* 1 = CRPAT packet generation out MDI interface - 0 = No CRPAT packet generation out MDI interface - */ - /*! \brief 1E.C47A.4 R/WPD Look-Aside Port Packet Generation - AQ_GlobalReservedProvisioning_HHD.u10.bits_10.look_asidePortPacketGeneration - - Provisionable Default = 0x0 - - 1 = CRPAT packet generation out 10G look-aside interface (KR0) - 0 = No CRPAT packet generation out 10G look-aside interface (KR0) - - - Notes: - Selecting this mode of operation causes the CRPAT packet generator in the PHY to output on KR0. - - NOTE!! This only functions if KR1 (SERDES2) is selected as the system interface in (4.C441.F:E). - - NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F - - The controls in this register are identical to, and mirrored with, the controls in 4.C444. */ - unsigned int look_asidePortPacketGeneration : 1; /* 1E.C47A.4 R/WPD Provisionable Default = 0x0 */ - /* 1 = CRPAT packet generation out 10G look-aside interface (KR0) - 0 = No CRPAT packet generation out 10G look-aside interface (KR0) - */ - /*! \brief 1E.C47A.3 R/WPD System I/F Packet Generation - AQ_GlobalReservedProvisioning_HHD.u10.bits_10.systemI_fPacketGeneration - - Provisionable Default = 0x0 - - 1 = CRPAT packet generation out 10G system interface - 0 = No CRPAT packet generation out 10G system interface - - - Notes: - Selecting this mode of operation causes the CRPAT packet generator in the PHY to output CRPAT packets on the selected 10G system interface (4.C441.F:E) - - NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F - - The controls in this register are identical to, and mirrored with, the controls in 4.C444. */ - unsigned int systemI_fPacketGeneration : 1; /* 1E.C47A.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = CRPAT packet generation out 10G system interface - 0 = No CRPAT packet generation out 10G system interface - */ - /*! \brief 1E.C47A.2 R/WPD Reserved Provisioning 11a - AQ_GlobalReservedProvisioning_HHD.u10.bits_10.reservedProvisioning_11a - - Provisionable Default = 0x0 - - Reserved for future use - - */ - unsigned int reservedProvisioning_11a : 1; /* 1E.C47A.2 R/WPD Provisionable Default = 0x0 */ - /* Reserved for future use - */ - /*! \brief 1E.C47A.1:0 R/WPD Rate [1:0] - AQ_GlobalReservedProvisioning_HHD.u10.bits_10.rate - - Provisionable Default = 0x0 - - 0x3 = 10G - 0x2 = 1G - 0x1 = 100M - 0x0 = reserved - - - Notes: - These bits select the rate for the loopback and packet generation. SERDES configuration, as well autonegotiation is controlled accordingly when a loopback is selected. For instance, if 100M system loopback on the network interface is selected, SGMII on the system interface is enabled to connect at 100M, and if passthrough is enabled 100BASE-TX will be the only advertised rate and will force a re-autonegotiation if not already connected at 100M. - - NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F - - The controls in this register are identical to, and mirrored with, the controls in 4.C444. */ - unsigned int rate : 2; /* 1E.C47A.1:0 R/WPD Provisionable Default = 0x0 */ - /* 0x3 = 10G - 0x2 = 1G - 0x1 = 100M - 0x0 = reserved - */ - } bits_10; - uint16_t word_10; - } u10; - /*! \brief Union for bit and word level access of word 11 of Global Reserved Provisioning */ - union - { - struct - { - /*! \brief 1E.C47B.F:2 R/WPD Reserved Provisioning 12 [D:0] - AQ_GlobalReservedProvisioning_HHD.u11.bits_11.reservedProvisioning_12 - - Provisionable Default = 0x0000 - - Reserved for future use - - */ - unsigned int reservedProvisioning_12 : 14; /* 1E.C47B.F:2 R/WPD Provisionable Default = 0x0000 */ - /* Reserved for future use - */ - /*! \brief 1E.C47B.1 R/WPD Enable MACSec - AQ_GlobalReservedProvisioning_HHD.u11.bits_11.enableMacsec - - Provisionable Default = 0x0 - - 1 = MACSec functionality is enabled - 0 = MACSec functionality is disabled - - - Notes: - If this bit is 1, the PTP/SEC block will be included in the data path, regardless of operating mode. */ - unsigned int enableMacsec : 1; /* 1E.C47B.1 R/WPD Provisionable Default = 0x0 */ - /* 1 = MACSec functionality is enabled - 0 = MACSec functionality is disabled - */ - /*! \brief 1E.C47B.0 R/WPD Enable PTP - AQ_GlobalReservedProvisioning_HHD.u11.bits_11.enablePtp - - Provisionable Default = 0x0 - - 1 = PTP functionality is enabled - 0 = PTP functionality is disabled - - - Notes: - If this bit is 1, the PTP/SEC block will be included in the data path, regardless of operating mode. */ - unsigned int enablePtp : 1; /* 1E.C47B.0 R/WPD Provisionable Default = 0x0 */ - /* 1 = PTP functionality is enabled - 0 = PTP functionality is disabled - */ - } bits_11; - uint16_t word_11; - } u11; -} AQ_GlobalReservedProvisioning_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief PIF Mailbox Control: 1E.C47C */ -/* PIF Mailbox Control: 1E.C47C */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of PIF Mailbox Control */ - union - { - struct - { - /*! \brief 1E.C47C.F:0 R/WPDuP PIF Mailbox Address [F:0] - AQ_PifMailboxControl_HHD.u0.bits_0.pifMailboxAddress - - Provisionable Default = 0x0000 - - The least 16 bits of the PIF address to read or write. - - */ - unsigned int pifMailboxAddress : 16; /* 1E.C47C.F:0 R/WPDuP Provisionable Default = 0x0000 */ - /* The least 16 bits of the PIF address to read or write. - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of PIF Mailbox Control */ - union - { - struct - { - /*! \brief 1E.C47D.F:0 R/WPDuP PIF Mailbox Data [F:0] - AQ_PifMailboxControl_HHD.u1.bits_1.pifMailboxData - - Provisionable Default = 0x0000 - - The data to be written, or that had been read. - - */ - unsigned int pifMailboxData : 16; /* 1E.C47D.F:0 R/WPDuP Provisionable Default = 0x0000 */ - /* The data to be written, or that had been read. - */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of PIF Mailbox Control */ - union - { - struct - { - /*! \brief 1E.C47E.F:C R/WPD Reserved PIF Mailbox Control 3 [3:0] - AQ_PifMailboxControl_HHD.u2.bits_2.reservedPifMailboxControl_3 - - Provisionable Default = 0x0 - - Reserved for future use - - */ - unsigned int reservedPifMailboxControl_3 : 4; /* 1E.C47E.F:C R/WPD Provisionable Default = 0x0 */ - /* Reserved for future use - */ - /*! \brief 1E.C47E.B:8 R/WPDuP PIF Mailbox Command Type [3:0] - AQ_PifMailboxControl_HHD.u2.bits_2.pifMailboxCommandType - - Provisionable Default = 0x0 - - 0 = No Action - 1 = Read - 2 = Write - - - Notes: - System SW writes non-zero value to start a PIF command. */ - unsigned int pifMailboxCommandType : 4; /* 1E.C47E.B:8 R/WPDuP Provisionable Default = 0x0 */ - /* 0 = No Action - 1 = Read - 2 = Write - */ - /*! \brief 1E.C47E.7:0 R/WPDuP PIF Mailbox MMD [7:0] - AQ_PifMailboxControl_HHD.u2.bits_2.pifMailboxMMD - - Provisionable Default = 0x00 - - MMD (upper 8 bits) of the PID address to read or write. - - */ - unsigned int pifMailboxMMD : 8; /* 1E.C47E.7:0 R/WPDuP Provisionable Default = 0x00 */ - /* MMD (upper 8 bits) of the PID address to read or write. - */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of PIF Mailbox Control */ - union - { - struct - { - /*! \brief 1E.C47F.F:4 R/WPD Reserved PIF Mailbox Control 4 [B:0] - AQ_PifMailboxControl_HHD.u3.bits_3.reservedPifMailboxControl_4 - - Provisionable Default = 0x000 - - Reserved for future use - - */ - unsigned int reservedPifMailboxControl_4 : 12; /* 1E.C47F.F:4 R/WPD Provisionable Default = 0x000 */ - /* Reserved for future use - */ - /*! \brief 1E.C47F.3:0 R/WPDuP PIF Mailbox Command Status [3:0] - AQ_PifMailboxControl_HHD.u3.bits_3.pifMailboxCommandStatus - - Provisionable Default = 0x0 - - 0 = Idle - 1 = Command completed - 2 = Command did not complete - - - Notes: - System SW should write 0 before writing Command Type to clear completion status */ - unsigned int pifMailboxCommandStatus : 4; /* 1E.C47F.3:0 R/WPDuP Provisionable Default = 0x0 */ - /* 0 = Idle - 1 = Command completed - 2 = Command did not complete - */ - } bits_3; - uint16_t word_3; - } u3; -} AQ_PifMailboxControl_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global SMBus 0 Provisioning: 1E.C485 */ -/* Global SMBus 0 Provisioning: 1E.C485 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global SMBus 0 Provisioning */ - union - { - struct - { - unsigned int reserved0 : 8; - /*! \brief 1E.C485.7:1 R/W SMB 0 Slave Address [7:1] - AQ_GlobalSmbus_0Provisioning_HHD.u0.bits_0.smb_0SlaveAddress - - Default = 0x00 - - SMB slave address configuration - - */ - unsigned int smb_0SlaveAddress : 7; /* 1E.C485.7:1 R/W Default = 0x00 */ - /* SMB slave address configuration - */ - unsigned int reserved1 : 1; - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalSmbus_0Provisioning_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global SMBus 1 Provisioning: 1E.C495 */ -/* Global SMBus 1 Provisioning: 1E.C495 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global SMBus 1 Provisioning */ - union - { - struct - { - unsigned int reserved0 : 8; - /*! \brief 1E.C495.7:1 R/W SMB 1 Slave Address [7:1] - AQ_GlobalSmbus_1Provisioning_HHD.u0.bits_0.smb_1SlaveAddress - - Default = 0x00 - - SMB slave address configuration - - */ - unsigned int smb_1SlaveAddress : 7; /* 1E.C495.7:1 R/W Default = 0x00 */ - /* SMB slave address configuration - */ - unsigned int reserved1 : 1; - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalSmbus_1Provisioning_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global EEE Provisioning: 1E.C4A0 */ -/* Global EEE Provisioning: 1E.C4A0 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global EEE Provisioning */ - union - { - struct - { - unsigned int reserved0 : 15; - /*! \brief 1E.C4A0.0 R/WPD EEE Mode - AQ_GlobalEeeProvisioning_HHD.u0.bits_0.eeeMode - - Provisionable Default = 0x0 - - 1 = EEE mode of operation - - - Notes: - EEE mode of operation (0=disable, 1=enable, default:0) */ - unsigned int eeeMode : 1; /* 1E.C4A0.0 R/WPD Provisionable Default = 0x0 */ - /* 1 = EEE mode of operation - */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalEeeProvisioning_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Cable Diagnostic Status: 1E.C800 */ -/* Global Cable Diagnostic Status: 1E.C800 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Cable Diagnostic Status */ - union - { - struct - { - unsigned int reserved0 : 1; - /*! \brief 1E.C800.E:C RO Pair A Status [2:0] - AQ_GlobalCableDiagnosticStatus_HHD.u0.bits_0.pairAStatus - - - - [F:D] - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair D - 010= Connected to Pair C - 001= Connected to Pair B - 000= OK - - Notes: - This register summarizes the worst impairment on Pair A. */ - unsigned int pairAStatus : 3; /* 1E.C800.E:C RO */ - /* [F:D] - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair D - 010= Connected to Pair C - 001= Connected to Pair B - 000= OK */ - unsigned int reserved1 : 1; - /*! \brief 1E.C800.A:8 RO Pair B Status [2:0] - AQ_GlobalCableDiagnosticStatus_HHD.u0.bits_0.pairBStatus - - - - [C:A] - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair A - 010= Connected to Pair D - 001= Connected to Pair C - 000= OK - - Notes: - This register summarizes the worst impairment on Pair B. */ - unsigned int pairBStatus : 3; /* 1E.C800.A:8 RO */ - /* [C:A] - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair A - 010= Connected to Pair D - 001= Connected to Pair C - 000= OK */ - unsigned int reserved2 : 1; - /*! \brief 1E.C800.6:4 RO Pair C Status [2:0] - AQ_GlobalCableDiagnosticStatus_HHD.u0.bits_0.pairCStatus - - - - [9:7] - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair B - 010= Connected to Pair A - 001= Connected to Pair D - 000= OK - - Notes: - This register summarizes the worst impairment on Pair C. */ - unsigned int pairCStatus : 3; /* 1E.C800.6:4 RO */ - /* [9:7] - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair B - 010= Connected to Pair A - 001= Connected to Pair D - 000= OK */ - unsigned int reserved3 : 1; - /*! \brief 1E.C800.2:0 RO Pair D Status [2:0] - AQ_GlobalCableDiagnosticStatus_HHD.u0.bits_0.pairDStatus - - - - [6:4] - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair C - 010= Connected to Pair B - 001= Connected to Pair A - 000= OK - - Notes: - This register summarizes the worst impairment on Pair D. */ - unsigned int pairDStatus : 3; /* 1E.C800.2:0 RO */ - /* [6:4] - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 011= Connected to Pair C - 010= Connected to Pair B - 001= Connected to Pair A - 000= OK */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C801.F:8 RO Pair A Reflection #1 [7:0] - AQ_GlobalCableDiagnosticStatus_HHD.u1.bits_1.pairAReflection_1 - - - - The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair A - - Notes: - The distance to this reflection is given in See Global Reserved Status 1: Address 1E.C870 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairAReflection_1 : 8; /* 1E.C801.F:8 RO */ - /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair A */ - /*! \brief 1E.C801.7:0 RO Pair A Reflection #2 [7:0] - AQ_GlobalCableDiagnosticStatus_HHD.u1.bits_1.pairAReflection_2 - - - - The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair A - - Notes: - The distance to this reflection is given in See Global Reserved Status 1: Address 1E.C870 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairAReflection_2 : 8; /* 1E.C801.7:0 RO */ - /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair A */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C802.F:0 RO Impulse Response MSW [F:0] - AQ_GlobalCableDiagnosticStatus_HHD.u2.bits_2.impulseResponseMSW - - - - The MSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type in 1E.C470.E:D - - Notes: - See 1E.C470 for more information */ - unsigned int impulseResponseMSW : 16; /* 1E.C802.F:0 RO */ - /* The MSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type in 1E.C470.E:D */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C803.F:8 RO Pair B Reflection #1 [7:0] - AQ_GlobalCableDiagnosticStatus_HHD.u3.bits_3.pairBReflection_1 - - - - The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair B - - Notes: - The distance to this reflection is given in See Global Reserved Status 2: Address 1E.C871 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairBReflection_1 : 8; /* 1E.C803.F:8 RO */ - /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair B */ - /*! \brief 1E.C803.7:0 RO Pair B Reflection #2 [7:0] - AQ_GlobalCableDiagnosticStatus_HHD.u3.bits_3.pairBReflection_2 - - - - The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair B - - Notes: - The distance to this reflection is given in See Global Reserved Status 2: Address 1E.C871 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairBReflection_2 : 8; /* 1E.C803.7:0 RO */ - /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair B */ - } bits_3; - uint16_t word_3; - } u3; - /*! \brief Union for bit and word level access of word 4 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C804.F:0 RO Impulse Response LSW [F:0] - AQ_GlobalCableDiagnosticStatus_HHD.u4.bits_4.impulseResponseLSW - - - - The LSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type specified in 1E.C470.E:D - - Notes: - See 1E.C470 for more information */ - unsigned int impulseResponseLSW : 16; /* 1E.C804.F:0 RO */ - /* The LSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type specified in 1E.C470.E:D */ - } bits_4; - uint16_t word_4; - } u4; - /*! \brief Union for bit and word level access of word 5 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C805.F:8 RO Pair C Reflection #1 [7:0] - AQ_GlobalCableDiagnosticStatus_HHD.u5.bits_5.pairCReflection_1 - - - - The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair C - - Notes: - The distance to this reflection is given in See Global Reserved Status 3: Address 1E.C872 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairCReflection_1 : 8; /* 1E.C805.F:8 RO */ - /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair C */ - /*! \brief 1E.C805.7:0 RO Pair C Reflection #2 [7:0] - AQ_GlobalCableDiagnosticStatus_HHD.u5.bits_5.pairCReflection_2 - - - - The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair C - - Notes: - The distance to this reflection is given in See Global Reserved Status 3: Address 1E.C872 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairCReflection_2 : 8; /* 1E.C805.7:0 RO */ - /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair C */ - } bits_5; - uint16_t word_5; - } u5; - /*! \brief Union for bit and word level access of word 6 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C806.F:0 RO Reserved 1 [F:0] - AQ_GlobalCableDiagnosticStatus_HHD.u6.bits_6.reserved_1 - - - - Reserved for future use - */ - unsigned int reserved_1 : 16; /* 1E.C806.F:0 RO */ - /* Reserved for future use */ - } bits_6; - uint16_t word_6; - } u6; - /*! \brief Union for bit and word level access of word 7 of Global Cable Diagnostic Status */ - union - { - struct - { - /*! \brief 1E.C807.F:8 RO Pair D Reflection #1 [7:0] - AQ_GlobalCableDiagnosticStatus_HHD.u7.bits_7.pairDReflection_1 - - - - The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair D - - Notes: - The distance to this reflection is given in See Global Reserved Status 4: Address 1E.C873 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairDReflection_1 : 8; /* 1E.C807.F:8 RO */ - /* The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair D */ - /*! \brief 1E.C807.7:0 RO Pair D Reflection #2 [7:0] - AQ_GlobalCableDiagnosticStatus_HHD.u7.bits_7.pairDReflection_2 - - - - The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair D - - Notes: - The distance to this reflection is given in See Global Reserved Status 4: Address 1E.C873 . A value of zero indicates that this reflection does not exist or was not computed. */ - unsigned int pairDReflection_2 : 8; /* 1E.C807.7:0 RO */ - /* The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair D */ - } bits_7; - uint16_t word_7; - } u7; -} AQ_GlobalCableDiagnosticStatus_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Thermal Status: 1E.C820 */ -/* Global Thermal Status: 1E.C820 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Thermal Status */ - union - { - struct - { - /*! \brief 1E.C820.F:0 RO Temperature [F:0] - AQ_GlobalThermalStatus_HHD.u0.bits_0.temperature - - - - [F:0] of temperature - - - Notes: - 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40 degreesC = 0xD800. Default is 70 degreesC. This is a mirror of the XENPAK register 1.A060 - 1.A061. The mirror is performed in H/W. */ - unsigned int temperature : 16; /* 1E.C820.F:0 RO */ - /* [F:0] of temperature - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Thermal Status */ - union - { - struct - { - unsigned int reserved0 : 15; - /*! \brief 1E.C821.0 RO Temperature Ready - AQ_GlobalThermalStatus_HHD.u1.bits_1.temperatureReady - - - - 1 = Temperature measurement is valid - - - Notes: - This is a mirror of the XENPAK register 1.A06E. */ - unsigned int temperatureReady : 1; /* 1E.C821.0 RO */ - /* 1 = Temperature measurement is valid - */ - } bits_1; - uint16_t word_1; - } u1; -} AQ_GlobalThermalStatus_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global General Status: 1E.C830 */ -/* Global General Status: 1E.C830 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global General Status */ - union - { - struct - { - unsigned int reserved0 : 1; - /*! \brief 1E.C830.E RO High Temperature Failure State - AQ_GlobalGeneralStatus_HHD.u0.bits_0.highTemperatureFailureState - - - - 1 = High temperature failure threshold has been exceeded - - Notes: - In XENPAK mode, F/W will copy this register to the 1.A070.7 register. - - */ - unsigned int highTemperatureFailureState : 1; /* 1E.C830.E RO */ - /* 1 = High temperature failure threshold has been exceeded */ - /*! \brief 1E.C830.D RO Low Temperature Failure State - AQ_GlobalGeneralStatus_HHD.u0.bits_0.lowTemperatureFailureState - - - - 1 = Low temperature failure threshold has been exceeded - - Notes: - In XENPAK mode, F/W will copy this register to the 1.A070.6 register. - - */ - unsigned int lowTemperatureFailureState : 1; /* 1E.C830.D RO */ - /* 1 = Low temperature failure threshold has been exceeded */ - /*! \brief 1E.C830.C RO High Temperature Warning State - AQ_GlobalGeneralStatus_HHD.u0.bits_0.highTemperatureWarningState - - - - 1 = High temperature warning threshold has been exceeded - - Notes: - In XENPAK mode, F/W will copy this register to the 1.A074.7 register. - - */ - unsigned int highTemperatureWarningState : 1; /* 1E.C830.C RO */ - /* 1 = High temperature warning threshold has been exceeded */ - /*! \brief 1E.C830.B RO Low Temperature Warning State - AQ_GlobalGeneralStatus_HHD.u0.bits_0.lowTemperatureWarningState - - - - 1 = Low temperature warning threshold has been exceeded - - Notes: - In XENPAK mode, F/W will copy this register to the 1.A074.6 register. - - */ - unsigned int lowTemperatureWarningState : 1; /* 1E.C830.B RO */ - /* 1 = Low temperature warning threshold has been exceeded */ - unsigned int reserved1 : 11; - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global General Status */ - union - { - struct - { - /*! \brief 1E.C831.F RO Processor Intensive MDIO Operation In- Progress - AQ_GlobalGeneralStatus_HHD.u1.bits_1.processorIntensiveMdioOperationIn_Progress - - - - 1 = PHY microprocessor is busy with a processor-intensive MDIO operation - 0 = Processor-intensive MDIO operation completed - - - Notes: - This bit should may be used with certain processor-intensive MDIO commands (such as Loopbacks, Test Modes, Low power modes, Tx-Disable, Restart autonegotiation, Cable Diagnostics, etc.) that take longer than an MDIO cycle to complete. Upon receiving an MDIO command that involves the PHY's microprocessor, this bit is set, and when the command is completed, this bit is cleared. - - NOTE!!! This bit should be checked only after 1 ms of issuing a processor-intensive MDIO operation. - - The list of operations that set this bit are as follows: - - 1.0.0, PMA Loopback - 1.0.B, Low power mode - 1.9.4:0, Tx Disable - 1.84, 10G Test modes - 1.8000.5, XENPAK Control - 1.9000, XENPAK Rx Fault Enable - 1.9002, XENPAK Alarm Enable - 1.E400.F, External loopback - 3.0.B, Low power mode - 3.0.E, System PCS loopback - 3.C471.5, PRBS Test - 3.C471.6, PRBS Test - 3.E471.5, PRBS Test - 3.E471.6, PRBS Test - 4.0.B, Low power mode - 4.0.E, PHY-XS network loopback - 4.C440, Output clock control, Load SERDES parameters - 4.F802.E, System loopback - 4.C444.F:B, Loopback Control - 4.C444.4:2, Packet generation - 4.C445.C, SERDES calibration - 7.0.9, Restart autonegotiation - 1D.C280, 1G/100M Network loopback - 1D.C500, 1G System loopback - 1D.C501, 1G / 100M Test modes - 1E.C470.4, Cable diagnostics - 1E.C47A.F:B, Loopback Control - 1E.C47A.4:2, Packet generation */ - unsigned int processorIntensiveMdioOperationIn_Progress : 1; /* 1E.C831.F RO */ - /* 1 = PHY microprocessor is busy with a processor-intensive MDIO operation - 0 = Processor-intensive MDIO operation completed - */ - unsigned int reserved0 : 15; - } bits_1; - uint16_t word_1; - } u1; -} AQ_GlobalGeneralStatus_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Pin Status: 1E.C840 */ -/* Global Pin Status: 1E.C840 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Pin Status */ - union - { - struct - { - unsigned int reserved0 : 1; - unsigned int reserved1 : 1; - /*! \brief 1E.C840.D RO DC_MASTER_N - AQ_GlobalPinStatus_HHD.u0.bits_0.dcMasterN - - - - Value of DC_MASTER_N pin: - - 0x1 = PHY Slave Daisy Chain Boot - 0x0 = PHY Master Daisy Chain Boot from FLASH - */ - unsigned int dcMasterN : 1; /* 1E.C840.D RO */ - /* Value of DC_MASTER_N pin: - - 0x1 = PHY Slave Daisy Chain Boot - 0x0 = PHY Master Daisy Chain Boot from FLASH */ - unsigned int reserved2 : 3; - /*! \brief 1E.C840.9 RO Package Connectivity - AQ_GlobalPinStatus_HHD.u0.bits_0.packageConnectivity - - - - Value of the package connection pin - - */ - unsigned int packageConnectivity : 1; /* 1E.C840.9 RO */ - /* Value of the package connection pin - */ - unsigned int reserved3 : 1; - /*! \brief 1E.C840.7 RO Tx Enable - AQ_GlobalPinStatus_HHD.u0.bits_0.txEnable - - - - Current Value of Tx Enable pin - - - Notes: - 0 = Disable Transmitter */ - unsigned int txEnable : 1; /* 1E.C840.7 RO */ - /* Current Value of Tx Enable pin - */ - unsigned int reserved4 : 1; - /*! \brief 1E.C840.5:0 RO LED Pullup State [5:0] - AQ_GlobalPinStatus_HHD.u0.bits_0.ledPullupState - - - - 1 = LED output pin is pulled high - 0 = LED output pin is pulled low - - */ - unsigned int ledPullupState : 6; /* 1E.C840.5:0 RO */ - /* 1 = LED output pin is pulled high - 0 = LED output pin is pulled low - */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalPinStatus_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Daisy Chain Status: 1E.C842 */ -/* Global Daisy Chain Status: 1E.C842 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Daisy Chain Status */ - union - { - struct - { - /*! \brief 1E.C842.F:0 RO Rx Daisy Chain Calculated CRC [F:0] - AQ_GlobalDaisyChainStatus_HHD.u0.bits_0.rxDaisyChainCalculatedCrc - - - - Rx Daisy Chain Calculated CRC - - - Notes: - This is the calculated daisy chain CRC. */ - unsigned int rxDaisyChainCalculatedCrc : 16; /* 1E.C842.F:0 RO */ - /* Rx Daisy Chain Calculated CRC - */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalDaisyChainStatus_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Fault Message: 1E.C850 */ -/* Global Fault Message: 1E.C850 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Fault Message */ - union - { - struct - { - /*! \brief 1E.C850.F:0 RO Message [F:0] - AQ_GlobalFaultMessage_HHD.u0.bits_0.message - - - - Error code describing fault - - Notes: - Code 0x8001: Firmware not compatible with chip architecture. This fault occurs when firmware compiled for a different microprocessor core is loaded. - Code 0x8002: VCO calibration failed. This occurs when the main PLLs on chip fail to lock: this is not possible to trigger. - Code 0x8003: XAUI calibration failed. This occurs when the XAUI PLLs fail to lock: this is not possible to trigger. - Code 0x8005: Unexpected device ID. This occurs if the device ID programmed into the internal E-Fuse registers in not valid: this is not possible to trigger. - Code 0x8006: Computed checksum does not match expected checksum. This occurs when the FLASH checksum check performed at boot time fails. This only occurs when the system boots from FLASH. - Code 0x8007: Detected a bit error in static memory. To trigger, corrupt one of the static regions. - Code 0xC001: Illegal Instruction exception. This occurs when the processor attempts to execute an illegal instruction. To trigger this, write an illegal instruction to program memory. It's possible that the bit error check will trigger before the illegal instruction is executed. - Code 0xC002 Instruction Fetch Error. Internal physical address or a data error during instruction fetch: this is not possible to trigger. - Code 0xC003 Load Store Error. Internal physical address or data error during load store operation: this is not possible to trigger.. - Code 0xC004 Privileged Instruction. Attempt to execute a privileged operation without sufficient privilege: this is not possible to trigger. - Code 0xC005 Unaligned Load or Store. Attempt to load or store data at an address which cannot be handled due to alignment: this is not possible to trigger. - Code 0xC006 Instruction fetch from prohibited space: this is not possible to trigger. - Code 0xC007 Data load from prohibited space: this is not possible to trigger. - Code 0xC008 Data store into prohibited space: this is not possible to trigger. */ - unsigned int message : 16; /* 1E.C850.F:0 RO */ - /* Error code describing fault */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalFaultMessage_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Cable Diagnostic Impedance: 1E.C880 */ -/* Global Cable Diagnostic Impedance: 1E.C880 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Cable Diagnostic Impedance */ - union - { - struct - { - /*! \brief 1E.C880.F RO Reserved 1 - AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.reserved_1 - - - - Reserved - - */ - unsigned int reserved_1 : 1; /* 1E.C880.F RO */ - /* Reserved - */ - /*! \brief 1E.C880.E:C RO Pair A Reflection #1 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.pairAReflection_1 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the first worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ - unsigned int pairAReflection_1 : 3; /* 1E.C880.E:C RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C880.B RO Reserved 2 - AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.reserved_2 - - - - Reserved - - */ - unsigned int reserved_2 : 1; /* 1E.C880.B RO */ - /* Reserved - */ - /*! \brief 1E.C880.A:8 RO Pair A Reflection #2 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.pairAReflection_2 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the second worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ - unsigned int pairAReflection_2 : 3; /* 1E.C880.A:8 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C880.7 RO Reserved 3 - AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.reserved_3 - - - - Reserved - - */ - unsigned int reserved_3 : 1; /* 1E.C880.7 RO */ - /* Reserved - */ - /*! \brief 1E.C880.6:4 RO Pair A Reflection #3 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.pairAReflection_3 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the third worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ - unsigned int pairAReflection_3 : 3; /* 1E.C880.6:4 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C880.3 RO Reserved 4 - AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.reserved_4 - - - - Reserved - - */ - unsigned int reserved_4 : 1; /* 1E.C880.3 RO */ - /* Reserved - */ - /*! \brief 1E.C880.2:0 RO Pair A Reflection #4 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u0.bits_0.pairAReflection_4 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the fourth worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in See Global Power Control - Address 1E.21 */ - unsigned int pairAReflection_4 : 3; /* 1E.C880.2:0 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Cable Diagnostic Impedance */ - union - { - struct - { - /*! \brief 1E.C881.F RO Reserved 5 - AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.reserved_5 - - - - Reserved - - */ - unsigned int reserved_5 : 1; /* 1E.C881.F RO */ - /* Reserved - */ - /*! \brief 1E.C881.E:C RO Pair B Reflection #1 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.pairBReflection_1 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the first worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ - unsigned int pairBReflection_1 : 3; /* 1E.C881.E:C RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C881.B RO Reserved 6 - AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.reserved_6 - - - - Reserved - - */ - unsigned int reserved_6 : 1; /* 1E.C881.B RO */ - /* Reserved - */ - /*! \brief 1E.C881.A:8 RO Pair B Reflection #2 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.pairBReflection_2 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the second worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ - unsigned int pairBReflection_2 : 3; /* 1E.C881.A:8 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C881.7 RO Reserved 7 - AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.reserved_7 - - - - Reserved - - */ - unsigned int reserved_7 : 1; /* 1E.C881.7 RO */ - /* Reserved - */ - /*! \brief 1E.C881.6:4 RO Pair B Reflection #3 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.pairBReflection_3 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the third worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ - unsigned int pairBReflection_3 : 3; /* 1E.C881.6:4 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C881.3 RO Reserved 8 - AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.reserved_8 - - - - Reserved - - */ - unsigned int reserved_8 : 1; /* 1E.C881.3 RO */ - /* Reserved - */ - /*! \brief 1E.C881.2:0 RO Pair B Reflection #4 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u1.bits_1.pairBReflection_4 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the fourth worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 2 - Address 1E.32 - 1E.33 */ - unsigned int pairBReflection_4 : 3; /* 1E.C881.2:0 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global Cable Diagnostic Impedance */ - union - { - struct - { - /*! \brief 1E.C882.F RO Reserved 9 - AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.reserved_9 - - - - Reserved - - */ - unsigned int reserved_9 : 1; /* 1E.C882.F RO */ - /* Reserved - */ - /*! \brief 1E.C882.E:C RO Pair C Reflection #1 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.pairCReflection_1 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the first worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ - unsigned int pairCReflection_1 : 3; /* 1E.C882.E:C RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C882.B RO Reserved 10 - AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.reserved_10 - - - - Reserved - - */ - unsigned int reserved_10 : 1; /* 1E.C882.B RO */ - /* Reserved - */ - /*! \brief 1E.C882.A:8 RO Pair C Reflection #2 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.pairCReflection_2 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the second worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ - unsigned int pairCReflection_2 : 3; /* 1E.C882.A:8 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C882.7 RO Reserved 11 - AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.reserved_11 - - - - Reserved - - */ - unsigned int reserved_11 : 1; /* 1E.C882.7 RO */ - /* Reserved - */ - /*! \brief 1E.C882.6:4 RO Pair C Reflection #3 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.pairCReflection_3 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the third worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ - unsigned int pairCReflection_3 : 3; /* 1E.C882.6:4 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C882.3 RO Reserved 12 - AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.reserved_12 - - - - Reserved - - */ - unsigned int reserved_12 : 1; /* 1E.C882.3 RO */ - /* Reserved - */ - /*! \brief 1E.C882.2:0 RO Pair C Reflection #4 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u2.bits_2.pairCReflection_4 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the fourth worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.33 */ - unsigned int pairCReflection_4 : 3; /* 1E.C882.2:0 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global Cable Diagnostic Impedance */ - union - { - struct - { - /*! \brief 1E.C883.F RO Reserved 13 - AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.reserved_13 - - - - Reserved - - */ - unsigned int reserved_13 : 1; /* 1E.C883.F RO */ - /* Reserved - */ - /*! \brief 1E.C883.E:C RO Pair D Reflection #1 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.pairDReflection_1 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the first worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ - unsigned int pairDReflection_1 : 3; /* 1E.C883.E:C RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C883.B RO Reserved 14 - AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.reserved_14 - - - - Reserved - - */ - unsigned int reserved_14 : 1; /* 1E.C883.B RO */ - /* Reserved - */ - /*! \brief 1E.C883.A:8 RO Pair D Reflection #2 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.pairDReflection_2 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the second worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ - unsigned int pairDReflection_2 : 3; /* 1E.C883.A:8 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C883.7 RO Reserved 15 - AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.reserved_15 - - - - Reserved - - */ - unsigned int reserved_15 : 1; /* 1E.C883.7 RO */ - /* Reserved - */ - /*! \brief 1E.C883.6:4 RO Pair D Reflection #3 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.pairDReflection_3 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the third worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ - unsigned int pairDReflection_3 : 3; /* 1E.C883.6:4 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - /*! \brief 1E.C883.3 RO Reserved 16 - AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.reserved_16 - - - - Reserved - - */ - unsigned int reserved_16 : 1; /* 1E.C883.3 RO */ - /* Reserved - */ - /*! \brief 1E.C883.2:0 RO Pair D Reflection #4 [2:0] - AQ_GlobalCableDiagnosticImpedance_HHD.u3.bits_3.pairDReflection_4 - - - - 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - - - Notes: - The impedance of the fourth worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in See Global Cable Diagnostic Status 3 - Address 1E.34 - 1E.35 */ - unsigned int pairDReflection_4 : 3; /* 1E.C883.2:0 RO */ - /* 111 = Open Circuit (> 300W) - 110 = High Mismatch (> 115W) - 101 = Low Mismatch (< 85W) - 100 = Short Circuit (< 30W) - 0xx= No information available - */ - } bits_3; - uint16_t word_3; - } u3; -} AQ_GlobalCableDiagnosticImpedance_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Status: 1E.C884 */ -/* Global Status: 1E.C884 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Status */ - union - { - struct - { - /*! \brief 1E.C884.F:8 RO Reserved Status 0 [7:0] - AQ_GlobalStatus_HHD.u0.bits_0.reservedStatus_0 - - - - Reserved - - */ - unsigned int reservedStatus_0 : 8; /* 1E.C884.F:8 RO */ - /* Reserved - */ - /*! \brief 1E.C884.7:0 RO Cable Length [7:0] - AQ_GlobalStatus_HHD.u0.bits_0.cableLength - - - - The estimated length of the cable in meters - - - Notes: - The length of the cable shown here is estimated from the cable diagnostic engine and should be accurate to +/-1m. */ - unsigned int cableLength : 8; /* 1E.C884.7:0 RO */ - /* The estimated length of the cable in meters - */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalStatus_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Reserved Status: 1E.C885 */ -/* Global Reserved Status: 1E.C885 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Reserved Status */ - union - { - struct - { - /*! \brief 1E.C885.F:A RO Nearly Seconds MSW[5:0] - AQ_GlobalReservedStatus_HHD.u0.bits_0.nearlySecondsMSW - - - - Bits 16 to 21 of the 22 bit "Nearly Seconds" uptime counter. - - - Notes: - The "Nearly Seconds" counter is incremented every 1024 milliseconds. */ - unsigned int nearlySecondsMSW : 6; /* 1E.C885.F:A RO */ - /* Bits 16 to 21 of the 22 bit "Nearly Seconds" uptime counter. - */ - /*! \brief 1E.C885.9:8 ROSPD XENPAK NVR Status [1:0] - AQ_GlobalReservedStatus_HHD.u0.bits_0.xenpakNvrStatus - - Provisionable Default = 0x0 - - Status of XENPAK NVR: - 0: NVR not enabled - 1: Last NVR operation succeeded - 2: Last NVR operation failed - 3: Reserved - - - Notes: - XENPAK register space is mirrored in NVR (SPI ROM). This register indicates the status of the last NVR operation. */ - unsigned int xenpakNvrStatus : 2; /* 1E.C885.9:8 ROSPD Provisionable Default = 0x0 */ - /* Status of XENPAK NVR: - 0: NVR not enabled - 1: Last NVR operation succeeded - 2: Last NVR operation failed - 3: Reserved - */ - /*! \brief 1E.C885.7:4 ROSPD Firmware Build ID [3:0] - AQ_GlobalReservedStatus_HHD.u0.bits_0.firmwareBuildID - - Provisionable Default = 0x0 - - Firmware Build ID - - - Notes: - Customers may receive multiple ROM images that differ only in their provisioning. This field is used to differentiate those images. This field is used in conjunction with the firmware major and minor revision numbers to uniquely identify ROM images. */ - unsigned int firmwareBuildID : 4; /* 1E.C885.7:4 ROSPD Provisionable Default = 0x0 */ - /* Firmware Build ID - */ - /*! \brief 1E.C885.3:0 ROSPD Provisioning ID [3:0] - AQ_GlobalReservedStatus_HHD.u0.bits_0.provisioningID - - Provisionable Default = 0x0 - - Provisioning ID - - - Notes: - Customers may receive multiple ROM images that differ only in their provisioning. This field is used to differentiate those images. This field is used in conjunction with the firmware major and minor revision numbers to uniquely identify ROM images. */ - unsigned int provisioningID : 4; /* 1E.C885.3:0 ROSPD Provisionable Default = 0x0 */ - /* Provisioning ID - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Reserved Status */ - union - { - struct - { - /*! \brief 1E.C886.F:0 RO Nearly Seconds LSW [F:0] - AQ_GlobalReservedStatus_HHD.u1.bits_1.nearlySecondsLSW - - - - Bits 0 to 15 of the 22 bit "Nearly Seconds" uptime counter - - - Notes: - The "Nearly Seconds" counter is incremented every 1024 milliseconds. */ - unsigned int nearlySecondsLSW : 16; /* 1E.C886.F:0 RO */ - /* Bits 0 to 15 of the 22 bit "Nearly Seconds" uptime counter - */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global Reserved Status */ - union - { - struct - { - /*! \brief 1E.C887.F ROS DTE Status - AQ_GlobalReservedStatus_HHD.u2.bits_2.dteStatus - - Default = 0x0 - - 1 = Need power - 0 = Don't need power - - */ - unsigned int dteStatus : 1; /* 1E.C887.F ROS Default = 0x0 */ - /* 1 = Need power - 0 = Don't need power - */ - /*! \brief 1E.C887.E ROS Power Up Stall Status - AQ_GlobalReservedStatus_HHD.u2.bits_2.powerUpStallStatus - - Default = 0x0 - - 1 = FW is stalled at power up - 0 = Firmware is unstalled - - */ - unsigned int powerUpStallStatus : 1; /* 1E.C887.E ROS Default = 0x0 */ - /* 1 = FW is stalled at power up - 0 = Firmware is unstalled - */ - /*! \brief 1E.C887.D:0 RO Reserved Status 3 [D:0] - AQ_GlobalReservedStatus_HHD.u2.bits_2.reservedStatus_3 - - - - Reserved for future use - - */ - unsigned int reservedStatus_3 : 14; /* 1E.C887.D:0 RO */ - /* Reserved for future use - */ - } bits_2; - uint16_t word_2; - } u2; - /*! \brief Union for bit and word level access of word 3 of Global Reserved Status */ - union - { - struct - { - /*! \brief 1E.C888.F:B RO Loopback Status [4:0] - AQ_GlobalReservedStatus_HHD.u3.bits_3.loopbackStatus - - Default = 0x00 - - 0x00 = No loopback - 0x01 = System Interface - System Loopback - 0x02 = System Interface - System Loopback with Passthrough - 0x03 = System Interface - Network Loopback - 0x04 = System Interface - Network Loopback with Passthrough - 0x05 = System Interface - Network Loopback with Passthrough and Merge - 0x06 = System Interface - Peer-to-peer loopback - 0x07 - 0x08 = Reserved - 0x09 = Network Interface - System Loopback - 0x0A = Network Interface - System Loopback with Passthrough - 0x0B = Network Interface - Network Loopback - 0x0C = Network Interface - Network Loopback with Passthrough - 0x0D = Network Interface - Peer-to-peer loopback - 0x0E - 0x0F = Reserved - 0x10 = Cross-connect System Loopback - 0x11 = Cross-connect Network Loopback - 0x12 - 0x13 = Reserved - 0x14 = Network Interface - System Loopback via Loopback Plug - 0x15 - 0x1F = Reserved - - - Notes: - These bits, in conjunction with the chip configuration and the rate (Bits 1:0), report the selected loopback. - - */ - unsigned int loopbackStatus : 5; /* 1E.C888.F:B RO Default = 0x00 */ - /* 0x00 = No loopback - 0x01 = System Interface - System Loopback - 0x02 = System Interface - System Loopback with Passthrough - 0x03 = System Interface - Network Loopback - 0x04 = System Interface - Network Loopback with Passthrough - 0x05 = System Interface - Network Loopback with Passthrough and Merge - 0x06 = System Interface - Peer-to-peer loopback - 0x07 - 0x08 = Reserved - 0x09 = Network Interface - System Loopback - 0x0A = Network Interface - System Loopback with Passthrough - 0x0B = Network Interface - Network Loopback - 0x0C = Network Interface - Network Loopback with Passthrough - 0x0D = Network Interface - Peer-to-peer loopback - 0x0E - 0x0F = Reserved - 0x10 = Cross-connect System Loopback - 0x11 = Cross-connect Network Loopback - 0x12 - 0x13 = Reserved - 0x14 = Network Interface - System Loopback via Loopback Plug - 0x15 - 0x1F = Reserved - */ - /*! \brief 1E.C888.A:6 RO Reserved Status 4 [4:0] - AQ_GlobalReservedStatus_HHD.u3.bits_3.reservedStatus_4 - - Default = 0x00 - - Reserved for future use - - */ - unsigned int reservedStatus_4 : 5; /* 1E.C888.A:6 RO Default = 0x00 */ - /* Reserved for future use - */ - /*! \brief 1E.C888.5 RO MDI Packet Generation Status - AQ_GlobalReservedStatus_HHD.u3.bits_3.mdiPacketGenerationStatus - - Default = 0x0 - - 1 = CRPAT packet generation out MDI interface - 0 = No CRPAT packet generation out MDI interface - - - Notes: - Reports whether the CRPAT packet generator in the PHY outputs on the MDI interface at the selected rate. */ - unsigned int mdiPacketGenerationStatus : 1; /* 1E.C888.5 RO Default = 0x0 */ - /* 1 = CRPAT packet generation out MDI interface - 0 = No CRPAT packet generation out MDI interface - */ - /*! \brief 1E.C888.4 RO Look-Aside Port Packet Generation Status - AQ_GlobalReservedStatus_HHD.u3.bits_3.look_asidePortPacketGenerationStatus - - Default = 0x0 - - 1 = CRPAT packet generation out 10G look-aside interface (KR0) - 0 = No CRPAT packet generation out 10G look-aside interface (KR0) - - - Notes: - Reports whether the CRPAT packet generator in the PHY outputs on the KR0 interface at the selected rate. */ - unsigned int look_asidePortPacketGenerationStatus : 1; /* 1E.C888.4 RO Default = 0x0 */ - /* 1 = CRPAT packet generation out 10G look-aside interface (KR0) - 0 = No CRPAT packet generation out 10G look-aside interface (KR0) - */ - /*! \brief 1E.C888.3 RO System I/F Packet Generation Status - AQ_GlobalReservedStatus_HHD.u3.bits_3.systemI_fPacketGenerationStatus - - Default = 0x0 - - 1 = CRPAT packet generation out 10G system interface - 0 = No CRPAT packet generation out 10G system interface - - - Notes: - Reports whether the CRPAT packet generator in the PHY outputs on the selected system interface at the selected rate. */ - unsigned int systemI_fPacketGenerationStatus : 1; /* 1E.C888.3 RO Default = 0x0 */ - /* 1 = CRPAT packet generation out 10G system interface - 0 = No CRPAT packet generation out 10G system interface - */ - /*! \brief 1E.C888.2 RO Reserved Status 4a - AQ_GlobalReservedStatus_HHD.u3.bits_3.reservedStatus_4a - - Default = 0x0 - - Reserved for future use - - */ - unsigned int reservedStatus_4a : 1; /* 1E.C888.2 RO Default = 0x0 */ - /* Reserved for future use - */ - /*! \brief 1E.C888.1:0 RO Rate [1:0] - AQ_GlobalReservedStatus_HHD.u3.bits_3.rate - - Default = 0x0 - - 0x3 = 10G - 0x2 = 1G - 0x1 = 100M - 0x0 = invalid - - - Notes: - These bits report the selected rate for the loopback and packet generation. */ - unsigned int rate : 2; /* 1E.C888.1:0 RO Default = 0x0 */ - /* 0x3 = 10G - 0x2 = 1G - 0x1 = 100M - 0x0 = invalid - */ - } bits_3; - uint16_t word_3; - } u3; -} AQ_GlobalReservedStatus_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Alarms: 1E.CC00 */ -/* Global Alarms: 1E.CC00 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Alarms */ - union - { - struct - { - unsigned int reserved0 : 1; - /*! \brief 1E.CC00.E LH High Temperature Failure - AQ_GlobalAlarms_HHD.u0.bits_0.highTemperatureFailure - - - - 1 = High temperature failure threshold has been exceeded - - - Notes: - - - - - These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ - unsigned int highTemperatureFailure : 1; /* 1E.CC00.E LH */ - /* 1 = High temperature failure threshold has been exceeded - */ - /*! \brief 1E.CC00.D LH Low Temperature Failure - AQ_GlobalAlarms_HHD.u0.bits_0.lowTemperatureFailure - - - - 1 = Low temperature failure threshold has been exceeded - - - Notes: - - - - - These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ - unsigned int lowTemperatureFailure : 1; /* 1E.CC00.D LH */ - /* 1 = Low temperature failure threshold has been exceeded - */ - /*! \brief 1E.CC00.C LH High Temperature Warning - AQ_GlobalAlarms_HHD.u0.bits_0.highTemperatureWarning - - - - 1 = High temperature warning threshold has been exceeded - - - Notes: - - - - - These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ - unsigned int highTemperatureWarning : 1; /* 1E.CC00.C LH */ - /* 1 = High temperature warning threshold has been exceeded - */ - /*! \brief 1E.CC00.B LH Low Temperature Warning - AQ_GlobalAlarms_HHD.u0.bits_0.lowTemperatureWarning - - - - 1 = Low temperature warning threshold has been exceeded - - - Notes: - - - - - These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in See Global General Status 1: Address 1E.C830 . */ - unsigned int lowTemperatureWarning : 1; /* 1E.CC00.B LH */ - /* 1 = Low temperature warning threshold has been exceeded - */ - unsigned int reserved1 : 4; - /*! \brief 1E.CC00.6 LH Reset completed - AQ_GlobalAlarms_HHD.u0.bits_0.resetCompleted - - - - 1 = Chip wide reset completed - - Notes: - This bit is set by the microprocessor when it has completed it's initialization sequence. This bit is mirrored in 1.CC02.0 */ - unsigned int resetCompleted : 1; /* 1E.CC00.6 LH */ - /* 1 = Chip wide reset completed */ - unsigned int reserved2 : 1; - /*! \brief 1E.CC00.4 LH Device Fault - AQ_GlobalAlarms_HHD.u0.bits_0.deviceFault - - - - 1 = Fault - - Notes: - When set, a fault has been detected by the uP and the associated 16 bit error code is visible in See Global Configuration Fault Message: Address 1E.C850 */ - unsigned int deviceFault : 1; /* 1E.CC00.4 LH */ - /* 1 = Fault */ - /*! \brief 1E.CC00.3 LH Reserved Alarm A - AQ_GlobalAlarms_HHD.u0.bits_0.reservedAlarmA - - - - Reserved for future use - - */ - unsigned int reservedAlarmA : 1; /* 1E.CC00.3 LH */ - /* Reserved for future use - */ - /*! \brief 1E.CC00.2 LH Reserved Alarm B - AQ_GlobalAlarms_HHD.u0.bits_0.reservedAlarmB - - - - Reserved for future use - - */ - unsigned int reservedAlarmB : 1; /* 1E.CC00.2 LH */ - /* Reserved for future use - */ - /*! \brief 1E.CC00.1 LH Reserved Alarm C - AQ_GlobalAlarms_HHD.u0.bits_0.reservedAlarmC - - - - Reserved for future use - - */ - unsigned int reservedAlarmC : 1; /* 1E.CC00.1 LH */ - /* Reserved for future use - */ - /*! \brief 1E.CC00.0 LH Reserved Alarm D - AQ_GlobalAlarms_HHD.u0.bits_0.reservedAlarmD - - - - Reserved for future use - - */ - unsigned int reservedAlarmD : 1; /* 1E.CC00.0 LH */ - /* Reserved for future use - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Alarms */ - union - { - struct - { - unsigned int reserved0 : 1; - /*! \brief 1E.CC01.E LH Smart Power-Down Entered - AQ_GlobalAlarms_HHD.u1.bits_1.smartPower_downEntered - - - - 1 = Smart Power-Down State Entered - - - Notes: - When this bit is set, it indicates that the Smart Power-Down state was entered */ - unsigned int smartPower_downEntered : 1; /* 1E.CC01.E LH */ - /* 1 = Smart Power-Down State Entered - */ - /*! \brief 1E.CC01.D RO XENPAK Alarm - AQ_GlobalAlarms_HHD.u1.bits_1.xenpakAlarm - - - - 1 = XENPAK Alarm - - */ - unsigned int xenpakAlarm : 1; /* 1E.CC01.D RO */ - /* 1 = XENPAK Alarm - */ - /*! \brief 1E.CC01.C LH IP Phone Detect - AQ_GlobalAlarms_HHD.u1.bits_1.ipPhoneDetect - - - - 1 = IP Phone Detect - - - Notes: - Assertion of this bit means that the presence of an IP Phone has been detected. */ - unsigned int ipPhoneDetect : 1; /* 1E.CC01.C LH */ - /* 1 = IP Phone Detect - */ - /*! \brief 1E.CC01.B LH DTE Status Change - AQ_GlobalAlarms_HHD.u1.bits_1.dteStatusChange - - - - 1 = DTE status change - - - Notes: - Change in 1E.C887[F]. */ - unsigned int dteStatusChange : 1; /* 1E.CC01.B LH */ - /* 1 = DTE status change - */ - /*! \brief 1E.CC01.A:8 LH Reserved Alarms [2:0] - AQ_GlobalAlarms_HHD.u1.bits_1.reservedAlarms - - - - Reserved - - - */ - unsigned int reservedAlarms : 3; /* 1E.CC01.A:8 LH */ - /* Reserved - - */ - /*! \brief 1E.CC01.7 LH MDIO Command Handling Overflow - AQ_GlobalAlarms_HHD.u1.bits_1.mdioCommandHandlingOverflow - - - - 1 = PHY was issued more MDIO requests than it could service in it's request buffer - - - Notes: - Assertion of this bit means that more MDIO commands were issued than FW could handle. */ - unsigned int mdioCommandHandlingOverflow : 1; /* 1E.CC01.7 LH */ - /* 1 = PHY was issued more MDIO requests than it could service in it's request buffer - */ - unsigned int reserved1 : 6; - unsigned int reserved2 : 1; - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global Alarms */ - union - { - struct - { - /*! \brief 1E.CC02.F LH NVR Operation Complete - AQ_GlobalAlarms_HHD.u2.bits_2.nvrOperationComplete - - - - 1 = NVR operation is complete - - - Notes: - NVR interface is ready interrupt for registers See Global NVR Interface 1: Address 1E.100 - See Global NVR Provisioning Data MSW - Address 1E.17 . */ - unsigned int nvrOperationComplete : 1; /* 1E.CC02.F LH */ - /* 1 = NVR operation is complete - */ - /*! \brief 1E.CC02.E LH Mailbox Operation: Complete - AQ_GlobalAlarms_HHD.u2.bits_2.mailboxOperation_Complete - - - - 1 = Mailbox operation is complete - - - Notes: - Mailbox interface is ready interrupt for registers See Global Vendor Specific Control - Address 1E.C000 - See Global Vendor Specific Provisioning 5 - Address 1E.C404 */ - unsigned int mailboxOperation_Complete : 1; /* 1E.CC02.E LH */ - /* 1 = Mailbox operation is complete - */ - unsigned int reserved0 : 3; - /*! \brief 1E.CC02.A LH uP DRAM Parity Error - AQ_GlobalAlarms_HHD.u2.bits_2.upDramParityError - - - - 1 = Parity error detected in the uP DRAM - - */ - unsigned int upDramParityError : 1; /* 1E.CC02.A LH */ - /* 1 = Parity error detected in the uP DRAM - */ - /*! \brief 1E.CC02.9:8 LH uP IRAM Parity Error [1:0] - AQ_GlobalAlarms_HHD.u2.bits_2.upIramParityError - - - - 1 = Parity error detected in the uP IRAM - - - Notes: - Bit 0 indicates a parity error was detected in the uP IRAM but was corrected. - Bit 1 indicates a multiple parity errors were detected in the uP IRAM and could not be corrected. - The uP IRAM is protected with ECC. */ - unsigned int upIramParityError : 2; /* 1E.CC02.9:8 LH */ - /* 1 = Parity error detected in the uP IRAM - */ - unsigned int reserved1 : 2; - /*! \brief 1E.CC02.5 LRF Tx Enable State Change - AQ_GlobalAlarms_HHD.u2.bits_2.txEnableStateChange - - - - 1 = TX_EN pin has changed state - - */ - unsigned int txEnableStateChange : 1; /* 1E.CC02.5 LRF */ - /* 1 = TX_EN pin has changed state - */ - unsigned int reserved2 : 2; - /*! \brief 1E.CC02.2 LH MDIO MMD Error - AQ_GlobalAlarms_HHD.u2.bits_2.mdioMMD_Error - - - - 1 = Invalid MMD address detected - - */ - unsigned int mdioMMD_Error : 1; /* 1E.CC02.2 LH */ - /* 1 = Invalid MMD address detected - */ - /*! \brief 1E.CC02.1 LH MDIO Timeout Error - AQ_GlobalAlarms_HHD.u2.bits_2.mdioTimeoutError - - - - 1 = MDIO timeout detected - - */ - unsigned int mdioTimeoutError : 1; /* 1E.CC02.1 LH */ - /* 1 = MDIO timeout detected - */ - /*! \brief 1E.CC02.0 LH Watchdog Timer Alarm - AQ_GlobalAlarms_HHD.u2.bits_2.watchdogTimerAlarm - - - - 1 = Watchdog timer alarm - - */ - unsigned int watchdogTimerAlarm : 1; /* 1E.CC02.0 LH */ - /* 1 = Watchdog timer alarm - */ - } bits_2; - uint16_t word_2; - } u2; -} AQ_GlobalAlarms_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Interrupt Mask: 1E.D400 */ -/* Global Interrupt Mask: 1E.D400 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Interrupt Mask */ - union - { - struct - { - unsigned int reserved0 : 1; - /*! \brief 1E.D400.E R/WPD High Temperature Failure Mask - AQ_GlobalInterruptMask_HHD.u0.bits_0.highTemperatureFailureMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int highTemperatureFailureMask : 1; /* 1E.D400.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.D400.D R/WPD Low Temperature Failure Mask - AQ_GlobalInterruptMask_HHD.u0.bits_0.lowTemperatureFailureMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int lowTemperatureFailureMask : 1; /* 1E.D400.D R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.D400.C R/WPD High Temperature Warning Mask - AQ_GlobalInterruptMask_HHD.u0.bits_0.highTemperatureWarningMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int highTemperatureWarningMask : 1; /* 1E.D400.C R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.D400.B R/WPD Low Temperature Warning Mask - AQ_GlobalInterruptMask_HHD.u0.bits_0.lowTemperatureWarningMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int lowTemperatureWarningMask : 1; /* 1E.D400.B R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - unsigned int reserved1 : 4; - /*! \brief 1E.D400.6 R/WPD Reset completed Mask - AQ_GlobalInterruptMask_HHD.u0.bits_0.resetCompletedMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int resetCompletedMask : 1; /* 1E.D400.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - unsigned int reserved2 : 1; - /*! \brief 1E.D400.4 R/WPD Device Fault Mask - AQ_GlobalInterruptMask_HHD.u0.bits_0.deviceFaultMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int deviceFaultMask : 1; /* 1E.D400.4 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.D400.3 R/WPD Reserved Alarm A Mask - AQ_GlobalInterruptMask_HHD.u0.bits_0.reservedAlarmAMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int reservedAlarmAMask : 1; /* 1E.D400.3 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - /*! \brief 1E.D400.2 R/WPD Reserved Alarm B Mask - AQ_GlobalInterruptMask_HHD.u0.bits_0.reservedAlarmBMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int reservedAlarmBMask : 1; /* 1E.D400.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - /*! \brief 1E.D400.1 R/WPD Reserved Alarm C Mask - AQ_GlobalInterruptMask_HHD.u0.bits_0.reservedAlarmCMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int reservedAlarmCMask : 1; /* 1E.D400.1 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - /*! \brief 1E.D400.0 R/WPD Reserved Alarm D Mask - AQ_GlobalInterruptMask_HHD.u0.bits_0.reservedAlarmDMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int reservedAlarmDMask : 1; /* 1E.D400.0 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - } bits_0; - uint16_t word_0; - } u0; - /*! \brief Union for bit and word level access of word 1 of Global Interrupt Mask */ - union - { - struct - { - unsigned int reserved0 : 1; - /*! \brief 1E.D401.E R/WPD Smart Power-Down Entered Mask - AQ_GlobalInterruptMask_HHD.u1.bits_1.smartPower_downEnteredMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int smartPower_downEnteredMask : 1; /* 1E.D401.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - /*! \brief 1E.D401.D R/WPD XENPAK Alarm Mask - AQ_GlobalInterruptMask_HHD.u1.bits_1.xenpakAlarmMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int xenpakAlarmMask : 1; /* 1E.D401.D R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.D401.C R/WPD IP Phone Detect Mask - AQ_GlobalInterruptMask_HHD.u1.bits_1.ipPhoneDetectMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int ipPhoneDetectMask : 1; /* 1E.D401.C R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - /*! \brief 1E.D401.B R/WPD DTE Status Change Mask - AQ_GlobalInterruptMask_HHD.u1.bits_1.dteStatusChangeMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int dteStatusChangeMask : 1; /* 1E.D401.B R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - /*! \brief 1E.D401.A:8 R/WPD Reserved Alarms Mask [2:0] - AQ_GlobalInterruptMask_HHD.u1.bits_1.reservedAlarmsMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int reservedAlarmsMask : 3; /* 1E.D401.A:8 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - /*! \brief 1E.D401.7 R/WPD MDIO Command Handling Overflow Mask - AQ_GlobalInterruptMask_HHD.u1.bits_1.mdioCommandHandlingOverflowMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int mdioCommandHandlingOverflowMask : 1; /* 1E.D401.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int reserved1 : 6; - /*! \brief 1E.D401.0 R/WPD Diagnostic Alarm Mask - AQ_GlobalInterruptMask_HHD.u1.bits_1.diagnosticAlarmMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int diagnosticAlarmMask : 1; /* 1E.D401.0 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - } bits_1; - uint16_t word_1; - } u1; - /*! \brief Union for bit and word level access of word 2 of Global Interrupt Mask */ - union - { - struct - { - /*! \brief 1E.D402.F R/WPD NVR Operation Complete Mask - AQ_GlobalInterruptMask_HHD.u2.bits_2.nvrOperationCompleteMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - Notes: - NVR interface is ready interrupt for registers See Global NVR Interface 1: Address 1E.100 - See Global NVR Provisioning Data MSW - Address 1E.17 */ - unsigned int nvrOperationCompleteMask : 1; /* 1E.D402.F R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.D402.E R/WPD Mailbox Operation Complete Mask - AQ_GlobalInterruptMask_HHD.u2.bits_2.mailboxOperationCompleteMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - Notes: - Mailbox interface is ready interrupt for registers See Global Vendor Specific Control - Address 1E.C000 - See Global Vendor Specific Provisioning 5 - Address 1E.C404 */ - unsigned int mailboxOperationCompleteMask : 1; /* 1E.D402.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - unsigned int reserved0 : 3; - /*! \brief 1E.D402.A R/WPD uP DRAM Parity Error Mask - AQ_GlobalInterruptMask_HHD.u2.bits_2.upDramParityErrorMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int upDramParityErrorMask : 1; /* 1E.D402.A R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - /*! \brief 1E.D402.9:8 R/WPD uP IRAM Parity Error Mask [1:0] - AQ_GlobalInterruptMask_HHD.u2.bits_2.upIramParityErrorMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - - */ - unsigned int upIramParityErrorMask : 2; /* 1E.D402.9:8 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int reserved1 : 2; - /*! \brief 1E.D402.5 R/WPD Tx Enable State Change Mask - AQ_GlobalInterruptMask_HHD.u2.bits_2.txEnableStateChangeMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int txEnableStateChangeMask : 1; /* 1E.D402.5 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - unsigned int reserved2 : 2; - /*! \brief 1E.D402.2 R/WPD MDIO MMD Error Mask - AQ_GlobalInterruptMask_HHD.u2.bits_2.mdioMMD_ErrorMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int mdioMMD_ErrorMask : 1; /* 1E.D402.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.D402.1 R/WPD MDIO Timeout Error Mask - AQ_GlobalInterruptMask_HHD.u2.bits_2.mdioTimeoutErrorMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int mdioTimeoutErrorMask : 1; /* 1E.D402.1 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.D402.0 R/WPD Watchdog Timer Alarm Mask - AQ_GlobalInterruptMask_HHD.u2.bits_2.watchdogTimerAlarmMask - - Provisionable Default = 0x1 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int watchdogTimerAlarmMask : 1; /* 1E.D402.0 R/WPD Provisionable Default = 0x1 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - } bits_2; - uint16_t word_2; - } u2; -} AQ_GlobalInterruptMask_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Chip-Wide Standard Interrupt Flags: 1E.FC00 */ -/* Global Chip-Wide Standard Interrupt Flags: 1E.FC00 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Chip-Wide Standard Interrupt Flags */ - union - { - struct - { - /*! \brief 1E.FC00.F RO PMA Standard Alarm 1 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.pmaStandardAlarm_1Interrupt - - - - 1 = Interrupt in PMA standard alarms 1 - - - Notes: - An interrupt was generated from bit 1.1.2. - An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ - unsigned int pmaStandardAlarm_1Interrupt : 1; /* 1E.FC00.F RO */ - /* 1 = Interrupt in PMA standard alarms 1 - */ - /*! \brief 1E.FC00.E RO PMA Standard Alarm 2 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.pmaStandardAlarm_2Interrupt - - - - 1 = Interrupt in PMA standard alarms 2 - - - Notes: - An interrupt was generated from either bit 1.8.B or 1.8.A. - An interrupt was generated from status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ - unsigned int pmaStandardAlarm_2Interrupt : 1; /* 1E.FC00.E RO */ - /* 1 = Interrupt in PMA standard alarms 2 - */ - /*! \brief 1E.FC00.D RO PCS Standard Alarm 1 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.pcsStandardAlarm_1Interrupt - - - - 1 = Interrupt in PCS standard alarms 1 - - - Notes: - An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ - unsigned int pcsStandardAlarm_1Interrupt : 1; /* 1E.FC00.D RO */ - /* 1 = Interrupt in PCS standard alarms 1 - */ - /*! \brief 1E.FC00.C RO PCS Standard Alarm 2 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.pcsStandardAlarm_2Interrupt - - - - 1 = Interrupt in PCS standard alarms 2 - - - Notes: - An interrupt was generated from status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ - unsigned int pcsStandardAlarm_2Interrupt : 1; /* 1E.FC00.C RO */ - /* 1 = Interrupt in PCS standard alarms 2 - */ - /*! \brief 1E.FC00.B RO PCS Standard Alarm 3 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.pcsStandardAlarm_3Interrupt - - - - 1 = Interrupt in PCS standard alarms 3 - - - Notes: - An interrupt was generated from status register ( See PCS 10GBASE-T Status 2 - Address 3.21 ) and the corresponding mask register. ( See PCS Standard Interrupt Mask 1 - Address 3.E021 ) */ - unsigned int pcsStandardAlarm_3Interrupt : 1; /* 1E.FC00.B RO */ - /* 1 = Interrupt in PCS standard alarms 3 - */ - /*! \brief 1E.FC00.A RO PHY XS Standard Alarms 1 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.phyXS_StandardAlarms_1Interrupt - - - - 1 = Interrupt in PHY XS standard alarms 1 - - - Notes: - An interrupt was generated from the status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 2 - Address 4.A001 ) */ - unsigned int phyXS_StandardAlarms_1Interrupt : 1; /* 1E.FC00.A RO */ - /* 1 = Interrupt in PHY XS standard alarms 1 - */ - /*! \brief 1E.FC00.9 RO PHY XS Standard Alarms 2 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.phyXS_StandardAlarms_2Interrupt - - - - 1 = Interrupt in PHY XS standard alarms 2 - - - Notes: - An interrupt was generated from the status register ( See PHY XS Standard Vendor Devices in Package - Address 4.8 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ - unsigned int phyXS_StandardAlarms_2Interrupt : 1; /* 1E.FC00.9 RO */ - /* 1 = Interrupt in PHY XS standard alarms 2 - */ - /*! \brief 1E.FC00.8 RO Autonegotiation Standard Alarms 1 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.autonegotiationStandardAlarms_1Interrupt - - - - 1 = Interrupt in Autonegotiation standard alarms 1 - - - Notes: - An interrupt was generated from status register ( See PHY XS Standard Status 1 - Address 4.1 ) and the corresponding mask register. ( See Autonegotiation Standard LASI Interrupt Mask 1: Address 7.D000 ) */ - unsigned int autonegotiationStandardAlarms_1Interrupt : 1; /* 1E.FC00.8 RO */ - /* 1 = Interrupt in Autonegotiation standard alarms 1 - */ - /*! \brief 1E.FC00.7 RO Autonegotiation Standard Alarms 2 Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.autonegotiationStandardAlarms_2Interrupt - - - - 1 = Interrupt in Autonegotiation standard alarms 2 - - - Notes: - An interrupt was generated from status register ( See Autonegotiation 10GBASE-T Status Register - Address 7.21 ) and the corresponding mask register. ( See PHY XS Standard Transmit XAUI Rx Interrupt Mask 8 - Address 4.A008 ) */ - unsigned int autonegotiationStandardAlarms_2Interrupt : 1; /* 1E.FC00.7 RO */ - /* 1 = Interrupt in Autonegotiation standard alarms 2 - */ - /*! \brief 1E.FC00.6 RO GbE Standard Alarms Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.gbeStandardAlarmsInterrupt - - - - 1 = Interrupt in GbE standard alarms - - - Notes: - An interrupt was generated from the TGE core. */ - unsigned int gbeStandardAlarmsInterrupt : 1; /* 1E.FC00.6 RO */ - /* 1 = Interrupt in GbE standard alarms - */ - unsigned int reserved0 : 5; - /*! \brief 1E.FC00.0 RO All Vendor Alarms Interrupt - AQ_GlobalChip_wideStandardInterruptFlags_HHD.u0.bits_0.allVendorAlarmsInterrupt - - - - 1 = Interrupt in all vendor alarms - - - Notes: - An interrupt was generated from status register ( See Global Chip-Wide LASI Vendor Interrupt Flags: Address 1E.FC01 ) and the corresponding mask register. ( See Global Interrupt LASI Mask: Address 1E.FF01 ) */ - unsigned int allVendorAlarmsInterrupt : 1; /* 1E.FC00.0 RO */ - /* 1 = Interrupt in all vendor alarms - */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalChip_wideStandardInterruptFlags_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Chip-Wide Vendor Interrupt Flags: 1E.FC01 */ -/* Global Chip-Wide Vendor Interrupt Flags: 1E.FC01 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Chip-Wide Vendor Interrupt Flags */ - union - { - struct - { - /*! \brief 1E.FC01.F RO PMA Vendor Alarm Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.pmaVendorAlarmInterrupt - - - - 1 = Interrupt in PMA vendor specific alarm - - - Notes: - A PMA alarm was generated. ( See PHY XS Vendor Global Interrupt Flags 1- Address 4.F800 ) */ - unsigned int pmaVendorAlarmInterrupt : 1; /* 1E.FC01.F RO */ - /* 1 = Interrupt in PMA vendor specific alarm - */ - /*! \brief 1E.FC01.E RO PCS Vendor Alarm Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.pcsVendorAlarmInterrupt - - - - 1 = Interrupt in PCS vendor specific alarm - - - Notes: - A PCS alarm was generated. ( See PHY XS Vendor Global Interrupt Flags 1- Address 4.F800 ) */ - unsigned int pcsVendorAlarmInterrupt : 1; /* 1E.FC01.E RO */ - /* 1 = Interrupt in PCS vendor specific alarm - */ - /*! \brief 1E.FC01.D RO PHY XS Vendor Alarm Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.phyXS_VendorAlarmInterrupt - - - - 1 = Interrupt in PHY XS vendor specific alarm - - - Notes: - A PHY XS alarm was generated. ( See PHY XS Vendor Global LASI Interrupt Flags 1: Address 4.FC00 ) */ - unsigned int phyXS_VendorAlarmInterrupt : 1; /* 1E.FC01.D RO */ - /* 1 = Interrupt in PHY XS vendor specific alarm - */ - /*! \brief 1E.FC01.C RO Autonegotiation Vendor Alarm Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.autonegotiationVendorAlarmInterrupt - - - - 1 = Interrupt in Autonegotiation vendor specific alarm - - - Notes: - An Autonegotiation alarm was generated. ( See Autonegotiation Vendor Global LASI Interrupt Flags 1: Address 7.FC00 ) */ - unsigned int autonegotiationVendorAlarmInterrupt : 1; /* 1E.FC01.C RO */ - /* 1 = Interrupt in Autonegotiation vendor specific alarm - */ - /*! \brief 1E.FC01.B RO GbE Vendor Alarm Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.gbeVendorAlarmInterrupt - - - - 1 = Interrupt in GbE vendor specific alarm - - - Notes: - A GbE alarm was generated. ( See GbE PHY Vendor Global LASI Interrupt Flags 1: Address 1D.FC00 ) */ - unsigned int gbeVendorAlarmInterrupt : 1; /* 1E.FC01.B RO */ - /* 1 = Interrupt in GbE vendor specific alarm - */ - unsigned int reserved0 : 8; - /*! \brief 1E.FC01.2 RO Global Alarms 1 Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.globalAlarms_1Interrupt - - - - 1 = Interrupt in Global alarms 1 - - - Notes: - An interrupt was generated from status register ( See Global Vendor Alarms 1 - Address 1E.CC00 ) and the corresponding mask register. ( See Global Vendor Interrupt Mask - Address 1E.D400 ) */ - unsigned int globalAlarms_1Interrupt : 1; /* 1E.FC01.2 RO */ - /* 1 = Interrupt in Global alarms 1 - */ - /*! \brief 1E.FC01.1 RO Global Alarms 2 Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.globalAlarms_2Interrupt - - - - 1 = Interrupt in Global alarms 2 - - - Notes: - An interrupt was generated from status register ( See Global Alarms 2: Address 1E.CC01 ) and the corresponding mask register. ( See Global LASI Interrupt Mask 2: Address 1E.D401 ) */ - unsigned int globalAlarms_2Interrupt : 1; /* 1E.FC01.1 RO */ - /* 1 = Interrupt in Global alarms 2 - */ - /*! \brief 1E.FC01.0 RO Global Alarms 3 Interrupt - AQ_GlobalChip_wideVendorInterruptFlags_HHD.u0.bits_0.globalAlarms_3Interrupt - - - - 1 = Interrupt in Global alarms 3 - - - Notes: - An interrupt was generated from status register ( See Global Vendor Alarms 2: Address 1E.CC01 ) and the corresponding mask register. ( See Global LASI Interrupt Mask 2: Address 1E.D401 ) */ - unsigned int globalAlarms_3Interrupt : 1; /* 1E.FC01.0 RO */ - /* 1 = Interrupt in Global alarms 3 - */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalChip_wideVendorInterruptFlags_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Interrupt Chip-Wide Standard Mask: 1E.FF00 */ -/* Global Interrupt Chip-Wide Standard Mask: 1E.FF00 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Interrupt Chip-Wide Standard Mask */ - union - { - struct - { - /*! \brief 1E.FF00.F R/WPD PMA Standard Alarm 1 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.pmaStandardAlarm_1InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int pmaStandardAlarm_1InterruptMask : 1; /* 1E.FF00.F R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.E R/WPD PMA Standard Alarm 2 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.pmaStandardAlarm_2InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int pmaStandardAlarm_2InterruptMask : 1; /* 1E.FF00.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.D R/WPD PCS Standard Alarm 1 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.pcsStandardAlarm_1InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int pcsStandardAlarm_1InterruptMask : 1; /* 1E.FF00.D R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.C R/WPD PCS Standard Alarm 2 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.pcsStandardAlarm_2InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int pcsStandardAlarm_2InterruptMask : 1; /* 1E.FF00.C R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.B R/WPD PCS Standard Alarm 3 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.pcsStandardAlarm_3InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int pcsStandardAlarm_3InterruptMask : 1; /* 1E.FF00.B R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.A R/WPD PHY XS Standard Alarms 1 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.phyXS_StandardAlarms_1InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int phyXS_StandardAlarms_1InterruptMask : 1; /* 1E.FF00.A R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.9 R/WPD PHY XS Standard Alarms 2 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.phyXS_StandardAlarms_2InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int phyXS_StandardAlarms_2InterruptMask : 1; /* 1E.FF00.9 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.8 R/WPD Autonegotiation Standard Alarms 1 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.autonegotiationStandardAlarms_1InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int autonegotiationStandardAlarms_1InterruptMask : 1; /* 1E.FF00.8 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.7 R/WPD Autonegotiation Standard Alarms 2 Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.autonegotiationStandardAlarms_2InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int autonegotiationStandardAlarms_2InterruptMask : 1; /* 1E.FF00.7 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF00.6 R/WPD Gbe Standard Alarms Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.gbeStandardAlarmsInterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int gbeStandardAlarmsInterruptMask : 1; /* 1E.FF00.6 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - unsigned int reserved0 : 5; - /*! \brief 1E.FF00.0 R/WPD All Vendor Alarms Interrupt Mask - AQ_GlobalInterruptChip_wideStandardMask_HHD.u0.bits_0.allVendorAlarmsInterruptMask - - Provisionable Default = 0x1 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int allVendorAlarmsInterruptMask : 1; /* 1E.FF00.0 R/WPD Provisionable Default = 0x1 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalInterruptChip_wideStandardMask_HHD; - - -/*---------------------------------------------------------------------------------*/ -/*! \brief Global Interrupt Chip-Wide Vendor Mask: 1E.FF01 */ -/* Global Interrupt Chip-Wide Vendor Mask: 1E.FF01 */ -/*---------------------------------------------------------------------------------*/ -typedef struct -{ - /*! \brief Union for bit and word level access of word 0 of Global Interrupt Chip-Wide Vendor Mask */ - union - { - struct - { - /*! \brief 1E.FF01.F R/WPD PMA Vendor Alarm Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.pmaVendorAlarmInterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int pmaVendorAlarmInterruptMask : 1; /* 1E.FF01.F R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF01.E R/WPD PCS Vendor Alarm Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.pcsVendorAlarmInterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int pcsVendorAlarmInterruptMask : 1; /* 1E.FF01.E R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF01.D R/WPD PHY XS Vendor Alarm Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.phyXS_VendorAlarmInterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int phyXS_VendorAlarmInterruptMask : 1; /* 1E.FF01.D R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF01.C R/WPD Autonegotiation Vendor Alarm Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.autonegotiationVendorAlarmInterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int autonegotiationVendorAlarmInterruptMask : 1; /* 1E.FF01.C R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF01.B R/WPD GbE Vendor Alarm Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.gbeVendorAlarmInterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int gbeVendorAlarmInterruptMask : 1; /* 1E.FF01.B R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - unsigned int reserved0 : 8; - /*! \brief 1E.FF01.2 R/WPD Global Alarms 1 Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.globalAlarms_1InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int globalAlarms_1InterruptMask : 1; /* 1E.FF01.2 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF01.1 R/WPD Global Alarms 2 Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.globalAlarms_2InterruptMask - - Provisionable Default = 0x0 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int globalAlarms_2InterruptMask : 1; /* 1E.FF01.1 R/WPD Provisionable Default = 0x0 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - /*! \brief 1E.FF01.0 R/WPD Global Alarms 3 Interrupt Mask - AQ_GlobalInterruptChip_wideVendorMask_HHD.u0.bits_0.globalAlarms_3InterruptMask - - Provisionable Default = 0x1 - - 1 = Enable interrupt generation - 0 = Disable interrupt generation - */ - unsigned int globalAlarms_3InterruptMask : 1; /* 1E.FF01.0 R/WPD Provisionable Default = 0x1 */ - /* 1 = Enable interrupt generation - 0 = Disable interrupt generation */ - } bits_0; - uint16_t word_0; - } u0; -} AQ_GlobalInterruptChip_wideVendorMask_HHD; - -#endif -/*@}*/ -/*@}*/ diff --git a/qca/aq-fw-download/src/mdioBootLoadCLD.c b/qca/aq-fw-download/src/mdioBootLoadCLD.c deleted file mode 100644 index a8e09d8c9..000000000 --- a/qca/aq-fw-download/src/mdioBootLoadCLD.c +++ /dev/null @@ -1,193 +0,0 @@ -/* mdioBootLoadCLD.c */ - -/************************************************************************************ -* Copyright (c) 2015 Aquantia -* -* Permission to use, copy, modify, and/or distribute this software for any -* purpose with or without fee is hereby granted, provided that the above -* copyright notice and this permission notice appear in all copies. -* -* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -* -* $File: //depot/icm/proj/Dena/rev1.0/c/Systems/tools/windows/flashUtilities/src/mdioBootLoadCLD.c $ -* -* $Revision: #12 $ -* -* $DateTime: 2014/05/19 15:34:49 $ -* -* $Author: joshd $ -* -* $Label: $ -* -************************************************************************************/ - -/*! \file -This file contains the main (int, char**) file for the mdioBootLoadCLD program, which burns a flash image into a target -Aquantia PHY using the AQ_API. This program calls the API function:

    - - uint8_t AQ_API_WriteBootLoadImage (uint8_t PHY_ID, uint8_t *image, uint16_t *crc16)

    - -to boot load a cld flash image into an Aquantia PHY */ - -/*! \addtogroup mdioBootLoad -@{ -*/ - - - -/*! \def DEBUG -Uncomment this to compile in debug mode. This sets the source to an arbitrary file, defined by DEBUG_FILENAME, -and an arbitrary PHY_ID, defined by DEBUG_PHY_ID. */ -/* #define DEBUG */ - -/*! The debug source file name */ -#define DEBUG_FILENAME "HelloWorld.cld" - -/*! The debug PHY ID */ -#define DEBUG_PHY_ID 0 - - -#include -#include -#include -#include -#include -#include -#include -#include - -#include "AQ_API.h" -#include "AQ_PhyInterface.h" - -int sock; -char devname[7]; - -int sock_init() -{ - if ((sock = socket(AF_INET, SOCK_DGRAM, 0)) < 0) { - fprintf(stderr, "Error creating socket: %s\n", strerror(errno)); - return -1; - } - - return 0; -} - -int main ( int argc, char **argp) -{ - /* declare local variables */ - FILE *pFile; - uint8_t* image; - uint8_t byte; - unsigned int PHY_ID; - AQ_Retcode resultCode; - AQ_Retcode resultCodes[4]; - uint32_t i; - uint32_t imageSize; - char sourceFileName[1000]; - AQ_API_Port targetPort0; - AQ_API_Port* targetPorts[1]; - AQ_API_Port broadcastPort; - unsigned int provisioningAddresses[1] = {0}; - uint32_t reg1, reg2; - - targetPorts[0] = &targetPort0; - - if(argc < 4) { - fprintf (stderr, "enter file name/netdev name/phy address\n"); - return (101); - } - - /*Copy the file name from command line arg*/ - if (strlcpy (sourceFileName, argp[1], sizeof(sourceFileName)) >= sizeof(sourceFileName)) { - fprintf (stderr, "Filename: %s too long \n", argp[1]); - return (101); - } - /*Copy the interface name from command line arg*/ - strlcpy (devname, argp[2], sizeof(devname)); - /*Get PHY Address from command line arg*/ - PHY_ID = (unsigned int)strtoul(argp[3], NULL, 0); - - /* FIXME: set port and device type */ - targetPort0.device = AQ_DEVICE_HHD; - targetPort0.PHY_ID = PHY_ID; - - broadcastPort.device = AQ_DEVICE_HHD; - broadcastPort.PHY_ID = PHY_ID; - - /* open the source in binary read mode */ - pFile = fopen(sourceFileName, "rb"); - if (pFile == NULL) - { - fprintf (stderr, "Unable to open source file %s\n", sourceFileName); - return (101); - } - fseek (pFile, 0, SEEK_END); - imageSize = ftell (pFile); - - image = (uint8_t*) malloc (imageSize * sizeof(uint8_t)); - fseek (pFile, 0, SEEK_SET); - - /* load the file */ - for (i = 0; i < imageSize; i++) - { - byte = (uint8_t) fgetc (pFile); - image[i] = byte; - } - fclose(pFile); - - - if (sock_init() < 0) - { - fprintf (stderr, "Unable to initialize interface\n"); - return (200); - } - - /* Write in the Auantia phy scratch pad register, - * read back the same reg and match the values written. - */ - AQ_API_MDIO_Write(PHY_ID, 0x1e, 0x300, 0xdead); - AQ_API_MDIO_Write(PHY_ID, 0x1e, 0x301, 0xbeaf); - reg1 = AQ_API_MDIO_Read(PHY_ID, 0x1e, 0x300); - reg2 = AQ_API_MDIO_Read(PHY_ID, 0x1e, 0x301); - if(reg1 != 0xdead && reg2 != 0xbeaf) { - fprintf (stderr, "Scratchpad Read/Write test fail\n"); - return (101); - } - - /* call the boot-load function */ - resultCode = AQ_API_WriteBootLoadImage(targetPorts, 1, provisioningAddresses, resultCodes, &imageSize, image, PHY_ID, &broadcastPort); - - switch (resultCode) - { - case 0: - printf("Image load good - mailbox CRC-16 matches\n"); - free (image); - close(sock); - return 0; - - case 1: - fprintf (stderr, "CRC-16 on file is bad\n"); - free (image); - close(sock); - return 1; - - case 2: - fprintf (stderr, "CRC-16 check on image load failed (mailbox CRC-16 check)\n"); - free (image); - close(sock); - return 2; - - default: - fprintf (stderr, "Invalid return code\n"); - free (image); - close(sock); - } - return 12; -} -/*@}*/ diff --git a/qca/aq-fw-download/src/src/AQ_API.c b/qca/aq-fw-download/src/src/AQ_API.c deleted file mode 100644 index 89e73344f..000000000 --- a/qca/aq-fw-download/src/src/AQ_API.c +++ /dev/null @@ -1,1021 +0,0 @@ -/*AQ_API.c*/ - -/************************************************************************************ -* Copyright (c) 2015, Aquantia -* -* Permission to use, copy, modify, and/or distribute this software for any -* purpose with or without fee is hereby granted, provided that the above -* copyright notice and this permission notice appear in all copies. -* -* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -* -* Description: -* -* This file contains the code for all of the API functions defined in AQ_API.h -* -************************************************************************************/ - - -/*! \file -* This file contains the code for all of the API functions defined in AQ_API.h - */ - -#include -#include - -#include "AQ_API.h" -#include "AQ_User.h" -#include "AQ_RegMacro.h" -#include "AQ_PlatformRoutines.h" -#include "AQ_RegMaps.h" -#include "AQ_ReturnCodes.h" - -#ifdef AQ_VERBOSE - #include - #include -#endif - - -#ifndef AQ_TIME_T_EXISTS - #ifndef AQ_MDIO_READS_PER_SECOND - #error AQ_MDIO_READS_PER_SECOND in AQ_User.h must be defined, as AQ_TIME_T_EXISTS is currently undefined! - #endif -#endif - -#ifdef AQ_TIME_T_EXISTS - #include -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef AQ_ENABLE_UP_BUSY_CHECKS - #ifdef AQ_VERBOSE - #define AQ_API_UP_BUSY_PRINT_STATEMENT printf("uP-busy check timed out.\n"); - #else - #define AQ_API_UP_BUSY_PRINT_STATEMENT /* nothing */ - #endif - - #ifdef AQ_TIME_T_EXISTS - #define AQ_API_UP_BUSY_TIMEOUT (CLOCKS_PER_SEC / 10) - - #define AQ_API_DECLARE_UP_BUSY_VARS AQ_API_Variable(AQ_GlobalGeneralStatus) \ - uint16_t uPbusy; \ - clock_t startTime; \ - AQ_boolean uPBusyTimeoutOccurred = False; - - #define AQ_API_CHECK_UP_NOT_BUSY AQ_API_Wait(1, port); \ - startTime = clock(); \ - do \ - { \ - AQ_API_Get(port->PHY_ID, AQ_GlobalGeneralStatus, processorIntensiveMdioOperationIn_Progress, uPbusy); \ - if ((clock() - startTime) > AQ_API_UP_BUSY_TIMEOUT) \ - { \ - AQ_API_UP_BUSY_PRINT_STATEMENT \ - uPBusyTimeoutOccurred = True; \ - break; \ - } \ - } while (uPbusy != 0); - #else - #define AQ_API_UP_BUSY_MAX_CHECKS (AQ_MDIO_READS_PER_SECOND * 5) - - #define AQ_API_DECLARE_UP_BUSY_VARS AQ_API_Variable(AQ_GlobalGeneralStatus) \ - uint16_t uPbusy; \ - uint32_t numChecks; \ - AQ_boolean uPBusyTimeoutOccurred = False; - - #define AQ_API_CHECK_UP_NOT_BUSY AQ_API_Wait(1, port); \ - numChecks = 0; \ - do \ - { \ - AQ_API_Get(port->PHY_ID, AQ_GlobalGeneralStatus, processorIntensiveMdioOperationIn_Progress, uPbusy); \ - if (numChecks++ > AQ_API_UP_BUSY_MAX_CHECKS) \ - { \ - AQ_API_UP_BUSY_PRINT_STATEMENT \ - uPBusyTimeoutOccurred = True; \ - break; \ - } \ - } while (uPbusy != 0); - #endif - - /* If a uP busy timeout occurred, return the corresponding return code; otherwise, return - * retval. retval should be a return code defined in AQ_ReturnCodes. */ - #define AQ_API_RETURN_UP_BUSY(retval) return (uPBusyTimeoutOccurred ? AQ_RET_UP_BUSY_TIMEOUT : retval); - -#else - #define AQ_API_DECLARE_UP_BUSY_VARS /* nothing */ - #define AQ_API_CHECK_UP_NOT_BUSY /* nothing */ - #define AQ_API_RETURN_UP_BUSY(retval) return retval; -#endif - - -/*! FW image version string maximum length. */ -#define AQ_VERSION_STRING_SIZE 0x40 - -/*! The byte offset from top of DRAM to the FW image version string. */ -#define AQ_VERSION_STRING_BLOCK_OFFSET 0x0200 - -/*! The byte address, in processor memory, of the start of the IRAM segment. */ -#define AQ_IRAM_BASE_ADDRESS 0x40000000 - -/*! The byte address, in processor memory, of the start of the DRAM segment. */ -#define AQ_DRAM_BASE_ADDRESS 0x3FFE0000 - -/*! The byte offset from the top of the PHY image to the header content (HHD devices). */ -#define AQ_PHY_IMAGE_HEADER_CONTENT_OFFSET_HHD 0x300 - -/*! The byte offset from the top of the PHY image to the header content (APPIA devices). */ -#define AQ_PHY_IMAGE_HEADER_CONTENT_OFFSET_APPIA 0 - -/*! The offset, from the start of DRAM, where the provisioning block begins. */ -#define AQ_PHY_IMAGE_PROVTABLE_OFFSET 0x680 - -/*! The offset, from the start of DRAM, where the provisioning block's ending address is recorded. */ -#define AQ_PHY_IMAGE_PROVTABLE_TERM_OFFSET 0x028C - -/*! The size of the space alloted within the PHY image for the provisioning table. */ -#define AQ_PHY_IMAGE_PROVTABLE_MAXSIZE 0x800 - -/*! The maximum number of polling cycles ever required before the FLASH interface is ready. */ -#define AQ_FLASH_INTERFACE_MAX_POLL_COUNT 20 - -/*! The maximum number of ports that can be MDIO bootloaded at once. */ -#define AQ_MAX_NUM_PHY_IDS 48 - -/*! The maximum allowed number of times to poll for debug-trace-freeze acknowledgement. */ -#define AQ_MAX_FREEZE_CHECKS 2000 - -/*! The maximum size of the debug trace buffer. */ -#define AQ_MAX_TRACE_BUFFER_LENGTH 8192 - -/*! The maximum allowed number of times to poll for SERDES Rx eye measurement done. */ -#define AQ_SERDESEYE_MAX_DONE_CHECKS 50 - -/*! The maximum allowed number of times to poll for PIF mailbox status. */ -#define MAX_NUM_COMMAND_STATUS_POLLS 700 - -/* REGDOC_START */ - - -/********************************************************************************************************************** -* MDIO Boot Load -**********************************************************************************************************************/ - -const uint16_t AQ_CRC16Table[256] = {0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50a5, 0x60c6, 0x70e7, - 0x8108, 0x9129, 0xa14a, 0xb16b, 0xc18c, 0xd1ad, 0xe1ce, 0xf1ef, - 0x1231, 0x0210, 0x3273, 0x2252, 0x52b5, 0x4294, 0x72f7, 0x62d6, - 0x9339, 0x8318, 0xb37b, 0xa35a, 0xd3bd, 0xc39c, 0xf3ff, 0xe3de, - 0x2462, 0x3443, 0x0420, 0x1401, 0x64e6, 0x74c7, 0x44a4, 0x5485, - 0xa56a, 0xb54b, 0x8528, 0x9509, 0xe5ee, 0xf5cf, 0xc5ac, 0xd58d, - 0x3653, 0x2672, 0x1611, 0x0630, 0x76d7, 0x66f6, 0x5695, 0x46b4, - 0xb75b, 0xa77a, 0x9719, 0x8738, 0xf7df, 0xe7fe, 0xd79d, 0xc7bc, - 0x48c4, 0x58e5, 0x6886, 0x78a7, 0x0840, 0x1861, 0x2802, 0x3823, - 0xc9cc, 0xd9ed, 0xe98e, 0xf9af, 0x8948, 0x9969, 0xa90a, 0xb92b, - 0x5af5, 0x4ad4, 0x7ab7, 0x6a96, 0x1a71, 0x0a50, 0x3a33, 0x2a12, - 0xdbfd, 0xcbdc, 0xfbbf, 0xeb9e, 0x9b79, 0x8b58, 0xbb3b, 0xab1a, - 0x6ca6, 0x7c87, 0x4ce4, 0x5cc5, 0x2c22, 0x3c03, 0x0c60, 0x1c41, - 0xedae, 0xfd8f, 0xcdec, 0xddcd, 0xad2a, 0xbd0b, 0x8d68, 0x9d49, - 0x7e97, 0x6eb6, 0x5ed5, 0x4ef4, 0x3e13, 0x2e32, 0x1e51, 0x0e70, - 0xff9f, 0xefbe, 0xdfdd, 0xcffc, 0xbf1b, 0xaf3a, 0x9f59, 0x8f78, - 0x9188, 0x81a9, 0xb1ca, 0xa1eb, 0xd10c, 0xc12d, 0xf14e, 0xe16f, - 0x1080, 0x00a1, 0x30c2, 0x20e3, 0x5004, 0x4025, 0x7046, 0x6067, - 0x83b9, 0x9398, 0xa3fb, 0xb3da, 0xc33d, 0xd31c, 0xe37f, 0xf35e, - 0x02b1, 0x1290, 0x22f3, 0x32d2, 0x4235, 0x5214, 0x6277, 0x7256, - 0xb5ea, 0xa5cb, 0x95a8, 0x8589, 0xf56e, 0xe54f, 0xd52c, 0xc50d, - 0x34e2, 0x24c3, 0x14a0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405, - 0xa7db, 0xb7fa, 0x8799, 0x97b8, 0xe75f, 0xf77e, 0xc71d, 0xd73c, - 0x26d3, 0x36f2, 0x0691, 0x16b0, 0x6657, 0x7676, 0x4615, 0x5634, - 0xd94c, 0xc96d, 0xf90e, 0xe92f, 0x99c8, 0x89e9, 0xb98a, 0xa9ab, - 0x5844, 0x4865, 0x7806, 0x6827, 0x18c0, 0x08e1, 0x3882, 0x28a3, - 0xcb7d, 0xdb5c, 0xeb3f, 0xfb1e, 0x8bf9, 0x9bd8, 0xabbb, 0xbb9a, - 0x4a75, 0x5a54, 0x6a37, 0x7a16, 0x0af1, 0x1ad0, 0x2ab3, 0x3a92, - 0xfd2e, 0xed0f, 0xdd6c, 0xcd4d, 0xbdaa, 0xad8b, 0x9de8, 0x8dc9, - 0x7c26, 0x6c07, 0x5c64, 0x4c45, 0x3ca2, 0x2c83, 0x1ce0, 0x0cc1, - 0xef1f, 0xff3e, 0xcf5d, 0xdf7c, 0xaf9b, 0xbfba, 0x8fd9, 0x9ff8, - 0x6e17, 0x7e36, 0x4e55, 0x5e74, 0x2e93, 0x3eb2, 0x0ed1, 0x1ef0}; - -/*! \addtogroup writingImages - @{ -*/ - -/*! Prepare the specified port for MDIO bootloading. Disables the daisy-chain, - * and explicitly sets the port's provisioningAddress. */ -void AQ_API_EnableMDIO_BootLoadMode -( - /*! The target PHY port.*/ - AQ_API_Port* port, - /*! The provisioning address to use when the FW starts and applies the - * bootloaded image's provisioned values. */ - unsigned int provisioningAddress -) -{ - AQ_API_Variable(AQ_GlobalNvrProvisioning) - - AQ_API_DeclareLocalStruct(AQ_GlobalReservedProvisioning, globalReservedProvisioning) - - - /* disable the daisy-chain */ - /* REGDOC: Read-Modify-Write bitfield (HHD/APPIA: 1E.C452.0) */ - AQ_API_Set(port->PHY_ID, AQ_GlobalNvrProvisioning, nvrDaisyChainDisable, 1); - - /* override the hop-count */ - AQ_API_AssignWordOfLocalStruct(globalReservedProvisioning, 1, - /* REGDOC: Read register (HHD/APPIA: 1E.C470 + 1) */ - AQ_API_ReadRegister(port->PHY_ID, AQ_GlobalReservedProvisioning, 1)); - /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C471.5:0) */ - AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalReservedProvisioning, globalReservedProvisioning, - daisy_chainHop_countOverrideValue, provisioningAddress); - /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C471.6) */ - AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalReservedProvisioning, globalReservedProvisioning, - enableDaisy_chainHop_countOverride, 1); - /* REGDOC: Write register (HHD/APPIA: 1E.C470 + 1) */ - AQ_API_WriteRegister(port->PHY_ID, AQ_GlobalReservedProvisioning, 1, - AQ_API_WordOfLocalStruct(globalReservedProvisioning, 1)); - - return; -} - - -/*! Prepare the specified port for MDIO bootloading, and set the temporary MDIO - * address to be used during the bootload process. Disables the daisy-chain, - * and explicitly sets the port's provisioningAddress. */ -void AQ_API_EnableGangLoadMode -( - /*! The target PHY port.*/ - AQ_API_Port* port, - /*! The provisioning address to use when the FW starts and applies the - * bootloaded image's provisioned values. */ - unsigned int provisioningAddress, - /*! The PHY's MDIO address will be changed to this value during the - * bootload process. */ - unsigned int gangLoadAddress -) -{ - /*AQ_API_Variable_DeviceRestricted(APPIA, AQ_GlobalGeneralProvisioning)*/ - AQ_API_Variable(AQ_GlobalGeneralProvisioning) - - - /* Get ready for MDIO bootloading. */ - AQ_API_EnableMDIO_BootLoadMode(port, provisioningAddress); - - /* Enable gangload mode. After doing this, the PHY will be - * addressable at the MDIO address indicated by gangLoadAddress. - * Now that the PHY is in gangload mode, MDIO reads are prohibited - * until AQ_API_DisableGangLoadMode is called. */ - if (AQ_DEVICE_APPIA == port->device) - { - /* REGDOC: Read-Modify-Write bitfield (APPIA: 1E.C440.8:4) */ - AQ_API_Set_DeviceRestricted(APPIA, port->PHY_ID, AQ_GlobalGeneralProvisioning, - gangLoadMdioAddress, gangLoadAddress); - } - else if (AQ_DEVICE_HHD == port->device) - { - /* REGDOC: Read-Modify-Write bitfield (HHD: 1E.C447.4:0) */ - AQ_API_Set_DeviceRestricted(HHD, port->PHY_ID, AQ_GlobalGeneralProvisioning, - mdioBroadcastAddressConfiguration, gangLoadAddress); - /* REGDOC: Read-Modify-Write bitfield (HHD: 1E.C441.E) */ - AQ_API_Set_DeviceRestricted(HHD, port->PHY_ID, AQ_GlobalGeneralProvisioning, - mdioBroadcastModeEnable, 1); - } - - return; -} - - -/*! Restore the PHY's MDIO address to the pin-specified value. Should be - * called when MDIO bootloading is complete, to return to normal MDIO - * addressing. - * This is a gang-load function, hence write-only! */ -void AQ_API_DisableGangLoadMode -( - /*! The target PHY port.*/ - AQ_API_Port* port, - /*! The value to write to of AQ_GlobalGeneralProvisioning.u1.word_1. */ - uint16_t origVal_GGP1 -) -{ - AQ_API_DeclareLocalStruct(AQ_GlobalGeneralProvisioning, globalGeneralProvisioning) - - - /* Restore the original value of globalGeneralProvisioning.u1, and set - * the MDIO address reset bit. This will cause the MDIO address to be - * reset to the value indicated by the pins. */ - AQ_API_AssignWordOfLocalStruct(globalGeneralProvisioning, 1, origVal_GGP1); - if (AQ_DEVICE_APPIA == port->device) - { - /* REGDOC: Assign to local representation of bitfield (APPIA: 1E.C441.2) */ - AQ_API_AssignBitfieldOfLocalStruct_DeviceRestricted(APPIA, AQ_GlobalGeneralProvisioning, - globalGeneralProvisioning, mdioAddressReset, 1); - } - else if (AQ_DEVICE_HHD == port->device) - { - /* REGDOC: Assign to local representation of bitfield (HHD: 1E.C441.E) */ - AQ_API_AssignBitfieldOfLocalStruct_DeviceRestricted(HHD, AQ_GlobalGeneralProvisioning, - globalGeneralProvisioning, mdioBroadcastModeEnable, 0); - } - /* REGDOC: Write register (HHD/APPIA: 1E.C440 + 1) */ - AQ_API_WriteRegister(port->PHY_ID, AQ_GlobalGeneralProvisioning, 1, - AQ_API_WordOfLocalStruct(globalGeneralProvisioning, 1)); - - /* The PHY has now exited gang-load mode. */ - return; -} - - -AQ_Retcode AQ_API_WriteBootLoadImageWithProvTable -( - AQ_API_Port** ports, - unsigned int numPorts, - unsigned int* provisioningAddresses, - AQ_Retcode* resultCodes, - uint32_t* imageSizePointer, - uint8_t* image, - uint8_t gangload_MDIO_address, - AQ_API_Port* gangloadPort, - uint32_t* provTableSizePointer, - uint8_t* provTableImage -) -{ - /*------------------------------------- NOTE!!!!!!!!!! ----------------------------------------------------------*/ - /* This function uses word level writes here as in gang-load mode we cannot do a read in a read-modify-write */ - /* operation */ - /*---------------------------------------------------------------------------------------------------------------*/ - - AQ_API_Variable_DeviceRestricted(APPIA, AQ_GlobalPinStatus) - - AQ_API_DeclareLocalStruct(AQ_GlobalControl, globalControl) - AQ_API_DeclareLocalStruct(AQ_GlobalMailboxInterface, globalMailboxInterface) - - AQ_API_Port* port; - uint32_t primaryHeaderPtr = 0x00000000; - uint32_t primaryIramPtr = 0x00000000; - uint32_t primaryDramPtr = 0x00000000; - uint32_t primaryIramSize = 0x00000000; - uint32_t primaryDramSize = 0x00000000; - uint32_t terminatorPtr = 0x00000000; - uint32_t phyImageHeaderContentOffset; - uint32_t i; - uint32_t j; - uint32_t imageSize; - uint32_t provTableImageSize = 0; - uint32_t bytePointer; - uint32_t byteSize; - uint32_t dWordSize; -#ifdef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE - uint32_t countPendingOps; /* A count of block MDIO operation pending... necessary to keep a count - in order to ensure we don't exceed the maximum pending operations. */ -#endif - uint16_t msw; - uint16_t lsw; - uint16_t crc16Calculated; - uint16_t provTableCrc16Calculated; - uint16_t fileCRC; - uint16_t provTableFileCRC; - uint16_t mailboxCRC; - uint16_t mailboxWrite; - uint16_t bootLoadMode; - uint16_t recordedGGP1Values[AQ_MAX_NUM_PHY_IDS]; /* When entering/exiting gangload mode, we record and restore - the AQ_GlobalGeneralProvisioning.u1 register values. */ - - - /* store the CRC-16 for the image, which is the last two bytes */ - imageSize = *imageSizePointer; - fileCRC = image[imageSize-2] << 8 | image[imageSize-1]; - - /*------------------------------------- Check the image integrity ------------------------------------------------*/ - crc16Calculated = 0x0000; - for (i = 0; i < imageSize-2; i++) - { - crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ image[i]]; - } - - if (crc16Calculated != fileCRC) - { - #ifdef AQ_VERBOSE - printf ("CRC check failed on image file (expected 0x%X, found 0x%X)\n", - fileCRC, crc16Calculated); - #endif - for (j = 0; j < numPorts; j++) - { - /* Before returning, set ALL result codes to indicate "bad image". */ - resultCodes[j] = AQ_RET_FLASH_IMAGE_CORRUPT; - } - return AQ_RET_ERROR; - } -#ifdef AQ_VERBOSE - else - { - printf ("CRC check good on image file (0x%04X)\n", crc16Calculated); - } -#endif - - /*-------------------------------- Check the provisioning table image integrity ----------------------------------*/ - if (provTableSizePointer != NULL && provTableImage != NULL) - { - provTableImageSize = (*provTableSizePointer) - 2; - provTableFileCRC = provTableImage[provTableImageSize + 1] << 8 | - provTableImage[provTableImageSize]; - - provTableCrc16Calculated = 0x0000; - for (i = 0; i < provTableImageSize; i++) - { - provTableCrc16Calculated = ((provTableCrc16Calculated & 0xFF) << 8) ^ - AQ_CRC16Table[(provTableCrc16Calculated >> 8) ^ provTableImage[i]]; - } - - if (provTableCrc16Calculated != provTableFileCRC) - { - #ifdef AQ_VERBOSE - printf ("CRC check failed on provisioning table file (expected 0x%X, found 0x%X)\n", - provTableFileCRC, provTableCrc16Calculated); - #endif - for (j = 0; j < numPorts; j++) - { - /* Before returning, set ALL result codes to indicate "bad image". */ - resultCodes[j] = AQ_RET_FLASH_IMAGE_CORRUPT; - } - return AQ_RET_ERROR; - } - #ifdef AQ_VERBOSE - else - { - printf ("CRC check good on provisioning table file (0x%04X)\n", - provTableCrc16Calculated); - } - #endif - } - - /*------------------------ Check that all provisioning addresses are in the proper range. ------------------------*/ - for (j = 0; j < numPorts; j++) - { - if (provisioningAddresses[j] > 47) - { - #ifdef AQ_VERBOSE - printf ("Provisioning address out of range 0-47 (index %u: %d)\n", j, provisioningAddresses[j]); - #endif - for (j = 0; j < numPorts; j++) - { - /* Before returning, set ALL result codes to indicate "provisioning address out-of-range". */ - resultCodes[j] = AQ_RET_BOOTLOAD_PROVADDR_OOR; - } - return AQ_RET_ERROR; - } - } - - /*--------------------------- Store 1E.C441 values for later use. Enforce uniformity. ---------------------------*/ - for (j = 0; j < numPorts; j++) - { - /* Record the original value of AQ_GlobalGeneralProvisioning.u1.word_1, - * so that we can restore it later after exiting gangload mode. */ - port = ports[j]; - /* REGDOC: Read register (HHD/APPIA: 1E.C440 + 1) */ - recordedGGP1Values[j] = AQ_API_ReadRegister(port->PHY_ID, AQ_GlobalGeneralProvisioning, 1); - - /* If any of the PHYs' GGP1 values don't match the others, set the appropriate - * error code and return. */ - if (j > 0 && recordedGGP1Values[j] != recordedGGP1Values[0]) - { - #ifdef AQ_VERBOSE - printf ("Non-uniform value of 1E.C441 found (expected 0x%X, found 0x%X)\n", - recordedGGP1Values[0], recordedGGP1Values[j]); - #endif - for (j = 0; j < numPorts; j++) - { - /* Before returning, set ALL result codes to indicate "non-uniform GGP1 values". */ - resultCodes[j] = AQ_RET_BOOTLOAD_NONUNIFORM_REGVALS; - } - return AQ_RET_ERROR; - } - } - - /*--------------------------- Put each PHY into gangload mode at the specified address ---------------------------*/ - for (j = 0; j < numPorts; j++) - { - AQ_API_EnableGangLoadMode(ports[j], provisioningAddresses[j], gangload_MDIO_address); - } - /* Set up the port context for using device-restricted macros while in - * gangload mode. */ - port = gangloadPort; - - /*------------------------------------- Stall the uP ------------------------------------------------------------*/ - AQ_API_AssignWordOfLocalStruct(globalControl, 1, 0x0000); - /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.6) */ - AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upRunStallOverride, 1); - /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.0) */ - AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upRunStall, 1); - /* REGDOC: Write register (HHD/APPIA: 1E.C000 + 1) */ - AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalControl, 1, - AQ_API_WordOfLocalStruct(globalControl, 1)); - - /*------------------------------------- Initialize the mailbox write command -------------------------------------*/ - AQ_API_AssignWordOfLocalStruct(globalMailboxInterface, 0, 0x0000); - /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.0200.E) */ - AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalMailboxInterface, globalMailboxInterface, upMailboxWriteMode, 1); - /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.0200.F) */ - AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalMailboxInterface, globalMailboxInterface, upMailboxExecuteOperation, 1); - mailboxWrite = AQ_API_WordOfLocalStruct(globalMailboxInterface, 0); - - /*------------------------------------- Read the segment addresses and sizes -------------------------------------*/ - primaryHeaderPtr = (((image[0x9] & 0x0F) << 8) | image[0x8]) << 12; - - if (AQ_DEVICE_APPIA == port->device) - phyImageHeaderContentOffset = AQ_PHY_IMAGE_HEADER_CONTENT_OFFSET_APPIA; - else /* HHD */ - phyImageHeaderContentOffset = AQ_PHY_IMAGE_HEADER_CONTENT_OFFSET_HHD; - - primaryIramPtr = (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0x4 + 2] << 16) | - (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0x4 + 1] << 8) | - image[primaryHeaderPtr + phyImageHeaderContentOffset + 0x4]; - primaryIramSize = (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0x7 + 2] << 16) | - (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0x7 + 1] << 8) | - image[primaryHeaderPtr + phyImageHeaderContentOffset + 0x7]; - primaryDramPtr = (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0xA + 2] << 16) | - (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0xA + 1] << 8) | - image[primaryHeaderPtr + phyImageHeaderContentOffset + 0xA]; - primaryDramSize = (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0xD + 2] << 16) | - (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0xD + 1] << 8) | - image[primaryHeaderPtr + phyImageHeaderContentOffset + 0xD]; - - if (AQ_DEVICE_HHD == port->device) - { - primaryIramPtr += primaryHeaderPtr; - primaryDramPtr += primaryHeaderPtr; - } - -#ifdef AQ_VERBOSE - printf ("\nSegment Addresses and Sizes as read from the PHY ROM image header:\n\n"); - printf ("Primary Iram Address: 0x%x\n", primaryIramPtr); - printf ("Primary Iram Size: 0x%x\n", primaryIramSize); - printf ("Primary Dram Address: 0x%x\n", primaryDramPtr); - printf ("Primary Dram Size: 0x%x\n\n", primaryDramSize); -#endif - - /*----------------------------- Merge the provisioning table into the main image ---------------------------------*/ - if (provTableSizePointer != NULL && provTableImage != NULL) - { - /* Locate the terminator of the built-in provisioning table */ - terminatorPtr = primaryDramPtr + - ((image[primaryDramPtr + AQ_PHY_IMAGE_PROVTABLE_TERM_OFFSET + 1] << 8) | - image[primaryDramPtr + AQ_PHY_IMAGE_PROVTABLE_TERM_OFFSET]); - - #ifdef AQ_VERBOSE - printf("Supplied Provisioning Table At Address: 0x%x\n\n", terminatorPtr); - #endif - - /* Check that the supplied provisioning table will fit within the alloted - * space. */ - if (terminatorPtr - (primaryDramPtr + AQ_PHY_IMAGE_PROVTABLE_OFFSET) + - provTableImageSize > AQ_PHY_IMAGE_PROVTABLE_MAXSIZE) - { - for (j = 0; j < numPorts; j++) - { - /* Before returning, set ALL result codes to indicate "provisioning - * table too large". */ - resultCodes[j] = AQ_RET_BOOTLOAD_PROVTABLE_TOO_LARGE; - } - return AQ_RET_ERROR; - } - - /* Write the supplied provisioning table into the image, starting at the - * terminator address. */ - for (i = 0; i < provTableImageSize; i++) - { - image[terminatorPtr + i] = provTableImage[i]; - } - } - - /*------------------------------------- Load IRAM and DRAM -------------------------------------------------------*/ - /* clear the mailbox CRC */ - AQ_API_AssignWordOfLocalStruct(globalMailboxInterface, 0, 0x0000); - /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.0200.C) */ - AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalMailboxInterface, globalMailboxInterface, resetUpMailboxCrc, 1); - /* REGDOC: Write register (HHD/APPIA: 1E.0200) */ - AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, - AQ_API_WordOfLocalStruct(globalMailboxInterface, 0)); - /* REGDOC: Write register (HHD/APPIA: 1E.0200) */ - AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, 0x0000); - - crc16Calculated = 0; /* This is to calculate what was written through the mailbox */ - - /* load the IRAM */ -#ifdef AQ_VERBOSE - printf ("\nLoading IRAM:\n\n"); -#endif - - /* dWord align the address: note the image addressing is byte based, but is properly aligned on dWord - boundaries, so the 2 LSbits of the block start are always zero. */ - msw = (uint16_t) (AQ_IRAM_BASE_ADDRESS >> 16); - AQ_API_AssignWordOfLocalStruct(globalMailboxInterface, 3, 0x0000); - /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.0203.1:0) */ - AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalMailboxInterface, globalMailboxInterface, - upMailboxAddressLSW , (AQ_IRAM_BASE_ADDRESS & 0xFFFF) >> 2); - lsw = AQ_API_WordOfLocalStruct(globalMailboxInterface, 3); - /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 2) */ - AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 2, msw); /* MSW */ - /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 3) */ - AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 3, lsw); /* LSW */ - - - /* set block size so that there are from 0-3 bytes remaining */ - byteSize = primaryIramSize; - dWordSize = byteSize >> 2; - - bytePointer = primaryIramPtr; -#ifdef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE - countPendingOps = 0; -#endif - for (i = 0; i < dWordSize; i++) - { - /* write 4 bytes of data */ - lsw = (image[bytePointer+1] << 8) | image[bytePointer]; - bytePointer += 2; - msw = (image[bytePointer+1] << 8) | image[bytePointer]; - bytePointer += 2; - - #ifdef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE - AQ_API_BlockWriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 4, msw); - AQ_API_BlockWriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 5, lsw); - AQ_API_BlockWriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, mailboxWrite); - - countPendingOps += 3; - /* Check if we've filled our output buffer, and if so, flush. */ - if (countPendingOps >= AQ_API_MDIO_MaxBlockOperations() - 3 ) - { - AQ_API_MDIO_BlockOperationExecute (gangloadPort->PHY_ID); - countPendingOps = 0; - } - #else - /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 4) */ - AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 4, msw); - /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 5) */ - AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 5, lsw); - /* REGDOC: Write register (HHD/APPIA: 1E.0200) */ - AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, mailboxWrite); - #endif - - /* update the calculated CRC */ - crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (msw >> 8)]; - crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (msw & 0xFF)]; - crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (lsw >> 8)]; - crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (lsw & 0xFF)]; - - #ifdef AQ_VERBOSE - if (i && ((i % 512) == 0)) printf(" Byte: %X:\n", i << 2); - #endif - } - -#ifdef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE - /* flush the output buffer one last time. */ - AQ_API_MDIO_BlockOperationExecute(gangloadPort->PHY_ID); - countPendingOps = 0; -#endif - - /* Note: this final write right-justifies non-dWord data in the final dWord */ - switch (byteSize & 0x3) - { - case 0x1: - /* write 1 byte of data */ - lsw = image[bytePointer++]; - msw = 0x0000; - /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 4) */ - AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 4, msw); - /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 5) */ - AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 5, lsw); - - /* no polling */ - /* REGDOC: Write register (HHD/APPIA: 1E.0200) */ - AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, mailboxWrite); - break; - - case 0x2: - /* write 2 bytes of data */ - lsw = (image[bytePointer+1] << 8) | image[bytePointer]; - bytePointer += 2; - msw = 0x0000; - /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 4) */ - AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 4, msw); - /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 5) */ - AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 5, lsw); - - /* no polling */ - /* REGDOC: Write register (HHD/APPIA: 1E.0200) */ - AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, mailboxWrite); - break; - - case 0x3: - /* write 3 bytes of data */ - lsw = (image[bytePointer+1] << 8) | image[bytePointer]; - bytePointer += 2; - msw = image[bytePointer++]; - /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 4) */ - AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 4, msw); - /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 5) */ - AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 5, lsw); - - /* no polling */ - /* REGDOC: Write register (HHD/APPIA: 1E.0200) */ - AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, mailboxWrite); - break; - } - - if (byteSize & 0x3) - { - /* update the calculated CRC */ - crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (msw >> 8)]; - crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (msw & 0xFF)]; - crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (lsw >> 8)]; - crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (lsw & 0xFF)]; - } - - /* load the DRAM */ -#ifdef AQ_VERBOSE - printf ("\nCRC-16 after loading IRAM: 0x%X\n", crc16Calculated); - printf ("\nLoading DRAM:\n\n"); -#endif - - /* dWord align the address: note the image addressing is byte based, but is properly aligned on dWord - boundaries, so the 2 LSbits of the block start are always zero. */ - msw = (uint16_t) (AQ_DRAM_BASE_ADDRESS >> 16); - AQ_API_AssignWordOfLocalStruct(globalMailboxInterface, 3, 0x0000); - /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.0203.1:0) */ - AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalMailboxInterface, globalMailboxInterface, - upMailboxAddressLSW, (AQ_DRAM_BASE_ADDRESS & 0xFFFF) >> 2); - lsw = AQ_API_WordOfLocalStruct(globalMailboxInterface, 3); - /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 2) */ - AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 2, msw); /* MSW */ - /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 3) */ - AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 3, lsw); /* LSW */ - - - /* set block size so that there are from 0-3 bytes remaining */ - byteSize = primaryDramSize; - dWordSize = byteSize >> 2; - - bytePointer = primaryDramPtr; - for (i = 0; i < dWordSize; i++) - { - /* write 4 bytes of data */ - lsw = (image[bytePointer+1] << 8) | image[bytePointer]; - bytePointer += 2; - msw = (image[bytePointer+1] << 8) | image[bytePointer]; - bytePointer += 2; - - #ifdef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE - AQ_API_BlockWriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 4, msw); - AQ_API_BlockWriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 5, lsw); - AQ_API_BlockWriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, mailboxWrite); - - countPendingOps += 3; - /* Check if we've filled our output buffer, and if so, flush. */ - if (countPendingOps >= AQ_API_MDIO_MaxBlockOperations() - 3 ) - { - AQ_API_MDIO_BlockOperationExecute (gangloadPort->PHY_ID); - countPendingOps = 0; - } - #else - /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 4) */ - AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 4, msw); - /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 5) */ - AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 5, lsw); - /* REGDOC: Write register (HHD/APPIA: 1E.0200) */ - AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, mailboxWrite); - #endif - - /* update the calculated CRC */ - crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (msw >> 8)]; - crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (msw & 0xFF)]; - crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (lsw >> 8)]; - crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (lsw & 0xFF)]; - - #ifdef AQ_VERBOSE - if (i && ((i % 512) == 0)) printf(" Byte: %X:\n", i << 2); - #endif - } - -#ifdef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE - /* flush the output buffer one last time. */ - AQ_API_MDIO_BlockOperationExecute(gangloadPort->PHY_ID); - countPendingOps = 0; -#endif - - /* Note: this final write right-justifies non-dWord data in the final dWord */ - switch (byteSize & 0x3) - { - case 0x1: - /* write 1 byte of data */ - lsw = image[bytePointer++]; - msw = 0x0000; - /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 4) */ - AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 4, msw); - /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 5) */ - AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 5, lsw); - - /* no polling */ - /* REGDOC: Write register (HHD/APPIA: 1E.0200) */ - AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, mailboxWrite); - break; - - case 0x2: - /* write 2 bytes of data */ - lsw = (image[bytePointer+1] << 8) | image[bytePointer]; - bytePointer += 2; - msw = 0x0000; - /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 4) */ - AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 4, msw); - /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 5) */ - AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 5, lsw); - - /* no polling */ - /* REGDOC: Write register (HHD/APPIA: 1E.0200) */ - AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, mailboxWrite); - break; - - case 0x3: - /* write 3 bytes of data */ - lsw = (image[bytePointer+1] << 8) | image[bytePointer]; - bytePointer += 2; - msw = image[bytePointer++]; - /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 4) */ - AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 4, msw); - /* REGDOC: Write register (HHD/APPIA: 1E.0200 + 5) */ - AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 5, lsw); - - /* no polling */ - /* REGDOC: Write register (HHD/APPIA: 1E.0200) */ - AQ_API_WriteRegister(gangloadPort->PHY_ID, AQ_GlobalMailboxInterface, 0, mailboxWrite); - break; - } - - if (byteSize & 0x3) - { - /* update the calculated CRC */ - crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (msw >> 8)]; - crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (msw & 0xFF)]; - crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (lsw >> 8)]; - crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (lsw & 0xFF)]; - } - - /*------------------------------------- Exit gangload mode -------------------------------------------------------*/ - AQ_API_DisableGangLoadMode(gangloadPort, recordedGGP1Values[0]); - - /*------------------------------------- Check mailbox CRCs -------------------------------------------------------*/ - /* check to make sure the mailbox CRC matches the calculated CRC */ - /*foundMailboxCRCMismatch = False;*/ - for (j = 0; j < numPorts; j++) - { - /* REGDOC: Read register (HHD/APPIA: 1E.0200 + 1) */ - mailboxCRC = AQ_API_ReadRegister(ports[j]->PHY_ID,AQ_GlobalMailboxInterface, 1); - if (mailboxCRC != crc16Calculated) - { - #ifdef AQ_VERBOSE - printf("\n%uth port: Mailbox CRC-16 (0x%X) does not match calculated CRC-16 (0x%X)\n", - j, mailboxCRC, crc16Calculated); - #endif - /* Note that we can't just return here, because we still need to - * release the uPs for the other PHYs that might have been - * bootloaded successfully. */ - resultCodes[j] = AQ_RET_BOOTLOAD_CRC_MISMATCH; - } - #ifdef AQ_VERBOSE - else - { - printf("\n%uth port: Image load good - mailbox CRC-16 matches (0x%X)\n", - j, mailboxCRC); - resultCodes[j] = AQ_RET_OK; - } - #endif - } - - /*------------------------------------- Clear any resets ---------------------------------------------------------*/ - for (j = 0; j < numPorts; j++) - { - /* REGDOC: Write register (HHD/APPIA: 1E.0000) */ - AQ_API_WriteRegister(ports[j]->PHY_ID,AQ_GlobalStandardControl_1, 0, 0x0000); - } - - /*------------------------------------- Release the uP -----------------------------------------------------------*/ - AQ_API_AssignWordOfLocalStruct(globalControl, 1, 0x0000); - /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.6) */ - AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upRunStallOverride, 1); - /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.0) */ - AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upRunStall, 1); - for (j = 0; j < numPorts; j++) - { - /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.F) */ - AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upReset, 0); - /* REGDOC: Write register (HHD/APPIA: 1E.C000 + 1) */ - AQ_API_WriteRegister(ports[j]->PHY_ID,AQ_GlobalControl, 1, - AQ_API_WordOfLocalStruct(globalControl, 1)); - /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.F) */ - AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upReset, 1); - /* REGDOC: Write register (HHD/APPIA: 1E.C000 + 1) */ - AQ_API_WriteRegister(ports[j]->PHY_ID,AQ_GlobalControl, 1, - AQ_API_WordOfLocalStruct(globalControl, 1)); - } - - /* Need to wait at least 100us. */ - AQ_API_Wait(1, ports[0]); - - /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.F) */ - AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upReset, 0); - /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.0) */ - AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upRunStall, 0); - for (j = 0; j < numPorts; j++) - { - if (AQ_DEVICE_APPIA == port->device) - { - /* If the BOOT_LD pins are set to MDIO boot load mode, we can't clear the - * uP run stall override bit. If we did, the uP would stall. */ - /* REGDOC: Read bitfield (APPIA: 1E.C840.E:D) */ - AQ_API_Get_DeviceRestricted(APPIA, j, AQ_GlobalPinStatus, mdioBootLoad, bootLoadMode); - if (bootLoadMode == 0x1) - { - /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.6) */ - AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upRunStallOverride, 1); - } - else - { - /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.6) */ - AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upRunStallOverride, 0); - } - } - else - { - /* For post-APPIA devices, always set the uP stall override bit to - * smooth over any packaging differences WRT the boot load pin. */ - /* REGDOC: Assign to local representation of bitfield (HHD/APPIA: 1E.C001.6) */ - AQ_API_AssignBitfieldOfLocalStruct(AQ_GlobalControl, globalControl, upRunStallOverride, 1); - } - - /* REGDOC: Write register (HHD/APPIA: 1E.C000 + 1) */ - AQ_API_WriteRegister(ports[j]->PHY_ID,AQ_GlobalControl, 1, - AQ_API_WordOfLocalStruct(globalControl, 1)); - } - - /* NOTE!!! We can't re-enable the daisy-chain here, as this will overwrite the IRAM and DRAM with the FLASH contents*/ - - /* If any of the ports was not bootloaded successfully, return AQ_RET_ERROR */ - for (j = 0; j < numPorts; j++) - { - if (resultCodes[j] != AQ_RET_OK) - return AQ_RET_ERROR; - } - - /* All ports were bootloaded successfully. */ - return AQ_RET_OK; -} - - -AQ_Retcode AQ_API_WriteBootLoadImage -( - AQ_API_Port** ports, - unsigned int numPorts, - unsigned int* provisioningAddresses, - AQ_Retcode* resultCodes, - uint32_t* imageSizePointer, - uint8_t* image, - uint8_t gangload_MDIO_address, - AQ_API_Port* gangloadPort -) -{ - return AQ_API_WriteBootLoadImageWithProvTable(ports, numPorts, - provisioningAddresses, resultCodes, imageSizePointer, image, - gangload_MDIO_address, gangloadPort, NULL, NULL); -} - - -AQ_Retcode AQ_API_EnableDaisyChain -( - /*! The target PHY port.*/ - AQ_API_Port* port -) -{ - - /* declare local variables */ - AQ_API_Variable(AQ_GlobalNvrProvisioning) - AQ_API_Variable(AQ_GlobalReservedProvisioning) - - /* disable the hop-count override */ - /* REGDOC: Read-Modify-Write bitfield (HHD/APPIA: 1E.C471.6) */ - AQ_API_Set(port->PHY_ID, AQ_GlobalReservedProvisioning, enableDaisy_chainHop_countOverride, 0); - - /* enable the daisy-chain */ - /* REGDOC: Read-Modify-Write bitfield (HHD/APPIA: 1E.C452.0) */ - AQ_API_Set(port->PHY_ID, AQ_GlobalNvrProvisioning, nvrDaisyChainDisable, 0); - - return AQ_RET_OK; -} - -/*@}*/ - - -#ifdef __cplusplus -} -#endif diff --git a/qca/aq-fw-download/src/src/AQ_PhyInterface.c b/qca/aq-fw-download/src/src/AQ_PhyInterface.c deleted file mode 100644 index 6a8fce125..000000000 --- a/qca/aq-fw-download/src/src/AQ_PhyInterface.c +++ /dev/null @@ -1,141 +0,0 @@ -/* AQ_PhyInterface.c */ - -/************************************************************************************ -* Copyright (c) 2015, Aquantia -* -* Permission to use, copy, modify, and/or distribute this software for any -* purpose with or without fee is hereby granted, provided that the above -* copyright notice and this permission notice appear in all copies. -* -* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -* -* $Revision: #12 $ -* -* $DateTime: 2015/02/25 15:34:49 $ -* -* $Label: $ -* -************************************************************************************/ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include - -#include "AQ_PhyInterface.h" -#include "AQ_PlatformRoutines.h" - -#define MII_ADDR_C45 (0x8000) - -extern int sock; -extern char devname[7]; - -static struct ifreq ifr; - -/*! Provides generic synchronous PHY register write functionality. It is the - * responsibility of the system designer to provide the specific MDIO address - * pointer updates, etc. in order to accomplish this write operation. - * It will be assumed that the write has been completed by the time this - * function returns.*/ -void AQ_API_MDIO_Write( - /*! Uniquely identifies the port within the system. AQ_Port must be - * defined to a whatever data type is suitable for the platform.*/ - AQ_Port PHY_ID, - /*! The address of the MMD within the target PHY. */ - unsigned int MMD, - /*! The 16-bit address of the PHY register being written. */ - unsigned int address, - /*! The 16-bits of data to write to the specified PHY register. */ - unsigned int data) -{ - struct mii_ioctl_data mii; - - /* - * Frame the control structures - * and send the ioctl to kernel. - */ - memset(&ifr, 0, sizeof(ifr)); - strlcpy(ifr.ifr_name, devname, sizeof(ifr.ifr_name)); - memset(&mii, 0, sizeof(mii)); - memcpy(&mii, &ifr.ifr_data, sizeof(mii)); - mii.phy_id = MII_ADDR_C45 | PHY_ID << 5 | MMD; - mii.reg_num = address; - mii.val_in = data; - memcpy(&ifr.ifr_data, &mii, sizeof(mii)); - - if (ioctl(sock, SIOCSMIIREG, &ifr) < 0) { - fprintf(stderr, "SIOCSMIIREG on %s failed: %s\n", ifr.ifr_name, - strerror(errno)); - } - - return; -} - -/*! Provides generic synchronous PHY register read functionality. It is the - * responsibility of the system designer to provide the specific MDIO address - * pointer updates, etc. in order to accomplish this read operation.*/ -unsigned int AQ_API_MDIO_Read -( - /*! Uniquely identifies the port within the system. AQ_Port must be - * defined to a whatever data type is suitable for the platform.*/ - AQ_Port PHY_ID, - /*! The address of the MMD within the target PHY. */ - unsigned int MMD, - /*! The 16-bit address of the PHY register being read. */ - unsigned int address) -{ - struct mii_ioctl_data mii; - - /* - * Frame the control structures - * and send the ioctl to kernel. - */ - memset(&ifr, 0, sizeof(ifr)); - strlcpy(ifr.ifr_name, devname, sizeof(ifr.ifr_name)); - memset(&mii, 0, sizeof(mii)); - memcpy(&mii, &ifr.ifr_data, sizeof(mii)); - mii.phy_id = MII_ADDR_C45 | PHY_ID << 5 | MMD; - mii.reg_num = address; - memcpy(&ifr.ifr_data, &mii, sizeof(mii)); - - if (ioctl(sock, SIOCGMIIREG, &ifr) < 0) { - fprintf(stderr, "SIOCGMIIREG on %s failed: %s\n", ifr.ifr_name, - strerror(errno)); - return -1; - } else { - memcpy(&mii, &ifr.ifr_data, sizeof(mii)); - } - - - return mii.val_out; -} - -/*! Returns after at least milliseconds have elapsed. This must be implemented - * * in a platform-approriate way. AQ_API functions will call this function to - * * block for the specified period of time. If necessary, PHY register reads - * * may be performed on port to busy-wait. */ -void AQ_API_Wait( - uint32_t milliseconds, /*!< The delay in milliseconds */ - AQ_API_Port* port /*!< The PHY to use if delay reads are necessary*/ ) -{ - unsigned long long mirco = milliseconds *1000; - usleep(mirco); -} diff --git a/qca/nss-eip-firmware/Makefile b/qca/nss-eip-firmware/Makefile deleted file mode 100644 index a20c9afd6..000000000 --- a/qca/nss-eip-firmware/Makefile +++ /dev/null @@ -1,34 +0,0 @@ -include $(TOPDIR)/rules.mk - -PKG_NAME:=nss-eip-firmware -PKG_VERSION=2.5.7 -PKG_RELEASE:=$(AUTORELEASE) - -PKG_MAINTAINER:=Robert Marko - -include $(INCLUDE_DIR)/package.mk - -define Package/nss-eip-firmware - SECTION:=firmware - CATEGORY:=Firmware - TITLE:=NSS EIP-197 firmware - DEPENDS:=@(TARGET_ipq807x||TARGET_ipq60xx) -endef - -define Build/Compile - -endef - -define Package/nss-eip-firmware/install - $(INSTALL_DIR) $(1)/lib/firmware/ - $(INSTALL_DATA) \ - $(PKG_BUILD_DIR)/ifpp.bin $(1)/lib/firmware/ifpp.bin - $(INSTALL_DATA) \ - $(PKG_BUILD_DIR)/ipue.bin $(1)/lib/firmware/ipue.bin - $(INSTALL_DATA) \ - $(PKG_BUILD_DIR)/ofpp.bin $(1)/lib/firmware/ofpp.bin - $(INSTALL_DATA) \ - $(PKG_BUILD_DIR)/opue.bin $(1)/lib/firmware/opue.bin -endef - -$(eval $(call BuildPackage,nss-eip-firmware)) diff --git a/qca/nss-eip-firmware/src/.gitkeep b/qca/nss-eip-firmware/src/.gitkeep deleted file mode 100644 index e69de29bb..000000000 diff --git a/qca/nss-firmware/Makefile b/qca/nss-firmware/Makefile deleted file mode 100644 index eff44a8fb..000000000 --- a/qca/nss-firmware/Makefile +++ /dev/null @@ -1,72 +0,0 @@ -# -# Copyright (C) 2021 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# - -include $(TOPDIR)/rules.mk - -PKG_NAME:=nss-firmware -PKG_SOURCE_DATE:=2022-05-16 -PKG_SOURCE_VERSION:=20c9a9b7e0ea2935b0a54f112104e433009312ca -PKG_MIRROR_HASH:=376b3605776f75bccb1da2b30dd522cc22d3f6b17dff6c954dd9b7222418d6c6 -PKG_RELEASE:=$(AUTORELEASE) - -PKG_SOURCE_PROTO:=git -PKG_SOURCE_URL:=https://github.com/quic/qca-sdk-nss-fw.git - -PKG_LICENSE_FILES:=LICENSE.md - -PKG_MAINTAINER:=Robert Marko - -include $(INCLUDE_DIR)/package.mk - -VERSION_PATH=$(PKG_BUILD_DIR)/QCA_Networking.SPF_11.5.0/CS - -define Package/nss-firmware-default - SECTION:=firmware - CATEGORY:=Firmware - URL:=$(PKG_SOURCE_URL) - DEPENDS:=@(TARGET_ipq807x||TARGET_ipq60xx) -endef - -define Package/nss-firmware-ipq6018 -$(Package/nss-firmware-default) - TITLE:=NSS firmware for IPQ6018 devices - NSS_ARCHIVE:=$(VERSION_PATH)/IPQ6018.ATH.11.4/BIN-NSS.CP.11.4.0.5-5-R.tar.bz2 -endef - -define Package/nss-firmware-ipq8074 -$(Package/nss-firmware-default) - TITLE:=NSS firmware for IPQ8074 devices - NSS_ARCHIVE:=$(VERSION_PATH)/IPQ8074.ATH.11.5.0/BIN-NSS.FW.12.0.r1-002-HK.R.tar.bz2 -endef - -define Build/Compile - -endef - -define Package/nss-firmware-ipq6018/install - mkdir -p $(PKG_BUILD_DIR)/IPQ6018 - $(TAR) -C $(PKG_BUILD_DIR)/IPQ6018 -xf $(NSS_ARCHIVE) --strip-components=1 - $(INSTALL_DIR) $(1)/lib/firmware/ - $(INSTALL_DATA) \ - $(PKG_BUILD_DIR)/IPQ6018/retail_router0.bin \ - $(1)/lib/firmware/qca-nss0-retail.bin -endef - -define Package/nss-firmware-ipq8074/install - mkdir -p $(PKG_BUILD_DIR)/IPQ8074 - $(TAR) -C $(PKG_BUILD_DIR)/IPQ8074 -xf $(NSS_ARCHIVE) --strip-components=1 - $(INSTALL_DIR) $(1)/lib/firmware/ - $(INSTALL_DATA) \ - $(PKG_BUILD_DIR)/IPQ8074/retail_router0.bin \ - $(1)/lib/firmware/qca-nss0-retail.bin - $(INSTALL_DATA) \ - $(PKG_BUILD_DIR)/IPQ8074/retail_router1.bin \ - $(1)/lib/firmware/qca-nss1-retail.bin -endef - -$(eval $(call BuildPackage,nss-firmware-ipq6018)) -$(eval $(call BuildPackage,nss-firmware-ipq8074)) diff --git a/qca/qca-nss-cfi/Makefile b/qca/qca-nss-cfi/Makefile deleted file mode 100644 index 64f7bd7ab..000000000 --- a/qca/qca-nss-cfi/Makefile +++ /dev/null @@ -1,71 +0,0 @@ -include $(TOPDIR)/rules.mk - -PKG_NAME:=qca-nss-cfi -PKG_RELEASE:=1 - -PKG_SOURCE_PROTO:=git -PKG_SOURCE_DATE:=2021-03-22 -PKG_SOURCE_URL:=https://source.codeaurora.org/quic/qsdk/oss/lklm/nss-cfi -PKG_SOURCE_VERSION:=73f2e5f5bf93cc244036ce5641faf9f859692cdf -PKG_MIRROR_HASH:=8c8edc9b8d8c68fdd14640152245013a93c123957b6b338c06f266f6c9db8cbd - -include $(INCLUDE_DIR)/kernel.mk -include $(INCLUDE_DIR)/package.mk - -# v1.0 is for Akronite -# v2.0 is for Hawkeye/Cypress/Maple -ifneq (, $(findstring $(BOARD), ipq50xx ipq60xx ipq807x)) - CFI_OCF_DIR:=ocf/v2.0 - CFI_CRYPTOAPI_DIR:=cryptoapi/v2.0 -else - CFI_CRYPTOAPI_DIR:=cryptoapi/v1.1 - CFI_OCF_DIR:=ocf/v1.0 - CFI_IPSEC_DIR:=ipsec/v1.0 -endif - -define KernelPackage/qca-nss-cfi-cryptoapi - SECTION:=kernel - CATEGORY:=Kernel modules - SUBMENU:=Network Devices - DEPENDS:=@TARGET_ipq60xx +kmod-crypto-authenc +kmod-qca-nss-crypto - TITLE:=Kernel driver for NSS cfi - FILES:=$(PKG_BUILD_DIR)/$(CFI_CRYPTOAPI_DIR)/qca-nss-cfi-cryptoapi.ko - AUTOLOAD:=$(call AutoLoad,59,qca-nss-cfi-cryptoapi) -endef - -define Build/InstallDev - $(INSTALL_DIR) $(1)/usr/include/qca-nss-cfi - $(CP) $(PKG_BUILD_DIR)/$(CFI_CRYPTOAPI_DIR)/../exports/* $(1)/usr/include/qca-nss-cfi - $(CP) $(PKG_BUILD_DIR)/include/* $(1)/usr/include/qca-nss-cfi -endef - -define KernelPackage/qca-nss-cfi/Description -This package contains a NSS cfi driver for QCA chipset -endef - -EXTRA_CFLAGS+= \ - -DCONFIG_NSS_DEBUG_LEVEL=4 \ - -I$(LINUX_DIR)/crypto/ocf \ - -I$(STAGING_DIR)/usr/include/qca-nss-crypto \ - -I$(STAGING_DIR)/usr/include/crypto \ - -I$(STAGING_DIR)/usr/include/qca-nss-drv - -ifneq (, $(findstring $(BOARD), ipq50xx ipq60xx ipq807x)) -EXTRA_CFLAGS+= -I$(STAGING_DIR)/usr/include/qca-nss-clients -endif - -define Build/Compile - $(MAKE) -C "$(LINUX_DIR)" \ - CROSS_COMPILE="$(TARGET_CROSS)" \ - EXTRA_CFLAGS="$(EXTRA_CFLAGS)" \ - CFI_CRYPTOAPI_DIR=$(CFI_CRYPTOAPI_DIR) \ - CFI_IPSEC_DIR=$(CFI_IPSEC_DIR) \ - CFI_OCF_DIR=$(CFI_OCF_DIR) \ - $(KERNEL_MAKE_FLAGS) \ - M="$(PKG_BUILD_DIR)" \ - SoC="$(BOARD)_64" \ - "cryptoapi=y" \ - modules -endef - -$(eval $(call KernelPackage,qca-nss-cfi-cryptoapi)) diff --git a/qca/qca-nss-cfi/patches/100-remove-noise-logs.patch b/qca/qca-nss-cfi/patches/100-remove-noise-logs.patch deleted file mode 100644 index 085aeaf24..000000000 --- a/qca/qca-nss-cfi/patches/100-remove-noise-logs.patch +++ /dev/null @@ -1,30 +0,0 @@ ---- a/cryptoapi/v2.0/nss_cryptoapi_ahash.c -+++ b/cryptoapi/v2.0/nss_cryptoapi_ahash.c -@@ -449,9 +449,12 @@ int nss_cryptoapi_ahash_digest(struct ahash_request *req) - int nss_cryptoapi_ahash_export(struct ahash_request *req, void *out) - { - struct nss_cryptoapi_ctx *ctx __attribute__((unused)) = crypto_tfm_ctx(req->base.tfm); -+ struct nss_cryptoapi_req_ctx *rctx = ahash_request_ctx(req); -+ struct nss_cryptoapi_req_ctx *state = out; -+ -+ *state = *rctx; - -- nss_cfi_warn("%px: ahash .export is not supported", ctx); -- return -ENOSYS; -+ return 0; - }; - - /* -@@ -464,7 +467,10 @@ int nss_cryptoapi_ahash_export(struct ahash_request *req, void *out) - int nss_cryptoapi_ahash_import(struct ahash_request *req, const void *in) - { - struct nss_cryptoapi_ctx *ctx __attribute__((unused)) = crypto_tfm_ctx(req->base.tfm); -+ struct nss_cryptoapi_req_ctx *rctx = ahash_request_ctx(req); -+ const struct nss_cryptoapi_req_ctx *state = in; -+ -+ *rctx = *state; - -- nss_cfi_warn("%px: ahash .import is not supported", ctx); -- return -ENOSYS; -+ return 0; - } diff --git a/qca/qca-nss-clients/Makefile b/qca/qca-nss-clients/Makefile deleted file mode 100644 index 274512780..000000000 --- a/qca/qca-nss-clients/Makefile +++ /dev/null @@ -1,102 +0,0 @@ -include $(TOPDIR)/rules.mk - -PKG_NAME:=qca-nss-clients -PKG_RELEASE:=$(AUTORELEASE) - -PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/nss-clients.git -PKG_SOURCE_PROTO:=git -PKG_SOURCE_DATE:=2021-07-23 -PKG_SOURCE_VERSION:=ec7a57bed8914adcbd5bf95de1f0b630296489c1 -PKG_MIRROR_HASH:=b7413c5b20a341d3d7ea49c1b86ff92b4a8795aa7c64986ca820ba18205e332d - -include $(INCLUDE_DIR)/kernel.mk -include $(INCLUDE_DIR)/package.mk - -define KernelPackage/qca-nss-drv-pppoe - SECTION:=kernel - CATEGORY:=Kernel modules - SUBMENU:=Network Devices - TITLE:=Kernel driver for NSS (connection manager) - PPPoE - DEPENDS:=@LINUX_5_10 @TARGET_ipq807x +kmod-qca-nss-drv +kmod-ppp +kmod-pppoe - FILES:=$(PKG_BUILD_DIR)/pppoe/qca-nss-pppoe.ko - AUTOLOAD:=$(call AutoLoad,51,qca-nss-pppoe) -endef - -define KernelPackage/qca-nss-drv-pppoe/Description -Kernel modules for NSS connection manager - Support for PPPoE -endef - -define KernelPackage/qca-nss-drv-bridge-mgr - SECTION:=kernel - CATEGORY:=Kernel modules - SUBMENU:=Network Devices - TITLE:=Kernel driver for NSS bridge manager - DEPENDS:=@LINUX_5_10 @TARGET_ipq807x +kmod-qca-nss-drv +kmod-qca-nss-drv-vlan-mgr - FILES:=$(PKG_BUILD_DIR)/bridge/qca-nss-bridge-mgr.ko - AUTOLOAD:=$(call AutoLoad,51,qca-nss-bridge-mgr) -endef - -define KernelPackage/qca-nss-drv-bridge-mgr/Description -Kernel modules for NSS bridge manager -endef - -define KernelPackage/qca-nss-drv-vlan-mgr - SECTION:=kernel - CATEGORY:=Kernel modules - SUBMENU:=Network Devices - TITLE:=Kernel driver for NSS vlan manager - DEPENDS:=@LINUX_5_10 @TARGET_ipq807x +kmod-qca-nss-drv - FILES:=$(PKG_BUILD_DIR)/vlan/qca-nss-vlan.ko - AUTOLOAD:=$(call AutoLoad,51,qca-nss-vlan) -endef - -define KernelPackage/qca-nss-drv-vlan-mgr/Description -Kernel modules for NSS vlan manager -endef - -EXTRA_CFLAGS+= \ - -I$(STAGING_DIR)/usr/include/qca-nss-drv \ - -I$(STAGING_DIR)/usr/include/qca-nss-crypto \ - -I$(STAGING_DIR)/usr/include/qca-nss-cfi \ - -I$(STAGING_DIR)/usr/include/qca-nss-gmac \ - -I$(STAGING_DIR)/usr/include/qca-ssdk \ - -I$(STAGING_DIR)/usr/include/qca-ssdk/fal \ - -I$(STAGING_DIR)/usr/include/nat46 - -ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-pppoe),) -NSS_CLIENTS_MAKE_OPTS+=pppoe=y -endif - -ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-bridge-mgr),) -NSS_CLIENTS_MAKE_OPTS+=bridge-mgr=y -#enable OVS bridge if ovsmgr is enabled -ifneq ($(CONFIG_PACKAGE_kmod-qca-ovsmgr),) -NSS_CLIENTS_MAKE_OPTS+= NSS_BRIDGE_MGR_OVS_ENABLE=y -EXTRA_CFLAGS+= -I$(STAGING_DIR)/usr/include/qca-ovsmgr -endif -endif - -ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-vlan-mgr),) -NSS_CLIENTS_MAKE_OPTS+=vlan-mgr=y -endif - -ifeq ($(CONFIG_TARGET_BOARD), "ipq807x") - SOC="ipq807x_64" -else ifeq ($(CONFIG_TARGET_BOARD), "ipq60xx") - SOC="ipq60xx_64" -endif - -define Build/Compile - $(MAKE) -C "$(LINUX_DIR)" $(strip $(NSS_CLIENTS_MAKE_OPTS)) \ - CROSS_COMPILE="$(TARGET_CROSS)" \ - ARCH="$(LINUX_KARCH)" \ - M="$(PKG_BUILD_DIR)" \ - EXTRA_CFLAGS="$(EXTRA_CFLAGS)" \ - SoC=$(SOC) \ - $(KERNEL_MAKE_FLAGS) \ - modules -endef - -$(eval $(call KernelPackage,qca-nss-drv-pppoe)) -$(eval $(call KernelPackage,qca-nss-drv-bridge-mgr)) -$(eval $(call KernelPackage,qca-nss-drv-vlan-mgr)) diff --git a/qca/qca-nss-clients/files/qca-nss-ipsec b/qca/qca-nss-clients/files/qca-nss-ipsec deleted file mode 100644 index 5f682c8e9..000000000 --- a/qca/qca-nss-clients/files/qca-nss-ipsec +++ /dev/null @@ -1,214 +0,0 @@ -#!/bin/sh /etc/rc.common -# -# Copyright (c) 2018-2019, 2021 The Linux Foundation. All rights reserved. -# -# Permission to use, copy, modify, and/or distribute this software for any -# purpose with or without fee is hereby granted, provided that the above -# copyright notice and this permission notice appear in all copies. -# -# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - -NSS_IPSEC_LOG_FILE=/tmp/.nss_ipsec_log -NSS_IPSEC_LOG_STR_ECM="ECM_Loaded" -NSS_IPSEC_OL_FILE=/tmp/qca_nss_ipsec_ol - -ecm_load () { - if [ ! -d /sys/module/ecm ]; then - /etc/init.d/qca-nss-ecm start - if [ -d /sys/module/ecm ]; then - echo ${NSS_IPSEC_LOG_STR_ECM} >> ${NSS_IPSEC_LOG_FILE} - fi - fi -} - -ecm_unload () { - if [ -f /tmp/.nss_ipsec_log ]; then - str=`grep ${NSS_IPSEC_LOG_STR_ECM} ${NSS_IPSEC_LOG_FILE}` - if [[ $str == ${NSS_IPSEC_LOG_STR_ECM} ]]; then - /etc/init.d/qca-nss-ecm stop - `sed 's/${NSS_IPSEC_LOG_STR_ECM}/ /g' $NSS_IPSEC_LOG_FILE > $NSS_IPSEC_LOG_FILE` - fi - fi -} - -ecm_disable() { - - if [ ! -d /sys/module/ecm ]; then - return; - fi - - echo 1 > /sys/kernel/debug/ecm/front_end_ipv4_stop - echo 1 > /sys/kernel/debug/ecm/front_end_ipv6_stop - echo 1 > /sys/kernel/debug/ecm/ecm_db/defunct_all - sleep 2 -} - -ecm_enable() { - if [ ! -d /sys/module/ecm ]; then - return; - fi - - echo 0 > /sys/kernel/debug/ecm/ecm_db/defunct_all - echo 0 > /sys/kernel/debug/ecm/front_end_ipv4_stop - echo 0 > /sys/kernel/debug/ecm/front_end_ipv6_stop -} - -kernel_version_check_5_4() { - major_ver=$(uname -r | awk -F '.' '{print $1}') - minor_ver=$(uname -r | awk -F '.' '{print $2}') - if [ $major_ver -lt 5 ] || ([ $major_ver -eq 5 ] && [ $minor_ver -lt 4 ] ) ; then - return 1 - else - return 0 - fi -} - -start_klips() { - if kernel_version_check_5_4 - then - echo "Kernel 5.4 doesn't support klips stack." - return $? - fi - - touch $NSS_IPSEC_OL_FILE - ecm_load - - local kernel_version=$(uname -r) - - insmod /lib/modules/${kernel_version}/qca-nss-ipsec-klips.ko - if [ "$?" -gt 0 ]; then - echo "Failed to load plugin. Please start ecm if not done already" - ecm_enable - rm $NSS_IPSEC_OL_FILE - return - fi - - /etc/init.d/ipsec start - sleep 2 - ipsec eroute - - ecm_enable -} - -stop_klips() { - if kernel_version_check_5_4 - then - echo "Kernel 5.4 doesn't support klips stack." - return $? - fi - - ecm_disable - - /etc/init.d/ipsec stop - rmmod qca-nss-ipsec-klips - rm $NSS_IPSEC_OL_FILE - - ecm_unload -} - -start_xfrm() { - touch $NSS_IPSEC_OL_FILE - ecm_load - - local kernel_version=$(uname -r) - - # load all NETKEY modules first. - for mod in xfrm_ipcomp ipcomp xfrm6_tunnel ipcomp6 xfrm6_mode_tunnel xfrm6_mode_beet xfrm6_mode_ro \ - xfrm6_mode_transport xfrm4_mode_transport xfrm4_mode_tunnel \ - xfrm4_tunnel xfrm4_mode_beet esp4 esp6 ah4 ah6 af_key - do - insmod $mod 2> /dev/null - done - - # Now load the xfrm plugin - insmod /lib/modules/${kernel_version}/qca-nss-ipsec-xfrm.ko - if [ "$?" -gt 0 ]; then - echo "Failed to load plugin. Please start ecm if not done already" - ecm_enable - rm $NSS_IPSEC_OL_FILE - return - fi - - /etc/init.d/ipsec start - sleep 2 - - ecm_enable -} - -stop_xfrm() { - ecm_disable - - #Shutdown Pluto first. Then only plugin can be removed. - plutopid=/var/run/pluto/pluto.pid - if [ -f $plutopid ]; then - pid=`cat $plutopid` - if [ ! -z "$pid" ]; then - ipsec whack --shutdown | grep -v "002"; - if [ -s $plutopid ]; then - echo "Attempt to shut Pluto down failed! Trying kill:" - kill $pid; - sleep 5; - fi - fi - rm -rf $plutopid - fi - ip xfrm state flush; - ip xfrm policy flush; - sleep 2 - - #Now we can remove the plugin - retries=5 - while [ -d /sys/module/qca_nss_ipsec_xfrm ] - do - rmmod qca-nss-ipsec-xfrm - if [ "$?" -eq 0 ]; then - rm $NSS_IPSEC_OL_FILE - break - fi - - if [ ${retries} -eq 0 ]; then - echo "Failed to unload qca-nss-ipsec-xfrm plugin!" - exit - fi - - echo "XFRM plugin unload failed; retrying ${retries} times" - sleep 1 - retries=`expr ${retries} - 1` - done - - /etc/init.d/ipsec stop - ecm_unload -} - -start() { - local protostack=`uci -q get ipsec.setup.protostack` - if [ "$protostack" = "klips" ]; then - start_klips - return $? - fi - - start_xfrm - return $? -} - -stop() { - local protostack=`uci -q get ipsec.setup.protostack` - if [ "$protostack" = "klips" ]; then - stop_klips - return $? - fi - - stop_xfrm - return $? -} - -restart() { - stop - start -} diff --git a/qca/qca-nss-clients/files/qca-nss-mirred.init b/qca/qca-nss-clients/files/qca-nss-mirred.init deleted file mode 100644 index 1f931f090..000000000 --- a/qca/qca-nss-clients/files/qca-nss-mirred.init +++ /dev/null @@ -1,28 +0,0 @@ -#!/bin/sh /etc/rc.common - -########################################################################### -# Copyright (c) 2019, The Linux Foundation. All rights reserved. -# Permission to use, copy, modify, and/or distribute this software for -# any purpose with or without fee is hereby granted, provided that the -# above copyright notice and this permission notice appear in all copies. -# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT -# OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -########################################################################### - -restart() { - rmmod act_nssmirred.ko - insmod act_nssmirred.ko -} - -start() { - insmod act_nssmirred.ko -} - -stop() { - rmmod act_nssmirred.ko -} diff --git a/qca/qca-nss-clients/files/qca-nss-ovpn.init b/qca/qca-nss-clients/files/qca-nss-ovpn.init deleted file mode 100644 index 622e295ee..000000000 --- a/qca/qca-nss-clients/files/qca-nss-ovpn.init +++ /dev/null @@ -1,69 +0,0 @@ -#!/bin/sh /etc/rc.common - -########################################################################### -# Copyright (c) 2019, The Linux Foundation. All rights reserved. -# Permission to use, copy, modify, and/or distribute this software for -# any purpose with or without fee is hereby granted, provided that the -# above copyright notice and this permission notice appear in all copies. -# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT -# OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -########################################################################### - -ecm_disable() { - if [ ! -d /sys/module/ecm ]; then - return - fi - - echo 1 > /sys/kernel/debug/ecm/front_end_ipv4_stop - echo 1 > /sys/kernel/debug/ecm/front_end_ipv6_stop - echo 1 > /sys/kernel/debug/ecm/ecm_db/defunct_all - sleep 2 -} - -ecm_enable() { - if [ ! -d /sys/module/ecm ]; then - return - fi - - echo 0 > /sys/kernel/debug/ecm/ecm_db/defunct_all - echo 0 > /sys/kernel/debug/ecm/front_end_ipv4_stop - echo 0 > /sys/kernel/debug/ecm/front_end_ipv6_stop -} - -restart() { - ecm_disable - - /etc/init.d/openvpn stop - rmmod qca-nss-ovpn-link - rmmod qca-nss-ovpn-mgr - - insmod qca-nss-ovpn-mgr - insmod qca-nss-ovpn-link - - if [ "$?" -gt 0 ]; then - echo "Failed to load plugin. Please start ecm if not done already" - ecm_enable - return - fi - - ecm_enable -} - -start() { - restart -} - -stop() { - ecm_disable - - /etc/init.d/openvpn stop - rmmod qca-nss-ovpn-link - rmmod qca-nss-ovpn-mgr - - ecm_enable -} diff --git a/qca/qca-nss-crypto/Makefile b/qca/qca-nss-crypto/Makefile deleted file mode 100644 index 5c1003b89..000000000 --- a/qca/qca-nss-crypto/Makefile +++ /dev/null @@ -1,72 +0,0 @@ -include $(TOPDIR)/rules.mk - -PKG_NAME:=qca-nss-crypto -PKG_RELEASE:=$(AUTORELEASE) - -PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/nss-crypto.git -PKG_SOURCE_PROTO:=git -PKG_SOURCE_DATE:=2021-03-20 -PKG_SOURCE_VERSION:=2271a3a66f7e8284d42a9e787ddec6f24a1d2e15 -PKG_MIRROR_HASH:=afd2b746779bf9abb72dfb58c755acf54d1cb51085b879013dd0edf9ba98d3c9 - -PKG_BUILD_PARALLEL:=1 - -include $(INCLUDE_DIR)/kernel.mk -include $(INCLUDE_DIR)/package.mk - -ifeq ($(CONFIG_TARGET_BOARD), "ipq807x") - SOC="ipq807x_64" -else ifeq ($(CONFIG_TARGET_BOARD), "ipq60xx") - SOC="ipq60xx_64" -endif - -# v1.0 is for Akronite -# v2.0 is for Hawkeye/Cypress/Maple -ifneq (, $(findstring $(CONFIG_TARGET_BOARD), "ipq807x" "ipq60xx")) -NSS_CRYPTO_DIR:=v2.0 -else -NSS_CRYPTO_DIR:=v1.0 -endif - -define KernelPackage/qca-nss-crypto - SECTION:=kernel - CATEGORY:=Kernel modules - SUBMENU:=Cryptographic API modules - DEPENDS:=@(TARGET_ipq807x||TARGET_ipq60xx) +kmod-qca-nss-drv +nss-eip-firmware - TITLE:=Kernel driver for NSS crypto driver - FILES:=$(PKG_BUILD_DIR)/$(NSS_CRYPTO_DIR)/src/qca-nss-crypto.ko \ - $(PKG_BUILD_DIR)/$(NSS_CRYPTO_DIR)/tool/qca-nss-crypto-tool.ko - AUTOLOAD:=$(call AutoLoad,52,qca-nss-crypto) -endef - -define KernelPackage/qca-nss-crypto/Description -This package contains a NSS crypto driver for QCA chipset -endef - -define Build/InstallDev - $(INSTALL_DIR) $(1)/usr/include/qca-nss-crypto - $(CP) $(PKG_BUILD_DIR)/$(NSS_CRYPTO_DIR)/include/* $(1)/usr/include/qca-nss-crypto -endef - -EXTRA_CFLAGS+= \ - -DCONFIG_NSS_DEBUG_LEVEL=4 \ - -I$(STAGING_DIR)/usr/include/qca-nss-crypto \ - -I$(STAGING_DIR)/usr/include/qca-nss-drv \ - -I$(PKG_BUILD_DIR)/$(NSS_CRYPTO_DIR)/include \ - -I$(PKG_BUILD_DIR)/$(NSS_CRYPTO_DIR)/src - -define Build/Compile - +$(MAKE) -C "$(LINUX_DIR)" \ - CC="$(TARGET_CC)" \ - CROSS_COMPILE="$(TARGET_CROSS)" \ - ARCH="$(LINUX_KARCH)" \ - M="$(PKG_BUILD_DIR)" \ - EXTRA_CFLAGS="$(EXTRA_CFLAGS)" \ - NSS_CRYPTO_DIR=$(NSS_CRYPTO_DIR) \ - SoC=$(SOC) \ - $(KERNEL_MAKE_FLAGS) \ - $(PKG_JOBS) \ - modules -endef - -$(eval $(call KernelPackage,qca-nss-crypto)) diff --git a/qca/qca-nss-crypto/patches/0001-nss-crypto-fix-SHA1-header-include.patch b/qca/qca-nss-crypto/patches/0001-nss-crypto-fix-SHA1-header-include.patch deleted file mode 100644 index 757b172ea..000000000 --- a/qca/qca-nss-crypto/patches/0001-nss-crypto-fix-SHA1-header-include.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 68b7776673aabc2f93bd75e73ef4b45a1ac561d9 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Sun, 13 Mar 2022 13:44:47 +0100 -Subject: [PATCH 1/3] nss-crypto: fix SHA1 header include - -SHA1 header has been merged to the generic SHA one, -and with that the cryptohash.h was dropped. - -So, fix include in kernels 5.8 and newer. - -Signed-off-by: Robert Marko ---- - v2.0/src/nss_crypto_hlos.h | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/v2.0/src/nss_crypto_hlos.h b/v2.0/src/nss_crypto_hlos.h -index 84740c2..e827f4f 100644 ---- a/v2.0/src/nss_crypto_hlos.h -+++ b/v2.0/src/nss_crypto_hlos.h -@@ -55,7 +55,9 @@ - #include - #include - #include -+#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 8, 0) - #include -+#endif - #include - #include - #include --- -2.35.1 - diff --git a/qca/qca-nss-crypto/patches/0002-nss-crypto-replace-ioremap_nocache-with-ioremap.patch b/qca/qca-nss-crypto/patches/0002-nss-crypto-replace-ioremap_nocache-with-ioremap.patch deleted file mode 100644 index 8c829c11e..000000000 --- a/qca/qca-nss-crypto/patches/0002-nss-crypto-replace-ioremap_nocache-with-ioremap.patch +++ /dev/null @@ -1,69 +0,0 @@ -From 80393ab565e26d572de56b7502b069b0a944bd40 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Tue, 8 Jun 2021 22:14:34 +0200 -Subject: [PATCH 2/3] nss-crypto: replace ioremap_nocache() with ioremap - -ioremap_nocache() was dropped in kernel 5.5 as regular -ioremap() was exactly the same. - -So, simply replace all of the ioremap_nocache() calls -with ioremap(). - -Signed-off-by: Robert Marko ---- - v2.0/src/hal/ipq50xx/nss_crypto_ce5.c | 4 ++-- - v2.0/src/hal/ipq60xx/nss_crypto_eip197.c | 2 +- - v2.0/src/hal/ipq807x/nss_crypto_eip197.c | 2 +- - 3 files changed, 4 insertions(+), 4 deletions(-) - -diff --git a/v2.0/src/hal/ipq50xx/nss_crypto_ce5.c b/v2.0/src/hal/ipq50xx/nss_crypto_ce5.c -index c89cd38..a7a46e0 100644 ---- a/v2.0/src/hal/ipq50xx/nss_crypto_ce5.c -+++ b/v2.0/src/hal/ipq50xx/nss_crypto_ce5.c -@@ -288,7 +288,7 @@ int nss_crypto_ce5_engine_init(struct platform_device *pdev, struct resource *cr - * remap the I/O addresses for crypto - */ - eng->crypto_paddr = crypto_res->start; -- eng->crypto_vaddr = ioremap_nocache(crypto_res->start, resource_size(crypto_res)); -+ eng->crypto_vaddr = ioremap(crypto_res->start, resource_size(crypto_res)); - if (!eng->crypto_vaddr) { - nss_crypto_warn("%px: unable to remap crypto_addr(0x%px)\n", node, (void *)eng->crypto_paddr); - nss_crypto_engine_free(eng); -@@ -299,7 +299,7 @@ int nss_crypto_ce5_engine_init(struct platform_device *pdev, struct resource *cr - * remap the I/O addresses for bam - */ - eng->dma_paddr = bam_res->start; -- eng->dma_vaddr = ioremap_nocache(bam_res->start, resource_size(bam_res)); -+ eng->dma_vaddr = ioremap(bam_res->start, resource_size(bam_res)); - if (!eng->dma_vaddr) { - iounmap(eng->crypto_vaddr); - nss_crypto_warn("%px: unable to remap dma_addr(0x%px)\n", node, (void *)eng->dma_paddr); -diff --git a/v2.0/src/hal/ipq60xx/nss_crypto_eip197.c b/v2.0/src/hal/ipq60xx/nss_crypto_eip197.c -index 8dfc35d..79649f9 100644 ---- a/v2.0/src/hal/ipq60xx/nss_crypto_eip197.c -+++ b/v2.0/src/hal/ipq60xx/nss_crypto_eip197.c -@@ -490,7 +490,7 @@ int nss_crypto_eip197_engine_init(struct platform_device *pdev, struct device_no - * remap the I/O addresses - */ - paddr = res->start + offset; -- vaddr = ioremap_nocache(paddr, resource_size(res)); -+ vaddr = ioremap(paddr, resource_size(res)); - if (!vaddr) { - nss_crypto_warn("%px: unable to remap crypto_addr(0x%px)\n", node, (void *)paddr); - return -EIO; -diff --git a/v2.0/src/hal/ipq807x/nss_crypto_eip197.c b/v2.0/src/hal/ipq807x/nss_crypto_eip197.c -index 632adca..5e2c146 100644 ---- a/v2.0/src/hal/ipq807x/nss_crypto_eip197.c -+++ b/v2.0/src/hal/ipq807x/nss_crypto_eip197.c -@@ -490,7 +490,7 @@ int nss_crypto_eip197_engine_init(struct platform_device *pdev, struct device_no - * remap the I/O addresses - */ - paddr = res->start + offset; -- vaddr = ioremap_nocache(paddr, resource_size(res)); -+ vaddr = ioremap(paddr, resource_size(res)); - if (!vaddr) { - nss_crypto_warn("%px: unable to remap crypto_addr(0x%px)\n", node, (void *)paddr); - return -EIO; --- -2.35.1 - diff --git a/qca/qca-nss-crypto/patches/0003-nss-crypto-fix-SHA-header-include-in-5.15.patch b/qca/qca-nss-crypto/patches/0003-nss-crypto-fix-SHA-header-include-in-5.15.patch deleted file mode 100644 index 311070d91..000000000 --- a/qca/qca-nss-crypto/patches/0003-nss-crypto-fix-SHA-header-include-in-5.15.patch +++ /dev/null @@ -1,51 +0,0 @@ -From 4c0cc66cde0c4a30aa049b586af311501304e9ce Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Sun, 13 Mar 2022 13:47:24 +0100 -Subject: [PATCH 3/3] nss-crypto: fix SHA header include in 5.15 - -SHA header was split into SHA-1 and SHA-2 headers in kernel 5.11, so -fix the include for newer kernels. - -Signed-off-by: Robert Marko ---- - v2.0/src/nss_crypto_ctrl.c | 6 ++++++ - v2.0/src/nss_crypto_hlos.h | 4 ++++ - 2 files changed, 10 insertions(+) - -diff --git a/v2.0/src/nss_crypto_ctrl.c b/v2.0/src/nss_crypto_ctrl.c -index 72d1602..a462705 100644 ---- a/v2.0/src/nss_crypto_ctrl.c -+++ b/v2.0/src/nss_crypto_ctrl.c -@@ -38,7 +38,13 @@ - #include - #include - #include -+#include -+#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 11, 0) - #include -+#else -+#include -+#include -+#endif - #include - #include - #include -diff --git a/v2.0/src/nss_crypto_hlos.h b/v2.0/src/nss_crypto_hlos.h -index e827f4f..5565472 100644 ---- a/v2.0/src/nss_crypto_hlos.h -+++ b/v2.0/src/nss_crypto_hlos.h -@@ -58,7 +58,11 @@ - #if LINUX_VERSION_CODE < KERNEL_VERSION(5, 8, 0) - #include - #endif -+#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 11, 0) - #include -+#else -+#include -+#endif - #include - #include - #include --- -2.35.1 - diff --git a/qca/qca-nss-dp/Makefile b/qca/qca-nss-dp/Makefile deleted file mode 100644 index 17627674a..000000000 --- a/qca/qca-nss-dp/Makefile +++ /dev/null @@ -1,56 +0,0 @@ -include $(TOPDIR)/rules.mk - -PKG_NAME:=qca-nss-dp -PKG_RELEASE:=$(AUTORELEASE) - -PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/nss-dp.git -PKG_SOURCE_PROTO:=git -PKG_SOURCE_DATE:=2022-04-30 -PKG_SOURCE_VERSION:=72e9ec4187414461cbcf6ccff100e8b5ebe5f40b -PKG_MIRROR_HASH:=805f16e59c75511132922f97740ebf6bf953845b0bbfd2089c4615456893bb37 - -PKG_BUILD_PARALLEL:=1 - -include $(INCLUDE_DIR)/kernel.mk -include $(INCLUDE_DIR)/package.mk - -define KernelPackage/qca-nss-dp - SECTION:=kernel - CATEGORY:=Kernel modules - SUBMENU:=Network Devices - DEPENDS:=@(TARGET_ipq807x||TARGET_ipq60xx) +kmod-qca-ssdk-nohnat - TITLE:=Kernel driver for NSS data plane - FILES:=$(PKG_BUILD_DIR)/qca-nss-dp.ko - AUTOLOAD:=$(call AutoLoad,31,qca-nss-dp,1) -endef - -define KernelPackage/qca-nss-dp/Description -This package contains a NSS data plane driver for QCA chipset -endef - -define Build/InstallDev - mkdir -p $(1)/usr/include/qca-nss-dp - $(CP) $(PKG_BUILD_DIR)/exports/* $(1)/usr/include/qca-nss-dp/ -endef - -EXTRA_CFLAGS+= \ - -I$(STAGING_DIR)/usr/include/qca-ssdk - -NSS_DP_HAL_DIR:=$(PKG_BUILD_DIR)/hal -define Build/Configure - $(LN) $(NSS_DP_HAL_DIR)/soc_ops/$(CONFIG_TARGET_BOARD)/nss_$(CONFIG_TARGET_BOARD).h \ - $(PKG_BUILD_DIR)/exports/nss_dp_arch.h -endef - -define Build/Compile - +$(MAKE) -C "$(LINUX_DIR)" \ - CROSS_COMPILE="$(TARGET_CROSS)" \ - ARCH="$(LINUX_KARCH)" \ - M="$(PKG_BUILD_DIR)" \ - EXTRA_CFLAGS="$(EXTRA_CFLAGS)" SoC="$(CONFIG_TARGET_BOARD)" \ - $(KERNEL_MAKE_FLAGS) \ - $(PKG_JOBS) \ - modules -endef - -$(eval $(call KernelPackage,qca-nss-dp)) diff --git a/qca/qca-nss-dp/patches/0001-edma_tx_rx-support-newer-kernels-time-stamping-API.patch b/qca/qca-nss-dp/patches/0001-edma_tx_rx-support-newer-kernels-time-stamping-API.patch deleted file mode 100644 index 1fed4ba8a..000000000 --- a/qca/qca-nss-dp/patches/0001-edma_tx_rx-support-newer-kernels-time-stamping-API.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 40979666b4371012405715ffa61ab5760fcdc6b3 Mon Sep 17 00:00:00 2001 -Message-Id: <40979666b4371012405715ffa61ab5760fcdc6b3.1620066716.git.baruch@tkos.co.il> -From: Baruch Siach -Date: Mon, 3 May 2021 20:07:36 +0300 -Subject: [PATCH 1/3] edma_tx_rx: support newer kernels time stamping API - ---- - hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c | 11 +++++++++++ - 1 file changed, 11 insertions(+) - ---- a/hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c -+++ b/hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c -@@ -227,10 +227,16 @@ void nss_phy_tstamp_rx_buf(__attribute__ - * set to the correct PTP class value by calling ptp_classify_raw - * in drv->rxtstamp function. - */ -+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 6, 0)) - if (ndev && ndev->phydev && ndev->phydev->drv && - ndev->phydev->drv->rxtstamp) - if(ndev->phydev->drv->rxtstamp(ndev->phydev, skb, 0)) - return; -+#else -+ if (ndev && phy_has_rxtstamp(ndev->phydev)) -+ if (phy_rxtstamp(ndev->phydev, skb, 0)) -+ return; -+#endif - - netif_receive_skb(skb); - } -@@ -248,9 +254,14 @@ void nss_phy_tstamp_tx_buf(struct net_de - * set to the correct PTP class value by calling ptp_classify_raw - * in the drv->txtstamp function. - */ -+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 6, 0)) - if (ndev && ndev->phydev && ndev->phydev->drv && - ndev->phydev->drv->txtstamp) - ndev->phydev->drv->txtstamp(ndev->phydev, skb, 0); -+#else -+ if (ndev && phy_has_txtstamp(ndev->phydev)) -+ phy_rxtstamp(ndev->phydev, skb, 0); -+#endif - } - EXPORT_SYMBOL(nss_phy_tstamp_tx_buf); - diff --git a/qca/qca-nss-dp/patches/0002-nss_dp_main-make-phy-mode-code-compatible-with-newer.patch b/qca/qca-nss-dp/patches/0002-nss_dp_main-make-phy-mode-code-compatible-with-newer.patch deleted file mode 100644 index 04adad86f..000000000 --- a/qca/qca-nss-dp/patches/0002-nss_dp_main-make-phy-mode-code-compatible-with-newer.patch +++ /dev/null @@ -1,48 +0,0 @@ -From cef7873a2d77df13ee702d902ed4e06b2248904b Mon Sep 17 00:00:00 2001 -Message-Id: -In-Reply-To: <40979666b4371012405715ffa61ab5760fcdc6b3.1620066716.git.baruch@tkos.co.il> -References: <40979666b4371012405715ffa61ab5760fcdc6b3.1620066716.git.baruch@tkos.co.il> -From: Baruch Siach -Date: Mon, 3 May 2021 20:17:22 +0300 -Subject: [PATCH 2/3] nss_dp_main: make phy mode code compatible with newer - kernels - ---- - include/nss_dp_dev.h | 4 ++-- - nss_dp_main.c | 4 ++++ - 2 files changed, 6 insertions(+), 2 deletions(-) - ---- a/include/nss_dp_dev.h -+++ b/include/nss_dp_dev.h -@@ -22,7 +22,7 @@ - #include - #include - #include --#include -+#include - #include - - #include "nss_dp_api_if.h" -@@ -99,7 +99,7 @@ struct nss_dp_dev { - /* Phy related stuff */ - struct phy_device *phydev; /* Phy device */ - struct mii_bus *miibus; /* MII bus */ -- uint32_t phy_mii_type; /* RGMII/SGMII/QSGMII */ -+ phy_interface_t phy_mii_type; /* RGMII/SGMII/QSGMII */ - uint32_t phy_mdio_addr; /* Mdio address */ - bool link_poll; /* Link polling enable? */ - uint32_t forced_speed; /* Forced speed? */ ---- a/nss_dp_main.c -+++ b/nss_dp_main.c -@@ -584,7 +584,11 @@ static int32_t nss_dp_of_get_pdata(struc - hal_pdata->netdev = netdev; - hal_pdata->macid = dp_priv->macid; - -+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 5, 0)) - dp_priv->phy_mii_type = of_get_phy_mode(np); -+#else -+ of_get_phy_mode(np, &dp_priv->phy_mii_type); -+#endif - dp_priv->link_poll = of_property_read_bool(np, "qcom,link-poll"); - if (of_property_read_u32(np, "qcom,phy-mdio-addr", - &dp_priv->phy_mdio_addr) && dp_priv->link_poll) { diff --git a/qca/qca-nss-dp/patches/0003-Drop-_nocache-variants-of-ioremap.patch b/qca/qca-nss-dp/patches/0003-Drop-_nocache-variants-of-ioremap.patch deleted file mode 100644 index 18bd85c8c..000000000 --- a/qca/qca-nss-dp/patches/0003-Drop-_nocache-variants-of-ioremap.patch +++ /dev/null @@ -1,48 +0,0 @@ -From c8c52512ff48bee578901c381a42f027e79eadf9 Mon Sep 17 00:00:00 2001 -Message-Id: -In-Reply-To: <40979666b4371012405715ffa61ab5760fcdc6b3.1620066716.git.baruch@tkos.co.il> -References: <40979666b4371012405715ffa61ab5760fcdc6b3.1620066716.git.baruch@tkos.co.il> -From: Baruch Siach -Date: Mon, 3 May 2021 20:20:29 +0300 -Subject: [PATCH 3/3] Drop _nocache variants of ioremap() - -Recent kernels removed them. ---- - hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c | 2 +- - hal/gmac_ops/qcom/qcom_if.c | 2 +- - hal/gmac_ops/syn/xgmac/syn_if.c | 2 +- - 3 files changed, 3 insertions(+), 3 deletions(-) - ---- a/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c -+++ b/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c -@@ -279,7 +279,7 @@ int edma_init(void) - /* - * Remap register resource - */ -- edma_hw.reg_base = ioremap_nocache((edma_hw.reg_resource)->start, -+ edma_hw.reg_base = ioremap((edma_hw.reg_resource)->start, - resource_size(edma_hw.reg_resource)); - if (!edma_hw.reg_base) { - pr_warn("Unable to remap EDMA register memory.\n"); ---- a/hal/gmac_ops/qcom/qcom_if.c -+++ b/hal/gmac_ops/qcom/qcom_if.c -@@ -418,7 +418,7 @@ static void *qcom_init(struct nss_gmac_h - qhd->nghd.mac_id = gmacpdata->macid; - - /* Populate the mac base addresses */ -- qhd->nghd.mac_base = devm_ioremap_nocache(&dp_priv->pdev->dev, -+ qhd->nghd.mac_base = devm_ioremap(&dp_priv->pdev->dev, - res->start, resource_size(res)); - if (!qhd->nghd.mac_base) { - netdev_dbg(ndev, "ioremap fail.\n"); ---- a/hal/gmac_ops/syn/xgmac/syn_if.c -+++ b/hal/gmac_ops/syn/xgmac/syn_if.c -@@ -432,7 +432,7 @@ static void *syn_init(struct nss_gmac_ha - - /* Populate the mac base addresses */ - shd->nghd.mac_base = -- devm_ioremap_nocache(&dp_priv->pdev->dev, res->start, -+ devm_ioremap(&dp_priv->pdev->dev, res->start, - resource_size(res)); - if (!shd->nghd.mac_base) { - netdev_dbg(ndev, "ioremap fail.\n"); diff --git a/qca/qca-nss-dp/patches/0004-EDMA-Fix-NAPI-packet-counting.patch b/qca/qca-nss-dp/patches/0004-EDMA-Fix-NAPI-packet-counting.patch deleted file mode 100644 index f7653729a..000000000 --- a/qca/qca-nss-dp/patches/0004-EDMA-Fix-NAPI-packet-counting.patch +++ /dev/null @@ -1,31 +0,0 @@ -From d74920e2a7c413ef40eed72f9cf287cf6fbd5fb8 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Thu, 20 May 2021 14:56:46 +0200 -Subject: [PATCH 1/2] EDMA: Fix NAPI packet counting - -There is a bug in the NAPI packet counting that will -cause NAPI over budget warnings. - -Signed-off-by: Baruch Siach -Signed-off-by: Robert Marko ---- - hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c -+++ b/hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c -@@ -459,12 +459,12 @@ int edma_napi(struct napi_struct *napi, - - for (i = 0; i < ehw->txcmpl_rings; i++) { - txcmpl_ring = &ehw->txcmpl_ring[i]; -- work_done += edma_clean_tx(ehw, txcmpl_ring); -+ edma_clean_tx(ehw, txcmpl_ring); - } - - for (i = 0; i < ehw->rxfill_rings; i++) { - rxfill_ring = &ehw->rxfill_ring[i]; -- work_done += edma_alloc_rx_buffer(ehw, rxfill_ring); -+ edma_alloc_rx_buffer(ehw, rxfill_ring); - } - - /* diff --git a/qca/qca-nss-dp/patches/0005-EDMA-Use-NAPI_POLL_WEIGHT-as-NAPI-weight.patch b/qca/qca-nss-dp/patches/0005-EDMA-Use-NAPI_POLL_WEIGHT-as-NAPI-weight.patch deleted file mode 100644 index 9c22fa790..000000000 --- a/qca/qca-nss-dp/patches/0005-EDMA-Use-NAPI_POLL_WEIGHT-as-NAPI-weight.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 44a30d94abcbb10aacc21db29be212518a6b1bf7 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Thu, 20 May 2021 14:57:46 +0200 -Subject: [PATCH] EDMA: Use NAPI_POLL_WEIGHT as NAPI weight - -Currently a weight of 100 is used by the EDMA, according -to upstream max of 64 should be used and that is used for -almost any driver. - -They also introduced NAPI_POLL_WEIGHT define which equals -to 64. - -So use NAPI_POLL_WEIGHT as the weight. - -Signed-off-by: Robert Marko ---- - hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c | 2 +- - hal/dp_ops/edma_dp/edma_v1/edma_data_plane.h | 1 - - 2 files changed, 1 insertion(+), 2 deletions(-) - ---- a/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c -+++ b/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c -@@ -837,7 +837,7 @@ static int edma_register_netdevice(struc - */ - if (!edma_hw.napi_added) { - netif_napi_add(netdev, &edma_hw.napi, edma_napi, -- EDMA_NAPI_WORK); -+ NAPI_POLL_WEIGHT); - /* - * Register the interrupt handlers and enable interrupts - */ ---- a/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.h -+++ b/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.h -@@ -26,7 +26,6 @@ - #define EDMA_RX_PREHDR_SIZE (sizeof(struct edma_rx_preheader)) - #define EDMA_TX_PREHDR_SIZE (sizeof(struct edma_tx_preheader)) - #define EDMA_RING_SIZE 128 --#define EDMA_NAPI_WORK 100 - #define EDMA_START_GMACS NSS_DP_HAL_START_IFNUM - #define EDMA_MAX_GMACS NSS_DP_HAL_MAX_PORTS - #define EDMA_TX_PKT_MIN_SIZE 33 /* IPQ807x EDMA needs a minimum packet size of 33 bytes */ diff --git a/qca/qca-nss-dp/patches/0006-NSS-DP-fix-of_get_mac_address.patch b/qca/qca-nss-dp/patches/0006-NSS-DP-fix-of_get_mac_address.patch deleted file mode 100644 index 1d7b49129..000000000 --- a/qca/qca-nss-dp/patches/0006-NSS-DP-fix-of_get_mac_address.patch +++ /dev/null @@ -1,46 +0,0 @@ -From cadeb62a42296563141d6954eec58e34ef86778d Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Fri, 13 Aug 2021 20:12:08 +0200 -Subject: [PATCH] NSS-DP: fix of_get_mac_address() - -Recently OpenWrt backported the updated of_get_mac_address() -function which returns and error code instead. - -So, patch the SSDK to use it and fix the compilation error. - -Signed-off-by: Robert Marko ---- - nss_dp_main.c | 13 ++++--------- - 1 file changed, 4 insertions(+), 9 deletions(-) - ---- a/nss_dp_main.c -+++ b/nss_dp_main.c -@@ -555,9 +555,10 @@ static int32_t nss_dp_of_get_pdata(struc - struct net_device *netdev, - struct nss_gmac_hal_platform_data *hal_pdata) - { -- uint8_t *maddr; -+ u8 maddr[ETH_ALEN]; - struct nss_dp_dev *dp_priv; - struct resource memres_devtree = {0}; -+ int ret; - - dp_priv = netdev_priv(netdev); - -@@ -600,14 +601,8 @@ static int32_t nss_dp_of_get_pdata(struc - of_property_read_u32(np, "qcom,forced-speed", &dp_priv->forced_speed); - of_property_read_u32(np, "qcom,forced-duplex", &dp_priv->forced_duplex); - -- maddr = (uint8_t *)of_get_mac_address(np); --#if (LINUX_VERSION_CODE > KERNEL_VERSION(5, 4, 0)) -- if (IS_ERR((void *)maddr)) { -- maddr = NULL; -- } --#endif -- -- if (maddr && is_valid_ether_addr(maddr)) { -+ ret = of_get_mac_address(np, maddr); -+ if (!ret && is_valid_ether_addr(maddr)) { - ether_addr_copy(netdev->dev_addr, maddr); - } else { - random_ether_addr(netdev->dev_addr); diff --git a/qca/qca-nss-dp/patches/0007-NSS-DP-implement-ethernet-IOCTL-s.patch b/qca/qca-nss-dp/patches/0007-NSS-DP-implement-ethernet-IOCTL-s.patch deleted file mode 100644 index 824f18634..000000000 --- a/qca/qca-nss-dp/patches/0007-NSS-DP-implement-ethernet-IOCTL-s.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 5da62ba19f554bf437752a44360fb5ae9f1a7f5e Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Tue, 8 Mar 2022 10:48:32 +0100 -Subject: [PATCH] NSS-DP: implement ethernet IOCTL-s - -Since kernel 5.15 ethernet/PHY related IOCTL-s have been split from the -generic IOCTL netdev op. -So, implement the new op instead of the generic one which is considered -for private IOCTL-s only now for 5.15+. - -Signed-off-by: Robert Marko ---- - nss_dp_main.c | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/nss_dp_main.c -+++ b/nss_dp_main.c -@@ -532,7 +532,11 @@ static const struct net_device_ops nss_d - .ndo_set_mac_address = nss_dp_set_mac_address, - .ndo_validate_addr = eth_validate_addr, - .ndo_change_mtu = nss_dp_change_mtu, -+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 15, 0)) - .ndo_do_ioctl = nss_dp_do_ioctl, -+#else -+ .ndo_eth_ioctl = nss_dp_do_ioctl, -+#endif - - #if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 5, 0)) - .ndo_bridge_setlink = switchdev_port_bridge_setlink, diff --git a/qca/qca-nss-dp/patches/0008-switchdev-remove-the-transaction-structure.patch b/qca/qca-nss-dp/patches/0008-switchdev-remove-the-transaction-structure.patch deleted file mode 100644 index 220be961a..000000000 --- a/qca/qca-nss-dp/patches/0008-switchdev-remove-the-transaction-structure.patch +++ /dev/null @@ -1,48 +0,0 @@ -From c9afdcdd2642485a6476906be9da2e811090fc7a Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Fri, 18 Mar 2022 18:06:03 +0100 -Subject: [PATCH] switchdev: remove the transaction structure - -Since 5.12 there is no transaction structure anymore, so drop it for -5.12 and newer. - -Signed-off-by: Robert Marko ---- - nss_dp_switchdev.c | 10 ++++++++++ - 1 file changed, 10 insertions(+) - ---- a/nss_dp_switchdev.c -+++ b/nss_dp_switchdev.c -@@ -279,13 +279,19 @@ void nss_dp_switchdev_setup(struct net_d - * Sets attributes - */ - static int nss_dp_port_attr_set(struct net_device *dev, -+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 12, 0)) - const struct switchdev_attr *attr, - struct switchdev_trans *trans) -+#else -+ const struct switchdev_attr *attr) -+#endif - { - struct nss_dp_dev *dp_priv = (struct nss_dp_dev *)netdev_priv(dev); - -+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 12, 0)) - if (switchdev_trans_ph_prepare(trans)) - return 0; -+#endif - - switch (attr->id) { - case SWITCHDEV_ATTR_ID_PORT_BRIDGE_FLAGS: -@@ -309,8 +315,12 @@ static int nss_dp_switchdev_port_attr_se - { - int err; - -+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 12, 0)) - err = nss_dp_port_attr_set(netdev, port_attr_info->attr, - port_attr_info->trans); -+#else -+ err = nss_dp_port_attr_set(netdev, port_attr_info->attr); -+#endif - - port_attr_info->handled = true; - return notifier_from_errno(err); diff --git a/qca/qca-nss-dp/patches/0009-switchdev-use-new-switchdev-flags.patch b/qca/qca-nss-dp/patches/0009-switchdev-use-new-switchdev-flags.patch deleted file mode 100644 index ecc84c174..000000000 --- a/qca/qca-nss-dp/patches/0009-switchdev-use-new-switchdev-flags.patch +++ /dev/null @@ -1,51 +0,0 @@ -From f95868d54301c0f54e968ec9d978c9caa02ee425 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Fri, 18 Mar 2022 18:24:18 +0100 -Subject: [PATCH] switchdev: use new switchdev flags - -Since kernel 5.12 switched utilizes a new way of setting the flags by -using a dedicated structure with flags and mask. - -So fix using kernels 5.12 and later. - -Signed-off-by: Robert Marko ---- - include/nss_dp_dev.h | 7 +++++++ - nss_dp_switchdev.c | 2 +- - 2 files changed, 8 insertions(+), 1 deletion(-) - ---- a/include/nss_dp_dev.h -+++ b/include/nss_dp_dev.h -@@ -24,6 +24,9 @@ - #include - #include - #include -+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 12, 0)) -+#include -+#endif - - #include "nss_dp_api_if.h" - #include "nss_dp_hal_if.h" -@@ -126,7 +129,11 @@ struct nss_dp_dev { - /* switchdev related attributes */ - #ifdef CONFIG_NET_SWITCHDEV - u8 stp_state; /* STP state of this physical port */ -+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 12, 0)) - unsigned long brport_flags; /* bridge port flags */ -+#else -+ struct switchdev_brport_flags brport_flags; /* bridge port flags */ -+#endif - #endif - uint32_t rx_page_mode; /* page mode for Rx processing */ - uint32_t rx_jumbo_mru; /* Jumbo mru value for Rx processing */ ---- a/nss_dp_switchdev.c -+++ b/nss_dp_switchdev.c -@@ -296,7 +296,7 @@ static int nss_dp_port_attr_set(struct n - switch (attr->id) { - case SWITCHDEV_ATTR_ID_PORT_BRIDGE_FLAGS: - dp_priv->brport_flags = attr->u.brport_flags; -- netdev_dbg(dev, "set brport_flags %lu\n", attr->u.brport_flags); -+ netdev_dbg(dev, "set brport_flags %lu\n", attr->u.brport_flags.val); - return 0; - case SWITCHDEV_ATTR_ID_PORT_STP_STATE: - return nss_dp_stp_state_set(dp_priv, attr->u.stp_state); diff --git a/qca/qca-nss-dp/patches/0010-switchdev-fix-FDB-roaming.patch b/qca/qca-nss-dp/patches/0010-switchdev-fix-FDB-roaming.patch deleted file mode 100644 index 19395ac42..000000000 --- a/qca/qca-nss-dp/patches/0010-switchdev-fix-FDB-roaming.patch +++ /dev/null @@ -1,110 +0,0 @@ -From d16102cad769f430144ca8094d928762b445e9b0 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Fri, 18 Mar 2022 22:02:01 +0100 -Subject: [PATCH] switchdev: fix FDB roaming - -Try and solve the roaming issue by trying to replicate what NSS bridge -module is doing, but by utilizing switchdev FDB notifiers instead of -adding new notifiers to the bridge code. - -We register a new non-blocking switchdev notifier and simply wait for -notification, and then process the SWITCHDEV_FDB_DEL_TO_DEVICE -notifications. - -Those tell us that a certain FDB entry should be removed, then a VSI ID -is fetched for the physical PPE port and using that VSI ID and the -notification provided MAC adress existing FDB entry gets removed. - -Signed-off-by: Robert Marko ---- - nss_dp_switchdev.c | 61 ++++++++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 61 insertions(+) - ---- a/nss_dp_switchdev.c -+++ b/nss_dp_switchdev.c -@@ -24,6 +24,8 @@ - #include "nss_dp_dev.h" - #include "fal/fal_stp.h" - #include "fal/fal_ctrlpkt.h" -+#include "fal/fal_fdb.h" -+#include "ref/ref_vsi.h" - - #define NSS_DP_SWITCH_ID 0 - #define NSS_DP_SW_ETHTYPE_PID 0 /* PPE ethtype profile ID for slow protocols */ -@@ -348,10 +350,64 @@ static int nss_dp_switchdev_event(struct - return NOTIFY_DONE; - } - -+static int nss_dp_switchdev_fdb_del_event(struct net_device *netdev, -+ struct switchdev_notifier_fdb_info *fdb_info) -+{ -+ struct nss_dp_dev *dp_priv = (struct nss_dp_dev *)netdev_priv(netdev); -+ fal_fdb_entry_t entry; -+ a_uint32_t vsi_id; -+ sw_error_t rv; -+ -+ netdev_dbg(netdev, "FDB DEL %pM port %d\n", fdb_info->addr, dp_priv->macid); -+ -+ rv = ppe_port_vsi_get(NSS_DP_SWITCH_ID, dp_priv->macid, &vsi_id); -+ if (rv) { -+ netdev_err(netdev, "cannot get VSI ID for port %d\n", dp_priv->macid); -+ return notifier_from_errno(rv); -+ } -+ -+ memset(&entry, 0, sizeof(entry)); -+ memcpy(&entry.addr, fdb_info->addr, ETH_ALEN); -+ entry.fid = vsi_id; -+ -+ rv = fal_fdb_entry_del_bymac(NSS_DP_SWITCH_ID, &entry); -+ if (rv) { -+ netdev_err(netdev, "FDB entry delete failed with MAC %pM and fid %d\n", -+ &entry.addr, entry.fid); -+ return notifier_from_errno(rv); -+ } -+ -+ return notifier_from_errno(rv); -+} -+ -+static int nss_dp_fdb_switchdev_event(struct notifier_block *nb, -+ unsigned long event, void *ptr) -+{ -+ struct net_device *dev = switchdev_notifier_info_to_dev(ptr); -+ -+ /* -+ * Handle switchdev event only for physical devices -+ */ -+ if (!nss_dp_is_phy_dev(dev)) { -+ return NOTIFY_DONE; -+ } -+ -+ switch (event) { -+ case SWITCHDEV_FDB_DEL_TO_DEVICE: -+ return nss_dp_switchdev_fdb_del_event(dev, ptr); -+ } -+ -+ return NOTIFY_DONE; -+} -+ - static struct notifier_block nss_dp_switchdev_notifier = { - .notifier_call = nss_dp_switchdev_event, - }; - -+static struct notifier_block nss_dp_switchdev_fdb_notifier = { -+ .notifier_call = nss_dp_fdb_switchdev_event, -+}; -+ - static bool switch_init_done; - - /* -@@ -366,6 +422,11 @@ void nss_dp_switchdev_setup(struct net_d - return; - } - -+ err = register_switchdev_notifier(&nss_dp_switchdev_fdb_notifier); -+ if (err) { -+ netdev_dbg(dev, "%px:Failed to register switchdev FDB notifier\n", dev); -+ } -+ - err = register_switchdev_blocking_notifier(&nss_dp_switchdev_notifier); - if (err) { - netdev_dbg(dev, "%px:Failed to register switchdev notifier\n", dev); diff --git a/qca/qca-nss-dp/patches/0011-treewide-fix-confusing-printing-of-registered-netdev.patch b/qca/qca-nss-dp/patches/0011-treewide-fix-confusing-printing-of-registered-netdev.patch deleted file mode 100644 index 63fea1982..000000000 --- a/qca/qca-nss-dp/patches/0011-treewide-fix-confusing-printing-of-registered-netdev.patch +++ /dev/null @@ -1,48 +0,0 @@ -From 7e4ae2d6285095794d73d2f2ce61404f61d4e633 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Tue, 17 May 2022 15:55:36 +0200 -Subject: [PATCH 11/11] treewide: fix confusing printing of registered netdev - -Net core implementation changed and now printing the netdev name cause -confusing printing if done before register_netdev. Move the old printing -to dbg and add an additional info log right after register_netdev to -give the user some info on correct nss-dp probe. - -Signed-off-by: Ansuel Smith ---- - hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c | 4 ++-- - nss_dp_main.c | 3 +++ - 2 files changed, 5 insertions(+), 2 deletions(-) - -diff --git a/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c b/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c -index 0af39c2..1d748db 100644 ---- a/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c -+++ b/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c -@@ -822,8 +822,8 @@ static int edma_register_netdevice(struct net_device *netdev, uint32_t macid) - return -EINVAL; - } - -- netdev_info(netdev, "nss_dp_edma: Registering netdev %s(qcom-id:%d) with EDMA\n", -- netdev->name, macid); -+ netdev_dbg(netdev, "nss_dp_edma: Registering netdev %s(qcom-id:%d) with EDMA\n", -+ netdev->name, macid); - - /* - * We expect 'macid' to correspond to ports numbers on -diff --git a/nss_dp_main.c b/nss_dp_main.c -index c0ae9d6..441c300 100644 ---- a/nss_dp_main.c -+++ b/nss_dp_main.c -@@ -875,6 +875,9 @@ static int32_t nss_dp_probe(struct platform_device *pdev) - goto phy_setup_fail; - } - -+ netdev_info(netdev, "Registered netdev %s(qcom-id:%d)\n", -+ netdev->name, port_id); -+ - dp_global_ctx.nss_dp[dp_priv->macid - 1] = dp_priv; - dp_global_ctx.slowproto_acl_bm = 0; - --- -2.34.1 - diff --git a/qca/qca-nss-dp/patches/0012-gmac-syn-xgmac-silence-debug-log-on-probe.patch b/qca/qca-nss-dp/patches/0012-gmac-syn-xgmac-silence-debug-log-on-probe.patch deleted file mode 100644 index 2bc576ccb..000000000 --- a/qca/qca-nss-dp/patches/0012-gmac-syn-xgmac-silence-debug-log-on-probe.patch +++ /dev/null @@ -1,28 +0,0 @@ -From fee52ef165e9fab2fca15492677082fd8e9e891f Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Thu, 19 May 2022 23:40:24 +0200 -Subject: [PATCH 12/12] gmac: syn: xgmac: silence debug log on probe - -Silence debug log set as info in xgmac port probe. - -Signed-off-by: Ansuel Smith ---- - hal/gmac_ops/syn/xgmac/syn_if.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/hal/gmac_ops/syn/xgmac/syn_if.c b/hal/gmac_ops/syn/xgmac/syn_if.c -index 1152f5c..bc2880d 100644 ---- a/hal/gmac_ops/syn/xgmac/syn_if.c -+++ b/hal/gmac_ops/syn/xgmac/syn_if.c -@@ -445,7 +445,7 @@ static void *syn_init(struct nss_gmac_hal_platform_data *gmacpdata) - - spin_lock_init(&shd->nghd.slock); - -- netdev_info(ndev, "ioremap OK.Size 0x%x Ndev base 0x%lx macbase 0x%px\n", -+ netdev_dbg(ndev, "ioremap OK.Size 0x%x Ndev base 0x%lx macbase 0x%px\n", - gmacpdata->reg_len, - ndev->base_addr, - shd->nghd.mac_base); --- -2.34.1 - diff --git a/qca/qca-nss-dp/patches/0013-nss_dp_main-Use-a-phy-handle-property-to-connect-to-.patch b/qca/qca-nss-dp/patches/0013-nss_dp_main-Use-a-phy-handle-property-to-connect-to-.patch deleted file mode 100644 index ea6993d75..000000000 --- a/qca/qca-nss-dp/patches/0013-nss_dp_main-Use-a-phy-handle-property-to-connect-to-.patch +++ /dev/null @@ -1,189 +0,0 @@ -From 8293a26ca56ee2e9a88e4efb5dcc7f647803cd8c Mon Sep 17 00:00:00 2001 -From: Alexandru Gagniuc -Date: Sun, 5 Jun 2022 21:45:09 -0500 -Subject: [PATCH] nss_dp_main: Use a 'phy-handle' property to connect to the - PHY - -The original method of connecting a PHY to the ethernet controller -requires the "qcom,link-poll", and "qcom,phy-mdio-addr" devicetree -properties. This is redundant. The PHY node already contains the MDIO -address, and attaching a PHY implies "link-poll". - -Allow using a "phy-handle" property. Remove the following properties, -as they are no longer used: - * "qcom,link-poll" - * "qcom,phy-mdio-addr" - * "mdio-bus" - * "qcom,forced-speed" - * "qcom,forced-duplex" - -Signed-off-by: Alexandru Gagniuc ---- - include/nss_dp_dev.h | 5 +-- - nss_dp_main.c | 91 +++++--------------------------------------- - 2 files changed, 10 insertions(+), 86 deletions(-) - -diff --git a/include/nss_dp_dev.h b/include/nss_dp_dev.h -index 19b3e78..63a857a 100644 ---- a/include/nss_dp_dev.h -+++ b/include/nss_dp_dev.h -@@ -100,13 +100,10 @@ struct nss_dp_dev { - unsigned long drv_flags; /* Driver specific feature flags */ - - /* Phy related stuff */ -+ struct device_node *phy_node; - struct phy_device *phydev; /* Phy device */ - struct mii_bus *miibus; /* MII bus */ - phy_interface_t phy_mii_type; /* RGMII/SGMII/QSGMII */ -- uint32_t phy_mdio_addr; /* Mdio address */ -- bool link_poll; /* Link polling enable? */ -- uint32_t forced_speed; /* Forced speed? */ -- uint32_t forced_duplex; /* Forced duplex? */ - uint32_t link_state; /* Current link state */ - uint32_t pause; /* Current flow control settings */ - -diff --git a/nss_dp_main.c b/nss_dp_main.c -index 441c300..a1e8627 100644 ---- a/nss_dp_main.c -+++ b/nss_dp_main.c -@@ -399,7 +399,7 @@ static int nss_dp_open(struct net_device *netdev) - - netif_start_queue(netdev); - -- if (!dp_priv->link_poll) { -+ if (!dp_priv->phydev) { - /* Notify data plane link is up */ - if (dp_priv->data_plane_ops->link_state(dp_priv->dpc, 1)) { - netdev_dbg(netdev, "Data plane set link failed\n"); -@@ -576,6 +576,8 @@ static int32_t nss_dp_of_get_pdata(struct device_node *np, - return -EFAULT; - } - -+ dp_priv->phy_node = of_parse_phandle(np, "phy-handle", 0); -+ - if (of_property_read_u32(np, "qcom,mactype", &hal_pdata->mactype)) { - pr_err("%s: error reading mactype\n", np->name); - return -EFAULT; -@@ -594,16 +596,6 @@ static int32_t nss_dp_of_get_pdata(struct device_node *np, - #else - of_get_phy_mode(np, &dp_priv->phy_mii_type); - #endif -- dp_priv->link_poll = of_property_read_bool(np, "qcom,link-poll"); -- if (of_property_read_u32(np, "qcom,phy-mdio-addr", -- &dp_priv->phy_mdio_addr) && dp_priv->link_poll) { -- pr_err("%s: mdio addr required if link polling is enabled\n", -- np->name); -- return -EFAULT; -- } -- -- of_property_read_u32(np, "qcom,forced-speed", &dp_priv->forced_speed); -- of_property_read_u32(np, "qcom,forced-duplex", &dp_priv->forced_duplex); - - ret = of_get_mac_address(np, maddr); - if (!ret && is_valid_ether_addr(maddr)) { -@@ -636,50 +628,6 @@ static int32_t nss_dp_of_get_pdata(struct device_node *np, - return 0; - } - --/* -- * nss_dp_mdio_attach() -- */ --static struct mii_bus *nss_dp_mdio_attach(struct platform_device *pdev) --{ -- struct device_node *mdio_node; -- struct platform_device *mdio_plat; -- struct ipq40xx_mdio_data *mdio_data; -- -- /* -- * Find mii_bus using "mdio-bus" handle. -- */ -- mdio_node = of_parse_phandle(pdev->dev.of_node, "mdio-bus", 0); -- if (mdio_node) { -- return of_mdio_find_bus(mdio_node); -- } -- -- mdio_node = of_find_compatible_node(NULL, NULL, "qcom,qca-mdio"); -- if (!mdio_node) { -- mdio_node = of_find_compatible_node(NULL, NULL, -- "qcom,ipq40xx-mdio"); -- if (!mdio_node) { -- dev_err(&pdev->dev, "cannot find mdio node by phandle\n"); -- return NULL; -- } -- } -- -- mdio_plat = of_find_device_by_node(mdio_node); -- if (!mdio_plat) { -- dev_err(&pdev->dev, "cannot find platform device from mdio node\n"); -- of_node_put(mdio_node); -- return NULL; -- } -- -- mdio_data = dev_get_drvdata(&mdio_plat->dev); -- if (!mdio_data) { -- dev_err(&pdev->dev, "cannot get mii bus reference from device data\n"); -- of_node_put(mdio_node); -- return NULL; -- } -- -- return mdio_data->mii_bus; --} -- - #ifdef CONFIG_NET_SWITCHDEV - /* - * nss_dp_is_phy_dev() -@@ -738,7 +686,6 @@ static int32_t nss_dp_probe(struct platform_device *pdev) - struct device_node *np = pdev->dev.of_node; - struct nss_gmac_hal_platform_data gmac_hal_pdata; - int32_t ret = 0; -- uint8_t phy_id[MII_BUS_ID_SIZE + 3]; - #if defined(NSS_DP_PPE_SUPPORT) - uint32_t vsi_id; - fal_port_t port_id; -@@ -813,37 +760,17 @@ static int32_t nss_dp_probe(struct platform_device *pdev) - - dp_priv->drv_flags |= NSS_DP_PRIV_FLAG(INIT_DONE); - -- if (dp_priv->link_poll) { -- dp_priv->miibus = nss_dp_mdio_attach(pdev); -- if (!dp_priv->miibus) { -- netdev_dbg(netdev, "failed to find miibus\n"); -- goto phy_setup_fail; -- } -- snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, -- dp_priv->miibus->id, dp_priv->phy_mdio_addr); -- -+ if (dp_priv->phy_node) { - SET_NETDEV_DEV(netdev, &pdev->dev); -- -- dp_priv->phydev = phy_connect(netdev, phy_id, -- &nss_dp_adjust_link, -- dp_priv->phy_mii_type); -+ dp_priv->phydev = of_phy_connect(netdev, dp_priv->phy_node, -+ &nss_dp_adjust_link, 0, -+ dp_priv->phy_mii_type); - if (IS_ERR(dp_priv->phydev)) { -- netdev_dbg(netdev, "failed to connect to phy device\n"); -+ dev_err(&pdev->dev, "Could not attach to PHY\n"); - goto phy_setup_fail; - } - --#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 5, 0)) -- dp_priv->phydev->advertising |= -- (ADVERTISED_Pause | ADVERTISED_Asym_Pause); -- dp_priv->phydev->supported |= -- (SUPPORTED_Pause | SUPPORTED_Asym_Pause); --#else -- linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, dp_priv->phydev->advertising); -- linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, dp_priv->phydev->advertising); -- -- linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, dp_priv->phydev->supported); -- linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, dp_priv->phydev->supported); --#endif -+ phy_attached_info(dp_priv->phydev); - } - - #if defined(NSS_DP_PPE_SUPPORT) --- -2.36.1 - diff --git a/qca/qca-nss-dp/patches/0014-nss-dp-edma-v1-switch-to-napi_gro_receive.patch b/qca/qca-nss-dp/patches/0014-nss-dp-edma-v1-switch-to-napi_gro_receive.patch deleted file mode 100644 index 3a437bd37..000000000 --- a/qca/qca-nss-dp/patches/0014-nss-dp-edma-v1-switch-to-napi_gro_receive.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 57b521e876986844dfe34457f39c62dc8100424d Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Thu, 23 Jun 2022 14:18:50 +0200 -Subject: [PATCH] nss-dp: edma-v1: switch to napi_gro_receive - -Utilize napi_gro_receive instead of plain netif_receive_skb on EDMA v1. -It provides significant performance improvements when testing with iperf3. - -Signed-off-by: Robert Marko ---- - Makefile | 2 +- - hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c | 4 ++++ - 2 files changed, 5 insertions(+), 1 deletion(-) - -diff --git a/Makefile b/Makefile -index 8e81317..dcfa8ca 100644 ---- a/Makefile -+++ b/Makefile -@@ -25,7 +25,7 @@ qca-nss-dp-objs += hal/dp_ops/edma_dp/edma_v1/edma_cfg.o \ - hal/gmac_ops/qcom/qcom_if.o \ - hal/gmac_ops/syn/xgmac/syn_if.o - NSS_DP_INCLUDE += -I$(obj)/hal/dp_ops/edma_dp/edma_v1/include --ccflags-y += -DNSS_DP_PPE_SUPPORT -+ccflags-y += -DNSS_DP_PPE_SUPPORT -DNSS_DP_ENABLE_NAPI_GRO - endif - - ifeq ($(SoC),$(filter $(SoC),ipq807x)) -diff --git a/hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c b/hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c -index 5780a30..6ee1451 100644 ---- a/hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c -+++ b/hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c -@@ -411,7 +411,11 @@ static uint32_t edma_clean_rx(struct edma_hw *ehw, - NSS_PTP_EVENT_SERVICE_CODE)) - nss_phy_tstamp_rx_buf(ndev, skb); - else -+#if defined(NSS_DP_ENABLE_NAPI_GRO) -+ napi_gro_receive(&ehw->napi, skb); -+#else - netif_receive_skb(skb); -+#endif - - next_rx_desc: - /* --- -2.36.1 - diff --git a/qca/qca-nss-drv/Makefile b/qca/qca-nss-drv/Makefile deleted file mode 100644 index 92616caaa..000000000 --- a/qca/qca-nss-drv/Makefile +++ /dev/null @@ -1,129 +0,0 @@ -include $(TOPDIR)/rules.mk - -PKG_NAME:=qca-nss-drv -PKG_RELEASE:=$(AUTORELEASE) - -PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/nss-drv.git -PKG_SOURCE_PROTO:=git -PKG_SOURCE_DATE:=2022-03-07 -PKG_SOURCE_VERSION:=397c88cf184e0eb011dd44ad82c2dfae60ece1b4 -PKG_MIRROR_HASH:=a3bea305d85fcec3d77f9b40d06a71b65ccf3d8b98018d9c8c23d6ad95e6aedc - -PKG_BUILD_PARALLEL:=1 - -include $(INCLUDE_DIR)/kernel.mk -include $(INCLUDE_DIR)/package.mk - -NSS_CLIENTS_DIR:=$(TOPDIR)/qca/src/qca-nss-clients - -define KernelPackage/qca-nss-drv - SECTION:=kernel - CATEGORY:=Kernel modules - SUBMENU:=Network Devices - DEPENDS:=@(TARGET_ipq807x||TARGET_ipq60xx) +kmod-qca-nss-dp - TITLE:=Kernel driver for NSS (core driver) - FILES:=$(PKG_BUILD_DIR)/qca-nss-drv.ko - AUTOLOAD:=$(call AutoLoad,32,qca-nss-drv) -endef - -define KernelPackage/qca-nss-drv/install - $(INSTALL_DIR) $(1)/lib/debug - $(INSTALL_DIR) $(1)/etc/init.d - $(INSTALL_DIR) $(1)/etc/sysctl.d - $(INSTALL_DIR) $(1)/etc/hotplug.d/firmware - $(INSTALL_DIR) $(1)/etc/config - - $(INSTALL_BIN) ./files/qca-nss-drv.debug $(1)/lib/debug/qca-nss-drv - $(INSTALL_BIN) ./files/qca-nss-drv.init $(1)/etc/init.d/qca-nss-drv - $(INSTALL_BIN) ./files/qca-nss-drv.sysctl $(1)/etc/sysctl.d/qca-nss-drv.conf - $(INSTALL_BIN) ./files/qca-nss-drv.hotplug $(1)/etc/hotplug.d/firmware/10-qca-nss-fw - $(INSTALL_BIN) ./files/qca-nss-drv.conf $(1)/etc/config/nss - -endef - -define KernelPackage/qca-nss-drv/Description -This package contains a NSS driver for QCA chipset -endef - -define Build/InstallDev - mkdir -p $(1)/usr/include/qca-nss-drv - $(CP) $(PKG_BUILD_DIR)/exports/* $(1)/usr/include/qca-nss-drv/ -endef - -EXTRA_CFLAGS+= -I$(STAGING_DIR)/usr/include/qca-nss-gmac \ - -I$(STAGING_DIR)/usr/include/qca-nss-dp \ - -I$(STAGING_DIR)/usr/include/qca-ssdk \ - -Wno-unused-variable - -ifneq (, $(findstring $(CONFIG_TARGET_BOARD), "ipq807x" "ipq60xx")) -EXTRA_CFLAGS+= -DNSS_MEM_PROFILE_MEDIUM -LOW_MEM_PROFILE_MAKE_OPTS=y -endif - -ifeq ($(CONFIG_KERNEL_SKB_FIXED_SIZE_2K),y) -EXTRA_CFLAGS+= -DNSS_SKB_FIXED_SIZE_2K -endif - -DRV_MAKE_OPTS:= -ifeq ($(LOW_MEM_PROFILE_MAKE_OPTS),y) -DRV_MAKE_OPTS+= \ - NSS_DRV_C2C_ENABLE=n \ - NSS_DRV_CAPWAP_ENABLE=n \ - NSS_DRV_CLMAP_ENABLE=n \ - NSS_DRV_CRYPTO_ENABLE=y \ - NSS_DRV_DTLS_ENABLE=n \ - NSS_DRV_GRE_ENABLE=n \ - NSS_DRV_GRE_REDIR_ENABLE=n \ - NSS_DRV_GRE_TUNNEL_ENABLE=n \ - NSS_DRV_IGS_ENABLE=n \ - NSS_DRV_IPSEC_ENABLE=n \ - NSS_DRV_LAG_ENABLE=n \ - NSS_DRV_L2TP_ENABLE=n \ - NSS_DRV_MAPT_ENABLE=n \ - NSS_DRV_OAM_ENABLE=n \ - NSS_DRV_PPTP_ENABLE=n \ - NSS_DRV_PORTID_ENABLE=n \ - NSS_DRV_PVXLAN_ENABLE=n \ - NSS_DRV_QRFS_ENABLE=n \ - NSS_DRV_QVPN_ENABLE=n \ - NSS_DRV_RMNET_ENABLE=n \ - NSS_DRV_SHAPER_ENABLE=n \ - NSS_DRV_SJACK_ENABLE=n \ - NSS_DRV_TLS_ENABLE=n \ - NSS_DRV_TRUSTSEC_ENABLE=n \ - NSS_DRV_TSTAMP_ENABLE=n \ - NSS_DRV_TUN6RD_ENABLE=n \ - NSS_DRV_TUNIPIP6_ENABLE=n \ - NSS_DRV_VXLAN_ENABLE=n \ - NSS_DRV_MATCH_ENABLE=n \ - NSS_DRV_MIRROR_ENABLE=n \ - NSS_DRV_PPPOE_ENABLE=n \ - NSS_DRV_VIRT_IF_ENABLE=n \ - NSS_DRV_VLAN_ENABLE=n \ - NSS_DRV_BRIDGE_ENABLE=n \ - NSS_DRV_WIFI_EXT_VDEV_ENABLE=n \ - NSS_DRV_WIFI_MESH_ENABLE=n -endif - -ifeq ($(CONFIG_TARGET_BOARD), "ipq807x") - SOC="ipq807x_64" -else ifeq ($(CONFIG_TARGET_BOARD), "ipq60xx") - SOC="ipq60xx_64" -endif - -define Build/Configure - $(LN) arch/nss_$(SOC).h $(PKG_BUILD_DIR)/exports/nss_arch.h -endef - -define Build/Compile - +$(MAKE) -C "$(LINUX_DIR)" $(strip $(DRV_MAKE_OPTS)) \ - CROSS_COMPILE="$(TARGET_CROSS)" \ - ARCH="$(LINUX_KARCH)" \ - M="$(PKG_BUILD_DIR)" \ - EXTRA_CFLAGS="$(EXTRA_CFLAGS)" SoC=$(SOC) \ - $(KERNEL_MAKE_FLAGS) \ - $(PKG_JOBS) \ - modules -endef - -$(eval $(call KernelPackage,qca-nss-drv)) diff --git a/qca/qca-nss-drv/files/qca-nss-drv.conf b/qca/qca-nss-drv/files/qca-nss-drv.conf deleted file mode 100644 index a8a1fbf40..000000000 --- a/qca/qca-nss-drv/files/qca-nss-drv.conf +++ /dev/null @@ -1,6 +0,0 @@ -config nss_firmware 'qca_nss_0' - -config nss_firmware 'qca_nss_1' - -config general - option enable_rps '1' diff --git a/qca/qca-nss-drv/files/qca-nss-drv.debug b/qca/qca-nss-drv/files/qca-nss-drv.debug deleted file mode 100644 index 5d435c3a7..000000000 --- a/qca/qca-nss-drv/files/qca-nss-drv.debug +++ /dev/null @@ -1,26 +0,0 @@ -#!/bin/sh /sbin/sysdebug -# -# Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. -# -# Permission to use, copy, modify, and/or distribute this software for any -# purpose with or without fee is hereby granted, provided that the above -# copyright notice and this permission notice appear in all copies. -# -# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -# - -log cat /sys/kernel/debug/qca-nss-drv/stats/pppoe -log cat /sys/kernel/debug/qca-nss-drv/stats/n2h -log cat /sys/kernel/debug/qca-nss-drv/stats/ipv6 -log cat /sys/kernel/debug/qca-nss-drv/stats/ipv4 -log cat /sys/kernel/debug/qca-nss-drv/stats/gmac -log cat /sys/kernel/debug/qca-nss-drv/stats/drv -log cat /sys/kernel/debug/qca-nss-drv/stats/wifi -log cat /sys/kernel/debug/qca-nss-drv/stats/wifi_if -log cat /sys/kernel/debug/qca-nss-drv/stats/eth_rx diff --git a/qca/qca-nss-drv/files/qca-nss-drv.hotplug b/qca/qca-nss-drv/files/qca-nss-drv.hotplug deleted file mode 100644 index 1e4813838..000000000 --- a/qca/qca-nss-drv/files/qca-nss-drv.hotplug +++ /dev/null @@ -1,70 +0,0 @@ -#!/bin/sh -# -# Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. -# -# Permission to use, copy, modify, and/or distribute this software for any -# purpose with or without fee is hereby granted, provided that the above -# copyright notice and this permission notice appear in all copies. -# -# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -# - -KERNEL=`uname -r` -case "${KERNEL}" in - 3.4*) - select_or_load=load_nss_fw - ;; - *) - select_or_load=select_nss_fw - ;; -esac - -load_nss_fw () { - ls -l $1 | awk ' { print $9,$5 } '> /dev/console - echo 1 > /sys/class/firmware/$DEVICENAME/loading - cat $1 > /sys/class/firmware/$DEVICENAME/data - echo 0 > /sys/class/firmware/$DEVICENAME/loading -} - -select_nss_fw () { - rm -f /lib/firmware/$DEVICENAME - ln -s $1 /lib/firmware/$DEVICENAME - ls -l /lib/firmware/$DEVICENAME | awk ' { print $9,$5 } '> /dev/console -} - -[ "$ACTION" != "add" ] && exit - -# dev name for UCI, since it doesn't let you use . or - -SDEVNAME=$(echo ${DEVICENAME} | sed s/[.-]/_/g) - -SELECTED_FW=$(uci get nss.${SDEVNAME}.firmware 2>/dev/null) -[ -e "${SELECTED_FW}" ] && { - $select_or_load ${SELECTED_FW} - exit -} - -case $DEVICENAME in - qca-nss0* | qca-nss.0*) - if [ -e /lib/firmware/qca-nss0-enterprise.bin ] ; then - $select_or_load /lib/firmware/qca-nss0-enterprise.bin - else - $select_or_load /lib/firmware/qca-nss0-retail.bin - fi - exit - ;; - qca-nss1* | qca-nss.1*) - if [ -e /lib/firmware/qca-nss1-enterprise.bin ] ; then - $select_or_load /lib/firmware/qca-nss1-enterprise.bin - else - $select_or_load /lib/firmware/qca-nss1-retail.bin - fi - exit - ;; -esac - diff --git a/qca/qca-nss-drv/files/qca-nss-drv.init b/qca/qca-nss-drv/files/qca-nss-drv.init deleted file mode 100644 index de12cb6d1..000000000 --- a/qca/qca-nss-drv/files/qca-nss-drv.init +++ /dev/null @@ -1,50 +0,0 @@ -#!/bin/sh /etc/rc.common -# -# Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. -# -# Permission to use, copy, modify, and/or distribute this software for any -# purpose with or without fee is hereby granted, provided that the above -# copyright notice and this permission notice appear in all copies. -# -# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -# - -START=70 - -enable_rps() { - irq_nss_rps=`grep nss_queue1 /proc/interrupts | cut -d ':' -f 1 | tr -d ' '` - for entry in $irq_nss_rps - do - echo 2 > /proc/irq/$entry/smp_affinity - done - - irq_nss_rps=`grep nss_queue2 /proc/interrupts | cut -d ':' -f 1 | tr -d ' '` - for entry in $irq_nss_rps - do - echo 4 > /proc/irq/$entry/smp_affinity - done - - irq_nss_rps=`grep nss_queue3 /proc/interrupts | cut -d ':' -f 1 | tr -d ' '` - for entry in $irq_nss_rps - do - echo 8 > /proc/irq/$entry/smp_affinity - done - - # Enable NSS RPS - sysctl -w dev.nss.rps.enable=1 >/dev/null 2>/dev/null - -} - - -start() { - local rps_enabled="$(uci_get nss @general[0] enable_rps)" - if [ "$rps_enabled" -eq 1 ]; then - enable_rps - fi -} diff --git a/qca/qca-nss-drv/files/qca-nss-drv.sysctl b/qca/qca-nss-drv/files/qca-nss-drv.sysctl deleted file mode 100644 index fc36c33eb..000000000 --- a/qca/qca-nss-drv/files/qca-nss-drv.sysctl +++ /dev/null @@ -1,4 +0,0 @@ -# Default Number of connection configuration -dev.nss.ipv4cfg.ipv4_conn=4096 -dev.nss.ipv6cfg.ipv6_conn=4096 - diff --git a/qca/qca-nss-drv/patches/0001-core-add-5.10-kernel-to-version-check.patch b/qca/qca-nss-drv/patches/0001-core-add-5.10-kernel-to-version-check.patch deleted file mode 100644 index 3fea9b5ce..000000000 --- a/qca/qca-nss-drv/patches/0001-core-add-5.10-kernel-to-version-check.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 3885c752e12f74cad6c97888b797e5903ad1930d Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Thu, 13 May 2021 23:22:38 +0200 -Subject: [PATCH] core: add 5.10 kernel to version check - -NSS DRV has a kernel version check, so simply add -5.10 as supported. - -Signed-off-by: Robert Marko ---- - nss_core.c | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - ---- a/nss_core.c -+++ b/nss_core.c -@@ -52,7 +52,8 @@ - (((LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0)))) || \ - (((LINUX_VERSION_CODE >= KERNEL_VERSION(3, 18, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 19, 0)))) || \ - (((LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(4, 5, 0)))) || \ --(((LINUX_VERSION_CODE >= KERNEL_VERSION(5, 4, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 5, 0)))))) -+(((LINUX_VERSION_CODE >= KERNEL_VERSION(5, 4, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 5, 0)))) || \ -+(((LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 11, 0)))))) - #error "Check skb recycle code in this file to match Linux version" - #endif - diff --git a/qca/qca-nss-drv/patches/0002-nss-drv-replace-ioremap_nocache-with-ioremap.patch b/qca/qca-nss-drv/patches/0002-nss-drv-replace-ioremap_nocache-with-ioremap.patch deleted file mode 100644 index 89d650be1..000000000 --- a/qca/qca-nss-drv/patches/0002-nss-drv-replace-ioremap_nocache-with-ioremap.patch +++ /dev/null @@ -1,181 +0,0 @@ -From 0cffa7bb366a4e0ff5665d6fc2fa33c1437cb397 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Thu, 13 May 2021 23:33:18 +0200 -Subject: [PATCH 2/8] nss-drv: replace ioremap_nocache() with ioremap() - -ioremap_nocache() does not exist anymore. - -Signed-off-by: Robert Marko ---- - nss_hal/ipq50xx/nss_hal_pvt.c | 6 +++--- - nss_hal/ipq60xx/nss_hal_pvt.c | 8 ++++---- - nss_hal/ipq806x/nss_hal_pvt.c | 4 ++-- - nss_hal/ipq807x/nss_hal_pvt.c | 6 +++--- - nss_hal/nss_hal.c | 4 ++-- - nss_meminfo.c | 2 +- - nss_ppe.c | 2 +- - 7 files changed, 16 insertions(+), 16 deletions(-) - -diff --git a/nss_hal/ipq50xx/nss_hal_pvt.c b/nss_hal/ipq50xx/nss_hal_pvt.c -index 3d6dfd0..e3e4bd2 100644 ---- a/nss_hal/ipq50xx/nss_hal_pvt.c -+++ b/nss_hal/ipq50xx/nss_hal_pvt.c -@@ -184,13 +184,13 @@ static struct nss_platform_data *__nss_hal_of_get_pdata(struct platform_device * - npd->nphys = res_nphys.start; - npd->qgic_phys = res_qgic_phys.start; - -- npd->nmap = ioremap_nocache(npd->nphys, resource_size(&res_nphys)); -+ npd->nmap = ioremap(npd->nphys, resource_size(&res_nphys)); - if (!npd->nmap) { - nss_info_always("%px: nss%d: ioremap() fail for nphys\n", nss_ctx, nss_ctx->id); - goto out; - } - -- npd->qgic_map = ioremap_nocache(npd->qgic_phys, resource_size(&res_qgic_phys)); -+ npd->qgic_map = ioremap(npd->qgic_phys, resource_size(&res_qgic_phys)); - if (!npd->qgic_map) { - nss_info_always("%px: nss%d: ioremap() fail for qgic map\n", nss_ctx, nss_ctx->id); - goto out; -@@ -348,7 +348,7 @@ static int __nss_hal_common_reset(struct platform_device *nss_dev) - - of_node_put(cmn); - -- nss_misc_reset = ioremap_nocache(res_nss_misc_reset.start, resource_size(&res_nss_misc_reset)); -+ nss_misc_reset = ioremap(res_nss_misc_reset.start, resource_size(&res_nss_misc_reset)); - if (!nss_misc_reset) { - pr_err("%px: ioremap fail for nss_misc_reset\n", nss_dev); - return -EFAULT; -diff --git a/nss_hal/ipq60xx/nss_hal_pvt.c b/nss_hal/ipq60xx/nss_hal_pvt.c -index 4c84cb9..e76ef6d 100644 ---- a/nss_hal/ipq60xx/nss_hal_pvt.c -+++ b/nss_hal/ipq60xx/nss_hal_pvt.c -@@ -207,13 +207,13 @@ static struct nss_platform_data *__nss_hal_of_get_pdata(struct platform_device * - npd->nphys = res_nphys.start; - npd->qgic_phys = res_qgic_phys.start; - -- npd->nmap = ioremap_nocache(npd->nphys, resource_size(&res_nphys)); -+ npd->nmap = ioremap(npd->nphys, resource_size(&res_nphys)); - if (!npd->nmap) { - nss_info_always("%px: nss%d: ioremap() fail for nphys\n", nss_ctx, nss_ctx->id); - goto out; - } - -- npd->qgic_map = ioremap_nocache(npd->qgic_phys, resource_size(&res_qgic_phys)); -+ npd->qgic_map = ioremap(npd->qgic_phys, resource_size(&res_qgic_phys)); - if (!npd->qgic_map) { - nss_info_always("%px: nss%d: ioremap() fail for qgic map\n", nss_ctx, nss_ctx->id); - goto out; -@@ -433,13 +433,13 @@ static int __nss_hal_common_reset(struct platform_device *nss_dev) - - of_node_put(cmn); - -- nss_misc_reset = ioremap_nocache(res_nss_misc_reset.start, resource_size(&res_nss_misc_reset)); -+ nss_misc_reset = ioremap(res_nss_misc_reset.start, resource_size(&res_nss_misc_reset)); - if (!nss_misc_reset) { - pr_err("%px: ioremap fail for nss_misc_reset\n", nss_dev); - return -EFAULT; - } - -- nss_misc_reset_flag = ioremap_nocache(res_nss_misc_reset_flag.start, resource_size(&res_nss_misc_reset_flag)); -+ nss_misc_reset_flag = ioremap(res_nss_misc_reset_flag.start, resource_size(&res_nss_misc_reset_flag)); - if (!nss_misc_reset_flag) { - pr_err("%px: ioremap fail for nss_misc_reset_flag\n", nss_dev); - return -EFAULT; -diff --git a/nss_hal/ipq806x/nss_hal_pvt.c b/nss_hal/ipq806x/nss_hal_pvt.c -index b8733e0..52d63b0 100644 ---- a/nss_hal/ipq806x/nss_hal_pvt.c -+++ b/nss_hal/ipq806x/nss_hal_pvt.c -@@ -458,7 +458,7 @@ static struct nss_platform_data *__nss_hal_of_get_pdata(struct platform_device * - npd->nphys = res_nphys.start; - npd->vphys = res_vphys.start; - -- npd->nmap = ioremap_nocache(npd->nphys, resource_size(&res_nphys)); -+ npd->nmap = ioremap(npd->nphys, resource_size(&res_nphys)); - if (!npd->nmap) { - nss_info_always("%px: nss%d: ioremap() fail for nphys\n", nss_ctx, nss_ctx->id); - goto out; -@@ -711,7 +711,7 @@ static int __nss_hal_common_reset(struct platform_device *nss_dev) - } - of_node_put(cmn); - -- fpb_base = ioremap_nocache(res_nss_fpb_base.start, resource_size(&res_nss_fpb_base)); -+ fpb_base = ioremap(res_nss_fpb_base.start, resource_size(&res_nss_fpb_base)); - if (!fpb_base) { - pr_err("%px: ioremap fail for nss_fpb_base\n", nss_dev); - return -EFAULT; -diff --git a/nss_hal/ipq807x/nss_hal_pvt.c b/nss_hal/ipq807x/nss_hal_pvt.c -index b95a23c..bb8f42f 100644 ---- a/nss_hal/ipq807x/nss_hal_pvt.c -+++ b/nss_hal/ipq807x/nss_hal_pvt.c -@@ -234,7 +234,7 @@ static struct nss_platform_data *__nss_hal_of_get_pdata(struct platform_device * - npd->vphys = res_vphys.start; - npd->qgic_phys = res_qgic_phys.start; - -- npd->nmap = ioremap_nocache(npd->nphys, resource_size(&res_nphys)); -+ npd->nmap = ioremap(npd->nphys, resource_size(&res_nphys)); - if (!npd->nmap) { - nss_info_always("%px: nss%d: ioremap() fail for nphys\n", nss_ctx, nss_ctx->id); - goto out; -@@ -247,7 +247,7 @@ static struct nss_platform_data *__nss_hal_of_get_pdata(struct platform_device * - goto out; - } - -- npd->qgic_map = ioremap_nocache(npd->qgic_phys, resource_size(&res_qgic_phys)); -+ npd->qgic_map = ioremap(npd->qgic_phys, resource_size(&res_qgic_phys)); - if (!npd->qgic_map) { - nss_info_always("%px: nss%d: ioremap() fail for qgic map\n", nss_ctx, nss_ctx->id); - goto out; -@@ -467,7 +467,7 @@ static int __nss_hal_common_reset(struct platform_device *nss_dev) - } - of_node_put(cmn); - -- nss_misc_reset = ioremap_nocache(res_nss_misc_reset.start, resource_size(&res_nss_misc_reset)); -+ nss_misc_reset = ioremap(res_nss_misc_reset.start, resource_size(&res_nss_misc_reset)); - if (!nss_misc_reset) { - pr_err("%px: ioremap fail for nss_misc_reset\n", nss_dev); - return -EFAULT; -diff --git a/nss_hal/nss_hal.c b/nss_hal/nss_hal.c -index d58bb57..57974c1 100644 ---- a/nss_hal/nss_hal.c -+++ b/nss_hal/nss_hal.c -@@ -78,9 +78,9 @@ int nss_hal_firmware_load(struct nss_ctx_instance *nss_ctx, struct platform_devi - return rc; - } - -- load_mem = ioremap_nocache(npd->load_addr, nss_fw->size); -+ load_mem = ioremap(npd->load_addr, nss_fw->size); - if (!load_mem) { -- nss_info_always("%px: ioremap_nocache failed: %x", nss_ctx, npd->load_addr); -+ nss_info_always("%px: ioremap failed: %x", nss_ctx, npd->load_addr); - release_firmware(nss_fw); - return rc; - } -diff --git a/nss_meminfo.c b/nss_meminfo.c -index e24e6be..2255eae 100644 ---- a/nss_meminfo.c -+++ b/nss_meminfo.c -@@ -728,7 +728,7 @@ bool nss_meminfo_init(struct nss_ctx_instance *nss_ctx) - /* - * meminfo_start is the label where the start address of meminfo map is stored. - */ -- meminfo_start = (uint32_t *)ioremap_nocache(nss_ctx->load + NSS_MEMINFO_MAP_START_OFFSET, -+ meminfo_start = (uint32_t *)ioremap(nss_ctx->load + NSS_MEMINFO_MAP_START_OFFSET, - NSS_MEMINFO_RESERVE_AREA_SIZE); - if (!meminfo_start) { - nss_info_always("%px: cannot remap meminfo start\n", nss_ctx); -diff --git a/nss_ppe.c b/nss_ppe.c -index 46ce217..644fc98 100644 ---- a/nss_ppe.c -+++ b/nss_ppe.c -@@ -357,7 +357,7 @@ void nss_ppe_init(void) - /* - * Get the PPE base address - */ -- ppe_pvt.ppe_base = ioremap_nocache(PPE_BASE_ADDR, PPE_REG_SIZE); -+ ppe_pvt.ppe_base = ioremap(PPE_BASE_ADDR, PPE_REG_SIZE); - if (!ppe_pvt.ppe_base) { - nss_warning("DRV can't get PPE base address\n"); - return; --- -2.34.1 - diff --git a/qca/qca-nss-drv/patches/0003-DMA-Fix-NULL-pointer-exceptions.patch b/qca/qca-nss-drv/patches/0003-DMA-Fix-NULL-pointer-exceptions.patch deleted file mode 100644 index 0c13a7887..000000000 --- a/qca/qca-nss-drv/patches/0003-DMA-Fix-NULL-pointer-exceptions.patch +++ /dev/null @@ -1,49 +0,0 @@ -From 62e457f262aaa0db7113ad3ccbcb7ae49d4d7ea8 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Tue, 8 Jun 2021 23:24:43 +0200 -Subject: [PATCH] DMA: Fix NULL pointer exceptions - -There are multiple instances that pass NULL instead -of device to DMA functions. -That is incorrect and will cause kernel NULL pointer -exceptions. - -So, simply pass the device structure pointers. - -Signed-off-by: Robert Marko ---- - nss_core.c | 2 +- - nss_coredump.c | 4 ++-- - 2 files changed, 3 insertions(+), 3 deletions(-) - ---- a/nss_core.c -+++ b/nss_core.c -@@ -1617,7 +1617,7 @@ static int32_t nss_core_handle_cause_que - * - */ - if (unlikely((buffer_type == N2H_BUFFER_CRYPTO_RESP))) { -- dma_unmap_single(NULL, (desc->buffer + desc->payload_offs), desc->payload_len, DMA_FROM_DEVICE); -+ dma_unmap_single(nss_ctx->dev, (desc->buffer + desc->payload_offs), desc->payload_len, DMA_FROM_DEVICE); - goto consume; - } - ---- a/nss_coredump.c -+++ b/nss_coredump.c -@@ -154,7 +154,7 @@ void nss_fw_coredump_notify(struct nss_c - dma_addr = nss_own->meminfo_ctx.logbuffer_dma; - } - -- dma_sync_single_for_cpu(NULL, dma_addr, sizeof(struct nss_log_descriptor), DMA_FROM_DEVICE); -+ dma_sync_single_for_cpu(nss_own->dev, dma_addr, sizeof(struct nss_log_descriptor), DMA_FROM_DEVICE); - - /* - * If the current entry is smaller than or equal to the number of NSS_LOG_COREDUMP_LINE_NUM, -@@ -181,7 +181,7 @@ void nss_fw_coredump_notify(struct nss_c - - offset = (index * sizeof(struct nss_log_entry)) - + offsetof(struct nss_log_descriptor, log_ring_buffer); -- dma_sync_single_for_cpu(NULL, dma_addr + offset, -+ dma_sync_single_for_cpu(nss_own->dev, dma_addr + offset, - sizeof(struct nss_log_entry), DMA_FROM_DEVICE); - nss_info_always("%px: %s\n", nss_own, nle_print->message); - nle_print++; diff --git a/qca/qca-nss-drv/patches/0004-nss-drv-rework-NSS_CORE_DMA_CACHE_MAINT-ops.patch b/qca/qca-nss-drv/patches/0004-nss-drv-rework-NSS_CORE_DMA_CACHE_MAINT-ops.patch deleted file mode 100644 index 6ef442aad..000000000 --- a/qca/qca-nss-drv/patches/0004-nss-drv-rework-NSS_CORE_DMA_CACHE_MAINT-ops.patch +++ /dev/null @@ -1,573 +0,0 @@ -From 12cf63f66bfe509da6d845e5c716efd99dadf01e Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Tue, 5 Apr 2022 15:38:18 +0200 -Subject: [PATCH 4/8] nss-drv: rework NSS_CORE_DMA_CACHE_MAINT ops - -Rework NSS_CORE_DMA_CACHE_MAINT ops to use standard dma sync ops instead -of using the direct arch function. This permit to skip any hack/patch -needed for nss-drv to correctly compile on upstream kernel. - -We drop any NSS_CORE_DMA_CACHE_MAINT use in nss_core and we correctly -use the dma_sync_single_for_device we correctly dma addr using the new -DMA helper. -We drop sync for IOREMAP addr and we just leave a memory block. -We hope the nss_profiler is correctly ported. -We finally drop the NSS_CORE_DMA_CACHE_MAINT jus in case someone wants -to use it. - -Signed-off-by: Ansuel Smith ---- - nss_core.c | 136 +++++++++++++++++++++++++--------- - nss_core.h | 41 +++++----- - nss_hal/ipq806x/nss_hal_pvt.c | 5 +- - nss_hal/ipq807x/nss_hal_pvt.c | 5 +- - nss_meminfo.c | 5 +- - nss_profiler.c | 3 +- - 6 files changed, 127 insertions(+), 68 deletions(-) - -diff --git a/nss_core.c b/nss_core.c -index 23dc155..f9e6014 100644 ---- a/nss_core.c -+++ b/nss_core.c -@@ -1429,6 +1429,8 @@ static inline void nss_core_handle_empty_buffers(struct nss_ctx_instance *nss_ct - uint32_t count, uint32_t hlos_index, - uint16_t mask) - { -+ struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; -+ - while (count) { - /* - * Since we only return the primary skb, we have no way to unmap -@@ -1482,7 +1484,9 @@ next: - n2h_desc_ring->hlos_index = hlos_index; - if_map->n2h_hlos_index[NSS_IF_N2H_EMPTY_BUFFER_RETURN_QUEUE] = hlos_index; - -- NSS_CORE_DMA_CACHE_MAINT((void *)&if_map->n2h_hlos_index[NSS_IF_N2H_EMPTY_BUFFER_RETURN_QUEUE], sizeof(uint32_t), DMA_TO_DEVICE); -+ dma_sync_single_for_device(nss_ctx->dev, -+ n2h_hlos_index_to_dma(mem_ctx->if_map_dma, NSS_IF_N2H_EMPTY_BUFFER_RETURN_QUEUE), -+ sizeof(uint32_t), DMA_TO_DEVICE); - NSS_CORE_DSB(); - } - -@@ -1504,6 +1508,7 @@ static int32_t nss_core_handle_cause_queue(struct int_ctx_instance *int_ctx, uin - struct nss_ctx_instance *nss_ctx = int_ctx->nss_ctx; - struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; - struct nss_if_mem_map *if_map = mem_ctx->if_map; -+ int dma_size; - - qid = nss_core_cause_to_queue(cause); - -@@ -1515,7 +1520,8 @@ static int32_t nss_core_handle_cause_queue(struct int_ctx_instance *int_ctx, uin - n2h_desc_ring = &nss_ctx->n2h_desc_ring[qid]; - desc_if = &n2h_desc_ring->desc_ring; - desc_ring = desc_if->desc; -- NSS_CORE_DMA_CACHE_MAINT((void *)&if_map->n2h_nss_index[qid], sizeof(uint32_t), DMA_FROM_DEVICE); -+ dma_sync_single_for_device(nss_ctx->dev, n2h_nss_index_to_dma(mem_ctx->if_map_dma, qid), -+ sizeof(uint32_t), DMA_FROM_DEVICE); - NSS_CORE_DSB(); - nss_index = if_map->n2h_nss_index[qid]; - -@@ -1544,13 +1550,23 @@ static int32_t nss_core_handle_cause_queue(struct int_ctx_instance *int_ctx, uin - start = hlos_index; - end = (hlos_index + count) & mask; - if (end > start) { -- dmac_inv_range((void *)&desc_ring[start], (void *)&desc_ring[end] + sizeof(struct n2h_descriptor)); -+ dma_size = sizeof(struct n2h_descriptor) * (end - start + 1); -+ -+ dma_sync_single_for_device(nss_ctx->dev, n2h_desc_index_to_dma(if_map, qid, start), -+ dma_size, DMA_FROM_DEVICE); - } else { - /* - * We have wrapped around - */ -- dmac_inv_range((void *)&desc_ring[start], (void *)&desc_ring[mask] + sizeof(struct n2h_descriptor)); -- dmac_inv_range((void *)&desc_ring[0], (void *)&desc_ring[end] + sizeof(struct n2h_descriptor)); -+ dma_size = sizeof(struct n2h_descriptor) * (mask - start + 1); -+ -+ dma_sync_single_for_device(nss_ctx->dev, n2h_desc_index_to_dma(if_map, qid, start), -+ dma_size, DMA_FROM_DEVICE); -+ -+ dma_size = sizeof(struct n2h_descriptor) * (end + 1); -+ -+ dma_sync_single_for_device(nss_ctx->dev, n2h_desc_index_to_dma(if_map, qid, 0), dma_size, -+ DMA_FROM_DEVICE); - } - - /* -@@ -1679,7 +1695,8 @@ next: - n2h_desc_ring->hlos_index = hlos_index; - if_map->n2h_hlos_index[qid] = hlos_index; - -- NSS_CORE_DMA_CACHE_MAINT((void *)&if_map->n2h_hlos_index[qid], sizeof(uint32_t), DMA_TO_DEVICE); -+ dma_sync_single_for_device(nss_ctx->dev, n2h_hlos_index_to_dma(mem_ctx->if_map_dma, qid), -+ sizeof(uint32_t), DMA_TO_DEVICE); - NSS_CORE_DSB(); - - return count; -@@ -1691,11 +1708,12 @@ next: - */ - static void nss_core_init_nss(struct nss_ctx_instance *nss_ctx, struct nss_if_mem_map *if_map) - { -+ struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; - struct nss_top_instance *nss_top; - int ret; - int i; - -- NSS_CORE_DMA_CACHE_MAINT((void *)if_map, sizeof(*if_map), DMA_FROM_DEVICE); -+ dma_sync_single_for_device(nss_ctx->dev, mem_ctx->if_map_dma, sizeof(*if_map), DMA_FROM_DEVICE); - NSS_CORE_DSB(); - - /* -@@ -1762,6 +1780,7 @@ static void nss_core_alloc_paged_buffers(struct nss_ctx_instance *nss_ctx, struc - uint16_t count, int16_t mask, int32_t hlos_index, uint32_t alloc_fail_count, - uint32_t buffer_type, uint32_t buffer_queue, uint32_t stats_index) - { -+ struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; - struct sk_buff *nbuf; - struct page *npage; - struct hlos_h2n_desc_rings *h2n_desc_ring = &nss_ctx->h2n_desc_rings[buffer_queue]; -@@ -1831,7 +1850,9 @@ static void nss_core_alloc_paged_buffers(struct nss_ctx_instance *nss_ctx, struc - /* - * Flush the descriptor - */ -- NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE); -+ dma_sync_single_for_device(nss_ctx->dev, -+ h2n_desc_index_to_dma(if_map, buffer_queue, hlos_index), -+ sizeof(*desc), DMA_TO_DEVICE); - - hlos_index = (hlos_index + 1) & (mask); - count--; -@@ -1845,7 +1866,8 @@ static void nss_core_alloc_paged_buffers(struct nss_ctx_instance *nss_ctx, struc - h2n_desc_ring->hlos_index = hlos_index; - if_map->h2n_hlos_index[buffer_queue] = hlos_index; - -- NSS_CORE_DMA_CACHE_MAINT(&if_map->h2n_hlos_index[buffer_queue], sizeof(uint32_t), DMA_TO_DEVICE); -+ dma_sync_single_for_device(nss_ctx->dev, h2n_hlos_index_to_dma(mem_ctx->if_map_dma, buffer_queue), -+ sizeof(uint32_t), DMA_TO_DEVICE); - NSS_CORE_DSB(); - - NSS_PKT_STATS_INC(&nss_top->stats_drv[stats_index]); -@@ -1858,7 +1880,7 @@ static void nss_core_alloc_paged_buffers(struct nss_ctx_instance *nss_ctx, struc - static void nss_core_alloc_jumbo_mru_buffers(struct nss_ctx_instance *nss_ctx, struct nss_if_mem_map *if_map, - int jumbo_mru, uint16_t count, int16_t mask, int32_t hlos_index) - { -- -+ struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; - struct sk_buff *nbuf; - struct hlos_h2n_desc_rings *h2n_desc_ring = &nss_ctx->h2n_desc_rings[NSS_IF_H2N_EMPTY_BUFFER_QUEUE]; - struct h2n_desc_if_instance *desc_if = &h2n_desc_ring->desc_ring; -@@ -1905,7 +1927,9 @@ static void nss_core_alloc_jumbo_mru_buffers(struct nss_ctx_instance *nss_ctx, s - /* - * Flush the descriptor - */ -- NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE); -+ dma_sync_single_for_device(nss_ctx->dev, -+ h2n_desc_index_to_dma(if_map, NSS_IF_H2N_EMPTY_BUFFER_QUEUE, hlos_index), -+ sizeof(*desc), DMA_TO_DEVICE); - - hlos_index = (hlos_index + 1) & (mask); - count--; -@@ -1919,7 +1943,8 @@ static void nss_core_alloc_jumbo_mru_buffers(struct nss_ctx_instance *nss_ctx, s - h2n_desc_ring->hlos_index = hlos_index; - if_map->h2n_hlos_index[NSS_IF_H2N_EMPTY_BUFFER_QUEUE] = hlos_index; - -- NSS_CORE_DMA_CACHE_MAINT(&if_map->h2n_hlos_index[NSS_IF_H2N_EMPTY_BUFFER_QUEUE], sizeof(uint32_t), DMA_TO_DEVICE); -+ dma_sync_single_for_device(nss_ctx->dev, h2n_hlos_index_to_dma(mem_ctx->if_map_dma, NSS_IF_H2N_EMPTY_BUFFER_QUEUE), -+ sizeof(uint32_t), DMA_TO_DEVICE); - NSS_CORE_DSB(); - - NSS_PKT_STATS_INC(&nss_top->stats_drv[NSS_DRV_STATS_TX_EMPTY]); -@@ -1932,6 +1957,7 @@ static void nss_core_alloc_jumbo_mru_buffers(struct nss_ctx_instance *nss_ctx, s - static void nss_core_alloc_max_avail_size_buffers(struct nss_ctx_instance *nss_ctx, struct nss_if_mem_map *if_map, - uint16_t max_buf_size, uint16_t count, int16_t mask, int32_t hlos_index) - { -+ struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; - struct hlos_h2n_desc_rings *h2n_desc_ring = &nss_ctx->h2n_desc_rings[NSS_IF_H2N_EMPTY_BUFFER_QUEUE]; - struct h2n_desc_if_instance *desc_if = &h2n_desc_ring->desc_ring; - struct h2n_descriptor *desc_ring = desc_if->desc; -@@ -1939,6 +1965,7 @@ static void nss_core_alloc_max_avail_size_buffers(struct nss_ctx_instance *nss_c - uint16_t payload_len = max_buf_size + NET_SKB_PAD; - uint16_t start = hlos_index; - uint16_t prev_hlos_index; -+ int dma_size; - - while (count) { - dma_addr_t buffer; -@@ -1991,13 +2018,26 @@ static void nss_core_alloc_max_avail_size_buffers(struct nss_ctx_instance *nss_c - * Flush the descriptors, including the descriptor at prev_hlos_index. - */ - if (prev_hlos_index > start) { -- dmac_clean_range((void *)&desc_ring[start], (void *)&desc_ring[prev_hlos_index] + sizeof(struct h2n_descriptor)); -+ dma_size = sizeof(struct h2n_descriptor) * (prev_hlos_index - start + 1); -+ -+ dma_sync_single_for_device(nss_ctx->dev, -+ h2n_desc_index_to_dma(if_map, NSS_IF_H2N_EMPTY_BUFFER_QUEUE, start), -+ dma_size, DMA_TO_DEVICE); - } else { - /* - * We have wrapped around - */ -- dmac_clean_range((void *)&desc_ring[start], (void *)&desc_ring[mask] + sizeof(struct h2n_descriptor)); -- dmac_clean_range((void *)&desc_ring[0], (void *)&desc_ring[prev_hlos_index] + sizeof(struct h2n_descriptor)); -+ dma_size = sizeof(struct h2n_descriptor) * (mask - start + 1); -+ -+ dma_sync_single_for_device(nss_ctx->dev, -+ h2n_desc_index_to_dma(if_map, NSS_IF_H2N_EMPTY_BUFFER_QUEUE, start), -+ dma_size, DMA_TO_DEVICE); -+ -+ dma_size = sizeof(struct h2n_descriptor) * (prev_hlos_index + 1); -+ -+ dma_sync_single_for_device(nss_ctx->dev, -+ h2n_desc_index_to_dma(if_map, NSS_IF_H2N_EMPTY_BUFFER_QUEUE, 0), -+ dma_size, DMA_TO_DEVICE); - } - - /* -@@ -2008,7 +2048,8 @@ static void nss_core_alloc_max_avail_size_buffers(struct nss_ctx_instance *nss_c - h2n_desc_ring->hlos_index = hlos_index; - if_map->h2n_hlos_index[NSS_IF_H2N_EMPTY_BUFFER_QUEUE] = hlos_index; - -- NSS_CORE_DMA_CACHE_MAINT(&if_map->h2n_hlos_index[NSS_IF_H2N_EMPTY_BUFFER_QUEUE], sizeof(uint32_t), DMA_TO_DEVICE); -+ dma_sync_single_for_device(nss_ctx->dev, h2n_hlos_index_to_dma(mem_ctx->if_map_dma, NSS_IF_H2N_EMPTY_BUFFER_QUEUE), -+ sizeof(uint32_t), DMA_TO_DEVICE); - NSS_CORE_DSB(); - - NSS_PKT_STATS_INC(&nss_top->stats_drv[NSS_DRV_STATS_TX_EMPTY]); -@@ -2021,6 +2062,7 @@ static void nss_core_alloc_max_avail_size_buffers(struct nss_ctx_instance *nss_c - static inline void nss_core_handle_empty_buffer_sos(struct nss_ctx_instance *nss_ctx, - struct nss_if_mem_map *if_map, uint16_t max_buf_size) - { -+ struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; - uint16_t count, size, mask; - int32_t nss_index, hlos_index; - struct hlos_h2n_desc_rings *h2n_desc_ring = &nss_ctx->h2n_desc_rings[NSS_IF_H2N_EMPTY_BUFFER_QUEUE]; -@@ -2031,7 +2073,8 @@ static inline void nss_core_handle_empty_buffer_sos(struct nss_ctx_instance *nss - /* - * Check how many empty buffers could be filled in queue - */ -- NSS_CORE_DMA_CACHE_MAINT(&if_map->h2n_nss_index[NSS_IF_H2N_EMPTY_BUFFER_QUEUE], sizeof(uint32_t), DMA_FROM_DEVICE); -+ dma_sync_single_for_device(nss_ctx->dev, h2n_nss_index_to_dma(mem_ctx->if_map_dma, NSS_IF_H2N_EMPTY_BUFFER_QUEUE), -+ sizeof(uint32_t), DMA_FROM_DEVICE); - NSS_CORE_DSB(); - nss_index = if_map->h2n_nss_index[NSS_IF_H2N_EMPTY_BUFFER_QUEUE]; - -@@ -2076,6 +2119,7 @@ static inline void nss_core_handle_empty_buffer_sos(struct nss_ctx_instance *nss - static inline void nss_core_handle_paged_empty_buffer_sos(struct nss_ctx_instance *nss_ctx, - struct nss_if_mem_map *if_map, uint16_t max_buf_size) - { -+ struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; - uint16_t count, size, mask; - int32_t nss_index, hlos_index; - struct hlos_h2n_desc_rings *h2n_desc_ring = &nss_ctx->h2n_desc_rings[NSS_IF_H2N_EMPTY_PAGED_BUFFER_QUEUE]; -@@ -2083,7 +2127,8 @@ static inline void nss_core_handle_paged_empty_buffer_sos(struct nss_ctx_instanc - /* - * Check how many empty buffers could be filled in queue - */ -- NSS_CORE_DMA_CACHE_MAINT((void *)&if_map->h2n_nss_index[NSS_IF_H2N_EMPTY_PAGED_BUFFER_QUEUE], sizeof(uint32_t), DMA_FROM_DEVICE); -+ dma_sync_single_for_device(nss_ctx->dev, h2n_nss_index_to_dma(mem_ctx->if_map_dma, NSS_IF_H2N_EMPTY_PAGED_BUFFER_QUEUE), -+ sizeof(uint32_t), DMA_FROM_DEVICE); - NSS_CORE_DSB(); - nss_index = if_map->h2n_nss_index[NSS_IF_H2N_EMPTY_PAGED_BUFFER_QUEUE]; - -@@ -2651,9 +2696,11 @@ void nss_skb_reuse(struct sk_buff *nbuf) - * Sends one skb to NSS FW - */ - static inline int32_t nss_core_send_buffer_simple_skb(struct nss_ctx_instance *nss_ctx, -- struct h2n_desc_if_instance *desc_if, uint32_t if_num, -- struct sk_buff *nbuf, uint16_t hlos_index, uint16_t flags, uint8_t buffer_type, uint16_t mss) -+ struct h2n_desc_if_instance *desc_if, uint32_t if_num, struct sk_buff *nbuf, -+ uint16_t qid, uint16_t hlos_index, uint16_t flags, uint8_t buffer_type, uint16_t mss) - { -+ struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; -+ struct nss_if_mem_map *if_map = mem_ctx->if_map; - struct h2n_descriptor *desc_ring = desc_if->desc; - struct h2n_descriptor *desc; - uint16_t bit_flags; -@@ -2707,7 +2754,8 @@ static inline int32_t nss_core_send_buffer_simple_skb(struct nss_ctx_instance *n - (nss_ptr_t)nbuf, (uint16_t)(nbuf->data - nbuf->head), nbuf->len, - sz, (uint32_t)nbuf->priority, mss, bit_flags); - -- NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE); -+ dma_sync_single_for_device(nss_ctx->dev, h2n_desc_index_to_dma(if_map, qid, hlos_index), -+ sizeof(*desc), DMA_TO_DEVICE); - - /* - * We are done using the skb fields and can reuse it now -@@ -2731,7 +2779,8 @@ no_reuse: - (nss_ptr_t)nbuf, (uint16_t)(nbuf->data - nbuf->head), nbuf->len, - (uint16_t)skb_end_offset(nbuf), (uint32_t)nbuf->priority, mss, bit_flags); - -- NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE); -+ dma_sync_single_for_device(nss_ctx->dev, h2n_desc_index_to_dma(if_map, qid, hlos_index), -+ sizeof(*desc), DMA_TO_DEVICE); - - NSS_PKT_STATS_INC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_TX_SIMPLE]); - return 1; -@@ -2745,9 +2794,11 @@ no_reuse: - * Used to differentiate from FRAGLIST - */ - static inline int32_t nss_core_send_buffer_nr_frags(struct nss_ctx_instance *nss_ctx, -- struct h2n_desc_if_instance *desc_if, uint32_t if_num, -- struct sk_buff *nbuf, uint16_t hlos_index, uint16_t flags, uint8_t buffer_type, uint16_t mss) -+ struct h2n_desc_if_instance *desc_if, uint32_t if_num, struct sk_buff *nbuf, -+ uint16_t qid, uint16_t hlos_index, uint16_t flags, uint8_t buffer_type, uint16_t mss) - { -+ struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; -+ struct nss_if_mem_map *if_map = mem_ctx->if_map; - struct h2n_descriptor *desc_ring = desc_if->desc; - struct h2n_descriptor *desc; - const skb_frag_t *frag; -@@ -2787,7 +2838,8 @@ static inline int32_t nss_core_send_buffer_nr_frags(struct nss_ctx_instance *nss - (nss_ptr_t)NULL, nbuf->data - nbuf->head, nbuf->len - nbuf->data_len, - skb_end_offset(nbuf), (uint32_t)nbuf->priority, mss, bit_flags | H2N_BIT_FLAG_FIRST_SEGMENT); - -- NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE); -+ dma_sync_single_for_device(nss_ctx->dev, h2n_desc_index_to_dma(if_map, qid, hlos_index), -+ sizeof(*desc), DMA_TO_DEVICE); - - /* - * Now handle rest of the fragments. -@@ -2811,7 +2863,8 @@ static inline int32_t nss_core_send_buffer_nr_frags(struct nss_ctx_instance *nss - (nss_ptr_t)NULL, 0, skb_frag_size(frag), skb_frag_size(frag), - nbuf->priority, mss, bit_flags); - -- NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE); -+ dma_sync_single_for_device(nss_ctx->dev, h2n_desc_index_to_dma(if_map, qid, hlos_index), -+ sizeof(*desc), DMA_TO_DEVICE); - } - - /* -@@ -2827,7 +2880,8 @@ static inline int32_t nss_core_send_buffer_nr_frags(struct nss_ctx_instance *nss - desc->bit_flags &= ~(H2N_BIT_FLAG_DISCARD); - desc->opaque = (nss_ptr_t)nbuf; - -- NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE); -+ dma_sync_single_for_device(nss_ctx->dev, h2n_desc_index_to_dma(if_map, qid, hlos_index), -+ sizeof(*desc), DMA_TO_DEVICE); - - NSS_PKT_STATS_INC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_TX_NR_FRAGS]); - return i+1; -@@ -2841,9 +2895,11 @@ static inline int32_t nss_core_send_buffer_nr_frags(struct nss_ctx_instance *nss - * Used to differentiate from FRAGS - */ - static inline int32_t nss_core_send_buffer_fraglist(struct nss_ctx_instance *nss_ctx, -- struct h2n_desc_if_instance *desc_if, uint32_t if_num, -- struct sk_buff *nbuf, uint16_t hlos_index, uint16_t flags, uint8_t buffer_type, uint16_t mss) -+ struct h2n_desc_if_instance *desc_if, uint32_t if_num, struct sk_buff *nbuf, -+ uint16_t qid, uint16_t hlos_index, uint16_t flags, uint8_t buffer_type, uint16_t mss) - { -+ struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx; -+ struct nss_if_mem_map *if_map = mem_ctx->if_map; - struct h2n_descriptor *desc_ring = desc_if->desc; - struct h2n_descriptor *desc; - dma_addr_t buffer; -@@ -2882,7 +2938,8 @@ static inline int32_t nss_core_send_buffer_fraglist(struct nss_ctx_instance *nss - (nss_ptr_t)nbuf, nbuf->data - nbuf->head, nbuf->len - nbuf->data_len, - skb_end_offset(nbuf), (uint32_t)nbuf->priority, mss, bit_flags | H2N_BIT_FLAG_FIRST_SEGMENT); - -- NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE); -+ dma_sync_single_for_device(nss_ctx->dev, h2n_desc_index_to_dma(if_map, qid, hlos_index), -+ sizeof(*desc), DMA_TO_DEVICE); - - /* - * Walk the frag_list in nbuf -@@ -2935,7 +2992,8 @@ static inline int32_t nss_core_send_buffer_fraglist(struct nss_ctx_instance *nss - (nss_ptr_t)iter, iter->data - iter->head, iter->len - iter->data_len, - skb_end_offset(iter), iter->priority, mss, bit_flags); - -- NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE); -+ dma_sync_single_for_device(nss_ctx->dev, h2n_desc_index_to_dma(if_map, qid, hlos_index), -+ sizeof(*desc), DMA_TO_DEVICE); - - i++; - } -@@ -2954,7 +3012,8 @@ static inline int32_t nss_core_send_buffer_fraglist(struct nss_ctx_instance *nss - * Update bit flag for last descriptor. - */ - desc->bit_flags |= H2N_BIT_FLAG_LAST_SEGMENT; -- NSS_CORE_DMA_CACHE_MAINT((void *)desc, sizeof(*desc), DMA_TO_DEVICE); -+ dma_sync_single_for_device(nss_ctx->dev, h2n_desc_index_to_dma(if_map, qid, hlos_index), -+ sizeof(*desc), DMA_TO_DEVICE); - - NSS_PKT_STATS_INC(&nss_ctx->nss_top->stats_drv[NSS_DRV_STATS_TX_FRAGLIST]); - return i+1; -@@ -3025,8 +3084,10 @@ int32_t nss_core_send_buffer(struct nss_ctx_instance *nss_ctx, uint32_t if_num, - * We need to work out if there's sufficent space in our transmit descriptor - * ring to place all the segments of a nbuf. - */ -- NSS_CORE_DMA_CACHE_MAINT((void *)&if_map->h2n_nss_index[qid], sizeof(uint32_t), DMA_FROM_DEVICE); -+ dma_sync_single_for_device(nss_ctx->dev, h2n_nss_index_to_dma(mem_ctx->if_map_dma, qid), -+ sizeof(uint32_t), DMA_FROM_DEVICE); - NSS_CORE_DSB(); -+ - nss_index = if_map->h2n_nss_index[qid]; - h2n_desc_ring->nss_index_local = nss_index; - count = ((nss_index - hlos_index - 1) + size) & (mask); -@@ -3095,13 +3156,13 @@ int32_t nss_core_send_buffer(struct nss_ctx_instance *nss_ctx, uint32_t if_num, - count = 0; - if (likely((segments == 0) || is_bounce)) { - count = nss_core_send_buffer_simple_skb(nss_ctx, desc_if, if_num, -- nbuf, hlos_index, flags, buffer_type, mss); -+ nbuf, qid, hlos_index, flags, buffer_type, mss); - } else if (skb_has_frag_list(nbuf)) { - count = nss_core_send_buffer_fraglist(nss_ctx, desc_if, if_num, -- nbuf, hlos_index, flags, buffer_type, mss); -+ nbuf, qid, hlos_index, flags, buffer_type, mss); - } else { - count = nss_core_send_buffer_nr_frags(nss_ctx, desc_if, if_num, -- nbuf, hlos_index, flags, buffer_type, mss); -+ nbuf, qid, hlos_index, flags, buffer_type, mss); - } - - if (unlikely(count <= 0)) { -@@ -3125,7 +3186,8 @@ int32_t nss_core_send_buffer(struct nss_ctx_instance *nss_ctx, uint32_t if_num, - h2n_desc_ring->hlos_index = hlos_index; - if_map->h2n_hlos_index[qid] = hlos_index; - -- NSS_CORE_DMA_CACHE_MAINT(&if_map->h2n_hlos_index[qid], sizeof(uint32_t), DMA_TO_DEVICE); -+ dma_sync_single_for_device(nss_ctx->dev, h2n_hlos_index_to_dma(mem_ctx->if_map_dma, qid), -+ sizeof(uint32_t), DMA_TO_DEVICE); - NSS_CORE_DSB(); - - #ifdef CONFIG_DEBUG_KMEMLEAK -diff --git a/nss_core.h b/nss_core.h -index d7f62fe..7ddf6ce 100644 ---- a/nss_core.h -+++ b/nss_core.h -@@ -100,31 +100,30 @@ - #endif - - /* -- * Cache operation -+ * DMA Offset helper - */ --#define NSS_CORE_DSB() dsb(sy) --#define NSS_CORE_DMA_CACHE_MAINT(start, size, dir) nss_core_dma_cache_maint(start, size, dir) -+#define n2h_desc_index_offset(_index) sizeof(struct n2h_descriptor) * (_index) -+#define h2n_desc_index_offset(_index) sizeof(struct h2n_descriptor) * (_index) -+ -+#define n2h_desc_index_to_dma(_if_map_addr, _qid, _index) (_if_map_addr)->n2h_desc_if[(_qid)].desc_addr + n2h_desc_index_offset(_index) -+#define h2n_desc_index_to_dma(_if_map_addr, _qid, _index) (_if_map_addr)->h2n_desc_if[(_qid)].desc_addr + h2n_desc_index_offset(_index) -+ -+#define h2n_nss_index_offset offsetof(struct nss_if_mem_map, h2n_nss_index) -+#define n2h_nss_index_offset offsetof(struct nss_if_mem_map, n2h_nss_index) -+#define h2n_hlos_index_offset offsetof(struct nss_if_mem_map, h2n_hlos_index) -+#define n2h_hlos_index_offset offsetof(struct nss_if_mem_map, n2h_hlos_index) -+ -+#define h2n_nss_index_to_dma(_if_map_addr, _index) (_if_map_addr) + h2n_nss_index_offset + (sizeof(uint32_t) * (_index)) -+#define n2h_nss_index_to_dma(_if_map_addr, _index) (_if_map_addr) + n2h_nss_index_offset + (sizeof(uint32_t) * (_index)) -+#define h2n_hlos_index_to_dma(_if_map_addr, _index) (_if_map_addr) + h2n_hlos_index_offset + (sizeof(uint32_t) * (_index)) -+#define n2h_hlos_index_to_dma(_if_map_addr, _index) (_if_map_addr) + n2h_hlos_index_offset + (sizeof(uint32_t) * (_index)) - - /* -- * nss_core_dma_cache_maint() -- * Perform the appropriate cache op based on direction -+ * Cache operation - */ --static inline void nss_core_dma_cache_maint(void *start, uint32_t size, int direction) --{ -- switch (direction) { -- case DMA_FROM_DEVICE:/* invalidate only */ -- dmac_inv_range(start, start + size); -- break; -- case DMA_TO_DEVICE:/* writeback only */ -- dmac_clean_range(start, start + size); -- break; -- case DMA_BIDIRECTIONAL:/* writeback and invalidate */ -- dmac_flush_range(start, start + size); -- break; -- default: -- BUG(); -- } --} -+#define NSS_CORE_DSB() dsb(sy) -+#define NSS_CORE_DMA_CACHE_MAINT(dev, start, size, dir) BUILD_BUG_ON_MSG(1, \ -+ "NSS_CORE_DMA_CACHE_MAINT is deprecated. Fix the code to use correct dma_sync_* API") - - #define NSS_DEVICE_IF_START NSS_PHYSICAL_IF_START - -diff --git a/nss_hal/ipq806x/nss_hal_pvt.c b/nss_hal/ipq806x/nss_hal_pvt.c -index 52d63b0..5375087 100644 ---- a/nss_hal/ipq806x/nss_hal_pvt.c -+++ b/nss_hal/ipq806x/nss_hal_pvt.c -@@ -474,10 +474,9 @@ static struct nss_platform_data *__nss_hal_of_get_pdata(struct platform_device * - /* - * Clear TCM memory used by this core - */ -- for (i = 0; i < resource_size(&res_vphys) ; i += 4) { -+ for (i = 0; i < resource_size(&res_vphys) ; i += 4) - nss_write_32(npd->vmap, i, 0); -- NSS_CORE_DMA_CACHE_MAINT((npd->vmap + i), 4, DMA_TO_DEVICE); -- } -+ - NSS_CORE_DSB(); - - /* -diff --git a/nss_hal/ipq807x/nss_hal_pvt.c b/nss_hal/ipq807x/nss_hal_pvt.c -index bb8f42f..733d7f1 100644 ---- a/nss_hal/ipq807x/nss_hal_pvt.c -+++ b/nss_hal/ipq807x/nss_hal_pvt.c -@@ -256,10 +256,9 @@ static struct nss_platform_data *__nss_hal_of_get_pdata(struct platform_device * - /* - * Clear TCM memory used by this core - */ -- for (i = 0; i < resource_size(&res_vphys) ; i += 4) { -+ for (i = 0; i < resource_size(&res_vphys) ; i += 4) - nss_write_32(npd->vmap, i, 0); -- NSS_CORE_DMA_CACHE_MAINT((npd->vmap + i), 4, DMA_TO_DEVICE); -- } -+ - NSS_CORE_DSB(); - - /* -diff --git a/nss_meminfo.c b/nss_meminfo.c -index 2255eae..d804524 100644 ---- a/nss_meminfo.c -+++ b/nss_meminfo.c -@@ -414,7 +414,6 @@ static bool nss_meminfo_init_block_lists(struct nss_ctx_instance *nss_ctx) - /* - * Flush the updated meminfo request. - */ -- NSS_CORE_DMA_CACHE_MAINT(r, sizeof(struct nss_meminfo_request), DMA_TO_DEVICE); - NSS_CORE_DSB(); - - /* -@@ -538,7 +537,7 @@ static bool nss_meminfo_configure_n2h_h2n_rings(struct nss_ctx_instance *nss_ctx - * Bring a fresh copy of if_map from memory in order to read it correctly. - */ - if_map = mem_ctx->if_map; -- NSS_CORE_DMA_CACHE_MAINT((void *)if_map, sizeof(struct nss_if_mem_map), DMA_FROM_DEVICE); -+ dma_sync_single_for_device(nss_ctx->dev, mem_ctx->if_map_dma, sizeof(struct nss_if_mem_map), DMA_FROM_DEVICE); - NSS_CORE_DSB(); - - if_map->n2h_rings = NSS_N2H_RING_COUNT; -@@ -576,7 +575,7 @@ static bool nss_meminfo_configure_n2h_h2n_rings(struct nss_ctx_instance *nss_ctx - /* - * Flush the updated nss_if_mem_map. - */ -- NSS_CORE_DMA_CACHE_MAINT((void *)if_map, sizeof(struct nss_if_mem_map), DMA_TO_DEVICE); -+ dma_sync_single_for_device(nss_ctx->dev, mem_ctx->if_map_dma, sizeof(struct nss_if_mem_map), DMA_TO_DEVICE); - NSS_CORE_DSB(); - - return true; -diff --git a/nss_profiler.c b/nss_profiler.c -index 5717ac3..aadc7c9 100755 ---- a/nss_profiler.c -+++ b/nss_profiler.c -@@ -199,11 +199,12 @@ EXPORT_SYMBOL(nss_profile_dma_deregister_cb); - struct nss_profile_sdma_ctrl *nss_profile_dma_get_ctrl(struct nss_ctx_instance *nss_ctx) - { - struct nss_profile_sdma_ctrl *ctrl = nss_ctx->meminfo_ctx.sdma_ctrl; -+ int size = offsetof(struct nss_profile_sdma_ctrl, cidx); - if (!ctrl) { - return ctrl; - } - -- dmac_inv_range(ctrl, &ctrl->cidx); -+ dma_sync_single_for_device(nss_ctx->dev, (dma_addr_t) ctrl, size, DMA_FROM_DEVICE); - dsb(sy); - return ctrl; - } --- -2.34.1 - diff --git a/qca/qca-nss-drv/patches/0005-nss-drv-add-support-for-kernel-5.15.patch b/qca/qca-nss-drv/patches/0005-nss-drv-add-support-for-kernel-5.15.patch deleted file mode 100644 index 0995e2a07..000000000 --- a/qca/qca-nss-drv/patches/0005-nss-drv-add-support-for-kernel-5.15.patch +++ /dev/null @@ -1,70 +0,0 @@ -From 6e65f6daecb09463688eaea0a234018a728196b8 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Tue, 5 Apr 2022 18:10:57 +0200 -Subject: [PATCH 5/8] nss-drv: add support for kernel 5.15 - -- Fix coredump panic notifier include change. -- Fix skb ZEROCOPY flag. -- Add skb reuse support for 5.15 kernel version. - -Signed-off-by: Ansuel Smith ---- - nss_core.c | 5 +++-- - nss_coredump.c | 4 ++++ - nss_hal/nss_hal.c | 1 + - 3 files changed, 8 insertions(+), 2 deletions(-) - -diff --git a/nss_core.c b/nss_core.c -index f9e6014..8cd1d4b 100644 ---- a/nss_core.c -+++ b/nss_core.c -@@ -53,7 +53,8 @@ - (((LINUX_VERSION_CODE >= KERNEL_VERSION(3, 18, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 19, 0)))) || \ - (((LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(4, 5, 0)))) || \ - (((LINUX_VERSION_CODE >= KERNEL_VERSION(5, 4, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 5, 0)))) || \ --(((LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 11, 0)))))) -+(((LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 11, 0)))) || \ -+(((LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 16, 0)))))) - #error "Check skb recycle code in this file to match Linux version" - #endif - -@@ -2623,7 +2624,7 @@ static inline bool nss_core_skb_can_reuse(struct nss_ctx_instance *nss_ctx, - if (unlikely(irqs_disabled())) - return false; - -- if (unlikely(skb_shinfo(nbuf)->tx_flags & SKBTX_DEV_ZEROCOPY)) -+ if (unlikely(skb_shinfo(nbuf)->flags & SKBFL_ZEROCOPY_ENABLE)) - return false; - - if (unlikely(skb_is_nonlinear(nbuf))) -diff --git a/nss_coredump.c b/nss_coredump.c -index ecad659..3ecef7e 100644 ---- a/nss_coredump.c -+++ b/nss_coredump.c -@@ -23,7 +23,11 @@ - #include "nss_hal.h" - #include "nss_log.h" - #include -+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 14, 0)) - #include /* for panic_notifier_list */ -+#else -+#include -+#endif - #include /* for time */ - #include "nss_tx_rx_common.h" - -diff --git a/nss_hal/nss_hal.c b/nss_hal/nss_hal.c -index 57974c1..d8c703b 100644 ---- a/nss_hal/nss_hal.c -+++ b/nss_hal/nss_hal.c -@@ -24,6 +24,7 @@ - #include - #include - #include -+#include - - #include "nss_hal.h" - #include "nss_arch.h" --- -2.34.1 - diff --git a/qca/qca-nss-drv/patches/0005-nss-drv-use-standard-skb_skip_tc_classify-instead-of.patch b/qca/qca-nss-drv/patches/0005-nss-drv-use-standard-skb_skip_tc_classify-instead-of.patch deleted file mode 100644 index 6e8b4cdfd..000000000 --- a/qca/qca-nss-drv/patches/0005-nss-drv-use-standard-skb_skip_tc_classify-instead-of.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 4dd701916186803172a9f35e7e982a953613ad55 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Mon, 11 Apr 2022 21:32:41 +0200 -Subject: [PATCH 5/9] nss-drv: use standard skb_skip_tc_classify instead of - custom api - -Use skb_skip_tc_classify to skip classify for packet handled by nss -instead of custom api. - -Signed-off-by: Ansuel Smith ---- - nss_core.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/nss_core.c b/nss_core.c -index f9e6014..6ab8038 100644 ---- a/nss_core.c -+++ b/nss_core.c -@@ -1075,7 +1075,7 @@ static inline void nss_core_set_skb_classify(struct sk_buff *nbuf) - #if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0)) - nbuf->tc_verd = SET_TC_NCLS_NSS(nbuf->tc_verd); - #else -- skb_set_tc_classify_offload(nbuf); -+ skb_skip_tc_classify(nbuf); - #endif - #endif - } --- -2.34.1 - diff --git a/qca/qca-nss-drv/patches/0008-Makefile-modularize-driver-even-more.patch b/qca/qca-nss-drv/patches/0008-Makefile-modularize-driver-even-more.patch deleted file mode 100644 index eb7f27d06..000000000 --- a/qca/qca-nss-drv/patches/0008-Makefile-modularize-driver-even-more.patch +++ /dev/null @@ -1,172 +0,0 @@ -From 895de8e4119afe3cbad2aa81566b1ebcb2b39dcd Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Tue, 17 May 2022 20:23:19 +0200 -Subject: [PATCH] Makefile: modularize driver even more - -Permit to disable even more module. - -Signed-off-by: Ansuel Smith ---- - Makefile | 56 ++++++++++++++++++++++++++++++++--------------- - nss_hal/nss_hal.c | 6 +++++ - nss_init.c | 4 ++++ - 3 files changed, 48 insertions(+), 18 deletions(-) - -diff --git a/Makefile b/Makefile -index f5c4b90..0194dbd 100644 ---- a/Makefile -+++ b/Makefile -@@ -39,35 +39,55 @@ qca-nss-drv-objs := \ - nss_pm.o \ - nss_profiler.o \ - nss_project.o \ -- nss_pppoe.o \ -- nss_pppoe_log.o \ -- nss_pppoe_stats.o \ -- nss_pppoe_strings.o \ - nss_rps.o \ - nss_stats.o \ - nss_strings.o \ - nss_tx_msg_sync.o \ - nss_unaligned.o \ - nss_unaligned_log.o \ -- nss_unaligned_stats.o \ -- nss_virt_if.o \ -- nss_virt_if_stats.o \ -- nss_vlan.o \ -- nss_vlan_log.o \ -- nss_wifi.o \ -- nss_wifi_log.o \ -- nss_wifi_stats.o \ -- nss_wifi_vdev.o \ -- nss_wifili.o \ -- nss_wifili_log.o \ -- nss_wifili_stats.o \ -- nss_wifili_strings.o \ -- nss_wifi_mac_db.o -+ nss_unaligned_stats.o - - # Base NSS data plane/HAL support - qca-nss-drv-objs += nss_data_plane/nss_data_plane_common.o - qca-nss-drv-objs += nss_hal/nss_hal.o - -+ifneq "$(NSS_DRV_PPPOE_ENABLE)" "n" -+ccflags-y += -DNSS_DRV_PPPOE_ENABLE -+qca-nss-drv-objs += \ -+ nss_pppoe.o \ -+ nss_pppoe_log.o \ -+ nss_pppoe_stats.o \ -+ nss_pppoe_strings.o -+endif -+ -+ifneq "$(NSS_DRV_VIRT_IF_ENABLE)" "n" -+ccflags-y += -DNSS_DRV_VIRT_IF_ENABLE -+qca-nss-drv-objs += \ -+ nss_virt_if.o \ -+ nss_virt_if_stats.o -+endif -+ -+ifneq "$(NSS_DRV_VLAN_ENABLE)" "n" -+ccflags-y += -DNSS_DRV_VLAN_ENABLE -+qca-nss-drv-objs += \ -+ nss_vlan.o \ -+ nss_vlan_log.o -+endif -+ -+ifneq "$(NSS_DRV_WIFI_ENABLE)" "n" -+ccflags-y += -DNSS_DRV_WIFI_ENABLE -+qca-nss-drv-objs += \ -+ nss_wifi.o \ -+ nss_wifi_log.o \ -+ nss_wifi_stats.o \ -+ nss_wifi_vdev.o \ -+ nss_wifili.o \ -+ nss_wifili_log.o \ -+ nss_wifili_stats.o \ -+ nss_wifili_strings.o \ -+ nss_wifi_mac_db.o -+endif -+ - ifneq "$(NSS_DRV_BRIDGE_ENABLE)" "n" - ccflags-y += -DNSS_DRV_BRIDGE_ENABLE - qca-nss-drv-objs += \ -diff --git a/nss_hal/nss_hal.c b/nss_hal/nss_hal.c -index 7e9a044..c0051e4 100644 ---- a/nss_hal/nss_hal.c -+++ b/nss_hal/nss_hal.c -@@ -460,10 +460,12 @@ int nss_hal_probe(struct platform_device *nss_dev) - } - #endif - -+#ifdef NSS_DRV_PPPOE_ENABLE - if (npd->pppoe_enabled == NSS_FEATURE_ENABLED) { - nss_top->pppoe_handler_id = nss_dev->id; - nss_pppoe_register_handler(); - } -+#endif - - #ifdef NSS_DRV_PPE_ENABLE - if (npd->ppe_enabled == NSS_FEATURE_ENABLED) { -@@ -558,6 +560,7 @@ int nss_hal_probe(struct platform_device *nss_dev) - } - #endif - -+#ifdef NSS_DRV_WIFI_ENABLE - if (npd->wifioffload_enabled == NSS_FEATURE_ENABLED) { - nss_top->wifi_handler_id = nss_dev->id; - nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_VAP] = nss_dev->id; -@@ -585,6 +588,7 @@ int nss_hal_probe(struct platform_device *nss_dev) - */ - nss_wifili_thread_scheme_db_init(nss_dev->id); - } -+#endif - - #ifdef NSS_DRV_OAM_ENABLE - if (npd->oam_enabled == NSS_FEATURE_ENABLED) { -@@ -601,11 +605,13 @@ int nss_hal_probe(struct platform_device *nss_dev) - } - #endif - -+#ifdef NSS_DRV_VLAN_ENABLE - if (npd->vlan_enabled == NSS_FEATURE_ENABLED) { - nss_top->vlan_handler_id = nss_dev->id; - nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_VLAN] = nss_dev->id; - nss_vlan_register_handler(); - } -+#endif - - #ifdef NSS_DRV_QVPN_ENABLE - #if defined(NSS_HAL_IPQ807x_SUPPORT) || defined(NSS_HAL_IPQ60XX_SUPPORT) -diff --git a/nss_init.c b/nss_init.c -index ebd2a12..40e9351 100644 ---- a/nss_init.c -+++ b/nss_init.c -@@ -775,10 +775,12 @@ static int __init nss_init(void) - */ - nss_project_register_sysctl(); - -+#ifdef NSS_DRV_PPPOE_ENABLE - /* - * Registering sysctl for pppoe specific config. - */ - nss_pppoe_register_sysctl(); -+#endif - - /* - * Setup Runtime Sample values -@@ -913,10 +915,12 @@ static void __exit nss_cleanup(void) - nss_c2c_tx_unregister_sysctl(); - #endif - -+#ifdef NSS_DRV_PPPOE_ENABLE - /* - * Unregister pppoe specific sysctl - */ - nss_pppoe_unregister_sysctl(); -+#endif - - /* - * Unregister ipv4/6 specific sysctl and free allocated to connection tables --- -2.34.1 - diff --git a/qca/qca-nss-ecm/Makefile b/qca/qca-nss-ecm/Makefile deleted file mode 100644 index ceedc1988..000000000 --- a/qca/qca-nss-ecm/Makefile +++ /dev/null @@ -1,97 +0,0 @@ -include $(TOPDIR)/rules.mk - -PKG_NAME:=qca-nss-ecm -PKG_RELEASE:=$(AUTORELEASE) - -PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/qca-nss-ecm.git -PKG_SOURCE_PROTO:=git -PKG_SOURCE_DATE:=2021-06-15 -PKG_SOURCE_VERSION:=34267065855d32f33264dc3054efb0e8103d627b -PKG_MIRROR_HASH:=0917659d69c5f3e6067d6671b9393b4b2d6b6cd5a7bacf5e7d6cf842dc906eca - -PKG_BUILD_PARALLEL:=1 - -include $(INCLUDE_DIR)/kernel.mk -include $(INCLUDE_DIR)/package.mk - -define KernelPackage/qca-nss-ecm - SECTION:=kernel - CATEGORY:=Kernel modules - SUBMENU:=Network Support - DEPENDS:=@LINUX_5_10 @(TARGET_ipq807x||TARGET_ipq60xx) \ - +kmod-qca-nss-drv \ - +iptables-mod-extra \ - +kmod-ipt-conntrack \ - +kmod-ipt-physdev \ - +iptables-mod-physdev \ - +kmod-ppp \ - +kmod-pppoe - TITLE:=QCA NSS Enhanced Connection Manager (ECM) - FILES:=$(PKG_BUILD_DIR)/*.ko - KCONFIG:=CONFIG_BRIDGE_NETFILTER=y \ - CONFIG_NF_CONNTRACK_EVENTS=y \ - CONFIG_NF_CONNTRACK_CHAIN_EVENTS=n \ - CONFIG_NF_CONNTRACK_DSCPREMARK_EXT=n -endef - -define KernelPackage/qca-nss-ecm/Description -This package contains the QCA NSS Enhanced Connection Manager -endef - -define KernelPackage/qca-nss-ecm/install - $(INSTALL_DIR) $(1)/etc/firewall.d $(1)/etc/init.d $(1)/usr/bin $(1)/lib/netifd/offload $(1)/etc/config $(1)/etc/uci-defaults $(1)/etc/sysctl.d - $(INSTALL_DATA) ./files/qca-nss-ecm.firewall $(1)/etc/firewall.d/qca-nss-ecm - $(INSTALL_BIN) ./files/qca-nss-ecm.init $(1)/etc/init.d/qca-nss-ecm - $(INSTALL_BIN) ./files/ecm_dump.sh $(1)/usr/bin/ - $(INSTALL_BIN) ./files/on-demand-down $(1)/lib/netifd/offload/on-demand-down - $(INSTALL_DATA) ./files/qca-nss-ecm.uci $(1)/etc/config/ecm - $(INSTALL_DATA) ./files/qca-nss-ecm.defaults $(1)/etc/uci-defaults/99-qca-nss-ecm - $(INSTALL_BIN) ./files/qca-nss-ecm.sysctl $(1)/etc/sysctl.d/qca-nss-ecm.conf - echo 'net.netfilter.nf_conntrack_max=8192' >> $(1)/etc/sysctl.d/qca-nss-ecm.conf -endef - -EXTRA_CFLAGS+=-I$(STAGING_DIR)/usr/include/qca-nss-drv - -ifneq (, $(findstring $(CONFIG_TARGET_BOARD), "ipq807x" "ipq60xx")) -ECM_MAKE_OPTS+= ECM_FRONT_END_NSS_ENABLE=y \ - ECM_CLASSIFIER_HYFI_ENABLE=n \ - ECM_MULTICAST_ENABLE=n \ - ECM_INTERFACE_IPSEC_ENABLE=n \ - ECM_INTERFACE_PPTP_ENABLE=n \ - ECM_INTERFACE_L2TPV2_ENABLE=n \ - ECM_INTERFACE_GRE_TAP_ENABLE=n \ - ECM_INTERFACE_GRE_TUN_ENABLE=n \ - ECM_INTERFACE_SIT_ENABLE=n \ - ECM_INTERFACE_TUNIPIP6_ENABLE=n \ - ECM_INTERFACE_RAWIP_ENABLE=n \ - ECM_INTERFACE_VLAN_ENABLE=n \ - ECM_CLASSIFIER_MARK_ENABLE=n \ - ECM_CLASSIFIER_DSCP_ENABLE=n \ - ECM_CLASSIFIER_PCC_ENABLE=n \ - ECM_BAND_STEERING_ENABLE=n \ - ECM_INTERFACE_PPPOE_ENABLE=y -endif - -ifeq ($(CONFIG_TARGET_BOARD), "ipq807x") - SOC="ipq807x_64" -else ifeq ($(CONFIG_TARGET_BOARD), "ipq60xx") - SOC="ipq60xx_64" -endif - -define Build/InstallDev - mkdir -p $(1)/usr/include/qca-nss-ecm - $(CP) $(PKG_BUILD_DIR)/exports/* $(1)/usr/include/qca-nss-ecm -endef - -define Build/Compile - +$(MAKE) -C "$(LINUX_DIR)" $(strip $(ECM_MAKE_OPTS)) \ - CROSS_COMPILE="$(TARGET_CROSS)" \ - ARCH="$(LINUX_KARCH)" \ - M="$(PKG_BUILD_DIR)" \ - EXTRA_CFLAGS="$(EXTRA_CFLAGS)" SoC=$(SOC) \ - $(KERNEL_MAKE_FLAGS) \ - $(PKG_JOBS) \ - modules -endef - -$(eval $(call KernelPackage,qca-nss-ecm)) diff --git a/qca/qca-nss-ecm/files/ecm_dump.sh b/qca/qca-nss-ecm/files/ecm_dump.sh deleted file mode 100644 index dbf7de753..000000000 --- a/qca/qca-nss-ecm/files/ecm_dump.sh +++ /dev/null @@ -1,95 +0,0 @@ -#!/bin/sh -# -# Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. -# -# Permission to use, copy, modify, and/or distribute this software for any -# purpose with or without fee is hereby granted, provided that the above -# copyright notice and this permission notice appear in all copies. -# -# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -# - -ECM_MODULE=${1:-ecm_state} -MOUNT_ROOT=/dev/ecm - -# -# usage: ecm_dump.sh [module=ecm_db] -# -# with no parameters, ecm_dump.sh will attempt to mount the -# ecm_db state file and cat its contents. -# -# example with a parameter: ecm_dump.sh ecm_classifier_default -# -# this will cause ecm_dump to attempt to find and mount the state -# file for the ecm_classifier_default module, and if successful -# cat the contents. -# - -# this is one of the state files, which happens to be the -# last module started in ecm -ECM_STATE=/sys/kernel/debug/ecm/ecm_state/state_dev_major - -# tests to see if ECM is up and ready to receive commands. -# returns 0 if ECM is fully up and ready, else 1 -ecm_is_ready() { - if [ ! -e "${ECM_STATE}" ] - then - return 1 - fi - return 0 -} - -# -# module_state_mount(module_name) -# Mounts the state file of the module, if supported -# -module_state_mount() { - local module_name=$1 - local mount_dir=$2 - local state_file="/sys/kernel/debug/ecm/${module_name}/state_dev_major" - - if [ -e "${mount_dir}/${module_name}" ] - then - # already mounted - return 0 - fi - - #echo "Mount state file for $module_name ..." - if [ ! -e "$state_file" ] - then - #echo "... $module_name does not support state" - return 1 - fi - - local major="`cat $state_file`" - #echo "... Mounting state $state_file with major: $major" - mknod "${mount_dir}/${module_name}" c $major 0 -} - -# -# main -# -ecm_is_ready || { - #echo "ECM is not running" - exit 1 -} - -# all state files are mounted under MOUNT_ROOT, so make sure it exists -mkdir -p ${MOUNT_ROOT} - -# -# attempt to mount state files for the requested module and cat it -# if the mount succeeded -# -module_state_mount ${ECM_MODULE} ${MOUNT_ROOT} && { - cat ${MOUNT_ROOT}/${ECM_MODULE} - exit 0 -} - -exit 2 diff --git a/qca/qca-nss-ecm/files/on-demand-down b/qca/qca-nss-ecm/files/on-demand-down deleted file mode 100644 index 02d708e03..000000000 --- a/qca/qca-nss-ecm/files/on-demand-down +++ /dev/null @@ -1,6 +0,0 @@ -#!/bin/sh -# Copyright (c) 2016 The Linux Foundation. All rights reserved. - -[ -e "/sys/kernel/debug/ecm/ecm_db/defunct_all" ] && { - echo 1 > /sys/kernel/debug/ecm/ecm_db/defunct_all -} diff --git a/qca/qca-nss-ecm/files/qca-nss-ecm.defaults b/qca/qca-nss-ecm/files/qca-nss-ecm.defaults deleted file mode 100644 index 308e265c9..000000000 --- a/qca/qca-nss-ecm/files/qca-nss-ecm.defaults +++ /dev/null @@ -1,28 +0,0 @@ -#!/bin/sh -# -# Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. -# -# Permission to use, copy, modify, and/or distribute this software for any -# purpose with or without fee is hereby granted, provided that the above -# copyright notice and this permission notice appear in all copies. -# -# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -# - -uci -q batch << EOF - delete firewall.qcanssecm - set firewall.qcanssecm=include - set firewall.qcanssecm.type=script - set firewall.qcanssecm.path=/etc/firewall.d/qca-nss-ecm - set firewall.qcanssecm.family=any - set firewall.qcanssecm.reload=1 - commit firewall -EOF - -exit 0 diff --git a/qca/qca-nss-ecm/files/qca-nss-ecm.firewall b/qca/qca-nss-ecm/files/qca-nss-ecm.firewall deleted file mode 100644 index 24c64def2..000000000 --- a/qca/qca-nss-ecm/files/qca-nss-ecm.firewall +++ /dev/null @@ -1,18 +0,0 @@ -#!/bin/sh -# -# Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. -# -# Permission to use, copy, modify, and/or distribute this software for any -# purpose with or without fee is hereby granted, provided that the above -# copyright notice and this permission notice appear in all copies. -# -# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -# - -iptables -A FORWARD -m physdev --physdev-is-bridged -j ACCEPT diff --git a/qca/qca-nss-ecm/files/qca-nss-ecm.init b/qca/qca-nss-ecm/files/qca-nss-ecm.init deleted file mode 100644 index e64f077bb..000000000 --- a/qca/qca-nss-ecm/files/qca-nss-ecm.init +++ /dev/null @@ -1,142 +0,0 @@ -#!/bin/sh /etc/rc.common -# -# Copyright (c) 2014, 2019-2020 The Linux Foundation. All rights reserved. -# -# Permission to use, copy, modify, and/or distribute this software for any -# purpose with or without fee is hereby granted, provided that the above -# copyright notice and this permission notice appear in all copies. -# -# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - -# The shebang above has an extra space intentially to avoid having -# openwrt build scripts automatically enable this package starting -# at boot. - -START=19 - -get_front_end_mode() { - config_load "ecm" - config_get front_end global acceleration_engine "auto" - - case $front_end in - auto) - echo '0' - ;; - nss) - echo '1' - ;; - sfe) - echo '2' - ;; - *) - echo 'uci_option_acceleration_engine is invalid' - esac -} - -support_bridge() { - #NSS support bridge acceleration - [ -d /sys/kernel/debug/ecm/ecm_nss_ipv4 ] && return 0 - #SFE doesn't support bridge acceleration - [ -d /sys/kernel/debug/ecm/ecm_sfe_ipv4 ] && return 1 -} - -load_sfe() { - local kernel_version=$(uname -r) - - [ -e "/lib/modules/$kernel_version/shortcut-fe.ko" ] && { - [ -d /sys/module/shortcut_fe ] || insmod shortcut-fe - } - - [ -e "/lib/modules/$kernel_version/shortcut-fe-ipv6.ko" ] && { - [ -d /sys/module/shortcut_fe_ipv6 ] || insmod shortcut-fe-ipv6 - } - - [ -e "/lib/modules/$kernel_version/shortcut-fe-drv.ko" ] && { - [ -d /sys/module/shortcut_fe_drv ] || insmod shortcut-fe-drv - } -} - -load_ecm() { - [ -d /sys/module/ecm ] || { - [ ! -e /proc/device-tree/MP_256 ] && load_sfe - insmod ecm front_end_selection=$(get_front_end_mode) - } - - support_bridge && { - sysctl -w net.bridge.bridge-nf-call-ip6tables=1 - sysctl -w net.bridge.bridge-nf-call-iptables=1 - } -} - -unload_ecm() { - sysctl -w net.bridge.bridge-nf-call-ip6tables=0 - sysctl -w net.bridge.bridge-nf-call-iptables=0 - - if [ -d /sys/module/ecm ]; then - # - # Stop ECM frontends - # - echo 1 > /sys/kernel/debug/ecm/front_end_ipv4_stop - echo 1 > /sys/kernel/debug/ecm/front_end_ipv6_stop - - # - # Defunct the connections - # - echo 1 > /sys/kernel/debug/ecm/ecm_db/defunct_all - sleep 5; - - rmmod ecm - sleep 1 - fi -} - -start() { - # If SFE CM is loaded, return. - if [ -d /sys/module/shortcut_fe_cm ]; then - echo "shortcut_fe CM is loaded, unload it first" - echo "cmd: /etc/init.d/shortcut_fe stop" - return - fi - - load_ecm - - # If the acceleration engine is NSS, enable wifi redirect. - [ -d /sys/kernel/debug/ecm/ecm_nss_ipv4 ] && sysctl -w dev.nss.general.redirect=1 - - support_bridge && { - if ([ -z "$(grep "net.bridge.bridge-nf-call-ip6tables=1" /etc/sysctl.d/qca-nss-ecm.conf)" ] && [ -z "$(grep "net.bridge.bridge-nf-call-iptables=1" /etc/sysctl.d/qca-nss-ecm.conf)" ]); then - echo 'net.bridge.bridge-nf-call-ip6tables=1' >> /etc/sysctl.d/qca-nss-ecm.conf - echo 'net.bridge.bridge-nf-call-iptables=1' >> /etc/sysctl.d/qca-nss-ecm.conf - fi - } - - if [ -d /sys/module/qca_ovsmgr ]; then - insmod ecm_ovs - fi - -} - -stop() { - # If ECM is already not loaded, just return. - if [ ! -d /sys/module/ecm ]; then - return - fi - - # If the acceleration engine is NSS, disable wifi redirect. - [ -d /sys/kernel/debug/ecm/ecm_nss_ipv4 ] && sysctl -w dev.nss.general.redirect=0 - - sed '/net.bridge.bridge-nf-call-ip6tables=1/d' -i /etc/sysctl.d/qca-nss-ecm.conf - sed '/net.bridge.bridge-nf-call-iptables=1/d' -i /etc/sysctl.d/qca-nss-ecm.conf - - if [ -d /sys/module/ecm_ovs ]; then - rmmod ecm_ovs - fi - - unload_ecm -} diff --git a/qca/qca-nss-ecm/files/qca-nss-ecm.sysctl b/qca/qca-nss-ecm/files/qca-nss-ecm.sysctl deleted file mode 100644 index 1a3d76b18..000000000 --- a/qca/qca-nss-ecm/files/qca-nss-ecm.sysctl +++ /dev/null @@ -1,2 +0,0 @@ -# nf_conntrack_tcp_no_window_check is 0 by default, set it to 1 -net.netfilter.nf_conntrack_tcp_no_window_check=1 diff --git a/qca/qca-nss-ecm/files/qca-nss-ecm.uci b/qca/qca-nss-ecm/files/qca-nss-ecm.uci deleted file mode 100644 index 4f2de6877..000000000 --- a/qca/qca-nss-ecm/files/qca-nss-ecm.uci +++ /dev/null @@ -1,2 +0,0 @@ -config ecm 'global' - option acceleration_engine 'auto' diff --git a/qca/qca-nss-ecm/patches/001-treewide-componentize-the-module-even-more.patch b/qca/qca-nss-ecm/patches/001-treewide-componentize-the-module-even-more.patch deleted file mode 100644 index 4e7932c9d..000000000 --- a/qca/qca-nss-ecm/patches/001-treewide-componentize-the-module-even-more.patch +++ /dev/null @@ -1,335 +0,0 @@ -From 73345c87b28a473b35b57e673f8de963c3d73da1 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Wed, 19 May 2021 02:38:53 +0200 -Subject: [PATCH] treewide: componentize the module even more - -Signed-off-by: Ansuel Smith ---- - Makefile | 56 +++++++++++++++++++++++++------- - ecm_db/ecm_db_connection.c | 8 +++++ - ecm_db/ecm_db_node.c | 4 +++ - ecm_interface.c | 8 +++++ - frontends/ecm_front_end_common.c | 7 ++++ - 5 files changed, 72 insertions(+), 11 deletions(-) - ---- a/Makefile -+++ b/Makefile -@@ -82,10 +82,18 @@ ccflags-$(ECM_INTERFACE_BOND_ENABLE) += - # Define ECM_INTERFACE_PPPOE_ENABLE=y in order - # to enable support for PPPoE acceleration. - # ############################################################################# --ECM_INTERFACE_PPPOE_ENABLE=y -+ifndef $(ECM_INTERFACE_PPPOE_ENABLE) -+ ECM_INTERFACE_PPPOE_ENABLE=y -+endif - ccflags-$(ECM_INTERFACE_PPPOE_ENABLE) += -DECM_INTERFACE_PPPOE_ENABLE - - # ############################################################################# -+# Define ECM_INTERFACE_L2TPV2_PPTP_ENABLE=y in order -+# to enable support for l2tpv2 or PPTP detection. -+# ############################################################################# -+ccflags-$(ECM_INTERFACE_L2TPV2_PPTP_ENABLE) += -DECM_INTERFACE_L2TPV2_PPTP_ENABLE -+ -+# ############################################################################# - # Define ECM_INTERFACE_L2TPV2_ENABLE=y in order - # to enable support for l2tpv2 acceleration. - # ############################################################################# -@@ -118,6 +126,12 @@ ccflags-$(ECM_INTERFACE_PPP_ENABLE) += - - ccflags-$(ECM_INTERFACE_MAP_T_ENABLE) += -DECM_INTERFACE_MAP_T_ENABLE - - # ############################################################################# -+# Define ECM_INTERFACE_GRE_ENABLE=y in order -+# to enable support for GRE detection. -+# ############################################################################# -+ccflags-$(ECM_INTERFACE_GRE_ENABLE) += -DECM_INTERFACE_GRE_ENABLE -+ -+# ############################################################################# - # Define ECM_INTERFACE_GRE_TAP_ENABLE=y in order - # to enable support for GRE TAP interface. - # ############################################################################# -@@ -186,7 +200,9 @@ ccflags-$(ECM_INTERFACE_OVS_BRIDGE_ENABL - # ############################################################################# - # Define ECM_INTERFACE_VLAN_ENABLE=y in order to enable support for VLAN - # ############################################################################# --ECM_INTERFACE_VLAN_ENABLE=y -+ifndef $(ECM_INTERFACE_VLAN_ENABLE) -+ ECM_INTERFACE_VLAN_ENABLE=y -+endif - ccflags-$(ECM_INTERFACE_VLAN_ENABLE) += -DECM_INTERFACE_VLAN_ENABLE - - # ############################################################################# -@@ -228,7 +244,9 @@ ccflags-$(ECM_CLASSIFIER_OVS_ENABLE) += - # ############################################################################# - # Define ECM_CLASSIFIER_MARK_ENABLE=y in order to enable mark classifier. - # ############################################################################# --ECM_CLASSIFIER_MARK_ENABLE=y -+ifndef $(ECM_CLASSIFIER_MARK_ENABLE) -+ ECM_CLASSIFIER_MARK_ENABLE=y -+endif - ecm-$(ECM_CLASSIFIER_MARK_ENABLE) += ecm_classifier_mark.o - ccflags-$(ECM_CLASSIFIER_MARK_ENABLE) += -DECM_CLASSIFIER_MARK_ENABLE - -@@ -247,7 +265,9 @@ ccflags-$(ECM_CLASSIFIER_NL_ENABLE) += - - # ############################################################################# - # Define ECM_CLASSIFIER_DSCP_ENABLE=y in order to enable DSCP classifier. - # ############################################################################# --ECM_CLASSIFIER_DSCP_ENABLE=y -+ifndef $(ECM_CLASSIFIER_DSCP_ENABLE) -+ ECM_CLASSIFIER_DSCP_ENABLE=y -+endif - ecm-$(ECM_CLASSIFIER_DSCP_ENABLE) += ecm_classifier_dscp.o - ccflags-$(ECM_CLASSIFIER_DSCP_ENABLE) += -DECM_CLASSIFIER_DSCP_ENABLE - ccflags-$(ECM_CLASSIFIER_DSCP_IGS) += -DECM_CLASSIFIER_DSCP_IGS -@@ -274,7 +294,9 @@ endif - # the Parental Controls subsystem classifier in ECM. Currently disabled until - # customers require it / if they need to integrate their Parental Controls with it. - # ############################################################################# --ECM_CLASSIFIER_PCC_ENABLE=y -+ifndef $(ECM_CLASSIFIER_PCC_ENABLE) -+ ECM_CLASSIFIER_PCC_ENABLE=y -+endif - ecm-$(ECM_CLASSIFIER_PCC_ENABLE) += ecm_classifier_pcc.o - ccflags-$(ECM_CLASSIFIER_PCC_ENABLE) += -DECM_CLASSIFIER_PCC_ENABLE - -@@ -301,28 +323,36 @@ ccflags-$(ECM_NON_PORTED_SUPPORT_ENABLE) - # ############################################################################# - # Define ECM_STATE_OUTPUT_ENABLE=y to support XML state output - # ############################################################################# --ECM_STATE_OUTPUT_ENABLE=y -+ifndef $(ECM_STATE_OUTPUT_ENABLE) -+ ECM_STATE_OUTPUT_ENABLE=y -+endif - ecm-$(ECM_STATE_OUTPUT_ENABLE) += ecm_state.o - ccflags-$(ECM_STATE_OUTPUT_ENABLE) += -DECM_STATE_OUTPUT_ENABLE - - # ############################################################################# - # Define ECM_DB_ADVANCED_STATS_ENABLE to support XML state output - # ############################################################################# --ECM_DB_ADVANCED_STATS_ENABLE=y -+ifndef $(ECM_DB_ADVANCED_STATS_ENABLE) -+ ECM_DB_ADVANCED_STATS_ENABLE=y -+endif - ccflags-$(ECM_DB_ADVANCED_STATS_ENABLE) += -DECM_DB_ADVANCED_STATS_ENABLE - - # ############################################################################# - # Define ECM_DB_CONNECTION_CROSS_REFERENCING_ENABLE=y in order to enable - # the database to track relationships between objects. - # ############################################################################# --ECM_DB_CONNECTION_CROSS_REFERENCING_ENABLE=y -+ifndef $(ECM_DB_CONNECTION_CROSS_REFERENCING_ENABLE) -+ ECM_DB_CONNECTION_CROSS_REFERENCING_ENABLE=y -+endif - ccflags-$(ECM_DB_CONNECTION_CROSS_REFERENCING_ENABLE) += -DECM_DB_XREF_ENABLE - - # ############################################################################# - # Define ECM_TRACKER_DPI_SUPPORT_ENABLE=y in order to enable support for - # deep packet inspection and tracking of data with the trackers. - # ############################################################################# --ECM_TRACKER_DPI_SUPPORT_ENABLE=y -+ifndef $(ECM_TRACKER_DPI_SUPPORT_ENABLE) -+ ECM_TRACKER_DPI_SUPPORT_ENABLE=y -+endif - ccflags-$(ECM_TRACKER_DPI_SUPPORT_ENABLE) += -DECM_TRACKER_DPI_SUPPORT_ENABLE - - # ############################################################################# -@@ -330,14 +360,18 @@ ccflags-$(ECM_TRACKER_DPI_SUPPORT_ENABLE - # support for the database keeping lists of connections that are assigned - # on a per TYPE of classifier basis. - # ############################################################################# --ECM_DB_CLASSIFIER_TYPE_ASSIGNMENTS_TRACK_ENABLE=y -+ifndef $(ECM_DB_CLASSIFIER_TYPE_ASSIGNMENTS_TRACK_ENABLE) -+ ECM_DB_CLASSIFIER_TYPE_ASSIGNMENTS_TRACK_ENABLE=y -+endif - ccflags-$(ECM_DB_CLASSIFIER_TYPE_ASSIGNMENTS_TRACK_ENABLE) += -DECM_DB_CTA_TRACK_ENABLE - - # ############################################################################# - # Define ECM_BAND_STEERING_ENABLE=y in order to enable - # band steering feature. - # ############################################################################# --ECM_BAND_STEERING_ENABLE=y -+ifndef $(ECM_BAND_STEERING_ENABLE) -+ ECM_BAND_STEERING_ENABLE=y -+endif - ccflags-$(ECM_BAND_STEERING_ENABLE) += -DECM_BAND_STEERING_ENABLE - - # ############################################################################# ---- a/ecm_db/ecm_db_connection.c -+++ b/ecm_db/ecm_db_connection.c -@@ -430,7 +430,9 @@ EXPORT_SYMBOL(ecm_db_connection_make_def - */ - void ecm_db_connection_data_totals_update(struct ecm_db_connection_instance *ci, bool is_from, uint64_t size, uint64_t packets) - { -+#ifdef ECM_DB_ADVANCED_STATS_ENABLE - int32_t i; -+#endif - - DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed\n", ci); - -@@ -529,7 +531,9 @@ EXPORT_SYMBOL(ecm_db_connection_data_tot - */ - void ecm_db_connection_data_totals_update_dropped(struct ecm_db_connection_instance *ci, bool is_from, uint64_t size, uint64_t packets) - { -+#ifdef ECM_DB_ADVANCED_STATS_ENABLE - int32_t i; -+#endif - - DEBUG_CHECK_MAGIC(ci, ECM_DB_CONNECTION_INSTANCE_MAGIC, "%px: magic failed\n", ci); - -@@ -1508,6 +1512,7 @@ void ecm_db_connection_defunct_all(void) - } - EXPORT_SYMBOL(ecm_db_connection_defunct_all); - -+#ifdef ECM_INTERFACE_OVS_BRIDGE_ENABLE - /* - * ecm_db_connection_defunct_by_classifier() - * Make defunct based on masked fields -@@ -1667,6 +1672,7 @@ next_ci: - ECM_IP_ADDR_TO_OCTAL(dest_addr_mask), dest_port_mask, proto_mask, cnt); - } - } -+#endif - - /* - * ecm_db_connection_defunct_by_port() -@@ -1956,6 +1962,7 @@ struct ecm_db_node_instance *ecm_db_conn - } - EXPORT_SYMBOL(ecm_db_connection_node_get_and_ref); - -+#ifdef ECM_DB_XREF_ENABLE - /* - * ecm_db_connection_mapping_get_and_ref_next() - * Return reference to next connection in the mapping chain in the specified direction. -@@ -1997,6 +2004,7 @@ struct ecm_db_connection_instance *ecm_d - return nci; - } - EXPORT_SYMBOL(ecm_db_connection_iface_get_and_ref_next); -+#endif - - /* - * ecm_db_connection_mapping_get_and_ref() ---- a/ecm_db/ecm_db_node.c -+++ b/ecm_db/ecm_db_node.c -@@ -224,9 +224,11 @@ EXPORT_SYMBOL(ecm_db_node_get_and_ref_ne - */ - int ecm_db_node_deref(struct ecm_db_node_instance *ni) - { -+#ifdef ECM_DB_XREF_ENABLE - #if (DEBUG_LEVEL >= 1) - int dir; - #endif -+#endif - DEBUG_CHECK_MAGIC(ni, ECM_DB_NODE_INSTANCE_MAGIC, "%px: magic failed\n", ni); - - spin_lock_bh(&ecm_db_lock); -@@ -486,9 +488,11 @@ EXPORT_SYMBOL(ecm_db_node_iface_get_and_ - void ecm_db_node_add(struct ecm_db_node_instance *ni, struct ecm_db_iface_instance *ii, uint8_t *address, - ecm_db_node_final_callback_t final, void *arg) - { -+#ifdef ECM_DB_XREF_ENABLE - #if (DEBUG_LEVEL >= 1) - int dir; - #endif -+#endif - ecm_db_node_hash_t hash_index; - struct ecm_db_listener_instance *li; - ---- a/ecm_interface.c -+++ b/ecm_interface.c -@@ -1343,6 +1343,7 @@ struct neighbour *ecm_interface_ipv6_nei - */ - bool ecm_interface_is_pptp(struct sk_buff *skb, const struct net_device *out) - { -+#ifdef ECM_INTERFACE_PPTP_ENABLE - struct net_device *in; - - /* -@@ -1367,6 +1368,7 @@ bool ecm_interface_is_pptp(struct sk_buf - } - - dev_put(in); -+#endif - return false; - } - -@@ -1379,6 +1381,7 @@ bool ecm_interface_is_pptp(struct sk_buf - */ - bool ecm_interface_is_l2tp_packet_by_version(struct sk_buff *skb, const struct net_device *out, int ver) - { -+#ifdef ECM_INTERFACE_L2TPV2_PPTP_ENABLE - uint32_t flag = 0; - struct net_device *in; - -@@ -1411,6 +1414,7 @@ bool ecm_interface_is_l2tp_packet_by_ver - } - - dev_put(in); -+#endif - return false; - } - -@@ -1423,6 +1427,7 @@ bool ecm_interface_is_l2tp_packet_by_ver - */ - bool ecm_interface_is_l2tp_pptp(struct sk_buff *skb, const struct net_device *out) - { -+#ifdef ECM_INTERFACE_L2TPV2_PPTP_ENABLE - struct net_device *in; - - /* -@@ -1445,6 +1450,7 @@ bool ecm_interface_is_l2tp_pptp(struct s - } - - dev_put(in); -+#endif - return false; - } - -@@ -6630,6 +6636,7 @@ static void ecm_interface_regenerate_con - return; - } - -+#ifdef ECM_DB_XREF_ENABLE - for (dir = 0; dir < ECM_DB_OBJ_DIR_MAX; dir++) { - /* - * Re-generate all connections associated with this interface -@@ -6645,6 +6652,7 @@ static void ecm_interface_regenerate_con - ci[dir] = cin; - } - } -+#endif - - #ifdef ECM_MULTICAST_ENABLE - /* ---- a/frontends/ecm_front_end_common.c -+++ b/frontends/ecm_front_end_common.c -@@ -106,6 +106,7 @@ bool ecm_front_end_gre_proto_is_accel_al - struct nf_conntrack_tuple *tuple, - int ip_version) - { -+#ifdef ECM_INTERFACE_GRE_ENABLE - struct net_device *dev; - struct gre_base_hdr *greh; - -@@ -117,10 +118,12 @@ bool ecm_front_end_gre_proto_is_accel_al - /* - * Case 1: PPTP locally terminated - */ -+#ifdef ECM_INTERFACE_PPTP_ENABLE - if (ecm_interface_is_pptp(skb, outdev)) { - DEBUG_TRACE("%px: PPTP GRE locally terminated - allow acceleration\n", skb); - return true; - } -+#endif - - /* - * Case 2: PPTP pass through -@@ -223,6 +226,10 @@ bool ecm_front_end_gre_proto_is_accel_al - */ - DEBUG_TRACE("%px: GRE IPv%d pass through - allow acceleration\n", skb, ip_version); - return true; -+#else -+ DEBUG_TRACE("%px: GRE%d feature is disabled - do not allow acceleration\n", skb, ip_version); -+ return false; -+#endif - } - - #ifdef ECM_CLASSIFIER_DSCP_ENABLE diff --git a/qca/qca-nss-ecm/patches/100-kernel-5.10-support.patch b/qca/qca-nss-ecm/patches/100-kernel-5.10-support.patch deleted file mode 100644 index 3729dd3b9..000000000 --- a/qca/qca-nss-ecm/patches/100-kernel-5.10-support.patch +++ /dev/null @@ -1,831 +0,0 @@ -From e8b642c23af9146c973e828a7f4e0fb56cfc8d0b Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Sat, 15 May 2021 03:51:14 +0200 -Subject: [PATCH] add support for kernel 5.10 - -Signed-off-by: Ansuel Smith ---- - ecm_classifier_default.c | 24 +++--------- - ecm_classifier_dscp.c | 8 +--- - ecm_classifier_emesh.c | 16 ++------ - ecm_classifier_hyfi.c | 7 +--- - ecm_classifier_mark.c | 8 +--- - ecm_classifier_ovs.c | 8 +--- - ecm_classifier_pcc.c | 8 +--- - ecm_conntrack_notifier.c | 8 +--- - ecm_db/ecm_db_connection.c | 7 +--- - ecm_db/ecm_db_host.c | 7 +--- - ecm_db/ecm_db_iface.c | 7 +--- - ecm_db/ecm_db_mapping.c | 7 +--- - ecm_db/ecm_db_node.c | 7 +--- - ecm_interface.c | 4 +- - ecm_state.c | 14 ++----- - frontends/ecm_front_end_common.c | 4 +- - frontends/ecm_front_end_ipv4.c | 7 +--- - frontends/ecm_front_end_ipv6.c | 7 +--- - frontends/nss/ecm_nss_bond_notifier.c | 8 +--- - frontends/nss/ecm_nss_ipv4.c | 49 +++++++------------------ - frontends/nss/ecm_nss_ipv6.c | 49 +++++++------------------ - frontends/nss/ecm_nss_multicast_ipv4.c | 7 +--- - frontends/nss/ecm_nss_multicast_ipv6.c | 7 +--- - frontends/nss/ecm_nss_non_ported_ipv4.c | 7 +--- - frontends/nss/ecm_nss_non_ported_ipv6.c | 7 +--- - frontends/nss/ecm_nss_ported_ipv4.c | 8 +--- - frontends/nss/ecm_nss_ported_ipv6.c | 8 +--- - frontends/sfe/ecm_sfe_ipv4.c | 49 +++++++------------------ - frontends/sfe/ecm_sfe_ipv6.c | 49 +++++++------------------ - frontends/sfe/ecm_sfe_non_ported_ipv4.c | 7 +--- - frontends/sfe/ecm_sfe_non_ported_ipv6.c | 7 +--- - frontends/sfe/ecm_sfe_ported_ipv4.c | 8 +--- - frontends/sfe/ecm_sfe_ported_ipv6.c | 8 +--- - 33 files changed, 122 insertions(+), 314 deletions(-) - ---- a/ecm_classifier_default.c -+++ b/ecm_classifier_default.c -@@ -776,26 +776,14 @@ int ecm_classifier_default_init(struct d - return -1; - } - -- if (!debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_default_dentry, -- (u32 *)&ecm_classifier_default_enabled)) { -- DEBUG_ERROR("Failed to create ecm deafult classifier enabled file in debugfs\n"); -- debugfs_remove_recursive(ecm_classifier_default_dentry); -- return -1; -- } -+ debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_default_dentry, -+ (u32 *)&ecm_classifier_default_enabled); - -- if (!debugfs_create_u32("accel_mode", S_IRUGO | S_IWUSR, ecm_classifier_default_dentry, -- (u32 *)&ecm_classifier_default_accel_mode)) { -- DEBUG_ERROR("Failed to create ecm deafult classifier accel_mode file in debugfs\n"); -- debugfs_remove_recursive(ecm_classifier_default_dentry); -- return -1; -- } -+ debugfs_create_u32("accel_mode", S_IRUGO | S_IWUSR, ecm_classifier_default_dentry, -+ (u32 *)&ecm_classifier_default_accel_mode); - -- if (!debugfs_create_u32("accel_delay_pkts", S_IRUGO | S_IWUSR, ecm_classifier_default_dentry, -- (u32 *)&ecm_classifier_accel_delay_pkts)) { -- DEBUG_ERROR("Failed to create accel delay packet counts in debugfs\n"); -- debugfs_remove_recursive(ecm_classifier_default_dentry); -- return -1; -- } -+ debugfs_create_u32("accel_delay_pkts", S_IRUGO | S_IWUSR, ecm_classifier_default_dentry, -+ (u32 *)&ecm_classifier_accel_delay_pkts); - - return 0; - } ---- a/ecm_classifier_dscp.c -+++ b/ecm_classifier_dscp.c -@@ -747,12 +747,8 @@ int ecm_classifier_dscp_init(struct dent - return -1; - } - -- if (!debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_dscp_dentry, -- (u32 *)&ecm_classifier_dscp_enabled)) { -- DEBUG_ERROR("Failed to create dscp enabled file in debugfs\n"); -- debugfs_remove_recursive(ecm_classifier_dscp_dentry); -- return -1; -- } -+ debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_dscp_dentry, -+ (u32 *)&ecm_classifier_dscp_enabled); - - return 0; - } ---- a/ecm_classifier_emesh.c -+++ b/ecm_classifier_emesh.c -@@ -974,19 +974,11 @@ int ecm_classifier_emesh_init(struct den - return -1; - } - -- if (!debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_emesh_dentry, -- (u32 *)&ecm_classifier_emesh_enabled)) { -- DEBUG_ERROR("Failed to create ecm emesh classifier enabled file in debugfs\n"); -- debugfs_remove_recursive(ecm_classifier_emesh_dentry); -- return -1; -- } -+ debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_emesh_dentry, -+ (u32 *)&ecm_classifier_emesh_enabled); - -- if (!debugfs_create_u32("latency_config_enabled", S_IRUGO | S_IWUSR, ecm_classifier_emesh_dentry, -- (u32 *)&ecm_classifier_emesh_latency_config_enabled)) { -- DEBUG_ERROR("Failed to create ecm emesh classifier latency config enabled file in debugfs\n"); -- debugfs_remove_recursive(ecm_classifier_emesh_dentry); -- return -1; -- } -+ debugfs_create_u32("latency_config_enabled", S_IRUGO | S_IWUSR, ecm_classifier_emesh_dentry, -+ (u32 *)&ecm_classifier_emesh_latency_config_enabled); - - /* - * Register for service prioritization notification update. ---- a/ecm_classifier_hyfi.c -+++ b/ecm_classifier_hyfi.c -@@ -1099,11 +1099,8 @@ int ecm_classifier_hyfi_rules_init(struc - goto classifier_task_cleanup; - } - -- if (!debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_hyfi_dentry, -- (u32 *)&ecm_classifier_hyfi_enabled)) { -- DEBUG_ERROR("Failed to create ecm hyfi classifier enabled file in debugfs\n"); -- goto classifier_task_cleanup; -- } -+ debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_hyfi_dentry, -+ (u32 *)&ecm_classifier_hyfi_enabled); - - if (!debugfs_create_file("cmd", S_IWUSR, ecm_classifier_hyfi_dentry, - NULL, &ecm_classifier_hyfi_cmd_fops)) { ---- a/ecm_classifier_mark.c -+++ b/ecm_classifier_mark.c -@@ -753,12 +753,8 @@ int ecm_classifier_mark_init(struct dent - return -1; - } - -- if (!debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_mark_dentry, -- (u32 *)&ecm_classifier_mark_enabled)) { -- DEBUG_ERROR("Failed to create mark enabled file in debugfs\n"); -- debugfs_remove_recursive(ecm_classifier_mark_dentry); -- return -1; -- } -+ debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_mark_dentry, -+ (u32 *)&ecm_classifier_mark_enabled); - - return 0; - } ---- a/ecm_classifier_ovs.c -+++ b/ecm_classifier_ovs.c -@@ -2200,12 +2200,8 @@ int ecm_classifier_ovs_init(struct dentr - return -1; - } - -- if (!debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_ovs_dentry, -- (u32 *)&ecm_classifier_ovs_enabled)) { -- DEBUG_ERROR("Failed to create ovs enabled file in debugfs\n"); -- debugfs_remove_recursive(ecm_classifier_ovs_dentry); -- return -1; -- } -+ debugfs_create_u32("enabled", S_IRUGO | S_IWUSR, ecm_classifier_ovs_dentry, -+ (u32 *)&ecm_classifier_ovs_enabled); - - return 0; - } ---- a/ecm_classifier_pcc.c -+++ b/ecm_classifier_pcc.c -@@ -1308,12 +1308,8 @@ int ecm_classifier_pcc_init(struct dentr - return -1; - } - -- if (!debugfs_create_u32("enabled", S_IRUGO, ecm_classifier_pcc_dentry, -- (u32 *)&ecm_classifier_pcc_enabled)) { -- DEBUG_ERROR("Failed to create pcc enabled file in debugfs\n"); -- debugfs_remove_recursive(ecm_classifier_pcc_dentry); -- return -1; -- } -+ debugfs_create_u32("enabled", S_IRUGO, ecm_classifier_pcc_dentry, -+ (u32 *)&ecm_classifier_pcc_enabled); - - return 0; - } ---- a/ecm_conntrack_notifier.c -+++ b/ecm_conntrack_notifier.c -@@ -414,12 +414,8 @@ int ecm_conntrack_notifier_init(struct d - return -1; - } - -- if (!debugfs_create_u32("stop", S_IRUGO | S_IWUSR, ecm_conntrack_notifier_dentry, -- (u32 *)&ecm_conntrack_notifier_stopped)) { -- DEBUG_ERROR("Failed to create ecm conntrack notifier stopped file in debugfs\n"); -- debugfs_remove_recursive(ecm_conntrack_notifier_dentry); -- return -1; -- } -+ debugfs_create_u32("stop", S_IRUGO | S_IWUSR, ecm_conntrack_notifier_dentry, -+ (u32 *)&ecm_conntrack_notifier_stopped); - - #ifdef CONFIG_NF_CONNTRACK_EVENTS - /* ---- a/ecm_db/ecm_db_connection.c -+++ b/ecm_db/ecm_db_connection.c -@@ -3642,11 +3642,8 @@ static struct file_operations ecm_db_con - */ - bool ecm_db_connection_init(struct dentry *dentry) - { -- if (!debugfs_create_u32("connection_count", S_IRUGO, dentry, -- (u32 *)&ecm_db_connection_count)) { -- DEBUG_ERROR("Failed to create ecm db connection count file in debugfs\n"); -- return false; -- } -+ debugfs_create_u32("connection_count", S_IRUGO, dentry, -+ (u32 *)&ecm_db_connection_count); - - if (!debugfs_create_file("connection_count_simple", S_IRUGO, dentry, - NULL, &ecm_db_connection_count_simple_fops)) { ---- a/ecm_db/ecm_db_host.c -+++ b/ecm_db/ecm_db_host.c -@@ -770,11 +770,8 @@ EXPORT_SYMBOL(ecm_db_host_alloc); - bool ecm_db_host_init(struct dentry *dentry) - { - -- if (!debugfs_create_u32("host_count", S_IRUGO, dentry, -- (u32 *)&ecm_db_host_count)) { -- DEBUG_ERROR("Failed to create ecm db host count file in debugfs\n"); -- return false;; -- } -+ debugfs_create_u32("host_count", S_IRUGO, dentry, -+ (u32 *)&ecm_db_host_count); - - ecm_db_host_table = vzalloc(sizeof(struct ecm_db_host_instance *) * ECM_DB_HOST_HASH_SLOTS); - if (!ecm_db_host_table) { ---- a/ecm_db/ecm_db_iface.c -+++ b/ecm_db/ecm_db_iface.c -@@ -3670,11 +3670,8 @@ EXPORT_SYMBOL(ecm_db_iface_alloc); - */ - bool ecm_db_iface_init(struct dentry *dentry) - { -- if (!debugfs_create_u32("iface_count", S_IRUGO, dentry, -- (u32 *)&ecm_db_iface_count)) { -- DEBUG_ERROR("Failed to create ecm db iface count file in debugfs\n"); -- return false; -- } -+ debugfs_create_u32("iface_count", S_IRUGO, dentry, -+ (u32 *)&ecm_db_iface_count); - - return true; - } ---- a/ecm_db/ecm_db_mapping.c -+++ b/ecm_db/ecm_db_mapping.c -@@ -806,11 +806,8 @@ EXPORT_SYMBOL(ecm_db_mapping_alloc); - */ - bool ecm_db_mapping_init(struct dentry *dentry) - { -- if (!debugfs_create_u32("mapping_count", S_IRUGO, dentry, -- (u32 *)&ecm_db_mapping_count)) { -- DEBUG_ERROR("Failed to create ecm db mapping count file in debugfs\n"); -- return false; -- } -+ debugfs_create_u32("mapping_count", S_IRUGO, dentry, -+ (u32 *)&ecm_db_mapping_count); - - ecm_db_mapping_table = vzalloc(sizeof(struct ecm_db_mapping_instance *) * ECM_DB_MAPPING_HASH_SLOTS); - if (!ecm_db_mapping_table) { ---- a/ecm_db/ecm_db_node.c -+++ b/ecm_db/ecm_db_node.c -@@ -1187,11 +1187,8 @@ keep_sni_conn: - */ - bool ecm_db_node_init(struct dentry *dentry) - { -- if (!debugfs_create_u32("node_count", S_IRUGO, dentry, -- (u32 *)&ecm_db_node_count)) { -- DEBUG_ERROR("Failed to create ecm db node count file in debugfs\n"); -- return false; -- } -+ debugfs_create_u32("node_count", S_IRUGO, dentry, -+ (u32 *)&ecm_db_node_count); - - ecm_db_node_table = vzalloc(sizeof(struct ecm_db_node_instance *) * ECM_DB_NODE_HASH_SLOTS); - if (!ecm_db_node_table) { ---- a/ecm_interface.c -+++ b/ecm_interface.c -@@ -332,7 +332,7 @@ static struct net_device *ecm_interface_ - struct net_device *dev; - - ECM_IP_ADDR_TO_NIN6_ADDR(addr6, addr); -- dev = (struct net_device *)ipv6_dev_find(&init_net, &addr6, 1); -+ dev = (struct net_device *)ipv6_dev_find_and_hold(&init_net, &addr6, 1); - return dev; - } - #endif -@@ -734,7 +734,7 @@ static bool ecm_interface_mac_addr_get_i - * Get the MAC address that corresponds to IP address given. - */ - ECM_IP_ADDR_TO_NIN6_ADDR(daddr, addr); -- local_dev = ipv6_dev_find(&init_net, &daddr, 1); -+ local_dev = ipv6_dev_find_and_hold(&init_net, &daddr, 1); - if (local_dev) { - DEBUG_TRACE("%pi6 is a local address\n", &daddr); - memcpy(mac_addr, dev->dev_addr, ETH_ALEN); ---- a/ecm_state.c -+++ b/ecm_state.c -@@ -899,17 +899,11 @@ int ecm_state_init(struct dentry *dentry - return -1; - } - -- if (!debugfs_create_u32("state_dev_major", S_IRUGO, ecm_state_dentry, -- (u32 *)&ecm_state_dev_major_id)) { -- DEBUG_ERROR("Failed to create ecm state dev major file in debugfs\n"); -- goto init_cleanup; -- } -+ debugfs_create_u32("state_dev_major", S_IRUGO, ecm_state_dentry, -+ (u32 *)&ecm_state_dev_major_id); - -- if (!debugfs_create_u32("state_file_output_mask", S_IRUGO | S_IWUSR, ecm_state_dentry, -- (u32 *)&ecm_state_file_output_mask)) { -- DEBUG_ERROR("Failed to create ecm state output mask file in debugfs\n"); -- goto init_cleanup; -- } -+ debugfs_create_u32("state_file_output_mask", S_IRUGO | S_IWUSR, ecm_state_dentry, -+ (u32 *)&ecm_state_file_output_mask); - - /* - * Register a char device that we will use to provide a dump of our state ---- a/frontends/ecm_front_end_common.c -+++ b/frontends/ecm_front_end_common.c -@@ -192,7 +192,7 @@ bool ecm_front_end_gre_proto_is_accel_al - return false; - } - } else { -- dev = ipv6_dev_find(&init_net, &(tuple->src.u3.in6), 1); -+ dev = ipv6_dev_find_and_hold(&init_net, &(tuple->src.u3.in6), 1); - if (dev) { - /* - * Source IP address is local -@@ -202,7 +202,7 @@ bool ecm_front_end_gre_proto_is_accel_al - return false; - } - -- dev = ipv6_dev_find(&init_net, &(tuple->dst.u3.in6), 1); -+ dev = ipv6_dev_find_and_hold(&init_net, &(tuple->dst.u3.in6), 1); - if (dev) { - /* - * Destination IP address is local ---- a/frontends/ecm_front_end_ipv4.c -+++ b/frontends/ecm_front_end_ipv4.c -@@ -376,11 +376,8 @@ void ecm_front_end_ipv4_stop(int num) - */ - int ecm_front_end_ipv4_init(struct dentry *dentry) - { -- if (!debugfs_create_u32("front_end_ipv4_stop", S_IRUGO | S_IWUSR, dentry, -- (u32 *)&ecm_front_end_ipv4_stopped)) { -- DEBUG_ERROR("Failed to create ecm front end ipv4 stop file in debugfs\n"); -- return -1; -- } -+ debugfs_create_u32("front_end_ipv4_stop", S_IRUGO | S_IWUSR, dentry, -+ (u32 *)&ecm_front_end_ipv4_stopped); - - switch (ecm_front_end_type_get()) { - case ECM_FRONT_END_TYPE_NSS: ---- a/frontends/ecm_front_end_ipv6.c -+++ b/frontends/ecm_front_end_ipv6.c -@@ -255,11 +255,8 @@ void ecm_front_end_ipv6_stop(int num) - */ - int ecm_front_end_ipv6_init(struct dentry *dentry) - { -- if (!debugfs_create_u32("front_end_ipv6_stop", S_IRUGO | S_IWUSR, dentry, -- (u32 *)&ecm_front_end_ipv6_stopped)) { -- DEBUG_ERROR("Failed to create ecm front end ipv6 stop file in debugfs\n"); -- return -1; -- } -+ debugfs_create_u32("front_end_ipv6_stop", S_IRUGO | S_IWUSR, dentry, -+ (u32 *)&ecm_front_end_ipv6_stopped); - - switch (ecm_front_end_type_get()) { - case ECM_FRONT_END_TYPE_NSS: ---- a/frontends/nss/ecm_nss_bond_notifier.c -+++ b/frontends/nss/ecm_nss_bond_notifier.c -@@ -240,12 +240,8 @@ int ecm_nss_bond_notifier_init(struct de - return -1; - } - -- if (!debugfs_create_u32("stop", S_IRUGO | S_IWUSR, ecm_nss_bond_notifier_dentry, -- (u32 *)&ecm_nss_bond_notifier_stopped)) { -- DEBUG_ERROR("Failed to create ecm bond notifier stopped file in debugfs\n"); -- debugfs_remove_recursive(ecm_nss_bond_notifier_dentry); -- return -1; -- } -+ debugfs_create_u32("stop", S_IRUGO | S_IWUSR, ecm_nss_bond_notifier_dentry, -+ (u32 *)&ecm_nss_bond_notifier_stopped); - - /* - * Register Link Aggregation callbacks with the bonding driver ---- a/frontends/nss/ecm_nss_ipv4.c -+++ b/frontends/nss/ecm_nss_ipv4.c -@@ -2802,41 +2802,23 @@ int ecm_nss_ipv4_init(struct dentry *den - return result; - } - -- if (!debugfs_create_u32("no_action_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, -- (u32 *)&ecm_nss_ipv4_no_action_limit_default)) { -- DEBUG_ERROR("Failed to create ecm nss ipv4 no_action_limit_default file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("no_action_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, -+ (u32 *)&ecm_nss_ipv4_no_action_limit_default); - -- if (!debugfs_create_u32("driver_fail_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, -- (u32 *)&ecm_nss_ipv4_driver_fail_limit_default)) { -- DEBUG_ERROR("Failed to create ecm nss ipv4 driver_fail_limit_default file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("driver_fail_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, -+ (u32 *)&ecm_nss_ipv4_driver_fail_limit_default); - -- if (!debugfs_create_u32("nack_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, -- (u32 *)&ecm_nss_ipv4_nack_limit_default)) { -- DEBUG_ERROR("Failed to create ecm nss ipv4 nack_limit_default file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("nack_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, -+ (u32 *)&ecm_nss_ipv4_nack_limit_default); - -- if (!debugfs_create_u32("accelerated_count", S_IRUGO, ecm_nss_ipv4_dentry, -- (u32 *)&ecm_nss_ipv4_accelerated_count)) { -- DEBUG_ERROR("Failed to create ecm nss ipv4 accelerated_count file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("accelerated_count", S_IRUGO, ecm_nss_ipv4_dentry, -+ (u32 *)&ecm_nss_ipv4_accelerated_count); - -- if (!debugfs_create_u32("pending_accel_count", S_IRUGO, ecm_nss_ipv4_dentry, -- (u32 *)&ecm_nss_ipv4_pending_accel_count)) { -- DEBUG_ERROR("Failed to create ecm nss ipv4 pending_accel_count file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("pending_accel_count", S_IRUGO, ecm_nss_ipv4_dentry, -+ (u32 *)&ecm_nss_ipv4_pending_accel_count); - -- if (!debugfs_create_u32("pending_decel_count", S_IRUGO, ecm_nss_ipv4_dentry, -- (u32 *)&ecm_nss_ipv4_pending_decel_count)) { -- DEBUG_ERROR("Failed to create ecm nss ipv4 pending_decel_count file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("pending_decel_count", S_IRUGO, ecm_nss_ipv4_dentry, -+ (u32 *)&ecm_nss_ipv4_pending_decel_count); - - if (!debugfs_create_file("accel_limit_mode", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, - NULL, &ecm_nss_ipv4_accel_limit_mode_fops)) { -@@ -2867,11 +2849,8 @@ int ecm_nss_ipv4_init(struct dentry *den - goto task_cleanup; - } - -- if (!debugfs_create_u32("vlan_passthrough_set", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, -- (u32 *)&ecm_nss_ipv4_vlan_passthrough_enable)) { -- DEBUG_ERROR("Failed to create ecm nss ipv4 vlan passthrough file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("vlan_passthrough_set", S_IRUGO | S_IWUSR, ecm_nss_ipv4_dentry, -+ (u32 *)&ecm_nss_ipv4_vlan_passthrough_enable); - - #ifdef ECM_NON_PORTED_SUPPORT_ENABLE - if (!ecm_nss_non_ported_ipv4_debugfs_init(ecm_nss_ipv4_dentry)) { ---- a/frontends/nss/ecm_nss_ipv6.c -+++ b/frontends/nss/ecm_nss_ipv6.c -@@ -2542,41 +2542,23 @@ int ecm_nss_ipv6_init(struct dentry *den - return result; - } - -- if (!debugfs_create_u32("no_action_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, -- (u32 *)&ecm_nss_ipv6_no_action_limit_default)) { -- DEBUG_ERROR("Failed to create ecm nss ipv6 no_action_limit_default file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("no_action_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, -+ (u32 *)&ecm_nss_ipv6_no_action_limit_default); - -- if (!debugfs_create_u32("driver_fail_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, -- (u32 *)&ecm_nss_ipv6_driver_fail_limit_default)) { -- DEBUG_ERROR("Failed to create ecm nss ipv6 driver_fail_limit_default file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("driver_fail_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, -+ (u32 *)&ecm_nss_ipv6_driver_fail_limit_default); - -- if (!debugfs_create_u32("nack_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, -- (u32 *)&ecm_nss_ipv6_nack_limit_default)) { -- DEBUG_ERROR("Failed to create ecm nss ipv6 nack_limit_default file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("nack_limit_default", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, -+ (u32 *)&ecm_nss_ipv6_nack_limit_default); - -- if (!debugfs_create_u32("accelerated_count", S_IRUGO, ecm_nss_ipv6_dentry, -- (u32 *)&ecm_nss_ipv6_accelerated_count)) { -- DEBUG_ERROR("Failed to create ecm nss ipv6 accelerated_count file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("accelerated_count", S_IRUGO, ecm_nss_ipv6_dentry, -+ (u32 *)&ecm_nss_ipv6_accelerated_count); - -- if (!debugfs_create_u32("pending_accel_count", S_IRUGO, ecm_nss_ipv6_dentry, -- (u32 *)&ecm_nss_ipv6_pending_accel_count)) { -- DEBUG_ERROR("Failed to create ecm nss ipv6 pending_accel_count file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("pending_accel_count", S_IRUGO, ecm_nss_ipv6_dentry, -+ (u32 *)&ecm_nss_ipv6_pending_accel_count); - -- if (!debugfs_create_u32("pending_decel_count", S_IRUGO, ecm_nss_ipv6_dentry, -- (u32 *)&ecm_nss_ipv6_pending_decel_count)) { -- DEBUG_ERROR("Failed to create ecm nss ipv6 pending_decel_count file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("pending_decel_count", S_IRUGO, ecm_nss_ipv6_dentry, -+ (u32 *)&ecm_nss_ipv6_pending_decel_count); - - if (!debugfs_create_file("accel_limit_mode", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, - NULL, &ecm_nss_ipv6_accel_limit_mode_fops)) { -@@ -2607,11 +2589,8 @@ int ecm_nss_ipv6_init(struct dentry *den - goto task_cleanup; - } - -- if (!debugfs_create_u32("vlan_passthrough_set", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, -- (u32 *)&ecm_nss_ipv6_vlan_passthrough_enable)) { -- DEBUG_ERROR("Failed to create ecm nss ipv6 vlan passthrough file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("vlan_passthrough_set", S_IRUGO | S_IWUSR, ecm_nss_ipv6_dentry, -+ (u32 *)&ecm_nss_ipv6_vlan_passthrough_enable); - - #ifdef ECM_NON_PORTED_SUPPORT_ENABLE - if (!ecm_nss_non_ported_ipv6_debugfs_init(ecm_nss_ipv6_dentry)) { ---- a/frontends/nss/ecm_nss_multicast_ipv4.c -+++ b/frontends/nss/ecm_nss_multicast_ipv4.c -@@ -4139,11 +4139,8 @@ void ecm_nss_multicast_ipv4_stop(int num - */ - int ecm_nss_multicast_ipv4_init(struct dentry *dentry) - { -- if (!debugfs_create_u32("ecm_nss_multicast_ipv4_stop", S_IRUGO | S_IWUSR, dentry, -- (u32 *)&ecm_front_end_ipv4_mc_stopped)) { -- DEBUG_ERROR("Failed to create ecm front end ipv4 mc stop file in debugfs\n"); -- return -1; -- } -+ debugfs_create_u32("ecm_nss_multicast_ipv4_stop", S_IRUGO | S_IWUSR, dentry, -+ (u32 *)&ecm_front_end_ipv4_mc_stopped); - - /* - * Register multicast update callback to MCS snooper ---- a/frontends/nss/ecm_nss_multicast_ipv6.c -+++ b/frontends/nss/ecm_nss_multicast_ipv6.c -@@ -3939,11 +3939,8 @@ void ecm_nss_multicast_ipv6_stop(int num - */ - int ecm_nss_multicast_ipv6_init(struct dentry *dentry) - { -- if (!debugfs_create_u32("ecm_nss_multicast_ipv6_stop", S_IRUGO | S_IWUSR, dentry, -- (u32 *)&ecm_front_end_ipv6_mc_stopped)) { -- DEBUG_ERROR("Failed to create ecm front end ipv6 mc stop file in debugfs\n"); -- return -1; -- } -+ debugfs_create_u32("ecm_nss_multicast_ipv6_stop", S_IRUGO | S_IWUSR, dentry, -+ (u32 *)&ecm_front_end_ipv6_mc_stopped); - - /* - * Register multicast update callback to MCS snooper ---- a/frontends/nss/ecm_nss_non_ported_ipv4.c -+++ b/frontends/nss/ecm_nss_non_ported_ipv4.c -@@ -2615,11 +2615,8 @@ done: - */ - bool ecm_nss_non_ported_ipv4_debugfs_init(struct dentry *dentry) - { -- if (!debugfs_create_u32("non_ported_accelerated_count", S_IRUGO, dentry, -- (u32 *)&ecm_nss_non_ported_ipv4_accelerated_count)) { -- DEBUG_ERROR("Failed to create ecm nss ipv4 non_ported_accelerated_count file in debugfs\n"); -- return false; -- } -+ debugfs_create_u32("non_ported_accelerated_count", S_IRUGO, dentry, -+ (u32 *)&ecm_nss_non_ported_ipv4_accelerated_count); - - return true; - } ---- a/frontends/nss/ecm_nss_non_ported_ipv6.c -+++ b/frontends/nss/ecm_nss_non_ported_ipv6.c -@@ -2329,11 +2329,8 @@ done: - */ - bool ecm_nss_non_ported_ipv6_debugfs_init(struct dentry *dentry) - { -- if (!debugfs_create_u32("non_ported_accelerated_count", S_IRUGO, dentry, -- (u32 *)&ecm_nss_non_ported_ipv6_accelerated_count)) { -- DEBUG_ERROR("Failed to create ecm nss ipv6 non_ported_accelerated_count file in debugfs\n"); -- return false; -- } -+ debugfs_create_u32("non_ported_accelerated_count", S_IRUGO, dentry, -+ (u32 *)&ecm_nss_non_ported_ipv6_accelerated_count); - - return true; - } ---- a/frontends/nss/ecm_nss_ported_ipv4.c -+++ b/frontends/nss/ecm_nss_ported_ipv4.c -@@ -2944,12 +2944,8 @@ bool ecm_nss_ported_ipv4_debugfs_init(st - return false; - } - -- if (!debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, -- &ecm_nss_ported_ipv4_accelerated_count[ECM_NSS_PORTED_IPV4_PROTO_TCP])) { -- DEBUG_ERROR("Failed to create ecm nss ipv4 tcp_accelerated_count file in debugfs\n"); -- debugfs_remove(udp_dentry); -- return false; -- } -+ debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, -+ &ecm_nss_ported_ipv4_accelerated_count[ECM_NSS_PORTED_IPV4_PROTO_TCP]); - - return true; - } ---- a/frontends/nss/ecm_nss_ported_ipv6.c -+++ b/frontends/nss/ecm_nss_ported_ipv6.c -@@ -2732,12 +2732,8 @@ bool ecm_nss_ported_ipv6_debugfs_init(st - return false; - } - -- if (!debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, -- &ecm_nss_ported_ipv6_accelerated_count[ECM_NSS_PORTED_IPV6_PROTO_TCP])) { -- DEBUG_ERROR("Failed to create ecm nss ipv6 tcp_accelerated_count file in debugfs\n"); -- debugfs_remove(udp_dentry); -- return false; -- } -+ debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, -+ &ecm_nss_ported_ipv6_accelerated_count[ECM_NSS_PORTED_IPV6_PROTO_TCP]); - - return true; - } ---- a/frontends/sfe/ecm_sfe_ipv4.c -+++ b/frontends/sfe/ecm_sfe_ipv4.c -@@ -1808,48 +1808,27 @@ int ecm_sfe_ipv4_init(struct dentry *den - } - - #ifdef CONFIG_XFRM -- if (!debugfs_create_u32("reject_acceleration_for_ipsec", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, -- (u32 *)&ecm_sfe_ipv4_reject_acceleration_for_ipsec)) { -- DEBUG_ERROR("Failed to create ecm sfe ipv4 reject_acceleration_for_ipsec file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("reject_acceleration_for_ipsec", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, -+ (u32 *)&ecm_sfe_ipv4_reject_acceleration_for_ipsec); - #endif - -- if (!debugfs_create_u32("no_action_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, -- (u32 *)&ecm_sfe_ipv4_no_action_limit_default)) { -- DEBUG_ERROR("Failed to create ecm sfe ipv4 no_action_limit_default file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("no_action_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, -+ (u32 *)&ecm_sfe_ipv4_no_action_limit_default); - -- if (!debugfs_create_u32("driver_fail_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, -- (u32 *)&ecm_sfe_ipv4_driver_fail_limit_default)) { -- DEBUG_ERROR("Failed to create ecm sfe ipv4 driver_fail_limit_default file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("driver_fail_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, -+ (u32 *)&ecm_sfe_ipv4_driver_fail_limit_default); - -- if (!debugfs_create_u32("nack_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, -- (u32 *)&ecm_sfe_ipv4_nack_limit_default)) { -- DEBUG_ERROR("Failed to create ecm sfe ipv4 nack_limit_default file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("nack_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, -+ (u32 *)&ecm_sfe_ipv4_nack_limit_default); - -- if (!debugfs_create_u32("accelerated_count", S_IRUGO, ecm_sfe_ipv4_dentry, -- (u32 *)&ecm_sfe_ipv4_accelerated_count)) { -- DEBUG_ERROR("Failed to create ecm sfe ipv4 accelerated_count file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("accelerated_count", S_IRUGO, ecm_sfe_ipv4_dentry, -+ (u32 *)&ecm_sfe_ipv4_accelerated_count); - -- if (!debugfs_create_u32("pending_accel_count", S_IRUGO, ecm_sfe_ipv4_dentry, -- (u32 *)&ecm_sfe_ipv4_pending_accel_count)) { -- DEBUG_ERROR("Failed to create ecm sfe ipv4 pending_accel_count file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("pending_accel_count", S_IRUGO, ecm_sfe_ipv4_dentry, -+ (u32 *)&ecm_sfe_ipv4_pending_accel_count); - -- if (!debugfs_create_u32("pending_decel_count", S_IRUGO, ecm_sfe_ipv4_dentry, -- (u32 *)&ecm_sfe_ipv4_pending_decel_count)) { -- DEBUG_ERROR("Failed to create ecm sfe ipv4 pending_decel_count file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("pending_decel_count", S_IRUGO, ecm_sfe_ipv4_dentry, -+ (u32 *)&ecm_sfe_ipv4_pending_decel_count); - - if (!debugfs_create_file("accel_limit_mode", S_IRUGO | S_IWUSR, ecm_sfe_ipv4_dentry, - NULL, &ecm_sfe_ipv4_accel_limit_mode_fops)) { ---- a/frontends/sfe/ecm_sfe_ipv6.c -+++ b/frontends/sfe/ecm_sfe_ipv6.c -@@ -1532,48 +1532,27 @@ int ecm_sfe_ipv6_init(struct dentry *den - } - - #ifdef CONFIG_XFRM -- if (!debugfs_create_u32("reject_acceleration_for_ipsec", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, -- (u32 *)&ecm_sfe_ipv6_reject_acceleration_for_ipsec)) { -- DEBUG_ERROR("Failed to create ecm sfe ipv6 reject_acceleration_for_ipsec file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("reject_acceleration_for_ipsec", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, -+ (u32 *)&ecm_sfe_ipv6_reject_acceleration_for_ipsec); - #endif - -- if (!debugfs_create_u32("no_action_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, -- (u32 *)&ecm_sfe_ipv6_no_action_limit_default)) { -- DEBUG_ERROR("Failed to create ecm sfe ipv6 no_action_limit_default file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("no_action_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, -+ (u32 *)&ecm_sfe_ipv6_no_action_limit_default); - -- if (!debugfs_create_u32("driver_fail_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, -- (u32 *)&ecm_sfe_ipv6_driver_fail_limit_default)) { -- DEBUG_ERROR("Failed to create ecm sfe ipv6 driver_fail_limit_default file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("driver_fail_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, -+ (u32 *)&ecm_sfe_ipv6_driver_fail_limit_default); - -- if (!debugfs_create_u32("nack_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, -- (u32 *)&ecm_sfe_ipv6_nack_limit_default)) { -- DEBUG_ERROR("Failed to create ecm sfe ipv6 nack_limit_default file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("nack_limit_default", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, -+ (u32 *)&ecm_sfe_ipv6_nack_limit_default); - -- if (!debugfs_create_u32("accelerated_count", S_IRUGO, ecm_sfe_ipv6_dentry, -- (u32 *)&ecm_sfe_ipv6_accelerated_count)) { -- DEBUG_ERROR("Failed to create ecm sfe ipv6 accelerated_count file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("accelerated_count", S_IRUGO, ecm_sfe_ipv6_dentry, -+ (u32 *)&ecm_sfe_ipv6_accelerated_count); - -- if (!debugfs_create_u32("pending_accel_count", S_IRUGO, ecm_sfe_ipv6_dentry, -- (u32 *)&ecm_sfe_ipv6_pending_accel_count)) { -- DEBUG_ERROR("Failed to create ecm sfe ipv6 pending_accel_count file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("pending_accel_count", S_IRUGO, ecm_sfe_ipv6_dentry, -+ (u32 *)&ecm_sfe_ipv6_pending_accel_count); - -- if (!debugfs_create_u32("pending_decel_count", S_IRUGO, ecm_sfe_ipv6_dentry, -- (u32 *)&ecm_sfe_ipv6_pending_decel_count)) { -- DEBUG_ERROR("Failed to create ecm sfe ipv6 pending_decel_count file in debugfs\n"); -- goto task_cleanup; -- } -+ debugfs_create_u32("pending_decel_count", S_IRUGO, ecm_sfe_ipv6_dentry, -+ (u32 *)&ecm_sfe_ipv6_pending_decel_count); - - if (!debugfs_create_file("accel_limit_mode", S_IRUGO | S_IWUSR, ecm_sfe_ipv6_dentry, - NULL, &ecm_sfe_ipv6_accel_limit_mode_fops)) { ---- a/frontends/sfe/ecm_sfe_non_ported_ipv4.c -+++ b/frontends/sfe/ecm_sfe_non_ported_ipv4.c -@@ -2284,11 +2284,8 @@ done: - */ - bool ecm_sfe_non_ported_ipv4_debugfs_init(struct dentry *dentry) - { -- if (!debugfs_create_u32("non_ported_accelerated_count", S_IRUGO, dentry, -- (u32 *)&ecm_sfe_non_ported_ipv4_accelerated_count)) { -- DEBUG_ERROR("Failed to create ecm sfe ipv4 non_ported_accelerated_count file in debugfs\n"); -- return false; -- } -+ debugfs_create_u32("non_ported_accelerated_count", S_IRUGO, dentry, -+ (u32 *)&ecm_sfe_non_ported_ipv4_accelerated_count); - - return true; - } ---- a/frontends/sfe/ecm_sfe_non_ported_ipv6.c -+++ b/frontends/sfe/ecm_sfe_non_ported_ipv6.c -@@ -2083,11 +2083,8 @@ done: - */ - bool ecm_sfe_non_ported_ipv6_debugfs_init(struct dentry *dentry) - { -- if (!debugfs_create_u32("non_ported_accelerated_count", S_IRUGO, dentry, -- (u32 *)&ecm_sfe_non_ported_ipv6_accelerated_count)) { -- DEBUG_ERROR("Failed to create ecm sfe ipv6 non_ported_accelerated_count file in debugfs\n"); -- return false; -- } -+ debugfs_create_u32("non_ported_accelerated_count", S_IRUGO, dentry, -+ (u32 *)&ecm_sfe_non_ported_ipv6_accelerated_count); - - return true; - } ---- a/frontends/sfe/ecm_sfe_ported_ipv4.c -+++ b/frontends/sfe/ecm_sfe_ported_ipv4.c -@@ -2528,12 +2528,8 @@ bool ecm_sfe_ported_ipv4_debugfs_init(st - return false; - } - -- if (!debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, -- &ecm_sfe_ported_ipv4_accelerated_count[ECM_SFE_PORTED_IPV4_PROTO_TCP])) { -- DEBUG_ERROR("Failed to create ecm sfe ipv4 tcp_accelerated_count file in debugfs\n"); -- debugfs_remove(udp_dentry); -- return false; -- } -+ debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, -+ &ecm_sfe_ported_ipv4_accelerated_count[ECM_SFE_PORTED_IPV4_PROTO_TCP]); - - return true; - } ---- a/frontends/sfe/ecm_sfe_ported_ipv6.c -+++ b/frontends/sfe/ecm_sfe_ported_ipv6.c -@@ -2374,12 +2374,8 @@ bool ecm_sfe_ported_ipv6_debugfs_init(st - return false; - } - -- if (!debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, -- &ecm_sfe_ported_ipv6_accelerated_count[ECM_SFE_PORTED_IPV6_PROTO_TCP])) { -- DEBUG_ERROR("Failed to create ecm sfe ipv6 tcp_accelerated_count file in debugfs\n"); -- debugfs_remove(udp_dentry); -- return false; -- } -+ debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, -+ &ecm_sfe_ported_ipv6_accelerated_count[ECM_SFE_PORTED_IPV6_PROTO_TCP]); - - return true; - } diff --git a/qca/qca-nss-ecm/patches/200-resolve-high-load.patch b/qca/qca-nss-ecm/patches/200-resolve-high-load.patch deleted file mode 100644 index 253b450a5..000000000 --- a/qca/qca-nss-ecm/patches/200-resolve-high-load.patch +++ /dev/null @@ -1,61 +0,0 @@ -From 6924b71ed809b37fffd74d6428a8ca83e5919746 Mon Sep 17 00:00:00 2001 -From: Dirk Buchwalder -Date: Sun, 27 Jun 2021 16:52:39 +0200 -Subject: [PATCH] qca-nss-ecm: resolve the cpu high load regarding ecm - -If using ECM, cpu load goes up (around 1.0) and stucks there. -This is due to using uninterruptible sleep function, -the patch changes this to interruptible sleep function. - -Signed-off-by: Dirk Buchwalder ---- - frontends/nss/ecm_nss_ipv4.c | 4 ++-- - frontends/nss/ecm_nss_ipv6.c | 4 ++-- - 2 files changed, 4 insertions(+), 4 deletions(-) - -diff --git a/frontends/nss/ecm_nss_ipv4.c b/frontends/nss/ecm_nss_ipv4.c -index e00553c..94b39cd 100644 ---- a/frontends/nss/ecm_nss_ipv4.c -+++ b/frontends/nss/ecm_nss_ipv4.c -@@ -2471,7 +2471,7 @@ static void ecm_nss_ipv4_stats_sync_req_work(struct work_struct *work) - } - spin_unlock_bh(&ecm_nss_ipv4_lock); - -- usleep_range(ECM_NSS_IPV4_STATS_SYNC_UDELAY - 100, ECM_NSS_IPV4_STATS_SYNC_UDELAY); -+ msleep_interruptible(ECM_NSS_IPV4_STATS_SYNC_UDELAY / 1000); - - /* - * If index is 0, we are starting a new round, but if we still have time remain -@@ -2485,7 +2485,7 @@ static void ecm_nss_ipv4_stats_sync_req_work(struct work_struct *work) - } - - if (time_after(ecm_nss_ipv4_next_req_time, current_jiffies)) { -- msleep(jiffies_to_msecs(ecm_nss_ipv4_next_req_time - current_jiffies)); -+ msleep_interruptible(jiffies_to_msecs(ecm_nss_ipv4_next_req_time - current_jiffies)); - } - ecm_nss_ipv4_roll_check_jiffies = jiffies; - ecm_nss_ipv4_next_req_time = ecm_nss_ipv4_roll_check_jiffies + ECM_NSS_IPV4_STATS_SYNC_PERIOD; -diff --git a/frontends/nss/ecm_nss_ipv6.c b/frontends/nss/ecm_nss_ipv6.c -index 82e739f..30af050 100644 ---- a/frontends/nss/ecm_nss_ipv6.c -+++ b/frontends/nss/ecm_nss_ipv6.c -@@ -2210,7 +2210,7 @@ static void ecm_nss_ipv6_stats_sync_req_work(struct work_struct *work) - } - spin_unlock_bh(&ecm_nss_ipv6_lock); - -- usleep_range(ECM_NSS_IPV6_STATS_SYNC_UDELAY - 100, ECM_NSS_IPV6_STATS_SYNC_UDELAY); -+ msleep_interruptible(ECM_NSS_IPV6_STATS_SYNC_UDELAY / 1000); - - /* - * If index is 0, we are starting a new round, but if we still have time remain -@@ -2224,7 +2224,7 @@ static void ecm_nss_ipv6_stats_sync_req_work(struct work_struct *work) - } - - if (time_after(ecm_nss_ipv6_next_req_time, current_jiffies)) { -- msleep(jiffies_to_msecs(ecm_nss_ipv6_next_req_time - current_jiffies)); -+ msleep_interruptible(jiffies_to_msecs(ecm_nss_ipv6_next_req_time - current_jiffies)); - } - ecm_nss_ipv6_roll_check_jiffies = jiffies; - ecm_nss_ipv6_next_req_time = ecm_nss_ipv6_roll_check_jiffies + ECM_NSS_IPV6_STATS_SYNC_PERIOD; --- -2.31.1 diff --git a/qca/qca-nss-ecm/patches/203-rework-nfct-notification.patch b/qca/qca-nss-ecm/patches/203-rework-nfct-notification.patch deleted file mode 100644 index 72005cd70..000000000 --- a/qca/qca-nss-ecm/patches/203-rework-nfct-notification.patch +++ /dev/null @@ -1,25 +0,0 @@ ---- a/ecm_conntrack_notifier.c -+++ b/ecm_conntrack_notifier.c -@@ -421,7 +421,11 @@ int ecm_conntrack_notifier_init(struct d - /* - * Eventing subsystem is available so we register a notifier hook to get fast notifications of expired connections - */ -+#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS -+ result = nf_conntrack_register_chain_notifier(&init_net, &ecm_conntrack_notifier); -+#else - result = nf_conntrack_register_notifier(&init_net, &ecm_conntrack_notifier); -+#endif - if (result < 0) { - DEBUG_ERROR("Can't register nf notifier hook.\n"); - debugfs_remove_recursive(ecm_conntrack_notifier_dentry); -@@ -439,7 +443,9 @@ EXPORT_SYMBOL(ecm_conntrack_notifier_ini - void ecm_conntrack_notifier_exit(void) - { - DEBUG_INFO("ECM Conntrack Notifier exit\n"); --#ifdef CONFIG_NF_CONNTRACK_EVENTS -+#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS -+ nf_conntrack_unregister_chain_notifier(&init_net, &ecm_conntrack_notifier); -+#else - nf_conntrack_unregister_notifier(&init_net, &ecm_conntrack_notifier); - #endif - /* diff --git a/qca/qca-nss-ecm/patches/204-More-compile-fixes.patch b/qca/qca-nss-ecm/patches/204-More-compile-fixes.patch deleted file mode 100644 index 63a83c193..000000000 --- a/qca/qca-nss-ecm/patches/204-More-compile-fixes.patch +++ /dev/null @@ -1,49 +0,0 @@ -From e6d701c0d454d841366c556b2ef07a5203ffb35d Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Fri, 21 May 2021 21:41:31 +0200 -Subject: [PATCH] More compile fixes - -More runtime compile fixes. - -Signed-off-by: Robert Marko ---- - frontends/nss/ecm_nss_ported_ipv4.c | 12 +++--------- - frontends/nss/ecm_nss_ported_ipv6.c | 12 +++--------- - 2 files changed, 6 insertions(+), 18 deletions(-) - ---- a/frontends/nss/ecm_nss_ported_ipv4.c -+++ b/frontends/nss/ecm_nss_ported_ipv4.c -@@ -2935,14 +2935,8 @@ done: - */ - bool ecm_nss_ported_ipv4_debugfs_init(struct dentry *dentry) - { -- struct dentry *udp_dentry; -- -- udp_dentry = debugfs_create_u32("udp_accelerated_count", S_IRUGO, dentry, -+ debugfs_create_u32("udp_accelerated_count", S_IRUGO, dentry, - &ecm_nss_ported_ipv4_accelerated_count[ECM_NSS_PORTED_IPV4_PROTO_UDP]); -- if (!udp_dentry) { -- DEBUG_ERROR("Failed to create ecm nss ipv4 udp_accelerated_count file in debugfs\n"); -- return false; -- } - - debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, - &ecm_nss_ported_ipv4_accelerated_count[ECM_NSS_PORTED_IPV4_PROTO_TCP]); ---- a/frontends/nss/ecm_nss_ported_ipv6.c -+++ b/frontends/nss/ecm_nss_ported_ipv6.c -@@ -2723,14 +2723,8 @@ done: - */ - bool ecm_nss_ported_ipv6_debugfs_init(struct dentry *dentry) - { -- struct dentry *udp_dentry; -- -- udp_dentry = debugfs_create_u32("udp_accelerated_count", S_IRUGO, dentry, -+ debugfs_create_u32("udp_accelerated_count", S_IRUGO, dentry, - &ecm_nss_ported_ipv6_accelerated_count[ECM_NSS_PORTED_IPV6_PROTO_UDP]); -- if (!udp_dentry) { -- DEBUG_ERROR("Failed to create ecm nss ipv6 udp_accelerated_count file in debugfs\n"); -- return false; -- } - - debugfs_create_u32("tcp_accelerated_count", S_IRUGO, dentry, - &ecm_nss_ported_ipv6_accelerated_count[ECM_NSS_PORTED_IPV6_PROTO_TCP]); diff --git a/qca/qca-nss-ecm/patches/205-resolve-high-load.patch b/qca/qca-nss-ecm/patches/205-resolve-high-load.patch deleted file mode 100644 index dd1ee13af..000000000 --- a/qca/qca-nss-ecm/patches/205-resolve-high-load.patch +++ /dev/null @@ -1,55 +0,0 @@ -From 6924b71ed809b37fffd74d6428a8ca83e5919746 Mon Sep 17 00:00:00 2001 -From: Dirk Buchwalder -Date: Sun, 27 Jun 2021 16:52:39 +0200 -Subject: [PATCH] qca-nss-ecm: resolve the cpu high load regarding ecm - -If using ECM, cpu load goes up (around 1.0) and stucks there. -This is due to using uninterruptible sleep function, -the patch changes this to interruptible sleep function. - -Signed-off-by: Dirk Buchwalder buchwalder@posteo.de ---- - frontends/nss/ecm_nss_ipv4.c | 4 ++-- - frontends/nss/ecm_nss_ipv6.c | 4 ++-- - 2 files changed, 4 insertions(+), 4 deletions(-) - ---- a/frontends/nss/ecm_nss_ipv4.c -+++ b/frontends/nss/ecm_nss_ipv4.c -@@ -2471,7 +2471,7 @@ static void ecm_nss_ipv4_stats_sync_req_ - } - spin_unlock_bh(&ecm_nss_ipv4_lock); - -- usleep_range(ECM_NSS_IPV4_STATS_SYNC_UDELAY - 100, ECM_NSS_IPV4_STATS_SYNC_UDELAY); -+ msleep_interruptible(ECM_NSS_IPV4_STATS_SYNC_UDELAY / 1000); - - /* - * If index is 0, we are starting a new round, but if we still have time remain -@@ -2485,7 +2485,7 @@ static void ecm_nss_ipv4_stats_sync_req_ - } - - if (time_after(ecm_nss_ipv4_next_req_time, current_jiffies)) { -- msleep(jiffies_to_msecs(ecm_nss_ipv4_next_req_time - current_jiffies)); -+ msleep_interruptible(jiffies_to_msecs(ecm_nss_ipv4_next_req_time - current_jiffies)); - } - ecm_nss_ipv4_roll_check_jiffies = jiffies; - ecm_nss_ipv4_next_req_time = ecm_nss_ipv4_roll_check_jiffies + ECM_NSS_IPV4_STATS_SYNC_PERIOD; ---- a/frontends/nss/ecm_nss_ipv6.c -+++ b/frontends/nss/ecm_nss_ipv6.c -@@ -2210,7 +2210,7 @@ static void ecm_nss_ipv6_stats_sync_req_ - } - spin_unlock_bh(&ecm_nss_ipv6_lock); - -- usleep_range(ECM_NSS_IPV6_STATS_SYNC_UDELAY - 100, ECM_NSS_IPV6_STATS_SYNC_UDELAY); -+ msleep_interruptible(ECM_NSS_IPV6_STATS_SYNC_UDELAY / 1000); - - /* - * If index is 0, we are starting a new round, but if we still have time remain -@@ -2224,7 +2224,7 @@ static void ecm_nss_ipv6_stats_sync_req_ - } - - if (time_after(ecm_nss_ipv6_next_req_time, current_jiffies)) { -- msleep(jiffies_to_msecs(ecm_nss_ipv6_next_req_time - current_jiffies)); -+ msleep_interruptible(jiffies_to_msecs(ecm_nss_ipv6_next_req_time - current_jiffies)); - } - ecm_nss_ipv6_roll_check_jiffies = jiffies; - ecm_nss_ipv6_next_req_time = ecm_nss_ipv6_roll_check_jiffies + ECM_NSS_IPV6_STATS_SYNC_PERIOD; diff --git a/qca/qca-ssdk-shell/Makefile b/qca/qca-ssdk-shell/Makefile deleted file mode 100644 index f872e431e..000000000 --- a/qca/qca-ssdk-shell/Makefile +++ /dev/null @@ -1,48 +0,0 @@ -include $(TOPDIR)/rules.mk - -PKG_NAME:=qca-ssdk-shell -PKG_RELEASE:=$(AUTORELEASE) - -PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/ssdk-shell.git -PKG_SOURCE_PROTO:=git -PKG_SOURCE_DATE:=2022-03-16 -PKG_SOURCE_VERSION:=72a7dc725ae9ccbe7d99f451a6518e7c0dde4740 -PKG_MIRROR_HASH:=a591875ad05d7a6779cf9da575d890bc470889308f239c89a14721924420ac2b - -include $(INCLUDE_DIR)/kernel.mk -include $(INCLUDE_DIR)/package.mk - -define Package/qca-ssdk-shell - SECTION:=QCA - CATEGORY:=Utilities - TITLE:=Shell application for QCA SSDK -endef - - -define Package/qca-ssdk-shell/Description - This package contains a qca-ssdk shell application for QCA chipset -endef - -ifndef CONFIG_TOOLCHAIN_BIN_PATH -CONFIG_TOOLCHAIN_BIN_PATH=$(TOOLCHAIN_DIR)/bin -endif - -QCASSDK_CONFIG_OPTS+= TOOL_PATH=$(CONFIG_TOOLCHAIN_BIN_PATH) \ - SYS_PATH=$(LINUX_DIR) \ - TOOLPREFIX=$(TARGET_CROSS) \ - KVER=$(LINUX_VERSION) \ - CFLAGS="$(TARGET_CFLAGS)" \ - LDFLAGS="$(TARGET_LDFLAGS)" \ - ARCH=$(LINUX_KARCH) - -define Build/Compile - $(MAKE) -C $(PKG_BUILD_DIR) $(strip $(QCASSDK_CONFIG_OPTS)) -endef - -define Package/qca-ssdk-shell/install - $(INSTALL_DIR) $(1)/usr/sbin - $(INSTALL_BIN) $(PKG_BUILD_DIR)/build/bin/ssdk_sh $(1)/usr/sbin/ -endef - - -$(eval $(call BuildPackage,qca-ssdk-shell)) diff --git a/qca/qca-ssdk/Makefile b/qca/qca-ssdk/Makefile deleted file mode 100644 index 5b1a7956f..000000000 --- a/qca/qca-ssdk/Makefile +++ /dev/null @@ -1,91 +0,0 @@ -include $(TOPDIR)/rules.mk - -PKG_NAME:=qca-ssdk -PKG_RELEASE:=$(AUTORELEASE) - -PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/qca-ssdk.git -PKG_SOURCE_PROTO:=git -PKG_SOURCE_DATE:=2022-04-07 -PKG_SOURCE_VERSION:=62955de3c838028d3f72313eef99c57fa4babb71 -PKG_MIRROR_HASH:=84c7de6d1ce82fb15acebea0e44158695a33ed6f18335da32ec9f248dcb4b285 - -include $(INCLUDE_DIR)/kernel.mk -include $(INCLUDE_DIR)/package.mk - -define KernelPackage/qca-ssdk-nohnat - SECTION:=kernel - CATEGORY:=Kernel modules - SUBMENU:=Network Devices - TITLE:=Kernel driver for QCA SSDK - DEPENDS:=@(TARGET_ipq807x) - FILES:=$(PKG_BUILD_DIR)/build/bin/qca-ssdk.ko - AUTOLOAD:=$(call AutoLoad,30,qca-ssdk) -endef - -define KernelPackage/qca-ssdk-nohnat/Description -This package contains a qca-ssdk driver for QCA chipset -endef - -GCC_VERSION=$(shell echo "$(CONFIG_GCC_VERSION)" | sed 's/[^0-9.]*\([0-9.]*\).*/\1/') - -ifdef CONFIG_TOOLCHAIN_BIN_PATH -TOOLCHAIN_BIN_PATH=$(CONFIG_TOOLCHAIN_BIN_PATH) -else -TOOLCHAIN_BIN_PATH=$(TOOLCHAIN_DIR)/bin -endif - -MAKE_FLAGS+= \ - TARGET_NAME=$(CONFIG_TARGET_NAME) \ - TOOL_PATH=$(TOOLCHAIN_BIN_PATH) \ - SYS_PATH=$(LINUX_DIR) \ - TOOLPREFIX=$(TARGET_CROSS) \ - KVER=$(LINUX_VERSION) \ - ARCH=$(LINUX_KARCH) \ - TARGET_SUFFIX=$(CONFIG_TARGET_SUFFIX) \ - GCC_VERSION=$(GCC_VERSION) \ - EXTRA_CFLAGS=-fno-stack-protector -I$(STAGING_DIR)/usr/include \ - $(KERNEL_MAKE_FLAGS) - -ifneq (, $(findstring $(CONFIG_TARGET_BOARD), "ipq60xx" "ipq807x")) - MAKE_FLAGS+= PTP_FEATURE=disable SWCONFIG_FEATURE=disable -endif - -ifeq ($(CONFIG_TARGET_BOARD), "ipq807x") - MAKE_FLAGS+= CHIP_TYPE=HPPE -else ifeq ($(CONFIG_TARGET_BOARD), "ipq60xx") - MAKE_FLAGS+= CHIP_TYPE=CPPE -endif - -define Build/InstallDev - $(INSTALL_DIR) $(1)/usr/include/qca-ssdk - $(INSTALL_DIR) $(1)/usr/include/qca-ssdk/api - $(INSTALL_DIR) $(1)/usr/include/qca-ssdk/ref - $(INSTALL_DIR) $(1)/usr/include/qca-ssdk/fal - $(INSTALL_DIR) $(1)/usr/include/qca-ssdk/sal - $(INSTALL_DIR) $(1)/usr/include/qca-ssdk/init - $(CP) -rf $(PKG_BUILD_DIR)/include/api/sw_ioctl.h $(1)/usr/include/qca-ssdk/api - if [ -f $(PKG_BUILD_DIR)/include/ref/ref_vsi.h ]; then \ - $(CP) -rf $(PKG_BUILD_DIR)/include/ref/ref_vsi.h $(1)/usr/include/qca-ssdk/ref/; \ - fi - if [ -f $(PKG_BUILD_DIR)/include/ref/ref_fdb.h ]; then \ - $(CP) -rf $(PKG_BUILD_DIR)/include/ref/ref_fdb.h $(1)/usr/include/qca-ssdk/ref/; \ - fi - if [ -f $(PKG_BUILD_DIR)/include/ref/ref_port_ctrl.h ]; then \ - $(CP) -rf $(PKG_BUILD_DIR)/include/ref/ref_port_ctrl.h $(1)/usr/include/qca-ssdk/ref/; \ - fi - if [ -f $(PKG_BUILD_DIR)/include/init/ssdk_init.h ]; then \ - $(CP) -rf $(PKG_BUILD_DIR)/include/init/ssdk_init.h $(1)/usr/include/qca-ssdk/init/; \ - fi - $(CP) -rf $(PKG_BUILD_DIR)/include/fal $(1)/usr/include/qca-ssdk - $(CP) -rf $(PKG_BUILD_DIR)/include/common/*.h $(1)/usr/include/qca-ssdk - $(CP) -rf $(PKG_BUILD_DIR)/include/sal/os/linux/*.h $(1)/usr/include/qca-ssdk - $(CP) -rf $(PKG_BUILD_DIR)/include/sal/os/*.h $(1)/usr/include/qca-ssdk - -endef - -define KernelPackage/qca-ssdk-nohnat/install - $(INSTALL_DIR) $(1)/etc/init.d - $(INSTALL_BIN) ./files/qca-ssdk $(1)/etc/init.d/qca-ssdk -endef - -$(eval $(call KernelPackage,qca-ssdk-nohnat)) diff --git a/qca/qca-ssdk/files/qca-ssdk b/qca/qca-ssdk/files/qca-ssdk deleted file mode 100644 index 389279c0c..000000000 --- a/qca/qca-ssdk/files/qca-ssdk +++ /dev/null @@ -1,206 +0,0 @@ -#!/bin/sh /etc/rc.common -# Copyright (c) 2018, The Linux Foundation. All rights reserved. -# -# Permission to use, copy, modify, and/or distribute this software for any -# purpose with or without fee is hereby granted, provided that the above -# copyright notice and this permission notice appear in all copies. -# -# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -# - -START=16 - -#!/bin/sh -ruletype="ip4 ip6" -side="wan lan" -qwan="1 3 2 0 5 7 6 4" -qlan="0 1 2 3 4 5 6 7" - -function create_war_acl_rules(){ - for lw in $side - do - #echo $lw - if [ "$lw" == "wan" ];then - listid=254 - queue=$qwan - portmap=0x20 - else - listid=255 - queue=$qlan - portmap=0x1e - fi - #echo $queue - #echo "creating list $listid" - ssdk_sh acl list create $listid 255 - ruleid=0 - for rt in $ruletype - do - for qid in $queue - do - cmd="ssdk_sh acl rule add $listid $ruleid 1 n 0 0" - #echo $cmd - if [ "$rt" == "ip4" ];then - cmd="$cmd ip4 n n n n n n n n n n n n n n n n n n n n n n n n n n n n n" - #echo $cmd - else - cmd="$cmd ip6 n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n" - #echo $cmd - fi - if [ $ruleid -le 3 ];then - #non-zero dscp - cmd="$cmd y 0x0 0xff" - elif [ $ruleid -le 7 ];then - #zero dscp - cmd="$cmd n" - elif [ $ruleid -le 11 ];then - #non-zero dscp - cmd="$cmd y 0x0 0xff" - else - #zero dscp - cmd="$cmd n" - fi - p=$((ruleid/2)) - cmd="$cmd y mask $((ruleid%2)) 0x1 y mask $((p%2)) 0x1 n n n n n n n n n n n n n n n y n n n n n n n y $qid n n 0 0 n n n n n n n n n n n n n n n n n n n n 0" - #echo $cmd - $cmd - ruleid=`expr $ruleid + 1` - done - done - ssdk_sh acl list bind $listid 0 1 $portmap - done -} - -function create_war_cosmap(){ - ssdk_sh cosmap pri2q set 0 0 - ssdk_sh cosmap pri2q set 1 0 - ssdk_sh cosmap pri2q set 2 0 - ssdk_sh cosmap pri2q set 3 0 - ssdk_sh cosmap pri2q set 4 1 - ssdk_sh cosmap pri2q set 5 1 - ssdk_sh cosmap pri2q set 6 1 - ssdk_sh cosmap pri2q set 7 1 - ssdk_sh cosmap pri2ehq set 0 0 - ssdk_sh cosmap pri2ehq set 1 0 - ssdk_sh cosmap pri2ehq set 2 0 - ssdk_sh cosmap pri2ehq set 3 0 - ssdk_sh cosmap pri2ehq set 4 1 - ssdk_sh cosmap pri2ehq set 5 1 - ssdk_sh cosmap pri2ehq set 6 1 - ssdk_sh cosmap pri2ehq set 7 1 -} - -function create_acl_byp_egstp_rules(){ - ssdk_sh debug module_func set servcode 0xf 0x0 0x0 - ssdk_sh servcode config set 1 n 0 0xfffefc7f 0xffbdff 0 0 0 0 0 0 - ssdk_sh debug module_func set servcode 0x0 0x0 0x0 - ssdk_sh acl list create 56 48 - ssdk_sh acl rule add 56 0 1 n 0 0 mac n n n n n y 01-80-c2-00-00-00 ff-ff-ff-ff-ff-ff n n n n n n n n n n n n n n n n n n n n n n n y n n n n n n n n n n 0 0 n n n n n n n n n n n n n y n n n n n n n n n n n n y n n n n n n n n n n n n 0 - ssdk_sh acl rule add 56 1 1 n 0 0 mac n n n n n n n yes 0x8809 0xffff n n n n n n n n n n n n n n n n n n n n n y n n n n n n n n n n 0 0 n n n n n n n n n n n n n y n n n n n n n n n n n n y n n n n n n n n n n n n 0 - ssdk_sh acl rule add 56 2 1 n 0 0 mac n n n n n n n yes 0x888e 0xffff n n n n n n n n n n n n n n n n n n n n n y n n n n n n n n n n 0 0 n n n n n n n n n n n n n y n n n n n n n n n n n n y n n n n n n n n n n n n 0 - ssdk_sh acl list bind 56 0 2 1 -} - -function delete_war_acl_rules(){ - for lw in $side - do - #echo $lw - if [ "$lw" == "wan" ];then - listid=254 - queue=$qwan - portmap=0x20 - else - listid=255 - queue=$qlan - portmap=0x1e - fi - ssdk_sh acl list unbind $listid 0 1 $portmap - for rt in $ruletype - do - for qid in $queue - do - cmd="ssdk_sh acl rule del $listid 0 1" - echo $cmd - $cmd - done - done - #echo "deleting list $listid" - ssdk_sh acl list destroy $listid - done -} - -function delete_war_cosmap(){ - ssdk_sh cosmap pri2q set 0 0 - ssdk_sh cosmap pri2q set 1 0 - ssdk_sh cosmap pri2q set 2 1 - ssdk_sh cosmap pri2q set 3 1 - ssdk_sh cosmap pri2q set 4 2 - ssdk_sh cosmap pri2q set 5 2 - ssdk_sh cosmap pri2q set 6 3 - ssdk_sh cosmap pri2q set 7 3 - ssdk_sh cosmap pri2ehq set 0 1 - ssdk_sh cosmap pri2ehq set 1 0 - ssdk_sh cosmap pri2ehq set 2 2 - ssdk_sh cosmap pri2ehq set 3 2 - ssdk_sh cosmap pri2ehq set 4 3 - ssdk_sh cosmap pri2ehq set 5 3 - ssdk_sh cosmap pri2ehq set 6 4 - ssdk_sh cosmap pri2ehq set 7 5 -} - -function delete_acl_byp_egstp_rules(){ - ssdk_sh debug module_func set servcode 0xf 0x0 0x0 - ssdk_sh servcode config set 1 n 0 0xfffefcff 0xffbfff 0 0 0 0 0 0 - ssdk_sh debug module_func set servcode 0x0 0x0 0x0 - ssdk_sh acl list unbind 56 0 2 1 - ssdk_sh acl rule del 56 0 1 - ssdk_sh acl rule del 56 1 1 - ssdk_sh acl rule del 56 2 1 - ssdk_sh acl list destroy 56 -} - -function edma_war_config_add(){ - create_war_cosmap - ssdk_sh acl status set enable - create_war_acl_rules -} - -function edma_war_config_del(){ - delete_war_acl_rules - delete_war_cosmap -} - -start() { - chip_ver=`ssdk_sh debug reg get 0 4 | grep Data | tr -d 'SSDK Init OK![Data]:'` - #The following commands should be uncommented to enable EDMA WAR - if [ "$chip_ver" = "0x1401" ]; then - #edma_war_config_add - echo '' - fi - #The following commands should be uncommented to add acl egress stp bypass rules - if [ "$chip_ver" = "0x1500" ] || [ "$chip_ver" = "0x1501" ]; then - #create_acl_byp_egstp_rules - echo '' - fi - echo starting -} - -stop() { - chip_ver=`ssdk_sh debug reg get 0 4 | grep Data | tr -d 'SSDK Init OK![Data]:'` - #The following commands should be uncommented to disable EDMA WAR - if [ "$chip_ver" = "0x1401" ]; then - #edma_war_config_del - echo '' - fi - #The following commands should be uncommented to delete acl egress stp bypass rules - if [ "$chip_ver" = "0x1500" ] || [ "$chip_ver" = "0x1501" ]; then - #delete_acl_byp_egstp_rules - echo '' - fi - echo stoping -} diff --git a/qca/qca-ssdk/patches/0001-SSDK-config-add-kernel-5.10.patch b/qca/qca-ssdk/patches/0001-SSDK-config-add-kernel-5.10.patch deleted file mode 100644 index 8ad541ebf..000000000 --- a/qca/qca-ssdk/patches/0001-SSDK-config-add-kernel-5.10.patch +++ /dev/null @@ -1,56 +0,0 @@ -From 472c0c8132784608312c80c4b02c03ea7c132235 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Wed, 12 May 2021 13:41:12 +0200 -Subject: [PATCH] SSDK: config: add kernel 5.10 - -This is purely to identify it and be able to set -flags correctly. - -Signed-off-by: Robert Marko ---- - config | 6 +++++- - make/linux_opt.mk | 4 ++-- - 2 files changed, 7 insertions(+), 3 deletions(-) - ---- a/config -+++ b/config -@@ -22,6 +22,10 @@ ifeq ($(KVER),$(filter 5.4%,$(KVER))) - OS_VER=5_4 - endif - -+ifeq ($(KVER),$(filter 5.10%,$(KVER))) -+OS_VER=5_10 -+endif -+ - ifeq ($(KVER), 3.4.0) - OS_VER=3_4 - endif -@@ -123,7 +127,7 @@ endif - endif - - ifeq ($(ARCH), arm64) -- ifeq ($(KVER),$(filter 4.1% 4.4% 4.9% 5.4%,$(KVER))) -+ ifeq ($(KVER),$(filter 4.1% 4.4% 4.9% 5.4% 5.10%,$(KVER))) - CPU_CFLAG= -DMODULE -Os -pipe -march=armv8-a -mcpu=cortex-a53+crypto -fno-caller-saves -fno-strict-aliasing -Werror -fno-common -Wno-format-security -Wno-pointer-sign -Wno-unused-but-set-variable -Wno-error=unused-result -mcmodel=large - endif - endif ---- a/make/linux_opt.mk -+++ b/make/linux_opt.mk -@@ -388,7 +388,7 @@ ifeq (KSLIB, $(MODULE_TYPE)) - KASAN_SHADOW_SCALE_SHIFT := 3 - endif - -- ifeq (5_4, $(OS_VER)) -+ ifeq ($(OS_VER),$(filter 5_4 5_10, $(OS_VER))) - ifeq ($(ARCH), arm64) - KASAN_OPTION += -DKASAN_SHADOW_SCALE_SHIFT=$(KASAN_SHADOW_SCALE_SHIFT) - endif -@@ -419,7 +419,7 @@ ifeq (KSLIB, $(MODULE_TYPE)) - - endif - -- ifeq ($(OS_VER),$(filter 4_4 5_4, $(OS_VER))) -+ ifeq ($(OS_VER),$(filter 4_4 5_4 5_10, $(OS_VER))) - MODULE_CFLAG += -DKVER34 - MODULE_CFLAG += -DKVER32 - MODULE_CFLAG += -DLNX26_22 diff --git a/qca/qca-ssdk/patches/0002-SSDK-replace-ioremap_nocache-with-ioremap.patch b/qca/qca-ssdk/patches/0002-SSDK-replace-ioremap_nocache-with-ioremap.patch deleted file mode 100644 index b293ad295..000000000 --- a/qca/qca-ssdk/patches/0002-SSDK-replace-ioremap_nocache-with-ioremap.patch +++ /dev/null @@ -1,102 +0,0 @@ -From 784f2cfdfaf3bdf44917924e157049230a0ef5f8 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Wed, 12 May 2021 13:45:45 +0200 -Subject: [PATCH] SSDK: replace ioremap_nocache with ioremap - -ioremap_nocache was dropped upstream, simply use the -generic variety. - -Signed-off-by: Robert Marko ---- - src/init/ssdk_clk.c | 10 +++++----- - src/init/ssdk_init.c | 2 +- - src/init/ssdk_plat.c | 6 +++--- - 3 files changed, 9 insertions(+), 9 deletions(-) - ---- a/src/init/ssdk_clk.c -+++ b/src/init/ssdk_clk.c -@@ -623,7 +623,7 @@ ssdk_mp_tcsr_get(a_uint32_t tcsr_offset, - { - void __iomem *tcsr_base = NULL; - -- tcsr_base = ioremap_nocache(TCSR_ETH_ADDR, TCSR_ETH_SIZE); -+ tcsr_base = ioremap(TCSR_ETH_ADDR, TCSR_ETH_SIZE); - if (!tcsr_base) - { - SSDK_ERROR("Failed to map tcsr eth address!\n"); -@@ -640,7 +640,7 @@ ssdk_mp_tcsr_set(a_uint32_t tcsr_offset, - { - void __iomem *tcsr_base = NULL; - -- tcsr_base = ioremap_nocache(TCSR_ETH_ADDR, TCSR_ETH_SIZE); -+ tcsr_base = ioremap(TCSR_ETH_ADDR, TCSR_ETH_SIZE); - if (!tcsr_base) - { - SSDK_ERROR("Failed to map tcsr eth address!\n"); -@@ -688,7 +688,7 @@ ssdk_mp_cmnblk_stable_check(void) - a_uint32_t reg_val; - int i, loops = 20; - -- pll_lock = ioremap_nocache(CMN_PLL_LOCKED_ADDR, CMN_PLL_LOCKED_SIZE); -+ pll_lock = ioremap(CMN_PLL_LOCKED_ADDR, CMN_PLL_LOCKED_SIZE); - if (!pll_lock) { - SSDK_ERROR("Failed to map CMN PLL LOCK register!\n"); - return A_FALSE; -@@ -745,7 +745,7 @@ static void ssdk_cmnblk_pll_src_set(enum - void __iomem *cmn_pll_src_base = NULL; - a_uint32_t reg_val; - -- cmn_pll_src_base = ioremap_nocache(CMN_BLK_PLL_SRC_ADDR, CMN_BLK_SIZE); -+ cmn_pll_src_base = ioremap(CMN_BLK_PLL_SRC_ADDR, CMN_BLK_SIZE); - if (!cmn_pll_src_base) { - SSDK_ERROR("Failed to map cmn pll source address!\n"); - return; -@@ -766,7 +766,7 @@ static void ssdk_cmnblk_init(enum cmnblk - void __iomem *gcc_pll_base = NULL; - a_uint32_t reg_val; - -- gcc_pll_base = ioremap_nocache(CMN_BLK_ADDR, CMN_BLK_SIZE); -+ gcc_pll_base = ioremap(CMN_BLK_ADDR, CMN_BLK_SIZE); - if (!gcc_pll_base) { - SSDK_ERROR("Failed to map gcc pll address!\n"); - return; ---- a/src/init/ssdk_init.c -+++ b/src/init/ssdk_init.c -@@ -2770,7 +2770,7 @@ static int ssdk_dess_mac_mode_init(a_uin - (a_uint8_t *)®_value, 4); - mdelay(10); - /*softreset psgmii, fixme*/ -- gcc_addr = ioremap_nocache(0x1812000, 0x200); -+ gcc_addr = ioremap(0x1812000, 0x200); - if (!gcc_addr) { - SSDK_ERROR("gcc map fail!\n"); - return 0; ---- a/src/init/ssdk_plat.c -+++ b/src/init/ssdk_plat.c -@@ -1312,7 +1312,7 @@ ssdk_plat_init(ssdk_init_cfg *cfg, a_uin - reg_mode = ssdk_uniphy_reg_access_mode_get(dev_id); - if(reg_mode == HSL_REG_LOCAL_BUS) { - ssdk_uniphy_reg_map_info_get(dev_id, &map); -- qca_phy_priv_global[dev_id]->uniphy_hw_addr = ioremap_nocache(map.base_addr, -+ qca_phy_priv_global[dev_id]->uniphy_hw_addr = ioremap(map.base_addr, - map.size); - if (!qca_phy_priv_global[dev_id]->uniphy_hw_addr) { - SSDK_ERROR("%s ioremap fail.", __func__); -@@ -1327,7 +1327,7 @@ ssdk_plat_init(ssdk_init_cfg *cfg, a_uin - reg_mode = ssdk_switch_reg_access_mode_get(dev_id); - if(reg_mode == HSL_REG_LOCAL_BUS) { - ssdk_switch_reg_map_info_get(dev_id, &map); -- qca_phy_priv_global[dev_id]->hw_addr = ioremap_nocache(map.base_addr, -+ qca_phy_priv_global[dev_id]->hw_addr = ioremap(map.base_addr, - map.size); - if (!qca_phy_priv_global[dev_id]->hw_addr) { - SSDK_ERROR("%s ioremap fail.", __func__); -@@ -1358,7 +1358,7 @@ ssdk_plat_init(ssdk_init_cfg *cfg, a_uin - return -1; - } - -- qca_phy_priv_global[dev_id]->psgmii_hw_addr = ioremap_nocache(map.base_addr, -+ qca_phy_priv_global[dev_id]->psgmii_hw_addr = ioremap(map.base_addr, - map.size); - if (!qca_phy_priv_global[dev_id]->psgmii_hw_addr) { - SSDK_ERROR("%s ioremap fail.", __func__); diff --git a/qca/qca-ssdk/patches/0004-platform-use-of_mdio_find_bus-to-get-MDIO-bus.patch b/qca/qca-ssdk/patches/0004-platform-use-of_mdio_find_bus-to-get-MDIO-bus.patch deleted file mode 100644 index 3bcbcccf6..000000000 --- a/qca/qca-ssdk/patches/0004-platform-use-of_mdio_find_bus-to-get-MDIO-bus.patch +++ /dev/null @@ -1,40 +0,0 @@ -From b6190ca46287d01a895c7cc14de30410c09ff1b8 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Wed, 12 May 2021 17:15:46 +0200 -Subject: [PATCH] SSDK: platform: use of_mdio_find_bus() to get MDIO bus - -Kernel has a generic of_mdio_find_bus() which can get the appropriate -MDIO bus based on the DT node. -So, drop the getting MDIO from platform data, which no longer works -in 5.4 and later and use of_mdio_find_bus(). - -Signed-off-by: Baruch Siach -Signed-off-by: Robert Marko ---- - src/init/ssdk_plat.c | 8 +------- - 1 file changed, 1 insertion(+), 7 deletions(-) - ---- a/src/init/ssdk_plat.c -+++ b/src/init/ssdk_plat.c -@@ -551,7 +551,6 @@ static int miibus_get(a_uint32_t dev_id) - struct device_node *mdio_node = NULL; - struct device_node *switch_node = NULL; - struct platform_device *mdio_plat = NULL; -- struct ipq40xx_mdio_data *mdio_data = NULL; - struct qca_phy_priv *priv; - hsl_reg_mode reg_mode = HSL_REG_LOCAL_BUS; - priv = qca_phy_priv_global[dev_id]; -@@ -584,12 +583,7 @@ static int miibus_get(a_uint32_t dev_id) - - if(reg_mode == HSL_REG_LOCAL_BUS) - { -- mdio_data = dev_get_drvdata(&mdio_plat->dev); -- if (!mdio_data) { -- SSDK_ERROR("cannot get mdio_data reference from device data\n"); -- return 1; -- } -- priv->miibus = mdio_data->mii_bus; -+ priv->miibus = of_mdio_find_bus(mdio_node); - } - else - priv->miibus = dev_get_drvdata(&mdio_plat->dev); diff --git a/qca/qca-ssdk/patches/0005-SSDK-dts-fix-of_get_mac_address.patch b/qca/qca-ssdk/patches/0005-SSDK-dts-fix-of_get_mac_address.patch deleted file mode 100644 index 29be93128..000000000 --- a/qca/qca-ssdk/patches/0005-SSDK-dts-fix-of_get_mac_address.patch +++ /dev/null @@ -1,42 +0,0 @@ -From f3a7b93137c1a6a1b8010b86296242178eed5d9e Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Fri, 13 Aug 2021 20:03:21 +0200 -Subject: [PATCH] SSDK: dts: fix of_get_mac_address() - -Recently OpenWrt backported the updated of_get_mac_address() -function which returns and error code instead. - -So, patch the SSDK to use it and fix the compilation error. - -Signed-off-by: Robert Marko ---- - src/init/ssdk_dts.c | 7 ++++--- - 1 file changed, 4 insertions(+), 3 deletions(-) - ---- a/src/init/ssdk_dts.c -+++ b/src/init/ssdk_dts.c -@@ -779,8 +779,9 @@ static void ssdk_dt_parse_intf_mac(void) - { - struct device_node *dp_node = NULL; - a_uint32_t dp = 0; -- a_uint8_t *maddr = NULL; -+ u8 maddr[ETH_ALEN]; - char dp_name[8] = {0}; -+ int ret; - - for (dp = 1; dp <= SSDK_MAX_NR_ETH; dp++) { - snprintf(dp_name, sizeof(dp_name), "dp%d", dp); -@@ -788,11 +789,11 @@ static void ssdk_dt_parse_intf_mac(void) - if (!dp_node) { - continue; - } -- maddr = (a_uint8_t *)of_get_mac_address(dp_node); -+ ret = of_get_mac_address(dp_node, maddr); - #if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0)) - if (maddr && is_valid_ether_addr(maddr)) { - #else -- if (!IS_ERR(maddr) && is_valid_ether_addr(maddr)) { -+ if (!ret && is_valid_ether_addr(maddr)) { - #endif - ssdk_dt_global.num_intf_mac++; - ether_addr_copy(ssdk_dt_global.intf_mac[dp-1].uc, maddr); diff --git a/qca/qca-ssdk/patches/0006-SSDK-config-add-kernel-5.15.patch b/qca/qca-ssdk/patches/0006-SSDK-config-add-kernel-5.15.patch deleted file mode 100644 index a4e1b2782..000000000 --- a/qca/qca-ssdk/patches/0006-SSDK-config-add-kernel-5.15.patch +++ /dev/null @@ -1,56 +0,0 @@ -From 599f19551dc8db3cb396e4c139a73bd72300ebf5 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Fri, 24 Dec 2021 19:39:02 +0100 -Subject: [PATCH] SSDK: config: add kernel 5.15 - -This is purely to identify it and be able to set -flags correctly. - -Signed-off-by: Robert Marko ---- - config | 6 +++++- - make/linux_opt.mk | 4 ++-- - 2 files changed, 7 insertions(+), 3 deletions(-) - ---- a/config -+++ b/config -@@ -26,6 +26,10 @@ ifeq ($(KVER),$(filter 5.10%,$(KVER))) - OS_VER=5_10 - endif - -+ifeq ($(KVER),$(filter 5.15%,$(KVER))) -+OS_VER=5_15 -+endif -+ - ifeq ($(KVER), 3.4.0) - OS_VER=3_4 - endif -@@ -127,7 +131,7 @@ endif - endif - - ifeq ($(ARCH), arm64) -- ifeq ($(KVER),$(filter 4.1% 4.4% 4.9% 5.4% 5.10%,$(KVER))) -+ ifeq ($(KVER),$(filter 4.1% 4.4% 4.9% 5.4% 5.10% 5.15%,$(KVER))) - CPU_CFLAG= -DMODULE -Os -pipe -march=armv8-a -mcpu=cortex-a53+crypto -fno-caller-saves -fno-strict-aliasing -Werror -fno-common -Wno-format-security -Wno-pointer-sign -Wno-unused-but-set-variable -Wno-error=unused-result -mcmodel=large - endif - endif ---- a/make/linux_opt.mk -+++ b/make/linux_opt.mk -@@ -388,7 +388,7 @@ ifeq (KSLIB, $(MODULE_TYPE)) - KASAN_SHADOW_SCALE_SHIFT := 3 - endif - -- ifeq ($(OS_VER),$(filter 5_4 5_10, $(OS_VER))) -+ ifeq ($(OS_VER),$(filter 5_4 5_10 5_15, $(OS_VER))) - ifeq ($(ARCH), arm64) - KASAN_OPTION += -DKASAN_SHADOW_SCALE_SHIFT=$(KASAN_SHADOW_SCALE_SHIFT) - endif -@@ -419,7 +419,7 @@ ifeq (KSLIB, $(MODULE_TYPE)) - - endif - -- ifeq ($(OS_VER),$(filter 4_4 5_4 5_10, $(OS_VER))) -+ ifeq ($(OS_VER),$(filter 4_4 5_4 5_10 5_15, $(OS_VER))) - MODULE_CFLAG += -DKVER34 - MODULE_CFLAG += -DKVER32 - MODULE_CFLAG += -DLNX26_22 diff --git a/qca/qca-ssdk/patches/0007-qca8081-convert-to-5.11-IRQ-model.patch b/qca/qca-ssdk/patches/0007-qca8081-convert-to-5.11-IRQ-model.patch deleted file mode 100644 index b0c272b17..000000000 --- a/qca/qca-ssdk/patches/0007-qca8081-convert-to-5.11-IRQ-model.patch +++ /dev/null @@ -1,83 +0,0 @@ -From 25ff0ae02accadd7b05f1dae788505f833d5c019 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Fri, 24 Dec 2021 20:02:32 +0100 -Subject: [PATCH] qca8081: convert to 5.11 IRQ model - -Kernel 5.11 introduced new IRQ handling model for PHY-s, -so provide those if 5.11 or later is used. - -Signed-off-by: Robert Marko ---- - src/hsl/phy/qca808x.c | 46 +++++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 46 insertions(+) - ---- a/src/hsl/phy/qca808x.c -+++ b/src/hsl/phy/qca808x.c -@@ -238,6 +238,7 @@ static int qca808x_config_intr(struct ph - return err; - } - -+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 11, 0)) - static int qca808x_ack_interrupt(struct phy_device *phydev) - { - int err; -@@ -257,6 +258,47 @@ static int qca808x_ack_interrupt(struct - - return (err < 0) ? err : 0; - } -+#endif -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(5, 11, 0)) -+static irqreturn_t qca808x_handle_interrupt(struct phy_device *phydev) -+{ -+ a_uint16_t irq_status, int_enabled; -+ a_uint32_t dev_id = 0, phy_id = 0; -+ qca808x_priv *priv = phydev->priv; -+ const struct qca808x_phy_info *pdata = priv->phy_info; -+ -+ if (!pdata) { -+ return SW_FAIL; -+ } -+ -+ dev_id = pdata->dev_id; -+ phy_id = pdata->phy_addr; -+ -+ irq_status = qca808x_phy_reg_read(dev_id, phy_id, -+ QCA808X_PHY_INTR_STATUS); -+ if (irq_status < 0) { -+ phy_error(phydev); -+ return IRQ_NONE; -+ } -+ -+ /* Read the current enabled interrupts */ -+ int_enabled = qca808x_phy_reg_read(dev_id, phy_id, -+ QCA808X_PHY_INTR_MASK); -+ if (int_enabled < 0) { -+ phy_error(phydev); -+ return IRQ_NONE; -+ } -+ -+ /* See if this was one of our enabled interrupts */ -+ if (!(irq_status & int_enabled)) -+ return IRQ_NONE; -+ -+ phy_trigger_machine(phydev); -+ -+ return IRQ_HANDLED; -+} -+#endif - - /* switch linux negtiation capability to fal avariable */ - #if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0)) -@@ -559,7 +601,11 @@ struct phy_driver qca808x_phy_driver = { - .config_intr = qca808x_config_intr, - .config_aneg = qca808x_config_aneg, - .aneg_done = qca808x_aneg_done, -+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 11, 0)) - .ack_interrupt = qca808x_ack_interrupt, -+#else -+ .handle_interrupt = qca808x_handle_interrupt, -+#endif - .read_status = qca808x_read_status, - .suspend = qca808x_suspend, - .resume = qca808x_resume, diff --git a/qca/qca-ssdk/patches/0008-qca807x-add-a-LED-quirk-for-Xiaomi-AX9000.patch b/qca/qca-ssdk/patches/0008-qca807x-add-a-LED-quirk-for-Xiaomi-AX9000.patch deleted file mode 100644 index 76f71be46..000000000 --- a/qca/qca-ssdk/patches/0008-qca807x-add-a-LED-quirk-for-Xiaomi-AX9000.patch +++ /dev/null @@ -1,74 +0,0 @@ -From 86624624c2b593c57999780a3838e6a9fe40b30c Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Tue, 11 Jan 2022 00:28:42 +0100 -Subject: [PATCH] qca807x: add a LED quirk for Xiaomi AX9000 - -Xiaomi AX9000 has a single LED for each of 4 gigabit ethernet ports that -are connected to QCA8075, and that LED is connected to the 100M LED pin. - -So, by default it will only work when in 10 or 100Mbit mode, this is quite -annoying and makes no sense(If they have connected it to the 1000Mbit LED -pin then it would have worked for 10/100 by default as well). - -So, to solve this add a check for system compatible as we cant parse if -from DTS in any other way and set the 100M LED to blink on 1000Base-T -as well. - -Signed-off-by: Robert Marko ---- - include/hsl/phy/malibu_phy.h | 2 ++ - src/hsl/phy/malibu_phy.c | 11 +++++++++++ - 2 files changed, 13 insertions(+) - -diff --git a/include/hsl/phy/malibu_phy.h b/include/hsl/phy/malibu_phy.h -index b7354041..ec7a0621 100755 ---- a/include/hsl/phy/malibu_phy.h -+++ b/include/hsl/phy/malibu_phy.h -@@ -94,6 +94,7 @@ extern "C" - #define MALIBU_DAC_CTRL_MASK 0x380 - #define MALIBU_DAC_CTRL_VALUE 0x280 - #define MALIBU_LED_1000_CTRL1_100_10_MASK 0x30 -+#define MALIBU_LED_100_CTRL1_1000_MASK 0x40 - - #define MALIBU_PHY_EEE_ADV_100M 0x0002 - #define MALIBU_PHY_EEE_ADV_1000M 0x0004 -@@ -118,6 +119,7 @@ extern "C" - #define MALIBU_PHY_MMD7_EGRESS_COUNTER_HIGH 0x802d - #define MALIBU_PHY_MMD7_EGRESS_COUNTER_LOW 0x802e - #define MALIBU_PHY_MMD7_EGRESS_ERROR_COUNTER 0x802f -+#define MALIBU_PHY_MMD7_LED_100_CTRL1 0x8074 - #define MALIBU_PHY_MMD7_LED_1000_CTRL1 0x8076 - - -diff --git a/src/hsl/phy/malibu_phy.c b/src/hsl/phy/malibu_phy.c -index 1f4dba15..2bef9fa3 100644 ---- a/src/hsl/phy/malibu_phy.c -+++ b/src/hsl/phy/malibu_phy.c -@@ -12,6 +12,8 @@ - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -+#include -+ - #include "sw.h" - #include "fal_port_ctrl.h" - #include "hsl_api.h" -@@ -2726,6 +2728,15 @@ malibu_phy_hw_init(a_uint32_t dev_id, a_uint32_t port_bmp) - led_status |= MALIBU_LED_1000_CTRL1_100_10_MASK; - malibu_phy_mmd_write(dev_id, phy_addr, MALIBU_PHY_MMD7_NUM, - MALIBU_PHY_MMD7_LED_1000_CTRL1, led_status); -+ if (of_machine_is_compatible("xiaomi,ax9000")) { -+ /* add 1000M link LED behavior for Xiaomi AX9000 */ -+ led_status = malibu_phy_mmd_read(dev_id, phy_addr, MALIBU_PHY_MMD7_NUM, -+ MALIBU_PHY_MMD7_LED_100_CTRL1); -+ led_status &= ~MALIBU_LED_100_CTRL1_1000_MASK; -+ led_status |= MALIBU_LED_100_CTRL1_1000_MASK; -+ malibu_phy_mmd_write(dev_id, phy_addr, MALIBU_PHY_MMD7_NUM, -+ MALIBU_PHY_MMD7_LED_100_CTRL1, led_status); -+ } - /*disable Extended next page*/ - phy_data = malibu_phy_reg_read(dev_id, phy_addr, MALIBU_AUTONEG_ADVERT); - phy_data &= ~MALIBU_EXTENDED_NEXT_PAGE_EN; --- -2.34.1 - diff --git a/qca/qca-ssdk/patches/0009-qca807x-add-a-LED-quirk-for-Xiaomi-AX3600.patch b/qca/qca-ssdk/patches/0009-qca807x-add-a-LED-quirk-for-Xiaomi-AX3600.patch deleted file mode 100644 index c31ea6da9..000000000 --- a/qca/qca-ssdk/patches/0009-qca807x-add-a-LED-quirk-for-Xiaomi-AX3600.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 913514b9177e77836f2c8d61fc498b54f54c6775 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Wed, 26 Jan 2022 14:47:33 +0100 -Subject: [PATCH] qca807x: add a LED quirk for Xiaomi AX3600 - -AX3600 requires the same LED quirk so that PHY LED-s will blink even -once Linux resets the PHY. - -So, just check for its compatible. - -Signed-off-by: Robert Marko ---- - src/hsl/phy/malibu_phy.c | 5 +++-- - 1 file changed, 3 insertions(+), 2 deletions(-) - ---- a/src/hsl/phy/malibu_phy.c -+++ b/src/hsl/phy/malibu_phy.c -@@ -2728,8 +2728,9 @@ malibu_phy_hw_init(a_uint32_t dev_id, a_ - led_status |= MALIBU_LED_1000_CTRL1_100_10_MASK; - malibu_phy_mmd_write(dev_id, phy_addr, MALIBU_PHY_MMD7_NUM, - MALIBU_PHY_MMD7_LED_1000_CTRL1, led_status); -- if (of_machine_is_compatible("xiaomi,ax9000")) { -- /* add 1000M link LED behavior for Xiaomi AX9000 */ -+ /* add 1000M link LED behavior for Xiaomi boards */ -+ if (of_machine_is_compatible("xiaomi,ax9000") || -+ of_machine_is_compatible("xiaomi,ax3600")) { - led_status = malibu_phy_mmd_read(dev_id, phy_addr, MALIBU_PHY_MMD7_NUM, - MALIBU_PHY_MMD7_LED_100_CTRL1); - led_status &= ~MALIBU_LED_100_CTRL1_1000_MASK; diff --git a/qca/qca-ssdk/patches/0012-include-fix-compilation-error-for-parse_uci_option.patch b/qca/qca-ssdk/patches/0012-include-fix-compilation-error-for-parse_uci_option.patch deleted file mode 100644 index 01b8deda9..000000000 --- a/qca/qca-ssdk/patches/0012-include-fix-compilation-error-for-parse_uci_option.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 8e3500df074625b3eb3a8ed4e8e0b1b116f13d0c Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Sat, 7 May 2022 19:03:55 +0200 -Subject: [PATCH] include: fix compilation error for parse_uci_option - -Fix missing include for parse_uci_option - -Signed-off-by: Ansuel Smith ---- - include/ref/ref_uci.h | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/include/ref/ref_uci.h b/include/ref/ref_uci.h -index a42ea153..0906c5ba 100755 ---- a/include/ref/ref_uci.h -+++ b/include/ref/ref_uci.h -@@ -19,6 +19,7 @@ - extern "C" { - #endif /* __cplusplus */ - -+#include - - #if defined(IN_SWCONFIG) - int --- -2.34.1 - From 79c43c6aef6fea1369078e59e21dd2454cfa5926 Mon Sep 17 00:00:00 2001 From: suyuan <175338101@qq.com> Date: Tue, 13 Sep 2022 17:29:21 +0800 Subject: [PATCH 19/19] add qca --- qca/nss-firmware/Makefile | 73 +++++++ qca/qca-nss-cfi/Makefile | 71 ++++++ .../patches/100-remove-noise-logs.patch | 30 +++ qca/qca-nss-clients/Makefile | 115 ++++++++++ qca/qca-nss-clients/files/qca-nss-ipsec | 92 ++++++++ qca/qca-nss-clients/files/qca-nss-mirred.init | 28 +++ qca/qca-nss-clients/files/qca-nss-ovpn.init | 69 ++++++ qca/qca-nss-crypto/Makefile | 62 ++++++ qca/qca-nss-dp/Makefile | 54 +++++ qca/qca-nss-drv/Makefile | 109 +++++++++ qca/qca-nss-drv/files/qca-nss-drv.conf | 6 + qca/qca-nss-drv/files/qca-nss-drv.debug | 26 +++ qca/qca-nss-drv/files/qca-nss-drv.hotplug | 70 ++++++ qca/qca-nss-drv/files/qca-nss-drv.init | 50 +++++ qca/qca-nss-drv/files/qca-nss-drv.sysctl | 3 + qca/qca-nss-ecm/Makefile | 90 ++++++++ qca/qca-nss-ecm/files/ecm_dump.sh | 95 ++++++++ qca/qca-nss-ecm/files/on-demand-down | 6 + qca/qca-nss-ecm/files/qca-nss-ecm.defaults | 28 +++ qca/qca-nss-ecm/files/qca-nss-ecm.firewall | 18 ++ qca/qca-nss-ecm/files/qca-nss-ecm.init | 139 ++++++++++++ qca/qca-nss-ecm/files/qca-nss-ecm.sysctl | 2 + qca/qca-nss-ecm/files/qca-nss-ecm.uci | 2 + .../patches/200-resolve-high-load.patch | 61 ++++++ qca/qca-nss-fw-eip/Makefile | 25 +++ qca/qca-nss-fw-eip/files/ipq60xx/ifpp.bin | Bin 0 -> 12272 bytes qca/qca-nss-fw-eip/files/ipq60xx/ipue.bin | Bin 0 -> 6116 bytes qca/qca-nss-fw-eip/files/ipq60xx/ofpp.bin | Bin 0 -> 6128 bytes qca/qca-nss-fw-eip/files/ipq60xx/opue.bin | Bin 0 -> 4068 bytes qca/qca-nss-fw-eip/files/ipq807x/ifpp.bin | Bin 0 -> 12272 bytes qca/qca-nss-fw-eip/files/ipq807x/ipue.bin | Bin 0 -> 6116 bytes qca/qca-nss-fw-eip/files/ipq807x/ofpp.bin | Bin 0 -> 6128 bytes qca/qca-nss-fw-eip/files/ipq807x/opue.bin | Bin 0 -> 4068 bytes qca/qca-ssdk-shell/Makefile | 48 ++++ qca/qca-ssdk/Makefile | 98 +++++++++ qca/qca-ssdk/files/qca-ssdk | 206 ++++++++++++++++++ 36 files changed, 1676 insertions(+) create mode 100644 qca/nss-firmware/Makefile create mode 100644 qca/qca-nss-cfi/Makefile create mode 100644 qca/qca-nss-cfi/patches/100-remove-noise-logs.patch create mode 100644 qca/qca-nss-clients/Makefile create mode 100644 qca/qca-nss-clients/files/qca-nss-ipsec create mode 100644 qca/qca-nss-clients/files/qca-nss-mirred.init create mode 100644 qca/qca-nss-clients/files/qca-nss-ovpn.init create mode 100644 qca/qca-nss-crypto/Makefile create mode 100644 qca/qca-nss-dp/Makefile create mode 100644 qca/qca-nss-drv/Makefile create mode 100644 qca/qca-nss-drv/files/qca-nss-drv.conf create mode 100644 qca/qca-nss-drv/files/qca-nss-drv.debug create mode 100644 qca/qca-nss-drv/files/qca-nss-drv.hotplug create mode 100644 qca/qca-nss-drv/files/qca-nss-drv.init create mode 100644 qca/qca-nss-drv/files/qca-nss-drv.sysctl create mode 100644 qca/qca-nss-ecm/Makefile create mode 100644 qca/qca-nss-ecm/files/ecm_dump.sh create mode 100644 qca/qca-nss-ecm/files/on-demand-down create mode 100644 qca/qca-nss-ecm/files/qca-nss-ecm.defaults create mode 100644 qca/qca-nss-ecm/files/qca-nss-ecm.firewall create mode 100644 qca/qca-nss-ecm/files/qca-nss-ecm.init create mode 100644 qca/qca-nss-ecm/files/qca-nss-ecm.sysctl create mode 100644 qca/qca-nss-ecm/files/qca-nss-ecm.uci create mode 100644 qca/qca-nss-ecm/patches/200-resolve-high-load.patch create mode 100644 qca/qca-nss-fw-eip/Makefile create mode 100644 qca/qca-nss-fw-eip/files/ipq60xx/ifpp.bin create mode 100644 qca/qca-nss-fw-eip/files/ipq60xx/ipue.bin create mode 100644 qca/qca-nss-fw-eip/files/ipq60xx/ofpp.bin create mode 100644 qca/qca-nss-fw-eip/files/ipq60xx/opue.bin create mode 100644 qca/qca-nss-fw-eip/files/ipq807x/ifpp.bin create mode 100644 qca/qca-nss-fw-eip/files/ipq807x/ipue.bin create mode 100644 qca/qca-nss-fw-eip/files/ipq807x/ofpp.bin create mode 100644 qca/qca-nss-fw-eip/files/ipq807x/opue.bin create mode 100644 qca/qca-ssdk-shell/Makefile create mode 100644 qca/qca-ssdk/Makefile create mode 100644 qca/qca-ssdk/files/qca-ssdk diff --git a/qca/nss-firmware/Makefile b/qca/nss-firmware/Makefile new file mode 100644 index 000000000..b56a3652f --- /dev/null +++ b/qca/nss-firmware/Makefile @@ -0,0 +1,73 @@ +# +# Copyright (C) 2021 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +include $(TOPDIR)/rules.mk + +PKG_NAME:=nss-firmware +PKG_RELEASE:=1 + +PKG_SOURCE_PROTO:=git +PKG_SOURCE_DATE:=2021-09-14 +PKG_SOURCE_URL:=https://github.com/quic/qca-sdk-nss-fw.git +PKG_SOURCE_VERSION:=b06171cb0d14360c90a4b8f9f835dc1c4647ea07 +PKG_MIRROR_HASH:=e851d4f6af8aaccbc34a05bc007991a88287913f17c5d9f0172a00745aed6e48 + +PKG_LICENSE_FILES:=LICENSE.md + +PKG_MAINTAINER:=Robert Marko + +include $(INCLUDE_DIR)/package.mk + +VERSION_PATH=$(PKG_BUILD_DIR)/QCA_Networking_2021.SPF_11.4/CS + +define Package/nss-firmware-default + SECTION:=firmware + CATEGORY:=Firmware + URL:=$(PKG_SOURCE_URL) +endef + +define Package/nss-firmware-ipq6018 +$(Package/nss-firmware-default) + DEPENDS:=@TARGET_ipq60xx + TITLE:=NSS firmware for IPQ6018 devices + NSS_ARCHIVE:=$(VERSION_PATH)/IPQ6018.ATH.11.4/BIN-NSS.CP.11.4.0.5-5-R.tar.bz2 +endef + +define Package/nss-firmware-ipq8074 +$(Package/nss-firmware-default) + DEPENDS:=@TARGET_ipq807x + TITLE:=NSS firmware for IPQ8074 devices + NSS_ARCHIVE:=$(VERSION_PATH)/IPQ8074.ATH.11.4/BIN-NSS.HK.11.4.0.5-5-R.tar.bz2 +endef + +define Build/Compile + true +endef + +define Package/nss-firmware-ipq6018/install + mkdir -p $(PKG_BUILD_DIR)/IPQ6018 + $(TAR) -C $(PKG_BUILD_DIR)/IPQ6018 -xf $(NSS_ARCHIVE) --strip-components=1 + $(INSTALL_DIR) $(1)/lib/firmware/ + $(INSTALL_DATA) \ + $(PKG_BUILD_DIR)/IPQ6018/retail_router0.bin \ + $(1)/lib/firmware/qca-nss0.bin +endef + +define Package/nss-firmware-ipq8074/install + mkdir -p $(PKG_BUILD_DIR)/IPQ8074 + $(TAR) -C $(PKG_BUILD_DIR)/IPQ8074 -xf $(NSS_ARCHIVE) --strip-components=1 + $(INSTALL_DIR) $(1)/lib/firmware/ + $(INSTALL_DATA) \ + $(PKG_BUILD_DIR)/IPQ8074/retail_router0.bin \ + $(1)/lib/firmware/qca-nss0.bin + $(INSTALL_DATA) \ + $(PKG_BUILD_DIR)/IPQ8074/retail_router1.bin \ + $(1)/lib/firmware/qca-nss1.bin +endef + +$(eval $(call BuildPackage,nss-firmware-ipq6018)) +$(eval $(call BuildPackage,nss-firmware-ipq8074)) diff --git a/qca/qca-nss-cfi/Makefile b/qca/qca-nss-cfi/Makefile new file mode 100644 index 000000000..64f7bd7ab --- /dev/null +++ b/qca/qca-nss-cfi/Makefile @@ -0,0 +1,71 @@ +include $(TOPDIR)/rules.mk + +PKG_NAME:=qca-nss-cfi +PKG_RELEASE:=1 + +PKG_SOURCE_PROTO:=git +PKG_SOURCE_DATE:=2021-03-22 +PKG_SOURCE_URL:=https://source.codeaurora.org/quic/qsdk/oss/lklm/nss-cfi +PKG_SOURCE_VERSION:=73f2e5f5bf93cc244036ce5641faf9f859692cdf +PKG_MIRROR_HASH:=8c8edc9b8d8c68fdd14640152245013a93c123957b6b338c06f266f6c9db8cbd + +include $(INCLUDE_DIR)/kernel.mk +include $(INCLUDE_DIR)/package.mk + +# v1.0 is for Akronite +# v2.0 is for Hawkeye/Cypress/Maple +ifneq (, $(findstring $(BOARD), ipq50xx ipq60xx ipq807x)) + CFI_OCF_DIR:=ocf/v2.0 + CFI_CRYPTOAPI_DIR:=cryptoapi/v2.0 +else + CFI_CRYPTOAPI_DIR:=cryptoapi/v1.1 + CFI_OCF_DIR:=ocf/v1.0 + CFI_IPSEC_DIR:=ipsec/v1.0 +endif + +define KernelPackage/qca-nss-cfi-cryptoapi + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + DEPENDS:=@TARGET_ipq60xx +kmod-crypto-authenc +kmod-qca-nss-crypto + TITLE:=Kernel driver for NSS cfi + FILES:=$(PKG_BUILD_DIR)/$(CFI_CRYPTOAPI_DIR)/qca-nss-cfi-cryptoapi.ko + AUTOLOAD:=$(call AutoLoad,59,qca-nss-cfi-cryptoapi) +endef + +define Build/InstallDev + $(INSTALL_DIR) $(1)/usr/include/qca-nss-cfi + $(CP) $(PKG_BUILD_DIR)/$(CFI_CRYPTOAPI_DIR)/../exports/* $(1)/usr/include/qca-nss-cfi + $(CP) $(PKG_BUILD_DIR)/include/* $(1)/usr/include/qca-nss-cfi +endef + +define KernelPackage/qca-nss-cfi/Description +This package contains a NSS cfi driver for QCA chipset +endef + +EXTRA_CFLAGS+= \ + -DCONFIG_NSS_DEBUG_LEVEL=4 \ + -I$(LINUX_DIR)/crypto/ocf \ + -I$(STAGING_DIR)/usr/include/qca-nss-crypto \ + -I$(STAGING_DIR)/usr/include/crypto \ + -I$(STAGING_DIR)/usr/include/qca-nss-drv + +ifneq (, $(findstring $(BOARD), ipq50xx ipq60xx ipq807x)) +EXTRA_CFLAGS+= -I$(STAGING_DIR)/usr/include/qca-nss-clients +endif + +define Build/Compile + $(MAKE) -C "$(LINUX_DIR)" \ + CROSS_COMPILE="$(TARGET_CROSS)" \ + EXTRA_CFLAGS="$(EXTRA_CFLAGS)" \ + CFI_CRYPTOAPI_DIR=$(CFI_CRYPTOAPI_DIR) \ + CFI_IPSEC_DIR=$(CFI_IPSEC_DIR) \ + CFI_OCF_DIR=$(CFI_OCF_DIR) \ + $(KERNEL_MAKE_FLAGS) \ + M="$(PKG_BUILD_DIR)" \ + SoC="$(BOARD)_64" \ + "cryptoapi=y" \ + modules +endef + +$(eval $(call KernelPackage,qca-nss-cfi-cryptoapi)) diff --git a/qca/qca-nss-cfi/patches/100-remove-noise-logs.patch b/qca/qca-nss-cfi/patches/100-remove-noise-logs.patch new file mode 100644 index 000000000..085aeaf24 --- /dev/null +++ b/qca/qca-nss-cfi/patches/100-remove-noise-logs.patch @@ -0,0 +1,30 @@ +--- a/cryptoapi/v2.0/nss_cryptoapi_ahash.c ++++ b/cryptoapi/v2.0/nss_cryptoapi_ahash.c +@@ -449,9 +449,12 @@ int nss_cryptoapi_ahash_digest(struct ahash_request *req) + int nss_cryptoapi_ahash_export(struct ahash_request *req, void *out) + { + struct nss_cryptoapi_ctx *ctx __attribute__((unused)) = crypto_tfm_ctx(req->base.tfm); ++ struct nss_cryptoapi_req_ctx *rctx = ahash_request_ctx(req); ++ struct nss_cryptoapi_req_ctx *state = out; ++ ++ *state = *rctx; + +- nss_cfi_warn("%px: ahash .export is not supported", ctx); +- return -ENOSYS; ++ return 0; + }; + + /* +@@ -464,7 +467,10 @@ int nss_cryptoapi_ahash_export(struct ahash_request *req, void *out) + int nss_cryptoapi_ahash_import(struct ahash_request *req, const void *in) + { + struct nss_cryptoapi_ctx *ctx __attribute__((unused)) = crypto_tfm_ctx(req->base.tfm); ++ struct nss_cryptoapi_req_ctx *rctx = ahash_request_ctx(req); ++ const struct nss_cryptoapi_req_ctx *state = in; ++ ++ *rctx = *state; + +- nss_cfi_warn("%px: ahash .import is not supported", ctx); +- return -ENOSYS; ++ return 0; + } diff --git a/qca/qca-nss-clients/Makefile b/qca/qca-nss-clients/Makefile new file mode 100644 index 000000000..2d9b82644 --- /dev/null +++ b/qca/qca-nss-clients/Makefile @@ -0,0 +1,115 @@ +include $(TOPDIR)/rules.mk + +PKG_NAME:=qca-nss-clients +PKG_RELEASE:=1 + +PKG_SOURCE_PROTO:=git +PKG_SOURCE_DATE:=2021-12-01 +PKG_SOURCE_URL:=https://source.codeaurora.org/quic/qsdk/oss/lklm/nss-clients +PKG_SOURCE_VERSION:=24fdeb3357cf4135f43add427e2b318139b6a1b9 +PKG_MIRROR_HASH:=c46b9cdf4bbd394507a92dc39f9183735a61c7ccdfed38832c525ed6d2381eb6 + +include $(INCLUDE_DIR)/kernel.mk +include $(INCLUDE_DIR)/package.mk + +define KernelPackage/qca-nss-drv-pppoe + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=Kernel driver for NSS PPPoE connection manager + DEPENDS:=@TARGET_ipq60xx +kmod-bonding +kmod-pppoe +kmod-qca-nss-drv + FILES:=$(PKG_BUILD_DIR)/pppoe/qca-nss-pppoe.ko + AUTOLOAD:=$(call AutoLoad,51,qca-nss-pppoe) +endef + +define KernelPackage/qca-nss-drv-pppoe/Description +Kernel modules for NSS connection manager - Support for PPPoE +endef + +define KernelPackage/qca-nss-drv-bridge-mgr + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=Kernel driver for NSS bridge manager + DEPENDS:=@TARGET_ipq60xx +kmod-bonding +kmod-qca-nss-drv-vlan-mgr + FILES:=$(PKG_BUILD_DIR)/bridge/qca-nss-bridge-mgr.ko + AUTOLOAD:=$(call AutoLoad,51,qca-nss-bridge-mgr) +endef + +define KernelPackage/qca-nss-drv-bridge-mgr/Description +Kernel modules for NSS bridge manager +endef + +define KernelPackage/qca-nss-drv-vlan-mgr + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=Kernel driver for NSS vlan manager + DEPENDS:=@TARGET_ipq60xx +kmod-bonding +kmod-qca-nss-drv + FILES:=$(PKG_BUILD_DIR)/vlan/qca-nss-vlan.ko + AUTOLOAD:=$(call AutoLoad,51,qca-nss-vlan) +endef + +define KernelPackage/qca-nss-drv-vlan-mgr/Description +Kernel modules for NSS vlan manager +endef + +define KernelPackage/qca-nss-drv-wifi-meshmgr + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + DEPENDS:=@TARGET_ipq60xx +kmod-qca-nss-drv + TITLE:=NSS WiFi-Mesh Manager for QCA NSS driver + FILES:=$(PKG_BUILD_DIR)/wifi_meshmgr/qca-nss-wifi-meshmgr.ko + AUTOLOAD:=$(call AutoLoad,51,qca-nss-wifi-meshmgr) +endef + +define KernelPackage/qca-nss-drv-wifi-meshmgr/Description +Kernel module for NSS WiFi Mesh manager +endef + +EXTRA_CFLAGS+= \ + -I$(STAGING_DIR)/usr/include/qca-nss-cfi \ + -I$(STAGING_DIR)/usr/include/qca-nss-crypto \ + -I$(STAGING_DIR)/usr/include/qca-nss-drv \ + -I$(STAGING_DIR)/usr/include/qca-nss-gmac \ + -I$(STAGING_DIR)/usr/include/qca-ssdk \ + -I$(STAGING_DIR)/usr/include/qca-ssdk/fal \ + -I$(STAGING_DIR)/usr/include/nat46 + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-pppoe),) +MAKE_OPTS+=pppoe=y +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-vlan-mgr),) +MAKE_OPTS+=vlan-mgr=y +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-bridge-mgr),) +MAKE_OPTS+=bridge-mgr=y +endif + +ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-wifi-meshmgr),) +MAKE_OPTS+=wifi-meshmgr=y +endif + +define Build/InstallDev + $(INSTALL_DIR) $(1)/usr/include/qca-nss-clients + $(CP) $(PKG_BUILD_DIR)/netlink/include/* $(1)/usr/include/qca-nss-clients/ + $(CP) $(PKG_BUILD_DIR)/exports/* $(1)/usr/include/qca-nss-clients/ +endef + +define Build/Compile + $(MAKE) -C "$(LINUX_DIR)" $(strip $(MAKE_OPTS)) \ + CROSS_COMPILE="$(TARGET_CROSS)" \ + EXTRA_CFLAGS="$(EXTRA_CFLAGS)" \ + $(KERNEL_MAKE_FLAGS) \ + M="$(PKG_BUILD_DIR)" \ + SoC="$(BOARD)_64" \ + modules +endef + +$(eval $(call KernelPackage,qca-nss-drv-pppoe)) +$(eval $(call KernelPackage,qca-nss-drv-vlan-mgr)) +$(eval $(call KernelPackage,qca-nss-drv-bridge-mgr)) +$(eval $(call KernelPackage,qca-nss-drv-wifi-meshmgr)) diff --git a/qca/qca-nss-clients/files/qca-nss-ipsec b/qca/qca-nss-clients/files/qca-nss-ipsec new file mode 100644 index 000000000..bb202e8e7 --- /dev/null +++ b/qca/qca-nss-clients/files/qca-nss-ipsec @@ -0,0 +1,92 @@ +#!/bin/sh /etc/rc.common +# +# Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +NSS_IPSEC_LOG_FILE=/tmp/.nss_ipsec_log +NSS_IPSEC_LOG_STR_ECM="ECM_Loaded" + +ecm_load () { + if [ ! -d /sys/module/ecm ]; then + /etc/init.d/qca-nss-ecm start + if [ -d /sys/module/ecm ]; then + echo ${NSS_IPSEC_LOG_STR_ECM} >> ${NSS_IPSEC_LOG_FILE} + fi + fi +} + +ecm_unload () { + if [ -f /tmp/.nss_ipsec_log ]; then + str=`grep ${NSS_IPSEC_LOG_STR_ECM} ${NSS_IPSEC_LOG_FILE}` + if [[ $str == ${NSS_IPSEC_LOG_STR_ECM} ]]; then + /etc/init.d/qca-nss-ecm stop + `sed 's/${NSS_IPSEC_LOG_STR_ECM}/ /g' $NSS_IPSEC_LOG_FILE > $NSS_IPSEC_LOG_FILE` + fi + fi +} + +ecm_disable() { + + if [ ! -d /sys/module/ecm ]; then + return; + fi + + echo 1 > /sys/kernel/debug/ecm/front_end_ipv4_stop + echo 1 > /sys/kernel/debug/ecm/front_end_ipv6_stop + echo 1 > /sys/kernel/debug/ecm/ecm_db/defunct_all + sleep 2 +} + +ecm_enable() { + if [ ! -d /sys/module/ecm ]; then + return; + fi + + echo 0 > /sys/kernel/debug/ecm/ecm_db/defunct_all + echo 0 > /sys/kernel/debug/ecm/front_end_ipv4_stop + echo 0 > /sys/kernel/debug/ecm/front_end_ipv6_stop +} + +start() { + ecm_load + + local kernel_version=$(uname -r) + + insmod /lib/modules/${kernel_version}/qca-nss-ipsec-klips.ko + if [ "$?" -gt 0 ]; then + echo "Failed to load plugin. Please start ecm if not done already" + ecm_enable + return + fi + + /etc/init.d/ipsec start + sleep 2 + ipsec eroute + + ecm_enable +} + +stop() { + ecm_disable + + /etc/init.d/ipsec stop + rmmod qca-nss-ipsec-klips + + ecm_unload +} + +restart() { + stop + start +} diff --git a/qca/qca-nss-clients/files/qca-nss-mirred.init b/qca/qca-nss-clients/files/qca-nss-mirred.init new file mode 100644 index 000000000..1f931f090 --- /dev/null +++ b/qca/qca-nss-clients/files/qca-nss-mirred.init @@ -0,0 +1,28 @@ +#!/bin/sh /etc/rc.common + +########################################################################### +# Copyright (c) 2019, The Linux Foundation. All rights reserved. +# Permission to use, copy, modify, and/or distribute this software for +# any purpose with or without fee is hereby granted, provided that the +# above copyright notice and this permission notice appear in all copies. +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT +# OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +########################################################################### + +restart() { + rmmod act_nssmirred.ko + insmod act_nssmirred.ko +} + +start() { + insmod act_nssmirred.ko +} + +stop() { + rmmod act_nssmirred.ko +} diff --git a/qca/qca-nss-clients/files/qca-nss-ovpn.init b/qca/qca-nss-clients/files/qca-nss-ovpn.init new file mode 100644 index 000000000..622e295ee --- /dev/null +++ b/qca/qca-nss-clients/files/qca-nss-ovpn.init @@ -0,0 +1,69 @@ +#!/bin/sh /etc/rc.common + +########################################################################### +# Copyright (c) 2019, The Linux Foundation. All rights reserved. +# Permission to use, copy, modify, and/or distribute this software for +# any purpose with or without fee is hereby granted, provided that the +# above copyright notice and this permission notice appear in all copies. +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT +# OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +########################################################################### + +ecm_disable() { + if [ ! -d /sys/module/ecm ]; then + return + fi + + echo 1 > /sys/kernel/debug/ecm/front_end_ipv4_stop + echo 1 > /sys/kernel/debug/ecm/front_end_ipv6_stop + echo 1 > /sys/kernel/debug/ecm/ecm_db/defunct_all + sleep 2 +} + +ecm_enable() { + if [ ! -d /sys/module/ecm ]; then + return + fi + + echo 0 > /sys/kernel/debug/ecm/ecm_db/defunct_all + echo 0 > /sys/kernel/debug/ecm/front_end_ipv4_stop + echo 0 > /sys/kernel/debug/ecm/front_end_ipv6_stop +} + +restart() { + ecm_disable + + /etc/init.d/openvpn stop + rmmod qca-nss-ovpn-link + rmmod qca-nss-ovpn-mgr + + insmod qca-nss-ovpn-mgr + insmod qca-nss-ovpn-link + + if [ "$?" -gt 0 ]; then + echo "Failed to load plugin. Please start ecm if not done already" + ecm_enable + return + fi + + ecm_enable +} + +start() { + restart +} + +stop() { + ecm_disable + + /etc/init.d/openvpn stop + rmmod qca-nss-ovpn-link + rmmod qca-nss-ovpn-mgr + + ecm_enable +} diff --git a/qca/qca-nss-crypto/Makefile b/qca/qca-nss-crypto/Makefile new file mode 100644 index 000000000..7b4baec25 --- /dev/null +++ b/qca/qca-nss-crypto/Makefile @@ -0,0 +1,62 @@ +include $(TOPDIR)/rules.mk + +PKG_NAME:=qca-nss-crypto +PKG_RELEASE:=1 + +PKG_SOURCE_PROTO:=git +PKG_SOURCE_DATE:=2021-03-22 +PKG_SOURCE_URL:=https://source.codeaurora.org/quic/qsdk/oss/lklm/nss-crypto +PKG_SOURCE_VERSION:=2271a3a66f7e8284d42a9e787ddec6f24a1d2e15 +PKG_MIRROR_HASH:=7e70ffa2cbddc3830376f25047575db8867f2027b2ae3a7276d87ead3e95eb80 + +include $(INCLUDE_DIR)/kernel.mk +include $(INCLUDE_DIR)/package.mk + +# v1.0 is for Akronite +# v2.0 is for Hawkeye/Cypress/Maple +ifneq (, $(findstring $(BOARD), ipq50xx ipq60xx ipq807x)) +NSS_CRYPTO_DIR:=v2.0 +else +NSS_CRYPTO_DIR:=v1.0 +endif + +define KernelPackage/qca-nss-crypto + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=Kernel driver for NSS crypto driver + FILES:= \ + $(PKG_BUILD_DIR)/$(NSS_CRYPTO_DIR)/src/qca-nss-crypto.ko \ + $(PKG_BUILD_DIR)/$(NSS_CRYPTO_DIR)/tool/qca-nss-crypto-tool.ko + DEPENDS:=@TARGET_ipq60xx +kmod-qca-nss-drv + AUTOLOAD:=$(call AutoLoad,52,qca-nss-crypto) +endef + +define KernelPackage/qca-nss-crypto/Description +This package contains a NSS crypto driver for QCA chipset +endef + +define Build/InstallDev + $(INSTALL_DIR) $(1)/usr/include/qca-nss-crypto + $(CP) $(PKG_BUILD_DIR)/$(NSS_CRYPTO_DIR)/include/* $(1)/usr/include/qca-nss-crypto +endef + +EXTRA_CFLAGS+= \ + -DCONFIG_NSS_DEBUG_LEVEL=4 \ + -I$(STAGING_DIR)/usr/include/qca-nss-crypto \ + -I$(STAGING_DIR)/usr/include/qca-nss-drv \ + -I$(PKG_BUILD_DIR)/$(NSS_CRYPTO_DIR)/include \ + -I$(PKG_BUILD_DIR)/$(NSS_CRYPTO_DIR)/src + +define Build/Compile + $(MAKE) -C "$(LINUX_DIR)" \ + NSS_CRYPTO_DIR=$(NSS_CRYPTO_DIR) \ + CROSS_COMPILE="$(TARGET_CROSS)" \ + EXTRA_CFLAGS="$(EXTRA_CFLAGS)" \ + $(KERNEL_MAKE_FLAGS) \ + M="$(PKG_BUILD_DIR)" \ + SoC="$(BOARD)_64" \ + modules +endef + +$(eval $(call KernelPackage,qca-nss-crypto)) diff --git a/qca/qca-nss-dp/Makefile b/qca/qca-nss-dp/Makefile new file mode 100644 index 000000000..4f85a43d1 --- /dev/null +++ b/qca/qca-nss-dp/Makefile @@ -0,0 +1,54 @@ +include $(TOPDIR)/rules.mk + +PKG_NAME:=qca-nss-dp +PKG_RELEASE:=1 + +PKG_SOURCE_PROTO:=git +PKG_SOURCE_DATE:=2021-03-26 +PKG_SOURCE_URL:=https://source.codeaurora.org/quic/qsdk/oss/lklm/nss-dp +PKG_SOURCE_VERSION:=e0c89348d5ad99559ce2fbe15d37b3b5bc66aa03 +PKG_MIRROR_HASH:=f369f0c3b33b5f4ad6d0a6ad6ac5495f63c9ecaf94e4e7fa345169f3e44fcf45 + +include $(INCLUDE_DIR)/kernel.mk +include $(INCLUDE_DIR)/package.mk + +define KernelPackage/qca-nss-dp + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + DEPENDS:=@TARGET_ipq60xx +kmod-qca-ssdk + TITLE:=Kernel driver for NSS data plane + FILES:=$(PKG_BUILD_DIR)/qca-nss-dp.ko + AUTOLOAD:=$(call AutoLoad,31,qca-nss-dp) +endef + +define KernelPackage/qca-nss-dp/Description +This package contains a NSS data plane driver for QCA chipset +endef + +define Build/InstallDev + mkdir -p $(1)/usr/include/qca-nss-dp + $(CP) $(PKG_BUILD_DIR)/exports/* $(1)/usr/include/qca-nss-dp/ +endef + +EXTRA_CFLAGS+= \ + -I$(STAGING_DIR)/usr/include/qca-ssdk + +NSS_DP_HAL_DIR:=$(PKG_BUILD_DIR)/hal + +define Build/Configure + $(LN) $(NSS_DP_HAL_DIR)/arch/$(BOARD)/nss_$(BOARD).h \ + $(PKG_BUILD_DIR)/exports/nss_dp_arch.h +endef + +define Build/Compile + $(MAKE) -C "$(LINUX_DIR)" \ + CROSS_COMPILE="$(TARGET_CROSS)" \ + EXTRA_CFLAGS="$(EXTRA_CFLAGS)" \ + $(KERNEL_MAKE_FLAGS) \ + M="$(PKG_BUILD_DIR)" \ + SoC="$(BOARD)_64" \ + modules +endef + +$(eval $(call KernelPackage,qca-nss-dp)) diff --git a/qca/qca-nss-drv/Makefile b/qca/qca-nss-drv/Makefile new file mode 100644 index 000000000..4fce341e5 --- /dev/null +++ b/qca/qca-nss-drv/Makefile @@ -0,0 +1,109 @@ +include $(TOPDIR)/rules.mk + +PKG_NAME:=qca-nss-drv +PKG_RELEASE:=1 + +PKG_SOURCE_PROTO:=git +PKG_SOURCE_DATE:=2021-11-12 +PKG_SOURCE_URL:=https://source.codeaurora.org/quic/qsdk/oss/lklm/nss-drv +PKG_SOURCE_VERSION:=5d47e4261bae9bc343ce50402011ee64729684f9 +PKG_MIRROR_HASH:=832a6f3af2d37f3e38231a3df41d5d7d9c7abc4975c0445f962146e8950a9433 + +include $(INCLUDE_DIR)/kernel.mk +include $(INCLUDE_DIR)/package.mk + +define KernelPackage/qca-nss-drv + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + DEPENDS:=@TARGET_ipq60xx +kmod-qca-nss-dp + TITLE:=Kernel driver for NSS (core driver) + FILES:=$(PKG_BUILD_DIR)/qca-nss-drv.ko + AUTOLOAD:=$(call AutoLoad,32,qca-nss-drv) +endef + +define KernelPackage/qca-nss-drv/install + $(INSTALL_DIR) $(1)/lib/debug + $(INSTALL_DIR) $(1)/etc/init.d + $(INSTALL_DIR) $(1)/etc/sysctl.d + $(INSTALL_DIR) $(1)/etc/config + + $(INSTALL_BIN) ./files/qca-nss-drv.debug $(1)/lib/debug/qca-nss-drv + $(INSTALL_BIN) ./files/qca-nss-drv.init $(1)/etc/init.d/qca-nss-drv + $(INSTALL_BIN) ./files/qca-nss-drv.sysctl $(1)/etc/sysctl.d/qca-nss-drv.conf + $(INSTALL_BIN) ./files/qca-nss-drv.conf $(1)/etc/config/nss +endef + +define KernelPackage/qca-nss-drv/Description +This package contains a NSS driver for QCA chipset +endef + +define Build/InstallDev + mkdir -p $(1)/usr/include/qca-nss-drv + $(CP) $(PKG_BUILD_DIR)/exports/* $(1)/usr/include/qca-nss-drv/ +endef + +EXTRA_CFLAGS+= -Wno-unused-variable \ + -I$(STAGING_DIR)/usr/include/qca-nss-dp \ + -I$(STAGING_DIR)/usr/include/qca-ssdk + +ifeq ($(CONFIG_KERNEL_IPQ_MEM_PROFILE),256) +EXTRA_CFLAGS+= -DNSS_MEM_PROFILE_LOW +endif + +ifeq ($(CONFIG_KERNEL_IPQ_MEM_PROFILE),512) +EXTRA_CFLAGS+= -DNSS_MEM_PROFILE_MEDIUM +endif + +ifeq ($(CONFIG_KERNEL_SKB_FIXED_SIZE_2K),y) +EXTRA_CFLAGS+= -DNSS_SKB_FIXED_SIZE_2K +endif + +DRV_MAKE_OPTS:= +ifeq ($(CONFIG_KERNEL_IPQ_MEM_PROFILE),256) +DRV_MAKE_OPTS+= \ + NSS_DRV_C2C_ENABLE=n \ + NSS_DRV_CAPWAP_ENABLE=n \ + NSS_DRV_CLMAP_ENABLE=n \ + NSS_DRV_CRYPTO_ENABLE=n \ + NSS_DRV_DTLS_ENABLE=n \ + NSS_DRV_GRE_ENABLE=n \ + NSS_DRV_GRE_REDIR_ENABLE=n \ + NSS_DRV_GRE_TUNNEL_ENABLE=n \ + NSS_DRV_IGS_ENABLE=n \ + NSS_DRV_IPSEC_ENABLE=n \ + NSS_DRV_LAG_ENABLE=n \ + NSS_DRV_L2TP_ENABLE=n \ + NSS_DRV_MAPT_ENABLE=n \ + NSS_DRV_OAM_ENABLE=n \ + NSS_DRV_PPTP_ENABLE=n \ + NSS_DRV_PORTID_ENABLE=n \ + NSS_DRV_PVXLAN_ENABLE=n \ + NSS_DRV_QRFS_ENABLE=n \ + NSS_DRV_QVPN_ENABLE=n \ + NSS_DRV_RMNET_ENABLE=n \ + NSS_DRV_SHAPER_ENABLE=n \ + NSS_DRV_SJACK_ENABLE=n \ + NSS_DRV_TLS_ENABLE=n \ + NSS_DRV_TRUSTSEC_ENABLE=n \ + NSS_DRV_TSTAMP_ENABLE=n \ + NSS_DRV_TUN6RD_ENABLE=n \ + NSS_DRV_TUNIPIP6_ENABLE=n \ + NSS_DRV_VXLAN_ENABLE=n +endif + +define Build/Configure + $(LN) arch/nss_$(BOARD)_64.h $(PKG_BUILD_DIR)/exports/nss_arch.h +endef + +define Build/Compile + $(MAKE) -C "$(LINUX_DIR)" $(strip $(DRV_MAKE_OPTS)) \ + CROSS_COMPILE="$(TARGET_CROSS)" \ + EXTRA_CFLAGS="$(EXTRA_CFLAGS)" \ + $(KERNEL_MAKE_FLAGS) \ + M="$(PKG_BUILD_DIR)" \ + SoC="$(BOARD)_64" \ + modules +endef + +$(eval $(call KernelPackage,qca-nss-drv)) diff --git a/qca/qca-nss-drv/files/qca-nss-drv.conf b/qca/qca-nss-drv/files/qca-nss-drv.conf new file mode 100644 index 000000000..a8a1fbf40 --- /dev/null +++ b/qca/qca-nss-drv/files/qca-nss-drv.conf @@ -0,0 +1,6 @@ +config nss_firmware 'qca_nss_0' + +config nss_firmware 'qca_nss_1' + +config general + option enable_rps '1' diff --git a/qca/qca-nss-drv/files/qca-nss-drv.debug b/qca/qca-nss-drv/files/qca-nss-drv.debug new file mode 100644 index 000000000..5d435c3a7 --- /dev/null +++ b/qca/qca-nss-drv/files/qca-nss-drv.debug @@ -0,0 +1,26 @@ +#!/bin/sh /sbin/sysdebug +# +# Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +# + +log cat /sys/kernel/debug/qca-nss-drv/stats/pppoe +log cat /sys/kernel/debug/qca-nss-drv/stats/n2h +log cat /sys/kernel/debug/qca-nss-drv/stats/ipv6 +log cat /sys/kernel/debug/qca-nss-drv/stats/ipv4 +log cat /sys/kernel/debug/qca-nss-drv/stats/gmac +log cat /sys/kernel/debug/qca-nss-drv/stats/drv +log cat /sys/kernel/debug/qca-nss-drv/stats/wifi +log cat /sys/kernel/debug/qca-nss-drv/stats/wifi_if +log cat /sys/kernel/debug/qca-nss-drv/stats/eth_rx diff --git a/qca/qca-nss-drv/files/qca-nss-drv.hotplug b/qca/qca-nss-drv/files/qca-nss-drv.hotplug new file mode 100644 index 000000000..1e4813838 --- /dev/null +++ b/qca/qca-nss-drv/files/qca-nss-drv.hotplug @@ -0,0 +1,70 @@ +#!/bin/sh +# +# Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +# + +KERNEL=`uname -r` +case "${KERNEL}" in + 3.4*) + select_or_load=load_nss_fw + ;; + *) + select_or_load=select_nss_fw + ;; +esac + +load_nss_fw () { + ls -l $1 | awk ' { print $9,$5 } '> /dev/console + echo 1 > /sys/class/firmware/$DEVICENAME/loading + cat $1 > /sys/class/firmware/$DEVICENAME/data + echo 0 > /sys/class/firmware/$DEVICENAME/loading +} + +select_nss_fw () { + rm -f /lib/firmware/$DEVICENAME + ln -s $1 /lib/firmware/$DEVICENAME + ls -l /lib/firmware/$DEVICENAME | awk ' { print $9,$5 } '> /dev/console +} + +[ "$ACTION" != "add" ] && exit + +# dev name for UCI, since it doesn't let you use . or - +SDEVNAME=$(echo ${DEVICENAME} | sed s/[.-]/_/g) + +SELECTED_FW=$(uci get nss.${SDEVNAME}.firmware 2>/dev/null) +[ -e "${SELECTED_FW}" ] && { + $select_or_load ${SELECTED_FW} + exit +} + +case $DEVICENAME in + qca-nss0* | qca-nss.0*) + if [ -e /lib/firmware/qca-nss0-enterprise.bin ] ; then + $select_or_load /lib/firmware/qca-nss0-enterprise.bin + else + $select_or_load /lib/firmware/qca-nss0-retail.bin + fi + exit + ;; + qca-nss1* | qca-nss.1*) + if [ -e /lib/firmware/qca-nss1-enterprise.bin ] ; then + $select_or_load /lib/firmware/qca-nss1-enterprise.bin + else + $select_or_load /lib/firmware/qca-nss1-retail.bin + fi + exit + ;; +esac + diff --git a/qca/qca-nss-drv/files/qca-nss-drv.init b/qca/qca-nss-drv/files/qca-nss-drv.init new file mode 100644 index 000000000..de12cb6d1 --- /dev/null +++ b/qca/qca-nss-drv/files/qca-nss-drv.init @@ -0,0 +1,50 @@ +#!/bin/sh /etc/rc.common +# +# Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +# + +START=70 + +enable_rps() { + irq_nss_rps=`grep nss_queue1 /proc/interrupts | cut -d ':' -f 1 | tr -d ' '` + for entry in $irq_nss_rps + do + echo 2 > /proc/irq/$entry/smp_affinity + done + + irq_nss_rps=`grep nss_queue2 /proc/interrupts | cut -d ':' -f 1 | tr -d ' '` + for entry in $irq_nss_rps + do + echo 4 > /proc/irq/$entry/smp_affinity + done + + irq_nss_rps=`grep nss_queue3 /proc/interrupts | cut -d ':' -f 1 | tr -d ' '` + for entry in $irq_nss_rps + do + echo 8 > /proc/irq/$entry/smp_affinity + done + + # Enable NSS RPS + sysctl -w dev.nss.rps.enable=1 >/dev/null 2>/dev/null + +} + + +start() { + local rps_enabled="$(uci_get nss @general[0] enable_rps)" + if [ "$rps_enabled" -eq 1 ]; then + enable_rps + fi +} diff --git a/qca/qca-nss-drv/files/qca-nss-drv.sysctl b/qca/qca-nss-drv/files/qca-nss-drv.sysctl new file mode 100644 index 000000000..0276bba12 --- /dev/null +++ b/qca/qca-nss-drv/files/qca-nss-drv.sysctl @@ -0,0 +1,3 @@ +# Default Number of connection configuration +dev.nss.ipv4cfg.ipv4_conn=4096 +dev.nss.ipv6cfg.ipv6_conn=4096 diff --git a/qca/qca-nss-ecm/Makefile b/qca/qca-nss-ecm/Makefile new file mode 100644 index 000000000..a32cc87c5 --- /dev/null +++ b/qca/qca-nss-ecm/Makefile @@ -0,0 +1,90 @@ +include $(TOPDIR)/rules.mk + +PKG_NAME:=qca-nss-ecm +PKG_RELEASE:=1 + +PKG_SOURCE_PROTO:=git +PKG_SOURCE_DATE:=2021-11-09 +PKG_SOURCE_URL:=https://source.codeaurora.org/quic/qsdk/oss/lklm/qca-nss-ecm +PKG_SOURCE_VERSION:=33122aebdd54803b5817065060289d6af5dfd3ba +PKG_MIRROR_HASH:=a857db70804e19a20efef2d1ad519fe26bce3a45decd6ae3bb4a26d53f464a8d + +include $(INCLUDE_DIR)/kernel.mk +include $(INCLUDE_DIR)/package.mk + +define KernelPackage/qca-nss-ecm + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Support + DEPENDS:=@TARGET_ipq60xx +iptables-mod-extra +iptables-mod-physdev \ + +kmod-ipt-conntrack +kmod-ipt-physdev +kmod-pppoe +kmod-qca-nss-drv + TITLE:=QCA NSS Enhanced Connection Manager (ECM) + FILES:=$(PKG_BUILD_DIR)/*.ko + KCONFIG:= \ + CONFIG_BRIDGE_NETFILTER=y \ + CONFIG_NF_CONNTRACK_EVENTS=y \ + CONFIG_NF_CONNTRACK_CHAIN_EVENTS=y \ + CONFIG_NF_CONNTRACK_DSCPREMARK_EXT=n +endef + +define KernelPackage/qca-nss-ecm/Description +This package contains the QCA NSS Enhanced Connection Manager +endef + +define KernelPackage/qca-nss-ecm/install + $(INSTALL_DIR) $(1)/etc/config + $(INSTALL_DATA) ./files/qca-nss-ecm.uci $(1)/etc/config/ecm + $(INSTALL_DIR) $(1)/etc/init.d + $(INSTALL_BIN) ./files/qca-nss-ecm.init $(1)/etc/init.d/qca-nss-ecm + $(INSTALL_DIR) $(1)/etc/firewall.d + $(INSTALL_DATA) ./files/qca-nss-ecm.firewall $(1)/etc/firewall.d/qca-nss-ecm + $(INSTALL_DIR) $(1)/etc/sysctl.d + $(INSTALL_BIN) ./files/qca-nss-ecm.sysctl $(1)/etc/sysctl.d/qca-nss-ecm.conf + $(INSTALL_DIR) $(1)/etc/uci-defaults + $(INSTALL_DATA) ./files/qca-nss-ecm.defaults $(1)/etc/uci-defaults/99-qca-nss-ecm + $(INSTALL_DIR) $(1)/usr/bin + $(INSTALL_BIN) ./files/ecm_dump.sh $(1)/usr/bin/ + $(INSTALL_DIR) $(1)/lib/netifd/offload + $(INSTALL_BIN) ./files/on-demand-down $(1)/lib/netifd/offload/on-demand-down +endef + +EXTRA_CFLAGS+=-I$(STAGING_DIR)/usr/include/qca-nss-drv + +ifneq (, $(findstring $(BOARD), ipq60xx ipq807x)) +ECM_MAKE_OPTS+= \ + ECM_BAND_STEERING_ENABLE=n \ + ECM_CLASSIFIER_DSCP_ENABLE=n \ + ECM_CLASSIFIER_HYFI_ENABLE=n \ + ECM_CLASSIFIER_MARK_ENABLE=n \ + ECM_CLASSIFIER_PCC_ENABLE=n \ + ECM_FRONT_END_NSS_ENABLE=y \ + ECM_INTERFACE_BOND_ENABLE=n \ + ECM_INTERFACE_GRE_TAP_ENABLE=n \ + ECM_INTERFACE_GRE_TUN_ENABLE=n \ + ECM_INTERFACE_IPSEC_ENABLE=n \ + ECM_INTERFACE_L2TPV2_ENABLE=n \ + ECM_INTERFACE_PPPOE_ENABLE=y \ + ECM_INTERFACE_PPTP_ENABLE=n \ + ECM_INTERFACE_RAWIP_ENABLE=n \ + ECM_INTERFACE_SIT_ENABLE=n \ + ECM_INTERFACE_TUNIPIP6_ENABLE=n \ + ECM_INTERFACE_VLAN_ENABLE=n \ + ECM_MULTICAST_ENABLE=n +endif + +define Build/InstallDev + mkdir -p $(1)/usr/include/qca-nss-ecm + $(CP) $(PKG_BUILD_DIR)/exports/* $(1)/usr/include/qca-nss-ecm +endef + +define Build/Compile + $(MAKE) -C "$(LINUX_DIR)" $(strip $(ECM_MAKE_OPTS)) \ + CROSS_COMPILE="$(TARGET_CROSS)" \ + EXTRA_CFLAGS="$(EXTRA_CFLAGS)" \ + $(KERNEL_MAKE_FLAGS) \ + M="$(PKG_BUILD_DIR)" \ + SoC="$(BOARD)_64" \ + modules +endef + +$(eval $(call KernelPackage,qca-nss-ecm)) diff --git a/qca/qca-nss-ecm/files/ecm_dump.sh b/qca/qca-nss-ecm/files/ecm_dump.sh new file mode 100644 index 000000000..dbf7de753 --- /dev/null +++ b/qca/qca-nss-ecm/files/ecm_dump.sh @@ -0,0 +1,95 @@ +#!/bin/sh +# +# Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +# + +ECM_MODULE=${1:-ecm_state} +MOUNT_ROOT=/dev/ecm + +# +# usage: ecm_dump.sh [module=ecm_db] +# +# with no parameters, ecm_dump.sh will attempt to mount the +# ecm_db state file and cat its contents. +# +# example with a parameter: ecm_dump.sh ecm_classifier_default +# +# this will cause ecm_dump to attempt to find and mount the state +# file for the ecm_classifier_default module, and if successful +# cat the contents. +# + +# this is one of the state files, which happens to be the +# last module started in ecm +ECM_STATE=/sys/kernel/debug/ecm/ecm_state/state_dev_major + +# tests to see if ECM is up and ready to receive commands. +# returns 0 if ECM is fully up and ready, else 1 +ecm_is_ready() { + if [ ! -e "${ECM_STATE}" ] + then + return 1 + fi + return 0 +} + +# +# module_state_mount(module_name) +# Mounts the state file of the module, if supported +# +module_state_mount() { + local module_name=$1 + local mount_dir=$2 + local state_file="/sys/kernel/debug/ecm/${module_name}/state_dev_major" + + if [ -e "${mount_dir}/${module_name}" ] + then + # already mounted + return 0 + fi + + #echo "Mount state file for $module_name ..." + if [ ! -e "$state_file" ] + then + #echo "... $module_name does not support state" + return 1 + fi + + local major="`cat $state_file`" + #echo "... Mounting state $state_file with major: $major" + mknod "${mount_dir}/${module_name}" c $major 0 +} + +# +# main +# +ecm_is_ready || { + #echo "ECM is not running" + exit 1 +} + +# all state files are mounted under MOUNT_ROOT, so make sure it exists +mkdir -p ${MOUNT_ROOT} + +# +# attempt to mount state files for the requested module and cat it +# if the mount succeeded +# +module_state_mount ${ECM_MODULE} ${MOUNT_ROOT} && { + cat ${MOUNT_ROOT}/${ECM_MODULE} + exit 0 +} + +exit 2 diff --git a/qca/qca-nss-ecm/files/on-demand-down b/qca/qca-nss-ecm/files/on-demand-down new file mode 100644 index 000000000..02d708e03 --- /dev/null +++ b/qca/qca-nss-ecm/files/on-demand-down @@ -0,0 +1,6 @@ +#!/bin/sh +# Copyright (c) 2016 The Linux Foundation. All rights reserved. + +[ -e "/sys/kernel/debug/ecm/ecm_db/defunct_all" ] && { + echo 1 > /sys/kernel/debug/ecm/ecm_db/defunct_all +} diff --git a/qca/qca-nss-ecm/files/qca-nss-ecm.defaults b/qca/qca-nss-ecm/files/qca-nss-ecm.defaults new file mode 100644 index 000000000..308e265c9 --- /dev/null +++ b/qca/qca-nss-ecm/files/qca-nss-ecm.defaults @@ -0,0 +1,28 @@ +#!/bin/sh +# +# Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +# + +uci -q batch << EOF + delete firewall.qcanssecm + set firewall.qcanssecm=include + set firewall.qcanssecm.type=script + set firewall.qcanssecm.path=/etc/firewall.d/qca-nss-ecm + set firewall.qcanssecm.family=any + set firewall.qcanssecm.reload=1 + commit firewall +EOF + +exit 0 diff --git a/qca/qca-nss-ecm/files/qca-nss-ecm.firewall b/qca/qca-nss-ecm/files/qca-nss-ecm.firewall new file mode 100644 index 000000000..24c64def2 --- /dev/null +++ b/qca/qca-nss-ecm/files/qca-nss-ecm.firewall @@ -0,0 +1,18 @@ +#!/bin/sh +# +# Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +# + +iptables -A FORWARD -m physdev --physdev-is-bridged -j ACCEPT diff --git a/qca/qca-nss-ecm/files/qca-nss-ecm.init b/qca/qca-nss-ecm/files/qca-nss-ecm.init new file mode 100644 index 000000000..48862dfbd --- /dev/null +++ b/qca/qca-nss-ecm/files/qca-nss-ecm.init @@ -0,0 +1,139 @@ +#!/bin/sh /etc/rc.common +# +# Copyright (c) 2014, 2019-2020 The Linux Foundation. All rights reserved. +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +# The shebang above has an extra space intentially to avoid having +# openwrt build scripts automatically enable this package starting +# at boot. + +START=19 + +get_front_end_mode() { + config_load "ecm" + config_get front_end global acceleration_engine "auto" + + case $front_end in + auto) + echo '0' + ;; + nss) + echo '1' + ;; + sfe) + echo '2' + ;; + *) + echo 'uci_option_acceleration_engine is invalid' + esac +} + +support_bridge() { + #NSS support bridge acceleration + [ -d /sys/kernel/debug/ecm/ecm_nss_ipv4 ] && return 0 + #SFE doesn't support bridge acceleration + [ -d /sys/kernel/debug/ecm/ecm_sfe_ipv4 ] && return 1 +} + +load_sfe() { + local kernel_version=$(uname -r) + + [ -e "/lib/modules/$kernel_version/shortcut-fe.ko" ] && { + [ -d /sys/module/shortcut_fe ] || insmod shortcut-fe + } + + [ -e "/lib/modules/$kernel_version/shortcut-fe-ipv6.ko" ] && { + [ -d /sys/module/shortcut_fe_ipv6 ] || insmod shortcut-fe-ipv6 + } + + [ -e "/lib/modules/$kernel_version/shortcut-fe-drv.ko" ] && { + [ -d /sys/module/shortcut_fe_drv ] || insmod shortcut-fe-drv + } +} + +load_ecm() { + [ -d /sys/module/ecm ] || { + [ ! -e /proc/device-tree/MP_256 ] && load_sfe + insmod ecm front_end_selection=$(get_front_end_mode) + } + + support_bridge && { + sysctl -w net.bridge.bridge-nf-call-ip6tables=1 + sysctl -w net.bridge.bridge-nf-call-iptables=1 + } +} + +unload_ecm() { + sysctl -w net.bridge.bridge-nf-call-ip6tables=0 + sysctl -w net.bridge.bridge-nf-call-iptables=0 + + if [ -d /sys/module/ecm ]; then + # + # Stop ECM frontends + # + echo 1 > /sys/kernel/debug/ecm/front_end_ipv4_stop + echo 1 > /sys/kernel/debug/ecm/front_end_ipv6_stop + + # + # Defunct the connections + # + echo 1 > /sys/kernel/debug/ecm/ecm_db/defunct_all + sleep 5; + + rmmod ecm + sleep 1 + fi +} + +start() { + # If SFE CM is loaded, return. + if [ -d /sys/module/shortcut_fe_cm ]; then + echo "shortcut_fe CM is loaded, unload it first" + echo "cmd: /etc/init.d/shortcut_fe stop" + return + fi + + load_ecm + + # If the acceleration engine is NSS, enable wifi redirect. + [ -d /sys/kernel/debug/ecm/ecm_nss_ipv4 ] && sysctl -w dev.nss.general.redirect=1 + + support_bridge && { + echo 'net.bridge.bridge-nf-call-ip6tables=1' >> /etc/sysctl.d/qca-nss-ecm.conf + echo 'net.bridge.bridge-nf-call-iptables=1' >> /etc/sysctl.d/qca-nss-ecm.conf + } + + if [ -d /sys/module/qca_ovsmgr ]; then + insmod ecm_ovs + fi +} + +stop() { + # If ECM is already not loaded, just return. + if [ ! -d /sys/module/ecm ]; then + return + fi + + # If the acceleration engine is NSS, disable wifi redirect. + [ -d /sys/kernel/debug/ecm/ecm_nss_ipv4 ] && sysctl -w dev.nss.general.redirect=0 + + sed '/net.bridge.bridge-nf-call-ip6tables=1/d' -i /etc/sysctl.d/qca-nss-ecm.conf + sed '/net.bridge.bridge-nf-call-iptables=1/d' -i /etc/sysctl.d/qca-nss-ecm.conf + + if [ -d /sys/module/ecm_ovs ]; then + rmmod ecm_ovs + fi + + unload_ecm +} diff --git a/qca/qca-nss-ecm/files/qca-nss-ecm.sysctl b/qca/qca-nss-ecm/files/qca-nss-ecm.sysctl new file mode 100644 index 000000000..1a3d76b18 --- /dev/null +++ b/qca/qca-nss-ecm/files/qca-nss-ecm.sysctl @@ -0,0 +1,2 @@ +# nf_conntrack_tcp_no_window_check is 0 by default, set it to 1 +net.netfilter.nf_conntrack_tcp_no_window_check=1 diff --git a/qca/qca-nss-ecm/files/qca-nss-ecm.uci b/qca/qca-nss-ecm/files/qca-nss-ecm.uci new file mode 100644 index 000000000..4f2de6877 --- /dev/null +++ b/qca/qca-nss-ecm/files/qca-nss-ecm.uci @@ -0,0 +1,2 @@ +config ecm 'global' + option acceleration_engine 'auto' diff --git a/qca/qca-nss-ecm/patches/200-resolve-high-load.patch b/qca/qca-nss-ecm/patches/200-resolve-high-load.patch new file mode 100644 index 000000000..253b450a5 --- /dev/null +++ b/qca/qca-nss-ecm/patches/200-resolve-high-load.patch @@ -0,0 +1,61 @@ +From 6924b71ed809b37fffd74d6428a8ca83e5919746 Mon Sep 17 00:00:00 2001 +From: Dirk Buchwalder +Date: Sun, 27 Jun 2021 16:52:39 +0200 +Subject: [PATCH] qca-nss-ecm: resolve the cpu high load regarding ecm + +If using ECM, cpu load goes up (around 1.0) and stucks there. +This is due to using uninterruptible sleep function, +the patch changes this to interruptible sleep function. + +Signed-off-by: Dirk Buchwalder +--- + frontends/nss/ecm_nss_ipv4.c | 4 ++-- + frontends/nss/ecm_nss_ipv6.c | 4 ++-- + 2 files changed, 4 insertions(+), 4 deletions(-) + +diff --git a/frontends/nss/ecm_nss_ipv4.c b/frontends/nss/ecm_nss_ipv4.c +index e00553c..94b39cd 100644 +--- a/frontends/nss/ecm_nss_ipv4.c ++++ b/frontends/nss/ecm_nss_ipv4.c +@@ -2471,7 +2471,7 @@ static void ecm_nss_ipv4_stats_sync_req_work(struct work_struct *work) + } + spin_unlock_bh(&ecm_nss_ipv4_lock); + +- usleep_range(ECM_NSS_IPV4_STATS_SYNC_UDELAY - 100, ECM_NSS_IPV4_STATS_SYNC_UDELAY); ++ msleep_interruptible(ECM_NSS_IPV4_STATS_SYNC_UDELAY / 1000); + + /* + * If index is 0, we are starting a new round, but if we still have time remain +@@ -2485,7 +2485,7 @@ static void ecm_nss_ipv4_stats_sync_req_work(struct work_struct *work) + } + + if (time_after(ecm_nss_ipv4_next_req_time, current_jiffies)) { +- msleep(jiffies_to_msecs(ecm_nss_ipv4_next_req_time - current_jiffies)); ++ msleep_interruptible(jiffies_to_msecs(ecm_nss_ipv4_next_req_time - current_jiffies)); + } + ecm_nss_ipv4_roll_check_jiffies = jiffies; + ecm_nss_ipv4_next_req_time = ecm_nss_ipv4_roll_check_jiffies + ECM_NSS_IPV4_STATS_SYNC_PERIOD; +diff --git a/frontends/nss/ecm_nss_ipv6.c b/frontends/nss/ecm_nss_ipv6.c +index 82e739f..30af050 100644 +--- a/frontends/nss/ecm_nss_ipv6.c ++++ b/frontends/nss/ecm_nss_ipv6.c +@@ -2210,7 +2210,7 @@ static void ecm_nss_ipv6_stats_sync_req_work(struct work_struct *work) + } + spin_unlock_bh(&ecm_nss_ipv6_lock); + +- usleep_range(ECM_NSS_IPV6_STATS_SYNC_UDELAY - 100, ECM_NSS_IPV6_STATS_SYNC_UDELAY); ++ msleep_interruptible(ECM_NSS_IPV6_STATS_SYNC_UDELAY / 1000); + + /* + * If index is 0, we are starting a new round, but if we still have time remain +@@ -2224,7 +2224,7 @@ static void ecm_nss_ipv6_stats_sync_req_work(struct work_struct *work) + } + + if (time_after(ecm_nss_ipv6_next_req_time, current_jiffies)) { +- msleep(jiffies_to_msecs(ecm_nss_ipv6_next_req_time - current_jiffies)); ++ msleep_interruptible(jiffies_to_msecs(ecm_nss_ipv6_next_req_time - current_jiffies)); + } + ecm_nss_ipv6_roll_check_jiffies = jiffies; + ecm_nss_ipv6_next_req_time = ecm_nss_ipv6_roll_check_jiffies + ECM_NSS_IPV6_STATS_SYNC_PERIOD; +-- +2.31.1 diff --git a/qca/qca-nss-fw-eip/Makefile b/qca/qca-nss-fw-eip/Makefile new file mode 100644 index 000000000..104fe5c14 --- /dev/null +++ b/qca/qca-nss-fw-eip/Makefile @@ -0,0 +1,25 @@ +include $(TOPDIR)/rules.mk + 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